Bug Summary

File:llvm/include/llvm/MC/LaneBitmask.h
Warning:line 85, column 34
The result of the left shift is undefined due to shifting by '4294967295', which is greater or equal to the width of type 'llvm::LaneBitmask::Type'

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name CodeGenRegisters.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/utils/TableGen -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/include -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/utils/TableGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-01-13-084841-49055-1 -x c++ /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp

1//===- CodeGenRegisters.cpp - Register and RegisterClass Info -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines structures to encapsulate information gleaned from the
10// target register and register class definitions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "CodeGenRegisters.h"
15#include "CodeGenTarget.h"
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/IntEqClasses.h"
20#include "llvm/ADT/SetVector.h"
21#include "llvm/ADT/SmallPtrSet.h"
22#include "llvm/ADT/SmallSet.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/StringExtras.h"
26#include "llvm/ADT/StringRef.h"
27#include "llvm/ADT/Twine.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/MathExtras.h"
30#include "llvm/Support/raw_ostream.h"
31#include "llvm/TableGen/Error.h"
32#include "llvm/TableGen/Record.h"
33#include <algorithm>
34#include <cassert>
35#include <cstdint>
36#include <iterator>
37#include <map>
38#include <queue>
39#include <set>
40#include <string>
41#include <tuple>
42#include <utility>
43#include <vector>
44
45using namespace llvm;
46
47#define DEBUG_TYPE"regalloc-emitter" "regalloc-emitter"
48
49//===----------------------------------------------------------------------===//
50// CodeGenSubRegIndex
51//===----------------------------------------------------------------------===//
52
53CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
54 : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) {
55 Name = R->getName();
56 if (R->getValue("Namespace"))
57 Namespace = R->getValueAsString("Namespace");
58 Size = R->getValueAsInt("Size");
59 Offset = R->getValueAsInt("Offset");
60}
61
62CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace,
63 unsigned Enum)
64 : TheDef(nullptr), Name(N), Namespace(Nspace), Size(-1), Offset(-1),
65 EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) {
66}
67
68std::string CodeGenSubRegIndex::getQualifiedName() const {
69 std::string N = getNamespace();
70 if (!N.empty())
71 N += "::";
72 N += getName();
73 return N;
74}
75
76void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
77 if (!TheDef)
78 return;
79
80 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
81 if (!Comps.empty()) {
82 if (Comps.size() != 2)
83 PrintFatalError(TheDef->getLoc(),
84 "ComposedOf must have exactly two entries");
85 CodeGenSubRegIndex *A = RegBank.getSubRegIdx(Comps[0]);
86 CodeGenSubRegIndex *B = RegBank.getSubRegIdx(Comps[1]);
87 CodeGenSubRegIndex *X = A->addComposite(B, this);
88 if (X)
89 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
90 }
91
92 std::vector<Record*> Parts =
93 TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
94 if (!Parts.empty()) {
95 if (Parts.size() < 2)
96 PrintFatalError(TheDef->getLoc(),
97 "CoveredBySubRegs must have two or more entries");
98 SmallVector<CodeGenSubRegIndex*, 8> IdxParts;
99 for (Record *Part : Parts)
100 IdxParts.push_back(RegBank.getSubRegIdx(Part));
101 setConcatenationOf(IdxParts);
102 }
103}
104
105LaneBitmask CodeGenSubRegIndex::computeLaneMask() const {
106 // Already computed?
107 if (LaneMask.any())
108 return LaneMask;
109
110 // Recursion guard, shouldn't be required.
111 LaneMask = LaneBitmask::getAll();
112
113 // The lane mask is simply the union of all sub-indices.
114 LaneBitmask M;
115 for (const auto &C : Composed)
116 M |= C.second->computeLaneMask();
117 assert(M.any() && "Missing lane mask, sub-register cycle?")((M.any() && "Missing lane mask, sub-register cycle?"
) ? static_cast<void> (0) : __assert_fail ("M.any() && \"Missing lane mask, sub-register cycle?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 117, __PRETTY_FUNCTION__))
;
118 LaneMask = M;
119 return LaneMask;
120}
121
122void CodeGenSubRegIndex::setConcatenationOf(
123 ArrayRef<CodeGenSubRegIndex*> Parts) {
124 if (ConcatenationOf.empty())
125 ConcatenationOf.assign(Parts.begin(), Parts.end());
126 else
127 assert(std::equal(Parts.begin(), Parts.end(),((std::equal(Parts.begin(), Parts.end(), ConcatenationOf.begin
()) && "parts consistent") ? static_cast<void> (
0) : __assert_fail ("std::equal(Parts.begin(), Parts.end(), ConcatenationOf.begin()) && \"parts consistent\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 128, __PRETTY_FUNCTION__))
128 ConcatenationOf.begin()) && "parts consistent")((std::equal(Parts.begin(), Parts.end(), ConcatenationOf.begin
()) && "parts consistent") ? static_cast<void> (
0) : __assert_fail ("std::equal(Parts.begin(), Parts.end(), ConcatenationOf.begin()) && \"parts consistent\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 128, __PRETTY_FUNCTION__))
;
129}
130
131void CodeGenSubRegIndex::computeConcatTransitiveClosure() {
132 for (SmallVectorImpl<CodeGenSubRegIndex*>::iterator
133 I = ConcatenationOf.begin(); I != ConcatenationOf.end(); /*empty*/) {
134 CodeGenSubRegIndex *SubIdx = *I;
135 SubIdx->computeConcatTransitiveClosure();
136#ifndef NDEBUG
137 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf)
138 assert(SRI->ConcatenationOf.empty() && "No transitive closure?")((SRI->ConcatenationOf.empty() && "No transitive closure?"
) ? static_cast<void> (0) : __assert_fail ("SRI->ConcatenationOf.empty() && \"No transitive closure?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 138, __PRETTY_FUNCTION__))
;
139#endif
140
141 if (SubIdx->ConcatenationOf.empty()) {
142 ++I;
143 } else {
144 I = ConcatenationOf.erase(I);
145 I = ConcatenationOf.insert(I, SubIdx->ConcatenationOf.begin(),
146 SubIdx->ConcatenationOf.end());
147 I += SubIdx->ConcatenationOf.size();
148 }
149 }
150}
151
152//===----------------------------------------------------------------------===//
153// CodeGenRegister
154//===----------------------------------------------------------------------===//
155
156CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
157 : TheDef(R),
158 EnumValue(Enum),
159 CostPerUse(R->getValueAsInt("CostPerUse")),
160 CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
161 HasDisjunctSubRegs(false),
162 SubRegsComplete(false),
163 SuperRegsComplete(false),
164 TopoSig(~0u) {
165 Artificial = R->getValueAsBit("isArtificial");
166}
167
168void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
169 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
170 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
171
172 if (SRIs.size() != SRs.size())
173 PrintFatalError(TheDef->getLoc(),
174 "SubRegs and SubRegIndices must have the same size");
175
176 for (unsigned i = 0, e = SRIs.size(); i != e; ++i) {
177 ExplicitSubRegIndices.push_back(RegBank.getSubRegIdx(SRIs[i]));
178 ExplicitSubRegs.push_back(RegBank.getReg(SRs[i]));
179 }
180
181 // Also compute leading super-registers. Each register has a list of
182 // covered-by-subregs super-registers where it appears as the first explicit
183 // sub-register.
184 //
185 // This is used by computeSecondarySubRegs() to find candidates.
186 if (CoveredBySubRegs && !ExplicitSubRegs.empty())
187 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this);
188
189 // Add ad hoc alias links. This is a symmetric relationship between two
190 // registers, so build a symmetric graph by adding links in both ends.
191 std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases");
192 for (Record *Alias : Aliases) {
193 CodeGenRegister *Reg = RegBank.getReg(Alias);
194 ExplicitAliases.push_back(Reg);
195 Reg->ExplicitAliases.push_back(this);
196 }
197}
198
199const StringRef CodeGenRegister::getName() const {
200 assert(TheDef && "no def")((TheDef && "no def") ? static_cast<void> (0) :
__assert_fail ("TheDef && \"no def\"", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 200, __PRETTY_FUNCTION__))
;
201 return TheDef->getName();
202}
203
204namespace {
205
206// Iterate over all register units in a set of registers.
207class RegUnitIterator {
208 CodeGenRegister::Vec::const_iterator RegI, RegE;
209 CodeGenRegister::RegUnitList::iterator UnitI, UnitE;
210
211public:
212 RegUnitIterator(const CodeGenRegister::Vec &Regs):
213 RegI(Regs.begin()), RegE(Regs.end()) {
214
215 if (RegI != RegE) {
216 UnitI = (*RegI)->getRegUnits().begin();
217 UnitE = (*RegI)->getRegUnits().end();
218 advance();
219 }
220 }
221
222 bool isValid() const { return UnitI != UnitE; }
223
224 unsigned operator* () const { assert(isValid())((isValid()) ? static_cast<void> (0) : __assert_fail ("isValid()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 224, __PRETTY_FUNCTION__))
; return *UnitI; }
225
226 const CodeGenRegister *getReg() const { assert(isValid())((isValid()) ? static_cast<void> (0) : __assert_fail ("isValid()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 226, __PRETTY_FUNCTION__))
; return *RegI; }
227
228 /// Preincrement. Move to the next unit.
229 void operator++() {
230 assert(isValid() && "Cannot advance beyond the last operand")((isValid() && "Cannot advance beyond the last operand"
) ? static_cast<void> (0) : __assert_fail ("isValid() && \"Cannot advance beyond the last operand\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 230, __PRETTY_FUNCTION__))
;
231 ++UnitI;
232 advance();
233 }
234
235protected:
236 void advance() {
237 while (UnitI == UnitE) {
238 if (++RegI == RegE)
239 break;
240 UnitI = (*RegI)->getRegUnits().begin();
241 UnitE = (*RegI)->getRegUnits().end();
242 }
243 }
244};
245
246} // end anonymous namespace
247
248// Return true of this unit appears in RegUnits.
249static bool hasRegUnit(CodeGenRegister::RegUnitList &RegUnits, unsigned Unit) {
250 return RegUnits.test(Unit);
251}
252
253// Inherit register units from subregisters.
254// Return true if the RegUnits changed.
255bool CodeGenRegister::inheritRegUnits(CodeGenRegBank &RegBank) {
256 bool changed = false;
257 for (const auto &SubReg : SubRegs) {
258 CodeGenRegister *SR = SubReg.second;
259 // Merge the subregister's units into this register's RegUnits.
260 changed |= (RegUnits |= SR->RegUnits);
261 }
262
263 return changed;
264}
265
266const CodeGenRegister::SubRegMap &
267CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
268 // Only compute this map once.
269 if (SubRegsComplete)
270 return SubRegs;
271 SubRegsComplete = true;
272
273 HasDisjunctSubRegs = ExplicitSubRegs.size() > 1;
274
275 // First insert the explicit subregs and make sure they are fully indexed.
276 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
277 CodeGenRegister *SR = ExplicitSubRegs[i];
278 CodeGenSubRegIndex *Idx = ExplicitSubRegIndices[i];
279 if (!SR->Artificial)
280 Idx->Artificial = false;
281 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
282 PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
283 " appears twice in Register " + getName());
284 // Map explicit sub-registers first, so the names take precedence.
285 // The inherited sub-registers are mapped below.
286 SubReg2Idx.insert(std::make_pair(SR, Idx));
287 }
288
289 // Keep track of inherited subregs and how they can be reached.
290 SmallPtrSet<CodeGenRegister*, 8> Orphans;
291
292 // Clone inherited subregs and place duplicate entries in Orphans.
293 // Here the order is important - earlier subregs take precedence.
294 for (CodeGenRegister *ESR : ExplicitSubRegs) {
295 const SubRegMap &Map = ESR->computeSubRegs(RegBank);
296 HasDisjunctSubRegs |= ESR->HasDisjunctSubRegs;
297
298 for (const auto &SR : Map) {
299 if (!SubRegs.insert(SR).second)
300 Orphans.insert(SR.second);
301 }
302 }
303
304 // Expand any composed subreg indices.
305 // If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
306 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
307 // expanded subreg indices recursively.
308 SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices;
309 for (unsigned i = 0; i != Indices.size(); ++i) {
310 CodeGenSubRegIndex *Idx = Indices[i];
311 const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
312 CodeGenRegister *SR = SubRegs[Idx];
313 const SubRegMap &Map = SR->computeSubRegs(RegBank);
314
315 // Look at the possible compositions of Idx.
316 // They may not all be supported by SR.
317 for (CodeGenSubRegIndex::CompMap::const_iterator I = Comps.begin(),
318 E = Comps.end(); I != E; ++I) {
319 SubRegMap::const_iterator SRI = Map.find(I->first);
320 if (SRI == Map.end())
321 continue; // Idx + I->first doesn't exist in SR.
322 // Add I->second as a name for the subreg SRI->second, assuming it is
323 // orphaned, and the name isn't already used for something else.
324 if (SubRegs.count(I->second) || !Orphans.erase(SRI->second))
325 continue;
326 // We found a new name for the orphaned sub-register.
327 SubRegs.insert(std::make_pair(I->second, SRI->second));
328 Indices.push_back(I->second);
329 }
330 }
331
332 // Now Orphans contains the inherited subregisters without a direct index.
333 // Create inferred indexes for all missing entries.
334 // Work backwards in the Indices vector in order to compose subregs bottom-up.
335 // Consider this subreg sequence:
336 //
337 // qsub_1 -> dsub_0 -> ssub_0
338 //
339 // The qsub_1 -> dsub_0 composition becomes dsub_2, so the ssub_0 register
340 // can be reached in two different ways:
341 //
342 // qsub_1 -> ssub_0
343 // dsub_2 -> ssub_0
344 //
345 // We pick the latter composition because another register may have [dsub_0,
346 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
347 // dsub_2 -> ssub_0 composition can be shared.
348 while (!Indices.empty() && !Orphans.empty()) {
349 CodeGenSubRegIndex *Idx = Indices.pop_back_val();
350 CodeGenRegister *SR = SubRegs[Idx];
351 const SubRegMap &Map = SR->computeSubRegs(RegBank);
352 for (const auto &SubReg : Map)
353 if (Orphans.erase(SubReg.second))
354 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second;
355 }
356
357 // Compute the inverse SubReg -> Idx map.
358 for (const auto &SubReg : SubRegs) {
359 if (SubReg.second == this) {
360 ArrayRef<SMLoc> Loc;
361 if (TheDef)
362 Loc = TheDef->getLoc();
363 PrintFatalError(Loc, "Register " + getName() +
364 " has itself as a sub-register");
365 }
366
367 // Compute AllSuperRegsCovered.
368 if (!CoveredBySubRegs)
369 SubReg.first->AllSuperRegsCovered = false;
370
371 // Ensure that every sub-register has a unique name.
372 DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins =
373 SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first;
374 if (Ins->second == SubReg.first)
375 continue;
376 // Trouble: Two different names for SubReg.second.
377 ArrayRef<SMLoc> Loc;
378 if (TheDef)
379 Loc = TheDef->getLoc();
380 PrintFatalError(Loc, "Sub-register can't have two names: " +
381 SubReg.second->getName() + " available as " +
382 SubReg.first->getName() + " and " + Ins->second->getName());
383 }
384
385 // Derive possible names for sub-register concatenations from any explicit
386 // sub-registers. By doing this before computeSecondarySubRegs(), we ensure
387 // that getConcatSubRegIndex() won't invent any concatenated indices that the
388 // user already specified.
389 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
390 CodeGenRegister *SR = ExplicitSubRegs[i];
391 if (!SR->CoveredBySubRegs || SR->ExplicitSubRegs.size() <= 1 ||
392 SR->Artificial)
393 continue;
394
395 // SR is composed of multiple sub-regs. Find their names in this register.
396 SmallVector<CodeGenSubRegIndex*, 8> Parts;
397 for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) {
398 CodeGenSubRegIndex &I = *SR->ExplicitSubRegIndices[j];
399 if (!I.Artificial)
400 Parts.push_back(getSubRegIndex(SR->ExplicitSubRegs[j]));
401 }
402
403 // Offer this as an existing spelling for the concatenation of Parts.
404 CodeGenSubRegIndex &Idx = *ExplicitSubRegIndices[i];
405 Idx.setConcatenationOf(Parts);
406 }
407
408 // Initialize RegUnitList. Because getSubRegs is called recursively, this
409 // processes the register hierarchy in postorder.
410 //
411 // Inherit all sub-register units. It is good enough to look at the explicit
412 // sub-registers, the other registers won't contribute any more units.
413 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
414 CodeGenRegister *SR = ExplicitSubRegs[i];
415 RegUnits |= SR->RegUnits;
416 }
417
418 // Absent any ad hoc aliasing, we create one register unit per leaf register.
419 // These units correspond to the maximal cliques in the register overlap
420 // graph which is optimal.
421 //
422 // When there is ad hoc aliasing, we simply create one unit per edge in the
423 // undirected ad hoc aliasing graph. Technically, we could do better by
424 // identifying maximal cliques in the ad hoc graph, but cliques larger than 2
425 // are extremely rare anyway (I've never seen one), so we don't bother with
426 // the added complexity.
427 for (unsigned i = 0, e = ExplicitAliases.size(); i != e; ++i) {
428 CodeGenRegister *AR = ExplicitAliases[i];
429 // Only visit each edge once.
430 if (AR->SubRegsComplete)
431 continue;
432 // Create a RegUnit representing this alias edge, and add it to both
433 // registers.
434 unsigned Unit = RegBank.newRegUnit(this, AR);
435 RegUnits.set(Unit);
436 AR->RegUnits.set(Unit);
437 }
438
439 // Finally, create units for leaf registers without ad hoc aliases. Note that
440 // a leaf register with ad hoc aliases doesn't get its own unit - it isn't
441 // necessary. This means the aliasing leaf registers can share a single unit.
442 if (RegUnits.empty())
443 RegUnits.set(RegBank.newRegUnit(this));
444
445 // We have now computed the native register units. More may be adopted later
446 // for balancing purposes.
447 NativeRegUnits = RegUnits;
448
449 return SubRegs;
450}
451
452// In a register that is covered by its sub-registers, try to find redundant
453// sub-registers. For example:
454//
455// QQ0 = {Q0, Q1}
456// Q0 = {D0, D1}
457// Q1 = {D2, D3}
458//
459// We can infer that D1_D2 is also a sub-register, even if it wasn't named in
460// the register definition.
461//
462// The explicitly specified registers form a tree. This function discovers
463// sub-register relationships that would force a DAG.
464//
465void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
466 SmallVector<SubRegMap::value_type, 8> NewSubRegs;
467
468 std::queue<std::pair<CodeGenSubRegIndex*,CodeGenRegister*>> SubRegQueue;
469 for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : SubRegs)
470 SubRegQueue.push(P);
471
472 // Look at the leading super-registers of each sub-register. Those are the
473 // candidates for new sub-registers, assuming they are fully contained in
474 // this register.
475 while (!SubRegQueue.empty()) {
476 CodeGenSubRegIndex *SubRegIdx;
477 const CodeGenRegister *SubReg;
478 std::tie(SubRegIdx, SubReg) = SubRegQueue.front();
479 SubRegQueue.pop();
480
481 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
482 for (unsigned i = 0, e = Leads.size(); i != e; ++i) {
483 CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]);
484 // Already got this sub-register?
485 if (Cand == this || getSubRegIndex(Cand))
486 continue;
487 // Check if each component of Cand is already a sub-register.
488 assert(!Cand->ExplicitSubRegs.empty() &&((!Cand->ExplicitSubRegs.empty() && "Super-register has no sub-registers"
) ? static_cast<void> (0) : __assert_fail ("!Cand->ExplicitSubRegs.empty() && \"Super-register has no sub-registers\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 489, __PRETTY_FUNCTION__))
489 "Super-register has no sub-registers")((!Cand->ExplicitSubRegs.empty() && "Super-register has no sub-registers"
) ? static_cast<void> (0) : __assert_fail ("!Cand->ExplicitSubRegs.empty() && \"Super-register has no sub-registers\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 489, __PRETTY_FUNCTION__))
;
490 if (Cand->ExplicitSubRegs.size() == 1)
491 continue;
492 SmallVector<CodeGenSubRegIndex*, 8> Parts;
493 // We know that the first component is (SubRegIdx,SubReg). However we
494 // may still need to split it into smaller subregister parts.
495 assert(Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct")((Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct"
) ? static_cast<void> (0) : __assert_fail ("Cand->ExplicitSubRegs[0] == SubReg && \"LeadingSuperRegs correct\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 495, __PRETTY_FUNCTION__))
;
496 assert(getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct")((getSubRegIndex(SubReg) == SubRegIdx && "LeadingSuperRegs correct"
) ? static_cast<void> (0) : __assert_fail ("getSubRegIndex(SubReg) == SubRegIdx && \"LeadingSuperRegs correct\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 496, __PRETTY_FUNCTION__))
;
497 for (CodeGenRegister *SubReg : Cand->ExplicitSubRegs) {
498 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) {
499 if (SubRegIdx->ConcatenationOf.empty()) {
500 Parts.push_back(SubRegIdx);
501 } else
502 for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf)
503 Parts.push_back(SubIdx);
504 } else {
505 // Sub-register doesn't exist.
506 Parts.clear();
507 break;
508 }
509 }
510 // There is nothing to do if some Cand sub-register is not part of this
511 // register.
512 if (Parts.empty())
513 continue;
514
515 // Each part of Cand is a sub-register of this. Make the full Cand also
516 // a sub-register with a concatenated sub-register index.
517 CodeGenSubRegIndex *Concat = RegBank.getConcatSubRegIndex(Parts);
518 std::pair<CodeGenSubRegIndex*,CodeGenRegister*> NewSubReg =
519 std::make_pair(Concat, Cand);
520
521 if (!SubRegs.insert(NewSubReg).second)
522 continue;
523
524 // We inserted a new subregister.
525 NewSubRegs.push_back(NewSubReg);
526 SubRegQueue.push(NewSubReg);
527 SubReg2Idx.insert(std::make_pair(Cand, Concat));
528 }
529 }
530
531 // Create sub-register index composition maps for the synthesized indices.
532 for (unsigned i = 0, e = NewSubRegs.size(); i != e; ++i) {
533 CodeGenSubRegIndex *NewIdx = NewSubRegs[i].first;
534 CodeGenRegister *NewSubReg = NewSubRegs[i].second;
535 for (SubRegMap::const_iterator SI = NewSubReg->SubRegs.begin(),
536 SE = NewSubReg->SubRegs.end(); SI != SE; ++SI) {
537 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
538 if (!SubIdx)
539 PrintFatalError(TheDef->getLoc(), "No SubRegIndex for " +
540 SI->second->getName() + " in " + getName());
541 NewIdx->addComposite(SI->first, SubIdx);
542 }
543 }
544}
545
546void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
547 // Only visit each register once.
548 if (SuperRegsComplete)
549 return;
550 SuperRegsComplete = true;
551
552 // Make sure all sub-registers have been visited first, so the super-reg
553 // lists will be topologically ordered.
554 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
555 I != E; ++I)
556 I->second->computeSuperRegs(RegBank);
557
558 // Now add this as a super-register on all sub-registers.
559 // Also compute the TopoSigId in post-order.
560 TopoSigId Id;
561 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
562 I != E; ++I) {
563 // Topological signature computed from SubIdx, TopoId(SubReg).
564 // Loops and idempotent indices have TopoSig = ~0u.
565 Id.push_back(I->first->EnumValue);
566 Id.push_back(I->second->TopoSig);
567
568 // Don't add duplicate entries.
569 if (!I->second->SuperRegs.empty() && I->second->SuperRegs.back() == this)
570 continue;
571 I->second->SuperRegs.push_back(this);
572 }
573 TopoSig = RegBank.getTopoSig(Id);
574}
575
576void
577CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
578 CodeGenRegBank &RegBank) const {
579 assert(SubRegsComplete && "Must precompute sub-registers")((SubRegsComplete && "Must precompute sub-registers")
? static_cast<void> (0) : __assert_fail ("SubRegsComplete && \"Must precompute sub-registers\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 579, __PRETTY_FUNCTION__))
;
580 for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
581 CodeGenRegister *SR = ExplicitSubRegs[i];
582 if (OSet.insert(SR))
583 SR->addSubRegsPreOrder(OSet, RegBank);
584 }
585 // Add any secondary sub-registers that weren't part of the explicit tree.
586 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
587 I != E; ++I)
588 OSet.insert(I->second);
589}
590
591// Get the sum of this register's unit weights.
592unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const {
593 unsigned Weight = 0;
594 for (RegUnitList::iterator I = RegUnits.begin(), E = RegUnits.end();
595 I != E; ++I) {
596 Weight += RegBank.getRegUnit(*I).Weight;
597 }
598 return Weight;
599}
600
601//===----------------------------------------------------------------------===//
602// RegisterTuples
603//===----------------------------------------------------------------------===//
604
605// A RegisterTuples def is used to generate pseudo-registers from lists of
606// sub-registers. We provide a SetTheory expander class that returns the new
607// registers.
608namespace {
609
610struct TupleExpander : SetTheory::Expander {
611 // Reference to SynthDefs in the containing CodeGenRegBank, to keep track of
612 // the synthesized definitions for their lifetime.
613 std::vector<std::unique_ptr<Record>> &SynthDefs;
614
615 TupleExpander(std::vector<std::unique_ptr<Record>> &SynthDefs)
616 : SynthDefs(SynthDefs) {}
617
618 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override {
619 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
620 unsigned Dim = Indices.size();
621 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
622 if (Dim != SubRegs->size())
623 PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
624 if (Dim < 2)
625 PrintFatalError(Def->getLoc(),
626 "Tuples must have at least 2 sub-registers");
627
628 // Evaluate the sub-register lists to be zipped.
629 unsigned Length = ~0u;
630 SmallVector<SetTheory::RecSet, 4> Lists(Dim);
631 for (unsigned i = 0; i != Dim; ++i) {
632 ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc());
633 Length = std::min(Length, unsigned(Lists[i].size()));
634 }
635
636 if (Length == 0)
637 return;
638
639 // Precompute some types.
640 Record *RegisterCl = Def->getRecords().getClass("Register");
641 RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
642 std::vector<StringRef> RegNames =
643 Def->getValueAsListOfStrings("RegAsmNames");
644
645 // Zip them up.
646 for (unsigned n = 0; n != Length; ++n) {
647 std::string Name;
648 Record *Proto = Lists[0][n];
649 std::vector<Init*> Tuple;
650 unsigned CostPerUse = 0;
651 for (unsigned i = 0; i != Dim; ++i) {
652 Record *Reg = Lists[i][n];
653 if (i) Name += '_';
654 Name += Reg->getName();
655 Tuple.push_back(DefInit::get(Reg));
656 CostPerUse = std::max(CostPerUse,
657 unsigned(Reg->getValueAsInt("CostPerUse")));
658 }
659
660 StringInit *AsmName = StringInit::get("");
661 if (!RegNames.empty()) {
662 if (RegNames.size() <= n)
663 PrintFatalError(Def->getLoc(),
664 "Register tuple definition missing name for '" +
665 Name + "'.");
666 AsmName = StringInit::get(RegNames[n]);
667 }
668
669 // Create a new Record representing the synthesized register. This record
670 // is only for consumption by CodeGenRegister, it is not added to the
671 // RecordKeeper.
672 SynthDefs.emplace_back(
673 std::make_unique<Record>(Name, Def->getLoc(), Def->getRecords()));
674 Record *NewReg = SynthDefs.back().get();
675 Elts.insert(NewReg);
676
677 // Copy Proto super-classes.
678 ArrayRef<std::pair<Record *, SMRange>> Supers = Proto->getSuperClasses();
679 for (const auto &SuperPair : Supers)
680 NewReg->addSuperClass(SuperPair.first, SuperPair.second);
681
682 // Copy Proto fields.
683 for (unsigned i = 0, e = Proto->getValues().size(); i != e; ++i) {
684 RecordVal RV = Proto->getValues()[i];
685
686 // Skip existing fields, like NAME.
687 if (NewReg->getValue(RV.getNameInit()))
688 continue;
689
690 StringRef Field = RV.getName();
691
692 // Replace the sub-register list with Tuple.
693 if (Field == "SubRegs")
694 RV.setValue(ListInit::get(Tuple, RegisterRecTy));
695
696 if (Field == "AsmName")
697 RV.setValue(AsmName);
698
699 // CostPerUse is aggregated from all Tuple members.
700 if (Field == "CostPerUse")
701 RV.setValue(IntInit::get(CostPerUse));
702
703 // Composite registers are always covered by sub-registers.
704 if (Field == "CoveredBySubRegs")
705 RV.setValue(BitInit::get(true));
706
707 // Copy fields from the RegisterTuples def.
708 if (Field == "SubRegIndices" ||
709 Field == "CompositeIndices") {
710 NewReg->addValue(*Def->getValue(Field));
711 continue;
712 }
713
714 // Some fields get their default uninitialized value.
715 if (Field == "DwarfNumbers" ||
716 Field == "DwarfAlias" ||
717 Field == "Aliases") {
718 if (const RecordVal *DefRV = RegisterCl->getValue(Field))
719 NewReg->addValue(*DefRV);
720 continue;
721 }
722
723 // Everything else is copied from Proto.
724 NewReg->addValue(RV);
725 }
726 }
727 }
728};
729
730} // end anonymous namespace
731
732//===----------------------------------------------------------------------===//
733// CodeGenRegisterClass
734//===----------------------------------------------------------------------===//
735
736static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
737 llvm::sort(M, deref<std::less<>>());
738 M.erase(std::unique(M.begin(), M.end(), deref<std::equal_to<>>()), M.end());
739}
740
741CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
742 : TheDef(R),
743 Name(R->getName()),
744 TopoSigs(RegBank.getNumTopoSigs()),
745 EnumValue(-1) {
746
747 std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
748 for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
749 Record *Type = TypeList[i];
750 if (!Type->isSubClassOf("ValueType"))
751 PrintFatalError(R->getLoc(),
752 "RegTypes list member '" + Type->getName() +
753 "' does not derive from the ValueType class!");
754 VTs.push_back(getValueTypeByHwMode(Type, RegBank.getHwModes()));
755 }
756 assert(!VTs.empty() && "RegisterClass must contain at least one ValueType!")((!VTs.empty() && "RegisterClass must contain at least one ValueType!"
) ? static_cast<void> (0) : __assert_fail ("!VTs.empty() && \"RegisterClass must contain at least one ValueType!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 756, __PRETTY_FUNCTION__))
;
757
758 // Allocation order 0 is the full set. AltOrders provides others.
759 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
760 ListInit *AltOrders = R->getValueAsListInit("AltOrders");
761 Orders.resize(1 + AltOrders->size());
762
763 // Default allocation order always contains all registers.
764 Artificial = true;
765 for (unsigned i = 0, e = Elements->size(); i != e; ++i) {
766 Orders[0].push_back((*Elements)[i]);
767 const CodeGenRegister *Reg = RegBank.getReg((*Elements)[i]);
768 Members.push_back(Reg);
769 Artificial &= Reg->Artificial;
770 TopoSigs.set(Reg->getTopoSig());
771 }
772 sortAndUniqueRegisters(Members);
773
774 // Alternative allocation orders may be subsets.
775 SetTheory::RecSet Order;
776 for (unsigned i = 0, e = AltOrders->size(); i != e; ++i) {
777 RegBank.getSets().evaluate(AltOrders->getElement(i), Order, R->getLoc());
778 Orders[1 + i].append(Order.begin(), Order.end());
779 // Verify that all altorder members are regclass members.
780 while (!Order.empty()) {
781 CodeGenRegister *Reg = RegBank.getReg(Order.back());
782 Order.pop_back();
783 if (!contains(Reg))
784 PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() +
785 " is not a class member");
786 }
787 }
788
789 Namespace = R->getValueAsString("Namespace");
790
791 if (const RecordVal *RV = R->getValue("RegInfos"))
792 if (DefInit *DI = dyn_cast_or_null<DefInit>(RV->getValue()))
793 RSI = RegSizeInfoByHwMode(DI->getDef(), RegBank.getHwModes());
794 unsigned Size = R->getValueAsInt("Size");
795 assert((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) &&(((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) &&
"Impossible to determine register size") ? static_cast<void
> (0) : __assert_fail ("(RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) && \"Impossible to determine register size\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 796, __PRETTY_FUNCTION__))
796 "Impossible to determine register size")(((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) &&
"Impossible to determine register size") ? static_cast<void
> (0) : __assert_fail ("(RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) && \"Impossible to determine register size\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 796, __PRETTY_FUNCTION__))
;
797 if (!RSI.hasDefault()) {
798 RegSizeInfo RI;
799 RI.RegSize = RI.SpillSize = Size ? Size
800 : VTs[0].getSimple().getSizeInBits();
801 RI.SpillAlignment = R->getValueAsInt("Alignment");
802 RSI.Map.insert({DefaultMode, RI});
803 }
804
805 CopyCost = R->getValueAsInt("CopyCost");
806 Allocatable = R->getValueAsBit("isAllocatable");
807 AltOrderSelect = R->getValueAsString("AltOrderSelect");
808 int AllocationPriority = R->getValueAsInt("AllocationPriority");
809 if (AllocationPriority < 0 || AllocationPriority > 63)
810 PrintFatalError(R->getLoc(), "AllocationPriority out of range [0,63]");
811 this->AllocationPriority = AllocationPriority;
812}
813
814// Create an inferred register class that was missing from the .td files.
815// Most properties will be inherited from the closest super-class after the
816// class structure has been computed.
817CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank,
818 StringRef Name, Key Props)
819 : Members(*Props.Members),
820 TheDef(nullptr),
821 Name(Name),
822 TopoSigs(RegBank.getNumTopoSigs()),
823 EnumValue(-1),
824 RSI(Props.RSI),
825 CopyCost(0),
826 Allocatable(true),
827 AllocationPriority(0) {
828 Artificial = true;
829 for (const auto R : Members) {
830 TopoSigs.set(R->getTopoSig());
831 Artificial &= R->Artificial;
832 }
833}
834
835// Compute inherited propertied for a synthesized register class.
836void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
837 assert(!getDef() && "Only synthesized classes can inherit properties")((!getDef() && "Only synthesized classes can inherit properties"
) ? static_cast<void> (0) : __assert_fail ("!getDef() && \"Only synthesized classes can inherit properties\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 837, __PRETTY_FUNCTION__))
;
838 assert(!SuperClasses.empty() && "Synthesized class without super class")((!SuperClasses.empty() && "Synthesized class without super class"
) ? static_cast<void> (0) : __assert_fail ("!SuperClasses.empty() && \"Synthesized class without super class\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 838, __PRETTY_FUNCTION__))
;
839
840 // The last super-class is the smallest one.
841 CodeGenRegisterClass &Super = *SuperClasses.back();
842
843 // Most properties are copied directly.
844 // Exceptions are members, size, and alignment
845 Namespace = Super.Namespace;
846 VTs = Super.VTs;
847 CopyCost = Super.CopyCost;
848 Allocatable = Super.Allocatable;
849 AltOrderSelect = Super.AltOrderSelect;
850 AllocationPriority = Super.AllocationPriority;
851
852 // Copy all allocation orders, filter out foreign registers from the larger
853 // super-class.
854 Orders.resize(Super.Orders.size());
855 for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)
856 for (unsigned j = 0, je = Super.Orders[i].size(); j != je; ++j)
857 if (contains(RegBank.getReg(Super.Orders[i][j])))
858 Orders[i].push_back(Super.Orders[i][j]);
859}
860
861bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
862 return std::binary_search(Members.begin(), Members.end(), Reg,
863 deref<std::less<>>());
864}
865
866namespace llvm {
867
868 raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
869 OS << "{ " << K.RSI;
870 for (const auto R : *K.Members)
871 OS << ", " << R->getName();
872 return OS << " }";
873 }
874
875} // end namespace llvm
876
877// This is a simple lexicographical order that can be used to search for sets.
878// It is not the same as the topological order provided by TopoOrderRC.
879bool CodeGenRegisterClass::Key::
880operator<(const CodeGenRegisterClass::Key &B) const {
881 assert(Members && B.Members)((Members && B.Members) ? static_cast<void> (0)
: __assert_fail ("Members && B.Members", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 881, __PRETTY_FUNCTION__))
;
882 return std::tie(*Members, RSI) < std::tie(*B.Members, B.RSI);
883}
884
885// Returns true if RC is a strict subclass.
886// RC is a sub-class of this class if it is a valid replacement for any
887// instruction operand where a register of this classis required. It must
888// satisfy these conditions:
889//
890// 1. All RC registers are also in this.
891// 2. The RC spill size must not be smaller than our spill size.
892// 3. RC spill alignment must be compatible with ours.
893//
894static bool testSubClass(const CodeGenRegisterClass *A,
895 const CodeGenRegisterClass *B) {
896 return A->RSI.isSubClassOf(B->RSI) &&
897 std::includes(A->getMembers().begin(), A->getMembers().end(),
898 B->getMembers().begin(), B->getMembers().end(),
899 deref<std::less<>>());
900}
901
902/// Sorting predicate for register classes. This provides a topological
903/// ordering that arranges all register classes before their sub-classes.
904///
905/// Register classes with the same registers, spill size, and alignment form a
906/// clique. They will be ordered alphabetically.
907///
908static bool TopoOrderRC(const CodeGenRegisterClass &PA,
909 const CodeGenRegisterClass &PB) {
910 auto *A = &PA;
911 auto *B = &PB;
912 if (A == B)
913 return false;
914
915 if (A->RSI < B->RSI)
916 return true;
917 if (A->RSI != B->RSI)
918 return false;
919
920 // Order by descending set size. Note that the classes' allocation order may
921 // not have been computed yet. The Members set is always vaild.
922 if (A->getMembers().size() > B->getMembers().size())
923 return true;
924 if (A->getMembers().size() < B->getMembers().size())
925 return false;
926
927 // Finally order by name as a tie breaker.
928 return StringRef(A->getName()) < B->getName();
929}
930
931std::string CodeGenRegisterClass::getQualifiedName() const {
932 if (Namespace.empty())
933 return getName();
934 else
935 return (Namespace + "::" + getName()).str();
936}
937
938// Compute sub-classes of all register classes.
939// Assume the classes are ordered topologically.
940void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
941 auto &RegClasses = RegBank.getRegClasses();
942
943 // Visit backwards so sub-classes are seen first.
944 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) {
945 CodeGenRegisterClass &RC = *I;
946 RC.SubClasses.resize(RegClasses.size());
947 RC.SubClasses.set(RC.EnumValue);
948 if (RC.Artificial)
949 continue;
950
951 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique.
952 for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) {
953 CodeGenRegisterClass &SubRC = *I2;
954 if (RC.SubClasses.test(SubRC.EnumValue))
955 continue;
956 if (!testSubClass(&RC, &SubRC))
957 continue;
958 // SubRC is a sub-class. Grap all its sub-classes so we won't have to
959 // check them again.
960 RC.SubClasses |= SubRC.SubClasses;
961 }
962
963 // Sweep up missed clique members. They will be immediately preceding RC.
964 for (auto I2 = std::next(I); I2 != E && testSubClass(&RC, &*I2); ++I2)
965 RC.SubClasses.set(I2->EnumValue);
966 }
967
968 // Compute the SuperClasses lists from the SubClasses vectors.
969 for (auto &RC : RegClasses) {
970 const BitVector &SC = RC.getSubClasses();
971 auto I = RegClasses.begin();
972 for (int s = 0, next_s = SC.find_first(); next_s != -1;
973 next_s = SC.find_next(s)) {
974 std::advance(I, next_s - s);
975 s = next_s;
976 if (&*I == &RC)
977 continue;
978 I->SuperClasses.push_back(&RC);
979 }
980 }
981
982 // With the class hierarchy in place, let synthesized register classes inherit
983 // properties from their closest super-class. The iteration order here can
984 // propagate properties down multiple levels.
985 for (auto &RC : RegClasses)
986 if (!RC.getDef())
987 RC.inheritProperties(RegBank);
988}
989
990Optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
991CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
992 CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const {
993 auto SizeOrder = [](const CodeGenRegisterClass *A,
994 const CodeGenRegisterClass *B) {
995 return A->getMembers().size() > B->getMembers().size();
996 };
997
998 auto &RegClasses = RegBank.getRegClasses();
999
1000 // Find all the subclasses of this one that fully support the sub-register
1001 // index and order them by size. BiggestSuperRC should always be first.
1002 CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx);
1003 if (!BiggestSuperRegRC)
1004 return None;
1005 BitVector SuperRegRCsBV = BiggestSuperRegRC->getSubClasses();
1006 std::vector<CodeGenRegisterClass *> SuperRegRCs;
1007 for (auto &RC : RegClasses)
1008 if (SuperRegRCsBV[RC.EnumValue])
1009 SuperRegRCs.emplace_back(&RC);
1010 llvm::sort(SuperRegRCs, SizeOrder);
1011 assert(SuperRegRCs.front() == BiggestSuperRegRC && "Biggest class wasn't first")((SuperRegRCs.front() == BiggestSuperRegRC && "Biggest class wasn't first"
) ? static_cast<void> (0) : __assert_fail ("SuperRegRCs.front() == BiggestSuperRegRC && \"Biggest class wasn't first\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1011, __PRETTY_FUNCTION__))
;
1012
1013 // Find all the subreg classes and order them by size too.
1014 std::vector<std::pair<CodeGenRegisterClass *, BitVector>> SuperRegClasses;
1015 for (auto &RC: RegClasses) {
1016 BitVector SuperRegClassesBV(RegClasses.size());
1017 RC.getSuperRegClasses(SubIdx, SuperRegClassesBV);
1018 if (SuperRegClassesBV.any())
1019 SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV));
1020 }
1021 llvm::sort(SuperRegClasses,
1022 [&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
1023 const std::pair<CodeGenRegisterClass *, BitVector> &B) {
1024 return SizeOrder(A.first, B.first);
1025 });
1026
1027 // Find the biggest subclass and subreg class such that R:subidx is in the
1028 // subreg class for all R in subclass.
1029 //
1030 // For example:
1031 // All registers in X86's GR64 have a sub_32bit subregister but no class
1032 // exists that contains all the 32-bit subregisters because GR64 contains RIP
1033 // but GR32 does not contain EIP. Instead, we constrain SuperRegRC to
1034 // GR32_with_sub_8bit (which is identical to GR32_with_sub_32bit) and then,
1035 // having excluded RIP, we are able to find a SubRegRC (GR32).
1036 CodeGenRegisterClass *ChosenSuperRegClass = nullptr;
1037 CodeGenRegisterClass *SubRegRC = nullptr;
1038 for (auto *SuperRegRC : SuperRegRCs) {
1039 for (const auto &SuperRegClassPair : SuperRegClasses) {
1040 const BitVector &SuperRegClassBV = SuperRegClassPair.second;
1041 if (SuperRegClassBV[SuperRegRC->EnumValue]) {
1042 SubRegRC = SuperRegClassPair.first;
1043 ChosenSuperRegClass = SuperRegRC;
1044
1045 // If SubRegRC is bigger than SuperRegRC then there are members of
1046 // SubRegRC that don't have super registers via SubIdx. Keep looking to
1047 // find a better fit and fall back on this one if there isn't one.
1048 //
1049 // This is intended to prevent X86 from making odd choices such as
1050 // picking LOW32_ADDR_ACCESS_RBP instead of GR32 in the example above.
1051 // LOW32_ADDR_ACCESS_RBP is a valid choice but contains registers that
1052 // aren't subregisters of SuperRegRC whereas GR32 has a direct 1:1
1053 // mapping.
1054 if (SuperRegRC->getMembers().size() >= SubRegRC->getMembers().size())
1055 return std::make_pair(ChosenSuperRegClass, SubRegRC);
1056 }
1057 }
1058
1059 // If we found a fit but it wasn't quite ideal because SubRegRC had excess
1060 // registers, then we're done.
1061 if (ChosenSuperRegClass)
1062 return std::make_pair(ChosenSuperRegClass, SubRegRC);
1063 }
1064
1065 return None;
1066}
1067
1068void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
1069 BitVector &Out) const {
1070 auto FindI = SuperRegClasses.find(SubIdx);
1071 if (FindI == SuperRegClasses.end())
1072 return;
1073 for (CodeGenRegisterClass *RC : FindI->second)
1074 Out.set(RC->EnumValue);
1075}
1076
1077// Populate a unique sorted list of units from a register set.
1078void CodeGenRegisterClass::buildRegUnitSet(const CodeGenRegBank &RegBank,
1079 std::vector<unsigned> &RegUnits) const {
1080 std::vector<unsigned> TmpUnits;
1081 for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI) {
1082 const RegUnit &RU = RegBank.getRegUnit(*UnitI);
1083 if (!RU.Artificial)
1084 TmpUnits.push_back(*UnitI);
1085 }
1086 llvm::sort(TmpUnits);
1087 std::unique_copy(TmpUnits.begin(), TmpUnits.end(),
1088 std::back_inserter(RegUnits));
1089}
1090
1091//===----------------------------------------------------------------------===//
1092// CodeGenRegBank
1093//===----------------------------------------------------------------------===//
1094
1095CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
1096 const CodeGenHwModes &Modes) : CGH(Modes) {
1097 // Configure register Sets to understand register classes and tuples.
1098 Sets.addFieldExpander("RegisterClass", "MemberList");
1099 Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
1100 Sets.addExpander("RegisterTuples",
1101 std::make_unique<TupleExpander>(SynthDefs));
1102
1103 // Read in the user-defined (named) sub-register indices.
1104 // More indices will be synthesized later.
1105 std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
1106 llvm::sort(SRIs, LessRecord());
1107 for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
1108 getSubRegIdx(SRIs[i]);
1109 // Build composite maps from ComposedOf fields.
1110 for (auto &Idx : SubRegIndices)
1111 Idx.updateComponents(*this);
1112
1113 // Read in the register definitions.
1114 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
1115 llvm::sort(Regs, LessRecordRegister());
1116 // Assign the enumeration values.
1117 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
1118 getReg(Regs[i]);
1119
1120 // Expand tuples and number the new registers.
1121 std::vector<Record*> Tups =
1122 Records.getAllDerivedDefinitions("RegisterTuples");
1123
1124 for (Record *R : Tups) {
1125 std::vector<Record *> TupRegs = *Sets.expand(R);
1126 llvm::sort(TupRegs, LessRecordRegister());
1127 for (Record *RC : TupRegs)
1128 getReg(RC);
1129 }
1130
1131 // Now all the registers are known. Build the object graph of explicit
1132 // register-register references.
1133 for (auto &Reg : Registers)
1134 Reg.buildObjectGraph(*this);
1135
1136 // Compute register name map.
1137 for (auto &Reg : Registers)
1138 // FIXME: This could just be RegistersByName[name] = register, except that
1139 // causes some failures in MIPS - perhaps they have duplicate register name
1140 // entries? (or maybe there's a reason for it - I don't know much about this
1141 // code, just drive-by refactoring)
1142 RegistersByName.insert(
1143 std::make_pair(Reg.TheDef->getValueAsString("AsmName"), &Reg));
1144
1145 // Precompute all sub-register maps.
1146 // This will create Composite entries for all inferred sub-register indices.
1147 for (auto &Reg : Registers)
1148 Reg.computeSubRegs(*this);
1149
1150 // Compute transitive closure of subregister index ConcatenationOf vectors
1151 // and initialize ConcatIdx map.
1152 for (CodeGenSubRegIndex &SRI : SubRegIndices) {
1153 SRI.computeConcatTransitiveClosure();
1154 if (!SRI.ConcatenationOf.empty())
1155 ConcatIdx.insert(std::make_pair(
1156 SmallVector<CodeGenSubRegIndex*,8>(SRI.ConcatenationOf.begin(),
1157 SRI.ConcatenationOf.end()), &SRI));
1158 }
1159
1160 // Infer even more sub-registers by combining leading super-registers.
1161 for (auto &Reg : Registers)
1162 if (Reg.CoveredBySubRegs)
1163 Reg.computeSecondarySubRegs(*this);
1164
1165 // After the sub-register graph is complete, compute the topologically
1166 // ordered SuperRegs list.
1167 for (auto &Reg : Registers)
1168 Reg.computeSuperRegs(*this);
1169
1170 // For each pair of Reg:SR, if both are non-artificial, mark the
1171 // corresponding sub-register index as non-artificial.
1172 for (auto &Reg : Registers) {
1173 if (Reg.Artificial)
1174 continue;
1175 for (auto P : Reg.getSubRegs()) {
1176 const CodeGenRegister *SR = P.second;
1177 if (!SR->Artificial)
1178 P.first->Artificial = false;
1179 }
1180 }
1181
1182 // Native register units are associated with a leaf register. They've all been
1183 // discovered now.
1184 NumNativeRegUnits = RegUnits.size();
1185
1186 // Read in register class definitions.
1187 std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
1188 if (RCs.empty())
1189 PrintFatalError("No 'RegisterClass' subclasses defined!");
1190
1191 // Allocate user-defined register classes.
1192 for (auto *R : RCs) {
1193 RegClasses.emplace_back(*this, R);
1194 CodeGenRegisterClass &RC = RegClasses.back();
1195 if (!RC.Artificial)
1196 addToMaps(&RC);
1197 }
1198
1199 // Infer missing classes to create a full algebra.
1200 computeInferredRegisterClasses();
1201
1202 // Order register classes topologically and assign enum values.
1203 RegClasses.sort(TopoOrderRC);
1204 unsigned i = 0;
1205 for (auto &RC : RegClasses)
1206 RC.EnumValue = i++;
1207 CodeGenRegisterClass::computeSubClasses(*this);
1208}
1209
1210// Create a synthetic CodeGenSubRegIndex without a corresponding Record.
1211CodeGenSubRegIndex*
1212CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) {
1213 SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1);
1214 return &SubRegIndices.back();
1215}
1216
1217CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
1218 CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
1219 if (Idx)
1220 return Idx;
1221 SubRegIndices.emplace_back(Def, SubRegIndices.size() + 1);
1222 Idx = &SubRegIndices.back();
1223 return Idx;
1224}
1225
1226CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
1227 CodeGenRegister *&Reg = Def2Reg[Def];
1228 if (Reg)
1229 return Reg;
1230 Registers.emplace_back(Def, Registers.size() + 1);
1231 Reg = &Registers.back();
1232 return Reg;
1233}
1234
1235void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
1236 if (Record *Def = RC->getDef())
1237 Def2RC.insert(std::make_pair(Def, RC));
1238
1239 // Duplicate classes are rejected by insert().
1240 // That's OK, we only care about the properties handled by CGRC::Key.
1241 CodeGenRegisterClass::Key K(*RC);
1242 Key2RC.insert(std::make_pair(K, RC));
1243}
1244
1245// Create a synthetic sub-class if it is missing.
1246CodeGenRegisterClass*
1247CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
1248 const CodeGenRegister::Vec *Members,
1249 StringRef Name) {
1250 // Synthetic sub-class has the same size and alignment as RC.
1251 CodeGenRegisterClass::Key K(Members, RC->RSI);
1252 RCKeyMap::const_iterator FoundI = Key2RC.find(K);
1253 if (FoundI != Key2RC.end())
1254 return FoundI->second;
1255
1256 // Sub-class doesn't exist, create a new one.
1257 RegClasses.emplace_back(*this, Name, K);
1258 addToMaps(&RegClasses.back());
1259 return &RegClasses.back();
1260}
1261
1262CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
1263 if (CodeGenRegisterClass *RC = Def2RC[Def])
1264 return RC;
1265
1266 PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
1267}
1268
1269CodeGenSubRegIndex*
1270CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
1271 CodeGenSubRegIndex *B) {
1272 // Look for an existing entry.
1273 CodeGenSubRegIndex *Comp = A->compose(B);
1274 if (Comp)
1275 return Comp;
1276
1277 // None exists, synthesize one.
1278 std::string Name = A->getName() + "_then_" + B->getName();
1279 Comp = createSubRegIndex(Name, A->getNamespace());
1280 A->addComposite(B, Comp);
1281 return Comp;
1282}
1283
1284CodeGenSubRegIndex *CodeGenRegBank::
1285getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) {
1286 assert(Parts.size() > 1 && "Need two parts to concatenate")((Parts.size() > 1 && "Need two parts to concatenate"
) ? static_cast<void> (0) : __assert_fail ("Parts.size() > 1 && \"Need two parts to concatenate\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1286, __PRETTY_FUNCTION__))
;
1287#ifndef NDEBUG
1288 for (CodeGenSubRegIndex *Idx : Parts) {
1289 assert(Idx->ConcatenationOf.empty() && "No transitive closure?")((Idx->ConcatenationOf.empty() && "No transitive closure?"
) ? static_cast<void> (0) : __assert_fail ("Idx->ConcatenationOf.empty() && \"No transitive closure?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1289, __PRETTY_FUNCTION__))
;
1290 }
1291#endif
1292
1293 // Look for an existing entry.
1294 CodeGenSubRegIndex *&Idx = ConcatIdx[Parts];
1295 if (Idx)
1296 return Idx;
1297
1298 // None exists, synthesize one.
1299 std::string Name = Parts.front()->getName();
1300 // Determine whether all parts are contiguous.
1301 bool isContinuous = true;
1302 unsigned Size = Parts.front()->Size;
1303 unsigned LastOffset = Parts.front()->Offset;
1304 unsigned LastSize = Parts.front()->Size;
1305 for (unsigned i = 1, e = Parts.size(); i != e; ++i) {
1306 Name += '_';
1307 Name += Parts[i]->getName();
1308 Size += Parts[i]->Size;
1309 if (Parts[i]->Offset != (LastOffset + LastSize))
1310 isContinuous = false;
1311 LastOffset = Parts[i]->Offset;
1312 LastSize = Parts[i]->Size;
1313 }
1314 Idx = createSubRegIndex(Name, Parts.front()->getNamespace());
1315 Idx->Size = Size;
1316 Idx->Offset = isContinuous ? Parts.front()->Offset : -1;
1317 Idx->ConcatenationOf.assign(Parts.begin(), Parts.end());
1318 return Idx;
1319}
1320
1321void CodeGenRegBank::computeComposites() {
1322 using RegMap = std::map<const CodeGenRegister*, const CodeGenRegister*>;
1323
1324 // Subreg -> { Reg->Reg }, where the right-hand side is the mapping from
1325 // register to (sub)register associated with the action of the left-hand
1326 // side subregister.
1327 std::map<const CodeGenSubRegIndex*, RegMap> SubRegAction;
1328 for (const CodeGenRegister &R : Registers) {
1329 const CodeGenRegister::SubRegMap &SM = R.getSubRegs();
1330 for (std::pair<const CodeGenSubRegIndex*, const CodeGenRegister*> P : SM)
1331 SubRegAction[P.first].insert({&R, P.second});
1332 }
1333
1334 // Calculate the composition of two subregisters as compositions of their
1335 // associated actions.
1336 auto compose = [&SubRegAction] (const CodeGenSubRegIndex *Sub1,
1337 const CodeGenSubRegIndex *Sub2) {
1338 RegMap C;
1339 const RegMap &Img1 = SubRegAction.at(Sub1);
1340 const RegMap &Img2 = SubRegAction.at(Sub2);
1341 for (std::pair<const CodeGenRegister*, const CodeGenRegister*> P : Img1) {
1342 auto F = Img2.find(P.second);
1343 if (F != Img2.end())
1344 C.insert({P.first, F->second});
1345 }
1346 return C;
1347 };
1348
1349 // Check if the two maps agree on the intersection of their domains.
1350 auto agree = [] (const RegMap &Map1, const RegMap &Map2) {
1351 // Technically speaking, an empty map agrees with any other map, but
1352 // this could flag false positives. We're interested in non-vacuous
1353 // agreements.
1354 if (Map1.empty() || Map2.empty())
1355 return false;
1356 for (std::pair<const CodeGenRegister*, const CodeGenRegister*> P : Map1) {
1357 auto F = Map2.find(P.first);
1358 if (F == Map2.end() || P.second != F->second)
1359 return false;
1360 }
1361 return true;
1362 };
1363
1364 using CompositePair = std::pair<const CodeGenSubRegIndex*,
1365 const CodeGenSubRegIndex*>;
1366 SmallSet<CompositePair,4> UserDefined;
1367 for (const CodeGenSubRegIndex &Idx : SubRegIndices)
1368 for (auto P : Idx.getComposites())
1369 UserDefined.insert(std::make_pair(&Idx, P.first));
1370
1371 // Keep track of TopoSigs visited. We only need to visit each TopoSig once,
1372 // and many registers will share TopoSigs on regular architectures.
1373 BitVector TopoSigs(getNumTopoSigs());
1374
1375 for (const auto &Reg1 : Registers) {
1376 // Skip identical subreg structures already processed.
1377 if (TopoSigs.test(Reg1.getTopoSig()))
1378 continue;
1379 TopoSigs.set(Reg1.getTopoSig());
1380
1381 const CodeGenRegister::SubRegMap &SRM1 = Reg1.getSubRegs();
1382 for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
1383 e1 = SRM1.end(); i1 != e1; ++i1) {
1384 CodeGenSubRegIndex *Idx1 = i1->first;
1385 CodeGenRegister *Reg2 = i1->second;
1386 // Ignore identity compositions.
1387 if (&Reg1 == Reg2)
1388 continue;
1389 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
1390 // Try composing Idx1 with another SubRegIndex.
1391 for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
1392 e2 = SRM2.end(); i2 != e2; ++i2) {
1393 CodeGenSubRegIndex *Idx2 = i2->first;
1394 CodeGenRegister *Reg3 = i2->second;
1395 // Ignore identity compositions.
1396 if (Reg2 == Reg3)
1397 continue;
1398 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
1399 CodeGenSubRegIndex *Idx3 = Reg1.getSubRegIndex(Reg3);
1400 assert(Idx3 && "Sub-register doesn't have an index")((Idx3 && "Sub-register doesn't have an index") ? static_cast
<void> (0) : __assert_fail ("Idx3 && \"Sub-register doesn't have an index\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1400, __PRETTY_FUNCTION__))
;
1401
1402 // Conflicting composition? Emit a warning but allow it.
1403 if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, Idx3)) {
1404 // If the composition was not user-defined, always emit a warning.
1405 if (!UserDefined.count({Idx1, Idx2}) ||
1406 agree(compose(Idx1, Idx2), SubRegAction.at(Idx3)))
1407 PrintWarning(Twine("SubRegIndex ") + Idx1->getQualifiedName() +
1408 " and " + Idx2->getQualifiedName() +
1409 " compose ambiguously as " + Prev->getQualifiedName() +
1410 " or " + Idx3->getQualifiedName());
1411 }
1412 }
1413 }
1414 }
1415}
1416
1417// Compute lane masks. This is similar to register units, but at the
1418// sub-register index level. Each bit in the lane mask is like a register unit
1419// class, and two lane masks will have a bit in common if two sub-register
1420// indices overlap in some register.
1421//
1422// Conservatively share a lane mask bit if two sub-register indices overlap in
1423// some registers, but not in others. That shouldn't happen a lot.
1424void CodeGenRegBank::computeSubRegLaneMasks() {
1425 // First assign individual bits to all the leaf indices.
1426 unsigned Bit = 0;
1427 // Determine mask of lanes that cover their registers.
1428 CoveringLanes = LaneBitmask::getAll();
1429 for (auto &Idx : SubRegIndices) {
1430 if (Idx.getComposites().empty()) {
1431 if (Bit > LaneBitmask::BitWidth) {
1432 PrintFatalError(
1433 Twine("Ran out of lanemask bits to represent subregister ")
1434 + Idx.getName());
1435 }
1436 Idx.LaneMask = LaneBitmask::getLane(Bit);
1437 ++Bit;
1438 } else {
1439 Idx.LaneMask = LaneBitmask::getNone();
1440 }
1441 }
1442
1443 // Compute transformation sequences for composeSubRegIndexLaneMask. The idea
1444 // here is that for each possible target subregister we look at the leafs
1445 // in the subregister graph that compose for this target and create
1446 // transformation sequences for the lanemasks. Each step in the sequence
1447 // consists of a bitmask and a bitrotate operation. As the rotation amounts
1448 // are usually the same for many subregisters we can easily combine the steps
1449 // by combining the masks.
1450 for (const auto &Idx : SubRegIndices) {
1451 const auto &Composites = Idx.getComposites();
1452 auto &LaneTransforms = Idx.CompositionLaneMaskTransform;
1453
1454 if (Composites.empty()) {
2
Assuming the condition is true
3
Taking true branch
1455 // Moving from a class with no subregisters we just had a single lane:
1456 // The subregister must be a leaf subregister and only occupies 1 bit.
1457 // Move the bit from the class without subregisters into that position.
1458 unsigned DstBit = Idx.LaneMask.getHighestLane();
4
Calling 'LaneBitmask::getHighestLane'
9
Returning from 'LaneBitmask::getHighestLane'
10
'DstBit' initialized to 4294967295
1459 assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) &&((Idx.LaneMask == LaneBitmask::getLane(DstBit) && "Must be a leaf subregister"
) ? static_cast<void> (0) : __assert_fail ("Idx.LaneMask == LaneBitmask::getLane(DstBit) && \"Must be a leaf subregister\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1460, __PRETTY_FUNCTION__))
11
Passing the value 4294967295 via 1st parameter 'Lane'
12
Calling 'LaneBitmask::getLane'
1460 "Must be a leaf subregister")((Idx.LaneMask == LaneBitmask::getLane(DstBit) && "Must be a leaf subregister"
) ? static_cast<void> (0) : __assert_fail ("Idx.LaneMask == LaneBitmask::getLane(DstBit) && \"Must be a leaf subregister\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1460, __PRETTY_FUNCTION__))
;
1461 MaskRolPair MaskRol = { LaneBitmask::getLane(0), (uint8_t)DstBit };
1462 LaneTransforms.push_back(MaskRol);
1463 } else {
1464 // Go through all leaf subregisters and find the ones that compose with
1465 // Idx. These make out all possible valid bits in the lane mask we want to
1466 // transform. Looking only at the leafs ensure that only a single bit in
1467 // the mask is set.
1468 unsigned NextBit = 0;
1469 for (auto &Idx2 : SubRegIndices) {
1470 // Skip non-leaf subregisters.
1471 if (!Idx2.getComposites().empty())
1472 continue;
1473 // Replicate the behaviour from the lane mask generation loop above.
1474 unsigned SrcBit = NextBit;
1475 LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit);
1476 if (NextBit < LaneBitmask::BitWidth-1)
1477 ++NextBit;
1478 assert(Idx2.LaneMask == SrcMask)((Idx2.LaneMask == SrcMask) ? static_cast<void> (0) : __assert_fail
("Idx2.LaneMask == SrcMask", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1478, __PRETTY_FUNCTION__))
;
1479
1480 // Get the composed subregister if there is any.
1481 auto C = Composites.find(&Idx2);
1482 if (C == Composites.end())
1483 continue;
1484 const CodeGenSubRegIndex *Composite = C->second;
1485 // The Composed subreg should be a leaf subreg too
1486 assert(Composite->getComposites().empty())((Composite->getComposites().empty()) ? static_cast<void
> (0) : __assert_fail ("Composite->getComposites().empty()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1486, __PRETTY_FUNCTION__))
;
1487
1488 // Create Mask+Rotate operation and merge with existing ops if possible.
1489 unsigned DstBit = Composite->LaneMask.getHighestLane();
1490 int Shift = DstBit - SrcBit;
1491 uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift
1492 : LaneBitmask::BitWidth + Shift;
1493 for (auto &I : LaneTransforms) {
1494 if (I.RotateLeft == RotateLeft) {
1495 I.Mask |= SrcMask;
1496 SrcMask = LaneBitmask::getNone();
1497 }
1498 }
1499 if (SrcMask.any()) {
1500 MaskRolPair MaskRol = { SrcMask, RotateLeft };
1501 LaneTransforms.push_back(MaskRol);
1502 }
1503 }
1504 }
1505
1506 // Optimize if the transformation consists of one step only: Set mask to
1507 // 0xffffffff (including some irrelevant invalid bits) so that it should
1508 // merge with more entries later while compressing the table.
1509 if (LaneTransforms.size() == 1)
1510 LaneTransforms[0].Mask = LaneBitmask::getAll();
1511
1512 // Further compression optimization: For invalid compositions resulting
1513 // in a sequence with 0 entries we can just pick any other. Choose
1514 // Mask 0xffffffff with Rotation 0.
1515 if (LaneTransforms.size() == 0) {
1516 MaskRolPair P = { LaneBitmask::getAll(), 0 };
1517 LaneTransforms.push_back(P);
1518 }
1519 }
1520
1521 // FIXME: What if ad-hoc aliasing introduces overlaps that aren't represented
1522 // by the sub-register graph? This doesn't occur in any known targets.
1523
1524 // Inherit lanes from composites.
1525 for (const auto &Idx : SubRegIndices) {
1526 LaneBitmask Mask = Idx.computeLaneMask();
1527 // If some super-registers without CoveredBySubRegs use this index, we can
1528 // no longer assume that the lanes are covering their registers.
1529 if (!Idx.AllSuperRegsCovered)
1530 CoveringLanes &= ~Mask;
1531 }
1532
1533 // Compute lane mask combinations for register classes.
1534 for (auto &RegClass : RegClasses) {
1535 LaneBitmask LaneMask;
1536 for (const auto &SubRegIndex : SubRegIndices) {
1537 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
1538 continue;
1539 LaneMask |= SubRegIndex.LaneMask;
1540 }
1541
1542 // For classes without any subregisters set LaneMask to 1 instead of 0.
1543 // This makes it easier for client code to handle classes uniformly.
1544 if (LaneMask.none())
1545 LaneMask = LaneBitmask::getLane(0);
1546
1547 RegClass.LaneMask = LaneMask;
1548 }
1549}
1550
1551namespace {
1552
1553// UberRegSet is a helper class for computeRegUnitWeights. Each UberRegSet is
1554// the transitive closure of the union of overlapping register
1555// classes. Together, the UberRegSets form a partition of the registers. If we
1556// consider overlapping register classes to be connected, then each UberRegSet
1557// is a set of connected components.
1558//
1559// An UberRegSet will likely be a horizontal slice of register names of
1560// the same width. Nontrivial subregisters should then be in a separate
1561// UberRegSet. But this property isn't required for valid computation of
1562// register unit weights.
1563//
1564// A Weight field caches the max per-register unit weight in each UberRegSet.
1565//
1566// A set of SingularDeterminants flags single units of some register in this set
1567// for which the unit weight equals the set weight. These units should not have
1568// their weight increased.
1569struct UberRegSet {
1570 CodeGenRegister::Vec Regs;
1571 unsigned Weight = 0;
1572 CodeGenRegister::RegUnitList SingularDeterminants;
1573
1574 UberRegSet() = default;
1575};
1576
1577} // end anonymous namespace
1578
1579// Partition registers into UberRegSets, where each set is the transitive
1580// closure of the union of overlapping register classes.
1581//
1582// UberRegSets[0] is a special non-allocatable set.
1583static void computeUberSets(std::vector<UberRegSet> &UberSets,
1584 std::vector<UberRegSet*> &RegSets,
1585 CodeGenRegBank &RegBank) {
1586 const auto &Registers = RegBank.getRegisters();
1587
1588 // The Register EnumValue is one greater than its index into Registers.
1589 assert(Registers.size() == Registers.back().EnumValue &&((Registers.size() == Registers.back().EnumValue && "register enum value mismatch"
) ? static_cast<void> (0) : __assert_fail ("Registers.size() == Registers.back().EnumValue && \"register enum value mismatch\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1590, __PRETTY_FUNCTION__))
1590 "register enum value mismatch")((Registers.size() == Registers.back().EnumValue && "register enum value mismatch"
) ? static_cast<void> (0) : __assert_fail ("Registers.size() == Registers.back().EnumValue && \"register enum value mismatch\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1590, __PRETTY_FUNCTION__))
;
1591
1592 // For simplicitly make the SetID the same as EnumValue.
1593 IntEqClasses UberSetIDs(Registers.size()+1);
1594 std::set<unsigned> AllocatableRegs;
1595 for (auto &RegClass : RegBank.getRegClasses()) {
1596 if (!RegClass.Allocatable)
1597 continue;
1598
1599 const CodeGenRegister::Vec &Regs = RegClass.getMembers();
1600 if (Regs.empty())
1601 continue;
1602
1603 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue);
1604 assert(USetID && "register number 0 is invalid")((USetID && "register number 0 is invalid") ? static_cast
<void> (0) : __assert_fail ("USetID && \"register number 0 is invalid\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1604, __PRETTY_FUNCTION__))
;
1605
1606 AllocatableRegs.insert((*Regs.begin())->EnumValue);
1607 for (auto I = std::next(Regs.begin()), E = Regs.end(); I != E; ++I) {
1608 AllocatableRegs.insert((*I)->EnumValue);
1609 UberSetIDs.join(USetID, (*I)->EnumValue);
1610 }
1611 }
1612 // Combine non-allocatable regs.
1613 for (const auto &Reg : Registers) {
1614 unsigned RegNum = Reg.EnumValue;
1615 if (AllocatableRegs.count(RegNum))
1616 continue;
1617
1618 UberSetIDs.join(0, RegNum);
1619 }
1620 UberSetIDs.compress();
1621
1622 // Make the first UberSet a special unallocatable set.
1623 unsigned ZeroID = UberSetIDs[0];
1624
1625 // Insert Registers into the UberSets formed by union-find.
1626 // Do not resize after this.
1627 UberSets.resize(UberSetIDs.getNumClasses());
1628 unsigned i = 0;
1629 for (const CodeGenRegister &Reg : Registers) {
1630 unsigned USetID = UberSetIDs[Reg.EnumValue];
1631 if (!USetID)
1632 USetID = ZeroID;
1633 else if (USetID == ZeroID)
1634 USetID = 0;
1635
1636 UberRegSet *USet = &UberSets[USetID];
1637 USet->Regs.push_back(&Reg);
1638 sortAndUniqueRegisters(USet->Regs);
1639 RegSets[i++] = USet;
1640 }
1641}
1642
1643// Recompute each UberSet weight after changing unit weights.
1644static void computeUberWeights(std::vector<UberRegSet> &UberSets,
1645 CodeGenRegBank &RegBank) {
1646 // Skip the first unallocatable set.
1647 for (std::vector<UberRegSet>::iterator I = std::next(UberSets.begin()),
1648 E = UberSets.end(); I != E; ++I) {
1649
1650 // Initialize all unit weights in this set, and remember the max units/reg.
1651 const CodeGenRegister *Reg = nullptr;
1652 unsigned MaxWeight = 0, Weight = 0;
1653 for (RegUnitIterator UnitI(I->Regs); UnitI.isValid(); ++UnitI) {
1654 if (Reg != UnitI.getReg()) {
1655 if (Weight > MaxWeight)
1656 MaxWeight = Weight;
1657 Reg = UnitI.getReg();
1658 Weight = 0;
1659 }
1660 if (!RegBank.getRegUnit(*UnitI).Artificial) {
1661 unsigned UWeight = RegBank.getRegUnit(*UnitI).Weight;
1662 if (!UWeight) {
1663 UWeight = 1;
1664 RegBank.increaseRegUnitWeight(*UnitI, UWeight);
1665 }
1666 Weight += UWeight;
1667 }
1668 }
1669 if (Weight > MaxWeight)
1670 MaxWeight = Weight;
1671 if (I->Weight != MaxWeight) {
1672 LLVM_DEBUG(dbgs() << "UberSet " << I - UberSets.begin() << " Weight "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UberSet " << I
- UberSets.begin() << " Weight " << MaxWeight; for
(auto &Unit : I->Regs) dbgs() << " " << Unit
->getName(); dbgs() << "\n"; } } while (false)
1673 << MaxWeight;do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UberSet " << I
- UberSets.begin() << " Weight " << MaxWeight; for
(auto &Unit : I->Regs) dbgs() << " " << Unit
->getName(); dbgs() << "\n"; } } while (false)
1674 for (auto &Unitdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UberSet " << I
- UberSets.begin() << " Weight " << MaxWeight; for
(auto &Unit : I->Regs) dbgs() << " " << Unit
->getName(); dbgs() << "\n"; } } while (false)
1675 : I->Regs) dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UberSet " << I
- UberSets.begin() << " Weight " << MaxWeight; for
(auto &Unit : I->Regs) dbgs() << " " << Unit
->getName(); dbgs() << "\n"; } } while (false)
1676 << " " << Unit->getName();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UberSet " << I
- UberSets.begin() << " Weight " << MaxWeight; for
(auto &Unit : I->Regs) dbgs() << " " << Unit
->getName(); dbgs() << "\n"; } } while (false)
1677 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UberSet " << I
- UberSets.begin() << " Weight " << MaxWeight; for
(auto &Unit : I->Regs) dbgs() << " " << Unit
->getName(); dbgs() << "\n"; } } while (false)
;
1678 // Update the set weight.
1679 I->Weight = MaxWeight;
1680 }
1681
1682 // Find singular determinants.
1683 for (const auto R : I->Regs) {
1684 if (R->getRegUnits().count() == 1 && R->getWeight(RegBank) == I->Weight) {
1685 I->SingularDeterminants |= R->getRegUnits();
1686 }
1687 }
1688 }
1689}
1690
1691// normalizeWeight is a computeRegUnitWeights helper that adjusts the weight of
1692// a register and its subregisters so that they have the same weight as their
1693// UberSet. Self-recursion processes the subregister tree in postorder so
1694// subregisters are normalized first.
1695//
1696// Side effects:
1697// - creates new adopted register units
1698// - causes superregisters to inherit adopted units
1699// - increases the weight of "singular" units
1700// - induces recomputation of UberWeights.
1701static bool normalizeWeight(CodeGenRegister *Reg,
1702 std::vector<UberRegSet> &UberSets,
1703 std::vector<UberRegSet*> &RegSets,
1704 BitVector &NormalRegs,
1705 CodeGenRegister::RegUnitList &NormalUnits,
1706 CodeGenRegBank &RegBank) {
1707 NormalRegs.resize(std::max(Reg->EnumValue + 1, NormalRegs.size()));
1708 if (NormalRegs.test(Reg->EnumValue))
1709 return false;
1710 NormalRegs.set(Reg->EnumValue);
1711
1712 bool Changed = false;
1713 const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
1714 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(),
1715 SRE = SRM.end(); SRI != SRE; ++SRI) {
1716 if (SRI->second == Reg)
1717 continue; // self-cycles happen
1718
1719 Changed |= normalizeWeight(SRI->second, UberSets, RegSets,
1720 NormalRegs, NormalUnits, RegBank);
1721 }
1722 // Postorder register normalization.
1723
1724 // Inherit register units newly adopted by subregisters.
1725 if (Reg->inheritRegUnits(RegBank))
1726 computeUberWeights(UberSets, RegBank);
1727
1728 // Check if this register is too skinny for its UberRegSet.
1729 UberRegSet *UberSet = RegSets[RegBank.getRegIndex(Reg)];
1730
1731 unsigned RegWeight = Reg->getWeight(RegBank);
1732 if (UberSet->Weight > RegWeight) {
1733 // A register unit's weight can be adjusted only if it is the singular unit
1734 // for this register, has not been used to normalize a subregister's set,
1735 // and has not already been used to singularly determine this UberRegSet.
1736 unsigned AdjustUnit = *Reg->getRegUnits().begin();
1737 if (Reg->getRegUnits().count() != 1
1738 || hasRegUnit(NormalUnits, AdjustUnit)
1739 || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
1740 // We don't have an adjustable unit, so adopt a new one.
1741 AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight);
1742 Reg->adoptRegUnit(AdjustUnit);
1743 // Adopting a unit does not immediately require recomputing set weights.
1744 }
1745 else {
1746 // Adjust the existing single unit.
1747 if (!RegBank.getRegUnit(AdjustUnit).Artificial)
1748 RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight);
1749 // The unit may be shared among sets and registers within this set.
1750 computeUberWeights(UberSets, RegBank);
1751 }
1752 Changed = true;
1753 }
1754
1755 // Mark these units normalized so superregisters can't change their weights.
1756 NormalUnits |= Reg->getRegUnits();
1757
1758 return Changed;
1759}
1760
1761// Compute a weight for each register unit created during getSubRegs.
1762//
1763// The goal is that two registers in the same class will have the same weight,
1764// where each register's weight is defined as sum of its units' weights.
1765void CodeGenRegBank::computeRegUnitWeights() {
1766 std::vector<UberRegSet> UberSets;
1767 std::vector<UberRegSet*> RegSets(Registers.size());
1768 computeUberSets(UberSets, RegSets, *this);
1769 // UberSets and RegSets are now immutable.
1770
1771 computeUberWeights(UberSets, *this);
1772
1773 // Iterate over each Register, normalizing the unit weights until reaching
1774 // a fix point.
1775 unsigned NumIters = 0;
1776 for (bool Changed = true; Changed; ++NumIters) {
1777 assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights")((NumIters <= NumNativeRegUnits && "Runaway register unit weights"
) ? static_cast<void> (0) : __assert_fail ("NumIters <= NumNativeRegUnits && \"Runaway register unit weights\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1777, __PRETTY_FUNCTION__))
;
1778 Changed = false;
1779 for (auto &Reg : Registers) {
1780 CodeGenRegister::RegUnitList NormalUnits;
1781 BitVector NormalRegs;
1782 Changed |= normalizeWeight(&Reg, UberSets, RegSets, NormalRegs,
1783 NormalUnits, *this);
1784 }
1785 }
1786}
1787
1788// Find a set in UniqueSets with the same elements as Set.
1789// Return an iterator into UniqueSets.
1790static std::vector<RegUnitSet>::const_iterator
1791findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
1792 const RegUnitSet &Set) {
1793 std::vector<RegUnitSet>::const_iterator
1794 I = UniqueSets.begin(), E = UniqueSets.end();
1795 for(;I != E; ++I) {
1796 if (I->Units == Set.Units)
1797 break;
1798 }
1799 return I;
1800}
1801
1802// Return true if the RUSubSet is a subset of RUSuperSet.
1803static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
1804 const std::vector<unsigned> &RUSuperSet) {
1805 return std::includes(RUSuperSet.begin(), RUSuperSet.end(),
1806 RUSubSet.begin(), RUSubSet.end());
1807}
1808
1809/// Iteratively prune unit sets. Prune subsets that are close to the superset,
1810/// but with one or two registers removed. We occasionally have registers like
1811/// APSR and PC thrown in with the general registers. We also see many
1812/// special-purpose register subsets, such as tail-call and Thumb
1813/// encodings. Generating all possible overlapping sets is combinatorial and
1814/// overkill for modeling pressure. Ideally we could fix this statically in
1815/// tablegen by (1) having the target define register classes that only include
1816/// the allocatable registers and marking other classes as non-allocatable and
1817/// (2) having a way to mark special purpose classes as "don't-care" classes for
1818/// the purpose of pressure. However, we make an attempt to handle targets that
1819/// are not nicely defined by merging nearly identical register unit sets
1820/// statically. This generates smaller tables. Then, dynamically, we adjust the
1821/// set limit by filtering the reserved registers.
1822///
1823/// Merge sets only if the units have the same weight. For example, on ARM,
1824/// Q-tuples with ssub index 0 include all S regs but also include D16+. We
1825/// should not expand the S set to include D regs.
1826void CodeGenRegBank::pruneUnitSets() {
1827 assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets")((RegClassUnitSets.empty() && "this invalidates RegClassUnitSets"
) ? static_cast<void> (0) : __assert_fail ("RegClassUnitSets.empty() && \"this invalidates RegClassUnitSets\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1827, __PRETTY_FUNCTION__))
;
1828
1829 // Form an equivalence class of UnitSets with no significant difference.
1830 std::vector<unsigned> SuperSetIDs;
1831 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1832 SubIdx != EndIdx; ++SubIdx) {
1833 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1834 unsigned SuperIdx = 0;
1835 for (; SuperIdx != EndIdx; ++SuperIdx) {
1836 if (SuperIdx == SubIdx)
1837 continue;
1838
1839 unsigned UnitWeight = RegUnits[SubSet.Units[0]].Weight;
1840 const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
1841 if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
1842 && (SubSet.Units.size() + 3 > SuperSet.Units.size())
1843 && UnitWeight == RegUnits[SuperSet.Units[0]].Weight
1844 && UnitWeight == RegUnits[SuperSet.Units.back()].Weight) {
1845 LLVM_DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdxdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UnitSet " << SubIdx
<< " subsumed by " << SuperIdx << "\n"; } }
while (false)
1846 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UnitSet " << SubIdx
<< " subsumed by " << SuperIdx << "\n"; } }
while (false)
;
1847 // We can pick any of the set names for the merged set. Go for the
1848 // shortest one to avoid picking the name of one of the classes that are
1849 // artificially created by tablegen. So "FPR128_lo" instead of
1850 // "QQQQ_with_qsub3_in_FPR128_lo".
1851 if (RegUnitSets[SubIdx].Name.size() < RegUnitSets[SuperIdx].Name.size())
1852 RegUnitSets[SuperIdx].Name = RegUnitSets[SubIdx].Name;
1853 break;
1854 }
1855 }
1856 if (SuperIdx == EndIdx)
1857 SuperSetIDs.push_back(SubIdx);
1858 }
1859 // Populate PrunedUnitSets with each equivalence class's superset.
1860 std::vector<RegUnitSet> PrunedUnitSets(SuperSetIDs.size());
1861 for (unsigned i = 0, e = SuperSetIDs.size(); i != e; ++i) {
1862 unsigned SuperIdx = SuperSetIDs[i];
1863 PrunedUnitSets[i].Name = RegUnitSets[SuperIdx].Name;
1864 PrunedUnitSets[i].Units.swap(RegUnitSets[SuperIdx].Units);
1865 }
1866 RegUnitSets.swap(PrunedUnitSets);
1867}
1868
1869// Create a RegUnitSet for each RegClass that contains all units in the class
1870// including adopted units that are necessary to model register pressure. Then
1871// iteratively compute RegUnitSets such that the union of any two overlapping
1872// RegUnitSets is repreresented.
1873//
1874// RegisterInfoEmitter will map each RegClass to its RegUnitClass and any
1875// RegUnitSet that is a superset of that RegUnitClass.
1876void CodeGenRegBank::computeRegUnitSets() {
1877 assert(RegUnitSets.empty() && "dirty RegUnitSets")((RegUnitSets.empty() && "dirty RegUnitSets") ? static_cast
<void> (0) : __assert_fail ("RegUnitSets.empty() && \"dirty RegUnitSets\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1877, __PRETTY_FUNCTION__))
;
1878
1879 // Compute a unique RegUnitSet for each RegClass.
1880 auto &RegClasses = getRegClasses();
1881 for (auto &RC : RegClasses) {
1882 if (!RC.Allocatable || RC.Artificial)
1883 continue;
1884
1885 // Speculatively grow the RegUnitSets to hold the new set.
1886 RegUnitSets.resize(RegUnitSets.size() + 1);
1887 RegUnitSets.back().Name = RC.getName();
1888
1889 // Compute a sorted list of units in this class.
1890 RC.buildRegUnitSet(*this, RegUnitSets.back().Units);
1891
1892 // Find an existing RegUnitSet.
1893 std::vector<RegUnitSet>::const_iterator SetI =
1894 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1895 if (SetI != std::prev(RegUnitSets.end()))
1896 RegUnitSets.pop_back();
1897 }
1898
1899 LLVM_DEBUG(dbgs() << "\nBefore pruning:\n"; for (unsigned USIdx = 0,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore pruning:\n"
; for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx <
USEnd; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; }; } } while (false)
1900 USEnd = RegUnitSets.size();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore pruning:\n"
; for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx <
USEnd; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; }; } } while (false)
1901 USIdx < USEnd; ++USIdx) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore pruning:\n"
; for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx <
USEnd; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; }; } } while (false)
1902 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore pruning:\n"
; for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx <
USEnd; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; }; } } while (false)
1903 for (auto &U : RegUnitSets[USIdx].Units)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore pruning:\n"
; for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx <
USEnd; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; }; } } while (false)
1904 printRegUnitName(U);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore pruning:\n"
; for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx <
USEnd; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; }; } } while (false)
1905 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore pruning:\n"
; for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx <
USEnd; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; }; } } while (false)
1906 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore pruning:\n"
; for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx <
USEnd; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; }; } } while (false)
;
1907
1908 // Iteratively prune unit sets.
1909 pruneUnitSets();
1910
1911 LLVM_DEBUG(dbgs() << "\nBefore union:\n"; for (unsigned USIdx = 0,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore union:\n"; for
(unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx < USEnd
; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; } dbgs() << "\nUnion sets:\n"; } } while
(false)
1912 USEnd = RegUnitSets.size();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore union:\n"; for
(unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx < USEnd
; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; } dbgs() << "\nUnion sets:\n"; } } while
(false)
1913 USIdx < USEnd; ++USIdx) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore union:\n"; for
(unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx < USEnd
; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; } dbgs() << "\nUnion sets:\n"; } } while
(false)
1914 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore union:\n"; for
(unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx < USEnd
; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; } dbgs() << "\nUnion sets:\n"; } } while
(false)
1915 for (auto &U : RegUnitSets[USIdx].Units)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore union:\n"; for
(unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx < USEnd
; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; } dbgs() << "\nUnion sets:\n"; } } while
(false)
1916 printRegUnitName(U);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore union:\n"; for
(unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx < USEnd
; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; } dbgs() << "\nUnion sets:\n"; } } while
(false)
1917 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore union:\n"; for
(unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx < USEnd
; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; } dbgs() << "\nUnion sets:\n"; } } while
(false)
1918 } dbgs() << "\nUnion sets:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\nBefore union:\n"; for
(unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx < USEnd
; ++USIdx) { dbgs() << "UnitSet " << USIdx <<
" " << RegUnitSets[USIdx].Name << ":"; for (auto
&U : RegUnitSets[USIdx].Units) printRegUnitName(U); dbgs
() << "\n"; } dbgs() << "\nUnion sets:\n"; } } while
(false)
;
1919
1920 // Iterate over all unit sets, including new ones added by this loop.
1921 unsigned NumRegUnitSubSets = RegUnitSets.size();
1922 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
1923 // In theory, this is combinatorial. In practice, it needs to be bounded
1924 // by a small number of sets for regpressure to be efficient.
1925 // If the assert is hit, we need to implement pruning.
1926 assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference")((Idx < (2*NumRegUnitSubSets) && "runaway unit set inference"
) ? static_cast<void> (0) : __assert_fail ("Idx < (2*NumRegUnitSubSets) && \"runaway unit set inference\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 1926, __PRETTY_FUNCTION__))
;
1927
1928 // Compare new sets with all original classes.
1929 for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
1930 SearchIdx != EndIdx; ++SearchIdx) {
1931 std::set<unsigned> Intersection;
1932 std::set_intersection(RegUnitSets[Idx].Units.begin(),
1933 RegUnitSets[Idx].Units.end(),
1934 RegUnitSets[SearchIdx].Units.begin(),
1935 RegUnitSets[SearchIdx].Units.end(),
1936 std::inserter(Intersection, Intersection.begin()));
1937 if (Intersection.empty())
1938 continue;
1939
1940 // Speculatively grow the RegUnitSets to hold the new set.
1941 RegUnitSets.resize(RegUnitSets.size() + 1);
1942 RegUnitSets.back().Name =
1943 RegUnitSets[Idx].Name + "+" + RegUnitSets[SearchIdx].Name;
1944
1945 std::set_union(RegUnitSets[Idx].Units.begin(),
1946 RegUnitSets[Idx].Units.end(),
1947 RegUnitSets[SearchIdx].Units.begin(),
1948 RegUnitSets[SearchIdx].Units.end(),
1949 std::inserter(RegUnitSets.back().Units,
1950 RegUnitSets.back().Units.begin()));
1951
1952 // Find an existing RegUnitSet, or add the union to the unique sets.
1953 std::vector<RegUnitSet>::const_iterator SetI =
1954 findRegUnitSet(RegUnitSets, RegUnitSets.back());
1955 if (SetI != std::prev(RegUnitSets.end()))
1956 RegUnitSets.pop_back();
1957 else {
1958 LLVM_DEBUG(dbgs() << "UnitSet " << RegUnitSets.size() - 1 << " "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UnitSet " << RegUnitSets
.size() - 1 << " " << RegUnitSets.back().Name <<
":"; for (auto &U : RegUnitSets.back().Units) printRegUnitName
(U); dbgs() << "\n";; } } while (false)
1959 << RegUnitSets.back().Name << ":";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UnitSet " << RegUnitSets
.size() - 1 << " " << RegUnitSets.back().Name <<
":"; for (auto &U : RegUnitSets.back().Units) printRegUnitName
(U); dbgs() << "\n";; } } while (false)
1960 for (auto &Udo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UnitSet " << RegUnitSets
.size() - 1 << " " << RegUnitSets.back().Name <<
":"; for (auto &U : RegUnitSets.back().Units) printRegUnitName
(U); dbgs() << "\n";; } } while (false)
1961 : RegUnitSets.back().Units) printRegUnitName(U);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UnitSet " << RegUnitSets
.size() - 1 << " " << RegUnitSets.back().Name <<
":"; for (auto &U : RegUnitSets.back().Units) printRegUnitName
(U); dbgs() << "\n";; } } while (false)
1962 dbgs() << "\n";)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "UnitSet " << RegUnitSets
.size() - 1 << " " << RegUnitSets.back().Name <<
":"; for (auto &U : RegUnitSets.back().Units) printRegUnitName
(U); dbgs() << "\n";; } } while (false)
;
1963 }
1964 }
1965 }
1966
1967 // Iteratively prune unit sets after inferring supersets.
1968 pruneUnitSets();
1969
1970 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\n"; for (unsigned USIdx
= 0, USEnd = RegUnitSets.size(); USIdx < USEnd; ++USIdx) {
dbgs() << "UnitSet " << USIdx << " " <<
RegUnitSets[USIdx].Name << ":"; for (auto &U : RegUnitSets
[USIdx].Units) printRegUnitName(U); dbgs() << "\n"; }; }
} while (false)
1971 dbgs() << "\n"; for (unsigned USIdx = 0, USEnd = RegUnitSets.size();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\n"; for (unsigned USIdx
= 0, USEnd = RegUnitSets.size(); USIdx < USEnd; ++USIdx) {
dbgs() << "UnitSet " << USIdx << " " <<
RegUnitSets[USIdx].Name << ":"; for (auto &U : RegUnitSets
[USIdx].Units) printRegUnitName(U); dbgs() << "\n"; }; }
} while (false)
1972 USIdx < USEnd; ++USIdx) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\n"; for (unsigned USIdx
= 0, USEnd = RegUnitSets.size(); USIdx < USEnd; ++USIdx) {
dbgs() << "UnitSet " << USIdx << " " <<
RegUnitSets[USIdx].Name << ":"; for (auto &U : RegUnitSets
[USIdx].Units) printRegUnitName(U); dbgs() << "\n"; }; }
} while (false)
1973 dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name << ":";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\n"; for (unsigned USIdx
= 0, USEnd = RegUnitSets.size(); USIdx < USEnd; ++USIdx) {
dbgs() << "UnitSet " << USIdx << " " <<
RegUnitSets[USIdx].Name << ":"; for (auto &U : RegUnitSets
[USIdx].Units) printRegUnitName(U); dbgs() << "\n"; }; }
} while (false)
1974 for (auto &U : RegUnitSets[USIdx].Units)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\n"; for (unsigned USIdx
= 0, USEnd = RegUnitSets.size(); USIdx < USEnd; ++USIdx) {
dbgs() << "UnitSet " << USIdx << " " <<
RegUnitSets[USIdx].Name << ":"; for (auto &U : RegUnitSets
[USIdx].Units) printRegUnitName(U); dbgs() << "\n"; }; }
} while (false)
1975 printRegUnitName(U);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\n"; for (unsigned USIdx
= 0, USEnd = RegUnitSets.size(); USIdx < USEnd; ++USIdx) {
dbgs() << "UnitSet " << USIdx << " " <<
RegUnitSets[USIdx].Name << ":"; for (auto &U : RegUnitSets
[USIdx].Units) printRegUnitName(U); dbgs() << "\n"; }; }
} while (false)
1976 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\n"; for (unsigned USIdx
= 0, USEnd = RegUnitSets.size(); USIdx < USEnd; ++USIdx) {
dbgs() << "UnitSet " << USIdx << " " <<
RegUnitSets[USIdx].Name << ":"; for (auto &U : RegUnitSets
[USIdx].Units) printRegUnitName(U); dbgs() << "\n"; }; }
} while (false)
1977 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\n"; for (unsigned USIdx
= 0, USEnd = RegUnitSets.size(); USIdx < USEnd; ++USIdx) {
dbgs() << "UnitSet " << USIdx << " " <<
RegUnitSets[USIdx].Name << ":"; for (auto &U : RegUnitSets
[USIdx].Units) printRegUnitName(U); dbgs() << "\n"; }; }
} while (false)
;
1978
1979 // For each register class, list the UnitSets that are supersets.
1980 RegClassUnitSets.resize(RegClasses.size());
1981 int RCIdx = -1;
1982 for (auto &RC : RegClasses) {
1983 ++RCIdx;
1984 if (!RC.Allocatable)
1985 continue;
1986
1987 // Recompute the sorted list of units in this class.
1988 std::vector<unsigned> RCRegUnits;
1989 RC.buildRegUnitSet(*this, RCRegUnits);
1990
1991 // Don't increase pressure for unallocatable regclasses.
1992 if (RCRegUnits.empty())
1993 continue;
1994
1995 LLVM_DEBUG(dbgs() << "RC " << RC.getName() << " Units: \n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "RC " << RC.getName
() << " Units: \n"; for (auto U : RCRegUnits) printRegUnitName
(U); dbgs() << "\n UnitSetIDs:"; } } while (false)
1996 for (auto Udo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "RC " << RC.getName
() << " Units: \n"; for (auto U : RCRegUnits) printRegUnitName
(U); dbgs() << "\n UnitSetIDs:"; } } while (false)
1997 : RCRegUnits) printRegUnitName(U);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "RC " << RC.getName
() << " Units: \n"; for (auto U : RCRegUnits) printRegUnitName
(U); dbgs() << "\n UnitSetIDs:"; } } while (false)
1998 dbgs() << "\n UnitSetIDs:")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "RC " << RC.getName
() << " Units: \n"; for (auto U : RCRegUnits) printRegUnitName
(U); dbgs() << "\n UnitSetIDs:"; } } while (false)
;
1999
2000 // Find all supersets.
2001 for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
2002 USIdx != USEnd; ++USIdx) {
2003 if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) {
2004 LLVM_DEBUG(dbgs() << " " << USIdx)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << " " << USIdx; }
} while (false)
;
2005 RegClassUnitSets[RCIdx].push_back(USIdx);
2006 }
2007 }
2008 LLVM_DEBUG(dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc-emitter")) { dbgs() << "\n"; } } while (false
)
;
2009 assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass")((!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass"
) ? static_cast<void> (0) : __assert_fail ("!RegClassUnitSets[RCIdx].empty() && \"missing unit set for regclass\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 2009, __PRETTY_FUNCTION__))
;
2010 }
2011
2012 // For each register unit, ensure that we have the list of UnitSets that
2013 // contain the unit. Normally, this matches an existing list of UnitSets for a
2014 // register class. If not, we create a new entry in RegClassUnitSets as a
2015 // "fake" register class.
2016 for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits;
2017 UnitIdx < UnitEnd; ++UnitIdx) {
2018 std::vector<unsigned> RUSets;
2019 for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) {
2020 RegUnitSet &RUSet = RegUnitSets[i];
2021 if (!is_contained(RUSet.Units, UnitIdx))
2022 continue;
2023 RUSets.push_back(i);
2024 }
2025 unsigned RCUnitSetsIdx = 0;
2026 for (unsigned e = RegClassUnitSets.size();
2027 RCUnitSetsIdx != e; ++RCUnitSetsIdx) {
2028 if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) {
2029 break;
2030 }
2031 }
2032 RegUnits[UnitIdx].RegClassUnitSetsIdx = RCUnitSetsIdx;
2033 if (RCUnitSetsIdx == RegClassUnitSets.size()) {
2034 // Create a new list of UnitSets as a "fake" register class.
2035 RegClassUnitSets.resize(RCUnitSetsIdx + 1);
2036 RegClassUnitSets[RCUnitSetsIdx].swap(RUSets);
2037 }
2038 }
2039}
2040
2041void CodeGenRegBank::computeRegUnitLaneMasks() {
2042 for (auto &Register : Registers) {
2043 // Create an initial lane mask for all register units.
2044 const auto &RegUnits = Register.getRegUnits();
2045 CodeGenRegister::RegUnitLaneMaskList
2046 RegUnitLaneMasks(RegUnits.count(), LaneBitmask::getNone());
2047 // Iterate through SubRegisters.
2048 typedef CodeGenRegister::SubRegMap SubRegMap;
2049 const SubRegMap &SubRegs = Register.getSubRegs();
2050 for (SubRegMap::const_iterator S = SubRegs.begin(),
2051 SE = SubRegs.end(); S != SE; ++S) {
2052 CodeGenRegister *SubReg = S->second;
2053 // Ignore non-leaf subregisters, their lane masks are fully covered by
2054 // the leaf subregisters anyway.
2055 if (!SubReg->getSubRegs().empty())
2056 continue;
2057 CodeGenSubRegIndex *SubRegIndex = S->first;
2058 const CodeGenRegister *SubRegister = S->second;
2059 LaneBitmask LaneMask = SubRegIndex->LaneMask;
2060 // Distribute LaneMask to Register Units touched.
2061 for (unsigned SUI : SubRegister->getRegUnits()) {
2062 bool Found = false;
2063 unsigned u = 0;
2064 for (unsigned RU : RegUnits) {
2065 if (SUI == RU) {
2066 RegUnitLaneMasks[u] |= LaneMask;
2067 assert(!Found)((!Found) ? static_cast<void> (0) : __assert_fail ("!Found"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 2067, __PRETTY_FUNCTION__))
;
2068 Found = true;
2069 }
2070 ++u;
2071 }
2072 (void)Found;
2073 assert(Found)((Found) ? static_cast<void> (0) : __assert_fail ("Found"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 2073, __PRETTY_FUNCTION__))
;
2074 }
2075 }
2076 Register.setRegUnitLaneMasks(RegUnitLaneMasks);
2077 }
2078}
2079
2080void CodeGenRegBank::computeDerivedInfo() {
2081 computeComposites();
2082 computeSubRegLaneMasks();
1
Calling 'CodeGenRegBank::computeSubRegLaneMasks'
2083
2084 // Compute a weight for each register unit created during getSubRegs.
2085 // This may create adopted register units (with unit # >= NumNativeRegUnits).
2086 computeRegUnitWeights();
2087
2088 // Compute a unique set of RegUnitSets. One for each RegClass and inferred
2089 // supersets for the union of overlapping sets.
2090 computeRegUnitSets();
2091
2092 computeRegUnitLaneMasks();
2093
2094 // Compute register class HasDisjunctSubRegs/CoveredBySubRegs flag.
2095 for (CodeGenRegisterClass &RC : RegClasses) {
2096 RC.HasDisjunctSubRegs = false;
2097 RC.CoveredBySubRegs = true;
2098 for (const CodeGenRegister *Reg : RC.getMembers()) {
2099 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs;
2100 RC.CoveredBySubRegs &= Reg->CoveredBySubRegs;
2101 }
2102 }
2103
2104 // Get the weight of each set.
2105 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
2106 RegUnitSets[Idx].Weight = getRegUnitSetWeight(RegUnitSets[Idx].Units);
2107
2108 // Find the order of each set.
2109 RegUnitSetOrder.reserve(RegUnitSets.size());
2110 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx)
2111 RegUnitSetOrder.push_back(Idx);
2112
2113 llvm::stable_sort(RegUnitSetOrder, [this](unsigned ID1, unsigned ID2) {
2114 return getRegPressureSet(ID1).Units.size() <
2115 getRegPressureSet(ID2).Units.size();
2116 });
2117 for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) {
2118 RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx;
2119 }
2120}
2121
2122//
2123// Synthesize missing register class intersections.
2124//
2125// Make sure that sub-classes of RC exists such that getCommonSubClass(RC, X)
2126// returns a maximal register class for all X.
2127//
2128void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
2129 assert(!RegClasses.empty())((!RegClasses.empty()) ? static_cast<void> (0) : __assert_fail
("!RegClasses.empty()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 2129, __PRETTY_FUNCTION__))
;
2130 // Stash the iterator to the last element so that this loop doesn't visit
2131 // elements added by the getOrCreateSubClass call within it.
2132 for (auto I = RegClasses.begin(), E = std::prev(RegClasses.end());
2133 I != std::next(E); ++I) {
2134 CodeGenRegisterClass *RC1 = RC;
2135 CodeGenRegisterClass *RC2 = &*I;
2136 if (RC1 == RC2)
2137 continue;
2138
2139 // Compute the set intersection of RC1 and RC2.
2140 const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
2141 const CodeGenRegister::Vec &Memb2 = RC2->getMembers();
2142 CodeGenRegister::Vec Intersection;
2143 std::set_intersection(Memb1.begin(), Memb1.end(), Memb2.begin(),
2144 Memb2.end(),
2145 std::inserter(Intersection, Intersection.begin()),
2146 deref<std::less<>>());
2147
2148 // Skip disjoint class pairs.
2149 if (Intersection.empty())
2150 continue;
2151
2152 // If RC1 and RC2 have different spill sizes or alignments, use the
2153 // stricter one for sub-classing. If they are equal, prefer RC1.
2154 if (RC2->RSI.hasStricterSpillThan(RC1->RSI))
2155 std::swap(RC1, RC2);
2156
2157 getOrCreateSubClass(RC1, &Intersection,
2158 RC1->getName() + "_and_" + RC2->getName());
2159 }
2160}
2161
2162//
2163// Synthesize missing sub-classes for getSubClassWithSubReg().
2164//
2165// Make sure that the set of registers in RC with a given SubIdx sub-register
2166// form a register class. Update RC->SubClassWithSubReg.
2167//
2168void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
2169 // Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
2170 typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec,
2171 deref<std::less<>>>
2172 SubReg2SetMap;
2173
2174 // Compute the set of registers supporting each SubRegIndex.
2175 SubReg2SetMap SRSets;
2176 for (const auto R : RC->getMembers()) {
2177 if (R->Artificial)
2178 continue;
2179 const CodeGenRegister::SubRegMap &SRM = R->getSubRegs();
2180 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
2181 E = SRM.end(); I != E; ++I) {
2182 if (!I->first->Artificial)
2183 SRSets[I->first].push_back(R);
2184 }
2185 }
2186
2187 for (auto I : SRSets)
2188 sortAndUniqueRegisters(I.second);
2189
2190 // Find matching classes for all SRSets entries. Iterate in SubRegIndex
2191 // numerical order to visit synthetic indices last.
2192 for (const auto &SubIdx : SubRegIndices) {
2193 if (SubIdx.Artificial)
2194 continue;
2195 SubReg2SetMap::const_iterator I = SRSets.find(&SubIdx);
2196 // Unsupported SubRegIndex. Skip it.
2197 if (I == SRSets.end())
2198 continue;
2199 // In most cases, all RC registers support the SubRegIndex.
2200 if (I->second.size() == RC->getMembers().size()) {
2201 RC->setSubClassWithSubReg(&SubIdx, RC);
2202 continue;
2203 }
2204 // This is a real subset. See if we have a matching class.
2205 CodeGenRegisterClass *SubRC =
2206 getOrCreateSubClass(RC, &I->second,
2207 RC->getName() + "_with_" + I->first->getName());
2208 RC->setSubClassWithSubReg(&SubIdx, SubRC);
2209 }
2210}
2211
2212//
2213// Synthesize missing sub-classes of RC for getMatchingSuperRegClass().
2214//
2215// Create sub-classes of RC such that getMatchingSuperRegClass(RC, SubIdx, X)
2216// has a maximal result for any SubIdx and any X >= FirstSubRegRC.
2217//
2218
2219void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
2220 std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
2221 SmallVector<std::pair<const CodeGenRegister*,
2222 const CodeGenRegister*>, 16> SSPairs;
2223 BitVector TopoSigs(getNumTopoSigs());
2224
2225 // Iterate in SubRegIndex numerical order to visit synthetic indices last.
2226 for (auto &SubIdx : SubRegIndices) {
2227 // Skip indexes that aren't fully supported by RC's registers. This was
2228 // computed by inferSubClassWithSubReg() above which should have been
2229 // called first.
2230 if (RC->getSubClassWithSubReg(&SubIdx) != RC)
2231 continue;
2232
2233 // Build list of (Super, Sub) pairs for this SubIdx.
2234 SSPairs.clear();
2235 TopoSigs.reset();
2236 for (const auto Super : RC->getMembers()) {
2237 const CodeGenRegister *Sub = Super->getSubRegs().find(&SubIdx)->second;
2238 assert(Sub && "Missing sub-register")((Sub && "Missing sub-register") ? static_cast<void
> (0) : __assert_fail ("Sub && \"Missing sub-register\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 2238, __PRETTY_FUNCTION__))
;
2239 SSPairs.push_back(std::make_pair(Super, Sub));
2240 TopoSigs.set(Sub->getTopoSig());
2241 }
2242
2243 // Iterate over sub-register class candidates. Ignore classes created by
2244 // this loop. They will never be useful.
2245 // Store an iterator to the last element (not end) so that this loop doesn't
2246 // visit newly inserted elements.
2247 assert(!RegClasses.empty())((!RegClasses.empty()) ? static_cast<void> (0) : __assert_fail
("!RegClasses.empty()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 2247, __PRETTY_FUNCTION__))
;
2248 for (auto I = FirstSubRegRC, E = std::prev(RegClasses.end());
2249 I != std::next(E); ++I) {
2250 CodeGenRegisterClass &SubRC = *I;
2251 if (SubRC.Artificial)
2252 continue;
2253 // Topological shortcut: SubRC members have the wrong shape.
2254 if (!TopoSigs.anyCommon(SubRC.getTopoSigs()))
2255 continue;
2256 // Compute the subset of RC that maps into SubRC.
2257 CodeGenRegister::Vec SubSetVec;
2258 for (unsigned i = 0, e = SSPairs.size(); i != e; ++i)
2259 if (SubRC.contains(SSPairs[i].second))
2260 SubSetVec.push_back(SSPairs[i].first);
2261
2262 if (SubSetVec.empty())
2263 continue;
2264
2265 // RC injects completely into SubRC.
2266 sortAndUniqueRegisters(SubSetVec);
2267 if (SubSetVec.size() == SSPairs.size()) {
2268 SubRC.addSuperRegClass(&SubIdx, RC);
2269 continue;
2270 }
2271
2272 // Only a subset of RC maps into SubRC. Make sure it is represented by a
2273 // class.
2274 getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" +
2275 SubIdx.getName() + "_in_" +
2276 SubRC.getName());
2277 }
2278 }
2279}
2280
2281//
2282// Infer missing register classes.
2283//
2284void CodeGenRegBank::computeInferredRegisterClasses() {
2285 assert(!RegClasses.empty())((!RegClasses.empty()) ? static_cast<void> (0) : __assert_fail
("!RegClasses.empty()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 2285, __PRETTY_FUNCTION__))
;
2286 // When this function is called, the register classes have not been sorted
2287 // and assigned EnumValues yet. That means getSubClasses(),
2288 // getSuperClasses(), and hasSubClass() functions are defunct.
2289
2290 // Use one-before-the-end so it doesn't move forward when new elements are
2291 // added.
2292 auto FirstNewRC = std::prev(RegClasses.end());
2293
2294 // Visit all register classes, including the ones being added by the loop.
2295 // Watch out for iterator invalidation here.
2296 for (auto I = RegClasses.begin(), E = RegClasses.end(); I != E; ++I) {
2297 CodeGenRegisterClass *RC = &*I;
2298 if (RC->Artificial)
2299 continue;
2300
2301 // Synthesize answers for getSubClassWithSubReg().
2302 inferSubClassWithSubReg(RC);
2303
2304 // Synthesize answers for getCommonSubClass().
2305 inferCommonSubClass(RC);
2306
2307 // Synthesize answers for getMatchingSuperRegClass().
2308 inferMatchingSuperRegClass(RC);
2309
2310 // New register classes are created while this loop is running, and we need
2311 // to visit all of them. I particular, inferMatchingSuperRegClass needs
2312 // to match old super-register classes with sub-register classes created
2313 // after inferMatchingSuperRegClass was called. At this point,
2314 // inferMatchingSuperRegClass has checked SuperRC = [0..rci] with SubRC =
2315 // [0..FirstNewRC). We need to cover SubRC = [FirstNewRC..rci].
2316 if (I == FirstNewRC) {
2317 auto NextNewRC = std::prev(RegClasses.end());
2318 for (auto I2 = RegClasses.begin(), E2 = std::next(FirstNewRC); I2 != E2;
2319 ++I2)
2320 inferMatchingSuperRegClass(&*I2, E2);
2321 FirstNewRC = NextNewRC;
2322 }
2323 }
2324}
2325
2326/// getRegisterClassForRegister - Find the register class that contains the
2327/// specified physical register. If the register is not in a register class,
2328/// return null. If the register is in multiple classes, and the classes have a
2329/// superset-subset relationship and the same set of types, return the
2330/// superclass. Otherwise return null.
2331const CodeGenRegisterClass*
2332CodeGenRegBank::getRegClassForRegister(Record *R) {
2333 const CodeGenRegister *Reg = getReg(R);
2334 const CodeGenRegisterClass *FoundRC = nullptr;
2335 for (const auto &RC : getRegClasses()) {
2336 if (!RC.contains(Reg))
2337 continue;
2338
2339 // If this is the first class that contains the register,
2340 // make a note of it and go on to the next class.
2341 if (!FoundRC) {
2342 FoundRC = &RC;
2343 continue;
2344 }
2345
2346 // If a register's classes have different types, return null.
2347 if (RC.getValueTypes() != FoundRC->getValueTypes())
2348 return nullptr;
2349
2350 // Check to see if the previously found class that contains
2351 // the register is a subclass of the current class. If so,
2352 // prefer the superclass.
2353 if (RC.hasSubClass(FoundRC)) {
2354 FoundRC = &RC;
2355 continue;
2356 }
2357
2358 // Check to see if the previously found class that contains
2359 // the register is a superclass of the current class. If so,
2360 // prefer the superclass.
2361 if (FoundRC->hasSubClass(&RC))
2362 continue;
2363
2364 // Multiple classes, and neither is a superclass of the other.
2365 // Return null.
2366 return nullptr;
2367 }
2368 return FoundRC;
2369}
2370
2371const CodeGenRegisterClass *
2372CodeGenRegBank::getMinimalPhysRegClass(Record *RegRecord,
2373 ValueTypeByHwMode *VT) {
2374 const CodeGenRegister *Reg = getReg(RegRecord);
2375 const CodeGenRegisterClass *BestRC = nullptr;
2376 for (const auto &RC : getRegClasses()) {
2377 if ((!VT || RC.hasType(*VT)) &&
2378 RC.contains(Reg) && (!BestRC || BestRC->hasSubClass(&RC)))
2379 BestRC = &RC;
2380 }
2381
2382 assert(BestRC && "Couldn't find the register class")((BestRC && "Couldn't find the register class") ? static_cast
<void> (0) : __assert_fail ("BestRC && \"Couldn't find the register class\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/utils/TableGen/CodeGenRegisters.cpp"
, 2382, __PRETTY_FUNCTION__))
;
2383 return BestRC;
2384}
2385
2386BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
2387 SetVector<const CodeGenRegister*> Set;
2388
2389 // First add Regs with all sub-registers.
2390 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
2391 CodeGenRegister *Reg = getReg(Regs[i]);
2392 if (Set.insert(Reg))
2393 // Reg is new, add all sub-registers.
2394 // The pre-ordering is not important here.
2395 Reg->addSubRegsPreOrder(Set, *this);
2396 }
2397
2398 // Second, find all super-registers that are completely covered by the set.
2399 for (unsigned i = 0; i != Set.size(); ++i) {
2400 const CodeGenRegister::SuperRegList &SR = Set[i]->getSuperRegs();
2401 for (unsigned j = 0, e = SR.size(); j != e; ++j) {
2402 const CodeGenRegister *Super = SR[j];
2403 if (!Super->CoveredBySubRegs || Set.count(Super))
2404 continue;
2405 // This new super-register is covered by its sub-registers.
2406 bool AllSubsInSet = true;
2407 const CodeGenRegister::SubRegMap &SRM = Super->getSubRegs();
2408 for (CodeGenRegister::SubRegMap::const_iterator I = SRM.begin(),
2409 E = SRM.end(); I != E; ++I)
2410 if (!Set.count(I->second)) {
2411 AllSubsInSet = false;
2412 break;
2413 }
2414 // All sub-registers in Set, add Super as well.
2415 // We will visit Super later to recheck its super-registers.
2416 if (AllSubsInSet)
2417 Set.insert(Super);
2418 }
2419 }
2420
2421 // Convert to BitVector.
2422 BitVector BV(Registers.size() + 1);
2423 for (unsigned i = 0, e = Set.size(); i != e; ++i)
2424 BV.set(Set[i]->EnumValue);
2425 return BV;
2426}
2427
2428void CodeGenRegBank::printRegUnitName(unsigned Unit) const {
2429 if (Unit < NumNativeRegUnits)
2430 dbgs() << ' ' << RegUnits[Unit].Roots[0]->getName();
2431 else
2432 dbgs() << " #" << Unit;
2433}

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/MC/LaneBitmask.h

1//===- llvm/MC/LaneBitmask.h ------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// A common definition of LaneBitmask for use in TableGen and CodeGen.
11///
12/// A lane mask is a bitmask representing the covering of a register with
13/// sub-registers.
14///
15/// This is typically used to track liveness at sub-register granularity.
16/// Lane masks for sub-register indices are similar to register units for
17/// physical registers. The individual bits in a lane mask can't be assigned
18/// any specific meaning. They can be used to check if two sub-register
19/// indices overlap.
20///
21/// Iff the target has a register such that:
22///
23/// getSubReg(Reg, A) overlaps getSubReg(Reg, B)
24///
25/// then:
26///
27/// (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0
28
29#ifndef LLVM_MC_LANEBITMASK_H
30#define LLVM_MC_LANEBITMASK_H
31
32#include "llvm/Support/Compiler.h"
33#include "llvm/Support/Format.h"
34#include "llvm/Support/Printable.h"
35#include "llvm/Support/raw_ostream.h"
36
37namespace llvm {
38
39 struct LaneBitmask {
40 // When changing the underlying type, change the format string as well.
41 using Type = unsigned;
42 enum : unsigned { BitWidth = 8*sizeof(Type) };
43 constexpr static const char *const FormatStr = "%08X";
44
45 constexpr LaneBitmask() = default;
46 explicit constexpr LaneBitmask(Type V) : Mask(V) {}
47
48 constexpr bool operator== (LaneBitmask M) const { return Mask == M.Mask; }
49 constexpr bool operator!= (LaneBitmask M) const { return Mask != M.Mask; }
50 constexpr bool operator< (LaneBitmask M) const { return Mask < M.Mask; }
51 constexpr bool none() const { return Mask == 0; }
52 constexpr bool any() const { return Mask != 0; }
53 constexpr bool all() const { return ~Mask == 0; }
54
55 constexpr LaneBitmask operator~() const {
56 return LaneBitmask(~Mask);
57 }
58 constexpr LaneBitmask operator|(LaneBitmask M) const {
59 return LaneBitmask(Mask | M.Mask);
60 }
61 constexpr LaneBitmask operator&(LaneBitmask M) const {
62 return LaneBitmask(Mask & M.Mask);
63 }
64 LaneBitmask &operator|=(LaneBitmask M) {
65 Mask |= M.Mask;
66 return *this;
67 }
68 LaneBitmask &operator&=(LaneBitmask M) {
69 Mask &= M.Mask;
70 return *this;
71 }
72
73 constexpr Type getAsInteger() const { return Mask; }
74
75 unsigned getNumLanes() const {
76 return countPopulation(Mask);
77 }
78 unsigned getHighestLane() const {
79 return Log2_32(Mask);
5
Calling 'Log2_32'
7
Returning from 'Log2_32'
8
Returning the value 4294967295
80 }
81
82 static constexpr LaneBitmask getNone() { return LaneBitmask(0); }
83 static constexpr LaneBitmask getAll() { return ~LaneBitmask(0); }
84 static constexpr LaneBitmask getLane(unsigned Lane) {
85 return LaneBitmask(Type(1) << Lane);
13
The result of the left shift is undefined due to shifting by '4294967295', which is greater or equal to the width of type 'llvm::LaneBitmask::Type'
86 }
87
88 private:
89 Type Mask = 0;
90 };
91
92 /// Create Printable object to print LaneBitmasks on a \ref raw_ostream.
93 inline Printable PrintLaneMask(LaneBitmask LaneMask) {
94 return Printable([LaneMask](raw_ostream &OS) {
95 OS << format(LaneBitmask::FormatStr, LaneMask.getAsInteger());
96 });
97 }
98
99} // end namespace llvm
100
101#endif // LLVM_MC_LANEBITMASK_H

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h

1//===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains some functions that are useful for math stuff.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_SUPPORT_MATHEXTRAS_H
14#define LLVM_SUPPORT_MATHEXTRAS_H
15
16#include "llvm/Support/Compiler.h"
17#include "llvm/Support/SwapByteOrder.h"
18#include <algorithm>
19#include <cassert>
20#include <climits>
21#include <cstring>
22#include <limits>
23#include <type_traits>
24
25#ifdef __ANDROID_NDK__
26#include <android/api-level.h>
27#endif
28
29#ifdef _MSC_VER
30// Declare these intrinsics manually rather including intrin.h. It's very
31// expensive, and MathExtras.h is popular.
32// #include <intrin.h>
33extern "C" {
34unsigned char _BitScanForward(unsigned long *_Index, unsigned long _Mask);
35unsigned char _BitScanForward64(unsigned long *_Index, unsigned __int64 _Mask);
36unsigned char _BitScanReverse(unsigned long *_Index, unsigned long _Mask);
37unsigned char _BitScanReverse64(unsigned long *_Index, unsigned __int64 _Mask);
38}
39#endif
40
41namespace llvm {
42
43/// The behavior an operation has on an input of 0.
44enum ZeroBehavior {
45 /// The returned value is undefined.
46 ZB_Undefined,
47 /// The returned value is numeric_limits<T>::max()
48 ZB_Max,
49 /// The returned value is numeric_limits<T>::digits
50 ZB_Width
51};
52
53/// Mathematical constants.
54namespace numbers {
55// TODO: Track C++20 std::numbers.
56// TODO: Favor using the hexadecimal FP constants (requires C++17).
57constexpr double e = 2.7182818284590452354, // (0x1.5bf0a8b145749P+1) https://oeis.org/A001113
58 egamma = .57721566490153286061, // (0x1.2788cfc6fb619P-1) https://oeis.org/A001620
59 ln2 = .69314718055994530942, // (0x1.62e42fefa39efP-1) https://oeis.org/A002162
60 ln10 = 2.3025850929940456840, // (0x1.24bb1bbb55516P+1) https://oeis.org/A002392
61 log2e = 1.4426950408889634074, // (0x1.71547652b82feP+0)
62 log10e = .43429448190325182765, // (0x1.bcb7b1526e50eP-2)
63 pi = 3.1415926535897932385, // (0x1.921fb54442d18P+1) https://oeis.org/A000796
64 inv_pi = .31830988618379067154, // (0x1.45f306bc9c883P-2) https://oeis.org/A049541
65 sqrtpi = 1.7724538509055160273, // (0x1.c5bf891b4ef6bP+0) https://oeis.org/A002161
66 inv_sqrtpi = .56418958354775628695, // (0x1.20dd750429b6dP-1) https://oeis.org/A087197
67 sqrt2 = 1.4142135623730950488, // (0x1.6a09e667f3bcdP+0) https://oeis.org/A00219
68 inv_sqrt2 = .70710678118654752440, // (0x1.6a09e667f3bcdP-1)
69 sqrt3 = 1.7320508075688772935, // (0x1.bb67ae8584caaP+0) https://oeis.org/A002194
70 inv_sqrt3 = .57735026918962576451, // (0x1.279a74590331cP-1)
71 phi = 1.6180339887498948482; // (0x1.9e3779b97f4a8P+0) https://oeis.org/A001622
72constexpr float ef = 2.71828183F, // (0x1.5bf0a8P+1) https://oeis.org/A001113
73 egammaf = .577215665F, // (0x1.2788d0P-1) https://oeis.org/A001620
74 ln2f = .693147181F, // (0x1.62e430P-1) https://oeis.org/A002162
75 ln10f = 2.30258509F, // (0x1.26bb1cP+1) https://oeis.org/A002392
76 log2ef = 1.44269504F, // (0x1.715476P+0)
77 log10ef = .434294482F, // (0x1.bcb7b2P-2)
78 pif = 3.14159265F, // (0x1.921fb6P+1) https://oeis.org/A000796
79 inv_pif = .318309886F, // (0x1.45f306P-2) https://oeis.org/A049541
80 sqrtpif = 1.77245385F, // (0x1.c5bf8aP+0) https://oeis.org/A002161
81 inv_sqrtpif = .564189584F, // (0x1.20dd76P-1) https://oeis.org/A087197
82 sqrt2f = 1.41421356F, // (0x1.6a09e6P+0) https://oeis.org/A002193
83 inv_sqrt2f = .707106781F, // (0x1.6a09e6P-1)
84 sqrt3f = 1.73205081F, // (0x1.bb67aeP+0) https://oeis.org/A002194
85 inv_sqrt3f = .577350269F, // (0x1.279a74P-1)
86 phif = 1.61803399F; // (0x1.9e377aP+0) https://oeis.org/A001622
87} // namespace numbers
88
89namespace detail {
90template <typename T, std::size_t SizeOfT> struct TrailingZerosCounter {
91 static unsigned count(T Val, ZeroBehavior) {
92 if (!Val)
93 return std::numeric_limits<T>::digits;
94 if (Val & 0x1)
95 return 0;
96
97 // Bisection method.
98 unsigned ZeroBits = 0;
99 T Shift = std::numeric_limits<T>::digits >> 1;
100 T Mask = std::numeric_limits<T>::max() >> Shift;
101 while (Shift) {
102 if ((Val & Mask) == 0) {
103 Val >>= Shift;
104 ZeroBits |= Shift;
105 }
106 Shift >>= 1;
107 Mask >>= Shift;
108 }
109 return ZeroBits;
110 }
111};
112
113#if defined(__GNUC__4) || defined(_MSC_VER)
114template <typename T> struct TrailingZerosCounter<T, 4> {
115 static unsigned count(T Val, ZeroBehavior ZB) {
116 if (ZB != ZB_Undefined && Val == 0)
117 return 32;
118
119#if __has_builtin(__builtin_ctz)1 || defined(__GNUC__4)
120 return __builtin_ctz(Val);
121#elif defined(_MSC_VER)
122 unsigned long Index;
123 _BitScanForward(&Index, Val);
124 return Index;
125#endif
126 }
127};
128
129#if !defined(_MSC_VER) || defined(_M_X64)
130template <typename T> struct TrailingZerosCounter<T, 8> {
131 static unsigned count(T Val, ZeroBehavior ZB) {
132 if (ZB != ZB_Undefined && Val == 0)
133 return 64;
134
135#if __has_builtin(__builtin_ctzll)1 || defined(__GNUC__4)
136 return __builtin_ctzll(Val);
137#elif defined(_MSC_VER)
138 unsigned long Index;
139 _BitScanForward64(&Index, Val);
140 return Index;
141#endif
142 }
143};
144#endif
145#endif
146} // namespace detail
147
148/// Count number of 0's from the least significant bit to the most
149/// stopping at the first 1.
150///
151/// Only unsigned integral types are allowed.
152///
153/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
154/// valid arguments.
155template <typename T>
156unsigned countTrailingZeros(T Val, ZeroBehavior ZB = ZB_Width) {
157 static_assert(std::numeric_limits<T>::is_integer &&
158 !std::numeric_limits<T>::is_signed,
159 "Only unsigned integral types are allowed.");
160 return llvm::detail::TrailingZerosCounter<T, sizeof(T)>::count(Val, ZB);
161}
162
163namespace detail {
164template <typename T, std::size_t SizeOfT> struct LeadingZerosCounter {
165 static unsigned count(T Val, ZeroBehavior) {
166 if (!Val)
167 return std::numeric_limits<T>::digits;
168
169 // Bisection method.
170 unsigned ZeroBits = 0;
171 for (T Shift = std::numeric_limits<T>::digits >> 1; Shift; Shift >>= 1) {
172 T Tmp = Val >> Shift;
173 if (Tmp)
174 Val = Tmp;
175 else
176 ZeroBits |= Shift;
177 }
178 return ZeroBits;
179 }
180};
181
182#if defined(__GNUC__4) || defined(_MSC_VER)
183template <typename T> struct LeadingZerosCounter<T, 4> {
184 static unsigned count(T Val, ZeroBehavior ZB) {
185 if (ZB != ZB_Undefined && Val == 0)
186 return 32;
187
188#if __has_builtin(__builtin_clz)1 || defined(__GNUC__4)
189 return __builtin_clz(Val);
190#elif defined(_MSC_VER)
191 unsigned long Index;
192 _BitScanReverse(&Index, Val);
193 return Index ^ 31;
194#endif
195 }
196};
197
198#if !defined(_MSC_VER) || defined(_M_X64)
199template <typename T> struct LeadingZerosCounter<T, 8> {
200 static unsigned count(T Val, ZeroBehavior ZB) {
201 if (ZB != ZB_Undefined && Val == 0)
202 return 64;
203
204#if __has_builtin(__builtin_clzll)1 || defined(__GNUC__4)
205 return __builtin_clzll(Val);
206#elif defined(_MSC_VER)
207 unsigned long Index;
208 _BitScanReverse64(&Index, Val);
209 return Index ^ 63;
210#endif
211 }
212};
213#endif
214#endif
215} // namespace detail
216
217/// Count number of 0's from the most significant bit to the least
218/// stopping at the first 1.
219///
220/// Only unsigned integral types are allowed.
221///
222/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are
223/// valid arguments.
224template <typename T>
225unsigned countLeadingZeros(T Val, ZeroBehavior ZB = ZB_Width) {
226 static_assert(std::numeric_limits<T>::is_integer &&
227 !std::numeric_limits<T>::is_signed,
228 "Only unsigned integral types are allowed.");
229 return llvm::detail::LeadingZerosCounter<T, sizeof(T)>::count(Val, ZB);
230}
231
232/// Get the index of the first set bit starting from the least
233/// significant bit.
234///
235/// Only unsigned integral types are allowed.
236///
237/// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined are
238/// valid arguments.
239template <typename T> T findFirstSet(T Val, ZeroBehavior ZB = ZB_Max) {
240 if (ZB == ZB_Max && Val == 0)
241 return std::numeric_limits<T>::max();
242
243 return countTrailingZeros(Val, ZB_Undefined);
244}
245
246/// Create a bitmask with the N right-most bits set to 1, and all other
247/// bits set to 0. Only unsigned types are allowed.
248template <typename T> T maskTrailingOnes(unsigned N) {
249 static_assert(std::is_unsigned<T>::value, "Invalid type!");
250 const unsigned Bits = CHAR_BIT8 * sizeof(T);
251 assert(N <= Bits && "Invalid bit index")((N <= Bits && "Invalid bit index") ? static_cast<
void> (0) : __assert_fail ("N <= Bits && \"Invalid bit index\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h"
, 251, __PRETTY_FUNCTION__))
;
252 return N == 0 ? 0 : (T(-1) >> (Bits - N));
253}
254
255/// Create a bitmask with the N left-most bits set to 1, and all other
256/// bits set to 0. Only unsigned types are allowed.
257template <typename T> T maskLeadingOnes(unsigned N) {
258 return ~maskTrailingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
259}
260
261/// Create a bitmask with the N right-most bits set to 0, and all other
262/// bits set to 1. Only unsigned types are allowed.
263template <typename T> T maskTrailingZeros(unsigned N) {
264 return maskLeadingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
265}
266
267/// Create a bitmask with the N left-most bits set to 0, and all other
268/// bits set to 1. Only unsigned types are allowed.
269template <typename T> T maskLeadingZeros(unsigned N) {
270 return maskTrailingOnes<T>(CHAR_BIT8 * sizeof(T) - N);
271}
272
273/// Get the index of the last set bit starting from the least
274/// significant bit.
275///
276/// Only unsigned integral types are allowed.
277///
278/// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined are
279/// valid arguments.
280template <typename T> T findLastSet(T Val, ZeroBehavior ZB = ZB_Max) {
281 if (ZB == ZB_Max && Val == 0)
282 return std::numeric_limits<T>::max();
283
284 // Use ^ instead of - because both gcc and llvm can remove the associated ^
285 // in the __builtin_clz intrinsic on x86.
286 return countLeadingZeros(Val, ZB_Undefined) ^
287 (std::numeric_limits<T>::digits - 1);
288}
289
290/// Macro compressed bit reversal table for 256 bits.
291///
292/// http://graphics.stanford.edu/~seander/bithacks.html#BitReverseTable
293static const unsigned char BitReverseTable256[256] = {
294#define R2(n) n, n + 2 * 64, n + 1 * 64, n + 3 * 64
295#define R4(n) R2(n), R2(n + 2 * 16), R2(n + 1 * 16), R2(n + 3 * 16)
296#define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4)
297 R6(0), R6(2), R6(1), R6(3)
298#undef R2
299#undef R4
300#undef R6
301};
302
303/// Reverse the bits in \p Val.
304template <typename T>
305T reverseBits(T Val) {
306 unsigned char in[sizeof(Val)];
307 unsigned char out[sizeof(Val)];
308 std::memcpy(in, &Val, sizeof(Val));
309 for (unsigned i = 0; i < sizeof(Val); ++i)
310 out[(sizeof(Val) - i) - 1] = BitReverseTable256[in[i]];
311 std::memcpy(&Val, out, sizeof(Val));
312 return Val;
313}
314
315// NOTE: The following support functions use the _32/_64 extensions instead of
316// type overloading so that signed and unsigned integers can be used without
317// ambiguity.
318
319/// Return the high 32 bits of a 64 bit value.
320constexpr inline uint32_t Hi_32(uint64_t Value) {
321 return static_cast<uint32_t>(Value >> 32);
322}
323
324/// Return the low 32 bits of a 64 bit value.
325constexpr inline uint32_t Lo_32(uint64_t Value) {
326 return static_cast<uint32_t>(Value);
327}
328
329/// Make a 64-bit integer from a high / low pair of 32-bit integers.
330constexpr inline uint64_t Make_64(uint32_t High, uint32_t Low) {
331 return ((uint64_t)High << 32) | (uint64_t)Low;
332}
333
334/// Checks if an integer fits into the given bit width.
335template <unsigned N> constexpr inline bool isInt(int64_t x) {
336 return N >= 64 || (-(INT64_C(1)1L<<(N-1)) <= x && x < (INT64_C(1)1L<<(N-1)));
337}
338// Template specializations to get better code for common cases.
339template <> constexpr inline bool isInt<8>(int64_t x) {
340 return static_cast<int8_t>(x) == x;
341}
342template <> constexpr inline bool isInt<16>(int64_t x) {
343 return static_cast<int16_t>(x) == x;
344}
345template <> constexpr inline bool isInt<32>(int64_t x) {
346 return static_cast<int32_t>(x) == x;
347}
348
349/// Checks if a signed integer is an N bit number shifted left by S.
350template <unsigned N, unsigned S>
351constexpr inline bool isShiftedInt(int64_t x) {
352 static_assert(
353 N > 0, "isShiftedInt<0> doesn't make sense (refers to a 0-bit number.");
354 static_assert(N + S <= 64, "isShiftedInt<N, S> with N + S > 64 is too wide.");
355 return isInt<N + S>(x) && (x % (UINT64_C(1)1UL << S) == 0);
356}
357
358/// Checks if an unsigned integer fits into the given bit width.
359///
360/// This is written as two functions rather than as simply
361///
362/// return N >= 64 || X < (UINT64_C(1) << N);
363///
364/// to keep MSVC from (incorrectly) warning on isUInt<64> that we're shifting
365/// left too many places.
366template <unsigned N>
367constexpr inline typename std::enable_if<(N < 64), bool>::type
368isUInt(uint64_t X) {
369 static_assert(N > 0, "isUInt<0> doesn't make sense");
370 return X < (UINT64_C(1)1UL << (N));
371}
372template <unsigned N>
373constexpr inline typename std::enable_if<N >= 64, bool>::type
374isUInt(uint64_t X) {
375 return true;
376}
377
378// Template specializations to get better code for common cases.
379template <> constexpr inline bool isUInt<8>(uint64_t x) {
380 return static_cast<uint8_t>(x) == x;
381}
382template <> constexpr inline bool isUInt<16>(uint64_t x) {
383 return static_cast<uint16_t>(x) == x;
384}
385template <> constexpr inline bool isUInt<32>(uint64_t x) {
386 return static_cast<uint32_t>(x) == x;
387}
388
389/// Checks if a unsigned integer is an N bit number shifted left by S.
390template <unsigned N, unsigned S>
391constexpr inline bool isShiftedUInt(uint64_t x) {
392 static_assert(
393 N > 0, "isShiftedUInt<0> doesn't make sense (refers to a 0-bit number)");
394 static_assert(N + S <= 64,
395 "isShiftedUInt<N, S> with N + S > 64 is too wide.");
396 // Per the two static_asserts above, S must be strictly less than 64. So
397 // 1 << S is not undefined behavior.
398 return isUInt<N + S>(x) && (x % (UINT64_C(1)1UL << S) == 0);
399}
400
401/// Gets the maximum value for a N-bit unsigned integer.
402inline uint64_t maxUIntN(uint64_t N) {
403 assert(N > 0 && N <= 64 && "integer width out of range")((N > 0 && N <= 64 && "integer width out of range"
) ? static_cast<void> (0) : __assert_fail ("N > 0 && N <= 64 && \"integer width out of range\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h"
, 403, __PRETTY_FUNCTION__))
;
404
405 // uint64_t(1) << 64 is undefined behavior, so we can't do
406 // (uint64_t(1) << N) - 1
407 // without checking first that N != 64. But this works and doesn't have a
408 // branch.
409 return UINT64_MAX(18446744073709551615UL) >> (64 - N);
410}
411
412/// Gets the minimum value for a N-bit signed integer.
413inline int64_t minIntN(int64_t N) {
414 assert(N > 0 && N <= 64 && "integer width out of range")((N > 0 && N <= 64 && "integer width out of range"
) ? static_cast<void> (0) : __assert_fail ("N > 0 && N <= 64 && \"integer width out of range\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h"
, 414, __PRETTY_FUNCTION__))
;
415
416 return -(UINT64_C(1)1UL<<(N-1));
417}
418
419/// Gets the maximum value for a N-bit signed integer.
420inline int64_t maxIntN(int64_t N) {
421 assert(N > 0 && N <= 64 && "integer width out of range")((N > 0 && N <= 64 && "integer width out of range"
) ? static_cast<void> (0) : __assert_fail ("N > 0 && N <= 64 && \"integer width out of range\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h"
, 421, __PRETTY_FUNCTION__))
;
422
423 // This relies on two's complement wraparound when N == 64, so we convert to
424 // int64_t only at the very end to avoid UB.
425 return (UINT64_C(1)1UL << (N - 1)) - 1;
426}
427
428/// Checks if an unsigned integer fits into the given (dynamic) bit width.
429inline bool isUIntN(unsigned N, uint64_t x) {
430 return N >= 64 || x <= maxUIntN(N);
431}
432
433/// Checks if an signed integer fits into the given (dynamic) bit width.
434inline bool isIntN(unsigned N, int64_t x) {
435 return N >= 64 || (minIntN(N) <= x && x <= maxIntN(N));
436}
437
438/// Return true if the argument is a non-empty sequence of ones starting at the
439/// least significant bit with the remainder zero (32 bit version).
440/// Ex. isMask_32(0x0000FFFFU) == true.
441constexpr inline bool isMask_32(uint32_t Value) {
442 return Value && ((Value + 1) & Value) == 0;
443}
444
445/// Return true if the argument is a non-empty sequence of ones starting at the
446/// least significant bit with the remainder zero (64 bit version).
447constexpr inline bool isMask_64(uint64_t Value) {
448 return Value && ((Value + 1) & Value) == 0;
449}
450
451/// Return true if the argument contains a non-empty sequence of ones with the
452/// remainder zero (32 bit version.) Ex. isShiftedMask_32(0x0000FF00U) == true.
453constexpr inline bool isShiftedMask_32(uint32_t Value) {
454 return Value && isMask_32((Value - 1) | Value);
455}
456
457/// Return true if the argument contains a non-empty sequence of ones with the
458/// remainder zero (64 bit version.)
459constexpr inline bool isShiftedMask_64(uint64_t Value) {
460 return Value && isMask_64((Value - 1) | Value);
461}
462
463/// Return true if the argument is a power of two > 0.
464/// Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.)
465constexpr inline bool isPowerOf2_32(uint32_t Value) {
466 return Value && !(Value & (Value - 1));
467}
468
469/// Return true if the argument is a power of two > 0 (64 bit edition.)
470constexpr inline bool isPowerOf2_64(uint64_t Value) {
471 return Value && !(Value & (Value - 1));
472}
473
474/// Return a byte-swapped representation of the 16-bit argument.
475inline uint16_t ByteSwap_16(uint16_t Value) {
476 return sys::SwapByteOrder_16(Value);
477}
478
479/// Return a byte-swapped representation of the 32-bit argument.
480inline uint32_t ByteSwap_32(uint32_t Value) {
481 return sys::SwapByteOrder_32(Value);
482}
483
484/// Return a byte-swapped representation of the 64-bit argument.
485inline uint64_t ByteSwap_64(uint64_t Value) {
486 return sys::SwapByteOrder_64(Value);
487}
488
489/// Count the number of ones from the most significant bit to the first
490/// zero bit.
491///
492/// Ex. countLeadingOnes(0xFF0FFF00) == 8.
493/// Only unsigned integral types are allowed.
494///
495/// \param ZB the behavior on an input of all ones. Only ZB_Width and
496/// ZB_Undefined are valid arguments.
497template <typename T>
498unsigned countLeadingOnes(T Value, ZeroBehavior ZB = ZB_Width) {
499 static_assert(std::numeric_limits<T>::is_integer &&
500 !std::numeric_limits<T>::is_signed,
501 "Only unsigned integral types are allowed.");
502 return countLeadingZeros<T>(~Value, ZB);
503}
504
505/// Count the number of ones from the least significant bit to the first
506/// zero bit.
507///
508/// Ex. countTrailingOnes(0x00FF00FF) == 8.
509/// Only unsigned integral types are allowed.
510///
511/// \param ZB the behavior on an input of all ones. Only ZB_Width and
512/// ZB_Undefined are valid arguments.
513template <typename T>
514unsigned countTrailingOnes(T Value, ZeroBehavior ZB = ZB_Width) {
515 static_assert(std::numeric_limits<T>::is_integer &&
516 !std::numeric_limits<T>::is_signed,
517 "Only unsigned integral types are allowed.");
518 return countTrailingZeros<T>(~Value, ZB);
519}
520
521namespace detail {
522template <typename T, std::size_t SizeOfT> struct PopulationCounter {
523 static unsigned count(T Value) {
524 // Generic version, forward to 32 bits.
525 static_assert(SizeOfT <= 4, "Not implemented!");
526#if defined(__GNUC__4)
527 return __builtin_popcount(Value);
528#else
529 uint32_t v = Value;
530 v = v - ((v >> 1) & 0x55555555);
531 v = (v & 0x33333333) + ((v >> 2) & 0x33333333);
532 return ((v + (v >> 4) & 0xF0F0F0F) * 0x1010101) >> 24;
533#endif
534 }
535};
536
537template <typename T> struct PopulationCounter<T, 8> {
538 static unsigned count(T Value) {
539#if defined(__GNUC__4)
540 return __builtin_popcountll(Value);
541#else
542 uint64_t v = Value;
543 v = v - ((v >> 1) & 0x5555555555555555ULL);
544 v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
545 v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
546 return unsigned((uint64_t)(v * 0x0101010101010101ULL) >> 56);
547#endif
548 }
549};
550} // namespace detail
551
552/// Count the number of set bits in a value.
553/// Ex. countPopulation(0xF000F000) = 8
554/// Returns 0 if the word is zero.
555template <typename T>
556inline unsigned countPopulation(T Value) {
557 static_assert(std::numeric_limits<T>::is_integer &&
558 !std::numeric_limits<T>::is_signed,
559 "Only unsigned integral types are allowed.");
560 return detail::PopulationCounter<T, sizeof(T)>::count(Value);
561}
562
563/// Compile time Log2.
564/// Valid only for positive powers of two.
565template <size_t kValue> constexpr inline size_t CTLog2() {
566 static_assert(kValue > 0 && llvm::isPowerOf2_64(kValue),
567 "Value is not a valid power of 2");
568 return 1 + CTLog2<kValue / 2>();
569}
570
571template <> constexpr inline size_t CTLog2<1>() { return 0; }
572
573/// Return the log base 2 of the specified value.
574inline double Log2(double Value) {
575#if defined(__ANDROID_API__) && __ANDROID_API__ < 18
576 return __builtin_log(Value) / __builtin_log(2.0);
577#else
578 return log2(Value);
579#endif
580}
581
582/// Return the floor log base 2 of the specified value, -1 if the value is zero.
583/// (32 bit edition.)
584/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
585inline unsigned Log2_32(uint32_t Value) {
586 return 31 - countLeadingZeros(Value);
6
Returning the value 4294967295
587}
588
589/// Return the floor log base 2 of the specified value, -1 if the value is zero.
590/// (64 bit edition.)
591inline unsigned Log2_64(uint64_t Value) {
592 return 63 - countLeadingZeros(Value);
593}
594
595/// Return the ceil log base 2 of the specified value, 32 if the value is zero.
596/// (32 bit edition).
597/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
598inline unsigned Log2_32_Ceil(uint32_t Value) {
599 return 32 - countLeadingZeros(Value - 1);
600}
601
602/// Return the ceil log base 2 of the specified value, 64 if the value is zero.
603/// (64 bit edition.)
604inline unsigned Log2_64_Ceil(uint64_t Value) {
605 return 64 - countLeadingZeros(Value - 1);
606}
607
608/// Return the greatest common divisor of the values using Euclid's algorithm.
609template <typename T>
610inline T greatestCommonDivisor(T A, T B) {
611 while (B) {
612 T Tmp = B;
613 B = A % B;
614 A = Tmp;
615 }
616 return A;
617}
618
619inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
620 return greatestCommonDivisor<uint64_t>(A, B);
621}
622
623/// This function takes a 64-bit integer and returns the bit equivalent double.
624inline double BitsToDouble(uint64_t Bits) {
625 double D;
626 static_assert(sizeof(uint64_t) == sizeof(double), "Unexpected type sizes");
627 memcpy(&D, &Bits, sizeof(Bits));
628 return D;
629}
630
631/// This function takes a 32-bit integer and returns the bit equivalent float.
632inline float BitsToFloat(uint32_t Bits) {
633 float F;
634 static_assert(sizeof(uint32_t) == sizeof(float), "Unexpected type sizes");
635 memcpy(&F, &Bits, sizeof(Bits));
636 return F;
637}
638
639/// This function takes a double and returns the bit equivalent 64-bit integer.
640/// Note that copying doubles around changes the bits of NaNs on some hosts,
641/// notably x86, so this routine cannot be used if these bits are needed.
642inline uint64_t DoubleToBits(double Double) {
643 uint64_t Bits;
644 static_assert(sizeof(uint64_t) == sizeof(double), "Unexpected type sizes");
645 memcpy(&Bits, &Double, sizeof(Double));
646 return Bits;
647}
648
649/// This function takes a float and returns the bit equivalent 32-bit integer.
650/// Note that copying floats around changes the bits of NaNs on some hosts,
651/// notably x86, so this routine cannot be used if these bits are needed.
652inline uint32_t FloatToBits(float Float) {
653 uint32_t Bits;
654 static_assert(sizeof(uint32_t) == sizeof(float), "Unexpected type sizes");
655 memcpy(&Bits, &Float, sizeof(Float));
656 return Bits;
657}
658
659/// A and B are either alignments or offsets. Return the minimum alignment that
660/// may be assumed after adding the two together.
661constexpr inline uint64_t MinAlign(uint64_t A, uint64_t B) {
662 // The largest power of 2 that divides both A and B.
663 //
664 // Replace "-Value" by "1+~Value" in the following commented code to avoid
665 // MSVC warning C4146
666 // return (A | B) & -(A | B);
667 return (A | B) & (1 + ~(A | B));
668}
669
670/// Returns the next power of two (in 64-bits) that is strictly greater than A.
671/// Returns zero on overflow.
672inline uint64_t NextPowerOf2(uint64_t A) {
673 A |= (A >> 1);
674 A |= (A >> 2);
675 A |= (A >> 4);
676 A |= (A >> 8);
677 A |= (A >> 16);
678 A |= (A >> 32);
679 return A + 1;
680}
681
682/// Returns the power of two which is less than or equal to the given value.
683/// Essentially, it is a floor operation across the domain of powers of two.
684inline uint64_t PowerOf2Floor(uint64_t A) {
685 if (!A) return 0;
686 return 1ull << (63 - countLeadingZeros(A, ZB_Undefined));
687}
688
689/// Returns the power of two which is greater than or equal to the given value.
690/// Essentially, it is a ceil operation across the domain of powers of two.
691inline uint64_t PowerOf2Ceil(uint64_t A) {
692 if (!A)
693 return 0;
694 return NextPowerOf2(A - 1);
695}
696
697/// Returns the next integer (mod 2**64) that is greater than or equal to
698/// \p Value and is a multiple of \p Align. \p Align must be non-zero.
699///
700/// If non-zero \p Skew is specified, the return value will be a minimal
701/// integer that is greater than or equal to \p Value and equal to
702/// \p Align * N + \p Skew for some integer N. If \p Skew is larger than
703/// \p Align, its value is adjusted to '\p Skew mod \p Align'.
704///
705/// Examples:
706/// \code
707/// alignTo(5, 8) = 8
708/// alignTo(17, 8) = 24
709/// alignTo(~0LL, 8) = 0
710/// alignTo(321, 255) = 510
711///
712/// alignTo(5, 8, 7) = 7
713/// alignTo(17, 8, 1) = 17
714/// alignTo(~0LL, 8, 3) = 3
715/// alignTo(321, 255, 42) = 552
716/// \endcode
717inline uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew = 0) {
718 assert(Align != 0u && "Align can't be 0.")((Align != 0u && "Align can't be 0.") ? static_cast<
void> (0) : __assert_fail ("Align != 0u && \"Align can't be 0.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h"
, 718, __PRETTY_FUNCTION__))
;
719 Skew %= Align;
720 return (Value + Align - 1 - Skew) / Align * Align + Skew;
721}
722
723/// Returns the next integer (mod 2**64) that is greater than or equal to
724/// \p Value and is a multiple of \c Align. \c Align must be non-zero.
725template <uint64_t Align> constexpr inline uint64_t alignTo(uint64_t Value) {
726 static_assert(Align != 0u, "Align must be non-zero");
727 return (Value + Align - 1) / Align * Align;
728}
729
730/// Returns the integer ceil(Numerator / Denominator).
731inline uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator) {
732 return alignTo(Numerator, Denominator) / Denominator;
733}
734
735/// Returns the integer nearest(Numerator / Denominator).
736inline uint64_t divideNearest(uint64_t Numerator, uint64_t Denominator) {
737 return (Numerator + (Denominator / 2)) / Denominator;
738}
739
740/// Returns the largest uint64_t less than or equal to \p Value and is
741/// \p Skew mod \p Align. \p Align must be non-zero
742inline uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew = 0) {
743 assert(Align != 0u && "Align can't be 0.")((Align != 0u && "Align can't be 0.") ? static_cast<
void> (0) : __assert_fail ("Align != 0u && \"Align can't be 0.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h"
, 743, __PRETTY_FUNCTION__))
;
744 Skew %= Align;
745 return (Value - Skew) / Align * Align + Skew;
746}
747
748/// Sign-extend the number in the bottom B bits of X to a 32-bit integer.
749/// Requires 0 < B <= 32.
750template <unsigned B> constexpr inline int32_t SignExtend32(uint32_t X) {
751 static_assert(B > 0, "Bit width can't be 0.");
752 static_assert(B <= 32, "Bit width out of range.");
753 return int32_t(X << (32 - B)) >> (32 - B);
754}
755
756/// Sign-extend the number in the bottom B bits of X to a 32-bit integer.
757/// Requires 0 < B < 32.
758inline int32_t SignExtend32(uint32_t X, unsigned B) {
759 assert(B > 0 && "Bit width can't be 0.")((B > 0 && "Bit width can't be 0.") ? static_cast<
void> (0) : __assert_fail ("B > 0 && \"Bit width can't be 0.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h"
, 759, __PRETTY_FUNCTION__))
;
760 assert(B <= 32 && "Bit width out of range.")((B <= 32 && "Bit width out of range.") ? static_cast
<void> (0) : __assert_fail ("B <= 32 && \"Bit width out of range.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h"
, 760, __PRETTY_FUNCTION__))
;
761 return int32_t(X << (32 - B)) >> (32 - B);
762}
763
764/// Sign-extend the number in the bottom B bits of X to a 64-bit integer.
765/// Requires 0 < B < 64.
766template <unsigned B> constexpr inline int64_t SignExtend64(uint64_t x) {
767 static_assert(B > 0, "Bit width can't be 0.");
768 static_assert(B <= 64, "Bit width out of range.");
769 return int64_t(x << (64 - B)) >> (64 - B);
770}
771
772/// Sign-extend the number in the bottom B bits of X to a 64-bit integer.
773/// Requires 0 < B < 64.
774inline int64_t SignExtend64(uint64_t X, unsigned B) {
775 assert(B > 0 && "Bit width can't be 0.")((B > 0 && "Bit width can't be 0.") ? static_cast<
void> (0) : __assert_fail ("B > 0 && \"Bit width can't be 0.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h"
, 775, __PRETTY_FUNCTION__))
;
776 assert(B <= 64 && "Bit width out of range.")((B <= 64 && "Bit width out of range.") ? static_cast
<void> (0) : __assert_fail ("B <= 64 && \"Bit width out of range.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/Support/MathExtras.h"
, 776, __PRETTY_FUNCTION__))
;
777 return int64_t(X << (64 - B)) >> (64 - B);
778}
779
780/// Subtract two unsigned integers, X and Y, of type T and return the absolute
781/// value of the result.
782template <typename T>
783typename std::enable_if<std::is_unsigned<T>::value, T>::type
784AbsoluteDifference(T X, T Y) {
785 return std::max(X, Y) - std::min(X, Y);
786}
787
788/// Add two unsigned integers, X and Y, of type T. Clamp the result to the
789/// maximum representable value of T on overflow. ResultOverflowed indicates if
790/// the result is larger than the maximum representable value of type T.
791template <typename T>
792typename std::enable_if<std::is_unsigned<T>::value, T>::type
793SaturatingAdd(T X, T Y, bool *ResultOverflowed = nullptr) {
794 bool Dummy;
795 bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
796 // Hacker's Delight, p. 29
797 T Z = X + Y;
798 Overflowed = (Z < X || Z < Y);
799 if (Overflowed)
800 return std::numeric_limits<T>::max();
801 else
802 return Z;
803}
804
805/// Multiply two unsigned integers, X and Y, of type T. Clamp the result to the
806/// maximum representable value of T on overflow. ResultOverflowed indicates if
807/// the result is larger than the maximum representable value of type T.
808template <typename T>
809typename std::enable_if<std::is_unsigned<T>::value, T>::type
810SaturatingMultiply(T X, T Y, bool *ResultOverflowed = nullptr) {
811 bool Dummy;
812 bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
813
814 // Hacker's Delight, p. 30 has a different algorithm, but we don't use that
815 // because it fails for uint16_t (where multiplication can have undefined
816 // behavior due to promotion to int), and requires a division in addition
817 // to the multiplication.
818
819 Overflowed = false;
820
821 // Log2(Z) would be either Log2Z or Log2Z + 1.
822 // Special case: if X or Y is 0, Log2_64 gives -1, and Log2Z
823 // will necessarily be less than Log2Max as desired.
824 int Log2Z = Log2_64(X) + Log2_64(Y);
825 const T Max = std::numeric_limits<T>::max();
826 int Log2Max = Log2_64(Max);
827 if (Log2Z < Log2Max) {
828 return X * Y;
829 }
830 if (Log2Z > Log2Max) {
831 Overflowed = true;
832 return Max;
833 }
834
835 // We're going to use the top bit, and maybe overflow one
836 // bit past it. Multiply all but the bottom bit then add
837 // that on at the end.
838 T Z = (X >> 1) * Y;
839 if (Z & ~(Max >> 1)) {
840 Overflowed = true;
841 return Max;
842 }
843 Z <<= 1;
844 if (X & 1)
845 return SaturatingAdd(Z, Y, ResultOverflowed);
846
847 return Z;
848}
849
850/// Multiply two unsigned integers, X and Y, and add the unsigned integer, A to
851/// the product. Clamp the result to the maximum representable value of T on
852/// overflow. ResultOverflowed indicates if the result is larger than the
853/// maximum representable value of type T.
854template <typename T>
855typename std::enable_if<std::is_unsigned<T>::value, T>::type
856SaturatingMultiplyAdd(T X, T Y, T A, bool *ResultOverflowed = nullptr) {
857 bool Dummy;
858 bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy;
859
860 T Product = SaturatingMultiply(X, Y, &Overflowed);
861 if (Overflowed)
862 return Product;
863
864 return SaturatingAdd(A, Product, &Overflowed);
865}
866
867/// Use this rather than HUGE_VALF; the latter causes warnings on MSVC.
868extern const float huge_valf;
869
870
871/// Add two signed integers, computing the two's complement truncated result,
872/// returning true if overflow occured.
873template <typename T>
874typename std::enable_if<std::is_signed<T>::value, T>::type
875AddOverflow(T X, T Y, T &Result) {
876#if __has_builtin(__builtin_add_overflow)1
877 return __builtin_add_overflow(X, Y, &Result);
878#else
879 // Perform the unsigned addition.
880 using U = typename std::make_unsigned<T>::type;
881 const U UX = static_cast<U>(X);
882 const U UY = static_cast<U>(Y);
883 const U UResult = UX + UY;
884
885 // Convert to signed.
886 Result = static_cast<T>(UResult);
887
888 // Adding two positive numbers should result in a positive number.
889 if (X > 0 && Y > 0)
890 return Result <= 0;
891 // Adding two negatives should result in a negative number.
892 if (X < 0 && Y < 0)
893 return Result >= 0;
894 return false;
895#endif
896}
897
898/// Subtract two signed integers, computing the two's complement truncated
899/// result, returning true if an overflow ocurred.
900template <typename T>
901typename std::enable_if<std::is_signed<T>::value, T>::type
902SubOverflow(T X, T Y, T &Result) {
903#if __has_builtin(__builtin_sub_overflow)1
904 return __builtin_sub_overflow(X, Y, &Result);
905#else
906 // Perform the unsigned addition.
907 using U = typename std::make_unsigned<T>::type;
908 const U UX = static_cast<U>(X);
909 const U UY = static_cast<U>(Y);
910 const U UResult = UX - UY;
911
912 // Convert to signed.
913 Result = static_cast<T>(UResult);
914
915 // Subtracting a positive number from a negative results in a negative number.
916 if (X <= 0 && Y > 0)
917 return Result >= 0;
918 // Subtracting a negative number from a positive results in a positive number.
919 if (X >= 0 && Y < 0)
920 return Result <= 0;
921 return false;
922#endif
923}
924
925
926/// Multiply two signed integers, computing the two's complement truncated
927/// result, returning true if an overflow ocurred.
928template <typename T>
929typename std::enable_if<std::is_signed<T>::value, T>::type
930MulOverflow(T X, T Y, T &Result) {
931 // Perform the unsigned multiplication on absolute values.
932 using U = typename std::make_unsigned<T>::type;
933 const U UX = X < 0 ? (0 - static_cast<U>(X)) : static_cast<U>(X);
934 const U UY = Y < 0 ? (0 - static_cast<U>(Y)) : static_cast<U>(Y);
935 const U UResult = UX * UY;
936
937 // Convert to signed.
938 const bool IsNegative = (X < 0) ^ (Y < 0);
939 Result = IsNegative ? (0 - UResult) : UResult;
940
941 // If any of the args was 0, result is 0 and no overflow occurs.
942 if (UX == 0 || UY == 0)
943 return false;
944
945 // UX and UY are in [1, 2^n], where n is the number of digits.
946 // Check how the max allowed absolute value (2^n for negative, 2^(n-1) for
947 // positive) divided by an argument compares to the other.
948 if (IsNegative)
949 return UX > (static_cast<U>(std::numeric_limits<T>::max()) + U(1)) / UY;
950 else
951 return UX > (static_cast<U>(std::numeric_limits<T>::max())) / UY;
952}
953
954} // End llvm namespace
955
956#endif