/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Bug Summary

File:	llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:	line 1149, column 10 Called C++ object pointer is null
Annotated Source Code

Press '?' to see keyboard shortcuts
Show analyzer invocation
clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name DAGCombiner.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-11/lib/clang/11.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/include -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-11/lib/clang/11.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-03-09-184146-41876-1 -x c++ /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

→
1//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass combines dag nodes to form fewer, simpler DAG nodes.  It can be run
10// both before and after the DAG is legalized.
11//
12// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
13// primarily intended to handle simplification opportunities that are implicit
14// in the LLVM IR and exposed by the various codegen lowering phases.
15//
16//===----------------------------------------------------------------------===//

18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/ArrayRef.h"
21#include "llvm/ADT/DenseMap.h"
22#include "llvm/ADT/IntervalMap.h"
23#include "llvm/ADT/None.h"
24#include "llvm/ADT/Optional.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SetVector.h"
27#include "llvm/ADT/SmallPtrSet.h"
28#include "llvm/ADT/SmallSet.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/Statistic.h"
31#include "llvm/Analysis/AliasAnalysis.h"
32#include "llvm/Analysis/MemoryLocation.h"
33#include "llvm/Analysis/VectorUtils.h"
34#include "llvm/CodeGen/DAGCombine.h"
35#include "llvm/CodeGen/ISDOpcodes.h"
36#include "llvm/CodeGen/MachineFrameInfo.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/RuntimeLibcalls.h"
40#include "llvm/CodeGen/SelectionDAG.h"
41#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
42#include "llvm/CodeGen/SelectionDAGNodes.h"
43#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
44#include "llvm/CodeGen/TargetLowering.h"
45#include "llvm/CodeGen/TargetRegisterInfo.h"
46#include "llvm/CodeGen/TargetSubtargetInfo.h"
47#include "llvm/CodeGen/ValueTypes.h"
48#include "llvm/IR/Attributes.h"
49#include "llvm/IR/Constant.h"
50#include "llvm/IR/DataLayout.h"
51#include "llvm/IR/DerivedTypes.h"
52#include "llvm/IR/Function.h"
53#include "llvm/IR/LLVMContext.h"
54#include "llvm/IR/Metadata.h"
55#include "llvm/Support/Casting.h"
56#include "llvm/Support/CodeGen.h"
57#include "llvm/Support/CommandLine.h"
58#include "llvm/Support/Compiler.h"
59#include "llvm/Support/Debug.h"
60#include "llvm/Support/ErrorHandling.h"
61#include "llvm/Support/KnownBits.h"
62#include "llvm/Support/MachineValueType.h"
63#include "llvm/Support/MathExtras.h"
64#include "llvm/Support/raw_ostream.h"
65#include "llvm/Target/TargetMachine.h"
66#include "llvm/Target/TargetOptions.h"
67#include <algorithm>
68#include <cassert>
69#include <cstdint>
70#include <functional>
71#include <iterator>
72#include <string>
73#include <tuple>
74#include <utility>

76using namespace llvm;

78#define DEBUG_TYPE"dagcombine" "dagcombine"

80STATISTIC(NodesCombined   , "Number of dag nodes combined")static llvm::Statistic NodesCombined = {"dagcombine", "NodesCombined"
, "Number of dag nodes combined"};
81STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created")static llvm::Statistic PreIndexedNodes = {"dagcombine", "PreIndexedNodes"
, "Number of pre-indexed nodes created"};
82STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created")static llvm::Statistic PostIndexedNodes = {"dagcombine", "PostIndexedNodes"
, "Number of post-indexed nodes created"};
83STATISTIC(OpsNarrowed     , "Number of load/op/store narrowed")static llvm::Statistic OpsNarrowed = {"dagcombine", "OpsNarrowed"
, "Number of load/op/store narrowed"};
84STATISTIC(LdStFP2Int      , "Number of fp load/store pairs transformed to int")static llvm::Statistic LdStFP2Int = {"dagcombine", "LdStFP2Int"
, "Number of fp load/store pairs transformed to int"};
85STATISTIC(SlicedLoads, "Number of load sliced")static llvm::Statistic SlicedLoads = {"dagcombine", "SlicedLoads"
, "Number of load sliced"};
86STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops")static llvm::Statistic NumFPLogicOpsConv = {"dagcombine", "NumFPLogicOpsConv"
, "Number of logic ops converted to fp ops"};

88static cl::opt<bool>
89CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
               cl::desc("Enable DAG combiner's use of IR alias analysis"));

92static cl::opt<bool>
93UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
      cl::desc("Enable DAG combiner's use of TBAA"));

96#ifndef NDEBUG
97static cl::opt<std::string>
98CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
                 cl::desc("Only use DAG-combiner alias analysis in this"
                          " function"));
101#endif

103/// Hidden option to stress test load slicing, i.e., when this option
104/// is enabled, load slicing bypasses most of its profitability guards.
105static cl::opt<bool>
106StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
                cl::desc("Bypass the profitability model of load slicing"),
                cl::init(false));

110static cl::opt<bool>
MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
                  cl::desc("DAG combiner may split indexing from loads"));

114static cl::opt<bool>
  EnableStoreMerging("combiner-store-merging", cl::Hidden, cl::init(true),
                     cl::desc("DAG combiner enable merging multiple stores "
                              "into a wider store"));

119static cl::opt<unsigned> TokenFactorInlineLimit(
  "combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048),
  cl::desc("Limit the number of operands to inline for Token Factors"));

123static cl::opt<unsigned> StoreMergeDependenceLimit(
  "combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10),
  cl::desc("Limit the number of times for the same StoreNode and RootNode "
           "to bail out in store merging dependence check"));

128namespace {

class DAGCombiner {
  SelectionDAG &DAG;
  const TargetLowering &TLI;
  CombineLevel Level;
  CodeGenOpt::Level OptLevel;
  bool LegalDAG = false;
  bool LegalOperations = false;
  bool LegalTypes = false;
  bool ForCodeSize;

  /// Worklist of all of the nodes that need to be simplified.
  ///
  /// This must behave as a stack -- new nodes to process are pushed onto the
  /// back and when processing we pop off of the back.
  ///
  /// The worklist will not contain duplicates but may contain null entries
  /// due to nodes being deleted from the underlying DAG.
  SmallVector<SDNode *, 64> Worklist;

  /// Mapping from an SDNode to its position on the worklist.
  ///
  /// This is used to find and remove nodes from the worklist (by nulling
  /// them) when they are deleted from the underlying DAG. It relies on
  /// stable indices of nodes within the worklist.
  DenseMap<SDNode *, unsigned> WorklistMap;
  /// This records all nodes attempted to add to the worklist since we
  /// considered a new worklist entry. As we keep do not add duplicate nodes
  /// in the worklist, this is different from the tail of the worklist.
  SmallSetVector<SDNode *, 32> PruningList;

  /// Set of nodes which have been combined (at least once).
  ///
  /// This is used to allow us to reliably add any operands of a DAG node
  /// which have not yet been combined to the worklist.
  SmallPtrSet<SDNode *, 32> CombinedNodes;

  /// Map from candidate StoreNode to the pair of RootNode and count.
  /// The count is used to track how many times we have seen the StoreNode
  /// with the same RootNode bail out in dependence check. If we have seen
  /// the bail out for the same pair many times over a limit, we won't
  /// consider the StoreNode with the same RootNode as store merging
  /// candidate again.
  DenseMap<SDNode *, std::pair<SDNode *, unsigned>> StoreRootCountMap;

  // AA - Used for DAG load/store alias analysis.
  AliasAnalysis *AA;

  /// When an instruction is simplified, add all users of the instruction to
  /// the work lists because they might get more simplified now.
  void AddUsersToWorklist(SDNode *N) {
    for (SDNode *Node : N->uses())
      AddToWorklist(Node);
  }

  /// Convenient shorthand to add a node and all of its user to the worklist.
  void AddToWorklistWithUsers(SDNode *N) {
    AddUsersToWorklist(N);
    AddToWorklist(N);
  }

  // Prune potentially dangling nodes. This is called after
  // any visit to a node, but should also be called during a visit after any
  // failed combine which may have created a DAG node.
  void clearAddedDanglingWorklistEntries() {
    // Check any nodes added to the worklist to see if they are prunable.
    while (!PruningList.empty()) {
      auto *N = PruningList.pop_back_val();
      if (N->use_empty())
        recursivelyDeleteUnusedNodes(N);
    }
  }

  SDNode *getNextWorklistEntry() {
    // Before we do any work, remove nodes that are not in use.
    clearAddedDanglingWorklistEntries();
    SDNode *N = nullptr;
    // The Worklist holds the SDNodes in order, but it may contain null
    // entries.
    while (!N && !Worklist.empty()) {
      N = Worklist.pop_back_val();
    }

    if (N) {
      bool GoodWorklistEntry = WorklistMap.erase(N);
      (void)GoodWorklistEntry;
      assert(GoodWorklistEntry &&((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 216, __PRETTY_FUNCTION__))
             "Found a worklist entry without a corresponding map entry!")((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 216, __PRETTY_FUNCTION__));
    }
    return N;
  }

  /// Call the node-specific routine that folds each particular type of node.
  SDValue visit(SDNode *N);

public:
  DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
      : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
        OptLevel(OL), AA(AA) {
    ForCodeSize = DAG.shouldOptForSize();

    MaximumLegalStoreInBits = 0;
    // We use the minimum store size here, since that's all we can guarantee
    // for the scalable vector types.
    for (MVT VT : MVT::all_valuetypes())
      if (EVT(VT).isSimple() && VT != MVT::Other &&
          TLI.isTypeLegal(EVT(VT)) &&
          VT.getSizeInBits().getKnownMinSize() >= MaximumLegalStoreInBits)
        MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinSize();
  }

  void ConsiderForPruning(SDNode *N) {
    // Mark this for potential pruning.
    PruningList.insert(N);
  }

  /// Add to the worklist making sure its instance is at the back (next to be
  /// processed.)
  void AddToWorklist(SDNode *N) {
    assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 249, __PRETTY_FUNCTION__))
           "Deleted Node added to Worklist")((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 249, __PRETTY_FUNCTION__));

    // Skip handle nodes as they can't usefully be combined and confuse the
    // zero-use deletion strategy.
    if (N->getOpcode() == ISD::HANDLENODE)
      return;

    ConsiderForPruning(N);

    if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
      Worklist.push_back(N);
  }

  /// Remove all instances of N from the worklist.
  void removeFromWorklist(SDNode *N) {
    CombinedNodes.erase(N);
    PruningList.remove(N);
    StoreRootCountMap.erase(N);

    auto It = WorklistMap.find(N);
    if (It == WorklistMap.end())
      return; // Not in the worklist.

    // Null out the entry rather than erasing it to avoid a linear operation.
    Worklist[It->second] = nullptr;
    WorklistMap.erase(It);
  }

  void deleteAndRecombine(SDNode *N);
  bool recursivelyDeleteUnusedNodes(SDNode *N);

  /// Replaces all uses of the results of one DAG node with new values.
  SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
                    bool AddTo = true);

  /// Replaces all uses of the results of one DAG node with new values.
  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
    return CombineTo(N, &Res, 1, AddTo);
  }

  /// Replaces all uses of the results of one DAG node with new values.
  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
                    bool AddTo = true) {
    SDValue To[] = { Res0, Res1 };
    return CombineTo(N, To, 2, AddTo);
  }

  void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);

private:
  unsigned MaximumLegalStoreInBits;

  /// Check the specified integer node value to see if it can be simplified or
  /// if things it uses can be simplified by bit propagation.
  /// If so, return true.
  bool SimplifyDemandedBits(SDValue Op) {
    unsigned BitWidth = Op.getScalarValueSizeInBits();
    APInt DemandedBits = APInt::getAllOnesValue(BitWidth);
    return SimplifyDemandedBits(Op, DemandedBits);
  }

  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) {
    EVT VT = Op.getValueType();
    unsigned NumElts = VT.isVector() ? VT.getVectorNumElements() : 1;
    APInt DemandedElts = APInt::getAllOnesValue(NumElts);
    return SimplifyDemandedBits(Op, DemandedBits, DemandedElts);
  }

  /// Check the specified vector node value to see if it can be simplified or
  /// if things it uses can be simplified as it only uses some of the
  /// elements. If so, return true.
  bool SimplifyDemandedVectorElts(SDValue Op) {
    unsigned NumElts = Op.getValueType().getVectorNumElements();
    APInt DemandedElts = APInt::getAllOnesValue(NumElts);
    return SimplifyDemandedVectorElts(Op, DemandedElts);
  }

  bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
                            const APInt &DemandedElts,
                            bool AssumeSingleUse = false);
  bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
                                  bool AssumeSingleUse = false);

  bool CombineToPreIndexedLoadStore(SDNode *N);
  bool CombineToPostIndexedLoadStore(SDNode *N);
  SDValue SplitIndexingFromLoad(LoadSDNode *LD);
  bool SliceUpLoad(SDNode *N);

  // Scalars have size 0 to distinguish from singleton vectors.
  SDValue ForwardStoreValueToDirectLoad(LoadSDNode *LD);
  bool getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val);
  bool extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val);

  /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
  ///   load.
  ///
  /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
  /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
  /// \param EltNo index of the vector element to load.
  /// \param OriginalLoad load that EVE came from to be replaced.
  /// \returns EVE on success SDValue() on failure.
  SDValue scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT,
                                       SDValue EltNo,
                                       LoadSDNode *OriginalLoad);
  void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
  SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
  SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
  SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
  SDValue PromoteIntBinOp(SDValue Op);
  SDValue PromoteIntShiftOp(SDValue Op);
  SDValue PromoteExtend(SDValue Op);
  bool PromoteLoad(SDValue Op);

  /// Call the node-specific routine that knows how to fold each
  /// particular type of node. If that doesn't do anything, try the
  /// target-specific DAG combines.
  SDValue combine(SDNode *N);

  // Visitation implementation - Implement dag node combining for different
  // node types.  The semantics are as follows:
  // Return Value:
  //   SDValue.getNode() == 0 - No change was made
  //   SDValue.getNode() == N - N was replaced, is dead and has been handled.
  //   otherwise              - N should be replaced by the returned Operand.
  //
  SDValue visitTokenFactor(SDNode *N);
  SDValue visitMERGE_VALUES(SDNode *N);
  SDValue visitADD(SDNode *N);
  SDValue visitADDLike(SDNode *N);
  SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
  SDValue visitSUB(SDNode *N);
  SDValue visitADDSAT(SDNode *N);
  SDValue visitSUBSAT(SDNode *N);
  SDValue visitADDC(SDNode *N);
  SDValue visitADDO(SDNode *N);
  SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
  SDValue visitSUBC(SDNode *N);
  SDValue visitSUBO(SDNode *N);
  SDValue visitADDE(SDNode *N);
  SDValue visitADDCARRY(SDNode *N);
  SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
  SDValue visitSUBE(SDNode *N);
  SDValue visitSUBCARRY(SDNode *N);
  SDValue visitMUL(SDNode *N);
  SDValue visitMULFIX(SDNode *N);
  SDValue useDivRem(SDNode *N);
  SDValue visitSDIV(SDNode *N);
  SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
  SDValue visitUDIV(SDNode *N);
  SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
  SDValue visitREM(SDNode *N);
  SDValue visitMULHU(SDNode *N);
  SDValue visitMULHS(SDNode *N);
  SDValue visitSMUL_LOHI(SDNode *N);
  SDValue visitUMUL_LOHI(SDNode *N);
  SDValue visitMULO(SDNode *N);
  SDValue visitIMINMAX(SDNode *N);
  SDValue visitAND(SDNode *N);
  SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
  SDValue visitOR(SDNode *N);
  SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
  SDValue visitXOR(SDNode *N);
  SDValue SimplifyVBinOp(SDNode *N);
  SDValue visitSHL(SDNode *N);
  SDValue visitSRA(SDNode *N);
  SDValue visitSRL(SDNode *N);
  SDValue visitFunnelShift(SDNode *N);
  SDValue visitRotate(SDNode *N);
  SDValue visitABS(SDNode *N);
  SDValue visitBSWAP(SDNode *N);
  SDValue visitBITREVERSE(SDNode *N);
  SDValue visitCTLZ(SDNode *N);
  SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
  SDValue visitCTTZ(SDNode *N);
  SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
  SDValue visitCTPOP(SDNode *N);
  SDValue visitSELECT(SDNode *N);
  SDValue visitVSELECT(SDNode *N);
  SDValue visitSELECT_CC(SDNode *N);
  SDValue visitSETCC(SDNode *N);
  SDValue visitSETCCCARRY(SDNode *N);
  SDValue visitSIGN_EXTEND(SDNode *N);
  SDValue visitZERO_EXTEND(SDNode *N);
  SDValue visitANY_EXTEND(SDNode *N);
  SDValue visitAssertExt(SDNode *N);
  SDValue visitSIGN_EXTEND_INREG(SDNode *N);
  SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
  SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
  SDValue visitTRUNCATE(SDNode *N);
  SDValue visitBITCAST(SDNode *N);
  SDValue visitBUILD_PAIR(SDNode *N);
  SDValue visitFADD(SDNode *N);
  SDValue visitFSUB(SDNode *N);
  SDValue visitFMUL(SDNode *N);
  SDValue visitFMA(SDNode *N);
  SDValue visitFDIV(SDNode *N);
  SDValue visitFREM(SDNode *N);
  SDValue visitFSQRT(SDNode *N);
  SDValue visitFCOPYSIGN(SDNode *N);
  SDValue visitFPOW(SDNode *N);
  SDValue visitSINT_TO_FP(SDNode *N);
  SDValue visitUINT_TO_FP(SDNode *N);
  SDValue visitFP_TO_SINT(SDNode *N);
  SDValue visitFP_TO_UINT(SDNode *N);
  SDValue visitFP_ROUND(SDNode *N);
  SDValue visitFP_EXTEND(SDNode *N);
  SDValue visitFNEG(SDNode *N);
  SDValue visitFABS(SDNode *N);
  SDValue visitFCEIL(SDNode *N);
  SDValue visitFTRUNC(SDNode *N);
  SDValue visitFFLOOR(SDNode *N);
  SDValue visitFMINNUM(SDNode *N);
  SDValue visitFMAXNUM(SDNode *N);
  SDValue visitFMINIMUM(SDNode *N);
  SDValue visitFMAXIMUM(SDNode *N);
  SDValue visitBRCOND(SDNode *N);
  SDValue visitBR_CC(SDNode *N);
  SDValue visitLOAD(SDNode *N);

  SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
  SDValue replaceStoreOfFPConstant(StoreSDNode *ST);

  SDValue visitSTORE(SDNode *N);
  SDValue visitLIFETIME_END(SDNode *N);
  SDValue visitINSERT_VECTOR_ELT(SDNode *N);
  SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
  SDValue visitBUILD_VECTOR(SDNode *N);
  SDValue visitCONCAT_VECTORS(SDNode *N);
  SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
  SDValue visitVECTOR_SHUFFLE(SDNode *N);
  SDValue visitSCALAR_TO_VECTOR(SDNode *N);
  SDValue visitINSERT_SUBVECTOR(SDNode *N);
  SDValue visitMLOAD(SDNode *N);
  SDValue visitMSTORE(SDNode *N);
  SDValue visitMGATHER(SDNode *N);
  SDValue visitMSCATTER(SDNode *N);
  SDValue visitFP_TO_FP16(SDNode *N);
  SDValue visitFP16_TO_FP(SDNode *N);
  SDValue visitVECREDUCE(SDNode *N);

  SDValue visitFADDForFMACombine(SDNode *N);
  SDValue visitFSUBForFMACombine(SDNode *N);
  SDValue visitFMULForFMADistributiveCombine(SDNode *N);

  SDValue XformToShuffleWithZero(SDNode *N);
  bool reassociationCanBreakAddressingModePattern(unsigned Opc,
                                                  const SDLoc &DL, SDValue N0,
                                                  SDValue N1);
  SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
                                    SDValue N1);
  SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
                         SDValue N1, SDNodeFlags Flags);

  SDValue visitShiftByConstant(SDNode *N);

  SDValue foldSelectOfConstants(SDNode *N);
  SDValue foldVSelectOfConstants(SDNode *N);
  SDValue foldBinOpIntoSelect(SDNode *BO);
  bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
  SDValue hoistLogicOpWithSameOpcodeHands(SDNode *N);
  SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
  SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
                           SDValue N2, SDValue N3, ISD::CondCode CC,
                           bool NotExtCompare = false);
  SDValue convertSelectOfFPConstantsToLoadOffset(
      const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
      ISD::CondCode CC);
  SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
                                 SDValue N2, SDValue N3, ISD::CondCode CC);
  SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
                            const SDLoc &DL);
  SDValue unfoldMaskedMerge(SDNode *N);
  SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
  SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
                        const SDLoc &DL, bool foldBooleans);
  SDValue rebuildSetCC(SDValue N);

  bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
                         SDValue &CC, bool MatchStrict = false) const;
  bool isOneUseSetCC(SDValue N) const;
  bool isCheaperToUseNegatedFPOps(SDValue X, SDValue Y);

  SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
                                       unsigned HiOp);
  SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
  SDValue CombineExtLoad(SDNode *N);
  SDValue CombineZExtLogicopShiftLoad(SDNode *N);
  SDValue combineRepeatedFPDivisors(SDNode *N);
  SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex);
  SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
  SDValue BuildSDIV(SDNode *N);
  SDValue BuildSDIVPow2(SDNode *N);
  SDValue BuildUDIV(SDNode *N);
  SDValue BuildLogBase2(SDValue V, const SDLoc &DL);
  SDValue BuildDivEstimate(SDValue N, SDValue Op, SDNodeFlags Flags);
  SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
  SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
  SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
  SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations,
                              SDNodeFlags Flags, bool Reciprocal);
  SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations,
                              SDNodeFlags Flags, bool Reciprocal);
  SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
                             bool DemandHighBits = true);
  SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
  SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
                            SDValue InnerPos, SDValue InnerNeg,
                            unsigned PosOpcode, unsigned NegOpcode,
                            const SDLoc &DL);
  SDValue MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
  SDValue MatchLoadCombine(SDNode *N);
  SDValue MatchStoreCombine(StoreSDNode *N);
  SDValue ReduceLoadWidth(SDNode *N);
  SDValue ReduceLoadOpStoreWidth(SDNode *N);
  SDValue splitMergedValStore(StoreSDNode *ST);
  SDValue TransformFPLoadStorePair(SDNode *N);
  SDValue convertBuildVecZextToZext(SDNode *N);
  SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
  SDValue reduceBuildVecTruncToBitCast(SDNode *N);
  SDValue reduceBuildVecToShuffle(SDNode *N);
  SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
                                ArrayRef<int> VectorMask, SDValue VecIn1,
                                SDValue VecIn2, unsigned LeftIdx,
                                bool DidSplitVec);
  SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast);

  /// Walk up chain skipping non-aliasing memory nodes,
  /// looking for aliasing nodes and adding them to the Aliases vector.
  void GatherAllAliases(SDNode *N, SDValue OriginalChain,
                        SmallVectorImpl<SDValue> &Aliases);

  /// Return true if there is any possibility that the two addresses overlap.
  bool isAlias(SDNode *Op0, SDNode *Op1) const;

  /// Walk up chain skipping non-aliasing memory nodes, looking for a better
  /// chain (aliasing node.)
  SDValue FindBetterChain(SDNode *N, SDValue Chain);

  /// Try to replace a store and any possibly adjacent stores on
  /// consecutive chains with better chains. Return true only if St is
  /// replaced.
  ///
  /// Notice that other chains may still be replaced even if the function
  /// returns false.
  bool findBetterNeighborChains(StoreSDNode *St);

  // Helper for findBetterNeighborChains. Walk up store chain add additional
  // chained stores that do not overlap and can be parallelized.
  bool parallelizeChainedStores(StoreSDNode *St);

  /// Holds a pointer to an LSBaseSDNode as well as information on where it
  /// is located in a sequence of memory operations connected by a chain.
  struct MemOpLink {
    // Ptr to the mem node.
    LSBaseSDNode *MemNode;

    // Offset from the base ptr.
    int64_t OffsetFromBase;

    MemOpLink(LSBaseSDNode *N, int64_t Offset)
        : MemNode(N), OffsetFromBase(Offset) {}
  };

  /// This is a helper function for visitMUL to check the profitability
  /// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
  /// MulNode is the original multiply, AddNode is (add x, c1),
  /// and ConstNode is c2.
  bool isMulAddWithConstProfitable(SDNode *MulNode,
                                   SDValue &AddNode,
                                   SDValue &ConstNode);

  /// This is a helper function for visitAND and visitZERO_EXTEND.  Returns
  /// true if the (and (load x) c) pattern matches an extload.  ExtVT returns
  /// the type of the loaded value to be extended.
  bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
                        EVT LoadResultTy, EVT &ExtVT);

  /// Helper function to calculate whether the given Load/Store can have its
  /// width reduced to ExtVT.
  bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType,
                         EVT &MemVT, unsigned ShAmt = 0);

  /// Used by BackwardsPropagateMask to find suitable loads.
  bool SearchForAndLoads(SDNode *N, SmallVectorImpl<LoadSDNode*> &Loads,
                         SmallPtrSetImpl<SDNode*> &NodesWithConsts,
                         ConstantSDNode *Mask, SDNode *&NodeToMask);
  /// Attempt to propagate a given AND node back to load leaves so that they
  /// can be combined into narrow loads.
  bool BackwardsPropagateMask(SDNode *N);

  /// Helper function for MergeConsecutiveStores which merges the
  /// component store chains.
  SDValue getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
                              unsigned NumStores);

  /// This is a helper function for MergeConsecutiveStores. When the
  /// source elements of the consecutive stores are all constants or
  /// all extracted vector elements, try to merge them into one
  /// larger store introducing bitcasts if necessary.  \return True
  /// if a merged store was created.
  bool MergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
                                       EVT MemVT, unsigned NumStores,
                                       bool IsConstantSrc, bool UseVector,
                                       bool UseTrunc);

  /// This is a helper function for MergeConsecutiveStores. Stores
  /// that potentially may be merged with St are placed in
  /// StoreNodes. RootNode is a chain predecessor to all store
  /// candidates.
  void getStoreMergeCandidates(StoreSDNode *St,
                               SmallVectorImpl<MemOpLink> &StoreNodes,
                               SDNode *&Root);

  /// Helper function for MergeConsecutiveStores. Checks if
  /// candidate stores have indirect dependency through their
  /// operands. RootNode is the predecessor to all stores calculated
  /// by getStoreMergeCandidates and is used to prune the dependency check.
  /// \return True if safe to merge.
  bool checkMergeStoreCandidatesForDependencies(
      SmallVectorImpl<MemOpLink> &StoreNodes, unsigned NumStores,
      SDNode *RootNode);

  /// Merge consecutive store operations into a wide store.
  /// This optimization uses wide integers or vectors when possible.
  /// \return number of stores that were merged into a merged store (the
  /// affected nodes are stored as a prefix in \p StoreNodes).
  bool MergeConsecutiveStores(StoreSDNode *St);

  /// Try to transform a truncation where C is a constant:
  ///     (trunc (and X, C)) -> (and (trunc X), (trunc C))
  ///
  /// \p N needs to be a truncation and its first operand an AND. Other
  /// requirements are checked by the function (e.g. that trunc is
  /// single-use) and if missed an empty SDValue is returned.
  SDValue distributeTruncateThroughAnd(SDNode *N);

  /// Helper function to determine whether the target supports operation
  /// given by \p Opcode for type \p VT, that is, whether the operation
  /// is legal or custom before legalizing operations, and whether is
  /// legal (but not custom) after legalization.
  bool hasOperation(unsigned Opcode, EVT VT) {
    if (LegalOperations)
      return TLI.isOperationLegal(Opcode, VT);
    return TLI.isOperationLegalOrCustom(Opcode, VT);
  }

public:
  /// Runs the dag combiner on all nodes in the work list
  void Run(CombineLevel AtLevel);

  SelectionDAG &getDAG() const { return DAG; }

  /// Returns a type large enough to hold any valid shift amount - before type
  /// legalization these can be huge.
  EVT getShiftAmountTy(EVT LHSTy) {
    assert(LHSTy.isInteger() && "Shift amount is not an integer type!")((LHSTy.isInteger() && "Shift amount is not an integer type!"
) ? static_cast<void> (0) : __assert_fail ("LHSTy.isInteger() && \"Shift amount is not an integer type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 704, __PRETTY_FUNCTION__));
    return TLI.getShiftAmountTy(LHSTy, DAG.getDataLayout(), LegalTypes);
  }

  /// This method returns true if we are running before type legalization or
  /// if the specified VT is legal.
  bool isTypeLegal(const EVT &VT) {
    if (!LegalTypes) return true;
    return TLI.isTypeLegal(VT);
  }

  /// Convenience wrapper around TargetLowering::getSetCCResultType
  EVT getSetCCResultType(EVT VT) const {
    return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
  }

  void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
                       SDValue OrigLoad, SDValue ExtLoad,
                       ISD::NodeType ExtType);
};

725/// This class is a DAGUpdateListener that removes any deleted
726/// nodes from the worklist.
727class WorklistRemover : public SelectionDAG::DAGUpdateListener {
DAGCombiner &DC;

730public:
explicit WorklistRemover(DAGCombiner &dc)
  : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}

void NodeDeleted(SDNode *N, SDNode *E) override {
  DC.removeFromWorklist(N);
}
737};

739class WorklistInserter : public SelectionDAG::DAGUpdateListener {
DAGCombiner &DC;

742public:
explicit WorklistInserter(DAGCombiner &dc)
    : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}

// FIXME: Ideally we could add N to the worklist, but this causes exponential
//        compile time costs in large DAGs, e.g. Halide.
void NodeInserted(SDNode *N) override { DC.ConsiderForPruning(N); }
749};

751} // end anonymous namespace

753//===----------------------------------------------------------------------===//
754//  TargetLowering::DAGCombinerInfo implementation
755//===----------------------------------------------------------------------===//

757void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
((DAGCombiner*)DC)->AddToWorklist(N);
759}

761SDValue TargetLowering::DAGCombinerInfo::
762CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
764}

766SDValue TargetLowering::DAGCombinerInfo::
767CombineTo(SDNode *N, SDValue Res, bool AddTo) {
return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
769}

771SDValue TargetLowering::DAGCombinerInfo::
772CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
774}

776bool TargetLowering::DAGCombinerInfo::
777recursivelyDeleteUnusedNodes(SDNode *N) {
return ((DAGCombiner*)DC)->recursivelyDeleteUnusedNodes(N);
779}

781void TargetLowering::DAGCombinerInfo::
782CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
784}

786//===----------------------------------------------------------------------===//
787// Helper Functions
788//===----------------------------------------------------------------------===//

790void DAGCombiner::deleteAndRecombine(SDNode *N) {
removeFromWorklist(N);

// If the operands of this node are only used by the node, they will now be
// dead. Make sure to re-visit them and recursively delete dead nodes.
for (const SDValue &Op : N->ops())
  // For an operand generating multiple values, one of the values may
  // become dead allowing further simplification (e.g. split index
  // arithmetic from an indexed load).
  if (Op->hasOneUse() || Op->getNumValues() > 1)
    AddToWorklist(Op.getNode());

DAG.DeleteNode(N);
803}

805// APInts must be the same size for most operations, this helper
806// function zero extends the shorter of the pair so that they match.
807// We provide an Offset so that we can create bitwidths that won't overflow.
808static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) {
unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth());
LHS = LHS.zextOrSelf(Bits);
RHS = RHS.zextOrSelf(Bits);
812}

814// Return true if this node is a setcc, or is a select_cc
815// that selects between the target values used for true and false, making it
816// equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
817// the appropriate nodes based on the type of node we are checking. This
818// simplifies life a bit for the callers.
819bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
                                  SDValue &CC, bool MatchStrict) const {
if (N.getOpcode() == ISD::SETCC) {
  LHS = N.getOperand(0);
  RHS = N.getOperand(1);
  CC  = N.getOperand(2);
  return true;
}

if (MatchStrict &&
    (N.getOpcode() == ISD::STRICT_FSETCC ||
     N.getOpcode() == ISD::STRICT_FSETCCS)) {
  LHS = N.getOperand(1);
  RHS = N.getOperand(2);
  CC  = N.getOperand(3);
  return true;
}

if (N.getOpcode() != ISD::SELECT_CC ||
    !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
    !TLI.isConstFalseVal(N.getOperand(3).getNode()))
  return false;

if (TLI.getBooleanContents(N.getValueType()) ==
    TargetLowering::UndefinedBooleanContent)
  return false;

LHS = N.getOperand(0);
RHS = N.getOperand(1);
CC  = N.getOperand(4);
return true;
850}

852/// Return true if this is a SetCC-equivalent operation with only one use.
853/// If this is true, it allows the users to invert the operation for free when
854/// it is profitable to do so.
855bool DAGCombiner::isOneUseSetCC(SDValue N) const {
SDValue N0, N1, N2;
if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
  return true;
return false;
860}

862// Returns the SDNode if it is a constant float BuildVector
863// or constant float.
864static SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) {
if (isa<ConstantFPSDNode>(N))
  return N.getNode();
if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
  return N.getNode();
return nullptr;
870}

872// Determines if it is a constant integer or a build vector of constant
873// integers (and undefs).
874// Do not permit build vector implicit truncation.
875static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) {
if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N))
  return !(Const->isOpaque() && NoOpaques);
if (N.getOpcode() != ISD::BUILD_VECTOR)
  return false;
unsigned BitWidth = N.getScalarValueSizeInBits();
for (const SDValue &Op : N->op_values()) {
  if (Op.isUndef())
    continue;
  ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op);
  if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth ||
      (Const->isOpaque() && NoOpaques))
    return false;
}
return true;
890}

892// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with
893// undef's.
894static bool isAnyConstantBuildVector(SDValue V, bool NoOpaques = false) {
if (V.getOpcode() != ISD::BUILD_VECTOR)
  return false;
return isConstantOrConstantVector(V, NoOpaques) ||
       ISD::isBuildVectorOfConstantFPSDNodes(V.getNode());
899}

901bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc,
                                                           const SDLoc &DL,
                                                           SDValue N0,
                                                           SDValue N1) {
// Currently this only tries to ensure we don't undo the GEP splits done by
// CodeGenPrepare when shouldConsiderGEPOffsetSplit is true. To ensure this,
// we check if the following transformation would be problematic:
// (load/store (add, (add, x, offset1), offset2)) ->
// (load/store (add, x, offset1+offset2)).

if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD)
  return false;

if (N0.hasOneUse())
  return false;

auto *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
auto *C2 = dyn_cast<ConstantSDNode>(N1);
if (!C1 || !C2)
  return false;

const APInt &C1APIntVal = C1->getAPIntValue();
const APInt &C2APIntVal = C2->getAPIntValue();
if (C1APIntVal.getBitWidth() > 64 || C2APIntVal.getBitWidth() > 64)
  return false;

const APInt CombinedValueIntVal = C1APIntVal + C2APIntVal;
if (CombinedValueIntVal.getBitWidth() > 64)
  return false;
const int64_t CombinedValue = CombinedValueIntVal.getSExtValue();

for (SDNode *Node : N0->uses()) {
  auto LoadStore = dyn_cast<MemSDNode>(Node);
  if (LoadStore) {
    // Is x[offset2] already not a legal addressing mode? If so then
    // reassociating the constants breaks nothing (we test offset2 because
    // that's the one we hope to fold into the load or store).
    TargetLoweringBase::AddrMode AM;
    AM.HasBaseReg = true;
    AM.BaseOffs = C2APIntVal.getSExtValue();
    EVT VT = LoadStore->getMemoryVT();
    unsigned AS = LoadStore->getAddressSpace();
    Type *AccessTy = VT.getTypeForEVT(*DAG.getContext());
    if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
      continue;

    // Would x[offset1+offset2] still be a legal addressing mode?
    AM.BaseOffs = CombinedValue;
    if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
      return true;
  }
}

return false;
955}

957// Helper for DAGCombiner::reassociateOps. Try to reassociate an expression
958// such as (Opc N0, N1), if \p N0 is the same kind of operation as \p Opc.
959SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
                                             SDValue N0, SDValue N1) {
EVT VT = N0.getValueType();

if (N0.getOpcode() != Opc)
  return SDValue();

// Don't reassociate reductions.
if (N0->getFlags().hasVectorReduction())
  return SDValue();

if (DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
  if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
    // Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
    if (SDValue OpNode =
            DAG.FoldConstantArithmetic(Opc, DL, VT, {N0.getOperand(1), N1}))
      return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
    return SDValue();
  }
  if (N0.hasOneUse()) {
    // Reassociate: (op (op x, c1), y) -> (op (op x, y), c1)
    //              iff (op x, c1) has one use
    SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
    if (!OpNode.getNode())
      return SDValue();
    return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
  }
}
return SDValue();
988}

990// Try to reassociate commutative binops.
991SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
                                  SDValue N1, SDNodeFlags Flags) {
assert(TLI.isCommutativeBinOp(Opc) && "Operation not commutative.")((TLI.isCommutativeBinOp(Opc) && "Operation not commutative."
) ? static_cast<void> (0) : __assert_fail ("TLI.isCommutativeBinOp(Opc) && \"Operation not commutative.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 993, __PRETTY_FUNCTION__));
// Don't reassociate reductions.
if (Flags.hasVectorReduction())
  return SDValue();

// Floating-point reassociation is not allowed without loose FP math.
if (N0.getValueType().isFloatingPoint() ||
    N1.getValueType().isFloatingPoint())
  if (!Flags.hasAllowReassociation() || !Flags.hasNoSignedZeros())
    return SDValue();

if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1))
  return Combined;
if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0))
  return Combined;
return SDValue();
1009}

1011SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
                             bool AddTo) {
assert(N->getNumValues() == NumTo && "Broken CombineTo call!")((N->getNumValues() == NumTo && "Broken CombineTo call!"
) ? static_cast<void> (0) : __assert_fail ("N->getNumValues() == NumTo && \"Broken CombineTo call!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1013, __PRETTY_FUNCTION__));
++NodesCombined;
LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
 " other values\n"; } } while (false)
           To[0].getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
 " other values\n"; } } while (false)
           dbgs() << " and " << NumTo - 1 << " other values\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
 " other values\n"; } } while (false);
for (unsigned i = 0, e = NumTo; i != e; ++i)
  assert((!To[i].getNode() ||(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1021, __PRETTY_FUNCTION__))
          N->getValueType(i) == To[i].getValueType()) &&(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1021, __PRETTY_FUNCTION__))
         "Cannot combine value to value of different type!")(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1021, __PRETTY_FUNCTION__));

WorklistRemover DeadNodes(*this);
DAG.ReplaceAllUsesWith(N, To);
if (AddTo) {
  // Push the new nodes and any users onto the worklist
  for (unsigned i = 0, e = NumTo; i != e; ++i) {
    if (To[i].getNode()) {
      AddToWorklist(To[i].getNode());
      AddUsersToWorklist(To[i].getNode());
    }
  }
}

// Finally, if the node is now dead, remove it from the graph.  The node
// may not be dead if the replacement process recursively simplified to
// something else needing this node.
if (N->use_empty())
  deleteAndRecombine(N);
return SDValue(N, 0);
1041}

1043void DAGCombiner::
1044CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
// Replace all uses.  If any nodes become isomorphic to other nodes and
// are deleted, make sure to remove them from our worklist.
WorklistRemover DeadNodes(*this);
DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);

// Push the new node and any (possibly new) users onto the worklist.
AddToWorklistWithUsers(TLO.New.getNode());

// Finally, if the node is now dead, remove it from the graph.  The node
// may not be dead if the replacement process recursively simplified to
// something else needing this node.
if (TLO.Old.getNode()->use_empty())
  deleteAndRecombine(TLO.Old.getNode());
1058}

1060/// Check the specified integer node value to see if it can be simplified or if
1061/// things it uses can be simplified by bit propagation. If so, return true.
1062bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
                                     const APInt &DemandedElts,
                                     bool AssumeSingleUse) {
TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
KnownBits Known;
if (!TLI.SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, 0,
                              AssumeSingleUse))
  return false;

// Revisit the node.
AddToWorklist(Op.getNode());

// Replace the old value with the new one.
++NodesCombined;
LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
           dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
           dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
);

CommitTargetLoweringOpt(TLO);
return true;
1082}

1084/// Check the specified vector node value to see if it can be simplified or
1085/// if things it uses can be simplified as it only uses some of the elements.
1086/// If so, return true.
1087bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op,
                                           const APInt &DemandedElts,
                                           bool AssumeSingleUse) {
TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
APInt KnownUndef, KnownZero;
if (!TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero,
                                    TLO, 0, AssumeSingleUse))
  return false;

// Revisit the node.
AddToWorklist(Op.getNode());

// Replace the old value with the new one.
++NodesCombined;
LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
           dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
           dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
);

CommitTargetLoweringOpt(TLO);
return true;
1107}

1109void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
SDLoc DL(Load);
EVT VT = Load->getValueType(0);
SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0));

LLVM_DEBUG(dbgs() << "\nReplacing.9 "; Load->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
           Trunc.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false);
WorklistRemover DeadNodes(*this);
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
deleteAndRecombine(Load);
AddToWorklist(Trunc.getNode());
1121}

1123SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
Replace = false;
SDLoc DL(Op);
if (ISD::isUNINDEXEDLoad(Op.getNode())) {
  LoadSDNode *LD = cast<LoadSDNode>(Op);
  EVT MemVT = LD->getMemoryVT();
  ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
                                                    : LD->getExtensionType();
  Replace = true;
  return DAG.getExtLoad(ExtType, DL, PVT,
                        LD->getChain(), LD->getBasePtr(),
                        MemVT, LD->getMemOperand());
}

unsigned Opc = Op.getOpcode();
switch (Opc) {
default: break;
case ISD::AssertSext:
  if (SDValue Op0 = SExtPromoteOperand(Op.getOperand(0), PVT))
    return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1));
  break;
case ISD::AssertZext:
  if (SDValue Op0 = ZExtPromoteOperand(Op.getOperand(0), PVT))
    return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1));
  break;
case ISD::Constant: {
  unsigned ExtOpc =
    Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
  return DAG.getNode(ExtOpc, DL, PVT, Op);
}
}

if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
  return SDValue();
return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op);
1158}

1160SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
  return SDValue();
EVT OldVT = Op.getValueType();
SDLoc DL(Op);
bool Replace = false;
SDValue NewOp = PromoteOperand(Op, PVT, Replace);
if (!NewOp.getNode())
  return SDValue();
AddToWorklist(NewOp.getNode());

if (Replace)
  ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp,
                   DAG.getValueType(OldVT));
1175}

1177SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
EVT OldVT = Op.getValueType();
SDLoc DL(Op);
bool Replace = false;
SDValue NewOp = PromoteOperand(Op, PVT, Replace);
if (!NewOp.getNode())
  return SDValue();
AddToWorklist(NewOp.getNode());

if (Replace)
  ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
return DAG.getZeroExtendInReg(NewOp, DL, OldVT);
1189}

1191/// Promote the specified integer binary operation if the target indicates it is
1192/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1193/// i32 since i16 instructions are longer.
1194SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
if (!LegalOperations)
  return SDValue();

EVT VT = Op.getValueType();
if (VT.isVector() || !VT.isInteger())
  return SDValue();

// If operation type is 'undesirable', e.g. i16 on x86, consider
// promoting it.
unsigned Opc = Op.getOpcode();
if (TLI.isTypeDesirableForOp(Opc, VT))
  return SDValue();

EVT PVT = VT;
// Consult target whether it is a good idea to promote this operation and
// what's the right type to promote it to.
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
  assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
 ? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1212, __PRETTY_FUNCTION__));

  LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false);

  bool Replace0 = false;
  SDValue N0 = Op.getOperand(0);
  SDValue NN0 = PromoteOperand(N0, PVT, Replace0);

  bool Replace1 = false;
  SDValue N1 = Op.getOperand(1);
  SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
  SDLoc DL(Op);

  SDValue RV =
      DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1));

  // We are always replacing N0/N1's use in N and only need
  // additional replacements if there are additional uses.
  Replace0 &= !N0->hasOneUse();
  Replace1 &= (N0 != N1) && !N1->hasOneUse();

  // Combine Op here so it is preserved past replacements.
  CombineTo(Op.getNode(), RV);

  // If operands have a use ordering, make sure we deal with
  // predecessor first.
  if (Replace0 && Replace1 && N0.getNode()->isPredecessorOf(N1.getNode())) {
    std::swap(N0, N1);
    std::swap(NN0, NN1);
  }

  if (Replace0) {
    AddToWorklist(NN0.getNode());
    ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
  }
  if (Replace1) {
    AddToWorklist(NN1.getNode());
    ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
  }
  return Op;
}
return SDValue();
1254}

1256/// Promote the specified integer shift operation if the target indicates it is
1257/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1258/// i32 since i16 instructions are longer.
1259SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
if (!LegalOperations)
  return SDValue();

EVT VT = Op.getValueType();
if (VT.isVector() || !VT.isInteger())
  return SDValue();

// If operation type is 'undesirable', e.g. i16 on x86, consider
// promoting it.
unsigned Opc = Op.getOpcode();
if (TLI.isTypeDesirableForOp(Opc, VT))
  return SDValue();

EVT PVT = VT;
// Consult target whether it is a good idea to promote this operation and
// what's the right type to promote it to.
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
  assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
 ? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1277, __PRETTY_FUNCTION__));

  LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false);

  bool Replace = false;
  SDValue N0 = Op.getOperand(0);
  SDValue N1 = Op.getOperand(1);
  if (Opc == ISD::SRA)
    N0 = SExtPromoteOperand(N0, PVT);
  else if (Opc == ISD::SRL)
    N0 = ZExtPromoteOperand(N0, PVT);
  else
    N0 = PromoteOperand(N0, PVT, Replace);

  if (!N0.getNode())
    return SDValue();

  SDLoc DL(Op);
  SDValue RV =
      DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));

  if (Replace)
    ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());

  // Deal with Op being deleted.
  if (Op && Op.getOpcode() != ISD::DELETED_NODE)
    return RV;
}
return SDValue();
1306}

1308SDValue DAGCombiner::PromoteExtend(SDValue Op) {
if (!LegalOperations)
  return SDValue();

EVT VT = Op.getValueType();
if (VT.isVector() || !VT.isInteger())
  return SDValue();

// If operation type is 'undesirable', e.g. i16 on x86, consider
// promoting it.
unsigned Opc = Op.getOpcode();
if (TLI.isTypeDesirableForOp(Opc, VT))
  return SDValue();

EVT PVT = VT;
// Consult target whether it is a good idea to promote this operation and
// what's the right type to promote it to.
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
  assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
 ? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1326, __PRETTY_FUNCTION__));
  // fold (aext (aext x)) -> (aext x)
  // fold (aext (zext x)) -> (zext x)
  // fold (aext (sext x)) -> (sext x)
  LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false);
  return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
}
return SDValue();
1334}

1336bool DAGCombiner::PromoteLoad(SDValue Op) {
if (!LegalOperations)
  return false;

if (!ISD::isUNINDEXEDLoad(Op.getNode()))
  return false;

EVT VT = Op.getValueType();
if (VT.isVector() || !VT.isInteger())
  return false;

// If operation type is 'undesirable', e.g. i16 on x86, consider
// promoting it.
unsigned Opc = Op.getOpcode();
if (TLI.isTypeDesirableForOp(Opc, VT))
  return false;

EVT PVT = VT;
// Consult target whether it is a good idea to promote this operation and
// what's the right type to promote it to.
if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
  assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
 ? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1357, __PRETTY_FUNCTION__));

  SDLoc DL(Op);
  SDNode *N = Op.getNode();
  LoadSDNode *LD = cast<LoadSDNode>(N);
  EVT MemVT = LD->getMemoryVT();
  ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
                                                    : LD->getExtensionType();
  SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT,
                                 LD->getChain(), LD->getBasePtr(),
                                 MemVT, LD->getMemOperand());
  SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);

  LLVM_DEBUG(dbgs() << "\nPromoting "; N->dump(&DAG); dbgs() << "\nTo: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
             Result.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false);
  WorklistRemover DeadNodes(*this);
  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
  DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
  deleteAndRecombine(N);
  AddToWorklist(Result.getNode());
  return true;
}
return false;
1380}

1382/// Recursively delete a node which has no uses and any operands for
1383/// which it is the only use.
1384///
1385/// Note that this both deletes the nodes and removes them from the worklist.
1386/// It also adds any nodes who have had a user deleted to the worklist as they
1387/// may now have only one use and subject to other combines.
1388bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
if (!N->use_empty())
  return false;

SmallSetVector<SDNode *, 16> Nodes;
Nodes.insert(N);
do {
  N = Nodes.pop_back_val();
  if (!N)
    continue;

  if (N->use_empty()) {
    for (const SDValue &ChildN : N->op_values())
      Nodes.insert(ChildN.getNode());

    removeFromWorklist(N);
    DAG.DeleteNode(N);
  } else {
    AddToWorklist(N);
  }
} while (!Nodes.empty());
return true;
1410}

1412//===----------------------------------------------------------------------===//
1413//  Main DAG Combiner implementation
1414//===----------------------------------------------------------------------===//

1416void DAGCombiner::Run(CombineLevel AtLevel) {
// set the instance variables, so that the various visit routines may use it.
Level = AtLevel;
LegalDAG = Level >= AfterLegalizeDAG;
LegalOperations = Level >= AfterLegalizeVectorOps;
LegalTypes = Level >= AfterLegalizeTypes;

WorklistInserter AddNodes(*this);

// Add all the dag nodes to the worklist.
for (SDNode &Node : DAG.allnodes())
  AddToWorklist(&Node);

// Create a dummy node (which is not added to allnodes), that adds a reference
// to the root node, preventing it from being deleted, and tracking any
// changes of the root.
HandleSDNode Dummy(DAG.getRoot());

// While we have a valid worklist entry node, try to combine it.
while (SDNode *N = getNextWorklistEntry()) {
  // If N has no uses, it is dead.  Make sure to revisit all N's operands once
  // N is deleted from the DAG, since they too may now be dead or may have a
  // reduced number of uses, allowing other xforms.
  if (recursivelyDeleteUnusedNodes(N))
    continue;

  WorklistRemover DeadNodes(*this);

  // If this combine is running after legalizing the DAG, re-legalize any
  // nodes pulled off the worklist.
  if (LegalDAG) {
    SmallSetVector<SDNode *, 16> UpdatedNodes;
    bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);

    for (SDNode *LN : UpdatedNodes)
      AddToWorklistWithUsers(LN);

    if (!NIsValid)
      continue;
  }

  LLVM_DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nCombining: "; N->dump
(&DAG); } } while (false);

  // Add any operands of the new node which have not yet been combined to the
  // worklist as well. Because the worklist uniques things already, this
  // won't repeatedly process the same operand.
  CombinedNodes.insert(N);
  for (const SDValue &ChildN : N->op_values())
    if (!CombinedNodes.count(ChildN.getNode()))
      AddToWorklist(ChildN.getNode());

  SDValue RV = combine(N);

  if (!RV.getNode())
    continue;

  ++NodesCombined;

  // If we get back the same node we passed in, rather than a new node or
  // zero, we know that the node must have defined multiple values and
  // CombineTo was used.  Since CombineTo takes care of the worklist
  // mechanics for us, we have no work to do in this case.
  if (RV.getNode() == N)
    continue;

  assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1483, __PRETTY_FUNCTION__))
         RV.getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1483, __PRETTY_FUNCTION__))
         "Node was deleted but visit returned new node!")((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1483, __PRETTY_FUNCTION__));

  LLVM_DEBUG(dbgs() << " ... into: "; RV.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << " ... into: "; RV.getNode()
->dump(&DAG); } } while (false);

  if (N->getNumValues() == RV.getNode()->getNumValues())
    DAG.ReplaceAllUsesWith(N, RV.getNode());
  else {
    assert(N->getValueType(0) == RV.getValueType() &&((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1491, __PRETTY_FUNCTION__))
           N->getNumValues() == 1 && "Type mismatch")((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1491, __PRETTY_FUNCTION__));
    DAG.ReplaceAllUsesWith(N, &RV);
  }

  // Push the new node and any users onto the worklist
  AddToWorklist(RV.getNode());
  AddUsersToWorklist(RV.getNode());

  // Finally, if the node is now dead, remove it from the graph.  The node
  // may not be dead if the replacement process recursively simplified to
  // something else needing this node. This will also take care of adding any
  // operands which have lost a user to the worklist.
  recursivelyDeleteUnusedNodes(N);
}

// If the root changed (e.g. it was a dead load, update the root).
DAG.setRoot(Dummy.getValue());
DAG.RemoveDeadNodes();
1509}

1511SDValue DAGCombiner::visit(SDNode *N) {
switch (N->getOpcode()) {
default: break;
case ISD::TokenFactor:        return visitTokenFactor(N);
case ISD::MERGE_VALUES:       return visitMERGE_VALUES(N);
case ISD::ADD:                return visitADD(N);
case ISD::SUB:                return visitSUB(N);
case ISD::SADDSAT:
case ISD::UADDSAT:            return visitADDSAT(N);
case ISD::SSUBSAT:
case ISD::USUBSAT:            return visitSUBSAT(N);
case ISD::ADDC:               return visitADDC(N);
case ISD::SADDO:
case ISD::UADDO:              return visitADDO(N);
case ISD::SUBC:               return visitSUBC(N);
case ISD::SSUBO:
case ISD::USUBO:              return visitSUBO(N);
case ISD::ADDE:               return visitADDE(N);
case ISD::ADDCARRY:           return visitADDCARRY(N);
case ISD::SUBE:               return visitSUBE(N);
case ISD::SUBCARRY:           return visitSUBCARRY(N);
case ISD::SMULFIX:
case ISD::SMULFIXSAT:
case ISD::UMULFIX:
case ISD::UMULFIXSAT:         return visitMULFIX(N);
case ISD::MUL:                return visitMUL(N);
case ISD::SDIV:               return visitSDIV(N);
case ISD::UDIV:               return visitUDIV(N);
case ISD::SREM:
case ISD::UREM:               return visitREM(N);
case ISD::MULHU:              return visitMULHU(N);
case ISD::MULHS:              return visitMULHS(N);
case ISD::SMUL_LOHI:          return visitSMUL_LOHI(N);
case ISD::UMUL_LOHI:          return visitUMUL_LOHI(N);
case ISD::SMULO:
case ISD::UMULO:              return visitMULO(N);
case ISD::SMIN:
case ISD::SMAX:
case ISD::UMIN:
case ISD::UMAX:               return visitIMINMAX(N);
case ISD::AND:                return visitAND(N);
case ISD::OR:                 return visitOR(N);
case ISD::XOR:                return visitXOR(N);
case ISD::SHL:                return visitSHL(N);
case ISD::SRA:                return visitSRA(N);
case ISD::SRL:                return visitSRL(N);
case ISD::ROTR:
case ISD::ROTL:               return visitRotate(N);
case ISD::FSHL:
case ISD::FSHR:               return visitFunnelShift(N);
case ISD::ABS:                return visitABS(N);
case ISD::BSWAP:              return visitBSWAP(N);
case ISD::BITREVERSE:         return visitBITREVERSE(N);
case ISD::CTLZ:               return visitCTLZ(N);
case ISD::CTLZ_ZERO_UNDEF:    return visitCTLZ_ZERO_UNDEF(N);
case ISD::CTTZ:               return visitCTTZ(N);
case ISD::CTTZ_ZERO_UNDEF:    return visitCTTZ_ZERO_UNDEF(N);
case ISD::CTPOP:              return visitCTPOP(N);
case ISD::SELECT:             return visitSELECT(N);
case ISD::VSELECT:            return visitVSELECT(N);
case ISD::SELECT_CC:          return visitSELECT_CC(N);
case ISD::SETCC:              return visitSETCC(N);
case ISD::SETCCCARRY:         return visitSETCCCARRY(N);
case ISD::SIGN_EXTEND:        return visitSIGN_EXTEND(N);
case ISD::ZERO_EXTEND:        return visitZERO_EXTEND(N);
case ISD::ANY_EXTEND:         return visitANY_EXTEND(N);
case ISD::AssertSext:
case ISD::AssertZext:         return visitAssertExt(N);
case ISD::SIGN_EXTEND_INREG:  return visitSIGN_EXTEND_INREG(N);
case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
case ISD::TRUNCATE:           return visitTRUNCATE(N);
case ISD::BITCAST:            return visitBITCAST(N);
case ISD::BUILD_PAIR:         return visitBUILD_PAIR(N);
case ISD::FADD:               return visitFADD(N);
case ISD::FSUB:               return visitFSUB(N);
case ISD::FMUL:               return visitFMUL(N);
case ISD::FMA:                return visitFMA(N);
case ISD::FDIV:               return visitFDIV(N);
case ISD::FREM:               return visitFREM(N);
case ISD::FSQRT:              return visitFSQRT(N);
case ISD::FCOPYSIGN:          return visitFCOPYSIGN(N);
case ISD::FPOW:               return visitFPOW(N);
case ISD::SINT_TO_FP:         return visitSINT_TO_FP(N);
case ISD::UINT_TO_FP:         return visitUINT_TO_FP(N);
case ISD::FP_TO_SINT:         return visitFP_TO_SINT(N);
case ISD::FP_TO_UINT:         return visitFP_TO_UINT(N);
case ISD::FP_ROUND:           return visitFP_ROUND(N);
case ISD::FP_EXTEND:          return visitFP_EXTEND(N);
case ISD::FNEG:               return visitFNEG(N);
case ISD::FABS:               return visitFABS(N);
case ISD::FFLOOR:             return visitFFLOOR(N);
case ISD::FMINNUM:            return visitFMINNUM(N);
case ISD::FMAXNUM:            return visitFMAXNUM(N);
case ISD::FMINIMUM:           return visitFMINIMUM(N);
case ISD::FMAXIMUM:           return visitFMAXIMUM(N);
case ISD::FCEIL:              return visitFCEIL(N);
case ISD::FTRUNC:             return visitFTRUNC(N);
case ISD::BRCOND:             return visitBRCOND(N);
case ISD::BR_CC:              return visitBR_CC(N);
case ISD::LOAD:               return visitLOAD(N);
case ISD::STORE:              return visitSTORE(N);
case ISD::INSERT_VECTOR_ELT:  return visitINSERT_VECTOR_ELT(N);
case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
case ISD::BUILD_VECTOR:       return visitBUILD_VECTOR(N);
case ISD::CONCAT_VECTORS:     return visitCONCAT_VECTORS(N);
case ISD::EXTRACT_SUBVECTOR:  return visitEXTRACT_SUBVECTOR(N);
case ISD::VECTOR_SHUFFLE:     return visitVECTOR_SHUFFLE(N);
case ISD::SCALAR_TO_VECTOR:   return visitSCALAR_TO_VECTOR(N);
case ISD::INSERT_SUBVECTOR:   return visitINSERT_SUBVECTOR(N);
case ISD::MGATHER:            return visitMGATHER(N);
case ISD::MLOAD:              return visitMLOAD(N);
case ISD::MSCATTER:           return visitMSCATTER(N);
case ISD::MSTORE:             return visitMSTORE(N);
case ISD::LIFETIME_END:       return visitLIFETIME_END(N);
case ISD::FP_TO_FP16:         return visitFP_TO_FP16(N);
case ISD::FP16_TO_FP:         return visitFP16_TO_FP(N);
case ISD::VECREDUCE_FADD:
case ISD::VECREDUCE_FMUL:
case ISD::VECREDUCE_ADD:
case ISD::VECREDUCE_MUL:
case ISD::VECREDUCE_AND:
case ISD::VECREDUCE_OR:
case ISD::VECREDUCE_XOR:
case ISD::VECREDUCE_SMAX:
case ISD::VECREDUCE_SMIN:
case ISD::VECREDUCE_UMAX:
case ISD::VECREDUCE_UMIN:
case ISD::VECREDUCE_FMAX:
case ISD::VECREDUCE_FMIN:     return visitVECREDUCE(N);
}
return SDValue();
1643}

1645SDValue DAGCombiner::combine(SDNode *N) {
SDValue RV = visit(N);

// If nothing happened, try a target-specific DAG combine.
if (!RV.getNode()) {
  assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1651, __PRETTY_FUNCTION__))
         "Node was deleted but visit returned NULL!")((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1651, __PRETTY_FUNCTION__));

  if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
      TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {

    // Expose the DAG combiner to the target combiner impls.
    TargetLowering::DAGCombinerInfo
      DagCombineInfo(DAG, Level, false, this);

    RV = TLI.PerformDAGCombine(N, DagCombineInfo);
  }
}

// If nothing happened still, try promoting the operation.
if (!RV.getNode()) {
  switch (N->getOpcode()) {
  default: break;
  case ISD::ADD:
  case ISD::SUB:
  case ISD::MUL:
  case ISD::AND:
  case ISD::OR:
  case ISD::XOR:
    RV = PromoteIntBinOp(SDValue(N, 0));
    break;
  case ISD::SHL:
  case ISD::SRA:
  case ISD::SRL:
    RV = PromoteIntShiftOp(SDValue(N, 0));
    break;
  case ISD::SIGN_EXTEND:
  case ISD::ZERO_EXTEND:
  case ISD::ANY_EXTEND:
    RV = PromoteExtend(SDValue(N, 0));
    break;
  case ISD::LOAD:
    if (PromoteLoad(SDValue(N, 0)))
      RV = SDValue(N, 0);
    break;
  }
}

// If N is a commutative binary node, try to eliminate it if the commuted
// version is already present in the DAG.
if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) &&
    N->getNumValues() == 1) {
  SDValue N0 = N->getOperand(0);
  SDValue N1 = N->getOperand(1);

  // Constant operands are canonicalized to RHS.
  if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
    SDValue Ops[] = {N1, N0};
    SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
                                          N->getFlags());
    if (CSENode)
      return SDValue(CSENode, 0);
  }
}

return RV;
1711}

1713/// Given a node, return its input chain if it has one, otherwise return a null
1714/// sd operand.
1715static SDValue getInputChainForNode(SDNode *N) {
if (unsigned NumOps = N->getNumOperands()) {
  if (N->getOperand(0).getValueType() == MVT::Other)
    return N->getOperand(0);
  if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
    return N->getOperand(NumOps-1);
  for (unsigned i = 1; i < NumOps-1; ++i)
    if (N->getOperand(i).getValueType() == MVT::Other)
      return N->getOperand(i);
}
return SDValue();
1726}

1728SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
// If N has two operands, where one has an input chain equal to the other,
// the 'other' chain is redundant.
if (N->getNumOperands() == 2) {
  if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
    return N->getOperand(0);
  if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
    return N->getOperand(1);
}

// Don't simplify token factors if optnone.
if (OptLevel == CodeGenOpt::None)
  return SDValue();

// If the sole user is a token factor, we should make sure we have a
// chance to merge them together. This prevents TF chains from inhibiting
// optimizations.
if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
  AddToWorklist(*(N->use_begin()));

SmallVector<SDNode *, 8> TFs;     // List of token factors to visit.
SmallVector<SDValue, 8> Ops;      // Ops for replacing token factor.
SmallPtrSet<SDNode*, 16> SeenOps;
bool Changed = false;             // If we should replace this token factor.

// Start out with this token factor.
TFs.push_back(N);

// Iterate through token factors.  The TFs grows when new token factors are
// encountered.
for (unsigned i = 0; i < TFs.size(); ++i) {
  // Limit number of nodes to inline, to avoid quadratic compile times.
  // We have to add the outstanding Token Factors to Ops, otherwise we might
  // drop Ops from the resulting Token Factors.
  if (Ops.size() > TokenFactorInlineLimit) {
    for (unsigned j = i; j < TFs.size(); j++)
      Ops.emplace_back(TFs[j], 0);
    // Drop unprocessed Token Factors from TFs, so we do not add them to the
    // combiner worklist later.
    TFs.resize(i);
    break;
  }

  SDNode *TF = TFs[i];
  // Check each of the operands.
  for (const SDValue &Op : TF->op_values()) {
    switch (Op.getOpcode()) {
    case ISD::EntryToken:
      // Entry tokens don't need to be added to the list. They are
      // redundant.
      Changed = true;
      break;

    case ISD::TokenFactor:
      if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) {
        // Queue up for processing.
        TFs.push_back(Op.getNode());
        Changed = true;
        break;
      }
      LLVM_FALLTHROUGH[[gnu::fallthrough]];

    default:
      // Only add if it isn't already in the list.
      if (SeenOps.insert(Op.getNode()).second)
        Ops.push_back(Op);
      else
        Changed = true;
      break;
    }
  }
}

// Re-visit inlined Token Factors, to clean them up in case they have been
// removed. Skip the first Token Factor, as this is the current node.
for (unsigned i = 1, e = TFs.size(); i < e; i++)
  AddToWorklist(TFs[i]);

// Remove Nodes that are chained to another node in the list. Do so
// by walking up chains breath-first stopping when we've seen
// another operand. In general we must climb to the EntryNode, but we can exit
// early if we find all remaining work is associated with just one operand as
// no further pruning is possible.

// List of nodes to search through and original Ops from which they originate.
SmallVector<std::pair<SDNode *, unsigned>, 8> Worklist;
SmallVector<unsigned, 8> OpWorkCount; // Count of work for each Op.
SmallPtrSet<SDNode *, 16> SeenChains;
bool DidPruneOps = false;

unsigned NumLeftToConsider = 0;
for (const SDValue &Op : Ops) {
  Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++));
  OpWorkCount.push_back(1);
}

auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) {
  // If this is an Op, we can remove the op from the list. Remark any
  // search associated with it as from the current OpNumber.
  if (SeenOps.count(Op) != 0) {
    Changed = true;
    DidPruneOps = true;
    unsigned OrigOpNumber = 0;
    while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op)
      OrigOpNumber++;
    assert((OrigOpNumber != Ops.size()) &&(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1834, __PRETTY_FUNCTION__))
           "expected to find TokenFactor Operand")(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1834, __PRETTY_FUNCTION__));
    // Re-mark worklist from OrigOpNumber to OpNumber
    for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) {
      if (Worklist[i].second == OrigOpNumber) {
        Worklist[i].second = OpNumber;
      }
    }
    OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber];
    OpWorkCount[OrigOpNumber] = 0;
    NumLeftToConsider--;
  }
  // Add if it's a new chain
  if (SeenChains.insert(Op).second) {
    OpWorkCount[OpNumber]++;
    Worklist.push_back(std::make_pair(Op, OpNumber));
  }
};

for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) {
  // We need at least be consider at least 2 Ops to prune.
  if (NumLeftToConsider <= 1)
    break;
  auto CurNode = Worklist[i].first;
  auto CurOpNumber = Worklist[i].second;
  assert((OpWorkCount[CurOpNumber] > 0) &&(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1859, __PRETTY_FUNCTION__))
         "Node should not appear in worklist")(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1859, __PRETTY_FUNCTION__));
  switch (CurNode->getOpcode()) {
  case ISD::EntryToken:
    // Hitting EntryToken is the only way for the search to terminate without
    // hitting
    // another operand's search. Prevent us from marking this operand
    // considered.
    NumLeftToConsider++;
    break;
  case ISD::TokenFactor:
    for (const SDValue &Op : CurNode->op_values())
      AddToWorklist(i, Op.getNode(), CurOpNumber);
    break;
  case ISD::LIFETIME_START:
  case ISD::LIFETIME_END:
  case ISD::CopyFromReg:
  case ISD::CopyToReg:
    AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber);
    break;
  default:
    if (auto *MemNode = dyn_cast<MemSDNode>(CurNode))
      AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber);
    break;
  }
  OpWorkCount[CurOpNumber]--;
  if (OpWorkCount[CurOpNumber] == 0)
    NumLeftToConsider--;
}

// If we've changed things around then replace token factor.
if (Changed) {
  SDValue Result;
  if (Ops.empty()) {
    // The entry token is the only possible outcome.
    Result = DAG.getEntryNode();
  } else {
    if (DidPruneOps) {
      SmallVector<SDValue, 8> PrunedOps;
      //
      for (const SDValue &Op : Ops) {
        if (SeenChains.count(Op.getNode()) == 0)
          PrunedOps.push_back(Op);
      }
      Result = DAG.getTokenFactor(SDLoc(N), PrunedOps);
    } else {
      Result = DAG.getTokenFactor(SDLoc(N), Ops);
    }
  }
  return Result;
}
return SDValue();
1910}

1912/// MERGE_VALUES can always be eliminated.
1913SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
WorklistRemover DeadNodes(*this);
// Replacing results may cause a different MERGE_VALUES to suddenly
// be CSE'd with N, and carry its uses with it. Iterate until no
// uses remain, to ensure that the node can be safely deleted.
// First add the users of this node to the work list so that they
// can be tried again once they have new operands.
AddUsersToWorklist(N);
do {
  // Do as a single replacement to avoid rewalking use lists.
  SmallVector<SDValue, 8> Ops;
  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
    Ops.push_back(N->getOperand(i));
  DAG.ReplaceAllUsesWith(N, Ops.data());
} while (!N->use_empty());
deleteAndRecombine(N);
return SDValue(N, 0);   // Return N so it doesn't get rechecked!
1930}

1932/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a
1933/// ConstantSDNode pointer else nullptr.
1934static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
1937}

1939SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 &&((TLI.isBinOp(BO->getOpcode()) && BO->getNumValues
() == 1 && "Unexpected binary operator") ? static_cast
<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1941, __PRETTY_FUNCTION__))
       "Unexpected binary operator")((TLI.isBinOp(BO->getOpcode()) && BO->getNumValues
() == 1 && "Unexpected binary operator") ? static_cast
<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1941, __PRETTY_FUNCTION__));

// Don't do this unless the old select is going away. We want to eliminate the
// binary operator, not replace a binop with a select.
// TODO: Handle ISD::SELECT_CC.
unsigned SelOpNo = 0;
SDValue Sel = BO->getOperand(0);
if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
  SelOpNo = 1;
  Sel = BO->getOperand(1);
}

if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
  return SDValue();

SDValue CT = Sel.getOperand(1);
if (!isConstantOrConstantVector(CT, true) &&
    !isConstantFPBuildVectorOrConstantFP(CT))
  return SDValue();

SDValue CF = Sel.getOperand(2);
if (!isConstantOrConstantVector(CF, true) &&
    !isConstantFPBuildVectorOrConstantFP(CF))
  return SDValue();

// Bail out if any constants are opaque because we can't constant fold those.
// The exception is "and" and "or" with either 0 or -1 in which case we can
// propagate non constant operands into select. I.e.:
// and (select Cond, 0, -1), X --> select Cond, 0, X
// or X, (select Cond, -1, 0) --> select Cond, -1, X
auto BinOpcode = BO->getOpcode();
bool CanFoldNonConst =
    (BinOpcode == ISD::AND || BinOpcode == ISD::OR) &&
    (isNullOrNullSplat(CT) || isAllOnesOrAllOnesSplat(CT)) &&
    (isNullOrNullSplat(CF) || isAllOnesOrAllOnesSplat(CF));

SDValue CBO = BO->getOperand(SelOpNo ^ 1);
if (!CanFoldNonConst &&
    !isConstantOrConstantVector(CBO, true) &&
    !isConstantFPBuildVectorOrConstantFP(CBO))
  return SDValue();

EVT VT = Sel.getValueType();

// In case of shift value and shift amount may have different VT. For instance
// on x86 shift amount is i8 regardles of LHS type. Bail out if we have
// swapped operands and value types do not match. NB: x86 is fine if operands
// are not swapped with shift amount VT being not bigger than shifted value.
// TODO: that is possible to check for a shift operation, correct VTs and
// still perform optimization on x86 if needed.
if (SelOpNo && VT != CBO.getValueType())
  return SDValue();

// We have a select-of-constants followed by a binary operator with a
// constant. Eliminate the binop by pulling the constant math into the select.
// Example: add (select Cond, CT, CF), CBO --> select Cond, CT + CBO, CF + CBO
SDLoc DL(Sel);
SDValue NewCT = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CT)
                        : DAG.getNode(BinOpcode, DL, VT, CT, CBO);
if (!CanFoldNonConst && !NewCT.isUndef() &&
    !isConstantOrConstantVector(NewCT, true) &&
    !isConstantFPBuildVectorOrConstantFP(NewCT))
  return SDValue();

SDValue NewCF = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CF)
                        : DAG.getNode(BinOpcode, DL, VT, CF, CBO);
if (!CanFoldNonConst && !NewCF.isUndef() &&
    !isConstantOrConstantVector(NewCF, true) &&
    !isConstantFPBuildVectorOrConstantFP(NewCF))
  return SDValue();

SDValue SelectOp = DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF);
SelectOp->setFlags(BO->getFlags());
return SelectOp;
2015}

2017static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) {
assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2019, __PRETTY_FUNCTION__))
       "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2019, __PRETTY_FUNCTION__));

// Match a constant operand and a zext operand for the math instruction:
// add Z, C
// sub C, Z
bool IsAdd = N->getOpcode() == ISD::ADD;
SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0);
SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1);
auto *CN = dyn_cast<ConstantSDNode>(C);
if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND)
  return SDValue();

// Match the zext operand as a setcc of a boolean.
if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
    Z.getOperand(0).getValueType() != MVT::i1)
  return SDValue();

// Match the compare as: setcc (X & 1), 0, eq.
SDValue SetCC = Z.getOperand(0);
ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) ||
    SetCC.getOperand(0).getOpcode() != ISD::AND ||
    !isOneConstant(SetCC.getOperand(0).getOperand(1)))
  return SDValue();

// We are adding/subtracting a constant and an inverted low bit. Turn that
// into a subtract/add of the low bit with incremented/decremented constant:
// add (zext i1 (seteq (X & 1), 0)), C --> sub C+1, (zext (X & 1))
// sub C, (zext i1 (seteq (X & 1), 0)) --> add C-1, (zext (X & 1))
EVT VT = C.getValueType();
SDLoc DL(N);
SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT);
SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) :
                     DAG.getConstant(CN->getAPIntValue() - 1, DL, VT);
return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
2054}

2056/// Try to fold a 'not' shifted sign-bit with add/sub with constant operand into
2057/// a shift and add with a different constant.
2058static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) {
assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2060, __PRETTY_FUNCTION__))
       "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2060, __PRETTY_FUNCTION__));

// We need a constant operand for the add/sub, and the other operand is a
// logical shift right: add (srl), C or sub C, (srl).
// TODO - support non-uniform vector amounts.
bool IsAdd = N->getOpcode() == ISD::ADD;
SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0);
SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1);
ConstantSDNode *C = isConstOrConstSplat(ConstantOp);
if (!C || ShiftOp.getOpcode() != ISD::SRL)
  return SDValue();

// The shift must be of a 'not' value.
SDValue Not = ShiftOp.getOperand(0);
if (!Not.hasOneUse() || !isBitwiseNot(Not))
  return SDValue();

// The shift must be moving the sign bit to the least-significant-bit.
EVT VT = ShiftOp.getValueType();
SDValue ShAmt = ShiftOp.getOperand(1);
ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
if (!ShAmtC || ShAmtC->getAPIntValue() != (VT.getScalarSizeInBits() - 1))
  return SDValue();

// Eliminate the 'not' by adjusting the shift and add/sub constant:
// add (srl (not X), 31), C --> add (sra X, 31), (C + 1)
// sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1)
SDLoc DL(N);
auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
SDValue NewShift = DAG.getNode(ShOpcode, DL, VT, Not.getOperand(0), ShAmt);
APInt NewC = IsAdd ? C->getAPIntValue() + 1 : C->getAPIntValue() - 1;
return DAG.getNode(ISD::ADD, DL, VT, NewShift, DAG.getConstant(NewC, DL, VT));
2092}

2094/// Try to fold a node that behaves like an ADD (note that N isn't necessarily
2095/// an ISD::ADD here, it could for example be an ISD::OR if we know that there
2096/// are no common bits set in the operands).
2097SDValue DAGCombiner::visitADDLike(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
SDLoc DL(N);

// fold vector ops
if (VT.isVector()) {
  if (SDValue FoldedVOp = SimplifyVBinOp(N))
    return FoldedVOp;

  // fold (add x, 0) -> x, vector edition
  if (ISD::isBuildVectorAllZeros(N1.getNode()))
    return N0;
  if (ISD::isBuildVectorAllZeros(N0.getNode()))
    return N1;
}

// fold (add x, undef) -> undef
if (N0.isUndef())
  return N0;

if (N1.isUndef())
  return N1;

if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
  // canonicalize constant to RHS
  if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
    return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
  // fold (add c1, c2) -> c1+c2
  return DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0, N1});
}

// fold (add x, 0) -> x
if (isNullConstant(N1))
  return N0;

if (isConstantOrConstantVector(N1, /* NoOpaque */ true)) {
  // fold ((A-c1)+c2) -> (A+(c2-c1))
  if (N0.getOpcode() == ISD::SUB &&
      isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) {
    SDValue Sub =
        DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N1, N0.getOperand(1)});
    assert(Sub && "Constant folding failed")((Sub && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("Sub && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2140, __PRETTY_FUNCTION__));
    return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Sub);
  }

  // fold ((c1-A)+c2) -> (c1+c2)-A
  if (N0.getOpcode() == ISD::SUB &&
      isConstantOrConstantVector(N0.getOperand(0), /* NoOpaque */ true)) {
    SDValue Add =
        DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N0.getOperand(0)});
    assert(Add && "Constant folding failed")((Add && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("Add && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2149, __PRETTY_FUNCTION__));
    return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
  }

  // add (sext i1 X), 1 -> zext (not i1 X)
  // We don't transform this pattern:
  //   add (zext i1 X), -1 -> sext (not i1 X)
  // because most (?) targets generate better code for the zext form.
  if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
      isOneOrOneSplat(N1)) {
    SDValue X = N0.getOperand(0);
    if ((!LegalOperations ||
         (TLI.isOperationLegal(ISD::XOR, X.getValueType()) &&
          TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) &&
        X.getScalarValueSizeInBits() == 1) {
      SDValue Not = DAG.getNOT(DL, X, X.getValueType());
      return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not);
    }
  }

  // Undo the add -> or combine to merge constant offsets from a frame index.
  if (N0.getOpcode() == ISD::OR &&
      isa<FrameIndexSDNode>(N0.getOperand(0)) &&
      isa<ConstantSDNode>(N0.getOperand(1)) &&
      DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) {
    SDValue Add0 = DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(1));
    return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add0);
  }
}

if (SDValue NewSel = foldBinOpIntoSelect(N))
  return NewSel;

// reassociate add
if (!reassociationCanBreakAddressingModePattern(ISD::ADD, DL, N0, N1)) {
  if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
    return RADD;
}
// fold ((0-A) + B) -> B-A
if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0)))
  return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));

// fold (A + (0-B)) -> A-B
if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
  return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1));

// fold (A+(B-A)) -> B
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
  return N1.getOperand(0);

// fold ((B-A)+A) -> B
if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
  return N0.getOperand(0);

// fold ((A-B)+(C-A)) -> (C-B)
if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
    N0.getOperand(0) == N1.getOperand(1))
  return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
                     N0.getOperand(1));

// fold ((A-B)+(B-C)) -> (A-C)
if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
    N0.getOperand(1) == N1.getOperand(0))
  return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
                     N1.getOperand(1));

// fold (A+(B-(A+C))) to (B-C)
if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
    N0 == N1.getOperand(1).getOperand(0))
  return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
                     N1.getOperand(1).getOperand(1));

// fold (A+(B-(C+A))) to (B-C)
if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
    N0 == N1.getOperand(1).getOperand(1))
  return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
                     N1.getOperand(1).getOperand(0));

// fold (A+((B-A)+or-C)) to (B+or-C)
if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
    N1.getOperand(0).getOpcode() == ISD::SUB &&
    N0 == N1.getOperand(0).getOperand(1))
  return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0),
                     N1.getOperand(1));

// fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
  SDValue N00 = N0.getOperand(0);
  SDValue N01 = N0.getOperand(1);
  SDValue N10 = N1.getOperand(0);
  SDValue N11 = N1.getOperand(1);

  if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10))
    return DAG.getNode(ISD::SUB, DL, VT,
                       DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
                       DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
}

// fold (add (umax X, C), -C) --> (usubsat X, C)
if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
  auto MatchUSUBSAT = [](ConstantSDNode *Max, ConstantSDNode *Op) {
    return (!Max && !Op) ||
           (Max && Op && Max->getAPIntValue() == (-Op->getAPIntValue()));
  };
  if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT,
                                /*AllowUndefs*/ true))
    return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
                       N0.getOperand(1));
}

if (SimplifyDemandedBits(SDValue(N, 0)))
  return SDValue(N, 0);

if (isOneOrOneSplat(N1)) {
  // fold (add (xor a, -1), 1) -> (sub 0, a)
  if (isBitwiseNot(N0))
    return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
                       N0.getOperand(0));

  // fold (add (add (xor a, -1), b), 1) -> (sub b, a)
  if (N0.getOpcode() == ISD::ADD ||
      N0.getOpcode() == ISD::UADDO ||
      N0.getOpcode() == ISD::SADDO) {
    SDValue A, Xor;

    if (isBitwiseNot(N0.getOperand(0))) {
      A = N0.getOperand(1);
      Xor = N0.getOperand(0);
    } else if (isBitwiseNot(N0.getOperand(1))) {
      A = N0.getOperand(0);
      Xor = N0.getOperand(1);
    }

    if (Xor)
      return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0));
  }

  // Look for:
  //   add (add x, y), 1
  // And if the target does not like this form then turn into:
  //   sub y, (xor x, -1)
  if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.hasOneUse() &&
      N0.getOpcode() == ISD::ADD) {
    SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
                              DAG.getAllOnesConstant(DL, VT));
    return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not);
  }
}

// (x - y) + -1  ->  add (xor y, -1), x
if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
    isAllOnesOrAllOnesSplat(N1)) {
  SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1), N1);
  return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
}

if (SDValue Combined = visitADDLikeCommutative(N0, N1, N))
  return Combined;

if (SDValue Combined = visitADDLikeCommutative(N1, N0, N))
  return Combined;

return SDValue();
2312}

2314SDValue DAGCombiner::visitADD(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
SDLoc DL(N);

if (SDValue Combined = visitADDLike(N))
  return Combined;

if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
  return V;

if (SDValue V = foldAddSubOfSignBit(N, DAG))
  return V;

// fold (a+b) -> (a|b) iff a and b share no bits.
if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
    DAG.haveNoCommonBitsSet(N0, N1))
  return DAG.getNode(ISD::OR, DL, VT, N0, N1);

// Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) {
  APInt C0 = N0->getConstantOperandAPInt(0);
  APInt C1 = N1->getConstantOperandAPInt(0);
  return DAG.getVScale(DL, VT, C0 + C1);
}

return SDValue();
2342}

2344SDValue DAGCombiner::visitADDSAT(SDNode *N) {
unsigned Opcode = N->getOpcode();
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
SDLoc DL(N);

// fold vector ops
if (VT.isVector()) {
  // TODO SimplifyVBinOp

  // fold (add_sat x, 0) -> x, vector edition
  if (ISD::isBuildVectorAllZeros(N1.getNode()))
    return N0;
  if (ISD::isBuildVectorAllZeros(N0.getNode()))
    return N1;
}

// fold (add_sat x, undef) -> -1
if (N0.isUndef() || N1.isUndef())
  return DAG.getAllOnesConstant(DL, VT);

if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
  // canonicalize constant to RHS
  if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
    return DAG.getNode(Opcode, DL, VT, N1, N0);
  // fold (add_sat c1, c2) -> c3
  return DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1});
}

// fold (add_sat x, 0) -> x
if (isNullConstant(N1))
  return N0;

// If it cannot overflow, transform into an add.
if (Opcode == ISD::UADDSAT)
  if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
    return DAG.getNode(ISD::ADD, DL, VT, N0, N1);

return SDValue();
2384}

2386static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
bool Masked = false;

// First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization.
while (true) {
  if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
    V = V.getOperand(0);
    continue;
  }

  if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
    Masked = true;
    V = V.getOperand(0);
    continue;
  }

  break;
}

// If this is not a carry, return.
if (V.getResNo() != 1)
  return SDValue();

if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
    V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
  return SDValue();

EVT VT = V.getNode()->getValueType(0);
if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT))
  return SDValue();

// If the result is masked, then no matter what kind of bool it is we can
// return. If it isn't, then we need to make sure the bool type is either 0 or
// 1 and not other values.
if (Masked ||
    TLI.getBooleanContents(V.getValueType()) ==
        TargetLoweringBase::ZeroOrOneBooleanContent)
  return V;

return SDValue();
2426}

2428/// Given the operands of an add/sub operation, see if the 2nd operand is a
2429/// masked 0/1 whose source operand is actually known to be 0/-1. If so, invert
2430/// the opcode and bypass the mask operation.
2431static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1,
                               SelectionDAG &DAG, const SDLoc &DL) {
if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
  return SDValue();

EVT VT = N0.getValueType();
if (DAG.ComputeNumSignBits(N1.getOperand(0)) != VT.getScalarSizeInBits())
  return SDValue();

// add N0, (and (AssertSext X, i1), 1) --> sub N0, X
// sub N0, (and (AssertSext X, i1), 1) --> add N0, X
return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N1.getOperand(0));
2443}

2445/// Helper for doing combines based on N0 and N1 being added to each other.
2446SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
                                        SDNode *LocReference) {
EVT VT = N0.getValueType();
SDLoc DL(LocReference);

// fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
    isNullOrNullSplat(N1.getOperand(0).getOperand(0)))
  return DAG.getNode(ISD::SUB, DL, VT, N0,
                     DAG.getNode(ISD::SHL, DL, VT,
                                 N1.getOperand(0).getOperand(1),
                                 N1.getOperand(1)));

if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL))
  return V;

// Look for:
//   add (add x, 1), y
// And if the target does not like this form then turn into:
//   sub y, (xor x, -1)
if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.hasOneUse() &&
    N0.getOpcode() == ISD::ADD && isOneOrOneSplat(N0.getOperand(1))) {
  SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
                            DAG.getAllOnesConstant(DL, VT));
  return DAG.getNode(ISD::SUB, DL, VT, N1, Not);
}

// Hoist one-use subtraction by non-opaque constant:
//   (x - C) + y  ->  (x + y) - C
// This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
    isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
  SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), N1);
  return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
}
// Hoist one-use subtraction from non-opaque constant:
//   (C - x) + y  ->  (y - x) + C
if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
    isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
  SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
  return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(0));
}

// If the target's bool is represented as 0/1, prefer to make this 'sub 0/1'
// rather than 'add 0/-1' (the zext should get folded).
// add (sext i1 Y), X --> sub X, (zext i1 Y)
if (N0.getOpcode() == ISD::SIGN_EXTEND &&
    N0.getOperand(0).getScalarValueSizeInBits() == 1 &&
    TLI.getBooleanContents(VT) == TargetLowering::ZeroOrOneBooleanContent) {
  SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
  return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
}

// add X, (sextinreg Y i1) -> sub X, (and Y 1)
if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
  VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
  if (TN->getVT() == MVT::i1) {
    SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
                               DAG.getConstant(1, DL, VT));
    return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
  }
}

// (add X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
    N1.getResNo() == 0)
  return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
                     N0, N1.getOperand(0), N1.getOperand(2));

// (add X, Carry) -> (addcarry X, 0, Carry)
if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
  if (SDValue Carry = getAsCarry(TLI, N1))
    return DAG.getNode(ISD::ADDCARRY, DL,
                       DAG.getVTList(VT, Carry.getValueType()), N0,
                       DAG.getConstant(0, DL, VT), Carry);

return SDValue();
2523}

2525SDValue DAGCombiner::visitADDC(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
SDLoc DL(N);

// If the flag result is dead, turn this into an ADD.
if (!N->hasAnyUseOfValue(1))
  return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
                   DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));

// canonicalize constant to RHS.
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
if (N0C && !N1C)
  return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);

// fold (addc x, 0) -> x + no carry out
if (isNullConstant(N1))
  return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
                                      DL, MVT::Glue));

// If it cannot overflow, transform into an add.
if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
  return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
                   DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));

return SDValue();
2553}

2555static SDValue flipBoolean(SDValue V, const SDLoc &DL,
                         SelectionDAG &DAG, const TargetLowering &TLI) {
EVT VT = V.getValueType();

SDValue Cst;
switch (TLI.getBooleanContents(VT)) {
case TargetLowering::ZeroOrOneBooleanContent:
case TargetLowering::UndefinedBooleanContent:
  Cst = DAG.getConstant(1, DL, VT);
  break;
case TargetLowering::ZeroOrNegativeOneBooleanContent:
  Cst = DAG.getAllOnesConstant(DL, VT);
  break;
}

return DAG.getNode(ISD::XOR, DL, VT, V, Cst);
2571}

2573/**
* Flips a boolean if it is cheaper to compute. If the Force parameters is set,
* then the flip also occurs if computing the inverse is the same cost.
* This function returns an empty SDValue in case it cannot flip the boolean
* without increasing the cost of the computation. If you want to flip a boolean
* no matter what, use flipBoolean.
*/
2580static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG,
                                const TargetLowering &TLI,
                                bool Force) {
if (Force && isa<ConstantSDNode>(V))
  return flipBoolean(V, SDLoc(V), DAG, TLI);

if (V.getOpcode() != ISD::XOR)
  return SDValue();

ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
if (!Const)
  return SDValue();

EVT VT = V.getValueType();

bool IsFlip = false;
switch(TLI.getBooleanContents(VT)) {
  case TargetLowering::ZeroOrOneBooleanContent:
    IsFlip = Const->isOne();
    break;
  case TargetLowering::ZeroOrNegativeOneBooleanContent:
    IsFlip = Const->isAllOnesValue();
    break;
  case TargetLowering::UndefinedBooleanContent:
    IsFlip = (Const->getAPIntValue() & 0x01) == 1;
    break;
}

if (IsFlip)
  return V.getOperand(0);
if (Force)
  return flipBoolean(V, SDLoc(V), DAG, TLI);
return SDValue();
2613}

2615SDValue DAGCombiner::visitADDO(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
bool IsSigned = (ISD::SADDO == N->getOpcode());

EVT CarryVT = N->getValueType(1);
SDLoc DL(N);

// If the flag result is dead, turn this into an ADD.
if (!N->hasAnyUseOfValue(1))
  return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
                   DAG.getUNDEF(CarryVT));

// canonicalize constant to RHS.
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
    !DAG.isConstantIntBuildVectorOrConstantInt(N1))
  return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);

// fold (addo x, 0) -> x + no carry out
if (isNullOrNullSplat(N1))
  return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));

if (!IsSigned) {
  // If it cannot overflow, transform into an add.
  if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
    return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
                     DAG.getConstant(0, DL, CarryVT));

  // fold (uaddo (xor a, -1), 1) -> (usub 0, a) and flip carry.
  if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) {
    SDValue Sub = DAG.getNode(ISD::USUBO, DL, N->getVTList(),
                              DAG.getConstant(0, DL, VT), N0.getOperand(0));
    return CombineTo(N, Sub,
                     flipBoolean(Sub.getValue(1), DL, DAG, TLI));
  }

  if (SDValue Combined = visitUADDOLike(N0, N1, N))
    return Combined;

  if (SDValue Combined = visitUADDOLike(N1, N0, N))
    return Combined;
}

return SDValue();
2660}

2662SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
EVT VT = N0.getValueType();
if (VT.isVector())
  return SDValue();

// (uaddo X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
// If Y + 1 cannot overflow.
if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
  SDValue Y = N1.getOperand(0);
  SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType());
  if (DAG.computeOverflowKind(Y, One) == SelectionDAG::OFK_Never)
    return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
                       N1.getOperand(2));
}

// (uaddo X, Carry) -> (addcarry X, 0, Carry)
if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
  if (SDValue Carry = getAsCarry(TLI, N1))
    return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
                       DAG.getConstant(0, SDLoc(N), VT), Carry);

return SDValue();
2684}

2686SDValue DAGCombiner::visitADDE(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue CarryIn = N->getOperand(2);

// canonicalize constant to RHS
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
if (N0C && !N1C)
  return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
                     N1, N0, CarryIn);

// fold (adde x, y, false) -> (addc x, y)
if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
  return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);

return SDValue();
2703}

2705SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue CarryIn = N->getOperand(2);
SDLoc DL(N);

// canonicalize constant to RHS
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
if (N0C && !N1C)
1
Assuming 'N0C' is null→
  return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);

// fold (addcarry x, y, false) -> (uaddo x, y)
if (isNullConstant(CarryIn)) {
2
←
Assuming the condition is false→
3
←
Taking false branch→
  if (!LegalOperations ||
      TLI.isOperationLegalOrCustom(ISD::UADDO, N->getValueType(0)))
    return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
}

// fold (addcarry 0, 0, X) -> (and (ext/trunc X), 1) and no carry.
if (isNullConstant(N0) && isNullConstant(N1)) {
4
←
Assuming the condition is false→
  EVT VT = N0.getValueType();
  EVT CarryVT = CarryIn.getValueType();
  SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT);
  AddToWorklist(CarryExt.getNode());
  return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,
                                  DAG.getConstant(1, DL, VT)),
                   DAG.getConstant(0, DL, CarryVT));
}

if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N))
5
←
Value assigned to 'N0.Node'→
6
←
Calling 'DAGCombiner::visitADDCARRYLike'→
  return Combined;

if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
  return Combined;

return SDValue();
2742}

2744/**
* If we are facing some sort of diamond carry propapagtion pattern try to
* break it up to generate something like:
*   (addcarry X, 0, (addcarry A, B, Z):Carry)
*
* The end result is usually an increase in operation required, but because the
* carry is now linearized, other tranforms can kick in and optimize the DAG.
*
* Patterns typically look something like
*            (uaddo A, B)
*             /       \
*          Carry      Sum
*            |          \
*            | (addcarry *, 0, Z)
*            |       /
*             \   Carry
*              |   /
* (addcarry X, *, *)
*
* But numerous variation exist. Our goal is to identify A, B, X and Z and
* produce a combine with a single path for carry propagation.
*/
2766static SDValue combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
                                    SDValue X, SDValue Carry0, SDValue Carry1,
                                    SDNode *N) {
if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1)
  return SDValue();
if (Carry1.getOpcode() != ISD::UADDO)
  return SDValue();

SDValue Z;

/**
 * First look for a suitable Z. It will present itself in the form of
 * (addcarry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true
 */
if (Carry0.getOpcode() == ISD::ADDCARRY &&
    isNullConstant(Carry0.getOperand(1))) {
  Z = Carry0.getOperand(2);
} else if (Carry0.getOpcode() == ISD::UADDO &&
           isOneConstant(Carry0.getOperand(1))) {
  EVT VT = Combiner.getSetCCResultType(Carry0.getValueType());
  Z = DAG.getConstant(1, SDLoc(Carry0.getOperand(1)), VT);
} else {
  // We couldn't find a suitable Z.
  return SDValue();
}


auto cancelDiamond = [&](SDValue A,SDValue B) {
  SDLoc DL(N);
  SDValue NewY = DAG.getNode(ISD::ADDCARRY, DL, Carry0->getVTList(), A, B, Z);
  Combiner.AddToWorklist(NewY.getNode());
  return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), X,
                     DAG.getConstant(0, DL, X.getValueType()),
                     NewY.getValue(1));
};

/**
 *      (uaddo A, B)
 *           |
 *          Sum
 *           |
 * (addcarry *, 0, Z)
 */
if (Carry0.getOperand(0) == Carry1.getValue(0)) {
  return cancelDiamond(Carry1.getOperand(0), Carry1.getOperand(1));
}

/**
 * (addcarry A, 0, Z)
 *         |
 *        Sum
 *         |
 *  (uaddo *, B)
 */
if (Carry1.getOperand(0) == Carry0.getValue(0)) {
  return cancelDiamond(Carry0.getOperand(0), Carry1.getOperand(1));
}

if (Carry1.getOperand(1) == Carry0.getValue(0)) {
  return cancelDiamond(Carry1.getOperand(0), Carry0.getOperand(0));
}

return SDValue();
2829}

2831// If we are facing some sort of diamond carry/borrow in/out pattern try to
2832// match patterns like:
2833//
2834//          (uaddo A, B)            CarryIn
2835//            |  \                     |
2836//            |   \                    |
2837//    PartialSum   PartialCarryOutX   /
2838//            |        |             /
2839//            |    ____|____________/
2840//            |   /    |
2841//     (uaddo *, *)    \________
2842//       |  \                   \
2843//       |   \                   |
2844//       |    PartialCarryOutY   |
2845//       |        \              |
2846//       |         \            /
2847//   AddCarrySum    |    ______/
2848//                  |   /
2849//   CarryOut = (or *, *)
2850//
2851// And generate ADDCARRY (or SUBCARRY) with two result values:
2852//
2853//    {AddCarrySum, CarryOut} = (addcarry A, B, CarryIn)
2854//
2855// Our goal is to identify A, B, and CarryIn and produce ADDCARRY/SUBCARRY with
2856// a single path for carry/borrow out propagation:
2857static SDValue combineCarryDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
                                 const TargetLowering &TLI, SDValue Carry0,
                                 SDValue Carry1, SDNode *N) {
if (Carry0.getResNo() != 1 || Carry1.getResNo() != 1)
  return SDValue();
unsigned Opcode = Carry0.getOpcode();
if (Opcode != Carry1.getOpcode())
  return SDValue();
if (Opcode != ISD::UADDO && Opcode != ISD::USUBO)
  return SDValue();

// Canonicalize the add/sub of A and B as Carry0 and the add/sub of the
// carry/borrow in as Carry1. (The top and middle uaddo nodes respectively in
// the above ASCII art.)
if (Carry1.getOperand(0) != Carry0.getValue(0) &&
    Carry1.getOperand(1) != Carry0.getValue(0))
  std::swap(Carry0, Carry1);
if (Carry1.getOperand(0) != Carry0.getValue(0) &&
    Carry1.getOperand(1) != Carry0.getValue(0))
  return SDValue();

// The carry in value must be on the righthand side for subtraction.
unsigned CarryInOperandNum =
    Carry1.getOperand(0) == Carry0.getValue(0) ? 1 : 0;
if (Opcode == ISD::USUBO && CarryInOperandNum != 1)
  return SDValue();
SDValue CarryIn = Carry1.getOperand(CarryInOperandNum);

unsigned NewOp = Opcode == ISD::UADDO ? ISD::ADDCARRY : ISD::SUBCARRY;
if (!TLI.isOperationLegalOrCustom(NewOp, Carry0.getValue(0).getValueType()))
  return SDValue();

// Verify that the carry/borrow in is plausibly a carry/borrow bit.
// TODO: make getAsCarry() aware of how partial carries are merged.
if (CarryIn.getOpcode() != ISD::ZERO_EXTEND)
  return SDValue();
CarryIn = CarryIn.getOperand(0);
if (CarryIn.getValueType() != MVT::i1)
  return SDValue();

SDLoc DL(N);
SDValue Merged =
    DAG.getNode(NewOp, DL, Carry1->getVTList(), Carry0.getOperand(0),
                Carry0.getOperand(1), CarryIn);

// Please note that because we have proven that the result of the UADDO/USUBO
// of A and B feeds into the UADDO/USUBO that does the carry/borrow in, we can
// therefore prove that if the first UADDO/USUBO overflows, the second
// UADDO/USUBO cannot. For example consider 8-bit numbers where 0xFF is the
// maximum value.
//
//   0xFF + 0xFF == 0xFE with carry but 0xFE + 1 does not carry
//   0x00 - 0xFF == 1 with a carry/borrow but 1 - 1 == 0 (no carry/borrow)
//
// This is important because it means that OR and XOR can be used to merge
// carry flags; and that AND can return a constant zero.
//
// TODO: match other operations that can merge flags (ADD, etc)
DAG.ReplaceAllUsesOfValueWith(Carry1.getValue(0), Merged.getValue(0));
if (N->getOpcode() == ISD::AND)
  return DAG.getConstant(0, DL, MVT::i1);
return Merged.getValue(1);
2919}

2921SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
                                     SDNode *N) {
// fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
if (isBitwiseNot(N0))
7
←
Assuming the condition is false→
8
←
Taking false branch→
  if (SDValue NotC = extractBooleanFlip(CarryIn, DAG, TLI, true)) {
    SDLoc DL(N);
    SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(), N1,
                              N0.getOperand(0), NotC);
    return CombineTo(N, Sub,
                     flipBoolean(Sub.getValue(1), DL, DAG, TLI));
  }

// Iff the flag result is dead:
// (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
// Don't do this if the Carry comes from the uaddo. It won't remove the uaddo
// or the dependency between the instructions.
if ((N0.getOpcode() == ISD::ADD ||
9
←
Calling 'SDValue::getOpcode'→
     (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 &&
      N0.getValue(1) != CarryIn)) &&
    isNullConstant(N1) && !N->hasAnyUseOfValue(1))
  return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
                     N0.getOperand(0), N0.getOperand(1), CarryIn);

/**
 * When one of the addcarry argument is itself a carry, we may be facing
 * a diamond carry propagation. In which case we try to transform the DAG
 * to ensure linear carry propagation if that is possible.
 */
if (auto Y = getAsCarry(TLI, N1)) {
  // Because both are carries, Y and Z can be swapped.
  if (auto R = combineADDCARRYDiamond(*this, DAG, N0, Y, CarryIn, N))
    return R;
  if (auto R = combineADDCARRYDiamond(*this, DAG, N0, CarryIn, Y, N))
    return R;
}

return SDValue();
2958}

2960// Since it may not be valid to emit a fold to zero for vector initializers
2961// check if we can before folding.
2962static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
                           SelectionDAG &DAG, bool LegalOperations) {
if (!VT.isVector())
  return DAG.getConstant(0, DL, VT);
if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
  return DAG.getConstant(0, DL, VT);
return SDValue();
2969}

2971SDValue DAGCombiner::visitSUB(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
SDLoc DL(N);

// fold vector ops
if (VT.isVector()) {
  if (SDValue FoldedVOp = SimplifyVBinOp(N))
    return FoldedVOp;

  // fold (sub x, 0) -> x, vector edition
  if (ISD::isBuildVectorAllZeros(N1.getNode()))
    return N0;
}

// fold (sub x, x) -> 0
// FIXME: Refactor this and xor and other similar operations together.
if (N0 == N1)
  return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);

// fold (sub c1, c2) -> c3
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N1}))
  return C;

if (SDValue NewSel = foldBinOpIntoSelect(N))
  return NewSel;

ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);

// fold (sub x, c) -> (add x, -c)
if (N1C) {
  return DAG.getNode(ISD::ADD, DL, VT, N0,
                     DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
}

if (isNullOrNullSplat(N0)) {
  unsigned BitWidth = VT.getScalarSizeInBits();
  // Right-shifting everything out but the sign bit followed by negation is
  // the same as flipping arithmetic/logical shift type without the negation:
  // -(X >>u 31) -> (X >>s 31)
  // -(X >>s 31) -> (X >>u 31)
  if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
    ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
    if (ShiftAmt && ShiftAmt->getAPIntValue() == (BitWidth - 1)) {
      auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
      if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
        return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));
    }
  }

  // 0 - X --> 0 if the sub is NUW.
  if (N->getFlags().hasNoUnsignedWrap())
    return N0;

  if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) {
    // N1 is either 0 or the minimum signed value. If the sub is NSW, then
    // N1 must be 0 because negating the minimum signed value is undefined.
    if (N->getFlags().hasNoSignedWrap())
      return N0;

    // 0 - X --> X if X is 0 or the minimum signed value.
    return N1;
  }
}

// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
if (isAllOnesOrAllOnesSplat(N0))
  return DAG.getNode(ISD::XOR, DL, VT, N1, N0);

// fold (A - (0-B)) -> A+B
if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
  return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1));

// fold A-(A-B) -> B
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
  return N1.getOperand(1);

// fold (A+B)-A -> B
if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
  return N0.getOperand(1);

// fold (A+B)-B -> A
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
  return N0.getOperand(0);

// fold (A+C1)-C2 -> A+(C1-C2)
if (N0.getOpcode() == ISD::ADD &&
    isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
    isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
  SDValue NewC =
      DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0.getOperand(1), N1});
  assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3063, __PRETTY_FUNCTION__));
  return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
}

// fold C2-(A+C1) -> (C2-C1)-A
if (N1.getOpcode() == ISD::ADD) {
  SDValue N11 = N1.getOperand(1);
  if (isConstantOrConstantVector(N0, /* NoOpaques */ true) &&
      isConstantOrConstantVector(N11, /* NoOpaques */ true)) {
    SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N11});
    assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3073, __PRETTY_FUNCTION__));
    return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
  }
}

// fold (A-C1)-C2 -> A-(C1+C2)
if (N0.getOpcode() == ISD::SUB &&
    isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
    isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
  SDValue NewC =
      DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0.getOperand(1), N1});
  assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3084, __PRETTY_FUNCTION__));
  return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC);
}

// fold (c1-A)-c2 -> (c1-c2)-A
if (N0.getOpcode() == ISD::SUB &&
    isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
    isConstantOrConstantVector(N0.getOperand(0), /* NoOpaques */ true)) {
  SDValue NewC =
      DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0.getOperand(0), N1});
  assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3094, __PRETTY_FUNCTION__));
  return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1));
}

// fold ((A+(B+or-C))-B) -> A+or-C
if (N0.getOpcode() == ISD::ADD &&
    (N0.getOperand(1).getOpcode() == ISD::SUB ||
     N0.getOperand(1).getOpcode() == ISD::ADD) &&
    N0.getOperand(1).getOperand(0) == N1)
  return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0),
                     N0.getOperand(1).getOperand(1));

// fold ((A+(C+B))-B) -> A+C
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD &&
    N0.getOperand(1).getOperand(1) == N1)
  return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0),
                     N0.getOperand(1).getOperand(0));

// fold ((A-(B-C))-C) -> A-B
if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
    N0.getOperand(1).getOperand(1) == N1)
  return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
                     N0.getOperand(1).getOperand(0));

// fold (A-(B-C)) -> A+(C-B)
if (N1.getOpcode() == ISD::SUB && N1.hasOneUse())
  return DAG.getNode(ISD::ADD, DL, VT, N0,
                     DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1),
                                 N1.getOperand(0)));

// A - (A & B)  ->  A & (~B)
if (N1.getOpcode() == ISD::AND) {
  SDValue A = N1.getOperand(0);
  SDValue B = N1.getOperand(1);
  if (A != N0)
    std::swap(A, B);
  if (A == N0 &&
      (N1.hasOneUse() || isConstantOrConstantVector(B, /*NoOpaques=*/true))) {
    SDValue InvB =
        DAG.getNode(ISD::XOR, DL, VT, B, DAG.getAllOnesConstant(DL, VT));
    return DAG.getNode(ISD::AND, DL, VT, A, InvB);
  }
}

// fold (X - (-Y * Z)) -> (X + (Y * Z))
if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) {
  if (N1.getOperand(0).getOpcode() == ISD::SUB &&
      isNullOrNullSplat(N1.getOperand(0).getOperand(0))) {
    SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
                              N1.getOperand(0).getOperand(1),
                              N1.getOperand(1));
    return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
  }
  if (N1.getOperand(1).getOpcode() == ISD::SUB &&
      isNullOrNullSplat(N1.getOperand(1).getOperand(0))) {
    SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
                              N1.getOperand(0),
                              N1.getOperand(1).getOperand(1));
    return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
  }
}

// If either operand of a sub is undef, the result is undef
if (N0.isUndef())
  return N0;
if (N1.isUndef())
  return N1;

if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
  return V;

if (SDValue V = foldAddSubOfSignBit(N, DAG))
  return V;

if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
  return V;

// (x - y) - 1  ->  add (xor y, -1), x
if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) {
  SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
                            DAG.getAllOnesConstant(DL, VT));
  return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
}

// Look for:
//   sub y, (xor x, -1)
// And if the target does not like this form then turn into:
//   add (add x, y), 1
if (TLI.preferIncOfAddToSubOfNot(VT) && N1.hasOneUse() && isBitwiseNot(N1)) {
  SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(0));
  return DAG.getNode(ISD::ADD, DL, VT, Add, DAG.getConstant(1, DL, VT));
}

// Hoist one-use addition by non-opaque constant:
//   (x + C) - y  ->  (x - y) + C
if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD &&
    isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
  SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
  return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
}
// y - (x + C)  ->  (y - x) - C
if (N1.hasOneUse() && N1.getOpcode() == ISD::ADD &&
    isConstantOrConstantVector(N1.getOperand(1), /*NoOpaques=*/true)) {
  SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
  return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1));
}
// (x - C) - y  ->  (x - y) - C
// This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
    isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
  SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
  return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
}
// (C - x) - y  ->  C - (x + y)
if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
    isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
  SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1);
  return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
}

// If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
// rather than 'sub 0/1' (the sext should get folded).
// sub X, (zext i1 Y) --> add X, (sext i1 Y)
if (N1.getOpcode() == ISD::ZERO_EXTEND &&
    N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
    TLI.getBooleanContents(VT) ==
        TargetLowering::ZeroOrNegativeOneBooleanContent) {
  SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
  return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
}

// fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X)
if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
  if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
    SDValue X0 = N0.getOperand(0), X1 = N0.getOperand(1);
    SDValue S0 = N1.getOperand(0);
    if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) {
      unsigned OpSizeInBits = VT.getScalarSizeInBits();
      if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1)))
        if (C->getAPIntValue() == (OpSizeInBits - 1))
          return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0);
    }
  }
}

// If the relocation model supports it, consider symbol offsets.
if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
  if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
    // fold (sub Sym, c) -> Sym-c
    if (N1C && GA->getOpcode() == ISD::GlobalAddress)
      return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
                                  GA->getOffset() -
                                      (uint64_t)N1C->getSExtValue());
    // fold (sub Sym+c1, Sym+c2) -> c1-c2
    if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
      if (GA->getGlobal() == GB->getGlobal())
        return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
                               DL, VT);
  }

// sub X, (sextinreg Y i1) -> add X, (and Y 1)
if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
  VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
  if (TN->getVT() == MVT::i1) {
    SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
                               DAG.getConstant(1, DL, VT));
    return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
  }
}

// canonicalize (sub X, (vscale * C)) to (add X,  (vscale * -C))
if (N1.getOpcode() == ISD::VSCALE) {
  APInt IntVal = N1.getConstantOperandAPInt(0);
  return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
}

// Prefer an add for more folding potential and possibly better codegen:
// sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1)
if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
  SDValue ShAmt = N1.getOperand(1);
  ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
  if (ShAmtC &&
      ShAmtC->getAPIntValue() == (N1.getScalarValueSizeInBits() - 1)) {
    SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
    return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
  }
}

if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) {
  // (sub Carry, X)  ->  (addcarry (sub 0, X), 0, Carry)
  if (SDValue Carry = getAsCarry(TLI, N0)) {
    SDValue X = N1;
    SDValue Zero = DAG.getConstant(0, DL, VT);
    SDValue NegX = DAG.getNode(ISD::SUB, DL, VT, Zero, X);
    return DAG.getNode(ISD::ADDCARRY, DL,
                       DAG.getVTList(VT, Carry.getValueType()), NegX, Zero,
                       Carry);
  }
}

return SDValue();
3295}

3297SDValue DAGCombiner::visitSUBSAT(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
SDLoc DL(N);

// fold vector ops
if (VT.isVector()) {
  // TODO SimplifyVBinOp

  // fold (sub_sat x, 0) -> x, vector edition
  if (ISD::isBuildVectorAllZeros(N1.getNode()))
    return N0;
}

// fold (sub_sat x, undef) -> 0
if (N0.isUndef() || N1.isUndef())
  return DAG.getConstant(0, DL, VT);

// fold (sub_sat x, x) -> 0
if (N0 == N1)
  return DAG.getConstant(0, DL, VT);

// fold (sub_sat c1, c2) -> c3
if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1}))
  return C;

// fold (sub_sat x, 0) -> x
if (isNullConstant(N1))
  return N0;

return SDValue();
3329}

3331SDValue DAGCombiner::visitSUBC(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
SDLoc DL(N);

// If the flag result is dead, turn this into an SUB.
if (!N->hasAnyUseOfValue(1))
  return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
                   DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));

// fold (subc x, x) -> 0 + no borrow
if (N0 == N1)
  return CombineTo(N, DAG.getConstant(0, DL, VT),
                   DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));

// fold (subc x, 0) -> x + no borrow
if (isNullConstant(N1))
  return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));

// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
if (isAllOnesConstant(N0))
  return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
                   DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));

return SDValue();
3357}

3359SDValue DAGCombiner::visitSUBO(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
bool IsSigned = (ISD::SSUBO == N->getOpcode());

EVT CarryVT = N->getValueType(1);
SDLoc DL(N);

// If the flag result is dead, turn this into an SUB.
if (!N->hasAnyUseOfValue(1))
  return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
                   DAG.getUNDEF(CarryVT));

// fold (subo x, x) -> 0 + no borrow
if (N0 == N1)
  return CombineTo(N, DAG.getConstant(0, DL, VT),
                   DAG.getConstant(0, DL, CarryVT));

ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);

// fold (subox, c) -> (addo x, -c)
if (IsSigned && N1C && !N1C->getAPIntValue().isMinSignedValue()) {
  return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0,
                     DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
}

// fold (subo x, 0) -> x + no borrow
if (isNullOrNullSplat(N1))
  return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));

// Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow
if (!IsSigned && isAllOnesOrAllOnesSplat(N0))
  return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
                   DAG.getConstant(0, DL, CarryVT));

return SDValue();
3396}

3398SDValue DAGCombiner::visitSUBE(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue CarryIn = N->getOperand(2);

// fold (sube x, y, false) -> (subc x, y)
if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
  return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);

return SDValue();
3408}

3410SDValue DAGCombiner::visitSUBCARRY(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue CarryIn = N->getOperand(2);

// fold (subcarry x, y, false) -> (usubo x, y)
if (isNullConstant(CarryIn)) {
  if (!LegalOperations ||
      TLI.isOperationLegalOrCustom(ISD::USUBO, N->getValueType(0)))
    return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
}

return SDValue();
3423}

3425// Notice that "mulfix" can be any of SMULFIX, SMULFIXSAT, UMULFIX and
3426// UMULFIXSAT here.
3427SDValue DAGCombiner::visitMULFIX(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
SDValue Scale = N->getOperand(2);
EVT VT = N0.getValueType();

// fold (mulfix x, undef, scale) -> 0
if (N0.isUndef() || N1.isUndef())
  return DAG.getConstant(0, SDLoc(N), VT);

// Canonicalize constant to RHS (vector doesn't have to splat)
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
   !DAG.isConstantIntBuildVectorOrConstantInt(N1))
  return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale);

// fold (mulfix x, 0, scale) -> 0
if (isNullConstant(N1))
  return DAG.getConstant(0, SDLoc(N), VT);

return SDValue();
3447}

3449SDValue DAGCombiner::visitMUL(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();

// fold (mul x, undef) -> 0
if (N0.isUndef() || N1.isUndef())
  return DAG.getConstant(0, SDLoc(N), VT);

bool N1IsConst = false;
bool N1IsOpaqueConst = false;
APInt ConstValue1;

// fold vector ops
if (VT.isVector()) {
  if (SDValue FoldedVOp = SimplifyVBinOp(N))
    return FoldedVOp;

  N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1);
  assert((!N1IsConst ||(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3470, __PRETTY_FUNCTION__))
          ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) &&(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3470, __PRETTY_FUNCTION__))
         "Splat APInt should be element width")(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3470, __PRETTY_FUNCTION__));
} else {
  N1IsConst = isa<ConstantSDNode>(N1);
  if (N1IsConst) {
    ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
    N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
  }
}

// fold (mul c1, c2) -> c1*c2
if (SDValue C = DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT, {N0, N1}))
  return C;

// canonicalize constant to RHS (vector doesn't have to splat)
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
   !DAG.isConstantIntBuildVectorOrConstantInt(N1))
  return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);

// fold (mul x, 0) -> 0
if (N1IsConst && ConstValue1.isNullValue())
  return N1;

// fold (mul x, 1) -> x
if (N1IsConst && ConstValue1.isOneValue())
  return N0;

if (SDValue NewSel = foldBinOpIntoSelect(N))
  return NewSel;

// fold (mul x, -1) -> 0-x
if (N1IsConst && ConstValue1.isAllOnesValue()) {
  SDLoc DL(N);
  return DAG.getNode(ISD::SUB, DL, VT,
                     DAG.getConstant(0, DL, VT), N0);
}

// fold (mul x, (1 << c)) -> x << c
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
    DAG.isKnownToBeAPowerOfTwo(N1) &&
    (!VT.isVector() || Level <= AfterLegalizeVectorOps)) {
  SDLoc DL(N);
  SDValue LogBase2 = BuildLogBase2(N1, DL);
  EVT ShiftVT = getShiftAmountTy(N0.getValueType());
  SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
  return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
}

// fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2()) {
  unsigned Log2Val = (-ConstValue1).logBase2();
  SDLoc DL(N);
  // FIXME: If the input is something that is easily negated (e.g. a
  // single-use add), we should put the negate there.
  return DAG.getNode(ISD::SUB, DL, VT,
                     DAG.getConstant(0, DL, VT),
                     DAG.getNode(ISD::SHL, DL, VT, N0,
                          DAG.getConstant(Log2Val, DL,
                                    getShiftAmountTy(N0.getValueType()))));
}

// Try to transform multiply-by-(power-of-2 +/- 1) into shift and add/sub.
// mul x, (2^N + 1) --> add (shl x, N), x
// mul x, (2^N - 1) --> sub (shl x, N), x
// Examples: x * 33 --> (x << 5) + x
//           x * 15 --> (x << 4) - x
//           x * -33 --> -((x << 5) + x)
//           x * -15 --> -((x << 4) - x) ; this reduces --> x - (x << 4)
if (N1IsConst && TLI.decomposeMulByConstant(*DAG.getContext(), VT, N1)) {
  // TODO: We could handle more general decomposition of any constant by
  //       having the target set a limit on number of ops and making a
  //       callback to determine that sequence (similar to sqrt expansion).
  unsigned MathOp = ISD::DELETED_NODE;
  APInt MulC = ConstValue1.abs();
  if ((MulC - 1).isPowerOf2())
    MathOp = ISD::ADD;
  else if ((MulC + 1).isPowerOf2())
    MathOp = ISD::SUB;

  if (MathOp != ISD::DELETED_NODE) {
    unsigned ShAmt =
        MathOp == ISD::ADD ? (MulC - 1).logBase2() : (MulC + 1).logBase2();
    assert(ShAmt < VT.getScalarSizeInBits() &&((ShAmt < VT.getScalarSizeInBits() && "multiply-by-constant generated out of bounds shift"
) ? static_cast<void> (0) : __assert_fail ("ShAmt < VT.getScalarSizeInBits() && \"multiply-by-constant generated out of bounds shift\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3552, __PRETTY_FUNCTION__))
           "multiply-by-constant generated out of bounds shift")((ShAmt < VT.getScalarSizeInBits() && "multiply-by-constant generated out of bounds shift"
) ? static_cast<void> (0) : __assert_fail ("ShAmt < VT.getScalarSizeInBits() && \"multiply-by-constant generated out of bounds shift\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3552, __PRETTY_FUNCTION__));
    SDLoc DL(N);
    SDValue Shl =
        DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT));
    SDValue R = DAG.getNode(MathOp, DL, VT, Shl, N0);
    if (ConstValue1.isNegative())
      R = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), R);
    return R;
  }
}

// (mul (shl X, c1), c2) -> (mul X, c2 << c1)
if (N0.getOpcode() == ISD::SHL &&
    isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
    isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
  SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
  if (isConstantOrConstantVector(C3))
    return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
}

// Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
// use.
{
  SDValue Sh(nullptr, 0), Y(nullptr, 0);

  // Check for both (mul (shl X, C), Y)  and  (mul Y, (shl X, C)).
  if (N0.getOpcode() == ISD::SHL &&
      isConstantOrConstantVector(N0.getOperand(1)) &&
      N0.getNode()->hasOneUse()) {
    Sh = N0; Y = N1;
  } else if (N1.getOpcode() == ISD::SHL &&
             isConstantOrConstantVector(N1.getOperand(1)) &&
             N1.getNode()->hasOneUse()) {
    Sh = N1; Y = N0;
  }

  if (Sh.getNode()) {
    SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, Sh.getOperand(0), Y);
    return DAG.getNode(ISD::SHL, SDLoc(N), VT, Mul, Sh.getOperand(1));
  }
}

// fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
if (DAG.isConstantIntBuildVectorOrConstantInt(N1) &&
    N0.getOpcode() == ISD::ADD &&
    DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
    isMulAddWithConstProfitable(N, N0, N1))
    return DAG.getNode(ISD::ADD, SDLoc(N), VT,
                       DAG.getNode(ISD::MUL, SDLoc(N0), VT,
                                   N0.getOperand(0), N1),
                       DAG.getNode(ISD::MUL, SDLoc(N1), VT,
                                   N0.getOperand(1), N1));

// Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)).
if (N0.getOpcode() == ISD::VSCALE)
  if (ConstantSDNode *NC1 = isConstOrConstSplat(N1)) {
    APInt C0 = N0.getConstantOperandAPInt(0);
    APInt C1 = NC1->getAPIntValue();
    return DAG.getVScale(SDLoc(N), VT, C0 * C1);
  }

// reassociate mul
if (SDValue RMUL = reassociateOps(ISD::MUL, SDLoc(N), N0, N1, N->getFlags()))
  return RMUL;

return SDValue();
3618}

3620/// Return true if divmod libcall is available.
3621static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
                                   const TargetLowering &TLI) {
RTLIB::Libcall LC;
EVT NodeType = Node->getValueType(0);
if (!NodeType.isSimple())
  return false;
switch (NodeType.getSimpleVT().SimpleTy) {
default: return false; // No libcall for vector types.
case MVT::i8:   LC= isSigned ? RTLIB::SDIVREM_I8  : RTLIB::UDIVREM_I8;  break;
case MVT::i16:  LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
case MVT::i32:  LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
case MVT::i64:  LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
}

return TLI.getLibcallName(LC) != nullptr;
3637}

3639/// Issue divrem if both quotient and remainder are needed.
3640SDValue DAGCombiner::useDivRem(SDNode *Node) {
if (Node->use_empty())
  return SDValue(); // This is a dead node, leave it alone.

unsigned Opcode = Node->getOpcode();
bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;

// DivMod lib calls can still work on non-legal types if using lib-calls.
EVT VT = Node->getValueType(0);
if (VT.isVector() || !VT.isInteger())
  return SDValue();

if (!TLI.isTypeLegal(VT) && !TLI.isOperationCustom(DivRemOpc, VT))
  return SDValue();

// If DIVREM is going to get expanded into a libcall,
// but there is no libcall available, then don't combine.
if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) &&
    !isDivRemLibcallAvailable(Node, isSigned, TLI))
  return SDValue();

// If div is legal, it's better to do the normal expansion
unsigned OtherOpcode = 0;
if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
  OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
  if (TLI.isOperationLegalOrCustom(Opcode, VT))
    return SDValue();
} else {
  OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
  if (TLI.isOperationLegalOrCustom(OtherOpcode, VT))
    return SDValue();
}

SDValue Op0 = Node->getOperand(0);
SDValue Op1 = Node->getOperand(1);
SDValue combined;
for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
       UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
  SDNode *User = *UI;
  if (User == Node || User->getOpcode() == ISD::DELETED_NODE ||
      User->use_empty())
    continue;
  // Convert the other matching node(s), too;
  // otherwise, the DIVREM may get target-legalized into something
  // target-specific that we won't be able to recognize.
  unsigned UserOpc = User->getOpcode();
  if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) &&
      User->getOperand(0) == Op0 &&
      User->getOperand(1) == Op1) {
    if (!combined) {
      if (UserOpc == OtherOpcode) {
        SDVTList VTs = DAG.getVTList(VT, VT);
        combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1);
      } else if (UserOpc == DivRemOpc) {
        combined = SDValue(User, 0);
      } else {
        assert(UserOpc == Opcode)((UserOpc == Opcode) ? static_cast<void> (0) : __assert_fail
 ("UserOpc == Opcode", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3697, __PRETTY_FUNCTION__));
        continue;
      }
    }
    if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
      CombineTo(User, combined);
    else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
      CombineTo(User, combined.getValue(1));
  }
}
return combined;
3708}

3710static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N->getValueType(0);
SDLoc DL(N);

unsigned Opc = N->getOpcode();
bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc);
ConstantSDNode *N1C = isConstOrConstSplat(N1);

// X / undef -> undef
// X % undef -> undef
// X / 0 -> undef
// X % 0 -> undef
// NOTE: This includes vectors where any divisor element is zero/undef.
if (DAG.isUndef(Opc, {N0, N1}))
  return DAG.getUNDEF(VT);

// undef / X -> 0
// undef % X -> 0
if (N0.isUndef())
  return DAG.getConstant(0, DL, VT);

// 0 / X -> 0
// 0 % X -> 0
ConstantSDNode *N0C = isConstOrConstSplat(N0);
if (N0C && N0C->isNullValue())
  return N0;

// X / X -> 1
// X % X -> 0
if (N0 == N1)
  return DAG.getConstant(IsDiv ? 1 : 0, DL, VT);

// X / 1 -> X
// X % 1 -> 0
// If this is a boolean op (single-bit element type), we can't have
// division-by-zero or remainder-by-zero, so assume the divisor is 1.
// TODO: Similarly, if we're zero-extending a boolean divisor, then assume
// it's a 1.
if ((N1C && N1C->isOne()) || (VT.getScalarType() == MVT::i1))
  return IsDiv ? N0 : DAG.getConstant(0, DL, VT);

return SDValue();
3754}

3756SDValue DAGCombiner::visitSDIV(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N->getValueType(0);
EVT CCVT = getSetCCResultType(VT);

// fold vector ops
if (VT.isVector())
  if (SDValue FoldedVOp = SimplifyVBinOp(N))
    return FoldedVOp;

SDLoc DL(N);

// fold (sdiv c1, c2) -> c1/c2
ConstantSDNode *N1C = isConstOrConstSplat(N1);
if (SDValue C = DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, {N0, N1}))
  return C;

// fold (sdiv X, -1) -> 0-X
if (N1C && N1C->isAllOnesValue())
  return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);

// fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0)
if (N1C && N1C->getAPIntValue().isMinSignedValue())
  return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
                       DAG.getConstant(1, DL, VT),
                       DAG.getConstant(0, DL, VT));

if (SDValue V = simplifyDivRem(N, DAG))
  return V;

if (SDValue NewSel = foldBinOpIntoSelect(N))
  return NewSel;

// If we know the sign bits of both operands are zero, strength reduce to a
// udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
  return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);

if (SDValue V = visitSDIVLike(N0, N1, N)) {
  // If the corresponding remainder node exists, update its users with
  // (Dividend - (Quotient * Divisor).
  if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(),
                                            { N0, N1 })) {
    SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
    SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
    AddToWorklist(Mul.getNode());
    AddToWorklist(Sub.getNode());
    CombineTo(RemNode, Sub);
  }
  return V;
}

// sdiv, srem -> sdivrem
// If the divisor is constant, then return DIVREM only if isIntDivCheap() is
// true.  Otherwise, we break the simplification logic in visitREM().
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
  if (SDValue DivRem = useDivRem(N))
      return DivRem;

return SDValue();
3818}

3820SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
SDLoc DL(N);
EVT VT = N->getValueType(0);
EVT CCVT = getSetCCResultType(VT);
unsigned BitWidth = VT.getScalarSizeInBits();

// Helper for determining whether a value is a power-2 constant scalar or a
// vector of such elements.
auto IsPowerOfTwo = [](ConstantSDNode *C) {
  if (C->isNullValue() || C->isOpaque())
    return false;
  if (C->getAPIntValue().isPowerOf2())
    return true;
  if ((-C->getAPIntValue()).isPowerOf2())
    return true;
  return false;
};

// fold (sdiv X, pow2) -> simple ops after legalize
// FIXME: We check for the exact bit here because the generic lowering gives
// better results in that case. The target-specific lowering should learn how
// to handle exact sdivs efficiently.
if (!N->getFlags().hasExact() && ISD::matchUnaryPredicate(N1, IsPowerOfTwo)) {
  // Target-specific implementation of sdiv x, pow2.
  if (SDValue Res = BuildSDIVPow2(N))
    return Res;

  // Create constants that are functions of the shift amount value.
  EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
  SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy);
  SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1);
  C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy);
  SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1);
  if (!isConstantOrConstantVector(Inexact))
    return SDValue();

  // Splat the sign bit into the register
  SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
                             DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy));
  AddToWorklist(Sign.getNode());

  // Add (N0 < 0) ? abs2 - 1 : 0;
  SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
  AddToWorklist(Srl.getNode());
  SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl);
  AddToWorklist(Add.getNode());
  SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);
  AddToWorklist(Sra.getNode());

  // Special case: (sdiv X, 1) -> X
  // Special Case: (sdiv X, -1) -> 0-X
  SDValue One = DAG.getConstant(1, DL, VT);
  SDValue AllOnes = DAG.getAllOnesConstant(DL, VT);
  SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ);
  SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ);
  SDValue IsOneOrAllOnes = DAG.getNode(ISD::OR, DL, CCVT, IsOne, IsAllOnes);
  Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra);

  // If dividing by a positive value, we're done. Otherwise, the result must
  // be negated.
  SDValue Zero = DAG.getConstant(0, DL, VT);
  SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra);

  // FIXME: Use SELECT_CC once we improve SELECT_CC constant-folding.
  SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT);
  SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra);
  return Res;
}

// If integer divide is expensive and we satisfy the requirements, emit an
// alternate sequence.  Targets may check function attributes for size/speed
// trade-offs.
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
if (isConstantOrConstantVector(N1) &&
    !TLI.isIntDivCheap(N->getValueType(0), Attr))
  if (SDValue Op = BuildSDIV(N))
    return Op;

return SDValue();
3899}

3901SDValue DAGCombiner::visitUDIV(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N->getValueType(0);
EVT CCVT = getSetCCResultType(VT);

// fold vector ops
if (VT.isVector())
  if (SDValue FoldedVOp = SimplifyVBinOp(N))
    return FoldedVOp;

SDLoc DL(N);

// fold (udiv c1, c2) -> c1/c2
ConstantSDNode *N1C = isConstOrConstSplat(N1);
if (SDValue C = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT, {N0, N1}))
  return C;

// fold (udiv X, -1) -> select(X == -1, 1, 0)
if (N1C && N1C->getAPIntValue().isAllOnesValue())
  return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
                       DAG.getConstant(1, DL, VT),
                       DAG.getConstant(0, DL, VT));

if (SDValue V = simplifyDivRem(N, DAG))
  return V;

if (SDValue NewSel = foldBinOpIntoSelect(N))
  return NewSel;

if (SDValue V = visitUDIVLike(N0, N1, N)) {
  // If the corresponding remainder node exists, update its users with
  // (Dividend - (Quotient * Divisor).
  if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(),
                                            { N0, N1 })) {
    SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
    SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
    AddToWorklist(Mul.getNode());
    AddToWorklist(Sub.getNode());
    CombineTo(RemNode, Sub);
  }
  return V;
}

// sdiv, srem -> sdivrem
// If the divisor is constant, then return DIVREM only if isIntDivCheap() is
// true.  Otherwise, we break the simplification logic in visitREM().
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
  if (SDValue DivRem = useDivRem(N))
      return DivRem;

return SDValue();
3954}

3956SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) {
SDLoc DL(N);
EVT VT = N->getValueType(0);

// fold (udiv x, (1 << c)) -> x >>u c
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
    DAG.isKnownToBeAPowerOfTwo(N1)) {
  SDValue LogBase2 = BuildLogBase2(N1, DL);
  AddToWorklist(LogBase2.getNode());

  EVT ShiftVT = getShiftAmountTy(N0.getValueType());
  SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
  AddToWorklist(Trunc.getNode());
  return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
}

// fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
if (N1.getOpcode() == ISD::SHL) {
  SDValue N10 = N1.getOperand(0);
  if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) &&
      DAG.isKnownToBeAPowerOfTwo(N10)) {
    SDValue LogBase2 = BuildLogBase2(N10, DL);
    AddToWorklist(LogBase2.getNode());

    EVT ADDVT = N1.getOperand(1).getValueType();
    SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT);
    AddToWorklist(Trunc.getNode());
    SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc);
    AddToWorklist(Add.getNode());
    return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
  }
}

// fold (udiv x, c) -> alternate
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
if (isConstantOrConstantVector(N1) &&
    !TLI.isIntDivCheap(N->getValueType(0), Attr))
  if (SDValue Op = BuildUDIV(N))
    return Op;

return SDValue();
3997}

3999// handles ISD::SREM and ISD::UREM
4000SDValue DAGCombiner::visitREM(SDNode *N) {
unsigned Opcode = N->getOpcode();
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N->getValueType(0);
EVT CCVT = getSetCCResultType(VT);

bool isSigned = (Opcode == ISD::SREM);
SDLoc DL(N);

// fold (rem c1, c2) -> c1%c2
ConstantSDNode *N1C = isConstOrConstSplat(N1);
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
  return C;

// fold (urem X, -1) -> select(X == -1, 0, x)
if (!isSigned && N1C && N1C->getAPIntValue().isAllOnesValue())
  return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
                       DAG.getConstant(0, DL, VT), N0);

if (SDValue V = simplifyDivRem(N, DAG))
  return V;

if (SDValue NewSel = foldBinOpIntoSelect(N))
  return NewSel;

if (isSigned) {
  // If we know the sign bits of both operands are zero, strength reduce to a
  // urem instead.  Handles (X & 0x0FFFFFFF) %s 16 -> X&15
  if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
    return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
} else {
  SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
  if (DAG.isKnownToBeAPowerOfTwo(N1)) {
    // fold (urem x, pow2) -> (and x, pow2-1)
    SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
    AddToWorklist(Add.getNode());
    return DAG.getNode(ISD::AND, DL, VT, N0, Add);
  }
  if (N1.getOpcode() == ISD::SHL &&
      DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) {
    // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
    SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
    AddToWorklist(Add.getNode());
    return DAG.getNode(ISD::AND, DL, VT, N0, Add);
  }
}

AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();

// If X/C can be simplified by the division-by-constant logic, lower
// X%C to the equivalent of X-X/C*C.
// Reuse the SDIVLike/UDIVLike combines - to avoid mangling nodes, the
// speculative DIV must not cause a DIVREM conversion.  We guard against this
// by skipping the simplification if isIntDivCheap().  When div is not cheap,
// combine will not return a DIVREM.  Regardless, checking cheapness here
// makes sense since the simplification results in fatter code.
if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) {
  SDValue OptimizedDiv =
      isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N);
  if (OptimizedDiv.getNode()) {
    // If the equivalent Div node also exists, update its users.
    unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
    if (SDNode *DivNode = DAG.getNodeIfExists(DivOpcode, N->getVTList(),
                                              { N0, N1 }))
      CombineTo(DivNode, OptimizedDiv);
    SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1);
    SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
    AddToWorklist(OptimizedDiv.getNode());
    AddToWorklist(Mul.getNode());
    return Sub;
  }
}

// sdiv, srem -> sdivrem
if (SDValue DivRem = useDivRem(N))
  return DivRem.getValue(1);

return SDValue();
4079}

4081SDValue DAGCombiner::visitMULHS(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N->getValueType(0);
SDLoc DL(N);

if (VT.isVector()) {
  // fold (mulhs x, 0) -> 0
  // do not return N0/N1, because undef node may exist.
  if (ISD::isBuildVectorAllZeros(N0.getNode()) ||
      ISD::isBuildVectorAllZeros(N1.getNode()))
    return DAG.getConstant(0, DL, VT);
}

// fold (mulhs x, 0) -> 0
if (isNullConstant(N1))
  return N1;
// fold (mulhs x, 1) -> (sra x, size(x)-1)
if (isOneConstant(N1))
  return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
                     DAG.getConstant(N0.getScalarValueSizeInBits() - 1, DL,
                                     getShiftAmountTy(N0.getValueType())));

// fold (mulhs x, undef) -> 0
if (N0.isUndef() || N1.isUndef())
  return DAG.getConstant(0, DL, VT);

// If the type twice as wide is legal, transform the mulhs to a wider multiply
// plus a shift.
if (VT.isSimple() && !VT.isVector()) {
  MVT Simple = VT.getSimpleVT();
  unsigned SimpleSize = Simple.getSizeInBits();
  EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
  if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
    N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
    N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
    N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
    N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
          DAG.getConstant(SimpleSize, DL,
                          getShiftAmountTy(N1.getValueType())));
    return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
  }
}

return SDValue();
4126}

4128SDValue DAGCombiner::visitMULHU(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N->getValueType(0);
SDLoc DL(N);

if (VT.isVector()) {
  // fold (mulhu x, 0) -> 0
  // do not return N0/N1, because undef node may exist.
  if (ISD::isBuildVectorAllZeros(N0.getNode()) ||
      ISD::isBuildVectorAllZeros(N1.getNode()))
    return DAG.getConstant(0, DL, VT);
}

// fold (mulhu x, 0) -> 0
if (isNullConstant(N1))
  return N1;
// fold (mulhu x, 1) -> 0
if (isOneConstant(N1))
  return DAG.getConstant(0, DL, N0.getValueType());
// fold (mulhu x, undef) -> 0
if (N0.isUndef() || N1.isUndef())
  return DAG.getConstant(0, DL, VT);

// fold (mulhu x, (1 << c)) -> x >> (bitwidth - c)
if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
    DAG.isKnownToBeAPowerOfTwo(N1) && hasOperation(ISD::SRL, VT)) {
  unsigned NumEltBits = VT.getScalarSizeInBits();
  SDValue LogBase2 = BuildLogBase2(N1, DL);
  SDValue SRLAmt = DAG.getNode(
      ISD::SUB, DL, VT, DAG.getConstant(NumEltBits, DL, VT), LogBase2);
  EVT ShiftVT = getShiftAmountTy(N0.getValueType());
  SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT);
  return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
}

// If the type twice as wide is legal, transform the mulhu to a wider multiply
// plus a shift.
if (VT.isSimple() && !VT.isVector()) {
  MVT Simple = VT.getSimpleVT();
  unsigned SimpleSize = Simple.getSizeInBits();
  EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
  if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
    N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
    N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
    N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
    N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
          DAG.getConstant(SimpleSize, DL,
                          getShiftAmountTy(N1.getValueType())));
    return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
  }
}

return SDValue();
4182}

4184/// Perform optimizations common to nodes that compute two values. LoOp and HiOp
4185/// give the opcodes for the two computations that are being performed. Return
4186/// true if a simplification was made.
4187SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
                                              unsigned HiOp) {
// If the high half is not needed, just compute the low half.
bool HiExists = N->hasAnyUseOfValue(1);
if (!HiExists && (!LegalOperations ||
                  TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
  SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
  return CombineTo(N, Res, Res);
}

// If the low half is not needed, just compute the high half.
bool LoExists = N->hasAnyUseOfValue(0);
if (!LoExists && (!LegalOperations ||
                  TLI.isOperationLegalOrCustom(HiOp, N->getValueType(1)))) {
  SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
  return CombineTo(N, Res, Res);
}

// If both halves are used, return as it is.
if (LoExists && HiExists)
  return SDValue();

// If the two computed results can be simplified separately, separate them.
if (LoExists) {
  SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
  AddToWorklist(Lo.getNode());
  SDValue LoOpt = combine(Lo.getNode());
  if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
      (!LegalOperations ||
       TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType())))
    return CombineTo(N, LoOpt, LoOpt);
}

if (HiExists) {
  SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
  AddToWorklist(Hi.getNode());
  SDValue HiOpt = combine(Hi.getNode());
  if (HiOpt.getNode() && HiOpt != Hi &&
      (!LegalOperations ||
       TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType())))
    return CombineTo(N, HiOpt, HiOpt);
}

return SDValue();
4231}

4233SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
  return Res;

EVT VT = N->getValueType(0);
SDLoc DL(N);

// If the type is twice as wide is legal, transform the mulhu to a wider
// multiply plus a shift.
if (VT.isSimple() && !VT.isVector()) {
  MVT Simple = VT.getSimpleVT();
  unsigned SimpleSize = Simple.getSizeInBits();
  EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
  if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
    SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
    SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
    Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
    // Compute the high part as N1.
    Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
          DAG.getConstant(SimpleSize, DL,
                          getShiftAmountTy(Lo.getValueType())));
    Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
    // Compute the low part as N0.
    Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
    return CombineTo(N, Lo, Hi);
  }
}

return SDValue();
4262}

4264SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
  return Res;

EVT VT = N->getValueType(0);
SDLoc DL(N);

// (umul_lohi N0, 0) -> (0, 0)
if (isNullConstant(N->getOperand(1))) {
  SDValue Zero = DAG.getConstant(0, DL, VT);
  return CombineTo(N, Zero, Zero);
}

// (umul_lohi N0, 1) -> (N0, 0)
if (isOneConstant(N->getOperand(1))) {
  SDValue Zero = DAG.getConstant(0, DL, VT);
  return CombineTo(N, N->getOperand(0), Zero);
}

// If the type is twice as wide is legal, transform the mulhu to a wider
// multiply plus a shift.
if (VT.isSimple() && !VT.isVector()) {
  MVT Simple = VT.getSimpleVT();
  unsigned SimpleSize = Simple.getSizeInBits();
  EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
  if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
    SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
    SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
    Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
    // Compute the high part as N1.
    Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
          DAG.getConstant(SimpleSize, DL,
                          getShiftAmountTy(Lo.getValueType())));
    Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
    // Compute the low part as N0.
    Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
    return CombineTo(N, Lo, Hi);
  }
}

return SDValue();
4305}

4307SDValue DAGCombiner::visitMULO(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
bool IsSigned = (ISD::SMULO == N->getOpcode());

EVT CarryVT = N->getValueType(1);
SDLoc DL(N);

// canonicalize constant to RHS.
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
    !DAG.isConstantIntBuildVectorOrConstantInt(N1))
  return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);

// fold (mulo x, 0) -> 0 + no carry out
if (isNullOrNullSplat(N1))
  return CombineTo(N, DAG.getConstant(0, DL, VT),
                   DAG.getConstant(0, DL, CarryVT));

// (mulo x, 2) -> (addo x, x)
if (ConstantSDNode *C2 = isConstOrConstSplat(N1))
  if (C2->getAPIntValue() == 2)
    return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL,
                       N->getVTList(), N0, N0);

return SDValue();
4333}

4335SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N0.getValueType();
unsigned Opcode = N->getOpcode();

// fold vector ops
if (VT.isVector())
  if (SDValue FoldedVOp = SimplifyVBinOp(N))
    return FoldedVOp;

// fold operation with constant operands.
if (SDValue C = DAG.FoldConstantArithmetic(Opcode, SDLoc(N), VT, {N0, N1}))
  return C;

// canonicalize constant to RHS
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
    !DAG.isConstantIntBuildVectorOrConstantInt(N1))
  return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);

// Is sign bits are zero, flip between UMIN/UMAX and SMIN/SMAX.
// Only do this if the current op isn't legal and the flipped is.
if (!TLI.isOperationLegal(Opcode, VT) &&
    (N0.isUndef() || DAG.SignBitIsZero(N0)) &&
    (N1.isUndef() || DAG.SignBitIsZero(N1))) {
  unsigned AltOpcode;
  switch (Opcode) {
  case ISD::SMIN: AltOpcode = ISD::UMIN; break;
  case ISD::SMAX: AltOpcode = ISD::UMAX; break;
  case ISD::UMIN: AltOpcode = ISD::SMIN; break;
  case ISD::UMAX: AltOpcode = ISD::SMAX; break;
  default: llvm_unreachable("Unknown MINMAX opcode")::llvm::llvm_unreachable_internal("Unknown MINMAX opcode", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4366);
  }
  if (TLI.isOperationLegal(AltOpcode, VT))
    return DAG.getNode(AltOpcode, SDLoc(N), VT, N0, N1);
}

return SDValue();
4373}

4375/// If this is a bitwise logic instruction and both operands have the same
4376/// opcode, try to sink the other opcode after the logic instruction.
4377SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
EVT VT = N0.getValueType();
unsigned LogicOpcode = N->getOpcode();
unsigned HandOpcode = N0.getOpcode();
assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
 == ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4383, __PRETTY_FUNCTION__))
        LogicOpcode == ISD::XOR) && "Expected logic opcode")(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
 == ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4383, __PRETTY_FUNCTION__));
assert(HandOpcode == N1.getOpcode() && "Bad input!")((HandOpcode == N1.getOpcode() && "Bad input!") ? static_cast
<void> (0) : __assert_fail ("HandOpcode == N1.getOpcode() && \"Bad input!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4384, __PRETTY_FUNCTION__));

// Bail early if none of these transforms apply.
if (N0.getNumOperands() == 0)
  return SDValue();

// FIXME: We should check number of uses of the operands to not increase
//        the instruction count for all transforms.

// Handle size-changing casts.
SDValue X = N0.getOperand(0);
SDValue Y = N1.getOperand(0);
EVT XVT = X.getValueType();
SDLoc DL(N);
if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND ||
    HandOpcode == ISD::SIGN_EXTEND) {
  // If both operands have other uses, this transform would create extra
  // instructions without eliminating anything.
  if (!N0.hasOneUse() && !N1.hasOneUse())
    return SDValue();
  // We need matching integer source types.
  if (XVT != Y.getValueType())
    return SDValue();
  // Don't create an illegal op during or after legalization. Don't ever
  // create an unsupported vector op.
  if ((VT.isVector() || LegalOperations) &&
      !TLI.isOperationLegalOrCustom(LogicOpcode, XVT))
    return SDValue();
  // Avoid infinite looping with PromoteIntBinOp.
  // TODO: Should we apply desirable/legal constraints to all opcodes?
  if (HandOpcode == ISD::ANY_EXTEND && LegalTypes &&
      !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
    return SDValue();
  // logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y)
  SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
  return DAG.getNode(HandOpcode, DL, VT, Logic);
}

// logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)
if (HandOpcode == ISD::TRUNCATE) {
  // If both operands have other uses, this transform would create extra
  // instructions without eliminating anything.
  if (!N0.hasOneUse() && !N1.hasOneUse())
    return SDValue();
  // We need matching source types.
  if (XVT != Y.getValueType())
    return SDValue();
  // Don't create an illegal op during or after legalization.
  if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
    return SDValue();
  // Be extra careful sinking truncate. If it's free, there's no benefit in
  // widening a binop. Also, don't create a logic op on an illegal type.
  if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT))
    return SDValue();
  if (!TLI.isTypeLegal(XVT))
    return SDValue();
  SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
  return DAG.getNode(HandOpcode, DL, VT, Logic);
}

// For binops SHL/SRL/SRA/AND:
//   logic_op (OP x, z), (OP y, z) --> OP (logic_op x, y), z
if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL ||
     HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
    N0.getOperand(1) == N1.getOperand(1)) {
  // If either operand has other uses, this transform is not an improvement.
  if (!N0.hasOneUse() || !N1.hasOneUse())
    return SDValue();
  SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
  return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
}

// Unary ops: logic_op (bswap x), (bswap y) --> bswap (logic_op x, y)
if (HandOpcode == ISD::BSWAP) {
  // If either operand has other uses, this transform is not an improvement.
  if (!N0.hasOneUse() || !N1.hasOneUse())
    return SDValue();
  SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
  return DAG.getNode(HandOpcode, DL, VT, Logic);
}

// Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
// Only perform this optimization up until type legalization, before
// LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
// adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
// we don't want to undo this promotion.
// We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
// on scalars.
if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
     Level <= AfterLegalizeTypes) {
  // Input types must be integer and the same.
  if (XVT.isInteger() && XVT == Y.getValueType() &&
      !(VT.isVector() && TLI.isTypeLegal(VT) &&
        !XVT.isVector() && !TLI.isTypeLegal(XVT))) {
    SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
    return DAG.getNode(HandOpcode, DL, VT, Logic);
  }
}

// Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
// Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
// If both shuffles use the same mask, and both shuffle within a single
// vector, then it is worthwhile to move the swizzle after the operation.
// The type-legalizer generates this pattern when loading illegal
// vector types from memory. In many cases this allows additional shuffle
// optimizations.
// There are other cases where moving the shuffle after the xor/and/or
// is profitable even if shuffles don't perform a swizzle.
// If both shuffles use the same mask, and both shuffles have the same first
// or second operand, then it might still be profitable to move the shuffle
// after the xor/and/or operation.
if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
  auto *SVN0 = cast<ShuffleVectorSDNode>(N0);
  auto *SVN1 = cast<ShuffleVectorSDNode>(N1);
  assert(X.getValueType() == Y.getValueType() &&((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4499, __PRETTY_FUNCTION__))
         "Inputs to shuffles are not the same type")((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4499, __PRETTY_FUNCTION__));

  // Check that both shuffles use the same mask. The masks are known to be of
  // the same length because the result vector type is the same.
  // Check also that shuffles have only one use to avoid introducing extra
  // instructions.
  if (!SVN0->hasOneUse() || !SVN1->hasOneUse() ||
      !SVN0->getMask().equals(SVN1->getMask()))
    return SDValue();

  // Don't try to fold this node if it requires introducing a
  // build vector of all zeros that might be illegal at this stage.
  SDValue ShOp = N0.getOperand(1);
  if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
    ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);

  // (logic_op (shuf (A, C), shuf (B, C))) --> shuf (logic_op (A, B), C)
  if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
    SDValue Logic = DAG.getNode(LogicOpcode, DL, VT,
                                N0.getOperand(0), N1.getOperand(0));
    return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask());
  }

  // Don't try to fold this node if it requires introducing a
  // build vector of all zeros that might be illegal at this stage.
  ShOp = N0.getOperand(0);
  if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
    ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);

  // (logic_op (shuf (C, A), shuf (C, B))) --> shuf (C, logic_op (A, B))
  if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
    SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
                                N1.getOperand(1));
    return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask());
  }
}

return SDValue();
4537}

4539/// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient.
4540SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
                                     const SDLoc &DL) {
SDValue LL, LR, RL, RR, N0CC, N1CC;
if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
    !isSetCCEquivalent(N1, RL, RR, N1CC))
  return SDValue();

assert(N0.getValueType() == N1.getValueType() &&((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4548, __PRETTY_FUNCTION__))
       "Unexpected operand types for bitwise logic op")((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4548, __PRETTY_FUNCTION__));
assert(LL.getValueType() == LR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4551, __PRETTY_FUNCTION__))
       RL.getValueType() == RR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4551, __PRETTY_FUNCTION__))
       "Unexpected operand types for setcc")((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4551, __PRETTY_FUNCTION__));

// If we're here post-legalization or the logic op type is not i1, the logic
// op type must match a setcc result type. Also, all folds require new
// operations on the left and right operands, so those types must match.
EVT VT = N0.getValueType();
EVT OpVT = LL.getValueType();
if (LegalOperations || VT.getScalarType() != MVT::i1)
  if (VT != getSetCCResultType(OpVT))
    return SDValue();
if (OpVT != RL.getValueType())
  return SDValue();

ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
bool IsInteger = OpVT.isInteger();
if (LR == RR && CC0 == CC1 && IsInteger) {
  bool IsZero = isNullOrNullSplat(LR);
  bool IsNeg1 = isAllOnesOrAllOnesSplat(LR);

  // All bits clear?
  bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
  // All sign bits clear?
  bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
  // Any bits set?
  bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
  // Any sign bits set?
  bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;

  // (and (seteq X,  0), (seteq Y,  0)) --> (seteq (or X, Y),  0)
  // (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
  // (or  (setne X,  0), (setne Y,  0)) --> (setne (or X, Y),  0)
  // (or  (setlt X,  0), (setlt Y,  0)) --> (setlt (or X, Y),  0)
  if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) {
    SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
    AddToWorklist(Or.getNode());
    return DAG.getSetCC(DL, VT, Or, LR, CC1);
  }

  // All bits set?
  bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
  // All sign bits set?
  bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
  // Any bits clear?
  bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1;
  // Any sign bits clear?
  bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1;

  // (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
  // (and (setlt X,  0), (setlt Y,  0)) --> (setlt (and X, Y),  0)
  // (or  (setne X, -1), (setne Y, -1)) --> (setne (and X, Y), -1)
  // (or  (setgt X, -1), (setgt Y  -1)) --> (setgt (and X, Y), -1)
  if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) {
    SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
    AddToWorklist(And.getNode());
    return DAG.getSetCC(DL, VT, And, LR, CC1);
  }
}

// TODO: What is the 'or' equivalent of this fold?
// (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 &&
    IsInteger && CC0 == ISD::SETNE &&
    ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
     (isAllOnesConstant(LR) && isNullConstant(RR)))) {
  SDValue One = DAG.getConstant(1, DL, OpVT);
  SDValue Two = DAG.getConstant(2, DL, OpVT);
  SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
  AddToWorklist(Add.getNode());
  return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
}

// Try more general transforms if the predicates match and the only user of
// the compares is the 'and' or 'or'.
if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 &&
    N0.hasOneUse() && N1.hasOneUse()) {
  // and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
  // or  (setne A, B), (setne C, D) --> setne (or (xor A, B), (xor C, D)), 0
  if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) {
    SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR);
    SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR);
    SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR);
    SDValue Zero = DAG.getConstant(0, DL, OpVT);
    return DAG.getSetCC(DL, VT, Or, Zero, CC1);
  }

  // Turn compare of constants whose difference is 1 bit into add+and+setcc.
  // TODO - support non-uniform vector amounts.
  if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) {
    // Match a shared variable operand and 2 non-opaque constant operands.
    ConstantSDNode *C0 = isConstOrConstSplat(LR);
    ConstantSDNode *C1 = isConstOrConstSplat(RR);
    if (LL == RL && C0 && C1 && !C0->isOpaque() && !C1->isOpaque()) {
      // Canonicalize larger constant as C0.
      if (C1->getAPIntValue().ugt(C0->getAPIntValue()))
        std::swap(C0, C1);

      // The difference of the constants must be a single bit.
      const APInt &C0Val = C0->getAPIntValue();
      const APInt &C1Val = C1->getAPIntValue();
      if ((C0Val - C1Val).isPowerOf2()) {
        // and/or (setcc X, C0, ne), (setcc X, C1, ne/eq) -->
        // setcc ((add X, -C1), ~(C0 - C1)), 0, ne/eq
        SDValue OffsetC = DAG.getConstant(-C1Val, DL, OpVT);
        SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LL, OffsetC);
        SDValue MaskC = DAG.getConstant(~(C0Val - C1Val), DL, OpVT);
        SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Add, MaskC);
        SDValue Zero = DAG.getConstant(0, DL, OpVT);
        return DAG.getSetCC(DL, VT, And, Zero, CC0);
      }
    }
  }
}

// Canonicalize equivalent operands to LL == RL.
if (LL == RR && LR == RL) {
  CC1 = ISD::getSetCCSwappedOperands(CC1);
  std::swap(RL, RR);
}

// (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
// (or  (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
if (LL == RL && LR == RR) {
  ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT)
                              : ISD::getSetCCOrOperation(CC0, CC1, OpVT);
  if (NewCC != ISD::SETCC_INVALID &&
      (!LegalOperations ||
       (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
        TLI.isOperationLegal(ISD::SETCC, OpVT))))
    return DAG.getSetCC(DL, VT, LL, LR, NewCC);
}

return SDValue();
4684}

4686/// This contains all DAGCombine rules which reduce two values combined by
4687/// an And operation to a single value. This makes them reusable in the context
4688/// of visitSELECT(). Rules involving constants are not included as
4689/// visitSELECT() already handles those cases.
4690SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
EVT VT = N1.getValueType();
SDLoc DL(N);

// fold (and x, undef) -> 0
if (N0.isUndef() || N1.isUndef())
  return DAG.getConstant(0, DL, VT);

if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
  return V;

if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
    VT.getSizeInBits() <= 64) {
  if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
    if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
      // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
      // immediate for an add, but it is legal if its top c2 bits are set,
      // transform the ADD so the immediate doesn't need to be materialized
      // in a register.
      APInt ADDC = ADDI->getAPIntValue();
      APInt SRLC = SRLI->getAPIntValue();
      if (ADDC.getMinSignedBits() <= 64 &&
          SRLC.ult(VT.getSizeInBits()) &&
          !TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
        APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
                                           SRLC.getZExtValue());
        if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
          ADDC |= Mask;
          if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
            SDLoc DL0(N0);
            SDValue NewAdd =
              DAG.getNode(ISD::ADD, DL0, VT,
                          N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
            CombineTo(N0.getNode(), NewAdd);
            // Return N so it doesn't get rechecked!
            return SDValue(N, 0);
          }
        }
      }
    }
  }
}

// Reduce bit extract of low half of an integer to the narrower type.
// (and (srl i64:x, K), KMask) ->
//   (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
  if (ConstantSDNode *CAnd = dyn_cast<ConstantSDNode>(N1)) {
    if (ConstantSDNode *CShift = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
      unsigned Size = VT.getSizeInBits();
      const APInt &AndMask = CAnd->getAPIntValue();
      unsigned ShiftBits = CShift->getZExtValue();

      // Bail out, this node will probably disappear anyway.
      if (ShiftBits == 0)
        return SDValue();

      unsigned MaskBits = AndMask.countTrailingOnes();
      EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);

      if (AndMask.isMask() &&
          // Required bits must not span the two halves of the integer and
          // must fit in the half size type.
          (ShiftBits + MaskBits <= Size / 2) &&
          TLI.isNarrowingProfitable(VT, HalfVT) &&
          TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
          TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) &&
          TLI.isTruncateFree(VT, HalfVT) &&
          TLI.isZExtFree(HalfVT, VT)) {
        // The isNarrowingProfitable is to avoid regressions on PPC and
        // AArch64 which match a few 64-bit bit insert / bit extract patterns
        // on downstream users of this. Those patterns could probably be
        // extended to handle extensions mixed in.

        SDValue SL(N0);
        assert(MaskBits <= Size)((MaskBits <= Size) ? static_cast<void> (0) : __assert_fail
 ("MaskBits <= Size", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4765, __PRETTY_FUNCTION__));

        // Extracting the highest bit of the low half.
        EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
        SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT,
                                    N0.getOperand(0));

        SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT);
        SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT);
        SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK);
        SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask);
        return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And);
      }
    }
  }
}

return SDValue();
4783}

4785bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
                                 EVT LoadResultTy, EVT &ExtVT) {
if (!AndC->getAPIntValue().isMask())
  return false;

unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes();

ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
EVT LoadedVT = LoadN->getMemoryVT();

if (ExtVT == LoadedVT &&
    (!LegalOperations ||
     TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
  // ZEXTLOAD will match without needing to change the size of the value being
  // loaded.
  return true;
}

// Do not change the width of a volatile or atomic loads.
if (!LoadN->isSimple())
  return false;

// Do not generate loads of non-round integer types since these can
// be expensive (and would be wrong if the type is not byte sized).
if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound())
  return false;

if (LegalOperations &&
    !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
  return false;

if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
  return false;

return true;
4820}

4822bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
                                  ISD::LoadExtType ExtType, EVT &MemVT,
                                  unsigned ShAmt) {
if (!LDST)
  return false;
// Only allow byte offsets.
if (ShAmt % 8)
  return false;

// Do not generate loads of non-round integer types since these can
// be expensive (and would be wrong if the type is not byte sized).
if (!MemVT.isRound())
  return false;

// Don't change the width of a volatile or atomic loads.
if (!LDST->isSimple())
  return false;

// Verify that we are actually reducing a load width here.
if (LDST->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits())
  return false;

// Ensure that this isn't going to produce an unsupported memory access.
if (ShAmt &&
    !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
                            LDST->getAddressSpace(), ShAmt / 8,
                            LDST->getMemOperand()->getFlags()))
  return false;

// It's not possible to generate a constant of extended or untyped type.
EVT PtrType = LDST->getBasePtr().getValueType();
if (PtrType == MVT::Untyped || PtrType.isExtended())
  return false;

if (isa<LoadSDNode>(LDST)) {
  LoadSDNode *Load = cast<LoadSDNode>(LDST);
  // Don't transform one with multiple uses, this would require adding a new
  // load.
  if (!SDValue(Load, 0).hasOneUse())
    return false;

  if (LegalOperations &&
      !TLI.isLoadExtLegal(ExtType, Load->getValueType(0), MemVT))
    return false;

  // For the transform to be legal, the load must produce only two values
  // (the value loaded and the chain).  Don't transform a pre-increment
  // load, for example, which produces an extra value.  Otherwise the
  // transformation is not equivalent, and the downstream logic to replace
  // uses gets things wrong.
  if (Load->getNumValues() > 2)
    return false;

  // If the load that we're shrinking is an extload and we're not just
  // discarding the extension we can't simply shrink the load. Bail.
  // TODO: It would be possible to merge the extensions in some cases.
  if (Load->getExtensionType() != ISD::NON_EXTLOAD &&
      Load->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
    return false;

  if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT))
    return false;
} else {
  assert(isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode")((isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode"
) ? static_cast<void> (0) : __assert_fail ("isa<StoreSDNode>(LDST) && \"It is not a Load nor a Store SDNode\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4885, __PRETTY_FUNCTION__));
  StoreSDNode *Store = cast<StoreSDNode>(LDST);
  // Can't write outside the original store
  if (Store->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
    return false;

  if (LegalOperations &&
      !TLI.isTruncStoreLegal(Store->getValue().getValueType(), MemVT))
    return false;
}
return true;
4896}

4898bool DAGCombiner::SearchForAndLoads(SDNode *N,
                                  SmallVectorImpl<LoadSDNode*> &Loads,
                                  SmallPtrSetImpl<SDNode*> &NodesWithConsts,
                                  ConstantSDNode *Mask,
                                  SDNode *&NodeToMask) {
// Recursively search for the operands, looking for loads which can be
// narrowed.
for (SDValue Op : N->op_values()) {
  if (Op.getValueType().isVector())
    return false;

  // Some constants may need fixing up later if they are too large.
  if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
    if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
        (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
      NodesWithConsts.insert(N);
    continue;
  }

  if (!Op.hasOneUse())
    return false;

  switch(Op.getOpcode()) {
  case ISD::LOAD: {
    auto *Load = cast<LoadSDNode>(Op);
    EVT ExtVT;
    if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
        isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) {

      // ZEXTLOAD is already small enough.
      if (Load->getExtensionType() == ISD::ZEXTLOAD &&
          ExtVT.bitsGE(Load->getMemoryVT()))
        continue;

      // Use LE to convert equal sized loads to zext.
      if (ExtVT.bitsLE(Load->getMemoryVT()))
        Loads.push_back(Load);

      continue;
    }
    return false;
  }
  case ISD::ZERO_EXTEND:
  case ISD::AssertZext: {
    unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
    EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
    EVT VT = Op.getOpcode() == ISD::AssertZext ?
      cast<VTSDNode>(Op.getOperand(1))->getVT() :
      Op.getOperand(0).getValueType();

    // We can accept extending nodes if the mask is wider or an equal
    // width to the original type.
    if (ExtVT.bitsGE(VT))
      continue;
    break;
  }
  case ISD::OR:
  case ISD::XOR:
  case ISD::AND:
    if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask,
                           NodeToMask))
      return false;
    continue;
  }

  // Allow one node which will masked along with any loads found.
  if (NodeToMask)
    return false;

  // Also ensure that the node to be masked only produces one data result.
  NodeToMask = Op.getNode();
  if (NodeToMask->getNumValues() > 1) {
    bool HasValue = false;
    for (unsigned i = 0, e = NodeToMask->getNumValues(); i < e; ++i) {
      MVT VT = SDValue(NodeToMask, i).getSimpleValueType();
      if (VT != MVT::Glue && VT != MVT::Other) {
        if (HasValue) {
          NodeToMask = nullptr;
          return false;
        }
        HasValue = true;
      }
    }
    assert(HasValue && "Node to be masked has no data result?")((HasValue && "Node to be masked has no data result?"
) ? static_cast<void> (0) : __assert_fail ("HasValue && \"Node to be masked has no data result?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4981, __PRETTY_FUNCTION__));
  }
}
return true;
4985}

4987bool DAGCombiner::BackwardsPropagateMask(SDNode *N) {
auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
if (!Mask)
  return false;

if (!Mask->getAPIntValue().isMask())
  return false;

// No need to do anything if the and directly uses a load.
if (isa<LoadSDNode>(N->getOperand(0)))
  return false;

SmallVector<LoadSDNode*, 8> Loads;
SmallPtrSet<SDNode*, 2> NodesWithConsts;
SDNode *FixupNode = nullptr;
if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) {
  if (Loads.size() == 0)
    return false;

  LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Backwards propagate AND: "
; N->dump(); } } while (false);
  SDValue MaskOp = N->getOperand(1);

  // If it exists, fixup the single node we allow in the tree that needs
  // masking.
  if (FixupNode) {
    LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "First, need to fix up: "; FixupNode
->dump(); } } while (false);
    SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
                              FixupNode->getValueType(0),
                              SDValue(FixupNode, 0), MaskOp);
    DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And);
    if (And.getOpcode() == ISD ::AND)
      DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOp);
  }

  // Narrow any constants that need it.
  for (auto *LogicN : NodesWithConsts) {
    SDValue Op0 = LogicN->getOperand(0);
    SDValue Op1 = LogicN->getOperand(1);

    if (isa<ConstantSDNode>(Op0))
        std::swap(Op0, Op1);

    SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(),
                              Op1, MaskOp);

    DAG.UpdateNodeOperands(LogicN, Op0, And);
  }

  // Create narrow loads.
  for (auto *Load : Loads) {
    LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Propagate AND back to: "; Load
->dump(); } } while (false);
    SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
                              SDValue(Load, 0), MaskOp);
    DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
    if (And.getOpcode() == ISD ::AND)
      And = SDValue(
          DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp), 0);
    SDValue NewLoad = ReduceLoadWidth(And.getNode());
    assert(NewLoad &&((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5046, __PRETTY_FUNCTION__))
           "Shouldn't be masking the load if it can't be narrowed")((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5046, __PRETTY_FUNCTION__));
    CombineTo(Load, NewLoad, NewLoad.getValue(1));
  }
  DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
  return true;
}
return false;
5053}

5055// Unfold
5056//    x &  (-1 'logical shift' y)
5057// To
5058//    (x 'opposite logical shift' y) 'logical shift' y
5059// if it is better for performance.
5060SDValue DAGCombiner::unfoldExtremeBitClearingToShifts(SDNode *N) {
assert(N->getOpcode() == ISD::AND)((N->getOpcode() == ISD::AND) ? static_cast<void> (0
) : __assert_fail ("N->getOpcode() == ISD::AND", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5061, __PRETTY_FUNCTION__));

SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);

// Do we actually prefer shifts over mask?
if (!TLI.shouldFoldMaskToVariableShiftPair(N0))
  return SDValue();

// Try to match  (-1 '[outer] logical shift' y)
unsigned OuterShift;
unsigned InnerShift; // The opposite direction to the OuterShift.
SDValue Y;           // Shift amount.
auto matchMask = [&OuterShift, &InnerShift, &Y](SDValue M) -> bool {
  if (!M.hasOneUse())
    return false;
  OuterShift = M->getOpcode();
  if (OuterShift == ISD::SHL)
    InnerShift = ISD::SRL;
  else if (OuterShift == ISD::SRL)
    InnerShift = ISD::SHL;
  else
    return false;
  if (!isAllOnesConstant(M->getOperand(0)))
    return false;
  Y = M->getOperand(1);
  return true;
};

SDValue X;
if (matchMask(N1))
  X = N0;
else if (matchMask(N0))
  X = N1;
else
  return SDValue();

SDLoc DL(N);
EVT VT = N->getValueType(0);

//     tmp = x   'opposite logical shift' y
SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y);
//     ret = tmp 'logical shift' y
SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y);

return T1;
5107}

5109/// Try to replace shift/logic that tests if a bit is clear with mask + setcc.
5110/// For a target with a bit test, this is expected to become test + set and save
5111/// at least 1 instruction.
5112static SDValue combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) {
assert(And->getOpcode() == ISD::AND && "Expected an 'and' op")((And->getOpcode() == ISD::AND && "Expected an 'and' op"
) ? static_cast<void> (0) : __assert_fail ("And->getOpcode() == ISD::AND && \"Expected an 'and' op\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5113, __PRETTY_FUNCTION__));

// This is probably not worthwhile without a supported type.
EVT VT = And->getValueType(0);
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (!TLI.isTypeLegal(VT))
  return SDValue();

// Look through an optional extension and find a 'not'.
// TODO: Should we favor test+set even without the 'not' op?
SDValue Not = And->getOperand(0), And1 = And->getOperand(1);
if (Not.getOpcode() == ISD::ANY_EXTEND)
  Not = Not.getOperand(0);
if (!isBitwiseNot(Not) || !Not.hasOneUse() || !isOneConstant(And1))
  return SDValue();

// Look though an optional truncation. The source operand may not be the same
// type as the original 'and', but that is ok because we are masking off
// everything but the low bit.
SDValue Srl = Not.getOperand(0);
if (Srl.getOpcode() == ISD::TRUNCATE)
  Srl = Srl.getOperand(0);

// Match a shift-right by constant.
if (Srl.getOpcode() != ISD::SRL || !Srl.hasOneUse() ||
    !isa<ConstantSDNode>(Srl.getOperand(1)))
  return SDValue();

// We might have looked through casts that make this transform invalid.
// TODO: If the source type is wider than the result type, do the mask and
//       compare in the source type.
const APInt &ShiftAmt = Srl.getConstantOperandAPInt(1);
unsigned VTBitWidth = VT.getSizeInBits();
if (ShiftAmt.uge(VTBitWidth))
  return SDValue();

// Turn this into a bit-test pattern using mask op + setcc:
// and (not (srl X, C)), 1 --> (and X, 1<<C) == 0
SDLoc DL(And);
SDValue X = DAG.getZExtOrTrunc(Srl.getOperand(0), DL, VT);
EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
SDValue Mask = DAG.getConstant(
    APInt::getOneBitSet(VTBitWidth, ShiftAmt.getZExtValue()), DL, VT);
SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, Mask);
SDValue Zero = DAG.getConstant(0, DL, VT);
SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ);
return DAG.getZExtOrTrunc(Setcc, DL, VT);
5160}

5162SDValue DAGCombiner::visitAND(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N1.getValueType();

// x & x --> x
if (N0 == N1)
  return N0;

// fold vector ops
if (VT.isVector()) {
  if (SDValue FoldedVOp = SimplifyVBinOp(N))
    return FoldedVOp;

  // fold (and x, 0) -> 0, vector edition
  if (ISD::isBuildVectorAllZeros(N0.getNode()))
    // do not return N0, because undef node may exist in N0
    return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()),
                           SDLoc(N), N0.getValueType());
  if (ISD::isBuildVectorAllZeros(N1.getNode()))
    // do not return N1, because undef node may exist in N1
    return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()),
                           SDLoc(N), N1.getValueType());

  // fold (and x, -1) -> x, vector edition
  if (ISD::isBuildVectorAllOnes(N0.getNode()))
    return N1;
  if (ISD::isBuildVectorAllOnes(N1.getNode()))
    return N0;
}

// fold (and c1, c2) -> c1&c2
ConstantSDNode *N1C = isConstOrConstSplat(N1);
if (SDValue C = DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, {N0, N1}))
  return C;

// canonicalize constant to RHS
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
    !DAG.isConstantIntBuildVectorOrConstantInt(N1))
  return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);

// fold (and x, -1) -> x
if (isAllOnesConstant(N1))
  return N0;

// if (and x, c) is known to be zero, return 0
unsigned BitWidth = VT.getScalarSizeInBits();
if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
                                 APInt::getAllOnesValue(BitWidth)))
  return DAG.getConstant(0, SDLoc(N), VT);

if (SDValue NewSel = foldBinOpIntoSelect(N))
  return NewSel;

// reassociate and
if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
  return RAND;

// Try to convert a constant mask AND into a shuffle clear mask.
if (VT.isVector())
  if (SDValue Shuffle = XformToShuffleWithZero(N))
    return Shuffle;

if (SDValue Combined = combineCarryDiamond(*this, DAG, TLI, N0, N1, N))
  return Combined;

// fold (and (or x, C), D) -> D if (C & D) == D
auto MatchSubset = [](ConstantSDNode *LHS, ConstantSDNode *RHS) {
  return RHS->getAPIntValue().isSubsetOf(LHS->getAPIntValue());
};
if (N0.getOpcode() == ISD::OR &&
    ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset))
  return N1;
// fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
  SDValue N0Op0 = N0.getOperand(0);
  APInt Mask = ~N1C->getAPIntValue();
  Mask = Mask.trunc(N0Op0.getScalarValueSizeInBits());
  if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
    SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
                               N0.getValueType(), N0Op0);

    // Replace uses of the AND with uses of the Zero extend node.
    CombineTo(N, Zext);

    // We actually want to replace all uses of the any_extend with the
    // zero_extend, to avoid duplicating things.  This will later cause this
    // AND to be folded.
    CombineTo(N0.getNode(), Zext);
    return SDValue(N, 0);   // Return N so it doesn't get rechecked!
  }
}

// similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
// (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
// already be zero by virtue of the width of the base type of the load.
//
// the 'X' node here can either be nothing or an extract_vector_elt to catch
// more cases.
if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
     N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
     N0.getOperand(0).getOpcode() == ISD::LOAD &&
     N0.getOperand(0).getResNo() == 0) ||
    (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
  LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
                                       N0 : N0.getOperand(0) );

  // Get the constant (if applicable) the zero'th operand is being ANDed with.
  // This can be a pure constant or a vector splat, in which case we treat the
  // vector as a scalar and use the splat value.
  APInt Constant = APInt::getNullValue(1);
  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
    Constant = C->getAPIntValue();
  } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
    APInt SplatValue, SplatUndef;
    unsigned SplatBitSize;
    bool HasAnyUndefs;
    bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
                                           SplatBitSize, HasAnyUndefs);
    if (IsSplat) {
      // Undef bits can contribute to a possible optimisation if set, so
      // set them.
      SplatValue |= SplatUndef;

      // The splat value may be something like "0x00FFFFFF", which means 0 for
      // the first vector value and FF for the rest, repeating. We need a mask
      // that will apply equally to all members of the vector, so AND all the
      // lanes of the constant together.
      unsigned EltBitWidth = Vector->getValueType(0).getScalarSizeInBits();

      // If the splat value has been compressed to a bitlength lower
      // than the size of the vector lane, we need to re-expand it to
      // the lane size.
      if (EltBitWidth > SplatBitSize)
        for (SplatValue = SplatValue.zextOrTrunc(EltBitWidth);
             SplatBitSize < EltBitWidth; SplatBitSize = SplatBitSize * 2)
          SplatValue |= SplatValue.shl(SplatBitSize);

      // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
      // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
      if ((SplatBitSize % EltBitWidth) == 0) {
        Constant = APInt::getAllOnesValue(EltBitWidth);
        for (unsigned i = 0, n = (SplatBitSize / EltBitWidth); i < n; ++i)
          Constant &= SplatValue.extractBits(EltBitWidth, i * EltBitWidth);
      }
    }
  }

  // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
  // actually legal and isn't going to get expanded, else this is a false
  // optimisation.
  bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
                                                  Load->getValueType(0),
                                                  Load->getMemoryVT());

  // Resize the constant to the same size as the original memory access before
  // extension. If it is still the AllOnesValue then this AND is completely
  // unneeded.
  Constant = Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits());

  bool B;
  switch (Load->getExtensionType()) {
  default: B = false; break;
  case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
  case ISD::ZEXTLOAD:
  case ISD::NON_EXTLOAD: B = true; break;
  }

  if (B && Constant.isAllOnesValue()) {
    // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
    // preserve semantics once we get rid of the AND.
    SDValue NewLoad(Load, 0);

    // Fold the AND away. NewLoad may get replaced immediately.
    CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);

    if (Load->getExtensionType() == ISD::EXTLOAD) {
      NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
                            Load->getValueType(0), SDLoc(Load),
                            Load->getChain(), Load->getBasePtr(),
                            Load->getOffset(), Load->getMemoryVT(),
                            Load->getMemOperand());
      // Replace uses of the EXTLOAD with the new ZEXTLOAD.
      if (Load->getNumValues() == 3) {
        // PRE/POST_INC loads have 3 values.
        SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
                         NewLoad.getValue(2) };
        CombineTo(Load, To, 3, true);
      } else {
        CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
      }
    }

    return SDValue(N, 0); // Return N so it doesn't get rechecked!
  }
}

// fold (and (load x), 255) -> (zextload x, i8)
// fold (and (extload x, i16), 255) -> (zextload x, i8)
// fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
                              (N0.getOpcode() == ISD::ANY_EXTEND &&
                               N0.getOperand(0).getOpcode() == ISD::LOAD))) {
  if (SDValue Res = ReduceLoadWidth(N)) {
    LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
      ? cast<LoadSDNode>(N0.getOperand(0)) : cast<LoadSDNode>(N0);
    AddToWorklist(N);
    DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 0), Res);
    return SDValue(N, 0);
  }
}

if (LegalTypes) {
  // Attempt to propagate the AND back up to the leaves which, if they're
  // loads, can be combined to narrow loads and the AND node can be removed.
  // Perform after legalization so that extend nodes will already be
  // combined into the loads.
  if (BackwardsPropagateMask(N))
    return SDValue(N, 0);
}

if (SDValue Combined = visitANDLike(N0, N1, N))
  return Combined;

// Simplify: (and (op x...), (op y...))  -> (op (and x, y))
if (N0.getOpcode() == N1.getOpcode())
  if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
    return V;

// Masking the negated extension of a boolean is just the zero-extended
// boolean:
// and (sub 0, zext(bool X)), 1 --> zext(bool X)
// and (sub 0, sext(bool X)), 1 --> zext(bool X)
//
// Note: the SimplifyDemandedBits fold below can make an information-losing
// transform, and then we have no way to find this better fold.
if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
  if (isNullOrNullSplat(N0.getOperand(0))) {
    SDValue SubRHS = N0.getOperand(1);
    if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
        SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
      return SubRHS;
    if (SubRHS.getOpcode() == ISD::SIGN_EXTEND &&
        SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
      return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0));
  }
}

// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
// fold (and (sra)) -> (and (srl)) when possible.
if (SimplifyDemandedBits(SDValue(N, 0)))
  return SDValue(N, 0);

// fold (zext_inreg (extload x)) -> (zextload x)
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
if (ISD::isUNINDEXEDLoad(N0.getNode()) &&
    (ISD::isEXTLoad(N0.getNode()) ||
     (ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) {
  LoadSDNode *LN0 = cast<LoadSDNode>(N0);
  EVT MemVT = LN0->getMemoryVT();
  // If we zero all the possible extended bits, then we can turn this into
  // a zextload if we are running before legalize or the operation is legal.
  unsigned ExtBitSize = N1.getScalarValueSizeInBits();
  unsigned MemBitSize = MemVT.getScalarSizeInBits();
  APInt ExtBits = APInt::getHighBitsSet(ExtBitSize, ExtBitSize - MemBitSize);
  if (DAG.MaskedValueIsZero(N1, ExtBits) &&
      ((!LegalOperations && LN0->isSimple()) ||
       TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
    SDValue ExtLoad =
        DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(),
                       LN0->getBasePtr(), MemVT, LN0->getMemOperand());
    AddToWorklist(N);
    CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
    return SDValue(N, 0); // Return N so it doesn't get rechecked!
  }
}

// fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
  if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
                                         N0.getOperand(1), false))
    return BSwap;
}

if (SDValue Shifts = unfoldExtremeBitClearingToShifts(N))
  return Shifts;

if (TLI.hasBitTest(N0, N1))
  if (SDValue V = combineShiftAnd1ToBitTest(N, DAG))
    return V;

return SDValue();
5454}

5456/// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
5457SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
                                      bool DemandHighBits) {
if (!LegalOperations)
  return SDValue();

EVT VT = N->getValueType(0);
if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
  return SDValue();
if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
  return SDValue();

// Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff)
bool LookPassAnd0 = false;
bool LookPassAnd1 = false;
if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
    std::swap(N0, N1);
if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
    std::swap(N0, N1);
if (N0.getOpcode() == ISD::AND) {
  if (!N0.getNode()->hasOneUse())
    return SDValue();
  ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
  // Also handle 0xffff since the LHS is guaranteed to have zeros there.
  // This is needed for X86.
  if (!N01C || (N01C->getZExtValue() != 0xFF00 &&
                N01C->getZExtValue() != 0xFFFF))
    return SDValue();
  N0 = N0.getOperand(0);
  LookPassAnd0 = true;
}

if (N1.getOpcode() == ISD::AND) {
  if (!N1.getNode()->hasOneUse())
    return SDValue();
  ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
  if (!N11C || N11C->getZExtValue() != 0xFF)
    return SDValue();
  N1 = N1.getOperand(0);
  LookPassAnd1 = true;
}

if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
  std::swap(N0, N1);
if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
  return SDValue();
if (!N0.getNode()->hasOneUse() || !N1.getNode()->hasOneUse())
  return SDValue();

ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
if (!N01C || !N11C)
  return SDValue();
if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
  return SDValue();

// Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
SDValue N00 = N0->getOperand(0);
if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
  if (!N00.getNode()->hasOneUse())
    return SDValue();
  ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
  if (!N001C || N001C->getZExtValue() != 0xFF)
    return SDValue();
  N00 = N00.getOperand(0);
  LookPassAnd0 = true;
}

SDValue N10 = N1->getOperand(0);
if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
  if (!N10.getNode()->hasOneUse())
    return SDValue();
  ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
  // Also allow 0xFFFF since the bits will be shifted out. This is needed
  // for X86.
  if (!N101C || (N101C->getZExtValue() != 0xFF00 &&
                 N101C->getZExtValue() != 0xFFFF))
    return SDValue();
  N10 = N10.getOperand(0);
  LookPassAnd1 = true;
}

if (N00 != N10)
  return SDValue();

// Make sure everything beyond the low halfword gets set to zero since the SRL
// 16 will clear the top bits.
unsigned OpSizeInBits = VT.getSizeInBits();
if (DemandHighBits && OpSizeInBits > 16) {
  // If the left-shift isn't masked out then the only way this is a bswap is
  // if all bits beyond the low 8 are 0. In that case the entire pattern
  // reduces to a left shift anyway: leave it for other parts of the combiner.
  if (!LookPassAnd0)
    return SDValue();

  // However, if the right shift isn't masked out then it might be because
  // it's not needed. See if we can spot that too.
  if (!LookPassAnd1 &&
      !DAG.MaskedValueIsZero(
          N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
    return SDValue();
}

SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
if (OpSizeInBits > 16) {
  SDLoc DL(N);
  Res = DAG.getNode(ISD::SRL, DL, VT, Res,
                    DAG.getConstant(OpSizeInBits - 16, DL,
                                    getShiftAmountTy(VT)));
}
return Res;
5567}

5569/// Return true if the specified node is an element that makes up a 32-bit
5570/// packed halfword byteswap.
5571/// ((x & 0x000000ff) << 8) |
5572/// ((x & 0x0000ff00) >> 8) |
5573/// ((x & 0x00ff0000) << 8) |
5574/// ((x & 0xff000000) >> 8)
5575static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
if (!N.getNode()->hasOneUse())
  return false;

unsigned Opc = N.getOpcode();
if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
  return false;

SDValue N0 = N.getOperand(0);
unsigned Opc0 = N0.getOpcode();
if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
  return false;

ConstantSDNode *N1C = nullptr;
// SHL or SRL: look upstream for AND mask operand
if (Opc == ISD::AND)
  N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
else if (Opc0 == ISD::AND)
  N1C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
if (!N1C)
  return false;

unsigned MaskByteOffset;
switch (N1C->getZExtValue()) {
default:
  return false;
case 0xFF:       MaskByteOffset = 0; break;
case 0xFF00:     MaskByteOffset = 1; break;
case 0xFFFF:
  // In case demanded bits didn't clear the bits that will be shifted out.
  // This is needed for X86.
  if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) {
    MaskByteOffset = 1;
    break;
  }
  return false;
case 0xFF0000:   MaskByteOffset = 2; break;
case 0xFF000000: MaskByteOffset = 3; break;
}

// Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
if (Opc == ISD::AND) {
  if (MaskByteOffset == 0 || MaskByteOffset == 2) {
    // (x >> 8) & 0xff
    // (x >> 8) & 0xff0000
    if (Opc0 != ISD::SRL)
      return false;
    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
    if (!C || C->getZExtValue() != 8)
      return false;
  } else {
    // (x << 8) & 0xff00
    // (x << 8) & 0xff000000
    if (Opc0 != ISD::SHL)
      return false;
    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
    if (!C || C->getZExtValue() != 8)
      return false;
  }
} else if (Opc == ISD::SHL) {
  // (x & 0xff) << 8
  // (x & 0xff0000) << 8
  if (MaskByteOffset != 0 && MaskByteOffset != 2)
    return false;
  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
  if (!C || C->getZExtValue() != 8)
    return false;
} else { // Opc == ISD::SRL
  // (x & 0xff00) >> 8
  // (x & 0xff000000) >> 8
  if (MaskByteOffset != 1 && MaskByteOffset != 3)
    return false;
  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
  if (!C || C->getZExtValue() != 8)
    return false;
}

if (Parts[MaskByteOffset])
  return false;

Parts[MaskByteOffset] = N0.getOperand(0).getNode();
return true;
5657}

5659// Match 2 elements of a packed halfword bswap.
5660static bool isBSwapHWordPair(SDValue N, MutableArrayRef<SDNode *> Parts) {
if (N.getOpcode() == ISD::OR)
  return isBSwapHWordElement(N.getOperand(0), Parts) &&
         isBSwapHWordElement(N.getOperand(1), Parts);

if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
  ConstantSDNode *C = isConstOrConstSplat(N.getOperand(1));
  if (!C || C->getAPIntValue() != 16)
    return false;
  Parts[0] = Parts[1] = N.getOperand(0).getOperand(0).getNode();
  return true;
}

return false;
5674}

5676// Match this pattern:
5677//   (or (and (shl (A, 8)), 0xff00ff00), (and (srl (A, 8)), 0x00ff00ff))
5678// And rewrite this to:
5679//   (rotr (bswap A), 16)
5680static SDValue matchBSwapHWordOrAndAnd(const TargetLowering &TLI,
                                     SelectionDAG &DAG, SDNode *N, SDValue N0,
                                     SDValue N1, EVT VT, EVT ShiftAmountTy) {
assert(N->getOpcode() == ISD::OR && VT == MVT::i32 &&((N->getOpcode() == ISD::OR && VT == MVT::i32 &&
 "MatchBSwapHWordOrAndAnd: expecting i32") ? static_cast<void
> (0) : __assert_fail ("N->getOpcode() == ISD::OR && VT == MVT::i32 && \"MatchBSwapHWordOrAndAnd: expecting i32\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5684, __PRETTY_FUNCTION__))
       "MatchBSwapHWordOrAndAnd: expecting i32")((N->getOpcode() == ISD::OR && VT == MVT::i32 &&
 "MatchBSwapHWordOrAndAnd: expecting i32") ? static_cast<void
> (0) : __assert_fail ("N->getOpcode() == ISD::OR && VT == MVT::i32 && \"MatchBSwapHWordOrAndAnd: expecting i32\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5684, __PRETTY_FUNCTION__));
if (!TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
  return SDValue();
if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
  return SDValue();
// TODO: this is too restrictive; lifting this restriction requires more tests
if (!N0->hasOneUse() || !N1->hasOneUse())
  return SDValue();
ConstantSDNode *Mask0 = isConstOrConstSplat(N0.getOperand(1));
ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1));
if (!Mask0 || !Mask1)
  return SDValue();
if (Mask0->getAPIntValue() != 0xff00ff00 ||
    Mask1->getAPIntValue() != 0x00ff00ff)
  return SDValue();
SDValue Shift0 = N0.getOperand(0);
SDValue Shift1 = N1.getOperand(0);
if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL)
  return SDValue();
ConstantSDNode *ShiftAmt0 = isConstOrConstSplat(Shift0.getOperand(1));
ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1));
if (!ShiftAmt0 || !ShiftAmt1)
  return SDValue();
if (ShiftAmt0->getAPIntValue() != 8 || ShiftAmt1->getAPIntValue() != 8)
  return SDValue();
if (Shift0.getOperand(0) != Shift1.getOperand(0))
  return SDValue();

SDLoc DL(N);
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Shift0.getOperand(0));
SDValue ShAmt = DAG.getConstant(16, DL, ShiftAmountTy);
return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
5716}

5718/// Match a 32-bit packed halfword bswap. That is
5719/// ((x & 0x000000ff) << 8) |
5720/// ((x & 0x0000ff00) >> 8) |
5721/// ((x & 0x00ff0000) << 8) |
5722/// ((x & 0xff000000) >> 8)
5723/// => (rotl (bswap x), 16)
5724SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
if (!LegalOperations)
  return SDValue();

EVT VT = N->getValueType(0);
if (VT != MVT::i32)
  return SDValue();
if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
  return SDValue();

if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N0, N1, VT,
                                            getShiftAmountTy(VT)))
return BSwap;

// Try again with commuted operands.
if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N1, N0, VT,
                                            getShiftAmountTy(VT)))
return BSwap;


// Look for either
// (or (bswaphpair), (bswaphpair))
// (or (or (bswaphpair), (and)), (and))
// (or (or (and), (bswaphpair)), (and))
SDNode *Parts[4] = {};

if (isBSwapHWordPair(N0, Parts)) {
  // (or (or (and), (and)), (or (and), (and)))
  if (!isBSwapHWordPair(N1, Parts))
    return SDValue();
} else if (N0.getOpcode() == ISD::OR) {
  // (or (or (or (and), (and)), (and)), (and))
  if (!isBSwapHWordElement(N1, Parts))
    return SDValue();
  SDValue N00 = N0.getOperand(0);
  SDValue N01 = N0.getOperand(1);
  if (!(isBSwapHWordElement(N01, Parts) && isBSwapHWordPair(N00, Parts)) &&
      !(isBSwapHWordElement(N00, Parts) && isBSwapHWordPair(N01, Parts)))
    return SDValue();
} else
  return SDValue();

// Make sure the parts are all coming from the same node.
if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
  return SDValue();

SDLoc DL(N);
SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
                            SDValue(Parts[0], 0));

// Result of the bswap should be rotated by 16. If it's not legal, then
// do  (x << 16) | (x >> 16).
SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT));
if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
  return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
  return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
return DAG.getNode(ISD::OR, DL, VT,
                   DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt),
                   DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
5784}

5786/// This contains all DAGCombine rules which reduce two values combined by
5787/// an Or operation to a single value \see visitANDLike().
5788SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *N) {
EVT VT = N1.getValueType();
SDLoc DL(N);

// fold (or x, undef) -> -1
if (!LegalOperations && (N0.isUndef() || N1.isUndef()))
  return DAG.getAllOnesConstant(DL, VT);

if (SDValue V = foldLogicOfSetCCs(false, N0, N1, DL))
  return V;

// (or (and X, C1), (and Y, C2))  -> (and (or X, Y), C3) if possible.
if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
    // Don't increase # computations.
    (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
  // We can only do this xform if we know that bits from X that are set in C2
  // but not in C1 are already zero.  Likewise for Y.
  if (const ConstantSDNode *N0O1C =
      getAsNonOpaqueConstant(N0.getOperand(1))) {
    if (const ConstantSDNode *N1O1C =
        getAsNonOpaqueConstant(N1.getOperand(1))) {
      // We can only do this xform if we know that bits from X that are set in
      // C2 but not in C1 are already zero.  Likewise for Y.
      const APInt &LHSMask = N0O1C->getAPIntValue();
      const APInt &RHSMask = N1O1C->getAPIntValue();

      if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
          DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
        SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
                                N0.getOperand(0), N1.getOperand(0));
        return DAG.getNode(ISD::AND, DL, VT, X,
                           DAG.getConstant(LHSMask | RHSMask, DL, VT));
      }
    }
  }
}

// (or (and X, M), (and X, N)) -> (and X, (or M, N))
if (N0.getOpcode() == ISD::AND &&
    N1.getOpcode() == ISD::AND &&
    N0.getOperand(0) == N1.getOperand(0) &&
    // Don't increase # computations.
    (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
  SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
                          N0.getOperand(1), N1.getOperand(1));
  return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X);
}

return SDValue();
5837}

5839/// OR combines for which the commuted variant will be tried as well.
5840static SDValue visitORCommutative(
  SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N) {
EVT VT = N0.getValueType();
if (N0.getOpcode() == ISD::AND) {
  // fold (or (and X, (xor Y, -1)), Y) -> (or X, Y)
  if (isBitwiseNot(N0.getOperand(1)) && N0.getOperand(1).getOperand(0) == N1)
    return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(0), N1);

  // fold (or (and (xor Y, -1), X), Y) -> (or X, Y)
  if (isBitwiseNot(N0.getOperand(0)) && N0.getOperand(0).getOperand(0) == N1)
    return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(1), N1);
}

return SDValue();
5854}

5856SDValue DAGCombiner::visitOR(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
EVT VT = N1.getValueType();

// x | x --> x
if (N0 == N1)
  return N0;

// fold vector ops
if (VT.isVector()) {
  if (SDValue FoldedVOp = SimplifyVBinOp(N))
    return FoldedVOp;

  // fold (or x, 0) -> x, vector edition
  if (ISD::isBuildVectorAllZeros(N0.getNode()))
    return N1;
  if (ISD::isBuildVectorAllZeros(N1.getNode()))
    return N0;

  // fold (or x, -1) -> -1, vector edition
  if (ISD::isBuildVectorAllOnes(N0.getNode()))
    // do not return N0, because undef node may exist in N0
    return DAG.getAllOnesConstant(SDLoc(N), N0.getValueType());
  if (ISD::isBuildVectorAllOnes(N1.getNode()))
    // do not return N1, because undef node may exist in N1
    return DAG.getAllOnesConstant(SDLoc(N), N1.getValueType());

  // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask)
  // Do this only if the resulting shuffle is legal.
  if (isa<ShuffleVectorSDNode>(N0) &&
      isa<ShuffleVectorSDNode>(N1) &&
      // Avoid folding a node with illegal type.
      TLI.isTypeLegal(VT)) {
    bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode());
    bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode());
    bool ZeroN10 = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
    bool ZeroN11 = ISD::isBuildVectorAllZeros(N1.getOperand(1).getNode());
    // Ensure both shuffles have a zero input.
    if ((ZeroN00 != ZeroN01) && (ZeroN10 != ZeroN11)) {
      assert((!ZeroN00 || !ZeroN01) && "Both inputs zero!")(((!ZeroN00 || !ZeroN01) && "Both inputs zero!") ? static_cast
<void> (0) : __assert_fail ("(!ZeroN00 || !ZeroN01) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5896, __PRETTY_FUNCTION__));
      assert((!ZeroN10 || !ZeroN11) && "Both inputs zero!")(((!ZeroN10 || !ZeroN11) && "Both inputs zero!") ? static_cast
<void> (0) : __assert_fail ("(!ZeroN10 || !ZeroN11) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5897, __PRETTY_FUNCTION__));
      const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
      const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
      bool CanFold = true;
      int NumElts = VT.getVectorNumElements();
      SmallVector<int, 4> Mask(NumElts);

      for (int i = 0; i != NumElts; ++i) {
        int M0 = SV0->getMaskElt(i);
        int M1 = SV1->getMaskElt(i);

        // Determine if either index is pointing to a zero vector.
        bool M0Zero = M0 < 0 || (ZeroN00 == (M0 < NumElts));
        bool M1Zero = M1 < 0 || (ZeroN10 == (M1 < NumElts));

        // If one element is zero and the otherside is undef, keep undef.
        // This also handles the case that both are undef.
        if ((M0Zero && M1 < 0) || (M1Zero && M0 < 0)) {
          Mask[i] = -1;
          continue;
        }

        // Make sure only one of the elements is zero.
        if (M0Zero == M1Zero) {
          CanFold = false;
          break;
        }

        assert((M0 >= 0 || M1 >= 0) && "Undef index!")(((M0 >= 0 || M1 >= 0) && "Undef index!") ? static_cast
<void> (0) : __assert_fail ("(M0 >= 0 || M1 >= 0) && \"Undef index!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5925, __PRETTY_FUNCTION__));

        // We have a zero and non-zero element. If the non-zero came from
        // SV0 make the index a LHS index. If it came from SV1, make it
        // a RHS index. We need to mod by NumElts because we don't care
        // which operand it came from in the original shuffles.
        Mask[i] = M1Zero ? M0 % NumElts : (M1 % NumElts) + NumElts;
      }

      if (CanFold) {
        SDValue NewLHS = ZeroN00 ? N0.getOperand(1) : N0.getOperand(0);
        SDValue NewRHS = ZeroN10 ? N1.getOperand(1) : N1.getOperand(0);

        SDValue LegalShuffle =
            TLI.buildLegalVectorShuffle(VT, SDLoc(N), NewLHS, NewRHS,
                                        Mask, DAG);
        if (LegalShuffle)
          return LegalShuffle;
      }
    }
  }
}

// fold (or c1, c2) -> c1|c2
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
if (SDValue C = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, {N0, N1}))
  return C;

// canonicalize constant to RHS
if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
   !DAG.isConstantIntBuildVectorOrConstantInt(N1))
  return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);

// fold (or x, 0) -> x
if (isNullConstant(N1))
  return N0;

// fold (or x, -1) -> -1
if (isAllOnesConstant(N1))
  return N1;

if (SDValue NewSel = foldBinOpIntoSelect(N))
  return NewSel;

// fold (or x, c) -> c iff (x & ~c) == 0
if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
  return N1;

if (SDValue Combined = visitORLike(N0, N1, N))
  return Combined;

if (SDValue Combined = combineCarryDiamond(*this, DAG, TLI, N0, N1, N))
  return Combined;

// Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
if (SDValue BSwap = MatchBSwapHWord(N, N0, N1))
  return BSwap;
if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1))
  return BSwap;

// reassociate or
if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags()))
  return ROR;

// Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
// iff (c1 & c2) != 0 or c1/c2 are undef.
auto MatchIntersect = [](ConstantSDNode *C1, ConstantSDNode *C2) {
  return !C1 || !C2 || C1->getAPIntValue().intersects(C2->getAPIntValue());
};
if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
    ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchIntersect, true)) {
  if (SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N1), VT,
                                               {N1, N0.getOperand(1)})) {
    SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1);
    AddToWorklist(IOR.getNode());
    return DAG.getNode(ISD::AND, SDLoc(N), VT, COR, IOR);
  }
}

if (SDValue Combined = visitORCommutative(DAG, N0, N1, N))
  return Combined;
if (SDValue Combined = visitORCommutative(DAG, N1, N0, N))
  return Combined;

// Simplify: (or (op x...), (op y...))  -> (op (or x, y))
if (N0.getOpcode() == N1.getOpcode())
  if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
    return V;

// See if this is some rotate idiom.
if (SDValue Rot = MatchRotate(N0, N1, SDLoc(N)))
  return Rot;

if (SDValue Load = MatchLoadCombine(N))
  return Load;

// Simplify the operands using demanded-bits information.
if (SimplifyDemandedBits(SDValue(N, 0)))
  return SDValue(N, 0);

// If OR can be rewritten into ADD, try combines based on ADD.
if ((!LegalOperations || TLI.isOperationLegal(ISD::ADD, VT)) &&
    DAG.haveNoCommonBitsSet(N0, N1))
  if (SDValue Combined = visitADDLike(N))
    return Combined;
