Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1153, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name DAGCombiner.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-11/lib/clang/11.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/include -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-11/lib/clang/11.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-03-09-184146-41876-1 -x c++ /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

1//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
10// both before and after the DAG is legalized.
11//
12// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
13// primarily intended to handle simplification opportunities that are implicit
14// in the LLVM IR and exposed by the various codegen lowering phases.
15//
16//===----------------------------------------------------------------------===//
17
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/ArrayRef.h"
21#include "llvm/ADT/DenseMap.h"
22#include "llvm/ADT/IntervalMap.h"
23#include "llvm/ADT/None.h"
24#include "llvm/ADT/Optional.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SetVector.h"
27#include "llvm/ADT/SmallPtrSet.h"
28#include "llvm/ADT/SmallSet.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/Statistic.h"
31#include "llvm/Analysis/AliasAnalysis.h"
32#include "llvm/Analysis/MemoryLocation.h"
33#include "llvm/Analysis/VectorUtils.h"
34#include "llvm/CodeGen/DAGCombine.h"
35#include "llvm/CodeGen/ISDOpcodes.h"
36#include "llvm/CodeGen/MachineFrameInfo.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/RuntimeLibcalls.h"
40#include "llvm/CodeGen/SelectionDAG.h"
41#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
42#include "llvm/CodeGen/SelectionDAGNodes.h"
43#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
44#include "llvm/CodeGen/TargetLowering.h"
45#include "llvm/CodeGen/TargetRegisterInfo.h"
46#include "llvm/CodeGen/TargetSubtargetInfo.h"
47#include "llvm/CodeGen/ValueTypes.h"
48#include "llvm/IR/Attributes.h"
49#include "llvm/IR/Constant.h"
50#include "llvm/IR/DataLayout.h"
51#include "llvm/IR/DerivedTypes.h"
52#include "llvm/IR/Function.h"
53#include "llvm/IR/LLVMContext.h"
54#include "llvm/IR/Metadata.h"
55#include "llvm/Support/Casting.h"
56#include "llvm/Support/CodeGen.h"
57#include "llvm/Support/CommandLine.h"
58#include "llvm/Support/Compiler.h"
59#include "llvm/Support/Debug.h"
60#include "llvm/Support/ErrorHandling.h"
61#include "llvm/Support/KnownBits.h"
62#include "llvm/Support/MachineValueType.h"
63#include "llvm/Support/MathExtras.h"
64#include "llvm/Support/raw_ostream.h"
65#include "llvm/Target/TargetMachine.h"
66#include "llvm/Target/TargetOptions.h"
67#include <algorithm>
68#include <cassert>
69#include <cstdint>
70#include <functional>
71#include <iterator>
72#include <string>
73#include <tuple>
74#include <utility>
75
76using namespace llvm;
77
78#define DEBUG_TYPE"dagcombine" "dagcombine"
79
80STATISTIC(NodesCombined , "Number of dag nodes combined")static llvm::Statistic NodesCombined = {"dagcombine", "NodesCombined"
, "Number of dag nodes combined"}
;
81STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created")static llvm::Statistic PreIndexedNodes = {"dagcombine", "PreIndexedNodes"
, "Number of pre-indexed nodes created"}
;
82STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created")static llvm::Statistic PostIndexedNodes = {"dagcombine", "PostIndexedNodes"
, "Number of post-indexed nodes created"}
;
83STATISTIC(OpsNarrowed , "Number of load/op/store narrowed")static llvm::Statistic OpsNarrowed = {"dagcombine", "OpsNarrowed"
, "Number of load/op/store narrowed"}
;
84STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int")static llvm::Statistic LdStFP2Int = {"dagcombine", "LdStFP2Int"
, "Number of fp load/store pairs transformed to int"}
;
85STATISTIC(SlicedLoads, "Number of load sliced")static llvm::Statistic SlicedLoads = {"dagcombine", "SlicedLoads"
, "Number of load sliced"}
;
86STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops")static llvm::Statistic NumFPLogicOpsConv = {"dagcombine", "NumFPLogicOpsConv"
, "Number of logic ops converted to fp ops"}
;
87
88static cl::opt<bool>
89CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
90 cl::desc("Enable DAG combiner's use of IR alias analysis"));
91
92static cl::opt<bool>
93UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
94 cl::desc("Enable DAG combiner's use of TBAA"));
95
96#ifndef NDEBUG
97static cl::opt<std::string>
98CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
99 cl::desc("Only use DAG-combiner alias analysis in this"
100 " function"));
101#endif
102
103/// Hidden option to stress test load slicing, i.e., when this option
104/// is enabled, load slicing bypasses most of its profitability guards.
105static cl::opt<bool>
106StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
107 cl::desc("Bypass the profitability model of load slicing"),
108 cl::init(false));
109
110static cl::opt<bool>
111 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
112 cl::desc("DAG combiner may split indexing from loads"));
113
114static cl::opt<bool>
115 EnableStoreMerging("combiner-store-merging", cl::Hidden, cl::init(true),
116 cl::desc("DAG combiner enable merging multiple stores "
117 "into a wider store"));
118
119static cl::opt<unsigned> TokenFactorInlineLimit(
120 "combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048),
121 cl::desc("Limit the number of operands to inline for Token Factors"));
122
123static cl::opt<unsigned> StoreMergeDependenceLimit(
124 "combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10),
125 cl::desc("Limit the number of times for the same StoreNode and RootNode "
126 "to bail out in store merging dependence check"));
127
128namespace {
129
130 class DAGCombiner {
131 SelectionDAG &DAG;
132 const TargetLowering &TLI;
133 CombineLevel Level;
134 CodeGenOpt::Level OptLevel;
135 bool LegalDAG = false;
136 bool LegalOperations = false;
137 bool LegalTypes = false;
138 bool ForCodeSize;
139
140 /// Worklist of all of the nodes that need to be simplified.
141 ///
142 /// This must behave as a stack -- new nodes to process are pushed onto the
143 /// back and when processing we pop off of the back.
144 ///
145 /// The worklist will not contain duplicates but may contain null entries
146 /// due to nodes being deleted from the underlying DAG.
147 SmallVector<SDNode *, 64> Worklist;
148
149 /// Mapping from an SDNode to its position on the worklist.
150 ///
151 /// This is used to find and remove nodes from the worklist (by nulling
152 /// them) when they are deleted from the underlying DAG. It relies on
153 /// stable indices of nodes within the worklist.
154 DenseMap<SDNode *, unsigned> WorklistMap;
155 /// This records all nodes attempted to add to the worklist since we
156 /// considered a new worklist entry. As we keep do not add duplicate nodes
157 /// in the worklist, this is different from the tail of the worklist.
158 SmallSetVector<SDNode *, 32> PruningList;
159
160 /// Set of nodes which have been combined (at least once).
161 ///
162 /// This is used to allow us to reliably add any operands of a DAG node
163 /// which have not yet been combined to the worklist.
164 SmallPtrSet<SDNode *, 32> CombinedNodes;
165
166 /// Map from candidate StoreNode to the pair of RootNode and count.
167 /// The count is used to track how many times we have seen the StoreNode
168 /// with the same RootNode bail out in dependence check. If we have seen
169 /// the bail out for the same pair many times over a limit, we won't
170 /// consider the StoreNode with the same RootNode as store merging
171 /// candidate again.
172 DenseMap<SDNode *, std::pair<SDNode *, unsigned>> StoreRootCountMap;
173
174 // AA - Used for DAG load/store alias analysis.
175 AliasAnalysis *AA;
176
177 /// When an instruction is simplified, add all users of the instruction to
178 /// the work lists because they might get more simplified now.
179 void AddUsersToWorklist(SDNode *N) {
180 for (SDNode *Node : N->uses())
181 AddToWorklist(Node);
182 }
183
184 /// Convenient shorthand to add a node and all of its user to the worklist.
185 void AddToWorklistWithUsers(SDNode *N) {
186 AddUsersToWorklist(N);
187 AddToWorklist(N);
188 }
189
190 // Prune potentially dangling nodes. This is called after
191 // any visit to a node, but should also be called during a visit after any
192 // failed combine which may have created a DAG node.
193 void clearAddedDanglingWorklistEntries() {
194 // Check any nodes added to the worklist to see if they are prunable.
195 while (!PruningList.empty()) {
196 auto *N = PruningList.pop_back_val();
197 if (N->use_empty())
198 recursivelyDeleteUnusedNodes(N);
199 }
200 }
201
202 SDNode *getNextWorklistEntry() {
203 // Before we do any work, remove nodes that are not in use.
204 clearAddedDanglingWorklistEntries();
205 SDNode *N = nullptr;
206 // The Worklist holds the SDNodes in order, but it may contain null
207 // entries.
208 while (!N && !Worklist.empty()) {
209 N = Worklist.pop_back_val();
210 }
211
212 if (N) {
213 bool GoodWorklistEntry = WorklistMap.erase(N);
214 (void)GoodWorklistEntry;
215 assert(GoodWorklistEntry &&((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 216, __PRETTY_FUNCTION__))
216 "Found a worklist entry without a corresponding map entry!")((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 216, __PRETTY_FUNCTION__))
;
217 }
218 return N;
219 }
220
221 /// Call the node-specific routine that folds each particular type of node.
222 SDValue visit(SDNode *N);
223
224 public:
225 DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
226 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
227 OptLevel(OL), AA(AA) {
228 ForCodeSize = DAG.shouldOptForSize();
229
230 MaximumLegalStoreInBits = 0;
231 // We use the minimum store size here, since that's all we can guarantee
232 // for the scalable vector types.
233 for (MVT VT : MVT::all_valuetypes())
234 if (EVT(VT).isSimple() && VT != MVT::Other &&
235 TLI.isTypeLegal(EVT(VT)) &&
236 VT.getSizeInBits().getKnownMinSize() >= MaximumLegalStoreInBits)
237 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinSize();
238 }
239
240 void ConsiderForPruning(SDNode *N) {
241 // Mark this for potential pruning.
242 PruningList.insert(N);
243 }
244
245 /// Add to the worklist making sure its instance is at the back (next to be
246 /// processed.)
247 void AddToWorklist(SDNode *N) {
248 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 249, __PRETTY_FUNCTION__))
249 "Deleted Node added to Worklist")((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 249, __PRETTY_FUNCTION__))
;
250
251 // Skip handle nodes as they can't usefully be combined and confuse the
252 // zero-use deletion strategy.
253 if (N->getOpcode() == ISD::HANDLENODE)
254 return;
255
256 ConsiderForPruning(N);
257
258 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
259 Worklist.push_back(N);
260 }
261
262 /// Remove all instances of N from the worklist.
263 void removeFromWorklist(SDNode *N) {
264 CombinedNodes.erase(N);
265 PruningList.remove(N);
266 StoreRootCountMap.erase(N);
267
268 auto It = WorklistMap.find(N);
269 if (It == WorklistMap.end())
270 return; // Not in the worklist.
271
272 // Null out the entry rather than erasing it to avoid a linear operation.
273 Worklist[It->second] = nullptr;
274 WorklistMap.erase(It);
275 }
276
277 void deleteAndRecombine(SDNode *N);
278 bool recursivelyDeleteUnusedNodes(SDNode *N);
279
280 /// Replaces all uses of the results of one DAG node with new values.
281 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
282 bool AddTo = true);
283
284 /// Replaces all uses of the results of one DAG node with new values.
285 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
286 return CombineTo(N, &Res, 1, AddTo);
287 }
288
289 /// Replaces all uses of the results of one DAG node with new values.
290 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
291 bool AddTo = true) {
292 SDValue To[] = { Res0, Res1 };
293 return CombineTo(N, To, 2, AddTo);
294 }
295
296 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
297
298 private:
299 unsigned MaximumLegalStoreInBits;
300
301 /// Check the specified integer node value to see if it can be simplified or
302 /// if things it uses can be simplified by bit propagation.
303 /// If so, return true.
304 bool SimplifyDemandedBits(SDValue Op) {
305 unsigned BitWidth = Op.getScalarValueSizeInBits();
306 APInt DemandedBits = APInt::getAllOnesValue(BitWidth);
307 return SimplifyDemandedBits(Op, DemandedBits);
308 }
309
310 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) {
311 EVT VT = Op.getValueType();
312 unsigned NumElts = VT.isVector() ? VT.getVectorNumElements() : 1;
313 APInt DemandedElts = APInt::getAllOnesValue(NumElts);
314 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts);
315 }
316
317 /// Check the specified vector node value to see if it can be simplified or
318 /// if things it uses can be simplified as it only uses some of the
319 /// elements. If so, return true.
320 bool SimplifyDemandedVectorElts(SDValue Op) {
321 unsigned NumElts = Op.getValueType().getVectorNumElements();
322 APInt DemandedElts = APInt::getAllOnesValue(NumElts);
323 return SimplifyDemandedVectorElts(Op, DemandedElts);
324 }
325
326 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
327 const APInt &DemandedElts,
328 bool AssumeSingleUse = false);
329 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
330 bool AssumeSingleUse = false);
331
332 bool CombineToPreIndexedLoadStore(SDNode *N);
333 bool CombineToPostIndexedLoadStore(SDNode *N);
334 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
335 bool SliceUpLoad(SDNode *N);
336
337 // Scalars have size 0 to distinguish from singleton vectors.
338 SDValue ForwardStoreValueToDirectLoad(LoadSDNode *LD);
339 bool getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val);
340 bool extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val);
341
342 /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
343 /// load.
344 ///
345 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
346 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
347 /// \param EltNo index of the vector element to load.
348 /// \param OriginalLoad load that EVE came from to be replaced.
349 /// \returns EVE on success SDValue() on failure.
350 SDValue scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT,
351 SDValue EltNo,
352 LoadSDNode *OriginalLoad);
353 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
354 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
355 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
356 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
357 SDValue PromoteIntBinOp(SDValue Op);
358 SDValue PromoteIntShiftOp(SDValue Op);
359 SDValue PromoteExtend(SDValue Op);
360 bool PromoteLoad(SDValue Op);
361
362 /// Call the node-specific routine that knows how to fold each
363 /// particular type of node. If that doesn't do anything, try the
364 /// target-specific DAG combines.
365 SDValue combine(SDNode *N);
366
367 // Visitation implementation - Implement dag node combining for different
368 // node types. The semantics are as follows:
369 // Return Value:
370 // SDValue.getNode() == 0 - No change was made
371 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
372 // otherwise - N should be replaced by the returned Operand.
373 //
374 SDValue visitTokenFactor(SDNode *N);
375 SDValue visitMERGE_VALUES(SDNode *N);
376 SDValue visitADD(SDNode *N);
377 SDValue visitADDLike(SDNode *N);
378 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
379 SDValue visitSUB(SDNode *N);
380 SDValue visitADDSAT(SDNode *N);
381 SDValue visitSUBSAT(SDNode *N);
382 SDValue visitADDC(SDNode *N);
383 SDValue visitADDO(SDNode *N);
384 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
385 SDValue visitSUBC(SDNode *N);
386 SDValue visitSUBO(SDNode *N);
387 SDValue visitADDE(SDNode *N);
388 SDValue visitADDCARRY(SDNode *N);
389 SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
390 SDValue visitSUBE(SDNode *N);
391 SDValue visitSUBCARRY(SDNode *N);
392 SDValue visitMUL(SDNode *N);
393 SDValue visitMULFIX(SDNode *N);
394 SDValue useDivRem(SDNode *N);
395 SDValue visitSDIV(SDNode *N);
396 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
397 SDValue visitUDIV(SDNode *N);
398 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
399 SDValue visitREM(SDNode *N);
400 SDValue visitMULHU(SDNode *N);
401 SDValue visitMULHS(SDNode *N);
402 SDValue visitSMUL_LOHI(SDNode *N);
403 SDValue visitUMUL_LOHI(SDNode *N);
404 SDValue visitMULO(SDNode *N);
405 SDValue visitIMINMAX(SDNode *N);
406 SDValue visitAND(SDNode *N);
407 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
408 SDValue visitOR(SDNode *N);
409 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
410 SDValue visitXOR(SDNode *N);
411 SDValue SimplifyVBinOp(SDNode *N);
412 SDValue visitSHL(SDNode *N);
413 SDValue visitSRA(SDNode *N);
414 SDValue visitSRL(SDNode *N);
415 SDValue visitFunnelShift(SDNode *N);
416 SDValue visitRotate(SDNode *N);
417 SDValue visitABS(SDNode *N);
418 SDValue visitBSWAP(SDNode *N);
419 SDValue visitBITREVERSE(SDNode *N);
420 SDValue visitCTLZ(SDNode *N);
421 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
422 SDValue visitCTTZ(SDNode *N);
423 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
424 SDValue visitCTPOP(SDNode *N);
425 SDValue visitSELECT(SDNode *N);
426 SDValue visitVSELECT(SDNode *N);
427 SDValue visitSELECT_CC(SDNode *N);
428 SDValue visitSETCC(SDNode *N);
429 SDValue visitSETCCCARRY(SDNode *N);
430 SDValue visitSIGN_EXTEND(SDNode *N);
431 SDValue visitZERO_EXTEND(SDNode *N);
432 SDValue visitANY_EXTEND(SDNode *N);
433 SDValue visitAssertExt(SDNode *N);
434 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
435 SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
436 SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
437 SDValue visitTRUNCATE(SDNode *N);
438 SDValue visitBITCAST(SDNode *N);
439 SDValue visitBUILD_PAIR(SDNode *N);
440 SDValue visitFADD(SDNode *N);
441 SDValue visitFSUB(SDNode *N);
442 SDValue visitFMUL(SDNode *N);
443 SDValue visitFMA(SDNode *N);
444 SDValue visitFDIV(SDNode *N);
445 SDValue visitFREM(SDNode *N);
446 SDValue visitFSQRT(SDNode *N);
447 SDValue visitFCOPYSIGN(SDNode *N);
448 SDValue visitFPOW(SDNode *N);
449 SDValue visitSINT_TO_FP(SDNode *N);
450 SDValue visitUINT_TO_FP(SDNode *N);
451 SDValue visitFP_TO_SINT(SDNode *N);
452 SDValue visitFP_TO_UINT(SDNode *N);
453 SDValue visitFP_ROUND(SDNode *N);
454 SDValue visitFP_EXTEND(SDNode *N);
455 SDValue visitFNEG(SDNode *N);
456 SDValue visitFABS(SDNode *N);
457 SDValue visitFCEIL(SDNode *N);
458 SDValue visitFTRUNC(SDNode *N);
459 SDValue visitFFLOOR(SDNode *N);
460 SDValue visitFMINNUM(SDNode *N);
461 SDValue visitFMAXNUM(SDNode *N);
462 SDValue visitFMINIMUM(SDNode *N);
463 SDValue visitFMAXIMUM(SDNode *N);
464 SDValue visitBRCOND(SDNode *N);
465 SDValue visitBR_CC(SDNode *N);
466 SDValue visitLOAD(SDNode *N);
467
468 SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
469 SDValue replaceStoreOfFPConstant(StoreSDNode *ST);
470
471 SDValue visitSTORE(SDNode *N);
472 SDValue visitLIFETIME_END(SDNode *N);
473 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
474 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
475 SDValue visitBUILD_VECTOR(SDNode *N);
476 SDValue visitCONCAT_VECTORS(SDNode *N);
477 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
478 SDValue visitVECTOR_SHUFFLE(SDNode *N);
479 SDValue visitSCALAR_TO_VECTOR(SDNode *N);
480 SDValue visitINSERT_SUBVECTOR(SDNode *N);
481 SDValue visitMLOAD(SDNode *N);
482 SDValue visitMSTORE(SDNode *N);
483 SDValue visitMGATHER(SDNode *N);
484 SDValue visitMSCATTER(SDNode *N);
485 SDValue visitFP_TO_FP16(SDNode *N);
486 SDValue visitFP16_TO_FP(SDNode *N);
487 SDValue visitVECREDUCE(SDNode *N);
488
489 SDValue visitFADDForFMACombine(SDNode *N);
490 SDValue visitFSUBForFMACombine(SDNode *N);
491 SDValue visitFMULForFMADistributiveCombine(SDNode *N);
492
493 SDValue XformToShuffleWithZero(SDNode *N);
494 bool reassociationCanBreakAddressingModePattern(unsigned Opc,
495 const SDLoc &DL, SDValue N0,
496 SDValue N1);
497 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
498 SDValue N1);
499 SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
500 SDValue N1, SDNodeFlags Flags);
501
502 SDValue visitShiftByConstant(SDNode *N);
503
504 SDValue foldSelectOfConstants(SDNode *N);
505 SDValue foldVSelectOfConstants(SDNode *N);
506 SDValue foldBinOpIntoSelect(SDNode *BO);
507 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
508 SDValue hoistLogicOpWithSameOpcodeHands(SDNode *N);
509 SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
510 SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
511 SDValue N2, SDValue N3, ISD::CondCode CC,
512 bool NotExtCompare = false);
513 SDValue convertSelectOfFPConstantsToLoadOffset(
514 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
515 ISD::CondCode CC);
516 SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
517 SDValue N2, SDValue N3, ISD::CondCode CC);
518 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
519 const SDLoc &DL);
520 SDValue unfoldMaskedMerge(SDNode *N);
521 SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
522 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
523 const SDLoc &DL, bool foldBooleans);
524 SDValue rebuildSetCC(SDValue N);
525
526 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
527 SDValue &CC, bool MatchStrict = false) const;
528 bool isOneUseSetCC(SDValue N) const;
529 bool isCheaperToUseNegatedFPOps(SDValue X, SDValue Y);
530
531 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
532 unsigned HiOp);
533 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
534 SDValue CombineExtLoad(SDNode *N);
535 SDValue CombineZExtLogicopShiftLoad(SDNode *N);
536 SDValue combineRepeatedFPDivisors(SDNode *N);
537 SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex);
538 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
539 SDValue BuildSDIV(SDNode *N);
540 SDValue BuildSDIVPow2(SDNode *N);
541 SDValue BuildUDIV(SDNode *N);
542 SDValue BuildLogBase2(SDValue V, const SDLoc &DL);
543 SDValue BuildDivEstimate(SDValue N, SDValue Op, SDNodeFlags Flags);
544 SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
545 SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
546 SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
547 SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations,
548 SDNodeFlags Flags, bool Reciprocal);
549 SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations,
550 SDNodeFlags Flags, bool Reciprocal);
551 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
552 bool DemandHighBits = true);
553 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
554 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
555 SDValue InnerPos, SDValue InnerNeg,
556 unsigned PosOpcode, unsigned NegOpcode,
557 const SDLoc &DL);
558 SDValue MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
559 SDValue MatchLoadCombine(SDNode *N);
560 SDValue MatchStoreCombine(StoreSDNode *N);
561 SDValue ReduceLoadWidth(SDNode *N);
562 SDValue ReduceLoadOpStoreWidth(SDNode *N);
563 SDValue splitMergedValStore(StoreSDNode *ST);
564 SDValue TransformFPLoadStorePair(SDNode *N);
565 SDValue convertBuildVecZextToZext(SDNode *N);
566 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
567 SDValue reduceBuildVecTruncToBitCast(SDNode *N);
568 SDValue reduceBuildVecToShuffle(SDNode *N);
569 SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
570 ArrayRef<int> VectorMask, SDValue VecIn1,
571 SDValue VecIn2, unsigned LeftIdx,
572 bool DidSplitVec);
573 SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast);
574
575 /// Walk up chain skipping non-aliasing memory nodes,
576 /// looking for aliasing nodes and adding them to the Aliases vector.
577 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
578 SmallVectorImpl<SDValue> &Aliases);
579
580 /// Return true if there is any possibility that the two addresses overlap.
581 bool isAlias(SDNode *Op0, SDNode *Op1) const;
582
583 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
584 /// chain (aliasing node.)
585 SDValue FindBetterChain(SDNode *N, SDValue Chain);
586
587 /// Try to replace a store and any possibly adjacent stores on
588 /// consecutive chains with better chains. Return true only if St is
589 /// replaced.
590 ///
591 /// Notice that other chains may still be replaced even if the function
592 /// returns false.
593 bool findBetterNeighborChains(StoreSDNode *St);
594
595 // Helper for findBetterNeighborChains. Walk up store chain add additional
596 // chained stores that do not overlap and can be parallelized.
597 bool parallelizeChainedStores(StoreSDNode *St);
598
599 /// Holds a pointer to an LSBaseSDNode as well as information on where it
600 /// is located in a sequence of memory operations connected by a chain.
601 struct MemOpLink {
602 // Ptr to the mem node.
603 LSBaseSDNode *MemNode;
604
605 // Offset from the base ptr.
606 int64_t OffsetFromBase;
607
608 MemOpLink(LSBaseSDNode *N, int64_t Offset)
609 : MemNode(N), OffsetFromBase(Offset) {}
610 };
611
612 /// This is a helper function for visitMUL to check the profitability
613 /// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
614 /// MulNode is the original multiply, AddNode is (add x, c1),
615 /// and ConstNode is c2.
616 bool isMulAddWithConstProfitable(SDNode *MulNode,
617 SDValue &AddNode,
618 SDValue &ConstNode);
619
620 /// This is a helper function for visitAND and visitZERO_EXTEND. Returns
621 /// true if the (and (load x) c) pattern matches an extload. ExtVT returns
622 /// the type of the loaded value to be extended.
623 bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
624 EVT LoadResultTy, EVT &ExtVT);
625
626 /// Helper function to calculate whether the given Load/Store can have its
627 /// width reduced to ExtVT.
628 bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType,
629 EVT &MemVT, unsigned ShAmt = 0);
630
631 /// Used by BackwardsPropagateMask to find suitable loads.
632 bool SearchForAndLoads(SDNode *N, SmallVectorImpl<LoadSDNode*> &Loads,
633 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
634 ConstantSDNode *Mask, SDNode *&NodeToMask);
635 /// Attempt to propagate a given AND node back to load leaves so that they
636 /// can be combined into narrow loads.
637 bool BackwardsPropagateMask(SDNode *N);
638
639 /// Helper function for MergeConsecutiveStores which merges the
640 /// component store chains.
641 SDValue getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
642 unsigned NumStores);
643
644 /// This is a helper function for MergeConsecutiveStores. When the
645 /// source elements of the consecutive stores are all constants or
646 /// all extracted vector elements, try to merge them into one
647 /// larger store introducing bitcasts if necessary. \return True
648 /// if a merged store was created.
649 bool MergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
650 EVT MemVT, unsigned NumStores,
651 bool IsConstantSrc, bool UseVector,
652 bool UseTrunc);
653
654 /// This is a helper function for MergeConsecutiveStores. Stores
655 /// that potentially may be merged with St are placed in
656 /// StoreNodes. RootNode is a chain predecessor to all store
657 /// candidates.
658 void getStoreMergeCandidates(StoreSDNode *St,
659 SmallVectorImpl<MemOpLink> &StoreNodes,
660 SDNode *&Root);
661
662 /// Helper function for MergeConsecutiveStores. Checks if
663 /// candidate stores have indirect dependency through their
664 /// operands. RootNode is the predecessor to all stores calculated
665 /// by getStoreMergeCandidates and is used to prune the dependency check.
666 /// \return True if safe to merge.
667 bool checkMergeStoreCandidatesForDependencies(
668 SmallVectorImpl<MemOpLink> &StoreNodes, unsigned NumStores,
669 SDNode *RootNode);
670
671 /// Merge consecutive store operations into a wide store.
672 /// This optimization uses wide integers or vectors when possible.
673 /// \return number of stores that were merged into a merged store (the
674 /// affected nodes are stored as a prefix in \p StoreNodes).
675 bool MergeConsecutiveStores(StoreSDNode *St);
676
677 /// Try to transform a truncation where C is a constant:
678 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
679 ///
680 /// \p N needs to be a truncation and its first operand an AND. Other
681 /// requirements are checked by the function (e.g. that trunc is
682 /// single-use) and if missed an empty SDValue is returned.
683 SDValue distributeTruncateThroughAnd(SDNode *N);
684
685 /// Helper function to determine whether the target supports operation
686 /// given by \p Opcode for type \p VT, that is, whether the operation
687 /// is legal or custom before legalizing operations, and whether is
688 /// legal (but not custom) after legalization.
689 bool hasOperation(unsigned Opcode, EVT VT) {
690 if (LegalOperations)
691 return TLI.isOperationLegal(Opcode, VT);
692 return TLI.isOperationLegalOrCustom(Opcode, VT);
693 }
694
695 public:
696 /// Runs the dag combiner on all nodes in the work list
697 void Run(CombineLevel AtLevel);
698
699 SelectionDAG &getDAG() const { return DAG; }
700
701 /// Returns a type large enough to hold any valid shift amount - before type
702 /// legalization these can be huge.
703 EVT getShiftAmountTy(EVT LHSTy) {
704 assert(LHSTy.isInteger() && "Shift amount is not an integer type!")((LHSTy.isInteger() && "Shift amount is not an integer type!"
) ? static_cast<void> (0) : __assert_fail ("LHSTy.isInteger() && \"Shift amount is not an integer type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 704, __PRETTY_FUNCTION__))
;
705 return TLI.getShiftAmountTy(LHSTy, DAG.getDataLayout(), LegalTypes);
706 }
707
708 /// This method returns true if we are running before type legalization or
709 /// if the specified VT is legal.
710 bool isTypeLegal(const EVT &VT) {
711 if (!LegalTypes) return true;
712 return TLI.isTypeLegal(VT);
713 }
714
715 /// Convenience wrapper around TargetLowering::getSetCCResultType
716 EVT getSetCCResultType(EVT VT) const {
717 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
718 }
719
720 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
721 SDValue OrigLoad, SDValue ExtLoad,
722 ISD::NodeType ExtType);
723 };
724
725/// This class is a DAGUpdateListener that removes any deleted
726/// nodes from the worklist.
727class WorklistRemover : public SelectionDAG::DAGUpdateListener {
728 DAGCombiner &DC;
729
730public:
731 explicit WorklistRemover(DAGCombiner &dc)
732 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
733
734 void NodeDeleted(SDNode *N, SDNode *E) override {
735 DC.removeFromWorklist(N);
736 }
737};
738
739class WorklistInserter : public SelectionDAG::DAGUpdateListener {
740 DAGCombiner &DC;
741
742public:
743 explicit WorklistInserter(DAGCombiner &dc)
744 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
745
746 // FIXME: Ideally we could add N to the worklist, but this causes exponential
747 // compile time costs in large DAGs, e.g. Halide.
748 void NodeInserted(SDNode *N) override { DC.ConsiderForPruning(N); }
749};
750
751} // end anonymous namespace
752
753//===----------------------------------------------------------------------===//
754// TargetLowering::DAGCombinerInfo implementation
755//===----------------------------------------------------------------------===//
756
757void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
758 ((DAGCombiner*)DC)->AddToWorklist(N);
759}
760
761SDValue TargetLowering::DAGCombinerInfo::
762CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
763 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
764}
765
766SDValue TargetLowering::DAGCombinerInfo::
767CombineTo(SDNode *N, SDValue Res, bool AddTo) {
768 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
769}
770
771SDValue TargetLowering::DAGCombinerInfo::
772CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
773 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
774}
775
776bool TargetLowering::DAGCombinerInfo::
777recursivelyDeleteUnusedNodes(SDNode *N) {
778 return ((DAGCombiner*)DC)->recursivelyDeleteUnusedNodes(N);
779}
780
781void TargetLowering::DAGCombinerInfo::
782CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
783 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
784}
785
786//===----------------------------------------------------------------------===//
787// Helper Functions
788//===----------------------------------------------------------------------===//
789
790void DAGCombiner::deleteAndRecombine(SDNode *N) {
791 removeFromWorklist(N);
792
793 // If the operands of this node are only used by the node, they will now be
794 // dead. Make sure to re-visit them and recursively delete dead nodes.
795 for (const SDValue &Op : N->ops())
796 // For an operand generating multiple values, one of the values may
797 // become dead allowing further simplification (e.g. split index
798 // arithmetic from an indexed load).
799 if (Op->hasOneUse() || Op->getNumValues() > 1)
800 AddToWorklist(Op.getNode());
801
802 DAG.DeleteNode(N);
803}
804
805// APInts must be the same size for most operations, this helper
806// function zero extends the shorter of the pair so that they match.
807// We provide an Offset so that we can create bitwidths that won't overflow.
808static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) {
809 unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth());
810 LHS = LHS.zextOrSelf(Bits);
811 RHS = RHS.zextOrSelf(Bits);
812}
813
814// Return true if this node is a setcc, or is a select_cc
815// that selects between the target values used for true and false, making it
816// equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
817// the appropriate nodes based on the type of node we are checking. This
818// simplifies life a bit for the callers.
819bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
820 SDValue &CC, bool MatchStrict) const {
821 if (N.getOpcode() == ISD::SETCC) {
822 LHS = N.getOperand(0);
823 RHS = N.getOperand(1);
824 CC = N.getOperand(2);
825 return true;
826 }
827
828 if (MatchStrict &&
829 (N.getOpcode() == ISD::STRICT_FSETCC ||
830 N.getOpcode() == ISD::STRICT_FSETCCS)) {
831 LHS = N.getOperand(1);
832 RHS = N.getOperand(2);
833 CC = N.getOperand(3);
834 return true;
835 }
836
837 if (N.getOpcode() != ISD::SELECT_CC ||
838 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
839 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
840 return false;
841
842 if (TLI.getBooleanContents(N.getValueType()) ==
843 TargetLowering::UndefinedBooleanContent)
844 return false;
845
846 LHS = N.getOperand(0);
847 RHS = N.getOperand(1);
848 CC = N.getOperand(4);
849 return true;
850}
851
852/// Return true if this is a SetCC-equivalent operation with only one use.
853/// If this is true, it allows the users to invert the operation for free when
854/// it is profitable to do so.
855bool DAGCombiner::isOneUseSetCC(SDValue N) const {
856 SDValue N0, N1, N2;
857 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
858 return true;
859 return false;
860}
861
862// Returns the SDNode if it is a constant float BuildVector
863// or constant float.
864static SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) {
865 if (isa<ConstantFPSDNode>(N))
866 return N.getNode();
867 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
868 return N.getNode();
869 return nullptr;
870}
871
872// Determines if it is a constant integer or a build vector of constant
873// integers (and undefs).
874// Do not permit build vector implicit truncation.
875static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) {
876 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N))
877 return !(Const->isOpaque() && NoOpaques);
878 if (N.getOpcode() != ISD::BUILD_VECTOR)
879 return false;
880 unsigned BitWidth = N.getScalarValueSizeInBits();
881 for (const SDValue &Op : N->op_values()) {
882 if (Op.isUndef())
883 continue;
884 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op);
885 if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth ||
886 (Const->isOpaque() && NoOpaques))
887 return false;
888 }
889 return true;
890}
891
892// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with
893// undef's.
894static bool isAnyConstantBuildVector(SDValue V, bool NoOpaques = false) {
895 if (V.getOpcode() != ISD::BUILD_VECTOR)
896 return false;
897 return isConstantOrConstantVector(V, NoOpaques) ||
898 ISD::isBuildVectorOfConstantFPSDNodes(V.getNode());
899}
900
901bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc,
902 const SDLoc &DL,
903 SDValue N0,
904 SDValue N1) {
905 // Currently this only tries to ensure we don't undo the GEP splits done by
906 // CodeGenPrepare when shouldConsiderGEPOffsetSplit is true. To ensure this,
907 // we check if the following transformation would be problematic:
908 // (load/store (add, (add, x, offset1), offset2)) ->
909 // (load/store (add, x, offset1+offset2)).
910
911 if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD)
912 return false;
913
914 if (N0.hasOneUse())
915 return false;
916
917 auto *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
918 auto *C2 = dyn_cast<ConstantSDNode>(N1);
919 if (!C1 || !C2)
920 return false;
921
922 const APInt &C1APIntVal = C1->getAPIntValue();
923 const APInt &C2APIntVal = C2->getAPIntValue();
924 if (C1APIntVal.getBitWidth() > 64 || C2APIntVal.getBitWidth() > 64)
925 return false;
926
927 const APInt CombinedValueIntVal = C1APIntVal + C2APIntVal;
928 if (CombinedValueIntVal.getBitWidth() > 64)
929 return false;
930 const int64_t CombinedValue = CombinedValueIntVal.getSExtValue();
931
932 for (SDNode *Node : N0->uses()) {
933 auto LoadStore = dyn_cast<MemSDNode>(Node);
934 if (LoadStore) {
935 // Is x[offset2] already not a legal addressing mode? If so then
936 // reassociating the constants breaks nothing (we test offset2 because
937 // that's the one we hope to fold into the load or store).
938 TargetLoweringBase::AddrMode AM;
939 AM.HasBaseReg = true;
940 AM.BaseOffs = C2APIntVal.getSExtValue();
941 EVT VT = LoadStore->getMemoryVT();
942 unsigned AS = LoadStore->getAddressSpace();
943 Type *AccessTy = VT.getTypeForEVT(*DAG.getContext());
944 if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
945 continue;
946
947 // Would x[offset1+offset2] still be a legal addressing mode?
948 AM.BaseOffs = CombinedValue;
949 if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
950 return true;
951 }
952 }
953
954 return false;
955}
956
957// Helper for DAGCombiner::reassociateOps. Try to reassociate an expression
958// such as (Opc N0, N1), if \p N0 is the same kind of operation as \p Opc.
959SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
960 SDValue N0, SDValue N1) {
961 EVT VT = N0.getValueType();
962
963 if (N0.getOpcode() != Opc)
964 return SDValue();
965
966 // Don't reassociate reductions.
967 if (N0->getFlags().hasVectorReduction())
968 return SDValue();
969
970 if (DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
971 if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
972 // Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
973 if (SDValue OpNode =
974 DAG.FoldConstantArithmetic(Opc, DL, VT, {N0.getOperand(1), N1}))
975 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
976 return SDValue();
977 }
978 if (N0.hasOneUse()) {
979 // Reassociate: (op (op x, c1), y) -> (op (op x, y), c1)
980 // iff (op x, c1) has one use
981 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
982 if (!OpNode.getNode())
983 return SDValue();
984 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
985 }
986 }
987 return SDValue();
988}
989
990// Try to reassociate commutative binops.
991SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
992 SDValue N1, SDNodeFlags Flags) {
993 assert(TLI.isCommutativeBinOp(Opc) && "Operation not commutative.")((TLI.isCommutativeBinOp(Opc) && "Operation not commutative."
) ? static_cast<void> (0) : __assert_fail ("TLI.isCommutativeBinOp(Opc) && \"Operation not commutative.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 993, __PRETTY_FUNCTION__))
;
994 // Don't reassociate reductions.
995 if (Flags.hasVectorReduction())
996 return SDValue();
997
998 // Floating-point reassociation is not allowed without loose FP math.
999 if (N0.getValueType().isFloatingPoint() ||
1000 N1.getValueType().isFloatingPoint())
1001 if (!Flags.hasAllowReassociation() || !Flags.hasNoSignedZeros())
1002 return SDValue();
1003
1004 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1))
1005 return Combined;
1006 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0))
1007 return Combined;
1008 return SDValue();
1009}
1010
1011SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
1012 bool AddTo) {
1013 assert(N->getNumValues() == NumTo && "Broken CombineTo call!")((N->getNumValues() == NumTo && "Broken CombineTo call!"
) ? static_cast<void> (0) : __assert_fail ("N->getNumValues() == NumTo && \"Broken CombineTo call!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1013, __PRETTY_FUNCTION__))
;
1014 ++NodesCombined;
1015 LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1016 To[0].getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1017 dbgs() << " and " << NumTo - 1 << " other values\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
;
1018 for (unsigned i = 0, e = NumTo; i != e; ++i)
1019 assert((!To[i].getNode() ||(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1021, __PRETTY_FUNCTION__))
1020 N->getValueType(i) == To[i].getValueType()) &&(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1021, __PRETTY_FUNCTION__))
1021 "Cannot combine value to value of different type!")(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1021, __PRETTY_FUNCTION__))
;
1022
1023 WorklistRemover DeadNodes(*this);
1024 DAG.ReplaceAllUsesWith(N, To);
1025 if (AddTo) {
1026 // Push the new nodes and any users onto the worklist
1027 for (unsigned i = 0, e = NumTo; i != e; ++i) {
1028 if (To[i].getNode()) {
1029 AddToWorklist(To[i].getNode());
1030 AddUsersToWorklist(To[i].getNode());
1031 }
1032 }
1033 }
1034
1035 // Finally, if the node is now dead, remove it from the graph. The node
1036 // may not be dead if the replacement process recursively simplified to
1037 // something else needing this node.
1038 if (N->use_empty())
1039 deleteAndRecombine(N);
1040 return SDValue(N, 0);
1041}
1042
1043void DAGCombiner::
1044CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
1045 // Replace all uses. If any nodes become isomorphic to other nodes and
1046 // are deleted, make sure to remove them from our worklist.
1047 WorklistRemover DeadNodes(*this);
1048 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
1049
1050 // Push the new node and any (possibly new) users onto the worklist.
1051 AddToWorklistWithUsers(TLO.New.getNode());
1052
1053 // Finally, if the node is now dead, remove it from the graph. The node
1054 // may not be dead if the replacement process recursively simplified to
1055 // something else needing this node.
1056 if (TLO.Old.getNode()->use_empty())
1057 deleteAndRecombine(TLO.Old.getNode());
1058}
1059
1060/// Check the specified integer node value to see if it can be simplified or if
1061/// things it uses can be simplified by bit propagation. If so, return true.
1062bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
1063 const APInt &DemandedElts,
1064 bool AssumeSingleUse) {
1065 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1066 KnownBits Known;
1067 if (!TLI.SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, 0,
1068 AssumeSingleUse))
1069 return false;
1070
1071 // Revisit the node.
1072 AddToWorklist(Op.getNode());
1073
1074 // Replace the old value with the new one.
1075 ++NodesCombined;
1076 LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1077 dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1078 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
;
1079
1080 CommitTargetLoweringOpt(TLO);
1081 return true;
1082}
1083
1084/// Check the specified vector node value to see if it can be simplified or
1085/// if things it uses can be simplified as it only uses some of the elements.
1086/// If so, return true.
1087bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op,
1088 const APInt &DemandedElts,
1089 bool AssumeSingleUse) {
1090 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1091 APInt KnownUndef, KnownZero;
1092 if (!TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero,
1093 TLO, 0, AssumeSingleUse))
1094 return false;
1095
1096 // Revisit the node.
1097 AddToWorklist(Op.getNode());
1098
1099 // Replace the old value with the new one.
1100 ++NodesCombined;
1101 LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1102 dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1103 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
;
1104
1105 CommitTargetLoweringOpt(TLO);
1106 return true;
1107}
1108
1109void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
1110 SDLoc DL(Load);
1111 EVT VT = Load->getValueType(0);
1112 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0));
1113
1114 LLVM_DEBUG(dbgs() << "\nReplacing.9 "; Load->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
1115 Trunc.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
;
1116 WorklistRemover DeadNodes(*this);
1117 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
1118 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
1119 deleteAndRecombine(Load);
1120 AddToWorklist(Trunc.getNode());
1121}
1122
1123SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
1124 Replace = false;
1125 SDLoc DL(Op);
1126 if (ISD::isUNINDEXEDLoad(Op.getNode())) {
1127 LoadSDNode *LD = cast<LoadSDNode>(Op);
1128 EVT MemVT = LD->getMemoryVT();
1129 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1130 : LD->getExtensionType();
1131 Replace = true;
1132 return DAG.getExtLoad(ExtType, DL, PVT,
1133 LD->getChain(), LD->getBasePtr(),
1134 MemVT, LD->getMemOperand());
1135 }
1136
1137 unsigned Opc = Op.getOpcode();
1138 switch (Opc) {
1139 default: break;
1140 case ISD::AssertSext:
1141 if (SDValue Op0 = SExtPromoteOperand(Op.getOperand(0), PVT))
1142 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1));
1143 break;
1144 case ISD::AssertZext:
1145 if (SDValue Op0 = ZExtPromoteOperand(Op.getOperand(0), PVT))
1146 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1));
1147 break;
1148 case ISD::Constant: {
1149 unsigned ExtOpc =
1150 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1151 return DAG.getNode(ExtOpc, DL, PVT, Op);
1152 }
1153 }
1154
1155 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
1156 return SDValue();
1157 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op);
1158}
1159
1160SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
1161 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
1162 return SDValue();
1163 EVT OldVT = Op.getValueType();
1164 SDLoc DL(Op);
1165 bool Replace = false;
1166 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1167 if (!NewOp.getNode())
1168 return SDValue();
1169 AddToWorklist(NewOp.getNode());
1170
1171 if (Replace)
1172 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1173 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp,
1174 DAG.getValueType(OldVT));
1175}
1176
1177SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
1178 EVT OldVT = Op.getValueType();
1179 SDLoc DL(Op);
1180 bool Replace = false;
1181 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1182 if (!NewOp.getNode())
1183 return SDValue();
1184 AddToWorklist(NewOp.getNode());
1185
1186 if (Replace)
1187 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1188 return DAG.getZeroExtendInReg(NewOp, DL, OldVT);
1189}
1190
1191/// Promote the specified integer binary operation if the target indicates it is
1192/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1193/// i32 since i16 instructions are longer.
1194SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
1195 if (!LegalOperations)
1196 return SDValue();
1197
1198 EVT VT = Op.getValueType();
1199 if (VT.isVector() || !VT.isInteger())
1200 return SDValue();
1201
1202 // If operation type is 'undesirable', e.g. i16 on x86, consider
1203 // promoting it.
1204 unsigned Opc = Op.getOpcode();
1205 if (TLI.isTypeDesirableForOp(Opc, VT))
1206 return SDValue();
1207
1208 EVT PVT = VT;
1209 // Consult target whether it is a good idea to promote this operation and
1210 // what's the right type to promote it to.
1211 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1212 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1212, __PRETTY_FUNCTION__))
;
1213
1214 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1215
1216 bool Replace0 = false;
1217 SDValue N0 = Op.getOperand(0);
1218 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1219
1220 bool Replace1 = false;
1221 SDValue N1 = Op.getOperand(1);
1222 SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
1223 SDLoc DL(Op);
1224
1225 SDValue RV =
1226 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1));
1227
1228 // We are always replacing N0/N1's use in N and only need
1229 // additional replacements if there are additional uses.
1230 Replace0 &= !N0->hasOneUse();
1231 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1232
1233 // Combine Op here so it is preserved past replacements.
1234 CombineTo(Op.getNode(), RV);
1235
1236 // If operands have a use ordering, make sure we deal with
1237 // predecessor first.
1238 if (Replace0 && Replace1 && N0.getNode()->isPredecessorOf(N1.getNode())) {
1239 std::swap(N0, N1);
1240 std::swap(NN0, NN1);
1241 }
1242
1243 if (Replace0) {
1244 AddToWorklist(NN0.getNode());
1245 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1246 }
1247 if (Replace1) {
1248 AddToWorklist(NN1.getNode());
1249 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1250 }
1251 return Op;
1252 }
1253 return SDValue();
1254}
1255
1256/// Promote the specified integer shift operation if the target indicates it is
1257/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1258/// i32 since i16 instructions are longer.
1259SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1260 if (!LegalOperations)
1261 return SDValue();
1262
1263 EVT VT = Op.getValueType();
1264 if (VT.isVector() || !VT.isInteger())
1265 return SDValue();
1266
1267 // If operation type is 'undesirable', e.g. i16 on x86, consider
1268 // promoting it.
1269 unsigned Opc = Op.getOpcode();
1270 if (TLI.isTypeDesirableForOp(Opc, VT))
1271 return SDValue();
1272
1273 EVT PVT = VT;
1274 // Consult target whether it is a good idea to promote this operation and
1275 // what's the right type to promote it to.
1276 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1277 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1277, __PRETTY_FUNCTION__))
;
1278
1279 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1280
1281 bool Replace = false;
1282 SDValue N0 = Op.getOperand(0);
1283 SDValue N1 = Op.getOperand(1);
1284 if (Opc == ISD::SRA)
1285 N0 = SExtPromoteOperand(N0, PVT);
1286 else if (Opc == ISD::SRL)
1287 N0 = ZExtPromoteOperand(N0, PVT);
1288 else
1289 N0 = PromoteOperand(N0, PVT, Replace);
1290
1291 if (!N0.getNode())
1292 return SDValue();
1293
1294 SDLoc DL(Op);
1295 SDValue RV =
1296 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
1297
1298 if (Replace)
1299 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1300
1301 // Deal with Op being deleted.
1302 if (Op && Op.getOpcode() != ISD::DELETED_NODE)
1303 return RV;
1304 }
1305 return SDValue();
1306}
1307
1308SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1309 if (!LegalOperations)
1310 return SDValue();
1311
1312 EVT VT = Op.getValueType();
1313 if (VT.isVector() || !VT.isInteger())
1314 return SDValue();
1315
1316 // If operation type is 'undesirable', e.g. i16 on x86, consider
1317 // promoting it.
1318 unsigned Opc = Op.getOpcode();
1319 if (TLI.isTypeDesirableForOp(Opc, VT))
1320 return SDValue();
1321
1322 EVT PVT = VT;
1323 // Consult target whether it is a good idea to promote this operation and
1324 // what's the right type to promote it to.
1325 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1326 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1326, __PRETTY_FUNCTION__))
;
1327 // fold (aext (aext x)) -> (aext x)
1328 // fold (aext (zext x)) -> (zext x)
1329 // fold (aext (sext x)) -> (sext x)
1330 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1331 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1332 }
1333 return SDValue();
1334}
1335
1336bool DAGCombiner::PromoteLoad(SDValue Op) {
1337 if (!LegalOperations)
1338 return false;
1339
1340 if (!ISD::isUNINDEXEDLoad(Op.getNode()))
1341 return false;
1342
1343 EVT VT = Op.getValueType();
1344 if (VT.isVector() || !VT.isInteger())
1345 return false;
1346
1347 // If operation type is 'undesirable', e.g. i16 on x86, consider
1348 // promoting it.
1349 unsigned Opc = Op.getOpcode();
1350 if (TLI.isTypeDesirableForOp(Opc, VT))
1351 return false;
1352
1353 EVT PVT = VT;
1354 // Consult target whether it is a good idea to promote this operation and
1355 // what's the right type to promote it to.
1356 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1357 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1357, __PRETTY_FUNCTION__))
;
1358
1359 SDLoc DL(Op);
1360 SDNode *N = Op.getNode();
1361 LoadSDNode *LD = cast<LoadSDNode>(N);
1362 EVT MemVT = LD->getMemoryVT();
1363 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1364 : LD->getExtensionType();
1365 SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT,
1366 LD->getChain(), LD->getBasePtr(),
1367 MemVT, LD->getMemOperand());
1368 SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1369
1370 LLVM_DEBUG(dbgs() << "\nPromoting "; N->dump(&DAG); dbgs() << "\nTo: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
1371 Result.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
;
1372 WorklistRemover DeadNodes(*this);
1373 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1374 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1375 deleteAndRecombine(N);
1376 AddToWorklist(Result.getNode());
1377 return true;
1378 }
1379 return false;
1380}
1381
1382/// Recursively delete a node which has no uses and any operands for
1383/// which it is the only use.
1384///
1385/// Note that this both deletes the nodes and removes them from the worklist.
1386/// It also adds any nodes who have had a user deleted to the worklist as they
1387/// may now have only one use and subject to other combines.
1388bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1389 if (!N->use_empty())
1390 return false;
1391
1392 SmallSetVector<SDNode *, 16> Nodes;
1393 Nodes.insert(N);
1394 do {
1395 N = Nodes.pop_back_val();
1396 if (!N)
1397 continue;
1398
1399 if (N->use_empty()) {
1400 for (const SDValue &ChildN : N->op_values())
1401 Nodes.insert(ChildN.getNode());
1402
1403 removeFromWorklist(N);
1404 DAG.DeleteNode(N);
1405 } else {
1406 AddToWorklist(N);
1407 }
1408 } while (!Nodes.empty());
1409 return true;
1410}
1411
1412//===----------------------------------------------------------------------===//
1413// Main DAG Combiner implementation
1414//===----------------------------------------------------------------------===//
1415
1416void DAGCombiner::Run(CombineLevel AtLevel) {
1417 // set the instance variables, so that the various visit routines may use it.
1418 Level = AtLevel;
1419 LegalDAG = Level >= AfterLegalizeDAG;
1420 LegalOperations = Level >= AfterLegalizeVectorOps;
1421 LegalTypes = Level >= AfterLegalizeTypes;
1422
1423 WorklistInserter AddNodes(*this);
1424
1425 // Add all the dag nodes to the worklist.
1426 for (SDNode &Node : DAG.allnodes())
1427 AddToWorklist(&Node);
1428
1429 // Create a dummy node (which is not added to allnodes), that adds a reference
1430 // to the root node, preventing it from being deleted, and tracking any
1431 // changes of the root.
1432 HandleSDNode Dummy(DAG.getRoot());
1433
1434 // While we have a valid worklist entry node, try to combine it.
1435 while (SDNode *N = getNextWorklistEntry()) {
1436 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1437 // N is deleted from the DAG, since they too may now be dead or may have a
1438 // reduced number of uses, allowing other xforms.
1439 if (recursivelyDeleteUnusedNodes(N))
1440 continue;
1441
1442 WorklistRemover DeadNodes(*this);
1443
1444 // If this combine is running after legalizing the DAG, re-legalize any
1445 // nodes pulled off the worklist.
1446 if (LegalDAG) {
1447 SmallSetVector<SDNode *, 16> UpdatedNodes;
1448 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1449
1450 for (SDNode *LN : UpdatedNodes)
1451 AddToWorklistWithUsers(LN);
1452
1453 if (!NIsValid)
1454 continue;
1455 }
1456
1457 LLVM_DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nCombining: "; N->dump
(&DAG); } } while (false)
;
1458
1459 // Add any operands of the new node which have not yet been combined to the
1460 // worklist as well. Because the worklist uniques things already, this
1461 // won't repeatedly process the same operand.
1462 CombinedNodes.insert(N);
1463 for (const SDValue &ChildN : N->op_values())
1464 if (!CombinedNodes.count(ChildN.getNode()))
1465 AddToWorklist(ChildN.getNode());
1466
1467 SDValue RV = combine(N);
1468
1469 if (!RV.getNode())
1470 continue;
1471
1472 ++NodesCombined;
1473
1474 // If we get back the same node we passed in, rather than a new node or
1475 // zero, we know that the node must have defined multiple values and
1476 // CombineTo was used. Since CombineTo takes care of the worklist
1477 // mechanics for us, we have no work to do in this case.
1478 if (RV.getNode() == N)
1479 continue;
1480
1481 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1483, __PRETTY_FUNCTION__))
1482 RV.getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1483, __PRETTY_FUNCTION__))
1483 "Node was deleted but visit returned new node!")((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1483, __PRETTY_FUNCTION__))
;
1484
1485 LLVM_DEBUG(dbgs() << " ... into: "; RV.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << " ... into: "; RV.getNode()
->dump(&DAG); } } while (false)
;
1486
1487 if (N->getNumValues() == RV.getNode()->getNumValues())
1488 DAG.ReplaceAllUsesWith(N, RV.getNode());
1489 else {
1490 assert(N->getValueType(0) == RV.getValueType() &&((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1491, __PRETTY_FUNCTION__))
1491 N->getNumValues() == 1 && "Type mismatch")((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1491, __PRETTY_FUNCTION__))
;
1492 DAG.ReplaceAllUsesWith(N, &RV);
1493 }
1494
1495 // Push the new node and any users onto the worklist
1496 AddToWorklist(RV.getNode());
1497 AddUsersToWorklist(RV.getNode());
1498
1499 // Finally, if the node is now dead, remove it from the graph. The node
1500 // may not be dead if the replacement process recursively simplified to
1501 // something else needing this node. This will also take care of adding any
1502 // operands which have lost a user to the worklist.
1503 recursivelyDeleteUnusedNodes(N);
1504 }
1505
1506 // If the root changed (e.g. it was a dead load, update the root).
1507 DAG.setRoot(Dummy.getValue());
1508 DAG.RemoveDeadNodes();
1509}
1510
1511SDValue DAGCombiner::visit(SDNode *N) {
1512 switch (N->getOpcode()) {
1513 default: break;
1514 case ISD::TokenFactor: return visitTokenFactor(N);
1515 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1516 case ISD::ADD: return visitADD(N);
1517 case ISD::SUB: return visitSUB(N);
1518 case ISD::SADDSAT:
1519 case ISD::UADDSAT: return visitADDSAT(N);
1520 case ISD::SSUBSAT:
1521 case ISD::USUBSAT: return visitSUBSAT(N);
1522 case ISD::ADDC: return visitADDC(N);
1523 case ISD::SADDO:
1524 case ISD::UADDO: return visitADDO(N);
1525 case ISD::SUBC: return visitSUBC(N);
1526 case ISD::SSUBO:
1527 case ISD::USUBO: return visitSUBO(N);
1528 case ISD::ADDE: return visitADDE(N);
1529 case ISD::ADDCARRY: return visitADDCARRY(N);
1530 case ISD::SUBE: return visitSUBE(N);
1531 case ISD::SUBCARRY: return visitSUBCARRY(N);
1532 case ISD::SMULFIX:
1533 case ISD::SMULFIXSAT:
1534 case ISD::UMULFIX:
1535 case ISD::UMULFIXSAT: return visitMULFIX(N);
1536 case ISD::MUL: return visitMUL(N);
1537 case ISD::SDIV: return visitSDIV(N);
1538 case ISD::UDIV: return visitUDIV(N);
1539 case ISD::SREM:
1540 case ISD::UREM: return visitREM(N);
1541 case ISD::MULHU: return visitMULHU(N);
1542 case ISD::MULHS: return visitMULHS(N);
1543 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1544 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1545 case ISD::SMULO:
1546 case ISD::UMULO: return visitMULO(N);
1547 case ISD::SMIN:
1548 case ISD::SMAX:
1549 case ISD::UMIN:
1550 case ISD::UMAX: return visitIMINMAX(N);
1551 case ISD::AND: return visitAND(N);
1552 case ISD::OR: return visitOR(N);
1553 case ISD::XOR: return visitXOR(N);
1554 case ISD::SHL: return visitSHL(N);
1555 case ISD::SRA: return visitSRA(N);
1556 case ISD::SRL: return visitSRL(N);
1557 case ISD::ROTR:
1558 case ISD::ROTL: return visitRotate(N);
1559 case ISD::FSHL:
1560 case ISD::FSHR: return visitFunnelShift(N);
1561 case ISD::ABS: return visitABS(N);
1562 case ISD::BSWAP: return visitBSWAP(N);
1563 case ISD::BITREVERSE: return visitBITREVERSE(N);
1564 case ISD::CTLZ: return visitCTLZ(N);
1565 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1566 case ISD::CTTZ: return visitCTTZ(N);
1567 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1568 case ISD::CTPOP: return visitCTPOP(N);
1569 case ISD::SELECT: return visitSELECT(N);
1570 case ISD::VSELECT: return visitVSELECT(N);
1571 case ISD::SELECT_CC: return visitSELECT_CC(N);
1572 case ISD::SETCC: return visitSETCC(N);
1573 case ISD::SETCCCARRY: return visitSETCCCARRY(N);
1574 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1575 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1576 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1577 case ISD::AssertSext:
1578 case ISD::AssertZext: return visitAssertExt(N);
1579 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1580 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
1581 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
1582 case ISD::TRUNCATE: return visitTRUNCATE(N);
1583 case ISD::BITCAST: return visitBITCAST(N);
1584 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1585 case ISD::FADD: return visitFADD(N);
1586 case ISD::FSUB: return visitFSUB(N);
1587 case ISD::FMUL: return visitFMUL(N);
1588 case ISD::FMA: return visitFMA(N);
1589 case ISD::FDIV: return visitFDIV(N);
1590 case ISD::FREM: return visitFREM(N);
1591 case ISD::FSQRT: return visitFSQRT(N);
1592 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1593 case ISD::FPOW: return visitFPOW(N);
1594 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1595 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1596 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1597 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1598 case ISD::FP_ROUND: return visitFP_ROUND(N);
1599 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1600 case ISD::FNEG: return visitFNEG(N);
1601 case ISD::FABS: return visitFABS(N);
1602 case ISD::FFLOOR: return visitFFLOOR(N);
1603 case ISD::FMINNUM: return visitFMINNUM(N);
1604 case ISD::FMAXNUM: return visitFMAXNUM(N);
1605 case ISD::FMINIMUM: return visitFMINIMUM(N);
1606 case ISD::FMAXIMUM: return visitFMAXIMUM(N);
1607 case ISD::FCEIL: return visitFCEIL(N);
1608 case ISD::FTRUNC: return visitFTRUNC(N);
1609 case ISD::BRCOND: return visitBRCOND(N);
1610 case ISD::BR_CC: return visitBR_CC(N);
1611 case ISD::LOAD: return visitLOAD(N);
1612 case ISD::STORE: return visitSTORE(N);
1613 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1614 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1615 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1616 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1617 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1618 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1619 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
1620 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1621 case ISD::MGATHER: return visitMGATHER(N);
1622 case ISD::MLOAD: return visitMLOAD(N);
1623 case ISD::MSCATTER: return visitMSCATTER(N);
1624 case ISD::MSTORE: return visitMSTORE(N);
1625 case ISD::LIFETIME_END: return visitLIFETIME_END(N);
1626 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
1627 case ISD::FP16_TO_FP: return visitFP16_TO_FP(N);
1628 case ISD::VECREDUCE_FADD:
1629 case ISD::VECREDUCE_FMUL:
1630 case ISD::VECREDUCE_ADD:
1631 case ISD::VECREDUCE_MUL:
1632 case ISD::VECREDUCE_AND:
1633 case ISD::VECREDUCE_OR:
1634 case ISD::VECREDUCE_XOR:
1635 case ISD::VECREDUCE_SMAX:
1636 case ISD::VECREDUCE_SMIN:
1637 case ISD::VECREDUCE_UMAX:
1638 case ISD::VECREDUCE_UMIN:
1639 case ISD::VECREDUCE_FMAX:
1640 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N);
1641 }
1642 return SDValue();
1643}
1644
1645SDValue DAGCombiner::combine(SDNode *N) {
1646 SDValue RV = visit(N);
1647
1648 // If nothing happened, try a target-specific DAG combine.
1649 if (!RV.getNode()) {
1650 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1651, __PRETTY_FUNCTION__))
1651 "Node was deleted but visit returned NULL!")((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1651, __PRETTY_FUNCTION__))
;
1652
1653 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1654 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1655
1656 // Expose the DAG combiner to the target combiner impls.
1657 TargetLowering::DAGCombinerInfo
1658 DagCombineInfo(DAG, Level, false, this);
1659
1660 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1661 }
1662 }
1663
1664 // If nothing happened still, try promoting the operation.
1665 if (!RV.getNode()) {
1666 switch (N->getOpcode()) {
1667 default: break;
1668 case ISD::ADD:
1669 case ISD::SUB:
1670 case ISD::MUL:
1671 case ISD::AND:
1672 case ISD::OR:
1673 case ISD::XOR:
1674 RV = PromoteIntBinOp(SDValue(N, 0));
1675 break;
1676 case ISD::SHL:
1677 case ISD::SRA:
1678 case ISD::SRL:
1679 RV = PromoteIntShiftOp(SDValue(N, 0));
1680 break;
1681 case ISD::SIGN_EXTEND:
1682 case ISD::ZERO_EXTEND:
1683 case ISD::ANY_EXTEND:
1684 RV = PromoteExtend(SDValue(N, 0));
1685 break;
1686 case ISD::LOAD:
1687 if (PromoteLoad(SDValue(N, 0)))
1688 RV = SDValue(N, 0);
1689 break;
1690 }
1691 }
1692
1693 // If N is a commutative binary node, try to eliminate it if the commuted
1694 // version is already present in the DAG.
1695 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) &&
1696 N->getNumValues() == 1) {
1697 SDValue N0 = N->getOperand(0);
1698 SDValue N1 = N->getOperand(1);
1699
1700 // Constant operands are canonicalized to RHS.
1701 if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
1702 SDValue Ops[] = {N1, N0};
1703 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1704 N->getFlags());
1705 if (CSENode)
1706 return SDValue(CSENode, 0);
1707 }
1708 }
1709
1710 return RV;
1711}
1712
1713/// Given a node, return its input chain if it has one, otherwise return a null
1714/// sd operand.
1715static SDValue getInputChainForNode(SDNode *N) {
1716 if (unsigned NumOps = N->getNumOperands()) {
1717 if (N->getOperand(0).getValueType() == MVT::Other)
1718 return N->getOperand(0);
1719 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1720 return N->getOperand(NumOps-1);
1721 for (unsigned i = 1; i < NumOps-1; ++i)
1722 if (N->getOperand(i).getValueType() == MVT::Other)
1723 return N->getOperand(i);
1724 }
1725 return SDValue();
1726}
1727
1728SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1729 // If N has two operands, where one has an input chain equal to the other,
1730 // the 'other' chain is redundant.
1731 if (N->getNumOperands() == 2) {
1732 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1733 return N->getOperand(0);
1734 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1735 return N->getOperand(1);
1736 }
1737
1738 // Don't simplify token factors if optnone.
1739 if (OptLevel == CodeGenOpt::None)
1740 return SDValue();
1741
1742 // If the sole user is a token factor, we should make sure we have a
1743 // chance to merge them together. This prevents TF chains from inhibiting
1744 // optimizations.
1745 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
1746 AddToWorklist(*(N->use_begin()));
1747
1748 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1749 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1750 SmallPtrSet<SDNode*, 16> SeenOps;
1751 bool Changed = false; // If we should replace this token factor.
1752
1753 // Start out with this token factor.
1754 TFs.push_back(N);
1755
1756 // Iterate through token factors. The TFs grows when new token factors are
1757 // encountered.
1758 for (unsigned i = 0; i < TFs.size(); ++i) {
1759 // Limit number of nodes to inline, to avoid quadratic compile times.
1760 // We have to add the outstanding Token Factors to Ops, otherwise we might
1761 // drop Ops from the resulting Token Factors.
1762 if (Ops.size() > TokenFactorInlineLimit) {
1763 for (unsigned j = i; j < TFs.size(); j++)
1764 Ops.emplace_back(TFs[j], 0);
1765 // Drop unprocessed Token Factors from TFs, so we do not add them to the
1766 // combiner worklist later.
1767 TFs.resize(i);
1768 break;
1769 }
1770
1771 SDNode *TF = TFs[i];
1772 // Check each of the operands.
1773 for (const SDValue &Op : TF->op_values()) {
1774 switch (Op.getOpcode()) {
1775 case ISD::EntryToken:
1776 // Entry tokens don't need to be added to the list. They are
1777 // redundant.
1778 Changed = true;
1779 break;
1780
1781 case ISD::TokenFactor:
1782 if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) {
1783 // Queue up for processing.
1784 TFs.push_back(Op.getNode());
1785 Changed = true;
1786 break;
1787 }
1788 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1789
1790 default:
1791 // Only add if it isn't already in the list.
1792 if (SeenOps.insert(Op.getNode()).second)
1793 Ops.push_back(Op);
1794 else
1795 Changed = true;
1796 break;
1797 }
1798 }
1799 }
1800
1801 // Re-visit inlined Token Factors, to clean them up in case they have been
1802 // removed. Skip the first Token Factor, as this is the current node.
1803 for (unsigned i = 1, e = TFs.size(); i < e; i++)
1804 AddToWorklist(TFs[i]);
1805
1806 // Remove Nodes that are chained to another node in the list. Do so
1807 // by walking up chains breath-first stopping when we've seen
1808 // another operand. In general we must climb to the EntryNode, but we can exit
1809 // early if we find all remaining work is associated with just one operand as
1810 // no further pruning is possible.
1811
1812 // List of nodes to search through and original Ops from which they originate.
1813 SmallVector<std::pair<SDNode *, unsigned>, 8> Worklist;
1814 SmallVector<unsigned, 8> OpWorkCount; // Count of work for each Op.
1815 SmallPtrSet<SDNode *, 16> SeenChains;
1816 bool DidPruneOps = false;
1817
1818 unsigned NumLeftToConsider = 0;
1819 for (const SDValue &Op : Ops) {
1820 Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++));
1821 OpWorkCount.push_back(1);
1822 }
1823
1824 auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) {
1825 // If this is an Op, we can remove the op from the list. Remark any
1826 // search associated with it as from the current OpNumber.
1827 if (SeenOps.count(Op) != 0) {
1828 Changed = true;
1829 DidPruneOps = true;
1830 unsigned OrigOpNumber = 0;
1831 while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op)
1832 OrigOpNumber++;
1833 assert((OrigOpNumber != Ops.size()) &&(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1834, __PRETTY_FUNCTION__))
1834 "expected to find TokenFactor Operand")(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1834, __PRETTY_FUNCTION__))
;
1835 // Re-mark worklist from OrigOpNumber to OpNumber
1836 for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) {
1837 if (Worklist[i].second == OrigOpNumber) {
1838 Worklist[i].second = OpNumber;
1839 }
1840 }
1841 OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber];
1842 OpWorkCount[OrigOpNumber] = 0;
1843 NumLeftToConsider--;
1844 }
1845 // Add if it's a new chain
1846 if (SeenChains.insert(Op).second) {
1847 OpWorkCount[OpNumber]++;
1848 Worklist.push_back(std::make_pair(Op, OpNumber));
1849 }
1850 };
1851
1852 for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) {
1853 // We need at least be consider at least 2 Ops to prune.
1854 if (NumLeftToConsider <= 1)
1855 break;
1856 auto CurNode = Worklist[i].first;
1857 auto CurOpNumber = Worklist[i].second;
1858 assert((OpWorkCount[CurOpNumber] > 0) &&(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1859, __PRETTY_FUNCTION__))
1859 "Node should not appear in worklist")(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1859, __PRETTY_FUNCTION__))
;
1860 switch (CurNode->getOpcode()) {
1861 case ISD::EntryToken:
1862 // Hitting EntryToken is the only way for the search to terminate without
1863 // hitting
1864 // another operand's search. Prevent us from marking this operand
1865 // considered.
1866 NumLeftToConsider++;
1867 break;
1868 case ISD::TokenFactor:
1869 for (const SDValue &Op : CurNode->op_values())
1870 AddToWorklist(i, Op.getNode(), CurOpNumber);
1871 break;
1872 case ISD::LIFETIME_START:
1873 case ISD::LIFETIME_END:
1874 case ISD::CopyFromReg:
1875 case ISD::CopyToReg:
1876 AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber);
1877 break;
1878 default:
1879 if (auto *MemNode = dyn_cast<MemSDNode>(CurNode))
1880 AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber);
1881 break;
1882 }
1883 OpWorkCount[CurOpNumber]--;
1884 if (OpWorkCount[CurOpNumber] == 0)
1885 NumLeftToConsider--;
1886 }
1887
1888 // If we've changed things around then replace token factor.
1889 if (Changed) {
1890 SDValue Result;
1891 if (Ops.empty()) {
1892 // The entry token is the only possible outcome.
1893 Result = DAG.getEntryNode();
1894 } else {
1895 if (DidPruneOps) {
1896 SmallVector<SDValue, 8> PrunedOps;
1897 //
1898 for (const SDValue &Op : Ops) {
1899 if (SeenChains.count(Op.getNode()) == 0)
1900 PrunedOps.push_back(Op);
1901 }
1902 Result = DAG.getTokenFactor(SDLoc(N), PrunedOps);
1903 } else {
1904 Result = DAG.getTokenFactor(SDLoc(N), Ops);
1905 }
1906 }
1907 return Result;
1908 }
1909 return SDValue();
1910}
1911
1912/// MERGE_VALUES can always be eliminated.
1913SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1914 WorklistRemover DeadNodes(*this);
1915 // Replacing results may cause a different MERGE_VALUES to suddenly
1916 // be CSE'd with N, and carry its uses with it. Iterate until no
1917 // uses remain, to ensure that the node can be safely deleted.
1918 // First add the users of this node to the work list so that they
1919 // can be tried again once they have new operands.
1920 AddUsersToWorklist(N);
1921 do {
1922 // Do as a single replacement to avoid rewalking use lists.
1923 SmallVector<SDValue, 8> Ops;
1924 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1925 Ops.push_back(N->getOperand(i));
1926 DAG.ReplaceAllUsesWith(N, Ops.data());
1927 } while (!N->use_empty());
1928 deleteAndRecombine(N);
1929 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1930}
1931
1932/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a
1933/// ConstantSDNode pointer else nullptr.
1934static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
1935 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
1936 return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
1937}
1938
1939SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
1940 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 &&((TLI.isBinOp(BO->getOpcode()) && BO->getNumValues
() == 1 && "Unexpected binary operator") ? static_cast
<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1941, __PRETTY_FUNCTION__))
1941 "Unexpected binary operator")((TLI.isBinOp(BO->getOpcode()) && BO->getNumValues
() == 1 && "Unexpected binary operator") ? static_cast
<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1941, __PRETTY_FUNCTION__))
;
1942
1943 // Don't do this unless the old select is going away. We want to eliminate the
1944 // binary operator, not replace a binop with a select.
1945 // TODO: Handle ISD::SELECT_CC.
1946 unsigned SelOpNo = 0;
1947 SDValue Sel = BO->getOperand(0);
1948 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
1949 SelOpNo = 1;
1950 Sel = BO->getOperand(1);
1951 }
1952
1953 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
1954 return SDValue();
1955
1956 SDValue CT = Sel.getOperand(1);
1957 if (!isConstantOrConstantVector(CT, true) &&
1958 !isConstantFPBuildVectorOrConstantFP(CT))
1959 return SDValue();
1960
1961 SDValue CF = Sel.getOperand(2);
1962 if (!isConstantOrConstantVector(CF, true) &&
1963 !isConstantFPBuildVectorOrConstantFP(CF))
1964 return SDValue();
1965
1966 // Bail out if any constants are opaque because we can't constant fold those.
1967 // The exception is "and" and "or" with either 0 or -1 in which case we can
1968 // propagate non constant operands into select. I.e.:
1969 // and (select Cond, 0, -1), X --> select Cond, 0, X
1970 // or X, (select Cond, -1, 0) --> select Cond, -1, X
1971 auto BinOpcode = BO->getOpcode();
1972 bool CanFoldNonConst =
1973 (BinOpcode == ISD::AND || BinOpcode == ISD::OR) &&
1974 (isNullOrNullSplat(CT) || isAllOnesOrAllOnesSplat(CT)) &&
1975 (isNullOrNullSplat(CF) || isAllOnesOrAllOnesSplat(CF));
1976
1977 SDValue CBO = BO->getOperand(SelOpNo ^ 1);
1978 if (!CanFoldNonConst &&
1979 !isConstantOrConstantVector(CBO, true) &&
1980 !isConstantFPBuildVectorOrConstantFP(CBO))
1981 return SDValue();
1982
1983 EVT VT = Sel.getValueType();
1984
1985 // In case of shift value and shift amount may have different VT. For instance
1986 // on x86 shift amount is i8 regardles of LHS type. Bail out if we have
1987 // swapped operands and value types do not match. NB: x86 is fine if operands
1988 // are not swapped with shift amount VT being not bigger than shifted value.
1989 // TODO: that is possible to check for a shift operation, correct VTs and
1990 // still perform optimization on x86 if needed.
1991 if (SelOpNo && VT != CBO.getValueType())
1992 return SDValue();
1993
1994 // We have a select-of-constants followed by a binary operator with a
1995 // constant. Eliminate the binop by pulling the constant math into the select.
1996 // Example: add (select Cond, CT, CF), CBO --> select Cond, CT + CBO, CF + CBO
1997 SDLoc DL(Sel);
1998 SDValue NewCT = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CT)
1999 : DAG.getNode(BinOpcode, DL, VT, CT, CBO);
2000 if (!CanFoldNonConst && !NewCT.isUndef() &&
2001 !isConstantOrConstantVector(NewCT, true) &&
2002 !isConstantFPBuildVectorOrConstantFP(NewCT))
2003 return SDValue();
2004
2005 SDValue NewCF = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CF)
2006 : DAG.getNode(BinOpcode, DL, VT, CF, CBO);
2007 if (!CanFoldNonConst && !NewCF.isUndef() &&
2008 !isConstantOrConstantVector(NewCF, true) &&
2009 !isConstantFPBuildVectorOrConstantFP(NewCF))
2010 return SDValue();
2011
2012 SDValue SelectOp = DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF);
2013 SelectOp->setFlags(BO->getFlags());
2014 return SelectOp;
2015}
2016
2017static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) {
2018 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2019, __PRETTY_FUNCTION__))
2019 "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2019, __PRETTY_FUNCTION__))
;
2020
2021 // Match a constant operand and a zext operand for the math instruction:
2022 // add Z, C
2023 // sub C, Z
2024 bool IsAdd = N->getOpcode() == ISD::ADD;
2025 SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0);
2026 SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1);
2027 auto *CN = dyn_cast<ConstantSDNode>(C);
2028 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND)
2029 return SDValue();
2030
2031 // Match the zext operand as a setcc of a boolean.
2032 if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
2033 Z.getOperand(0).getValueType() != MVT::i1)
2034 return SDValue();
2035
2036 // Match the compare as: setcc (X & 1), 0, eq.
2037 SDValue SetCC = Z.getOperand(0);
2038 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
2039 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) ||
2040 SetCC.getOperand(0).getOpcode() != ISD::AND ||
2041 !isOneConstant(SetCC.getOperand(0).getOperand(1)))
2042 return SDValue();
2043
2044 // We are adding/subtracting a constant and an inverted low bit. Turn that
2045 // into a subtract/add of the low bit with incremented/decremented constant:
2046 // add (zext i1 (seteq (X & 1), 0)), C --> sub C+1, (zext (X & 1))
2047 // sub C, (zext i1 (seteq (X & 1), 0)) --> add C-1, (zext (X & 1))
2048 EVT VT = C.getValueType();
2049 SDLoc DL(N);
2050 SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT);
2051 SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) :
2052 DAG.getConstant(CN->getAPIntValue() - 1, DL, VT);
2053 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
2054}
2055
2056/// Try to fold a 'not' shifted sign-bit with add/sub with constant operand into
2057/// a shift and add with a different constant.
2058static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) {
2059 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2060, __PRETTY_FUNCTION__))
2060 "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2060, __PRETTY_FUNCTION__))
;
2061
2062 // We need a constant operand for the add/sub, and the other operand is a
2063 // logical shift right: add (srl), C or sub C, (srl).
2064 // TODO - support non-uniform vector amounts.
2065 bool IsAdd = N->getOpcode() == ISD::ADD;
2066 SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0);
2067 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1);
2068 ConstantSDNode *C = isConstOrConstSplat(ConstantOp);
2069 if (!C || ShiftOp.getOpcode() != ISD::SRL)
2070 return SDValue();
2071
2072 // The shift must be of a 'not' value.
2073 SDValue Not = ShiftOp.getOperand(0);
2074 if (!Not.hasOneUse() || !isBitwiseNot(Not))
2075 return SDValue();
2076
2077 // The shift must be moving the sign bit to the least-significant-bit.
2078 EVT VT = ShiftOp.getValueType();
2079 SDValue ShAmt = ShiftOp.getOperand(1);
2080 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
2081 if (!ShAmtC || ShAmtC->getAPIntValue() != (VT.getScalarSizeInBits() - 1))
2082 return SDValue();
2083
2084 // Eliminate the 'not' by adjusting the shift and add/sub constant:
2085 // add (srl (not X), 31), C --> add (sra X, 31), (C + 1)
2086 // sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1)
2087 SDLoc DL(N);
2088 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
2089 SDValue NewShift = DAG.getNode(ShOpcode, DL, VT, Not.getOperand(0), ShAmt);
2090 APInt NewC = IsAdd ? C->getAPIntValue() + 1 : C->getAPIntValue() - 1;
2091 return DAG.getNode(ISD::ADD, DL, VT, NewShift, DAG.getConstant(NewC, DL, VT));
2092}
2093
2094/// Try to fold a node that behaves like an ADD (note that N isn't necessarily
2095/// an ISD::ADD here, it could for example be an ISD::OR if we know that there
2096/// are no common bits set in the operands).
2097SDValue DAGCombiner::visitADDLike(SDNode *N) {
2098 SDValue N0 = N->getOperand(0);
2099 SDValue N1 = N->getOperand(1);
2100 EVT VT = N0.getValueType();
2101 SDLoc DL(N);
2102
2103 // fold vector ops
2104 if (VT.isVector()) {
2105 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2106 return FoldedVOp;
2107
2108 // fold (add x, 0) -> x, vector edition
2109 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2110 return N0;
2111 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2112 return N1;
2113 }
2114
2115 // fold (add x, undef) -> undef
2116 if (N0.isUndef())
2117 return N0;
2118
2119 if (N1.isUndef())
2120 return N1;
2121
2122 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2123 // canonicalize constant to RHS
2124 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2125 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
2126 // fold (add c1, c2) -> c1+c2
2127 return DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0, N1});
2128 }
2129
2130 // fold (add x, 0) -> x
2131 if (isNullConstant(N1))
2132 return N0;
2133
2134 if (isConstantOrConstantVector(N1, /* NoOpaque */ true)) {
2135 // fold ((A-c1)+c2) -> (A+(c2-c1))
2136 if (N0.getOpcode() == ISD::SUB &&
2137 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) {
2138 SDValue Sub =
2139 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N1, N0.getOperand(1)});
2140 assert(Sub && "Constant folding failed")((Sub && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("Sub && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2140, __PRETTY_FUNCTION__))
;
2141 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Sub);
2142 }
2143
2144 // fold ((c1-A)+c2) -> (c1+c2)-A
2145 if (N0.getOpcode() == ISD::SUB &&
2146 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaque */ true)) {
2147 SDValue Add =
2148 DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N0.getOperand(0)});
2149 assert(Add && "Constant folding failed")((Add && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("Add && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2149, __PRETTY_FUNCTION__))
;
2150 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2151 }
2152
2153 // add (sext i1 X), 1 -> zext (not i1 X)
2154 // We don't transform this pattern:
2155 // add (zext i1 X), -1 -> sext (not i1 X)
2156 // because most (?) targets generate better code for the zext form.
2157 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2158 isOneOrOneSplat(N1)) {
2159 SDValue X = N0.getOperand(0);
2160 if ((!LegalOperations ||
2161 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) &&
2162 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) &&
2163 X.getScalarValueSizeInBits() == 1) {
2164 SDValue Not = DAG.getNOT(DL, X, X.getValueType());
2165 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not);
2166 }
2167 }
2168
2169 // Undo the add -> or combine to merge constant offsets from a frame index.
2170 if (N0.getOpcode() == ISD::OR &&
2171 isa<FrameIndexSDNode>(N0.getOperand(0)) &&
2172 isa<ConstantSDNode>(N0.getOperand(1)) &&
2173 DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) {
2174 SDValue Add0 = DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(1));
2175 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add0);
2176 }
2177 }
2178
2179 if (SDValue NewSel = foldBinOpIntoSelect(N))
2180 return NewSel;
2181
2182 // reassociate add
2183 if (!reassociationCanBreakAddressingModePattern(ISD::ADD, DL, N0, N1)) {
2184 if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
2185 return RADD;
2186 }
2187 // fold ((0-A) + B) -> B-A
2188 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0)))
2189 return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2190
2191 // fold (A + (0-B)) -> A-B
2192 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2193 return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1));
2194
2195 // fold (A+(B-A)) -> B
2196 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
2197 return N1.getOperand(0);
2198
2199 // fold ((B-A)+A) -> B
2200 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
2201 return N0.getOperand(0);
2202
2203 // fold ((A-B)+(C-A)) -> (C-B)
2204 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2205 N0.getOperand(0) == N1.getOperand(1))
2206 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2207 N0.getOperand(1));
2208
2209 // fold ((A-B)+(B-C)) -> (A-C)
2210 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2211 N0.getOperand(1) == N1.getOperand(0))
2212 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
2213 N1.getOperand(1));
2214
2215 // fold (A+(B-(A+C))) to (B-C)
2216 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2217 N0 == N1.getOperand(1).getOperand(0))
2218 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2219 N1.getOperand(1).getOperand(1));
2220
2221 // fold (A+(B-(C+A))) to (B-C)
2222 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2223 N0 == N1.getOperand(1).getOperand(1))
2224 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2225 N1.getOperand(1).getOperand(0));
2226
2227 // fold (A+((B-A)+or-C)) to (B+or-C)
2228 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
2229 N1.getOperand(0).getOpcode() == ISD::SUB &&
2230 N0 == N1.getOperand(0).getOperand(1))
2231 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0),
2232 N1.getOperand(1));
2233
2234 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
2235 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2236 SDValue N00 = N0.getOperand(0);
2237 SDValue N01 = N0.getOperand(1);
2238 SDValue N10 = N1.getOperand(0);
2239 SDValue N11 = N1.getOperand(1);
2240
2241 if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10))
2242 return DAG.getNode(ISD::SUB, DL, VT,
2243 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
2244 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
2245 }
2246
2247 // fold (add (umax X, C), -C) --> (usubsat X, C)
2248 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2249 auto MatchUSUBSAT = [](ConstantSDNode *Max, ConstantSDNode *Op) {
2250 return (!Max && !Op) ||
2251 (Max && Op && Max->getAPIntValue() == (-Op->getAPIntValue()));
2252 };
2253 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT,
2254 /*AllowUndefs*/ true))
2255 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
2256 N0.getOperand(1));
2257 }
2258
2259 if (SimplifyDemandedBits(SDValue(N, 0)))
2260 return SDValue(N, 0);
2261
2262 if (isOneOrOneSplat(N1)) {
2263 // fold (add (xor a, -1), 1) -> (sub 0, a)
2264 if (isBitwiseNot(N0))
2265 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
2266 N0.getOperand(0));
2267
2268 // fold (add (add (xor a, -1), b), 1) -> (sub b, a)
2269 if (N0.getOpcode() == ISD::ADD ||
2270 N0.getOpcode() == ISD::UADDO ||
2271 N0.getOpcode() == ISD::SADDO) {
2272 SDValue A, Xor;
2273
2274 if (isBitwiseNot(N0.getOperand(0))) {
2275 A = N0.getOperand(1);
2276 Xor = N0.getOperand(0);
2277 } else if (isBitwiseNot(N0.getOperand(1))) {
2278 A = N0.getOperand(0);
2279 Xor = N0.getOperand(1);
2280 }
2281
2282 if (Xor)
2283 return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0));
2284 }
2285
2286 // Look for:
2287 // add (add x, y), 1
2288 // And if the target does not like this form then turn into:
2289 // sub y, (xor x, -1)
2290 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.hasOneUse() &&
2291 N0.getOpcode() == ISD::ADD) {
2292 SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
2293 DAG.getAllOnesConstant(DL, VT));
2294 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not);
2295 }
2296 }
2297
2298 // (x - y) + -1 -> add (xor y, -1), x
2299 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2300 isAllOnesOrAllOnesSplat(N1)) {
2301 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1), N1);
2302 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
2303 }
2304
2305 if (SDValue Combined = visitADDLikeCommutative(N0, N1, N))
2306 return Combined;
2307
2308 if (SDValue Combined = visitADDLikeCommutative(N1, N0, N))
2309 return Combined;
2310
2311 return SDValue();
2312}
2313
2314SDValue DAGCombiner::visitADD(SDNode *N) {
2315 SDValue N0 = N->getOperand(0);
2316 SDValue N1 = N->getOperand(1);
2317 EVT VT = N0.getValueType();
2318 SDLoc DL(N);
2319
2320 if (SDValue Combined = visitADDLike(N))
2321 return Combined;
2322
2323 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
2324 return V;
2325
2326 if (SDValue V = foldAddSubOfSignBit(N, DAG))
2327 return V;
2328
2329 // fold (a+b) -> (a|b) iff a and b share no bits.
2330 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
2331 DAG.haveNoCommonBitsSet(N0, N1))
2332 return DAG.getNode(ISD::OR, DL, VT, N0, N1);
2333
2334 // Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
2335 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) {
2336 APInt C0 = N0->getConstantOperandAPInt(0);
2337 APInt C1 = N1->getConstantOperandAPInt(0);
2338 return DAG.getVScale(DL, VT, C0 + C1);
2339 }
2340
2341 return SDValue();
2342}
2343
2344SDValue DAGCombiner::visitADDSAT(SDNode *N) {
2345 unsigned Opcode = N->getOpcode();
2346 SDValue N0 = N->getOperand(0);
2347 SDValue N1 = N->getOperand(1);
2348 EVT VT = N0.getValueType();
2349 SDLoc DL(N);
2350
2351 // fold vector ops
2352 if (VT.isVector()) {
2353 // TODO SimplifyVBinOp
2354
2355 // fold (add_sat x, 0) -> x, vector edition
2356 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2357 return N0;
2358 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2359 return N1;
2360 }
2361
2362 // fold (add_sat x, undef) -> -1
2363 if (N0.isUndef() || N1.isUndef())
2364 return DAG.getAllOnesConstant(DL, VT);
2365
2366 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2367 // canonicalize constant to RHS
2368 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2369 return DAG.getNode(Opcode, DL, VT, N1, N0);
2370 // fold (add_sat c1, c2) -> c3
2371 return DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1});
2372 }
2373
2374 // fold (add_sat x, 0) -> x
2375 if (isNullConstant(N1))
2376 return N0;
2377
2378 // If it cannot overflow, transform into an add.
2379 if (Opcode == ISD::UADDSAT)
2380 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2381 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
2382
2383 return SDValue();
2384}
2385
2386static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
2387 bool Masked = false;
2388
2389 // First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization.
2390 while (true) {
2391 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
2392 V = V.getOperand(0);
2393 continue;
2394 }
2395
2396 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
2397 Masked = true;
2398 V = V.getOperand(0);
2399 continue;
2400 }
2401
2402 break;
2403 }
2404
2405 // If this is not a carry, return.
2406 if (V.getResNo() != 1)
2407 return SDValue();
2408
2409 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
2410 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
2411 return SDValue();
2412
2413 EVT VT = V.getNode()->getValueType(0);
2414 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT))
2415 return SDValue();
2416
2417 // If the result is masked, then no matter what kind of bool it is we can
2418 // return. If it isn't, then we need to make sure the bool type is either 0 or
2419 // 1 and not other values.
2420 if (Masked ||
2421 TLI.getBooleanContents(V.getValueType()) ==
2422 TargetLoweringBase::ZeroOrOneBooleanContent)
2423 return V;
2424
2425 return SDValue();
2426}
2427
2428/// Given the operands of an add/sub operation, see if the 2nd operand is a
2429/// masked 0/1 whose source operand is actually known to be 0/-1. If so, invert
2430/// the opcode and bypass the mask operation.
2431static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1,
2432 SelectionDAG &DAG, const SDLoc &DL) {
2433 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
2434 return SDValue();
2435
2436 EVT VT = N0.getValueType();
2437 if (DAG.ComputeNumSignBits(N1.getOperand(0)) != VT.getScalarSizeInBits())
2438 return SDValue();
2439
2440 // add N0, (and (AssertSext X, i1), 1) --> sub N0, X
2441 // sub N0, (and (AssertSext X, i1), 1) --> add N0, X
2442 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N1.getOperand(0));
2443}
2444
2445/// Helper for doing combines based on N0 and N1 being added to each other.
2446SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
2447 SDNode *LocReference) {
2448 EVT VT = N0.getValueType();
2449 SDLoc DL(LocReference);
2450
2451 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
2452 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2453 isNullOrNullSplat(N1.getOperand(0).getOperand(0)))
2454 return DAG.getNode(ISD::SUB, DL, VT, N0,
2455 DAG.getNode(ISD::SHL, DL, VT,
2456 N1.getOperand(0).getOperand(1),
2457 N1.getOperand(1)));
2458
2459 if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL))
2460 return V;
2461
2462 // Look for:
2463 // add (add x, 1), y
2464 // And if the target does not like this form then turn into:
2465 // sub y, (xor x, -1)
2466 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.hasOneUse() &&
2467 N0.getOpcode() == ISD::ADD && isOneOrOneSplat(N0.getOperand(1))) {
2468 SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
2469 DAG.getAllOnesConstant(DL, VT));
2470 return DAG.getNode(ISD::SUB, DL, VT, N1, Not);
2471 }
2472
2473 // Hoist one-use subtraction by non-opaque constant:
2474 // (x - C) + y -> (x + y) - C
2475 // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
2476 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2477 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
2478 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), N1);
2479 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2480 }
2481 // Hoist one-use subtraction from non-opaque constant:
2482 // (C - x) + y -> (y - x) + C
2483 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2484 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
2485 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2486 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(0));
2487 }
2488
2489 // If the target's bool is represented as 0/1, prefer to make this 'sub 0/1'
2490 // rather than 'add 0/-1' (the zext should get folded).
2491 // add (sext i1 Y), X --> sub X, (zext i1 Y)
2492 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
2493 N0.getOperand(0).getScalarValueSizeInBits() == 1 &&
2494 TLI.getBooleanContents(VT) == TargetLowering::ZeroOrOneBooleanContent) {
2495 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
2496 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
2497 }
2498
2499 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
2500 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2501 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
2502 if (TN->getVT() == MVT::i1) {
2503 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
2504 DAG.getConstant(1, DL, VT));
2505 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
2506 }
2507 }
2508
2509 // (add X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2510 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
2511 N1.getResNo() == 0)
2512 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
2513 N0, N1.getOperand(0), N1.getOperand(2));
2514
2515 // (add X, Carry) -> (addcarry X, 0, Carry)
2516 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2517 if (SDValue Carry = getAsCarry(TLI, N1))
2518 return DAG.getNode(ISD::ADDCARRY, DL,
2519 DAG.getVTList(VT, Carry.getValueType()), N0,
2520 DAG.getConstant(0, DL, VT), Carry);
2521
2522 return SDValue();
2523}
2524
2525SDValue DAGCombiner::visitADDC(SDNode *N) {
2526 SDValue N0 = N->getOperand(0);
2527 SDValue N1 = N->getOperand(1);
2528 EVT VT = N0.getValueType();
2529 SDLoc DL(N);
2530
2531 // If the flag result is dead, turn this into an ADD.
2532 if (!N->hasAnyUseOfValue(1))
2533 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2534 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2535
2536 // canonicalize constant to RHS.
2537 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2538 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2539 if (N0C && !N1C)
2540 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
2541
2542 // fold (addc x, 0) -> x + no carry out
2543 if (isNullConstant(N1))
2544 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
2545 DL, MVT::Glue));
2546
2547 // If it cannot overflow, transform into an add.
2548 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2549 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2550 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2551
2552 return SDValue();
2553}
2554
2555static SDValue flipBoolean(SDValue V, const SDLoc &DL,
2556 SelectionDAG &DAG, const TargetLowering &TLI) {
2557 EVT VT = V.getValueType();
2558
2559 SDValue Cst;
2560 switch (TLI.getBooleanContents(VT)) {
2561 case TargetLowering::ZeroOrOneBooleanContent:
2562 case TargetLowering::UndefinedBooleanContent:
2563 Cst = DAG.getConstant(1, DL, VT);
2564 break;
2565 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2566 Cst = DAG.getAllOnesConstant(DL, VT);
2567 break;
2568 }
2569
2570 return DAG.getNode(ISD::XOR, DL, VT, V, Cst);
2571}
2572
2573/**
2574 * Flips a boolean if it is cheaper to compute. If the Force parameters is set,
2575 * then the flip also occurs if computing the inverse is the same cost.
2576 * This function returns an empty SDValue in case it cannot flip the boolean
2577 * without increasing the cost of the computation. If you want to flip a boolean
2578 * no matter what, use flipBoolean.
2579 */
2580static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG,
2581 const TargetLowering &TLI,
2582 bool Force) {
2583 if (Force && isa<ConstantSDNode>(V))
2584 return flipBoolean(V, SDLoc(V), DAG, TLI);
2585
2586 if (V.getOpcode() != ISD::XOR)
2587 return SDValue();
2588
2589 ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
2590 if (!Const)
2591 return SDValue();
2592
2593 EVT VT = V.getValueType();
2594
2595 bool IsFlip = false;
2596 switch(TLI.getBooleanContents(VT)) {
2597 case TargetLowering::ZeroOrOneBooleanContent:
2598 IsFlip = Const->isOne();
2599 break;
2600 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2601 IsFlip = Const->isAllOnesValue();
2602 break;
2603 case TargetLowering::UndefinedBooleanContent:
2604 IsFlip = (Const->getAPIntValue() & 0x01) == 1;
2605 break;
2606 }
2607
2608 if (IsFlip)
2609 return V.getOperand(0);
2610 if (Force)
2611 return flipBoolean(V, SDLoc(V), DAG, TLI);
2612 return SDValue();
2613}
2614
2615SDValue DAGCombiner::visitADDO(SDNode *N) {
2616 SDValue N0 = N->getOperand(0);
2617 SDValue N1 = N->getOperand(1);
2618 EVT VT = N0.getValueType();
2619 bool IsSigned = (ISD::SADDO == N->getOpcode());
2620
2621 EVT CarryVT = N->getValueType(1);
2622 SDLoc DL(N);
2623
2624 // If the flag result is dead, turn this into an ADD.
2625 if (!N->hasAnyUseOfValue(1))
2626 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2627 DAG.getUNDEF(CarryVT));
2628
2629 // canonicalize constant to RHS.
2630 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2631 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
2632 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
2633
2634 // fold (addo x, 0) -> x + no carry out
2635 if (isNullOrNullSplat(N1))
2636 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
2637
2638 if (!IsSigned) {
2639 // If it cannot overflow, transform into an add.
2640 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2641 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2642 DAG.getConstant(0, DL, CarryVT));
2643
2644 // fold (uaddo (xor a, -1), 1) -> (usub 0, a) and flip carry.
2645 if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) {
2646 SDValue Sub = DAG.getNode(ISD::USUBO, DL, N->getVTList(),
2647 DAG.getConstant(0, DL, VT), N0.getOperand(0));
2648 return CombineTo(N, Sub,
2649 flipBoolean(Sub.getValue(1), DL, DAG, TLI));
2650 }
2651
2652 if (SDValue Combined = visitUADDOLike(N0, N1, N))
2653 return Combined;
2654
2655 if (SDValue Combined = visitUADDOLike(N1, N0, N))
2656 return Combined;
2657 }
2658
2659 return SDValue();
2660}
2661
2662SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
2663 EVT VT = N0.getValueType();
2664 if (VT.isVector())
2665 return SDValue();
2666
2667 // (uaddo X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2668 // If Y + 1 cannot overflow.
2669 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
2670 SDValue Y = N1.getOperand(0);
2671 SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType());
2672 if (DAG.computeOverflowKind(Y, One) == SelectionDAG::OFK_Never)
2673 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
2674 N1.getOperand(2));
2675 }
2676
2677 // (uaddo X, Carry) -> (addcarry X, 0, Carry)
2678 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2679 if (SDValue Carry = getAsCarry(TLI, N1))
2680 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2681 DAG.getConstant(0, SDLoc(N), VT), Carry);
2682
2683 return SDValue();
2684}
2685
2686SDValue DAGCombiner::visitADDE(SDNode *N) {
2687 SDValue N0 = N->getOperand(0);
2688 SDValue N1 = N->getOperand(1);
2689 SDValue CarryIn = N->getOperand(2);
2690
2691 // canonicalize constant to RHS
2692 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2693 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2694 if (N0C && !N1C)
2695 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
2696 N1, N0, CarryIn);
2697
2698 // fold (adde x, y, false) -> (addc x, y)
2699 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2700 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
2701
2702 return SDValue();
2703}
2704
2705SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
2706 SDValue N0 = N->getOperand(0);
1
Value assigned to 'N0.Node'
2707 SDValue N1 = N->getOperand(1);
2708 SDValue CarryIn = N->getOperand(2);
2709 SDLoc DL(N);
2710
2711 // canonicalize constant to RHS
2712 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2
Calling 'dyn_cast<llvm::ConstantSDNode, llvm::SDValue>'
17
Returning from 'dyn_cast<llvm::ConstantSDNode, llvm::SDValue>'
2713 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2714 if (N0C && !N1C)
18
Assuming 'N0C' is null
2715 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);
2716
2717 // fold (addcarry x, y, false) -> (uaddo x, y)
2718 if (isNullConstant(CarryIn)) {
19
Assuming the condition is false
20
Taking false branch
2719 if (!LegalOperations ||
2720 TLI.isOperationLegalOrCustom(ISD::UADDO, N->getValueType(0)))
2721 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
2722 }
2723
2724 // fold (addcarry 0, 0, X) -> (and (ext/trunc X), 1) and no carry.
2725 if (isNullConstant(N0) && isNullConstant(N1)) {
21
Assuming the condition is true
22
Assuming the condition is true
23
Taking true branch
2726 EVT VT = N0.getValueType();
24
Calling 'SDValue::getValueType'
2727 EVT CarryVT = CarryIn.getValueType();
2728 SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT);
2729 AddToWorklist(CarryExt.getNode());
2730 return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,
2731 DAG.getConstant(1, DL, VT)),
2732 DAG.getConstant(0, DL, CarryVT));
2733 }
2734
2735 if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N))
2736 return Combined;
2737
2738 if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
2739 return Combined;
2740
2741 return SDValue();
2742}
2743
2744/**
2745 * If we are facing some sort of diamond carry propapagtion pattern try to
2746 * break it up to generate something like:
2747 * (addcarry X, 0, (addcarry A, B, Z):Carry)
2748 *
2749 * The end result is usually an increase in operation required, but because the
2750 * carry is now linearized, other tranforms can kick in and optimize the DAG.
2751 *
2752 * Patterns typically look something like
2753 * (uaddo A, B)
2754 * / \
2755 * Carry Sum
2756 * | \
2757 * | (addcarry *, 0, Z)
2758 * | /
2759 * \ Carry
2760 * | /
2761 * (addcarry X, *, *)
2762 *
2763 * But numerous variation exist. Our goal is to identify A, B, X and Z and
2764 * produce a combine with a single path for carry propagation.
2765 */
2766static SDValue combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
2767 SDValue X, SDValue Carry0, SDValue Carry1,
2768 SDNode *N) {
2769 if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1)
2770 return SDValue();
2771 if (Carry1.getOpcode() != ISD::UADDO)
2772 return SDValue();
2773
2774 SDValue Z;
2775
2776 /**
2777 * First look for a suitable Z. It will present itself in the form of
2778 * (addcarry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true
2779 */
2780 if (Carry0.getOpcode() == ISD::ADDCARRY &&
2781 isNullConstant(Carry0.getOperand(1))) {
2782 Z = Carry0.getOperand(2);
2783 } else if (Carry0.getOpcode() == ISD::UADDO &&
2784 isOneConstant(Carry0.getOperand(1))) {
2785 EVT VT = Combiner.getSetCCResultType(Carry0.getValueType());
2786 Z = DAG.getConstant(1, SDLoc(Carry0.getOperand(1)), VT);
2787 } else {
2788 // We couldn't find a suitable Z.
2789 return SDValue();
2790 }
2791
2792
2793 auto cancelDiamond = [&](SDValue A,SDValue B) {
2794 SDLoc DL(N);
2795 SDValue NewY = DAG.getNode(ISD::ADDCARRY, DL, Carry0->getVTList(), A, B, Z);
2796 Combiner.AddToWorklist(NewY.getNode());
2797 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), X,
2798 DAG.getConstant(0, DL, X.getValueType()),
2799 NewY.getValue(1));
2800 };
2801
2802 /**
2803 * (uaddo A, B)
2804 * |
2805 * Sum
2806 * |
2807 * (addcarry *, 0, Z)
2808 */
2809 if (Carry0.getOperand(0) == Carry1.getValue(0)) {
2810 return cancelDiamond(Carry1.getOperand(0), Carry1.getOperand(1));
2811 }
2812
2813 /**
2814 * (addcarry A, 0, Z)
2815 * |
2816 * Sum
2817 * |
2818 * (uaddo *, B)
2819 */
2820 if (Carry1.getOperand(0) == Carry0.getValue(0)) {
2821 return cancelDiamond(Carry0.getOperand(0), Carry1.getOperand(1));
2822 }
2823
2824 if (Carry1.getOperand(1) == Carry0.getValue(0)) {
2825 return cancelDiamond(Carry1.getOperand(0), Carry0.getOperand(0));
2826 }
2827
2828 return SDValue();
2829}
2830
2831// If we are facing some sort of diamond carry/borrow in/out pattern try to
2832// match patterns like:
2833//
2834// (uaddo A, B) CarryIn
2835// | \ |
2836// | \ |
2837// PartialSum PartialCarryOutX /
2838// | | /
2839// | ____|____________/
2840// | / |
2841// (uaddo *, *) \________
2842// | \ \
2843// | \ |
2844// | PartialCarryOutY |
2845// | \ |
2846// | \ /
2847// AddCarrySum | ______/
2848// | /
2849// CarryOut = (or *, *)
2850//
2851// And generate ADDCARRY (or SUBCARRY) with two result values:
2852//
2853// {AddCarrySum, CarryOut} = (addcarry A, B, CarryIn)
2854//
2855// Our goal is to identify A, B, and CarryIn and produce ADDCARRY/SUBCARRY with
2856// a single path for carry/borrow out propagation:
2857static SDValue combineCarryDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
2858 const TargetLowering &TLI, SDValue Carry0,
2859 SDValue Carry1, SDNode *N) {
2860 if (Carry0.getResNo() != 1 || Carry1.getResNo() != 1)
2861 return SDValue();
2862 unsigned Opcode = Carry0.getOpcode();
2863 if (Opcode != Carry1.getOpcode())
2864 return SDValue();
2865 if (Opcode != ISD::UADDO && Opcode != ISD::USUBO)
2866 return SDValue();
2867
2868 // Canonicalize the add/sub of A and B as Carry0 and the add/sub of the
2869 // carry/borrow in as Carry1. (The top and middle uaddo nodes respectively in
2870 // the above ASCII art.)
2871 if (Carry1.getOperand(0) != Carry0.getValue(0) &&
2872 Carry1.getOperand(1) != Carry0.getValue(0))
2873 std::swap(Carry0, Carry1);
2874 if (Carry1.getOperand(0) != Carry0.getValue(0) &&
2875 Carry1.getOperand(1) != Carry0.getValue(0))
2876 return SDValue();
2877
2878 // The carry in value must be on the righthand side for subtraction.
2879 unsigned CarryInOperandNum =
2880 Carry1.getOperand(0) == Carry0.getValue(0) ? 1 : 0;
2881 if (Opcode == ISD::USUBO && CarryInOperandNum != 1)
2882 return SDValue();
2883 SDValue CarryIn = Carry1.getOperand(CarryInOperandNum);
2884
2885 unsigned NewOp = Opcode == ISD::UADDO ? ISD::ADDCARRY : ISD::SUBCARRY;
2886 if (!TLI.isOperationLegalOrCustom(NewOp, Carry0.getValue(0).getValueType()))
2887 return SDValue();
2888
2889 // Verify that the carry/borrow in is plausibly a carry/borrow bit.
2890 // TODO: make getAsCarry() aware of how partial carries are merged.
2891 if (CarryIn.getOpcode() != ISD::ZERO_EXTEND)
2892 return SDValue();
2893 CarryIn = CarryIn.getOperand(0);
2894 if (CarryIn.getValueType() != MVT::i1)
2895 return SDValue();
2896
2897 SDLoc DL(N);
2898 SDValue Merged =
2899 DAG.getNode(NewOp, DL, Carry1->getVTList(), Carry0.getOperand(0),
2900 Carry0.getOperand(1), CarryIn);
2901
2902 // Please note that because we have proven that the result of the UADDO/USUBO
2903 // of A and B feeds into the UADDO/USUBO that does the carry/borrow in, we can
2904 // therefore prove that if the first UADDO/USUBO overflows, the second
2905 // UADDO/USUBO cannot. For example consider 8-bit numbers where 0xFF is the
2906 // maximum value.
2907 //
2908 // 0xFF + 0xFF == 0xFE with carry but 0xFE + 1 does not carry
2909 // 0x00 - 0xFF == 1 with a carry/borrow but 1 - 1 == 0 (no carry/borrow)
2910 //
2911 // This is important because it means that OR and XOR can be used to merge
2912 // carry flags; and that AND can return a constant zero.
2913 //
2914 // TODO: match other operations that can merge flags (ADD, etc)
2915 DAG.ReplaceAllUsesOfValueWith(Carry1.getValue(0), Merged.getValue(0));
2916 if (N->getOpcode() == ISD::AND)
2917 return DAG.getConstant(0, DL, MVT::i1);
2918 return Merged.getValue(1);
2919}
2920
2921SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
2922 SDNode *N) {
2923 // fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
2924 if (isBitwiseNot(N0))
2925 if (SDValue NotC = extractBooleanFlip(CarryIn, DAG, TLI, true)) {
2926 SDLoc DL(N);
2927 SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(), N1,
2928 N0.getOperand(0), NotC);
2929 return CombineTo(N, Sub,
2930 flipBoolean(Sub.getValue(1), DL, DAG, TLI));
2931 }
2932
2933 // Iff the flag result is dead:
2934 // (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
2935 // Don't do this if the Carry comes from the uaddo. It won't remove the uaddo
2936 // or the dependency between the instructions.
2937 if ((N0.getOpcode() == ISD::ADD ||
2938 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 &&
2939 N0.getValue(1) != CarryIn)) &&
2940 isNullConstant(N1) && !N->hasAnyUseOfValue(1))
2941 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
2942 N0.getOperand(0), N0.getOperand(1), CarryIn);
2943
2944 /**
2945 * When one of the addcarry argument is itself a carry, we may be facing
2946 * a diamond carry propagation. In which case we try to transform the DAG
2947 * to ensure linear carry propagation if that is possible.
2948 */
2949 if (auto Y = getAsCarry(TLI, N1)) {
2950 // Because both are carries, Y and Z can be swapped.
2951 if (auto R = combineADDCARRYDiamond(*this, DAG, N0, Y, CarryIn, N))
2952 return R;
2953 if (auto R = combineADDCARRYDiamond(*this, DAG, N0, CarryIn, Y, N))
2954 return R;
2955 }
2956
2957 return SDValue();
2958}
2959
2960// Since it may not be valid to emit a fold to zero for vector initializers
2961// check if we can before folding.
2962static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
2963 SelectionDAG &DAG, bool LegalOperations) {
2964 if (!VT.isVector())
2965 return DAG.getConstant(0, DL, VT);
2966 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
2967 return DAG.getConstant(0, DL, VT);
2968 return SDValue();
2969}
2970
2971SDValue DAGCombiner::visitSUB(SDNode *N) {
2972 SDValue N0 = N->getOperand(0);
2973 SDValue N1 = N->getOperand(1);
2974 EVT VT = N0.getValueType();
2975 SDLoc DL(N);
2976
2977 // fold vector ops
2978 if (VT.isVector()) {
2979 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2980 return FoldedVOp;
2981
2982 // fold (sub x, 0) -> x, vector edition
2983 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2984 return N0;
2985 }
2986
2987 // fold (sub x, x) -> 0
2988 // FIXME: Refactor this and xor and other similar operations together.
2989 if (N0 == N1)
2990 return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
2991
2992 // fold (sub c1, c2) -> c3
2993 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N1}))
2994 return C;
2995
2996 if (SDValue NewSel = foldBinOpIntoSelect(N))
2997 return NewSel;
2998
2999 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3000
3001 // fold (sub x, c) -> (add x, -c)
3002 if (N1C) {
3003 return DAG.getNode(ISD::ADD, DL, VT, N0,
3004 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
3005 }
3006
3007 if (isNullOrNullSplat(N0)) {
3008 unsigned BitWidth = VT.getScalarSizeInBits();
3009 // Right-shifting everything out but the sign bit followed by negation is
3010 // the same as flipping arithmetic/logical shift type without the negation:
3011 // -(X >>u 31) -> (X >>s 31)
3012 // -(X >>s 31) -> (X >>u 31)
3013 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3014 ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
3015 if (ShiftAmt && ShiftAmt->getAPIntValue() == (BitWidth - 1)) {
3016 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
3017 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
3018 return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));
3019 }
3020 }
3021
3022 // 0 - X --> 0 if the sub is NUW.
3023 if (N->getFlags().hasNoUnsignedWrap())
3024 return N0;
3025
3026 if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) {
3027 // N1 is either 0 or the minimum signed value. If the sub is NSW, then
3028 // N1 must be 0 because negating the minimum signed value is undefined.
3029 if (N->getFlags().hasNoSignedWrap())
3030 return N0;
3031
3032 // 0 - X --> X if X is 0 or the minimum signed value.
3033 return N1;
3034 }
3035 }
3036
3037 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
3038 if (isAllOnesOrAllOnesSplat(N0))
3039 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
3040
3041 // fold (A - (0-B)) -> A+B
3042 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
3043 return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1));
3044
3045 // fold A-(A-B) -> B
3046 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
3047 return N1.getOperand(1);
3048
3049 // fold (A+B)-A -> B
3050 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
3051 return N0.getOperand(1);
3052
3053 // fold (A+B)-B -> A
3054 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
3055 return N0.getOperand(0);
3056
3057 // fold (A+C1)-C2 -> A+(C1-C2)
3058 if (N0.getOpcode() == ISD::ADD &&
3059 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3060 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3061 SDValue NewC =
3062 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0.getOperand(1), N1});
3063 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3063, __PRETTY_FUNCTION__))
;
3064 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
3065 }
3066
3067 // fold C2-(A+C1) -> (C2-C1)-A
3068 if (N1.getOpcode() == ISD::ADD) {
3069 SDValue N11 = N1.getOperand(1);
3070 if (isConstantOrConstantVector(N0, /* NoOpaques */ true) &&
3071 isConstantOrConstantVector(N11, /* NoOpaques */ true)) {
3072 SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N11});
3073 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3073, __PRETTY_FUNCTION__))
;
3074 return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
3075 }
3076 }
3077
3078 // fold (A-C1)-C2 -> A-(C1+C2)
3079 if (N0.getOpcode() == ISD::SUB &&
3080 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3081 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3082 SDValue NewC =
3083 DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0.getOperand(1), N1});
3084 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3084, __PRETTY_FUNCTION__))
;
3085 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC);
3086 }
3087
3088 // fold (c1-A)-c2 -> (c1-c2)-A
3089 if (N0.getOpcode() == ISD::SUB &&
3090 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3091 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaques */ true)) {
3092 SDValue NewC =
3093 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0.getOperand(0), N1});
3094 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3094, __PRETTY_FUNCTION__))
;
3095 return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1));
3096 }
3097
3098 // fold ((A+(B+or-C))-B) -> A+or-C
3099 if (N0.getOpcode() == ISD::ADD &&
3100 (N0.getOperand(1).getOpcode() == ISD::SUB ||
3101 N0.getOperand(1).getOpcode() == ISD::ADD) &&
3102 N0.getOperand(1).getOperand(0) == N1)
3103 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0),
3104 N0.getOperand(1).getOperand(1));
3105
3106 // fold ((A+(C+B))-B) -> A+C
3107 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD &&
3108 N0.getOperand(1).getOperand(1) == N1)
3109 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0),
3110 N0.getOperand(1).getOperand(0));
3111
3112 // fold ((A-(B-C))-C) -> A-B
3113 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
3114 N0.getOperand(1).getOperand(1) == N1)
3115 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
3116 N0.getOperand(1).getOperand(0));
3117
3118 // fold (A-(B-C)) -> A+(C-B)
3119 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse())
3120 return DAG.getNode(ISD::ADD, DL, VT, N0,
3121 DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1),
3122 N1.getOperand(0)));
3123
3124 // A - (A & B) -> A & (~B)
3125 if (N1.getOpcode() == ISD::AND) {
3126 SDValue A = N1.getOperand(0);
3127 SDValue B = N1.getOperand(1);
3128 if (A != N0)
3129 std::swap(A, B);
3130 if (A == N0 &&
3131 (N1.hasOneUse() || isConstantOrConstantVector(B, /*NoOpaques=*/true))) {
3132 SDValue InvB =
3133 DAG.getNode(ISD::XOR, DL, VT, B, DAG.getAllOnesConstant(DL, VT));
3134 return DAG.getNode(ISD::AND, DL, VT, A, InvB);
3135 }
3136 }
3137
3138 // fold (X - (-Y * Z)) -> (X + (Y * Z))
3139 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) {
3140 if (N1.getOperand(0).getOpcode() == ISD::SUB &&
3141 isNullOrNullSplat(N1.getOperand(0).getOperand(0))) {
3142 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3143 N1.getOperand(0).getOperand(1),
3144 N1.getOperand(1));
3145 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
3146 }
3147 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
3148 isNullOrNullSplat(N1.getOperand(1).getOperand(0))) {
3149 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3150 N1.getOperand(0),
3151 N1.getOperand(1).getOperand(1));
3152 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
3153 }
3154 }
3155
3156 // If either operand of a sub is undef, the result is undef
3157 if (N0.isUndef())
3158 return N0;
3159 if (N1.isUndef())
3160 return N1;
3161
3162 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
3163 return V;
3164
3165 if (SDValue V = foldAddSubOfSignBit(N, DAG))
3166 return V;
3167
3168 if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
3169 return V;
3170
3171 // (x - y) - 1 -> add (xor y, -1), x
3172 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) {
3173 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
3174 DAG.getAllOnesConstant(DL, VT));
3175 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
3176 }
3177
3178 // Look for:
3179 // sub y, (xor x, -1)
3180 // And if the target does not like this form then turn into:
3181 // add (add x, y), 1
3182 if (TLI.preferIncOfAddToSubOfNot(VT) && N1.hasOneUse() && isBitwiseNot(N1)) {
3183 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(0));
3184 return DAG.getNode(ISD::ADD, DL, VT, Add, DAG.getConstant(1, DL, VT));
3185 }
3186
3187 // Hoist one-use addition by non-opaque constant:
3188 // (x + C) - y -> (x - y) + C
3189 if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD &&
3190 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3191 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3192 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
3193 }
3194 // y - (x + C) -> (y - x) - C
3195 if (N1.hasOneUse() && N1.getOpcode() == ISD::ADD &&
3196 isConstantOrConstantVector(N1.getOperand(1), /*NoOpaques=*/true)) {
3197 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
3198 return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1));
3199 }
3200 // (x - C) - y -> (x - y) - C
3201 // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
3202 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3203 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3204 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3205 return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
3206 }
3207 // (C - x) - y -> C - (x + y)
3208 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3209 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
3210 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1);
3211 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
3212 }
3213
3214 // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
3215 // rather than 'sub 0/1' (the sext should get folded).
3216 // sub X, (zext i1 Y) --> add X, (sext i1 Y)
3217 if (N1.getOpcode() == ISD::ZERO_EXTEND &&
3218 N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
3219 TLI.getBooleanContents(VT) ==
3220 TargetLowering::ZeroOrNegativeOneBooleanContent) {
3221 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
3222 return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
3223 }
3224
3225 // fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X)
3226 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
3227 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
3228 SDValue X0 = N0.getOperand(0), X1 = N0.getOperand(1);
3229 SDValue S0 = N1.getOperand(0);
3230 if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) {
3231 unsigned OpSizeInBits = VT.getScalarSizeInBits();
3232 if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1)))
3233 if (C->getAPIntValue() == (OpSizeInBits - 1))
3234 return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0);
3235 }
3236 }
3237 }
3238
3239 // If the relocation model supports it, consider symbol offsets.
3240 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
3241 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
3242 // fold (sub Sym, c) -> Sym-c
3243 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
3244 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
3245 GA->getOffset() -
3246 (uint64_t)N1C->getSExtValue());
3247 // fold (sub Sym+c1, Sym+c2) -> c1-c2
3248 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
3249 if (GA->getGlobal() == GB->getGlobal())
3250 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
3251 DL, VT);
3252 }
3253
3254 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
3255 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
3256 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
3257 if (TN->getVT() == MVT::i1) {
3258 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
3259 DAG.getConstant(1, DL, VT));
3260 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
3261 }
3262 }
3263
3264 // canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C))
3265 if (N1.getOpcode() == ISD::VSCALE) {
3266 APInt IntVal = N1.getConstantOperandAPInt(0);
3267 return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
3268 }
3269
3270 // Prefer an add for more folding potential and possibly better codegen:
3271 // sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1)
3272 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
3273 SDValue ShAmt = N1.getOperand(1);
3274 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
3275 if (ShAmtC &&
3276 ShAmtC->getAPIntValue() == (N1.getScalarValueSizeInBits() - 1)) {
3277 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
3278 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
3279 }
3280 }
3281
3282 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) {
3283 // (sub Carry, X) -> (addcarry (sub 0, X), 0, Carry)
3284 if (SDValue Carry = getAsCarry(TLI, N0)) {
3285 SDValue X = N1;
3286 SDValue Zero = DAG.getConstant(0, DL, VT);
3287 SDValue NegX = DAG.getNode(ISD::SUB, DL, VT, Zero, X);
3288 return DAG.getNode(ISD::ADDCARRY, DL,
3289 DAG.getVTList(VT, Carry.getValueType()), NegX, Zero,
3290 Carry);
3291 }
3292 }
3293
3294 return SDValue();
3295}
3296
3297SDValue DAGCombiner::visitSUBSAT(SDNode *N) {
3298 SDValue N0 = N->getOperand(0);
3299 SDValue N1 = N->getOperand(1);
3300 EVT VT = N0.getValueType();
3301 SDLoc DL(N);
3302
3303 // fold vector ops
3304 if (VT.isVector()) {
3305 // TODO SimplifyVBinOp
3306
3307 // fold (sub_sat x, 0) -> x, vector edition
3308 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3309 return N0;
3310 }
3311
3312 // fold (sub_sat x, undef) -> 0
3313 if (N0.isUndef() || N1.isUndef())
3314 return DAG.getConstant(0, DL, VT);
3315
3316 // fold (sub_sat x, x) -> 0
3317 if (N0 == N1)
3318 return DAG.getConstant(0, DL, VT);
3319
3320 // fold (sub_sat c1, c2) -> c3
3321 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1}))
3322 return C;
3323
3324 // fold (sub_sat x, 0) -> x
3325 if (isNullConstant(N1))
3326 return N0;
3327
3328 return SDValue();
3329}
3330
3331SDValue DAGCombiner::visitSUBC(SDNode *N) {
3332 SDValue N0 = N->getOperand(0);
3333 SDValue N1 = N->getOperand(1);
3334 EVT VT = N0.getValueType();
3335 SDLoc DL(N);
3336
3337 // If the flag result is dead, turn this into an SUB.
3338 if (!N->hasAnyUseOfValue(1))
3339 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3340 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3341
3342 // fold (subc x, x) -> 0 + no borrow
3343 if (N0 == N1)
3344 return CombineTo(N, DAG.getConstant(0, DL, VT),
3345 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3346
3347 // fold (subc x, 0) -> x + no borrow
3348 if (isNullConstant(N1))
3349 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3350
3351 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3352 if (isAllOnesConstant(N0))
3353 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3354 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3355
3356 return SDValue();
3357}
3358
3359SDValue DAGCombiner::visitSUBO(SDNode *N) {
3360 SDValue N0 = N->getOperand(0);
3361 SDValue N1 = N->getOperand(1);
3362 EVT VT = N0.getValueType();
3363 bool IsSigned = (ISD::SSUBO == N->getOpcode());
3364
3365 EVT CarryVT = N->getValueType(1);
3366 SDLoc DL(N);
3367
3368 // If the flag result is dead, turn this into an SUB.
3369 if (!N->hasAnyUseOfValue(1))
3370 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3371 DAG.getUNDEF(CarryVT));
3372
3373 // fold (subo x, x) -> 0 + no borrow
3374 if (N0 == N1)
3375 return CombineTo(N, DAG.getConstant(0, DL, VT),
3376 DAG.getConstant(0, DL, CarryVT));
3377
3378 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3379
3380 // fold (subox, c) -> (addo x, -c)
3381 if (IsSigned && N1C && !N1C->getAPIntValue().isMinSignedValue()) {
3382 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0,
3383 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
3384 }
3385
3386 // fold (subo x, 0) -> x + no borrow
3387 if (isNullOrNullSplat(N1))
3388 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
3389
3390 // Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3391 if (!IsSigned && isAllOnesOrAllOnesSplat(N0))
3392 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3393 DAG.getConstant(0, DL, CarryVT));
3394
3395 return SDValue();
3396}
3397
3398SDValue DAGCombiner::visitSUBE(SDNode *N) {
3399 SDValue N0 = N->getOperand(0);
3400 SDValue N1 = N->getOperand(1);
3401 SDValue CarryIn = N->getOperand(2);
3402
3403 // fold (sube x, y, false) -> (subc x, y)
3404 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
3405 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
3406
3407 return SDValue();
3408}
3409
3410SDValue DAGCombiner::visitSUBCARRY(SDNode *N) {
3411 SDValue N0 = N->getOperand(0);
3412 SDValue N1 = N->getOperand(1);
3413 SDValue CarryIn = N->getOperand(2);
3414
3415 // fold (subcarry x, y, false) -> (usubo x, y)
3416 if (isNullConstant(CarryIn)) {
3417 if (!LegalOperations ||
3418 TLI.isOperationLegalOrCustom(ISD::USUBO, N->getValueType(0)))
3419 return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
3420 }
3421
3422 return SDValue();
3423}
3424
3425// Notice that "mulfix" can be any of SMULFIX, SMULFIXSAT, UMULFIX and
3426// UMULFIXSAT here.
3427SDValue DAGCombiner::visitMULFIX(SDNode *N) {
3428 SDValue N0 = N->getOperand(0);
3429 SDValue N1 = N->getOperand(1);
3430 SDValue Scale = N->getOperand(2);
3431 EVT VT = N0.getValueType();
3432
3433 // fold (mulfix x, undef, scale) -> 0
3434 if (N0.isUndef() || N1.isUndef())
3435 return DAG.getConstant(0, SDLoc(N), VT);
3436
3437 // Canonicalize constant to RHS (vector doesn't have to splat)
3438 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3439 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3440 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale);
3441
3442 // fold (mulfix x, 0, scale) -> 0
3443 if (isNullConstant(N1))
3444 return DAG.getConstant(0, SDLoc(N), VT);
3445
3446 return SDValue();
3447}
3448
3449SDValue DAGCombiner::visitMUL(SDNode *N) {
3450 SDValue N0 = N->getOperand(0);
3451 SDValue N1 = N->getOperand(1);
3452 EVT VT = N0.getValueType();
3453
3454 // fold (mul x, undef) -> 0
3455 if (N0.isUndef() || N1.isUndef())
3456 return DAG.getConstant(0, SDLoc(N), VT);
3457
3458 bool N1IsConst = false;
3459 bool N1IsOpaqueConst = false;
3460 APInt ConstValue1;
3461
3462 // fold vector ops
3463 if (VT.isVector()) {
3464 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3465 return FoldedVOp;
3466
3467 N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1);
3468 assert((!N1IsConst ||(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3470, __PRETTY_FUNCTION__))
3469 ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) &&(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3470, __PRETTY_FUNCTION__))
3470 "Splat APInt should be element width")(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3470, __PRETTY_FUNCTION__))
;
3471 } else {
3472 N1IsConst = isa<ConstantSDNode>(N1);
3473 if (N1IsConst) {
3474 ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
3475 N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
3476 }
3477 }
3478
3479 // fold (mul c1, c2) -> c1*c2
3480 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT, {N0, N1}))
3481 return C;
3482
3483 // canonicalize constant to RHS (vector doesn't have to splat)
3484 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3485 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3486 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
3487
3488 // fold (mul x, 0) -> 0
3489 if (N1IsConst && ConstValue1.isNullValue())
3490 return N1;
3491
3492 // fold (mul x, 1) -> x
3493 if (N1IsConst && ConstValue1.isOneValue())
3494 return N0;
3495
3496 if (SDValue NewSel = foldBinOpIntoSelect(N))
3497 return NewSel;
3498
3499 // fold (mul x, -1) -> 0-x
3500 if (N1IsConst && ConstValue1.isAllOnesValue()) {
3501 SDLoc DL(N);
3502 return DAG.getNode(ISD::SUB, DL, VT,
3503 DAG.getConstant(0, DL, VT), N0);
3504 }
3505
3506 // fold (mul x, (1 << c)) -> x << c
3507 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3508 DAG.isKnownToBeAPowerOfTwo(N1) &&
3509 (!VT.isVector() || Level <= AfterLegalizeVectorOps)) {
3510 SDLoc DL(N);
3511 SDValue LogBase2 = BuildLogBase2(N1, DL);
3512 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3513 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
3514 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
3515 }
3516
3517 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
3518 if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2()) {
3519 unsigned Log2Val = (-ConstValue1).logBase2();
3520 SDLoc DL(N);
3521 // FIXME: If the input is something that is easily negated (e.g. a
3522 // single-use add), we should put the negate there.
3523 return DAG.getNode(ISD::SUB, DL, VT,
3524 DAG.getConstant(0, DL, VT),
3525 DAG.getNode(ISD::SHL, DL, VT, N0,
3526 DAG.getConstant(Log2Val, DL,
3527 getShiftAmountTy(N0.getValueType()))));
3528 }
3529
3530 // Try to transform multiply-by-(power-of-2 +/- 1) into shift and add/sub.
3531 // mul x, (2^N + 1) --> add (shl x, N), x
3532 // mul x, (2^N - 1) --> sub (shl x, N), x
3533 // Examples: x * 33 --> (x << 5) + x
3534 // x * 15 --> (x << 4) - x
3535 // x * -33 --> -((x << 5) + x)
3536 // x * -15 --> -((x << 4) - x) ; this reduces --> x - (x << 4)
3537 if (N1IsConst && TLI.decomposeMulByConstant(*DAG.getContext(), VT, N1)) {
3538 // TODO: We could handle more general decomposition of any constant by
3539 // having the target set a limit on number of ops and making a
3540 // callback to determine that sequence (similar to sqrt expansion).
3541 unsigned MathOp = ISD::DELETED_NODE;
3542 APInt MulC = ConstValue1.abs();
3543 if ((MulC - 1).isPowerOf2())
3544 MathOp = ISD::ADD;
3545 else if ((MulC + 1).isPowerOf2())
3546 MathOp = ISD::SUB;
3547
3548 if (MathOp != ISD::DELETED_NODE) {
3549 unsigned ShAmt =
3550 MathOp == ISD::ADD ? (MulC - 1).logBase2() : (MulC + 1).logBase2();
3551 assert(ShAmt < VT.getScalarSizeInBits() &&((ShAmt < VT.getScalarSizeInBits() && "multiply-by-constant generated out of bounds shift"
) ? static_cast<void> (0) : __assert_fail ("ShAmt < VT.getScalarSizeInBits() && \"multiply-by-constant generated out of bounds shift\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3552, __PRETTY_FUNCTION__))
3552 "multiply-by-constant generated out of bounds shift")((ShAmt < VT.getScalarSizeInBits() && "multiply-by-constant generated out of bounds shift"
) ? static_cast<void> (0) : __assert_fail ("ShAmt < VT.getScalarSizeInBits() && \"multiply-by-constant generated out of bounds shift\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3552, __PRETTY_FUNCTION__))
;
3553 SDLoc DL(N);
3554 SDValue Shl =
3555 DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT));
3556 SDValue R = DAG.getNode(MathOp, DL, VT, Shl, N0);
3557 if (ConstValue1.isNegative())
3558 R = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), R);
3559 return R;
3560 }
3561 }
3562
3563 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
3564 if (N0.getOpcode() == ISD::SHL &&
3565 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3566 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3567 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
3568 if (isConstantOrConstantVector(C3))
3569 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
3570 }
3571
3572 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
3573 // use.
3574 {
3575 SDValue Sh(nullptr, 0), Y(nullptr, 0);
3576
3577 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
3578 if (N0.getOpcode() == ISD::SHL &&
3579 isConstantOrConstantVector(N0.getOperand(1)) &&
3580 N0.getNode()->hasOneUse()) {
3581 Sh = N0; Y = N1;
3582 } else if (N1.getOpcode() == ISD::SHL &&
3583 isConstantOrConstantVector(N1.getOperand(1)) &&
3584 N1.getNode()->hasOneUse()) {
3585 Sh = N1; Y = N0;
3586 }
3587
3588 if (Sh.getNode()) {
3589 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, Sh.getOperand(0), Y);
3590 return DAG.getNode(ISD::SHL, SDLoc(N), VT, Mul, Sh.getOperand(1));
3591 }
3592 }
3593
3594 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
3595 if (DAG.isConstantIntBuildVectorOrConstantInt(N1) &&
3596 N0.getOpcode() == ISD::ADD &&
3597 DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
3598 isMulAddWithConstProfitable(N, N0, N1))
3599 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
3600 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
3601 N0.getOperand(0), N1),
3602 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
3603 N0.getOperand(1), N1));
3604
3605 // Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)).
3606 if (N0.getOpcode() == ISD::VSCALE)
3607 if (ConstantSDNode *NC1 = isConstOrConstSplat(N1)) {
3608 APInt C0 = N0.getConstantOperandAPInt(0);
3609 APInt C1 = NC1->getAPIntValue();
3610 return DAG.getVScale(SDLoc(N), VT, C0 * C1);
3611 }
3612
3613 // reassociate mul
3614 if (SDValue RMUL = reassociateOps(ISD::MUL, SDLoc(N), N0, N1, N->getFlags()))
3615 return RMUL;
3616
3617 return SDValue();
3618}
3619
3620/// Return true if divmod libcall is available.
3621static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
3622 const TargetLowering &TLI) {
3623 RTLIB::Libcall LC;
3624 EVT NodeType = Node->getValueType(0);
3625 if (!NodeType.isSimple())
3626 return false;
3627 switch (NodeType.getSimpleVT().SimpleTy) {
3628 default: return false; // No libcall for vector types.
3629 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
3630 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
3631 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
3632 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
3633 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
3634 }
3635
3636 return TLI.getLibcallName(LC) != nullptr;
3637}
3638
3639/// Issue divrem if both quotient and remainder are needed.
3640SDValue DAGCombiner::useDivRem(SDNode *Node) {
3641 if (Node->use_empty())
3642 return SDValue(); // This is a dead node, leave it alone.
3643
3644 unsigned Opcode = Node->getOpcode();
3645 bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
3646 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3647
3648 // DivMod lib calls can still work on non-legal types if using lib-calls.
3649 EVT VT = Node->getValueType(0);
3650 if (VT.isVector() || !VT.isInteger())
3651 return SDValue();
3652
3653 if (!TLI.isTypeLegal(VT) && !TLI.isOperationCustom(DivRemOpc, VT))
3654 return SDValue();
3655
3656 // If DIVREM is going to get expanded into a libcall,
3657 // but there is no libcall available, then don't combine.
3658 if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) &&
3659 !isDivRemLibcallAvailable(Node, isSigned, TLI))
3660 return SDValue();
3661
3662 // If div is legal, it's better to do the normal expansion
3663 unsigned OtherOpcode = 0;
3664 if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
3665 OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
3666 if (TLI.isOperationLegalOrCustom(Opcode, VT))
3667 return SDValue();
3668 } else {
3669 OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
3670 if (TLI.isOperationLegalOrCustom(OtherOpcode, VT))
3671 return SDValue();
3672 }
3673
3674 SDValue Op0 = Node->getOperand(0);
3675 SDValue Op1 = Node->getOperand(1);
3676 SDValue combined;
3677 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
3678 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
3679 SDNode *User = *UI;
3680 if (User == Node || User->getOpcode() == ISD::DELETED_NODE ||
3681 User->use_empty())
3682 continue;
3683 // Convert the other matching node(s), too;
3684 // otherwise, the DIVREM may get target-legalized into something
3685 // target-specific that we won't be able to recognize.
3686 unsigned UserOpc = User->getOpcode();
3687 if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) &&
3688 User->getOperand(0) == Op0 &&
3689 User->getOperand(1) == Op1) {
3690 if (!combined) {
3691 if (UserOpc == OtherOpcode) {
3692 SDVTList VTs = DAG.getVTList(VT, VT);
3693 combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1);
3694 } else if (UserOpc == DivRemOpc) {
3695 combined = SDValue(User, 0);
3696 } else {
3697 assert(UserOpc == Opcode)((UserOpc == Opcode) ? static_cast<void> (0) : __assert_fail
("UserOpc == Opcode", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3697, __PRETTY_FUNCTION__))
;
3698 continue;
3699 }
3700 }
3701 if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
3702 CombineTo(User, combined);
3703 else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
3704 CombineTo(User, combined.getValue(1));
3705 }
3706 }
3707 return combined;
3708}
3709
3710static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) {
3711 SDValue N0 = N->getOperand(0);
3712 SDValue N1 = N->getOperand(1);
3713 EVT VT = N->getValueType(0);
3714 SDLoc DL(N);
3715
3716 unsigned Opc = N->getOpcode();
3717 bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc);
3718 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3719
3720 // X / undef -> undef
3721 // X % undef -> undef
3722 // X / 0 -> undef
3723 // X % 0 -> undef
3724 // NOTE: This includes vectors where any divisor element is zero/undef.
3725 if (DAG.isUndef(Opc, {N0, N1}))
3726 return DAG.getUNDEF(VT);
3727
3728 // undef / X -> 0
3729 // undef % X -> 0
3730 if (N0.isUndef())
3731 return DAG.getConstant(0, DL, VT);
3732
3733 // 0 / X -> 0
3734 // 0 % X -> 0
3735 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3736 if (N0C && N0C->isNullValue())
3737 return N0;
3738
3739 // X / X -> 1
3740 // X % X -> 0
3741 if (N0 == N1)
3742 return DAG.getConstant(IsDiv ? 1 : 0, DL, VT);
3743
3744 // X / 1 -> X
3745 // X % 1 -> 0
3746 // If this is a boolean op (single-bit element type), we can't have
3747 // division-by-zero or remainder-by-zero, so assume the divisor is 1.
3748 // TODO: Similarly, if we're zero-extending a boolean divisor, then assume
3749 // it's a 1.
3750 if ((N1C && N1C->isOne()) || (VT.getScalarType() == MVT::i1))
3751 return IsDiv ? N0 : DAG.getConstant(0, DL, VT);
3752
3753 return SDValue();
3754}
3755
3756SDValue DAGCombiner::visitSDIV(SDNode *N) {
3757 SDValue N0 = N->getOperand(0);
3758 SDValue N1 = N->getOperand(1);
3759 EVT VT = N->getValueType(0);
3760 EVT CCVT = getSetCCResultType(VT);
3761
3762 // fold vector ops
3763 if (VT.isVector())
3764 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3765 return FoldedVOp;
3766
3767 SDLoc DL(N);
3768
3769 // fold (sdiv c1, c2) -> c1/c2
3770 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3771 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, {N0, N1}))
3772 return C;
3773
3774 // fold (sdiv X, -1) -> 0-X
3775 if (N1C && N1C->isAllOnesValue())
3776 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
3777
3778 // fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0)
3779 if (N1C && N1C->getAPIntValue().isMinSignedValue())
3780 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
3781 DAG.getConstant(1, DL, VT),
3782 DAG.getConstant(0, DL, VT));
3783
3784 if (SDValue V = simplifyDivRem(N, DAG))
3785 return V;
3786
3787 if (SDValue NewSel = foldBinOpIntoSelect(N))
3788 return NewSel;
3789
3790 // If we know the sign bits of both operands are zero, strength reduce to a
3791 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
3792 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
3793 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
3794
3795 if (SDValue V = visitSDIVLike(N0, N1, N)) {
3796 // If the corresponding remainder node exists, update its users with
3797 // (Dividend - (Quotient * Divisor).
3798 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(),
3799 { N0, N1 })) {
3800 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
3801 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3802 AddToWorklist(Mul.getNode());
3803 AddToWorklist(Sub.getNode());
3804 CombineTo(RemNode, Sub);
3805 }
3806 return V;
3807 }
3808
3809 // sdiv, srem -> sdivrem
3810 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
3811 // true. Otherwise, we break the simplification logic in visitREM().
3812 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3813 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
3814 if (SDValue DivRem = useDivRem(N))
3815 return DivRem;
3816
3817 return SDValue();
3818}
3819
3820SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
3821 SDLoc DL(N);
3822 EVT VT = N->getValueType(0);
3823 EVT CCVT = getSetCCResultType(VT);
3824 unsigned BitWidth = VT.getScalarSizeInBits();
3825
3826 // Helper for determining whether a value is a power-2 constant scalar or a
3827 // vector of such elements.
3828 auto IsPowerOfTwo = [](ConstantSDNode *C) {
3829 if (C->isNullValue() || C->isOpaque())
3830 return false;
3831 if (C->getAPIntValue().isPowerOf2())
3832 return true;
3833 if ((-C->getAPIntValue()).isPowerOf2())
3834 return true;
3835 return false;
3836 };
3837
3838 // fold (sdiv X, pow2) -> simple ops after legalize
3839 // FIXME: We check for the exact bit here because the generic lowering gives
3840 // better results in that case. The target-specific lowering should learn how
3841 // to handle exact sdivs efficiently.
3842 if (!N->getFlags().hasExact() && ISD::matchUnaryPredicate(N1, IsPowerOfTwo)) {
3843 // Target-specific implementation of sdiv x, pow2.
3844 if (SDValue Res = BuildSDIVPow2(N))
3845 return Res;
3846
3847 // Create constants that are functions of the shift amount value.
3848 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
3849 SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy);
3850 SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1);
3851 C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy);
3852 SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1);
3853 if (!isConstantOrConstantVector(Inexact))
3854 return SDValue();
3855
3856 // Splat the sign bit into the register
3857 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
3858 DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy));
3859 AddToWorklist(Sign.getNode());
3860
3861 // Add (N0 < 0) ? abs2 - 1 : 0;
3862 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
3863 AddToWorklist(Srl.getNode());
3864 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl);
3865 AddToWorklist(Add.getNode());
3866 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);
3867 AddToWorklist(Sra.getNode());
3868
3869 // Special case: (sdiv X, 1) -> X
3870 // Special Case: (sdiv X, -1) -> 0-X
3871 SDValue One = DAG.getConstant(1, DL, VT);
3872 SDValue AllOnes = DAG.getAllOnesConstant(DL, VT);
3873 SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ);
3874 SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ);
3875 SDValue IsOneOrAllOnes = DAG.getNode(ISD::OR, DL, CCVT, IsOne, IsAllOnes);
3876 Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra);
3877
3878 // If dividing by a positive value, we're done. Otherwise, the result must
3879 // be negated.
3880 SDValue Zero = DAG.getConstant(0, DL, VT);
3881 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra);
3882
3883 // FIXME: Use SELECT_CC once we improve SELECT_CC constant-folding.
3884 SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT);
3885 SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra);
3886 return Res;
3887 }
3888
3889 // If integer divide is expensive and we satisfy the requirements, emit an
3890 // alternate sequence. Targets may check function attributes for size/speed
3891 // trade-offs.
3892 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3893 if (isConstantOrConstantVector(N1) &&
3894 !TLI.isIntDivCheap(N->getValueType(0), Attr))
3895 if (SDValue Op = BuildSDIV(N))
3896 return Op;
3897
3898 return SDValue();
3899}
3900
3901SDValue DAGCombiner::visitUDIV(SDNode *N) {
3902 SDValue N0 = N->getOperand(0);
3903 SDValue N1 = N->getOperand(1);
3904 EVT VT = N->getValueType(0);
3905 EVT CCVT = getSetCCResultType(VT);
3906
3907 // fold vector ops
3908 if (VT.isVector())
3909 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3910 return FoldedVOp;
3911
3912 SDLoc DL(N);
3913
3914 // fold (udiv c1, c2) -> c1/c2
3915 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3916 if (SDValue C = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT, {N0, N1}))
3917 return C;
3918
3919 // fold (udiv X, -1) -> select(X == -1, 1, 0)
3920 if (N1C && N1C->getAPIntValue().isAllOnesValue())
3921 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
3922 DAG.getConstant(1, DL, VT),
3923 DAG.getConstant(0, DL, VT));
3924
3925 if (SDValue V = simplifyDivRem(N, DAG))
3926 return V;
3927
3928 if (SDValue NewSel = foldBinOpIntoSelect(N))
3929 return NewSel;
3930
3931 if (SDValue V = visitUDIVLike(N0, N1, N)) {
3932 // If the corresponding remainder node exists, update its users with
3933 // (Dividend - (Quotient * Divisor).
3934 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(),
3935 { N0, N1 })) {
3936 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
3937 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3938 AddToWorklist(Mul.getNode());
3939 AddToWorklist(Sub.getNode());
3940 CombineTo(RemNode, Sub);
3941 }
3942 return V;
3943 }
3944
3945 // sdiv, srem -> sdivrem
3946 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
3947 // true. Otherwise, we break the simplification logic in visitREM().
3948 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3949 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
3950 if (SDValue DivRem = useDivRem(N))
3951 return DivRem;
3952
3953 return SDValue();
3954}
3955
3956SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) {
3957 SDLoc DL(N);
3958 EVT VT = N->getValueType(0);
3959
3960 // fold (udiv x, (1 << c)) -> x >>u c
3961 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3962 DAG.isKnownToBeAPowerOfTwo(N1)) {
3963 SDValue LogBase2 = BuildLogBase2(N1, DL);
3964 AddToWorklist(LogBase2.getNode());
3965
3966 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3967 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
3968 AddToWorklist(Trunc.getNode());
3969 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
3970 }
3971
3972 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
3973 if (N1.getOpcode() == ISD::SHL) {
3974 SDValue N10 = N1.getOperand(0);
3975 if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) &&
3976 DAG.isKnownToBeAPowerOfTwo(N10)) {
3977 SDValue LogBase2 = BuildLogBase2(N10, DL);
3978 AddToWorklist(LogBase2.getNode());
3979
3980 EVT ADDVT = N1.getOperand(1).getValueType();
3981 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT);
3982 AddToWorklist(Trunc.getNode());
3983 SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc);
3984 AddToWorklist(Add.getNode());
3985 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
3986 }
3987 }
3988
3989 // fold (udiv x, c) -> alternate
3990 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3991 if (isConstantOrConstantVector(N1) &&
3992 !TLI.isIntDivCheap(N->getValueType(0), Attr))
3993 if (SDValue Op = BuildUDIV(N))
3994 return Op;
3995
3996 return SDValue();
3997}
3998
3999// handles ISD::SREM and ISD::UREM
4000SDValue DAGCombiner::visitREM(SDNode *N) {
4001 unsigned Opcode = N->getOpcode();
4002 SDValue N0 = N->getOperand(0);
4003 SDValue N1 = N->getOperand(1);
4004 EVT VT = N->getValueType(0);
4005 EVT CCVT = getSetCCResultType(VT);
4006
4007 bool isSigned = (Opcode == ISD::SREM);
4008 SDLoc DL(N);
4009
4010 // fold (rem c1, c2) -> c1%c2
4011 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4012 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
4013 return C;
4014
4015 // fold (urem X, -1) -> select(X == -1, 0, x)
4016 if (!isSigned && N1C && N1C->getAPIntValue().isAllOnesValue())
4017 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4018 DAG.getConstant(0, DL, VT), N0);
4019
4020 if (SDValue V = simplifyDivRem(N, DAG))
4021 return V;
4022
4023 if (SDValue NewSel = foldBinOpIntoSelect(N))
4024 return NewSel;
4025
4026 if (isSigned) {
4027 // If we know the sign bits of both operands are zero, strength reduce to a
4028 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
4029 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
4030 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
4031 } else {
4032 SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
4033 if (DAG.isKnownToBeAPowerOfTwo(N1)) {
4034 // fold (urem x, pow2) -> (and x, pow2-1)
4035 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
4036 AddToWorklist(Add.getNode());
4037 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
4038 }
4039 if (N1.getOpcode() == ISD::SHL &&
4040 DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) {
4041 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
4042 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
4043 AddToWorklist(Add.getNode());
4044 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
4045 }
4046 }
4047
4048 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4049
4050 // If X/C can be simplified by the division-by-constant logic, lower
4051 // X%C to the equivalent of X-X/C*C.
4052 // Reuse the SDIVLike/UDIVLike combines - to avoid mangling nodes, the
4053 // speculative DIV must not cause a DIVREM conversion. We guard against this
4054 // by skipping the simplification if isIntDivCheap(). When div is not cheap,
4055 // combine will not return a DIVREM. Regardless, checking cheapness here
4056 // makes sense since the simplification results in fatter code.
4057 if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) {
4058 SDValue OptimizedDiv =
4059 isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N);
4060 if (OptimizedDiv.getNode()) {
4061 // If the equivalent Div node also exists, update its users.
4062 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
4063 if (SDNode *DivNode = DAG.getNodeIfExists(DivOpcode, N->getVTList(),
4064 { N0, N1 }))
4065 CombineTo(DivNode, OptimizedDiv);
4066 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1);
4067 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4068 AddToWorklist(OptimizedDiv.getNode());
4069 AddToWorklist(Mul.getNode());
4070 return Sub;
4071 }
4072 }
4073
4074 // sdiv, srem -> sdivrem
4075 if (SDValue DivRem = useDivRem(N))
4076 return DivRem.getValue(1);
4077
4078 return SDValue();
4079}
4080
4081SDValue DAGCombiner::visitMULHS(SDNode *N) {
4082 SDValue N0 = N->getOperand(0);
4083 SDValue N1 = N->getOperand(1);
4084 EVT VT = N->getValueType(0);
4085 SDLoc DL(N);
4086
4087 if (VT.isVector()) {
4088 // fold (mulhs x, 0) -> 0
4089 // do not return N0/N1, because undef node may exist.
4090 if (ISD::isBuildVectorAllZeros(N0.getNode()) ||
4091 ISD::isBuildVectorAllZeros(N1.getNode()))
4092 return DAG.getConstant(0, DL, VT);
4093 }
4094
4095 // fold (mulhs x, 0) -> 0
4096 if (isNullConstant(N1))
4097 return N1;
4098 // fold (mulhs x, 1) -> (sra x, size(x)-1)
4099 if (isOneConstant(N1))
4100 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
4101 DAG.getConstant(N0.getScalarValueSizeInBits() - 1, DL,
4102 getShiftAmountTy(N0.getValueType())));
4103
4104 // fold (mulhs x, undef) -> 0
4105 if (N0.isUndef() || N1.isUndef())
4106 return DAG.getConstant(0, DL, VT);
4107
4108 // If the type twice as wide is legal, transform the mulhs to a wider multiply
4109 // plus a shift.
4110 if (VT.isSimple() && !VT.isVector()) {
4111 MVT Simple = VT.getSimpleVT();
4112 unsigned SimpleSize = Simple.getSizeInBits();
4113 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4114 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4115 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
4116 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
4117 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
4118 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
4119 DAG.getConstant(SimpleSize, DL,
4120 getShiftAmountTy(N1.getValueType())));
4121 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
4122 }
4123 }
4124
4125 return SDValue();
4126}
4127
4128SDValue DAGCombiner::visitMULHU(SDNode *N) {
4129 SDValue N0 = N->getOperand(0);
4130 SDValue N1 = N->getOperand(1);
4131 EVT VT = N->getValueType(0);
4132 SDLoc DL(N);
4133
4134 if (VT.isVector()) {
4135 // fold (mulhu x, 0) -> 0
4136 // do not return N0/N1, because undef node may exist.
4137 if (ISD::isBuildVectorAllZeros(N0.getNode()) ||
4138 ISD::isBuildVectorAllZeros(N1.getNode()))
4139 return DAG.getConstant(0, DL, VT);
4140 }
4141
4142 // fold (mulhu x, 0) -> 0
4143 if (isNullConstant(N1))
4144 return N1;
4145 // fold (mulhu x, 1) -> 0
4146 if (isOneConstant(N1))
4147 return DAG.getConstant(0, DL, N0.getValueType());
4148 // fold (mulhu x, undef) -> 0
4149 if (N0.isUndef() || N1.isUndef())
4150 return DAG.getConstant(0, DL, VT);
4151
4152 // fold (mulhu x, (1 << c)) -> x >> (bitwidth - c)
4153 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
4154 DAG.isKnownToBeAPowerOfTwo(N1) && hasOperation(ISD::SRL, VT)) {
4155 unsigned NumEltBits = VT.getScalarSizeInBits();
4156 SDValue LogBase2 = BuildLogBase2(N1, DL);
4157 SDValue SRLAmt = DAG.getNode(
4158 ISD::SUB, DL, VT, DAG.getConstant(NumEltBits, DL, VT), LogBase2);
4159 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
4160 SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT);
4161 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
4162 }
4163
4164 // If the type twice as wide is legal, transform the mulhu to a wider multiply
4165 // plus a shift.
4166 if (VT.isSimple() && !VT.isVector()) {
4167 MVT Simple = VT.getSimpleVT();
4168 unsigned SimpleSize = Simple.getSizeInBits();
4169 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4170 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4171 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
4172 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
4173 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
4174 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
4175 DAG.getConstant(SimpleSize, DL,
4176 getShiftAmountTy(N1.getValueType())));
4177 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
4178 }
4179 }
4180
4181 return SDValue();
4182}
4183
4184/// Perform optimizations common to nodes that compute two values. LoOp and HiOp
4185/// give the opcodes for the two computations that are being performed. Return
4186/// true if a simplification was made.
4187SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
4188 unsigned HiOp) {
4189 // If the high half is not needed, just compute the low half.
4190 bool HiExists = N->hasAnyUseOfValue(1);
4191 if (!HiExists && (!LegalOperations ||
4192 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
4193 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4194 return CombineTo(N, Res, Res);
4195 }
4196
4197 // If the low half is not needed, just compute the high half.
4198 bool LoExists = N->hasAnyUseOfValue(0);
4199 if (!LoExists && (!LegalOperations ||
4200 TLI.isOperationLegalOrCustom(HiOp, N->getValueType(1)))) {
4201 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4202 return CombineTo(N, Res, Res);
4203 }
4204
4205 // If both halves are used, return as it is.
4206 if (LoExists && HiExists)
4207 return SDValue();
4208
4209 // If the two computed results can be simplified separately, separate them.
4210 if (LoExists) {
4211 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4212 AddToWorklist(Lo.getNode());
4213 SDValue LoOpt = combine(Lo.getNode());
4214 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
4215 (!LegalOperations ||
4216 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType())))
4217 return CombineTo(N, LoOpt, LoOpt);
4218 }
4219
4220 if (HiExists) {
4221 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4222 AddToWorklist(Hi.getNode());
4223 SDValue HiOpt = combine(Hi.getNode());
4224 if (HiOpt.getNode() && HiOpt != Hi &&
4225 (!LegalOperations ||
4226 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType())))
4227 return CombineTo(N, HiOpt, HiOpt);
4228 }
4229
4230 return SDValue();
4231}
4232
4233SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
4234 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
4235 return Res;
4236
4237 EVT VT = N->getValueType(0);
4238 SDLoc DL(N);
4239
4240 // If the type is twice as wide is legal, transform the mulhu to a wider
4241 // multiply plus a shift.
4242 if (VT.isSimple() && !VT.isVector()) {
4243 MVT Simple = VT.getSimpleVT();
4244 unsigned SimpleSize = Simple.getSizeInBits();
4245 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4246 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4247 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
4248 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
4249 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
4250 // Compute the high part as N1.
4251 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
4252 DAG.getConstant(SimpleSize, DL,
4253 getShiftAmountTy(Lo.getValueType())));
4254 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
4255 // Compute the low part as N0.
4256 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
4257 return CombineTo(N, Lo, Hi);
4258 }
4259 }
4260
4261 return SDValue();
4262}
4263
4264SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
4265 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
4266 return Res;
4267
4268 EVT VT = N->getValueType(0);
4269 SDLoc DL(N);
4270
4271 // (umul_lohi N0, 0) -> (0, 0)
4272 if (isNullConstant(N->getOperand(1))) {
4273 SDValue Zero = DAG.getConstant(0, DL, VT);
4274 return CombineTo(N, Zero, Zero);
4275 }
4276
4277 // (umul_lohi N0, 1) -> (N0, 0)
4278 if (isOneConstant(N->getOperand(1))) {
4279 SDValue Zero = DAG.getConstant(0, DL, VT);
4280 return CombineTo(N, N->getOperand(0), Zero);
4281 }
4282
4283 // If the type is twice as wide is legal, transform the mulhu to a wider
4284 // multiply plus a shift.
4285 if (VT.isSimple() && !VT.isVector()) {
4286 MVT Simple = VT.getSimpleVT();
4287 unsigned SimpleSize = Simple.getSizeInBits();
4288 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4289 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4290 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
4291 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
4292 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
4293 // Compute the high part as N1.
4294 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
4295 DAG.getConstant(SimpleSize, DL,
4296 getShiftAmountTy(Lo.getValueType())));
4297 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
4298 // Compute the low part as N0.
4299 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
4300 return CombineTo(N, Lo, Hi);
4301 }
4302 }
4303
4304 return SDValue();
4305}
4306
4307SDValue DAGCombiner::visitMULO(SDNode *N) {
4308 SDValue N0 = N->getOperand(0);
4309 SDValue N1 = N->getOperand(1);
4310 EVT VT = N0.getValueType();
4311 bool IsSigned = (ISD::SMULO == N->getOpcode());
4312
4313 EVT CarryVT = N->getValueType(1);
4314 SDLoc DL(N);
4315
4316 // canonicalize constant to RHS.
4317 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4318 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4319 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
4320
4321 // fold (mulo x, 0) -> 0 + no carry out
4322 if (isNullOrNullSplat(N1))
4323 return CombineTo(N, DAG.getConstant(0, DL, VT),
4324 DAG.getConstant(0, DL, CarryVT));
4325
4326 // (mulo x, 2) -> (addo x, x)
4327 if (ConstantSDNode *C2 = isConstOrConstSplat(N1))
4328 if (C2->getAPIntValue() == 2)
4329 return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL,
4330 N->getVTList(), N0, N0);
4331
4332 return SDValue();
4333}
4334
4335SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
4336 SDValue N0 = N->getOperand(0);
4337 SDValue N1 = N->getOperand(1);
4338 EVT VT = N0.getValueType();
4339 unsigned Opcode = N->getOpcode();
4340
4341 // fold vector ops
4342 if (VT.isVector())
4343 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4344 return FoldedVOp;
4345
4346 // fold operation with constant operands.
4347 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, SDLoc(N), VT, {N0, N1}))
4348 return C;
4349
4350 // canonicalize constant to RHS
4351 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4352 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4353 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
4354
4355 // Is sign bits are zero, flip between UMIN/UMAX and SMIN/SMAX.
4356 // Only do this if the current op isn't legal and the flipped is.
4357 if (!TLI.isOperationLegal(Opcode, VT) &&
4358 (N0.isUndef() || DAG.SignBitIsZero(N0)) &&
4359 (N1.isUndef() || DAG.SignBitIsZero(N1))) {
4360 unsigned AltOpcode;
4361 switch (Opcode) {
4362 case ISD::SMIN: AltOpcode = ISD::UMIN; break;
4363 case ISD::SMAX: AltOpcode = ISD::UMAX; break;
4364 case ISD::UMIN: AltOpcode = ISD::SMIN; break;
4365 case ISD::UMAX: AltOpcode = ISD::SMAX; break;
4366 default: llvm_unreachable("Unknown MINMAX opcode")::llvm::llvm_unreachable_internal("Unknown MINMAX opcode", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4366)
;
4367 }
4368 if (TLI.isOperationLegal(AltOpcode, VT))
4369 return DAG.getNode(AltOpcode, SDLoc(N), VT, N0, N1);
4370 }
4371
4372 return SDValue();
4373}
4374
4375/// If this is a bitwise logic instruction and both operands have the same
4376/// opcode, try to sink the other opcode after the logic instruction.
4377SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
4378 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4379 EVT VT = N0.getValueType();
4380 unsigned LogicOpcode = N->getOpcode();
4381 unsigned HandOpcode = N0.getOpcode();
4382 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
== ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4383, __PRETTY_FUNCTION__))
4383 LogicOpcode == ISD::XOR) && "Expected logic opcode")(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
== ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4383, __PRETTY_FUNCTION__))
;
4384 assert(HandOpcode == N1.getOpcode() && "Bad input!")((HandOpcode == N1.getOpcode() && "Bad input!") ? static_cast
<void> (0) : __assert_fail ("HandOpcode == N1.getOpcode() && \"Bad input!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4384, __PRETTY_FUNCTION__))
;
4385
4386 // Bail early if none of these transforms apply.
4387 if (N0.getNumOperands() == 0)
4388 return SDValue();
4389
4390 // FIXME: We should check number of uses of the operands to not increase
4391 // the instruction count for all transforms.
4392
4393 // Handle size-changing casts.
4394 SDValue X = N0.getOperand(0);
4395 SDValue Y = N1.getOperand(0);
4396 EVT XVT = X.getValueType();
4397 SDLoc DL(N);
4398 if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND ||
4399 HandOpcode == ISD::SIGN_EXTEND) {
4400 // If both operands have other uses, this transform would create extra
4401 // instructions without eliminating anything.
4402 if (!N0.hasOneUse() && !N1.hasOneUse())
4403 return SDValue();
4404 // We need matching integer source types.
4405 if (XVT != Y.getValueType())
4406 return SDValue();
4407 // Don't create an illegal op during or after legalization. Don't ever
4408 // create an unsupported vector op.
4409 if ((VT.isVector() || LegalOperations) &&
4410 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT))
4411 return SDValue();
4412 // Avoid infinite looping with PromoteIntBinOp.
4413 // TODO: Should we apply desirable/legal constraints to all opcodes?
4414 if (HandOpcode == ISD::ANY_EXTEND && LegalTypes &&
4415 !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
4416 return SDValue();
4417 // logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y)
4418 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4419 return DAG.getNode(HandOpcode, DL, VT, Logic);
4420 }
4421
4422 // logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)
4423 if (HandOpcode == ISD::TRUNCATE) {
4424 // If both operands have other uses, this transform would create extra
4425 // instructions without eliminating anything.
4426 if (!N0.hasOneUse() && !N1.hasOneUse())
4427 return SDValue();
4428 // We need matching source types.
4429 if (XVT != Y.getValueType())
4430 return SDValue();
4431 // Don't create an illegal op during or after legalization.
4432 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
4433 return SDValue();
4434 // Be extra careful sinking truncate. If it's free, there's no benefit in
4435 // widening a binop. Also, don't create a logic op on an illegal type.
4436 if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT))
4437 return SDValue();
4438 if (!TLI.isTypeLegal(XVT))
4439 return SDValue();
4440 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4441 return DAG.getNode(HandOpcode, DL, VT, Logic);
4442 }
4443
4444 // For binops SHL/SRL/SRA/AND:
4445 // logic_op (OP x, z), (OP y, z) --> OP (logic_op x, y), z
4446 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL ||
4447 HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
4448 N0.getOperand(1) == N1.getOperand(1)) {
4449 // If either operand has other uses, this transform is not an improvement.
4450 if (!N0.hasOneUse() || !N1.hasOneUse())
4451 return SDValue();
4452 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4453 return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
4454 }
4455
4456 // Unary ops: logic_op (bswap x), (bswap y) --> bswap (logic_op x, y)
4457 if (HandOpcode == ISD::BSWAP) {
4458 // If either operand has other uses, this transform is not an improvement.
4459 if (!N0.hasOneUse() || !N1.hasOneUse())
4460 return SDValue();
4461 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4462 return DAG.getNode(HandOpcode, DL, VT, Logic);
4463 }
4464
4465 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
4466 // Only perform this optimization up until type legalization, before
4467 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
4468 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
4469 // we don't want to undo this promotion.
4470 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
4471 // on scalars.
4472 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
4473 Level <= AfterLegalizeTypes) {
4474 // Input types must be integer and the same.
4475 if (XVT.isInteger() && XVT == Y.getValueType() &&
4476 !(VT.isVector() && TLI.isTypeLegal(VT) &&
4477 !XVT.isVector() && !TLI.isTypeLegal(XVT))) {
4478 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4479 return DAG.getNode(HandOpcode, DL, VT, Logic);
4480 }
4481 }
4482
4483 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
4484 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
4485 // If both shuffles use the same mask, and both shuffle within a single
4486 // vector, then it is worthwhile to move the swizzle after the operation.
4487 // The type-legalizer generates this pattern when loading illegal
4488 // vector types from memory. In many cases this allows additional shuffle
4489 // optimizations.
4490 // There are other cases where moving the shuffle after the xor/and/or
4491 // is profitable even if shuffles don't perform a swizzle.
4492 // If both shuffles use the same mask, and both shuffles have the same first
4493 // or second operand, then it might still be profitable to move the shuffle
4494 // after the xor/and/or operation.
4495 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
4496 auto *SVN0 = cast<ShuffleVectorSDNode>(N0);
4497 auto *SVN1 = cast<ShuffleVectorSDNode>(N1);
4498 assert(X.getValueType() == Y.getValueType() &&((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4499, __PRETTY_FUNCTION__))
4499 "Inputs to shuffles are not the same type")((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4499, __PRETTY_FUNCTION__))
;
4500
4501 // Check that both shuffles use the same mask. The masks are known to be of
4502 // the same length because the result vector type is the same.
4503 // Check also that shuffles have only one use to avoid introducing extra
4504 // instructions.
4505 if (!SVN0->hasOneUse() || !SVN1->hasOneUse() ||
4506 !SVN0->getMask().equals(SVN1->getMask()))
4507 return SDValue();
4508
4509 // Don't try to fold this node if it requires introducing a
4510 // build vector of all zeros that might be illegal at this stage.
4511 SDValue ShOp = N0.getOperand(1);
4512 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4513 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4514
4515 // (logic_op (shuf (A, C), shuf (B, C))) --> shuf (logic_op (A, B), C)
4516 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
4517 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT,
4518 N0.getOperand(0), N1.getOperand(0));
4519 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask());
4520 }
4521
4522 // Don't try to fold this node if it requires introducing a
4523 // build vector of all zeros that might be illegal at this stage.
4524 ShOp = N0.getOperand(0);
4525 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4526 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4527
4528 // (logic_op (shuf (C, A), shuf (C, B))) --> shuf (C, logic_op (A, B))
4529 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
4530 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
4531 N1.getOperand(1));
4532 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask());
4533 }
4534 }
4535
4536 return SDValue();
4537}
4538
4539/// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient.
4540SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
4541 const SDLoc &DL) {
4542 SDValue LL, LR, RL, RR, N0CC, N1CC;
4543 if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
4544 !isSetCCEquivalent(N1, RL, RR, N1CC))
4545 return SDValue();
4546
4547 assert(N0.getValueType() == N1.getValueType() &&((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4548, __PRETTY_FUNCTION__))
4548 "Unexpected operand types for bitwise logic op")((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4548, __PRETTY_FUNCTION__))
;
4549 assert(LL.getValueType() == LR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4551, __PRETTY_FUNCTION__))
4550 RL.getValueType() == RR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4551, __PRETTY_FUNCTION__))
4551 "Unexpected operand types for setcc")((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4551, __PRETTY_FUNCTION__))
;
4552
4553 // If we're here post-legalization or the logic op type is not i1, the logic
4554 // op type must match a setcc result type. Also, all folds require new
4555 // operations on the left and right operands, so those types must match.
4556 EVT VT = N0.getValueType();
4557 EVT OpVT = LL.getValueType();
4558 if (LegalOperations || VT.getScalarType() != MVT::i1)
4559 if (VT != getSetCCResultType(OpVT))
4560 return SDValue();
4561 if (OpVT != RL.getValueType())
4562 return SDValue();
4563
4564 ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
4565 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
4566 bool IsInteger = OpVT.isInteger();
4567 if (LR == RR && CC0 == CC1 && IsInteger) {
4568 bool IsZero = isNullOrNullSplat(LR);
4569 bool IsNeg1 = isAllOnesOrAllOnesSplat(LR);
4570
4571 // All bits clear?
4572 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
4573 // All sign bits clear?
4574 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
4575 // Any bits set?
4576 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
4577 // Any sign bits set?
4578 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
4579
4580 // (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0)
4581 // (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
4582 // (or (setne X, 0), (setne Y, 0)) --> (setne (or X, Y), 0)
4583 // (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0)
4584 if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) {
4585 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
4586 AddToWorklist(Or.getNode());
4587 return DAG.getSetCC(DL, VT, Or, LR, CC1);
4588 }
4589
4590 // All bits set?
4591 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
4592 // All sign bits set?
4593 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
4594 // Any bits clear?
4595 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1;
4596 // Any sign bits clear?
4597 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1;
4598
4599 // (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
4600 // (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0)
4601 // (or (setne X, -1), (setne Y, -1)) --> (setne (and X, Y), -1)
4602 // (or (setgt X, -1), (setgt Y -1)) --> (setgt (and X, Y), -1)
4603 if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) {
4604 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
4605 AddToWorklist(And.getNode());
4606 return DAG.getSetCC(DL, VT, And, LR, CC1);
4607 }
4608 }
4609
4610 // TODO: What is the 'or' equivalent of this fold?
4611 // (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
4612 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 &&
4613 IsInteger && CC0 == ISD::SETNE &&
4614 ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
4615 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
4616 SDValue One = DAG.getConstant(1, DL, OpVT);
4617 SDValue Two = DAG.getConstant(2, DL, OpVT);
4618 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
4619 AddToWorklist(Add.getNode());
4620 return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
4621 }
4622
4623 // Try more general transforms if the predicates match and the only user of
4624 // the compares is the 'and' or 'or'.
4625 if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 &&
4626 N0.hasOneUse() && N1.hasOneUse()) {
4627 // and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
4628 // or (setne A, B), (setne C, D) --> setne (or (xor A, B), (xor C, D)), 0
4629 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) {
4630 SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR);
4631 SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR);
4632 SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR);
4633 SDValue Zero = DAG.getConstant(0, DL, OpVT);
4634 return DAG.getSetCC(DL, VT, Or, Zero, CC1);
4635 }
4636
4637 // Turn compare of constants whose difference is 1 bit into add+and+setcc.
4638 // TODO - support non-uniform vector amounts.
4639 if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) {
4640 // Match a shared variable operand and 2 non-opaque constant operands.
4641 ConstantSDNode *C0 = isConstOrConstSplat(LR);
4642 ConstantSDNode *C1 = isConstOrConstSplat(RR);
4643 if (LL == RL && C0 && C1 && !C0->isOpaque() && !C1->isOpaque()) {
4644 // Canonicalize larger constant as C0.
4645 if (C1->getAPIntValue().ugt(C0->getAPIntValue()))
4646 std::swap(C0, C1);
4647
4648 // The difference of the constants must be a single bit.
4649 const APInt &C0Val = C0->getAPIntValue();
4650 const APInt &C1Val = C1->getAPIntValue();
4651 if ((C0Val - C1Val).isPowerOf2()) {
4652 // and/or (setcc X, C0, ne), (setcc X, C1, ne/eq) -->
4653 // setcc ((add X, -C1), ~(C0 - C1)), 0, ne/eq
4654 SDValue OffsetC = DAG.getConstant(-C1Val, DL, OpVT);
4655 SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LL, OffsetC);
4656 SDValue MaskC = DAG.getConstant(~(C0Val - C1Val), DL, OpVT);
4657 SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Add, MaskC);
4658 SDValue Zero = DAG.getConstant(0, DL, OpVT);
4659 return DAG.getSetCC(DL, VT, And, Zero, CC0);
4660 }
4661 }
4662 }
4663 }
4664
4665 // Canonicalize equivalent operands to LL == RL.
4666 if (LL == RR && LR == RL) {
4667 CC1 = ISD::getSetCCSwappedOperands(CC1);
4668 std::swap(RL, RR);
4669 }
4670
4671 // (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
4672 // (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
4673 if (LL == RL && LR == RR) {
4674 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT)
4675 : ISD::getSetCCOrOperation(CC0, CC1, OpVT);
4676 if (NewCC != ISD::SETCC_INVALID &&
4677 (!LegalOperations ||
4678 (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
4679 TLI.isOperationLegal(ISD::SETCC, OpVT))))
4680 return DAG.getSetCC(DL, VT, LL, LR, NewCC);
4681 }
4682
4683 return SDValue();
4684}
4685
4686/// This contains all DAGCombine rules which reduce two values combined by
4687/// an And operation to a single value. This makes them reusable in the context
4688/// of visitSELECT(). Rules involving constants are not included as
4689/// visitSELECT() already handles those cases.
4690SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
4691 EVT VT = N1.getValueType();
4692 SDLoc DL(N);
4693
4694 // fold (and x, undef) -> 0
4695 if (N0.isUndef() || N1.isUndef())
4696 return DAG.getConstant(0, DL, VT);
4697
4698 if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
4699 return V;
4700
4701 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
4702 VT.getSizeInBits() <= 64) {
4703 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4704 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
4705 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
4706 // immediate for an add, but it is legal if its top c2 bits are set,
4707 // transform the ADD so the immediate doesn't need to be materialized
4708 // in a register.
4709 APInt ADDC = ADDI->getAPIntValue();
4710 APInt SRLC = SRLI->getAPIntValue();
4711 if (ADDC.getMinSignedBits() <= 64 &&
4712 SRLC.ult(VT.getSizeInBits()) &&
4713 !TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
4714 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
4715 SRLC.getZExtValue());
4716 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
4717 ADDC |= Mask;
4718 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
4719 SDLoc DL0(N0);
4720 SDValue NewAdd =
4721 DAG.getNode(ISD::ADD, DL0, VT,
4722 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
4723 CombineTo(N0.getNode(), NewAdd);
4724 // Return N so it doesn't get rechecked!
4725 return SDValue(N, 0);
4726 }
4727 }
4728 }
4729 }
4730 }
4731 }
4732
4733 // Reduce bit extract of low half of an integer to the narrower type.
4734 // (and (srl i64:x, K), KMask) ->
4735 // (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
4736 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4737 if (ConstantSDNode *CAnd = dyn_cast<ConstantSDNode>(N1)) {
4738 if (ConstantSDNode *CShift = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4739 unsigned Size = VT.getSizeInBits();
4740 const APInt &AndMask = CAnd->getAPIntValue();
4741 unsigned ShiftBits = CShift->getZExtValue();
4742
4743 // Bail out, this node will probably disappear anyway.
4744 if (ShiftBits == 0)
4745 return SDValue();
4746
4747 unsigned MaskBits = AndMask.countTrailingOnes();
4748 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);
4749
4750 if (AndMask.isMask() &&
4751 // Required bits must not span the two halves of the integer and
4752 // must fit in the half size type.
4753 (ShiftBits + MaskBits <= Size / 2) &&
4754 TLI.isNarrowingProfitable(VT, HalfVT) &&
4755 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
4756 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) &&
4757 TLI.isTruncateFree(VT, HalfVT) &&
4758 TLI.isZExtFree(HalfVT, VT)) {
4759 // The isNarrowingProfitable is to avoid regressions on PPC and
4760 // AArch64 which match a few 64-bit bit insert / bit extract patterns
4761 // on downstream users of this. Those patterns could probably be
4762 // extended to handle extensions mixed in.
4763
4764 SDValue SL(N0);
4765 assert(MaskBits <= Size)((MaskBits <= Size) ? static_cast<void> (0) : __assert_fail
("MaskBits <= Size", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4765, __PRETTY_FUNCTION__))
;
4766
4767 // Extracting the highest bit of the low half.
4768 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
4769 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT,
4770 N0.getOperand(0));
4771
4772 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT);
4773 SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT);
4774 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK);
4775 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask);
4776 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And);
4777 }
4778 }
4779 }
4780 }
4781
4782 return SDValue();
4783}
4784
4785bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
4786 EVT LoadResultTy, EVT &ExtVT) {
4787 if (!AndC->getAPIntValue().isMask())
4788 return false;
4789
4790 unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes();
4791
4792 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
4793 EVT LoadedVT = LoadN->getMemoryVT();
4794
4795 if (ExtVT == LoadedVT &&
4796 (!LegalOperations ||
4797 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
4798 // ZEXTLOAD will match without needing to change the size of the value being
4799 // loaded.
4800 return true;
4801 }
4802
4803 // Do not change the width of a volatile or atomic loads.
4804 if (!LoadN->isSimple())
4805 return false;
4806
4807 // Do not generate loads of non-round integer types since these can
4808 // be expensive (and would be wrong if the type is not byte sized).
4809 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound())
4810 return false;
4811
4812 if (LegalOperations &&
4813 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
4814 return false;
4815
4816 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
4817 return false;
4818
4819 return true;
4820}
4821
4822bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
4823 ISD::LoadExtType ExtType, EVT &MemVT,
4824 unsigned ShAmt) {
4825 if (!LDST)
4826 return false;
4827 // Only allow byte offsets.
4828 if (ShAmt % 8)
4829 return false;
4830
4831 // Do not generate loads of non-round integer types since these can
4832 // be expensive (and would be wrong if the type is not byte sized).
4833 if (!MemVT.isRound())
4834 return false;
4835
4836 // Don't change the width of a volatile or atomic loads.
4837 if (!LDST->isSimple())
4838 return false;
4839
4840 // Verify that we are actually reducing a load width here.
4841 if (LDST->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits())
4842 return false;
4843
4844 // Ensure that this isn't going to produce an unsupported memory access.
4845 if (ShAmt &&
4846 !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
4847 LDST->getAddressSpace(), ShAmt / 8,
4848 LDST->getMemOperand()->getFlags()))
4849 return false;
4850
4851 // It's not possible to generate a constant of extended or untyped type.
4852 EVT PtrType = LDST->getBasePtr().getValueType();
4853 if (PtrType == MVT::Untyped || PtrType.isExtended())
4854 return false;
4855
4856 if (isa<LoadSDNode>(LDST)) {
4857 LoadSDNode *Load = cast<LoadSDNode>(LDST);
4858 // Don't transform one with multiple uses, this would require adding a new
4859 // load.
4860 if (!SDValue(Load, 0).hasOneUse())
4861 return false;
4862
4863 if (LegalOperations &&
4864 !TLI.isLoadExtLegal(ExtType, Load->getValueType(0), MemVT))
4865 return false;
4866
4867 // For the transform to be legal, the load must produce only two values
4868 // (the value loaded and the chain). Don't transform a pre-increment
4869 // load, for example, which produces an extra value. Otherwise the
4870 // transformation is not equivalent, and the downstream logic to replace
4871 // uses gets things wrong.
4872 if (Load->getNumValues() > 2)
4873 return false;
4874
4875 // If the load that we're shrinking is an extload and we're not just
4876 // discarding the extension we can't simply shrink the load. Bail.
4877 // TODO: It would be possible to merge the extensions in some cases.
4878 if (Load->getExtensionType() != ISD::NON_EXTLOAD &&
4879 Load->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
4880 return false;
4881
4882 if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT))
4883 return false;
4884 } else {
4885 assert(isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode")((isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode"
) ? static_cast<void> (0) : __assert_fail ("isa<StoreSDNode>(LDST) && \"It is not a Load nor a Store SDNode\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4885, __PRETTY_FUNCTION__))
;
4886 StoreSDNode *Store = cast<StoreSDNode>(LDST);
4887 // Can't write outside the original store
4888 if (Store->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
4889 return false;
4890
4891 if (LegalOperations &&
4892 !TLI.isTruncStoreLegal(Store->getValue().getValueType(), MemVT))
4893 return false;
4894 }
4895 return true;
4896}
4897
4898bool DAGCombiner::SearchForAndLoads(SDNode *N,
4899 SmallVectorImpl<LoadSDNode*> &Loads,
4900 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
4901 ConstantSDNode *Mask,
4902 SDNode *&NodeToMask) {
4903 // Recursively search for the operands, looking for loads which can be
4904 // narrowed.
4905 for (SDValue Op : N->op_values()) {
4906 if (Op.getValueType().isVector())
4907 return false;
4908
4909 // Some constants may need fixing up later if they are too large.
4910 if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
4911 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
4912 (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
4913 NodesWithConsts.insert(N);
4914 continue;
4915 }
4916
4917 if (!Op.hasOneUse())
4918 return false;
4919
4920 switch(Op.getOpcode()) {
4921 case ISD::LOAD: {
4922 auto *Load = cast<LoadSDNode>(Op);
4923 EVT ExtVT;
4924 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
4925 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) {
4926
4927 // ZEXTLOAD is already small enough.
4928 if (Load->getExtensionType() == ISD::ZEXTLOAD &&
4929 ExtVT.bitsGE(Load->getMemoryVT()))
4930 continue;
4931
4932 // Use LE to convert equal sized loads to zext.
4933 if (ExtVT.bitsLE(Load->getMemoryVT()))
4934 Loads.push_back(Load);
4935
4936 continue;
4937 }
4938 return false;
4939 }
4940 case ISD::ZERO_EXTEND:
4941 case ISD::AssertZext: {
4942 unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
4943 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
4944 EVT VT = Op.getOpcode() == ISD::AssertZext ?
4945 cast<VTSDNode>(Op.getOperand(1))->getVT() :
4946 Op.getOperand(0).getValueType();
4947
4948 // We can accept extending nodes if the mask is wider or an equal
4949 // width to the original type.
4950 if (ExtVT.bitsGE(VT))
4951 continue;
4952 break;
4953 }
4954 case ISD::OR:
4955 case ISD::XOR:
4956 case ISD::AND:
4957 if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask,
4958 NodeToMask))
4959 return false;
4960 continue;
4961 }
4962
4963 // Allow one node which will masked along with any loads found.
4964 if (NodeToMask)
4965 return false;
4966
4967 // Also ensure that the node to be masked only produces one data result.
4968 NodeToMask = Op.getNode();
4969 if (NodeToMask->getNumValues() > 1) {
4970 bool HasValue = false;
4971 for (unsigned i = 0, e = NodeToMask->getNumValues(); i < e; ++i) {
4972 MVT VT = SDValue(NodeToMask, i).getSimpleValueType();
4973 if (VT != MVT::Glue && VT != MVT::Other) {
4974 if (HasValue) {
4975 NodeToMask = nullptr;
4976 return false;
4977 }
4978 HasValue = true;
4979 }
4980 }
4981 assert(HasValue && "Node to be masked has no data result?")((HasValue && "Node to be masked has no data result?"
) ? static_cast<void> (0) : __assert_fail ("HasValue && \"Node to be masked has no data result?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4981, __PRETTY_FUNCTION__))
;
4982 }
4983 }
4984 return true;
4985}
4986
4987bool DAGCombiner::BackwardsPropagateMask(SDNode *N) {
4988 auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
4989 if (!Mask)
4990 return false;
4991
4992 if (!Mask->getAPIntValue().isMask())
4993 return false;
4994
4995 // No need to do anything if the and directly uses a load.
4996 if (isa<LoadSDNode>(N->getOperand(0)))
4997 return false;
4998
4999 SmallVector<LoadSDNode*, 8> Loads;
5000 SmallPtrSet<SDNode*, 2> NodesWithConsts;
5001 SDNode *FixupNode = nullptr;
5002 if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) {
5003 if (Loads.size() == 0)
5004 return false;
5005
5006 LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Backwards propagate AND: "
; N->dump(); } } while (false)
;
5007 SDValue MaskOp = N->getOperand(1);
5008
5009 // If it exists, fixup the single node we allow in the tree that needs
5010 // masking.
5011 if (FixupNode) {
5012 LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "First, need to fix up: "; FixupNode
->dump(); } } while (false)
;
5013 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
5014 FixupNode->getValueType(0),
5015 SDValue(FixupNode, 0), MaskOp);
5016 DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And);
5017 if (And.getOpcode() == ISD ::AND)
5018 DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOp);
5019 }
5020
5021 // Narrow any constants that need it.
5022 for (auto *LogicN : NodesWithConsts) {
5023 SDValue Op0 = LogicN->getOperand(0);
5024 SDValue Op1 = LogicN->getOperand(1);
5025
5026 if (isa<ConstantSDNode>(Op0))
5027 std::swap(Op0, Op1);
5028
5029 SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(),
5030 Op1, MaskOp);
5031
5032 DAG.UpdateNodeOperands(LogicN, Op0, And);
5033 }
5034
5035 // Create narrow loads.
5036 for (auto *Load : Loads) {
5037 LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Propagate AND back to: "; Load
->dump(); } } while (false)
;
5038 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
5039 SDValue(Load, 0), MaskOp);
5040 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
5041 if (And.getOpcode() == ISD ::AND)
5042 And = SDValue(
5043 DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp), 0);
5044 SDValue NewLoad = ReduceLoadWidth(And.getNode());
5045 assert(NewLoad &&((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5046, __PRETTY_FUNCTION__))
5046 "Shouldn't be masking the load if it can't be narrowed")((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5046, __PRETTY_FUNCTION__))
;
5047 CombineTo(Load, NewLoad, NewLoad.getValue(1));
5048 }
5049 DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
5050 return true;
5051 }
5052 return false;
5053}
5054
5055// Unfold
5056// x & (-1 'logical shift' y)
5057// To
5058// (x 'opposite logical shift' y) 'logical shift' y
5059// if it is better for performance.
5060SDValue DAGCombiner::unfoldExtremeBitClearingToShifts(SDNode *N) {
5061 assert(N->getOpcode() == ISD::AND)((N->getOpcode() == ISD::AND) ? static_cast<void> (0
) : __assert_fail ("N->getOpcode() == ISD::AND", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5061, __PRETTY_FUNCTION__))
;
5062
5063 SDValue N0 = N->getOperand(0);
5064 SDValue N1 = N->getOperand(1);
5065
5066 // Do we actually prefer shifts over mask?
5067 if (!TLI.shouldFoldMaskToVariableShiftPair(N0))
5068 return SDValue();
5069
5070 // Try to match (-1 '[outer] logical shift' y)
5071 unsigned OuterShift;
5072 unsigned InnerShift; // The opposite direction to the OuterShift.
5073 SDValue Y; // Shift amount.
5074 auto matchMask = [&OuterShift, &InnerShift, &Y](SDValue M) -> bool {
5075 if (!M.hasOneUse())
5076 return false;
5077 OuterShift = M->getOpcode();
5078 if (OuterShift == ISD::SHL)
5079 InnerShift = ISD::SRL;
5080 else if (OuterShift == ISD::SRL)
5081 InnerShift = ISD::SHL;
5082 else
5083 return false;
5084 if (!isAllOnesConstant(M->getOperand(0)))
5085 return false;
5086 Y = M->getOperand(1);
5087 return true;
5088 };
5089
5090 SDValue X;
5091 if (matchMask(N1))
5092 X = N0;
5093 else if (matchMask(N0))
5094 X = N1;
5095 else
5096 return SDValue();
5097
5098 SDLoc DL(N);
5099 EVT VT = N->getValueType(0);
5100
5101 // tmp = x 'opposite logical shift' y
5102 SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y);
5103 // ret = tmp 'logical shift' y
5104 SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y);
5105
5106 return T1;
5107}
5108
5109/// Try to replace shift/logic that tests if a bit is clear with mask + setcc.
5110/// For a target with a bit test, this is expected to become test + set and save
5111/// at least 1 instruction.
5112static SDValue combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) {
5113 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op")((And->getOpcode() == ISD::AND && "Expected an 'and' op"
) ? static_cast<void> (0) : __assert_fail ("And->getOpcode() == ISD::AND && \"Expected an 'and' op\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5113, __PRETTY_FUNCTION__))
;
5114
5115 // This is probably not worthwhile without a supported type.
5116 EVT VT = And->getValueType(0);
5117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5118 if (!TLI.isTypeLegal(VT))
5119 return SDValue();
5120
5121 // Look through an optional extension and find a 'not'.
5122 // TODO: Should we favor test+set even without the 'not' op?
5123 SDValue Not = And->getOperand(0), And1 = And->getOperand(1);
5124 if (Not.getOpcode() == ISD::ANY_EXTEND)
5125 Not = Not.getOperand(0);
5126 if (!isBitwiseNot(Not) || !Not.hasOneUse() || !isOneConstant(And1))
5127 return SDValue();
5128
5129 // Look though an optional truncation. The source operand may not be the same
5130 // type as the original 'and', but that is ok because we are masking off
5131 // everything but the low bit.
5132 SDValue Srl = Not.getOperand(0);
5133 if (Srl.getOpcode() == ISD::TRUNCATE)
5134 Srl = Srl.getOperand(0);
5135
5136 // Match a shift-right by constant.
5137 if (Srl.getOpcode() != ISD::SRL || !Srl.hasOneUse() ||
5138 !isa<ConstantSDNode>(Srl.getOperand(1)))
5139 return SDValue();
5140
5141 // We might have looked through casts that make this transform invalid.
5142 // TODO: If the source type is wider than the result type, do the mask and
5143 // compare in the source type.
5144 const APInt &ShiftAmt = Srl.getConstantOperandAPInt(1);
5145 unsigned VTBitWidth = VT.getSizeInBits();
5146 if (ShiftAmt.uge(VTBitWidth))
5147 return SDValue();
5148
5149 // Turn this into a bit-test pattern using mask op + setcc:
5150 // and (not (srl X, C)), 1 --> (and X, 1<<C) == 0
5151 SDLoc DL(And);
5152 SDValue X = DAG.getZExtOrTrunc(Srl.getOperand(0), DL, VT);
5153 EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
5154 SDValue Mask = DAG.getConstant(
5155 APInt::getOneBitSet(VTBitWidth, ShiftAmt.getZExtValue()), DL, VT);
5156 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, Mask);
5157 SDValue Zero = DAG.getConstant(0, DL, VT);
5158 SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ);
5159 return DAG.getZExtOrTrunc(Setcc, DL, VT);
5160}
5161
5162SDValue DAGCombiner::visitAND(SDNode *N) {
5163 SDValue N0 = N->getOperand(0);
5164 SDValue N1 = N->getOperand(1);
5165 EVT VT = N1.getValueType();
5166
5167 // x & x --> x
5168 if (N0 == N1)
5169 return N0;
5170
5171 // fold vector ops
5172 if (VT.isVector()) {
5173 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5174 return FoldedVOp;
5175
5176 // fold (and x, 0) -> 0, vector edition
5177 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5178 // do not return N0, because undef node may exist in N0
5179 return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()),
5180 SDLoc(N), N0.getValueType());
5181 if (ISD::isBuildVectorAllZeros(N1.getNode()))
5182 // do not return N1, because undef node may exist in N1
5183 return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()),
5184 SDLoc(N), N1.getValueType());
5185
5186 // fold (and x, -1) -> x, vector edition
5187 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5188 return N1;
5189 if (ISD::isBuildVectorAllOnes(N1.getNode()))
5190 return N0;
5191 }
5192
5193 // fold (and c1, c2) -> c1&c2
5194 ConstantSDNode *N1C = isConstOrConstSplat(N1);
5195 if (SDValue C = DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, {N0, N1}))
5196 return C;
5197
5198 // canonicalize constant to RHS
5199 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5200 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
5201 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
5202
5203 // fold (and x, -1) -> x
5204 if (isAllOnesConstant(N1))
5205 return N0;
5206
5207 // if (and x, c) is known to be zero, return 0
5208 unsigned BitWidth = VT.getScalarSizeInBits();
5209 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
5210 APInt::getAllOnesValue(BitWidth)))
5211 return DAG.getConstant(0, SDLoc(N), VT);
5212
5213 if (SDValue NewSel = foldBinOpIntoSelect(N))
5214 return NewSel;
5215
5216 // reassociate and
5217 if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
5218 return RAND;
5219
5220 // Try to convert a constant mask AND into a shuffle clear mask.
5221 if (VT.isVector())
5222 if (SDValue Shuffle = XformToShuffleWithZero(N))
5223 return Shuffle;
5224
5225 if (SDValue Combined = combineCarryDiamond(*this, DAG, TLI, N0, N1, N))
5226 return Combined;
5227
5228 // fold (and (or x, C), D) -> D if (C & D) == D
5229 auto MatchSubset = [](ConstantSDNode *LHS, ConstantSDNode *RHS) {
5230 return RHS->getAPIntValue().isSubsetOf(LHS->getAPIntValue());
5231 };
5232 if (N0.getOpcode() == ISD::OR &&
5233 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset))
5234 return N1;
5235 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
5236 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
5237 SDValue N0Op0 = N0.getOperand(0);
5238 APInt Mask = ~N1C->getAPIntValue();
5239 Mask = Mask.trunc(N0Op0.getScalarValueSizeInBits());
5240 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
5241 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
5242 N0.getValueType(), N0Op0);
5243
5244 // Replace uses of the AND with uses of the Zero extend node.
5245 CombineTo(N, Zext);
5246
5247 // We actually want to replace all uses of the any_extend with the
5248 // zero_extend, to avoid duplicating things. This will later cause this
5249 // AND to be folded.
5250 CombineTo(N0.getNode(), Zext);
5251 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5252 }
5253 }
5254
5255 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
5256 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
5257 // already be zero by virtue of the width of the base type of the load.
5258 //
5259 // the 'X' node here can either be nothing or an extract_vector_elt to catch
5260 // more cases.
5261 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5262 N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
5263 N0.getOperand(0).getOpcode() == ISD::LOAD &&
5264 N0.getOperand(0).getResNo() == 0) ||
5265 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
5266 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
5267 N0 : N0.getOperand(0) );
5268
5269 // Get the constant (if applicable) the zero'th operand is being ANDed with.
5270 // This can be a pure constant or a vector splat, in which case we treat the
5271 // vector as a scalar and use the splat value.
5272 APInt Constant = APInt::getNullValue(1);
5273 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
5274 Constant = C->getAPIntValue();
5275 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
5276 APInt SplatValue, SplatUndef;
5277 unsigned SplatBitSize;
5278 bool HasAnyUndefs;
5279 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
5280 SplatBitSize, HasAnyUndefs);
5281 if (IsSplat) {
5282 // Undef bits can contribute to a possible optimisation if set, so
5283 // set them.
5284 SplatValue |= SplatUndef;
5285
5286 // The splat value may be something like "0x00FFFFFF", which means 0 for
5287 // the first vector value and FF for the rest, repeating. We need a mask
5288 // that will apply equally to all members of the vector, so AND all the
5289 // lanes of the constant together.
5290 unsigned EltBitWidth = Vector->getValueType(0).getScalarSizeInBits();
5291
5292 // If the splat value has been compressed to a bitlength lower
5293 // than the size of the vector lane, we need to re-expand it to
5294 // the lane size.
5295 if (EltBitWidth > SplatBitSize)
5296 for (SplatValue = SplatValue.zextOrTrunc(EltBitWidth);
5297 SplatBitSize < EltBitWidth; SplatBitSize = SplatBitSize * 2)
5298 SplatValue |= SplatValue.shl(SplatBitSize);
5299
5300 // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
5301 // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
5302 if ((SplatBitSize % EltBitWidth) == 0) {
5303 Constant = APInt::getAllOnesValue(EltBitWidth);
5304 for (unsigned i = 0, n = (SplatBitSize / EltBitWidth); i < n; ++i)
5305 Constant &= SplatValue.extractBits(EltBitWidth, i * EltBitWidth);
5306 }
5307 }
5308 }
5309
5310 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
5311 // actually legal and isn't going to get expanded, else this is a false
5312 // optimisation.
5313 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
5314 Load->getValueType(0),
5315 Load->getMemoryVT());
5316
5317 // Resize the constant to the same size as the original memory access before
5318 // extension. If it is still the AllOnesValue then this AND is completely
5319 // unneeded.
5320 Constant = Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits());
5321
5322 bool B;
5323 switch (Load->getExtensionType()) {
5324 default: B = false; break;
5325 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
5326 case ISD::ZEXTLOAD:
5327 case ISD::NON_EXTLOAD: B = true; break;
5328 }
5329
5330 if (B && Constant.isAllOnesValue()) {
5331 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
5332 // preserve semantics once we get rid of the AND.
5333 SDValue NewLoad(Load, 0);
5334
5335 // Fold the AND away. NewLoad may get replaced immediately.
5336 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
5337
5338 if (Load->getExtensionType() == ISD::EXTLOAD) {
5339 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
5340 Load->getValueType(0), SDLoc(Load),
5341 Load->getChain(), Load->getBasePtr(),
5342 Load->getOffset(), Load->getMemoryVT(),
5343 Load->getMemOperand());
5344 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
5345 if (Load->getNumValues() == 3) {
5346 // PRE/POST_INC loads have 3 values.
5347 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
5348 NewLoad.getValue(2) };
5349 CombineTo(Load, To, 3, true);
5350 } else {
5351 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
5352 }
5353 }
5354
5355 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5356 }
5357 }
5358
5359 // fold (and (load x), 255) -> (zextload x, i8)
5360 // fold (and (extload x, i16), 255) -> (zextload x, i8)
5361 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
5362 if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
5363 (N0.getOpcode() == ISD::ANY_EXTEND &&
5364 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
5365 if (SDValue Res = ReduceLoadWidth(N)) {
5366 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
5367 ? cast<LoadSDNode>(N0.getOperand(0)) : cast<LoadSDNode>(N0);
5368 AddToWorklist(N);
5369 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 0), Res);
5370 return SDValue(N, 0);
5371 }
5372 }
5373
5374 if (LegalTypes) {
5375 // Attempt to propagate the AND back up to the leaves which, if they're
5376 // loads, can be combined to narrow loads and the AND node can be removed.
5377 // Perform after legalization so that extend nodes will already be
5378 // combined into the loads.
5379 if (BackwardsPropagateMask(N))
5380 return SDValue(N, 0);
5381 }
5382
5383 if (SDValue Combined = visitANDLike(N0, N1, N))
5384 return Combined;
5385
5386 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
5387 if (N0.getOpcode() == N1.getOpcode())
5388 if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
5389 return V;
5390
5391 // Masking the negated extension of a boolean is just the zero-extended
5392 // boolean:
5393 // and (sub 0, zext(bool X)), 1 --> zext(bool X)
5394 // and (sub 0, sext(bool X)), 1 --> zext(bool X)
5395 //
5396 // Note: the SimplifyDemandedBits fold below can make an information-losing
5397 // transform, and then we have no way to find this better fold.
5398 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
5399 if (isNullOrNullSplat(N0.getOperand(0))) {
5400 SDValue SubRHS = N0.getOperand(1);
5401 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
5402 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
5403 return SubRHS;
5404 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND &&
5405 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
5406 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0));
5407 }
5408 }
5409
5410 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
5411 // fold (and (sra)) -> (and (srl)) when possible.
5412 if (SimplifyDemandedBits(SDValue(N, 0)))
5413 return SDValue(N, 0);
5414
5415 // fold (zext_inreg (extload x)) -> (zextload x)
5416 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
5417 if (ISD::isUNINDEXEDLoad(N0.getNode()) &&
5418 (ISD::isEXTLoad(N0.getNode()) ||
5419 (ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) {
5420 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5421 EVT MemVT = LN0->getMemoryVT();
5422 // If we zero all the possible extended bits, then we can turn this into
5423 // a zextload if we are running before legalize or the operation is legal.
5424 unsigned ExtBitSize = N1.getScalarValueSizeInBits();
5425 unsigned MemBitSize = MemVT.getScalarSizeInBits();
5426 APInt ExtBits = APInt::getHighBitsSet(ExtBitSize, ExtBitSize - MemBitSize);
5427 if (DAG.MaskedValueIsZero(N1, ExtBits) &&
5428 ((!LegalOperations && LN0->isSimple()) ||
5429 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
5430 SDValue ExtLoad =
5431 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(),
5432 LN0->getBasePtr(), MemVT, LN0->getMemOperand());
5433 AddToWorklist(N);
5434 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5435 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5436 }
5437 }
5438
5439 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
5440 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
5441 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5442 N0.getOperand(1), false))
5443 return BSwap;
5444 }
5445
5446 if (SDValue Shifts = unfoldExtremeBitClearingToShifts(N))
5447 return Shifts;
5448
5449 if (TLI.hasBitTest(N0, N1))
5450 if (SDValue V = combineShiftAnd1ToBitTest(N, DAG))
5451 return V;
5452
5453 return SDValue();
5454}
5455
5456/// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
5457SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
5458 bool DemandHighBits) {
5459 if (!LegalOperations)
5460 return SDValue();
5461
5462 EVT VT = N->getValueType(0);
5463 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
5464 return SDValue();
5465 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5466 return SDValue();
5467
5468 // Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff)
5469 bool LookPassAnd0 = false;
5470 bool LookPassAnd1 = false;
5471 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
5472 std::swap(N0, N1);
5473 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
5474 std::swap(N0, N1);
5475 if (N0.getOpcode() == ISD::AND) {
5476 if (!N0.getNode()->hasOneUse())
5477 return SDValue();
5478 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5479 // Also handle 0xffff since the LHS is guaranteed to have zeros there.
5480 // This is needed for X86.
5481 if (!N01C || (N01C->getZExtValue() != 0xFF00 &&
5482 N01C->getZExtValue() != 0xFFFF))
5483 return SDValue();
5484 N0 = N0.getOperand(0);
5485 LookPassAnd0 = true;
5486 }
5487
5488 if (N1.getOpcode() == ISD::AND) {
5489 if (!N1.getNode()->hasOneUse())
5490 return SDValue();
5491 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5492 if (!N11C || N11C->getZExtValue() != 0xFF)
5493 return SDValue();
5494 N1 = N1.getOperand(0);
5495 LookPassAnd1 = true;
5496 }
5497
5498 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
5499 std::swap(N0, N1);
5500 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
5501 return SDValue();
5502 if (!N0.getNode()->hasOneUse() || !N1.getNode()->hasOneUse())
5503 return SDValue();
5504
5505 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5506 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5507 if (!N01C || !N11C)
5508 return SDValue();
5509 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
5510 return SDValue();
5511
5512 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
5513 SDValue N00 = N0->getOperand(0);
5514 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
5515 if (!N00.getNode()->hasOneUse())
5516 return SDValue();
5517 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
5518 if (!N001C || N001C->getZExtValue() != 0xFF)
5519 return SDValue();
5520 N00 = N00.getOperand(0);
5521 LookPassAnd0 = true;
5522 }
5523
5524 SDValue N10 = N1->getOperand(0);
5525 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
5526 if (!N10.getNode()->hasOneUse())
5527 return SDValue();
5528 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
5529 // Also allow 0xFFFF since the bits will be shifted out. This is needed
5530 // for X86.
5531 if (!N101C || (N101C->getZExtValue() != 0xFF00 &&
5532 N101C->getZExtValue() != 0xFFFF))
5533 return SDValue();
5534 N10 = N10.getOperand(0);
5535 LookPassAnd1 = true;
5536 }
5537
5538 if (N00 != N10)
5539 return SDValue();
5540
5541 // Make sure everything beyond the low halfword gets set to zero since the SRL
5542 // 16 will clear the top bits.
5543 unsigned OpSizeInBits = VT.getSizeInBits();
5544 if (DemandHighBits && OpSizeInBits > 16) {
5545 // If the left-shift isn't masked out then the only way this is a bswap is
5546 // if all bits beyond the low 8 are 0. In that case the entire pattern
5547 // reduces to a left shift anyway: leave it for other parts of the combiner.
5548 if (!LookPassAnd0)
5549 return SDValue();
5550
5551 // However, if the right shift isn't masked out then it might be because
5552 // it's not needed. See if we can spot that too.
5553 if (!LookPassAnd1 &&
5554 !DAG.MaskedValueIsZero(
5555 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
5556 return SDValue();
5557 }
5558
5559 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
5560 if (OpSizeInBits > 16) {
5561 SDLoc DL(N);
5562 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
5563 DAG.getConstant(OpSizeInBits - 16, DL,
5564 getShiftAmountTy(VT)));
5565 }
5566 return Res;
5567}
5568
5569/// Return true if the specified node is an element that makes up a 32-bit
5570/// packed halfword byteswap.
5571/// ((x & 0x000000ff) << 8) |
5572/// ((x & 0x0000ff00) >> 8) |
5573/// ((x & 0x00ff0000) << 8) |
5574/// ((x & 0xff000000) >> 8)
5575static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
5576 if (!N.getNode()->hasOneUse())
5577 return false;
5578
5579 unsigned Opc = N.getOpcode();
5580 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
5581 return false;
5582
5583 SDValue N0 = N.getOperand(0);
5584 unsigned Opc0 = N0.getOpcode();
5585 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
5586 return false;
5587
5588 ConstantSDNode *N1C = nullptr;
5589 // SHL or SRL: look upstream for AND mask operand
5590 if (Opc == ISD::AND)
5591 N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5592 else if (Opc0 == ISD::AND)
5593 N1C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5594 if (!N1C)
5595 return false;
5596
5597 unsigned MaskByteOffset;
5598 switch (N1C->getZExtValue()) {
5599 default:
5600 return false;
5601 case 0xFF: MaskByteOffset = 0; break;
5602 case 0xFF00: MaskByteOffset = 1; break;
5603 case 0xFFFF:
5604 // In case demanded bits didn't clear the bits that will be shifted out.
5605 // This is needed for X86.
5606 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) {
5607 MaskByteOffset = 1;
5608 break;
5609 }
5610 return false;
5611 case 0xFF0000: MaskByteOffset = 2; break;
5612 case 0xFF000000: MaskByteOffset = 3; break;
5613 }
5614
5615 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
5616 if (Opc == ISD::AND) {
5617 if (MaskByteOffset == 0 || MaskByteOffset == 2) {
5618 // (x >> 8) & 0xff
5619 // (x >> 8) & 0xff0000
5620 if (Opc0 != ISD::SRL)
5621 return false;
5622 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5623 if (!C || C->getZExtValue() != 8)
5624 return false;
5625 } else {
5626 // (x << 8) & 0xff00
5627 // (x << 8) & 0xff000000
5628 if (Opc0 != ISD::SHL)
5629 return false;
5630 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5631 if (!C || C->getZExtValue() != 8)
5632 return false;
5633 }
5634 } else if (Opc == ISD::SHL) {
5635 // (x & 0xff) << 8
5636 // (x & 0xff0000) << 8
5637 if (MaskByteOffset != 0 && MaskByteOffset != 2)
5638 return false;
5639 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5640 if (!C || C->getZExtValue() != 8)
5641 return false;
5642 } else { // Opc == ISD::SRL
5643 // (x & 0xff00) >> 8
5644 // (x & 0xff000000) >> 8
5645 if (MaskByteOffset != 1 && MaskByteOffset != 3)
5646 return false;
5647 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5648 if (!C || C->getZExtValue() != 8)
5649 return false;
5650 }
5651
5652 if (Parts[MaskByteOffset])
5653 return false;
5654
5655 Parts[MaskByteOffset] = N0.getOperand(0).getNode();
5656 return true;
5657}
5658
5659// Match 2 elements of a packed halfword bswap.
5660static bool isBSwapHWordPair(SDValue N, MutableArrayRef<SDNode *> Parts) {
5661 if (N.getOpcode() == ISD::OR)
5662 return isBSwapHWordElement(N.getOperand(0), Parts) &&
5663 isBSwapHWordElement(N.getOperand(1), Parts);
5664
5665 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
5666 ConstantSDNode *C = isConstOrConstSplat(N.getOperand(1));
5667 if (!C || C->getAPIntValue() != 16)
5668 return false;
5669 Parts[0] = Parts[1] = N.getOperand(0).getOperand(0).getNode();
5670 return true;
5671 }
5672
5673 return false;
5674}
5675
5676// Match this pattern:
5677// (or (and (shl (A, 8)), 0xff00ff00), (and (srl (A, 8)), 0x00ff00ff))
5678// And rewrite this to:
5679// (rotr (bswap A), 16)
5680static SDValue matchBSwapHWordOrAndAnd(const TargetLowering &TLI,
5681 SelectionDAG &DAG, SDNode *N, SDValue N0,
5682 SDValue N1, EVT VT, EVT ShiftAmountTy) {
5683 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 &&((N->getOpcode() == ISD::OR && VT == MVT::i32 &&
"MatchBSwapHWordOrAndAnd: expecting i32") ? static_cast<void
> (0) : __assert_fail ("N->getOpcode() == ISD::OR && VT == MVT::i32 && \"MatchBSwapHWordOrAndAnd: expecting i32\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5684, __PRETTY_FUNCTION__))
5684 "MatchBSwapHWordOrAndAnd: expecting i32")((N->getOpcode() == ISD::OR && VT == MVT::i32 &&
"MatchBSwapHWordOrAndAnd: expecting i32") ? static_cast<void
> (0) : __assert_fail ("N->getOpcode() == ISD::OR && VT == MVT::i32 && \"MatchBSwapHWordOrAndAnd: expecting i32\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5684, __PRETTY_FUNCTION__))
;
5685 if (!TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
5686 return SDValue();
5687 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
5688 return SDValue();
5689 // TODO: this is too restrictive; lifting this restriction requires more tests
5690 if (!N0->hasOneUse() || !N1->hasOneUse())
5691 return SDValue();
5692 ConstantSDNode *Mask0 = isConstOrConstSplat(N0.getOperand(1));
5693 ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1));
5694 if (!Mask0 || !Mask1)
5695 return SDValue();
5696 if (Mask0->getAPIntValue() != 0xff00ff00 ||
5697 Mask1->getAPIntValue() != 0x00ff00ff)
5698 return SDValue();
5699 SDValue Shift0 = N0.getOperand(0);
5700 SDValue Shift1 = N1.getOperand(0);
5701 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL)
5702 return SDValue();
5703 ConstantSDNode *ShiftAmt0 = isConstOrConstSplat(Shift0.getOperand(1));
5704 ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1));
5705 if (!ShiftAmt0 || !ShiftAmt1)
5706 return SDValue();
5707 if (ShiftAmt0->getAPIntValue() != 8 || ShiftAmt1->getAPIntValue() != 8)
5708 return SDValue();
5709 if (Shift0.getOperand(0) != Shift1.getOperand(0))
5710 return SDValue();
5711
5712 SDLoc DL(N);
5713 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Shift0.getOperand(0));
5714 SDValue ShAmt = DAG.getConstant(16, DL, ShiftAmountTy);
5715 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
5716}
5717
5718/// Match a 32-bit packed halfword bswap. That is
5719/// ((x & 0x000000ff) << 8) |
5720/// ((x & 0x0000ff00) >> 8) |
5721/// ((x & 0x00ff0000) << 8) |
5722/// ((x & 0xff000000) >> 8)
5723/// => (rotl (bswap x), 16)
5724SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
5725 if (!LegalOperations)
5726 return SDValue();
5727
5728 EVT VT = N->getValueType(0);
5729 if (VT != MVT::i32)
5730 return SDValue();
5731 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5732 return SDValue();
5733
5734 if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N0, N1, VT,
5735 getShiftAmountTy(VT)))
5736 return BSwap;
5737
5738 // Try again with commuted operands.
5739 if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N1, N0, VT,
5740 getShiftAmountTy(VT)))
5741 return BSwap;
5742
5743
5744 // Look for either
5745 // (or (bswaphpair), (bswaphpair))
5746 // (or (or (bswaphpair), (and)), (and))
5747 // (or (or (and), (bswaphpair)), (and))
5748 SDNode *Parts[4] = {};
5749
5750 if (isBSwapHWordPair(N0, Parts)) {
5751 // (or (or (and), (and)), (or (and), (and)))
5752 if (!isBSwapHWordPair(N1, Parts))
5753 return SDValue();
5754 } else if (N0.getOpcode() == ISD::OR) {
5755 // (or (or (or (and), (and)), (and)), (and))
5756 if (!isBSwapHWordElement(N1, Parts))
5757 return SDValue();
5758 SDValue N00 = N0.getOperand(0);
5759 SDValue N01 = N0.getOperand(1);
5760 if (!(isBSwapHWordElement(N01, Parts) && isBSwapHWordPair(N00, Parts)) &&
5761 !(isBSwapHWordElement(N00, Parts) && isBSwapHWordPair(N01, Parts)))
5762 return SDValue();
5763 } else
5764 return SDValue();
5765
5766 // Make sure the parts are all coming from the same node.
5767 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
5768 return SDValue();
5769
5770 SDLoc DL(N);
5771 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
5772 SDValue(Parts[0], 0));
5773
5774 // Result of the bswap should be rotated by 16. If it's not legal, then
5775 // do (x << 16) | (x >> 16).
5776 SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT));
5777 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
5778 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
5779 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
5780 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
5781 return DAG.getNode(ISD::OR, DL, VT,
5782 DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt),
5783 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
5784}
5785
5786/// This contains all DAGCombine rules which reduce two values combined by
5787/// an Or operation to a single value \see visitANDLike().
5788SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *N) {
5789 EVT VT = N1.getValueType();
5790 SDLoc DL(N);
5791
5792 // fold (or x, undef) -> -1
5793 if (!LegalOperations && (N0.isUndef() || N1.isUndef()))
5794 return DAG.getAllOnesConstant(DL, VT);
5795
5796 if (SDValue V = foldLogicOfSetCCs(false, N0, N1, DL))
5797 return V;
5798
5799 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
5800 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
5801 // Don't increase # computations.
5802 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
5803 // We can only do this xform if we know that bits from X that are set in C2
5804 // but not in C1 are already zero. Likewise for Y.
5805 if (const ConstantSDNode *N0O1C =
5806 getAsNonOpaqueConstant(N0.getOperand(1))) {
5807 if (const ConstantSDNode *N1O1C =
5808 getAsNonOpaqueConstant(N1.getOperand(1))) {
5809 // We can only do this xform if we know that bits from X that are set in
5810 // C2 but not in C1 are already zero. Likewise for Y.
5811 const APInt &LHSMask = N0O1C->getAPIntValue();
5812 const APInt &RHSMask = N1O1C->getAPIntValue();
5813
5814 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
5815 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
5816 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
5817 N0.getOperand(0), N1.getOperand(0));
5818 return DAG.getNode(ISD::AND, DL, VT, X,
5819 DAG.getConstant(LHSMask | RHSMask, DL, VT));
5820 }
5821 }
5822 }
5823 }
5824
5825 // (or (and X, M), (and X, N)) -> (and X, (or M, N))
5826 if (N0.getOpcode() == ISD::AND &&
5827 N1.getOpcode() == ISD::AND &&
5828 N0.getOperand(0) == N1.getOperand(0) &&
5829 // Don't increase # computations.
5830 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
5831 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
5832 N0.getOperand(1), N1.getOperand(1));
5833 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X);
5834 }
5835
5836 return SDValue();
5837}
5838
5839/// OR combines for which the commuted variant will be tried as well.
5840static SDValue visitORCommutative(
5841 SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N) {
5842 EVT VT = N0.getValueType();
5843 if (N0.getOpcode() == ISD::AND) {
5844 // fold (or (and X, (xor Y, -1)), Y) -> (or X, Y)
5845 if (isBitwiseNot(N0.getOperand(1)) && N0.getOperand(1).getOperand(0) == N1)
5846 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(0), N1);
5847
5848 // fold (or (and (xor Y, -1), X), Y) -> (or X, Y)
5849 if (isBitwiseNot(N0.getOperand(0)) && N0.getOperand(0).getOperand(0) == N1)
5850 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(1), N1);
5851 }
5852
5853 return SDValue();
5854}
5855
5856SDValue DAGCombiner::visitOR(SDNode *N) {
5857 SDValue N0 = N->getOperand(0);
5858 SDValue N1 = N->getOperand(1);
5859 EVT VT = N1.getValueType();
5860
5861 // x | x --> x
5862 if (N0 == N1)
5863 return N0;
5864
5865 // fold vector ops
5866 if (VT.isVector()) {
5867 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5868 return FoldedVOp;
5869
5870 // fold (or x, 0) -> x, vector edition
5871 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5872 return N1;
5873 if (ISD::isBuildVectorAllZeros(N1.getNode()))
5874 return N0;
5875
5876 // fold (or x, -1) -> -1, vector edition
5877 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5878 // do not return N0, because undef node may exist in N0
5879 return DAG.getAllOnesConstant(SDLoc(N), N0.getValueType());
5880 if (ISD::isBuildVectorAllOnes(N1.getNode()))
5881 // do not return N1, because undef node may exist in N1
5882 return DAG.getAllOnesConstant(SDLoc(N), N1.getValueType());
5883
5884 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask)
5885 // Do this only if the resulting shuffle is legal.
5886 if (isa<ShuffleVectorSDNode>(N0) &&
5887 isa<ShuffleVectorSDNode>(N1) &&
5888 // Avoid folding a node with illegal type.
5889 TLI.isTypeLegal(VT)) {
5890 bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode());
5891 bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode());
5892 bool ZeroN10 = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
5893 bool ZeroN11 = ISD::isBuildVectorAllZeros(N1.getOperand(1).getNode());
5894 // Ensure both shuffles have a zero input.
5895 if ((ZeroN00 != ZeroN01) && (ZeroN10 != ZeroN11)) {
5896 assert((!ZeroN00 || !ZeroN01) && "Both inputs zero!")(((!ZeroN00 || !ZeroN01) && "Both inputs zero!") ? static_cast
<void> (0) : __assert_fail ("(!ZeroN00 || !ZeroN01) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5896, __PRETTY_FUNCTION__))
;
5897 assert((!ZeroN10 || !ZeroN11) && "Both inputs zero!")(((!ZeroN10 || !ZeroN11) && "Both inputs zero!") ? static_cast
<void> (0) : __assert_fail ("(!ZeroN10 || !ZeroN11) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5897, __PRETTY_FUNCTION__))
;
5898 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
5899 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
5900 bool CanFold = true;
5901 int NumElts = VT.getVectorNumElements();
5902 SmallVector<int, 4> Mask(NumElts);
5903
5904 for (int i = 0; i != NumElts; ++i) {
5905 int M0 = SV0->getMaskElt(i);
5906 int M1 = SV1->getMaskElt(i);
5907
5908 // Determine if either index is pointing to a zero vector.
5909 bool M0Zero = M0 < 0 || (ZeroN00 == (M0 < NumElts));
5910 bool M1Zero = M1 < 0 || (ZeroN10 == (M1 < NumElts));
5911
5912 // If one element is zero and the otherside is undef, keep undef.
5913 // This also handles the case that both are undef.
5914 if ((M0Zero && M1 < 0) || (M1Zero && M0 < 0)) {
5915 Mask[i] = -1;
5916 continue;
5917 }
5918
5919 // Make sure only one of the elements is zero.
5920 if (M0Zero == M1Zero) {
5921 CanFold = false;
5922 break;
5923 }
5924
5925 assert((M0 >= 0 || M1 >= 0) && "Undef index!")(((M0 >= 0 || M1 >= 0) && "Undef index!") ? static_cast
<void> (0) : __assert_fail ("(M0 >= 0 || M1 >= 0) && \"Undef index!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5925, __PRETTY_FUNCTION__))
;
5926
5927 // We have a zero and non-zero element. If the non-zero came from
5928 // SV0 make the index a LHS index. If it came from SV1, make it
5929 // a RHS index. We need to mod by NumElts because we don't care
5930 // which operand it came from in the original shuffles.
5931 Mask[i] = M1Zero ? M0 % NumElts : (M1 % NumElts) + NumElts;
5932 }
5933
5934 if (CanFold) {
5935 SDValue NewLHS = ZeroN00 ? N0.getOperand(1) : N0.getOperand(0);
5936 SDValue NewRHS = ZeroN10 ? N1.getOperand(1) : N1.getOperand(0);
5937
5938 SDValue LegalShuffle =
5939 TLI.buildLegalVectorShuffle(VT, SDLoc(N), NewLHS, NewRHS,
5940 Mask, DAG);
5941 if (LegalShuffle)
5942 return LegalShuffle;
5943 }
5944 }
5945 }
5946 }
5947
5948 // fold (or c1, c2) -> c1|c2
5949 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5950 if (SDValue C = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, {N0, N1}))
5951 return C;
5952
5953 // canonicalize constant to RHS
5954 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5955 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
5956 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
5957
5958 // fold (or x, 0) -> x
5959 if (isNullConstant(N1))
5960 return N0;
5961
5962 // fold (or x, -1) -> -1
5963 if (isAllOnesConstant(N1))
5964 return N1;
5965
5966 if (SDValue NewSel = foldBinOpIntoSelect(N))
5967 return NewSel;
5968
5969 // fold (or x, c) -> c iff (x & ~c) == 0
5970 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
5971 return N1;
5972
5973 if (SDValue Combined = visitORLike(N0, N1, N))
5974 return Combined;
5975
5976 if (SDValue Combined = combineCarryDiamond(*this, DAG, TLI, N0, N1, N))
5977 return Combined;
5978
5979 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
5980 if (SDValue BSwap = MatchBSwapHWord(N, N0, N1))
5981 return BSwap;
5982 if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1))
5983 return BSwap;
5984
5985 // reassociate or
5986 if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags()))
5987 return ROR;
5988
5989 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
5990 // iff (c1 & c2) != 0 or c1/c2 are undef.
5991 auto MatchIntersect = [](ConstantSDNode *C1, ConstantSDNode *C2) {
5992 return !C1 || !C2 || C1->getAPIntValue().intersects(C2->getAPIntValue());
5993 };
5994 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
5995 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchIntersect, true)) {
5996 if (SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N1), VT,
5997 {N1, N0.getOperand(1)})) {
5998 SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1);
5999 AddToWorklist(IOR.getNode());
6000 return DAG.getNode(ISD::AND, SDLoc(N), VT, COR, IOR);
6001 }
6002 }
6003
6004 if (SDValue Combined = visitORCommutative(DAG, N0, N1, N))
6005 return Combined;
6006 if (SDValue Combined = visitORCommutative(DAG, N1, N0, N))
6007 return Combined;
6008
6009 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
6010 if (N0.getOpcode() == N1.getOpcode())
6011 if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
6012 return V;
6013
6014 // See if this is some rotate idiom.
6015 if (SDValue Rot = MatchRotate(N0, N1, SDLoc(N)))
6016 return Rot;
6017
6018 if (SDValue Load = MatchLoadCombine(N))
6019 return Load;
6020
6021 // Simplify the operands using demanded-bits information.
6022 if (SimplifyDemandedBits(SDValue(N, 0)))
6023 return SDValue(N, 0);
6024
6025 // If OR can be rewritten into ADD, try combines based on ADD.
6026 if ((!LegalOperations || TLI.isOperationLegal(ISD::ADD, VT)) &&
6027 DAG.haveNo