Bug Summary

File:include/llvm/ADT/APInt.h
Warning:line 983, column 15
Assigned value is garbage or undefined

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name DAGCombiner.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-9/lib/clang/9.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/include -I /build/llvm-toolchain-snapshot-9~svn362543/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/9.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-9/lib/clang/9.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-9~svn362543=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2019-06-05-060531-1271-1 -x c++ /build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp -faddrsig

/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

1//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
10// both before and after the DAG is legalized.
11//
12// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
13// primarily intended to handle simplification opportunities that are implicit
14// in the LLVM IR and exposed by the various codegen lowering phases.
15//
16//===----------------------------------------------------------------------===//
17
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/ArrayRef.h"
21#include "llvm/ADT/DenseMap.h"
22#include "llvm/ADT/IntervalMap.h"
23#include "llvm/ADT/None.h"
24#include "llvm/ADT/Optional.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SetVector.h"
27#include "llvm/ADT/SmallBitVector.h"
28#include "llvm/ADT/SmallPtrSet.h"
29#include "llvm/ADT/SmallSet.h"
30#include "llvm/ADT/SmallVector.h"
31#include "llvm/ADT/Statistic.h"
32#include "llvm/Analysis/AliasAnalysis.h"
33#include "llvm/Analysis/MemoryLocation.h"
34#include "llvm/CodeGen/DAGCombine.h"
35#include "llvm/CodeGen/ISDOpcodes.h"
36#include "llvm/CodeGen/MachineFrameInfo.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/RuntimeLibcalls.h"
40#include "llvm/CodeGen/SelectionDAG.h"
41#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
42#include "llvm/CodeGen/SelectionDAGNodes.h"
43#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
44#include "llvm/CodeGen/TargetLowering.h"
45#include "llvm/CodeGen/TargetRegisterInfo.h"
46#include "llvm/CodeGen/TargetSubtargetInfo.h"
47#include "llvm/CodeGen/ValueTypes.h"
48#include "llvm/IR/Attributes.h"
49#include "llvm/IR/Constant.h"
50#include "llvm/IR/DataLayout.h"
51#include "llvm/IR/DerivedTypes.h"
52#include "llvm/IR/Function.h"
53#include "llvm/IR/LLVMContext.h"
54#include "llvm/IR/Metadata.h"
55#include "llvm/Support/Casting.h"
56#include "llvm/Support/CodeGen.h"
57#include "llvm/Support/CommandLine.h"
58#include "llvm/Support/Compiler.h"
59#include "llvm/Support/Debug.h"
60#include "llvm/Support/ErrorHandling.h"
61#include "llvm/Support/KnownBits.h"
62#include "llvm/Support/MachineValueType.h"
63#include "llvm/Support/MathExtras.h"
64#include "llvm/Support/raw_ostream.h"
65#include "llvm/Target/TargetMachine.h"
66#include "llvm/Target/TargetOptions.h"
67#include <algorithm>
68#include <cassert>
69#include <cstdint>
70#include <functional>
71#include <iterator>
72#include <string>
73#include <tuple>
74#include <utility>
75
76using namespace llvm;
77
78#define DEBUG_TYPE"dagcombine" "dagcombine"
79
80STATISTIC(NodesCombined , "Number of dag nodes combined")static llvm::Statistic NodesCombined = {"dagcombine", "NodesCombined"
, "Number of dag nodes combined", {0}, {false}}
;
81STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created")static llvm::Statistic PreIndexedNodes = {"dagcombine", "PreIndexedNodes"
, "Number of pre-indexed nodes created", {0}, {false}}
;
82STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created")static llvm::Statistic PostIndexedNodes = {"dagcombine", "PostIndexedNodes"
, "Number of post-indexed nodes created", {0}, {false}}
;
83STATISTIC(OpsNarrowed , "Number of load/op/store narrowed")static llvm::Statistic OpsNarrowed = {"dagcombine", "OpsNarrowed"
, "Number of load/op/store narrowed", {0}, {false}}
;
84STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int")static llvm::Statistic LdStFP2Int = {"dagcombine", "LdStFP2Int"
, "Number of fp load/store pairs transformed to int", {0}, {false
}}
;
85STATISTIC(SlicedLoads, "Number of load sliced")static llvm::Statistic SlicedLoads = {"dagcombine", "SlicedLoads"
, "Number of load sliced", {0}, {false}}
;
86STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops")static llvm::Statistic NumFPLogicOpsConv = {"dagcombine", "NumFPLogicOpsConv"
, "Number of logic ops converted to fp ops", {0}, {false}}
;
87
88static cl::opt<bool>
89CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
90 cl::desc("Enable DAG combiner's use of IR alias analysis"));
91
92static cl::opt<bool>
93UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
94 cl::desc("Enable DAG combiner's use of TBAA"));
95
96#ifndef NDEBUG
97static cl::opt<std::string>
98CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
99 cl::desc("Only use DAG-combiner alias analysis in this"
100 " function"));
101#endif
102
103/// Hidden option to stress test load slicing, i.e., when this option
104/// is enabled, load slicing bypasses most of its profitability guards.
105static cl::opt<bool>
106StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
107 cl::desc("Bypass the profitability model of load slicing"),
108 cl::init(false));
109
110static cl::opt<bool>
111 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
112 cl::desc("DAG combiner may split indexing from loads"));
113
114static cl::opt<unsigned> TokenFactorInlineLimit(
115 "combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048),
116 cl::desc("Limit the number of operands to inline for Token Factors"));
117
118namespace {
119
120 class DAGCombiner {
121 SelectionDAG &DAG;
122 const TargetLowering &TLI;
123 CombineLevel Level;
124 CodeGenOpt::Level OptLevel;
125 bool LegalOperations = false;
126 bool LegalTypes = false;
127 bool ForCodeSize;
128
129 /// Worklist of all of the nodes that need to be simplified.
130 ///
131 /// This must behave as a stack -- new nodes to process are pushed onto the
132 /// back and when processing we pop off of the back.
133 ///
134 /// The worklist will not contain duplicates but may contain null entries
135 /// due to nodes being deleted from the underlying DAG.
136 SmallVector<SDNode *, 64> Worklist;
137
138 /// Mapping from an SDNode to its position on the worklist.
139 ///
140 /// This is used to find and remove nodes from the worklist (by nulling
141 /// them) when they are deleted from the underlying DAG. It relies on
142 /// stable indices of nodes within the worklist.
143 DenseMap<SDNode *, unsigned> WorklistMap;
144 /// This records all nodes attempted to add to the worklist since we
145 /// considered a new worklist entry. As we keep do not add duplicate nodes
146 /// in the worklist, this is different from the tail of the worklist.
147 SmallSetVector<SDNode *, 32> PruningList;
148
149 /// Set of nodes which have been combined (at least once).
150 ///
151 /// This is used to allow us to reliably add any operands of a DAG node
152 /// which have not yet been combined to the worklist.
153 SmallPtrSet<SDNode *, 32> CombinedNodes;
154
155 // AA - Used for DAG load/store alias analysis.
156 AliasAnalysis *AA;
157
158 /// When an instruction is simplified, add all users of the instruction to
159 /// the work lists because they might get more simplified now.
160 void AddUsersToWorklist(SDNode *N) {
161 for (SDNode *Node : N->uses())
162 AddToWorklist(Node);
163 }
164
165 // Prune potentially dangling nodes. This is called after
166 // any visit to a node, but should also be called during a visit after any
167 // failed combine which may have created a DAG node.
168 void clearAddedDanglingWorklistEntries() {
169 // Check any nodes added to the worklist to see if they are prunable.
170 while (!PruningList.empty()) {
171 auto *N = PruningList.pop_back_val();
172 if (N->use_empty())
173 recursivelyDeleteUnusedNodes(N);
174 }
175 }
176
177 SDNode *getNextWorklistEntry() {
178 // Before we do any work, remove nodes that are not in use.
179 clearAddedDanglingWorklistEntries();
180 SDNode *N = nullptr;
181 // The Worklist holds the SDNodes in order, but it may contain null
182 // entries.
183 while (!N && !Worklist.empty()) {
184 N = Worklist.pop_back_val();
185 }
186
187 if (N) {
188 bool GoodWorklistEntry = WorklistMap.erase(N);
189 (void)GoodWorklistEntry;
190 assert(GoodWorklistEntry &&((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 191, __PRETTY_FUNCTION__))
191 "Found a worklist entry without a corresponding map entry!")((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 191, __PRETTY_FUNCTION__))
;
192 }
193 return N;
194 }
195
196 /// Call the node-specific routine that folds each particular type of node.
197 SDValue visit(SDNode *N);
198
199 public:
200 DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
201 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
202 OptLevel(OL), AA(AA) {
203 ForCodeSize = DAG.getMachineFunction().getFunction().hasOptSize();
204
205 MaximumLegalStoreInBits = 0;
206 for (MVT VT : MVT::all_valuetypes())
207 if (EVT(VT).isSimple() && VT != MVT::Other &&
208 TLI.isTypeLegal(EVT(VT)) &&
209 VT.getSizeInBits() >= MaximumLegalStoreInBits)
210 MaximumLegalStoreInBits = VT.getSizeInBits();
211 }
212
213 void ConsiderForPruning(SDNode *N) {
214 // Mark this for potential pruning.
215 PruningList.insert(N);
216 }
217
218 /// Add to the worklist making sure its instance is at the back (next to be
219 /// processed.)
220 void AddToWorklist(SDNode *N) {
221 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 222, __PRETTY_FUNCTION__))
222 "Deleted Node added to Worklist")((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 222, __PRETTY_FUNCTION__))
;
223
224 // Skip handle nodes as they can't usefully be combined and confuse the
225 // zero-use deletion strategy.
226 if (N->getOpcode() == ISD::HANDLENODE)
227 return;
228
229 ConsiderForPruning(N);
230
231 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
232 Worklist.push_back(N);
233 }
234
235 /// Remove all instances of N from the worklist.
236 void removeFromWorklist(SDNode *N) {
237 CombinedNodes.erase(N);
238 PruningList.remove(N);
239
240 auto It = WorklistMap.find(N);
241 if (It == WorklistMap.end())
242 return; // Not in the worklist.
243
244 // Null out the entry rather than erasing it to avoid a linear operation.
245 Worklist[It->second] = nullptr;
246 WorklistMap.erase(It);
247 }
248
249 void deleteAndRecombine(SDNode *N);
250 bool recursivelyDeleteUnusedNodes(SDNode *N);
251
252 /// Replaces all uses of the results of one DAG node with new values.
253 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
254 bool AddTo = true);
255
256 /// Replaces all uses of the results of one DAG node with new values.
257 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
258 return CombineTo(N, &Res, 1, AddTo);
259 }
260
261 /// Replaces all uses of the results of one DAG node with new values.
262 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
263 bool AddTo = true) {
264 SDValue To[] = { Res0, Res1 };
265 return CombineTo(N, To, 2, AddTo);
266 }
267
268 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
269
270 private:
271 unsigned MaximumLegalStoreInBits;
272
273 /// Check the specified integer node value to see if it can be simplified or
274 /// if things it uses can be simplified by bit propagation.
275 /// If so, return true.
276 bool SimplifyDemandedBits(SDValue Op) {
277 unsigned BitWidth = Op.getScalarValueSizeInBits();
278 APInt DemandedBits = APInt::getAllOnesValue(BitWidth);
279 return SimplifyDemandedBits(Op, DemandedBits);
280 }
281
282 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) {
283 EVT VT = Op.getValueType();
284 unsigned NumElts = VT.isVector() ? VT.getVectorNumElements() : 1;
285 APInt DemandedElts = APInt::getAllOnesValue(NumElts);
286 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts);
287 }
288
289 /// Check the specified vector node value to see if it can be simplified or
290 /// if things it uses can be simplified as it only uses some of the
291 /// elements. If so, return true.
292 bool SimplifyDemandedVectorElts(SDValue Op) {
293 unsigned NumElts = Op.getValueType().getVectorNumElements();
294 APInt DemandedElts = APInt::getAllOnesValue(NumElts);
295 return SimplifyDemandedVectorElts(Op, DemandedElts);
296 }
297
298 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
299 const APInt &DemandedElts);
300 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
301 bool AssumeSingleUse = false);
302
303 bool CombineToPreIndexedLoadStore(SDNode *N);
304 bool CombineToPostIndexedLoadStore(SDNode *N);
305 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
306 bool SliceUpLoad(SDNode *N);
307
308 // Scalars have size 0 to distinguish from singleton vectors.
309 SDValue ForwardStoreValueToDirectLoad(LoadSDNode *LD);
310 bool getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val);
311 bool extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val);
312
313 /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
314 /// load.
315 ///
316 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
317 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
318 /// \param EltNo index of the vector element to load.
319 /// \param OriginalLoad load that EVE came from to be replaced.
320 /// \returns EVE on success SDValue() on failure.
321 SDValue scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT,
322 SDValue EltNo,
323 LoadSDNode *OriginalLoad);
324 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
325 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
326 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
327 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
328 SDValue PromoteIntBinOp(SDValue Op);
329 SDValue PromoteIntShiftOp(SDValue Op);
330 SDValue PromoteExtend(SDValue Op);
331 bool PromoteLoad(SDValue Op);
332
333 /// Call the node-specific routine that knows how to fold each
334 /// particular type of node. If that doesn't do anything, try the
335 /// target-specific DAG combines.
336 SDValue combine(SDNode *N);
337
338 // Visitation implementation - Implement dag node combining for different
339 // node types. The semantics are as follows:
340 // Return Value:
341 // SDValue.getNode() == 0 - No change was made
342 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
343 // otherwise - N should be replaced by the returned Operand.
344 //
345 SDValue visitTokenFactor(SDNode *N);
346 SDValue visitMERGE_VALUES(SDNode *N);
347 SDValue visitADD(SDNode *N);
348 SDValue visitADDLike(SDNode *N);
349 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
350 SDValue visitSUB(SDNode *N);
351 SDValue visitADDSAT(SDNode *N);
352 SDValue visitSUBSAT(SDNode *N);
353 SDValue visitADDC(SDNode *N);
354 SDValue visitADDO(SDNode *N);
355 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
356 SDValue visitSUBC(SDNode *N);
357 SDValue visitSUBO(SDNode *N);
358 SDValue visitADDE(SDNode *N);
359 SDValue visitADDCARRY(SDNode *N);
360 SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
361 SDValue visitSUBE(SDNode *N);
362 SDValue visitSUBCARRY(SDNode *N);
363 SDValue visitMUL(SDNode *N);
364 SDValue useDivRem(SDNode *N);
365 SDValue visitSDIV(SDNode *N);
366 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
367 SDValue visitUDIV(SDNode *N);
368 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
369 SDValue visitREM(SDNode *N);
370 SDValue visitMULHU(SDNode *N);
371 SDValue visitMULHS(SDNode *N);
372 SDValue visitSMUL_LOHI(SDNode *N);
373 SDValue visitUMUL_LOHI(SDNode *N);
374 SDValue visitMULO(SDNode *N);
375 SDValue visitIMINMAX(SDNode *N);
376 SDValue visitAND(SDNode *N);
377 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
378 SDValue visitOR(SDNode *N);
379 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
380 SDValue visitXOR(SDNode *N);
381 SDValue SimplifyVBinOp(SDNode *N);
382 SDValue visitSHL(SDNode *N);
383 SDValue visitSRA(SDNode *N);
384 SDValue visitSRL(SDNode *N);
385 SDValue visitFunnelShift(SDNode *N);
386 SDValue visitRotate(SDNode *N);
387 SDValue visitABS(SDNode *N);
388 SDValue visitBSWAP(SDNode *N);
389 SDValue visitBITREVERSE(SDNode *N);
390 SDValue visitCTLZ(SDNode *N);
391 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
392 SDValue visitCTTZ(SDNode *N);
393 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
394 SDValue visitCTPOP(SDNode *N);
395 SDValue visitSELECT(SDNode *N);
396 SDValue visitVSELECT(SDNode *N);
397 SDValue visitSELECT_CC(SDNode *N);
398 SDValue visitSETCC(SDNode *N);
399 SDValue visitSETCCCARRY(SDNode *N);
400 SDValue visitSIGN_EXTEND(SDNode *N);
401 SDValue visitZERO_EXTEND(SDNode *N);
402 SDValue visitANY_EXTEND(SDNode *N);
403 SDValue visitAssertExt(SDNode *N);
404 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
405 SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
406 SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
407 SDValue visitTRUNCATE(SDNode *N);
408 SDValue visitBITCAST(SDNode *N);
409 SDValue visitBUILD_PAIR(SDNode *N);
410 SDValue visitFADD(SDNode *N);
411 SDValue visitFSUB(SDNode *N);
412 SDValue visitFMUL(SDNode *N);
413 SDValue visitFMA(SDNode *N);
414 SDValue visitFDIV(SDNode *N);
415 SDValue visitFREM(SDNode *N);
416 SDValue visitFSQRT(SDNode *N);
417 SDValue visitFCOPYSIGN(SDNode *N);
418 SDValue visitFPOW(SDNode *N);
419 SDValue visitSINT_TO_FP(SDNode *N);
420 SDValue visitUINT_TO_FP(SDNode *N);
421 SDValue visitFP_TO_SINT(SDNode *N);
422 SDValue visitFP_TO_UINT(SDNode *N);
423 SDValue visitFP_ROUND(SDNode *N);
424 SDValue visitFP_ROUND_INREG(SDNode *N);
425 SDValue visitFP_EXTEND(SDNode *N);
426 SDValue visitFNEG(SDNode *N);
427 SDValue visitFABS(SDNode *N);
428 SDValue visitFCEIL(SDNode *N);
429 SDValue visitFTRUNC(SDNode *N);
430 SDValue visitFFLOOR(SDNode *N);
431 SDValue visitFMINNUM(SDNode *N);
432 SDValue visitFMAXNUM(SDNode *N);
433 SDValue visitFMINIMUM(SDNode *N);
434 SDValue visitFMAXIMUM(SDNode *N);
435 SDValue visitBRCOND(SDNode *N);
436 SDValue visitBR_CC(SDNode *N);
437 SDValue visitLOAD(SDNode *N);
438
439 SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
440 SDValue replaceStoreOfFPConstant(StoreSDNode *ST);
441
442 SDValue visitSTORE(SDNode *N);
443 SDValue visitLIFETIME_END(SDNode *N);
444 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
445 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
446 SDValue visitBUILD_VECTOR(SDNode *N);
447 SDValue visitCONCAT_VECTORS(SDNode *N);
448 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
449 SDValue visitVECTOR_SHUFFLE(SDNode *N);
450 SDValue visitSCALAR_TO_VECTOR(SDNode *N);
451 SDValue visitINSERT_SUBVECTOR(SDNode *N);
452 SDValue visitMLOAD(SDNode *N);
453 SDValue visitMSTORE(SDNode *N);
454 SDValue visitMGATHER(SDNode *N);
455 SDValue visitMSCATTER(SDNode *N);
456 SDValue visitFP_TO_FP16(SDNode *N);
457 SDValue visitFP16_TO_FP(SDNode *N);
458 SDValue visitVECREDUCE(SDNode *N);
459
460 SDValue visitFADDForFMACombine(SDNode *N);
461 SDValue visitFSUBForFMACombine(SDNode *N);
462 SDValue visitFMULForFMADistributiveCombine(SDNode *N);
463
464 SDValue XformToShuffleWithZero(SDNode *N);
465 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
466 SDValue N1);
467 SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
468 SDValue N1, SDNodeFlags Flags);
469
470 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
471
472 SDValue foldSelectOfConstants(SDNode *N);
473 SDValue foldVSelectOfConstants(SDNode *N);
474 SDValue foldBinOpIntoSelect(SDNode *BO);
475 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
476 SDValue hoistLogicOpWithSameOpcodeHands(SDNode *N);
477 SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
478 SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
479 SDValue N2, SDValue N3, ISD::CondCode CC,
480 bool NotExtCompare = false);
481 SDValue convertSelectOfFPConstantsToLoadOffset(
482 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
483 ISD::CondCode CC);
484 SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
485 SDValue N2, SDValue N3, ISD::CondCode CC);
486 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
487 const SDLoc &DL);
488 SDValue unfoldMaskedMerge(SDNode *N);
489 SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
490 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
491 const SDLoc &DL, bool foldBooleans);
492 SDValue rebuildSetCC(SDValue N);
493
494 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
495 SDValue &CC) const;
496 bool isOneUseSetCC(SDValue N) const;
497
498 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
499 unsigned HiOp);
500 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
501 SDValue CombineExtLoad(SDNode *N);
502 SDValue CombineZExtLogicopShiftLoad(SDNode *N);
503 SDValue combineRepeatedFPDivisors(SDNode *N);
504 SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex);
505 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
506 SDValue BuildSDIV(SDNode *N);
507 SDValue BuildSDIVPow2(SDNode *N);
508 SDValue BuildUDIV(SDNode *N);
509 SDValue BuildLogBase2(SDValue V, const SDLoc &DL);
510 SDValue BuildReciprocalEstimate(SDValue Op, SDNodeFlags Flags);
511 SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
512 SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
513 SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
514 SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations,
515 SDNodeFlags Flags, bool Reciprocal);
516 SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations,
517 SDNodeFlags Flags, bool Reciprocal);
518 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
519 bool DemandHighBits = true);
520 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
521 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
522 SDValue InnerPos, SDValue InnerNeg,
523 unsigned PosOpcode, unsigned NegOpcode,
524 const SDLoc &DL);
525 SDNode *MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
526 SDValue MatchLoadCombine(SDNode *N);
527 SDValue ReduceLoadWidth(SDNode *N);
528 SDValue ReduceLoadOpStoreWidth(SDNode *N);
529 SDValue splitMergedValStore(StoreSDNode *ST);
530 SDValue TransformFPLoadStorePair(SDNode *N);
531 SDValue convertBuildVecZextToZext(SDNode *N);
532 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
533 SDValue reduceBuildVecToShuffle(SDNode *N);
534 SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
535 ArrayRef<int> VectorMask, SDValue VecIn1,
536 SDValue VecIn2, unsigned LeftIdx,
537 bool DidSplitVec);
538 SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast);
539
540 /// Walk up chain skipping non-aliasing memory nodes,
541 /// looking for aliasing nodes and adding them to the Aliases vector.
542 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
543 SmallVectorImpl<SDValue> &Aliases);
544
545 /// Return true if there is any possibility that the two addresses overlap.
546 bool isAlias(SDNode *Op0, SDNode *Op1) const;
547
548 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
549 /// chain (aliasing node.)
550 SDValue FindBetterChain(SDNode *N, SDValue Chain);
551
552 /// Try to replace a store and any possibly adjacent stores on
553 /// consecutive chains with better chains. Return true only if St is
554 /// replaced.
555 ///
556 /// Notice that other chains may still be replaced even if the function
557 /// returns false.
558 bool findBetterNeighborChains(StoreSDNode *St);
559
560 // Helper for findBetterNeighborChains. Walk up store chain add additional
561 // chained stores that do not overlap and can be parallelized.
562 bool parallelizeChainedStores(StoreSDNode *St);
563
564 /// Holds a pointer to an LSBaseSDNode as well as information on where it
565 /// is located in a sequence of memory operations connected by a chain.
566 struct MemOpLink {
567 // Ptr to the mem node.
568 LSBaseSDNode *MemNode;
569
570 // Offset from the base ptr.
571 int64_t OffsetFromBase;
572
573 MemOpLink(LSBaseSDNode *N, int64_t Offset)
574 : MemNode(N), OffsetFromBase(Offset) {}
575 };
576
577 /// This is a helper function for visitMUL to check the profitability
578 /// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
579 /// MulNode is the original multiply, AddNode is (add x, c1),
580 /// and ConstNode is c2.
581 bool isMulAddWithConstProfitable(SDNode *MulNode,
582 SDValue &AddNode,
583 SDValue &ConstNode);
584
585 /// This is a helper function for visitAND and visitZERO_EXTEND. Returns
586 /// true if the (and (load x) c) pattern matches an extload. ExtVT returns
587 /// the type of the loaded value to be extended.
588 bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
589 EVT LoadResultTy, EVT &ExtVT);
590
591 /// Helper function to calculate whether the given Load/Store can have its
592 /// width reduced to ExtVT.
593 bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType,
594 EVT &MemVT, unsigned ShAmt = 0);
595
596 /// Used by BackwardsPropagateMask to find suitable loads.
597 bool SearchForAndLoads(SDNode *N, SmallVectorImpl<LoadSDNode*> &Loads,
598 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
599 ConstantSDNode *Mask, SDNode *&NodeToMask);
600 /// Attempt to propagate a given AND node back to load leaves so that they
601 /// can be combined into narrow loads.
602 bool BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG);
603
604 /// Helper function for MergeConsecutiveStores which merges the
605 /// component store chains.
606 SDValue getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
607 unsigned NumStores);
608
609 /// This is a helper function for MergeConsecutiveStores. When the
610 /// source elements of the consecutive stores are all constants or
611 /// all extracted vector elements, try to merge them into one
612 /// larger store introducing bitcasts if necessary. \return True
613 /// if a merged store was created.
614 bool MergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
615 EVT MemVT, unsigned NumStores,
616 bool IsConstantSrc, bool UseVector,
617 bool UseTrunc);
618
619 /// This is a helper function for MergeConsecutiveStores. Stores
620 /// that potentially may be merged with St are placed in
621 /// StoreNodes. RootNode is a chain predecessor to all store
622 /// candidates.
623 void getStoreMergeCandidates(StoreSDNode *St,
624 SmallVectorImpl<MemOpLink> &StoreNodes,
625 SDNode *&Root);
626
627 /// Helper function for MergeConsecutiveStores. Checks if
628 /// candidate stores have indirect dependency through their
629 /// operands. RootNode is the predecessor to all stores calculated
630 /// by getStoreMergeCandidates and is used to prune the dependency check.
631 /// \return True if safe to merge.
632 bool checkMergeStoreCandidatesForDependencies(
633 SmallVectorImpl<MemOpLink> &StoreNodes, unsigned NumStores,
634 SDNode *RootNode);
635
636 /// Merge consecutive store operations into a wide store.
637 /// This optimization uses wide integers or vectors when possible.
638 /// \return number of stores that were merged into a merged store (the
639 /// affected nodes are stored as a prefix in \p StoreNodes).
640 bool MergeConsecutiveStores(StoreSDNode *St);
641
642 /// Try to transform a truncation where C is a constant:
643 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
644 ///
645 /// \p N needs to be a truncation and its first operand an AND. Other
646 /// requirements are checked by the function (e.g. that trunc is
647 /// single-use) and if missed an empty SDValue is returned.
648 SDValue distributeTruncateThroughAnd(SDNode *N);
649
650 /// Helper function to determine whether the target supports operation
651 /// given by \p Opcode for type \p VT, that is, whether the operation
652 /// is legal or custom before legalizing operations, and whether is
653 /// legal (but not custom) after legalization.
654 bool hasOperation(unsigned Opcode, EVT VT) {
655 if (LegalOperations)
656 return TLI.isOperationLegal(Opcode, VT);
657 return TLI.isOperationLegalOrCustom(Opcode, VT);
658 }
659
660 public:
661 /// Runs the dag combiner on all nodes in the work list
662 void Run(CombineLevel AtLevel);
663
664 SelectionDAG &getDAG() const { return DAG; }
665
666 /// Returns a type large enough to hold any valid shift amount - before type
667 /// legalization these can be huge.
668 EVT getShiftAmountTy(EVT LHSTy) {
669 assert(LHSTy.isInteger() && "Shift amount is not an integer type!")((LHSTy.isInteger() && "Shift amount is not an integer type!"
) ? static_cast<void> (0) : __assert_fail ("LHSTy.isInteger() && \"Shift amount is not an integer type!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 669, __PRETTY_FUNCTION__))
;
670 return TLI.getShiftAmountTy(LHSTy, DAG.getDataLayout(), LegalTypes);
671 }
672
673 /// This method returns true if we are running before type legalization or
674 /// if the specified VT is legal.
675 bool isTypeLegal(const EVT &VT) {
676 if (!LegalTypes) return true;
677 return TLI.isTypeLegal(VT);
678 }
679
680 /// Convenience wrapper around TargetLowering::getSetCCResultType
681 EVT getSetCCResultType(EVT VT) const {
682 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
683 }
684
685 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
686 SDValue OrigLoad, SDValue ExtLoad,
687 ISD::NodeType ExtType);
688 };
689
690/// This class is a DAGUpdateListener that removes any deleted
691/// nodes from the worklist.
692class WorklistRemover : public SelectionDAG::DAGUpdateListener {
693 DAGCombiner &DC;
694
695public:
696 explicit WorklistRemover(DAGCombiner &dc)
697 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
698
699 void NodeDeleted(SDNode *N, SDNode *E) override {
700 DC.removeFromWorklist(N);
701 }
702};
703
704class WorklistInserter : public SelectionDAG::DAGUpdateListener {
705 DAGCombiner &DC;
706
707public:
708 explicit WorklistInserter(DAGCombiner &dc)
709 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
710
711 // FIXME: Ideally we could add N to the worklist, but this causes exponential
712 // compile time costs in large DAGs, e.g. Halide.
713 void NodeInserted(SDNode *N) override { DC.ConsiderForPruning(N); }
714};
715
716} // end anonymous namespace
717
718//===----------------------------------------------------------------------===//
719// TargetLowering::DAGCombinerInfo implementation
720//===----------------------------------------------------------------------===//
721
722void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
723 ((DAGCombiner*)DC)->AddToWorklist(N);
724}
725
726SDValue TargetLowering::DAGCombinerInfo::
727CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
728 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
729}
730
731SDValue TargetLowering::DAGCombinerInfo::
732CombineTo(SDNode *N, SDValue Res, bool AddTo) {
733 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
734}
735
736SDValue TargetLowering::DAGCombinerInfo::
737CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
738 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
739}
740
741void TargetLowering::DAGCombinerInfo::
742CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
743 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
744}
745
746//===----------------------------------------------------------------------===//
747// Helper Functions
748//===----------------------------------------------------------------------===//
749
750void DAGCombiner::deleteAndRecombine(SDNode *N) {
751 removeFromWorklist(N);
752
753 // If the operands of this node are only used by the node, they will now be
754 // dead. Make sure to re-visit them and recursively delete dead nodes.
755 for (const SDValue &Op : N->ops())
756 // For an operand generating multiple values, one of the values may
757 // become dead allowing further simplification (e.g. split index
758 // arithmetic from an indexed load).
759 if (Op->hasOneUse() || Op->getNumValues() > 1)
760 AddToWorklist(Op.getNode());
761
762 DAG.DeleteNode(N);
763}
764
765/// Return 1 if we can compute the negated form of the specified expression for
766/// the same cost as the expression itself, or 2 if we can compute the negated
767/// form more cheaply than the expression itself.
768static char isNegatibleForFree(SDValue Op, bool LegalOperations,
769 const TargetLowering &TLI,
770 const TargetOptions *Options,
771 bool ForCodeSize,
772 unsigned Depth = 0) {
773 // fneg is removable even if it has multiple uses.
774 if (Op.getOpcode() == ISD::FNEG) return 2;
775
776 // Don't allow anything with multiple uses unless we know it is free.
777 EVT VT = Op.getValueType();
778 const SDNodeFlags Flags = Op->getFlags();
779 if (!Op.hasOneUse())
780 if (!(Op.getOpcode() == ISD::FP_EXTEND &&
781 TLI.isFPExtFree(VT, Op.getOperand(0).getValueType())))
782 return 0;
783
784 // Don't recurse exponentially.
785 if (Depth > 6) return 0;
786
787 switch (Op.getOpcode()) {
788 default: return false;
789 case ISD::ConstantFP: {
790 if (!LegalOperations)
791 return 1;
792
793 // Don't invert constant FP values after legalization unless the target says
794 // the negated constant is legal.
795 return TLI.isOperationLegal(ISD::ConstantFP, VT) ||
796 TLI.isFPImmLegal(neg(cast<ConstantFPSDNode>(Op)->getValueAPF()), VT,
797 ForCodeSize);
798 }
799 case ISD::FADD:
800 if (!Options->UnsafeFPMath && !Flags.hasNoSignedZeros())
801 return 0;
802
803 // After operation legalization, it might not be legal to create new FSUBs.
804 if (LegalOperations && !TLI.isOperationLegalOrCustom(ISD::FSUB, VT))
805 return 0;
806
807 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
808 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
809 Options, ForCodeSize, Depth + 1))
810 return V;
811 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
812 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
813 ForCodeSize, Depth + 1);
814 case ISD::FSUB:
815 // We can't turn -(A-B) into B-A when we honor signed zeros.
816 if (!Options->NoSignedZerosFPMath &&
817 !Flags.hasNoSignedZeros())
818 return 0;
819
820 // fold (fneg (fsub A, B)) -> (fsub B, A)
821 return 1;
822
823 case ISD::FMUL:
824 case ISD::FDIV:
825 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
826 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
827 Options, ForCodeSize, Depth + 1))
828 return V;
829
830 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
831 ForCodeSize, Depth + 1);
832
833 case ISD::FP_EXTEND:
834 case ISD::FP_ROUND:
835 case ISD::FSIN:
836 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
837 ForCodeSize, Depth + 1);
838 }
839}
840
841/// If isNegatibleForFree returns true, return the newly negated expression.
842static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
843 bool LegalOperations, bool ForCodeSize,
844 unsigned Depth = 0) {
845 const TargetOptions &Options = DAG.getTarget().Options;
846 // fneg is removable even if it has multiple uses.
847 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
848
849 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree")((Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"
) ? static_cast<void> (0) : __assert_fail ("Depth <= 6 && \"GetNegatedExpression doesn't match isNegatibleForFree\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 849, __PRETTY_FUNCTION__))
;
850
851 const SDNodeFlags Flags = Op.getNode()->getFlags();
852
853 switch (Op.getOpcode()) {
854 default: llvm_unreachable("Unknown code")::llvm::llvm_unreachable_internal("Unknown code", "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 854)
;
855 case ISD::ConstantFP: {
856 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
857 V.changeSign();
858 return DAG.getConstantFP(V, SDLoc(Op), Op.getValueType());
859 }
860 case ISD::FADD:
861 assert(Options.UnsafeFPMath || Flags.hasNoSignedZeros())((Options.UnsafeFPMath || Flags.hasNoSignedZeros()) ? static_cast
<void> (0) : __assert_fail ("Options.UnsafeFPMath || Flags.hasNoSignedZeros()"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 861, __PRETTY_FUNCTION__))
;
862
863 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
864 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
865 DAG.getTargetLoweringInfo(), &Options, ForCodeSize,
866 Depth+1))
867 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
868 GetNegatedExpression(Op.getOperand(0), DAG,
869 LegalOperations, ForCodeSize,
870 Depth+1),
871 Op.getOperand(1), Flags);
872 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
873 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
874 GetNegatedExpression(Op.getOperand(1), DAG,
875 LegalOperations, ForCodeSize,
876 Depth+1),
877 Op.getOperand(0), Flags);
878 case ISD::FSUB:
879 // fold (fneg (fsub 0, B)) -> B
880 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
881 if (N0CFP->isZero())
882 return Op.getOperand(1);
883
884 // fold (fneg (fsub A, B)) -> (fsub B, A)
885 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
886 Op.getOperand(1), Op.getOperand(0), Flags);
887
888 case ISD::FMUL:
889 case ISD::FDIV:
890 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
891 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
892 DAG.getTargetLoweringInfo(), &Options, ForCodeSize,
893 Depth+1))
894 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
895 GetNegatedExpression(Op.getOperand(0), DAG,
896 LegalOperations, ForCodeSize,
897 Depth+1),
898 Op.getOperand(1), Flags);
899
900 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
901 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
902 Op.getOperand(0),
903 GetNegatedExpression(Op.getOperand(1), DAG,
904 LegalOperations, ForCodeSize,
905 Depth+1), Flags);
906
907 case ISD::FP_EXTEND:
908 case ISD::FSIN:
909 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
910 GetNegatedExpression(Op.getOperand(0), DAG,
911 LegalOperations, ForCodeSize,
912 Depth+1));
913 case ISD::FP_ROUND:
914 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
915 GetNegatedExpression(Op.getOperand(0), DAG,
916 LegalOperations, ForCodeSize,
917 Depth+1),
918 Op.getOperand(1));
919 }
920}
921
922// APInts must be the same size for most operations, this helper
923// function zero extends the shorter of the pair so that they match.
924// We provide an Offset so that we can create bitwidths that won't overflow.
925static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) {
926 unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth());
927 LHS = LHS.zextOrSelf(Bits);
928 RHS = RHS.zextOrSelf(Bits);
929}
930
931// Return true if this node is a setcc, or is a select_cc
932// that selects between the target values used for true and false, making it
933// equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
934// the appropriate nodes based on the type of node we are checking. This
935// simplifies life a bit for the callers.
936bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
937 SDValue &CC) const {
938 if (N.getOpcode() == ISD::SETCC) {
939 LHS = N.getOperand(0);
940 RHS = N.getOperand(1);
941 CC = N.getOperand(2);
942 return true;
943 }
944
945 if (N.getOpcode() != ISD::SELECT_CC ||
946 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
947 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
948 return false;
949
950 if (TLI.getBooleanContents(N.getValueType()) ==
951 TargetLowering::UndefinedBooleanContent)
952 return false;
953
954 LHS = N.getOperand(0);
955 RHS = N.getOperand(1);
956 CC = N.getOperand(4);
957 return true;
958}
959
960/// Return true if this is a SetCC-equivalent operation with only one use.
961/// If this is true, it allows the users to invert the operation for free when
962/// it is profitable to do so.
963bool DAGCombiner::isOneUseSetCC(SDValue N) const {
964 SDValue N0, N1, N2;
965 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
966 return true;
967 return false;
968}
969
970// Returns the SDNode if it is a constant float BuildVector
971// or constant float.
972static SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) {
973 if (isa<ConstantFPSDNode>(N))
974 return N.getNode();
975 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
976 return N.getNode();
977 return nullptr;
978}
979
980// Determines if it is a constant integer or a build vector of constant
981// integers (and undefs).
982// Do not permit build vector implicit truncation.
983static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) {
984 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N))
985 return !(Const->isOpaque() && NoOpaques);
986 if (N.getOpcode() != ISD::BUILD_VECTOR)
987 return false;
988 unsigned BitWidth = N.getScalarValueSizeInBits();
989 for (const SDValue &Op : N->op_values()) {
990 if (Op.isUndef())
991 continue;
992 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op);
993 if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth ||
994 (Const->isOpaque() && NoOpaques))
995 return false;
996 }
997 return true;
998}
999
1000// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with
1001// undef's.
1002static bool isAnyConstantBuildVector(SDValue V, bool NoOpaques = false) {
1003 if (V.getOpcode() != ISD::BUILD_VECTOR)
1004 return false;
1005 return isConstantOrConstantVector(V, NoOpaques) ||
1006 ISD::isBuildVectorOfConstantFPSDNodes(V.getNode());
1007}
1008
1009// Helper for DAGCombiner::reassociateOps. Try to reassociate an expression
1010// such as (Opc N0, N1), if \p N0 is the same kind of operation as \p Opc.
1011SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
1012 SDValue N0, SDValue N1) {
1013 EVT VT = N0.getValueType();
1014
1015 if (N0.getOpcode() != Opc)
1016 return SDValue();
1017
1018 // Don't reassociate reductions.
1019 if (N0->getFlags().hasVectorReduction())
1020 return SDValue();
1021
1022 if (SDNode *C1 = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
1023 if (SDNode *C2 = DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
1024 // Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
1025 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, C1, C2))
1026 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
1027 return SDValue();
1028 }
1029 if (N0.hasOneUse()) {
1030 // Reassociate: (op (op x, c1), y) -> (op (op x, y), c1)
1031 // iff (op x, c1) has one use
1032 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
1033 if (!OpNode.getNode())
1034 return SDValue();
1035 AddToWorklist(OpNode.getNode());
1036 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
1037 }
1038 }
1039 return SDValue();
1040}
1041
1042// Try to reassociate commutative binops.
1043SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
1044 SDValue N1, SDNodeFlags Flags) {
1045 assert(TLI.isCommutativeBinOp(Opc) && "Operation not commutative.")((TLI.isCommutativeBinOp(Opc) && "Operation not commutative."
) ? static_cast<void> (0) : __assert_fail ("TLI.isCommutativeBinOp(Opc) && \"Operation not commutative.\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1045, __PRETTY_FUNCTION__))
;
1046 // Don't reassociate reductions.
1047 if (Flags.hasVectorReduction())
1048 return SDValue();
1049
1050 // Floating-point reassociation is not allowed without loose FP math.
1051 if (N0.getValueType().isFloatingPoint() ||
1052 N1.getValueType().isFloatingPoint())
1053 if (!Flags.hasAllowReassociation() || !Flags.hasNoSignedZeros())
1054 return SDValue();
1055
1056 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1))
1057 return Combined;
1058 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0))
1059 return Combined;
1060 return SDValue();
1061}
1062
1063SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
1064 bool AddTo) {
1065 assert(N->getNumValues() == NumTo && "Broken CombineTo call!")((N->getNumValues() == NumTo && "Broken CombineTo call!"
) ? static_cast<void> (0) : __assert_fail ("N->getNumValues() == NumTo && \"Broken CombineTo call!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1065, __PRETTY_FUNCTION__))
;
1066 ++NodesCombined;
1067 LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1068 To[0].getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1069 dbgs() << " and " << NumTo - 1 << " other values\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
;
1070 for (unsigned i = 0, e = NumTo; i != e; ++i)
1071 assert((!To[i].getNode() ||(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1073, __PRETTY_FUNCTION__))
1072 N->getValueType(i) == To[i].getValueType()) &&(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1073, __PRETTY_FUNCTION__))
1073 "Cannot combine value to value of different type!")(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1073, __PRETTY_FUNCTION__))
;
1074
1075 WorklistRemover DeadNodes(*this);
1076 DAG.ReplaceAllUsesWith(N, To);
1077 if (AddTo) {
1078 // Push the new nodes and any users onto the worklist
1079 for (unsigned i = 0, e = NumTo; i != e; ++i) {
1080 if (To[i].getNode()) {
1081 AddToWorklist(To[i].getNode());
1082 AddUsersToWorklist(To[i].getNode());
1083 }
1084 }
1085 }
1086
1087 // Finally, if the node is now dead, remove it from the graph. The node
1088 // may not be dead if the replacement process recursively simplified to
1089 // something else needing this node.
1090 if (N->use_empty())
1091 deleteAndRecombine(N);
1092 return SDValue(N, 0);
1093}
1094
1095void DAGCombiner::
1096CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
1097 // Replace all uses. If any nodes become isomorphic to other nodes and
1098 // are deleted, make sure to remove them from our worklist.
1099 WorklistRemover DeadNodes(*this);
1100 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
1101
1102 // Push the new node and any (possibly new) users onto the worklist.
1103 AddToWorklist(TLO.New.getNode());
1104 AddUsersToWorklist(TLO.New.getNode());
1105
1106 // Finally, if the node is now dead, remove it from the graph. The node
1107 // may not be dead if the replacement process recursively simplified to
1108 // something else needing this node.
1109 if (TLO.Old.getNode()->use_empty())
1110 deleteAndRecombine(TLO.Old.getNode());
1111}
1112
1113/// Check the specified integer node value to see if it can be simplified or if
1114/// things it uses can be simplified by bit propagation. If so, return true.
1115bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
1116 const APInt &DemandedElts) {
1117 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1118 KnownBits Known;
1119 if (!TLI.SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO))
1120 return false;
1121
1122 // Revisit the node.
1123 AddToWorklist(Op.getNode());
1124
1125 // Replace the old value with the new one.
1126 ++NodesCombined;
1127 LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1128 dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1129 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
;
1130
1131 CommitTargetLoweringOpt(TLO);
1132 return true;
1133}
1134
1135/// Check the specified vector node value to see if it can be simplified or
1136/// if things it uses can be simplified as it only uses some of the elements.
1137/// If so, return true.
1138bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op,
1139 const APInt &DemandedElts,
1140 bool AssumeSingleUse) {
1141 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1142 APInt KnownUndef, KnownZero;
1143 if (!TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero,
1144 TLO, 0, AssumeSingleUse))
1145 return false;
1146
1147 // Revisit the node.
1148 AddToWorklist(Op.getNode());
1149
1150 // Replace the old value with the new one.
1151 ++NodesCombined;
1152 LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1153 dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1154 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
;
1155
1156 CommitTargetLoweringOpt(TLO);
1157 return true;
1158}
1159
1160void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
1161 SDLoc DL(Load);
1162 EVT VT = Load->getValueType(0);
1163 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0));
1164
1165 LLVM_DEBUG(dbgs() << "\nReplacing.9 "; Load->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
1166 Trunc.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
;
1167 WorklistRemover DeadNodes(*this);
1168 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
1169 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
1170 deleteAndRecombine(Load);
1171 AddToWorklist(Trunc.getNode());
1172}
1173
1174SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
1175 Replace = false;
1176 SDLoc DL(Op);
1177 if (ISD::isUNINDEXEDLoad(Op.getNode())) {
1178 LoadSDNode *LD = cast<LoadSDNode>(Op);
1179 EVT MemVT = LD->getMemoryVT();
1180 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1181 : LD->getExtensionType();
1182 Replace = true;
1183 return DAG.getExtLoad(ExtType, DL, PVT,
1184 LD->getChain(), LD->getBasePtr(),
1185 MemVT, LD->getMemOperand());
1186 }
1187
1188 unsigned Opc = Op.getOpcode();
1189 switch (Opc) {
1190 default: break;
1191 case ISD::AssertSext:
1192 if (SDValue Op0 = SExtPromoteOperand(Op.getOperand(0), PVT))
1193 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1));
1194 break;
1195 case ISD::AssertZext:
1196 if (SDValue Op0 = ZExtPromoteOperand(Op.getOperand(0), PVT))
1197 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1));
1198 break;
1199 case ISD::Constant: {
1200 unsigned ExtOpc =
1201 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1202 return DAG.getNode(ExtOpc, DL, PVT, Op);
1203 }
1204 }
1205
1206 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
1207 return SDValue();
1208 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op);
1209}
1210
1211SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
1212 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
1213 return SDValue();
1214 EVT OldVT = Op.getValueType();
1215 SDLoc DL(Op);
1216 bool Replace = false;
1217 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1218 if (!NewOp.getNode())
1219 return SDValue();
1220 AddToWorklist(NewOp.getNode());
1221
1222 if (Replace)
1223 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1224 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp,
1225 DAG.getValueType(OldVT));
1226}
1227
1228SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
1229 EVT OldVT = Op.getValueType();
1230 SDLoc DL(Op);
1231 bool Replace = false;
1232 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1233 if (!NewOp.getNode())
1234 return SDValue();
1235 AddToWorklist(NewOp.getNode());
1236
1237 if (Replace)
1238 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1239 return DAG.getZeroExtendInReg(NewOp, DL, OldVT);
1240}
1241
1242/// Promote the specified integer binary operation if the target indicates it is
1243/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1244/// i32 since i16 instructions are longer.
1245SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
1246 if (!LegalOperations)
1247 return SDValue();
1248
1249 EVT VT = Op.getValueType();
1250 if (VT.isVector() || !VT.isInteger())
1251 return SDValue();
1252
1253 // If operation type is 'undesirable', e.g. i16 on x86, consider
1254 // promoting it.
1255 unsigned Opc = Op.getOpcode();
1256 if (TLI.isTypeDesirableForOp(Opc, VT))
1257 return SDValue();
1258
1259 EVT PVT = VT;
1260 // Consult target whether it is a good idea to promote this operation and
1261 // what's the right type to promote it to.
1262 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1263 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1263, __PRETTY_FUNCTION__))
;
1264
1265 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1266
1267 bool Replace0 = false;
1268 SDValue N0 = Op.getOperand(0);
1269 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1270
1271 bool Replace1 = false;
1272 SDValue N1 = Op.getOperand(1);
1273 SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
1274 SDLoc DL(Op);
1275
1276 SDValue RV =
1277 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1));
1278
1279 // We are always replacing N0/N1's use in N and only need
1280 // additional replacements if there are additional uses.
1281 Replace0 &= !N0->hasOneUse();
1282 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1283
1284 // Combine Op here so it is preserved past replacements.
1285 CombineTo(Op.getNode(), RV);
1286
1287 // If operands have a use ordering, make sure we deal with
1288 // predecessor first.
1289 if (Replace0 && Replace1 && N0.getNode()->isPredecessorOf(N1.getNode())) {
1290 std::swap(N0, N1);
1291 std::swap(NN0, NN1);
1292 }
1293
1294 if (Replace0) {
1295 AddToWorklist(NN0.getNode());
1296 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1297 }
1298 if (Replace1) {
1299 AddToWorklist(NN1.getNode());
1300 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1301 }
1302 return Op;
1303 }
1304 return SDValue();
1305}
1306
1307/// Promote the specified integer shift operation if the target indicates it is
1308/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1309/// i32 since i16 instructions are longer.
1310SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1311 if (!LegalOperations)
1312 return SDValue();
1313
1314 EVT VT = Op.getValueType();
1315 if (VT.isVector() || !VT.isInteger())
1316 return SDValue();
1317
1318 // If operation type is 'undesirable', e.g. i16 on x86, consider
1319 // promoting it.
1320 unsigned Opc = Op.getOpcode();
1321 if (TLI.isTypeDesirableForOp(Opc, VT))
1322 return SDValue();
1323
1324 EVT PVT = VT;
1325 // Consult target whether it is a good idea to promote this operation and
1326 // what's the right type to promote it to.
1327 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1328 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1328, __PRETTY_FUNCTION__))
;
1329
1330 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1331
1332 bool Replace = false;
1333 SDValue N0 = Op.getOperand(0);
1334 SDValue N1 = Op.getOperand(1);
1335 if (Opc == ISD::SRA)
1336 N0 = SExtPromoteOperand(N0, PVT);
1337 else if (Opc == ISD::SRL)
1338 N0 = ZExtPromoteOperand(N0, PVT);
1339 else
1340 N0 = PromoteOperand(N0, PVT, Replace);
1341
1342 if (!N0.getNode())
1343 return SDValue();
1344
1345 SDLoc DL(Op);
1346 SDValue RV =
1347 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
1348
1349 AddToWorklist(N0.getNode());
1350 if (Replace)
1351 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1352
1353 // Deal with Op being deleted.
1354 if (Op && Op.getOpcode() != ISD::DELETED_NODE)
1355 return RV;
1356 }
1357 return SDValue();
1358}
1359
1360SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1361 if (!LegalOperations)
1362 return SDValue();
1363
1364 EVT VT = Op.getValueType();
1365 if (VT.isVector() || !VT.isInteger())
1366 return SDValue();
1367
1368 // If operation type is 'undesirable', e.g. i16 on x86, consider
1369 // promoting it.
1370 unsigned Opc = Op.getOpcode();
1371 if (TLI.isTypeDesirableForOp(Opc, VT))
1372 return SDValue();
1373
1374 EVT PVT = VT;
1375 // Consult target whether it is a good idea to promote this operation and
1376 // what's the right type to promote it to.
1377 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1378 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1378, __PRETTY_FUNCTION__))
;
1379 // fold (aext (aext x)) -> (aext x)
1380 // fold (aext (zext x)) -> (zext x)
1381 // fold (aext (sext x)) -> (sext x)
1382 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1383 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1384 }
1385 return SDValue();
1386}
1387
1388bool DAGCombiner::PromoteLoad(SDValue Op) {
1389 if (!LegalOperations)
1390 return false;
1391
1392 if (!ISD::isUNINDEXEDLoad(Op.getNode()))
1393 return false;
1394
1395 EVT VT = Op.getValueType();
1396 if (VT.isVector() || !VT.isInteger())
1397 return false;
1398
1399 // If operation type is 'undesirable', e.g. i16 on x86, consider
1400 // promoting it.
1401 unsigned Opc = Op.getOpcode();
1402 if (TLI.isTypeDesirableForOp(Opc, VT))
1403 return false;
1404
1405 EVT PVT = VT;
1406 // Consult target whether it is a good idea to promote this operation and
1407 // what's the right type to promote it to.
1408 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1409 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1409, __PRETTY_FUNCTION__))
;
1410
1411 SDLoc DL(Op);
1412 SDNode *N = Op.getNode();
1413 LoadSDNode *LD = cast<LoadSDNode>(N);
1414 EVT MemVT = LD->getMemoryVT();
1415 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1416 : LD->getExtensionType();
1417 SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT,
1418 LD->getChain(), LD->getBasePtr(),
1419 MemVT, LD->getMemOperand());
1420 SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1421
1422 LLVM_DEBUG(dbgs() << "\nPromoting "; N->dump(&DAG); dbgs() << "\nTo: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
1423 Result.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
;
1424 WorklistRemover DeadNodes(*this);
1425 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1426 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1427 deleteAndRecombine(N);
1428 AddToWorklist(Result.getNode());
1429 return true;
1430 }
1431 return false;
1432}
1433
1434/// Recursively delete a node which has no uses and any operands for
1435/// which it is the only use.
1436///
1437/// Note that this both deletes the nodes and removes them from the worklist.
1438/// It also adds any nodes who have had a user deleted to the worklist as they
1439/// may now have only one use and subject to other combines.
1440bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1441 if (!N->use_empty())
1442 return false;
1443
1444 SmallSetVector<SDNode *, 16> Nodes;
1445 Nodes.insert(N);
1446 do {
1447 N = Nodes.pop_back_val();
1448 if (!N)
1449 continue;
1450
1451 if (N->use_empty()) {
1452 for (const SDValue &ChildN : N->op_values())
1453 Nodes.insert(ChildN.getNode());
1454
1455 removeFromWorklist(N);
1456 DAG.DeleteNode(N);
1457 } else {
1458 AddToWorklist(N);
1459 }
1460 } while (!Nodes.empty());
1461 return true;
1462}
1463
1464//===----------------------------------------------------------------------===//
1465// Main DAG Combiner implementation
1466//===----------------------------------------------------------------------===//
1467
1468void DAGCombiner::Run(CombineLevel AtLevel) {
1469 // set the instance variables, so that the various visit routines may use it.
1470 Level = AtLevel;
1471 LegalOperations = Level >= AfterLegalizeVectorOps;
1472 LegalTypes = Level >= AfterLegalizeTypes;
1473
1474 WorklistInserter AddNodes(*this);
1475
1476 // Add all the dag nodes to the worklist.
1477 for (SDNode &Node : DAG.allnodes())
1478 AddToWorklist(&Node);
1479
1480 // Create a dummy node (which is not added to allnodes), that adds a reference
1481 // to the root node, preventing it from being deleted, and tracking any
1482 // changes of the root.
1483 HandleSDNode Dummy(DAG.getRoot());
1484
1485 // While we have a valid worklist entry node, try to combine it.
1486 while (SDNode *N = getNextWorklistEntry()) {
1487 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1488 // N is deleted from the DAG, since they too may now be dead or may have a
1489 // reduced number of uses, allowing other xforms.
1490 if (recursivelyDeleteUnusedNodes(N))
1491 continue;
1492
1493 WorklistRemover DeadNodes(*this);
1494
1495 // If this combine is running after legalizing the DAG, re-legalize any
1496 // nodes pulled off the worklist.
1497 if (Level == AfterLegalizeDAG) {
1498 SmallSetVector<SDNode *, 16> UpdatedNodes;
1499 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1500
1501 for (SDNode *LN : UpdatedNodes) {
1502 AddToWorklist(LN);
1503 AddUsersToWorklist(LN);
1504 }
1505 if (!NIsValid)
1506 continue;
1507 }
1508
1509 LLVM_DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nCombining: "; N->dump
(&DAG); } } while (false)
;
1510
1511 // Add any operands of the new node which have not yet been combined to the
1512 // worklist as well. Because the worklist uniques things already, this
1513 // won't repeatedly process the same operand.
1514 CombinedNodes.insert(N);
1515 for (const SDValue &ChildN : N->op_values())
1516 if (!CombinedNodes.count(ChildN.getNode()))
1517 AddToWorklist(ChildN.getNode());
1518
1519 SDValue RV = combine(N);
1520
1521 if (!RV.getNode())
1522 continue;
1523
1524 ++NodesCombined;
1525
1526 // If we get back the same node we passed in, rather than a new node or
1527 // zero, we know that the node must have defined multiple values and
1528 // CombineTo was used. Since CombineTo takes care of the worklist
1529 // mechanics for us, we have no work to do in this case.
1530 if (RV.getNode() == N)
1531 continue;
1532
1533 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1535, __PRETTY_FUNCTION__))
1534 RV.getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1535, __PRETTY_FUNCTION__))
1535 "Node was deleted but visit returned new node!")((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1535, __PRETTY_FUNCTION__))
;
1536
1537 LLVM_DEBUG(dbgs() << " ... into: "; RV.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << " ... into: "; RV.getNode()
->dump(&DAG); } } while (false)
;
1538
1539 if (N->getNumValues() == RV.getNode()->getNumValues())
1540 DAG.ReplaceAllUsesWith(N, RV.getNode());
1541 else {
1542 assert(N->getValueType(0) == RV.getValueType() &&((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1543, __PRETTY_FUNCTION__))
1543 N->getNumValues() == 1 && "Type mismatch")((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1543, __PRETTY_FUNCTION__))
;
1544 DAG.ReplaceAllUsesWith(N, &RV);
1545 }
1546
1547 // Push the new node and any users onto the worklist
1548 AddToWorklist(RV.getNode());
1549 AddUsersToWorklist(RV.getNode());
1550
1551 // Finally, if the node is now dead, remove it from the graph. The node
1552 // may not be dead if the replacement process recursively simplified to
1553 // something else needing this node. This will also take care of adding any
1554 // operands which have lost a user to the worklist.
1555 recursivelyDeleteUnusedNodes(N);
1556 }
1557
1558 // If the root changed (e.g. it was a dead load, update the root).
1559 DAG.setRoot(Dummy.getValue());
1560 DAG.RemoveDeadNodes();
1561}
1562
1563SDValue DAGCombiner::visit(SDNode *N) {
1564 switch (N->getOpcode()) {
1565 default: break;
1566 case ISD::TokenFactor: return visitTokenFactor(N);
1567 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1568 case ISD::ADD: return visitADD(N);
1569 case ISD::SUB: return visitSUB(N);
1570 case ISD::SADDSAT:
1571 case ISD::UADDSAT: return visitADDSAT(N);
1572 case ISD::SSUBSAT:
1573 case ISD::USUBSAT: return visitSUBSAT(N);
1574 case ISD::ADDC: return visitADDC(N);
1575 case ISD::SADDO:
1576 case ISD::UADDO: return visitADDO(N);
1577 case ISD::SUBC: return visitSUBC(N);
1578 case ISD::SSUBO:
1579 case ISD::USUBO: return visitSUBO(N);
1580 case ISD::ADDE: return visitADDE(N);
1581 case ISD::ADDCARRY: return visitADDCARRY(N);
1582 case ISD::SUBE: return visitSUBE(N);
1583 case ISD::SUBCARRY: return visitSUBCARRY(N);
1584 case ISD::MUL: return visitMUL(N);
1585 case ISD::SDIV: return visitSDIV(N);
1586 case ISD::UDIV: return visitUDIV(N);
1587 case ISD::SREM:
1588 case ISD::UREM: return visitREM(N);
1589 case ISD::MULHU: return visitMULHU(N);
1590 case ISD::MULHS: return visitMULHS(N);
1591 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1592 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1593 case ISD::SMULO:
1594 case ISD::UMULO: return visitMULO(N);
1595 case ISD::SMIN:
1596 case ISD::SMAX:
1597 case ISD::UMIN:
1598 case ISD::UMAX: return visitIMINMAX(N);
1599 case ISD::AND: return visitAND(N);
1600 case ISD::OR: return visitOR(N);
1601 case ISD::XOR: return visitXOR(N);
1602 case ISD::SHL: return visitSHL(N);
1603 case ISD::SRA: return visitSRA(N);
1604 case ISD::SRL: return visitSRL(N);
1605 case ISD::ROTR:
1606 case ISD::ROTL: return visitRotate(N);
1607 case ISD::FSHL:
1608 case ISD::FSHR: return visitFunnelShift(N);
1609 case ISD::ABS: return visitABS(N);
1610 case ISD::BSWAP: return visitBSWAP(N);
1611 case ISD::BITREVERSE: return visitBITREVERSE(N);
1612 case ISD::CTLZ: return visitCTLZ(N);
1613 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1614 case ISD::CTTZ: return visitCTTZ(N);
1615 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1616 case ISD::CTPOP: return visitCTPOP(N);
1617 case ISD::SELECT: return visitSELECT(N);
1618 case ISD::VSELECT: return visitVSELECT(N);
1619 case ISD::SELECT_CC: return visitSELECT_CC(N);
1620 case ISD::SETCC: return visitSETCC(N);
1621 case ISD::SETCCCARRY: return visitSETCCCARRY(N);
1622 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1623 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1624 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1625 case ISD::AssertSext:
1626 case ISD::AssertZext: return visitAssertExt(N);
1627 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1628 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
1629 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
1630 case ISD::TRUNCATE: return visitTRUNCATE(N);
1631 case ISD::BITCAST: return visitBITCAST(N);
1632 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1633 case ISD::FADD: return visitFADD(N);
1634 case ISD::FSUB: return visitFSUB(N);
1635 case ISD::FMUL: return visitFMUL(N);
1636 case ISD::FMA: return visitFMA(N);
1637 case ISD::FDIV: return visitFDIV(N);
1638 case ISD::FREM: return visitFREM(N);
1639 case ISD::FSQRT: return visitFSQRT(N);
1640 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1641 case ISD::FPOW: return visitFPOW(N);
1642 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1643 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1644 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1645 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1646 case ISD::FP_ROUND: return visitFP_ROUND(N);
1647 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1648 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1649 case ISD::FNEG: return visitFNEG(N);
1650 case ISD::FABS: return visitFABS(N);
1651 case ISD::FFLOOR: return visitFFLOOR(N);
1652 case ISD::FMINNUM: return visitFMINNUM(N);
1653 case ISD::FMAXNUM: return visitFMAXNUM(N);
1654 case ISD::FMINIMUM: return visitFMINIMUM(N);
1655 case ISD::FMAXIMUM: return visitFMAXIMUM(N);
1656 case ISD::FCEIL: return visitFCEIL(N);
1657 case ISD::FTRUNC: return visitFTRUNC(N);
1658 case ISD::BRCOND: return visitBRCOND(N);
1659 case ISD::BR_CC: return visitBR_CC(N);
1660 case ISD::LOAD: return visitLOAD(N);
1661 case ISD::STORE: return visitSTORE(N);
1662 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1663 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1664 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1665 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1666 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1667 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1668 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
1669 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1670 case ISD::MGATHER: return visitMGATHER(N);
1671 case ISD::MLOAD: return visitMLOAD(N);
1672 case ISD::MSCATTER: return visitMSCATTER(N);
1673 case ISD::MSTORE: return visitMSTORE(N);
1674 case ISD::LIFETIME_END: return visitLIFETIME_END(N);
1675 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
1676 case ISD::FP16_TO_FP: return visitFP16_TO_FP(N);
1677 case ISD::VECREDUCE_FADD:
1678 case ISD::VECREDUCE_FMUL:
1679 case ISD::VECREDUCE_ADD:
1680 case ISD::VECREDUCE_MUL:
1681 case ISD::VECREDUCE_AND:
1682 case ISD::VECREDUCE_OR:
1683 case ISD::VECREDUCE_XOR:
1684 case ISD::VECREDUCE_SMAX:
1685 case ISD::VECREDUCE_SMIN:
1686 case ISD::VECREDUCE_UMAX:
1687 case ISD::VECREDUCE_UMIN:
1688 case ISD::VECREDUCE_FMAX:
1689 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N);
1690 }
1691 return SDValue();
1692}
1693
1694SDValue DAGCombiner::combine(SDNode *N) {
1695 SDValue RV = visit(N);
1696
1697 // If nothing happened, try a target-specific DAG combine.
1698 if (!RV.getNode()) {
1699 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1700, __PRETTY_FUNCTION__))
1700 "Node was deleted but visit returned NULL!")((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1700, __PRETTY_FUNCTION__))
;
1701
1702 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1703 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1704
1705 // Expose the DAG combiner to the target combiner impls.
1706 TargetLowering::DAGCombinerInfo
1707 DagCombineInfo(DAG, Level, false, this);
1708
1709 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1710 }
1711 }
1712
1713 // If nothing happened still, try promoting the operation.
1714 if (!RV.getNode()) {
1715 switch (N->getOpcode()) {
1716 default: break;
1717 case ISD::ADD:
1718 case ISD::SUB:
1719 case ISD::MUL:
1720 case ISD::AND:
1721 case ISD::OR:
1722 case ISD::XOR:
1723 RV = PromoteIntBinOp(SDValue(N, 0));
1724 break;
1725 case ISD::SHL:
1726 case ISD::SRA:
1727 case ISD::SRL:
1728 RV = PromoteIntShiftOp(SDValue(N, 0));
1729 break;
1730 case ISD::SIGN_EXTEND:
1731 case ISD::ZERO_EXTEND:
1732 case ISD::ANY_EXTEND:
1733 RV = PromoteExtend(SDValue(N, 0));
1734 break;
1735 case ISD::LOAD:
1736 if (PromoteLoad(SDValue(N, 0)))
1737 RV = SDValue(N, 0);
1738 break;
1739 }
1740 }
1741
1742 // If N is a commutative binary node, try to eliminate it if the commuted
1743 // version is already present in the DAG.
1744 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) &&
1745 N->getNumValues() == 1) {
1746 SDValue N0 = N->getOperand(0);
1747 SDValue N1 = N->getOperand(1);
1748
1749 // Constant operands are canonicalized to RHS.
1750 if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
1751 SDValue Ops[] = {N1, N0};
1752 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1753 N->getFlags());
1754 if (CSENode)
1755 return SDValue(CSENode, 0);
1756 }
1757 }
1758
1759 return RV;
1760}
1761
1762/// Given a node, return its input chain if it has one, otherwise return a null
1763/// sd operand.
1764static SDValue getInputChainForNode(SDNode *N) {
1765 if (unsigned NumOps = N->getNumOperands()) {
1766 if (N->getOperand(0).getValueType() == MVT::Other)
1767 return N->getOperand(0);
1768 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1769 return N->getOperand(NumOps-1);
1770 for (unsigned i = 1; i < NumOps-1; ++i)
1771 if (N->getOperand(i).getValueType() == MVT::Other)
1772 return N->getOperand(i);
1773 }
1774 return SDValue();
1775}
1776
1777SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1778 // If N has two operands, where one has an input chain equal to the other,
1779 // the 'other' chain is redundant.
1780 if (N->getNumOperands() == 2) {
1781 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1782 return N->getOperand(0);
1783 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1784 return N->getOperand(1);
1785 }
1786
1787 // Don't simplify token factors if optnone.
1788 if (OptLevel == CodeGenOpt::None)
1789 return SDValue();
1790
1791 // If the sole user is a token factor, we should make sure we have a
1792 // chance to merge them together. This prevents TF chains from inhibiting
1793 // optimizations.
1794 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
1795 AddToWorklist(*(N->use_begin()));
1796
1797 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1798 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1799 SmallPtrSet<SDNode*, 16> SeenOps;
1800 bool Changed = false; // If we should replace this token factor.
1801
1802 // Start out with this token factor.
1803 TFs.push_back(N);
1804
1805 // Iterate through token factors. The TFs grows when new token factors are
1806 // encountered.
1807 for (unsigned i = 0; i < TFs.size(); ++i) {
1808 // Limit number of nodes to inline, to avoid quadratic compile times.
1809 // We have to add the outstanding Token Factors to Ops, otherwise we might
1810 // drop Ops from the resulting Token Factors.
1811 if (Ops.size() > TokenFactorInlineLimit) {
1812 for (unsigned j = i; j < TFs.size(); j++)
1813 Ops.emplace_back(TFs[j], 0);
1814 // Drop unprocessed Token Factors from TFs, so we do not add them to the
1815 // combiner worklist later.
1816 TFs.resize(i);
1817 break;
1818 }
1819
1820 SDNode *TF = TFs[i];
1821 // Check each of the operands.
1822 for (const SDValue &Op : TF->op_values()) {
1823 switch (Op.getOpcode()) {
1824 case ISD::EntryToken:
1825 // Entry tokens don't need to be added to the list. They are
1826 // redundant.
1827 Changed = true;
1828 break;
1829
1830 case ISD::TokenFactor:
1831 if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) {
1832 // Queue up for processing.
1833 TFs.push_back(Op.getNode());
1834 Changed = true;
1835 break;
1836 }
1837 LLVM_FALLTHROUGH[[clang::fallthrough]];
1838
1839 default:
1840 // Only add if it isn't already in the list.
1841 if (SeenOps.insert(Op.getNode()).second)
1842 Ops.push_back(Op);
1843 else
1844 Changed = true;
1845 break;
1846 }
1847 }
1848 }
1849
1850 // Re-visit inlined Token Factors, to clean them up in case they have been
1851 // removed. Skip the first Token Factor, as this is the current node.
1852 for (unsigned i = 1, e = TFs.size(); i < e; i++)
1853 AddToWorklist(TFs[i]);
1854
1855 // Remove Nodes that are chained to another node in the list. Do so
1856 // by walking up chains breath-first stopping when we've seen
1857 // another operand. In general we must climb to the EntryNode, but we can exit
1858 // early if we find all remaining work is associated with just one operand as
1859 // no further pruning is possible.
1860
1861 // List of nodes to search through and original Ops from which they originate.
1862 SmallVector<std::pair<SDNode *, unsigned>, 8> Worklist;
1863 SmallVector<unsigned, 8> OpWorkCount; // Count of work for each Op.
1864 SmallPtrSet<SDNode *, 16> SeenChains;
1865 bool DidPruneOps = false;
1866
1867 unsigned NumLeftToConsider = 0;
1868 for (const SDValue &Op : Ops) {
1869 Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++));
1870 OpWorkCount.push_back(1);
1871 }
1872
1873 auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) {
1874 // If this is an Op, we can remove the op from the list. Remark any
1875 // search associated with it as from the current OpNumber.
1876 if (SeenOps.count(Op) != 0) {
1877 Changed = true;
1878 DidPruneOps = true;
1879 unsigned OrigOpNumber = 0;
1880 while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op)
1881 OrigOpNumber++;
1882 assert((OrigOpNumber != Ops.size()) &&(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1883, __PRETTY_FUNCTION__))
1883 "expected to find TokenFactor Operand")(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1883, __PRETTY_FUNCTION__))
;
1884 // Re-mark worklist from OrigOpNumber to OpNumber
1885 for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) {
1886 if (Worklist[i].second == OrigOpNumber) {
1887 Worklist[i].second = OpNumber;
1888 }
1889 }
1890 OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber];
1891 OpWorkCount[OrigOpNumber] = 0;
1892 NumLeftToConsider--;
1893 }
1894 // Add if it's a new chain
1895 if (SeenChains.insert(Op).second) {
1896 OpWorkCount[OpNumber]++;
1897 Worklist.push_back(std::make_pair(Op, OpNumber));
1898 }
1899 };
1900
1901 for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) {
1902 // We need at least be consider at least 2 Ops to prune.
1903 if (NumLeftToConsider <= 1)
1904 break;
1905 auto CurNode = Worklist[i].first;
1906 auto CurOpNumber = Worklist[i].second;
1907 assert((OpWorkCount[CurOpNumber] > 0) &&(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1908, __PRETTY_FUNCTION__))
1908 "Node should not appear in worklist")(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1908, __PRETTY_FUNCTION__))
;
1909 switch (CurNode->getOpcode()) {
1910 case ISD::EntryToken:
1911 // Hitting EntryToken is the only way for the search to terminate without
1912 // hitting
1913 // another operand's search. Prevent us from marking this operand
1914 // considered.
1915 NumLeftToConsider++;
1916 break;
1917 case ISD::TokenFactor:
1918 for (const SDValue &Op : CurNode->op_values())
1919 AddToWorklist(i, Op.getNode(), CurOpNumber);
1920 break;
1921 case ISD::LIFETIME_START:
1922 case ISD::LIFETIME_END:
1923 case ISD::CopyFromReg:
1924 case ISD::CopyToReg:
1925 AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber);
1926 break;
1927 default:
1928 if (auto *MemNode = dyn_cast<MemSDNode>(CurNode))
1929 AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber);
1930 break;
1931 }
1932 OpWorkCount[CurOpNumber]--;
1933 if (OpWorkCount[CurOpNumber] == 0)
1934 NumLeftToConsider--;
1935 }
1936
1937 // If we've changed things around then replace token factor.
1938 if (Changed) {
1939 SDValue Result;
1940 if (Ops.empty()) {
1941 // The entry token is the only possible outcome.
1942 Result = DAG.getEntryNode();
1943 } else {
1944 if (DidPruneOps) {
1945 SmallVector<SDValue, 8> PrunedOps;
1946 //
1947 for (const SDValue &Op : Ops) {
1948 if (SeenChains.count(Op.getNode()) == 0)
1949 PrunedOps.push_back(Op);
1950 }
1951 Result = DAG.getTokenFactor(SDLoc(N), PrunedOps);
1952 } else {
1953 Result = DAG.getTokenFactor(SDLoc(N), Ops);
1954 }
1955 }
1956 return Result;
1957 }
1958 return SDValue();
1959}
1960
1961/// MERGE_VALUES can always be eliminated.
1962SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1963 WorklistRemover DeadNodes(*this);
1964 // Replacing results may cause a different MERGE_VALUES to suddenly
1965 // be CSE'd with N, and carry its uses with it. Iterate until no
1966 // uses remain, to ensure that the node can be safely deleted.
1967 // First add the users of this node to the work list so that they
1968 // can be tried again once they have new operands.
1969 AddUsersToWorklist(N);
1970 do {
1971 // Do as a single replacement to avoid rewalking use lists.
1972 SmallVector<SDValue, 8> Ops;
1973 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1974 Ops.push_back(N->getOperand(i));
1975 DAG.ReplaceAllUsesWith(N, Ops.data());
1976 } while (!N->use_empty());
1977 deleteAndRecombine(N);
1978 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1979}
1980
1981/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a
1982/// ConstantSDNode pointer else nullptr.
1983static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
1984 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
1985 return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
1986}
1987
1988SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
1989 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 &&((TLI.isBinOp(BO->getOpcode()) && BO->getNumValues
() == 1 && "Unexpected binary operator") ? static_cast
<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1990, __PRETTY_FUNCTION__))
1990 "Unexpected binary operator")((TLI.isBinOp(BO->getOpcode()) && BO->getNumValues
() == 1 && "Unexpected binary operator") ? static_cast
<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1990, __PRETTY_FUNCTION__))
;
1991
1992 // Don't do this unless the old select is going away. We want to eliminate the
1993 // binary operator, not replace a binop with a select.
1994 // TODO: Handle ISD::SELECT_CC.
1995 unsigned SelOpNo = 0;
1996 SDValue Sel = BO->getOperand(0);
1997 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
1998 SelOpNo = 1;
1999 Sel = BO->getOperand(1);
2000 }
2001
2002 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
2003 return SDValue();
2004
2005 SDValue CT = Sel.getOperand(1);
2006 if (!isConstantOrConstantVector(CT, true) &&
2007 !isConstantFPBuildVectorOrConstantFP(CT))
2008 return SDValue();
2009
2010 SDValue CF = Sel.getOperand(2);
2011 if (!isConstantOrConstantVector(CF, true) &&
2012 !isConstantFPBuildVectorOrConstantFP(CF))
2013 return SDValue();
2014
2015 // Bail out if any constants are opaque because we can't constant fold those.
2016 // The exception is "and" and "or" with either 0 or -1 in which case we can
2017 // propagate non constant operands into select. I.e.:
2018 // and (select Cond, 0, -1), X --> select Cond, 0, X
2019 // or X, (select Cond, -1, 0) --> select Cond, -1, X
2020 auto BinOpcode = BO->getOpcode();
2021 bool CanFoldNonConst =
2022 (BinOpcode == ISD::AND || BinOpcode == ISD::OR) &&
2023 (isNullOrNullSplat(CT) || isAllOnesOrAllOnesSplat(CT)) &&
2024 (isNullOrNullSplat(CF) || isAllOnesOrAllOnesSplat(CF));
2025
2026 SDValue CBO = BO->getOperand(SelOpNo ^ 1);
2027 if (!CanFoldNonConst &&
2028 !isConstantOrConstantVector(CBO, true) &&
2029 !isConstantFPBuildVectorOrConstantFP(CBO))
2030 return SDValue();
2031
2032 EVT VT = Sel.getValueType();
2033
2034 // In case of shift value and shift amount may have different VT. For instance
2035 // on x86 shift amount is i8 regardles of LHS type. Bail out if we have
2036 // swapped operands and value types do not match. NB: x86 is fine if operands
2037 // are not swapped with shift amount VT being not bigger than shifted value.
2038 // TODO: that is possible to check for a shift operation, correct VTs and
2039 // still perform optimization on x86 if needed.
2040 if (SelOpNo && VT != CBO.getValueType())
2041 return SDValue();
2042
2043 // We have a select-of-constants followed by a binary operator with a
2044 // constant. Eliminate the binop by pulling the constant math into the select.
2045 // Example: add (select Cond, CT, CF), CBO --> select Cond, CT + CBO, CF + CBO
2046 SDLoc DL(Sel);
2047 SDValue NewCT = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CT)
2048 : DAG.getNode(BinOpcode, DL, VT, CT, CBO);
2049 if (!CanFoldNonConst && !NewCT.isUndef() &&
2050 !isConstantOrConstantVector(NewCT, true) &&
2051 !isConstantFPBuildVectorOrConstantFP(NewCT))
2052 return SDValue();
2053
2054 SDValue NewCF = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CF)
2055 : DAG.getNode(BinOpcode, DL, VT, CF, CBO);
2056 if (!CanFoldNonConst && !NewCF.isUndef() &&
2057 !isConstantOrConstantVector(NewCF, true) &&
2058 !isConstantFPBuildVectorOrConstantFP(NewCF))
2059 return SDValue();
2060
2061 return DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF);
2062}
2063
2064static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) {
2065 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2066, __PRETTY_FUNCTION__))
2066 "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2066, __PRETTY_FUNCTION__))
;
2067
2068 // Match a constant operand and a zext operand for the math instruction:
2069 // add Z, C
2070 // sub C, Z
2071 bool IsAdd = N->getOpcode() == ISD::ADD;
2072 SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0);
2073 SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1);
2074 auto *CN = dyn_cast<ConstantSDNode>(C);
2075 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND)
2076 return SDValue();
2077
2078 // Match the zext operand as a setcc of a boolean.
2079 if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
2080 Z.getOperand(0).getValueType() != MVT::i1)
2081 return SDValue();
2082
2083 // Match the compare as: setcc (X & 1), 0, eq.
2084 SDValue SetCC = Z.getOperand(0);
2085 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
2086 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) ||
2087 SetCC.getOperand(0).getOpcode() != ISD::AND ||
2088 !isOneConstant(SetCC.getOperand(0).getOperand(1)))
2089 return SDValue();
2090
2091 // We are adding/subtracting a constant and an inverted low bit. Turn that
2092 // into a subtract/add of the low bit with incremented/decremented constant:
2093 // add (zext i1 (seteq (X & 1), 0)), C --> sub C+1, (zext (X & 1))
2094 // sub C, (zext i1 (seteq (X & 1), 0)) --> add C-1, (zext (X & 1))
2095 EVT VT = C.getValueType();
2096 SDLoc DL(N);
2097 SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT);
2098 SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) :
2099 DAG.getConstant(CN->getAPIntValue() - 1, DL, VT);
2100 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
2101}
2102
2103/// Try to fold a 'not' shifted sign-bit with add/sub with constant operand into
2104/// a shift and add with a different constant.
2105static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) {
2106 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2107, __PRETTY_FUNCTION__))
2107 "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2107, __PRETTY_FUNCTION__))
;
2108
2109 // We need a constant operand for the add/sub, and the other operand is a
2110 // logical shift right: add (srl), C or sub C, (srl).
2111 bool IsAdd = N->getOpcode() == ISD::ADD;
2112 SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0);
2113 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1);
2114 ConstantSDNode *C = isConstOrConstSplat(ConstantOp);
2115 if (!C || ShiftOp.getOpcode() != ISD::SRL)
2116 return SDValue();
2117
2118 // The shift must be of a 'not' value.
2119 SDValue Not = ShiftOp.getOperand(0);
2120 if (!Not.hasOneUse() || !isBitwiseNot(Not))
2121 return SDValue();
2122
2123 // The shift must be moving the sign bit to the least-significant-bit.
2124 EVT VT = ShiftOp.getValueType();
2125 SDValue ShAmt = ShiftOp.getOperand(1);
2126 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
2127 if (!ShAmtC || ShAmtC->getZExtValue() != VT.getScalarSizeInBits() - 1)
2128 return SDValue();
2129
2130 // Eliminate the 'not' by adjusting the shift and add/sub constant:
2131 // add (srl (not X), 31), C --> add (sra X, 31), (C + 1)
2132 // sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1)
2133 SDLoc DL(N);
2134 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
2135 SDValue NewShift = DAG.getNode(ShOpcode, DL, VT, Not.getOperand(0), ShAmt);
2136 APInt NewC = IsAdd ? C->getAPIntValue() + 1 : C->getAPIntValue() - 1;
2137 return DAG.getNode(ISD::ADD, DL, VT, NewShift, DAG.getConstant(NewC, DL, VT));
2138}
2139
2140/// Try to fold a node that behaves like an ADD (note that N isn't necessarily
2141/// an ISD::ADD here, it could for example be an ISD::OR if we know that there
2142/// are no common bits set in the operands).
2143SDValue DAGCombiner::visitADDLike(SDNode *N) {
2144 SDValue N0 = N->getOperand(0);
2145 SDValue N1 = N->getOperand(1);
2146 EVT VT = N0.getValueType();
2147 SDLoc DL(N);
2148
2149 // fold vector ops
2150 if (VT.isVector()) {
2151 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2152 return FoldedVOp;
2153
2154 // fold (add x, 0) -> x, vector edition
2155 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2156 return N0;
2157 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2158 return N1;
2159 }
2160
2161 // fold (add x, undef) -> undef
2162 if (N0.isUndef())
2163 return N0;
2164
2165 if (N1.isUndef())
2166 return N1;
2167
2168 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2169 // canonicalize constant to RHS
2170 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2171 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
2172 // fold (add c1, c2) -> c1+c2
2173 return DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, N0.getNode(),
2174 N1.getNode());
2175 }
2176
2177 // fold (add x, 0) -> x
2178 if (isNullConstant(N1))
2179 return N0;
2180
2181 if (isConstantOrConstantVector(N1, /* NoOpaque */ true)) {
2182 // fold ((A-c1)+c2) -> (A+(c2-c1))
2183 if (N0.getOpcode() == ISD::SUB &&
2184 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) {
2185 SDValue Sub = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N1.getNode(),
2186 N0.getOperand(1).getNode());
2187 assert(Sub && "Constant folding failed")((Sub && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("Sub && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2187, __PRETTY_FUNCTION__))
;
2188 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Sub);
2189 }
2190
2191 // fold ((c1-A)+c2) -> (c1+c2)-A
2192 if (N0.getOpcode() == ISD::SUB &&
2193 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaque */ true)) {
2194 SDValue Add = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, N1.getNode(),
2195 N0.getOperand(0).getNode());
2196 assert(Add && "Constant folding failed")((Add && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("Add && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2196, __PRETTY_FUNCTION__))
;
2197 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2198 }
2199
2200 // add (sext i1 X), 1 -> zext (not i1 X)
2201 // We don't transform this pattern:
2202 // add (zext i1 X), -1 -> sext (not i1 X)
2203 // because most (?) targets generate better code for the zext form.
2204 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2205 isOneOrOneSplat(N1)) {
2206 SDValue X = N0.getOperand(0);
2207 if ((!LegalOperations ||
2208 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) &&
2209 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) &&
2210 X.getScalarValueSizeInBits() == 1) {
2211 SDValue Not = DAG.getNOT(DL, X, X.getValueType());
2212 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not);
2213 }
2214 }
2215
2216 // Undo the add -> or combine to merge constant offsets from a frame index.
2217 if (N0.getOpcode() == ISD::OR &&
2218 isa<FrameIndexSDNode>(N0.getOperand(0)) &&
2219 isa<ConstantSDNode>(N0.getOperand(1)) &&
2220 DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) {
2221 SDValue Add0 = DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(1));
2222 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add0);
2223 }
2224 }
2225
2226 if (SDValue NewSel = foldBinOpIntoSelect(N))
2227 return NewSel;
2228
2229 // reassociate add
2230 if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
2231 return RADD;
2232
2233 // fold ((0-A) + B) -> B-A
2234 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0)))
2235 return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2236
2237 // fold (A + (0-B)) -> A-B
2238 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2239 return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1));
2240
2241 // fold (A+(B-A)) -> B
2242 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
2243 return N1.getOperand(0);
2244
2245 // fold ((B-A)+A) -> B
2246 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
2247 return N0.getOperand(0);
2248
2249 // fold ((A-B)+(C-A)) -> (C-B)
2250 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2251 N0.getOperand(0) == N1.getOperand(1))
2252 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2253 N0.getOperand(1));
2254
2255 // fold ((A-B)+(B-C)) -> (A-C)
2256 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2257 N0.getOperand(1) == N1.getOperand(0))
2258 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
2259 N1.getOperand(1));
2260
2261 // fold (A+(B-(A+C))) to (B-C)
2262 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2263 N0 == N1.getOperand(1).getOperand(0))
2264 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2265 N1.getOperand(1).getOperand(1));
2266
2267 // fold (A+(B-(C+A))) to (B-C)
2268 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2269 N0 == N1.getOperand(1).getOperand(1))
2270 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2271 N1.getOperand(1).getOperand(0));
2272
2273 // fold (A+((B-A)+or-C)) to (B+or-C)
2274 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
2275 N1.getOperand(0).getOpcode() == ISD::SUB &&
2276 N0 == N1.getOperand(0).getOperand(1))
2277 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0),
2278 N1.getOperand(1));
2279
2280 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
2281 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2282 SDValue N00 = N0.getOperand(0);
2283 SDValue N01 = N0.getOperand(1);
2284 SDValue N10 = N1.getOperand(0);
2285 SDValue N11 = N1.getOperand(1);
2286
2287 if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10))
2288 return DAG.getNode(ISD::SUB, DL, VT,
2289 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
2290 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
2291 }
2292
2293 // fold (add (umax X, C), -C) --> (usubsat X, C)
2294 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2295 auto MatchUSUBSAT = [](ConstantSDNode *Max, ConstantSDNode *Op) {
2296 return (!Max && !Op) ||
2297 (Max && Op && Max->getAPIntValue() == (-Op->getAPIntValue()));
2298 };
2299 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT,
2300 /*AllowUndefs*/ true))
2301 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
2302 N0.getOperand(1));
2303 }
2304
2305 if (SimplifyDemandedBits(SDValue(N, 0)))
2306 return SDValue(N, 0);
2307
2308 if (isOneOrOneSplat(N1)) {
2309 // fold (add (xor a, -1), 1) -> (sub 0, a)
2310 if (isBitwiseNot(N0))
2311 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
2312 N0.getOperand(0));
2313
2314 // fold (add (add (xor a, -1), b), 1) -> (sub b, a)
2315 if (N0.getOpcode() == ISD::ADD ||
2316 N0.getOpcode() == ISD::UADDO ||
2317 N0.getOpcode() == ISD::SADDO) {
2318 SDValue A, Xor;
2319
2320 if (isBitwiseNot(N0.getOperand(0))) {
2321 A = N0.getOperand(1);
2322 Xor = N0.getOperand(0);
2323 } else if (isBitwiseNot(N0.getOperand(1))) {
2324 A = N0.getOperand(0);
2325 Xor = N0.getOperand(1);
2326 }
2327
2328 if (Xor)
2329 return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0));
2330 }
2331 }
2332
2333 // (x - y) + -1 -> add (xor y, -1), x
2334 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2335 isAllOnesOrAllOnesSplat(N1)) {
2336 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1), N1);
2337 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
2338 }
2339
2340 if (SDValue Combined = visitADDLikeCommutative(N0, N1, N))
2341 return Combined;
2342
2343 if (SDValue Combined = visitADDLikeCommutative(N1, N0, N))
2344 return Combined;
2345
2346 return SDValue();
2347}
2348
2349SDValue DAGCombiner::visitADD(SDNode *N) {
2350 SDValue N0 = N->getOperand(0);
2351 SDValue N1 = N->getOperand(1);
2352 EVT VT = N0.getValueType();
2353 SDLoc DL(N);
2354
2355 if (SDValue Combined = visitADDLike(N))
2356 return Combined;
2357
2358 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
2359 return V;
2360
2361 if (SDValue V = foldAddSubOfSignBit(N, DAG))
2362 return V;
2363
2364 // fold (a+b) -> (a|b) iff a and b share no bits.
2365 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
2366 DAG.haveNoCommonBitsSet(N0, N1))
2367 return DAG.getNode(ISD::OR, DL, VT, N0, N1);
2368
2369 return SDValue();
2370}
2371
2372SDValue DAGCombiner::visitADDSAT(SDNode *N) {
2373 unsigned Opcode = N->getOpcode();
2374 SDValue N0 = N->getOperand(0);
2375 SDValue N1 = N->getOperand(1);
2376 EVT VT = N0.getValueType();
2377 SDLoc DL(N);
2378
2379 // fold vector ops
2380 if (VT.isVector()) {
2381 // TODO SimplifyVBinOp
2382
2383 // fold (add_sat x, 0) -> x, vector edition
2384 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2385 return N0;
2386 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2387 return N1;
2388 }
2389
2390 // fold (add_sat x, undef) -> -1
2391 if (N0.isUndef() || N1.isUndef())
2392 return DAG.getAllOnesConstant(DL, VT);
2393
2394 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2395 // canonicalize constant to RHS
2396 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2397 return DAG.getNode(Opcode, DL, VT, N1, N0);
2398 // fold (add_sat c1, c2) -> c3
2399 return DAG.FoldConstantArithmetic(Opcode, DL, VT, N0.getNode(),
2400 N1.getNode());
2401 }
2402
2403 // fold (add_sat x, 0) -> x
2404 if (isNullConstant(N1))
2405 return N0;
2406
2407 // If it cannot overflow, transform into an add.
2408 if (Opcode == ISD::UADDSAT)
2409 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2410 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
2411
2412 return SDValue();
2413}
2414
2415static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
2416 bool Masked = false;
2417
2418 // First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization.
2419 while (true) {
2420 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
2421 V = V.getOperand(0);
2422 continue;
2423 }
2424
2425 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
2426 Masked = true;
2427 V = V.getOperand(0);
2428 continue;
2429 }
2430
2431 break;
2432 }
2433
2434 // If this is not a carry, return.
2435 if (V.getResNo() != 1)
2436 return SDValue();
2437
2438 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
2439 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
2440 return SDValue();
2441
2442 EVT VT = V.getNode()->getValueType(0);
2443 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT))
2444 return SDValue();
2445
2446 // If the result is masked, then no matter what kind of bool it is we can
2447 // return. If it isn't, then we need to make sure the bool type is either 0 or
2448 // 1 and not other values.
2449 if (Masked ||
2450 TLI.getBooleanContents(V.getValueType()) ==
2451 TargetLoweringBase::ZeroOrOneBooleanContent)
2452 return V;
2453
2454 return SDValue();
2455}
2456
2457/// Given the operands of an add/sub operation, see if the 2nd operand is a
2458/// masked 0/1 whose source operand is actually known to be 0/-1. If so, invert
2459/// the opcode and bypass the mask operation.
2460static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1,
2461 SelectionDAG &DAG, const SDLoc &DL) {
2462 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
2463 return SDValue();
2464
2465 EVT VT = N0.getValueType();
2466 if (DAG.ComputeNumSignBits(N1.getOperand(0)) != VT.getScalarSizeInBits())
2467 return SDValue();
2468
2469 // add N0, (and (AssertSext X, i1), 1) --> sub N0, X
2470 // sub N0, (and (AssertSext X, i1), 1) --> add N0, X
2471 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N1.getOperand(0));
2472}
2473
2474/// Helper for doing combines based on N0 and N1 being added to each other.
2475SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
2476 SDNode *LocReference) {
2477 EVT VT = N0.getValueType();
2478 SDLoc DL(LocReference);
2479
2480 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
2481 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2482 isNullOrNullSplat(N1.getOperand(0).getOperand(0)))
2483 return DAG.getNode(ISD::SUB, DL, VT, N0,
2484 DAG.getNode(ISD::SHL, DL, VT,
2485 N1.getOperand(0).getOperand(1),
2486 N1.getOperand(1)));
2487
2488 if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL))
2489 return V;
2490
2491 // Hoist one-use subtraction by non-opaque constant:
2492 // (x - C) + y -> (x + y) - C
2493 // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
2494 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2495 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
2496 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), N1);
2497 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2498 }
2499 // Hoist one-use subtraction from non-opaque constant:
2500 // (C - x) + y -> (y - x) + C
2501 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2502 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
2503 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2504 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(0));
2505 }
2506
2507 // If the target's bool is represented as 0/1, prefer to make this 'sub 0/1'
2508 // rather than 'add 0/-1' (the zext should get folded).
2509 // add (sext i1 Y), X --> sub X, (zext i1 Y)
2510 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
2511 N0.getOperand(0).getScalarValueSizeInBits() == 1 &&
2512 TLI.getBooleanContents(VT) == TargetLowering::ZeroOrOneBooleanContent) {
2513 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
2514 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
2515 }
2516
2517 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
2518 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2519 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
2520 if (TN->getVT() == MVT::i1) {
2521 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
2522 DAG.getConstant(1, DL, VT));
2523 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
2524 }
2525 }
2526
2527 // (add X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2528 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
2529 N1.getResNo() == 0)
2530 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
2531 N0, N1.getOperand(0), N1.getOperand(2));
2532
2533 // (add X, Carry) -> (addcarry X, 0, Carry)
2534 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2535 if (SDValue Carry = getAsCarry(TLI, N1))
2536 return DAG.getNode(ISD::ADDCARRY, DL,
2537 DAG.getVTList(VT, Carry.getValueType()), N0,
2538 DAG.getConstant(0, DL, VT), Carry);
2539
2540 return SDValue();
2541}
2542
2543SDValue DAGCombiner::visitADDC(SDNode *N) {
2544 SDValue N0 = N->getOperand(0);
2545 SDValue N1 = N->getOperand(1);
2546 EVT VT = N0.getValueType();
2547 SDLoc DL(N);
2548
2549 // If the flag result is dead, turn this into an ADD.
2550 if (!N->hasAnyUseOfValue(1))
2551 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2552 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2553
2554 // canonicalize constant to RHS.
2555 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2556 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2557 if (N0C && !N1C)
2558 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
2559
2560 // fold (addc x, 0) -> x + no carry out
2561 if (isNullConstant(N1))
2562 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
2563 DL, MVT::Glue));
2564
2565 // If it cannot overflow, transform into an add.
2566 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2567 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2568 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2569
2570 return SDValue();
2571}
2572
2573static SDValue flipBoolean(SDValue V, const SDLoc &DL,
2574 SelectionDAG &DAG, const TargetLowering &TLI) {
2575 EVT VT = V.getValueType();
2576
2577 SDValue Cst;
2578 switch (TLI.getBooleanContents(VT)) {
2579 case TargetLowering::ZeroOrOneBooleanContent:
2580 case TargetLowering::UndefinedBooleanContent:
2581 Cst = DAG.getConstant(1, DL, VT);
2582 break;
2583 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2584 Cst = DAG.getConstant(-1, DL, VT);
2585 break;
2586 }
2587
2588 return DAG.getNode(ISD::XOR, DL, VT, V, Cst);
2589}
2590
2591static SDValue extractBooleanFlip(SDValue V, const TargetLowering &TLI) {
2592 if (V.getOpcode() != ISD::XOR)
2593 return SDValue();
2594
2595 ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
2596 if (!Const)
2597 return SDValue();
2598
2599 EVT VT = V.getValueType();
2600
2601 bool IsFlip = false;
2602 switch(TLI.getBooleanContents(VT)) {
2603 case TargetLowering::ZeroOrOneBooleanContent:
2604 IsFlip = Const->isOne();
2605 break;
2606 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2607 IsFlip = Const->isAllOnesValue();
2608 break;
2609 case TargetLowering::UndefinedBooleanContent:
2610 IsFlip = (Const->getAPIntValue() & 0x01) == 1;
2611 break;
2612 }
2613
2614 if (IsFlip)
2615 return V.getOperand(0);
2616 return SDValue();
2617}
2618
2619SDValue DAGCombiner::visitADDO(SDNode *N) {
2620 SDValue N0 = N->getOperand(0);
2621 SDValue N1 = N->getOperand(1);
2622 EVT VT = N0.getValueType();
2623 bool IsSigned = (ISD::SADDO == N->getOpcode());
2624
2625 EVT CarryVT = N->getValueType(1);
2626 SDLoc DL(N);
2627
2628 // If the flag result is dead, turn this into an ADD.
2629 if (!N->hasAnyUseOfValue(1))
2630 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2631 DAG.getUNDEF(CarryVT));
2632
2633 // canonicalize constant to RHS.
2634 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2635 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
2636 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
2637
2638 // fold (addo x, 0) -> x + no carry out
2639 if (isNullOrNullSplat(N1))
2640 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
2641
2642 if (!IsSigned) {
2643 // If it cannot overflow, transform into an add.
2644 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2645 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2646 DAG.getConstant(0, DL, CarryVT));
2647
2648 // fold (uaddo (xor a, -1), 1) -> (usub 0, a) and flip carry.
2649 if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) {
2650 SDValue Sub = DAG.getNode(ISD::USUBO, DL, N->getVTList(),
2651 DAG.getConstant(0, DL, VT), N0.getOperand(0));
2652 return CombineTo(N, Sub,
2653 flipBoolean(Sub.getValue(1), DL, DAG, TLI));
2654 }
2655
2656 if (SDValue Combined = visitUADDOLike(N0, N1, N))
2657 return Combined;
2658
2659 if (SDValue Combined = visitUADDOLike(N1, N0, N))
2660 return Combined;
2661 }
2662
2663 return SDValue();
2664}
2665
2666SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
2667 EVT VT = N0.getValueType();
2668 if (VT.isVector())
2669 return SDValue();
2670
2671 // (uaddo X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2672 // If Y + 1 cannot overflow.
2673 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
2674 SDValue Y = N1.getOperand(0);
2675 SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType());
2676 if (DAG.computeOverflowKind(Y, One) == SelectionDAG::OFK_Never)
2677 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
2678 N1.getOperand(2));
2679 }
2680
2681 // (uaddo X, Carry) -> (addcarry X, 0, Carry)
2682 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2683 if (SDValue Carry = getAsCarry(TLI, N1))
2684 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2685 DAG.getConstant(0, SDLoc(N), VT), Carry);
2686
2687 return SDValue();
2688}
2689
2690SDValue DAGCombiner::visitADDE(SDNode *N) {
2691 SDValue N0 = N->getOperand(0);
2692 SDValue N1 = N->getOperand(1);
2693 SDValue CarryIn = N->getOperand(2);
2694
2695 // canonicalize constant to RHS
2696 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2697 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2698 if (N0C && !N1C)
2699 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
2700 N1, N0, CarryIn);
2701
2702 // fold (adde x, y, false) -> (addc x, y)
2703 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2704 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
2705
2706 return SDValue();
2707}
2708
2709SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
2710 SDValue N0 = N->getOperand(0);
2711 SDValue N1 = N->getOperand(1);
2712 SDValue CarryIn = N->getOperand(2);
2713 SDLoc DL(N);
2714
2715 // canonicalize constant to RHS
2716 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2717 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2718 if (N0C && !N1C)
2719 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);
2720
2721 // fold (addcarry x, y, false) -> (uaddo x, y)
2722 if (isNullConstant(CarryIn)) {
2723 if (!LegalOperations ||
2724 TLI.isOperationLegalOrCustom(ISD::UADDO, N->getValueType(0)))
2725 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
2726 }
2727
2728 EVT CarryVT = CarryIn.getValueType();
2729
2730 // fold (addcarry 0, 0, X) -> (and (ext/trunc X), 1) and no carry.
2731 if (isNullConstant(N0) && isNullConstant(N1)) {
2732 EVT VT = N0.getValueType();
2733 SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT);
2734 AddToWorklist(CarryExt.getNode());
2735 return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,
2736 DAG.getConstant(1, DL, VT)),
2737 DAG.getConstant(0, DL, CarryVT));
2738 }
2739
2740 // fold (addcarry (xor a, -1), 0, !b) -> (subcarry 0, a, b) and flip carry.
2741 if (isBitwiseNot(N0) && isNullConstant(N1)) {
2742 if (SDValue B = extractBooleanFlip(CarryIn, TLI)) {
2743 SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(),
2744 DAG.getConstant(0, DL, N0.getValueType()),
2745 N0.getOperand(0), B);
2746 return CombineTo(N, Sub,
2747 flipBoolean(Sub.getValue(1), DL, DAG, TLI));
2748 }
2749 }
2750
2751 if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N))
2752 return Combined;
2753
2754 if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
2755 return Combined;
2756
2757 return SDValue();
2758}
2759
2760SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
2761 SDNode *N) {
2762 // Iff the flag result is dead:
2763 // (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
2764 if ((N0.getOpcode() == ISD::ADD ||
2765 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0)) &&
2766 isNullConstant(N1) && !N->hasAnyUseOfValue(1))
2767 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
2768 N0.getOperand(0), N0.getOperand(1), CarryIn);
2769
2770 /**
2771 * When one of the addcarry argument is itself a carry, we may be facing
2772 * a diamond carry propagation. In which case we try to transform the DAG
2773 * to ensure linear carry propagation if that is possible.
2774 *
2775 * We are trying to get:
2776 * (addcarry X, 0, (addcarry A, B, Z):Carry)
2777 */
2778 if (auto Y = getAsCarry(TLI, N1)) {
2779 /**
2780 * (uaddo A, B)
2781 * / \
2782 * Carry Sum
2783 * | \
2784 * | (addcarry *, 0, Z)
2785 * | /
2786 * \ Carry
2787 * | /
2788 * (addcarry X, *, *)
2789 */
2790 if (Y.getOpcode() == ISD::UADDO &&
2791 CarryIn.getResNo() == 1 &&
2792 CarryIn.getOpcode() == ISD::ADDCARRY &&
2793 isNullConstant(CarryIn.getOperand(1)) &&
2794 CarryIn.getOperand(0) == Y.getValue(0)) {
2795 auto NewY = DAG.getNode(ISD::ADDCARRY, SDLoc(N), Y->getVTList(),
2796 Y.getOperand(0), Y.getOperand(1),
2797 CarryIn.getOperand(2));
2798 AddToWorklist(NewY.getNode());
2799 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2800 DAG.getConstant(0, SDLoc(N), N0.getValueType()),
2801 NewY.getValue(1));
2802 }
2803 }
2804
2805 return SDValue();
2806}
2807
2808// Since it may not be valid to emit a fold to zero for vector initializers
2809// check if we can before folding.
2810static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
2811 SelectionDAG &DAG, bool LegalOperations) {
2812 if (!VT.isVector())
2813 return DAG.getConstant(0, DL, VT);
2814 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
2815 return DAG.getConstant(0, DL, VT);
2816 return SDValue();
2817}
2818
2819SDValue DAGCombiner::visitSUB(SDNode *N) {
2820 SDValue N0 = N->getOperand(0);
2821 SDValue N1 = N->getOperand(1);
2822 EVT VT = N0.getValueType();
2823 SDLoc DL(N);
2824
2825 // fold vector ops
2826 if (VT.isVector()) {
2827 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2828 return FoldedVOp;
2829
2830 // fold (sub x, 0) -> x, vector edition
2831 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2832 return N0;
2833 }
2834
2835 // fold (sub x, x) -> 0
2836 // FIXME: Refactor this and xor and other similar operations together.
2837 if (N0 == N1)
2838 return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
2839 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2840 DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
2841 // fold (sub c1, c2) -> c1-c2
2842 return DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(),
2843 N1.getNode());
2844 }
2845
2846 if (SDValue NewSel = foldBinOpIntoSelect(N))
2847 return NewSel;
2848
2849 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
2850
2851 // fold (sub x, c) -> (add x, -c)
2852 if (N1C) {
2853 return DAG.getNode(ISD::ADD, DL, VT, N0,
2854 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
2855 }
2856
2857 if (isNullOrNullSplat(N0)) {
2858 unsigned BitWidth = VT.getScalarSizeInBits();
2859 // Right-shifting everything out but the sign bit followed by negation is
2860 // the same as flipping arithmetic/logical shift type without the negation:
2861 // -(X >>u 31) -> (X >>s 31)
2862 // -(X >>s 31) -> (X >>u 31)
2863 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
2864 ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
2865 if (ShiftAmt && ShiftAmt->getZExtValue() == BitWidth - 1) {
2866 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
2867 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
2868 return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));
2869 }
2870 }
2871
2872 // 0 - X --> 0 if the sub is NUW.
2873 if (N->getFlags().hasNoUnsignedWrap())
2874 return N0;
2875
2876 if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) {
2877 // N1 is either 0 or the minimum signed value. If the sub is NSW, then
2878 // N1 must be 0 because negating the minimum signed value is undefined.
2879 if (N->getFlags().hasNoSignedWrap())
2880 return N0;
2881
2882 // 0 - X --> X if X is 0 or the minimum signed value.
2883 return N1;
2884 }
2885 }
2886
2887 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
2888 if (isAllOnesOrAllOnesSplat(N0))
2889 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
2890
2891 // fold (A - (0-B)) -> A+B
2892 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2893 return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1));
2894
2895 // fold A-(A-B) -> B
2896 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
2897 return N1.getOperand(1);
2898
2899 // fold (A+B)-A -> B
2900 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
2901 return N0.getOperand(1);
2902
2903 // fold (A+B)-B -> A
2904 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
2905 return N0.getOperand(0);
2906
2907 // fold (A+C1)-C2 -> A+(C1-C2)
2908 if (N0.getOpcode() == ISD::ADD &&
2909 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
2910 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
2911 SDValue NewC = DAG.FoldConstantArithmetic(
2912 ISD::SUB, DL, VT, N0.getOperand(1).getNode(), N1.getNode());
2913 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2913, __PRETTY_FUNCTION__))
;
2914 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
2915 }
2916
2917 // fold C2-(A+C1) -> (C2-C1)-A
2918 if (N1.getOpcode() == ISD::ADD) {
2919 SDValue N11 = N1.getOperand(1);
2920 if (isConstantOrConstantVector(N0, /* NoOpaques */ true) &&
2921 isConstantOrConstantVector(N11, /* NoOpaques */ true)) {
2922 SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(),
2923 N11.getNode());
2924 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2924, __PRETTY_FUNCTION__))
;
2925 return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
2926 }
2927 }
2928
2929 // fold (A-C1)-C2 -> A-(C1+C2)
2930 if (N0.getOpcode() == ISD::SUB &&
2931 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
2932 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
2933 SDValue NewC = DAG.FoldConstantArithmetic(
2934 ISD::ADD, DL, VT, N0.getOperand(1).getNode(), N1.getNode());
2935 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2935, __PRETTY_FUNCTION__))
;
2936 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC);
2937 }
2938
2939 // fold (c1-A)-c2 -> (c1-c2)-A
2940 if (N0.getOpcode() == ISD::SUB &&
2941 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
2942 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaques */ true)) {
2943 SDValue NewC = DAG.FoldConstantArithmetic(
2944 ISD::SUB, DL, VT, N0.getOperand(0).getNode(), N1.getNode());
2945 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2945, __PRETTY_FUNCTION__))
;
2946 return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1));
2947 }
2948
2949 // fold ((A+(B+or-C))-B) -> A+or-C
2950 if (N0.getOpcode() == ISD::ADD &&
2951 (N0.getOperand(1).getOpcode() == ISD::SUB ||
2952 N0.getOperand(1).getOpcode() == ISD::ADD) &&
2953 N0.getOperand(1).getOperand(0) == N1)
2954 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0),
2955 N0.getOperand(1).getOperand(1));
2956
2957 // fold ((A+(C+B))-B) -> A+C
2958 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD &&
2959 N0.getOperand(1).getOperand(1) == N1)
2960 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0),
2961 N0.getOperand(1).getOperand(0));
2962
2963 // fold ((A-(B-C))-C) -> A-B
2964 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
2965 N0.getOperand(1).getOperand(1) == N1)
2966 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
2967 N0.getOperand(1).getOperand(0));
2968
2969 // fold (A-(B-C)) -> A+(C-B)
2970 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse())
2971 return DAG.getNode(ISD::ADD, DL, VT, N0,
2972 DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1),
2973 N1.getOperand(0)));
2974
2975 // fold (X - (-Y * Z)) -> (X + (Y * Z))
2976 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) {
2977 if (N1.getOperand(0).getOpcode() == ISD::SUB &&
2978 isNullOrNullSplat(N1.getOperand(0).getOperand(0))) {
2979 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
2980 N1.getOperand(0).getOperand(1),
2981 N1.getOperand(1));
2982 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
2983 }
2984 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
2985 isNullOrNullSplat(N1.getOperand(1).getOperand(0))) {
2986 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
2987 N1.getOperand(0),
2988 N1.getOperand(1).getOperand(1));
2989 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
2990 }
2991 }
2992
2993 // If either operand of a sub is undef, the result is undef
2994 if (N0.isUndef())
2995 return N0;
2996 if (N1.isUndef())
2997 return N1;
2998
2999 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
3000 return V;
3001
3002 if (SDValue V = foldAddSubOfSignBit(N, DAG))
3003 return V;
3004
3005 if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
3006 return V;
3007
3008 // (x - y) - 1 -> add (xor y, -1), x
3009 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) {
3010 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
3011 DAG.getAllOnesConstant(DL, VT));
3012 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
3013 }
3014
3015 // Hoist one-use addition by non-opaque constant:
3016 // (x + C) - y -> (x - y) + C
3017 if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD &&
3018 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3019 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3020 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
3021 }
3022 // y - (x + C) -> (y - x) - C
3023 if (N1.hasOneUse() && N1.getOpcode() == ISD::ADD &&
3024 isConstantOrConstantVector(N1.getOperand(1), /*NoOpaques=*/true)) {
3025 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
3026 return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1));
3027 }
3028 // (x - C) - y -> (x - y) - C
3029 // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
3030 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3031 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3032 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3033 return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
3034 }
3035 // (C - x) - y -> C - (x + y)
3036 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3037 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
3038 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1);
3039 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
3040 }
3041
3042 // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
3043 // rather than 'sub 0/1' (the sext should get folded).
3044 // sub X, (zext i1 Y) --> add X, (sext i1 Y)
3045 if (N1.getOpcode() == ISD::ZERO_EXTEND &&
3046 N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
3047 TLI.getBooleanContents(VT) ==
3048 TargetLowering::ZeroOrNegativeOneBooleanContent) {
3049 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
3050 return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
3051 }
3052
3053 // fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X)
3054 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
3055 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
3056 SDValue X0 = N0.getOperand(0), X1 = N0.getOperand(1);
3057 SDValue S0 = N1.getOperand(0);
3058 if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) {
3059 unsigned OpSizeInBits = VT.getScalarSizeInBits();
3060 if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1)))
3061 if (C->getAPIntValue() == (OpSizeInBits - 1))
3062 return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0);
3063 }
3064 }
3065 }
3066
3067 // If the relocation model supports it, consider symbol offsets.
3068 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
3069 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
3070 // fold (sub Sym, c) -> Sym-c
3071 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
3072 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
3073 GA->getOffset() -
3074 (uint64_t)N1C->getSExtValue());
3075 // fold (sub Sym+c1, Sym+c2) -> c1-c2
3076 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
3077 if (GA->getGlobal() == GB->getGlobal())
3078 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
3079 DL, VT);
3080 }
3081
3082 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
3083 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
3084 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
3085 if (TN->getVT() == MVT::i1) {
3086 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
3087 DAG.getConstant(1, DL, VT));
3088 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
3089 }
3090 }
3091
3092 // Prefer an add for more folding potential and possibly better codegen:
3093 // sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1)
3094 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
3095 SDValue ShAmt = N1.getOperand(1);
3096 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
3097 if (ShAmtC && ShAmtC->getZExtValue() == N1.getScalarValueSizeInBits() - 1) {
3098 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
3099 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
3100 }
3101 }
3102
3103 return SDValue();
3104}
3105
3106SDValue DAGCombiner::visitSUBSAT(SDNode *N) {
3107 SDValue N0 = N->getOperand(0);
3108 SDValue N1 = N->getOperand(1);
3109 EVT VT = N0.getValueType();
3110 SDLoc DL(N);
3111
3112 // fold vector ops
3113 if (VT.isVector()) {
3114 // TODO SimplifyVBinOp
3115
3116 // fold (sub_sat x, 0) -> x, vector edition
3117 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3118 return N0;
3119 }
3120
3121 // fold (sub_sat x, undef) -> 0
3122 if (N0.isUndef() || N1.isUndef())
3123 return DAG.getConstant(0, DL, VT);
3124
3125 // fold (sub_sat x, x) -> 0
3126 if (N0 == N1)
3127 return DAG.getConstant(0, DL, VT);
3128
3129 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3130 DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
3131 // fold (sub_sat c1, c2) -> c3
3132 return DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, N0.getNode(),
3133 N1.getNode());
3134 }
3135
3136 // fold (sub_sat x, 0) -> x
3137 if (isNullConstant(N1))
3138 return N0;
3139
3140 return SDValue();
3141}
3142
3143SDValue DAGCombiner::visitSUBC(SDNode *N) {
3144 SDValue N0 = N->getOperand(0);
3145 SDValue N1 = N->getOperand(1);
3146 EVT VT = N0.getValueType();
3147 SDLoc DL(N);
3148
3149 // If the flag result is dead, turn this into an SUB.
3150 if (!N->hasAnyUseOfValue(1))
3151 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3152 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3153
3154 // fold (subc x, x) -> 0 + no borrow
3155 if (N0 == N1)
3156 return CombineTo(N, DAG.getConstant(0, DL, VT),
3157 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3158
3159 // fold (subc x, 0) -> x + no borrow
3160 if (isNullConstant(N1))
3161 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3162
3163 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3164 if (isAllOnesConstant(N0))
3165 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3166 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3167
3168 return SDValue();
3169}
3170
3171SDValue DAGCombiner::visitSUBO(SDNode *N) {
3172 SDValue N0 = N->getOperand(0);
3173 SDValue N1 = N->getOperand(1);
3174 EVT VT = N0.getValueType();
3175 bool IsSigned = (ISD::SSUBO == N->getOpcode());
3176
3177 EVT CarryVT = N->getValueType(1);
3178 SDLoc DL(N);
3179
3180 // If the flag result is dead, turn this into an SUB.
3181 if (!N->hasAnyUseOfValue(1))
3182 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3183 DAG.getUNDEF(CarryVT));
3184
3185 // fold (subo x, x) -> 0 + no borrow
3186 if (N0 == N1)
3187 return CombineTo(N, DAG.getConstant(0, DL, VT),
3188 DAG.getConstant(0, DL, CarryVT));
3189
3190 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3191
3192 // fold (subox, c) -> (addo x, -c)
3193 if (IsSigned && N1C && !N1C->getAPIntValue().isMinSignedValue()) {
3194 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0,
3195 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
3196 }
3197
3198 // fold (subo x, 0) -> x + no borrow
3199 if (isNullOrNullSplat(N1))
3200 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
3201
3202 // Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3203 if (!IsSigned && isAllOnesOrAllOnesSplat(N0))
3204 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3205 DAG.getConstant(0, DL, CarryVT));
3206
3207 return SDValue();
3208}
3209
3210SDValue DAGCombiner::visitSUBE(SDNode *N) {
3211 SDValue N0 = N->getOperand(0);
3212 SDValue N1 = N->getOperand(1);
3213 SDValue CarryIn = N->getOperand(2);
3214
3215 // fold (sube x, y, false) -> (subc x, y)
3216 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
3217 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
3218
3219 return SDValue();
3220}
3221
3222SDValue DAGCombiner::visitSUBCARRY(SDNode *N) {
3223 SDValue N0 = N->getOperand(0);
3224 SDValue N1 = N->getOperand(1);
3225 SDValue CarryIn = N->getOperand(2);
3226
3227 // fold (subcarry x, y, false) -> (usubo x, y)
3228 if (isNullConstant(CarryIn)) {
3229 if (!LegalOperations ||
3230 TLI.isOperationLegalOrCustom(ISD::USUBO, N->getValueType(0)))
3231 return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
3232 }
3233
3234 return SDValue();
3235}
3236
3237SDValue DAGCombiner::visitMUL(SDNode *N) {
3238 SDValue N0 = N->getOperand(0);
3239 SDValue N1 = N->getOperand(1);
3240 EVT VT = N0.getValueType();
3241
3242 // fold (mul x, undef) -> 0
3243 if (N0.isUndef() || N1.isUndef())
3244 return DAG.getConstant(0, SDLoc(N), VT);
3245
3246 bool N0IsConst = false;
3247 bool N1IsConst = false;
3248 bool N1IsOpaqueConst = false;
3249 bool N0IsOpaqueConst = false;
3250 APInt ConstValue0, ConstValue1;
3251 // fold vector ops
3252 if (VT.isVector()) {
3253 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3254 return FoldedVOp;
3255
3256 N0IsConst = ISD::isConstantSplatVector(N0.getNode(), ConstValue0);
3257 N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1);
3258 assert((!N0IsConst ||(((!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3260, __PRETTY_FUNCTION__))
3259 ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) &&(((!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3260, __PRETTY_FUNCTION__))
3260 "Splat APInt should be element width")(((!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3260, __PRETTY_FUNCTION__))
;
3261 assert((!N1IsConst ||(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3263, __PRETTY_FUNCTION__))
3262 ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) &&(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3263, __PRETTY_FUNCTION__))
3263 "Splat APInt should be element width")(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3263, __PRETTY_FUNCTION__))
;
3264 } else {
3265 N0IsConst = isa<ConstantSDNode>(N0);
3266 if (N0IsConst) {
3267 ConstValue0 = cast<ConstantSDNode>(N0)->getAPIntValue();
3268 N0IsOpaqueConst = cast<ConstantSDNode>(N0)->isOpaque();
3269 }
3270 N1IsConst = isa<ConstantSDNode>(N1);
3271 if (N1IsConst) {
3272 ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
3273 N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
3274 }
3275 }
3276
3277 // fold (mul c1, c2) -> c1*c2
3278 if (N0IsConst && N1IsConst && !N0IsOpaqueConst && !N1IsOpaqueConst)
3279 return DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT,
3280 N0.getNode(), N1.getNode());
3281
3282 // canonicalize constant to RHS (vector doesn't have to splat)
3283 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3284 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3285 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
3286 // fold (mul x, 0) -> 0
3287 if (N1IsConst && ConstValue1.isNullValue())
3288 return N1;
3289 // fold (mul x, 1) -> x
3290 if (N1IsConst && ConstValue1.isOneValue())
3291 return N0;
3292
3293 if (SDValue NewSel = foldBinOpIntoSelect(N))
3294 return NewSel;
3295
3296 // fold (mul x, -1) -> 0-x
3297 if (N1IsConst && ConstValue1.isAllOnesValue()) {
3298 SDLoc DL(N);
3299 return DAG.getNode(ISD::SUB, DL, VT,
3300 DAG.getConstant(0, DL, VT), N0);
3301 }
3302 // fold (mul x, (1 << c)) -> x << c
3303 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3304 DAG.isKnownToBeAPowerOfTwo(N1) &&
3305 (!VT.isVector() || Level <= AfterLegalizeVectorOps)) {
3306 SDLoc DL(N);
3307 SDValue LogBase2 = BuildLogBase2(N1, DL);
3308 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3309 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
3310 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
3311 }
3312 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
3313 if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2()) {
3314 unsigned Log2Val = (-ConstValue1).logBase2();
3315 SDLoc DL(N);
3316 // FIXME: If the input is something that is easily negated (e.g. a
3317 // single-use add), we should put the negate there.
3318 return DAG.getNode(ISD::SUB, DL, VT,
3319 DAG.getConstant(0, DL, VT),
3320 DAG.getNode(ISD::SHL, DL, VT, N0,
3321 DAG.getConstant(Log2Val, DL,
3322 getShiftAmountTy(N0.getValueType()))));
3323 }
3324
3325 // Try to transform multiply-by-(power-of-2 +/- 1) into shift and add/sub.
3326 // mul x, (2^N + 1) --> add (shl x, N), x
3327 // mul x, (2^N - 1) --> sub (shl x, N), x
3328 // Examples: x * 33 --> (x << 5) + x
3329 // x * 15 --> (x << 4) - x
3330 // x * -33 --> -((x << 5) + x)
3331 // x * -15 --> -((x << 4) - x) ; this reduces --> x - (x << 4)
3332 if (N1IsConst && TLI.decomposeMulByConstant(VT, N1)) {
3333 // TODO: We could handle more general decomposition of any constant by
3334 // having the target set a limit on number of ops and making a
3335 // callback to determine that sequence (similar to sqrt expansion).
3336 unsigned MathOp = ISD::DELETED_NODE;
3337 APInt MulC = ConstValue1.abs();
3338 if ((MulC - 1).isPowerOf2())
3339 MathOp = ISD::ADD;
3340 else if ((MulC + 1).isPowerOf2())
3341 MathOp = ISD::SUB;
3342
3343 if (MathOp != ISD::DELETED_NODE) {
3344 unsigned ShAmt = MathOp == ISD::ADD ? (MulC - 1).logBase2()
3345 : (MulC + 1).logBase2();
3346 assert(ShAmt > 0 && ShAmt < VT.getScalarSizeInBits() &&((ShAmt > 0 && ShAmt < VT.getScalarSizeInBits()
&& "Not expecting multiply-by-constant that could have simplified"
) ? static_cast<void> (0) : __assert_fail ("ShAmt > 0 && ShAmt < VT.getScalarSizeInBits() && \"Not expecting multiply-by-constant that could have simplified\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3347, __PRETTY_FUNCTION__))
3347 "Not expecting multiply-by-constant that could have simplified")((ShAmt > 0 && ShAmt < VT.getScalarSizeInBits()
&& "Not expecting multiply-by-constant that could have simplified"
) ? static_cast<void> (0) : __assert_fail ("ShAmt > 0 && ShAmt < VT.getScalarSizeInBits() && \"Not expecting multiply-by-constant that could have simplified\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3347, __PRETTY_FUNCTION__))
;
3348 SDLoc DL(N);
3349 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, N0,
3350 DAG.getConstant(ShAmt, DL, VT));
3351 SDValue R = DAG.getNode(MathOp, DL, VT, Shl, N0);
3352 if (ConstValue1.isNegative())
3353 R = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), R);
3354 return R;
3355 }
3356 }
3357
3358 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
3359 if (N0.getOpcode() == ISD::SHL &&
3360 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3361 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3362 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
3363 if (isConstantOrConstantVector(C3))
3364 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
3365 }
3366
3367 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
3368 // use.
3369 {
3370 SDValue Sh(nullptr, 0), Y(nullptr, 0);
3371
3372 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
3373 if (N0.getOpcode() == ISD::SHL &&
3374 isConstantOrConstantVector(N0.getOperand(1)) &&
3375 N0.getNode()->hasOneUse()) {
3376 Sh = N0; Y = N1;
3377 } else if (N1.getOpcode() == ISD::SHL &&
3378 isConstantOrConstantVector(N1.getOperand(1)) &&
3379 N1.getNode()->hasOneUse()) {
3380 Sh = N1; Y = N0;
3381 }
3382
3383 if (Sh.getNode()) {
3384 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, Sh.getOperand(0), Y);
3385 return DAG.getNode(ISD::SHL, SDLoc(N), VT, Mul, Sh.getOperand(1));
3386 }
3387 }
3388
3389 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
3390 if (DAG.isConstantIntBuildVectorOrConstantInt(N1) &&
3391 N0.getOpcode() == ISD::ADD &&
3392 DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
3393 isMulAddWithConstProfitable(N, N0, N1))
3394 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
3395 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
3396 N0.getOperand(0), N1),
3397 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
3398 N0.getOperand(1), N1));
3399
3400 // reassociate mul
3401 if (SDValue RMUL = reassociateOps(ISD::MUL, SDLoc(N), N0, N1, N->getFlags()))
3402 return RMUL;
3403
3404 return SDValue();
3405}
3406
3407/// Return true if divmod libcall is available.
3408static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
3409 const TargetLowering &TLI) {
3410 RTLIB::Libcall LC;
3411 EVT NodeType = Node->getValueType(0);
3412 if (!NodeType.isSimple())
3413 return false;
3414 switch (NodeType.getSimpleVT().SimpleTy) {
3415 default: return false; // No libcall for vector types.
3416 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
3417 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
3418 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
3419 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
3420 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
3421 }
3422
3423 return TLI.getLibcallName(LC) != nullptr;
3424}
3425
3426/// Issue divrem if both quotient and remainder are needed.
3427SDValue DAGCombiner::useDivRem(SDNode *Node) {
3428 if (Node->use_empty())
3429 return SDValue(); // This is a dead node, leave it alone.
3430
3431 unsigned Opcode = Node->getOpcode();
3432 bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
3433 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3434
3435 // DivMod lib calls can still work on non-legal types if using lib-calls.
3436 EVT VT = Node->getValueType(0);
3437 if (VT.isVector() || !VT.isInteger())
3438 return SDValue();
3439
3440 if (!TLI.isTypeLegal(VT) && !TLI.isOperationCustom(DivRemOpc, VT))
3441 return SDValue();
3442
3443 // If DIVREM is going to get expanded into a libcall,
3444 // but there is no libcall available, then don't combine.
3445 if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) &&
3446 !isDivRemLibcallAvailable(Node, isSigned, TLI))
3447 return SDValue();
3448
3449 // If div is legal, it's better to do the normal expansion
3450 unsigned OtherOpcode = 0;
3451 if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
3452 OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
3453 if (TLI.isOperationLegalOrCustom(Opcode, VT))
3454 return SDValue();
3455 } else {
3456 OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
3457 if (TLI.isOperationLegalOrCustom(OtherOpcode, VT))
3458 return SDValue();
3459 }
3460
3461 SDValue Op0 = Node->getOperand(0);
3462 SDValue Op1 = Node->getOperand(1);
3463 SDValue combined;
3464 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
3465 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
3466 SDNode *User = *UI;
3467 if (User == Node || User->getOpcode() == ISD::DELETED_NODE ||
3468 User->use_empty())
3469 continue;
3470 // Convert the other matching node(s), too;
3471 // otherwise, the DIVREM may get target-legalized into something
3472 // target-specific that we won't be able to recognize.
3473 unsigned UserOpc = User->getOpcode();
3474 if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) &&
3475 User->getOperand(0) == Op0 &&
3476 User->getOperand(1) == Op1) {
3477 if (!combined) {
3478 if (UserOpc == OtherOpcode) {
3479 SDVTList VTs = DAG.getVTList(VT, VT);
3480 combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1);
3481 } else if (UserOpc == DivRemOpc) {
3482 combined = SDValue(User, 0);
3483 } else {
3484 assert(UserOpc == Opcode)((UserOpc == Opcode) ? static_cast<void> (0) : __assert_fail
("UserOpc == Opcode", "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3484, __PRETTY_FUNCTION__))
;
3485 continue;
3486 }
3487 }
3488 if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
3489 CombineTo(User, combined);
3490 else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
3491 CombineTo(User, combined.getValue(1));
3492 }
3493 }
3494 return combined;
3495}
3496
3497static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) {
3498 SDValue N0 = N->getOperand(0);
3499 SDValue N1 = N->getOperand(1);
3500 EVT VT = N->getValueType(0);
3501 SDLoc DL(N);
3502
3503 unsigned Opc = N->getOpcode();
3504 bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc);
3505 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3506
3507 // X / undef -> undef
3508 // X % undef -> undef
3509 // X / 0 -> undef
3510 // X % 0 -> undef
3511 // NOTE: This includes vectors where any divisor element is zero/undef.
3512 if (DAG.isUndef(Opc, {N0, N1}))
3513 return DAG.getUNDEF(VT);
3514
3515 // undef / X -> 0
3516 // undef % X -> 0
3517 if (N0.isUndef())
3518 return DAG.getConstant(0, DL, VT);
3519
3520 // 0 / X -> 0
3521 // 0 % X -> 0
3522 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3523 if (N0C && N0C->isNullValue())
3524 return N0;
3525
3526 // X / X -> 1
3527 // X % X -> 0
3528 if (N0 == N1)
3529 return DAG.getConstant(IsDiv ? 1 : 0, DL, VT);
3530
3531 // X / 1 -> X
3532 // X % 1 -> 0
3533 // If this is a boolean op (single-bit element type), we can't have
3534 // division-by-zero or remainder-by-zero, so assume the divisor is 1.
3535 // TODO: Similarly, if we're zero-extending a boolean divisor, then assume
3536 // it's a 1.
3537 if ((N1C && N1C->isOne()) || (VT.getScalarType() == MVT::i1))
3538 return IsDiv ? N0 : DAG.getConstant(0, DL, VT);
3539
3540 return SDValue();
3541}
3542
3543SDValue DAGCombiner::visitSDIV(SDNode *N) {
3544 SDValue N0 = N->getOperand(0);
3545 SDValue N1 = N->getOperand(1);
3546 EVT VT = N->getValueType(0);
3547 EVT CCVT = getSetCCResultType(VT);
3548
3549 // fold vector ops
3550 if (VT.isVector())
3551 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3552 return FoldedVOp;
3553
3554 SDLoc DL(N);
3555
3556 // fold (sdiv c1, c2) -> c1/c2
3557 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3558 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3559 if (N0C && N1C && !N0C->isOpaque() && !N1C->isOpaque())
3560 return DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, N0C, N1C);
3561 // fold (sdiv X, -1) -> 0-X
3562 if (N1C && N1C->isAllOnesValue())
3563 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
3564 // fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0)
3565 if (N1C && N1C->getAPIntValue().isMinSignedValue())
3566 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
3567 DAG.getConstant(1, DL, VT),
3568 DAG.getConstant(0, DL, VT));
3569
3570 if (SDValue V = simplifyDivRem(N, DAG))
3571 return V;
3572
3573 if (SDValue NewSel = foldBinOpIntoSelect(N))
3574 return NewSel;
3575
3576 // If we know the sign bits of both operands are zero, strength reduce to a
3577 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
3578 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
3579 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
3580
3581 if (SDValue V = visitSDIVLike(N0, N1, N)) {
3582 // If the corresponding remainder node exists, update its users with
3583 // (Dividend - (Quotient * Divisor).
3584 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(),
3585 { N0, N1 })) {
3586 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
3587 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3588 AddToWorklist(Mul.getNode());
3589 AddToWorklist(Sub.getNode());
3590 CombineTo(RemNode, Sub);
3591 }
3592 return V;
3593 }
3594
3595 // sdiv, srem -> sdivrem
3596 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
3597 // true. Otherwise, we break the simplification logic in visitREM().
3598 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3599 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
3600 if (SDValue DivRem = useDivRem(N))
3601 return DivRem;
3602
3603 return SDValue();
3604}
3605
3606SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
3607 SDLoc DL(N);
3608 EVT VT = N->getValueType(0);
3609 EVT CCVT = getSetCCResultType(VT);
3610 unsigned BitWidth = VT.getScalarSizeInBits();
3611
3612 // Helper for determining whether a value is a power-2 constant scalar or a
3613 // vector of such elements.
3614 auto IsPowerOfTwo = [](ConstantSDNode *C) {
3615 if (C->isNullValue() || C->isOpaque())
3616 return false;
3617 if (C->getAPIntValue().isPowerOf2())
3618 return true;
3619 if ((-C->getAPIntValue()).isPowerOf2())
3620 return true;
3621 return false;
3622 };
3623
3624 // fold (sdiv X, pow2) -> simple ops after legalize
3625 // FIXME: We check for the exact bit here because the generic lowering gives
3626 // better results in that case. The target-specific lowering should learn how
3627 // to handle exact sdivs efficiently.
3628 if (!N->getFlags().hasExact() && ISD::matchUnaryPredicate(N1, IsPowerOfTwo)) {
3629 // Target-specific implementation of sdiv x, pow2.
3630 if (SDValue Res = BuildSDIVPow2(N))
3631 return Res;
3632
3633 // Create constants that are functions of the shift amount value.
3634 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
3635 SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy);
3636 SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1);
3637 C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy);
3638 SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1);
3639 if (!isConstantOrConstantVector(Inexact))
3640 return SDValue();
3641
3642 // Splat the sign bit into the register
3643 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
3644 DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy));
3645 AddToWorklist(Sign.getNode());
3646
3647 // Add (N0 < 0) ? abs2 - 1 : 0;
3648 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
3649 AddToWorklist(Srl.getNode());
3650 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl);
3651 AddToWorklist(Add.getNode());
3652 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);
3653 AddToWorklist(Sra.getNode());
3654
3655 // Special case: (sdiv X, 1) -> X
3656 // Special Case: (sdiv X, -1) -> 0-X
3657 SDValue One = DAG.getConstant(1, DL, VT);
3658 SDValue AllOnes = DAG.getAllOnesConstant(DL, VT);
3659 SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ);
3660 SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ);
3661 SDValue IsOneOrAllOnes = DAG.getNode(ISD::OR, DL, CCVT, IsOne, IsAllOnes);
3662 Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra);
3663
3664 // If dividing by a positive value, we're done. Otherwise, the result must
3665 // be negated.
3666 SDValue Zero = DAG.getConstant(0, DL, VT);
3667 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra);
3668
3669 // FIXME: Use SELECT_CC once we improve SELECT_CC constant-folding.
3670 SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT);
3671 SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra);
3672 return Res;
3673 }
3674
3675 // If integer divide is expensive and we satisfy the requirements, emit an
3676 // alternate sequence. Targets may check function attributes for size/speed
3677 // trade-offs.
3678 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3679 if (isConstantOrConstantVector(N1) &&
3680 !TLI.isIntDivCheap(N->getValueType(0), Attr))
3681 if (SDValue Op = BuildSDIV(N))
3682 return Op;
3683
3684 return SDValue();
3685}
3686
3687SDValue DAGCombiner::visitUDIV(SDNode *N) {
3688 SDValue N0 = N->getOperand(0);
3689 SDValue N1 = N->getOperand(1);
3690 EVT VT = N->getValueType(0);
3691 EVT CCVT = getSetCCResultType(VT);
3692
3693 // fold vector ops
3694 if (VT.isVector())
3695 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3696 return FoldedVOp;
3697
3698 SDLoc DL(N);
3699
3700 // fold (udiv c1, c2) -> c1/c2
3701 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3702 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3703 if (N0C && N1C)
3704 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT,
3705 N0C, N1C))
3706 return Folded;
3707 // fold (udiv X, -1) -> select(X == -1, 1, 0)
3708 if (N1C && N1C->getAPIntValue().isAllOnesValue())
3709 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
3710 DAG.getConstant(1, DL, VT),
3711 DAG.getConstant(0, DL, VT));
3712
3713 if (SDValue V = simplifyDivRem(N, DAG))
3714 return V;
3715
3716 if (SDValue NewSel = foldBinOpIntoSelect(N))
3717 return NewSel;
3718
3719 if (SDValue V = visitUDIVLike(N0, N1, N)) {
3720 // If the corresponding remainder node exists, update its users with
3721 // (Dividend - (Quotient * Divisor).
3722 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(),
3723 { N0, N1 })) {
3724 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
3725 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3726 AddToWorklist(Mul.getNode());
3727 AddToWorklist(Sub.getNode());
3728 CombineTo(RemNode, Sub);
3729 }
3730 return V;
3731 }
3732
3733 // sdiv, srem -> sdivrem
3734 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
3735 // true. Otherwise, we break the simplification logic in visitREM().
3736 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3737 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
3738 if (SDValue DivRem = useDivRem(N))
3739 return DivRem;
3740
3741 return SDValue();
3742}
3743
3744SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) {
3745 SDLoc DL(N);
3746 EVT VT = N->getValueType(0);
3747
3748 // fold (udiv x, (1 << c)) -> x >>u c
3749 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3750 DAG.isKnownToBeAPowerOfTwo(N1)) {
3751 SDValue LogBase2 = BuildLogBase2(N1, DL);
3752 AddToWorklist(LogBase2.getNode());
3753
3754 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3755 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
3756 AddToWorklist(Trunc.getNode());
3757 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
3758 }
3759
3760 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
3761 if (N1.getOpcode() == ISD::SHL) {
3762 SDValue N10 = N1.getOperand(0);
3763 if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) &&
3764 DAG.isKnownToBeAPowerOfTwo(N10)) {
3765 SDValue LogBase2 = BuildLogBase2(N10, DL);
3766 AddToWorklist(LogBase2.getNode());
3767
3768 EVT ADDVT = N1.getOperand(1).getValueType();
3769 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT);
3770 AddToWorklist(Trunc.getNode());
3771 SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc);
3772 AddToWorklist(Add.getNode());
3773 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
3774 }
3775 }
3776
3777 // fold (udiv x, c) -> alternate
3778 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3779 if (isConstantOrConstantVector(N1) &&
3780 !TLI.isIntDivCheap(N->getValueType(0), Attr))
3781 if (SDValue Op = BuildUDIV(N))
3782 return Op;
3783
3784 return SDValue();
3785}
3786
3787// handles ISD::SREM and ISD::UREM
3788SDValue DAGCombiner::visitREM(SDNode *N) {
3789 unsigned Opcode = N->getOpcode();
3790 SDValue N0 = N->getOperand(0);
3791 SDValue N1 = N->getOperand(1);
3792 EVT VT = N->getValueType(0);
3793 EVT CCVT = getSetCCResultType(VT);
3794
3795 bool isSigned = (Opcode == ISD::SREM);
3796 SDLoc DL(N);
3797
3798 // fold (rem c1, c2) -> c1%c2
3799 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3800 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3801 if (N0C && N1C)
3802 if (SDValue Folded = DAG.FoldConstantArithmetic(Opcode, DL, VT, N0C, N1C))
3803 return Folded;
3804 // fold (urem X, -1) -> select(X == -1, 0, x)
3805 if (!isSigned && N1C && N1C->getAPIntValue().isAllOnesValue())
3806 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
3807 DAG.getConstant(0, DL, VT), N0);
3808
3809 if (SDValue V = simplifyDivRem(N, DAG))
3810 return V;
3811
3812 if (SDValue NewSel = foldBinOpIntoSelect(N))
3813 return NewSel;
3814
3815 if (isSigned) {
3816 // If we know the sign bits of both operands are zero, strength reduce to a
3817 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
3818 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
3819 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
3820 } else {
3821 SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
3822 if (DAG.isKnownToBeAPowerOfTwo(N1)) {
3823 // fold (urem x, pow2) -> (and x, pow2-1)
3824 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
3825 AddToWorklist(Add.getNode());
3826 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
3827 }
3828 if (N1.getOpcode() == ISD::SHL &&
3829 DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) {
3830 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
3831 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
3832 AddToWorklist(Add.getNode());
3833 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
3834 }
3835 }
3836
3837 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3838
3839 // If X/C can be simplified by the division-by-constant logic, lower
3840 // X%C to the equivalent of X-X/C*C.
3841 // Reuse the SDIVLike/UDIVLike combines - to avoid mangling nodes, the
3842 // speculative DIV must not cause a DIVREM conversion. We guard against this
3843 // by skipping the simplification if isIntDivCheap(). When div is not cheap,
3844 // combine will not return a DIVREM. Regardless, checking cheapness here
3845 // makes sense since the simplification results in fatter code.
3846 if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) {
3847 SDValue OptimizedDiv =
3848 isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N);
3849 if (OptimizedDiv.getNode()) {
3850 // If the equivalent Div node also exists, update its users.
3851 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
3852 if (SDNode *DivNode = DAG.getNodeIfExists(DivOpcode, N->getVTList(),
3853 { N0, N1 }))
3854 CombineTo(DivNode, OptimizedDiv);
3855 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1);
3856 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3857 AddToWorklist(OptimizedDiv.getNode());
3858 AddToWorklist(Mul.getNode());
3859 return Sub;
3860 }
3861 }
3862
3863 // sdiv, srem -> sdivrem
3864 if (SDValue DivRem = useDivRem(N))
3865 return DivRem.getValue(1);
3866
3867 return SDValue();
3868}
3869
3870SDValue DAGCombiner::visitMULHS(SDNode *N) {
3871 SDValue N0 = N->getOperand(0);
3872 SDValue N1 = N->getOperand(1);
3873 EVT VT = N->getValueType(0);
3874 SDLoc DL(N);
3875
3876 if (VT.isVector()) {
3877 // fold (mulhs x, 0) -> 0
3878 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3879 return N1;
3880 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3881 return N0;
3882 }
3883
3884 // fold (mulhs x, 0) -> 0
3885 if (isNullConstant(N1))
3886 return N1;
3887 // fold (mulhs x, 1) -> (sra x, size(x)-1)
3888 if (isOneConstant(N1))
3889 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
3890 DAG.getConstant(N0.getValueSizeInBits() - 1, DL,
3891 getShiftAmountTy(N0.getValueType())));
3892
3893 // fold (mulhs x, undef) -> 0
3894 if (N0.isUndef() || N1.isUndef())
3895 return DAG.getConstant(0, DL, VT);
3896
3897 // If the type twice as wide is legal, transform the mulhs to a wider multiply
3898 // plus a shift.
3899 if (VT.isSimple() && !VT.isVector()) {
3900 MVT Simple = VT.getSimpleVT();
3901 unsigned SimpleSize = Simple.getSizeInBits();
3902 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
3903 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
3904 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
3905 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
3906 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
3907 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
3908 DAG.getConstant(SimpleSize, DL,
3909 getShiftAmountTy(N1.getValueType())));
3910 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
3911 }
3912 }
3913
3914 return SDValue();
3915}
3916
3917SDValue DAGCombiner::visitMULHU(SDNode *N) {
3918 SDValue N0 = N->getOperand(0);
3919 SDValue N1 = N->getOperand(1);
3920 EVT VT = N->getValueType(0);
3921 SDLoc DL(N);
3922
3923 if (VT.isVector()) {
3924 // fold (mulhu x, 0) -> 0
3925 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3926 return N1;
3927 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3928 return N0;
3929 }
3930
3931 // fold (mulhu x, 0) -> 0
3932 if (isNullConstant(N1))
3933 return N1;
3934 // fold (mulhu x, 1) -> 0
3935 if (isOneConstant(N1))
3936 return DAG.getConstant(0, DL, N0.getValueType());
3937 // fold (mulhu x, undef) -> 0
3938 if (N0.isUndef() || N1.isUndef())
3939 return DAG.getConstant(0, DL, VT);
3940
3941 // fold (mulhu x, (1 << c)) -> x >> (bitwidth - c)
3942 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3943 DAG.isKnownToBeAPowerOfTwo(N1) && hasOperation(ISD::SRL, VT)) {
3944 unsigned NumEltBits = VT.getScalarSizeInBits();
3945 SDValue LogBase2 = BuildLogBase2(N1, DL);
3946 SDValue SRLAmt = DAG.getNode(
3947 ISD::SUB, DL, VT, DAG.getConstant(NumEltBits, DL, VT), LogBase2);
3948 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3949 SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT);
3950 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
3951 }
3952
3953 // If the type twice as wide is legal, transform the mulhu to a wider multiply
3954 // plus a shift.
3955 if (VT.isSimple() && !VT.isVector()) {
3956 MVT Simple = VT.getSimpleVT();
3957 unsigned SimpleSize = Simple.getSizeInBits();
3958 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
3959 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
3960 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
3961 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
3962 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
3963 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
3964 DAG.getConstant(SimpleSize, DL,
3965 getShiftAmountTy(N1.getValueType())));
3966 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
3967 }
3968 }
3969
3970 return SDValue();
3971}
3972
3973/// Perform optimizations common to nodes that compute two values. LoOp and HiOp
3974/// give the opcodes for the two computations that are being performed. Return
3975/// true if a simplification was made.
3976SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
3977 unsigned HiOp) {
3978 // If the high half is not needed, just compute the low half.
3979 bool HiExists = N->hasAnyUseOfValue(1);
3980 if (!HiExists && (!LegalOperations ||
3981 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
3982 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
3983 return CombineTo(N, Res, Res);
3984 }
3985
3986 // If the low half is not needed, just compute the high half.
3987 bool LoExists = N->hasAnyUseOfValue(0);
3988 if (!LoExists && (!LegalOperations ||
3989 TLI.isOperationLegalOrCustom(HiOp, N->getValueType(1)))) {
3990 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
3991 return CombineTo(N, Res, Res);
3992 }
3993
3994 // If both halves are used, return as it is.
3995 if (LoExists && HiExists)
3996 return SDValue();
3997
3998 // If the two computed results can be simplified separately, separate them.
3999 if (LoExists) {
4000 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4001 AddToWorklist(Lo.getNode());
4002 SDValue LoOpt = combine(Lo.getNode());
4003 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
4004 (!LegalOperations ||
4005 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType())))
4006 return CombineTo(N, LoOpt, LoOpt);
4007 }
4008
4009 if (HiExists) {
4010 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4011 AddToWorklist(Hi.getNode());
4012 SDValue HiOpt = combine(Hi.getNode());
4013 if (HiOpt.getNode() && HiOpt != Hi &&
4014 (!LegalOperations ||
4015 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType())))
4016 return CombineTo(N, HiOpt, HiOpt);
4017 }
4018
4019 return SDValue();
4020}
4021
4022SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
4023 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
4024 return Res;
4025
4026 EVT VT = N->getValueType(0);
4027 SDLoc DL(N);
4028
4029 // If the type is twice as wide is legal, transform the mulhu to a wider
4030 // multiply plus a shift.
4031 if (VT.isSimple() && !VT.isVector()) {
4032 MVT Simple = VT.getSimpleVT();
4033 unsigned SimpleSize = Simple.getSizeInBits();
4034 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4035 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4036 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
4037 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
4038 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
4039 // Compute the high part as N1.
4040 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
4041 DAG.getConstant(SimpleSize, DL,
4042 getShiftAmountTy(Lo.getValueType())));
4043 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
4044 // Compute the low part as N0.
4045 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
4046 return CombineTo(N, Lo, Hi);
4047 }
4048 }
4049
4050 return SDValue();
4051}
4052
4053SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
4054 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
4055 return Res;
4056
4057 EVT VT = N->getValueType(0);
4058 SDLoc DL(N);
4059
4060 // If the type is twice as wide is legal, transform the mulhu to a wider
4061 // multiply plus a shift.
4062 if (VT.isSimple() && !VT.isVector()) {
4063 MVT Simple = VT.getSimpleVT();
4064 unsigned SimpleSize = Simple.getSizeInBits();
4065 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4066 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4067 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
4068 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
4069 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
4070 // Compute the high part as N1.
4071 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
4072 DAG.getConstant(SimpleSize, DL,
4073 getShiftAmountTy(Lo.getValueType())));
4074 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
4075 // Compute the low part as N0.
4076 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
4077 return CombineTo(N, Lo, Hi);
4078 }
4079 }
4080
4081 return SDValue();
4082}
4083
4084SDValue DAGCombiner::visitMULO(SDNode *N) {
4085 bool IsSigned = (ISD::SMULO == N->getOpcode());
4086
4087 // (mulo x, 2) -> (addo x, x)
4088 if (ConstantSDNode *C2 = isConstOrConstSplat(N->getOperand(1)))
4089 if (C2->getAPIntValue() == 2)
4090 return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, SDLoc(N),
4091 N->getVTList(), N->getOperand(0), N->getOperand(0));
4092
4093 return SDValue();
4094}
4095
4096SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
4097 SDValue N0 = N->getOperand(0);
4098 SDValue N1 = N->getOperand(1);
4099 EVT VT = N0.getValueType();
4100
4101 // fold vector ops
4102 if (VT.isVector())
4103 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4104 return FoldedVOp;
4105
4106 // fold operation with constant operands.
4107 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4108 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
4109 if (N0C && N1C)
4110 return DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, N0C, N1C);
4111
4112 // canonicalize constant to RHS
4113 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4114 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4115 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
4116
4117 // Is sign bits are zero, flip between UMIN/UMAX and SMIN/SMAX.
4118 // Only do this if the current op isn't legal and the flipped is.
4119 unsigned Opcode = N->getOpcode();
4120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4121 if (!TLI.isOperationLegal(Opcode, VT) &&
4122 (N0.isUndef() || DAG.SignBitIsZero(N0)) &&
4123 (N1.isUndef() || DAG.SignBitIsZero(N1))) {
4124 unsigned AltOpcode;
4125 switch (Opcode) {
4126 case ISD::SMIN: AltOpcode = ISD::UMIN; break;
4127 case ISD::SMAX: AltOpcode = ISD::UMAX; break;
4128 case ISD::UMIN: AltOpcode = ISD::SMIN; break;
4129 case ISD::UMAX: AltOpcode = ISD::SMAX; break;
4130 default: llvm_unreachable("Unknown MINMAX opcode")::llvm::llvm_unreachable_internal("Unknown MINMAX opcode", "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4130)
;
4131 }
4132 if (TLI.isOperationLegal(AltOpcode, VT))
4133 return DAG.getNode(AltOpcode, SDLoc(N), VT, N0, N1);
4134 }
4135
4136 return SDValue();
4137}
4138
4139/// If this is a bitwise logic instruction and both operands have the same
4140/// opcode, try to sink the other opcode after the logic instruction.
4141SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
4142 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4143 EVT VT = N0.getValueType();
4144 unsigned LogicOpcode = N->getOpcode();
4145 unsigned HandOpcode = N0.getOpcode();
4146 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
== ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4147, __PRETTY_FUNCTION__))
4147 LogicOpcode == ISD::XOR) && "Expected logic opcode")(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
== ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4147, __PRETTY_FUNCTION__))
;
4148 assert(HandOpcode == N1.getOpcode() && "Bad input!")((HandOpcode == N1.getOpcode() && "Bad input!") ? static_cast
<void> (0) : __assert_fail ("HandOpcode == N1.getOpcode() && \"Bad input!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4148, __PRETTY_FUNCTION__))
;
4149
4150 // Bail early if none of these transforms apply.
4151 if (N0.getNumOperands() == 0)
4152 return SDValue();
4153
4154 // FIXME: We should check number of uses of the operands to not increase
4155 // the instruction count for all transforms.
4156
4157 // Handle size-changing casts.
4158 SDValue X = N0.getOperand(0);
4159 SDValue Y = N1.getOperand(0);
4160 EVT XVT = X.getValueType();
4161 SDLoc DL(N);
4162 if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND ||
4163 HandOpcode == ISD::SIGN_EXTEND) {
4164 // If both operands have other uses, this transform would create extra
4165 // instructions without eliminating anything.
4166 if (!N0.hasOneUse() && !N1.hasOneUse())
4167 return SDValue();
4168 // We need matching integer source types.
4169 if (XVT != Y.getValueType())
4170 return SDValue();
4171 // Don't create an illegal op during or after legalization. Don't ever
4172 // create an unsupported vector op.
4173 if ((VT.isVector() || LegalOperations) &&
4174 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT))
4175 return SDValue();
4176 // Avoid infinite looping with PromoteIntBinOp.
4177 // TODO: Should we apply desirable/legal constraints to all opcodes?
4178 if (HandOpcode == ISD::ANY_EXTEND && LegalTypes &&
4179 !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
4180 return SDValue();
4181 // logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y)
4182 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4183 return DAG.getNode(HandOpcode, DL, VT, Logic);
4184 }
4185
4186 // logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)
4187 if (HandOpcode == ISD::TRUNCATE) {
4188 // If both operands have other uses, this transform would create extra
4189 // instructions without eliminating anything.
4190 if (!N0.hasOneUse() && !N1.hasOneUse())
4191 return SDValue();
4192 // We need matching source types.
4193 if (XVT != Y.getValueType())
4194 return SDValue();
4195 // Don't create an illegal op during or after legalization.
4196 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
4197 return SDValue();
4198 // Be extra careful sinking truncate. If it's free, there's no benefit in
4199 // widening a binop. Also, don't create a logic op on an illegal type.
4200 if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT))
4201 return SDValue();
4202 if (!TLI.isTypeLegal(XVT))
4203 return SDValue();
4204 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4205 return DAG.getNode(HandOpcode, DL, VT, Logic);
4206 }
4207
4208 // For binops SHL/SRL/SRA/AND:
4209 // logic_op (OP x, z), (OP y, z) --> OP (logic_op x, y), z
4210 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL ||
4211 HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
4212 N0.getOperand(1) == N1.getOperand(1)) {
4213 // If either operand has other uses, this transform is not an improvement.
4214 if (!N0.hasOneUse() || !N1.hasOneUse())
4215 return SDValue();
4216 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4217 return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
4218 }
4219
4220 // Unary ops: logic_op (bswap x), (bswap y) --> bswap (logic_op x, y)
4221 if (HandOpcode == ISD::BSWAP) {
4222 // If either operand has other uses, this transform is not an improvement.
4223 if (!N0.hasOneUse() || !N1.hasOneUse())
4224 return SDValue();
4225 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4226 return DAG.getNode(HandOpcode, DL, VT, Logic);
4227 }
4228
4229 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
4230 // Only perform this optimization up until type legalization, before
4231 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
4232 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
4233 // we don't want to undo this promotion.
4234 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
4235 // on scalars.
4236 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
4237 Level <= AfterLegalizeTypes) {
4238 // Input types must be integer and the same.
4239 if (XVT.isInteger() && XVT == Y.getValueType()) {
4240 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4241 return DAG.getNode(HandOpcode, DL, VT, Logic);
4242 }
4243 }
4244
4245 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
4246 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
4247 // If both shuffles use the same mask, and both shuffle within a single
4248 // vector, then it is worthwhile to move the swizzle after the operation.
4249 // The type-legalizer generates this pattern when loading illegal
4250 // vector types from memory. In many cases this allows additional shuffle
4251 // optimizations.
4252 // There are other cases where moving the shuffle after the xor/and/or
4253 // is profitable even if shuffles don't perform a swizzle.
4254 // If both shuffles use the same mask, and both shuffles have the same first
4255 // or second operand, then it might still be profitable to move the shuffle
4256 // after the xor/and/or operation.
4257 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
4258 auto *SVN0 = cast<ShuffleVectorSDNode>(N0);
4259 auto *SVN1 = cast<ShuffleVectorSDNode>(N1);
4260 assert(X.getValueType() == Y.getValueType() &&((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4261, __PRETTY_FUNCTION__))
4261 "Inputs to shuffles are not the same type")((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4261, __PRETTY_FUNCTION__))
;
4262
4263 // Check that both shuffles use the same mask. The masks are known to be of
4264 // the same length because the result vector type is the same.
4265 // Check also that shuffles have only one use to avoid introducing extra
4266 // instructions.
4267 if (!SVN0->hasOneUse() || !SVN1->hasOneUse() ||
4268 !SVN0->getMask().equals(SVN1->getMask()))
4269 return SDValue();
4270
4271 // Don't try to fold this node if it requires introducing a
4272 // build vector of all zeros that might be illegal at this stage.
4273 SDValue ShOp = N0.getOperand(1);
4274 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4275 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4276
4277 // (logic_op (shuf (A, C), shuf (B, C))) --> shuf (logic_op (A, B), C)
4278 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
4279 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT,
4280 N0.getOperand(0), N1.getOperand(0));
4281 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask());
4282 }
4283
4284 // Don't try to fold this node if it requires introducing a
4285 // build vector of all zeros that might be illegal at this stage.
4286 ShOp = N0.getOperand(0);
4287 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4288 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4289
4290 // (logic_op (shuf (C, A), shuf (C, B))) --> shuf (C, logic_op (A, B))
4291 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
4292 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
4293 N1.getOperand(1));
4294 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask());
4295 }
4296 }
4297
4298 return SDValue();
4299}
4300
4301/// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient.
4302SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
4303 const SDLoc &DL) {
4304 SDValue LL, LR, RL, RR, N0CC, N1CC;
4305 if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
4306 !isSetCCEquivalent(N1, RL, RR, N1CC))
4307 return SDValue();
4308
4309 assert(N0.getValueType() == N1.getValueType() &&((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4310, __PRETTY_FUNCTION__))
4310 "Unexpected operand types for bitwise logic op")((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4310, __PRETTY_FUNCTION__))
;
4311 assert(LL.getValueType() == LR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4313, __PRETTY_FUNCTION__))
4312 RL.getValueType() == RR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4313, __PRETTY_FUNCTION__))
4313 "Unexpected operand types for setcc")((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4313, __PRETTY_FUNCTION__))
;
4314
4315 // If we're here post-legalization or the logic op type is not i1, the logic
4316 // op type must match a setcc result type. Also, all folds require new
4317 // operations on the left and right operands, so those types must match.
4318 EVT VT = N0.getValueType();
4319 EVT OpVT = LL.getValueType();
4320 if (LegalOperations || VT.getScalarType() != MVT::i1)
4321 if (VT != getSetCCResultType(OpVT))
4322 return SDValue();
4323 if (OpVT != RL.getValueType())
4324 return SDValue();
4325
4326 ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
4327 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
4328 bool IsInteger = OpVT.isInteger();
4329 if (LR == RR && CC0 == CC1 && IsInteger) {
4330 bool IsZero = isNullOrNullSplat(LR);
4331 bool IsNeg1 = isAllOnesOrAllOnesSplat(LR);
4332
4333 // All bits clear?
4334 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
4335 // All sign bits clear?
4336 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
4337 // Any bits set?
4338 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
4339 // Any sign bits set?
4340 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
4341
4342 // (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0)
4343 // (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
4344 // (or (setne X, 0), (setne Y, 0)) --> (setne (or X, Y), 0)
4345 // (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0)
4346 if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) {
4347 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
4348 AddToWorklist(Or.getNode());
4349 return DAG.getSetCC(DL, VT, Or, LR, CC1);
4350 }
4351
4352 // All bits set?
4353 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
4354 // All sign bits set?
4355 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
4356 // Any bits clear?
4357 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1;
4358 // Any sign bits clear?
4359 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1;
4360
4361 // (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
4362 // (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0)
4363 // (or (setne X, -1), (setne Y, -1)) --> (setne (and X, Y), -1)
4364 // (or (setgt X, -1), (setgt Y -1)) --> (setgt (and X, Y), -1)
4365 if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) {
4366 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
4367 AddToWorklist(And.getNode());
4368 return DAG.getSetCC(DL, VT, And, LR, CC1);
4369 }
4370 }
4371
4372 // TODO: What is the 'or' equivalent of this fold?
4373 // (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
4374 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 &&
4375 IsInteger && CC0 == ISD::SETNE &&
4376 ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
4377 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
4378 SDValue One = DAG.getConstant(1, DL, OpVT);
4379 SDValue Two = DAG.getConstant(2, DL, OpVT);
4380 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
4381 AddToWorklist(Add.getNode());
4382 return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
4383 }
4384
4385 // Try more general transforms if the predicates match and the only user of
4386 // the compares is the 'and' or 'or'.
4387 if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 &&
4388 N0.hasOneUse() && N1.hasOneUse()) {
4389 // and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
4390 // or (setne A, B), (setne C, D) --> setne (or (xor A, B), (xor C, D)), 0
4391 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) {
4392 SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR);
4393 SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR);
4394 SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR);
4395 SDValue Zero = DAG.getConstant(0, DL, OpVT);
4396 return DAG.getSetCC(DL, VT, Or, Zero, CC1);
4397 }
4398
4399 // Turn compare of constants whose difference is 1 bit into add+and+setcc.
4400 if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) {
4401 // Match a shared variable operand and 2 non-opaque constant operands.
4402 ConstantSDNode *C0 = isConstOrConstSplat(LR);
4403 ConstantSDNode *C1 = isConstOrConstSplat(RR);
4404 if (LL == RL && C0 && C1 && !C0->isOpaque() && !C1->isOpaque()) {
4405 // Canonicalize larger constant as C0.
4406 if (C1->getAPIntValue().ugt(C0->getAPIntValue()))
4407 std::swap(C0, C1);
4408
4409 // The difference of the constants must be a single bit.
4410 const APInt &C0Val = C0->getAPIntValue();
4411 const APInt &C1Val = C1->getAPIntValue();
4412 if ((C0Val - C1Val).isPowerOf2()) {
4413 // and/or (setcc X, C0, ne), (setcc X, C1, ne/eq) -->
4414 // setcc ((add X, -C1), ~(C0 - C1)), 0, ne/eq
4415 SDValue OffsetC = DAG.getConstant(-C1Val, DL, OpVT);
4416 SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LL, OffsetC);
4417 SDValue MaskC = DAG.getConstant(~(C0Val - C1Val), DL, OpVT);
4418 SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Add, MaskC);
4419 SDValue Zero = DAG.getConstant(0, DL, OpVT);
4420 return DAG.getSetCC(DL, VT, And, Zero, CC0);
4421 }
4422 }
4423 }
4424 }
4425
4426 // Canonicalize equivalent operands to LL == RL.
4427 if (LL == RR && LR == RL) {
4428 CC1 = ISD::getSetCCSwappedOperands(CC1);
4429 std::swap(RL, RR);
4430 }
4431
4432 // (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
4433 // (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
4434 if (LL == RL && LR == RR) {
4435 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, IsInteger)
4436 : ISD::getSetCCOrOperation(CC0, CC1, IsInteger);
4437 if (NewCC != ISD::SETCC_INVALID &&
4438 (!LegalOperations ||
4439 (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
4440 TLI.isOperationLegal(ISD::SETCC, OpVT))))
4441 return DAG.getSetCC(DL, VT, LL, LR, NewCC);
4442 }
4443
4444 return SDValue();
4445}
4446
4447/// This contains all DAGCombine rules which reduce two values combined by
4448/// an And operation to a single value. This makes them reusable in the context
4449/// of visitSELECT(). Rules involving constants are not included as
4450/// visitSELECT() already handles those cases.
4451SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
4452 EVT VT = N1.getValueType();
4453 SDLoc DL(N);
4454
4455 // fold (and x, undef) -> 0
4456 if (N0.isUndef() || N1.isUndef())
4457 return DAG.getConstant(0, DL, VT);
4458
4459 if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
4460 return V;
4461
4462 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
4463 VT.getSizeInBits() <= 64) {
4464 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4465 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
4466 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
4467 // immediate for an add, but it is legal if its top c2 bits are set,
4468 // transform the ADD so the immediate doesn't need to be materialized
4469 // in a register.
4470 APInt ADDC = ADDI->getAPIntValue();
4471 APInt SRLC = SRLI->getAPIntValue();
4472 if (ADDC.getMinSignedBits() <= 64 &&
4473 SRLC.ult(VT.getSizeInBits()) &&
4474 !TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
4475 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
4476 SRLC.getZExtValue());
4477 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
4478 ADDC |= Mask;
4479 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
4480 SDLoc DL0(N0);
4481 SDValue NewAdd =
4482 DAG.getNode(ISD::ADD, DL0, VT,
4483 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
4484 CombineTo(N0.getNode(), NewAdd);
4485 // Return N so it doesn't get rechecked!
4486 return SDValue(N, 0);
4487 }
4488 }
4489 }
4490 }
4491 }
4492 }
4493
4494 // Reduce bit extract of low half of an integer to the narrower type.
4495 // (and (srl i64:x, K), KMask) ->
4496 // (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
4497 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4498 if (ConstantSDNode *CAnd = dyn_cast<ConstantSDNode>(N1)) {
4499 if (ConstantSDNode *CShift = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4500 unsigned Size = VT.getSizeInBits();
4501 const APInt &AndMask = CAnd->getAPIntValue();
4502 unsigned ShiftBits = CShift->getZExtValue();
4503
4504 // Bail out, this node will probably disappear anyway.
4505 if (ShiftBits == 0)
4506 return SDValue();
4507
4508 unsigned MaskBits = AndMask.countTrailingOnes();
4509 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);
4510
4511 if (AndMask.isMask() &&
4512 // Required bits must not span the two halves of the integer and
4513 // must fit in the half size type.
4514 (ShiftBits + MaskBits <= Size / 2) &&
4515 TLI.isNarrowingProfitable(VT, HalfVT) &&
4516 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
4517 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) &&
4518 TLI.isTruncateFree(VT, HalfVT) &&
4519 TLI.isZExtFree(HalfVT, VT)) {
4520 // The isNarrowingProfitable is to avoid regressions on PPC and
4521 // AArch64 which match a few 64-bit bit insert / bit extract patterns
4522 // on downstream users of this. Those patterns could probably be
4523 // extended to handle extensions mixed in.
4524
4525 SDValue SL(N0);
4526 assert(MaskBits <= Size)((MaskBits <= Size) ? static_cast<void> (0) : __assert_fail
("MaskBits <= Size", "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4526, __PRETTY_FUNCTION__))
;
4527
4528 // Extracting the highest bit of the low half.
4529 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
4530 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT,
4531 N0.getOperand(0));
4532
4533 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT);
4534 SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT);
4535 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK);
4536 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask);
4537 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And);
4538 }
4539 }
4540 }
4541 }
4542
4543 return SDValue();
4544}
4545
4546bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
4547 EVT LoadResultTy, EVT &ExtVT) {
4548 if (!AndC->getAPIntValue().isMask())
4549 return false;
4550
4551 unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes();
4552
4553 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
4554 EVT LoadedVT = LoadN->getMemoryVT();
4555
4556 if (ExtVT == LoadedVT &&
4557 (!LegalOperations ||
4558 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
4559 // ZEXTLOAD will match without needing to change the size of the value being
4560 // loaded.
4561 return true;
4562 }
4563
4564 // Do not change the width of a volatile load.
4565 if (LoadN->isVolatile())
4566 return false;
4567
4568 // Do not generate loads of non-round integer types since these can
4569 // be expensive (and would be wrong if the type is not byte sized).
4570 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound())
4571 return false;
4572
4573 if (LegalOperations &&
4574 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
4575 return false;
4576
4577 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
4578 return false;
4579
4580 return true;
4581}
4582
4583bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
4584 ISD::LoadExtType ExtType, EVT &MemVT,
4585 unsigned ShAmt) {
4586 if (!LDST)
4587 return false;
4588 // Only allow byte offsets.
4589 if (ShAmt % 8)
4590 return false;
4591
4592 // Do not generate loads of non-round integer types since these can
4593 // be expensive (and would be wrong if the type is not byte sized).
4594 if (!MemVT.isRound())
4595 return false;
4596
4597 // Don't change the width of a volatile load.
4598 if (LDST->isVolatile())
4599 return false;
4600
4601 // Verify that we are actually reducing a load width here.
4602 if (LDST->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits())
4603 return false;
4604
4605 // Ensure that this isn't going to produce an unsupported unaligned access.
4606 if (ShAmt &&
4607 !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
4608 LDST->getAddressSpace(), ShAmt / 8))
4609 return false;
4610
4611 // It's not possible to generate a constant of extended or untyped type.
4612 EVT PtrType = LDST->getBasePtr().getValueType();
4613 if (PtrType == MVT::Untyped || PtrType.isExtended())
4614 return false;
4615
4616 if (isa<LoadSDNode>(LDST)) {
4617 LoadSDNode *Load = cast<LoadSDNode>(LDST);
4618 // Don't transform one with multiple uses, this would require adding a new
4619 // load.
4620 if (!SDValue(Load, 0).hasOneUse())
4621 return false;
4622
4623 if (LegalOperations &&
4624 !TLI.isLoadExtLegal(ExtType, Load->getValueType(0), MemVT))
4625 return false;
4626
4627 // For the transform to be legal, the load must produce only two values
4628 // (the value loaded and the chain). Don't transform a pre-increment
4629 // load, for example, which produces an extra value. Otherwise the
4630 // transformation is not equivalent, and the downstream logic to replace
4631 // uses gets things wrong.
4632 if (Load->getNumValues() > 2)
4633 return false;
4634
4635 // If the load that we're shrinking is an extload and we're not just
4636 // discarding the extension we can't simply shrink the load. Bail.
4637 // TODO: It would be possible to merge the extensions in some cases.
4638 if (Load->getExtensionType() != ISD::NON_EXTLOAD &&
4639 Load->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
4640 return false;
4641
4642 if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT))
4643 return false;
4644 } else {
4645 assert(isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode")((isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode"
) ? static_cast<void> (0) : __assert_fail ("isa<StoreSDNode>(LDST) && \"It is not a Load nor a Store SDNode\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4645, __PRETTY_FUNCTION__))
;
4646 StoreSDNode *Store = cast<StoreSDNode>(LDST);
4647 // Can't write outside the original store
4648 if (Store->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
4649 return false;
4650
4651 if (LegalOperations &&
4652 !TLI.isTruncStoreLegal(Store->getValue().getValueType(), MemVT))
4653 return false;
4654 }
4655 return true;
4656}
4657
4658bool DAGCombiner::SearchForAndLoads(SDNode *N,
4659 SmallVectorImpl<LoadSDNode*> &Loads,
4660 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
4661 ConstantSDNode *Mask,
4662 SDNode *&NodeToMask) {
4663 // Recursively search for the operands, looking for loads which can be
4664 // narrowed.
4665 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) {
4666 SDValue Op = N->getOperand(i);
4667
4668 if (Op.getValueType().isVector())
4669 return false;
4670
4671 // Some constants may need fixing up later if they are too large.
4672 if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
4673 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
4674 (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
4675 NodesWithConsts.insert(N);
4676 continue;
4677 }
4678
4679 if (!Op.hasOneUse())
4680 return false;
4681
4682 switch(Op.getOpcode()) {
4683 case ISD::LOAD: {
4684 auto *Load = cast<LoadSDNode>(Op);
4685 EVT ExtVT;
4686 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
4687 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) {
4688
4689 // ZEXTLOAD is already small enough.
4690 if (Load->getExtensionType() == ISD::ZEXTLOAD &&
4691 ExtVT.bitsGE(Load->getMemoryVT()))
4692 continue;
4693
4694 // Use LE to convert equal sized loads to zext.
4695 if (ExtVT.bitsLE(Load->getMemoryVT()))
4696 Loads.push_back(Load);
4697
4698 continue;
4699 }
4700 return false;
4701 }
4702 case ISD::ZERO_EXTEND:
4703 case ISD::AssertZext: {
4704 unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
4705 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
4706 EVT VT = Op.getOpcode() == ISD::AssertZext ?
4707 cast<VTSDNode>(Op.getOperand(1))->getVT() :
4708 Op.getOperand(0).getValueType();
4709
4710 // We can accept extending nodes if the mask is wider or an equal
4711 // width to the original type.
4712 if (ExtVT.bitsGE(VT))
4713 continue;
4714 break;
4715 }
4716 case ISD::OR:
4717 case ISD::XOR:
4718 case ISD::AND:
4719 if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask,
4720 NodeToMask))
4721 return false;
4722 continue;
4723 }
4724
4725 // Allow one node which will masked along with any loads found.
4726 if (NodeToMask)
4727 return false;
4728
4729 // Also ensure that the node to be masked only produces one data result.
4730 NodeToMask = Op.getNode();
4731 if (NodeToMask->getNumValues() > 1) {
4732 bool HasValue = false;
4733 for (unsigned i = 0, e = NodeToMask->getNumValues(); i < e; ++i) {
4734 MVT VT = SDValue(NodeToMask, i).getSimpleValueType();
4735 if (VT != MVT::Glue && VT != MVT::Other) {
4736 if (HasValue) {
4737 NodeToMask = nullptr;
4738 return false;
4739 }
4740 HasValue = true;
4741 }
4742 }
4743 assert(HasValue && "Node to be masked has no data result?")((HasValue && "Node to be masked has no data result?"
) ? static_cast<void> (0) : __assert_fail ("HasValue && \"Node to be masked has no data result?\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4743, __PRETTY_FUNCTION__))
;
4744 }
4745 }
4746 return true;
4747}
4748
4749bool DAGCombiner::BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG) {
4750 auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
4751 if (!Mask)
4752 return false;
4753
4754 if (!Mask->getAPIntValue().isMask())
4755 return false;
4756
4757 // No need to do anything if the and directly uses a load.
4758 if (isa<LoadSDNode>(N->getOperand(0)))
4759 return false;
4760
4761 SmallVector<LoadSDNode*, 8> Loads;
4762 SmallPtrSet<SDNode*, 2> NodesWithConsts;
4763 SDNode *FixupNode = nullptr;
4764 if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) {
4765 if (Loads.size() == 0)
4766 return false;
4767
4768 LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Backwards propagate AND: "
; N->dump(); } } while (false)
;
4769 SDValue MaskOp = N->getOperand(1);
4770
4771 // If it exists, fixup the single node we allow in the tree that needs
4772 // masking.
4773 if (FixupNode) {
4774 LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "First, need to fix up: "; FixupNode
->dump(); } } while (false)
;
4775 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
4776 FixupNode->getValueType(0),
4777 SDValue(FixupNode, 0), MaskOp);
4778 DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And);
4779 if (And.getOpcode() == ISD ::AND)
4780 DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOp);
4781 }
4782
4783 // Narrow any constants that need it.
4784 for (auto *LogicN : NodesWithConsts) {
4785 SDValue Op0 = LogicN->getOperand(0);
4786 SDValue Op1 = LogicN->getOperand(1);
4787
4788 if (isa<ConstantSDNode>(Op0))
4789 std::swap(Op0, Op1);
4790
4791 SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(),
4792 Op1, MaskOp);
4793
4794 DAG.UpdateNodeOperands(LogicN, Op0, And);
4795 }
4796
4797 // Create narrow loads.
4798 for (auto *Load : Loads) {
4799 LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Propagate AND back to: "; Load
->dump(); } } while (false)
;
4800 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
4801 SDValue(Load, 0), MaskOp);
4802 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
4803 if (And.getOpcode() == ISD ::AND)
4804 And = SDValue(
4805 DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp), 0);
4806 SDValue NewLoad = ReduceLoadWidth(And.getNode());
4807 assert(NewLoad &&((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4808, __PRETTY_FUNCTION__))
4808 "Shouldn't be masking the load if it can't be narrowed")((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4808, __PRETTY_FUNCTION__))
;
4809 CombineTo(Load, NewLoad, NewLoad.getValue(1));
4810 }
4811 DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
4812 return true;
4813 }
4814 return false;
4815}
4816
4817// Unfold
4818// x & (-1 'logical shift' y)
4819// To
4820// (x 'opposite logical shift' y) 'logical shift' y
4821// if it is better for performance.
4822SDValue DAGCombiner::unfoldExtremeBitClearingToShifts(SDNode *N) {
4823 assert(N->getOpcode() == ISD::AND)((N->getOpcode() == ISD::AND) ? static_cast<void> (0
) : __assert_fail ("N->getOpcode() == ISD::AND", "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4823, __PRETTY_FUNCTION__))
;
4824
4825 SDValue N0 = N->getOperand(0);
4826 SDValue N1 = N->getOperand(1);
4827
4828 // Do we actually prefer shifts over mask?
4829 if (!TLI.shouldFoldMaskToVariableShiftPair(N0))
4830 return SDValue();
4831
4832 // Try to match (-1 '[outer] logical shift' y)
4833 unsigned OuterShift;
4834 unsigned InnerShift; // The opposite direction to the OuterShift.
4835 SDValue Y; // Shift amount.
4836 auto matchMask = [&OuterShift, &InnerShift, &Y](SDValue M) -> bool {
4837 if (!M.hasOneUse())
4838 return false;
4839 OuterShift = M->getOpcode();
4840 if (OuterShift == ISD::SHL)
4841 InnerShift = ISD::SRL;
4842 else if (OuterShift == ISD::SRL)
4843 InnerShift = ISD::SHL;
4844 else
4845 return false;
4846 if (!isAllOnesConstant(M->getOperand(0)))
4847 return false;
4848 Y = M->getOperand(1);
4849 return true;
4850 };
4851
4852 SDValue X;
4853 if (matchMask(N1))
4854 X = N0;
4855 else if (matchMask(N0))
4856 X = N1;
4857 else
4858 return SDValue();
4859
4860 SDLoc DL(N);
4861 EVT VT = N->getValueType(0);
4862
4863 // tmp = x 'opposite logical shift' y
4864 SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y);
4865 // ret = tmp 'logical shift' y
4866 SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y);
4867
4868 return T1;
4869}
4870
4871SDValue DAGCombiner::visitAND(SDNode *N) {
4872 SDValue N0 = N->getOperand(0);
4873 SDValue N1 = N->getOperand(1);
4874 EVT VT = N1.getValueType();
4875
4876 // x & x --> x
4877 if (N0 == N1)
4878 return N0;
4879
4880 // fold vector ops
4881 if (VT.isVector()) {
4882 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4883 return FoldedVOp;
4884
4885 // fold (and x, 0) -> 0, vector edition
4886 if (ISD::isBuildVectorAllZeros(N0.getNode()))
4887 // do not return N0, because undef node may exist in N0
4888 return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()),
4889 SDLoc(N), N0.getValueType());
4890 if (ISD::isBuildVectorAllZeros(N1.getNode()))
4891 // do not return N1, because undef node may exist in N1
4892 return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()),
4893 SDLoc(N), N1.getValueType());
4894
4895 // fold (and x, -1) -> x, vector edition
4896 if (ISD::isBuildVectorAllOnes(N0.getNode()))
4897 return N1;
4898 if (ISD::isBuildVectorAllOnes(N1.getNode()))
4899 return N0;
4900 }
4901
4902 // fold (and c1, c2) -> c1&c2
4903 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4904 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4905 if (N0C && N1C && !N1C->isOpaque())
4906 return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C);
4907 // canonicalize constant to RHS
4908 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4909 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4910 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
4911 // fold (and x, -1) -> x
4912 if (isAllOnesConstant(N1))
4913 return N0;
4914 // if (and x, c) is known to be zero, return 0
4915 unsigned BitWidth = VT.getScalarSizeInBits();
4916 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4917 APInt::getAllOnesValue(BitWidth)))
4918 return DAG.getConstant(0, SDLoc(N), VT);
4919
4920 if (SDValue NewSel = foldBinOpIntoSelect(N))
4921 return NewSel;
4922
4923 // reassociate and
4924 if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
4925 return RAND;
4926
4927 // Try to convert a constant mask AND into a shuffle clear mask.
4928 if (VT.isVector())
4929 if (SDValue Shuffle = XformToShuffleWithZero(N))
4930 return Shuffle;
4931
4932 // fold (and (or x, C), D) -> D if (C & D) == D
4933 auto MatchSubset = [](ConstantSDNode *LHS, ConstantSDNode *RHS) {
4934 return RHS->getAPIntValue().isSubsetOf(LHS->getAPIntValue());
4935 };
4936 if (N0.getOpcode() == ISD::OR &&
4937 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset))
4938 return N1;
4939 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
4940 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4941 SDValue N0Op0 = N0.getOperand(0);
4942 APInt Mask = ~N1C->getAPIntValue();
4943 Mask = Mask.trunc(N0Op0.getScalarValueSizeInBits());
4944 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
4945 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4946 N0.getValueType(), N0Op0);
4947
4948 // Replace uses of the AND with uses of the Zero extend node.
4949 CombineTo(N, Zext);
4950
4951 // We actually want to replace all uses of the any_extend with the
4952 // zero_extend, to avoid duplicating things. This will later cause this
4953 // AND to be folded.
4954 CombineTo(N0.getNode(), Zext);
4955 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4956 }
4957 }
4958 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
4959 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
4960 // already be zero by virtue of the width of the base type of the load.
4961 //
4962 // the 'X' node here can either be nothing or an extract_vector_elt to catch
4963 // more cases.
4964 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4965 N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
4966 N0.getOperand(0).getOpcode() == ISD::LOAD &&
4967 N0.getOperand(0).getResNo() == 0) ||
4968 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
4969 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
4970 N0 : N0.getOperand(0) );
4971
4972 // Get the constant (if applicable) the zero'th operand is being ANDed with.
4973 // This can be a pure constant or a vector splat, in which case we treat the
4974 // vector as a scalar and use the splat value.
4975 APInt Constant = APInt::getNullValue(1);
4976 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
4977 Constant = C->getAPIntValue();
4978 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
4979 APInt SplatValue, SplatUndef;
4980 unsigned SplatBitSize;
4981 bool HasAnyUndefs;
4982 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
4983 SplatBitSize, HasAnyUndefs);
4984 if (IsSplat) {
4985 // Undef bits can contribute to a possible optimisation if set, so
4986 // set them.
4987 SplatValue |= SplatUndef;
4988
4989 // The splat value may be something like "0x00FFFFFF", which means 0 for
4990 // the first vector value and FF for the rest, repeating. We need a mask
4991 // that will apply equally to all members of the vector, so AND all the
4992 // lanes of the constant together.
4993 EVT VT = Vector->getValueType(0);
4994 unsigned BitWidth = VT.getScalarSizeInBits();
4995
4996 // If the splat value has been compressed to a bitlength lower
4997 // than the size of the vector lane, we need to re-expand it to
4998 // the lane size.
4999 if (BitWidth > SplatBitSize)
5000 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
5001 SplatBitSize < BitWidth;
5002 SplatBitSize = SplatBitSize * 2)
5003 SplatValue |= SplatValue.shl(SplatBitSize);
5004
5005 // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
5006 // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
5007 if (SplatBitSize % BitWidth == 0) {
5008 Constant = APInt::getAllOnesValue(BitWidth);
5009 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
5010 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
5011 }
5012 }
5013 }
5014
5015 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
5016 // actually legal and isn't going to get expanded, else this is a false
5017 // optimisation.
5018 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
5019 Load->getValueType(0),
5020 Load->getMemoryVT());
5021
5022 // Resize the constant to the same size as the original memory access before
5023 // extension. If it is still the AllOnesValue then this AND is completely
5024 // unneeded.
5025 Constant = Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits());
5026
5027 bool B;
5028 switch (Load->getExtensionType()) {
5029 default: B = false; break;
5030 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
5031 case ISD::ZEXTLOAD:
5032 case ISD::NON_EXTLOAD: B = true; break;
5033 }
5034
5035 if (B && Constant.isAllOnesValue()) {
5036 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
5037 // preserve semantics once we get rid of the AND.
5038 SDValue NewLoad(Load, 0);
5039
5040 // Fold the AND away. NewLoad may get replaced immediately.
5041 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
5042
5043 if (Load->getExtensionType() == ISD::EXTLOAD) {
5044 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
5045 Load->getValueType(0), SDLoc(Load),
5046 Load->getChain(), Load->getBasePtr(),
5047 Load->getOffset(), Load->getMemoryVT(),
5048 Load->getMemOperand());
5049 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
5050 if (Load->getNumValues() == 3) {
5051 // PRE/POST_INC loads have 3 values.
5052 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
5053 NewLoad.getValue(2) };
5054 CombineTo(Load, To, 3, true);
5055 } else {
5056 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
5057 }
5058 }
5059
5060 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5061 }
5062 }
5063
5064 // fold (and (load x), 255) -> (zextload x, i8)
5065 // fold (and (extload x, i16), 255) -> (zextload x, i8)
5066 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
5067 if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
5068 (N0.getOpcode() == ISD::ANY_EXTEND &&
5069 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
5070 if (SDValue Res = ReduceLoadWidth(N)) {
5071 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
5072 ? cast<LoadSDNode>(N0.getOperand(0)) : cast<LoadSDNode>(N0);
5073 AddToWorklist(N);
5074 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 0), Res);
5075 return SDValue(N, 0);
5076 }
5077 }
5078
5079 if (Level >= AfterLegalizeTypes) {
5080 // Attempt to propagate the AND back up to the leaves which, if they're
5081 // loads, can be combined to narrow loads and the AND node can be removed.
5082 // Perform after legalization so that extend nodes will already be
5083 // combined into the loads.
5084 if (BackwardsPropagateMask(N, DAG)) {
5085 return SDValue(N, 0);
5086 }
5087 }
5088
5089 if (SDValue Combined = visitANDLike(N0, N1, N))
5090 return Combined;
5091
5092 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
5093 if (N0.getOpcode() == N1.getOpcode())
5094 if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
5095 return V;
5096
5097 // Masking the negated extension of a boolean is just the zero-extended
5098 // boolean:
5099 // and (sub 0, zext(bool X)), 1 --> zext(bool X)
5100 // and (sub 0, sext(bool X)), 1 --> zext(bool X)
5101 //
5102 // Note: the SimplifyDemandedBits fold below can make an information-losing
5103 // transform, and then we have no way to find this better fold.
5104 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
5105 if (isNullOrNullSplat(N0.getOperand(0))) {
5106 SDValue SubRHS = N0.getOperand(1);
5107 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
5108 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
5109 return SubRHS;
5110 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND &&
5111 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
5112 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0));
5113 }
5114 }
5115
5116 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
5117 // fold (and (sra)) -> (and (srl)) when possible.
5118 if (SimplifyDemandedBits(SDValue(N, 0)))
5119 return SDValue(N, 0);
5120
5121 // fold (zext_inreg (extload x)) -> (zextload x)
5122 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
5123 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5124 EVT MemVT = LN0->getMemoryVT();
5125 // If we zero all the possible extended bits, then we can turn this into
5126 // a zextload if we are running before legalize or the operation is legal.
5127 unsigned BitWidth = N1.getScalarValueSizeInBits();
5128 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
5129 BitWidth - MemVT.getScalarSizeInBits())) &&
5130 ((!LegalOperations && !LN0->isVolatile()) ||
5131 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
5132 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
5133 LN0->getChain(), LN0->getBasePtr(),
5134 MemVT, LN0->getMemOperand());
5135 AddToWorklist(N);
5136 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5137 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5138 }
5139 }
5140 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
5141 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5142 N0.hasOneUse()) {
5143 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5144 EVT MemVT = LN0->getMemoryVT();
5145 // If we zero all the possible extended bits, then we can turn this into
5146 // a zextload if we are running before legalize or the operation is legal.
5147 unsigned BitWidth = N1.getScalarValueSizeInBits();
5148 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
5149 BitWidth - MemVT.getScalarSizeInBits())) &&
5150 ((!LegalOperations && !LN0->isVolatile()) ||
5151 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
5152 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
5153 LN0->getChain(), LN0->getBasePtr(),
5154 MemVT, LN0->getMemOperand());
5155 AddToWorklist(N);
5156 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5157 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5158 }
5159 }
5160 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
5161 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
5162 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5163 N0.getOperand(1), false))
5164 return BSwap;
5165 }
5166
5167 if (SDValue Shifts = unfoldExtremeBitClearingToShifts(N))
5168 return Shifts;
5169
5170 return SDValue();
5171}
5172
5173/// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
5174SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
5175 bool DemandHighBits) {
5176 if (!LegalOperations)
5177 return SDValue();
5178
5179 EVT VT = N->getValueType(0);
5180 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
5181 return SDValue();
5182 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5183 return SDValue();
5184
5185 // Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff)
5186 bool LookPassAnd0 = false;
5187 bool LookPassAnd1 = false;
5188 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
5189 std::swap(N0, N1);
5190 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
5191 std::swap(N0, N1);
5192 if (N0.getOpcode() == ISD::AND) {
5193 if (!N0.getNode()->hasOneUse())
5194 return SDValue();
5195 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5196 // Also handle 0xffff since the LHS is guaranteed to have zeros there.
5197 // This is needed for X86.
5198 if (!N01C || (N01C->getZExtValue() != 0xFF00 &&
5199 N01C->getZExtValue() != 0xFFFF))
5200 return SDValue();
5201 N0 = N0.getOperand(0);
5202 LookPassAnd0 = true;
5203 }
5204
5205 if (N1.getOpcode() == ISD::AND) {
5206 if (!N1.getNode()->hasOneUse())
5207 return SDValue();
5208 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5209 if (!N11C || N11C->getZExtValue() != 0xFF)
5210 return SDValue();
5211 N1 = N1.getOperand(0);
5212 LookPassAnd1 = true;
5213 }
5214
5215 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
5216 std::swap(N0, N1);
5217 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
5218 return SDValue();
5219 if (!N0.getNode()->hasOneUse() || !N1.getNode()->hasOneUse())
5220 return SDValue();
5221
5222 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5223 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5224 if (!N01C || !N11C)
5225 return SDValue();
5226 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
5227 return SDValue();
5228
5229 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
5230 SDValue N00 = N0->getOperand(0);
5231 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
5232 if (!N00.getNode()->hasOneUse())
5233 return SDValue();
5234 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
5235 if (!N001C || N001C->getZExtValue() != 0xFF)
5236 return SDValue();
5237 N00 = N00.getOperand(0);
5238 LookPassAnd0 = true;
5239 }
5240
5241 SDValue N10 = N1->getOperand(0);
5242 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
5243 if (!N10.getNode()->hasOneUse())
5244 return SDValue();
5245 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
5246 // Also allow 0xFFFF since the bits will be shifted out. This is needed
5247 // for X86.
5248 if (!N101C || (N101C->getZExtValue() != 0xFF00 &&
5249 N101C->getZExtValue() != 0xFFFF))
5250 return SDValue();
5251 N10 = N10.getOperand(0);
5252 LookPassAnd1 = true;
5253 }
5254
5255 if (N00 != N10)
5256 return SDValue();
5257
5258 // Make sure everything beyond the low halfword gets set to zero since the SRL
5259 // 16 will clear the top bits.
5260 unsigned OpSizeInBits = VT.getSizeInBits();
5261 if (DemandHighBits && OpSizeInBits > 16) {
5262 // If the left-shift isn't masked out then the only way this is a bswap is
5263 // if all bits beyond the low 8 are 0. In that case the entire pattern
5264 // reduces to a left shift anyway: leave it for other parts of the combiner.
5265 if (!LookPassAnd0)
5266 return SDValue();
5267
5268 // However, if the right shift isn't masked out then it might be because
5269 // it's not needed. See if we can spot that too.
5270 if (!LookPassAnd1 &&
5271 !DAG.MaskedValueIsZero(
5272 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
5273 return SDValue();
5274 }
5275
5276 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
5277 if (OpSizeInBits > 16) {
5278 SDLoc DL(N);
5279 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
5280 DAG.getConstant(OpSizeInBits - 16, DL,
5281 getShiftAmountTy(VT)));
5282 }
5283 return Res;
5284}
5285
5286/// Return true if the specified node is an element that makes up a 32-bit
5287/// packed halfword byteswap.
5288/// ((x & 0x000000ff) << 8) |
5289/// ((x & 0x0000ff00) >> 8) |
5290/// ((x & 0x00ff0000) << 8) |
5291/// ((x & 0xff000000) >> 8)
5292static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
5293 if (!N.getNode()->hasOneUse())
5294 return false;
5295
5296 unsigned Opc = N.getOpcode();
5297 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
5298 return false;
5299
5300 SDValue N0 = N.getOperand(0);
5301 unsigned Opc0 = N0.getOpcode();
5302 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
5303 return false;
5304
5305 ConstantSDNode *N1C = nullptr;
5306 // SHL or SRL: look upstream for AND mask operand
5307 if (Opc == ISD::AND)
5308 N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5309 else if (Opc0 == ISD::AND)
5310 N1C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5311 if (!N1C)
5312 return false;
5313
5314 unsigned MaskByteOffset;
5315 switch (N1C->getZExtValue()) {
5316 default:
5317 return false;
5318 case 0xFF: MaskByteOffset = 0; break;
5319 case 0xFF00: MaskByteOffset = 1; break;
5320 case 0xFFFF:
5321 // In case demanded bits didn't clear the bits that will be shifted out.
5322 // This is needed for X86.
5323 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) {
5324 MaskByteOffset = 1;
5325 break;
5326 }
5327 return false;
5328 case 0xFF0000: MaskByteOffset = 2; break;
5329 case 0xFF000000: MaskByteOffset = 3; break;
5330 }
5331
5332 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
5333 if (Opc == ISD::AND) {
5334 if (MaskByteOffset == 0 || MaskByteOffset == 2) {
5335 // (x >> 8) & 0xff
5336 // (x >> 8) & 0xff0000
5337 if (Opc0 != ISD::SRL)
5338 return false;
5339 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5340 if (!C || C->getZExtValue() != 8)
5341 return false;
5342 } else {
5343 // (x << 8) & 0xff00
5344 // (x << 8) & 0xff000000
5345 if (Opc0 != ISD::SHL)
5346 return false;
5347 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5348 if (!C || C->getZExtValue() != 8)
5349 return false;
5350 }
5351 } else if (Opc == ISD::SHL) {
5352 // (x & 0xff) << 8
5353 // (x & 0xff0000) << 8
5354 if (MaskByteOffset != 0 && MaskByteOffset != 2)
5355 return false;
5356 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5357 if (!C || C->getZExtValue() != 8)
5358 return false;
5359 } else { // Opc == ISD::SRL
5360 // (x & 0xff00) >> 8
5361 // (x & 0xff000000) >> 8
5362 if (MaskByteOffset != 1 && MaskByteOffset != 3)
5363 return false;
5364 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5365 if (!C || C->getZExtValue() != 8)
5366 return false;
5367 }
5368
5369 if (Parts[MaskByteOffset])
5370 return false;
5371
5372 Parts[MaskByteOffset] = N0.getOperand(0).getNode();
5373 return true;
5374}
5375
5376/// Match a 32-bit packed halfword bswap. That is
5377/// ((x & 0x000000ff) << 8) |
5378/// ((x & 0x0000ff00) >> 8) |
5379/// ((x & 0x00ff0000) << 8) |
5380/// ((x & 0xff000000) >> 8)
5381/// => (rotl (bswap x), 16)
5382SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
5383 if (!LegalOperations)
5384 return SDValue();
5385
5386 EVT VT = N->getValueType(0);
5387 if (VT != MVT::i32)
5388 return SDValue();
5389 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5390 return SDValue();
5391
5392 // Look for either
5393 // (or (or (and), (and)), (or (and), (and)))
5394 // (or (or (or (and), (and)), (and)), (and))
5395 if (N0.getOpcode() != ISD::OR)
5396 return SDValue();
5397 SDValue N00 = N0.getOperand(0);
5398 SDValue N01 = N0.getOperand(1);
5399 SDNode *Parts[4] = {};
5400
5401 if (N1.getOpcode() == ISD::OR &&
5402 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
5403 // (or (or (and), (and)), (or (and), (and)))
5404 if (!isBSwapHWordElement(N00, Parts))
5405 return SDValue();
5406
5407 if (!isBSwapHWordElement(N01, Parts))
5408 return SDValue();
5409 SDValue N10 = N1.getOperand(0);
5410 if (!isBSwapHWordElement(N10, Parts))
5411 return SDValue();
5412 SDValue N11 = N1.getOperand(1);
5413 if (!isBSwapHWordElement(N11, Parts))
5414 return SDValue();
5415 } else {
5416 // (or (or (or (and), (and)), (and)), (and))
5417 if (!isBSwapHWordElement(N1, Parts))
5418 return SDValue();
5419 if (!isBSwapHWordElement(N01, Parts))
5420 return SDValue();
5421 if (N00.getOpcode() != ISD::OR)
5422 return SDValue();
5423 SDValue N000 = N00.getOperand(0);
5424 if (!isBSwapHWordElement(N000, Parts))
5425 return SDValue();
5426 SDValue N001 = N00.getOperand(1);
5427 if (!isBSwapHWordElement(N001, Parts))
5428 return SDValue();
5429 }
5430
5431 // Make sure the parts are all coming from the same node.
5432 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
5433 return SDValue();
5434
5435 SDLoc DL(N);
5436 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
5437 SDValue(Parts[0], 0));
5438
5439 // Result of the bswap should be rotated by 16. If it's not legal, then
5440 // do (x << 16) | (x >> 16).
5441 SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT));
5442 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
5443 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
5444 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
5445 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
5446 return DAG.getNode(ISD::OR, DL, VT,
5447 DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt),
5448 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
5449}
5450
5451/// This contains all DAGCombine rules which reduce two values combined by
5452/// an Or operation to a single value \see visitANDLike().
5453SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *N) {
5454 EVT VT = N1.getValueType();
5455 SDLoc DL(N);
5456
5457 // fold (or x, undef) -> -1
5458 if (!LegalOperations && (N0.isUndef() || N1.isUndef()))
5459 return DAG.getAllOnesConstant(DL, VT);
5460
5461 if (SDValue V = foldLogicOfSetCCs(false, N0, N1, DL))
5462 return V;
5463
5464 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
5465 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
5466 // Don't increase # computations.
5467 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
5468 // We can only do this xform if we know that bits from X that are set in C2
5469 // but not in C1 are already zero. Likewise for Y.
5470 if (const ConstantSDNode *N0O1C =
5471 getAsNonOpaqueConstant(N0.getOperand(1))) {
5472 if (const ConstantSDNode *N1O1C =
5473 getAsNonOpaqueConstant(N1.getOperand(1))) {
5474 // We can only do this xform if we know that bits from X that are set in
5475 // C2 but not in C1 are already zero. Likewise for Y.
5476 const APInt &LHSMask = N0O1C->getAPIntValue();
5477 const APInt &RHSMask = N1O1C->getAPIntValue();
5478
5479 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
5480 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
5481 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
5482 N0.getOperand(0), N1.getOperand(0));
5483 return DAG.getNode(ISD::AND, DL, VT, X,
5484 DAG.getConstant(LHSMask | RHSMask, DL, VT));
5485 }
5486 }
5487 }
5488 }
5489
5490 // (or (and X, M), (and X, N)) -> (and X, (or M, N))
5491 if (N0.getOpcode() == ISD::AND &&
5492 N1.getOpcode() == ISD::AND &&
5493 N0.getOperand(0) == N1.getOperand(0) &&
5494 // Don't increase # computations.
5495 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
5496 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
5497 N0.getOperand(1), N1.getOperand(1));
5498 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X);
5499 }
5500
5501 return SDValue();
5502}
5503
5504/// OR combines for which the commuted variant will be tried as well.
5505static SDValue visitORCommutative(
5506 SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N) {
5507 EVT VT = N0.getValueType();
5508 if (N0.getOpcode() == ISD::AND) {
5509 // fold (or (and X, (xor Y, -1)), Y) -> (or X, Y)
5510 if (isBitwiseNot(N0.getOperand(1)) && N0.getOperand(1).getOperand(0) == N1)
5511 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(0), N1);
5512
5513 // fold (or (and (xor Y, -1), X), Y) -> (or X, Y)
5514 if (isBitwiseNot(N0.getOperand(0)) && N0.getOperand(0).getOperand(0) == N1)
5515 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(1), N1);
5516 }
5517
5518 return SDValue();
5519}
5520
5521SDValue DAGCombiner::visitOR(SDNode *N) {
5522 SDValue N0 = N->getOperand(0);
5523 SDValue N1 = N->getOperand(1);
5524 EVT VT = N1.getValueType();
5525
5526 // x | x --> x
5527 if (N0 == N1)
5528 return N0;
5529
5530 // fold vector ops
5531 if (VT.isVector()) {
5532 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5533 return FoldedVOp;
5534
5535 // fold (or x, 0) -> x, vector edition
5536 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5537 return N1;
5538 if (ISD::isBuildVectorAllZeros(N1.getNode()))
5539 return N0;
5540
5541 // fold (or x, -1) -> -1, vector edition
5542 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5543 // do not return N0, because undef node may exist in N0
5544 return DAG.getAllOnesConstant(SDLoc(N), N0.getValueType());
5545 if (ISD::isBuildVectorAllOnes(N1.getNode()))
5546 // do not return N1, because undef node may exist in N1
5547 return DAG.getAllOnesConstant(SDLoc(N), N1.getValueType());
5548
5549 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask)
5550 // Do this only if the resulting shuffle is legal.
5551 if (isa<ShuffleVectorSDNode>(N0) &&
5552 isa<ShuffleVectorSDNode>(N1) &&
5553 // Avoid folding a node with illegal type.
5554 TLI.isTypeLegal(VT)) {
5555 bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode());
5556 bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode());
5557 bool ZeroN10 = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
5558 bool ZeroN11 = ISD::isBuildVectorAllZeros(N1.getOperand(1).getNode());
5559 // Ensure both shuffles have a zero input.
5560 if ((ZeroN00 != ZeroN01) && (ZeroN10 != ZeroN11)) {
5561 assert((!ZeroN00 || !ZeroN01) && "Both inputs zero!")(((!ZeroN00 || !ZeroN01) && "Both inputs zero!") ? static_cast
<void> (0) : __assert_fail ("(!ZeroN00 || !ZeroN01) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5561, __PRETTY_FUNCTION__))
;
5562 assert((!ZeroN10 || !ZeroN11) && "Both inputs zero!")(((!ZeroN10 || !ZeroN11) && "Both inputs zero!") ? static_cast
<void> (0) : __assert_fail ("(!ZeroN10 || !ZeroN11) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5562, __PRETTY_FUNCTION__))
;
5563 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
5564 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
5565 bool CanFold = true;
5566 int NumElts = VT.getVectorNumElements();
5567 SmallVector<int, 4> Mask(NumElts);
5568
5569 for (int i = 0; i != NumElts; ++i) {
5570 int M0 = SV0->getMaskElt(i);
5571 int M1 = SV1->getMaskElt(i);
5572
5573 // Determine if either index is pointing to a zero vector.
5574 bool M0Zero = M0 < 0 || (ZeroN00 == (M0 < NumElts));
5575 bool M1Zero = M1 < 0 || (ZeroN10 == (M1 < NumElts));
5576
5577 // If one element is zero and the otherside is undef, keep undef.
5578 // This also handles the case that both are undef.
5579 if ((M0Zero && M1 < 0) || (M1Zero && M0 < 0)) {
5580 Mask[i] = -1;
5581 continue;
5582 }
5583
5584 // Make sure only one of the elements is zero.
5585 if (M0Zero == M1Zero) {
5586 CanFold = false;
5587 break;
5588 }
5589
5590 assert((M0 >= 0 || M1 >= 0) && "Undef index!")(((M0 >= 0 || M1 >= 0) && "Undef index!") ? static_cast
<void> (0) : __assert_fail ("(M0 >= 0 || M1 >= 0) && \"Undef index!\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5590, __PRETTY_FUNCTION__))
;
5591
5592 // We have a zero and non-zero element. If the non-zero came from
5593 // SV0 make the index a LHS index. If it came from SV1, make it
5594 // a RHS index. We need to mod by NumElts because we don't care
5595 // which operand it came from in the original shuffles.
5596 Mask[i] = M1Zero ? M0 % NumElts : (M1 % NumElts) + NumElts;
5597 }
5598
5599 if (CanFold) {
5600 SDValue NewLHS = ZeroN00 ? N0.getOperand(1) : N0.getOperand(0);
5601 SDValue NewRHS = ZeroN10 ? N1.getOperand(1) : N1.getOperand(0);
5602
5603 bool LegalMask = TLI.isShuffleMaskLegal(Mask, VT);
5604 if (!LegalMask) {
5605 std::swap(NewLHS, NewRHS);
5606 ShuffleVectorSDNode::commuteMask(Mask);
5607 LegalMask = TLI.isShuffleMaskLegal(Mask, VT);
5608 }
5609
5610 if (LegalMask)
5611 return DAG.getVectorShuffle(VT, SDLoc(N), NewLHS, NewRHS, Mask);
5612 }
5613 }
5614 }
5615 }
5616
5617 // fold (or c1, c2) -> c1|c2
5618 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
5619 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5620 if (N0C && N1C && !N1C->isOpaque())
5621 return DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, N0C, N1C);
5622 // canonicalize constant to RHS
5623 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5624 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
5625 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
5626 // fold (or x, 0) -> x
5627 if (isNullConstant(N1))
5628 return N0;
5629 // fold (or x, -1) -> -1
5630 if (isAllOnesConstant(N1))
5631 return N1;
5632
5633 if (SDValue NewSel = foldBinOpIntoSelect(N))
5634 return NewSel;
5635
5636 // fold (or x, c) -> c iff (x & ~c) == 0
5637 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
5638 return N1;
5639
5640 if (SDValue Combined = visitORLike(N0, N1, N))
5641 return Combined;
5642
5643 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
5644 if (SDValue BSwap = MatchBSwapHWord(N, N0, N1))
5645 return BSwap;
5646 if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1))
5647 return BSwap;
5648
5649 // reassociate or
5650 if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags()))
5651 return ROR;
5652
5653 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
5654 // iff (c1 & c2) != 0 or c1/c2 are undef.
5655 auto MatchIntersect = [](ConstantSDNode *C1, ConstantSDNode *C2) {
5656 return !C1 || !C2 || C1->getAPIntValue().intersects(C2->getAPIntValue());
5657 };
5658 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
5659 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchIntersect, true)) {
5660 if (SDValue COR = DAG.FoldConstantArithmetic(
5661 ISD::OR, SDLoc(N1), VT, N1.getNode(), N0.getOperand(1).getNode())) {
5662 SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1);
5663 AddToWorklist(IOR.getNode());
5664 return DAG.getNode(ISD::AND, SDLoc(N), VT, COR, IOR);
5665 }
5666 }
5667
5668 if (SDValue Combined = visitORCommutative(DAG, N0, N1, N))
5669 return Combined;
5670 if (SDValue Combined = visitORCommutative(DAG, N1, N0, N))
5671 return Combined;
5672
5673 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
5674 if (N0.getOpcode() == N1.getOpcode())
5675 if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
5676 return V;
5677
5678 // See if this is some rotate idiom.
5679 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
5680 return SDValue(Rot, 0);
5681
5682 if (SDValue Load = MatchLoadCombine(N))
5683 return Load;
5684
5685 // Simplify the operands using demanded-bits information.
5686 if (SimplifyDemandedBits(SDValue(N, 0)))
5687 return SDValue(N, 0);
5688
5689 // If OR can be rewritten into ADD, try combines based on ADD.
5690 if ((!LegalOperations || TLI.isOperationLegal(ISD::ADD, VT)) &&
5691 DAG.haveNoCommonBitsSet(N0, N1))
5692 if (SDValue Combined = visitADDLike(N))
5693 return Combined;
5694
5695 return SDValue();
5696}
5697
5698static SDValue stripConstantMask(SelectionDAG &DAG, SDValue Op, SDValue &Mask) {
5699 if (Op.getOpcode() == ISD::AND &&
5700 DAG.isConstantIntBuildVectorOrConstantInt(Op.getOperand(1))) {
5701 Mask = Op.getOperand(1);
5702 return Op.getOperand(0);
5703 }
5704 return Op;
5705}
5706
5707/// Match "(X shl/srl V1) & V2" where V2 may not be present.
5708static bool matchRotateHalf(SelectionDAG &DAG, SDValue Op, SDValue &Shift,
5709 SDValue &Mask) {
5710 Op = stripConstantMask(DAG, Op, Mask);
5711 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
5712 Shift = Op;
5713 return true;
5714 }
5715 return false;
5716}
5717
5718/// Helper function for visitOR to extract the needed side of a rotate idiom
5719/// from a shl/srl/mul/udiv. This is meant to handle cases where
5720/// InstCombine merged some outside op with one of the shifts from
5721/// the rotate pattern.
5722/// \returns An empty \c SDValue if the needed shift couldn't be extracted.
5723/// Otherwise, returns an expansion of \p ExtractFrom based on the following
5724/// patterns:
5725///
5726/// (or (mul v c0) (shrl (mul v c1) c2)):
5727/// expands (mul v c0) -> (shl (mul v c1) c3)
5728///
5729/// (or (udiv v c0) (shl (udiv v c1) c2)):
5730/// expands (udiv v c0) -> (shrl (udiv v c1) c3)
5731///
5732/// (or (shl v c0) (shrl (shl v c1) c2)):
5733/// expands (shl v c0) -> (shl (shl v c1) c3)
5734///
5735/// (or (shrl v c0) (shl (shrl v c1) c2)):
5736/// expands (shrl v c0) -> (shrl (shrl v c1) c3)
5737///
5738/// Such that in all cases, c3+c2==bitwidth(op v c1).
5739static SDValue extractShiftForRotate(SelectionDAG &DAG, SDValue OppShift,
5740 SDValue ExtractFrom, SDValue &Mask,
5741 const SDLoc &DL) {
5742 assert(OppShift && ExtractFrom && "Empty SDValue")((OppShift && ExtractFrom && "Empty SDValue")
? static_cast<void> (0) : __assert_fail ("OppShift && ExtractFrom && \"Empty SDValue\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5742, __PRETTY_FUNCTION__))
;
5743 assert((((OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() ==
ISD::SRL) && "Existing shift must be valid as a rotate half"
) ? static_cast<void> (0) : __assert_fail ("(OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) && \"Existing shift must be valid as a rotate half\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5745, __PRETTY_FUNCTION__))
5744 (OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) &&(((OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() ==
ISD::SRL) && "Existing shift must be valid as a rotate half"
) ? static_cast<void> (0) : __assert_fail ("(OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) && \"Existing shift must be valid as a rotate half\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5745, __PRETTY_FUNCTION__))
5745 "Existing shift must be valid as a rotate half")(((OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() ==
ISD::SRL) && "Existing shift must be valid as a rotate half"
) ? static_cast<void> (0) : __assert_fail ("(OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) && \"Existing shift must be valid as a rotate half\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5745, __PRETTY_FUNCTION__))
;
5746
5747 ExtractFrom = stripConstantMask(DAG, ExtractFrom, Mask);
5748 // Preconditions:
5749 // (or (op0 v c0) (shiftl/r (op0 v c1) c2))
5750 //
5751 // Find opcode of the needed shift to be extracted from (op0 v c0).
5752 unsigned Opcode = ISD::DELETED_NODE;
5753 bool IsMulOrDiv = false;
5754 // Set Opcode and IsMulOrDiv if the extract opcode matches the needed shift
5755 // opcode or its arithmetic (mul or udiv) variant.
5756 auto SelectOpcode = [&](unsigned NeededShift, unsigned MulOrDivVariant) {
5757 IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant;
5758 if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift)
5759 return false;
5760 Opcode = NeededShift;
5761 return true;
5762 };
5763 // op0 must be either the needed shift opcode or the mul/udiv equivalent
5764 // that the needed shift can be extracted from.
5765 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) &&
5766 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV)))
5767 return SDValue();
5768
5769 // op0 must be the same opcode on both sides, have the same LHS argument,
5770 // and produce the same value type.
5771 SDValue OppShiftLHS = OppShift.getOperand(0);
5772 EVT ShiftedVT = OppShiftLHS.getValueType();
5773 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() ||
5774 OppShiftLHS.getOperand(0) != ExtractFrom.getOperand(0) ||
5775 ShiftedVT != ExtractFrom.getValueType())
5776 return SDValue();
5777
5778 // Amount of the existing shift.
5779 ConstantSDNode *OppShiftCst = isConstOrConstSplat(OppShift.getOperand(1));
5780 // Constant mul/udiv/shift amount from the RHS of the shift's LHS op.
5781 ConstantSDNode *OppLHSCst = isConstOrConstSplat(OppShiftLHS.getOperand(1));
5782 // Constant mul/udiv/shift amount from the RHS of the ExtractFrom op.
5783 ConstantSDNode *ExtractFromCst =
5784 isConstOrConstSplat(ExtractFrom.getOperand(1));
5785 // TODO: We should be able to handle non-uniform constant vectors for these values
5786 // Check that we have constant values.
5787 if (!OppShiftCst || !OppShiftCst->getAPIntValue() ||
5788 !OppLHSCst || !OppLHSCst->getAPIntValue() ||
5789 !ExtractFromCst || !ExtractFromCst->getAPIntValue())
5790 return SDValue();
5791
5792 // Compute the shift amount we need to extract to complete the rotate.
5793 const unsigned VTWidth = ShiftedVT.getScalarSizeInBits();
5794 if (OppShiftCst->getAPIntValue().ugt(VTWidth))
5795 return SDValue();
5796 APInt NeededShiftAmt = VTWidth - OppShiftCst->getAPIntValue();
5797 // Normalize the bitwidth of the two mul/udiv/shift constant operands.
5798 APInt ExtractFromAmt = ExtractFromCst->getAPIntValue();
5799 APInt OppLHSAmt = OppLHSCst->getAPIntValue();
5800 zeroExtendToMatch(ExtractFromAmt, OppLHSAmt);
5801
5802 // Now try extract the needed shift from the ExtractFrom op and see if the
5803 // result matches up with the existing shift's LHS op.
5804 if (IsMulOrDiv) {
5805 // Op to extract from is a mul or udiv by a constant.
5806 // Check:
5807 // c2 / (1 << (bitwidth(op0 v c0) - c1)) == c0
5808 // c2 % (1 << (bitwidth(op0 v c0) - c1)) == 0
5809 const APInt ExtractDiv = APInt::getOneBitSet(ExtractFromAmt.getBitWidth(),
5810 NeededShiftAmt.getZExtValue());
5811 APInt ResultAmt;
5812 APInt Rem;
5813 APInt::udivrem(ExtractFromAmt, ExtractDiv, ResultAmt, Rem);
5814 if (Rem != 0 || ResultAmt != OppLHSAmt)
5815 return SDValue();
5816 } else {
5817 // Op to extract from is a shift by a constant.
5818 // Check:
5819 // c2 - (bitwidth(op0 v c0) - c1) == c0
5820 if (OppLHSAmt != ExtractFromAmt - NeededShiftAmt.zextOrTrunc(
5821 ExtractFromAmt.getBitWidth()))
5822 return SDValue();
5823 }
5824
5825 // Return the expanded shift op that should allow a rotate to be formed.
5826 EVT ShiftVT = OppShift.getOperand(1).getValueType();
5827 EVT ResVT = ExtractFrom.getValueType();
5828 SDValue NewShiftNode = DAG.getConstant(NeededShiftAmt, DL, ShiftVT);
5829 return DAG.getNode(Opcode, DL, ResVT, OppShiftLHS, NewShiftNode);
5830}
5831
5832// Return true if we can prove that, whenever Neg and Pos are both in the
5833// range [0, EltSize), Neg == (Pos == 0 ? 0 : EltSize - Pos). This means that
5834// for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
5835//
5836// (or (shift1 X, Neg), (shift2 X, Pos))
5837//
5838// reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
5839// in direction shift1 by Neg. The range [0, EltSize) means that we only need
5840// to consider shift amounts with defined behavior.
5841static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize,
5842 SelectionDAG &DAG) {
5843 // If EltSize is a power of 2 then:
5844 //
5845 // (a) (Pos == 0 ? 0 : EltSize - Pos) == (EltSize - Pos) & (EltSize - 1)
5846 // (b) Neg == Neg & (EltSize - 1) whenever Neg is in [0, EltSize).
5847 //
5848 // So if EltSize is a power of 2 and Neg is (and Neg', EltSize-1), we check
5849 // for the stronger condition:
5850 //
5851 // Neg & (EltSize - 1) == (EltSize - Pos) & (EltSize - 1) [A]
5852 //
5853 // for all Neg and Pos. Since Neg & (EltSize - 1) == Neg' & (EltSize - 1)
5854 // we can just replace Neg with Neg' for the rest of the function.
5855 //
5856 // In other cases we check for the even stronger condition:
5857 //
5858 // Neg == EltSize - Pos [B]
5859 //
5860 // for all Neg and Pos. Note that the (or ...) then invokes undefined
5861 // behavior if Pos == 0 (and consequently Neg == EltSize).
5862 //
5863 // We could actually use [A] whenever EltSize is a power of 2, but the
5864 // only extra cases that it would match are those uninteresting ones
5865 // where Neg and Pos are never in range at the same time. E.g. for
5866 // EltSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
5867 // as well as (sub 32, Pos), but:
5868 //
5869 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
5870 //
5871 // always invokes undefined behavior for 32-bit X.
5872 //
5873 // Below, Mask == EltSize - 1 when using [A] and is all-ones otherwise.
5874 unsigned MaskLoBits = 0;
5875 if (Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) {
5876 if (ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(1))) {
5877 KnownBits Known = DAG.computeKnownBits(Neg.getOperand(0));
5878 unsigned Bits = Log2_64(EltSize);
5879 if (NegC->getAPIntValue().getActiveBits() <= Bits &&
5880 ((NegC->getAPIntValue() | Known.Zero).countTrailingOnes() >= Bits)) {
5881 Neg = Neg.getOperand(0);
5882 MaskLoBits = Bits;
5883 }
5884 }
5885 }
5886
5887 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
5888 if (Neg.getOpcode() != ISD::SUB)
5889 return false;
5890 ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(0));
5891 if (!NegC)
5892 return false;
5893 SDValue NegOp1 = Neg.getOperand(1);
5894
5895 // On the RHS of [A], if Pos is Pos' & (EltSize - 1), just replace Pos with
5896 // Pos'. The truncation is redundant for the purpose of the equality.
5897 if (MaskLoBits && Pos.getOpcode() == ISD::AND) {
5898 if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1))) {
5899 KnownBits Known = DAG.computeKnownBits(Pos.getOperand(0));
5900 if (PosC->getAPIntValue().getActiveBits() <= MaskLoBits &&
5901 ((PosC->getAPIntValue() | Known.Zero).countTrailingOnes() >=
5902 MaskLoBits))
5903 Pos = Pos.getOperand(0);
5904 }
5905 }
5906
5907 // The condition we need is now:
5908 //
5909 // (NegC - NegOp1) & Mask == (EltSize - Pos) & Mask
5910 //
5911 // If NegOp1 == Pos then we need:
5912 //
5913 // EltSize & Mask == NegC & Mask
5914 //
5915 // (because "x & Mask" is a truncation and distributes through subtraction).
5916 APInt Width;
5917 if (Pos == NegOp1)
5918 Width = NegC->getAPIntValue();
5919
5920 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
5921 // Then the condition we want to prove becomes:
5922 //
5923 // (NegC - NegOp1) & Mask == (EltSize - (NegOp1 + PosC)) & Mask
5924 //
5925 // which, again because "x & Mask" is a truncation, becomes:
5926 //
5927 // NegC & Mask == (EltSize - PosC) & Mask
5928 // EltSize & Mask == (NegC + PosC) & Mask
5929 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) {
5930 if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1)))
5931 Width = PosC->getAPIntValue() + NegC->getAPIntValue();
5932 else
5933 return false;
5934 } else
5935 return false;
5936
5937 // Now we just need to check that EltSize & Mask == Width & Mask.
5938 if (MaskLoBits)
5939 // EltSize & Mask is 0 since Mask is EltSize - 1.
5940 return Width.getLoBits(MaskLoBits) == 0;
5941 return Width == EltSize;
5942}
5943
5944// A subroutine of MatchRotate used once we have found an OR of two opposite
5945// shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
5946// to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
5947// former being preferred if supported. InnerPos and InnerNeg are Pos and
5948// Neg with outer conversions stripped away.
5949SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
5950 SDValue Neg, SDValue InnerPos,
5951 SDValue InnerNeg, unsigned PosOpcode,
5952 unsigned NegOpcode, const SDLoc &DL) {
5953 // fold (or (shl x, (*ext y)),
5954 // (srl x, (*ext (sub 32, y)))) ->
5955 // (rotl x, y) or (rotr x, (sub 32, y))
5956 //
5957 // fold (or (shl x, (*ext (sub 32, y))),
5958 // (srl x, (*ext y))) ->
5959 // (rotr x, y) or (rotl x, (sub 32, y))
5960 EVT VT = Shifted.getValueType();
5961 if (matchRotateSub(InnerPos, InnerNeg, VT.getScalarSizeInBits(), DAG)) {
5962 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
5963 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
5964 HasPos ? Pos : Neg).getNode();
5965 }
5966
5967 return nullptr;
5968}
5969
5970// MatchRotate - Handle an 'or' of two operands. If this is one of the many
5971// idioms for rotate, and if the target supports rotation instructions, generate
5972// a rot[lr].
5973SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
5974 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
5975 EVT VT = LHS.getValueType();
5976 if (!TLI.isTypeLegal(VT)) return nullptr;
5977
5978 // The target must have at least one rotate flavor.
5979 bool HasROTL = hasOperation(ISD::ROTL, VT);
5980 bool HasROTR = hasOperation(ISD::ROTR, VT);
5981 if (!HasROTL && !HasROTR) return nullptr;
5982
5983 // Check for truncated rotate.
5984 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE &&
5985 LHS.getOperand(0).getValueType() == RHS.getOperand(0).getValueType()) {
5986 assert(LHS.getValueType() == RHS.getValueType())((LHS.getValueType() == RHS.getValueType()) ? static_cast<
void> (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType()"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5986, __PRETTY_FUNCTION__))
;
5987 if (SDNode *Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) {
5988 return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(),
5989 SDValue(Rot, 0)).getNode();
5990 }
5991 }
5992
5993 // Match "(X shl/srl V1) & V2" where V2 may not be present.
5994 SDValue LHSShift; // The shift.
5995 SDValue LHSMask; // AND value if any.
5996 matchRotateHalf(DAG, LHS, LHSShift, LHSMask);
5997
5998 SDValue RHSShift; // The shift.
5999 SDValue RHSMask; // AND value if any.
6000 matchRotateHalf(DAG, RHS, RHSShift, RHSMask);
6001
6002 // If neither side matched a rotate half, bail
6003 if (!LHSShift && !RHSShift)
6004 return nullptr;
6005
6006 // InstCombine may have combined a constant shl, srl, mul, or udiv with one
6007 // side of the rotate, so try to handle that here. In all cases we need to
6008 // pass the matched shift from the opposite side to compute the opcode and
6009 // needed shift amount to extract. We still want to do this if both sides
6010 // matched a rotate half because one half may be a potential overshift that
6011 // can be broken down (ie if InstCombine merged two shl or srl ops into a
6012 // single one).
6013
6014 // Have LHS side of the rotate, try to extract the needed shift from the RHS.
6015 if (LHSShift)
6016 if (SDValue NewRHSShift =
6017 extractShiftForRotate(DAG, LHSShift, RHS, RHSMask, DL))
6018 RHSShift = NewRHSShift;
6019 // Have RHS side of the rotate, try to extract the needed shif