Bug Summary

File:llvm/include/llvm/ADT/APInt.h
Warning:line 1000, column 15
Assigned value is garbage or undefined

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name DAGCombiner.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/build-llvm/lib/CodeGen/SelectionDAG -resource-dir /usr/lib/llvm-13/lib/clang/13.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/build-llvm/include -I /build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-13/lib/clang/13.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c=. -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-07-26-235520-9401-1 -x c++ /build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

1//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
10// both before and after the DAG is legalized.
11//
12// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
13// primarily intended to handle simplification opportunities that are implicit
14// in the LLVM IR and exposed by the various codegen lowering phases.
15//
16//===----------------------------------------------------------------------===//
17
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/ArrayRef.h"
21#include "llvm/ADT/DenseMap.h"
22#include "llvm/ADT/IntervalMap.h"
23#include "llvm/ADT/None.h"
24#include "llvm/ADT/Optional.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SetVector.h"
27#include "llvm/ADT/SmallBitVector.h"
28#include "llvm/ADT/SmallPtrSet.h"
29#include "llvm/ADT/SmallSet.h"
30#include "llvm/ADT/SmallVector.h"
31#include "llvm/ADT/Statistic.h"
32#include "llvm/Analysis/AliasAnalysis.h"
33#include "llvm/Analysis/MemoryLocation.h"
34#include "llvm/Analysis/TargetLibraryInfo.h"
35#include "llvm/Analysis/VectorUtils.h"
36#include "llvm/CodeGen/DAGCombine.h"
37#include "llvm/CodeGen/ISDOpcodes.h"
38#include "llvm/CodeGen/MachineFrameInfo.h"
39#include "llvm/CodeGen/MachineFunction.h"
40#include "llvm/CodeGen/MachineMemOperand.h"
41#include "llvm/CodeGen/RuntimeLibcalls.h"
42#include "llvm/CodeGen/SelectionDAG.h"
43#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
44#include "llvm/CodeGen/SelectionDAGNodes.h"
45#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
46#include "llvm/CodeGen/TargetLowering.h"
47#include "llvm/CodeGen/TargetRegisterInfo.h"
48#include "llvm/CodeGen/TargetSubtargetInfo.h"
49#include "llvm/CodeGen/ValueTypes.h"
50#include "llvm/IR/Attributes.h"
51#include "llvm/IR/Constant.h"
52#include "llvm/IR/DataLayout.h"
53#include "llvm/IR/DerivedTypes.h"
54#include "llvm/IR/Function.h"
55#include "llvm/IR/LLVMContext.h"
56#include "llvm/IR/Metadata.h"
57#include "llvm/Support/Casting.h"
58#include "llvm/Support/CodeGen.h"
59#include "llvm/Support/CommandLine.h"
60#include "llvm/Support/Compiler.h"
61#include "llvm/Support/Debug.h"
62#include "llvm/Support/ErrorHandling.h"
63#include "llvm/Support/KnownBits.h"
64#include "llvm/Support/MachineValueType.h"
65#include "llvm/Support/MathExtras.h"
66#include "llvm/Support/raw_ostream.h"
67#include "llvm/Target/TargetMachine.h"
68#include "llvm/Target/TargetOptions.h"
69#include <algorithm>
70#include <cassert>
71#include <cstdint>
72#include <functional>
73#include <iterator>
74#include <string>
75#include <tuple>
76#include <utility>
77
78using namespace llvm;
79
80#define DEBUG_TYPE"dagcombine" "dagcombine"
81
82STATISTIC(NodesCombined , "Number of dag nodes combined")static llvm::Statistic NodesCombined = {"dagcombine", "NodesCombined"
, "Number of dag nodes combined"}
;
83STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created")static llvm::Statistic PreIndexedNodes = {"dagcombine", "PreIndexedNodes"
, "Number of pre-indexed nodes created"}
;
84STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created")static llvm::Statistic PostIndexedNodes = {"dagcombine", "PostIndexedNodes"
, "Number of post-indexed nodes created"}
;
85STATISTIC(OpsNarrowed , "Number of load/op/store narrowed")static llvm::Statistic OpsNarrowed = {"dagcombine", "OpsNarrowed"
, "Number of load/op/store narrowed"}
;
86STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int")static llvm::Statistic LdStFP2Int = {"dagcombine", "LdStFP2Int"
, "Number of fp load/store pairs transformed to int"}
;
87STATISTIC(SlicedLoads, "Number of load sliced")static llvm::Statistic SlicedLoads = {"dagcombine", "SlicedLoads"
, "Number of load sliced"}
;
88STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops")static llvm::Statistic NumFPLogicOpsConv = {"dagcombine", "NumFPLogicOpsConv"
, "Number of logic ops converted to fp ops"}
;
89
90static cl::opt<bool>
91CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
92 cl::desc("Enable DAG combiner's use of IR alias analysis"));
93
94static cl::opt<bool>
95UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
96 cl::desc("Enable DAG combiner's use of TBAA"));
97
98#ifndef NDEBUG
99static cl::opt<std::string>
100CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
101 cl::desc("Only use DAG-combiner alias analysis in this"
102 " function"));
103#endif
104
105/// Hidden option to stress test load slicing, i.e., when this option
106/// is enabled, load slicing bypasses most of its profitability guards.
107static cl::opt<bool>
108StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
109 cl::desc("Bypass the profitability model of load slicing"),
110 cl::init(false));
111
112static cl::opt<bool>
113 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
114 cl::desc("DAG combiner may split indexing from loads"));
115
116static cl::opt<bool>
117 EnableStoreMerging("combiner-store-merging", cl::Hidden, cl::init(true),
118 cl::desc("DAG combiner enable merging multiple stores "
119 "into a wider store"));
120
121static cl::opt<unsigned> TokenFactorInlineLimit(
122 "combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048),
123 cl::desc("Limit the number of operands to inline for Token Factors"));
124
125static cl::opt<unsigned> StoreMergeDependenceLimit(
126 "combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10),
127 cl::desc("Limit the number of times for the same StoreNode and RootNode "
128 "to bail out in store merging dependence check"));
129
130static cl::opt<bool> EnableReduceLoadOpStoreWidth(
131 "combiner-reduce-load-op-store-width", cl::Hidden, cl::init(true),
132 cl::desc("DAG cominber enable reducing the width of load/op/store "
133 "sequence"));
134
135static cl::opt<bool> EnableShrinkLoadReplaceStoreWithStore(
136 "combiner-shrink-load-replace-store-with-store", cl::Hidden, cl::init(true),
137 cl::desc("DAG cominber enable load/<replace bytes>/store with "
138 "a narrower store"));
139
140namespace {
141
142 class DAGCombiner {
143 SelectionDAG &DAG;
144 const TargetLowering &TLI;
145 const SelectionDAGTargetInfo *STI;
146 CombineLevel Level;
147 CodeGenOpt::Level OptLevel;
148 bool LegalDAG = false;
149 bool LegalOperations = false;
150 bool LegalTypes = false;
151 bool ForCodeSize;
152 bool DisableGenericCombines;
153
154 /// Worklist of all of the nodes that need to be simplified.
155 ///
156 /// This must behave as a stack -- new nodes to process are pushed onto the
157 /// back and when processing we pop off of the back.
158 ///
159 /// The worklist will not contain duplicates but may contain null entries
160 /// due to nodes being deleted from the underlying DAG.
161 SmallVector<SDNode *, 64> Worklist;
162
163 /// Mapping from an SDNode to its position on the worklist.
164 ///
165 /// This is used to find and remove nodes from the worklist (by nulling
166 /// them) when they are deleted from the underlying DAG. It relies on
167 /// stable indices of nodes within the worklist.
168 DenseMap<SDNode *, unsigned> WorklistMap;
169 /// This records all nodes attempted to add to the worklist since we
170 /// considered a new worklist entry. As we keep do not add duplicate nodes
171 /// in the worklist, this is different from the tail of the worklist.
172 SmallSetVector<SDNode *, 32> PruningList;
173
174 /// Set of nodes which have been combined (at least once).
175 ///
176 /// This is used to allow us to reliably add any operands of a DAG node
177 /// which have not yet been combined to the worklist.
178 SmallPtrSet<SDNode *, 32> CombinedNodes;
179
180 /// Map from candidate StoreNode to the pair of RootNode and count.
181 /// The count is used to track how many times we have seen the StoreNode
182 /// with the same RootNode bail out in dependence check. If we have seen
183 /// the bail out for the same pair many times over a limit, we won't
184 /// consider the StoreNode with the same RootNode as store merging
185 /// candidate again.
186 DenseMap<SDNode *, std::pair<SDNode *, unsigned>> StoreRootCountMap;
187
188 // AA - Used for DAG load/store alias analysis.
189 AliasAnalysis *AA;
190
191 /// When an instruction is simplified, add all users of the instruction to
192 /// the work lists because they might get more simplified now.
193 void AddUsersToWorklist(SDNode *N) {
194 for (SDNode *Node : N->uses())
195 AddToWorklist(Node);
196 }
197
198 /// Convenient shorthand to add a node and all of its user to the worklist.
199 void AddToWorklistWithUsers(SDNode *N) {
200 AddUsersToWorklist(N);
201 AddToWorklist(N);
202 }
203
204 // Prune potentially dangling nodes. This is called after
205 // any visit to a node, but should also be called during a visit after any
206 // failed combine which may have created a DAG node.
207 void clearAddedDanglingWorklistEntries() {
208 // Check any nodes added to the worklist to see if they are prunable.
209 while (!PruningList.empty()) {
210 auto *N = PruningList.pop_back_val();
211 if (N->use_empty())
212 recursivelyDeleteUnusedNodes(N);
213 }
214 }
215
216 SDNode *getNextWorklistEntry() {
217 // Before we do any work, remove nodes that are not in use.
218 clearAddedDanglingWorklistEntries();
219 SDNode *N = nullptr;
220 // The Worklist holds the SDNodes in order, but it may contain null
221 // entries.
222 while (!N && !Worklist.empty()) {
223 N = Worklist.pop_back_val();
224 }
225
226 if (N) {
227 bool GoodWorklistEntry = WorklistMap.erase(N);
228 (void)GoodWorklistEntry;
229 assert(GoodWorklistEntry &&(static_cast <bool> (GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? void (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 230, __extension__ __PRETTY_FUNCTION__))
230 "Found a worklist entry without a corresponding map entry!")(static_cast <bool> (GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? void (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 230, __extension__ __PRETTY_FUNCTION__))
;
231 }
232 return N;
233 }
234
235 /// Call the node-specific routine that folds each particular type of node.
236 SDValue visit(SDNode *N);
237
238 public:
239 DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
240 : DAG(D), TLI(D.getTargetLoweringInfo()),
241 STI(D.getSubtarget().getSelectionDAGInfo()),
242 Level(BeforeLegalizeTypes), OptLevel(OL), AA(AA) {
243 ForCodeSize = DAG.shouldOptForSize();
244 DisableGenericCombines = STI && STI->disableGenericCombines(OptLevel);
245
246 MaximumLegalStoreInBits = 0;
247 // We use the minimum store size here, since that's all we can guarantee
248 // for the scalable vector types.
249 for (MVT VT : MVT::all_valuetypes())
250 if (EVT(VT).isSimple() && VT != MVT::Other &&
251 TLI.isTypeLegal(EVT(VT)) &&
252 VT.getSizeInBits().getKnownMinSize() >= MaximumLegalStoreInBits)
253 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinSize();
254 }
255
256 void ConsiderForPruning(SDNode *N) {
257 // Mark this for potential pruning.
258 PruningList.insert(N);
259 }
260
261 /// Add to the worklist making sure its instance is at the back (next to be
262 /// processed.)
263 void AddToWorklist(SDNode *N) {
264 assert(N->getOpcode() != ISD::DELETED_NODE &&(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& "Deleted Node added to Worklist") ? void (0) : __assert_fail
("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 265, __extension__ __PRETTY_FUNCTION__))
265 "Deleted Node added to Worklist")(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& "Deleted Node added to Worklist") ? void (0) : __assert_fail
("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 265, __extension__ __PRETTY_FUNCTION__))
;
266
267 // Skip handle nodes as they can't usefully be combined and confuse the
268 // zero-use deletion strategy.
269 if (N->getOpcode() == ISD::HANDLENODE)
270 return;
271
272 ConsiderForPruning(N);
273
274 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
275 Worklist.push_back(N);
276 }
277
278 /// Remove all instances of N from the worklist.
279 void removeFromWorklist(SDNode *N) {
280 CombinedNodes.erase(N);
281 PruningList.remove(N);
282 StoreRootCountMap.erase(N);
283
284 auto It = WorklistMap.find(N);
285 if (It == WorklistMap.end())
286 return; // Not in the worklist.
287
288 // Null out the entry rather than erasing it to avoid a linear operation.
289 Worklist[It->second] = nullptr;
290 WorklistMap.erase(It);
291 }
292
293 void deleteAndRecombine(SDNode *N);
294 bool recursivelyDeleteUnusedNodes(SDNode *N);
295
296 /// Replaces all uses of the results of one DAG node with new values.
297 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
298 bool AddTo = true);
299
300 /// Replaces all uses of the results of one DAG node with new values.
301 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
302 return CombineTo(N, &Res, 1, AddTo);
303 }
304
305 /// Replaces all uses of the results of one DAG node with new values.
306 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
307 bool AddTo = true) {
308 SDValue To[] = { Res0, Res1 };
309 return CombineTo(N, To, 2, AddTo);
310 }
311
312 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
313
314 private:
315 unsigned MaximumLegalStoreInBits;
316
317 /// Check the specified integer node value to see if it can be simplified or
318 /// if things it uses can be simplified by bit propagation.
319 /// If so, return true.
320 bool SimplifyDemandedBits(SDValue Op) {
321 unsigned BitWidth = Op.getScalarValueSizeInBits();
322 APInt DemandedBits = APInt::getAllOnesValue(BitWidth);
323 return SimplifyDemandedBits(Op, DemandedBits);
324 }
325
326 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) {
327 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
328 KnownBits Known;
329 if (!TLI.SimplifyDemandedBits(Op, DemandedBits, Known, TLO, 0, false))
330 return false;
331
332 // Revisit the node.
333 AddToWorklist(Op.getNode());
334
335 CommitTargetLoweringOpt(TLO);
336 return true;
337 }
338
339 /// Check the specified vector node value to see if it can be simplified or
340 /// if things it uses can be simplified as it only uses some of the
341 /// elements. If so, return true.
342 bool SimplifyDemandedVectorElts(SDValue Op) {
343 // TODO: For now just pretend it cannot be simplified.
344 if (Op.getValueType().isScalableVector())
345 return false;
346
347 unsigned NumElts = Op.getValueType().getVectorNumElements();
348 APInt DemandedElts = APInt::getAllOnesValue(NumElts);
349 return SimplifyDemandedVectorElts(Op, DemandedElts);
350 }
351
352 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
353 const APInt &DemandedElts,
354 bool AssumeSingleUse = false);
355 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
356 bool AssumeSingleUse = false);
357
358 bool CombineToPreIndexedLoadStore(SDNode *N);
359 bool CombineToPostIndexedLoadStore(SDNode *N);
360 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
361 bool SliceUpLoad(SDNode *N);
362
363 // Scalars have size 0 to distinguish from singleton vectors.
364 SDValue ForwardStoreValueToDirectLoad(LoadSDNode *LD);
365 bool getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val);
366 bool extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val);
367
368 /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
369 /// load.
370 ///
371 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
372 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
373 /// \param EltNo index of the vector element to load.
374 /// \param OriginalLoad load that EVE came from to be replaced.
375 /// \returns EVE on success SDValue() on failure.
376 SDValue scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT,
377 SDValue EltNo,
378 LoadSDNode *OriginalLoad);
379 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
380 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
381 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
382 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
383 SDValue PromoteIntBinOp(SDValue Op);
384 SDValue PromoteIntShiftOp(SDValue Op);
385 SDValue PromoteExtend(SDValue Op);
386 bool PromoteLoad(SDValue Op);
387
388 /// Call the node-specific routine that knows how to fold each
389 /// particular type of node. If that doesn't do anything, try the
390 /// target-specific DAG combines.
391 SDValue combine(SDNode *N);
392
393 // Visitation implementation - Implement dag node combining for different
394 // node types. The semantics are as follows:
395 // Return Value:
396 // SDValue.getNode() == 0 - No change was made
397 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
398 // otherwise - N should be replaced by the returned Operand.
399 //
400 SDValue visitTokenFactor(SDNode *N);
401 SDValue visitMERGE_VALUES(SDNode *N);
402 SDValue visitADD(SDNode *N);
403 SDValue visitADDLike(SDNode *N);
404 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
405 SDValue visitSUB(SDNode *N);
406 SDValue visitADDSAT(SDNode *N);
407 SDValue visitSUBSAT(SDNode *N);
408 SDValue visitADDC(SDNode *N);
409 SDValue visitADDO(SDNode *N);
410 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
411 SDValue visitSUBC(SDNode *N);
412 SDValue visitSUBO(SDNode *N);
413 SDValue visitADDE(SDNode *N);
414 SDValue visitADDCARRY(SDNode *N);
415 SDValue visitSADDO_CARRY(SDNode *N);
416 SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
417 SDValue visitSUBE(SDNode *N);
418 SDValue visitSUBCARRY(SDNode *N);
419 SDValue visitSSUBO_CARRY(SDNode *N);
420 SDValue visitMUL(SDNode *N);
421 SDValue visitMULFIX(SDNode *N);
422 SDValue useDivRem(SDNode *N);
423 SDValue visitSDIV(SDNode *N);
424 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
425 SDValue visitUDIV(SDNode *N);
426 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
427 SDValue visitREM(SDNode *N);
428 SDValue visitMULHU(SDNode *N);
429 SDValue visitMULHS(SDNode *N);
430 SDValue visitSMUL_LOHI(SDNode *N);
431 SDValue visitUMUL_LOHI(SDNode *N);
432 SDValue visitMULO(SDNode *N);
433 SDValue visitIMINMAX(SDNode *N);
434 SDValue visitAND(SDNode *N);
435 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
436 SDValue visitOR(SDNode *N);
437 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
438 SDValue visitXOR(SDNode *N);
439 SDValue SimplifyVBinOp(SDNode *N);
440 SDValue visitSHL(SDNode *N);
441 SDValue visitSRA(SDNode *N);
442 SDValue visitSRL(SDNode *N);
443 SDValue visitFunnelShift(SDNode *N);
444 SDValue visitRotate(SDNode *N);
445 SDValue visitABS(SDNode *N);
446 SDValue visitBSWAP(SDNode *N);
447 SDValue visitBITREVERSE(SDNode *N);
448 SDValue visitCTLZ(SDNode *N);
449 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
450 SDValue visitCTTZ(SDNode *N);
451 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
452 SDValue visitCTPOP(SDNode *N);
453 SDValue visitSELECT(SDNode *N);
454 SDValue visitVSELECT(SDNode *N);
455 SDValue visitSELECT_CC(SDNode *N);
456 SDValue visitSETCC(SDNode *N);
457 SDValue visitSETCCCARRY(SDNode *N);
458 SDValue visitSIGN_EXTEND(SDNode *N);
459 SDValue visitZERO_EXTEND(SDNode *N);
460 SDValue visitANY_EXTEND(SDNode *N);
461 SDValue visitAssertExt(SDNode *N);
462 SDValue visitAssertAlign(SDNode *N);
463 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
464 SDValue visitEXTEND_VECTOR_INREG(SDNode *N);
465 SDValue visitTRUNCATE(SDNode *N);
466 SDValue visitBITCAST(SDNode *N);
467 SDValue visitFREEZE(SDNode *N);
468 SDValue visitBUILD_PAIR(SDNode *N);
469 SDValue visitFADD(SDNode *N);
470 SDValue visitSTRICT_FADD(SDNode *N);
471 SDValue visitFSUB(SDNode *N);
472 SDValue visitFMUL(SDNode *N);
473 SDValue visitFMA(SDNode *N);
474 SDValue visitFDIV(SDNode *N);
475 SDValue visitFREM(SDNode *N);
476 SDValue visitFSQRT(SDNode *N);
477 SDValue visitFCOPYSIGN(SDNode *N);
478 SDValue visitFPOW(SDNode *N);
479 SDValue visitSINT_TO_FP(SDNode *N);
480 SDValue visitUINT_TO_FP(SDNode *N);
481 SDValue visitFP_TO_SINT(SDNode *N);
482 SDValue visitFP_TO_UINT(SDNode *N);
483 SDValue visitFP_ROUND(SDNode *N);
484 SDValue visitFP_EXTEND(SDNode *N);
485 SDValue visitFNEG(SDNode *N);
486 SDValue visitFABS(SDNode *N);
487 SDValue visitFCEIL(SDNode *N);
488 SDValue visitFTRUNC(SDNode *N);
489 SDValue visitFFLOOR(SDNode *N);
490 SDValue visitFMINNUM(SDNode *N);
491 SDValue visitFMAXNUM(SDNode *N);
492 SDValue visitFMINIMUM(SDNode *N);
493 SDValue visitFMAXIMUM(SDNode *N);
494 SDValue visitBRCOND(SDNode *N);
495 SDValue visitBR_CC(SDNode *N);
496 SDValue visitLOAD(SDNode *N);
497
498 SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
499 SDValue replaceStoreOfFPConstant(StoreSDNode *ST);
500
501 SDValue visitSTORE(SDNode *N);
502 SDValue visitLIFETIME_END(SDNode *N);
503 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
504 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
505 SDValue visitBUILD_VECTOR(SDNode *N);
506 SDValue visitCONCAT_VECTORS(SDNode *N);
507 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
508 SDValue visitVECTOR_SHUFFLE(SDNode *N);
509 SDValue visitSCALAR_TO_VECTOR(SDNode *N);
510 SDValue visitINSERT_SUBVECTOR(SDNode *N);
511 SDValue visitMLOAD(SDNode *N);
512 SDValue visitMSTORE(SDNode *N);
513 SDValue visitMGATHER(SDNode *N);
514 SDValue visitMSCATTER(SDNode *N);
515 SDValue visitFP_TO_FP16(SDNode *N);
516 SDValue visitFP16_TO_FP(SDNode *N);
517 SDValue visitVECREDUCE(SDNode *N);
518
519 SDValue visitFADDForFMACombine(SDNode *N);
520 SDValue visitFSUBForFMACombine(SDNode *N);
521 SDValue visitFMULForFMADistributiveCombine(SDNode *N);
522
523 SDValue XformToShuffleWithZero(SDNode *N);
524 bool reassociationCanBreakAddressingModePattern(unsigned Opc,
525 const SDLoc &DL, SDValue N0,
526 SDValue N1);
527 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
528 SDValue N1);
529 SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
530 SDValue N1, SDNodeFlags Flags);
531
532 SDValue visitShiftByConstant(SDNode *N);
533
534 SDValue foldSelectOfConstants(SDNode *N);
535 SDValue foldVSelectOfConstants(SDNode *N);
536 SDValue foldBinOpIntoSelect(SDNode *BO);
537 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
538 SDValue hoistLogicOpWithSameOpcodeHands(SDNode *N);
539 SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
540 SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
541 SDValue N2, SDValue N3, ISD::CondCode CC,
542 bool NotExtCompare = false);
543 SDValue convertSelectOfFPConstantsToLoadOffset(
544 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
545 ISD::CondCode CC);
546 SDValue foldSignChangeInBitcast(SDNode *N);
547 SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
548 SDValue N2, SDValue N3, ISD::CondCode CC);
549 SDValue foldSelectOfBinops(SDNode *N);
550 SDValue foldSextSetcc(SDNode *N);
551 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
552 const SDLoc &DL);
553 SDValue foldSubToUSubSat(EVT DstVT, SDNode *N);
554 SDValue unfoldMaskedMerge(SDNode *N);
555 SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
556 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
557 const SDLoc &DL, bool foldBooleans);
558 SDValue rebuildSetCC(SDValue N);
559
560 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
561 SDValue &CC, bool MatchStrict = false) const;
562 bool isOneUseSetCC(SDValue N) const;
563
564 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
565 unsigned HiOp);
566 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
567 SDValue CombineExtLoad(SDNode *N);
568 SDValue CombineZExtLogicopShiftLoad(SDNode *N);
569 SDValue combineRepeatedFPDivisors(SDNode *N);
570 SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex);
571 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
572 SDValue BuildSDIV(SDNode *N);
573 SDValue BuildSDIVPow2(SDNode *N);
574 SDValue BuildUDIV(SDNode *N);
575 SDValue BuildLogBase2(SDValue V, const SDLoc &DL);
576 SDValue BuildDivEstimate(SDValue N, SDValue Op, SDNodeFlags Flags);
577 SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
578 SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
579 SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
580 SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations,
581 SDNodeFlags Flags, bool Reciprocal);
582 SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations,
583 SDNodeFlags Flags, bool Reciprocal);
584 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
585 bool DemandHighBits = true);
586 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
587 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
588 SDValue InnerPos, SDValue InnerNeg,
589 unsigned PosOpcode, unsigned NegOpcode,
590 const SDLoc &DL);
591 SDValue MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, SDValue Neg,
592 SDValue InnerPos, SDValue InnerNeg,
593 unsigned PosOpcode, unsigned NegOpcode,
594 const SDLoc &DL);
595 SDValue MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
596 SDValue MatchLoadCombine(SDNode *N);
597 SDValue mergeTruncStores(StoreSDNode *N);
598 SDValue ReduceLoadWidth(SDNode *N);
599 SDValue ReduceLoadOpStoreWidth(SDNode *N);
600 SDValue splitMergedValStore(StoreSDNode *ST);
601 SDValue TransformFPLoadStorePair(SDNode *N);
602 SDValue convertBuildVecZextToZext(SDNode *N);
603 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
604 SDValue reduceBuildVecTruncToBitCast(SDNode *N);
605 SDValue reduceBuildVecToShuffle(SDNode *N);
606 SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
607 ArrayRef<int> VectorMask, SDValue VecIn1,
608 SDValue VecIn2, unsigned LeftIdx,
609 bool DidSplitVec);
610 SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast);
611
612 /// Walk up chain skipping non-aliasing memory nodes,
613 /// looking for aliasing nodes and adding them to the Aliases vector.
614 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
615 SmallVectorImpl<SDValue> &Aliases);
616
617 /// Return true if there is any possibility that the two addresses overlap.
618 bool isAlias(SDNode *Op0, SDNode *Op1) const;
619
620 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
621 /// chain (aliasing node.)
622 SDValue FindBetterChain(SDNode *N, SDValue Chain);
623
624 /// Try to replace a store and any possibly adjacent stores on
625 /// consecutive chains with better chains. Return true only if St is
626 /// replaced.
627 ///
628 /// Notice that other chains may still be replaced even if the function
629 /// returns false.
630 bool findBetterNeighborChains(StoreSDNode *St);
631
632 // Helper for findBetterNeighborChains. Walk up store chain add additional
633 // chained stores that do not overlap and can be parallelized.
634 bool parallelizeChainedStores(StoreSDNode *St);
635
636 /// Holds a pointer to an LSBaseSDNode as well as information on where it
637 /// is located in a sequence of memory operations connected by a chain.
638 struct MemOpLink {
639 // Ptr to the mem node.
640 LSBaseSDNode *MemNode;
641
642 // Offset from the base ptr.
643 int64_t OffsetFromBase;
644
645 MemOpLink(LSBaseSDNode *N, int64_t Offset)
646 : MemNode(N), OffsetFromBase(Offset) {}
647 };
648
649 // Classify the origin of a stored value.
650 enum class StoreSource { Unknown, Constant, Extract, Load };
651 StoreSource getStoreSource(SDValue StoreVal) {
652 switch (StoreVal.getOpcode()) {
653 case ISD::Constant:
654 case ISD::ConstantFP:
655 return StoreSource::Constant;
656 case ISD::EXTRACT_VECTOR_ELT:
657 case ISD::EXTRACT_SUBVECTOR:
658 return StoreSource::Extract;
659 case ISD::LOAD:
660 return StoreSource::Load;
661 default:
662 return StoreSource::Unknown;
663 }
664 }
665
666 /// This is a helper function for visitMUL to check the profitability
667 /// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
668 /// MulNode is the original multiply, AddNode is (add x, c1),
669 /// and ConstNode is c2.
670 bool isMulAddWithConstProfitable(SDNode *MulNode,
671 SDValue &AddNode,
672 SDValue &ConstNode);
673
674 /// This is a helper function for visitAND and visitZERO_EXTEND. Returns
675 /// true if the (and (load x) c) pattern matches an extload. ExtVT returns
676 /// the type of the loaded value to be extended.
677 bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
678 EVT LoadResultTy, EVT &ExtVT);
679
680 /// Helper function to calculate whether the given Load/Store can have its
681 /// width reduced to ExtVT.
682 bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType,
683 EVT &MemVT, unsigned ShAmt = 0);
684
685 /// Used by BackwardsPropagateMask to find suitable loads.
686 bool SearchForAndLoads(SDNode *N, SmallVectorImpl<LoadSDNode*> &Loads,
687 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
688 ConstantSDNode *Mask, SDNode *&NodeToMask);
689 /// Attempt to propagate a given AND node back to load leaves so that they
690 /// can be combined into narrow loads.
691 bool BackwardsPropagateMask(SDNode *N);
692
693 /// Helper function for mergeConsecutiveStores which merges the component
694 /// store chains.
695 SDValue getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
696 unsigned NumStores);
697
698 /// This is a helper function for mergeConsecutiveStores. When the source
699 /// elements of the consecutive stores are all constants or all extracted
700 /// vector elements, try to merge them into one larger store introducing
701 /// bitcasts if necessary. \return True if a merged store was created.
702 bool mergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
703 EVT MemVT, unsigned NumStores,
704 bool IsConstantSrc, bool UseVector,
705 bool UseTrunc);
706
707 /// This is a helper function for mergeConsecutiveStores. Stores that
708 /// potentially may be merged with St are placed in StoreNodes. RootNode is
709 /// a chain predecessor to all store candidates.
710 void getStoreMergeCandidates(StoreSDNode *St,
711 SmallVectorImpl<MemOpLink> &StoreNodes,
712 SDNode *&Root);
713
714 /// Helper function for mergeConsecutiveStores. Checks if candidate stores
715 /// have indirect dependency through their operands. RootNode is the
716 /// predecessor to all stores calculated by getStoreMergeCandidates and is
717 /// used to prune the dependency check. \return True if safe to merge.
718 bool checkMergeStoreCandidatesForDependencies(
719 SmallVectorImpl<MemOpLink> &StoreNodes, unsigned NumStores,
720 SDNode *RootNode);
721
722 /// This is a helper function for mergeConsecutiveStores. Given a list of
723 /// store candidates, find the first N that are consecutive in memory.
724 /// Returns 0 if there are not at least 2 consecutive stores to try merging.
725 unsigned getConsecutiveStores(SmallVectorImpl<MemOpLink> &StoreNodes,
726 int64_t ElementSizeBytes) const;
727
728 /// This is a helper function for mergeConsecutiveStores. It is used for
729 /// store chains that are composed entirely of constant values.
730 bool tryStoreMergeOfConstants(SmallVectorImpl<MemOpLink> &StoreNodes,
731 unsigned NumConsecutiveStores,
732 EVT MemVT, SDNode *Root, bool AllowVectors);
733
734 /// This is a helper function for mergeConsecutiveStores. It is used for
735 /// store chains that are composed entirely of extracted vector elements.
736 /// When extracting multiple vector elements, try to store them in one
737 /// vector store rather than a sequence of scalar stores.
738 bool tryStoreMergeOfExtracts(SmallVectorImpl<MemOpLink> &StoreNodes,
739 unsigned NumConsecutiveStores, EVT MemVT,
740 SDNode *Root);
741
742 /// This is a helper function for mergeConsecutiveStores. It is used for
743 /// store chains that are composed entirely of loaded values.
744 bool tryStoreMergeOfLoads(SmallVectorImpl<MemOpLink> &StoreNodes,
745 unsigned NumConsecutiveStores, EVT MemVT,
746 SDNode *Root, bool AllowVectors,
747 bool IsNonTemporalStore, bool IsNonTemporalLoad);
748
749 /// Merge consecutive store operations into a wide store.
750 /// This optimization uses wide integers or vectors when possible.
751 /// \return true if stores were merged.
752 bool mergeConsecutiveStores(StoreSDNode *St);
753
754 /// Try to transform a truncation where C is a constant:
755 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
756 ///
757 /// \p N needs to be a truncation and its first operand an AND. Other
758 /// requirements are checked by the function (e.g. that trunc is
759 /// single-use) and if missed an empty SDValue is returned.
760 SDValue distributeTruncateThroughAnd(SDNode *N);
761
762 /// Helper function to determine whether the target supports operation
763 /// given by \p Opcode for type \p VT, that is, whether the operation
764 /// is legal or custom before legalizing operations, and whether is
765 /// legal (but not custom) after legalization.
766 bool hasOperation(unsigned Opcode, EVT VT) {
767 return TLI.isOperationLegalOrCustom(Opcode, VT, LegalOperations);
768 }
769
770 public:
771 /// Runs the dag combiner on all nodes in the work list
772 void Run(CombineLevel AtLevel);
773
774 SelectionDAG &getDAG() const { return DAG; }
775
776 /// Returns a type large enough to hold any valid shift amount - before type
777 /// legalization these can be huge.
778 EVT getShiftAmountTy(EVT LHSTy) {
779 assert(LHSTy.isInteger() && "Shift amount is not an integer type!")(static_cast <bool> (LHSTy.isInteger() && "Shift amount is not an integer type!"
) ? void (0) : __assert_fail ("LHSTy.isInteger() && \"Shift amount is not an integer type!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 779, __extension__ __PRETTY_FUNCTION__))
;
780 return TLI.getShiftAmountTy(LHSTy, DAG.getDataLayout(), LegalTypes);
781 }
782
783 /// This method returns true if we are running before type legalization or
784 /// if the specified VT is legal.
785 bool isTypeLegal(const EVT &VT) {
786 if (!LegalTypes) return true;
787 return TLI.isTypeLegal(VT);
788 }
789
790 /// Convenience wrapper around TargetLowering::getSetCCResultType
791 EVT getSetCCResultType(EVT VT) const {
792 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
793 }
794
795 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
796 SDValue OrigLoad, SDValue ExtLoad,
797 ISD::NodeType ExtType);
798 };
799
800/// This class is a DAGUpdateListener that removes any deleted
801/// nodes from the worklist.
802class WorklistRemover : public SelectionDAG::DAGUpdateListener {
803 DAGCombiner &DC;
804
805public:
806 explicit WorklistRemover(DAGCombiner &dc)
807 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
808
809 void NodeDeleted(SDNode *N, SDNode *E) override {
810 DC.removeFromWorklist(N);
811 }
812};
813
814class WorklistInserter : public SelectionDAG::DAGUpdateListener {
815 DAGCombiner &DC;
816
817public:
818 explicit WorklistInserter(DAGCombiner &dc)
819 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
820
821 // FIXME: Ideally we could add N to the worklist, but this causes exponential
822 // compile time costs in large DAGs, e.g. Halide.
823 void NodeInserted(SDNode *N) override { DC.ConsiderForPruning(N); }
824};
825
826} // end anonymous namespace
827
828//===----------------------------------------------------------------------===//
829// TargetLowering::DAGCombinerInfo implementation
830//===----------------------------------------------------------------------===//
831
832void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
833 ((DAGCombiner*)DC)->AddToWorklist(N);
834}
835
836SDValue TargetLowering::DAGCombinerInfo::
837CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
838 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
839}
840
841SDValue TargetLowering::DAGCombinerInfo::
842CombineTo(SDNode *N, SDValue Res, bool AddTo) {
843 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
844}
845
846SDValue TargetLowering::DAGCombinerInfo::
847CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
848 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
849}
850
851bool TargetLowering::DAGCombinerInfo::
852recursivelyDeleteUnusedNodes(SDNode *N) {
853 return ((DAGCombiner*)DC)->recursivelyDeleteUnusedNodes(N);
854}
855
856void TargetLowering::DAGCombinerInfo::
857CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
858 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
859}
860
861//===----------------------------------------------------------------------===//
862// Helper Functions
863//===----------------------------------------------------------------------===//
864
865void DAGCombiner::deleteAndRecombine(SDNode *N) {
866 removeFromWorklist(N);
867
868 // If the operands of this node are only used by the node, they will now be
869 // dead. Make sure to re-visit them and recursively delete dead nodes.
870 for (const SDValue &Op : N->ops())
871 // For an operand generating multiple values, one of the values may
872 // become dead allowing further simplification (e.g. split index
873 // arithmetic from an indexed load).
874 if (Op->hasOneUse() || Op->getNumValues() > 1)
875 AddToWorklist(Op.getNode());
876
877 DAG.DeleteNode(N);
878}
879
880// APInts must be the same size for most operations, this helper
881// function zero extends the shorter of the pair so that they match.
882// We provide an Offset so that we can create bitwidths that won't overflow.
883static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) {
884 unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth());
885 LHS = LHS.zextOrSelf(Bits);
886 RHS = RHS.zextOrSelf(Bits);
887}
888
889// Return true if this node is a setcc, or is a select_cc
890// that selects between the target values used for true and false, making it
891// equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
892// the appropriate nodes based on the type of node we are checking. This
893// simplifies life a bit for the callers.
894bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
895 SDValue &CC, bool MatchStrict) const {
896 if (N.getOpcode() == ISD::SETCC) {
897 LHS = N.getOperand(0);
898 RHS = N.getOperand(1);
899 CC = N.getOperand(2);
900 return true;
901 }
902
903 if (MatchStrict &&
904 (N.getOpcode() == ISD::STRICT_FSETCC ||
905 N.getOpcode() == ISD::STRICT_FSETCCS)) {
906 LHS = N.getOperand(1);
907 RHS = N.getOperand(2);
908 CC = N.getOperand(3);
909 return true;
910 }
911
912 if (N.getOpcode() != ISD::SELECT_CC ||
913 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
914 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
915 return false;
916
917 if (TLI.getBooleanContents(N.getValueType()) ==
918 TargetLowering::UndefinedBooleanContent)
919 return false;
920
921 LHS = N.getOperand(0);
922 RHS = N.getOperand(1);
923 CC = N.getOperand(4);
924 return true;
925}
926
927/// Return true if this is a SetCC-equivalent operation with only one use.
928/// If this is true, it allows the users to invert the operation for free when
929/// it is profitable to do so.
930bool DAGCombiner::isOneUseSetCC(SDValue N) const {
931 SDValue N0, N1, N2;
932 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
933 return true;
934 return false;
935}
936
937static bool isConstantSplatVectorMaskForType(SDNode *N, EVT ScalarTy) {
938 if (!ScalarTy.isSimple())
939 return false;
940
941 uint64_t MaskForTy = 0ULL;
942 switch (ScalarTy.getSimpleVT().SimpleTy) {
943 case MVT::i8:
944 MaskForTy = 0xFFULL;
945 break;
946 case MVT::i16:
947 MaskForTy = 0xFFFFULL;
948 break;
949 case MVT::i32:
950 MaskForTy = 0xFFFFFFFFULL;
951 break;
952 default:
953 return false;
954 break;
955 }
956
957 APInt Val;
958 if (ISD::isConstantSplatVector(N, Val))
959 return Val.getLimitedValue() == MaskForTy;
960
961 return false;
962}
963
964// Determines if it is a constant integer or a splat/build vector of constant
965// integers (and undefs).
966// Do not permit build vector implicit truncation.
967static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) {
968 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N))
969 return !(Const->isOpaque() && NoOpaques);
970 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR)
971 return false;
972 unsigned BitWidth = N.getScalarValueSizeInBits();
973 for (const SDValue &Op : N->op_values()) {
974 if (Op.isUndef())
975 continue;
976 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op);
977 if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth ||
978 (Const->isOpaque() && NoOpaques))
979 return false;
980 }
981 return true;
982}
983
984// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with
985// undef's.
986static bool isAnyConstantBuildVector(SDValue V, bool NoOpaques = false) {
987 if (V.getOpcode() != ISD::BUILD_VECTOR)
988 return false;
989 return isConstantOrConstantVector(V, NoOpaques) ||
990 ISD::isBuildVectorOfConstantFPSDNodes(V.getNode());
991}
992
993// Determine if this an indexed load with an opaque target constant index.
994static bool canSplitIdx(LoadSDNode *LD) {
995 return MaySplitLoadIndex &&
996 (LD->getOperand(2).getOpcode() != ISD::TargetConstant ||
997 !cast<ConstantSDNode>(LD->getOperand(2))->isOpaque());
998}
999
1000bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc,
1001 const SDLoc &DL,
1002 SDValue N0,
1003 SDValue N1) {
1004 // Currently this only tries to ensure we don't undo the GEP splits done by
1005 // CodeGenPrepare when shouldConsiderGEPOffsetSplit is true. To ensure this,
1006 // we check if the following transformation would be problematic:
1007 // (load/store (add, (add, x, offset1), offset2)) ->
1008 // (load/store (add, x, offset1+offset2)).
1009
1010 if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD)
1011 return false;
1012
1013 if (N0.hasOneUse())
1014 return false;
1015
1016 auto *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1017 auto *C2 = dyn_cast<ConstantSDNode>(N1);
1018 if (!C1 || !C2)
1019 return false;
1020
1021 const APInt &C1APIntVal = C1->getAPIntValue();
1022 const APInt &C2APIntVal = C2->getAPIntValue();
1023 if (C1APIntVal.getBitWidth() > 64 || C2APIntVal.getBitWidth() > 64)
1024 return false;
1025
1026 const APInt CombinedValueIntVal = C1APIntVal + C2APIntVal;
1027 if (CombinedValueIntVal.getBitWidth() > 64)
1028 return false;
1029 const int64_t CombinedValue = CombinedValueIntVal.getSExtValue();
1030
1031 for (SDNode *Node : N0->uses()) {
1032 auto LoadStore = dyn_cast<MemSDNode>(Node);
1033 if (LoadStore) {
1034 // Is x[offset2] already not a legal addressing mode? If so then
1035 // reassociating the constants breaks nothing (we test offset2 because
1036 // that's the one we hope to fold into the load or store).
1037 TargetLoweringBase::AddrMode AM;
1038 AM.HasBaseReg = true;
1039 AM.BaseOffs = C2APIntVal.getSExtValue();
1040 EVT VT = LoadStore->getMemoryVT();
1041 unsigned AS = LoadStore->getAddressSpace();
1042 Type *AccessTy = VT.getTypeForEVT(*DAG.getContext());
1043 if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
1044 continue;
1045
1046 // Would x[offset1+offset2] still be a legal addressing mode?
1047 AM.BaseOffs = CombinedValue;
1048 if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
1049 return true;
1050 }
1051 }
1052
1053 return false;
1054}
1055
1056// Helper for DAGCombiner::reassociateOps. Try to reassociate an expression
1057// such as (Opc N0, N1), if \p N0 is the same kind of operation as \p Opc.
1058SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
1059 SDValue N0, SDValue N1) {
1060 EVT VT = N0.getValueType();
1061
1062 if (N0.getOpcode() != Opc)
1063 return SDValue();
1064
1065 if (DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
1066 if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
1067 // Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
1068 if (SDValue OpNode =
1069 DAG.FoldConstantArithmetic(Opc, DL, VT, {N0.getOperand(1), N1}))
1070 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
1071 return SDValue();
1072 }
1073 if (N0.hasOneUse()) {
1074 // Reassociate: (op (op x, c1), y) -> (op (op x, y), c1)
1075 // iff (op x, c1) has one use
1076 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
1077 if (!OpNode.getNode())
1078 return SDValue();
1079 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
1080 }
1081 }
1082 return SDValue();
1083}
1084
1085// Try to reassociate commutative binops.
1086SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
1087 SDValue N1, SDNodeFlags Flags) {
1088 assert(TLI.isCommutativeBinOp(Opc) && "Operation not commutative.")(static_cast <bool> (TLI.isCommutativeBinOp(Opc) &&
"Operation not commutative.") ? void (0) : __assert_fail ("TLI.isCommutativeBinOp(Opc) && \"Operation not commutative.\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1088, __extension__ __PRETTY_FUNCTION__))
;
1089
1090 // Floating-point reassociation is not allowed without loose FP math.
1091 if (N0.getValueType().isFloatingPoint() ||
1092 N1.getValueType().isFloatingPoint())
1093 if (!Flags.hasAllowReassociation() || !Flags.hasNoSignedZeros())
1094 return SDValue();
1095
1096 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1))
1097 return Combined;
1098 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0))
1099 return Combined;
1100 return SDValue();
1101}
1102
1103SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
1104 bool AddTo) {
1105 assert(N->getNumValues() == NumTo && "Broken CombineTo call!")(static_cast <bool> (N->getNumValues() == NumTo &&
"Broken CombineTo call!") ? void (0) : __assert_fail ("N->getNumValues() == NumTo && \"Broken CombineTo call!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1105, __extension__ __PRETTY_FUNCTION__))
;
1106 ++NodesCombined;
1107 LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1108 To[0].getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1109 dbgs() << " and " << NumTo - 1 << " other values\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
;
1110 for (unsigned i = 0, e = NumTo; i != e; ++i)
1111 assert((!To[i].getNode() ||(static_cast <bool> ((!To[i].getNode() || N->getValueType
(i) == To[i].getValueType()) && "Cannot combine value to value of different type!"
) ? void (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1113, __extension__ __PRETTY_FUNCTION__))
1112 N->getValueType(i) == To[i].getValueType()) &&(static_cast <bool> ((!To[i].getNode() || N->getValueType
(i) == To[i].getValueType()) && "Cannot combine value to value of different type!"
) ? void (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1113, __extension__ __PRETTY_FUNCTION__))
1113 "Cannot combine value to value of different type!")(static_cast <bool> ((!To[i].getNode() || N->getValueType
(i) == To[i].getValueType()) && "Cannot combine value to value of different type!"
) ? void (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1113, __extension__ __PRETTY_FUNCTION__))
;
1114
1115 WorklistRemover DeadNodes(*this);
1116 DAG.ReplaceAllUsesWith(N, To);
1117 if (AddTo) {
1118 // Push the new nodes and any users onto the worklist
1119 for (unsigned i = 0, e = NumTo; i != e; ++i) {
1120 if (To[i].getNode()) {
1121 AddToWorklist(To[i].getNode());
1122 AddUsersToWorklist(To[i].getNode());
1123 }
1124 }
1125 }
1126
1127 // Finally, if the node is now dead, remove it from the graph. The node
1128 // may not be dead if the replacement process recursively simplified to
1129 // something else needing this node.
1130 if (N->use_empty())
1131 deleteAndRecombine(N);
1132 return SDValue(N, 0);
1133}
1134
1135void DAGCombiner::
1136CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
1137 // Replace the old value with the new one.
1138 ++NodesCombined;
1139 LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1140 dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1141 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
;
1142
1143 // Replace all uses. If any nodes become isomorphic to other nodes and
1144 // are deleted, make sure to remove them from our worklist.
1145 WorklistRemover DeadNodes(*this);
1146 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
1147
1148 // Push the new node and any (possibly new) users onto the worklist.
1149 AddToWorklistWithUsers(TLO.New.getNode());
1150
1151 // Finally, if the node is now dead, remove it from the graph. The node
1152 // may not be dead if the replacement process recursively simplified to
1153 // something else needing this node.
1154 if (TLO.Old.getNode()->use_empty())
1155 deleteAndRecombine(TLO.Old.getNode());
1156}
1157
1158/// Check the specified integer node value to see if it can be simplified or if
1159/// things it uses can be simplified by bit propagation. If so, return true.
1160bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
1161 const APInt &DemandedElts,
1162 bool AssumeSingleUse) {
1163 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1164 KnownBits Known;
1165 if (!TLI.SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, 0,
1166 AssumeSingleUse))
1167 return false;
1168
1169 // Revisit the node.
1170 AddToWorklist(Op.getNode());
1171
1172 CommitTargetLoweringOpt(TLO);
1173 return true;
1174}
1175
1176/// Check the specified vector node value to see if it can be simplified or
1177/// if things it uses can be simplified as it only uses some of the elements.
1178/// If so, return true.
1179bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op,
1180 const APInt &DemandedElts,
1181 bool AssumeSingleUse) {
1182 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1183 APInt KnownUndef, KnownZero;
1184 if (!TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero,
1185 TLO, 0, AssumeSingleUse))
1186 return false;
1187
1188 // Revisit the node.
1189 AddToWorklist(Op.getNode());
1190
1191 CommitTargetLoweringOpt(TLO);
1192 return true;
1193}
1194
1195void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
1196 SDLoc DL(Load);
1197 EVT VT = Load->getValueType(0);
1198 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0));
1199
1200 LLVM_DEBUG(dbgs() << "\nReplacing.9 "; Load->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
1201 Trunc.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
;
1202 WorklistRemover DeadNodes(*this);
1203 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
1204 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
1205 deleteAndRecombine(Load);
1206 AddToWorklist(Trunc.getNode());
1207}
1208
1209SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
1210 Replace = false;
1211 SDLoc DL(Op);
1212 if (ISD::isUNINDEXEDLoad(Op.getNode())) {
1213 LoadSDNode *LD = cast<LoadSDNode>(Op);
1214 EVT MemVT = LD->getMemoryVT();
1215 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1216 : LD->getExtensionType();
1217 Replace = true;
1218 return DAG.getExtLoad(ExtType, DL, PVT,
1219 LD->getChain(), LD->getBasePtr(),
1220 MemVT, LD->getMemOperand());
1221 }
1222
1223 unsigned Opc = Op.getOpcode();
1224 switch (Opc) {
1225 default: break;
1226 case ISD::AssertSext:
1227 if (SDValue Op0 = SExtPromoteOperand(Op.getOperand(0), PVT))
1228 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1));
1229 break;
1230 case ISD::AssertZext:
1231 if (SDValue Op0 = ZExtPromoteOperand(Op.getOperand(0), PVT))
1232 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1));
1233 break;
1234 case ISD::Constant: {
1235 unsigned ExtOpc =
1236 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1237 return DAG.getNode(ExtOpc, DL, PVT, Op);
1238 }
1239 }
1240
1241 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
1242 return SDValue();
1243 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op);
1244}
1245
1246SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
1247 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
1248 return SDValue();
1249 EVT OldVT = Op.getValueType();
1250 SDLoc DL(Op);
1251 bool Replace = false;
1252 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1253 if (!NewOp.getNode())
1254 return SDValue();
1255 AddToWorklist(NewOp.getNode());
1256
1257 if (Replace)
1258 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1259 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp,
1260 DAG.getValueType(OldVT));
1261}
1262
1263SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
1264 EVT OldVT = Op.getValueType();
1265 SDLoc DL(Op);
1266 bool Replace = false;
1267 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1268 if (!NewOp.getNode())
1269 return SDValue();
1270 AddToWorklist(NewOp.getNode());
1271
1272 if (Replace)
1273 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1274 return DAG.getZeroExtendInReg(NewOp, DL, OldVT);
1275}
1276
1277/// Promote the specified integer binary operation if the target indicates it is
1278/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1279/// i32 since i16 instructions are longer.
1280SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
1281 if (!LegalOperations)
1282 return SDValue();
1283
1284 EVT VT = Op.getValueType();
1285 if (VT.isVector() || !VT.isInteger())
1286 return SDValue();
1287
1288 // If operation type is 'undesirable', e.g. i16 on x86, consider
1289 // promoting it.
1290 unsigned Opc = Op.getOpcode();
1291 if (TLI.isTypeDesirableForOp(Opc, VT))
1292 return SDValue();
1293
1294 EVT PVT = VT;
1295 // Consult target whether it is a good idea to promote this operation and
1296 // what's the right type to promote it to.
1297 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1298 assert(PVT != VT && "Don't know what type to promote to!")(static_cast <bool> (PVT != VT && "Don't know what type to promote to!"
) ? void (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1298, __extension__ __PRETTY_FUNCTION__))
;
1299
1300 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1301
1302 bool Replace0 = false;
1303 SDValue N0 = Op.getOperand(0);
1304 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1305
1306 bool Replace1 = false;
1307 SDValue N1 = Op.getOperand(1);
1308 SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
1309 SDLoc DL(Op);
1310
1311 SDValue RV =
1312 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1));
1313
1314 // We are always replacing N0/N1's use in N and only need additional
1315 // replacements if there are additional uses.
1316 // Note: We are checking uses of the *nodes* (SDNode) rather than values
1317 // (SDValue) here because the node may reference multiple values
1318 // (for example, the chain value of a load node).
1319 Replace0 &= !N0->hasOneUse();
1320 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1321
1322 // Combine Op here so it is preserved past replacements.
1323 CombineTo(Op.getNode(), RV);
1324
1325 // If operands have a use ordering, make sure we deal with
1326 // predecessor first.
1327 if (Replace0 && Replace1 && N0.getNode()->isPredecessorOf(N1.getNode())) {
1328 std::swap(N0, N1);
1329 std::swap(NN0, NN1);
1330 }
1331
1332 if (Replace0) {
1333 AddToWorklist(NN0.getNode());
1334 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1335 }
1336 if (Replace1) {
1337 AddToWorklist(NN1.getNode());
1338 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1339 }
1340 return Op;
1341 }
1342 return SDValue();
1343}
1344
1345/// Promote the specified integer shift operation if the target indicates it is
1346/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1347/// i32 since i16 instructions are longer.
1348SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1349 if (!LegalOperations)
1350 return SDValue();
1351
1352 EVT VT = Op.getValueType();
1353 if (VT.isVector() || !VT.isInteger())
1354 return SDValue();
1355
1356 // If operation type is 'undesirable', e.g. i16 on x86, consider
1357 // promoting it.
1358 unsigned Opc = Op.getOpcode();
1359 if (TLI.isTypeDesirableForOp(Opc, VT))
1360 return SDValue();
1361
1362 EVT PVT = VT;
1363 // Consult target whether it is a good idea to promote this operation and
1364 // what's the right type to promote it to.
1365 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1366 assert(PVT != VT && "Don't know what type to promote to!")(static_cast <bool> (PVT != VT && "Don't know what type to promote to!"
) ? void (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1366, __extension__ __PRETTY_FUNCTION__))
;
1367
1368 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1369
1370 bool Replace = false;
1371 SDValue N0 = Op.getOperand(0);
1372 SDValue N1 = Op.getOperand(1);
1373 if (Opc == ISD::SRA)
1374 N0 = SExtPromoteOperand(N0, PVT);
1375 else if (Opc == ISD::SRL)
1376 N0 = ZExtPromoteOperand(N0, PVT);
1377 else
1378 N0 = PromoteOperand(N0, PVT, Replace);
1379
1380 if (!N0.getNode())
1381 return SDValue();
1382
1383 SDLoc DL(Op);
1384 SDValue RV =
1385 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
1386
1387 if (Replace)
1388 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1389
1390 // Deal with Op being deleted.
1391 if (Op && Op.getOpcode() != ISD::DELETED_NODE)
1392 return RV;
1393 }
1394 return SDValue();
1395}
1396
1397SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1398 if (!LegalOperations)
1399 return SDValue();
1400
1401 EVT VT = Op.getValueType();
1402 if (VT.isVector() || !VT.isInteger())
1403 return SDValue();
1404
1405 // If operation type is 'undesirable', e.g. i16 on x86, consider
1406 // promoting it.
1407 unsigned Opc = Op.getOpcode();
1408 if (TLI.isTypeDesirableForOp(Opc, VT))
1409 return SDValue();
1410
1411 EVT PVT = VT;
1412 // Consult target whether it is a good idea to promote this operation and
1413 // what's the right type to promote it to.
1414 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1415 assert(PVT != VT && "Don't know what type to promote to!")(static_cast <bool> (PVT != VT && "Don't know what type to promote to!"
) ? void (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1415, __extension__ __PRETTY_FUNCTION__))
;
1416 // fold (aext (aext x)) -> (aext x)
1417 // fold (aext (zext x)) -> (zext x)
1418 // fold (aext (sext x)) -> (sext x)
1419 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1420 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1421 }
1422 return SDValue();
1423}
1424
1425bool DAGCombiner::PromoteLoad(SDValue Op) {
1426 if (!LegalOperations)
1427 return false;
1428
1429 if (!ISD::isUNINDEXEDLoad(Op.getNode()))
1430 return false;
1431
1432 EVT VT = Op.getValueType();
1433 if (VT.isVector() || !VT.isInteger())
1434 return false;
1435
1436 // If operation type is 'undesirable', e.g. i16 on x86, consider
1437 // promoting it.
1438 unsigned Opc = Op.getOpcode();
1439 if (TLI.isTypeDesirableForOp(Opc, VT))
1440 return false;
1441
1442 EVT PVT = VT;
1443 // Consult target whether it is a good idea to promote this operation and
1444 // what's the right type to promote it to.
1445 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1446 assert(PVT != VT && "Don't know what type to promote to!")(static_cast <bool> (PVT != VT && "Don't know what type to promote to!"
) ? void (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1446, __extension__ __PRETTY_FUNCTION__))
;
1447
1448 SDLoc DL(Op);
1449 SDNode *N = Op.getNode();
1450 LoadSDNode *LD = cast<LoadSDNode>(N);
1451 EVT MemVT = LD->getMemoryVT();
1452 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1453 : LD->getExtensionType();
1454 SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT,
1455 LD->getChain(), LD->getBasePtr(),
1456 MemVT, LD->getMemOperand());
1457 SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1458
1459 LLVM_DEBUG(dbgs() << "\nPromoting "; N->dump(&DAG); dbgs() << "\nTo: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
1460 Result.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
;
1461 WorklistRemover DeadNodes(*this);
1462 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1463 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1464 deleteAndRecombine(N);
1465 AddToWorklist(Result.getNode());
1466 return true;
1467 }
1468 return false;
1469}
1470
1471/// Recursively delete a node which has no uses and any operands for
1472/// which it is the only use.
1473///
1474/// Note that this both deletes the nodes and removes them from the worklist.
1475/// It also adds any nodes who have had a user deleted to the worklist as they
1476/// may now have only one use and subject to other combines.
1477bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1478 if (!N->use_empty())
1479 return false;
1480
1481 SmallSetVector<SDNode *, 16> Nodes;
1482 Nodes.insert(N);
1483 do {
1484 N = Nodes.pop_back_val();
1485 if (!N)
1486 continue;
1487
1488 if (N->use_empty()) {
1489 for (const SDValue &ChildN : N->op_values())
1490 Nodes.insert(ChildN.getNode());
1491
1492 removeFromWorklist(N);
1493 DAG.DeleteNode(N);
1494 } else {
1495 AddToWorklist(N);
1496 }
1497 } while (!Nodes.empty());
1498 return true;
1499}
1500
1501//===----------------------------------------------------------------------===//
1502// Main DAG Combiner implementation
1503//===----------------------------------------------------------------------===//
1504
1505void DAGCombiner::Run(CombineLevel AtLevel) {
1506 // set the instance variables, so that the various visit routines may use it.
1507 Level = AtLevel;
1508 LegalDAG = Level >= AfterLegalizeDAG;
1509 LegalOperations = Level >= AfterLegalizeVectorOps;
1510 LegalTypes = Level >= AfterLegalizeTypes;
1511
1512 WorklistInserter AddNodes(*this);
1513
1514 // Add all the dag nodes to the worklist.
1515 for (SDNode &Node : DAG.allnodes())
1516 AddToWorklist(&Node);
1517
1518 // Create a dummy node (which is not added to allnodes), that adds a reference
1519 // to the root node, preventing it from being deleted, and tracking any
1520 // changes of the root.
1521 HandleSDNode Dummy(DAG.getRoot());
1522
1523 // While we have a valid worklist entry node, try to combine it.
1524 while (SDNode *N = getNextWorklistEntry()) {
1525 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1526 // N is deleted from the DAG, since they too may now be dead or may have a
1527 // reduced number of uses, allowing other xforms.
1528 if (recursivelyDeleteUnusedNodes(N))
1529 continue;
1530
1531 WorklistRemover DeadNodes(*this);
1532
1533 // If this combine is running after legalizing the DAG, re-legalize any
1534 // nodes pulled off the worklist.
1535 if (LegalDAG) {
1536 SmallSetVector<SDNode *, 16> UpdatedNodes;
1537 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1538
1539 for (SDNode *LN : UpdatedNodes)
1540 AddToWorklistWithUsers(LN);
1541
1542 if (!NIsValid)
1543 continue;
1544 }
1545
1546 LLVM_DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nCombining: "; N->dump
(&DAG); } } while (false)
;
1547
1548 // Add any operands of the new node which have not yet been combined to the
1549 // worklist as well. Because the worklist uniques things already, this
1550 // won't repeatedly process the same operand.
1551 CombinedNodes.insert(N);
1552 for (const SDValue &ChildN : N->op_values())
1553 if (!CombinedNodes.count(ChildN.getNode()))
1554 AddToWorklist(ChildN.getNode());
1555
1556 SDValue RV = combine(N);
1557
1558 if (!RV.getNode())
1559 continue;
1560
1561 ++NodesCombined;
1562
1563 // If we get back the same node we passed in, rather than a new node or
1564 // zero, we know that the node must have defined multiple values and
1565 // CombineTo was used. Since CombineTo takes care of the worklist
1566 // mechanics for us, we have no work to do in this case.
1567 if (RV.getNode() == N)
1568 continue;
1569
1570 assert(N->getOpcode() != ISD::DELETED_NODE &&(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& RV.getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? void (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1572, __extension__ __PRETTY_FUNCTION__))
1571 RV.getOpcode() != ISD::DELETED_NODE &&(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& RV.getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? void (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1572, __extension__ __PRETTY_FUNCTION__))
1572 "Node was deleted but visit returned new node!")(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& RV.getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? void (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1572, __extension__ __PRETTY_FUNCTION__))
;
1573
1574 LLVM_DEBUG(dbgs() << " ... into: "; RV.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << " ... into: "; RV.getNode()
->dump(&DAG); } } while (false)
;
1575
1576 if (N->getNumValues() == RV.getNode()->getNumValues())
1577 DAG.ReplaceAllUsesWith(N, RV.getNode());
1578 else {
1579 assert(N->getValueType(0) == RV.getValueType() &&(static_cast <bool> (N->getValueType(0) == RV.getValueType
() && N->getNumValues() == 1 && "Type mismatch"
) ? void (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1580, __extension__ __PRETTY_FUNCTION__))
1580 N->getNumValues() == 1 && "Type mismatch")(static_cast <bool> (N->getValueType(0) == RV.getValueType
() && N->getNumValues() == 1 && "Type mismatch"
) ? void (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1580, __extension__ __PRETTY_FUNCTION__))
;
1581 DAG.ReplaceAllUsesWith(N, &RV);
1582 }
1583
1584 // Push the new node and any users onto the worklist. Omit this if the
1585 // new node is the EntryToken (e.g. if a store managed to get optimized
1586 // out), because re-visiting the EntryToken and its users will not uncover
1587 // any additional opportunities, but there may be a large number of such
1588 // users, potentially causing compile time explosion.
1589 if (RV.getOpcode() != ISD::EntryToken) {
1590 AddToWorklist(RV.getNode());
1591 AddUsersToWorklist(RV.getNode());
1592 }
1593
1594 // Finally, if the node is now dead, remove it from the graph. The node
1595 // may not be dead if the replacement process recursively simplified to
1596 // something else needing this node. This will also take care of adding any
1597 // operands which have lost a user to the worklist.
1598 recursivelyDeleteUnusedNodes(N);
1599 }
1600
1601 // If the root changed (e.g. it was a dead load, update the root).
1602 DAG.setRoot(Dummy.getValue());
1603 DAG.RemoveDeadNodes();
1604}
1605
1606SDValue DAGCombiner::visit(SDNode *N) {
1607 switch (N->getOpcode()) {
1608 default: break;
1609 case ISD::TokenFactor: return visitTokenFactor(N);
1610 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1611 case ISD::ADD: return visitADD(N);
1612 case ISD::SUB: return visitSUB(N);
1613 case ISD::SADDSAT:
1614 case ISD::UADDSAT: return visitADDSAT(N);
1615 case ISD::SSUBSAT:
1616 case ISD::USUBSAT: return visitSUBSAT(N);
1617 case ISD::ADDC: return visitADDC(N);
1618 case ISD::SADDO:
1619 case ISD::UADDO: return visitADDO(N);
1620 case ISD::SUBC: return visitSUBC(N);
1621 case ISD::SSUBO:
1622 case ISD::USUBO: return visitSUBO(N);
1623 case ISD::ADDE: return visitADDE(N);
1624 case ISD::ADDCARRY: return visitADDCARRY(N);
1625 case ISD::SADDO_CARRY: return visitSADDO_CARRY(N);
1626 case ISD::SUBE: return visitSUBE(N);
1627 case ISD::SUBCARRY: return visitSUBCARRY(N);
1628 case ISD::SSUBO_CARRY: return visitSSUBO_CARRY(N);
1629 case ISD::SMULFIX:
1630 case ISD::SMULFIXSAT:
1631 case ISD::UMULFIX:
1632 case ISD::UMULFIXSAT: return visitMULFIX(N);
1633 case ISD::MUL: return visitMUL(N);
1634 case ISD::SDIV: return visitSDIV(N);
1635 case ISD::UDIV: return visitUDIV(N);
1636 case ISD::SREM:
1637 case ISD::UREM: return visitREM(N);
1638 case ISD::MULHU: return visitMULHU(N);
1639 case ISD::MULHS: return visitMULHS(N);
1640 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1641 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1642 case ISD::SMULO:
1643 case ISD::UMULO: return visitMULO(N);
1644 case ISD::SMIN:
1645 case ISD::SMAX:
1646 case ISD::UMIN:
1647 case ISD::UMAX: return visitIMINMAX(N);
1648 case ISD::AND: return visitAND(N);
1649 case ISD::OR: return visitOR(N);
1650 case ISD::XOR: return visitXOR(N);
1651 case ISD::SHL: return visitSHL(N);
1652 case ISD::SRA: return visitSRA(N);
1653 case ISD::SRL: return visitSRL(N);
1654 case ISD::ROTR:
1655 case ISD::ROTL: return visitRotate(N);
1656 case ISD::FSHL:
1657 case ISD::FSHR: return visitFunnelShift(N);
1658 case ISD::ABS: return visitABS(N);
1659 case ISD::BSWAP: return visitBSWAP(N);
1660 case ISD::BITREVERSE: return visitBITREVERSE(N);
1661 case ISD::CTLZ: return visitCTLZ(N);
1662 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1663 case ISD::CTTZ: return visitCTTZ(N);
1664 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1665 case ISD::CTPOP: return visitCTPOP(N);
1666 case ISD::SELECT: return visitSELECT(N);
1667 case ISD::VSELECT: return visitVSELECT(N);
1668 case ISD::SELECT_CC: return visitSELECT_CC(N);
1669 case ISD::SETCC: return visitSETCC(N);
1670 case ISD::SETCCCARRY: return visitSETCCCARRY(N);
1671 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1672 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1673 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1674 case ISD::AssertSext:
1675 case ISD::AssertZext: return visitAssertExt(N);
1676 case ISD::AssertAlign: return visitAssertAlign(N);
1677 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1678 case ISD::SIGN_EXTEND_VECTOR_INREG:
1679 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitEXTEND_VECTOR_INREG(N);
1680 case ISD::TRUNCATE: return visitTRUNCATE(N);
1681 case ISD::BITCAST: return visitBITCAST(N);
1682 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1683 case ISD::FADD: return visitFADD(N);
1684 case ISD::STRICT_FADD: return visitSTRICT_FADD(N);
1685 case ISD::FSUB: return visitFSUB(N);
1686 case ISD::FMUL: return visitFMUL(N);
1687 case ISD::FMA: return visitFMA(N);
1688 case ISD::FDIV: return visitFDIV(N);
1689 case ISD::FREM: return visitFREM(N);
1690 case ISD::FSQRT: return visitFSQRT(N);
1691 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1692 case ISD::FPOW: return visitFPOW(N);
1693 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1694 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1695 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1696 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1697 case ISD::FP_ROUND: return visitFP_ROUND(N);
1698 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1699 case ISD::FNEG: return visitFNEG(N);
1700 case ISD::FABS: return visitFABS(N);
1701 case ISD::FFLOOR: return visitFFLOOR(N);
1702 case ISD::FMINNUM: return visitFMINNUM(N);
1703 case ISD::FMAXNUM: return visitFMAXNUM(N);
1704 case ISD::FMINIMUM: return visitFMINIMUM(N);
1705 case ISD::FMAXIMUM: return visitFMAXIMUM(N);
1706 case ISD::FCEIL: return visitFCEIL(N);
1707 case ISD::FTRUNC: return visitFTRUNC(N);
1708 case ISD::BRCOND: return visitBRCOND(N);
1709 case ISD::BR_CC: return visitBR_CC(N);
1710 case ISD::LOAD: return visitLOAD(N);
1711 case ISD::STORE: return visitSTORE(N);
1712 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1713 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1714 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1715 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1716 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1717 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1718 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
1719 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1720 case ISD::MGATHER: return visitMGATHER(N);
1721 case ISD::MLOAD: return visitMLOAD(N);
1722 case ISD::MSCATTER: return visitMSCATTER(N);
1723 case ISD::MSTORE: return visitMSTORE(N);
1724 case ISD::LIFETIME_END: return visitLIFETIME_END(N);
1725 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
1726 case ISD::FP16_TO_FP: return visitFP16_TO_FP(N);
1727 case ISD::FREEZE: return visitFREEZE(N);
1728 case ISD::VECREDUCE_FADD:
1729 case ISD::VECREDUCE_FMUL:
1730 case ISD::VECREDUCE_ADD:
1731 case ISD::VECREDUCE_MUL:
1732 case ISD::VECREDUCE_AND:
1733 case ISD::VECREDUCE_OR:
1734 case ISD::VECREDUCE_XOR:
1735 case ISD::VECREDUCE_SMAX:
1736 case ISD::VECREDUCE_SMIN:
1737 case ISD::VECREDUCE_UMAX:
1738 case ISD::VECREDUCE_UMIN:
1739 case ISD::VECREDUCE_FMAX:
1740 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N);
1741 }
1742 return SDValue();
1743}
1744
1745SDValue DAGCombiner::combine(SDNode *N) {
1746 SDValue RV;
1747 if (!DisableGenericCombines)
1748 RV = visit(N);
1749
1750 // If nothing happened, try a target-specific DAG combine.
1751 if (!RV.getNode()) {
1752 assert(N->getOpcode() != ISD::DELETED_NODE &&(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& "Node was deleted but visit returned NULL!") ? void
(0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1753, __extension__ __PRETTY_FUNCTION__))
1753 "Node was deleted but visit returned NULL!")(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& "Node was deleted but visit returned NULL!") ? void
(0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1753, __extension__ __PRETTY_FUNCTION__))
;
1754
1755 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1756 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1757
1758 // Expose the DAG combiner to the target combiner impls.
1759 TargetLowering::DAGCombinerInfo
1760 DagCombineInfo(DAG, Level, false, this);
1761
1762 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1763 }
1764 }
1765
1766 // If nothing happened still, try promoting the operation.
1767 if (!RV.getNode()) {
1768 switch (N->getOpcode()) {
1769 default: break;
1770 case ISD::ADD:
1771 case ISD::SUB:
1772 case ISD::MUL:
1773 case ISD::AND:
1774 case ISD::OR:
1775 case ISD::XOR:
1776 RV = PromoteIntBinOp(SDValue(N, 0));
1777 break;
1778 case ISD::SHL:
1779 case ISD::SRA:
1780 case ISD::SRL:
1781 RV = PromoteIntShiftOp(SDValue(N, 0));
1782 break;
1783 case ISD::SIGN_EXTEND:
1784 case ISD::ZERO_EXTEND:
1785 case ISD::ANY_EXTEND:
1786 RV = PromoteExtend(SDValue(N, 0));
1787 break;
1788 case ISD::LOAD:
1789 if (PromoteLoad(SDValue(N, 0)))
1790 RV = SDValue(N, 0);
1791 break;
1792 }
1793 }
1794
1795 // If N is a commutative binary node, try to eliminate it if the commuted
1796 // version is already present in the DAG.
1797 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) &&
1798 N->getNumValues() == 1) {
1799 SDValue N0 = N->getOperand(0);
1800 SDValue N1 = N->getOperand(1);
1801
1802 // Constant operands are canonicalized to RHS.
1803 if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
1804 SDValue Ops[] = {N1, N0};
1805 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1806 N->getFlags());
1807 if (CSENode)
1808 return SDValue(CSENode, 0);
1809 }
1810 }
1811
1812 return RV;
1813}
1814
1815/// Given a node, return its input chain if it has one, otherwise return a null
1816/// sd operand.
1817static SDValue getInputChainForNode(SDNode *N) {
1818 if (unsigned NumOps = N->getNumOperands()) {
1819 if (N->getOperand(0).getValueType() == MVT::Other)
1820 return N->getOperand(0);
1821 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1822 return N->getOperand(NumOps-1);
1823 for (unsigned i = 1; i < NumOps-1; ++i)
1824 if (N->getOperand(i).getValueType() == MVT::Other)
1825 return N->getOperand(i);
1826 }
1827 return SDValue();
1828}
1829
1830SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1831 // If N has two operands, where one has an input chain equal to the other,
1832 // the 'other' chain is redundant.
1833 if (N->getNumOperands() == 2) {
1834 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1835 return N->getOperand(0);
1836 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1837 return N->getOperand(1);
1838 }
1839
1840 // Don't simplify token factors if optnone.
1841 if (OptLevel == CodeGenOpt::None)
1842 return SDValue();
1843
1844 // Don't simplify the token factor if the node itself has too many operands.
1845 if (N->getNumOperands() > TokenFactorInlineLimit)
1846 return SDValue();
1847
1848 // If the sole user is a token factor, we should make sure we have a
1849 // chance to merge them together. This prevents TF chains from inhibiting
1850 // optimizations.
1851 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
1852 AddToWorklist(*(N->use_begin()));
1853
1854 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1855 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1856 SmallPtrSet<SDNode*, 16> SeenOps;
1857 bool Changed = false; // If we should replace this token factor.
1858
1859 // Start out with this token factor.
1860 TFs.push_back(N);
1861
1862 // Iterate through token factors. The TFs grows when new token factors are
1863 // encountered.
1864 for (unsigned i = 0; i < TFs.size(); ++i) {
1865 // Limit number of nodes to inline, to avoid quadratic compile times.
1866 // We have to add the outstanding Token Factors to Ops, otherwise we might
1867 // drop Ops from the resulting Token Factors.
1868 if (Ops.size() > TokenFactorInlineLimit) {
1869 for (unsigned j = i; j < TFs.size(); j++)
1870 Ops.emplace_back(TFs[j], 0);
1871 // Drop unprocessed Token Factors from TFs, so we do not add them to the
1872 // combiner worklist later.
1873 TFs.resize(i);
1874 break;
1875 }
1876
1877 SDNode *TF = TFs[i];
1878 // Check each of the operands.
1879 for (const SDValue &Op : TF->op_values()) {
1880 switch (Op.getOpcode()) {
1881 case ISD::EntryToken:
1882 // Entry tokens don't need to be added to the list. They are
1883 // redundant.
1884 Changed = true;
1885 break;
1886
1887 case ISD::TokenFactor:
1888 if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) {
1889 // Queue up for processing.
1890 TFs.push_back(Op.getNode());
1891 Changed = true;
1892 break;
1893 }
1894 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1895
1896 default:
1897 // Only add if it isn't already in the list.
1898 if (SeenOps.insert(Op.getNode()).second)
1899 Ops.push_back(Op);
1900 else
1901 Changed = true;
1902 break;
1903 }
1904 }
1905 }
1906
1907 // Re-visit inlined Token Factors, to clean them up in case they have been
1908 // removed. Skip the first Token Factor, as this is the current node.
1909 for (unsigned i = 1, e = TFs.size(); i < e; i++)
1910 AddToWorklist(TFs[i]);
1911
1912 // Remove Nodes that are chained to another node in the list. Do so
1913 // by walking up chains breath-first stopping when we've seen
1914 // another operand. In general we must climb to the EntryNode, but we can exit
1915 // early if we find all remaining work is associated with just one operand as
1916 // no further pruning is possible.
1917
1918 // List of nodes to search through and original Ops from which they originate.
1919 SmallVector<std::pair<SDNode *, unsigned>, 8> Worklist;
1920 SmallVector<unsigned, 8> OpWorkCount; // Count of work for each Op.
1921 SmallPtrSet<SDNode *, 16> SeenChains;
1922 bool DidPruneOps = false;
1923
1924 unsigned NumLeftToConsider = 0;
1925 for (const SDValue &Op : Ops) {
1926 Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++));
1927 OpWorkCount.push_back(1);
1928 }
1929
1930 auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) {
1931 // If this is an Op, we can remove the op from the list. Remark any
1932 // search associated with it as from the current OpNumber.
1933 if (SeenOps.contains(Op)) {
1934 Changed = true;
1935 DidPruneOps = true;
1936 unsigned OrigOpNumber = 0;
1937 while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op)
1938 OrigOpNumber++;
1939 assert((OrigOpNumber != Ops.size()) &&(static_cast <bool> ((OrigOpNumber != Ops.size()) &&
"expected to find TokenFactor Operand") ? void (0) : __assert_fail
("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1940, __extension__ __PRETTY_FUNCTION__))
1940 "expected to find TokenFactor Operand")(static_cast <bool> ((OrigOpNumber != Ops.size()) &&
"expected to find TokenFactor Operand") ? void (0) : __assert_fail
("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1940, __extension__ __PRETTY_FUNCTION__))
;
1941 // Re-mark worklist from OrigOpNumber to OpNumber
1942 for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) {
1943 if (Worklist[i].second == OrigOpNumber) {
1944 Worklist[i].second = OpNumber;
1945 }
1946 }
1947 OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber];
1948 OpWorkCount[OrigOpNumber] = 0;
1949 NumLeftToConsider--;
1950 }
1951 // Add if it's a new chain
1952 if (SeenChains.insert(Op).second) {
1953 OpWorkCount[OpNumber]++;
1954 Worklist.push_back(std::make_pair(Op, OpNumber));
1955 }
1956 };
1957
1958 for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) {
1959 // We need at least be consider at least 2 Ops to prune.
1960 if (NumLeftToConsider <= 1)
1961 break;
1962 auto CurNode = Worklist[i].first;
1963 auto CurOpNumber = Worklist[i].second;
1964 assert((OpWorkCount[CurOpNumber] > 0) &&(static_cast <bool> ((OpWorkCount[CurOpNumber] > 0) &&
"Node should not appear in worklist") ? void (0) : __assert_fail
("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1965, __extension__ __PRETTY_FUNCTION__))
1965 "Node should not appear in worklist")(static_cast <bool> ((OpWorkCount[CurOpNumber] > 0) &&
"Node should not appear in worklist") ? void (0) : __assert_fail
("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1965, __extension__ __PRETTY_FUNCTION__))
;
1966 switch (CurNode->getOpcode()) {
1967 case ISD::EntryToken:
1968 // Hitting EntryToken is the only way for the search to terminate without
1969 // hitting
1970 // another operand's search. Prevent us from marking this operand
1971 // considered.
1972 NumLeftToConsider++;
1973 break;
1974 case ISD::TokenFactor:
1975 for (const SDValue &Op : CurNode->op_values())
1976 AddToWorklist(i, Op.getNode(), CurOpNumber);
1977 break;
1978 case ISD::LIFETIME_START:
1979 case ISD::LIFETIME_END:
1980 case ISD::CopyFromReg:
1981 case ISD::CopyToReg:
1982 AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber);
1983 break;
1984 default:
1985 if (auto *MemNode = dyn_cast<MemSDNode>(CurNode))
1986 AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber);
1987 break;
1988 }
1989 OpWorkCount[CurOpNumber]--;
1990 if (OpWorkCount[CurOpNumber] == 0)
1991 NumLeftToConsider--;
1992 }
1993
1994 // If we've changed things around then replace token factor.
1995 if (Changed) {
1996 SDValue Result;
1997 if (Ops.empty()) {
1998 // The entry token is the only possible outcome.
1999 Result = DAG.getEntryNode();
2000 } else {
2001 if (DidPruneOps) {
2002 SmallVector<SDValue, 8> PrunedOps;
2003 //
2004 for (const SDValue &Op : Ops) {
2005 if (SeenChains.count(Op.getNode()) == 0)
2006 PrunedOps.push_back(Op);
2007 }
2008 Result = DAG.getTokenFactor(SDLoc(N), PrunedOps);
2009 } else {
2010 Result = DAG.getTokenFactor(SDLoc(N), Ops);
2011 }
2012 }
2013 return Result;
2014 }
2015 return SDValue();
2016}
2017
2018/// MERGE_VALUES can always be eliminated.
2019SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
2020 WorklistRemover DeadNodes(*this);
2021 // Replacing results may cause a different MERGE_VALUES to suddenly
2022 // be CSE'd with N, and carry its uses with it. Iterate until no
2023 // uses remain, to ensure that the node can be safely deleted.
2024 // First add the users of this node to the work list so that they
2025 // can be tried again once they have new operands.
2026 AddUsersToWorklist(N);
2027 do {
2028 // Do as a single replacement to avoid rewalking use lists.
2029 SmallVector<SDValue, 8> Ops;
2030 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
2031 Ops.push_back(N->getOperand(i));
2032 DAG.ReplaceAllUsesWith(N, Ops.data());
2033 } while (!N->use_empty());
2034 deleteAndRecombine(N);
2035 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2036}
2037
2038/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a
2039/// ConstantSDNode pointer else nullptr.
2040static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
2041 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
2042 return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
2043}
2044
2045/// Return true if 'Use' is a load or a store that uses N as its base pointer
2046/// and that N may be folded in the load / store addressing mode.
2047static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, SelectionDAG &DAG,
2048 const TargetLowering &TLI) {
2049 EVT VT;
2050 unsigned AS;
2051
2052 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
2053 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
2054 return false;
2055 VT = LD->getMemoryVT();
2056 AS = LD->getAddressSpace();
2057 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
2058 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
2059 return false;
2060 VT = ST->getMemoryVT();
2061 AS = ST->getAddressSpace();
2062 } else if (MaskedLoadSDNode *LD = dyn_cast<MaskedLoadSDNode>(Use)) {
2063 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
2064 return false;
2065 VT = LD->getMemoryVT();
2066 AS = LD->getAddressSpace();
2067 } else if (MaskedStoreSDNode *ST = dyn_cast<MaskedStoreSDNode>(Use)) {
2068 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
2069 return false;
2070 VT = ST->getMemoryVT();
2071 AS = ST->getAddressSpace();
2072 } else
2073 return false;
2074
2075 TargetLowering::AddrMode AM;
2076 if (N->getOpcode() == ISD::ADD) {
2077 AM.HasBaseReg = true;
2078 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2079 if (Offset)
2080 // [reg +/- imm]
2081 AM.BaseOffs = Offset->getSExtValue();
2082 else
2083 // [reg +/- reg]
2084 AM.Scale = 1;
2085 } else if (N->getOpcode() == ISD::SUB) {
2086 AM.HasBaseReg = true;
2087 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2088 if (Offset)
2089 // [reg +/- imm]
2090 AM.BaseOffs = -Offset->getSExtValue();
2091 else
2092 // [reg +/- reg]
2093 AM.Scale = 1;
2094 } else
2095 return false;
2096
2097 return TLI.isLegalAddressingMode(DAG.getDataLayout(), AM,
2098 VT.getTypeForEVT(*DAG.getContext()), AS);
2099}
2100
2101SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
2102 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 &&(static_cast <bool> (TLI.isBinOp(BO->getOpcode()) &&
BO->getNumValues() == 1 && "Unexpected binary operator"
) ? void (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2103, __extension__ __PRETTY_FUNCTION__))
2103 "Unexpected binary operator")(static_cast <bool> (TLI.isBinOp(BO->getOpcode()) &&
BO->getNumValues() == 1 && "Unexpected binary operator"
) ? void (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2103, __extension__ __PRETTY_FUNCTION__))
;
2104
2105 // Don't do this unless the old select is going away. We want to eliminate the
2106 // binary operator, not replace a binop with a select.
2107 // TODO: Handle ISD::SELECT_CC.
2108 unsigned SelOpNo = 0;
2109 SDValue Sel = BO->getOperand(0);
2110 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
2111 SelOpNo = 1;
2112 Sel = BO->getOperand(1);
2113 }
2114
2115 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
2116 return SDValue();
2117
2118 SDValue CT = Sel.getOperand(1);
2119 if (!isConstantOrConstantVector(CT, true) &&
2120 !DAG.isConstantFPBuildVectorOrConstantFP(CT))
2121 return SDValue();
2122
2123 SDValue CF = Sel.getOperand(2);
2124 if (!isConstantOrConstantVector(CF, true) &&
2125 !DAG.isConstantFPBuildVectorOrConstantFP(CF))
2126 return SDValue();
2127
2128 // Bail out if any constants are opaque because we can't constant fold those.
2129 // The exception is "and" and "or" with either 0 or -1 in which case we can
2130 // propagate non constant operands into select. I.e.:
2131 // and (select Cond, 0, -1), X --> select Cond, 0, X
2132 // or X, (select Cond, -1, 0) --> select Cond, -1, X
2133 auto BinOpcode = BO->getOpcode();
2134 bool CanFoldNonConst =
2135 (BinOpcode == ISD::AND || BinOpcode == ISD::OR) &&
2136 (isNullOrNullSplat(CT) || isAllOnesOrAllOnesSplat(CT)) &&
2137 (isNullOrNullSplat(CF) || isAllOnesOrAllOnesSplat(CF));
2138
2139 SDValue CBO = BO->getOperand(SelOpNo ^ 1);
2140 if (!CanFoldNonConst &&
2141 !isConstantOrConstantVector(CBO, true) &&
2142 !DAG.isConstantFPBuildVectorOrConstantFP(CBO))
2143 return SDValue();
2144
2145 EVT VT = BO->getValueType(0);
2146
2147 // We have a select-of-constants followed by a binary operator with a
2148 // constant. Eliminate the binop by pulling the constant math into the select.
2149 // Example: add (select Cond, CT, CF), CBO --> select Cond, CT + CBO, CF + CBO
2150 SDLoc DL(Sel);
2151 SDValue NewCT = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CT)
2152 : DAG.getNode(BinOpcode, DL, VT, CT, CBO);
2153 if (!CanFoldNonConst && !NewCT.isUndef() &&
2154 !isConstantOrConstantVector(NewCT, true) &&
2155 !DAG.isConstantFPBuildVectorOrConstantFP(NewCT))
2156 return SDValue();
2157
2158 SDValue NewCF = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CF)
2159 : DAG.getNode(BinOpcode, DL, VT, CF, CBO);
2160 if (!CanFoldNonConst && !NewCF.isUndef() &&
2161 !isConstantOrConstantVector(NewCF, true) &&
2162 !DAG.isConstantFPBuildVectorOrConstantFP(NewCF))
2163 return SDValue();
2164
2165 SDValue SelectOp = DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF);
2166 SelectOp->setFlags(BO->getFlags());
2167 return SelectOp;
2168}
2169
2170static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) {
2171 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(static_cast <bool> ((N->getOpcode() == ISD::ADD || N
->getOpcode() == ISD::SUB) && "Expecting add or sub"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2172, __extension__ __PRETTY_FUNCTION__))
2172 "Expecting add or sub")(static_cast <bool> ((N->getOpcode() == ISD::ADD || N
->getOpcode() == ISD::SUB) && "Expecting add or sub"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2172, __extension__ __PRETTY_FUNCTION__))
;
2173
2174 // Match a constant operand and a zext operand for the math instruction:
2175 // add Z, C
2176 // sub C, Z
2177 bool IsAdd = N->getOpcode() == ISD::ADD;
2178 SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0);
2179 SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1);
2180 auto *CN = dyn_cast<ConstantSDNode>(C);
2181 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND)
2182 return SDValue();
2183
2184 // Match the zext operand as a setcc of a boolean.
2185 if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
2186 Z.getOperand(0).getValueType() != MVT::i1)
2187 return SDValue();
2188
2189 // Match the compare as: setcc (X & 1), 0, eq.
2190 SDValue SetCC = Z.getOperand(0);
2191 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
2192 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) ||
2193 SetCC.getOperand(0).getOpcode() != ISD::AND ||
2194 !isOneConstant(SetCC.getOperand(0).getOperand(1)))
2195 return SDValue();
2196
2197 // We are adding/subtracting a constant and an inverted low bit. Turn that
2198 // into a subtract/add of the low bit with incremented/decremented constant:
2199 // add (zext i1 (seteq (X & 1), 0)), C --> sub C+1, (zext (X & 1))
2200 // sub C, (zext i1 (seteq (X & 1), 0)) --> add C-1, (zext (X & 1))
2201 EVT VT = C.getValueType();
2202 SDLoc DL(N);
2203 SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT);
2204 SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) :
2205 DAG.getConstant(CN->getAPIntValue() - 1, DL, VT);
2206 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
2207}
2208
2209/// Try to fold a 'not' shifted sign-bit with add/sub with constant operand into
2210/// a shift and add with a different constant.
2211static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) {
2212 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(static_cast <bool> ((N->getOpcode() == ISD::ADD || N
->getOpcode() == ISD::SUB) && "Expecting add or sub"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2213, __extension__ __PRETTY_FUNCTION__))
2213 "Expecting add or sub")(static_cast <bool> ((N->getOpcode() == ISD::ADD || N
->getOpcode() == ISD::SUB) && "Expecting add or sub"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2213, __extension__ __PRETTY_FUNCTION__))
;
2214
2215 // We need a constant operand for the add/sub, and the other operand is a
2216 // logical shift right: add (srl), C or sub C, (srl).
2217 bool IsAdd = N->getOpcode() == ISD::ADD;
2218 SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0);
2219 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1);
2220 if (!DAG.isConstantIntBuildVectorOrConstantInt(ConstantOp) ||
2221 ShiftOp.getOpcode() != ISD::SRL)
2222 return SDValue();
2223
2224 // The shift must be of a 'not' value.
2225 SDValue Not = ShiftOp.getOperand(0);
2226 if (!Not.hasOneUse() || !isBitwiseNot(Not))
2227 return SDValue();
2228
2229 // The shift must be moving the sign bit to the least-significant-bit.
2230 EVT VT = ShiftOp.getValueType();
2231 SDValue ShAmt = ShiftOp.getOperand(1);
2232 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
2233 if (!ShAmtC || ShAmtC->getAPIntValue() != (VT.getScalarSizeInBits() - 1))
2234 return SDValue();
2235
2236 // Eliminate the 'not' by adjusting the shift and add/sub constant:
2237 // add (srl (not X), 31), C --> add (sra X, 31), (C + 1)
2238 // sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1)
2239 SDLoc DL(N);
2240 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
2241 SDValue NewShift = DAG.getNode(ShOpcode, DL, VT, Not.getOperand(0), ShAmt);
2242 if (SDValue NewC =
2243 DAG.FoldConstantArithmetic(IsAdd ? ISD::ADD : ISD::SUB, DL, VT,
2244 {ConstantOp, DAG.getConstant(1, DL, VT)}))
2245 return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC);
2246 return SDValue();
2247}
2248
2249/// Try to fold a node that behaves like an ADD (note that N isn't necessarily
2250/// an ISD::ADD here, it could for example be an ISD::OR if we know that there
2251/// are no common bits set in the operands).
2252SDValue DAGCombiner::visitADDLike(SDNode *N) {
2253 SDValue N0 = N->getOperand(0);
2254 SDValue N1 = N->getOperand(1);
2255 EVT VT = N0.getValueType();
2256 SDLoc DL(N);
2257
2258 // fold vector ops
2259 if (VT.isVector()) {
2260 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2261 return FoldedVOp;
2262
2263 // fold (add x, 0) -> x, vector edition
2264 if (ISD::isConstantSplatVectorAllZeros(N1.getNode()))
2265 return N0;
2266 if (ISD::isConstantSplatVectorAllZeros(N0.getNode()))
2267 return N1;
2268 }
2269
2270 // fold (add x, undef) -> undef
2271 if (N0.isUndef())
2272 return N0;
2273
2274 if (N1.isUndef())
2275 return N1;
2276
2277 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2278 // canonicalize constant to RHS
2279 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2280 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
2281 // fold (add c1, c2) -> c1+c2
2282 return DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0, N1});
2283 }
2284
2285 // fold (add x, 0) -> x
2286 if (isNullConstant(N1))
2287 return N0;
2288
2289 if (isConstantOrConstantVector(N1, /* NoOpaque */ true)) {
2290 // fold ((A-c1)+c2) -> (A+(c2-c1))
2291 if (N0.getOpcode() == ISD::SUB &&
2292 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) {
2293 SDValue Sub =
2294 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N1, N0.getOperand(1)});
2295 assert(Sub && "Constant folding failed")(static_cast <bool> (Sub && "Constant folding failed"
) ? void (0) : __assert_fail ("Sub && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2295, __extension__ __PRETTY_FUNCTION__))
;
2296 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Sub);
2297 }
2298
2299 // fold ((c1-A)+c2) -> (c1+c2)-A
2300 if (N0.getOpcode() == ISD::SUB &&
2301 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaque */ true)) {
2302 SDValue Add =
2303 DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N0.getOperand(0)});
2304 assert(Add && "Constant folding failed")(static_cast <bool> (Add && "Constant folding failed"
) ? void (0) : __assert_fail ("Add && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2304, __extension__ __PRETTY_FUNCTION__))
;
2305 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2306 }
2307
2308 // add (sext i1 X), 1 -> zext (not i1 X)
2309 // We don't transform this pattern:
2310 // add (zext i1 X), -1 -> sext (not i1 X)
2311 // because most (?) targets generate better code for the zext form.
2312 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2313 isOneOrOneSplat(N1)) {
2314 SDValue X = N0.getOperand(0);
2315 if ((!LegalOperations ||
2316 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) &&
2317 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) &&
2318 X.getScalarValueSizeInBits() == 1) {
2319 SDValue Not = DAG.getNOT(DL, X, X.getValueType());
2320 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not);
2321 }
2322 }
2323
2324 // Fold (add (or x, c0), c1) -> (add x, (c0 + c1)) if (or x, c0) is
2325 // equivalent to (add x, c0).
2326 if (N0.getOpcode() == ISD::OR &&
2327 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true) &&
2328 DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) {
2329 if (SDValue Add0 = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT,
2330 {N1, N0.getOperand(1)}))
2331 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add0);
2332 }
2333 }
2334
2335 if (SDValue NewSel = foldBinOpIntoSelect(N))
2336 return NewSel;
2337
2338 // reassociate add
2339 if (!reassociationCanBreakAddressingModePattern(ISD::ADD, DL, N0, N1)) {
2340 if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
2341 return RADD;
2342
2343 // Reassociate (add (or x, c), y) -> (add add(x, y), c)) if (or x, c) is
2344 // equivalent to (add x, c).
2345 auto ReassociateAddOr = [&](SDValue N0, SDValue N1) {
2346 if (N0.getOpcode() == ISD::OR && N0.hasOneUse() &&
2347 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true) &&
2348 DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) {
2349 return DAG.getNode(ISD::ADD, DL, VT,
2350 DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(0)),
2351 N0.getOperand(1));
2352 }
2353 return SDValue();
2354 };
2355 if (SDValue Add = ReassociateAddOr(N0, N1))
2356 return Add;
2357 if (SDValue Add = ReassociateAddOr(N1, N0))
2358 return Add;
2359 }
2360 // fold ((0-A) + B) -> B-A
2361 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0)))
2362 return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2363
2364 // fold (A + (0-B)) -> A-B
2365 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2366 return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1));
2367
2368 // fold (A+(B-A)) -> B
2369 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
2370 return N1.getOperand(0);
2371
2372 // fold ((B-A)+A) -> B
2373 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
2374 return N0.getOperand(0);
2375
2376 // fold ((A-B)+(C-A)) -> (C-B)
2377 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2378 N0.getOperand(0) == N1.getOperand(1))
2379 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2380 N0.getOperand(1));
2381
2382 // fold ((A-B)+(B-C)) -> (A-C)
2383 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2384 N0.getOperand(1) == N1.getOperand(0))
2385 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
2386 N1.getOperand(1));
2387
2388 // fold (A+(B-(A+C))) to (B-C)
2389 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2390 N0 == N1.getOperand(1).getOperand(0))
2391 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2392 N1.getOperand(1).getOperand(1));
2393
2394 // fold (A+(B-(C+A))) to (B-C)
2395 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2396 N0 == N1.getOperand(1).getOperand(1))
2397 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2398 N1.getOperand(1).getOperand(0));
2399
2400 // fold (A+((B-A)+or-C)) to (B+or-C)
2401 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
2402 N1.getOperand(0).getOpcode() == ISD::SUB &&
2403 N0 == N1.getOperand(0).getOperand(1))
2404 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0),
2405 N1.getOperand(1));
2406
2407 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
2408 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2409 SDValue N00 = N0.getOperand(0);
2410 SDValue N01 = N0.getOperand(1);
2411 SDValue N10 = N1.getOperand(0);
2412 SDValue N11 = N1.getOperand(1);
2413
2414 if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10))
2415 return DAG.getNode(ISD::SUB, DL, VT,
2416 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
2417 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
2418 }
2419
2420 // fold (add (umax X, C), -C) --> (usubsat X, C)
2421 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2422 auto MatchUSUBSAT = [](ConstantSDNode *Max, ConstantSDNode *Op) {
2423 return (!Max && !Op) ||
2424 (Max && Op && Max->getAPIntValue() == (-Op->getAPIntValue()));
2425 };
2426 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT,
2427 /*AllowUndefs*/ true))
2428 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
2429 N0.getOperand(1));
2430 }
2431
2432 if (SimplifyDemandedBits(SDValue(N, 0)))
2433 return SDValue(N, 0);
2434
2435 if (isOneOrOneSplat(N1)) {
2436 // fold (add (xor a, -1), 1) -> (sub 0, a)
2437 if (isBitwiseNot(N0))
2438 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
2439 N0.getOperand(0));
2440
2441 // fold (add (add (xor a, -1), b), 1) -> (sub b, a)
2442 if (N0.getOpcode() == ISD::ADD ||
2443 N0.getOpcode() == ISD::UADDO ||
2444 N0.getOpcode() == ISD::SADDO) {
2445 SDValue A, Xor;
2446
2447 if (isBitwiseNot(N0.getOperand(0))) {
2448 A = N0.getOperand(1);
2449 Xor = N0.getOperand(0);
2450 } else if (isBitwiseNot(N0.getOperand(1))) {
2451 A = N0.getOperand(0);
2452 Xor = N0.getOperand(1);
2453 }
2454
2455 if (Xor)
2456 return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0));
2457 }
2458
2459 // Look for:
2460 // add (add x, y), 1
2461 // And if the target does not like this form then turn into:
2462 // sub y, (xor x, -1)
2463 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.hasOneUse() &&
2464 N0.getOpcode() == ISD::ADD) {
2465 SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
2466 DAG.getAllOnesConstant(DL, VT));
2467 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not);
2468 }
2469 }
2470
2471 // (x - y) + -1 -> add (xor y, -1), x
2472 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2473 isAllOnesOrAllOnesSplat(N1)) {
2474 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1), N1);
2475 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
2476 }
2477
2478 if (SDValue Combined = visitADDLikeCommutative(N0, N1, N))
2479 return Combined;
2480
2481 if (SDValue Combined = visitADDLikeCommutative(N1, N0, N))
2482 return Combined;
2483
2484 return SDValue();
2485}
2486
2487SDValue DAGCombiner::visitADD(SDNode *N) {
2488 SDValue N0 = N->getOperand(0);
2489 SDValue N1 = N->getOperand(1);
2490 EVT VT = N0.getValueType();
2491 SDLoc DL(N);
2492
2493 if (SDValue Combined = visitADDLike(N))
2494 return Combined;
2495
2496 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
2497 return V;
2498
2499 if (SDValue V = foldAddSubOfSignBit(N, DAG))
2500 return V;
2501
2502 // fold (a+b) -> (a|b) iff a and b share no bits.
2503 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
2504 DAG.haveNoCommonBitsSet(N0, N1))
2505 return DAG.getNode(ISD::OR, DL, VT, N0, N1);
2506
2507 // Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
2508 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) {
2509 const APInt &C0 = N0->getConstantOperandAPInt(0);
2510 const APInt &C1 = N1->getConstantOperandAPInt(0);
2511 return DAG.getVScale(DL, VT, C0 + C1);
2512 }
2513
2514 // fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2)
2515 if ((N0.getOpcode() == ISD::ADD) &&
2516 (N0.getOperand(1).getOpcode() == ISD::VSCALE) &&
2517 (N1.getOpcode() == ISD::VSCALE)) {
2518 const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
2519 const APInt &VS1 = N1->getConstantOperandAPInt(0);
2520 SDValue VS = DAG.getVScale(DL, VT, VS0 + VS1);
2521 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), VS);
2522 }
2523
2524 // Fold (add step_vector(c1), step_vector(c2) to step_vector(c1+c2))
2525 if (N0.getOpcode() == ISD::STEP_VECTOR &&
2526 N1.getOpcode() == ISD::STEP_VECTOR) {
2527 const APInt &C0 = N0->getConstantOperandAPInt(0);
2528 const APInt &C1 = N1->getConstantOperandAPInt(0);
2529 APInt NewStep = C0 + C1;
2530 return DAG.getStepVector(DL, VT, NewStep);
2531 }
2532
2533 // Fold a + step_vector(c1) + step_vector(c2) to a + step_vector(c1+c2)
2534 if ((N0.getOpcode() == ISD::ADD) &&
2535 (N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR) &&
2536 (N1.getOpcode() == ISD::STEP_VECTOR)) {
2537 const APInt &SV0 = N0.getOperand(1)->getConstantOperandAPInt(0);
2538 const APInt &SV1 = N1->getConstantOperandAPInt(0);
2539 APInt NewStep = SV0 + SV1;
2540 SDValue SV = DAG.getStepVector(DL, VT, NewStep);
2541 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), SV);
2542 }
2543
2544 return SDValue();
2545}
2546
2547SDValue DAGCombiner::visitADDSAT(SDNode *N) {
2548 unsigned Opcode = N->getOpcode();
2549 SDValue N0 = N->getOperand(0);
2550 SDValue N1 = N->getOperand(1);
2551 EVT VT = N0.getValueType();
2552 SDLoc DL(N);
2553
2554 // fold vector ops
2555 if (VT.isVector()) {
2556 // TODO SimplifyVBinOp
2557
2558 // fold (add_sat x, 0) -> x, vector edition
2559 if (ISD::isConstantSplatVectorAllZeros(N1.getNode()))
2560 return N0;
2561 if (ISD::isConstantSplatVectorAllZeros(N0.getNode()))
2562 return N1;
2563 }
2564
2565 // fold (add_sat x, undef) -> -1
2566 if (N0.isUndef() || N1.isUndef())
2567 return DAG.getAllOnesConstant(DL, VT);
2568
2569 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2570 // canonicalize constant to RHS
2571 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2572 return DAG.getNode(Opcode, DL, VT, N1, N0);
2573 // fold (add_sat c1, c2) -> c3
2574 return DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1});
2575 }
2576
2577 // fold (add_sat x, 0) -> x
2578 if (isNullConstant(N1))
2579 return N0;
2580
2581 // If it cannot overflow, transform into an add.
2582 if (Opcode == ISD::UADDSAT)
2583 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2584 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
2585
2586 return SDValue();
2587}
2588
2589static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
2590 bool Masked = false;
2591
2592 // First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization.
2593 while (true) {
2594 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
2595 V = V.getOperand(0);
2596 continue;
2597 }
2598
2599 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
2600 Masked = true;
2601 V = V.getOperand(0);
2602 continue;
2603 }
2604
2605 break;
2606 }
2607
2608 // If this is not a carry, return.
2609 if (V.getResNo() != 1)
2610 return SDValue();
2611
2612 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
2613 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
2614 return SDValue();
2615
2616 EVT VT = V.getNode()->getValueType(0);
2617 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT))
2618 return SDValue();
2619
2620 // If the result is masked, then no matter what kind of bool it is we can
2621 // return. If it isn't, then we need to make sure the bool type is either 0 or
2622 // 1 and not other values.
2623 if (Masked ||
2624 TLI.getBooleanContents(V.getValueType()) ==
2625 TargetLoweringBase::ZeroOrOneBooleanContent)
2626 return V;
2627
2628 return SDValue();
2629}
2630
2631/// Given the operands of an add/sub operation, see if the 2nd operand is a
2632/// masked 0/1 whose source operand is actually known to be 0/-1. If so, invert
2633/// the opcode and bypass the mask operation.
2634static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1,
2635 SelectionDAG &DAG, const SDLoc &DL) {
2636 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
2637 return SDValue();
2638
2639 EVT VT = N0.getValueType();
2640 if (DAG.ComputeNumSignBits(N1.getOperand(0)) != VT.getScalarSizeInBits())
2641 return SDValue();
2642
2643 // add N0, (and (AssertSext X, i1), 1) --> sub N0, X
2644 // sub N0, (and (AssertSext X, i1), 1) --> add N0, X
2645 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N1.getOperand(0));
2646}
2647
2648/// Helper for doing combines based on N0 and N1 being added to each other.
2649SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
2650 SDNode *LocReference) {
2651 EVT VT = N0.getValueType();
2652 SDLoc DL(LocReference);
2653
2654 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
2655 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2656 isNullOrNullSplat(N1.getOperand(0).getOperand(0)))
2657 return DAG.getNode(ISD::SUB, DL, VT, N0,
2658 DAG.getNode(ISD::SHL, DL, VT,
2659 N1.getOperand(0).getOperand(1),
2660 N1.getOperand(1)));
2661
2662 if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL))
2663 return V;
2664
2665 // Look for:
2666 // add (add x, 1), y
2667 // And if the target does not like this form then turn into:
2668 // sub y, (xor x, -1)
2669 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.hasOneUse() &&
2670 N0.getOpcode() == ISD::ADD && isOneOrOneSplat(N0.getOperand(1))) {
2671 SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
2672 DAG.getAllOnesConstant(DL, VT));
2673 return DAG.getNode(ISD::SUB, DL, VT, N1, Not);
2674 }
2675
2676 // Hoist one-use subtraction by non-opaque constant:
2677 // (x - C) + y -> (x + y) - C
2678 // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
2679 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2680 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
2681 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), N1);
2682 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2683 }
2684 // Hoist one-use subtraction from non-opaque constant:
2685 // (C - x) + y -> (y - x) + C
2686 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2687 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
2688 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2689 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(0));
2690 }
2691
2692 // If the target's bool is represented as 0/1, prefer to make this 'sub 0/1'
2693 // rather than 'add 0/-1' (the zext should get folded).
2694 // add (sext i1 Y), X --> sub X, (zext i1 Y)
2695 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
2696 N0.getOperand(0).getScalarValueSizeInBits() == 1 &&
2697 TLI.getBooleanContents(VT) == TargetLowering::ZeroOrOneBooleanContent) {
2698 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
2699 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
2700 }
2701
2702 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
2703 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2704 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
2705 if (TN->getVT() == MVT::i1) {
2706 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
2707 DAG.getConstant(1, DL, VT));
2708 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
2709 }
2710 }
2711
2712 // (add X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2713 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
2714 N1.getResNo() == 0)
2715 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
2716 N0, N1.getOperand(0), N1.getOperand(2));
2717
2718 // (add X, Carry) -> (addcarry X, 0, Carry)
2719 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2720 if (SDValue Carry = getAsCarry(TLI, N1))
2721 return DAG.getNode(ISD::ADDCARRY, DL,
2722 DAG.getVTList(VT, Carry.getValueType()), N0,
2723 DAG.getConstant(0, DL, VT), Carry);
2724
2725 return SDValue();
2726}
2727
2728SDValue DAGCombiner::visitADDC(SDNode *N) {
2729 SDValue N0 = N->getOperand(0);
2730 SDValue N1 = N->getOperand(1);
2731 EVT VT = N0.getValueType();
2732 SDLoc DL(N);
2733
2734 // If the flag result is dead, turn this into an ADD.
2735 if (!N->hasAnyUseOfValue(1))
2736 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2737 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2738
2739 // canonicalize constant to RHS.
2740 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2741 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2742 if (N0C && !N1C)
2743 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
2744
2745 // fold (addc x, 0) -> x + no carry out
2746 if (isNullConstant(N1))
2747 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
2748 DL, MVT::Glue));
2749
2750 // If it cannot overflow, transform into an add.
2751 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2752 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2753 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2754
2755 return SDValue();
2756}
2757
2758/**
2759 * Flips a boolean if it is cheaper to compute. If the Force parameters is set,
2760 * then the flip also occurs if computing the inverse is the same cost.
2761 * This function returns an empty SDValue in case it cannot flip the boolean
2762 * without increasing the cost of the computation. If you want to flip a boolean
2763 * no matter what, use DAG.getLogicalNOT.
2764 */
2765static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG,
2766 const TargetLowering &TLI,
2767 bool Force) {
2768 if (Force && isa<ConstantSDNode>(V))
2769 return DAG.getLogicalNOT(SDLoc(V), V, V.getValueType());
2770
2771 if (V.getOpcode() != ISD::XOR)
2772 return SDValue();
2773
2774 ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
2775 if (!Const)
2776 return SDValue();
2777
2778 EVT VT = V.getValueType();
2779
2780 bool IsFlip = false;
2781 switch(TLI.getBooleanContents(VT)) {
2782 case TargetLowering::ZeroOrOneBooleanContent:
2783 IsFlip = Const->isOne();
2784 break;
2785 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2786 IsFlip = Const->isAllOnesValue();
2787 break;
2788 case TargetLowering::UndefinedBooleanContent:
2789 IsFlip = (Const->getAPIntValue() & 0x01) == 1;
2790 break;
2791 }
2792
2793 if (IsFlip)
2794 return V.getOperand(0);
2795 if (Force)
2796 return DAG.getLogicalNOT(SDLoc(V), V, V.getValueType());
2797 return SDValue();
2798}
2799
2800SDValue DAGCombiner::visitADDO(SDNode *N) {
2801 SDValue N0 = N->getOperand(0);
2802 SDValue N1 = N->getOperand(1);
2803 EVT VT = N0.getValueType();
2804 bool IsSigned = (ISD::SADDO == N->getOpcode());
2805
2806 EVT CarryVT = N->getValueType(1);
2807 SDLoc DL(N);
2808
2809 // If the flag result is dead, turn this into an ADD.
2810 if (!N->hasAnyUseOfValue(1))
2811 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2812 DAG.getUNDEF(CarryVT));
2813
2814 // canonicalize constant to RHS.
2815 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2816 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
2817 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
2818
2819 // fold (addo x, 0) -> x + no carry out
2820 if (isNullOrNullSplat(N1))
2821 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
2822
2823 if (!IsSigned) {
2824 // If it cannot overflow, transform into an add.
2825 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2826 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2827 DAG.getConstant(0, DL, CarryVT));
2828
2829 // fold (uaddo (xor a, -1), 1) -> (usub 0, a) and flip carry.
2830 if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) {
2831 SDValue Sub = DAG.getNode(ISD::USUBO, DL, N->getVTList(),
2832 DAG.getConstant(0, DL, VT), N0.getOperand(0));
2833 return CombineTo(
2834 N, Sub, DAG.getLogicalNOT(DL, Sub.getValue(1), Sub->getValueType(1)));
2835 }
2836
2837 if (SDValue Combined = visitUADDOLike(N0, N1, N))
2838 return Combined;
2839
2840 if (SDValue Combined = visitUADDOLike(N1, N0, N))
2841 return Combined;
2842 }
2843
2844 return SDValue();
2845}
2846
2847SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
2848 EVT VT = N0.getValueType();
2849 if (VT.isVector())
2850 return SDValue();
2851
2852 // (uaddo X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2853 // If Y + 1 cannot overflow.
2854 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
2855 SDValue Y = N1.getOperand(0);
2856 SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType());
2857 if (DAG.computeOverflowKind(Y, One) == SelectionDAG::OFK_Never)
2858 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
2859 N1.getOperand(2));
2860 }
2861
2862 // (uaddo X, Carry) -> (addcarry X, 0, Carry)
2863 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2864 if (SDValue Carry = getAsCarry(TLI, N1))
2865 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2866 DAG.getConstant(0, SDLoc(N), VT), Carry);
2867
2868 return SDValue();
2869}
2870
2871SDValue DAGCombiner::visitADDE(SDNode *N) {
2872 SDValue N0 = N->getOperand(0);
2873 SDValue N1 = N->getOperand(1);
2874 SDValue CarryIn = N->getOperand(2);
2875
2876 // canonicalize constant to RHS
2877 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2878 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2879 if (N0C && !N1C)
2880 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
2881 N1, N0, CarryIn);
2882
2883 // fold (adde x, y, false) -> (addc x, y)
2884 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2885 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
2886
2887 return SDValue();
2888}
2889
2890SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
2891 SDValue N0 = N->getOperand(0);
2892 SDValue N1 = N->getOperand(1);
2893 SDValue CarryIn = N->getOperand(2);
2894 SDLoc DL(N);
2895
2896 // canonicalize constant to RHS
2897 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2898 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2899 if (N0C && !N1C)
2900 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);
2901
2902 // fold (addcarry x, y, false) -> (uaddo x, y)
2903 if (isNullConstant(CarryIn)) {
2904 if (!LegalOperations ||
2905 TLI.isOperationLegalOrCustom(ISD::UADDO, N->getValueType(0)))
2906 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
2907 }
2908
2909 // fold (addcarry 0, 0, X) -> (and (ext/trunc X), 1) and no carry.
2910 if (isNullConstant(N0) && isNullConstant(N1)) {
2911 EVT VT = N0.getValueType();
2912 EVT CarryVT = CarryIn.getValueType();
2913 SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT);
2914 AddToWorklist(CarryExt.getNode());
2915 return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,
2916 DAG.getConstant(1, DL, VT)),
2917 DAG.getConstant(0, DL, CarryVT));
2918 }
2919
2920 if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N))
2921 return Combined;
2922
2923 if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
2924 return Combined;
2925
2926 return SDValue();
2927}
2928
2929SDValue DAGCombiner::visitSADDO_CARRY(SDNode *N) {
2930 SDValue N0 = N->getOperand(0);
2931 SDValue N1 = N->getOperand(1);
2932 SDValue CarryIn = N->getOperand(2);
2933 SDLoc DL(N);
2934
2935 // canonicalize constant to RHS
2936 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2937 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2938 if (N0C && !N1C)
2939 return DAG.getNode(ISD::SADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn);
2940
2941 // fold (saddo_carry x, y, false) -> (saddo x, y)
2942 if (isNullConstant(CarryIn)) {
2943 if (!LegalOperations ||
2944 TLI.isOperationLegalOrCustom(ISD::SADDO, N->getValueType(0)))
2945 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, N1);
2946 }
2947
2948 return SDValue();
2949}
2950
2951/**
2952 * If we are facing some sort of diamond carry propapagtion pattern try to
2953 * break it up to generate something like:
2954 * (addcarry X, 0, (addcarry A, B, Z):Carry)
2955 *
2956 * The end result is usually an increase in operation required, but because the
2957 * carry is now linearized, other tranforms can kick in and optimize the DAG.
2958 *
2959 * Patterns typically look something like
2960 * (uaddo A, B)
2961 * / \
2962 * Carry Sum
2963 * | \
2964 * | (addcarry *, 0, Z)
2965 * | /
2966 * \ Carry
2967 * | /
2968 * (addcarry X, *, *)
2969 *
2970 * But numerous variation exist. Our goal is to identify A, B, X and Z and
2971 * produce a combine with a single path for carry propagation.
2972 */
2973static SDValue combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
2974 SDValue X, SDValue Carry0, SDValue Carry1,
2975 SDNode *N) {
2976 if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1)
2977 return SDValue();
2978 if (Carry1.getOpcode() != ISD::UADDO)
2979 return SDValue();
2980
2981 SDValue Z;
2982
2983 /**
2984 * First look for a suitable Z. It will present itself in the form of
2985 * (addcarry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true
2986 */
2987 if (Carry0.getOpcode() == ISD::ADDCARRY &&
2988 isNullConstant(Carry0.getOperand(1))) {
2989 Z = Carry0.getOperand(2);
2990 } else if (Carry0.getOpcode() == ISD::UADDO &&
2991 isOneConstant(Carry0.getOperand(1))) {
2992 EVT VT = Combiner.getSetCCResultType(Carry0.getValueType());
2993 Z = DAG.getConstant(1, SDLoc(Carry0.getOperand(1)), VT);
2994 } else {
2995 // We couldn't find a suitable Z.
2996 return SDValue();
2997 }
2998
2999
3000 auto cancelDiamond = [&](SDValue A,SDValue B) {
3001 SDLoc DL(N);
3002 SDValue NewY = DAG.getNode(ISD::ADDCARRY, DL, Carry0->getVTList(), A, B, Z);
3003 Combiner.AddToWorklist(NewY.getNode());
3004 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), X,
3005 DAG.getConstant(0, DL, X.getValueType()),
3006 NewY.getValue(1));
3007 };
3008
3009 /**
3010 * (uaddo A, B)
3011 * |
3012 * Sum
3013 * |
3014 * (addcarry *, 0, Z)
3015 */
3016 if (Carry0.getOperand(0) == Carry1.getValue(0)) {
3017 return cancelDiamond(Carry1.getOperand(0), Carry1.getOperand(1));
3018 }
3019
3020 /**
3021 * (addcarry A, 0, Z)
3022 * |
3023 * Sum
3024 * |
3025 * (uaddo *, B)
3026 */
3027 if (Carry1.getOperand(0) == Carry0.getValue(0)) {
3028 return cancelDiamond(Carry0.getOperand(0), Carry1.getOperand(1));
3029 }
3030
3031 if (Carry1.getOperand(1) == Carry0.getValue(0)) {
3032 return cancelDiamond(Carry1.getOperand(0), Carry0.getOperand(0));
3033 }
3034
3035 return SDValue();
3036}
3037
3038// If we are facing some sort of diamond carry/borrow in/out pattern try to
3039// match patterns like:
3040//
3041// (uaddo A, B) CarryIn
3042// | \ |
3043// | \ |
3044// PartialSum PartialCarryOutX /
3045// | | /
3046// | ____|____________/
3047// | / |
3048// (uaddo *, *) \________
3049// | \ \
3050// | \ |
3051// | PartialCarryOutY |
3052// | \ |
3053// | \ /
3054// AddCarrySum | ______/
3055// | /
3056// CarryOut = (or *, *)
3057//
3058// And generate ADDCARRY (or SUBCARRY) with two result values:
3059//
3060// {AddCarrySum, CarryOut} = (addcarry A, B, CarryIn)
3061//
3062// Our goal is to identify A, B, and CarryIn and produce ADDCARRY/SUBCARRY with
3063// a single path for carry/borrow out propagation:
3064static SDValue combineCarryDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
3065 const TargetLowering &TLI, SDValue Carry0,
3066 SDValue Carry1, SDNode *N) {
3067 if (Carry0.getResNo() != 1 || Carry1.getResNo() != 1)
3068 return SDValue();
3069 unsigned Opcode = Carry0.getOpcode();
3070 if (Opcode != Carry1.getOpcode())
3071 return SDValue();
3072 if (Opcode != ISD::UADDO && Opcode != ISD::USUBO)
3073 return SDValue();
3074
3075 // Canonicalize the add/sub of A and B as Carry0 and the add/sub of the
3076 // carry/borrow in as Carry1. (The top and middle uaddo nodes respectively in
3077 // the above ASCII art.)
3078 if (Carry1.getOperand(0) != Carry0.getValue(0) &&
3079 Carry1.getOperand(1) != Carry0.getValue(0))
3080 std::swap(Carry0, Carry1);
3081 if (Carry1.getOperand(0) != Carry0.getValue(0) &&
3082 Carry1.getOperand(1) != Carry0.getValue(0))
3083 return SDValue();
3084
3085 // The carry in value must be on the righthand side for subtraction.
3086 unsigned CarryInOperandNum =
3087 Carry1.getOperand(0) == Carry0.getValue(0) ? 1 : 0;
3088 if (Opcode == ISD::USUBO && CarryInOperandNum != 1)
3089 return SDValue();
3090 SDValue CarryIn = Carry1.getOperand(CarryInOperandNum);
3091
3092 unsigned NewOp = Opcode == ISD::UADDO ? ISD::ADDCARRY : ISD::SUBCARRY;
3093 if (!TLI.isOperationLegalOrCustom(NewOp, Carry0.getValue(0).getValueType()))
3094 return SDValue();
3095
3096 // Verify that the carry/borrow in is plausibly a carry/borrow bit.
3097 // TODO: make getAsCarry() aware of how partial carries are merged.
3098 if (CarryIn.getOpcode() != ISD::ZERO_EXTEND)
3099 return SDValue();
3100 CarryIn = CarryIn.getOperand(0);
3101 if (CarryIn.getValueType() != MVT::i1)
3102 return SDValue();
3103
3104 SDLoc DL(N);
3105 SDValue Merged =
3106 DAG.getNode(NewOp, DL, Carry1->getVTList(), Carry0.getOperand(0),
3107 Carry0.getOperand(1), CarryIn);
3108
3109 // Please note that because we have proven that the result of the UADDO/USUBO
3110 // of A and B feeds into the UADDO/USUBO that does the carry/borrow in, we can
3111 // therefore prove that if the first UADDO/USUBO overflows, the second
3112 // UADDO/USUBO cannot. For example consider 8-bit numbers where 0xFF is the
3113 // maximum value.
3114 //
3115 // 0xFF + 0xFF == 0xFE with carry but 0xFE + 1 does not carry
3116 // 0x00 - 0xFF == 1 with a carry/borrow but 1 - 1 == 0 (no carry/borrow)
3117 //
3118 // This is important because it means that OR and XOR can be used to merge
3119 // carry flags; and that AND can return a constant zero.
3120 //
3121 // TODO: match other operations that can merge flags (ADD, etc)
3122 DAG.ReplaceAllUsesOfValueWith(Carry1.getValue(0), Merged.getValue(0));
3123 if (N->getOpcode() == ISD::AND)
3124 return DAG.getConstant(0, DL, MVT::i1);
3125 return Merged.getValue(1);
3126}
3127
3128SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
3129 SDNode *N) {
3130 // fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
3131 if (isBitwiseNot(N0))
3132 if (SDValue NotC = extractBooleanFlip(CarryIn, DAG, TLI, true)) {
3133 SDLoc DL(N);
3134 SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(), N1,
3135 N0.getOperand(0), NotC);
3136 return CombineTo(
3137 N, Sub, DAG.getLogicalNOT(DL, Sub.getValue(1), Sub->getValueType(1)));
3138 }
3139
3140 // Iff the flag result is dead:
3141 // (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
3142 // Don't do this if the Carry comes from the uaddo. It won't remove the uaddo
3143 // or the dependency between the instructions.
3144 if ((N0.getOpcode() == ISD::ADD ||
3145 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 &&
3146 N0.getValue(1) != CarryIn)) &&
3147 isNullConstant(N1) && !N->hasAnyUseOfValue(1))
3148 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
3149 N0.getOperand(0), N0.getOperand(1), CarryIn);
3150
3151 /**
3152 * When one of the addcarry argument is itself a carry, we may be facing
3153 * a diamond carry propagation. In which case we try to transform the DAG
3154 * to ensure linear carry propagation if that is possible.
3155 */
3156 if (auto Y = getAsCarry(TLI, N1)) {
3157 // Because both are carries, Y and Z can be swapped.
3158 if (auto R = combineADDCARRYDiamond(*this, DAG, N0, Y, CarryIn, N))
3159 return R;
3160 if (auto R = combineADDCARRYDiamond(*this, DAG, N0, CarryIn, Y, N))
3161 return R;
3162 }
3163
3164 return SDValue();
3165}
3166
3167// Attempt to create a USUBSAT(LHS, RHS) node with DstVT, performing a
3168// clamp/truncation if necessary.
3169static SDValue getTruncatedUSUBSAT(EVT DstVT, EVT SrcVT, SDValue LHS,
3170 SDValue RHS, SelectionDAG &DAG,
3171 const SDLoc &DL) {
3172 assert(DstVT.getScalarSizeInBits() <= SrcVT.getScalarSizeInBits() &&(static_cast <bool> (DstVT.getScalarSizeInBits() <= SrcVT
.getScalarSizeInBits() && "Illegal truncation") ? void
(0) : __assert_fail ("DstVT.getScalarSizeInBits() <= SrcVT.getScalarSizeInBits() && \"Illegal truncation\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3173, __extension__ __PRETTY_FUNCTION__))
3173 "Illegal truncation")(static_cast <bool> (DstVT.getScalarSizeInBits() <= SrcVT
.getScalarSizeInBits() && "Illegal truncation") ? void
(0) : __assert_fail ("DstVT.getScalarSizeInBits() <= SrcVT.getScalarSizeInBits() && \"Illegal truncation\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3173, __extension__ __PRETTY_FUNCTION__))
;
3174
3175 if (DstVT == SrcVT)
3176 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS);
3177
3178 // If the LHS is zero-extended then we can perform the USUBSAT as DstVT by
3179 // clamping RHS.
3180 APInt UpperBits = APInt::getBitsSetFrom(SrcVT.getScalarSizeInBits(),
3181 DstVT.getScalarSizeInBits());
3182 if (!DAG.MaskedValueIsZero(LHS, UpperBits))
3183 return SDValue();
3184
3185 SDValue SatLimit =
3186 DAG.getConstant(APInt::getLowBitsSet(SrcVT.getScalarSizeInBits(),
3187 DstVT.getScalarSizeInBits()),
3188 DL, SrcVT);
3189 RHS = DAG.getNode(ISD::UMIN, DL, SrcVT, RHS, SatLimit);
3190 RHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, RHS);
3191 LHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, LHS);
3192 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS);
3193}
3194
3195// Try to find umax(a,b) - b or a - umin(a,b) patterns that may be converted to
3196// usubsat(a,b), optionally as a truncated type.
3197SDValue DAGCombiner::foldSubToUSubSat(EVT DstVT, SDNode *N) {
3198 if (N->getOpcode() != ISD::SUB ||
3199 !(!LegalOperations || hasOperation(ISD::USUBSAT, DstVT)))
3200 return SDValue();
3201
3202 EVT SubVT = N->getValueType(0);
3203 SDValue Op0 = N->getOperand(0);
3204 SDValue Op1 = N->getOperand(1);
3205
3206 // Try to find umax(a,b) - b or a - umin(a,b) patterns
3207 // they may be converted to usubsat(a,b).
3208 if (Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
3209 SDValue MaxLHS = Op0.getOperand(0);
3210 SDValue MaxRHS = Op0.getOperand(1);
3211 if (MaxLHS == Op1)
3212 return getTruncatedUSUBSAT(DstVT, SubVT, MaxRHS, Op1, DAG, SDLoc(N));
3213 if (MaxRHS == Op1)
3214 return getTruncatedUSUBSAT(DstVT, SubVT, MaxLHS, Op1, DAG, SDLoc(N));
3215 }
3216
3217 if (Op1.getOpcode() == ISD::UMIN && Op1.hasOneUse()) {
3218 SDValue MinLHS = Op1.getOperand(0);
3219 SDValue MinRHS = Op1.getOperand(1);
3220 if (MinLHS == Op0)
3221 return getTruncatedUSUBSAT(DstVT, SubVT, Op0, MinRHS, DAG, SDLoc(N));
3222 if (MinRHS == Op0)
3223 return getTruncatedUSUBSAT(DstVT, SubVT, Op0, MinLHS, DAG, SDLoc(N));
3224 }
3225
3226 // sub(a,trunc(umin(zext(a),b))) -> usubsat(a,trunc(umin(b,SatLimit)))
3227 if (Op1.getOpcode() == ISD::TRUNCATE &&
3228 Op1.getOperand(0).getOpcode() == ISD::UMIN &&
3229 Op1.getOperand(0).hasOneUse()) {
3230 SDValue MinLHS = Op1.getOperand(0).getOperand(0);
3231 SDValue MinRHS = Op1.getOperand(0).getOperand(1);
3232 if (MinLHS.getOpcode() == ISD::ZERO_EXTEND && MinLHS.getOperand(0) == Op0)
3233 return getTruncatedUSUBSAT(DstVT, MinLHS.getValueType(), MinLHS, MinRHS,
3234 DAG, SDLoc(N));
3235 if (MinRHS.getOpcode() == ISD::ZERO_EXTEND && MinRHS.getOperand(0) == Op0)
3236 return getTruncatedUSUBSAT(DstVT, MinLHS.getValueType(), MinRHS, MinLHS,
3237 DAG, SDLoc(N));
3238 }
3239
3240 return SDValue();
3241}
3242
3243// Since it may not be valid to emit a fold to zero for vector initializers
3244// check if we can before folding.
3245static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
3246 SelectionDAG &DAG, bool LegalOperations) {
3247 if (!VT.isVector())
3248 return DAG.getConstant(0, DL, VT);
3249 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
3250 return DAG.getConstant(0, DL, VT);
3251 return SDValue();
3252}
3253
3254SDValue DAGCombiner::visitSUB(SDNode *N) {
3255 SDValue N0 = N->getOperand(0);
3256 SDValue N1 = N->getOperand(1);
3257 EVT VT = N0.getValueType();
3258 SDLoc DL(N);
3259
3260 // fold vector ops
3261 if (VT.isVector()) {
3262 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3263 return FoldedVOp;
3264
3265 // fold (sub x, 0) -> x, vector edition
3266 if (ISD::isConstantSplatVectorAllZeros(N1.getNode()))
3267 return N0;
3268 }
3269
3270 // fold (sub x, x) -> 0
3271 // FIXME: Refactor this and xor and other similar operations together.
3272 if (N0 == N1)
3273 return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
3274
3275 // fold (sub c1, c2) -> c3
3276 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N1}))
3277 return C;
3278
3279 if (SDValue NewSel = foldBinOpIntoSelect(N))
3280 return NewSel;
3281
3282 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3283
3284 // fold (sub x, c) -> (add x, -c)
3285 if (N1C) {
3286 return DAG.getNode(ISD::ADD, DL, VT, N0,
3287 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
3288 }
3289
3290 if (isNullOrNullSplat(N0)) {
3291 unsigned BitWidth = VT.getScalarSizeInBits();
3292 // Right-shifting everything out but the sign bit followed by negation is
3293 // the same as flipping arithmetic/logical shift type without the negation:
3294 // -(X >>u 31) -> (X >>s 31)
3295 // -(X >>s 31) -> (X >>u 31)
3296 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3297 ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
3298 if (ShiftAmt && ShiftAmt->getAPIntValue() == (BitWidth - 1)) {
3299 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
3300 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
3301 return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));
3302 }
3303 }
3304
3305 // 0 - X --> 0 if the sub is NUW.
3306 if (N->getFlags().hasNoUnsignedWrap())
3307 return N0;
3308
3309 if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) {
3310 // N1 is either 0 or the minimum signed value. If the sub is NSW, then
3311 // N1 must be 0 because negating the minimum signed value is undefined.
3312 if (N->getFlags().hasNoSignedWrap())
3313 return N0;
3314
3315 // 0 - X --> X if X is 0 or the minimum signed value.
3316 return N1;
3317 }
3318
3319 // Convert 0 - abs(x).
3320 SDValue Result;
3321 if (N1->getOpcode() == ISD::ABS &&
3322 !TLI.isOperationLegalOrCustom(ISD::ABS, VT) &&
3323 TLI.expandABS(N1.getNode(), Result, DAG, true))
3324 return Result;
3325
3326 // Fold neg(splat(neg(x)) -> splat(x)
3327 if (VT.isVector()) {
3328 SDValue N1S = DAG.getSplatValue(N1, true);
3329 if (N1S && N1S.getOpcode() == ISD::SUB &&
3330 isNullConstant(N1S.getOperand(0))) {
3331 if (VT.isScalableVector())
3332 return DAG.getSplatVector(VT, DL, N1S.getOperand(1));
3333 return DAG.getSplatBuildVector(VT, DL, N1S.getOperand(1));
3334 }
3335 }
3336 }
3337
3338 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
3339 if (isAllOnesOrAllOnesSplat(N0))
3340 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
3341
3342 // fold (A - (0-B)) -> A+B
3343 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
3344 return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1));
3345
3346 // fold A-(A-B) -> B
3347 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
3348 return N1.getOperand(1);
3349
3350 // fold (A+B)-A -> B
3351 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
3352 return N0.getOperand(1);
3353
3354 // fold (A+B)-B -> A
3355 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
3356 return N0.getOperand(0);
3357
3358 // fold (A+C1)-C2 -> A+(C1-C2)
3359 if (N0.getOpcode() == ISD::ADD &&
3360 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3361 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3362 SDValue NewC =
3363 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0.getOperand(1), N1});
3364 assert(NewC && "Constant folding failed")(static_cast <bool> (NewC && "Constant folding failed"
) ? void (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3364, __extension__ __PRETTY_FUNCTION__))
;
3365 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
3366 }
3367
3368 // fold C2-(A+C1) -> (C2-C1)-A
3369 if (N1.getOpcode() == ISD::ADD) {
3370 SDValue N11 = N1.getOperand(1);
3371 if (isConstantOrConstantVector(N0, /* NoOpaques */ true) &&
3372 isConstantOrConstantVector(N11, /* NoOpaques */ true)) {
3373 SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N11});
3374 assert(NewC && "Constant folding failed")(static_cast <bool> (NewC && "Constant folding failed"
) ? void (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3374, __extension__ __PRETTY_FUNCTION__))
;
3375 return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
3376 }
3377 }
3378
3379 // fold (A-C1)-C2 -> A-(C1+C2)
3380 if (N0.getOpcode() == ISD::SUB &&
3381 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3382 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3383 SDValue NewC =
3384 DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0.getOperand(1), N1});
3385 assert(NewC && "Constant folding failed")(static_cast <bool> (NewC && "Constant folding failed"
) ? void (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3385, __extension__ __PRETTY_FUNCTION__))
;
3386 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC);
3387 }
3388
3389 // fold (c1-A)-c2 -> (c1-c2)-A
3390 if (N0.getOpcode() == ISD::SUB &&
3391 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3392 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaques */ true)) {
3393 SDValue NewC =
3394 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0.getOperand(0), N1});
3395 assert(NewC && "Constant folding failed")(static_cast <bool> (NewC && "Constant folding failed"
) ? void (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3395, __extension__ __PRETTY_FUNCTION__))
;
3396 return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1));
3397 }
3398
3399 // fold ((A+(B+or-C))-B) -> A+or-C
3400 if (N0.getOpcode() == ISD::ADD &&
3401 (N0.getOperand(1).getOpcode() == ISD::SUB ||
3402 N0.getOperand(1).getOpcode() == ISD::ADD) &&
3403 N0.getOperand(1).getOperand(0) == N1)
3404 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0),
3405 N0.getOperand(1).getOperand(1));
3406
3407 // fold ((A+(C+B))-B) -> A+C
3408 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD &&
3409 N0.getOperand(1).getOperand(1) == N1)
3410 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0),
3411 N0.getOperand(1).getOperand(0));
3412
3413 // fold ((A-(B-C))-C) -> A-B
3414 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
3415 N0.getOperand(1).getOperand(1) == N1)
3416 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
3417 N0.getOperand(1).getOperand(0));
3418
3419 // fold (A-(B-C)) -> A+(C-B)
3420 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse())
3421 return DAG.getNode(ISD::ADD, DL, VT, N0,
3422 DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1),
3423 N1.getOperand(0)));
3424
3425 // A - (A & B) -> A & (~B)
3426 if (N1.getOpcode() == ISD::AND) {
3427 SDValue A = N1.getOperand(0);
3428 SDValue B = N1.getOperand(1);
3429 if (A != N0)
3430 std::swap(A, B);
3431 if (A == N0 &&
3432 (N1.hasOneUse() || isConstantOrConstantVector(B, /*NoOpaques=*/true))) {
3433 SDValue InvB =
3434 DAG.getNode(ISD::XOR, DL, VT, B, DAG.getAllOnesConstant(DL, VT));
3435 return DAG.getNode(ISD::AND, DL, VT, A, InvB);
3436 }
3437 }
3438
3439 // fold (X - (-Y * Z)) -> (X + (Y * Z))
3440 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) {
3441 if (N1.getOperand(0).getOpcode() == ISD::SUB &&
3442 isNullOrNullSplat(N1.getOperand(0).getOperand(0))) {
3443 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3444 N1.getOperand(0).getOperand(1),
3445 N1.getOperand(1));
3446 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
3447 }
3448 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
3449 isNullOrNullSplat(N1.getOperand(1).getOperand(0))) {
3450 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3451 N1.getOperand(0),
3452 N1.getOperand(1).getOperand(1));
3453 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
3454 }
3455 }
3456
3457 // If either operand of a sub is undef, the result is undef
3458 if (N0.isUndef())
3459 return N0;
3460 if (N1.isUndef())
3461 return N1;
3462
3463 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
3464 return V;
3465
3466 if (SDValue V = foldAddSubOfSignBit(N, DAG))
3467 return V;
3468
3469 if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
3470 return V;
3471
3472 if (SDValue V = foldSubToUSubSat(VT, N))
3473 return V;
3474
3475 // (x - y) - 1 -> add (xor y, -1), x
3476 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) {
3477 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
3478 DAG.getAllOnesConstant(DL, VT));
3479 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
3480 }
3481
3482 // Look for:
3483 // sub y, (xor x, -1)
3484 // And if the target does not like this form then turn into:
3485 // add (add x, y), 1
3486 if (TLI.preferIncOfAddToSubOfNot(VT) && N1.hasOneUse() && isBitwiseNot(N1)) {
3487 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(0));
3488 return DAG.getNode(ISD::ADD, DL, VT, Add, DAG.getConstant(1, DL, VT));
3489 }
3490
3491 // Hoist one-use addition by non-opaque constant:
3492 // (x + C) - y -> (x - y) + C
3493 if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD &&
3494 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3495 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3496 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
3497 }
3498 // y - (x + C) -> (y - x) - C
3499 if (N1.hasOneUse() && N1.getOpcode() == ISD::ADD &&
3500 isConstantOrConstantVector(N1.getOperand(1), /*NoOpaques=*/true)) {
3501 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
3502 return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1));
3503 }
3504 // (x - C) - y -> (x - y) - C
3505 // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
3506 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3507 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3508 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3509 return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
3510 }
3511 // (C - x) - y -> C - (x + y)
3512 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3513 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
3514 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1);
3515 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
3516 }
3517
3518 // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
3519 // rather than 'sub 0/1' (the sext should get folded).
3520 // sub X, (zext i1 Y) --> add X, (sext i1 Y)
3521 if (N1.getOpcode() == ISD::ZERO_EXTEND &&
3522 N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
3523 TLI.getBooleanContents(VT) ==
3524 TargetLowering::ZeroOrNegativeOneBooleanContent) {
3525 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
3526 return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
3527 }
3528
3529 // fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X)
3530 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
3531 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
3532 SDValue X0 = N0.getOperand(0), X1 = N0.getOperand(1);
3533 SDValue S0 = N1.getOperand(0);
3534 if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0))
3535 if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1)))
3536 if (C->getAPIntValue() == (VT.getScalarSizeInBits() - 1))
3537 return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0);
3538 }
3539 }
3540
3541 // If the relocation model supports it, consider symbol offsets.
3542 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
3543 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
3544 // fold (sub Sym, c) -> Sym-c
3545 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
3546 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
3547 GA->getOffset() -
3548 (uint64_t)N1C->getSExtValue());
3549 // fold (sub Sym+c1, Sym+c2) -> c1-c2
3550 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
3551 if (GA->getGlobal() == GB->getGlobal())
3552 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
3553 DL, VT);
3554 }
3555
3556 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
3557 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
3558 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
3559 if (TN->getVT() == MVT::i1) {
3560 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
3561 DAG.getConstant(1, DL, VT));
3562 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
3563 }
3564 }
3565
3566 // canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C))
3567 if (N1.getOpcode() == ISD::VSCALE) {
3568 const APInt &IntVal = N1.getConstantOperandAPInt(0);
3569 return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
3570 }
3571
3572 // canonicalize (sub X, step_vector(C)) to (add X, step_vector(-C))
3573 if (N1.getOpcode() == ISD::STEP_VECTOR && N1.hasOneUse()) {
3574 APInt NewStep = -N1.getConstantOperandAPInt(0);
3575 return DAG.getNode(ISD::ADD, DL, VT, N0,
3576 DAG.getStepVector(DL, VT, NewStep));
3577 }
3578
3579 // Prefer an add for more folding potential and possibly better codegen:
3580 // sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1)
3581 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
3582 SDValue ShAmt = N1.getOperand(1);
3583 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
3584 if (ShAmtC &&
3585 ShAmtC->getAPIntValue() == (N1.getScalarValueSizeInBits() - 1)) {
3586 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
3587 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
3588 }
3589 }
3590
3591 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) {
3592 // (sub Carry, X) -> (addcarry (sub 0, X), 0, Carry)
3593 if (SDValue Carry = getAsCarry(TLI, N0)) {
3594 SDValue X = N1;
3595 SDValue Zero = DAG.getConstant(0, DL, VT);
3596 SDValue NegX = DAG.getNode(ISD::SUB, DL, VT, Zero, X);
3597 return DAG.getNode(ISD::ADDCARRY, DL,
3598 DAG.getVTList(VT, Carry.getValueType()), NegX, Zero,
3599 Carry);
3600 }
3601 }
3602
3603 return SDValue();
3604}
3605
3606SDValue DAGCombiner::visitSUBSAT(SDNode *N) {
3607 SDValue N0 = N->getOperand(0);
3608 SDValue N1 = N->getOperand(1);
3609 EVT VT = N0.getValueType();
3610 SDLoc DL(N);
3611
3612 // fold vector ops
3613 if (VT.isVector()) {
3614 // TODO SimplifyVBinOp
3615
3616 // fold (sub_sat x, 0) -> x, vector edition
3617 if (ISD::isConstantSplatVectorAllZeros(N1.getNode()))
3618 return N0;
3619 }
3620
3621 // fold (sub_sat x, undef) -> 0
3622 if (N0.isUndef() || N1.isUndef())
3623 return DAG.getConstant(0, DL, VT);
3624
3625 // fold (sub_sat x, x) -> 0
3626 if (N0 == N1)
3627 return DAG.getConstant(0, DL, VT);
3628
3629 // fold (sub_sat c1, c2) -> c3
3630 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1}))
3631 return C;
3632
3633 // fold (sub_sat x, 0) -> x
3634 if (isNullConstant(N1))
3635 return N0;
3636
3637 return SDValue();
3638}
3639
3640SDValue DAGCombiner::visitSUBC(SDNode *N) {
3641 SDValue N0 = N->getOperand(0);
3642 SDValue N1 = N->getOperand(1);
3643 EVT VT = N0.getValueType();
3644 SDLoc DL(N);
3645
3646 // If the flag result is dead, turn this into an SUB.
3647 if (!N->hasAnyUseOfValue(1))
3648 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3649 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3650
3651 // fold (subc x, x) -> 0 + no borrow
3652 if (N0 == N1)
3653 return CombineTo(N, DAG.getConstant(0, DL, VT),
3654 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3655
3656 // fold (subc x, 0) -> x + no borrow
3657 if (isNullConstant(N1))
3658 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3659
3660 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3661 if (isAllOnesConstant(N0))
3662 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3663 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3664
3665 return SDValue();
3666}
3667
3668SDValue DAGCombiner::visitSUBO(SDNode *N) {
3669 SDValue N0 = N->getOperand(0);
3670 SDValue N1 = N->getOperand(1);
3671 EVT VT = N0.getValueType();
3672 bool IsSigned = (ISD::SSUBO == N->getOpcode());
3673
3674 EVT CarryVT = N->getValueType(1);
3675 SDLoc DL(N);
3676
3677 // If the flag result is dead, turn this into an SUB.
3678 if (!N->hasAnyUseOfValue(1))
3679 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3680 DAG.getUNDEF(CarryVT));
3681
3682 // fold (subo x, x) -> 0 + no borrow
3683 if (N0 == N1)
3684 return CombineTo(N, DAG.getConstant(0, DL, VT),
3685 DAG.getConstant(0, DL, CarryVT));
3686
3687 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3688
3689 // fold (subox, c) -> (addo x, -c)
3690 if (IsSigned && N1C && !N1C->getAPIntValue().isMinSignedValue()) {
3691 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0,
3692 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
3693 }
3694
3695 // fold (subo x, 0) -> x + no borrow
3696 if (isNullOrNullSplat(N1))
3697 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
3698
3699 // Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3700 if (!IsSigned && isAllOnesOrAllOnesSplat(N0))
3701 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3702 DAG.getConstant(0, DL, CarryVT));
3703
3704 return SDValue();
3705}
3706
3707SDValue DAGCombiner::visitSUBE(SDNode *N) {
3708 SDValue N0 = N->getOperand(0);
3709 SDValue N1 = N->getOperand(1);
3710 SDValue CarryIn = N->getOperand(2);
3711
3712 // fold (sube x, y, false) -> (subc x, y)
3713 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
3714 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
3715
3716 return SDValue();
3717}
3718
3719SDValue DAGCombiner::visitSUBCARRY(SDNode *N) {
3720 SDValue N0 = N->getOperand(0);
3721 SDValue N1 = N->getOperand(1);
3722 SDValue CarryIn = N->getOperand(2);
3723
3724 // fold (subcarry x, y, false) -> (usubo x, y)
3725 if (isNullConstant(CarryIn)) {
3726 if (!LegalOperations ||
3727 TLI.isOperationLegalOrCustom(ISD::USUBO, N->getValueType(0)))
3728 return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
3729 }
3730
3731 return SDValue();
3732}
3733
3734SDValue DAGCombiner::visitSSUBO_CARRY(SDNode *N) {
3735 SDValue N0 = N->getOperand(0);
3736 SDValue N1 = N->getOperand(1);
3737 SDValue CarryIn = N->getOperand(2);
3738
3739 // fold (ssubo_carry x, y, false) -> (ssubo x, y)
3740 if (isNullConstant(CarryIn)) {
3741 if (!LegalOperations ||
3742 TLI.isOperationLegalOrCustom(ISD::SSUBO, N->getValueType(0)))
3743 return DAG.getNode(ISD::SSUBO, SDLoc(N), N->getVTList(), N0, N1);
3744 }
3745
3746 return SDValue();
3747}
3748
3749// Notice that "mulfix" can be any of SMULFIX, SMULFIXSAT, UMULFIX and
3750// UMULFIXSAT here.
3751SDValue DAGCombiner::visitMULFIX(SDNode *N) {
3752 SDValue N0 = N->getOperand(0);
3753 SDValue N1 = N->getOperand(1);
3754 SDValue Scale = N->getOperand(2);
3755 EVT VT = N0.getValueType();
3756
3757 // fold (mulfix x, undef, scale) -> 0
3758 if (N0.isUndef() || N1.isUndef())
3759 return DAG.getConstant(0, SDLoc(N), VT);
3760
3761 // Canonicalize constant to RHS (vector doesn't have to splat)
3762 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3763 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3764 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale);
3765
3766 // fold (mulfix x, 0, scale) -> 0
3767 if (isNullConstant(N1))
3768 return DAG.getConstant(0, SDLoc(N), VT);
3769
3770 return SDValue();
3771}
3772
3773SDValue DAGCombiner::visitMUL(SDNode *N) {
3774 SDValue N0 = N->getOperand(0);
3775 SDValue N1 = N->getOperand(1);
3776 EVT VT = N0.getValueType();
3777
3778 // fold (mul x, undef) -> 0
3779 if (N0.isUndef() || N1.isUndef())
3780 return DAG.getConstant(0, SDLoc(N), VT);
3781
3782 bool N1IsConst = false;
3783 bool N1IsOpaqueConst = false;
3784 APInt ConstValue1;
3785
3786 // fold vector ops
3787 if (VT.isVector()) {
3788 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3789 return FoldedVOp;
3790
3791 N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1);
3792 assert((!N1IsConst ||(static_cast <bool> ((!N1IsConst || ConstValue1.getBitWidth
() == VT.getScalarSizeInBits()) && "Splat APInt should be element width"
) ? void (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3794, __extension__ __PRETTY_FUNCTION__))
3793 ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) &&(static_cast <bool> ((!N1IsConst || ConstValue1.getBitWidth
() == VT.getScalarSizeInBits()) && "Splat APInt should be element width"
) ? void (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3794, __extension__ __PRETTY_FUNCTION__))
3794 "Splat APInt should be element width")(static_cast <bool> ((!N1IsConst || ConstValue1.getBitWidth
() == VT.getScalarSizeInBits()) && "Splat APInt should be element width"
) ? void (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3794, __extension__ __PRETTY_FUNCTION__))
;
3795 } else {
3796 N1IsConst = isa<ConstantSDNode>(N1);
3797 if (N1IsConst) {
3798 ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
3799 N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
3800 }
3801 }
3802
3803 // fold (mul c1, c2) -> c1*c2
3804 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT, {N0, N1}))
3805 return C;
3806
3807 // canonicalize constant to RHS (vector doesn't have to splat)
3808 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3809 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3810 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
3811
3812 // fold (mul x, 0) -> 0
3813 if (N1IsConst && ConstValue1.isNullValue())
3814 return N1;
3815
3816 // fold (mul x, 1) -> x
3817 if (N1IsConst && ConstValue1.isOneValue())
3818 return N0;
3819
3820 if (SDValue NewSel = foldBinOpIntoSelect(N))
3821 return NewSel;
3822
3823 // fold (mul x, -1) -> 0-x
3824 if (N1IsConst && ConstValue1.isAllOnesValue()) {
3825 SDLoc DL(N);
3826 return DAG.getNode(ISD::SUB, DL, VT,
3827 DAG.getConstant(0, DL, VT), N0);
3828 }
3829
3830 // fold (mul x, (1 << c)) -> x << c
3831 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3832 DAG.isKnownToBeAPowerOfTwo(N1) &&
3833 (!VT.isVector() || Level <= AfterLegalizeVectorOps)) {
3834 SDLoc DL(N);
3835 SDValue LogBase2 = BuildLogBase2(N1, DL);
3836 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3837 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
3838 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
3839 }
3840
3841 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
3842 if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2()) {
3843 unsigned Log2Val = (-ConstValue1).logBase2();
3844 SDLoc DL(N);
3845 // FIXME: If the input is something that is easily negated (e.g. a
3846 // single-use add), we should put the negate there.
3847 return DAG.getNode(ISD::SUB, DL, VT,
3848 DAG.getConstant(0, DL, VT),
3849 DAG.getNode(ISD::SHL, DL, VT, N0,
3850 DAG.getConstant(Log2Val, DL,
3851 getShiftAmountTy(N0.getValueType()))));
3852 }
3853
3854 // Try to transform:
3855 // (1) multiply-by-(power-of-2 +/- 1) into shift and add/sub.
3856 // mul x, (2^N + 1) --> add (shl x, N), x
3857 // mul x, (2^N - 1) --> sub (shl x, N), x
3858 // Examples: x * 33 --> (x << 5) + x
3859 // x * 15 --> (x << 4) - x
3860 // x * -33 --> -((x << 5) + x)
3861 // x * -15 --> -((x << 4) - x) ; this reduces --> x - (x << 4)
3862 // (2) multiply-by-(power-of-2 +/- power-of-2) into shifts and add/sub.
3863 // mul x, (2^N + 2^M) --> (add (shl x, N), (shl x, M))
3864 // mul x, (2^N - 2^M) --> (sub (shl x, N), (shl x, M))
3865 // Examples: x * 0x8800 --> (x << 15) + (x << 11)
3866 // x * 0xf800 --> (x << 16) - (x << 11)
3867 // x * -0x8800 --> -((x << 15) + (x << 11))
3868 // x * -0xf800 --> -((x << 16) - (x << 11)) ; (x << 11) - (x << 16)
3869 if (N1IsConst && TLI.decomposeMulByConstant(*DAG.getContext(), VT, N1)) {
3870 // TODO: We could handle more general decomposition of any constant by
3871 // having the target set a limit on number of ops and making a
3872 // callback to determine that sequence (similar to sqrt expansion).
3873 unsigned MathOp = ISD::DELETED_NODE;
3874 APInt MulC = ConstValue1.abs();
3875 // The constant `2` should be treated as (2^0 + 1).
3876 unsigned TZeros = MulC == 2 ? 0 : MulC.countTrailingZeros();
3877 MulC.lshrInPlace(TZeros);
3878 if ((MulC - 1).isPowerOf2())
3879 MathOp = ISD::ADD;
3880 else if ((MulC + 1).isPowerOf2())
3881 MathOp = ISD::SUB;
3882
3883 if (MathOp != ISD::DELETED_NODE) {
3884 unsigned ShAmt =
3885 MathOp == ISD::ADD ? (MulC - 1).logBase2() : (MulC + 1).logBase2();
3886 ShAmt += TZeros;
3887 assert(ShAmt < VT.getScalarSizeInBits() &&(static_cast <bool> (ShAmt < VT.getScalarSizeInBits(
) && "multiply-by-constant generated out of bounds shift"
) ? void (0) : __assert_fail ("ShAmt < VT.getScalarSizeInBits() && \"multiply-by-constant generated out of bounds shift\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3888, __extension__ __PRETTY_FUNCTION__))
3888 "multiply-by-constant generated out of bounds shift")(static_cast <bool> (ShAmt < VT.getScalarSizeInBits(
) && "multiply-by-constant generated out of bounds shift"
) ? void (0) : __assert_fail ("ShAmt < VT.getScalarSizeInBits() && \"multiply-by-constant generated out of bounds shift\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3888, __extension__ __PRETTY_FUNCTION__))
;
3889 SDLoc DL(N);
3890 SDValue Shl =
3891 DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT));
3892 SDValue R =
3893 TZeros ? DAG.getNode(MathOp, DL, VT, Shl,
3894 DAG.getNode(ISD::SHL, DL, VT, N0,
3895 DAG.getConstant(TZeros, DL, VT)))
3896 : DAG.getNode(MathOp, DL, VT, Shl, N0);
3897 if (ConstValue1.isNegative())
3898 R = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), R);
3899 return R;
3900 }
3901 }
3902
3903 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
3904 if (N0.getOpcode() == ISD::SHL &&
3905 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3906 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3907 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
3908 if (isConstantOrConstantVector(C3))
3909 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
3910 }
3911
3912 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
3913 // use.
3914 {
3915 SDValue Sh(nullptr, 0), Y(nullptr, 0);
3916
3917 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
3918 if (N0.getOpcode() == ISD::SHL &&
3919 isConstantOrConstantVector(N0.getOperand(1)) &&
3920 N0.getNode()->hasOneUse()) {
3921 Sh = N0; Y = N1;
3922 } else if (N1.getOpcode() == ISD::SHL &&
3923 isConstantOrConstantVector(N1.getOperand(1)) &&
3924 N1.getNode()->hasOneUse()) {
3925 Sh = N1; Y = N0;
3926 }
3927
3928 if (Sh.getNode()) {
3929 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, Sh.getOperand(0), Y);
3930 return DAG.getNode(ISD::SHL, SDLoc(N), VT, Mul, Sh.getOperand(1));
3931 }
3932 }
3933
3934 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
3935 if (DAG.isConstantIntBuildVectorOrConstantInt(N1) &&
3936 N0.getOpcode() == ISD::ADD &&
3937 DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
3938 isMulAddWithConstProfitable(N, N0, N1))
3939 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
3940 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
3941 N0.getOperand(0), N1),
3942 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
3943 N0.getOperand(1), N1));
3944
3945 // Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)).
3946 if (N0.getOpcode() == ISD::VSCALE)
3947 if (ConstantSDNode *NC1 = isConstOrConstSplat(N1)) {
3948 const APInt &C0 = N0.getConstantOperandAPInt(0);
3949 const APInt &C1 = NC1->getAPIntValue();
3950 return DAG.getVScale(SDLoc(N), VT, C0 * C1);
3951 }
3952
3953 // Fold (mul step_vector(C0), C1) to (step_vector(C0 * C1)).
3954 APInt MulVal;
3955 if (N0.getOpcode() == ISD::STEP_VECTOR)
3956 if (ISD::isConstantSplatVector(N1.getNode(), MulVal)) {
3957 const APInt &C0 = N0.getConstantOperandAPInt(0);
3958 APInt NewStep = C0 * MulVal;
3959 return DAG.getStepVector(SDLoc(N), VT, NewStep);
3960 }
3961
3962 // Fold ((mul x, 0/undef) -> 0,
3963 // (mul x, 1) -> x) -> x)
3964 // -> and(x, mask)
3965 // We can replace vectors with '0' and '1' factors with a clearing mask.
3966 if (VT.isFixedLengthVector()) {
3967 unsigned NumElts = VT.getVectorNumElements();
3968 SmallBitVector ClearMask;
3969 ClearMask.reserve(NumElts);
3970 auto IsClearMask = [&ClearMask](ConstantSDNode *V) {
3971 if (!V || V->isNullValue()) {
3972 ClearMask.push_back(true);
3973 return true;
3974 }
3975 ClearMask.push_back(false);
3976 return V->isOne();
3977 };
3978 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::AND, VT)) &&
3979 ISD::matchUnaryPredicate(N1, IsClearMask, /*AllowUndefs*/ true)) {
3980 assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector")(static_cast <bool> (N1.getOpcode() == ISD::BUILD_VECTOR
&& "Unknown constant vector") ? void (0) : __assert_fail
("N1.getOpcode() == ISD::BUILD_VECTOR && \"Unknown constant vector\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3980, __extension__ __PRETTY_FUNCTION__))
;
3981 SDLoc DL(N);
3982 EVT LegalSVT = N1.getOperand(0).getValueType();
3983 SDValue Zero = DAG.getConstant(0, DL, LegalSVT);
3984 SDValue AllOnes = DAG.getAllOnesConstant(DL, LegalSVT);
3985 SmallVector<SDValue, 16> Mask(NumElts, AllOnes);
3986 for (unsigned I = 0; I != NumElts; ++I)
3987 if (ClearMask[I])
3988 Mask[I] = Zero;
3989 return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getBuildVector(VT, DL, Mask));
3990 }
3991 }
3992
3993 // reassociate mul
3994 if (SDValue RMUL = reassociateOps(ISD::MUL, SDLoc(N), N0, N1, N->getFlags()))
3995 return RMUL;
3996
3997 return SDValue();
3998}
3999
4000/// Return true if divmod libcall is available.
4001static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
4002 const TargetLowering &TLI) {
4003 RTLIB::Libcall LC;
4004 EVT NodeType = Node->getValueType(0);
4005 if (!NodeType.isSimple())
4006 return false;
4007 switch (NodeType.getSimpleVT().SimpleTy) {
4008 default: return false; // No libcall for vector types.
4009 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
4010 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
4011 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
4012 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
4013 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
4014 }
4015
4016 return TLI.getLibcallName(LC) != nullptr;
4017}
4018
4019/// Issue divrem if both quotient and remainder are needed.
4020SDValue DAGCombiner::useDivRem(SDNode *Node) {
4021 if (Node->use_empty())
4022 return SDValue(); // This is a dead node, leave it alone.
4023
4024 unsigned Opcode = Node->getOpcode();
4025 bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
4026 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
4027
4028 // DivMod lib calls can still work on non-legal types if using lib-calls.
4029 EVT VT = Node->getValueType(0);
4030 if (VT.isVector() || !VT.isInteger())
4031 return SDValue();
4032
4033 if (!TLI.isTypeLegal(VT) && !TLI.isOperationCustom(DivRemOpc, VT))
4034 return SDValue();
4035
4036 // If DIVREM is going to get expanded into a libcall,
4037 // but there is no libcall available, then don't combine.
4038 if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) &&
4039 !isDivRemLibcallAvailable(Node, isSigned, TLI))
4040 return SDValue();
4041
4042 // If div is legal, it's better to do the normal expansion
4043 unsigned OtherOpcode = 0;
4044 if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
4045 OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
4046 if (TLI.isOperationLegalOrCustom(Opcode, VT))
4047 return SDValue();
4048 } else {
4049 OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
4050 if (TLI.isOperationLegalOrCustom(OtherOpcode, VT))
4051 return SDValue();
4052 }
4053
4054 SDValue Op0 = Node->getOperand(0);
4055 SDValue Op1 = Node->getOperand(1);
4056 SDValue combined;
4057 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
4058 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
4059 SDNode *User = *UI;
4060 if (User == Node || User->getOpcode() == ISD::DELETED_NODE ||
4061 User->use_empty())
4062 continue;
4063 // Convert the other matching node(s), too;
4064 // otherwise, the DIVREM may get target-legalized into something
4065 // target-specific that we won't be able to recognize.
4066 unsigned UserOpc = User->getOpcode();
4067 if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) &&
4068 User->getOperand(0) == Op0 &&
4069 User->getOperand(1) == Op1) {
4070 if (!combined) {
4071 if (UserOpc == OtherOpcode) {
4072 SDVTList VTs = DAG.getVTList(VT, VT);
4073 combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1);
4074 } else if (UserOpc == DivRemOpc) {
4075 combined = SDValue(User, 0);
4076 } else {
4077 assert(UserOpc == Opcode)(static_cast <bool> (UserOpc == Opcode) ? void (0) : __assert_fail
("UserOpc == Opcode", "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4077, __extension__ __PRETTY_FUNCTION__))
;
4078 continue;
4079 }
4080 }
4081 if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
4082 CombineTo(User, combined);
4083 else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
4084 CombineTo(User, combined.getValue(1));
4085 }
4086 }
4087 return combined;
4088}
4089
4090static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) {
4091 SDValue N0 = N->getOperand(0);
4092 SDValue N1 = N->getOperand(1);
4093 EVT VT = N->getValueType(0);
4094 SDLoc DL(N);
4095
4096 unsigned Opc = N->getOpcode();
4097 bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc);
4098 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4099
4100 // X / undef -> undef
4101 // X % undef -> undef
4102 // X / 0 -> undef
4103 // X % 0 -> undef
4104 // NOTE: This includes vectors where any divisor element is zero/undef.
4105 if (DAG.isUndef(Opc, {N0, N1}))
4106 return DAG.getUNDEF(VT);
4107
4108 // undef / X -> 0
4109 // undef % X -> 0
4110 if (N0.isUndef())
4111 return DAG.getConstant(0, DL, VT);
4112
4113 // 0 / X -> 0
4114 // 0 % X -> 0
4115 ConstantSDNode *N0C = isConstOrConstSplat(N0);
4116 if (N0C && N0C->isNullValue())
4117 return N0;
4118
4119 // X / X -> 1
4120 // X % X -> 0
4121 if (N0 == N1)
4122 return DAG.getConstant(IsDiv ? 1 : 0, DL, VT);
4123
4124 // X / 1 -> X
4125 // X % 1 -> 0
4126 // If this is a boolean op (single-bit element type), we can't have
4127 // division-by-zero or remainder-by-zero, so assume the divisor is 1.
4128 // TODO: Similarly, if we're zero-extending a boolean divisor, then assume
4129 // it's a 1.
4130 if ((N1C && N1C->isOne()) || (VT.getScalarType() == MVT::i1))
4131 return IsDiv ? N0 : DAG.getConstant(0, DL, VT);
4132
4133 return SDValue();
4134}
4135
4136SDValue DAGCombiner::visitSDIV(SDNode *N) {
4137 SDValue N0 = N->getOperand(0);
4138 SDValue N1 = N->getOperand(1);
4139 EVT VT = N->getValueType(0);
4140 EVT CCVT = getSetCCResultType(VT);
4141
4142 // fold vector ops
4143 if (VT.isVector())
4144 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4145 return FoldedVOp;
4146
4147 SDLoc DL(N);
4148
4149 // fold (sdiv c1, c2) -> c1/c2
4150 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4151 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, {N0, N1}))
4152 return C;
4153
4154 // fold (sdiv X, -1) -> 0-X
4155 if (N1C && N1C->isAllOnesValue())
4156 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
4157
4158 // fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0)
4159 if (N1C && N1C->getAPIntValue().isMinSignedValue())
4160 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4161 DAG.getConstant(1, DL, VT),
4162 DAG.getConstant(0, DL, VT));
4163
4164 if (SDValue V = simplifyDivRem(N, DAG))
4165 return V;
4166
4167 if (SDValue NewSel = foldBinOpIntoSelect(N))
4168 return NewSel;
4169
4170 // If we know the sign bits of both operands are zero, strength reduce to a
4171 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
4172 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
4173 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
4174
4175 if (SDValue V = visitSDIVLike(N0, N1, N)) {
4176 // If the corresponding remainder node exists, update its users with
4177 // (Dividend - (Quotient * Divisor).
4178 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(),
4179 { N0, N1 })) {
4180 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
4181 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4182 AddToWorklist(Mul.getNode());
4183 AddToWorklist(Sub.getNode());
4184 CombineTo(RemNode, Sub);
4185 }
4186 return V;
4187 }
4188
4189 // sdiv, srem -> sdivrem
4190 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
4191 // true. Otherwise, we break the simplification logic in visitREM().
4192 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4193 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
4194 if (SDValue DivRem = useDivRem(N))
4195 return DivRem;
4196
4197 return SDValue();
4198}
4199
4200SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
4201 SDLoc DL(N);
4202 EVT VT = N->getValueType(0);
4203 EVT CCVT = getSetCCResultType(VT);
4204 unsigned BitWidth = VT.getScalarSizeInBits();
4205
4206 // Helper for determining whether a value is a power-2 constant scalar or a
4207 // vector of such elements.
4208 auto IsPowerOfTwo = [](ConstantSDNode *C) {
4209 if (C->isNullValue() || C->isOpaque())
4210 return false;
4211 if (C->getAPIntValue().isPowerOf2())
4212 return true;
4213 if ((-C->getAPIntValue()).isPowerOf2())
4214 return true;
4215 return false;
4216 };
4217
4218 // fold (sdiv X, pow2) -> simple ops after legalize
4219 // FIXME: We check for the exact bit here because the generic lowering gives
4220 // better results in that case. The target-specific lowering should learn how
4221 // to handle exact sdivs efficiently.
4222 if (!N->getFlags().hasExact() && ISD::matchUnaryPredicate(N1, IsPowerOfTwo)) {
4223 // Target-specific implementation of sdiv x, pow2.
4224 if (SDValue Res = BuildSDIVPow2(N))
4225 return Res;
4226
4227 // Create constants that are functions of the shift amount value.
4228 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
4229 SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy);
4230 SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1);
4231 C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy);
4232 SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1);
4233 if (!isConstantOrConstantVector(Inexact))
4234 return SDValue();
4235
4236 // Splat the sign bit into the register
4237 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
4238 DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy));
4239 AddToWorklist(Sign.getNode());
4240
4241 // Add (N0 < 0) ? abs2 - 1 : 0;
4242 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
4243 AddToWorklist(Srl.getNode());
4244 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl);
4245 AddToWorklist(Add.getNode());
4246 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);
4247 AddToWorklist(Sra.getNode());
4248
4249 // Special case: (sdiv X, 1) -> X
4250 // Special Case: (sdiv X, -1) -> 0-X
4251 SDValue One = DAG.getConstant(1, DL, VT);
4252 SDValue AllOnes = DAG.getAllOnesConstant(DL, VT);
4253 SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ);
4254 SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ);
4255 SDValue IsOneOrAllOnes = DAG.getNode(ISD::OR, DL, CCVT, IsOne, IsAllOnes);
4256 Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra);
4257
4258 // If dividing by a positive value, we're done. Otherwise, the result must
4259 // be negated.
4260 SDValue Zero = DAG.getConstant(0, DL, VT);
4261 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra);
4262
4263 // FIXME: Use SELECT_CC once we improve SELECT_CC constant-folding.
4264 SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT);
4265 SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra);
4266 return Res;
4267 }
4268
4269 // If integer divide is expensive and we satisfy the requirements, emit an
4270 // alternate sequence. Targets may check function attributes for size/speed
4271 // trade-offs.
4272 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4273 if (isConstantOrConstantVector(N1) &&
4274 !TLI.isIntDivCheap(N->getValueType(0), Attr))
4275 if (SDValue Op = BuildSDIV(N))
4276 return Op;
4277
4278 return SDValue();
4279}
4280
4281SDValue DAGCombiner::visitUDIV(SDNode *N) {
4282 SDValue N0 = N->getOperand(0);
4283 SDValue N1 = N->getOperand(1);
4284 EVT VT = N->getValueType(0);
4285 EVT CCVT = getSetCCResultType(VT);
4286
4287 // fold vector ops
4288 if (VT.isVector())
4289 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4290 return FoldedVOp;
4291
4292 SDLoc DL(N);
4293
4294 // fold (udiv c1, c2) -> c1/c2
4295 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4296 if (SDValue C = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT, {N0, N1}))
4297 return C;
4298
4299 // fold (udiv X, -1) -> select(X == -1, 1, 0)
4300 if (N1C && N1C->getAPIntValue().isAllOnesValue())
4301 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4302 DAG.getConstant(1, DL, VT),
4303 DAG.getConstant(0, DL, VT));
4304
4305 if (SDValue V = simplifyDivRem(N, DAG))
4306 return V;
4307
4308 if (SDValue NewSel = foldBinOpIntoSelect(N))
4309 return NewSel;
4310
4311 if (SDValue V = visitUDIVLike(N0, N1, N)) {
4312 // If the corresponding remainder node exists, update its users with
4313 // (Dividend - (Quotient * Divisor).
4314 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(),
4315 { N0, N1 })) {
4316 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
4317 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4318 AddToWorklist(Mul.getNode());
4319 AddToWorklist(Sub.getNode());
4320 CombineTo(RemNode, Sub);
4321 }
4322 return V;
4323 }
4324
4325 // sdiv, srem -> sdivrem
4326 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
4327 // true. Otherwise, we break the simplification logic in visitREM().
4328 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4329 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
4330 if (SDValue DivRem = useDivRem(N))
4331 return DivRem;
4332
4333 return SDValue();
4334}
4335
4336SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) {
4337 SDLoc DL(N);
4338 EVT VT = N->getValueType(0);
4339
4340 // fold (udiv x, (1 << c)) -> x >>u c
4341 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
4342 DAG.isKnownToBeAPowerOfTwo(N1)) {
4343 SDValue LogBase2 = BuildLogBase2(N1, DL);
4344 AddToWorklist(LogBase2.getNode());
4345
4346 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
4347 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
4348 AddToWorklist(Trunc.getNode());
4349 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
4350 }
4351
4352 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
4353 if (N1.getOpcode() == ISD::SHL) {
4354 SDValue N10 = N1.getOperand(0);
4355 if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) &&
4356 DAG.isKnownToBeAPowerOfTwo(N10)) {
4357 SDValue LogBase2 = BuildLogBase2(N10, DL);
4358 AddToWorklist(LogBase2.getNode());
4359
4360 EVT ADDVT = N1.getOperand(1).getValueType();
4361 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT);
4362 AddToWorklist(Trunc.getNode());
4363 SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc);
4364 AddToWorklist(Add.getNode());
4365 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
4366 }
4367 }
4368
4369 // fold (udiv x, c) -> alternate
4370 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4371 if (isConstantOrConstantVector(N1) &&
4372 !TLI.isIntDivCheap(N->getValueType(0), Attr))
4373 if (SDValue Op = BuildUDIV(N))
4374 return Op;
4375
4376 return SDValue();
4377}
4378
4379// handles ISD::SREM and ISD::UREM
4380SDValue DAGCombiner::visitREM(SDNode *N) {
4381 unsigned Opcode = N->getOpcode();
4382 SDValue N0 = N->getOperand(0);
4383 SDValue N1 = N->getOperand(1);
4384 EVT VT = N->getValueType(0);
4385 EVT CCVT = getSetCCResultType(VT);
4386
4387 bool isSigned = (Opcode == ISD::SREM);
4388 SDLoc DL(N);
4389
4390 // fold (rem c1, c2) -> c1%c2
4391 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4392 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
4393 return C;
4394
4395 // fold (urem X, -1) -> select(X == -1, 0, x)
4396 if (!isSigned && N1C && N1C->getAPIntValue().isAllOnesValue())
4397 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4398 DAG.getConstant(0, DL, VT), N0);
4399
4400 if (SDValue V = simplifyDivRem(N, DAG))
4401 return V;
4402
4403 if (SDValue NewSel = foldBinOpIntoSelect(N))
4404 return NewSel;
4405
4406 if (isSigned) {
4407 // If we know the sign bits of both operands are zero, strength reduce to a
4408 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
4409 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
4410 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
4411 } else {
4412 if (DAG.isKnownToBeAPowerOfTwo(N1)) {
4413 // fold (urem x, pow2) -> (and x, pow2-1)
4414 SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
4415 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
4416 AddToWorklist(Add.getNode());
4417 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
4418 }
4419 if (N1.getOpcode() == ISD::SHL &&
4420 DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) {
4421 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
4422 SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
4423 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
4424 AddToWorklist(Add.getNode());
4425 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
4426 }
4427 }
4428
4429 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4430
4431 // If X/C can be simplified by the division-by-constant logic, lower
4432 // X%C to the equivalent of X-X/C*C.
4433 // Reuse the SDIVLike/UDIVLike combines - to avoid mangling nodes, the
4434 // speculative DIV must not cause a DIVREM conversion. We guard against this
4435 // by skipping the simplification if isIntDivCheap(). When div is not cheap,
4436 // combine will not return a DIVREM. Regardless, checking cheapness here
4437 // makes sense since the simplification results in fatter code.
4438 if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) {
4439 SDValue OptimizedDiv =
4440 isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N);
4441 if (OptimizedDiv.getNode()) {
4442 // If the equivalent Div node also exists, update its users.
4443 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
4444 if (SDNode *DivNode = DAG.getNodeIfExists(DivOpcode, N->getVTList(),
4445 { N0, N1 }))
4446 CombineTo(DivNode, OptimizedDiv);
4447 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1);
4448 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4449 AddToWorklist(OptimizedDiv.getNode());
4450 AddToWorklist(Mul.getNode());
4451 return Sub;
4452 }
4453 }
4454
4455 // sdiv, srem -> sdivrem
4456 if (SDValue DivRem = useDivRem(N))
4457 return DivRem.getValue(1);
4458
4459 return SDValue();
4460}
4461
4462SDValue DAGCombiner::visitMULHS(SDNode *N) {
4463 SDValue N0 = N->getOperand(0);
4464 SDValue N1 = N->getOperand(1);
4465 EVT VT = N->getValueType(0);
4466 SDLoc DL(N);
4467
4468 if (VT.isVector()) {
4469 // fold (mulhs x, 0) -> 0
4470 // do not return N0/N1, because undef node may exist.
4471 if (ISD::isConstantSplatVectorAllZeros(N0.getNode()) ||
4472 ISD::isConstantSplatVectorAllZeros(N1.getNode()))
4473 return DAG.getConstant(0, DL, VT);
4474 }
4475
4476 // fold (mulhs c1, c2)
4477 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHS, DL, VT, {N0, N1}))
4478 return C;
4479
4480 // fold (mulhs x, 0) -> 0
4481 if (isNullConstant(N1))
4482 return N1;
4483 // fold (mulhs x, 1) -> (sra x, size(x)-1)
4484 if (isOneConstant(N1))
4485 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
4486 DAG.getConstant(N0.getScalarValueSizeInBits() - 1, DL,
4487 getShiftAmountTy(N0.getValueType())));
4488
4489 // fold (mulhs x, undef) -> 0
4490 if (N0.isUndef() || N1.isUndef())
4491 return DAG.getConstant(0, DL, VT);
4492
4493 // If the type twice as wide is legal, transform the mulhs to a wider multiply
4494 // plus a shift.
4495 if (!TLI.isOperationLegalOrCustom(ISD::MULHS, VT) && VT.isSimple() &&
4496 !VT.isVector()) {
4497 MVT Simple = VT.getSimpleVT();
4498 unsigned SimpleSize = Simple.getSizeInBits();
4499 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4500 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4501 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
4502 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
4503 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
4504 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
4505 DAG.getConstant(SimpleSize, DL,
4506 getShiftAmountTy(N1.getValueType())));
4507 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
4508 }
4509 }
4510
4511 return SDValue();
4512}
4513
4514SDValue DAGCombiner::visitMULHU(SDNode *N) {
4515 SDValue N0 = N->getOperand(0);
4516 SDValue N1 = N->getOperand(1);
4517 EVT VT = N->getValueType(0);
4518 SDLoc DL(N);
4519
4520 if (VT.isVector()) {
4521 // fold (mulhu x, 0) -> 0
4522 // do not return N0/N1, because undef node may exist.
4523 if (ISD::isConstantSplatVectorAllZeros(N0.getNode()) ||
4524 ISD::isConstantSplatVectorAllZeros(N1.getNode()))
4525 return DAG.getConstant(0, DL, VT);
4526 }
4527
4528 // fold (mulhu c1, c2)
4529 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHU, DL, VT, {N0, N1}))
4530 return C;
4531
4532 // fold (mulhu x, 0) -> 0
4533 if (isNullConstant(N1))
4534 return N1;
4535 // fold (mulhu x, 1) -> 0
4536 if (isOneConstant(N1))
4537 return DAG.getConstant(0, DL, N0.getValueType());
4538 // fold (mulhu x, undef) -> 0
4539 if (N0.isUndef() || N1.isUndef())
4540 return DAG.getConstant(0, DL, VT);
4541
4542 // fold (mulhu x, (1 << c)) -> x >> (bitwidth - c)
4543 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
4544 DAG.isKnownToBeAPowerOfTwo(N1) && hasOperation(ISD::SRL, VT)) {
4545 unsigned NumEltBits = VT.getScalarSizeInBits();
4546 SDValue LogBase2 = BuildLogBase2(N1, DL);
4547 SDValue SRLAmt = DAG.getNode(
4548 ISD::SUB, DL, VT, DAG.getConstant(NumEltBits, DL, VT), LogBase2);
4549 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
4550 SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT);
4551 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
4552 }
4553
4554 // If the type twice as wide is legal, transform the mulhu to a wider multiply
4555 // plus a shift.
4556 if (!TLI.isOperationLegalOrCustom(ISD::MULHU, VT) && VT.isSimple() &&
4557 !VT.isVector()) {
4558 MVT Simple = VT.getSimpleVT();
4559 unsigned SimpleSize = Simple.getSizeInBits();
4560 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4561 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4562 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
4563 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
4564 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
4565 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
4566 DAG.getConstant(SimpleSize, DL,
4567 getShiftAmountTy(N1.getValueType())));
4568 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
4569 }
4570 }
4571
4572 return SDValue();
4573}
4574
4575/// Perform optimizations common to nodes that compute two values. LoOp and HiOp
4576/// give the opcodes for the two computations that are being performed. Return
4577/// true if a simplification was made.
4578SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
4579 unsigned HiOp) {
4580 // If the high half is not needed, just compute the low half.
4581 bool HiExists = N->hasAnyUseOfValue(1);
4582 if (!HiExists && (!LegalOperations ||
4583 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
4584 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4585 return CombineTo(N, Res, Res);
4586 }
4587
4588 // If the low half is not needed, just compute the high half.
4589 bool LoExists = N->hasAnyUseOfValue(0);
4590 if (!LoExists && (!LegalOperations ||
4591 TLI.isOperationLegalOrCustom(HiOp, N->getValueType(1)))) {
4592 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4593 return CombineTo(N, Res, Res);
4594 }
4595
4596 // If both halves are used, return as it is.
4597 if (LoExists && HiExists)
4598 return SDValue();
4599
4600 // If the two computed results can be simplified separately, separate them.
4601 if (LoExists) {
4602 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4603 AddToWorklist(Lo.getNode());
4604 SDValue LoOpt = combine(Lo.getNode());
4605 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
4606 (!LegalOperations ||
4607 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType())))
4608 return CombineTo(N, LoOpt, LoOpt);
4609 }
4610
4611 if (HiExists) {
4612 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4613 AddToWorklist(Hi.getNode());
4614 SDValue HiOpt = combine(Hi.getNode());
4615 if (HiOpt.getNode() && HiOpt != Hi &&
4616 (!LegalOperations ||
4617 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType())))
4618 return CombineTo(N, HiOpt, HiOpt);
4619 }
4620
4621 return SDValue();
4622}
4623
4624SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
4625 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
4626 return Res;
4627
4628 EVT VT = N->getValueType(0);
4629 SDLoc DL(N);
4630
4631 // If the type is twice as wide is legal, transform the mulhu to a wider
4632 // multiply plus a shift.
4633 if (VT.isSimple() && !VT.isVector()) {
4634 MVT Simple = VT.getSimpleVT();
4635 unsigned SimpleSize = Simple.getSizeInBits();
4636 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4637 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4638 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
4639 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
4640 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
4641 // Compute the high part as N1.
4642 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
4643 DAG.getConstant(SimpleSize, DL,
4644 getShiftAmountTy(Lo.getValueType())));
4645 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
4646 // Compute the low part as N0.
4647 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
4648 return CombineTo(N, Lo, Hi);
4649 }
4650 }
4651
4652 return SDValue();
4653}
4654
4655SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
4656 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
4657 return Res;
4658
4659 EVT VT = N->getValueType(0);
4660 SDLoc DL(N);
4661
4662 // (umul_lohi N0, 0) -> (0, 0)
4663 if (isNullConstant(N->getOperand(1))) {
4664 SDValue Zero = DAG.getConstant(0, DL, VT);
4665 return CombineTo(N, Zero, Zero);
4666 }
4667
4668 // (umul_lohi N0, 1) -> (N0, 0)
4669 if (isOneConstant(N->getOperand(1))) {
4670 SDValue Zero = DAG.getConstant(0, DL, VT);
4671 return CombineTo(N, N->getOperand(0), Zero);
4672 }
4673
4674 // If the type is twice as wide is legal, transform the mulhu to a wider
4675 // multiply plus a shift.
4676 if (VT.isSimple() && !VT.isVector()) {
4677 MVT Simple = VT.getSimpleVT();
4678 unsigned SimpleSize = Simple.getSizeInBits();
4679 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4680 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4681 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
4682 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
4683 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
4684 // Compute the high part as N1.
4685 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
4686 DAG.getConstant(SimpleSize, DL,
4687 getShiftAmountTy(Lo.getValueType())));
4688 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
4689 // Compute the low part as N0.
4690 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
4691 return CombineTo(N, Lo, Hi);
4692 }
4693 }
4694
4695 return SDValue();
4696}
4697
4698SDValue DAGCombiner::visitMULO(SDNode *N) {
4699 SDValue N0 = N->getOperand(0);
4700 SDValue N1 = N->getOperand(1);
4701 EVT VT = N0.getValueType();
4702 bool IsSigned = (ISD::SMULO == N->getOpcode());
4703
4704 EVT CarryVT = N->getValueType(1);
4705 SDLoc DL(N);
4706
4707 ConstantSDNode *N0C = isConstOrConstSplat(N0);
4708 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4709
4710 // fold operation with constant operands.
4711 // TODO: Move this to FoldConstantArithmetic when it supports nodes with
4712 // multiple results.
4713 if (N0C && N1C) {
4714 bool Overflow;
4715 APInt Result =
4716 IsSigned ? N0C->getAPIntValue().smul_ov(N1C->getAPIntValue(), Overflow)
4717 : N0C->getAPIntValue().umul_ov(N1C->getAPIntValue(), Overflow);
4718 return CombineTo(N, DAG.getConstant(Result, DL, VT),
4719 DAG.getBoolConstant(Overflow, DL, CarryVT, CarryVT));
4720 }
4721
4722 // canonicalize constant to RHS.
4723 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4724 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4725 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
4726
4727 // fold (mulo x, 0) -> 0 + no carry out
4728 if (isNullOrNullSplat(N1))
4729 return CombineTo(N, DAG.getConstant(0, DL, VT),
4730 DAG.getConstant(0, DL, CarryVT));
4731
4732 // (mulo x, 2) -> (addo x, x)
4733 if (N1C && N1C->getAPIntValue() == 2)
4734 return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL,
4735 N->getVTList(), N0, N0);
4736
4737 if (IsSigned) {
4738 // A 1 bit SMULO overflows if both inputs are 1.
4739 if (VT.getScalarSizeInBits() == 1) {
4740 SDValue And = DAG.getNode(ISD::AND, DL, VT, N0, N1);
4741 return CombineTo(N, And,
4742 DAG.getSetCC(DL, CarryVT, And,
4743 DAG.getConstant(0, DL, VT), ISD::SETNE));
4744 }
4745
4746 // Multiplying n * m significant bits yields a result of n + m significant
4747 // bits. If the total number of significant bits does not exceed the
4748 // result bit width (minus 1), there is no overflow.
4749 unsigned SignBits = DAG.ComputeNumSignBits(N0);
4750 if (SignBits > 1)
4751 SignBits += DAG.ComputeNumSignBits(N1);
4752 if (SignBits > VT.getScalarSizeInBits() + 1)
4753 return CombineTo(N, DAG.getNode(ISD::MUL, DL, VT, N0, N1),
4754 DAG.getConstant(0, DL, CarryVT));
4755 } else {
4756 KnownBits N1Known = DAG.computeKnownBits(N1);
4757 KnownBits N0Known = DAG.computeKnownBits(N0);
4758 bool Overflow;
4759 (void)N0Known.getMaxValue().umul_ov(N1Known.getMaxValue(), Overflow);
4760 if (!Overflow)
4761 return CombineTo(N, DAG.getNode(ISD::MUL, DL, VT, N0, N1),
4762 DAG.getConstant(0, DL, CarryVT));
4763 }
4764
4765 return SDValue();
4766}
4767
4768SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
4769 SDValue N0 = N->getOperand(0);
4770 SDValue N1 = N->getOperand(1);
4771 EVT VT = N0.getValueType();
4772 unsigned Opcode = N->getOpcode();
4773
4774 // fold vector ops
4775 if (VT.isVector())
4776 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4777 return FoldedVOp;
4778
4779 // fold operation with constant operands.
4780 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, SDLoc(N), VT, {N0, N1}))
4781 return C;
4782
4783 // canonicalize constant to RHS
4784 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4785 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4786 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
4787
4788 // Is sign bits are zero, flip between UMIN/UMAX and SMIN/SMAX.
4789 // Only do this if the current op isn't legal and the flipped is.
4790 if (!TLI.isOperationLegal(Opcode, VT) &&
4791 (N0.isUndef() || DAG.SignBitIsZero(N0)) &&
4792 (N1.isUndef() || DAG.SignBitIsZero(N1))) {
4793 unsigned AltOpcode;
4794 switch (Opcode) {
4795 case ISD::SMIN: AltOpcode = ISD::UMIN; break;
4796 case ISD::SMAX: AltOpcode = ISD::UMAX; break;
4797 case ISD::UMIN: AltOpcode = ISD::SMIN; break;
4798 case ISD::UMAX: AltOpcode = ISD::SMAX; break;
4799 default: llvm_unreachable("Unknown MINMAX opcode")::llvm::llvm_unreachable_internal("Unknown MINMAX opcode", "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4799)
;
4800 }
4801 if (TLI.isOperationLegal(AltOpcode, VT))
4802 return DAG.getNode(AltOpcode, SDLoc(N), VT, N0, N1);
4803 }
4804
4805 // Simplify the operands using demanded-bits information.
4806 if (SimplifyDemandedBits(SDValue(N, 0)))
4807 return SDValue(N, 0);
4808
4809 return SDValue();
4810}
4811
4812/// If this is a bitwise logic instruction and both operands have the same
4813/// opcode, try to sink the other opcode after the logic instruction.
4814SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
4815 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4816 EVT VT = N0.getValueType();
4817 unsigned LogicOpcode = N->getOpcode();
4818 unsigned HandOpcode = N0.getOpcode();
4819 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||(static_cast <bool> ((LogicOpcode == ISD::AND || LogicOpcode
== ISD::OR || LogicOpcode == ISD::XOR) && "Expected logic opcode"
) ? void (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4820, __extension__ __PRETTY_FUNCTION__))
4820 LogicOpcode == ISD::XOR) && "Expected logic opcode")(static_cast <bool> ((LogicOpcode == ISD::AND || LogicOpcode
== ISD::OR || LogicOpcode == ISD::XOR) && "Expected logic opcode"
) ? void (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4820, __extension__ __PRETTY_FUNCTION__))
;
4821 assert(HandOpcode == N1.getOpcode() && "Bad input!")(static_cast <bool> (HandOpcode == N1.getOpcode() &&
"Bad input!") ? void (0) : __assert_fail ("HandOpcode == N1.getOpcode() && \"Bad input!\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4821, __extension__ __PRETTY_FUNCTION__))
;
4822
4823 // Bail early if none of these transforms apply.
4824 if (N0.getNumOperands() == 0)
4825 return SDValue();
4826
4827 // FIXME: We should check number of uses of the operands to not increase
4828 // the instruction count for all transforms.
4829
4830 // Handle size-changing casts.
4831 SDValue X = N0.getOperand(0);
4832 SDValue Y = N1.getOperand(0);
4833 EVT XVT = X.getValueType();
4834 SDLoc DL(N);
4835 if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND ||
4836 HandOpcode == ISD::SIGN_EXTEND) {
4837 // If both operands have other uses, this transform would create extra
4838 // instructions without eliminating anything.
4839 if (!N0.hasOneUse() && !N1.hasOneUse())
4840 return SDValue();
4841 // We need matching integer source types.
4842 if (XVT != Y.getValueType())
4843 return SDValue();
4844 // Don't create an illegal op during or after legalization. Don't ever
4845 // create an unsupported vector op.
4846 if ((VT.isVector() || LegalOperations) &&
4847 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT))
4848 return SDValue();
4849 // Avoid infinite looping with PromoteIntBinOp.
4850 // TODO: Should we apply desirable/legal constraints to all opcodes?
4851 if (HandOpcode == ISD::ANY_EXTEND && LegalTypes &&
4852 !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
4853 return SDValue();
4854 // logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y)
4855 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4856 return DAG.getNode(HandOpcode, DL, VT, Logic);
4857 }
4858
4859 // logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)
4860 if (HandOpcode == ISD::TRUNCATE) {
4861 // If both operands have other uses, this transform would create extra
4862 // instructions without eliminating anything.
4863 if (!N0.hasOneUse() && !N1.hasOneUse())
4864 return SDValue();
4865 // We need matching source types.
4866 if (XVT != Y.getValueType())
4867 return SDValue();
4868 // Don't create an illegal op during or after legalization.
4869 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
4870 return SDValue();
4871 // Be extra careful sinking truncate. If it's free, there's no benefit in
4872 // widening a binop. Also, don't create a logic op on an illegal type.
4873 if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT))
4874 return SDValue();
4875 if (!TLI.isTypeLegal(XVT))
4876 return SDValue();
4877 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4878 return DAG.getNode(HandOpcode, DL, VT, Logic);
4879 }
4880
4881 // For binops SHL/SRL/SRA/AND:
4882 // logic_op (OP x, z), (OP y, z) --> OP (logic_op x, y), z
4883 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL ||
4884 HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
4885 N0.getOperand(1) == N1.getOperand(1)) {
4886 // If either operand has other uses, this transform is not an improvement.
4887 if (!N0.hasOneUse() || !N1.hasOneUse())
4888 return SDValue();
4889 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4890 return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
4891 }
4892
4893 // Unary ops: logic_op (bswap x), (bswap y) --> bswap (logic_op x, y)
4894 if (HandOpcode == ISD::BSWAP) {
4895 // If either operand has other uses, this transform is not an improvement.
4896 if (!N0.hasOneUse() || !N1.hasOneUse())
4897 return SDValue();
4898 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4899 return DAG.getNode(HandOpcode, DL, VT, Logic);
4900 }
4901
4902 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
4903 // Only perform this optimization up until type legalization, before
4904 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
4905 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
4906 // we don't want to undo this promotion.
4907 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
4908 // on scalars.
4909 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
4910 Level <= AfterLegalizeTypes) {
4911 // Input types must be integer and the same.
4912 if (XVT.isInteger() && XVT == Y.getValueType() &&
4913 !(VT.isVector() && TLI.isTypeLegal(VT) &&
4914 !XVT.isVector() && !TLI.isTypeLegal(XVT))) {
4915 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4916 return DAG.getNode(HandOpcode, DL, VT, Logic);
4917 }
4918 }
4919
4920 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
4921 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
4922 // If both shuffles use the same mask, and both shuffle within a single
4923 // vector, then it is worthwhile to move the swizzle after the operation.
4924 // The type-legalizer generates this pattern when loading illegal
4925 // vector types from memory. In many cases this allows additional shuffle
4926 // optimizations.
4927 // There are other cases where moving the shuffle after the xor/and/or
4928 // is profitable even if shuffles don't perform a swizzle.
4929 // If both shuffles use the same mask, and both shuffles have the same first
4930 // or second operand, then it might still be profitable to move the shuffle
4931 // after the xor/and/or operation.
4932 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
4933 auto *SVN0 = cast<ShuffleVectorSDNode>(N0);
4934 auto *SVN1 = cast<ShuffleVectorSDNode>(N1);
4935 assert(X.getValueType() == Y.getValueType() &&(static_cast <bool> (X.getValueType() == Y.getValueType
() && "Inputs to shuffles are not the same type") ? void
(0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4936, __extension__ __PRETTY_FUNCTION__))
4936 "Inputs to shuffles are not the same type")(static_cast <bool> (X.getValueType() == Y.getValueType
() && "Inputs to shuffles are not the same type") ? void
(0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4936, __extension__ __PRETTY_FUNCTION__))
;
4937
4938 // Check that both shuffles use the same mask. The masks are known to be of
4939 // the same length because the result vector type is the same.
4940 // Check also that shuffles have only one use to avoid introducing extra
4941 // instructions.
4942 if (!SVN0->hasOneUse() || !SVN1->hasOneUse() ||
4943 !SVN0->getMask().equals(SVN1->getMask()))
4944 return SDValue();
4945
4946 // Don't try to fold this node if it requires introducing a
4947 // build vector of all zeros that might be illegal at this stage.
4948 SDValue ShOp = N0.getOperand(1);
4949 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4950 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4951
4952 // (logic_op (shuf (A, C), shuf (B, C))) --> shuf (logic_op (A, B), C)
4953 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
4954 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT,
4955 N0.getOperand(0), N1.getOperand(0));
4956 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask());
4957 }
4958
4959 // Don't try to fold this node if it requires introducing a
4960 // build vector of all zeros that might be illegal at this stage.
4961 ShOp = N0.getOperand(0);
4962 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4963 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4964
4965 // (logic_op (shuf (C, A), shuf (C, B))) --> shuf (C, logic_op (A, B))
4966 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
4967 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
4968 N1.getOperand(1));
4969 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask());
4970 }
4971 }
4972
4973 return SDValue();
4974}
4975
4976/// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient.
4977SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
4978 const SDLoc &DL) {
4979 SDValue LL, LR, RL, RR, N0CC, N1CC;
4980 if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
4981 !isSetCCEquivalent(N1, RL, RR, N1CC))
4982 return SDValue();
4983
4984 assert(N0.getValueType() == N1.getValueType() &&(static_cast <bool> (N0.getValueType() == N1.getValueType
() && "Unexpected operand types for bitwise logic op"
) ? void (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4985, __extension__ __PRETTY_FUNCTION__))
4985 "Unexpected operand types for bitwise logic op")(static_cast <bool> (N0.getValueType() == N1.getValueType
() && "Unexpected operand types for bitwise logic op"
) ? void (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4985, __extension__ __PRETTY_FUNCTION__))
;
4986 assert(LL.getValueType() == LR.getValueType() &&(static_cast <bool> (LL.getValueType() == LR.getValueType
() && RL.getValueType() == RR.getValueType() &&
"Unexpected operand types for setcc") ? void (0) : __assert_fail
("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4988, __extension__ __PRETTY_FUNCTION__))
4987 RL.getValueType() == RR.getValueType() &&(static_cast <bool> (LL.getValueType() == LR.getValueType
() && RL.getValueType() == RR.getValueType() &&
"Unexpected operand types for setcc") ? void (0) : __assert_fail
("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4988, __extension__ __PRETTY_FUNCTION__))
4988 "Unexpected operand types for setcc")(static_cast <bool> (LL.getValueType() == LR.getValueType
() && RL.getValueType() == RR.getValueType() &&
"Unexpected operand types for setcc") ? void (0) : __assert_fail
("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4988, __extension__ __PRETTY_FUNCTION__))
;
4989
4990 // If we're here post-legalization or the logic op type is not i1, the logic
4991 // op type must match a setcc result type. Also, all folds require new
4992 // operations on the left and right operands, so those types must match.
4993 EVT VT = N0.getValueType();
4994 EVT OpVT = LL.getValueType();
4995 if (LegalOperations || VT.getScalarType() != MVT::i1)
4996 if (VT != getSetCCResultType(OpVT))
4997 return SDValue();
4998 if (OpVT != RL.getValueType())
4999 return SDValue();
5000
5001 ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
5002 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
5003 bool IsInteger = OpVT.isInteger();
5004 if (LR == RR && CC0 == CC1 && IsInteger) {
5005 bool IsZero = isNullOrNullSplat(LR);
5006 bool IsNeg1 = isAllOnesOrAllOnesSplat(LR);
5007
5008 // All bits clear?
5009 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
5010 // All sign bits clear?
5011 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
5012 // Any bits set?
5013 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
5014 // Any sign bits set?
5015 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
5016
5017 // (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0)
5018 // (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
5019 // (or (setne X, 0), (setne Y, 0)) --> (setne (or X, Y), 0)
5020 // (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0)
5021 if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) {
5022 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
5023 AddToWorklist(Or.getNode());
5024 return DAG.getSetCC(DL, VT, Or, LR, CC1);
5025 }
5026
5027 // All bits set?
5028 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
5029 // All sign bits set?
5030 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
5031 // Any bits clear?
5032 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1;
5033 // Any sign bits clear?
5034 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1;
5035
5036 // (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
5037 // (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0)
5038 // (or (setne X, -1), (setne Y, -1)) --> (setne (and X, Y), -1)
5039 // (or (setgt X, -1), (setgt Y -1)) --> (setgt (and X, Y), -1)
5040 if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) {
5041 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
5042 AddToWorklist(And.getNode());
5043 return DAG.getSetCC(DL, VT, And, LR, CC1);
5044 }
5045 }
5046
5047 // TODO: What is the 'or' equivalent of this fold?
5048 // (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
5049 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 &&
5050 IsInteger && CC0 == ISD::SETNE &&
5051 ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
5052 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
5053 SDValue One = DAG.getConstant(1, DL, OpVT);
5054 SDValue Two = DAG.getConstant(2, DL, OpVT);
5055 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
5056 AddToWorklist(Add.getNode());
5057 return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
5058 }
5059
5060 // Try more general transforms if the predicates match and the only user of
5061 // the compares is the 'and' or 'or'.
5062 if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 &&
5063 N0.hasOneUse() && N1.hasOneUse()) {
5064 // and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
5065 // or (setne A, B), (setne C, D) --> setne (or (xor A, B), (xor C, D)), 0
5066 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) {
5067 SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR);
5068 SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR);
5069 SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR);
5070 SDValue Zero = DAG.getConstant(0, DL, OpVT);
5071 return DAG.getSetCC(DL, VT, Or, Zero, CC1);
5072 }
5073
5074 // Turn compare of constants whose difference is 1 bit into add+and+setcc.
5075 // TODO - support non-uniform vector amounts.
5076 if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) {
5077 // Match a shared variable operand and 2 non-opaque constant operands.
5078 ConstantSDNode *C0 = isConstOrConstSplat(LR);
5079 ConstantSDNode *C1 = isConstOrConstSplat(RR);
5080 if (LL == RL && C0 && C1 && !C0->isOpaque() && !C1->isOpaque()) {
5081 const APInt &CMax =
5082 APIntOps::umax(C0->getAPIntValue(), C1->getAPIntValue());
5083 const APInt &CMin =
5084 APIntOps::umin(C0->getAPIntValue(), C1->getAPIntValue());
5085 // The difference of the constants must be a single bit.
5086 if ((CMax - CMin).isPowerOf2()) {
5087 // and/or (setcc X, CMax, ne), (setcc X, CMin, ne/eq) -->
5088 // setcc ((sub X, CMin), ~(CMax - CMin)), 0, ne/eq
5089 SDValue Max = DAG.getNode(ISD::UMAX, DL, OpVT, LR, RR);
5090 SDValue Min = DAG.getNode(ISD::UMIN, DL, OpVT, LR, RR);
5091 SDValue Offset = DAG.getNode(ISD::SUB, DL, OpVT, LL, Min);
5092 SDValue Diff = DAG.getNode(ISD::SUB, DL, OpVT, Max, Min);
5093 SDValue Mask = DAG.getNOT(DL, Diff, OpVT);
5094 SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Offset, Mask);
5095 SDValue Zero = DAG.getConstant(0, DL, OpVT);
5096 return DAG.getSetCC(DL, VT, And, Zero, CC0);
5097 }
5098 }
5099 }
5100 }
5101
5102 // Canonicalize equivalent operands to LL == RL.
5103 if (LL == RR && LR == RL) {
5104 CC1 = ISD::getSetCCSwappedOperands(CC1);
5105 std::swap(RL, RR);
5106 }
5107
5108 // (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
5109 // (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
5110 if (LL == RL && LR == RR) {
5111 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT)
5112 : ISD::getSetCCOrOperation(CC0, CC1, OpVT);
5113 if (NewCC != ISD::SETCC_INVALID &&
5114 (!LegalOperations ||
5115 (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
5116 TLI.isOperationLegal(ISD::SETCC, OpVT))))
5117 return DAG.getSetCC(DL, VT, LL, LR, NewCC);
5118 }
5119
5120 return SDValue();
5121}
5122
5123/// This contains all DAGCombine rules which reduce two values combined by
5124/// an And operation to a single value. This makes them reusable in the context
5125/// of visitSELECT(). Rules involving constants are not included as
5126/// visitSELECT() already handles those cases.
5127SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
5128 EVT VT = N1.getValueType();
5129 SDLoc DL(N);
5130
5131 // fold (and x, undef) -> 0
5132 if (N0.isUndef() || N1.isUndef())
5133 return DAG.getConstant(0, DL, VT);
5134
5135 if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
5136 return V;
5137
5138 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
5139 VT.getSizeInBits() <= 64) {
5140 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5141 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
5142 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
5143 // immediate for an add, but it is legal if its top c2 bits are set,
5144 // transform the ADD so the immediate doesn't need to be materialized
5145 // in a register.
5146 APInt ADDC = ADDI->getAPIntValue();
5147 APInt SRLC = SRLI->getAPIntValue();
5148 if (ADDC.getMinSignedBits() <= 64 &&
5149 SRLC.ult(VT.getSizeInBits()) &&
5150 !TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
5151 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
5152 SRLC.getZExtValue());
5153 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
5154 ADDC |= Mask;
5155 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
5156 SDLoc DL0(N0);
5157 SDValue NewAdd =
5158 DAG.getNode(ISD::ADD, DL0, VT,
5159 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
5160 CombineTo(N0.getNode(), NewAdd);
5161 // Return N so it doesn't get rechecked!
5162 return SDValue(N, 0);
5163 }
5164 }
5165 }
5166 }
5167 }
5168 }
5169
5170 // Reduce bit extract of low half of an integer to the narrower type.
5171 // (and (srl i64:x, K), KMask) ->
5172 // (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
5173 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5174 if (ConstantSDNode *CAnd = dyn_cast<ConstantSDNode>(N1)) {
5175 if (ConstantSDNode *CShift = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5176 unsigned Size = VT.getSizeInBits();
5177 const APInt &AndMask = CAnd->getAPIntValue();
5178 unsigned ShiftBits = CShift->getZExtValue();
5179
5180 // Bail out, this node will probably disappear anyway.
5181 if (ShiftBits == 0)
5182 return SDValue();
5183
5184 unsigned MaskBits = AndMask.countTrailingOnes();
5185 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);
5186
5187 if (AndMask.isMask() &&
5188 // Required bits must not span the two halves of the integer and
5189 // must fit in the half size type.
5190 (ShiftBits + MaskBits <= Size / 2) &&
5191 TLI.isNarrowingProfitable(VT, HalfVT) &&
5192 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
5193 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) &&
5194 TLI.isTruncateFree(VT, HalfVT) &&
5195 TLI.isZExtFree(HalfVT, VT)) {
5196 // The isNarrowingProfitable is to avoid regressions on PPC and
5197 // AArch64 which match a few 64-bit bit insert / bit extract patterns
5198 // on downstream users of this. Those patterns could probably be
5199 // extended to handle extensions mixed in.
5200
5201 SDValue SL(N0);
5202 assert(MaskBits <= Size)(static_cast <bool> (MaskBits <= Size) ? void (0) : __assert_fail
("MaskBits <= Size", "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5202, __extension__ __PRETTY_FUNCTION__))
;
5203
5204 // Extracting the highest bit of the low half.
5205 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
5206 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT,
5207 N0.getOperand(0));
5208
5209 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT);
5210 SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT);
5211 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK);
5212 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask);
5213 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And);
5214 }
5215 }
5216 }
5217 }
5218
5219 return SDValue();
5220}
5221
5222bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
5223 EVT LoadResultTy, EVT &ExtVT) {
5224 if (!AndC->getAPIntValue().isMask())
5225 return false;
5226
5227 unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes();
5228
5229 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
5230 EVT LoadedVT = LoadN->getMemoryVT();
5231
5232 if (ExtVT == LoadedVT &&
5233 (!LegalOperations ||
5234 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
5235 // ZEXTLOAD will match without needing to change the size of the value being
5236 // loaded.
5237 return true;
5238 }
5239
5240 // Do not change the width of a volatile or atomic loads.
5241 if (!LoadN->isSimple())
5242 return false;
5243
5244 // Do not generate loads of non-round integer types since these can
5245 // be expensive (and would be wrong if the type is not byte sized).
5246 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound())
5247 return false;
5248
5249 if (LegalOperations &&
5250 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
5251 return false;
5252
5253 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
5254 return false;
5255
5256 return true;
5257}
5258
5259bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
5260 ISD::LoadExtType ExtType, EVT &MemVT,
5261 unsigned ShAmt) {
5262 if (!LDST)
5263 return false;
5264 // Only allow byte offsets.
5265 if (ShAmt % 8)
5266 return false;
5267
5268 // Do not generate loads of non-round integer types since these can
5269 // be expensive (and would be wrong if the type is not byte sized).
5270 if (!MemVT.isRound())
5271 return false;
5272
5273 // Don't change the width of a volatile or atomic loads.
5274 if (!LDST->isSimple())
5275 return false;
5276
5277 EVT LdStMemVT = LDST->getMemoryVT();
5278
5279 // Bail out when changing the scalable property, since we can't be sure that
5280 // we're actually narrowing here.
5281 if (LdStMemVT.isScalableVector() != MemVT.isScalableVector())
5282 return false;
5283
5284 // Verify that we are actually reducing a load width here.
5285 if (LdStMemVT.bitsLT(MemVT))
5286 return false;
5287
5288 // Ensure that this isn't going to produce an unsupported memory access.
5289 if (ShAmt) {
5290 assert(ShAmt % 8 == 0 && "ShAmt is byte offset")(static_cast <bool> (ShAmt % 8 == 0 && "ShAmt is byte offset"
) ? void (0) : __assert_fail ("ShAmt % 8 == 0 && \"ShAmt is byte offset\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5290, __extension__ __PRETTY_FUNCTION__))
;
5291 const unsigned ByteShAmt = ShAmt / 8;
5292 const Align LDSTAlign = LDST->getAlign();
5293 const Align NarrowAlign = commonAlignment(LDSTAlign, ByteShAmt);
5294 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
5295 LDST->getAddressSpace(), NarrowAlign,
5296 LDST->getMemOperand()->getFlags()))
5297 return false;
5298 }
5299
5300 // It's not possible to generate a constant of extended or untyped type.
5301 EVT PtrType = LDST->getBasePtr().getValueType();
5302 if (PtrType == MVT::Untyped || PtrType.isExtended())
5303 return false;
5304
5305 if (isa<LoadSDNode>(LDST)) {
5306 LoadSDNode *Load = cast<LoadSDNode>(LDST);
5307 // Don't transform one with multiple uses, this would require adding a new
5308 // load.
5309 if (!SDValue(Load, 0).hasOneUse())
5310 return false;
5311
5312 if (LegalOperations &&
5313 !TLI.isLoadExtLegal(ExtType, Load->getValueType(0), MemVT))
5314 return false;
5315
5316 // For the transform to be legal, the load must produce only two values
5317 // (the value loaded and the chain). Don't transform a pre-increment
5318 // load, for example, which produces an extra value. Otherwise the
5319 // transformation is not equivalent, and the downstream logic to replace
5320 // uses gets things wrong.
5321 if (Load->getNumValues() > 2)
5322 return false;
5323
5324 // If the load that we're shrinking is an extload and we're not just
5325 // discarding the extension we can't simply shrink the load. Bail.
5326 // TODO: It would be possible to merge the extensions in some cases.
5327 if (Load->getExtensionType() != ISD::NON_EXTLOAD &&
5328 Load->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
5329 return false;
5330
5331 if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT))
5332 return false;
5333 } else {
5334 assert(isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode")(static_cast <bool> (isa<StoreSDNode>(LDST) &&
"It is not a Load nor a Store SDNode") ? void (0) : __assert_fail
("isa<StoreSDNode>(LDST) && \"It is not a Load nor a Store SDNode\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5334, __extension__ __PRETTY_FUNCTION__))
;
5335 StoreSDNode *Store = cast<StoreSDNode>(LDST);
5336 // Can't write outside the original store
5337 if (Store->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
5338 return false;
5339
5340 if (LegalOperations &&
5341 !TLI.isTruncStoreLegal(Store->getValue().getValueType(), MemVT))
5342 return false;
5343 }
5344 return true;
5345}
5346
5347bool DAGCombiner::SearchForAndLoads(SDNode *N,
5348 SmallVectorImpl<LoadSDNode*> &Loads,
5349 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
5350 ConstantSDNode *Mask,
5351 SDNode *&NodeToMask) {
5352 // Recursively search for the operands, looking for loads which can be
5353 // narrowed.
5354 for (SDValue Op : N->op_values()) {
5355 if (Op.getValueType().isVector())
5356 return false;
5357
5358 // Some constants may need fixing up later if they are too large.
5359 if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
5360 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
5361 (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
5362 NodesWithConsts.insert(N);
5363 continue;
5364 }
5365
5366 if (!Op.hasOneUse())
5367 return false;
5368
5369 switch(Op.getOpcode()) {
5370 case ISD::LOAD: {
5371 auto *Load = cast<LoadSDNode>(Op);
5372 EVT ExtVT;
5373 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
5374 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) {
5375
5376 // ZEXTLOAD is already small enough.
5377 if (Load->getExtensionType() == ISD::ZEXTLOAD &&
5378 ExtVT.bitsGE(Load->getMemoryVT()))
5379 continue;
5380
5381 // Use LE to convert equal sized loads to zext.
5382 if (ExtVT.bitsLE(Load->getMemoryVT()))
5383 Loads.push_back(Load);
5384
5385 continue;
5386 }
5387 return false;
5388 }
5389 case ISD::ZERO_EXTEND:
5390 case ISD::AssertZext: {
5391 unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
5392 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
5393 EVT VT = Op.getOpcode() == ISD::AssertZext ?
5394 cast<VTSDNode>(Op.getOperand(1))->getVT() :
5395 Op.getOperand(0).getValueType();
5396
5397 // We can accept extending nodes if the mask is wider or an equal
5398 // width to the original type.
5399 if (ExtVT.bitsGE(VT))
5400 continue;
5401 break;
5402 }
5403 case ISD::OR:
5404 case ISD::XOR:
5405 case ISD::AND:
5406 if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask,
5407 NodeToMask))
5408 return false;
5409 continue;
5410 }
5411
5412 // Allow one node which will masked along with any loads found.
5413 if (NodeToMask)
5414 return false;
5415
5416 // Also ensure that the node to be masked only produces one data result.
5417 NodeToMask = Op.getNode();
5418 if (NodeToMask->getNumValues() > 1) {
5419 bool HasValue = false;
5420 for (unsigned i = 0, e = NodeToMask->getNumValues(); i < e; ++i) {
5421 MVT VT = SDValue(NodeToMask, i).getSimpleValueType();
5422 if (VT != MVT::Glue && VT != MVT::Other) {
5423 if (HasValue) {
5424 NodeToMask = nullptr;
5425 return false;
5426 }
5427 HasValue = true;
5428 }
5429 }
5430 assert(HasValue && "Node to be masked has no data result?")(static_cast <bool> (HasValue && "Node to be masked has no data result?"
) ? void (0) : __assert_fail ("HasValue && \"Node to be masked has no data result?\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5430, __extension__ __PRETTY_FUNCTION__))
;
5431 }
5432 }
5433 return true;
5434}
5435
5436bool DAGCombiner::BackwardsPropagateMask(SDNode *N) {
5437 auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
5438 if (!Mask)
5439 return false;
5440
5441 if (!Mask->getAPIntValue().isMask())
5442 return false;
5443
5444 // No need to do anything if the and directly uses a load.
5445 if (isa<LoadSDNode>(N->getOperand(0)))
5446 return false;
5447
5448 SmallVector<LoadSDNode*, 8> Loads;
5449 SmallPtrSet<SDNode*, 2> NodesWithConsts;
5450 SDNode *FixupNode = nullptr;
5451 if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) {
5452 if (Loads.size() == 0)
5453 return false;
5454
5455 LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Backwards propagate AND: "
; N->dump(); } } while (false)
;
5456 SDValue MaskOp = N->getOperand(1);
5457
5458 // If it exists, fixup the single node we allow in the tree that needs
5459 // masking.
5460 if (FixupNode) {
5461 LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "First, need to fix up: "; FixupNode
->dump(); } } while (false)
;
5462 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
5463 FixupNode->getValueType(0),
5464 SDValue(FixupNode, 0), MaskOp);
5465 DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And);
5466 if (And.getOpcode() == ISD ::AND)
5467 DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOp);
5468 }
5469
5470 // Narrow any constants that need it.
5471 for (auto *LogicN : NodesWithConsts) {
5472 SDValue Op0 = LogicN->getOperand(0);
5473 SDValue Op1 = LogicN->getOperand(1);
5474
5475 if (isa<ConstantSDNode>(Op0))
5476 std::swap(Op0, Op1);
5477
5478 SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(),
5479 Op1, MaskOp);
5480
5481 DAG.UpdateNodeOperands(LogicN, Op0, And);
5482 }
5483
5484 // Create narrow loads.
5485 for (auto *Load : Loads) {
5486 LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Propagate AND back to: "; Load
->dump(); } } while (false)
;
5487 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
5488 SDValue(Load, 0), MaskOp);
5489 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
5490 if (And.getOpcode() == ISD ::AND)
5491 And = SDValue(
5492 DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp), 0);
5493 SDValue NewLoad = ReduceLoadWidth(And.getNode());
5494 assert(NewLoad &&(static_cast <bool> (NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? void (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5495, __extension__ __PRETTY_FUNCTION__))
5495 "Shouldn't be masking the load if it can't be narrowed")(static_cast <bool> (NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? void (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5495, __extension__ __PRETTY_FUNCTION__))
;
5496 CombineTo(Load, NewLoad, NewLoad.getValue(1));
5497 }
5498 DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
5499 return true;
5500 }
5501 return false;
5502}
5503
5504// Unfold
5505// x & (-1 'logical shift' y)
5506// To
5507// (x 'opposite logical shift' y) 'logical shift' y
5508// if it is better for performance.
5509SDValue DAGCombiner::unfoldExtremeBitClearingToShifts(SDNode *N) {
5510 assert(N->getOpcode() == ISD::AND)(static_cast <bool> (N->getOpcode() == ISD::AND) ? void
(0) : __assert_fail ("N->getOpcode() == ISD::AND", "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5510, __extension__ __PRETTY_FUNCTION__))
;
5511
5512 SDValue N0 = N->getOperand(0);
5513 SDValue N1 = N->getOperand(1);
5514
5515 // Do we actually prefer shifts over mask?
5516 if (!TLI.shouldFoldMaskToVariableShiftPair(N0))
5517 return SDValue();
5518
5519 // Try to match (-1 '[outer] logical shift' y)
5520 unsigned OuterShift;
5521 unsigned InnerShift; // The opposite direction to the OuterShift.
5522 SDValue Y; // Shift amount.
5523 auto matchMask = [&OuterShift, &InnerShift, &Y](SDValue M) -> bool {
5524 if (!M.hasOneUse())
5525 return false;
5526 OuterShift = M->getOpcode();
5527 if (OuterShift == ISD::SHL)
5528 InnerShift = ISD::SRL;
5529 else if (OuterShift == ISD::SRL)
5530 InnerShift = ISD::SHL;
5531 else
5532 return false;
5533 if (!isAllOnesConstant(M->getOperand(0)))
5534 return false;
5535 Y = M->getOperand(1);
5536 return true;
5537 };
5538
5539 SDValue X;
5540 if (matchMask(N1))
5541 X = N0;
5542 else if (matchMask(N0))
5543 X = N1;
5544 else
5545 return SDValue();
5546
5547 SDLoc DL(N);
5548 EVT VT = N->getValueType(0);
5549
5550 // tmp = x 'opposite logical shift' y
5551 SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y);
5552 // ret = tmp 'logical shift' y
5553 SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y);
5554
5555 return T1;
5556}
5557
5558/// Try to replace shift/logic that tests if a bit is clear with mask + setcc.
5559/// For a target with a bit test, this is expected to become test + set and save
5560/// at least 1 instruction.
5561static SDValue combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) {
5562 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op")(static_cast <bool> (And->getOpcode() == ISD::AND &&
"Expected an 'and' op") ? void (0) : __assert_fail ("And->getOpcode() == ISD::AND && \"Expected an 'and' op\""
, "/build/llvm-toolchain-snapshot-13~++20210726100616+dead50d4427c/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5562, __extension__ __PRETTY_FUNCTION__))
;
5563
5564 // This is probably not worthwhile without a supported type.
5565 EVT VT = And->getValueType(0);
5566 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5567 if (!TLI.isTypeLegal(VT))
5568 return SDValue();
5569
5570 // Look through an optional extension and find a 'not'.
5571 // TODO: Should we favor test+set even without the 'not' op?
5572 SDValue Not = And->getOperand(0), And1 = And->getOperand(1);
5573 if (Not.getOpcode() == ISD::ANY_EXTEND)
5574 Not = Not.getOperand(0);
5575 if (!isBitwiseNot(Not) || !Not.hasOneUse() || !isOneConstant(And1))
5576 return SDValue();
5577
5578 // Look though an optional truncation. The source operand may not be the same
5579 // type as the original 'and', but that is ok because we are masking off
5580 // everything but the low bit.
5581 SDValue Srl = Not.getOperand(0);
5582 if (Srl.getOpcode() == ISD::TRUNCATE)
5583 Srl = Srl.getOperand(0);
5584
5585 // Match a shift-right by constant.
5586 if (Srl.getOpcode() != ISD::SRL || !Srl.hasOneUse() ||
5587 !isa<ConstantSDNode>(Srl.getOperand(1)))
5588 return SDValue();
5589
5590 // We might have looked through casts that make this transform invalid.
5591 // TODO: If the source type is wider than the result type, do the mask and
5592 // compare in the source type.
5593 const APInt &ShiftAmt = Srl.getConstantOperandAPInt(1);
5594 unsigned VTBitWidth = VT.getSizeInBits();
5595 if (ShiftAmt.uge(VTBitWidth))
5596 return SDValue();
5597
5598 // Turn this into a bit-test pattern using mask op + setcc:
5599 // and (not (srl X, C)), 1 --> (and X, 1<<C) == 0
5600 SDLoc DL(And);
5601 SDValue X = DAG.getZExtOrTrunc(Srl.getOperand(0), DL, VT);
5602 EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
5603 SDValue Mask = DAG.getConstant(
5604 APInt::getOneBitSet(VTBitWidth, ShiftAmt.getZExtValue()), DL, VT);
5605 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, Mask);
5606 SDValue Zero = DAG.getConstant(0, DL, VT);
5607 SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ);
5608 return DAG.getZExtOrTrunc(Setcc, DL, VT);
5609}
5610
5611SDValue DAGCombiner::visitAND(SDNode *N) {
5612 SDValue N0 = N->getOperand(0);
5613 SDValue N1 = N->getOperand(1);
5614 EVT VT = N1.getValueType();
5615
5616 // x & x --> x
5617 if (N0 == N1)
5618 return N0;
5619
5620 // fold vector ops
5621 if (VT.isVector()) {
5622 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5623 return FoldedVOp;
5624
5625 // fold (and x, 0) -> 0, vector edition
5626 if (ISD::isConstantSplatVectorAllZeros(N0.getNode()))
5627 // do not return N0, because undef node may exist in N0
5628 return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()),
5629 SDLoc(N), N0.getValueType());
5630 if (ISD::isConstantSplatVectorAllZeros(N1.getNode()))
5631 // do not return N1, because undef node may exist in N1
5632 return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()),
5633 SDLoc(N), N1.getValueType());
5634
5635 // fold (and x, -1) -> x, vector edition
5636 if (ISD::isConstantSplatVectorAllOnes(N0.getNode()))
5637 return N1;
5638 if (ISD::isConstantSplatVectorAllOnes(N1.getNode()))
5639 return N0;
5640
5641 // fold (and (masked_load) (build_vec (x, ...))) to zext_masked_load
5642 auto *MLoad = dyn_cast<MaskedLoadSDNode>(N0);
5643 auto *BVec = dyn_cast<BuildVectorSDNode>(N1);
5644 if (MLoad && BVec && MLoad->getExtensionType() == ISD::EXTLOAD &&
5645 N0.hasOneUse() && N1.hasOneUse()) {
5646 EVT LoadVT = MLoad->getMemoryVT();
5647 EVT ExtVT = VT;
5648 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) {
5649 // For this AND to be a zero extension of the masked load the elements
5650 // of the BuildVec must mask the bottom bits of the extended element
5651 // type
5652 if (ConstantSDNode *Splat = BVec->getConstantSplatNode()) {
5653 uint64_t ElementSize =
5654 LoadVT.getVectorElementType().getScalarSizeInBits();
5655 if (Splat->getAPIntValue().isMask(ElementSize)) {
5656 return DAG.getMaskedLoad(
5657 ExtVT, SDLoc(N), MLoad->getChain(), MLoad->getBasePtr(),
5658 MLoad->getOffset(), MLoad->getMask(), MLoad->getPassThru(),
5659 LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(),
5660 ISD::ZEXTLOAD, MLoad->isExpandingLoad());
5661 }
5662 }
5663 }
5664 }
5665 }
5666
5667 // fold (and c1, c2) -> c1&c2
5668 ConstantSDNode *N1C = isConstOrConstSplat(N1);
5669 if (SDValue C = DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, {N0, N1}))
5670 return C;
5671
5672 // canonicalize constant to RHS
5673 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5674 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
5675 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
5676
5677 // fold (and x, -1) -> x
5678 if (isAllOnesConstant(N1))
5679 return N0;
5680
5681 // if (and x, c) is known to be zero, return 0
5682 unsigned BitWidth = VT.getScalarSizeInBits();
5683 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
5684 APInt::getAllOnesValue(BitWidth)))
5685 return DAG.getConstant(0, SDLoc(N), VT);
5686
5687 if (SDValue NewSel = foldBinOpIntoSelect(N))
5688 return NewSel;
5689
5690 // reassociate and
5691 if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
5692 return RAND;
5693
5694 // Try to convert a constant mask AND into a shuffle clear mask.
5695 if (VT.isVector())
5696 if (SDValue Shuffle = XformToShuffleWithZero(N))
5697 return Shuffle;
5698
5699 if (SDValue Combined = combineCarryDiamond(*this, DAG, TLI, N0, N1, N))
5700 return Combined;
5701
5702 // fold (and (or x, C), D) -> D if (C & D) == D
5703 auto MatchSubset = [](ConstantSDNode *LHS, ConstantSDNode *RHS) {
5704 return RHS->getAPIntValue().isSubsetOf(LHS->getAPIntValue());
5705 };
5706 if (N0.getOpcode() == ISD::OR &&
5707 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset))
5708 return N1;
5709 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
5710 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
5711 SDValue N0Op0 = N0.getOperand(0);
5712 APInt Mask = ~N1C->getAPIntValue();
5713 Mask = Mask.trunc(N0Op0.getScalarValueSizeInBits());
5714 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
5715 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
5716 N0.getValueType(), N0Op0);
5717
5718 // Replace uses of the AND with uses of the Zero extend node.
5719 CombineTo(N, Zext);
5720
5721 // We actually want to replace all uses of the any_extend with the
5722 // zero_extend, to avoid duplicating things. This will later cause this
5723 // AND to be folded.
5724 CombineTo(N0.getNode(), Zext);
5725 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5726 }
5727 }
5728
5729 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
5730 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
5731 // already be zero by virtue of the width of the base type of the load.
5732 //
5733 // the 'X' node here can either be nothing or an extract_vector_elt to catch
5734 // more cases.
5735 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5736 N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
5737 N0.getOperand(0).getOpcode() == ISD::LOAD &&
5738 N0.getOperand(0).getResNo() == 0) ||
5739 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
5740 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
5741 N0 : N0.getOperand(0) );
5742
5743 // Get the constant (if applicable) the zero'th operand is being ANDed with.
5744 // This can be a pure constant or a vector splat, in which case we treat the
5745 // vector as a scalar and use the splat value.
5746 APInt Constant = APInt::getNullValue(1);
5747 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
5748 Constant = C->getAPIntValue();
5749 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
5750 APInt SplatValue, SplatUndef;
5751 unsigned SplatBitSize;
5752 bool HasAnyUndefs;
5753 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
5754 SplatBitSize, HasAnyUndefs);
5755 if (IsSplat) {
5756 // Undef bits can contribute to a possible optimisation if set, so
5757 // set them.
5758 SplatValue |= SplatUndef;
5759
5760 // The splat value may be something like "0x00FFFFFF", which means 0 for
5761 // the first vector value and FF for the rest, repeating. We need a mask
5762 // that will apply equally to all members of the vector, so AND all the
5763 // lanes of the constant together.
5764 unsigned EltBitWidth = Vector->getValueType(0).getScalarSizeInBits();
5765
5766 // If the splat value has been compressed to a bitlength lower
5767 // than the size of the vector lane, we need to re-expand it to
5768 // the lane size.
5769 if (EltBitWidth > SplatBitSize)
5770 for (SplatValue = SplatValue.zextOrTrunc(EltBitWidth);
5771 SplatBitSize < EltBitWidth; SplatBitSize = SplatBitSize * 2)
5772 SplatValue |= SplatValue.shl(SplatBitSize);
5773
5774 // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
5775 // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
5776 if ((SplatBitSize % EltBitWidth) == 0) {
5777 Constant = APInt::getAllOnesValue(EltBitWidth);
5778 for (unsigned i = 0, n = (SplatBitSize / EltBitWidth); i < n; ++i)
5779 Constant &= SplatValue.extractBits(EltBitWidth, i * EltBitWidth);
5780 }
5781 }
5782 }
5783
5784 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
5785 // actually legal and isn't going to get expanded, else this is a false
5786 // optimisation.
5787 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
5788 Load->getValueType(0),
5789 Load->getMemoryVT());
5790
5791 // Resize the constant to the same size as the original memory access before
5792 // extension. If it is still the AllOnesValue then this AND is completely
5793 // unneeded.
5794 Constant = Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits());
5795
5796 bool B;
5797 switch (Load->getExtensionType()) {
5798 default: B = false; break;
5799 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
5800 case ISD::ZEXTLOAD:
5801 case ISD::NON_EXTLOAD: B = true; break;
5802 }
5803
5804 if (B && Constant.isAllOnesValue()) {
5805 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
5806 // preserve semantics once we get rid of the AND.
5807 SDValue NewLoad(Load, 0);
5808
5809 // Fold the AND away. NewLoad may get replaced immediately.
5810 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
5811
5812 if (Load->getExtensionType() == ISD::EXTLOAD) {
5813 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
5814 Load->getValueType(0), SDLoc(Load),
5815 Load->getChain(), Load->getBasePtr(),
5816 Load->getOffset(), Load->getMemoryVT(),
5817 Load->getMemOperand());
5818 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
5819 if (Load->getNumValues() == 3) {
5820 // PRE/POST_INC loads have 3 values.
5821 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
5822 NewLoad.getValue(2) };
5823 CombineTo(Load, To, 3, true);
5824 } else {
5825 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
5826 }
5827 }
5828
5829 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5830 }
5831 }
5832
5833 // fold (and (masked_gather x)) -> (zext_masked_gather x)
5834 if (auto *GN0 = dyn_cast<MaskedGatherSDNode>(N0)) {
5835 EVT MemVT = GN0->getMemoryVT();
5836 EVT ScalarVT = MemVT.getScalarType();
5837
5838 if (SDValue(GN0, 0).hasOneUse() &&
5839 isConstantSplatVectorMaskForType(N1.getNode(), ScalarVT) &&
5840 TLI.isVectorLoadExtDesirable(SDValue(SDValue(GN0, 0)))) {
5841 SDValue Ops[] = {GN0->getChain(), GN0->getPassThru(), GN0->getMask(),
5842 GN0->getBasePtr(), GN0->getIndex(), GN0->getScale()};
5843
5844 SDValue ZExtLoad = DAG.getMaskedGather(
5845 DAG.getVTList(VT, MVT::Other), MemVT, SDLoc(N), Ops,
5846 GN0->getMemOperand(), GN0->getIndexType(), ISD::ZEXTLOAD);
5847
5848 CombineTo(N, ZExtLoad);
5849 AddToWorklist(ZExtLoad.getNode());
5850 // Avoid recheck of N.
5851 return SDValue(N, 0);
5852 }
5853 }
5854
5855 // fold (and (load x), 255) -> (zextload x, i8)
5856 // fold (and (extload x, i16), 255) -> (zextload x, i8)
5857 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
5858 if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
5859 (N0.getOpcode() == ISD::ANY_EXTEND &&
5860 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
5861 if (SDValue Res = ReduceLoadWidth(N)) {
5862 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
5863 ? cast<LoadSDNode>(N0.getOperand(0)) : cast<LoadSDNode>(N0);
5864 AddToWorklist(N);
5865 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 0), Res);
5866 return SDValue(N, 0);
5867 }
5868 }
5869
5870 if (LegalTypes) {
5871 // Attempt to propagate the AND back up to the leaves which, if they're
5872 // loads, can be combined to narrow loads and the AND node can be removed.
5873 // Perform after legalization so that extend nodes will already be
5874 // combined into the loads.
5875 if (BackwardsPropagateMask(N))
5876 return SDValue(N, 0);
5877 }
5878
5879 if (SDValue Combined = visitANDLike(N0, N1, N))
5880 return Combined;
5881
5882 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
5883 if (N0.getOpcode() == N1.getOpcode())
5884 if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
5885 return V;
5886
5887 // Masking the negated extension of a boolean is just the zero-extended
5888 // boolean:
5889 // and (sub 0, zext(bool X)), 1 --> zext(bool X)
5890 // and (sub 0, sext(bool X)), 1 --> zext(bool X)
5891 //
5892 // Note: the SimplifyDemandedBits fold below can make an information-losing
5893 // transform, and then we have no way to find this better fold.
5894 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
5895 if (isNullOrNullSplat(N0.getOperand(0))) {
5896 SDValue SubRHS = N0.getOperand(1);
5897 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
5898 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
5899 return SubRHS;
5900 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND &&
5901 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
5902 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0));
5903 }
5904 }
5905
5906 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
5907 // fold (and (sra)) -> (and (srl)) when possible.
5908 if (SimplifyDemandedBits(SDValue(N, 0)))
5909 return SDValue(N, 0);
5910
5911 // fold (zext_inreg (extload x)) -> (zextload x)
5912 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
5913 if (ISD::isUNINDEXEDLoad(N0.getNode()) &&
5914 (ISD::isEXTLoad(N0.getNode()) ||
5915 (ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) {
5916 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5917 EVT MemVT = LN0->getMemoryVT();
5918 // If we zero all the possible extended bits, then we can turn this into
5919 // a zextload if we are running before legalize or the operation is legal.
5920 unsigned ExtBitSize = N1.getScalarValueSizeInBits();
5921 unsigned MemBitSize = MemVT.getScalarSizeInBits();
5922 APInt ExtBits = APInt::getHighBitsSet(ExtBitSize, ExtBitSize - MemBitSize);
5923 if (DAG.MaskedValueIsZero(N1, ExtBits) &&
5924 ((!LegalOperations && LN0->isSimple()) ||
5925 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
5926 SDValue ExtLoad =
5927 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(),
5928 LN0->getBasePtr(), MemVT, LN0->getMemOperand());
5929 AddToWorklist(N);
5930 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5931 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5932 }
5933 }
5934
5935 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
5936 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
5937 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5938 N0.getOperand(1), false))
5939 return BSwap;
5940 }
5941
5942 if (SDValue Shifts = unfoldExtremeBitClearingToShifts(N))
5943 return Shifts;
5944
5945 if (TLI.hasBitTest(N0, N1))
5946 if (SDValue V = combineShiftAnd1ToBitTest(N, DAG))
5947 return V;
5948
5949 // Recognize the following pattern:
5950 //
5951 // AndVT = (and (sign_extend NarrowVT to AndVT) #bitmask)
5952 //
5953 // where bitmask is a mask that clears the upper bits of AndVT. The
5954 // number of bits in bitmask must be a power of two.
5955 auto IsAndZeroExtMask = [](SDValue LHS, SDValue RHS) {
5956 if (LHS->getOpcode() != ISD::SIGN_EXTEND)
5957 return false;
5958
5959 auto *C = dyn_cast<ConstantSDNode>(RHS);
5960 if (!C)
5961 return false;
5962
5963 if (!C->getAPIntValue().isMask(
5964 LHS.getOperand(0).getValueType().getFixedSizeInBits()))
5965 return false;
5966
5967 return true;
5968 };
5969
5970 // Replace (and (sign_extend ...) #bitmask) with (zero_extend ...).
5971 if (IsAndZeroExtMask(N0, N1))
5972 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0.getOperand(0));
5973
5974 return SDValue();
5975}
5976
5977/// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
5978SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
5979 bool DemandHighBits) {
5980 if (!LegalOperations)
5981 return SDValue();
5982
5983 EVT VT = N->getValueType(0);
5984 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
5985 return SDValue();
5986 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5987 return SDValue();
5988
5989 // Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff)
5990 bool LookPassAnd0 = false;
5991 bool LookPassAnd1 = false;
5992 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
5993 std::swap(N0, N1);
5994 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
5995 std::swap(N0, N1);
5996 if (N0.getOpcode() == ISD::AND) {
5997 if (!N0.getNode()->hasOneUse())
5998 return SDValue();
5999 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
6000 // Also handle 0xffff since the LHS is guaranteed to have zeros there.
6001 // This is needed for X86.
6002 if (!N01C || (N01C->getZExtValue() != 0xFF00 &&
6003 N01C->getZExtValue() != 0xFFFF))
6004 return SDValue();
6005 N0 = N0.getOperand(0);
6006 LookPassAnd0 = true;
6007 }
6008
6009 if (N1.getOpcode() == ISD::AND) {
6010 if (!N1.getNode()->hasOneUse())
6011 return SDValue();
6012 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6013 if (!N11C || N11C->getZExtValue() != 0xFF)
6014 return SDValue();
6015 N1 = N1.getOperand(0);
6016 LookPassAnd1 = true;
6017 }
6018
6019 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
6020 std::swap(N0, N1);
6021 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
6022 return SDValue();
6023 if (!N0.getNode()->hasOneUse() || !N1.getNode()->hasOneUse())
6024 return SDValue();
6025
6026 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
6027 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6028 if (!N01C || !N11C)
6029 return SDValue();
6030 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
6031 return SDValue();
6032
6033 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
6034 SDValue N00 = N0->getOperand(0);
6035 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
6036 if (!N00.getNode()->hasOneUse())
6037 return SDValue();
6038 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
6039 if (!N001C || N001C->getZExtValue() != 0xFF)
6040 return SDValue();