Bug Summary

File:utils/TableGen/FastISelEmitter.cpp
Warning:line 442, column 35
Potential leak of memory pointed to by 'PhysRegInputs'

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name FastISelEmitter.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/utils/TableGen -I /build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/utils/TableGen -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp
1///===- FastISelEmitter.cpp - Generate an instruction selector -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend emits code for use by the "fast" instruction
11// selection algorithm. See the comments at the top of
12// lib/CodeGen/SelectionDAG/FastISel.cpp for background.
13//
14// This file scans through the target's tablegen instruction-info files
15// and extracts instructions with obvious-looking patterns, and it emits
16// code to look up these instructions by type and operator.
17//
18//===----------------------------------------------------------------------===//
19
20#include "CodeGenDAGPatterns.h"
21#include "llvm/ADT/StringSwitch.h"
22#include "llvm/Support/Debug.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/TableGen/Error.h"
25#include "llvm/TableGen/Record.h"
26#include "llvm/TableGen/TableGenBackend.h"
27#include <utility>
28using namespace llvm;
29
30
31/// InstructionMemo - This class holds additional information about an
32/// instruction needed to emit code for it.
33///
34namespace {
35struct InstructionMemo {
36 std::string Name;
37 const CodeGenRegisterClass *RC;
38 std::string SubRegNo;
39 std::vector<std::string>* PhysRegs;
40 std::string PredicateCheck;
41};
42} // End anonymous namespace
43
44/// ImmPredicateSet - This uniques predicates (represented as a string) and
45/// gives them unique (small) integer ID's that start at 0.
46namespace {
47class ImmPredicateSet {
48 DenseMap<TreePattern *, unsigned> ImmIDs;
49 std::vector<TreePredicateFn> PredsByName;
50public:
51
52 unsigned getIDFor(TreePredicateFn Pred) {
53 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()];
54 if (Entry == 0) {
55 PredsByName.push_back(Pred);
56 Entry = PredsByName.size();
57 }
58 return Entry-1;
59 }
60
61 const TreePredicateFn &getPredicate(unsigned i) {
62 assert(i < PredsByName.size())(static_cast <bool> (i < PredsByName.size()) ? void (
0) : __assert_fail ("i < PredsByName.size()", "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 62, __extension__ __PRETTY_FUNCTION__));
63 return PredsByName[i];
64 }
65
66 typedef std::vector<TreePredicateFn>::const_iterator iterator;
67 iterator begin() const { return PredsByName.begin(); }
68 iterator end() const { return PredsByName.end(); }
69
70};
71} // End anonymous namespace
72
73/// OperandsSignature - This class holds a description of a list of operand
74/// types. It has utility methods for emitting text based on the operands.
75///
76namespace {
77struct OperandsSignature {
78 class OpKind {
79 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 };
80 char Repr;
81 public:
82
83 OpKind() : Repr(OK_Invalid) {}
84
85 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; }
86 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; }
87
88 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; }
89 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; }
90 static OpKind getImm(unsigned V) {
91 assert((unsigned)OK_Imm+V < 128 &&(static_cast <bool> ((unsigned)OK_Imm+V < 128 &&
"Too many integer predicates for the 'Repr' char") ? void (0
) : __assert_fail ("(unsigned)OK_Imm+V < 128 && \"Too many integer predicates for the 'Repr' char\""
, "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 92, __extension__ __PRETTY_FUNCTION__))
92 "Too many integer predicates for the 'Repr' char")(static_cast <bool> ((unsigned)OK_Imm+V < 128 &&
"Too many integer predicates for the 'Repr' char") ? void (0
) : __assert_fail ("(unsigned)OK_Imm+V < 128 && \"Too many integer predicates for the 'Repr' char\""
, "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 92, __extension__ __PRETTY_FUNCTION__));
93 OpKind K; K.Repr = OK_Imm+V; return K;
94 }
95
96 bool isReg() const { return Repr == OK_Reg; }
97 bool isFP() const { return Repr == OK_FP; }
98 bool isImm() const { return Repr >= OK_Imm; }
99
100 unsigned getImmCode() const { assert(isImm())(static_cast <bool> (isImm()) ? void (0) : __assert_fail
("isImm()", "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 100, __extension__ __PRETTY_FUNCTION__)); return Repr-OK_Imm; }
101
102 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
103 bool StripImmCodes) const {
104 if (isReg())
105 OS << 'r';
106 else if (isFP())
107 OS << 'f';
108 else {
109 OS << 'i';
110 if (!StripImmCodes)
111 if (unsigned Code = getImmCode())
112 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName();
113 }
114 }
115 };
116
117
118 SmallVector<OpKind, 3> Operands;
119
120 bool operator<(const OperandsSignature &O) const {
121 return Operands < O.Operands;
122 }
123 bool operator==(const OperandsSignature &O) const {
124 return Operands == O.Operands;
125 }
126
127 bool empty() const { return Operands.empty(); }
128
129 bool hasAnyImmediateCodes() const {
130 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
131 if (Operands[i].isImm() && Operands[i].getImmCode() != 0)
132 return true;
133 return false;
134 }
135
136 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced
137 /// to zero.
138 OperandsSignature getWithoutImmCodes() const {
139 OperandsSignature Result;
140 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
141 if (!Operands[i].isImm())
142 Result.Operands.push_back(Operands[i]);
143 else
144 Result.Operands.push_back(OpKind::getImm(0));
145 return Result;
146 }
147
148 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) {
149 bool EmittedAnything = false;
150 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
151 if (!Operands[i].isImm()) continue;
152
153 unsigned Code = Operands[i].getImmCode();
154 if (Code == 0) continue;
155
156 if (EmittedAnything)
157 OS << " &&\n ";
158
159 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1);
160
161 // Emit the type check.
162 TreePattern *TP = PredFn.getOrigPatFragRecord();
163 ValueTypeByHwMode VVT = TP->getTree(0)->getType(0);
164 assert(VVT.isSimple() &&(static_cast <bool> (VVT.isSimple() && "Cannot use variable value types with fast isel"
) ? void (0) : __assert_fail ("VVT.isSimple() && \"Cannot use variable value types with fast isel\""
, "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 165, __extension__ __PRETTY_FUNCTION__))
165 "Cannot use variable value types with fast isel")(static_cast <bool> (VVT.isSimple() && "Cannot use variable value types with fast isel"
) ? void (0) : __assert_fail ("VVT.isSimple() && \"Cannot use variable value types with fast isel\""
, "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 165, __extension__ __PRETTY_FUNCTION__));
166 OS << "VT == " << getEnumName(VVT.getSimple().SimpleTy) << " && ";
167
168 OS << PredFn.getFnName() << "(imm" << i <<')';
169 EmittedAnything = true;
170 }
171 }
172
173 /// initialize - Examine the given pattern and initialize the contents
174 /// of the Operands array accordingly. Return true if all the operands
175 /// are supported, false otherwise.
176 ///
177 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target,
178 MVT::SimpleValueType VT,
179 ImmPredicateSet &ImmediatePredicates,
180 const CodeGenRegisterClass *OrigDstRC) {
181 if (InstPatNode->isLeaf())
182 return false;
183
184 if (InstPatNode->getOperator()->getName() == "imm") {
185 Operands.push_back(OpKind::getImm(0));
186 return true;
187 }
188
189 if (InstPatNode->getOperator()->getName() == "fpimm") {
190 Operands.push_back(OpKind::getFP());
191 return true;
192 }
193
194 const CodeGenRegisterClass *DstRC = nullptr;
195
196 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
197 TreePatternNode *Op = InstPatNode->getChild(i);
198
199 // Handle imm operands specially.
200 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") {
201 unsigned PredNo = 0;
202 if (!Op->getPredicateFns().empty()) {
203 TreePredicateFn PredFn = Op->getPredicateFns()[0];
204 // If there is more than one predicate weighing in on this operand
205 // then we don't handle it. This doesn't typically happen for
206 // immediates anyway.
207 if (Op->getPredicateFns().size() > 1 ||
208 !PredFn.isImmediatePattern())
209 return false;
210 // Ignore any instruction with 'FastIselShouldIgnore', these are
211 // not needed and just bloat the fast instruction selector. For
212 // example, X86 doesn't need to generate code to match ADD16ri8 since
213 // ADD16ri will do just fine.
214 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord();
215 if (Rec->getValueAsBit("FastIselShouldIgnore"))
216 return false;
217
218 PredNo = ImmediatePredicates.getIDFor(PredFn)+1;
219 }
220
221 Operands.push_back(OpKind::getImm(PredNo));
222 continue;
223 }
224
225
226 // For now, filter out any operand with a predicate.
227 // For now, filter out any operand with multiple values.
228 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1)
229 return false;
230
231 if (!Op->isLeaf()) {
232 if (Op->getOperator()->getName() == "fpimm") {
233 Operands.push_back(OpKind::getFP());
234 continue;
235 }
236 // For now, ignore other non-leaf nodes.
237 return false;
238 }
239
240 assert(Op->hasConcreteType(0) && "Type infererence not done?")(static_cast <bool> (Op->hasConcreteType(0) &&
"Type infererence not done?") ? void (0) : __assert_fail ("Op->hasConcreteType(0) && \"Type infererence not done?\""
, "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 240, __extension__ __PRETTY_FUNCTION__));
241
242 // For now, all the operands must have the same type (if they aren't
243 // immediates). Note that this causes us to reject variable sized shifts
244 // on X86.
245 if (Op->getSimpleType(0) != VT)
246 return false;
247
248 DefInit *OpDI = dyn_cast<DefInit>(Op->getLeafValue());
249 if (!OpDI)
250 return false;
251 Record *OpLeafRec = OpDI->getDef();
252
253 // For now, the only other thing we accept is register operands.
254 const CodeGenRegisterClass *RC = nullptr;
255 if (OpLeafRec->isSubClassOf("RegisterOperand"))
256 OpLeafRec = OpLeafRec->getValueAsDef("RegClass");
257 if (OpLeafRec->isSubClassOf("RegisterClass"))
258 RC = &Target.getRegisterClass(OpLeafRec);
259 else if (OpLeafRec->isSubClassOf("Register"))
260 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
261 else if (OpLeafRec->isSubClassOf("ValueType")) {
262 RC = OrigDstRC;
263 } else
264 return false;
265
266 // For now, this needs to be a register class of some sort.
267 if (!RC)
268 return false;
269
270 // For now, all the operands must have the same register class or be
271 // a strict subclass of the destination.
272 if (DstRC) {
273 if (DstRC != RC && !DstRC->hasSubClass(RC))
274 return false;
275 } else
276 DstRC = RC;
277 Operands.push_back(OpKind::getReg());
278 }
279 return true;
280 }
281
282 void PrintParameters(raw_ostream &OS) const {
283 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
284 if (Operands[i].isReg()) {
285 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
286 } else if (Operands[i].isImm()) {
287 OS << "uint64_t imm" << i;
288 } else if (Operands[i].isFP()) {
289 OS << "const ConstantFP *f" << i;
290 } else {
291 llvm_unreachable("Unknown operand kind!")::llvm::llvm_unreachable_internal("Unknown operand kind!", "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 291);
292 }
293 if (i + 1 != e)
294 OS << ", ";
295 }
296 }
297
298 void PrintArguments(raw_ostream &OS,
299 const std::vector<std::string> &PR) const {
300 assert(PR.size() == Operands.size())(static_cast <bool> (PR.size() == Operands.size()) ? void
(0) : __assert_fail ("PR.size() == Operands.size()", "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 300, __extension__ __PRETTY_FUNCTION__));
301 bool PrintedArg = false;
302 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
303 if (PR[i] != "")
304 // Implicit physical register operand.
305 continue;
306
307 if (PrintedArg)
308 OS << ", ";
309 if (Operands[i].isReg()) {
310 OS << "Op" << i << ", Op" << i << "IsKill";
311 PrintedArg = true;
312 } else if (Operands[i].isImm()) {
313 OS << "imm" << i;
314 PrintedArg = true;
315 } else if (Operands[i].isFP()) {
316 OS << "f" << i;
317 PrintedArg = true;
318 } else {
319 llvm_unreachable("Unknown operand kind!")::llvm::llvm_unreachable_internal("Unknown operand kind!", "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 319);
320 }
321 }
322 }
323
324 void PrintArguments(raw_ostream &OS) const {
325 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
326 if (Operands[i].isReg()) {
327 OS << "Op" << i << ", Op" << i << "IsKill";
328 } else if (Operands[i].isImm()) {
329 OS << "imm" << i;
330 } else if (Operands[i].isFP()) {
331 OS << "f" << i;
332 } else {
333 llvm_unreachable("Unknown operand kind!")::llvm::llvm_unreachable_internal("Unknown operand kind!", "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 333);
334 }
335 if (i + 1 != e)
336 OS << ", ";
337 }
338 }
339
340
341 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR,
342 ImmPredicateSet &ImmPredicates,
343 bool StripImmCodes = false) const {
344 for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
345 if (PR[i] != "")
346 // Implicit physical register operand. e.g. Instruction::Mul expect to
347 // select to a binary op. On x86, mul may take a single operand with
348 // the other operand being implicit. We must emit something that looks
349 // like a binary instruction except for the very inner fastEmitInst_*
350 // call.
351 continue;
352 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
353 }
354 }
355
356 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates,
357 bool StripImmCodes = false) const {
358 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
359 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes);
360 }
361};
362} // End anonymous namespace
363
364namespace {
365class FastISelMap {
366 // A multimap is needed instead of a "plain" map because the key is
367 // the instruction's complexity (an int) and they are not unique.
368 typedef std::multimap<int, InstructionMemo> PredMap;
369 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap;
370 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap;
371 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap;
372 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap>
373 OperandsOpcodeTypeRetPredMap;
374
375 OperandsOpcodeTypeRetPredMap SimplePatterns;
376
377 // This is used to check that there are no duplicate predicates
378 typedef std::multimap<std::string, bool> PredCheckMap;
379 typedef std::map<MVT::SimpleValueType, PredCheckMap> RetPredCheckMap;
380 typedef std::map<MVT::SimpleValueType, RetPredCheckMap> TypeRetPredCheckMap;
381 typedef std::map<std::string, TypeRetPredCheckMap> OpcodeTypeRetPredCheckMap;
382 typedef std::map<OperandsSignature, OpcodeTypeRetPredCheckMap>
383 OperandsOpcodeTypeRetPredCheckMap;
384
385 OperandsOpcodeTypeRetPredCheckMap SimplePatternsCheck;
386
387 std::map<OperandsSignature, std::vector<OperandsSignature> >
388 SignaturesWithConstantForms;
389
390 StringRef InstNS;
391 ImmPredicateSet ImmediatePredicates;
392public:
393 explicit FastISelMap(StringRef InstNS);
394
395 void collectPatterns(CodeGenDAGPatterns &CGP);
396 void printImmediatePredicates(raw_ostream &OS);
397 void printFunctionDefinitions(raw_ostream &OS);
398private:
399 void emitInstructionCode(raw_ostream &OS,
400 const OperandsSignature &Operands,
401 const PredMap &PM,
402 const std::string &RetVTName);
403};
404} // End anonymous namespace
405
406static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) {
407 return CGP.getSDNodeInfo(Op).getEnumName();
408}
409
410static std::string getLegalCName(std::string OpName) {
411 std::string::size_type pos = OpName.find("::");
412 if (pos != std::string::npos)
413 OpName.replace(pos, 2, "_");
414 return OpName;
415}
416
417FastISelMap::FastISelMap(StringRef instns) : InstNS(instns) {}
418
419static std::string PhyRegForNode(TreePatternNode *Op,
420 const CodeGenTarget &Target) {
421 std::string PhysReg;
422
423 if (!Op->isLeaf())
424 return PhysReg;
425
426 Record *OpLeafRec = cast<DefInit>(Op->getLeafValue())->getDef();
427 if (!OpLeafRec->isSubClassOf("Register"))
428 return PhysReg;
429
430 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue())
431 ->getValue();
432 PhysReg += "::";
433 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
434 return PhysReg;
435}
436
437void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) {
438 const CodeGenTarget &Target = CGP.getTargetInfo();
439
440 // Scan through all the patterns and record the simple ones.
441 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(),
1
Loop condition is true. Entering loop body
→
442 E = CGP.ptm_end(); I != E; ++I) {
34
←
Potential leak of memory pointed to by 'PhysRegInputs'
443 const PatternToMatch &Pattern = *I;
444
445 // For now, just look at Instructions, so that we don't have to worry
446 // about emitting multiple instructions for a pattern.
447 TreePatternNode *Dst = Pattern.getDstPattern();
448 if (Dst->isLeaf()) continue;
2
←
Taking false branch
→
449 Record *Op = Dst->getOperator();
450 if (!Op->isSubClassOf("Instruction"))
3
←
Taking false branch
→
451 continue;
452 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op);
453 if (II.Operands.empty())
4
←
Assuming the condition is false
→
5
←
Taking false branch
→
454 continue;
455
456 // For now, ignore multi-instruction patterns.
457 bool MultiInsts = false;
458 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) {
6
←
Assuming 'i' is equal to 'e'
→
7
←
Loop condition is false. Execution continues on line 467
→
459 TreePatternNode *ChildOp = Dst->getChild(i);
460 if (ChildOp->isLeaf())
461 continue;
462 if (ChildOp->getOperator()->isSubClassOf("Instruction")) {
463 MultiInsts = true;
464 break;
465 }
466 }
467 if (MultiInsts)
8
←
Taking false branch
→
468 continue;
469
470 // For now, ignore instructions where the first operand is not an
471 // output register.
472 const CodeGenRegisterClass *DstRC = nullptr;
473 std::string SubRegNo;
474 if (Op->getName() != "EXTRACT_SUBREG") {
9
←
Taking false branch
→
475 Record *Op0Rec = II.Operands[0].Rec;
476 if (Op0Rec->isSubClassOf("RegisterOperand"))
477 Op0Rec = Op0Rec->getValueAsDef("RegClass");
478 if (!Op0Rec->isSubClassOf("RegisterClass"))
479 continue;
480 DstRC = &Target.getRegisterClass(Op0Rec);
481 if (!DstRC)
482 continue;
483 } else {
484 // If this isn't a leaf, then continue since the register classes are
485 // a bit too complicated for now.
486 if (!Dst->getChild(1)->isLeaf()) continue;
10
←
Taking false branch
→
487
488 DefInit *SR = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue());
489 if (SR)
11
←
Taking false branch
→
490 SubRegNo = getQualifiedName(SR->getDef());
491 else
492 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString();
493 }
494
495 // Inspect the pattern.
496 TreePatternNode *InstPatNode = Pattern.getSrcPattern();
497 if (!InstPatNode) continue;
12
←
Assuming 'InstPatNode' is non-null
→
13
←
Taking false branch
→
498 if (InstPatNode->isLeaf()) continue;
14
←
Taking false branch
→
499
500 // Ignore multiple result nodes for now.
501 if (InstPatNode->getNumTypes() > 1) continue;
15
←
Assuming the condition is false
→
16
←
Taking false branch
→
502
503 Record *InstPatOp = InstPatNode->getOperator();
504 std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
505 MVT::SimpleValueType RetVT = MVT::isVoid;
506 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getSimpleType(0);
17
←
Assuming the condition is false
→
18
←
Taking false branch
→
507 MVT::SimpleValueType VT = RetVT;
508 if (InstPatNode->getNumChildren()) {
19
←
Assuming the condition is false
→
20
←
Taking false branch
→
509 assert(InstPatNode->getChild(0)->getNumTypes() == 1)(static_cast <bool> (InstPatNode->getChild(0)->getNumTypes
() == 1) ? void (0) : __assert_fail ("InstPatNode->getChild(0)->getNumTypes() == 1"
, "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 509, __extension__ __PRETTY_FUNCTION__));
510 VT = InstPatNode->getChild(0)->getSimpleType(0);
511 }
512
513 // For now, filter out any instructions with predicates.
514 if (!InstPatNode->getPredicateFns().empty())
21
←
Assuming the condition is false
→
22
←
Taking false branch
→
515 continue;
516
517 // Check all the operands.
518 OperandsSignature Operands;
519 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates,
23
←
Taking false branch
→
520 DstRC))
521 continue;
522
523 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>();
24
←
Memory is allocated
→
524 if (InstPatNode->getOperator()->getName() == "imm" ||
25
←
Assuming the condition is false
→
26
←
Assuming the condition is false
→
27
←
Taking false branch
→
525 InstPatNode->getOperator()->getName() == "fpimm")
526 PhysRegInputs->push_back("");
527 else {
528 // Compute the PhysRegs used by the given pattern, and check that
529 // the mapping from the src to dst patterns is simple.
530 bool FoundNonSimplePattern = false;
531 unsigned DstIndex = 0;
532 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
28
←
Assuming 'i' is equal to 'e'
→
29
←
Loop condition is false. Execution continues on line 547
→
533 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target);
534 if (PhysReg.empty()) {
535 if (DstIndex >= Dst->getNumChildren() ||
536 Dst->getChild(DstIndex)->getName() !=
537 InstPatNode->getChild(i)->getName()) {
538 FoundNonSimplePattern = true;
539 break;
540 }
541 ++DstIndex;
542 }
543
544 PhysRegInputs->push_back(PhysReg);
545 }
546
547 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren())
30
←
Assuming the condition is true
→
31
←
Taking true branch
→
548 FoundNonSimplePattern = true;
549
550 if (FoundNonSimplePattern)
32
←
Taking true branch
→
551 continue;
33
←
 Execution continues on line 442
→
552 }
553
554 // Check if the operands match one of the patterns handled by FastISel.
555 std::string ManglingSuffix;
556 raw_string_ostream SuffixOS(ManglingSuffix);
557 Operands.PrintManglingSuffix(SuffixOS, ImmediatePredicates, true);
558 SuffixOS.flush();
559 if (!StringSwitch<bool>(ManglingSuffix)
560 .Cases("", "r", "rr", "ri", "i", "f", true)
561 .Default(false))
562 continue;
563
564 // Get the predicate that guards this pattern.
565 std::string PredicateCheck = Pattern.getPredicateCheck();
566
567 // Ok, we found a pattern that we can handle. Remember it.
568 InstructionMemo Memo = {
569 Pattern.getDstPattern()->getOperator()->getName(),
570 DstRC,
571 SubRegNo,
572 PhysRegInputs,
573 PredicateCheck
574 };
575
576 int complexity = Pattern.getPatternComplexity(CGP);
577
578 if (SimplePatternsCheck[Operands][OpcodeName][VT]
579 [RetVT].count(PredicateCheck)) {
580 PrintFatalError(Pattern.getSrcRecord()->getLoc(),
581 "Duplicate predicate in FastISel table!");
582 }
583 SimplePatternsCheck[Operands][OpcodeName][VT][RetVT].insert(
584 std::make_pair(PredicateCheck, true));
585
586 // Note: Instructions with the same complexity will appear in the order
587 // that they are encountered.
588 SimplePatterns[Operands][OpcodeName][VT][RetVT].insert(
589 std::make_pair(complexity, Memo));
590
591 // If any of the operands were immediates with predicates on them, strip
592 // them down to a signature that doesn't have predicates so that we can
593 // associate them with the stripped predicate version.
594 if (Operands.hasAnyImmediateCodes()) {
595 SignaturesWithConstantForms[Operands.getWithoutImmCodes()]
596 .push_back(Operands);
597 }
598 }
599}
600
601void FastISelMap::printImmediatePredicates(raw_ostream &OS) {
602 if (ImmediatePredicates.begin() == ImmediatePredicates.end())
603 return;
604
605 OS << "\n// FastEmit Immediate Predicate functions.\n";
606 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(),
607 E = ImmediatePredicates.end(); I != E; ++I) {
608 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n";
609 OS << I->getImmediatePredicateCode() << "\n}\n";
610 }
611
612 OS << "\n\n";
613}
614
615void FastISelMap::emitInstructionCode(raw_ostream &OS,
616 const OperandsSignature &Operands,
617 const PredMap &PM,
618 const std::string &RetVTName) {
619 // Emit code for each possible instruction. There may be
620 // multiple if there are subtarget concerns. A reverse iterator
621 // is used to produce the ones with highest complexity first.
622
623 bool OneHadNoPredicate = false;
624 for (PredMap::const_reverse_iterator PI = PM.rbegin(), PE = PM.rend();
625 PI != PE; ++PI) {
626 const InstructionMemo &Memo = PI->second;
627 std::string PredicateCheck = Memo.PredicateCheck;
628
629 if (PredicateCheck.empty()) {
630 assert(!OneHadNoPredicate &&(static_cast <bool> (!OneHadNoPredicate && "Multiple instructions match and more than one had "
"no predicate!") ? void (0) : __assert_fail ("!OneHadNoPredicate && \"Multiple instructions match and more than one had \" \"no predicate!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 632, __extension__ __PRETTY_FUNCTION__))
631 "Multiple instructions match and more than one had "(static_cast <bool> (!OneHadNoPredicate && "Multiple instructions match and more than one had "
"no predicate!") ? void (0) : __assert_fail ("!OneHadNoPredicate && \"Multiple instructions match and more than one had \" \"no predicate!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 632, __extension__ __PRETTY_FUNCTION__))
632 "no predicate!")(static_cast <bool> (!OneHadNoPredicate && "Multiple instructions match and more than one had "
"no predicate!") ? void (0) : __assert_fail ("!OneHadNoPredicate && \"Multiple instructions match and more than one had \" \"no predicate!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 632, __extension__ __PRETTY_FUNCTION__));
633 OneHadNoPredicate = true;
634 } else {
635 if (OneHadNoPredicate) {
636 PrintFatalError("Multiple instructions match and one with no "
637 "predicate came before one with a predicate! "
638 "name:" + Memo.Name + " predicate: " + PredicateCheck);
639 }
640 OS << " if (" + PredicateCheck + ") {\n";
641 OS << " ";
642 }
643
644 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
645 if ((*Memo.PhysRegs)[i] != "")
646 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, "
647 << "TII.get(TargetOpcode::COPY), "
648 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n";
649 }
650
651 OS << " return fastEmitInst_";
652 if (Memo.SubRegNo.empty()) {
653 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs,
654 ImmediatePredicates, true);
655 OS << "(" << InstNS << "::" << Memo.Name << ", ";
656 OS << "&" << InstNS << "::" << Memo.RC->getName() << "RegClass";
657 if (!Operands.empty())
658 OS << ", ";
659 Operands.PrintArguments(OS, *Memo.PhysRegs);
660 OS << ");\n";
661 } else {
662 OS << "extractsubreg(" << RetVTName
663 << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n";
664 }
665
666 if (!PredicateCheck.empty()) {
667 OS << " }\n";
668 }
669 }
670 // Return 0 if all of the possibilities had predicates but none
671 // were satisfied.
672 if (!OneHadNoPredicate)
673 OS << " return 0;\n";
674 OS << "}\n";
675 OS << "\n";
676}
677
678
679void FastISelMap::printFunctionDefinitions(raw_ostream &OS) {
680 // Now emit code for all the patterns that we collected.
681 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(),
682 OE = SimplePatterns.end(); OI != OE; ++OI) {
683 const OperandsSignature &Operands = OI->first;
684 const OpcodeTypeRetPredMap &OTM = OI->second;
685
686 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
687 I != E; ++I) {
688 const std::string &Opcode = I->first;
689 const TypeRetPredMap &TM = I->second;
690
691 OS << "// FastEmit functions for " << Opcode << ".\n";
692 OS << "\n";
693
694 // Emit one function for each opcode,type pair.
695 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
696 TI != TE; ++TI) {
697 MVT::SimpleValueType VT = TI->first;
698 const RetPredMap &RM = TI->second;
699 if (RM.size() != 1) {
700 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
701 RI != RE; ++RI) {
702 MVT::SimpleValueType RetVT = RI->first;
703 const PredMap &PM = RI->second;
704
705 OS << "unsigned fastEmit_"
706 << getLegalCName(Opcode)
707 << "_" << getLegalCName(getName(VT))
708 << "_" << getLegalCName(getName(RetVT)) << "_";
709 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
710 OS << "(";
711 Operands.PrintParameters(OS);
712 OS << ") {\n";
713
714 emitInstructionCode(OS, Operands, PM, getName(RetVT));
715 }
716
717 // Emit one function for the type that demultiplexes on return type.
718 OS << "unsigned fastEmit_"
719 << getLegalCName(Opcode) << "_"
720 << getLegalCName(getName(VT)) << "_";
721 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
722 OS << "(MVT RetVT";
723 if (!Operands.empty())
724 OS << ", ";
725 Operands.PrintParameters(OS);
726 OS << ") {\nswitch (RetVT.SimpleTy) {\n";
727 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end();
728 RI != RE; ++RI) {
729 MVT::SimpleValueType RetVT = RI->first;
730 OS << " case " << getName(RetVT) << ": return fastEmit_"
731 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
732 << "_" << getLegalCName(getName(RetVT)) << "_";
733 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
734 OS << "(";
735 Operands.PrintArguments(OS);
736 OS << ");\n";
737 }
738 OS << " default: return 0;\n}\n}\n\n";
739
740 } else {
741 // Non-variadic return type.
742 OS << "unsigned fastEmit_"
743 << getLegalCName(Opcode) << "_"
744 << getLegalCName(getName(VT)) << "_";
745 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
746 OS << "(MVT RetVT";
747 if (!Operands.empty())
748 OS << ", ";
749 Operands.PrintParameters(OS);
750 OS << ") {\n";
751
752 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first)
753 << ")\n return 0;\n";
754
755 const PredMap &PM = RM.begin()->second;
756
757 emitInstructionCode(OS, Operands, PM, "RetVT");
758 }
759 }
760
761 // Emit one function for the opcode that demultiplexes based on the type.
762 OS << "unsigned fastEmit_"
763 << getLegalCName(Opcode) << "_";
764 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
765 OS << "(MVT VT, MVT RetVT";
766 if (!Operands.empty())
767 OS << ", ";
768 Operands.PrintParameters(OS);
769 OS << ") {\n";
770 OS << " switch (VT.SimpleTy) {\n";
771 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end();
772 TI != TE; ++TI) {
773 MVT::SimpleValueType VT = TI->first;
774 std::string TypeName = getName(VT);
775 OS << " case " << TypeName << ": return fastEmit_"
776 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
777 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
778 OS << "(RetVT";
779 if (!Operands.empty())
780 OS << ", ";
781 Operands.PrintArguments(OS);
782 OS << ");\n";
783 }
784 OS << " default: return 0;\n";
785 OS << " }\n";
786 OS << "}\n";
787 OS << "\n";
788 }
789
790 OS << "// Top-level FastEmit function.\n";
791 OS << "\n";
792
793 // Emit one function for the operand signature that demultiplexes based
794 // on opcode and type.
795 OS << "unsigned fastEmit_";
796 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
797 OS << "(MVT VT, MVT RetVT, unsigned Opcode";
798 if (!Operands.empty())
799 OS << ", ";
800 Operands.PrintParameters(OS);
801 OS << ") ";
802 if (!Operands.hasAnyImmediateCodes())
803 OS << "override ";
804 OS << "{\n";
805
806 // If there are any forms of this signature available that operate on
807 // constrained forms of the immediate (e.g., 32-bit sext immediate in a
808 // 64-bit operand), check them first.
809
810 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI
811 = SignaturesWithConstantForms.find(Operands);
812 if (MI != SignaturesWithConstantForms.end()) {
813 // Unique any duplicates out of the list.
814 llvm::sort(MI->second.begin(), MI->second.end());
815 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()),
816 MI->second.end());
817
818 // Check each in order it was seen. It would be nice to have a good
819 // relative ordering between them, but we're not going for optimality
820 // here.
821 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) {
822 OS << " if (";
823 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates);
824 OS << ")\n if (unsigned Reg = fastEmit_";
825 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates);
826 OS << "(VT, RetVT, Opcode";
827 if (!MI->second[i].empty())
828 OS << ", ";
829 MI->second[i].PrintArguments(OS);
830 OS << "))\n return Reg;\n\n";
831 }
832
833 // Done with this, remove it.
834 SignaturesWithConstantForms.erase(MI);
835 }
836
837 OS << " switch (Opcode) {\n";
838 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end();
839 I != E; ++I) {
840 const std::string &Opcode = I->first;
841
842 OS << " case " << Opcode << ": return fastEmit_"
843 << getLegalCName(Opcode) << "_";
844 Operands.PrintManglingSuffix(OS, ImmediatePredicates);
845 OS << "(VT, RetVT";
846 if (!Operands.empty())
847 OS << ", ";
848 Operands.PrintArguments(OS);
849 OS << ");\n";
850 }
851 OS << " default: return 0;\n";
852 OS << " }\n";
853 OS << "}\n";
854 OS << "\n";
855 }
856
857 // TODO: SignaturesWithConstantForms should be empty here.
858}
859
860namespace llvm {
861
862void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) {
863 CodeGenDAGPatterns CGP(RK);
864 const CodeGenTarget &Target = CGP.getTargetInfo();
865 emitSourceFileHeader("\"Fast\" Instruction Selector for the " +
866 Target.getName().str() + " target", OS);
867
868 // Determine the target's namespace name.
869 StringRef InstNS = Target.getInstNamespace();
870 assert(!InstNS.empty() && "Can't determine target-specific namespace!")(static_cast <bool> (!InstNS.empty() && "Can't determine target-specific namespace!"
) ? void (0) : __assert_fail ("!InstNS.empty() && \"Can't determine target-specific namespace!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/utils/TableGen/FastISelEmitter.cpp"
, 870, __extension__ __PRETTY_FUNCTION__));
871
872 FastISelMap F(InstNS);
873 F.collectPatterns(CGP);
874 F.printImmediatePredicates(OS);
875 F.printFunctionDefinitions(OS);
876}
877
878} // End llvm namespace