Bug Summary

File:lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
Warning:line 641, column 7
Forming reference to null pointer

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name HexagonAsmParser.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/Hexagon/AsmParser -I /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser -I /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn345461/include -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/Hexagon/AsmParser/.. -I /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/.. -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/Hexagon/AsmParser -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-10-27-211344-32123-1 -x c++ /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp -faddrsig
1//===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE"mcasmparser" "mcasmparser"
11
12#include "Hexagon.h"
13#include "HexagonTargetStreamer.h"
14#include "MCTargetDesc/HexagonMCChecker.h"
15#include "MCTargetDesc/HexagonMCELFStreamer.h"
16#include "MCTargetDesc/HexagonMCExpr.h"
17#include "MCTargetDesc/HexagonMCInstrInfo.h"
18#include "MCTargetDesc/HexagonMCTargetDesc.h"
19#include "MCTargetDesc/HexagonShuffler.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/ADT/StringExtras.h"
23#include "llvm/ADT/StringRef.h"
24#include "llvm/ADT/Twine.h"
25#include "llvm/BinaryFormat/ELF.h"
26#include "llvm/MC/MCAssembler.h"
27#include "llvm/MC/MCContext.h"
28#include "llvm/MC/MCDirectives.h"
29#include "llvm/MC/MCELFStreamer.h"
30#include "llvm/MC/MCExpr.h"
31#include "llvm/MC/MCInst.h"
32#include "llvm/MC/MCParser/MCAsmLexer.h"
33#include "llvm/MC/MCParser/MCAsmParser.h"
34#include "llvm/MC/MCParser/MCAsmParserExtension.h"
35#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
36#include "llvm/MC/MCParser/MCTargetAsmParser.h"
37#include "llvm/MC/MCRegisterInfo.h"
38#include "llvm/MC/MCSectionELF.h"
39#include "llvm/MC/MCStreamer.h"
40#include "llvm/MC/MCSubtargetInfo.h"
41#include "llvm/MC/MCSymbol.h"
42#include "llvm/MC/MCValue.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/CommandLine.h"
45#include "llvm/Support/Debug.h"
46#include "llvm/Support/ErrorHandling.h"
47#include "llvm/Support/Format.h"
48#include "llvm/Support/MathExtras.h"
49#include "llvm/Support/SMLoc.h"
50#include "llvm/Support/SourceMgr.h"
51#include "llvm/Support/TargetRegistry.h"
52#include "llvm/Support/raw_ostream.h"
53#include <algorithm>
54#include <cassert>
55#include <cctype>
56#include <cstddef>
57#include <cstdint>
58#include <memory>
59#include <string>
60#include <utility>
61
62using namespace llvm;
63
64static cl::opt<bool> WarnMissingParenthesis(
65 "mwarn-missing-parenthesis",
66 cl::desc("Warn for missing parenthesis around predicate registers"),
67 cl::init(true));
68static cl::opt<bool> ErrorMissingParenthesis(
69 "merror-missing-parenthesis",
70 cl::desc("Error for missing parenthesis around predicate registers"),
71 cl::init(false));
72static cl::opt<bool> WarnSignedMismatch(
73 "mwarn-sign-mismatch",
74 cl::desc("Warn for mismatching a signed and unsigned value"),
75 cl::init(true));
76static cl::opt<bool> WarnNoncontigiousRegister(
77 "mwarn-noncontigious-register",
78 cl::desc("Warn for register names that arent contigious"), cl::init(true));
79static cl::opt<bool> ErrorNoncontigiousRegister(
80 "merror-noncontigious-register",
81 cl::desc("Error for register names that aren't contigious"),
82 cl::init(false));
83
84namespace {
85
86struct HexagonOperand;
87
88class HexagonAsmParser : public MCTargetAsmParser {
89
90 HexagonTargetStreamer &getTargetStreamer() {
91 MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer();
92 return static_cast<HexagonTargetStreamer &>(TS);
93 }
94
95 MCAsmParser &Parser;
96 MCInst MCB;
97 bool InBrackets;
98
99 MCAsmParser &getParser() const { return Parser; }
100 MCAssembler *getAssembler() const {
101 MCAssembler *Assembler = nullptr;
102 // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
103 if (!Parser.getStreamer().hasRawTextSupport()) {
104 MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
105 Assembler = &MES->getAssembler();
106 }
107 return Assembler;
108 }
109
110 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
111
112 bool equalIsAsmAssignment() override { return false; }
113 bool isLabel(AsmToken &Token) override;
114
115 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
116 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
117 bool ParseDirectiveFalign(unsigned Size, SMLoc L);
118
119 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
120 bool ParseDirectiveSubsection(SMLoc L);
121 bool ParseDirectiveComm(bool IsLocal, SMLoc L);
122 bool RegisterMatchesArch(unsigned MatchNum) const;
123
124 bool matchBundleOptions();
125 bool handleNoncontigiousRegister(bool Contigious, SMLoc &Loc);
126 bool finishBundle(SMLoc IDLoc, MCStreamer &Out);
127 void canonicalizeImmediates(MCInst &MCI);
128 bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
129 OperandVector &InstOperands, uint64_t &ErrorInfo,
130 bool MatchingInlineAsm);
131 void eatToEndOfPacket();
132 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
133 OperandVector &Operands, MCStreamer &Out,
134 uint64_t &ErrorInfo,
135 bool MatchingInlineAsm) override;
136
137 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
138 unsigned Kind) override;
139 bool OutOfRange(SMLoc IDLoc, long long Val, long long Max);
140 int processInstruction(MCInst &Inst, OperandVector const &Operands,
141 SMLoc IDLoc);
142
143 // Check if we have an assembler and, if so, set the ELF e_header flags.
144 void chksetELFHeaderEFlags(unsigned flags) {
145 if (getAssembler())
146 getAssembler()->setELFHeaderEFlags(flags);
147 }
148
149 unsigned matchRegister(StringRef Name);
150
151/// @name Auto-generated Match Functions
152/// {
153
154#define GET_ASSEMBLER_HEADER
155#include "HexagonGenAsmMatcher.inc"
156
157 /// }
158
159public:
160 HexagonAsmParser(const MCSubtargetInfo &_STI, MCAsmParser &_Parser,
161 const MCInstrInfo &MII, const MCTargetOptions &Options)
162 : MCTargetAsmParser(Options, _STI, MII), Parser(_Parser),
163 InBrackets(false) {
164 MCB.setOpcode(Hexagon::BUNDLE);
165 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
166
167 Parser.addAliasForDirective(".half", ".2byte");
168 Parser.addAliasForDirective(".hword", ".2byte");
169 Parser.addAliasForDirective(".word", ".4byte");
170
171 MCAsmParserExtension::Initialize(_Parser);
172 }
173
174 bool splitIdentifier(OperandVector &Operands);
175 bool parseOperand(OperandVector &Operands);
176 bool parseInstruction(OperandVector &Operands);
177 bool implicitExpressionLocation(OperandVector &Operands);
178 bool parseExpressionOrOperand(OperandVector &Operands);
179 bool parseExpression(MCExpr const *&Expr);
180
181 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
182 SMLoc NameLoc, OperandVector &Operands) override {
183 llvm_unreachable("Unimplemented")::llvm::llvm_unreachable_internal("Unimplemented", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 183)
;
184 }
185
186 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, AsmToken ID,
187 OperandVector &Operands) override;
188
189 bool ParseDirective(AsmToken DirectiveID) override;
190};
191
192/// HexagonOperand - Instances of this class represent a parsed Hexagon machine
193/// instruction.
194struct HexagonOperand : public MCParsedAsmOperand {
195 enum KindTy { Token, Immediate, Register } Kind;
196 MCContext &Context;
197
198 SMLoc StartLoc, EndLoc;
199
200 struct TokTy {
201 const char *Data;
202 unsigned Length;
203 };
204
205 struct RegTy {
206 unsigned RegNum;
207 };
208
209 struct ImmTy {
210 const MCExpr *Val;
211 };
212
213 struct InstTy {
214 OperandVector *SubInsts;
215 };
216
217 union {
218 struct TokTy Tok;
219 struct RegTy Reg;
220 struct ImmTy Imm;
221 };
222
223 HexagonOperand(KindTy K, MCContext &Context)
224 : MCParsedAsmOperand(), Kind(K), Context(Context) {}
225
226public:
227 HexagonOperand(const HexagonOperand &o)
228 : MCParsedAsmOperand(), Context(o.Context) {
229 Kind = o.Kind;
230 StartLoc = o.StartLoc;
231 EndLoc = o.EndLoc;
232 switch (Kind) {
233 case Register:
234 Reg = o.Reg;
235 break;
236 case Immediate:
237 Imm = o.Imm;
238 break;
239 case Token:
240 Tok = o.Tok;
241 break;
242 }
243 }
244
245 /// getStartLoc - Get the location of the first token of this operand.
246 SMLoc getStartLoc() const override { return StartLoc; }
247
248 /// getEndLoc - Get the location of the last token of this operand.
249 SMLoc getEndLoc() const override { return EndLoc; }
250
251 unsigned getReg() const override {
252 assert(Kind == Register && "Invalid access!")((Kind == Register && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("Kind == Register && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 252, __PRETTY_FUNCTION__))
;
253 return Reg.RegNum;
254 }
255
256 const MCExpr *getImm() const {
257 assert(Kind == Immediate && "Invalid access!")((Kind == Immediate && "Invalid access!") ? static_cast
<void> (0) : __assert_fail ("Kind == Immediate && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 257, __PRETTY_FUNCTION__))
;
258 return Imm.Val;
259 }
260
261 bool isToken() const override { return Kind == Token; }
262 bool isImm() const override { return Kind == Immediate; }
263 bool isMem() const override { llvm_unreachable("No isMem")::llvm::llvm_unreachable_internal("No isMem", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 263)
; }
264 bool isReg() const override { return Kind == Register; }
265
266 bool CheckImmRange(int immBits, int zeroBits, bool isSigned,
267 bool isRelocatable, bool Extendable) const {
268 if (Kind == Immediate) {
269 const MCExpr *myMCExpr = &HexagonMCInstrInfo::getExpr(*getImm());
270 if (HexagonMCInstrInfo::mustExtend(*Imm.Val) && !Extendable)
271 return false;
272 int64_t Res;
273 if (myMCExpr->evaluateAsAbsolute(Res)) {
274 int bits = immBits + zeroBits;
275 // Field bit range is zerobits + bits
276 // zeroBits must be 0
277 if (Res & ((1 << zeroBits) - 1))
278 return false;
279 if (isSigned) {
280 if (Res < (1LL << (bits - 1)) && Res >= -(1LL << (bits - 1)))
281 return true;
282 } else {
283 if (bits == 64)
284 return true;
285 if (Res >= 0)
286 return ((uint64_t)Res < (uint64_t)(1ULL << bits));
287 else {
288 const int64_t high_bit_set = 1ULL << 63;
289 const uint64_t mask = (high_bit_set >> (63 - bits));
290 return (((uint64_t)Res & mask) == mask);
291 }
292 }
293 } else if (myMCExpr->getKind() == MCExpr::SymbolRef && isRelocatable)
294 return true;
295 else if (myMCExpr->getKind() == MCExpr::Binary ||
296 myMCExpr->getKind() == MCExpr::Unary)
297 return true;
298 }
299 return false;
300 }
301
302 bool isa30_2Imm() const { return CheckImmRange(30, 2, true, true, true); }
303 bool isb30_2Imm() const { return CheckImmRange(30, 2, true, true, true); }
304 bool isb15_2Imm() const { return CheckImmRange(15, 2, true, true, false); }
305 bool isb13_2Imm() const { return CheckImmRange(13, 2, true, true, false); }
306
307 bool ism32_0Imm() const { return true; }
308
309 bool isf32Imm() const { return false; }
310 bool isf64Imm() const { return false; }
311 bool iss32_0Imm() const { return true; }
312 bool iss31_1Imm() const { return true; }
313 bool iss30_2Imm() const { return true; }
314 bool iss29_3Imm() const { return true; }
315 bool iss27_2Imm() const { return CheckImmRange(27, 2, true, true, false); }
316 bool iss10_0Imm() const { return CheckImmRange(10, 0, true, false, false); }
317 bool iss10_6Imm() const { return CheckImmRange(10, 6, true, false, false); }
318 bool iss9_0Imm() const { return CheckImmRange(9, 0, true, false, false); }
319 bool iss8_0Imm() const { return CheckImmRange(8, 0, true, false, false); }
320 bool iss8_0Imm64() const { return CheckImmRange(8, 0, true, true, false); }
321 bool iss7_0Imm() const { return CheckImmRange(7, 0, true, false, false); }
322 bool iss6_0Imm() const { return CheckImmRange(6, 0, true, false, false); }
323 bool iss6_3Imm() const { return CheckImmRange(6, 3, true, false, false); }
324 bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); }
325 bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
326 bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
327 bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
328 bool iss3_0Imm() const { return CheckImmRange(3, 0, true, false, false); }
329
330 bool isu64_0Imm() const { return CheckImmRange(64, 0, false, true, true); }
331 bool isu32_0Imm() const { return true; }
332 bool isu31_1Imm() const { return true; }
333 bool isu30_2Imm() const { return true; }
334 bool isu29_3Imm() const { return true; }
335 bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); }
336 bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); }
337 bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); }
338 bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); }
339 bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); }
340 bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); }
341 bool isu10_0Imm() const { return CheckImmRange(10, 0, false, false, false); }
342 bool isu9_0Imm() const { return CheckImmRange(9, 0, false, false, false); }
343 bool isu8_0Imm() const { return CheckImmRange(8, 0, false, false, false); }
344 bool isu7_0Imm() const { return CheckImmRange(7, 0, false, false, false); }
345 bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
346 bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); }
347 bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); }
348 bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); }
349 bool isu5_0Imm() const { return CheckImmRange(5, 0, false, false, false); }
350 bool isu5_2Imm() const { return CheckImmRange(5, 2, false, false, false); }
351 bool isu5_3Imm() const { return CheckImmRange(5, 3, false, false, false); }
352 bool isu4_0Imm() const { return CheckImmRange(4, 0, false, false, false); }
353 bool isu4_2Imm() const { return CheckImmRange(4, 2, false, false, false); }
354 bool isu3_0Imm() const { return CheckImmRange(3, 0, false, false, false); }
355 bool isu3_1Imm() const { return CheckImmRange(3, 1, false, false, false); }
356 bool isu2_0Imm() const { return CheckImmRange(2, 0, false, false, false); }
357 bool isu1_0Imm() const { return CheckImmRange(1, 0, false, false, false); }
358
359 bool isn1Const() const {
360 if (!isImm())
361 return false;
362 int64_t Value;
363 if (!getImm()->evaluateAsAbsolute(Value))
364 return false;
365 return Value == -1;
366 }
367 bool iss11_0Imm() const {
368 return CheckImmRange(11 + 26, 0, true, true, true);
369 }
370 bool iss11_1Imm() const {
371 return CheckImmRange(11 + 26, 1, true, true, true);
372 }
373 bool iss11_2Imm() const {
374 return CheckImmRange(11 + 26, 2, true, true, true);
375 }
376 bool iss11_3Imm() const {
377 return CheckImmRange(11 + 26, 3, true, true, true);
378 }
379 bool isu32_0MustExt() const { return isImm(); }
380
381 void addRegOperands(MCInst &Inst, unsigned N) const {
382 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 382, __PRETTY_FUNCTION__))
;
383 Inst.addOperand(MCOperand::createReg(getReg()));
384 }
385
386 void addImmOperands(MCInst &Inst, unsigned N) const {
387 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 387, __PRETTY_FUNCTION__))
;
388 Inst.addOperand(MCOperand::createExpr(getImm()));
389 }
390
391 void addSignedImmOperands(MCInst &Inst, unsigned N) const {
392 assert(N == 1 && "Invalid number of operands!")((N == 1 && "Invalid number of operands!") ? static_cast
<void> (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 392, __PRETTY_FUNCTION__))
;
393 HexagonMCExpr *Expr =
394 const_cast<HexagonMCExpr *>(cast<HexagonMCExpr>(getImm()));
395 int64_t Value;
396 if (!Expr->evaluateAsAbsolute(Value)) {
397 Inst.addOperand(MCOperand::createExpr(Expr));
398 return;
399 }
400 int64_t Extended = SignExtend64(Value, 32);
401 HexagonMCExpr *NewExpr = HexagonMCExpr::create(
402 MCConstantExpr::create(Extended, Context), Context);
403 if ((Extended < 0) != (Value < 0))
404 NewExpr->setSignMismatch();
405 NewExpr->setMustExtend(Expr->mustExtend());
406 NewExpr->setMustNotExtend(Expr->mustNotExtend());
407 Inst.addOperand(MCOperand::createExpr(NewExpr));
408 }
409
410 void addn1ConstOperands(MCInst &Inst, unsigned N) const {
411 addImmOperands(Inst, N);
412 }
413
414 StringRef getToken() const {
415 assert(Kind == Token && "Invalid access!")((Kind == Token && "Invalid access!") ? static_cast<
void> (0) : __assert_fail ("Kind == Token && \"Invalid access!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 415, __PRETTY_FUNCTION__))
;
416 return StringRef(Tok.Data, Tok.Length);
417 }
418
419 void print(raw_ostream &OS) const override;
420
421 static std::unique_ptr<HexagonOperand> CreateToken(MCContext &Context,
422 StringRef Str, SMLoc S) {
423 HexagonOperand *Op = new HexagonOperand(Token, Context);
424 Op->Tok.Data = Str.data();
425 Op->Tok.Length = Str.size();
426 Op->StartLoc = S;
427 Op->EndLoc = S;
428 return std::unique_ptr<HexagonOperand>(Op);
429 }
430
431 static std::unique_ptr<HexagonOperand>
432 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) {
433 HexagonOperand *Op = new HexagonOperand(Register, Context);
434 Op->Reg.RegNum = RegNum;
435 Op->StartLoc = S;
436 Op->EndLoc = E;
437 return std::unique_ptr<HexagonOperand>(Op);
438 }
439
440 static std::unique_ptr<HexagonOperand>
441 CreateImm(MCContext &Context, const MCExpr *Val, SMLoc S, SMLoc E) {
442 HexagonOperand *Op = new HexagonOperand(Immediate, Context);
443 Op->Imm.Val = Val;
444 Op->StartLoc = S;
445 Op->EndLoc = E;
446 return std::unique_ptr<HexagonOperand>(Op);
447 }
448};
449
450} // end anonymous namespace
451
452void HexagonOperand::print(raw_ostream &OS) const {
453 switch (Kind) {
454 case Immediate:
455 getImm()->print(OS, nullptr);
456 break;
457 case Register:
458 OS << "<register R";
459 OS << getReg() << ">";
460 break;
461 case Token:
462 OS << "'" << getToken() << "'";
463 break;
464 }
465}
466
467bool HexagonAsmParser::finishBundle(SMLoc IDLoc, MCStreamer &Out) {
468 LLVM_DEBUG(dbgs() << "Bundle:")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mcasmparser")) { dbgs() << "Bundle:"; } } while (false
)
;
469 LLVM_DEBUG(MCB.dump_pretty(dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mcasmparser")) { MCB.dump_pretty(dbgs()); } } while (false)
;
470 LLVM_DEBUG(dbgs() << "--\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mcasmparser")) { dbgs() << "--\n"; } } while (false)
;
471
472 MCB.setLoc(IDLoc);
473 // Check the bundle for errors.
474 const MCRegisterInfo *RI = getContext().getRegisterInfo();
475 HexagonMCChecker Check(getContext(), MII, getSTI(), MCB, *RI);
476
477 bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MII, getSTI(),
478 getContext(), MCB,
479 &Check);
480
481 if (CheckOk) {
482 if (HexagonMCInstrInfo::bundleSize(MCB) == 0) {
483 assert(!HexagonMCInstrInfo::isInnerLoop(MCB))((!HexagonMCInstrInfo::isInnerLoop(MCB)) ? static_cast<void
> (0) : __assert_fail ("!HexagonMCInstrInfo::isInnerLoop(MCB)"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 483, __PRETTY_FUNCTION__))
;
484 assert(!HexagonMCInstrInfo::isOuterLoop(MCB))((!HexagonMCInstrInfo::isOuterLoop(MCB)) ? static_cast<void
> (0) : __assert_fail ("!HexagonMCInstrInfo::isOuterLoop(MCB)"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 484, __PRETTY_FUNCTION__))
;
485 // Empty packets are valid yet aren't emitted
486 return false;
487 }
488 Out.EmitInstruction(MCB, getSTI());
489 } else {
490 // If compounding and duplexing didn't reduce the size below
491 // 4 or less we have a packet that is too big.
492 if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE4) {
493 Error(IDLoc, "invalid instruction packet: out of slots");
494 }
495 return true; // Error
496 }
497
498 return false; // No error
499}
500
501bool HexagonAsmParser::matchBundleOptions() {
502 MCAsmParser &Parser = getParser();
503 while (true) {
504 if (!Parser.getTok().is(AsmToken::Colon))
505 return false;
506 Lex();
507 char const *MemNoShuffMsg =
508 "invalid instruction packet: mem_noshuf specifier not "
509 "supported with this architecture";
510 StringRef Option = Parser.getTok().getString();
511 auto IDLoc = Parser.getTok().getLoc();
512 if (Option.compare_lower("endloop01") == 0) {
513 HexagonMCInstrInfo::setInnerLoop(MCB);
514 HexagonMCInstrInfo::setOuterLoop(MCB);
515 } else if (Option.compare_lower("endloop0") == 0) {
516 HexagonMCInstrInfo::setInnerLoop(MCB);
517 } else if (Option.compare_lower("endloop1") == 0) {
518 HexagonMCInstrInfo::setOuterLoop(MCB);
519 } else if (Option.compare_lower("mem_noshuf") == 0) {
520 if (getSTI().getFeatureBits()[Hexagon::FeatureMemNoShuf])
521 HexagonMCInstrInfo::setMemReorderDisabled(MCB);
522 else
523 return getParser().Error(IDLoc, MemNoShuffMsg);
524 } else
525 return getParser().Error(IDLoc, llvm::Twine("'") + Option +
526 "' is not a valid bundle option");
527 Lex();
528 }
529}
530
531// For instruction aliases, immediates are generated rather than
532// MCConstantExpr. Convert them for uniform MCExpr.
533// Also check for signed/unsigned mismatches and warn
534void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
535 MCInst NewInst;
536 NewInst.setOpcode(MCI.getOpcode());
537 for (MCOperand &I : MCI)
538 if (I.isImm()) {
539 int64_t Value(I.getImm());
540 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
541 MCConstantExpr::create(Value, getContext()), getContext())));
542 } else {
543 if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() &&
544 WarnSignedMismatch)
545 Warning(MCI.getLoc(), "Signed/Unsigned mismatch");
546 NewInst.addOperand(I);
547 }
548 MCI = NewInst;
549}
550
551bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
552 OperandVector &InstOperands,
553 uint64_t &ErrorInfo,
554 bool MatchingInlineAsm) {
555 // Perform matching with tablegen asmmatcher generated function
556 int result =
557 MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);
558 if (result == Match_Success) {
559 MCI.setLoc(IDLoc);
560 canonicalizeImmediates(MCI);
561 result = processInstruction(MCI, InstOperands, IDLoc);
562
563 LLVM_DEBUG(dbgs() << "Insn:")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mcasmparser")) { dbgs() << "Insn:"; } } while (false)
;
564 LLVM_DEBUG(MCI.dump_pretty(dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mcasmparser")) { MCI.dump_pretty(dbgs()); } } while (false)
;
565 LLVM_DEBUG(dbgs() << "\n\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mcasmparser")) { dbgs() << "\n\n"; } } while (false)
;
566
567 MCI.setLoc(IDLoc);
568 }
569
570 // Create instruction operand for bundle instruction
571 // Break this into a separate function Code here is less readable
572 // Think about how to get an instruction error to report correctly.
573 // SMLoc will return the "{"
574 switch (result) {
575 default:
576 break;
577 case Match_Success:
578 return false;
579 case Match_MissingFeature:
580 return Error(IDLoc, "invalid instruction");
581 case Match_MnemonicFail:
582 return Error(IDLoc, "unrecognized instruction");
583 case Match_InvalidOperand:
584 case Match_InvalidTiedOperand:
585 SMLoc ErrorLoc = IDLoc;
586 if (ErrorInfo != ~0U) {
587 if (ErrorInfo >= InstOperands.size())
588 return Error(IDLoc, "too few operands for instruction");
589
590 ErrorLoc = (static_cast<HexagonOperand *>(InstOperands[ErrorInfo].get()))
591 ->getStartLoc();
592 if (ErrorLoc == SMLoc())
593 ErrorLoc = IDLoc;
594 }
595 return Error(ErrorLoc, "invalid operand for instruction");
596 }
597 llvm_unreachable("Implement any new match types added!")::llvm::llvm_unreachable_internal("Implement any new match types added!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 597)
;
598}
599
600void HexagonAsmParser::eatToEndOfPacket() {
601 assert(InBrackets)((InBrackets) ? static_cast<void> (0) : __assert_fail (
"InBrackets", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 601, __PRETTY_FUNCTION__))
;
602 MCAsmLexer &Lexer = getLexer();
603 while (!Lexer.is(AsmToken::RCurly))
604 Lexer.Lex();
605 Lexer.Lex();
606 InBrackets = false;
607}
608
609bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
610 OperandVector &Operands,
611 MCStreamer &Out,
612 uint64_t &ErrorInfo,
613 bool MatchingInlineAsm) {
614 if (!InBrackets) {
1
Assuming the condition is false
2
Taking false branch
615 MCB.clear();
616 MCB.addOperand(MCOperand::createImm(0));
617 }
618 HexagonOperand &FirstOperand = static_cast<HexagonOperand &>(*Operands[0]);
619 if (FirstOperand.isToken() && FirstOperand.getToken() == "{") {
3
Assuming the condition is false
4
Taking false branch
620 assert(Operands.size() == 1 && "Brackets should be by themselves")((Operands.size() == 1 && "Brackets should be by themselves"
) ? static_cast<void> (0) : __assert_fail ("Operands.size() == 1 && \"Brackets should be by themselves\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 620, __PRETTY_FUNCTION__))
;
621 if (InBrackets) {
622 getParser().Error(IDLoc, "Already in a packet");
623 InBrackets = false;
624 return true;
625 }
626 InBrackets = true;
627 return false;
628 }
629 if (FirstOperand.isToken() && FirstOperand.getToken() == "}") {
5
Assuming the condition is false
6
Taking false branch
630 assert(Operands.size() == 1 && "Brackets should be by themselves")((Operands.size() == 1 && "Brackets should be by themselves"
) ? static_cast<void> (0) : __assert_fail ("Operands.size() == 1 && \"Brackets should be by themselves\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 630, __PRETTY_FUNCTION__))
;
631 if (!InBrackets) {
632 getParser().Error(IDLoc, "Not in a packet");
633 return true;
634 }
635 InBrackets = false;
636 if (matchBundleOptions())
637 return true;
638 return finishBundle(IDLoc, Out);
639 }
640 MCInst *SubInst = new (getParser().getContext()) MCInst;
7
'SubInst' initialized to a null pointer value
641 if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
8
Forming reference to null pointer
642 MatchingInlineAsm)) {
643 if (InBrackets)
644 eatToEndOfPacket();
645 return true;
646 }
647 HexagonMCInstrInfo::extendIfNeeded(
648 getParser().getContext(), MII, MCB, *SubInst);
649 MCB.addOperand(MCOperand::createInst(SubInst));
650 if (!InBrackets)
651 return finishBundle(IDLoc, Out);
652 return false;
653}
654
655/// ParseDirective parses the Hexagon specific directives
656bool HexagonAsmParser::ParseDirective(AsmToken DirectiveID) {
657 StringRef IDVal = DirectiveID.getIdentifier();
658 if (IDVal.lower() == ".falign")
659 return ParseDirectiveFalign(256, DirectiveID.getLoc());
660 if ((IDVal.lower() == ".lcomm") || (IDVal.lower() == ".lcommon"))
661 return ParseDirectiveComm(true, DirectiveID.getLoc());
662 if ((IDVal.lower() == ".comm") || (IDVal.lower() == ".common"))
663 return ParseDirectiveComm(false, DirectiveID.getLoc());
664 if (IDVal.lower() == ".subsection")
665 return ParseDirectiveSubsection(DirectiveID.getLoc());
666
667 return true;
668}
669bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) {
670 const MCExpr *Subsection = nullptr;
671 int64_t Res;
672
673 assert((getLexer().isNot(AsmToken::EndOfStatement)) &&(((getLexer().isNot(AsmToken::EndOfStatement)) && "Invalid subsection directive"
) ? static_cast<void> (0) : __assert_fail ("(getLexer().isNot(AsmToken::EndOfStatement)) && \"Invalid subsection directive\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 674, __PRETTY_FUNCTION__))
674 "Invalid subsection directive")(((getLexer().isNot(AsmToken::EndOfStatement)) && "Invalid subsection directive"
) ? static_cast<void> (0) : __assert_fail ("(getLexer().isNot(AsmToken::EndOfStatement)) && \"Invalid subsection directive\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 674, __PRETTY_FUNCTION__))
;
675 getParser().parseExpression(Subsection);
676
677 if (!Subsection->evaluateAsAbsolute(Res))
678 return Error(L, "Cannot evaluate subsection number");
679
680 if (getLexer().isNot(AsmToken::EndOfStatement))
681 return TokError("unexpected token in directive");
682
683 // 0-8192 is the hard-coded range in MCObjectStreamper.cpp, this keeps the
684 // negative subsections together and in the same order but at the opposite
685 // end of the section. Only legacy hexagon-gcc created assembly code
686 // used negative subsections.
687 if ((Res < 0) && (Res > -8193))
688 Subsection = HexagonMCExpr::create(
689 MCConstantExpr::create(8192 + Res, getContext()), getContext());
690
691 getStreamer().SubSection(Subsection);
692 return false;
693}
694
695/// ::= .falign [expression]
696bool HexagonAsmParser::ParseDirectiveFalign(unsigned Size, SMLoc L) {
697
698 int64_t MaxBytesToFill = 15;
699
700 // if there is an argument
701 if (getLexer().isNot(AsmToken::EndOfStatement)) {
702 const MCExpr *Value;
703 SMLoc ExprLoc = L;
704
705 // Make sure we have a number (false is returned if expression is a number)
706 if (!getParser().parseExpression(Value)) {
707 // Make sure this is a number that is in range
708 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(Value);
709 uint64_t IntValue = MCE->getValue();
710 if (!isUIntN(Size, IntValue) && !isIntN(Size, IntValue))
711 return Error(ExprLoc, "literal value out of range (256) for falign");
712 MaxBytesToFill = IntValue;
713 Lex();
714 } else {
715 return Error(ExprLoc, "not a valid expression for falign directive");
716 }
717 }
718
719 getTargetStreamer().emitFAlign(16, MaxBytesToFill);
720 Lex();
721
722 return false;
723}
724
725// This is largely a copy of AsmParser's ParseDirectiveComm extended to
726// accept a 3rd argument, AccessAlignment which indicates the smallest
727// memory access made to the symbol, expressed in bytes. If no
728// AccessAlignment is specified it defaults to the Alignment Value.
729// Hexagon's .lcomm:
730// .lcomm Symbol, Length, Alignment, AccessAlignment
731bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) {
732 // FIXME: need better way to detect if AsmStreamer (upstream removed
733 // getKind())
734 if (getStreamer().hasRawTextSupport())
735 return true; // Only object file output requires special treatment.
736
737 StringRef Name;
738 if (getParser().parseIdentifier(Name))
739 return TokError("expected identifier in directive");
740 // Handle the identifier as the key symbol.
741 MCSymbol *Sym = getContext().getOrCreateSymbol(Name);
742
743 if (getLexer().isNot(AsmToken::Comma))
744 return TokError("unexpected token in directive");
745 Lex();
746
747 int64_t Size;
748 SMLoc SizeLoc = getLexer().getLoc();
749 if (getParser().parseAbsoluteExpression(Size))
750 return true;
751
752 int64_t ByteAlignment = 1;
753 SMLoc ByteAlignmentLoc;
754 if (getLexer().is(AsmToken::Comma)) {
755 Lex();
756 ByteAlignmentLoc = getLexer().getLoc();
757 if (getParser().parseAbsoluteExpression(ByteAlignment))
758 return true;
759 if (!isPowerOf2_64(ByteAlignment))
760 return Error(ByteAlignmentLoc, "alignment must be a power of 2");
761 }
762
763 int64_t AccessAlignment = 0;
764 if (getLexer().is(AsmToken::Comma)) {
765 // The optional access argument specifies the size of the smallest memory
766 // access to be made to the symbol, expressed in bytes.
767 SMLoc AccessAlignmentLoc;
768 Lex();
769 AccessAlignmentLoc = getLexer().getLoc();
770 if (getParser().parseAbsoluteExpression(AccessAlignment))
771 return true;
772
773 if (!isPowerOf2_64(AccessAlignment))
774 return Error(AccessAlignmentLoc, "access alignment must be a power of 2");
775 }
776
777 if (getLexer().isNot(AsmToken::EndOfStatement))
778 return TokError("unexpected token in '.comm' or '.lcomm' directive");
779
780 Lex();
781
782 // NOTE: a size of zero for a .comm should create a undefined symbol
783 // but a size of .lcomm creates a bss symbol of size zero.
784 if (Size < 0)
785 return Error(SizeLoc, "invalid '.comm' or '.lcomm' directive size, can't "
786 "be less than zero");
787
788 // NOTE: The alignment in the directive is a power of 2 value, the assembler
789 // may internally end up wanting an alignment in bytes.
790 // FIXME: Diagnose overflow.
791 if (ByteAlignment < 0)
792 return Error(ByteAlignmentLoc, "invalid '.comm' or '.lcomm' directive "
793 "alignment, can't be less than zero");
794
795 if (!Sym->isUndefined())
796 return Error(Loc, "invalid symbol redefinition");
797
798 HexagonMCELFStreamer &HexagonELFStreamer =
799 static_cast<HexagonMCELFStreamer &>(getStreamer());
800 if (IsLocal) {
801 HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(Sym, Size, ByteAlignment,
802 AccessAlignment);
803 return false;
804 }
805
806 HexagonELFStreamer.HexagonMCEmitCommonSymbol(Sym, Size, ByteAlignment,
807 AccessAlignment);
808 return false;
809}
810
811// validate register against architecture
812bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const {
813 if (HexagonMCRegisterClasses[Hexagon::V62RegsRegClassID].contains(MatchNum))
814 if (!getSTI().getFeatureBits()[Hexagon::ArchV62])
815 return false;
816 return true;
817}
818
819// extern "C" void LLVMInitializeHexagonAsmLexer();
820
821/// Force static initialization.
822extern "C" void LLVMInitializeHexagonAsmParser() {
823 RegisterMCAsmParser<HexagonAsmParser> X(getTheHexagonTarget());
824}
825
826#define GET_MATCHER_IMPLEMENTATION
827#define GET_REGISTER_MATCHER
828#include "HexagonGenAsmMatcher.inc"
829
830static bool previousEqual(OperandVector &Operands, size_t Index,
831 StringRef String) {
832 if (Index >= Operands.size())
833 return false;
834 MCParsedAsmOperand &Operand = *Operands[Operands.size() - Index - 1];
835 if (!Operand.isToken())
836 return false;
837 return static_cast<HexagonOperand &>(Operand).getToken().equals_lower(String);
838}
839
840static bool previousIsLoop(OperandVector &Operands, size_t Index) {
841 return previousEqual(Operands, Index, "loop0") ||
842 previousEqual(Operands, Index, "loop1") ||
843 previousEqual(Operands, Index, "sp1loop0") ||
844 previousEqual(Operands, Index, "sp2loop0") ||
845 previousEqual(Operands, Index, "sp3loop0");
846}
847
848bool HexagonAsmParser::splitIdentifier(OperandVector &Operands) {
849 AsmToken const &Token = getParser().getTok();
850 StringRef String = Token.getString();
851 SMLoc Loc = Token.getLoc();
852 Lex();
853 do {
854 std::pair<StringRef, StringRef> HeadTail = String.split('.');
855 if (!HeadTail.first.empty())
856 Operands.push_back(
857 HexagonOperand::CreateToken(getContext(), HeadTail.first, Loc));
858 if (!HeadTail.second.empty())
859 Operands.push_back(HexagonOperand::CreateToken(
860 getContext(), String.substr(HeadTail.first.size(), 1), Loc));
861 String = HeadTail.second;
862 } while (!String.empty());
863 return false;
864}
865
866bool HexagonAsmParser::parseOperand(OperandVector &Operands) {
867 unsigned Register;
868 SMLoc Begin;
869 SMLoc End;
870 MCAsmLexer &Lexer = getLexer();
871 if (!ParseRegister(Register, Begin, End)) {
872 if (!ErrorMissingParenthesis)
873 switch (Register) {
874 default:
875 break;
876 case Hexagon::P0:
877 case Hexagon::P1:
878 case Hexagon::P2:
879 case Hexagon::P3:
880 if (previousEqual(Operands, 0, "if")) {
881 if (WarnMissingParenthesis)
882 Warning(Begin, "Missing parenthesis around predicate register");
883 static char const *LParen = "(";
884 static char const *RParen = ")";
885 Operands.push_back(
886 HexagonOperand::CreateToken(getContext(), LParen, Begin));
887 Operands.push_back(
888 HexagonOperand::CreateReg(getContext(), Register, Begin, End));
889 const AsmToken &MaybeDotNew = Lexer.getTok();
890 if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
891 MaybeDotNew.getString().equals_lower(".new"))
892 splitIdentifier(Operands);
893 Operands.push_back(
894 HexagonOperand::CreateToken(getContext(), RParen, Begin));
895 return false;
896 }
897 if (previousEqual(Operands, 0, "!") &&
898 previousEqual(Operands, 1, "if")) {
899 if (WarnMissingParenthesis)
900 Warning(Begin, "Missing parenthesis around predicate register");
901 static char const *LParen = "(";
902 static char const *RParen = ")";
903 Operands.insert(Operands.end() - 1, HexagonOperand::CreateToken(
904 getContext(), LParen, Begin));
905 Operands.push_back(
906 HexagonOperand::CreateReg(getContext(), Register, Begin, End));
907 const AsmToken &MaybeDotNew = Lexer.getTok();
908 if (MaybeDotNew.is(AsmToken::TokenKind::Identifier) &&
909 MaybeDotNew.getString().equals_lower(".new"))
910 splitIdentifier(Operands);
911 Operands.push_back(
912 HexagonOperand::CreateToken(getContext(), RParen, Begin));
913 return false;
914 }
915 break;
916 }
917 Operands.push_back(
918 HexagonOperand::CreateReg(getContext(), Register, Begin, End));
919 return false;
920 }
921 return splitIdentifier(Operands);
922}
923
924bool HexagonAsmParser::isLabel(AsmToken &Token) {
925 MCAsmLexer &Lexer = getLexer();
926 AsmToken const &Second = Lexer.getTok();
927 AsmToken Third = Lexer.peekTok();
928 StringRef String = Token.getString();
929 if (Token.is(AsmToken::TokenKind::LCurly) ||
930 Token.is(AsmToken::TokenKind::RCurly))
931 return false;
932 // special case for parsing vwhist256:sat
933 if (String.lower() == "vwhist256" && Second.is(AsmToken::Colon) &&
934 Third.getString().lower() == "sat")
935 return false;
936 if (!Token.is(AsmToken::TokenKind::Identifier))
937 return true;
938 if (!matchRegister(String.lower()))
939 return true;
940 assert(Second.is(AsmToken::Colon))((Second.is(AsmToken::Colon)) ? static_cast<void> (0) :
__assert_fail ("Second.is(AsmToken::Colon)", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 940, __PRETTY_FUNCTION__))
;
941 StringRef Raw(String.data(), Third.getString().data() - String.data() +
942 Third.getString().size());
943 std::string Collapsed = Raw;
944 Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end());
945 StringRef Whole = Collapsed;
946 std::pair<StringRef, StringRef> DotSplit = Whole.split('.');
947 if (!matchRegister(DotSplit.first.lower()))
948 return true;
949 return false;
950}
951
952bool HexagonAsmParser::handleNoncontigiousRegister(bool Contigious,
953 SMLoc &Loc) {
954 if (!Contigious && ErrorNoncontigiousRegister) {
955 Error(Loc, "Register name is not contigious");
956 return true;
957 }
958 if (!Contigious && WarnNoncontigiousRegister)
959 Warning(Loc, "Register name is not contigious");
960 return false;
961}
962
963bool HexagonAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
964 SMLoc &EndLoc) {
965 MCAsmLexer &Lexer = getLexer();
966 StartLoc = getLexer().getLoc();
967 SmallVector<AsmToken, 5> Lookahead;
968 StringRef RawString(Lexer.getTok().getString().data(), 0);
969 bool Again = Lexer.is(AsmToken::Identifier);
970 bool NeededWorkaround = false;
971 while (Again) {
972 AsmToken const &Token = Lexer.getTok();
973 RawString = StringRef(RawString.data(), Token.getString().data() -
974 RawString.data() +
975 Token.getString().size());
976 Lookahead.push_back(Token);
977 Lexer.Lex();
978 bool Contigious = Lexer.getTok().getString().data() ==
979 Lookahead.back().getString().data() +
980 Lookahead.back().getString().size();
981 bool Type = Lexer.is(AsmToken::Identifier) || Lexer.is(AsmToken::Dot) ||
982 Lexer.is(AsmToken::Integer) || Lexer.is(AsmToken::Real) ||
983 Lexer.is(AsmToken::Colon);
984 bool Workaround =
985 Lexer.is(AsmToken::Colon) || Lookahead.back().is(AsmToken::Colon);
986 Again = (Contigious && Type) || (Workaround && Type);
987 NeededWorkaround = NeededWorkaround || (Again && !(Contigious && Type));
988 }
989 std::string Collapsed = RawString;
990 Collapsed.erase(llvm::remove_if(Collapsed, isspace), Collapsed.end());
991 StringRef FullString = Collapsed;
992 std::pair<StringRef, StringRef> DotSplit = FullString.split('.');
993 unsigned DotReg = matchRegister(DotSplit.first.lower());
994 if (DotReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
995 if (DotSplit.second.empty()) {
996 RegNo = DotReg;
997 EndLoc = Lexer.getLoc();
998 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
999 return true;
1000 return false;
1001 } else {
1002 RegNo = DotReg;
1003 size_t First = RawString.find('.');
1004 StringRef DotString (RawString.data() + First, RawString.size() - First);
1005 Lexer.UnLex(AsmToken(AsmToken::Identifier, DotString));
1006 EndLoc = Lexer.getLoc();
1007 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1008 return true;
1009 return false;
1010 }
1011 }
1012 std::pair<StringRef, StringRef> ColonSplit = StringRef(FullString).split(':');
1013 unsigned ColonReg = matchRegister(ColonSplit.first.lower());
1014 if (ColonReg != Hexagon::NoRegister && RegisterMatchesArch(DotReg)) {
1015 do {
1016 Lexer.UnLex(Lookahead.back());
1017 Lookahead.pop_back();
1018 } while (!Lookahead.empty () && !Lexer.is(AsmToken::Colon));
1019 RegNo = ColonReg;
1020 EndLoc = Lexer.getLoc();
1021 if (handleNoncontigiousRegister(!NeededWorkaround, StartLoc))
1022 return true;
1023 return false;
1024 }
1025 while (!Lookahead.empty()) {
1026 Lexer.UnLex(Lookahead.back());
1027 Lookahead.pop_back();
1028 }
1029 return true;
1030}
1031
1032bool HexagonAsmParser::implicitExpressionLocation(OperandVector &Operands) {
1033 if (previousEqual(Operands, 0, "call"))
1034 return true;
1035 if (previousEqual(Operands, 0, "jump"))
1036 if (!getLexer().getTok().is(AsmToken::Colon))
1037 return true;
1038 if (previousEqual(Operands, 0, "(") && previousIsLoop(Operands, 1))
1039 return true;
1040 if (previousEqual(Operands, 1, ":") && previousEqual(Operands, 2, "jump") &&
1041 (previousEqual(Operands, 0, "nt") || previousEqual(Operands, 0, "t")))
1042 return true;
1043 return false;
1044}
1045
1046bool HexagonAsmParser::parseExpression(MCExpr const *&Expr) {
1047 SmallVector<AsmToken, 4> Tokens;
1048 MCAsmLexer &Lexer = getLexer();
1049 bool Done = false;
1050 static char const *Comma = ",";
1051 do {
1052 Tokens.emplace_back(Lexer.getTok());
1053 Lex();
1054 switch (Tokens.back().getKind()) {
1055 case AsmToken::TokenKind::Hash:
1056 if (Tokens.size() > 1)
1057 if ((Tokens.end() - 2)->getKind() == AsmToken::TokenKind::Plus) {
1058 Tokens.insert(Tokens.end() - 2,
1059 AsmToken(AsmToken::TokenKind::Comma, Comma));
1060 Done = true;
1061 }
1062 break;
1063 case AsmToken::TokenKind::RCurly:
1064 case AsmToken::TokenKind::EndOfStatement:
1065 case AsmToken::TokenKind::Eof:
1066 Done = true;
1067 break;
1068 default:
1069 break;
1070 }
1071 } while (!Done);
1072 while (!Tokens.empty()) {
1073 Lexer.UnLex(Tokens.back());
1074 Tokens.pop_back();
1075 }
1076 SMLoc Loc = Lexer.getLoc();
1077 return getParser().parseExpression(Expr, Loc);
1078}
1079
1080bool HexagonAsmParser::parseExpressionOrOperand(OperandVector &Operands) {
1081 if (implicitExpressionLocation(Operands)) {
1082 MCAsmParser &Parser = getParser();
1083 SMLoc Loc = Parser.getLexer().getLoc();
1084 MCExpr const *Expr = nullptr;
1085 bool Error = parseExpression(Expr);
1086 Expr = HexagonMCExpr::create(Expr, getContext());
1087 if (!Error)
1088 Operands.push_back(
1089 HexagonOperand::CreateImm(getContext(), Expr, Loc, Loc));
1090 return Error;
1091 }
1092 return parseOperand(Operands);
1093}
1094
1095/// Parse an instruction.
1096bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
1097 MCAsmParser &Parser = getParser();
1098 MCAsmLexer &Lexer = getLexer();
1099 while (true) {
1100 AsmToken const &Token = Parser.getTok();
1101 switch (Token.getKind()) {
1102 case AsmToken::Eof:
1103 case AsmToken::EndOfStatement: {
1104 Lex();
1105 return false;
1106 }
1107 case AsmToken::LCurly: {
1108 if (!Operands.empty())
1109 return true;
1110 Operands.push_back(HexagonOperand::CreateToken(
1111 getContext(), Token.getString(), Token.getLoc()));
1112 Lex();
1113 return false;
1114 }
1115 case AsmToken::RCurly: {
1116 if (Operands.empty()) {
1117 Operands.push_back(HexagonOperand::CreateToken(
1118 getContext(), Token.getString(), Token.getLoc()));
1119 Lex();
1120 }
1121 return false;
1122 }
1123 case AsmToken::Comma: {
1124 Lex();
1125 continue;
1126 }
1127 case AsmToken::EqualEqual:
1128 case AsmToken::ExclaimEqual:
1129 case AsmToken::GreaterEqual:
1130 case AsmToken::GreaterGreater:
1131 case AsmToken::LessEqual:
1132 case AsmToken::LessLess: {
1133 Operands.push_back(HexagonOperand::CreateToken(
1134 getContext(), Token.getString().substr(0, 1), Token.getLoc()));
1135 Operands.push_back(HexagonOperand::CreateToken(
1136 getContext(), Token.getString().substr(1, 1), Token.getLoc()));
1137 Lex();
1138 continue;
1139 }
1140 case AsmToken::Hash: {
1141 bool MustNotExtend = false;
1142 bool ImplicitExpression = implicitExpressionLocation(Operands);
1143 SMLoc ExprLoc = Lexer.getLoc();
1144 if (!ImplicitExpression)
1145 Operands.push_back(HexagonOperand::CreateToken(
1146 getContext(), Token.getString(), Token.getLoc()));
1147 Lex();
1148 bool MustExtend = false;
1149 bool HiOnly = false;
1150 bool LoOnly = false;
1151 if (Lexer.is(AsmToken::Hash)) {
1152 Lex();
1153 MustExtend = true;
1154 } else if (ImplicitExpression)
1155 MustNotExtend = true;
1156 AsmToken const &Token = Parser.getTok();
1157 if (Token.is(AsmToken::Identifier)) {
1158 StringRef String = Token.getString();
1159 if (String.lower() == "hi") {
1160 HiOnly = true;
1161 } else if (String.lower() == "lo") {
1162 LoOnly = true;
1163 }
1164 if (HiOnly || LoOnly) {
1165 AsmToken LParen = Lexer.peekTok();
1166 if (!LParen.is(AsmToken::LParen)) {
1167 HiOnly = false;
1168 LoOnly = false;
1169 } else {
1170 Lex();
1171 }
1172 }
1173 }
1174 MCExpr const *Expr = nullptr;
1175 if (parseExpression(Expr))
1176 return true;
1177 int64_t Value;
1178 MCContext &Context = Parser.getContext();
1179 assert(Expr != nullptr)((Expr != nullptr) ? static_cast<void> (0) : __assert_fail
("Expr != nullptr", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 1179, __PRETTY_FUNCTION__))
;
1180 if (Expr->evaluateAsAbsolute(Value)) {
1181 if (HiOnly)
1182 Expr = MCBinaryExpr::createLShr(
1183 Expr, MCConstantExpr::create(16, Context), Context);
1184 if (HiOnly || LoOnly)
1185 Expr = MCBinaryExpr::createAnd(
1186 Expr, MCConstantExpr::create(0xffff, Context), Context);
1187 } else {
1188 MCValue Value;
1189 if (Expr->evaluateAsRelocatable(Value, nullptr, nullptr)) {
1190 if (!Value.isAbsolute()) {
1191 switch (Value.getAccessVariant()) {
1192 case MCSymbolRefExpr::VariantKind::VK_TPREL:
1193 case MCSymbolRefExpr::VariantKind::VK_DTPREL:
1194 // Don't lazy extend these expression variants
1195 MustNotExtend = !MustExtend;
1196 break;
1197 default:
1198 break;
1199 }
1200 }
1201 }
1202 }
1203 Expr = HexagonMCExpr::create(Expr, Context);
1204 HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);
1205 HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
1206 std::unique_ptr<HexagonOperand> Operand =
1207 HexagonOperand::CreateImm(getContext(), Expr, ExprLoc, ExprLoc);
1208 Operands.push_back(std::move(Operand));
1209 continue;
1210 }
1211 default:
1212 break;
1213 }
1214 if (parseExpressionOrOperand(Operands))
1215 return true;
1216 }
1217}
1218
1219bool HexagonAsmParser::ParseInstruction(ParseInstructionInfo &Info,
1220 StringRef Name, AsmToken ID,
1221 OperandVector &Operands) {
1222 getLexer().UnLex(ID);
1223 return parseInstruction(Operands);
1224}
1225
1226static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1,
1227 MCOperand &MO2) {
1228 MCInst TmpInst;
1229 TmpInst.setOpcode(opCode);
1230 TmpInst.addOperand(Rdd);
1231 TmpInst.addOperand(MO1);
1232 TmpInst.addOperand(MO2);
1233
1234 return TmpInst;
1235}
1236
1237// Define this matcher function after the auto-generated include so we
1238// have the match class enum definitions.
1239unsigned HexagonAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1240 unsigned Kind) {
1241 HexagonOperand *Op = static_cast<HexagonOperand *>(&AsmOp);
1242
1243 switch (Kind) {
1244 case MCK_0: {
1245 int64_t Value;
1246 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 0
1247 ? Match_Success
1248 : Match_InvalidOperand;
1249 }
1250 case MCK_1: {
1251 int64_t Value;
1252 return Op->isImm() && Op->Imm.Val->evaluateAsAbsolute(Value) && Value == 1
1253 ? Match_Success
1254 : Match_InvalidOperand;
1255 }
1256 }
1257 if (Op->Kind == HexagonOperand::Token && Kind != InvalidMatchClass) {
1258 StringRef myStringRef = StringRef(Op->Tok.Data, Op->Tok.Length);
1259 if (matchTokenString(myStringRef.lower()) == (MatchClassKind)Kind)
1260 return Match_Success;
1261 if (matchTokenString(myStringRef.upper()) == (MatchClassKind)Kind)
1262 return Match_Success;
1263 }
1264
1265 LLVM_DEBUG(dbgs() << "Unmatched Operand:")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mcasmparser")) { dbgs() << "Unmatched Operand:"; } } while
(false)
;
1266 LLVM_DEBUG(Op->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mcasmparser")) { Op->dump(); } } while (false)
;
1267 LLVM_DEBUG(dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mcasmparser")) { dbgs() << "\n"; } } while (false)
;
1268
1269 return Match_InvalidOperand;
1270}
1271
1272// FIXME: Calls to OutOfRange shoudl propagate failure up to parseStatement.
1273bool HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
1274 std::string errStr;
1275 raw_string_ostream ES(errStr);
1276 ES << "value " << Val << "(" << format_hex(Val, 0) << ") out of range: ";
1277 if (Max >= 0)
1278 ES << "0-" << Max;
1279 else
1280 ES << Max << "-" << (-Max - 1);
1281 return Parser.printError(IDLoc, ES.str());
1282}
1283
1284int HexagonAsmParser::processInstruction(MCInst &Inst,
1285 OperandVector const &Operands,
1286 SMLoc IDLoc) {
1287 MCContext &Context = getParser().getContext();
1288 const MCRegisterInfo *RI = getContext().getRegisterInfo();
1289 std::string r = "r";
1290 std::string v = "v";
1291 std::string Colon = ":";
1292
1293 bool is32bit = false; // used to distinguish between CONST32 and CONST64
1294 switch (Inst.getOpcode()) {
1295 default:
1296 if (HexagonMCInstrInfo::getDesc(MII, Inst).isPseudo()) {
1297 SMDiagnostic Diag = getSourceManager().GetMessage(
1298 IDLoc, SourceMgr::DK_Error,
1299 "Found pseudo instruction with no expansion");
1300 Diag.print("", errs());
1301 report_fatal_error("Invalid pseudo instruction");
1302 }
1303 break;
1304
1305 case Hexagon::J2_trap1:
1306 if (!getSTI().getFeatureBits()[Hexagon::ArchV65]) {
1307 MCOperand &Rx = Inst.getOperand(0);
1308 MCOperand &Ry = Inst.getOperand(1);
1309 if (Rx.getReg() != Hexagon::R0 || Ry.getReg() != Hexagon::R0) {
1310 Error(IDLoc, "trap1 can only have register r0 as operand");
1311 return Match_InvalidOperand;
1312 }
1313 }
1314 break;
1315
1316 case Hexagon::A2_iconst: {
1317 Inst.setOpcode(Hexagon::A2_addi);
1318 MCOperand Reg = Inst.getOperand(0);
1319 MCOperand S27 = Inst.getOperand(1);
1320 HexagonMCInstrInfo::setMustNotExtend(*S27.getExpr());
1321 HexagonMCInstrInfo::setS27_2_reloc(*S27.getExpr());
1322 Inst.clear();
1323 Inst.addOperand(Reg);
1324 Inst.addOperand(MCOperand::createReg(Hexagon::R0));
1325 Inst.addOperand(S27);
1326 break;
1327 }
1328 case Hexagon::M4_mpyrr_addr:
1329 case Hexagon::S4_addi_asl_ri:
1330 case Hexagon::S4_addi_lsr_ri:
1331 case Hexagon::S4_andi_asl_ri:
1332 case Hexagon::S4_andi_lsr_ri:
1333 case Hexagon::S4_ori_asl_ri:
1334 case Hexagon::S4_ori_lsr_ri:
1335 case Hexagon::S4_or_andix:
1336 case Hexagon::S4_subi_asl_ri:
1337 case Hexagon::S4_subi_lsr_ri: {
1338 MCOperand &Ry = Inst.getOperand(0);
1339 MCOperand &src = Inst.getOperand(2);
1340 if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg()))
1341 return Match_InvalidOperand;
1342 break;
1343 }
1344
1345 case Hexagon::C2_cmpgei: {
1346 MCOperand &MO = Inst.getOperand(2);
1347 MO.setExpr(HexagonMCExpr::create(
1348 MCBinaryExpr::createSub(MO.getExpr(),
1349 MCConstantExpr::create(1, Context), Context),
1350 Context));
1351 Inst.setOpcode(Hexagon::C2_cmpgti);
1352 break;
1353 }
1354
1355 case Hexagon::C2_cmpgeui: {
1356 MCOperand &MO = Inst.getOperand(2);
1357 int64_t Value;
1358 bool Success = MO.getExpr()->evaluateAsAbsolute(Value);
1359 (void)Success;
1360 assert(Success && "Assured by matcher")((Success && "Assured by matcher") ? static_cast<void
> (0) : __assert_fail ("Success && \"Assured by matcher\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 1360, __PRETTY_FUNCTION__))
;
1361 if (Value == 0) {
1362 MCInst TmpInst;
1363 MCOperand &Pd = Inst.getOperand(0);
1364 MCOperand &Rt = Inst.getOperand(1);
1365 TmpInst.setOpcode(Hexagon::C2_cmpeq);
1366 TmpInst.addOperand(Pd);
1367 TmpInst.addOperand(Rt);
1368 TmpInst.addOperand(Rt);
1369 Inst = TmpInst;
1370 } else {
1371 MO.setExpr(HexagonMCExpr::create(
1372 MCBinaryExpr::createSub(MO.getExpr(),
1373 MCConstantExpr::create(1, Context), Context),
1374 Context));
1375 Inst.setOpcode(Hexagon::C2_cmpgtui);
1376 }
1377 break;
1378 }
1379
1380 // Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
1381 case Hexagon::A2_tfrp: {
1382 MCOperand &MO = Inst.getOperand(1);
1383 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1384 std::string R1 = r + utostr(RegPairNum + 1);
1385 StringRef Reg1(R1);
1386 MO.setReg(matchRegister(Reg1));
1387 // Add a new operand for the second register in the pair.
1388 std::string R2 = r + utostr(RegPairNum);
1389 StringRef Reg2(R2);
1390 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1391 Inst.setOpcode(Hexagon::A2_combinew);
1392 break;
1393 }
1394
1395 case Hexagon::A2_tfrpt:
1396 case Hexagon::A2_tfrpf: {
1397 MCOperand &MO = Inst.getOperand(2);
1398 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1399 std::string R1 = r + utostr(RegPairNum + 1);
1400 StringRef Reg1(R1);
1401 MO.setReg(matchRegister(Reg1));
1402 // Add a new operand for the second register in the pair.
1403 std::string R2 = r + utostr(RegPairNum);
1404 StringRef Reg2(R2);
1405 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1406 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
1407 ? Hexagon::C2_ccombinewt
1408 : Hexagon::C2_ccombinewf);
1409 break;
1410 }
1411 case Hexagon::A2_tfrptnew:
1412 case Hexagon::A2_tfrpfnew: {
1413 MCOperand &MO = Inst.getOperand(2);
1414 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1415 std::string R1 = r + utostr(RegPairNum + 1);
1416 StringRef Reg1(R1);
1417 MO.setReg(matchRegister(Reg1));
1418 // Add a new operand for the second register in the pair.
1419 std::string R2 = r + utostr(RegPairNum);
1420 StringRef Reg2(R2);
1421 Inst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1422 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
1423 ? Hexagon::C2_ccombinewnewt
1424 : Hexagon::C2_ccombinewnewf);
1425 break;
1426 }
1427
1428 // Translate a "$Vdd = $Vss" to "$Vdd = vcombine($Vs, $Vt)"
1429 case Hexagon::V6_vassignp: {
1430 MCOperand &MO = Inst.getOperand(1);
1431 unsigned int RegPairNum = RI->getEncodingValue(MO.getReg());
1432 std::string R1 = v + utostr(RegPairNum + 1);
1433 MO.setReg(MatchRegisterName(R1));
1434 // Add a new operand for the second register in the pair.
1435 std::string R2 = v + utostr(RegPairNum);
1436 Inst.addOperand(MCOperand::createReg(MatchRegisterName(R2)));
1437 Inst.setOpcode(Hexagon::V6_vcombine);
1438 break;
1439 }
1440
1441 // Translate a "$Rx = CONST32(#imm)" to "$Rx = memw(gp+#LABEL) "
1442 case Hexagon::CONST32:
1443 is32bit = true;
1444 LLVM_FALLTHROUGH[[clang::fallthrough]];
1445 // Translate a "$Rx:y = CONST64(#imm)" to "$Rx:y = memd(gp+#LABEL) "
1446 case Hexagon::CONST64:
1447 // FIXME: need better way to detect AsmStreamer (upstream removed getKind())
1448 if (!Parser.getStreamer().hasRawTextSupport()) {
1449 MCELFStreamer *MES = static_cast<MCELFStreamer *>(&Parser.getStreamer());
1450 MCOperand &MO_1 = Inst.getOperand(1);
1451 MCOperand &MO_0 = Inst.getOperand(0);
1452
1453 // push section onto section stack
1454 MES->PushSection();
1455
1456 std::string myCharStr;
1457 MCSectionELF *mySection;
1458
1459 // check if this as an immediate or a symbol
1460 int64_t Value;
1461 bool Absolute = MO_1.getExpr()->evaluateAsAbsolute(Value);
1462 if (Absolute) {
1463 // Create a new section - one for each constant
1464 // Some or all of the zeros are replaced with the given immediate.
1465 if (is32bit) {
1466 std::string myImmStr = utohexstr(static_cast<uint32_t>(Value));
1467 myCharStr = StringRef(".gnu.linkonce.l4.CONST_00000000")
1468 .drop_back(myImmStr.size())
1469 .str() +
1470 myImmStr;
1471 } else {
1472 std::string myImmStr = utohexstr(Value);
1473 myCharStr = StringRef(".gnu.linkonce.l8.CONST_0000000000000000")
1474 .drop_back(myImmStr.size())
1475 .str() +
1476 myImmStr;
1477 }
1478
1479 mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1480 ELF::SHF_ALLOC | ELF::SHF_WRITE);
1481 } else if (MO_1.isExpr()) {
1482 // .lita - for expressions
1483 myCharStr = ".lita";
1484 mySection = getContext().getELFSection(myCharStr, ELF::SHT_PROGBITS,
1485 ELF::SHF_ALLOC | ELF::SHF_WRITE);
1486 } else
1487 llvm_unreachable("unexpected type of machine operand!")::llvm::llvm_unreachable_internal("unexpected type of machine operand!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 1487)
;
1488
1489 MES->SwitchSection(mySection);
1490 unsigned byteSize = is32bit ? 4 : 8;
1491 getStreamer().EmitCodeAlignment(byteSize, byteSize);
1492
1493 MCSymbol *Sym;
1494
1495 // for symbols, get rid of prepended ".gnu.linkonce.lx."
1496
1497 // emit symbol if needed
1498 if (Absolute) {
1499 Sym = getContext().getOrCreateSymbol(StringRef(myCharStr.c_str() + 16));
1500 if (Sym->isUndefined()) {
1501 getStreamer().EmitLabel(Sym);
1502 getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
1503 getStreamer().EmitIntValue(Value, byteSize);
1504 }
1505 } else if (MO_1.isExpr()) {
1506 const char *StringStart = nullptr;
1507 const char *StringEnd = nullptr;
1508 if (*Operands[4]->getStartLoc().getPointer() == '#') {
1509 StringStart = Operands[5]->getStartLoc().getPointer();
1510 StringEnd = Operands[6]->getStartLoc().getPointer();
1511 } else { // no pound
1512 StringStart = Operands[4]->getStartLoc().getPointer();
1513 StringEnd = Operands[5]->getStartLoc().getPointer();
1514 }
1515
1516 unsigned size = StringEnd - StringStart;
1517 std::string DotConst = ".CONST_";
1518 Sym = getContext().getOrCreateSymbol(DotConst +
1519 StringRef(StringStart, size));
1520
1521 if (Sym->isUndefined()) {
1522 // case where symbol is not yet defined: emit symbol
1523 getStreamer().EmitLabel(Sym);
1524 getStreamer().EmitSymbolAttribute(Sym, MCSA_Local);
1525 getStreamer().EmitValue(MO_1.getExpr(), 4);
1526 }
1527 } else
1528 llvm_unreachable("unexpected type of machine operand!")::llvm::llvm_unreachable_internal("unexpected type of machine operand!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 1528)
;
1529
1530 MES->PopSection();
1531
1532 if (Sym) {
1533 MCInst TmpInst;
1534 if (is32bit) // 32 bit
1535 TmpInst.setOpcode(Hexagon::L2_loadrigp);
1536 else // 64 bit
1537 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
1538
1539 TmpInst.addOperand(MO_0);
1540 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
1541 MCSymbolRefExpr::create(Sym, getContext()), getContext())));
1542 Inst = TmpInst;
1543 }
1544 }
1545 break;
1546
1547 // Translate a "$Rdd = #-imm" to "$Rdd = combine(#[-1,0], #-imm)"
1548 case Hexagon::A2_tfrpi: {
1549 MCOperand &Rdd = Inst.getOperand(0);
1550 MCOperand &MO = Inst.getOperand(1);
1551 int64_t Value;
1552 int sVal = (MO.getExpr()->evaluateAsAbsolute(Value) && Value < 0) ? -1 : 0;
1553 MCOperand imm(MCOperand::createExpr(
1554 HexagonMCExpr::create(MCConstantExpr::create(sVal, Context), Context)));
1555 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, imm, MO);
1556 break;
1557 }
1558
1559 // Translate a "$Rdd = [#]#imm" to "$Rdd = combine(#, [#]#imm)"
1560 case Hexagon::TFRI64_V4: {
1561 MCOperand &Rdd = Inst.getOperand(0);
1562 MCOperand &MO = Inst.getOperand(1);
1563 int64_t Value;
1564 if (MO.getExpr()->evaluateAsAbsolute(Value)) {
1565 int s8 = Hi_32(Value);
1566 if (!isInt<8>(s8))
1567 OutOfRange(IDLoc, s8, -128);
1568 MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1569 MCConstantExpr::create(s8, Context), Context))); // upper 32
1570 auto Expr = HexagonMCExpr::create(
1571 MCConstantExpr::create(Lo_32(Value), Context), Context);
1572 HexagonMCInstrInfo::setMustExtend(
1573 *Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
1574 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
1575 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
1576 } else {
1577 MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
1578 MCConstantExpr::create(0, Context), Context))); // upper 32
1579 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, MO);
1580 }
1581 break;
1582 }
1583
1584 // Handle $Rdd = combine(##imm, #imm)"
1585 case Hexagon::TFRI64_V2_ext: {
1586 MCOperand &Rdd = Inst.getOperand(0);
1587 MCOperand &MO1 = Inst.getOperand(1);
1588 MCOperand &MO2 = Inst.getOperand(2);
1589 int64_t Value;
1590 if (MO2.getExpr()->evaluateAsAbsolute(Value)) {
1591 int s8 = Value;
1592 if (s8 < -128 || s8 > 127)
1593 OutOfRange(IDLoc, s8, -128);
1594 }
1595 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2);
1596 break;
1597 }
1598
1599 // Handle $Rdd = combine(#imm, ##imm)"
1600 case Hexagon::A4_combineii: {
1601 MCOperand &Rdd = Inst.getOperand(0);
1602 MCOperand &MO1 = Inst.getOperand(1);
1603 int64_t Value;
1604 if (MO1.getExpr()->evaluateAsAbsolute(Value)) {
1605 int s8 = Value;
1606 if (s8 < -128 || s8 > 127)
1607 OutOfRange(IDLoc, s8, -128);
1608 }
1609 MCOperand &MO2 = Inst.getOperand(2);
1610 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2);
1611 break;
1612 }
1613
1614 case Hexagon::S2_tableidxb_goodsyntax:
1615 Inst.setOpcode(Hexagon::S2_tableidxb);
1616 break;
1617
1618 case Hexagon::S2_tableidxh_goodsyntax: {
1619 MCInst TmpInst;
1620 MCOperand &Rx = Inst.getOperand(0);
1621 MCOperand &Rs = Inst.getOperand(2);
1622 MCOperand &Imm4 = Inst.getOperand(3);
1623 MCOperand &Imm6 = Inst.getOperand(4);
1624 Imm6.setExpr(HexagonMCExpr::create(
1625 MCBinaryExpr::createSub(Imm6.getExpr(),
1626 MCConstantExpr::create(1, Context), Context),
1627 Context));
1628 TmpInst.setOpcode(Hexagon::S2_tableidxh);
1629 TmpInst.addOperand(Rx);
1630 TmpInst.addOperand(Rx);
1631 TmpInst.addOperand(Rs);
1632 TmpInst.addOperand(Imm4);
1633 TmpInst.addOperand(Imm6);
1634 Inst = TmpInst;
1635 break;
1636 }
1637
1638 case Hexagon::S2_tableidxw_goodsyntax: {
1639 MCInst TmpInst;
1640 MCOperand &Rx = Inst.getOperand(0);
1641 MCOperand &Rs = Inst.getOperand(2);
1642 MCOperand &Imm4 = Inst.getOperand(3);
1643 MCOperand &Imm6 = Inst.getOperand(4);
1644 Imm6.setExpr(HexagonMCExpr::create(
1645 MCBinaryExpr::createSub(Imm6.getExpr(),
1646 MCConstantExpr::create(2, Context), Context),
1647 Context));
1648 TmpInst.setOpcode(Hexagon::S2_tableidxw);
1649 TmpInst.addOperand(Rx);
1650 TmpInst.addOperand(Rx);
1651 TmpInst.addOperand(Rs);
1652 TmpInst.addOperand(Imm4);
1653 TmpInst.addOperand(Imm6);
1654 Inst = TmpInst;
1655 break;
1656 }
1657
1658 case Hexagon::S2_tableidxd_goodsyntax: {
1659 MCInst TmpInst;
1660 MCOperand &Rx = Inst.getOperand(0);
1661 MCOperand &Rs = Inst.getOperand(2);
1662 MCOperand &Imm4 = Inst.getOperand(3);
1663 MCOperand &Imm6 = Inst.getOperand(4);
1664 Imm6.setExpr(HexagonMCExpr::create(
1665 MCBinaryExpr::createSub(Imm6.getExpr(),
1666 MCConstantExpr::create(3, Context), Context),
1667 Context));
1668 TmpInst.setOpcode(Hexagon::S2_tableidxd);
1669 TmpInst.addOperand(Rx);
1670 TmpInst.addOperand(Rx);
1671 TmpInst.addOperand(Rs);
1672 TmpInst.addOperand(Imm4);
1673 TmpInst.addOperand(Imm6);
1674 Inst = TmpInst;
1675 break;
1676 }
1677
1678 case Hexagon::M2_mpyui:
1679 Inst.setOpcode(Hexagon::M2_mpyi);
1680 break;
1681 case Hexagon::M2_mpysmi: {
1682 MCInst TmpInst;
1683 MCOperand &Rd = Inst.getOperand(0);
1684 MCOperand &Rs = Inst.getOperand(1);
1685 MCOperand &Imm = Inst.getOperand(2);
1686 int64_t Value;
1687 MCExpr const &Expr = *Imm.getExpr();
1688 bool Absolute = Expr.evaluateAsAbsolute(Value);
1689 assert(Absolute)((Absolute) ? static_cast<void> (0) : __assert_fail ("Absolute"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 1689, __PRETTY_FUNCTION__))
;
1690 (void)Absolute;
1691 if (!HexagonMCInstrInfo::mustExtend(Expr) &&
1692 ((Value <= -256) || Value >= 256))
1693 return Match_InvalidOperand;
1694 if (Value < 0 && Value > -256) {
1695 Imm.setExpr(HexagonMCExpr::create(
1696 MCConstantExpr::create(Value * -1, Context), Context));
1697 TmpInst.setOpcode(Hexagon::M2_mpysin);
1698 } else
1699 TmpInst.setOpcode(Hexagon::M2_mpysip);
1700 TmpInst.addOperand(Rd);
1701 TmpInst.addOperand(Rs);
1702 TmpInst.addOperand(Imm);
1703 Inst = TmpInst;
1704 break;
1705 }
1706
1707 case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
1708 MCOperand &Imm = Inst.getOperand(2);
1709 MCInst TmpInst;
1710 int64_t Value;
1711 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1712 assert(Absolute)((Absolute) ? static_cast<void> (0) : __assert_fail ("Absolute"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 1712, __PRETTY_FUNCTION__))
;
1713 (void)Absolute;
1714 if (Value == 0) { // convert to $Rd = $Rs
1715 TmpInst.setOpcode(Hexagon::A2_tfr);
1716 MCOperand &Rd = Inst.getOperand(0);
1717 MCOperand &Rs = Inst.getOperand(1);
1718 TmpInst.addOperand(Rd);
1719 TmpInst.addOperand(Rs);
1720 } else {
1721 Imm.setExpr(HexagonMCExpr::create(
1722 MCBinaryExpr::createSub(Imm.getExpr(),
1723 MCConstantExpr::create(1, Context), Context),
1724 Context));
1725 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
1726 MCOperand &Rd = Inst.getOperand(0);
1727 MCOperand &Rs = Inst.getOperand(1);
1728 TmpInst.addOperand(Rd);
1729 TmpInst.addOperand(Rs);
1730 TmpInst.addOperand(Imm);
1731 }
1732 Inst = TmpInst;
1733 break;
1734 }
1735
1736 case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
1737 MCOperand &Rdd = Inst.getOperand(0);
1738 MCOperand &Rss = Inst.getOperand(1);
1739 MCOperand &Imm = Inst.getOperand(2);
1740 int64_t Value;
1741 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1742 assert(Absolute)((Absolute) ? static_cast<void> (0) : __assert_fail ("Absolute"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 1742, __PRETTY_FUNCTION__))
;
1743 (void)Absolute;
1744 if (Value == 0) { // convert to $Rdd = combine ($Rs[0], $Rs[1])
1745 MCInst TmpInst;
1746 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1747 std::string R1 = r + utostr(RegPairNum + 1);
1748 StringRef Reg1(R1);
1749 Rss.setReg(matchRegister(Reg1));
1750 // Add a new operand for the second register in the pair.
1751 std::string R2 = r + utostr(RegPairNum);
1752 StringRef Reg2(R2);
1753 TmpInst.setOpcode(Hexagon::A2_combinew);
1754 TmpInst.addOperand(Rdd);
1755 TmpInst.addOperand(Rss);
1756 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1757 Inst = TmpInst;
1758 } else {
1759 Imm.setExpr(HexagonMCExpr::create(
1760 MCBinaryExpr::createSub(Imm.getExpr(),
1761 MCConstantExpr::create(1, Context), Context),
1762 Context));
1763 Inst.setOpcode(Hexagon::S2_asr_i_p_rnd);
1764 }
1765 break;
1766 }
1767
1768 case Hexagon::A4_boundscheck: {
1769 MCOperand &Rs = Inst.getOperand(1);
1770 unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1771 if (RegNum & 1) { // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
1772 Inst.setOpcode(Hexagon::A4_boundscheck_hi);
1773 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1774 StringRef RegPair = Name;
1775 Rs.setReg(matchRegister(RegPair));
1776 } else { // raw:lo
1777 Inst.setOpcode(Hexagon::A4_boundscheck_lo);
1778 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1779 StringRef RegPair = Name;
1780 Rs.setReg(matchRegister(RegPair));
1781 }
1782 break;
1783 }
1784
1785 case Hexagon::A2_addsp: {
1786 MCOperand &Rs = Inst.getOperand(1);
1787 unsigned int RegNum = RI->getEncodingValue(Rs.getReg());
1788 if (RegNum & 1) { // Odd mapped to raw:hi
1789 Inst.setOpcode(Hexagon::A2_addsph);
1790 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1791 StringRef RegPair = Name;
1792 Rs.setReg(matchRegister(RegPair));
1793 } else { // Even mapped raw:lo
1794 Inst.setOpcode(Hexagon::A2_addspl);
1795 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1796 StringRef RegPair = Name;
1797 Rs.setReg(matchRegister(RegPair));
1798 }
1799 break;
1800 }
1801
1802 case Hexagon::M2_vrcmpys_s1: {
1803 MCOperand &Rt = Inst.getOperand(2);
1804 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
1805 if (RegNum & 1) { // Odd mapped to sat:raw:hi
1806 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
1807 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1808 StringRef RegPair = Name;
1809 Rt.setReg(matchRegister(RegPair));
1810 } else { // Even mapped sat:raw:lo
1811 Inst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
1812 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1813 StringRef RegPair = Name;
1814 Rt.setReg(matchRegister(RegPair));
1815 }
1816 break;
1817 }
1818
1819 case Hexagon::M2_vrcmpys_acc_s1: {
1820 MCInst TmpInst;
1821 MCOperand &Rxx = Inst.getOperand(0);
1822 MCOperand &Rss = Inst.getOperand(2);
1823 MCOperand &Rt = Inst.getOperand(3);
1824 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
1825 if (RegNum & 1) { // Odd mapped to sat:raw:hi
1826 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
1827 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1828 StringRef RegPair = Name;
1829 Rt.setReg(matchRegister(RegPair));
1830 } else { // Even mapped sat:raw:lo
1831 TmpInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
1832 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1833 StringRef RegPair = Name;
1834 Rt.setReg(matchRegister(RegPair));
1835 }
1836 // Registers are in different positions
1837 TmpInst.addOperand(Rxx);
1838 TmpInst.addOperand(Rxx);
1839 TmpInst.addOperand(Rss);
1840 TmpInst.addOperand(Rt);
1841 Inst = TmpInst;
1842 break;
1843 }
1844
1845 case Hexagon::M2_vrcmpys_s1rp: {
1846 MCOperand &Rt = Inst.getOperand(2);
1847 unsigned int RegNum = RI->getEncodingValue(Rt.getReg());
1848 if (RegNum & 1) { // Odd mapped to rnd:sat:raw:hi
1849 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
1850 std::string Name = r + utostr(RegNum) + Colon + utostr(RegNum - 1);
1851 StringRef RegPair = Name;
1852 Rt.setReg(matchRegister(RegPair));
1853 } else { // Even mapped rnd:sat:raw:lo
1854 Inst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
1855 std::string Name = r + utostr(RegNum + 1) + Colon + utostr(RegNum);
1856 StringRef RegPair = Name;
1857 Rt.setReg(matchRegister(RegPair));
1858 }
1859 break;
1860 }
1861
1862 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
1863 MCOperand &Imm = Inst.getOperand(2);
1864 int64_t Value;
1865 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1866 assert(Absolute)((Absolute) ? static_cast<void> (0) : __assert_fail ("Absolute"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 1866, __PRETTY_FUNCTION__))
;
1867 (void)Absolute;
1868 if (Value == 0)
1869 Inst.setOpcode(Hexagon::S2_vsathub);
1870 else {
1871 Imm.setExpr(HexagonMCExpr::create(
1872 MCBinaryExpr::createSub(Imm.getExpr(),
1873 MCConstantExpr::create(1, Context), Context),
1874 Context));
1875 Inst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
1876 }
1877 break;
1878 }
1879
1880 case Hexagon::S5_vasrhrnd_goodsyntax: {
1881 MCOperand &Rdd = Inst.getOperand(0);
1882 MCOperand &Rss = Inst.getOperand(1);
1883 MCOperand &Imm = Inst.getOperand(2);
1884 int64_t Value;
1885 bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
1886 assert(Absolute)((Absolute) ? static_cast<void> (0) : __assert_fail ("Absolute"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp"
, 1886, __PRETTY_FUNCTION__))
;
1887 (void)Absolute;
1888 if (Value == 0) {
1889 MCInst TmpInst;
1890 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg());
1891 std::string R1 = r + utostr(RegPairNum + 1);
1892 StringRef Reg1(R1);
1893 Rss.setReg(matchRegister(Reg1));
1894 // Add a new operand for the second register in the pair.
1895 std::string R2 = r + utostr(RegPairNum);
1896 StringRef Reg2(R2);
1897 TmpInst.setOpcode(Hexagon::A2_combinew);
1898 TmpInst.addOperand(Rdd);
1899 TmpInst.addOperand(Rss);
1900 TmpInst.addOperand(MCOperand::createReg(matchRegister(Reg2)));
1901 Inst = TmpInst;
1902 } else {
1903 Imm.setExpr(HexagonMCExpr::create(
1904 MCBinaryExpr::createSub(Imm.getExpr(),
1905 MCConstantExpr::create(1, Context), Context),
1906 Context));
1907 Inst.setOpcode(Hexagon::S5_vasrhrnd);
1908 }
1909 break;
1910 }
1911
1912 case Hexagon::A2_not: {
1913 MCInst TmpInst;
1914 MCOperand &Rd = Inst.getOperand(0);
1915 MCOperand &Rs = Inst.getOperand(1);
1916 TmpInst.setOpcode(Hexagon::A2_subri);
1917 TmpInst.addOperand(Rd);
1918 TmpInst.addOperand(MCOperand::createExpr(
1919 HexagonMCExpr::create(MCConstantExpr::create(-1, Context), Context)));
1920 TmpInst.addOperand(Rs);
1921 Inst = TmpInst;
1922 break;
1923 }
1924 case Hexagon::PS_loadrubabs:
1925 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1926 Inst.setOpcode(Hexagon::L2_loadrubgp);
1927 break;
1928 case Hexagon::PS_loadrbabs:
1929 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1930 Inst.setOpcode(Hexagon::L2_loadrbgp);
1931 break;
1932 case Hexagon::PS_loadruhabs:
1933 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1934 Inst.setOpcode(Hexagon::L2_loadruhgp);
1935 break;
1936 case Hexagon::PS_loadrhabs:
1937 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1938 Inst.setOpcode(Hexagon::L2_loadrhgp);
1939 break;
1940 case Hexagon::PS_loadriabs:
1941 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1942 Inst.setOpcode(Hexagon::L2_loadrigp);
1943 break;
1944 case Hexagon::PS_loadrdabs:
1945 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr()))
1946 Inst.setOpcode(Hexagon::L2_loadrdgp);
1947 break;
1948 case Hexagon::PS_storerbabs:
1949 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1950 Inst.setOpcode(Hexagon::S2_storerbgp);
1951 break;
1952 case Hexagon::PS_storerhabs:
1953 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1954 Inst.setOpcode(Hexagon::S2_storerhgp);
1955 break;
1956 case Hexagon::PS_storerfabs:
1957 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1958 Inst.setOpcode(Hexagon::S2_storerfgp);
1959 break;
1960 case Hexagon::PS_storeriabs:
1961 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1962 Inst.setOpcode(Hexagon::S2_storerigp);
1963 break;
1964 case Hexagon::PS_storerdabs:
1965 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1966 Inst.setOpcode(Hexagon::S2_storerdgp);
1967 break;
1968 case Hexagon::PS_storerbnewabs:
1969 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1970 Inst.setOpcode(Hexagon::S2_storerbnewgp);
1971 break;
1972 case Hexagon::PS_storerhnewabs:
1973 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1974 Inst.setOpcode(Hexagon::S2_storerhnewgp);
1975 break;
1976 case Hexagon::PS_storerinewabs:
1977 if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr()))
1978 Inst.setOpcode(Hexagon::S2_storerinewgp);
1979 break;
1980 case Hexagon::A2_zxtb: {
1981 Inst.setOpcode(Hexagon::A2_andir);
1982 Inst.addOperand(
1983 MCOperand::createExpr(MCConstantExpr::create(255, Context)));
1984 break;
1985 }
1986 } // switch
1987
1988 return Match_Success;
1989}
1990
1991unsigned HexagonAsmParser::matchRegister(StringRef Name) {
1992 if (unsigned Reg = MatchRegisterName(Name))
1993 return Reg;
1994 return MatchRegisterAltName(Name);
1995}