Bug Summary

File:llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
Warning:line 786, column 24
Division by zero

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name HexagonHardwareLoops.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-11/lib/clang/11.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/include -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-11/lib/clang/11.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/Target/Hexagon -fdebug-prefix-map=/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347=. -ferror-limit 19 -fmessage-length 0 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-03-09-184146-41876-1 -x c++ /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

1//===- HexagonHardwareLoops.cpp - Identify and generate hardware loops ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass identifies loops where we can generate the Hexagon hardware
10// loop instruction. The hardware loop can perform loop branches with a
11// zero-cycle overhead.
12//
13// The pattern that defines the induction variable can changed depending on
14// prior optimizations. For example, the IndVarSimplify phase run by 'opt'
15// normalizes induction variables, and the Loop Strength Reduction pass
16// run by 'llc' may also make changes to the induction variable.
17// The pattern detected by this phase is due to running Strength Reduction.
18//
19// Criteria for hardware loops:
20// - Countable loops (w/ ind. var for a trip count)
21// - Assumes loops are normalized by IndVarSimplify
22// - Try inner-most loops first
23// - No function calls in loops.
24//
25//===----------------------------------------------------------------------===//
26
27#include "HexagonInstrInfo.h"
28#include "HexagonSubtarget.h"
29#include "llvm/ADT/ArrayRef.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallSet.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/ADT/StringRef.h"
35#include "llvm/CodeGen/MachineBasicBlock.h"
36#include "llvm/CodeGen/MachineDominators.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineFunctionPass.h"
39#include "llvm/CodeGen/MachineInstr.h"
40#include "llvm/CodeGen/MachineInstrBuilder.h"
41#include "llvm/CodeGen/MachineLoopInfo.h"
42#include "llvm/CodeGen/MachineOperand.h"
43#include "llvm/CodeGen/MachineRegisterInfo.h"
44#include "llvm/CodeGen/TargetRegisterInfo.h"
45#include "llvm/IR/Constants.h"
46#include "llvm/IR/DebugLoc.h"
47#include "llvm/InitializePasses.h"
48#include "llvm/Pass.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Debug.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/MathExtras.h"
53#include "llvm/Support/raw_ostream.h"
54#include <cassert>
55#include <cstdint>
56#include <cstdlib>
57#include <iterator>
58#include <map>
59#include <set>
60#include <string>
61#include <utility>
62#include <vector>
63
64using namespace llvm;
65
66#define DEBUG_TYPE"hwloops" "hwloops"
67
68#ifndef NDEBUG
69static cl::opt<int> HWLoopLimit("hexagon-max-hwloop", cl::Hidden, cl::init(-1));
70
71// Option to create preheader only for a specific function.
72static cl::opt<std::string> PHFn("hexagon-hwloop-phfn", cl::Hidden,
73 cl::init(""));
74#endif
75
76// Option to create a preheader if one doesn't exist.
77static cl::opt<bool> HWCreatePreheader("hexagon-hwloop-preheader",
78 cl::Hidden, cl::init(true),
79 cl::desc("Add a preheader to a hardware loop if one doesn't exist"));
80
81// Turn it off by default. If a preheader block is not created here, the
82// software pipeliner may be unable to find a block suitable to serve as
83// a preheader. In that case SWP will not run.
84static cl::opt<bool> SpecPreheader("hwloop-spec-preheader", cl::init(false),
85 cl::Hidden, cl::ZeroOrMore, cl::desc("Allow speculation of preheader "
86 "instructions"));
87
88STATISTIC(NumHWLoops, "Number of loops converted to hardware loops")static llvm::Statistic NumHWLoops = {"hwloops", "NumHWLoops",
"Number of loops converted to hardware loops"}
;
89
90namespace llvm {
91
92 FunctionPass *createHexagonHardwareLoops();
93 void initializeHexagonHardwareLoopsPass(PassRegistry&);
94
95} // end namespace llvm
96
97namespace {
98
99 class CountValue;
100
101 struct HexagonHardwareLoops : public MachineFunctionPass {
102 MachineLoopInfo *MLI;
103 MachineRegisterInfo *MRI;
104 MachineDominatorTree *MDT;
105 const HexagonInstrInfo *TII;
106 const HexagonRegisterInfo *TRI;
107#ifndef NDEBUG
108 static int Counter;
109#endif
110
111 public:
112 static char ID;
113
114 HexagonHardwareLoops() : MachineFunctionPass(ID) {}
115
116 bool runOnMachineFunction(MachineFunction &MF) override;
117
118 StringRef getPassName() const override { return "Hexagon Hardware Loops"; }
119
120 void getAnalysisUsage(AnalysisUsage &AU) const override {
121 AU.addRequired<MachineDominatorTree>();
122 AU.addRequired<MachineLoopInfo>();
123 MachineFunctionPass::getAnalysisUsage(AU);
124 }
125
126 private:
127 using LoopFeederMap = std::map<unsigned, MachineInstr *>;
128
129 /// Kinds of comparisons in the compare instructions.
130 struct Comparison {
131 enum Kind {
132 EQ = 0x01,
133 NE = 0x02,
134 L = 0x04,
135 G = 0x08,
136 U = 0x40,
137 LTs = L,
138 LEs = L | EQ,
139 GTs = G,
140 GEs = G | EQ,
141 LTu = L | U,
142 LEu = L | EQ | U,
143 GTu = G | U,
144 GEu = G | EQ | U
145 };
146
147 static Kind getSwappedComparison(Kind Cmp) {
148 assert ((!((Cmp & L) && (Cmp & G))) && "Malformed comparison operator")(((!((Cmp & L) && (Cmp & G))) && "Malformed comparison operator"
) ? static_cast<void> (0) : __assert_fail ("(!((Cmp & L) && (Cmp & G))) && \"Malformed comparison operator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 148, __PRETTY_FUNCTION__))
;
149 if ((Cmp & L) || (Cmp & G))
150 return (Kind)(Cmp ^ (L|G));
151 return Cmp;
152 }
153
154 static Kind getNegatedComparison(Kind Cmp) {
155 if ((Cmp & L) || (Cmp & G))
156 return (Kind)((Cmp ^ (L | G)) ^ EQ);
157 if ((Cmp & NE) || (Cmp & EQ))
158 return (Kind)(Cmp ^ (EQ | NE));
159 return (Kind)0;
160 }
161
162 static bool isSigned(Kind Cmp) {
163 return (Cmp & (L | G) && !(Cmp & U));
164 }
165
166 static bool isUnsigned(Kind Cmp) {
167 return (Cmp & U);
168 }
169 };
170
171 /// Find the register that contains the loop controlling
172 /// induction variable.
173 /// If successful, it will return true and set the \p Reg, \p IVBump
174 /// and \p IVOp arguments. Otherwise it will return false.
175 /// The returned induction register is the register R that follows the
176 /// following induction pattern:
177 /// loop:
178 /// R = phi ..., [ R.next, LatchBlock ]
179 /// R.next = R + #bump
180 /// if (R.next < #N) goto loop
181 /// IVBump is the immediate value added to R, and IVOp is the instruction
182 /// "R.next = R + #bump".
183 bool findInductionRegister(MachineLoop *L, unsigned &Reg,
184 int64_t &IVBump, MachineInstr *&IVOp) const;
185
186 /// Return the comparison kind for the specified opcode.
187 Comparison::Kind getComparisonKind(unsigned CondOpc,
188 MachineOperand *InitialValue,
189 const MachineOperand *Endvalue,
190 int64_t IVBump) const;
191
192 /// Analyze the statements in a loop to determine if the loop
193 /// has a computable trip count and, if so, return a value that represents
194 /// the trip count expression.
195 CountValue *getLoopTripCount(MachineLoop *L,
196 SmallVectorImpl<MachineInstr *> &OldInsts);
197
198 /// Return the expression that represents the number of times
199 /// a loop iterates. The function takes the operands that represent the
200 /// loop start value, loop end value, and induction value. Based upon
201 /// these operands, the function attempts to compute the trip count.
202 /// If the trip count is not directly available (as an immediate value,
203 /// or a register), the function will attempt to insert computation of it
204 /// to the loop's preheader.
205 CountValue *computeCount(MachineLoop *Loop, const MachineOperand *Start,
206 const MachineOperand *End, unsigned IVReg,
207 int64_t IVBump, Comparison::Kind Cmp) const;
208
209 /// Return true if the instruction is not valid within a hardware
210 /// loop.
211 bool isInvalidLoopOperation(const MachineInstr *MI,
212 bool IsInnerHWLoop) const;
213
214 /// Return true if the loop contains an instruction that inhibits
215 /// using the hardware loop.
216 bool containsInvalidInstruction(MachineLoop *L, bool IsInnerHWLoop) const;
217
218 /// Given a loop, check if we can convert it to a hardware loop.
219 /// If so, then perform the conversion and return true.
220 bool convertToHardwareLoop(MachineLoop *L, bool &L0used, bool &L1used);
221
222 /// Return true if the instruction is now dead.
223 bool isDead(const MachineInstr *MI,
224 SmallVectorImpl<MachineInstr *> &DeadPhis) const;
225
226 /// Remove the instruction if it is now dead.
227 void removeIfDead(MachineInstr *MI);
228
229 /// Make sure that the "bump" instruction executes before the
230 /// compare. We need that for the IV fixup, so that the compare
231 /// instruction would not use a bumped value that has not yet been
232 /// defined. If the instructions are out of order, try to reorder them.
233 bool orderBumpCompare(MachineInstr *BumpI, MachineInstr *CmpI);
234
235 /// Return true if MO and MI pair is visited only once. If visited
236 /// more than once, this indicates there is recursion. In such a case,
237 /// return false.
238 bool isLoopFeeder(MachineLoop *L, MachineBasicBlock *A, MachineInstr *MI,
239 const MachineOperand *MO,
240 LoopFeederMap &LoopFeederPhi) const;
241
242 /// Return true if the Phi may generate a value that may underflow,
243 /// or may wrap.
244 bool phiMayWrapOrUnderflow(MachineInstr *Phi, const MachineOperand *EndVal,
245 MachineBasicBlock *MBB, MachineLoop *L,
246 LoopFeederMap &LoopFeederPhi) const;
247
248 /// Return true if the induction variable may underflow an unsigned
249 /// value in the first iteration.
250 bool loopCountMayWrapOrUnderFlow(const MachineOperand *InitVal,
251 const MachineOperand *EndVal,
252 MachineBasicBlock *MBB, MachineLoop *L,
253 LoopFeederMap &LoopFeederPhi) const;
254
255 /// Check if the given operand has a compile-time known constant
256 /// value. Return true if yes, and false otherwise. When returning true, set
257 /// Val to the corresponding constant value.
258 bool checkForImmediate(const MachineOperand &MO, int64_t &Val) const;
259
260 /// Check if the operand has a compile-time known constant value.
261 bool isImmediate(const MachineOperand &MO) const {
262 int64_t V;
263 return checkForImmediate(MO, V);
264 }
265
266 /// Return the immediate for the specified operand.
267 int64_t getImmediate(const MachineOperand &MO) const {
268 int64_t V;
269 if (!checkForImmediate(MO, V))
270 llvm_unreachable("Invalid operand")::llvm::llvm_unreachable_internal("Invalid operand", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 270)
;
271 return V;
272 }
273
274 /// Reset the given machine operand to now refer to a new immediate
275 /// value. Assumes that the operand was already referencing an immediate
276 /// value, either directly, or via a register.
277 void setImmediate(MachineOperand &MO, int64_t Val);
278
279 /// Fix the data flow of the induction variable.
280 /// The desired flow is: phi ---> bump -+-> comparison-in-latch.
281 /// |
282 /// +-> back to phi
283 /// where "bump" is the increment of the induction variable:
284 /// iv = iv + #const.
285 /// Due to some prior code transformations, the actual flow may look
286 /// like this:
287 /// phi -+-> bump ---> back to phi
288 /// |
289 /// +-> comparison-in-latch (against upper_bound-bump),
290 /// i.e. the comparison that controls the loop execution may be using
291 /// the value of the induction variable from before the increment.
292 ///
293 /// Return true if the loop's flow is the desired one (i.e. it's
294 /// either been fixed, or no fixing was necessary).
295 /// Otherwise, return false. This can happen if the induction variable
296 /// couldn't be identified, or if the value in the latch's comparison
297 /// cannot be adjusted to reflect the post-bump value.
298 bool fixupInductionVariable(MachineLoop *L);
299
300 /// Given a loop, if it does not have a preheader, create one.
301 /// Return the block that is the preheader.
302 MachineBasicBlock *createPreheaderForLoop(MachineLoop *L);
303 };
304
305 char HexagonHardwareLoops::ID = 0;
306#ifndef NDEBUG
307 int HexagonHardwareLoops::Counter = 0;
308#endif
309
310 /// Abstraction for a trip count of a loop. A smaller version
311 /// of the MachineOperand class without the concerns of changing the
312 /// operand representation.
313 class CountValue {
314 public:
315 enum CountValueType {
316 CV_Register,
317 CV_Immediate
318 };
319
320 private:
321 CountValueType Kind;
322 union Values {
323 struct {
324 unsigned Reg;
325 unsigned Sub;
326 } R;
327 unsigned ImmVal;
328 } Contents;
329
330 public:
331 explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) {
332 Kind = t;
333 if (Kind == CV_Register) {
334 Contents.R.Reg = v;
335 Contents.R.Sub = u;
336 } else {
337 Contents.ImmVal = v;
338 }
339 }
340
341 bool isReg() const { return Kind == CV_Register; }
342 bool isImm() const { return Kind == CV_Immediate; }
343
344 unsigned getReg() const {
345 assert(isReg() && "Wrong CountValue accessor")((isReg() && "Wrong CountValue accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong CountValue accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 345, __PRETTY_FUNCTION__))
;
346 return Contents.R.Reg;
347 }
348
349 unsigned getSubReg() const {
350 assert(isReg() && "Wrong CountValue accessor")((isReg() && "Wrong CountValue accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong CountValue accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 350, __PRETTY_FUNCTION__))
;
351 return Contents.R.Sub;
352 }
353
354 unsigned getImm() const {
355 assert(isImm() && "Wrong CountValue accessor")((isImm() && "Wrong CountValue accessor") ? static_cast
<void> (0) : __assert_fail ("isImm() && \"Wrong CountValue accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 355, __PRETTY_FUNCTION__))
;
356 return Contents.ImmVal;
357 }
358
359 void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {
360 if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }
361 if (isImm()) { OS << Contents.ImmVal; }
362 }
363 };
364
365} // end anonymous namespace
366
367INITIALIZE_PASS_BEGIN(HexagonHardwareLoops, "hwloops",static void *initializeHexagonHardwareLoopsPassOnce(PassRegistry
&Registry) {
368 "Hexagon Hardware Loops", false, false)static void *initializeHexagonHardwareLoopsPassOnce(PassRegistry
&Registry) {
369INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)initializeMachineDominatorTreePass(Registry);
370INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)initializeMachineLoopInfoPass(Registry);
371INITIALIZE_PASS_END(HexagonHardwareLoops, "hwloops",PassInfo *PI = new PassInfo( "Hexagon Hardware Loops", "hwloops"
, &HexagonHardwareLoops::ID, PassInfo::NormalCtor_t(callDefaultCtor
<HexagonHardwareLoops>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeHexagonHardwareLoopsPassFlag
; void llvm::initializeHexagonHardwareLoopsPass(PassRegistry &
Registry) { llvm::call_once(InitializeHexagonHardwareLoopsPassFlag
, initializeHexagonHardwareLoopsPassOnce, std::ref(Registry))
; }
372 "Hexagon Hardware Loops", false, false)PassInfo *PI = new PassInfo( "Hexagon Hardware Loops", "hwloops"
, &HexagonHardwareLoops::ID, PassInfo::NormalCtor_t(callDefaultCtor
<HexagonHardwareLoops>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeHexagonHardwareLoopsPassFlag
; void llvm::initializeHexagonHardwareLoopsPass(PassRegistry &
Registry) { llvm::call_once(InitializeHexagonHardwareLoopsPassFlag
, initializeHexagonHardwareLoopsPassOnce, std::ref(Registry))
; }
373
374FunctionPass *llvm::createHexagonHardwareLoops() {
375 return new HexagonHardwareLoops();
376}
377
378bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) {
379 LLVM_DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "********* Hexagon Hardware Loops *********\n"
; } } while (false)
;
380 if (skipFunction(MF.getFunction()))
381 return false;
382
383 bool Changed = false;
384
385 MLI = &getAnalysis<MachineLoopInfo>();
386 MRI = &MF.getRegInfo();
387 MDT = &getAnalysis<MachineDominatorTree>();
388 const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
389 TII = HST.getInstrInfo();
390 TRI = HST.getRegisterInfo();
391
392 for (auto &L : *MLI)
393 if (!L->getParentLoop()) {
394 bool L0Used = false;
395 bool L1Used = false;
396 Changed |= convertToHardwareLoop(L, L0Used, L1Used);
397 }
398
399 return Changed;
400}
401
402bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L,
403 unsigned &Reg,
404 int64_t &IVBump,
405 MachineInstr *&IVOp
406 ) const {
407 MachineBasicBlock *Header = L->getHeader();
408 MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);
409 MachineBasicBlock *Latch = L->getLoopLatch();
410 MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
411 if (!Header || !Preheader || !Latch || !ExitingBlock)
412 return false;
413
414 // This pair represents an induction register together with an immediate
415 // value that will be added to it in each loop iteration.
416 using RegisterBump = std::pair<unsigned, int64_t>;
417
418 // Mapping: R.next -> (R, bump), where R, R.next and bump are derived
419 // from an induction operation
420 // R.next = R + bump
421 // where bump is an immediate value.
422 using InductionMap = std::map<unsigned, RegisterBump>;
423
424 InductionMap IndMap;
425
426 using instr_iterator = MachineBasicBlock::instr_iterator;
427
428 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
429 I != E && I->isPHI(); ++I) {
430 MachineInstr *Phi = &*I;
431
432 // Have a PHI instruction. Get the operand that corresponds to the
433 // latch block, and see if is a result of an addition of form "reg+imm",
434 // where the "reg" is defined by the PHI node we are looking at.
435 for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
436 if (Phi->getOperand(i+1).getMBB() != Latch)
437 continue;
438
439 Register PhiOpReg = Phi->getOperand(i).getReg();
440 MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
441
442 if (DI->getDesc().isAdd()) {
443 // If the register operand to the add is the PHI we're looking at, this
444 // meets the induction pattern.
445 Register IndReg = DI->getOperand(1).getReg();
446 MachineOperand &Opnd2 = DI->getOperand(2);
447 int64_t V;
448 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
449 Register UpdReg = DI->getOperand(0).getReg();
450 IndMap.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
451 }
452 }
453 } // for (i)
454 } // for (instr)
455
456 SmallVector<MachineOperand,2> Cond;
457 MachineBasicBlock *TB = nullptr, *FB = nullptr;
458 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
459 if (NotAnalyzed)
460 return false;
461
462 unsigned PredR, PredPos, PredRegFlags;
463 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags))
464 return false;
465
466 MachineInstr *PredI = MRI->getVRegDef(PredR);
467 if (!PredI->isCompare())
468 return false;
469
470 unsigned CmpReg1 = 0, CmpReg2 = 0;
471 int CmpImm = 0, CmpMask = 0;
472 bool CmpAnalyzed =
473 TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm);
474 // Fail if the compare was not analyzed, or it's not comparing a register
475 // with an immediate value. Not checking the mask here, since we handle
476 // the individual compare opcodes (including A4_cmpb*) later on.
477 if (!CmpAnalyzed)
478 return false;
479
480 // Exactly one of the input registers to the comparison should be among
481 // the induction registers.
482 InductionMap::iterator IndMapEnd = IndMap.end();
483 InductionMap::iterator F = IndMapEnd;
484 if (CmpReg1 != 0) {
485 InductionMap::iterator F1 = IndMap.find(CmpReg1);
486 if (F1 != IndMapEnd)
487 F = F1;
488 }
489 if (CmpReg2 != 0) {
490 InductionMap::iterator F2 = IndMap.find(CmpReg2);
491 if (F2 != IndMapEnd) {
492 if (F != IndMapEnd)
493 return false;
494 F = F2;
495 }
496 }
497 if (F == IndMapEnd)
498 return false;
499
500 Reg = F->second.first;
501 IVBump = F->second.second;
502 IVOp = MRI->getVRegDef(F->first);
503 return true;
504}
505
506// Return the comparison kind for the specified opcode.
507HexagonHardwareLoops::Comparison::Kind
508HexagonHardwareLoops::getComparisonKind(unsigned CondOpc,
509 MachineOperand *InitialValue,
510 const MachineOperand *EndValue,
511 int64_t IVBump) const {
512 Comparison::Kind Cmp = (Comparison::Kind)0;
513 switch (CondOpc) {
514 case Hexagon::C2_cmpeq:
515 case Hexagon::C2_cmpeqi:
516 case Hexagon::C2_cmpeqp:
517 Cmp = Comparison::EQ;
518 break;
519 case Hexagon::C4_cmpneq:
520 case Hexagon::C4_cmpneqi:
521 Cmp = Comparison::NE;
522 break;
523 case Hexagon::C2_cmplt:
524 Cmp = Comparison::LTs;
525 break;
526 case Hexagon::C2_cmpltu:
527 Cmp = Comparison::LTu;
528 break;
529 case Hexagon::C4_cmplte:
530 case Hexagon::C4_cmpltei:
531 Cmp = Comparison::LEs;
532 break;
533 case Hexagon::C4_cmplteu:
534 case Hexagon::C4_cmplteui:
535 Cmp = Comparison::LEu;
536 break;
537 case Hexagon::C2_cmpgt:
538 case Hexagon::C2_cmpgti:
539 case Hexagon::C2_cmpgtp:
540 Cmp = Comparison::GTs;
541 break;
542 case Hexagon::C2_cmpgtu:
543 case Hexagon::C2_cmpgtui:
544 case Hexagon::C2_cmpgtup:
545 Cmp = Comparison::GTu;
546 break;
547 case Hexagon::C2_cmpgei:
548 Cmp = Comparison::GEs;
549 break;
550 case Hexagon::C2_cmpgeui:
551 Cmp = Comparison::GEs;
552 break;
553 default:
554 return (Comparison::Kind)0;
555 }
556 return Cmp;
557}
558
559/// Analyze the statements in a loop to determine if the loop has
560/// a computable trip count and, if so, return a value that represents
561/// the trip count expression.
562///
563/// This function iterates over the phi nodes in the loop to check for
564/// induction variable patterns that are used in the calculation for
565/// the number of time the loop is executed.
566CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
567 SmallVectorImpl<MachineInstr *> &OldInsts) {
568 MachineBasicBlock *TopMBB = L->getTopBlock();
569 MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();
570 assert(PI != TopMBB->pred_end() &&((PI != TopMBB->pred_end() && "Loop must have more than one incoming edge!"
) ? static_cast<void> (0) : __assert_fail ("PI != TopMBB->pred_end() && \"Loop must have more than one incoming edge!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 571, __PRETTY_FUNCTION__))
571 "Loop must have more than one incoming edge!")((PI != TopMBB->pred_end() && "Loop must have more than one incoming edge!"
) ? static_cast<void> (0) : __assert_fail ("PI != TopMBB->pred_end() && \"Loop must have more than one incoming edge!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 571, __PRETTY_FUNCTION__))
;
572 MachineBasicBlock *Backedge = *PI++;
573 if (PI == TopMBB->pred_end()) // dead loop?
574 return nullptr;
575 MachineBasicBlock *Incoming = *PI++;
576 if (PI != TopMBB->pred_end()) // multiple backedges?
577 return nullptr;
578
579 // Make sure there is one incoming and one backedge and determine which
580 // is which.
581 if (L->contains(Incoming)) {
582 if (L->contains(Backedge))
583 return nullptr;
584 std::swap(Incoming, Backedge);
585 } else if (!L->contains(Backedge))
586 return nullptr;
587
588 // Look for the cmp instruction to determine if we can get a useful trip
589 // count. The trip count can be either a register or an immediate. The
590 // location of the value depends upon the type (reg or imm).
591 MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
592 if (!ExitingBlock)
593 return nullptr;
594
595 unsigned IVReg = 0;
596 int64_t IVBump = 0;
597 MachineInstr *IVOp;
598 bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp);
599 if (!FoundIV)
600 return nullptr;
601
602 MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);
603
604 MachineOperand *InitialValue = nullptr;
605 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg);
606 MachineBasicBlock *Latch = L->getLoopLatch();
607 for (unsigned i = 1, n = IV_Phi->getNumOperands(); i < n; i += 2) {
608 MachineBasicBlock *MBB = IV_Phi->getOperand(i+1).getMBB();
609 if (MBB == Preheader)
610 InitialValue = &IV_Phi->getOperand(i);
611 else if (MBB == Latch)
612 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump.
613 }
614 if (!InitialValue)
615 return nullptr;
616
617 SmallVector<MachineOperand,2> Cond;
618 MachineBasicBlock *TB = nullptr, *FB = nullptr;
619 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
620 if (NotAnalyzed)
621 return nullptr;
622
623 MachineBasicBlock *Header = L->getHeader();
624 // TB must be non-null. If FB is also non-null, one of them must be
625 // the header. Otherwise, branch to TB could be exiting the loop, and
626 // the fall through can go to the header.
627 assert (TB && "Exit block without a branch?")((TB && "Exit block without a branch?") ? static_cast
<void> (0) : __assert_fail ("TB && \"Exit block without a branch?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 627, __PRETTY_FUNCTION__))
;
628 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) {
629 MachineBasicBlock *LTB = nullptr, *LFB = nullptr;
630 SmallVector<MachineOperand,2> LCond;
631 bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false);
632 if (NotAnalyzed)
633 return nullptr;
634 if (TB == Latch)
635 TB = (LTB == Header) ? LTB : LFB;
636 else
637 FB = (LTB == Header) ? LTB: LFB;
638 }
639 assert ((!FB || TB == Header || FB == Header) && "Branches not to header?")(((!FB || TB == Header || FB == Header) && "Branches not to header?"
) ? static_cast<void> (0) : __assert_fail ("(!FB || TB == Header || FB == Header) && \"Branches not to header?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 639, __PRETTY_FUNCTION__))
;
640 if (!TB || (FB && TB != Header && FB != Header))
641 return nullptr;
642
643 // Branches of form "if (!P) ..." cause HexagonInstrInfo::analyzeBranch
644 // to put imm(0), followed by P in the vector Cond.
645 // If TB is not the header, it means that the "not-taken" path must lead
646 // to the header.
647 bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);
648 unsigned PredReg, PredPos, PredRegFlags;
649 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags))
650 return nullptr;
651 MachineInstr *CondI = MRI->getVRegDef(PredReg);
652 unsigned CondOpc = CondI->getOpcode();
653
654 unsigned CmpReg1 = 0, CmpReg2 = 0;
655 int Mask = 0, ImmValue = 0;
656 bool AnalyzedCmp =
657 TII->analyzeCompare(*CondI, CmpReg1, CmpReg2, Mask, ImmValue);
658 if (!AnalyzedCmp)
659 return nullptr;
660
661 // The comparison operator type determines how we compute the loop
662 // trip count.
663 OldInsts.push_back(CondI);
664 OldInsts.push_back(IVOp);
665
666 // Sadly, the following code gets information based on the position
667 // of the operands in the compare instruction. This has to be done
668 // this way, because the comparisons check for a specific relationship
669 // between the operands (e.g. is-less-than), rather than to find out
670 // what relationship the operands are in (as on PPC).
671 Comparison::Kind Cmp;
672 bool isSwapped = false;
673 const MachineOperand &Op1 = CondI->getOperand(1);
674 const MachineOperand &Op2 = CondI->getOperand(2);
675 const MachineOperand *EndValue = nullptr;
676
677 if (Op1.isReg()) {
678 if (Op2.isImm() || Op1.getReg() == IVReg)
679 EndValue = &Op2;
680 else {
681 EndValue = &Op1;
682 isSwapped = true;
683 }
684 }
685
686 if (!EndValue)
687 return nullptr;
688
689 Cmp = getComparisonKind(CondOpc, InitialValue, EndValue, IVBump);
690 if (!Cmp)
691 return nullptr;
692 if (Negated)
693 Cmp = Comparison::getNegatedComparison(Cmp);
694 if (isSwapped)
695 Cmp = Comparison::getSwappedComparison(Cmp);
696
697 if (InitialValue->isReg()) {
698 Register R = InitialValue->getReg();
699 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
700 if (!MDT->properlyDominates(DefBB, Header)) {
701 int64_t V;
702 if (!checkForImmediate(*InitialValue, V))
703 return nullptr;
704 }
705 OldInsts.push_back(MRI->getVRegDef(R));
706 }
707 if (EndValue->isReg()) {
708 Register R = EndValue->getReg();
709 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
710 if (!MDT->properlyDominates(DefBB, Header)) {
711 int64_t V;
712 if (!checkForImmediate(*EndValue, V))
713 return nullptr;
714 }
715 OldInsts.push_back(MRI->getVRegDef(R));
716 }
717
718 return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);
719}
720
721/// Helper function that returns the expression that represents the
722/// number of times a loop iterates. The function takes the operands that
723/// represent the loop start value, loop end value, and induction value.
724/// Based upon these operands, the function attempts to compute the trip count.
725CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
726 const MachineOperand *Start,
727 const MachineOperand *End,
728 unsigned IVReg,
729 int64_t IVBump,
730 Comparison::Kind Cmp) const {
731 // Cannot handle comparison EQ, i.e. while (A == B).
732 if (Cmp == Comparison::EQ)
1
Assuming 'Cmp' is not equal to EQ
2
Taking false branch
733 return nullptr;
734
735 // Check if either the start or end values are an assignment of an immediate.
736 // If so, use the immediate value rather than the register.
737 if (Start->isReg()) {
3
Taking false branch
738 const MachineInstr *StartValInstr = MRI->getVRegDef(Start->getReg());
739 if (StartValInstr && (StartValInstr->getOpcode() == Hexagon::A2_tfrsi ||
740 StartValInstr->getOpcode() == Hexagon::A2_tfrpi))
741 Start = &StartValInstr->getOperand(1);
742 }
743 if (End->isReg()) {
4
Taking false branch
744 const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
745 if (EndValInstr && (EndValInstr->getOpcode() == Hexagon::A2_tfrsi ||
746 EndValInstr->getOpcode() == Hexagon::A2_tfrpi))
747 End = &EndValInstr->getOperand(1);
748 }
749
750 if (!Start->isReg() && !Start->isImm())
5
Calling 'MachineOperand::isReg'
7
Returning from 'MachineOperand::isReg'
8
Calling 'MachineOperand::isImm'
11
Returning from 'MachineOperand::isImm'
12
Taking false branch
751 return nullptr;
752 if (!End->isReg() && !End->isImm())
13
Calling 'MachineOperand::isReg'
15
Returning from 'MachineOperand::isReg'
16
Calling 'MachineOperand::isImm'
19
Returning from 'MachineOperand::isImm'
20
Taking false branch
753 return nullptr;
754
755 bool CmpLess = Cmp & Comparison::L;
756 bool CmpGreater = Cmp & Comparison::G;
757 bool CmpHasEqual = Cmp & Comparison::EQ;
758
759 // Avoid certain wrap-arounds. This doesn't detect all wrap-arounds.
760 if (CmpLess && IVBump < 0)
21
Assuming 'CmpLess' is true
22
Assuming 'IVBump' is >= 0
23
Taking false branch
761 // Loop going while iv is "less" with the iv value going down. Must wrap.
762 return nullptr;
763
764 if (CmpGreater && IVBump > 0)
24
Assuming 'CmpGreater' is true
25
Assuming 'IVBump' is <= 0
26
Taking false branch
765 // Loop going while iv is "greater" with the iv value going up. Must wrap.
766 return nullptr;
767
768 // Phis that may feed into the loop.
769 LoopFeederMap LoopFeederPhi;
770
771 // Check if the initial value may be zero and can be decremented in the first
772 // iteration. If the value is zero, the endloop instruction will not decrement
773 // the loop counter, so we shouldn't generate a hardware loop in this case.
774 if (loopCountMayWrapOrUnderFlow(Start, End, Loop->getLoopPreheader(), Loop,
27
Calling 'HexagonHardwareLoops::loopCountMayWrapOrUnderFlow'
33
Returning from 'HexagonHardwareLoops::loopCountMayWrapOrUnderFlow'
34
Taking false branch
775 LoopFeederPhi))
776 return nullptr;
777
778 if (Start->isImm() && End->isImm()) {
35
Calling 'MachineOperand::isImm'
37
Returning from 'MachineOperand::isImm'
38
Calling 'MachineOperand::isImm'
40
Returning from 'MachineOperand::isImm'
41
Taking true branch
779 // Both, start and end are immediates.
780 int64_t StartV = Start->getImm();
781 int64_t EndV = End->getImm();
782 int64_t Dist = EndV - StartV;
783 if (Dist == 0)
42
Assuming 'Dist' is not equal to 0
43
Taking false branch
784 return nullptr;
785
786 bool Exact = (Dist % IVBump) == 0;
44
Division by zero
787
788 if (Cmp == Comparison::NE) {
789 if (!Exact)
790 return nullptr;
791 if ((Dist < 0) ^ (IVBump < 0))
792 return nullptr;
793 }
794
795 // For comparisons that include the final value (i.e. include equality
796 // with the final value), we need to increase the distance by 1.
797 if (CmpHasEqual)
798 Dist = Dist > 0 ? Dist+1 : Dist-1;
799
800 // For the loop to iterate, CmpLess should imply Dist > 0. Similarly,
801 // CmpGreater should imply Dist < 0. These conditions could actually
802 // fail, for example, in unreachable code (which may still appear to be
803 // reachable in the CFG).
804 if ((CmpLess && Dist < 0) || (CmpGreater && Dist > 0))
805 return nullptr;
806
807 // "Normalized" distance, i.e. with the bump set to +-1.
808 int64_t Dist1 = (IVBump > 0) ? (Dist + (IVBump - 1)) / IVBump
809 : (-Dist + (-IVBump - 1)) / (-IVBump);
810 assert (Dist1 > 0 && "Fishy thing. Both operands have the same sign.")((Dist1 > 0 && "Fishy thing. Both operands have the same sign."
) ? static_cast<void> (0) : __assert_fail ("Dist1 > 0 && \"Fishy thing. Both operands have the same sign.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 810, __PRETTY_FUNCTION__))
;
811
812 uint64_t Count = Dist1;
813
814 if (Count > 0xFFFFFFFFULL)
815 return nullptr;
816
817 return new CountValue(CountValue::CV_Immediate, Count);
818 }
819
820 // A general case: Start and End are some values, but the actual
821 // iteration count may not be available. If it is not, insert
822 // a computation of it into the preheader.
823
824 // If the induction variable bump is not a power of 2, quit.
825 // Othwerise we'd need a general integer division.
826 if (!isPowerOf2_64(std::abs(IVBump)))
827 return nullptr;
828
829 MachineBasicBlock *PH = MLI->findLoopPreheader(Loop, SpecPreheader);
830 assert (PH && "Should have a preheader by now")((PH && "Should have a preheader by now") ? static_cast
<void> (0) : __assert_fail ("PH && \"Should have a preheader by now\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 830, __PRETTY_FUNCTION__))
;
831 MachineBasicBlock::iterator InsertPos = PH->getFirstTerminator();
832 DebugLoc DL;
833 if (InsertPos != PH->end())
834 DL = InsertPos->getDebugLoc();
835
836 // If Start is an immediate and End is a register, the trip count
837 // will be "reg - imm". Hexagon's "subtract immediate" instruction
838 // is actually "reg + -imm".
839
840 // If the loop IV is going downwards, i.e. if the bump is negative,
841 // then the iteration count (computed as End-Start) will need to be
842 // negated. To avoid the negation, just swap Start and End.
843 if (IVBump < 0) {
844 std::swap(Start, End);
845 IVBump = -IVBump;
846 }
847 // Cmp may now have a wrong direction, e.g. LEs may now be GEs.
848 // Signedness, and "including equality" are preserved.
849
850 bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm)
851 bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg)
852
853 int64_t StartV = 0, EndV = 0;
854 if (Start->isImm())
855 StartV = Start->getImm();
856 if (End->isImm())
857 EndV = End->getImm();
858
859 int64_t AdjV = 0;
860 // To compute the iteration count, we would need this computation:
861 // Count = (End - Start + (IVBump-1)) / IVBump
862 // or, when CmpHasEqual:
863 // Count = (End - Start + (IVBump-1)+1) / IVBump
864 // The "IVBump-1" part is the adjustment (AdjV). We can avoid
865 // generating an instruction specifically to add it if we can adjust
866 // the immediate values for Start or End.
867
868 if (CmpHasEqual) {
869 // Need to add 1 to the total iteration count.
870 if (Start->isImm())
871 StartV--;
872 else if (End->isImm())
873 EndV++;
874 else
875 AdjV += 1;
876 }
877
878 if (Cmp != Comparison::NE) {
879 if (Start->isImm())
880 StartV -= (IVBump-1);
881 else if (End->isImm())
882 EndV += (IVBump-1);
883 else
884 AdjV += (IVBump-1);
885 }
886
887 unsigned R = 0, SR = 0;
888 if (Start->isReg()) {
889 R = Start->getReg();
890 SR = Start->getSubReg();
891 } else {
892 R = End->getReg();
893 SR = End->getSubReg();
894 }
895 const TargetRegisterClass *RC = MRI->getRegClass(R);
896 // Hardware loops cannot handle 64-bit registers. If it's a double
897 // register, it has to have a subregister.
898 if (!SR && RC == &Hexagon::DoubleRegsRegClass)
899 return nullptr;
900 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
901
902 // Compute DistR (register with the distance between Start and End).
903 unsigned DistR, DistSR;
904
905 // Avoid special case, where the start value is an imm(0).
906 if (Start->isImm() && StartV == 0) {
907 DistR = End->getReg();
908 DistSR = End->getSubReg();
909 } else {
910 const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::A2_sub) :
911 (RegToImm ? TII->get(Hexagon::A2_subri) :
912 TII->get(Hexagon::A2_addi));
913 if (RegToReg || RegToImm) {
914 Register SubR = MRI->createVirtualRegister(IntRC);
915 MachineInstrBuilder SubIB =
916 BuildMI(*PH, InsertPos, DL, SubD, SubR);
917
918 if (RegToReg)
919 SubIB.addReg(End->getReg(), 0, End->getSubReg())
920 .addReg(Start->getReg(), 0, Start->getSubReg());
921 else
922 SubIB.addImm(EndV)
923 .addReg(Start->getReg(), 0, Start->getSubReg());
924 DistR = SubR;
925 } else {
926 // If the loop has been unrolled, we should use the original loop count
927 // instead of recalculating the value. This will avoid additional
928 // 'Add' instruction.
929 const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
930 if (EndValInstr->getOpcode() == Hexagon::A2_addi &&
931 EndValInstr->getOperand(1).getSubReg() == 0 &&
932 EndValInstr->getOperand(2).getImm() == StartV) {
933 DistR = EndValInstr->getOperand(1).getReg();
934 } else {
935 Register SubR = MRI->createVirtualRegister(IntRC);
936 MachineInstrBuilder SubIB =
937 BuildMI(*PH, InsertPos, DL, SubD, SubR);
938 SubIB.addReg(End->getReg(), 0, End->getSubReg())
939 .addImm(-StartV);
940 DistR = SubR;
941 }
942 }
943 DistSR = 0;
944 }
945
946 // From DistR, compute AdjR (register with the adjusted distance).
947 unsigned AdjR, AdjSR;
948
949 if (AdjV == 0) {
950 AdjR = DistR;
951 AdjSR = DistSR;
952 } else {
953 // Generate CountR = ADD DistR, AdjVal
954 Register AddR = MRI->createVirtualRegister(IntRC);
955 MCInstrDesc const &AddD = TII->get(Hexagon::A2_addi);
956 BuildMI(*PH, InsertPos, DL, AddD, AddR)
957 .addReg(DistR, 0, DistSR)
958 .addImm(AdjV);
959
960 AdjR = AddR;
961 AdjSR = 0;
962 }
963
964 // From AdjR, compute CountR (register with the final count).
965 unsigned CountR, CountSR;
966
967 if (IVBump == 1) {
968 CountR = AdjR;
969 CountSR = AdjSR;
970 } else {
971 // The IV bump is a power of two. Log_2(IV bump) is the shift amount.
972 unsigned Shift = Log2_32(IVBump);
973
974 // Generate NormR = LSR DistR, Shift.
975 Register LsrR = MRI->createVirtualRegister(IntRC);
976 const MCInstrDesc &LsrD = TII->get(Hexagon::S2_lsr_i_r);
977 BuildMI(*PH, InsertPos, DL, LsrD, LsrR)
978 .addReg(AdjR, 0, AdjSR)
979 .addImm(Shift);
980
981 CountR = LsrR;
982 CountSR = 0;
983 }
984
985 return new CountValue(CountValue::CV_Register, CountR, CountSR);
986}
987
988/// Return true if the operation is invalid within hardware loop.
989bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI,
990 bool IsInnerHWLoop) const {
991 // Call is not allowed because the callee may use a hardware loop except for
992 // the case when the call never returns.
993 if (MI->getDesc().isCall())
994 return !TII->doesNotReturn(*MI);
995
996 // Check if the instruction defines a hardware loop register.
997 using namespace Hexagon;
998
999 static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 };
1000 static const unsigned Regs1[] = { LC1, SA1 };
1001 auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, array_lengthof(Regs01))
1002 : makeArrayRef(Regs1, array_lengthof(Regs1));
1003 for (unsigned R : CheckRegs)
1004 if (MI->modifiesRegister(R, TRI))
1005 return true;
1006
1007 return false;
1008}
1009
1010/// Return true if the loop contains an instruction that inhibits
1011/// the use of the hardware loop instruction.
1012bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L,
1013 bool IsInnerHWLoop) const {
1014 LLVM_DEBUG(dbgs() << "\nhw_loop head, "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nhw_loop head, " << printMBBReference
(**L->block_begin()); } } while (false)
1015 << printMBBReference(**L->block_begin()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nhw_loop head, " << printMBBReference
(**L->block_begin()); } } while (false)
;
1016 for (MachineBasicBlock *MBB : L->getBlocks()) {
1017 for (MachineBasicBlock::iterator
1018 MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) {
1019 const MachineInstr *MI = &*MII;
1020 if (isInvalidLoopOperation(MI, IsInnerHWLoop)) {
1021 LLVM_DEBUG(dbgs() << "\nCannot convert to hw_loop due to:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nCannot convert to hw_loop due to:"
; MI->dump();; } } while (false)
1022 MI->dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nCannot convert to hw_loop due to:"
; MI->dump();; } } while (false)
;
1023 return true;
1024 }
1025 }
1026 }
1027 return false;
1028}
1029
1030/// Returns true if the instruction is dead. This was essentially
1031/// copied from DeadMachineInstructionElim::isDead, but with special cases
1032/// for inline asm, physical registers and instructions with side effects
1033/// removed.
1034bool HexagonHardwareLoops::isDead(const MachineInstr *MI,
1035 SmallVectorImpl<MachineInstr *> &DeadPhis) const {
1036 // Examine each operand.
1037 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1038 const MachineOperand &MO = MI->getOperand(i);
1039 if (!MO.isReg() || !MO.isDef())
1040 continue;
1041
1042 Register Reg = MO.getReg();
1043 if (MRI->use_nodbg_empty(Reg))
1044 continue;
1045
1046 using use_nodbg_iterator = MachineRegisterInfo::use_nodbg_iterator;
1047
1048 // This instruction has users, but if the only user is the phi node for the
1049 // parent block, and the only use of that phi node is this instruction, then
1050 // this instruction is dead: both it (and the phi node) can be removed.
1051 use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);
1052 use_nodbg_iterator End = MRI->use_nodbg_end();
1053 if (std::next(I) != End || !I->getParent()->isPHI())
1054 return false;
1055
1056 MachineInstr *OnePhi = I->getParent();
1057 for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {
1058 const MachineOperand &OPO = OnePhi->getOperand(j);
1059 if (!OPO.isReg() || !OPO.isDef())
1060 continue;
1061
1062 Register OPReg = OPO.getReg();
1063 use_nodbg_iterator nextJ;
1064 for (use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg);
1065 J != End; J = nextJ) {
1066 nextJ = std::next(J);
1067 MachineOperand &Use = *J;
1068 MachineInstr *UseMI = Use.getParent();
1069
1070 // If the phi node has a user that is not MI, bail.
1071 if (MI != UseMI)
1072 return false;
1073 }
1074 }
1075 DeadPhis.push_back(OnePhi);
1076 }
1077
1078 // If there are no defs with uses, the instruction is dead.
1079 return true;
1080}
1081
1082void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) {
1083 // This procedure was essentially copied from DeadMachineInstructionElim.
1084
1085 SmallVector<MachineInstr*, 1> DeadPhis;
1086 if (isDead(MI, DeadPhis)) {
1087 LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "HW looping will remove: " <<
*MI; } } while (false)
;
1088
1089 // It is possible that some DBG_VALUE instructions refer to this
1090 // instruction. Examine each def operand for such references;
1091 // if found, mark the DBG_VALUE as undef (but don't delete it).
1092 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1093 const MachineOperand &MO = MI->getOperand(i);
1094 if (!MO.isReg() || !MO.isDef())
1095 continue;
1096 Register Reg = MO.getReg();
1097 MachineRegisterInfo::use_iterator nextI;
1098 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
1099 E = MRI->use_end(); I != E; I = nextI) {
1100 nextI = std::next(I); // I is invalidated by the setReg
1101 MachineOperand &Use = *I;
1102 MachineInstr *UseMI = I->getParent();
1103 if (UseMI == MI)
1104 continue;
1105 if (Use.isDebug())
1106 UseMI->getOperand(0).setReg(0U);
1107 }
1108 }
1109
1110 MI->eraseFromParent();
1111 for (unsigned i = 0; i < DeadPhis.size(); ++i)
1112 DeadPhis[i]->eraseFromParent();
1113 }
1114}
1115
1116/// Check if the loop is a candidate for converting to a hardware
1117/// loop. If so, then perform the transformation.
1118///
1119/// This function works on innermost loops first. A loop can be converted
1120/// if it is a counting loop; either a register value or an immediate.
1121///
1122/// The code makes several assumptions about the representation of the loop
1123/// in llvm.
1124bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L,
1125 bool &RecL0used,
1126 bool &RecL1used) {
1127 // This is just for sanity.
1128 assert(L->getHeader() && "Loop without a header?")((L->getHeader() && "Loop without a header?") ? static_cast
<void> (0) : __assert_fail ("L->getHeader() && \"Loop without a header?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1128, __PRETTY_FUNCTION__))
;
1129
1130 bool Changed = false;
1131 bool L0Used = false;
1132 bool L1Used = false;
1133
1134 // Process nested loops first.
1135 for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
1136 Changed |= convertToHardwareLoop(*I, RecL0used, RecL1used);
1137 L0Used |= RecL0used;
1138 L1Used |= RecL1used;
1139 }
1140
1141 // If a nested loop has been converted, then we can't convert this loop.
1142 if (Changed && L0Used && L1Used)
1143 return Changed;
1144
1145 unsigned LOOP_i;
1146 unsigned LOOP_r;
1147 unsigned ENDLOOP;
1148
1149 // Flag used to track loopN instruction:
1150 // 1 - Hardware loop is being generated for the inner most loop.
1151 // 0 - Hardware loop is being generated for the outer loop.
1152 unsigned IsInnerHWLoop = 1;
1153
1154 if (L0Used) {
1155 LOOP_i = Hexagon::J2_loop1i;
1156 LOOP_r = Hexagon::J2_loop1r;
1157 ENDLOOP = Hexagon::ENDLOOP1;
1158 IsInnerHWLoop = 0;
1159 } else {
1160 LOOP_i = Hexagon::J2_loop0i;
1161 LOOP_r = Hexagon::J2_loop0r;
1162 ENDLOOP = Hexagon::ENDLOOP0;
1163 }
1164
1165#ifndef NDEBUG
1166 // Stop trying after reaching the limit (if any).
1167 int Limit = HWLoopLimit;
1168 if (Limit >= 0) {
1169 if (Counter >= HWLoopLimit)
1170 return false;
1171 Counter++;
1172 }
1173#endif
1174
1175 // Does the loop contain any invalid instructions?
1176 if (containsInvalidInstruction(L, IsInnerHWLoop))
1177 return false;
1178
1179 MachineBasicBlock *LastMBB = L->findLoopControlBlock();
1180 // Don't generate hw loop if the loop has more than one exit.
1181 if (!LastMBB)
1182 return false;
1183
1184 MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
1185 if (LastI == LastMBB->end())
1186 return false;
1187
1188 // Is the induction variable bump feeding the latch condition?
1189 if (!fixupInductionVariable(L))
1190 return false;
1191
1192 // Ensure the loop has a preheader: the loop instruction will be
1193 // placed there.
1194 MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);
1195 if (!Preheader) {
1196 Preheader = createPreheaderForLoop(L);
1197 if (!Preheader)
1198 return false;
1199 }
1200
1201 MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();
1202
1203 SmallVector<MachineInstr*, 2> OldInsts;
1204 // Are we able to determine the trip count for the loop?
1205 CountValue *TripCount = getLoopTripCount(L, OldInsts);
1206 if (!TripCount)
1207 return false;
1208
1209 // Is the trip count available in the preheader?
1210 if (TripCount->isReg()) {
1211 // There will be a use of the register inserted into the preheader,
1212 // so make sure that the register is actually defined at that point.
1213 MachineInstr *TCDef = MRI->getVRegDef(TripCount->getReg());
1214 MachineBasicBlock *BBDef = TCDef->getParent();
1215 if (!MDT->dominates(BBDef, Preheader))
1216 return false;
1217 }
1218
1219 // Determine the loop start.
1220 MachineBasicBlock *TopBlock = L->getTopBlock();
1221 MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
1222 MachineBasicBlock *LoopStart = nullptr;
1223 if (ExitingBlock != L->getLoopLatch()) {
1224 MachineBasicBlock *TB = nullptr, *FB = nullptr;
1225 SmallVector<MachineOperand, 2> Cond;
1226
1227 if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false))
1228 return false;
1229
1230 if (L->contains(TB))
1231 LoopStart = TB;
1232 else if (L->contains(FB))
1233 LoopStart = FB;
1234 else
1235 return false;
1236 }
1237 else
1238 LoopStart = TopBlock;
1239
1240 // Convert the loop to a hardware loop.
1241 LLVM_DEBUG(dbgs() << "Change to hardware loop at "; L->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "Change to hardware loop at ";
L->dump(); } } while (false)
;
1242 DebugLoc DL;
1243 if (InsertPos != Preheader->end())
1244 DL = InsertPos->getDebugLoc();
1245
1246 if (TripCount->isReg()) {
1247 // Create a copy of the loop count register.
1248 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1249 BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg)
1250 .addReg(TripCount->getReg(), 0, TripCount->getSubReg());
1251 // Add the Loop instruction to the beginning of the loop.
1252 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart)
1253 .addReg(CountReg);
1254 } else {
1255 assert(TripCount->isImm() && "Expecting immediate value for trip count")((TripCount->isImm() && "Expecting immediate value for trip count"
) ? static_cast<void> (0) : __assert_fail ("TripCount->isImm() && \"Expecting immediate value for trip count\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1255, __PRETTY_FUNCTION__))
;
1256 // Add the Loop immediate instruction to the beginning of the loop,
1257 // if the immediate fits in the instructions. Otherwise, we need to
1258 // create a new virtual register.
1259 int64_t CountImm = TripCount->getImm();
1260 if (!TII->isValidOffset(LOOP_i, CountImm, TRI)) {
1261 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1262 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg)
1263 .addImm(CountImm);
1264 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r))
1265 .addMBB(LoopStart).addReg(CountReg);
1266 } else
1267 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_i))
1268 .addMBB(LoopStart).addImm(CountImm);
1269 }
1270
1271 // Make sure the loop start always has a reference in the CFG. We need
1272 // to create a BlockAddress operand to get this mechanism to work both the
1273 // MachineBasicBlock and BasicBlock objects need the flag set.
1274 LoopStart->setHasAddressTaken();
1275 // This line is needed to set the hasAddressTaken flag on the BasicBlock
1276 // object.
1277 BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
1278
1279 // Replace the loop branch with an endloop instruction.
1280 DebugLoc LastIDL = LastI->getDebugLoc();
1281 BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart);
1282
1283 // The loop ends with either:
1284 // - a conditional branch followed by an unconditional branch, or
1285 // - a conditional branch to the loop start.
1286 if (LastI->getOpcode() == Hexagon::J2_jumpt ||
1287 LastI->getOpcode() == Hexagon::J2_jumpf) {
1288 // Delete one and change/add an uncond. branch to out of the loop.
1289 MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();
1290 LastI = LastMBB->erase(LastI);
1291 if (!L->contains(BranchTarget)) {
1292 if (LastI != LastMBB->end())
1293 LastI = LastMBB->erase(LastI);
1294 SmallVector<MachineOperand, 0> Cond;
1295 TII->insertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL);
1296 }
1297 } else {
1298 // Conditional branch to loop start; just delete it.
1299 LastMBB->erase(LastI);
1300 }
1301 delete TripCount;
1302
1303 // The induction operation and the comparison may now be
1304 // unneeded. If these are unneeded, then remove them.
1305 for (unsigned i = 0; i < OldInsts.size(); ++i)
1306 removeIfDead(OldInsts[i]);
1307
1308 ++NumHWLoops;
1309
1310 // Set RecL1used and RecL0used only after hardware loop has been
1311 // successfully generated. Doing it earlier can cause wrong loop instruction
1312 // to be used.
1313 if (L0Used) // Loop0 was already used. So, the correct loop must be loop1.
1314 RecL1used = true;
1315 else
1316 RecL0used = true;
1317
1318 return true;
1319}
1320
1321bool HexagonHardwareLoops::orderBumpCompare(MachineInstr *BumpI,
1322 MachineInstr *CmpI) {
1323 assert (BumpI != CmpI && "Bump and compare in the same instruction?")((BumpI != CmpI && "Bump and compare in the same instruction?"
) ? static_cast<void> (0) : __assert_fail ("BumpI != CmpI && \"Bump and compare in the same instruction?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1323, __PRETTY_FUNCTION__))
;
1324
1325 MachineBasicBlock *BB = BumpI->getParent();
1326 if (CmpI->getParent() != BB)
1327 return false;
1328
1329 using instr_iterator = MachineBasicBlock::instr_iterator;
1330
1331 // Check if things are in order to begin with.
1332 for (instr_iterator I(BumpI), E = BB->instr_end(); I != E; ++I)
1333 if (&*I == CmpI)
1334 return true;
1335
1336 // Out of order.
1337 Register PredR = CmpI->getOperand(0).getReg();
1338 bool FoundBump = false;
1339 instr_iterator CmpIt = CmpI->getIterator(), NextIt = std::next(CmpIt);
1340 for (instr_iterator I = NextIt, E = BB->instr_end(); I != E; ++I) {
1341 MachineInstr *In = &*I;
1342 for (unsigned i = 0, n = In->getNumOperands(); i < n; ++i) {
1343 MachineOperand &MO = In->getOperand(i);
1344 if (MO.isReg() && MO.isUse()) {
1345 if (MO.getReg() == PredR) // Found an intervening use of PredR.
1346 return false;
1347 }
1348 }
1349
1350 if (In == BumpI) {
1351 BB->splice(++BumpI->getIterator(), BB, CmpI->getIterator());
1352 FoundBump = true;
1353 break;
1354 }
1355 }
1356 assert (FoundBump && "Cannot determine instruction order")((FoundBump && "Cannot determine instruction order") ?
static_cast<void> (0) : __assert_fail ("FoundBump && \"Cannot determine instruction order\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1356, __PRETTY_FUNCTION__))
;
1357 return FoundBump;
1358}
1359
1360/// This function is required to break recursion. Visiting phis in a loop may
1361/// result in recursion during compilation. We break the recursion by making
1362/// sure that we visit a MachineOperand and its definition in a
1363/// MachineInstruction only once. If we attempt to visit more than once, then
1364/// there is recursion, and will return false.
1365bool HexagonHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A,
1366 MachineInstr *MI,
1367 const MachineOperand *MO,
1368 LoopFeederMap &LoopFeederPhi) const {
1369 if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) {
1370 LLVM_DEBUG(dbgs() << "\nhw_loop head, "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nhw_loop head, " << printMBBReference
(**L->block_begin()); } } while (false)
1371 << printMBBReference(**L->block_begin()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nhw_loop head, " << printMBBReference
(**L->block_begin()); } } while (false)
;
1372 // Ignore all BBs that form Loop.
1373 for (MachineBasicBlock *MBB : L->getBlocks()) {
1374 if (A == MBB)
1375 return false;
1376 }
1377 MachineInstr *Def = MRI->getVRegDef(MO->getReg());
1378 LoopFeederPhi.insert(std::make_pair(MO->getReg(), Def));
1379 return true;
1380 } else
1381 // Already visited node.
1382 return false;
1383}
1384
1385/// Return true if a Phi may generate a value that can underflow.
1386/// This function calls loopCountMayWrapOrUnderFlow for each Phi operand.
1387bool HexagonHardwareLoops::phiMayWrapOrUnderflow(
1388 MachineInstr *Phi, const MachineOperand *EndVal, MachineBasicBlock *MBB,
1389 MachineLoop *L, LoopFeederMap &LoopFeederPhi) const {
1390 assert(Phi->isPHI() && "Expecting a Phi.")((Phi->isPHI() && "Expecting a Phi.") ? static_cast
<void> (0) : __assert_fail ("Phi->isPHI() && \"Expecting a Phi.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1390, __PRETTY_FUNCTION__))
;
1391 // Walk through each Phi, and its used operands. Make sure that
1392 // if there is recursion in Phi, we won't generate hardware loops.
1393 for (int i = 1, n = Phi->getNumOperands(); i < n; i += 2)
1394 if (isLoopFeeder(L, MBB, Phi, &(Phi->getOperand(i)), LoopFeederPhi))
1395 if (loopCountMayWrapOrUnderFlow(&(Phi->getOperand(i)), EndVal,
1396 Phi->getParent(), L, LoopFeederPhi))
1397 return true;
1398 return false;
1399}
1400
1401/// Return true if the induction variable can underflow in the first iteration.
1402/// An example, is an initial unsigned value that is 0 and is decrement in the
1403/// first itertion of a do-while loop. In this case, we cannot generate a
1404/// hardware loop because the endloop instruction does not decrement the loop
1405/// counter if it is <= 1. We only need to perform this analysis if the
1406/// initial value is a register.
1407///
1408/// This function assumes the initial value may underfow unless proven
1409/// otherwise. If the type is signed, then we don't care because signed
1410/// underflow is undefined. We attempt to prove the initial value is not
1411/// zero by perfoming a crude analysis of the loop counter. This function
1412/// checks if the initial value is used in any comparison prior to the loop
1413/// and, if so, assumes the comparison is a range check. This is inexact,
1414/// but will catch the simple cases.
1415bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow(
1416 const MachineOperand *InitVal, const MachineOperand *EndVal,
1417 MachineBasicBlock *MBB, MachineLoop *L,
1418 LoopFeederMap &LoopFeederPhi) const {
1419 // Only check register values since they are unknown.
1420 if (!InitVal->isReg())
28
Calling 'MachineOperand::isReg'
30
Returning from 'MachineOperand::isReg'
31
Taking true branch
1421 return false;
32
Returning zero, which participates in a condition later
1422
1423 if (!EndVal->isImm())
1424 return false;
1425
1426 // A register value that is assigned an immediate is a known value, and it
1427 // won't underflow in the first iteration.
1428 int64_t Imm;
1429 if (checkForImmediate(*InitVal, Imm))
1430 return (EndVal->getImm() == Imm);
1431
1432 Register Reg = InitVal->getReg();
1433
1434 // We don't know the value of a physical register.
1435 if (!Register::isVirtualRegister(Reg))
1436 return true;
1437
1438 MachineInstr *Def = MRI->getVRegDef(Reg);
1439 if (!Def)
1440 return true;
1441
1442 // If the initial value is a Phi or copy and the operands may not underflow,
1443 // then the definition cannot be underflow either.
1444 if (Def->isPHI() && !phiMayWrapOrUnderflow(Def, EndVal, Def->getParent(),
1445 L, LoopFeederPhi))
1446 return false;
1447 if (Def->isCopy() && !loopCountMayWrapOrUnderFlow(&(Def->getOperand(1)),
1448 EndVal, Def->getParent(),
1449 L, LoopFeederPhi))
1450 return false;
1451
1452 // Iterate over the uses of the initial value. If the initial value is used
1453 // in a compare, then we assume this is a range check that ensures the loop
1454 // doesn't underflow. This is not an exact test and should be improved.
1455 for (MachineRegisterInfo::use_instr_nodbg_iterator I = MRI->use_instr_nodbg_begin(Reg),
1456 E = MRI->use_instr_nodbg_end(); I != E; ++I) {
1457 MachineInstr *MI = &*I;
1458 unsigned CmpReg1 = 0, CmpReg2 = 0;
1459 int CmpMask = 0, CmpValue = 0;
1460
1461 if (!TII->analyzeCompare(*MI, CmpReg1, CmpReg2, CmpMask, CmpValue))
1462 continue;
1463
1464 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
1465 SmallVector<MachineOperand, 2> Cond;
1466 if (TII->analyzeBranch(*MI->getParent(), TBB, FBB, Cond, false))
1467 continue;
1468
1469 Comparison::Kind Cmp =
1470 getComparisonKind(MI->getOpcode(), nullptr, nullptr, 0);
1471 if (Cmp == 0)
1472 continue;
1473 if (TII->predOpcodeHasNot(Cond) ^ (TBB != MBB))
1474 Cmp = Comparison::getNegatedComparison(Cmp);
1475 if (CmpReg2 != 0 && CmpReg2 == Reg)
1476 Cmp = Comparison::getSwappedComparison(Cmp);
1477
1478 // Signed underflow is undefined.
1479 if (Comparison::isSigned(Cmp))
1480 return false;
1481
1482 // Check if there is a comparison of the initial value. If the initial value
1483 // is greater than or not equal to another value, then assume this is a
1484 // range check.
1485 if ((Cmp & Comparison::G) || Cmp == Comparison::NE)
1486 return false;
1487 }
1488
1489 // OK - this is a hack that needs to be improved. We really need to analyze
1490 // the instructions performed on the initial value. This works on the simplest
1491 // cases only.
1492 if (!Def->isCopy() && !Def->isPHI())
1493 return false;
1494
1495 return true;
1496}
1497
1498bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO,
1499 int64_t &Val) const {
1500 if (MO.isImm()) {
1501 Val = MO.getImm();
1502 return true;
1503 }
1504 if (!MO.isReg())
1505 return false;
1506
1507 // MO is a register. Check whether it is defined as an immediate value,
1508 // and if so, get the value of it in TV. That value will then need to be
1509 // processed to handle potential subregisters in MO.
1510 int64_t TV;
1511
1512 Register R = MO.getReg();
1513 if (!Register::isVirtualRegister(R))
1514 return false;
1515 MachineInstr *DI = MRI->getVRegDef(R);
1516 unsigned DOpc = DI->getOpcode();
1517 switch (DOpc) {
1518 case TargetOpcode::COPY:
1519 case Hexagon::A2_tfrsi:
1520 case Hexagon::A2_tfrpi:
1521 case Hexagon::CONST32:
1522 case Hexagon::CONST64:
1523 // Call recursively to avoid an extra check whether operand(1) is
1524 // indeed an immediate (it could be a global address, for example),
1525 // plus we can handle COPY at the same time.
1526 if (!checkForImmediate(DI->getOperand(1), TV))
1527 return false;
1528 break;
1529 case Hexagon::A2_combineii:
1530 case Hexagon::A4_combineir:
1531 case Hexagon::A4_combineii:
1532 case Hexagon::A4_combineri:
1533 case Hexagon::A2_combinew: {
1534 const MachineOperand &S1 = DI->getOperand(1);
1535 const MachineOperand &S2 = DI->getOperand(2);
1536 int64_t V1, V2;
1537 if (!checkForImmediate(S1, V1) || !checkForImmediate(S2, V2))
1538 return false;
1539 TV = V2 | (static_cast<uint64_t>(V1) << 32);
1540 break;
1541 }
1542 case TargetOpcode::REG_SEQUENCE: {
1543 const MachineOperand &S1 = DI->getOperand(1);
1544 const MachineOperand &S3 = DI->getOperand(3);
1545 int64_t V1, V3;
1546 if (!checkForImmediate(S1, V1) || !checkForImmediate(S3, V3))
1547 return false;
1548 unsigned Sub2 = DI->getOperand(2).getImm();
1549 unsigned Sub4 = DI->getOperand(4).getImm();
1550 if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi)
1551 TV = V1 | (V3 << 32);
1552 else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo)
1553 TV = V3 | (V1 << 32);
1554 else
1555 llvm_unreachable("Unexpected form of REG_SEQUENCE")::llvm::llvm_unreachable_internal("Unexpected form of REG_SEQUENCE"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1555)
;
1556 break;
1557 }
1558
1559 default:
1560 return false;
1561 }
1562
1563 // By now, we should have successfully obtained the immediate value defining
1564 // the register referenced in MO. Handle a potential use of a subregister.
1565 switch (MO.getSubReg()) {
1566 case Hexagon::isub_lo:
1567 Val = TV & 0xFFFFFFFFULL;
1568 break;
1569 case Hexagon::isub_hi:
1570 Val = (TV >> 32) & 0xFFFFFFFFULL;
1571 break;
1572 default:
1573 Val = TV;
1574 break;
1575 }
1576 return true;
1577}
1578
1579void HexagonHardwareLoops::setImmediate(MachineOperand &MO, int64_t Val) {
1580 if (MO.isImm()) {
1581 MO.setImm(Val);
1582 return;
1583 }
1584
1585 assert(MO.isReg())((MO.isReg()) ? static_cast<void> (0) : __assert_fail (
"MO.isReg()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1585, __PRETTY_FUNCTION__))
;
1586 Register R = MO.getReg();
1587 MachineInstr *DI = MRI->getVRegDef(R);
1588
1589 const TargetRegisterClass *RC = MRI->getRegClass(R);
1590 Register NewR = MRI->createVirtualRegister(RC);
1591 MachineBasicBlock &B = *DI->getParent();
1592 DebugLoc DL = DI->getDebugLoc();
1593 BuildMI(B, DI, DL, TII->get(DI->getOpcode()), NewR).addImm(Val);
1594 MO.setReg(NewR);
1595}
1596
1597static bool isImmValidForOpcode(unsigned CmpOpc, int64_t Imm) {
1598 // These two instructions are not extendable.
1599 if (CmpOpc == Hexagon::A4_cmpbeqi)
1600 return isUInt<8>(Imm);
1601 if (CmpOpc == Hexagon::A4_cmpbgti)
1602 return isInt<8>(Imm);
1603 // The rest of the comparison-with-immediate instructions are extendable.
1604 return true;
1605}
1606
1607bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
1608 MachineBasicBlock *Header = L->getHeader();
1609 MachineBasicBlock *Latch = L->getLoopLatch();
1610 MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
1611
1612 if (!(Header && Latch && ExitingBlock))
1613 return false;
1614
1615 // These data structures follow the same concept as the corresponding
1616 // ones in findInductionRegister (where some comments are).
1617 using RegisterBump = std::pair<unsigned, int64_t>;
1618 using RegisterInduction = std::pair<unsigned, RegisterBump>;
1619 using RegisterInductionSet = std::set<RegisterInduction>;
1620
1621 // Register candidates for induction variables, with their associated bumps.
1622 RegisterInductionSet IndRegs;
1623
1624 // Look for induction patterns:
1625 // %1 = PHI ..., [ latch, %2 ]
1626 // %2 = ADD %1, imm
1627 using instr_iterator = MachineBasicBlock::instr_iterator;
1628
1629 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1630 I != E && I->isPHI(); ++I) {
1631 MachineInstr *Phi = &*I;
1632
1633 // Have a PHI instruction.
1634 for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
1635 if (Phi->getOperand(i+1).getMBB() != Latch)
1636 continue;
1637
1638 Register PhiReg = Phi->getOperand(i).getReg();
1639 MachineInstr *DI = MRI->getVRegDef(PhiReg);
1640
1641 if (DI->getDesc().isAdd()) {
1642 // If the register operand to the add/sub is the PHI we are looking
1643 // at, this meets the induction pattern.
1644 Register IndReg = DI->getOperand(1).getReg();
1645 MachineOperand &Opnd2 = DI->getOperand(2);
1646 int64_t V;
1647 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
1648 Register UpdReg = DI->getOperand(0).getReg();
1649 IndRegs.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
1650 }
1651 }
1652 } // for (i)
1653 } // for (instr)
1654
1655 if (IndRegs.empty())
1656 return false;
1657
1658 MachineBasicBlock *TB = nullptr, *FB = nullptr;
1659 SmallVector<MachineOperand,2> Cond;
1660 // analyzeBranch returns true if it fails to analyze branch.
1661 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
1662 if (NotAnalyzed || Cond.empty())
1663 return false;
1664
1665 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) {
1666 MachineBasicBlock *LTB = nullptr, *LFB = nullptr;
1667 SmallVector<MachineOperand,2> LCond;
1668 bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false);
1669 if (NotAnalyzed)
1670 return false;
1671
1672 // Since latch is not the exiting block, the latch branch should be an
1673 // unconditional branch to the loop header.
1674 if (TB == Latch)
1675 TB = (LTB == Header) ? LTB : LFB;
1676 else
1677 FB = (LTB == Header) ? LTB : LFB;
1678 }
1679 if (TB != Header) {
1680 if (FB != Header) {
1681 // The latch/exit block does not go back to the header.
1682 return false;
1683 }
1684 // FB is the header (i.e., uncond. jump to branch header)
1685 // In this case, the LoopBody -> TB should not be a back edge otherwise
1686 // it could result in an infinite loop after conversion to hw_loop.
1687 // This case can happen when the Latch has two jumps like this:
1688 // Jmp_c OuterLoopHeader <-- TB
1689 // Jmp InnerLoopHeader <-- FB
1690 if (MDT->dominates(TB, FB))
1691 return false;
1692 }
1693
1694 // Expecting a predicate register as a condition. It won't be a hardware
1695 // predicate register at this point yet, just a vreg.
1696 // HexagonInstrInfo::analyzeBranch for negated branches inserts imm(0)
1697 // into Cond, followed by the predicate register. For non-negated branches
1698 // it's just the register.
1699 unsigned CSz = Cond.size();
1700 if (CSz != 1 && CSz != 2)
1701 return false;
1702
1703 if (!Cond[CSz-1].isReg())
1704 return false;
1705
1706 Register P = Cond[CSz - 1].getReg();
1707 MachineInstr *PredDef = MRI->getVRegDef(P);
1708
1709 if (!PredDef->isCompare())
1710 return false;
1711
1712 SmallSet<unsigned,2> CmpRegs;
1713 MachineOperand *CmpImmOp = nullptr;
1714
1715 // Go over all operands to the compare and look for immediate and register
1716 // operands. Assume that if the compare has a single register use and a
1717 // single immediate operand, then the register is being compared with the
1718 // immediate value.
1719 for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
1720 MachineOperand &MO = PredDef->getOperand(i);
1721 if (MO.isReg()) {
1722 // Skip all implicit references. In one case there was:
1723 // %140 = FCMPUGT32_rr %138, %139, implicit %usr
1724 if (MO.isImplicit())
1725 continue;
1726 if (MO.isUse()) {
1727 if (!isImmediate(MO)) {
1728 CmpRegs.insert(MO.getReg());
1729 continue;
1730 }
1731 // Consider the register to be the "immediate" operand.
1732 if (CmpImmOp)
1733 return false;
1734 CmpImmOp = &MO;
1735 }
1736 } else if (MO.isImm()) {
1737 if (CmpImmOp) // A second immediate argument? Confusing. Bail out.
1738 return false;
1739 CmpImmOp = &MO;
1740 }
1741 }
1742
1743 if (CmpRegs.empty())
1744 return false;
1745
1746 // Check if the compared register follows the order we want. Fix if needed.
1747 for (RegisterInductionSet::iterator I = IndRegs.begin(), E = IndRegs.end();
1748 I != E; ++I) {
1749 // This is a success. If the register used in the comparison is one that
1750 // we have identified as a bumped (updated) induction register, there is
1751 // nothing to do.
1752 if (CmpRegs.count(I->first))
1753 return true;
1754
1755 // Otherwise, if the register being compared comes out of a PHI node,
1756 // and has been recognized as following the induction pattern, and is
1757 // compared against an immediate, we can fix it.
1758 const RegisterBump &RB = I->second;
1759 if (CmpRegs.count(RB.first)) {
1760 if (!CmpImmOp) {
1761 // If both operands to the compare instruction are registers, see if
1762 // it can be changed to use induction register as one of the operands.
1763 MachineInstr *IndI = nullptr;
1764 MachineInstr *nonIndI = nullptr;
1765 MachineOperand *IndMO = nullptr;
1766 MachineOperand *nonIndMO = nullptr;
1767
1768 for (unsigned i = 1, n = PredDef->getNumOperands(); i < n; ++i) {
1769 MachineOperand &MO = PredDef->getOperand(i);
1770 if (MO.isReg() && MO.getReg() == RB.first) {
1771 LLVM_DEBUG(dbgs() << "\n DefMI(" << ido { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\n DefMI(" << i <<
") = " << *(MRI->getVRegDef(I->first)); } } while
(false)
1772 << ") = " << *(MRI->getVRegDef(I->first)))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\n DefMI(" << i <<
") = " << *(MRI->getVRegDef(I->first)); } } while
(false)
;
1773 if (IndI)
1774 return false;
1775
1776 IndI = MRI->getVRegDef(I->first);
1777 IndMO = &MO;
1778 } else if (MO.isReg()) {
1779 LLVM_DEBUG(dbgs() << "\n DefMI(" << ido { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\n DefMI(" << i <<
") = " << *(MRI->getVRegDef(MO.getReg())); } } while
(false)
1780 << ") = " << *(MRI->getVRegDef(MO.getReg())))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\n DefMI(" << i <<
") = " << *(MRI->getVRegDef(MO.getReg())); } } while
(false)
;
1781 if (nonIndI)
1782 return false;
1783
1784 nonIndI = MRI->getVRegDef(MO.getReg());
1785 nonIndMO = &MO;
1786 }
1787 }
1788 if (IndI && nonIndI &&
1789 nonIndI->getOpcode() == Hexagon::A2_addi &&
1790 nonIndI->getOperand(2).isImm() &&
1791 nonIndI->getOperand(2).getImm() == - RB.second) {
1792 bool Order = orderBumpCompare(IndI, PredDef);
1793 if (Order) {
1794 IndMO->setReg(I->first);
1795 nonIndMO->setReg(nonIndI->getOperand(1).getReg());
1796 return true;
1797 }
1798 }
1799 return false;
1800 }
1801
1802 // It is not valid to do this transformation on an unsigned comparison
1803 // because it may underflow.
1804 Comparison::Kind Cmp =
1805 getComparisonKind(PredDef->getOpcode(), nullptr, nullptr, 0);
1806 if (!Cmp || Comparison::isUnsigned(Cmp))
1807 return false;
1808
1809 // If the register is being compared against an immediate, try changing
1810 // the compare instruction to use induction register and adjust the
1811 // immediate operand.
1812 int64_t CmpImm = getImmediate(*CmpImmOp);
1813 int64_t V = RB.second;
1814 // Handle Overflow (64-bit).
1815 if (((V > 0) && (CmpImm > INT64_MAX(9223372036854775807L) - V)) ||
1816 ((V < 0) && (CmpImm < INT64_MIN(-9223372036854775807L -1) - V)))
1817 return false;
1818 CmpImm += V;
1819 // Most comparisons of register against an immediate value allow
1820 // the immediate to be constant-extended. There are some exceptions
1821 // though. Make sure the new combination will work.
1822 if (CmpImmOp->isImm())
1823 if (!isImmValidForOpcode(PredDef->getOpcode(), CmpImm))
1824 return false;
1825
1826 // Make sure that the compare happens after the bump. Otherwise,
1827 // after the fixup, the compare would use a yet-undefined register.
1828 MachineInstr *BumpI = MRI->getVRegDef(I->first);
1829 bool Order = orderBumpCompare(BumpI, PredDef);
1830 if (!Order)
1831 return false;
1832
1833 // Finally, fix the compare instruction.
1834 setImmediate(*CmpImmOp, CmpImm);
1835 for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
1836 MachineOperand &MO = PredDef->getOperand(i);
1837 if (MO.isReg() && MO.getReg() == RB.first) {
1838 MO.setReg(I->first);
1839 return true;
1840 }
1841 }
1842 }
1843 }
1844
1845 return false;
1846}
1847
1848/// createPreheaderForLoop - Create a preheader for a given loop.
1849MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
1850 MachineLoop *L) {
1851 if (MachineBasicBlock *TmpPH = MLI->findLoopPreheader(L, SpecPreheader))
1852 return TmpPH;
1853 if (!HWCreatePreheader)
1854 return nullptr;
1855
1856 MachineBasicBlock *Header = L->getHeader();
1857 MachineBasicBlock *Latch = L->getLoopLatch();
1858 MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
1859 MachineFunction *MF = Header->getParent();
1860 DebugLoc DL;
1861
1862#ifndef NDEBUG
1863 if ((!PHFn.empty()) && (PHFn != MF->getName()))
1864 return nullptr;
1865#endif
1866
1867 if (!Latch || !ExitingBlock || Header->hasAddressTaken())
1868 return nullptr;
1869
1870 using instr_iterator = MachineBasicBlock::instr_iterator;
1871
1872 // Verify that all existing predecessors have analyzable branches
1873 // (or no branches at all).
1874 using MBBVector = std::vector<MachineBasicBlock *>;
1875
1876 MBBVector Preds(Header->pred_begin(), Header->pred_end());
1877 SmallVector<MachineOperand,2> Tmp1;
1878 MachineBasicBlock *TB = nullptr, *FB = nullptr;
1879
1880 if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false))
1881 return nullptr;
1882
1883 for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
1884 MachineBasicBlock *PB = *I;
1885 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false);
1886 if (NotAnalyzed)
1887 return nullptr;
1888 }
1889
1890 MachineBasicBlock *NewPH = MF->CreateMachineBasicBlock();
1891 MF->insert(Header->getIterator(), NewPH);
1892
1893 if (Header->pred_size() > 2) {
1894 // Ensure that the header has only two predecessors: the preheader and
1895 // the loop latch. Any additional predecessors of the header should
1896 // join at the newly created preheader. Inspect all PHI nodes from the
1897 // header and create appropriate corresponding PHI nodes in the preheader.
1898
1899 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1900 I != E && I->isPHI(); ++I) {
1901 MachineInstr *PN = &*I;
1902
1903 const MCInstrDesc &PD = TII->get(TargetOpcode::PHI);
1904 MachineInstr *NewPN = MF->CreateMachineInstr(PD, DL);
1905 NewPH->insert(NewPH->end(), NewPN);
1906
1907 Register PR = PN->getOperand(0).getReg();
1908 const TargetRegisterClass *RC = MRI->getRegClass(PR);
1909 Register NewPR = MRI->createVirtualRegister(RC);
1910 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true));
1911
1912 // Copy all non-latch operands of a header's PHI node to the newly
1913 // created PHI node in the preheader.
1914 for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
1915 Register PredR = PN->getOperand(i).getReg();
1916 unsigned PredRSub = PN->getOperand(i).getSubReg();
1917 MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
1918 if (PredB == Latch)
1919 continue;
1920
1921 MachineOperand MO = MachineOperand::CreateReg(PredR, false);
1922 MO.setSubReg(PredRSub);
1923 NewPN->addOperand(MO);
1924 NewPN->addOperand(MachineOperand::CreateMBB(PredB));
1925 }
1926
1927 // Remove copied operands from the old PHI node and add the value
1928 // coming from the preheader's PHI.
1929 for (int i = PN->getNumOperands()-2; i > 0; i -= 2) {
1930 MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
1931 if (PredB != Latch) {
1932 PN->RemoveOperand(i+1);
1933 PN->RemoveOperand(i);
1934 }
1935 }
1936 PN->addOperand(MachineOperand::CreateReg(NewPR, false));
1937 PN->addOperand(MachineOperand::CreateMBB(NewPH));
1938 }
1939 } else {
1940 assert(Header->pred_size() == 2)((Header->pred_size() == 2) ? static_cast<void> (0) :
__assert_fail ("Header->pred_size() == 2", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1940, __PRETTY_FUNCTION__))
;
1941
1942 // The header has only two predecessors, but the non-latch predecessor
1943 // is not a preheader (e.g. it has other successors, etc.)
1944 // In such a case we don't need any extra PHI nodes in the new preheader,
1945 // all we need is to adjust existing PHIs in the header to now refer to
1946 // the new preheader.
1947 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1948 I != E && I->isPHI(); ++I) {
1949 MachineInstr *PN = &*I;
1950 for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
1951 MachineOperand &MO = PN->getOperand(i+1);
1952 if (MO.getMBB() != Latch)
1953 MO.setMBB(NewPH);
1954 }
1955 }
1956 }
1957
1958 // "Reroute" the CFG edges to link in the new preheader.
1959 // If any of the predecessors falls through to the header, insert a branch
1960 // to the new preheader in that place.
1961 SmallVector<MachineOperand,1> Tmp2;
1962 SmallVector<MachineOperand,1> EmptyCond;
1963
1964 TB = FB = nullptr;
1965
1966 for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
1967 MachineBasicBlock *PB = *I;
1968 if (PB != Latch) {
1969 Tmp2.clear();
1970 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false);
1971 (void)NotAnalyzed; // suppress compiler warning
1972 assert (!NotAnalyzed && "Should be analyzable!")((!NotAnalyzed && "Should be analyzable!") ? static_cast
<void> (0) : __assert_fail ("!NotAnalyzed && \"Should be analyzable!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1972, __PRETTY_FUNCTION__))
;
1973 if (TB != Header && (Tmp2.empty() || FB != Header))
1974 TII->insertBranch(*PB, NewPH, nullptr, EmptyCond, DL);
1975 PB->ReplaceUsesOfBlockWith(Header, NewPH);
1976 }
1977 }
1978
1979 // It can happen that the latch block will fall through into the header.
1980 // Insert an unconditional branch to the header.
1981 TB = FB = nullptr;
1982 bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false);
1983 (void)LatchNotAnalyzed; // suppress compiler warning
1984 assert (!LatchNotAnalyzed && "Should be analyzable!")((!LatchNotAnalyzed && "Should be analyzable!") ? static_cast
<void> (0) : __assert_fail ("!LatchNotAnalyzed && \"Should be analyzable!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1984, __PRETTY_FUNCTION__))
;
1985 if (!TB && !FB)
1986 TII->insertBranch(*Latch, Header, nullptr, EmptyCond, DL);
1987
1988 // Finally, the branch from the preheader to the header.
1989 TII->insertBranch(*NewPH, Header, nullptr, EmptyCond, DL);
1990 NewPH->addSuccessor(Header);
1991
1992 MachineLoop *ParentLoop = L->getParentLoop();
1993 if (ParentLoop)
1994 ParentLoop->addBasicBlockToLoop(NewPH, MLI->getBase());
1995
1996 // Update the dominator information with the new preheader.
1997 if (MDT) {
1998 if (MachineDomTreeNode *HN = MDT->getNode(Header)) {
1999 if (MachineDomTreeNode *DHN = HN->getIDom()) {
2000 MDT->addNewBlock(NewPH, DHN->getBlock());
2001 MDT->changeImmediateDominator(Header, NewPH);
2002 }
2003 }
2004 }
2005
2006 return NewPH;
2007}

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h

1//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineOperand class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEOPERAND_H
14#define LLVM_CODEGEN_MACHINEOPERAND_H
15
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/CodeGen/Register.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/DataTypes.h"
20#include "llvm/Support/LowLevelTypeImpl.h"
21#include <cassert>
22
23namespace llvm {
24
25class BlockAddress;
26class Constant;
27class ConstantFP;
28class ConstantInt;
29class GlobalValue;
30class MachineBasicBlock;
31class MachineInstr;
32class MachineRegisterInfo;
33class MCCFIInstruction;
34class MDNode;
35class ModuleSlotTracker;
36class TargetMachine;
37class TargetIntrinsicInfo;
38class TargetRegisterInfo;
39class hash_code;
40class raw_ostream;
41class MCSymbol;
42
43/// MachineOperand class - Representation of each machine instruction operand.
44///
45/// This class isn't a POD type because it has a private constructor, but its
46/// destructor must be trivial. Functions like MachineInstr::addOperand(),
47/// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
48/// not having to call the MachineOperand destructor.
49///
50class MachineOperand {
51public:
52 enum MachineOperandType : unsigned char {
53 MO_Register, ///< Register operand.
54 MO_Immediate, ///< Immediate operand
55 MO_CImmediate, ///< Immediate >64bit operand
56 MO_FPImmediate, ///< Floating-point immediate operand
57 MO_MachineBasicBlock, ///< MachineBasicBlock reference
58 MO_FrameIndex, ///< Abstract Stack Frame Index
59 MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
60 MO_TargetIndex, ///< Target-dependent index+offset operand.
61 MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
62 MO_ExternalSymbol, ///< Name of external global symbol
63 MO_GlobalAddress, ///< Address of a global value
64 MO_BlockAddress, ///< Address of a basic block
65 MO_RegisterMask, ///< Mask of preserved registers.
66 MO_RegisterLiveOut, ///< Mask of live-out registers.
67 MO_Metadata, ///< Metadata reference (for debug info)
68 MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
69 MO_CFIIndex, ///< MCCFIInstruction index.
70 MO_IntrinsicID, ///< Intrinsic ID for ISel
71 MO_Predicate, ///< Generic predicate for ISel
72 MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
73 MO_Last = MO_ShuffleMask
74 };
75
76private:
77 /// OpKind - Specify what kind of operand this is. This discriminates the
78 /// union.
79 unsigned OpKind : 8;
80
81 /// Subregister number for MO_Register. A value of 0 indicates the
82 /// MO_Register has no subReg.
83 ///
84 /// For all other kinds of operands, this field holds target-specific flags.
85 unsigned SubReg_TargetFlags : 12;
86
87 /// TiedTo - Non-zero when this register operand is tied to another register
88 /// operand. The encoding of this field is described in the block comment
89 /// before MachineInstr::tieOperands().
90 unsigned TiedTo : 4;
91
92 /// IsDef - True if this is a def, false if this is a use of the register.
93 /// This is only valid on register operands.
94 ///
95 unsigned IsDef : 1;
96
97 /// IsImp - True if this is an implicit def or use, false if it is explicit.
98 /// This is only valid on register opderands.
99 ///
100 unsigned IsImp : 1;
101
102 /// IsDeadOrKill
103 /// For uses: IsKill - True if this instruction is the last use of the
104 /// register on this path through the function.
105 /// For defs: IsDead - True if this register is never used by a subsequent
106 /// instruction.
107 /// This is only valid on register operands.
108 unsigned IsDeadOrKill : 1;
109
110 /// See isRenamable().
111 unsigned IsRenamable : 1;
112
113 /// IsUndef - True if this register operand reads an "undef" value, i.e. the
114 /// read value doesn't matter. This flag can be set on both use and def
115 /// operands. On a sub-register def operand, it refers to the part of the
116 /// register that isn't written. On a full-register def operand, it is a
117 /// noop. See readsReg().
118 ///
119 /// This is only valid on registers.
120 ///
121 /// Note that an instruction may have multiple <undef> operands referring to
122 /// the same register. In that case, the instruction may depend on those
123 /// operands reading the same dont-care value. For example:
124 ///
125 /// %1 = XOR undef %2, undef %2
126 ///
127 /// Any register can be used for %2, and its value doesn't matter, but
128 /// the two operands must be the same register.
129 ///
130 unsigned IsUndef : 1;
131
132 /// IsInternalRead - True if this operand reads a value that was defined
133 /// inside the same instruction or bundle. This flag can be set on both use
134 /// and def operands. On a sub-register def operand, it refers to the part
135 /// of the register that isn't written. On a full-register def operand, it
136 /// is a noop.
137 ///
138 /// When this flag is set, the instruction bundle must contain at least one
139 /// other def of the register. If multiple instructions in the bundle define
140 /// the register, the meaning is target-defined.
141 unsigned IsInternalRead : 1;
142
143 /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
144 /// by the MachineInstr before all input registers are read. This is used to
145 /// model the GCC inline asm '&' constraint modifier.
146 unsigned IsEarlyClobber : 1;
147
148 /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
149 /// not a real instruction. Such uses should be ignored during codegen.
150 unsigned IsDebug : 1;
151
152 /// SmallContents - This really should be part of the Contents union, but
153 /// lives out here so we can get a better packed struct.
154 /// MO_Register: Register number.
155 /// OffsetedInfo: Low bits of offset.
156 union {
157 unsigned RegNo; // For MO_Register.
158 unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
159 } SmallContents;
160
161 /// ParentMI - This is the instruction that this operand is embedded into.
162 /// This is valid for all operand types, when the operand is in an instr.
163 MachineInstr *ParentMI;
164
165 /// Contents union - This contains the payload for the various operand types.
166 union ContentsUnion {
167 ContentsUnion() {}
168 MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
169 const ConstantFP *CFP; // For MO_FPImmediate.
170 const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
171 int64_t ImmVal; // For MO_Immediate.
172 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
173 const MDNode *MD; // For MO_Metadata.
174 MCSymbol *Sym; // For MO_MCSymbol.
175 unsigned CFIIndex; // For MO_CFI.
176 Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
177 unsigned Pred; // For MO_Predicate
178 ArrayRef<int> ShuffleMask; // For MO_ShuffleMask
179
180 struct { // For MO_Register.
181 // Register number is in SmallContents.RegNo.
182 MachineOperand *Prev; // Access list for register. See MRI.
183 MachineOperand *Next;
184 } Reg;
185
186 /// OffsetedInfo - This struct contains the offset and an object identifier.
187 /// this represent the object as with an optional offset from it.
188 struct {
189 union {
190 int Index; // For MO_*Index - The index itself.
191 const char *SymbolName; // For MO_ExternalSymbol.
192 const GlobalValue *GV; // For MO_GlobalAddress.
193 const BlockAddress *BA; // For MO_BlockAddress.
194 } Val;
195 // Low bits of offset are in SmallContents.OffsetLo.
196 int OffsetHi; // An offset from the object, high 32 bits.
197 } OffsetedInfo;
198 } Contents;
199
200 explicit MachineOperand(MachineOperandType K)
201 : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
202 // Assert that the layout is what we expect. It's easy to grow this object.
203 static_assert(alignof(MachineOperand) <= alignof(int64_t),
204 "MachineOperand shouldn't be more than 8 byte aligned");
205 static_assert(sizeof(Contents) <= 2 * sizeof(void *),
206 "Contents should be at most two pointers");
207 static_assert(sizeof(MachineOperand) <=
208 alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
209 3 * sizeof(void *)),
210 "MachineOperand too big. Should be Kind, SmallContents, "
211 "ParentMI, and Contents");
212 }
213
214public:
215 /// getType - Returns the MachineOperandType for this operand.
216 ///
217 MachineOperandType getType() const { return (MachineOperandType)OpKind; }
218
219 unsigned getTargetFlags() const {
220 return isReg() ? 0 : SubReg_TargetFlags;
221 }
222 void setTargetFlags(unsigned F) {
223 assert(!isReg() && "Register operands can't have target flags")((!isReg() && "Register operands can't have target flags"
) ? static_cast<void> (0) : __assert_fail ("!isReg() && \"Register operands can't have target flags\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 223, __PRETTY_FUNCTION__))
;
224 SubReg_TargetFlags = F;
225 assert(SubReg_TargetFlags == F && "Target flags out of range")((SubReg_TargetFlags == F && "Target flags out of range"
) ? static_cast<void> (0) : __assert_fail ("SubReg_TargetFlags == F && \"Target flags out of range\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 225, __PRETTY_FUNCTION__))
;
226 }
227 void addTargetFlag(unsigned F) {
228 assert(!isReg() && "Register operands can't have target flags")((!isReg() && "Register operands can't have target flags"
) ? static_cast<void> (0) : __assert_fail ("!isReg() && \"Register operands can't have target flags\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 228, __PRETTY_FUNCTION__))
;
229 SubReg_TargetFlags |= F;
230 assert((SubReg_TargetFlags & F) && "Target flags out of range")(((SubReg_TargetFlags & F) && "Target flags out of range"
) ? static_cast<void> (0) : __assert_fail ("(SubReg_TargetFlags & F) && \"Target flags out of range\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 230, __PRETTY_FUNCTION__))
;
231 }
232
233
234 /// getParent - Return the instruction that this operand belongs to.
235 ///
236 MachineInstr *getParent() { return ParentMI; }
237 const MachineInstr *getParent() const { return ParentMI; }
238
239 /// clearParent - Reset the parent pointer.
240 ///
241 /// The MachineOperand copy constructor also copies ParentMI, expecting the
242 /// original to be deleted. If a MachineOperand is ever stored outside a
243 /// MachineInstr, the parent pointer must be cleared.
244 ///
245 /// Never call clearParent() on an operand in a MachineInstr.
246 ///
247 void clearParent() { ParentMI = nullptr; }
248
249 /// Print a subreg index operand.
250 /// MO_Immediate operands can also be subreg idices. If it's the case, the
251 /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
252 /// called to check this.
253 static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
254 const TargetRegisterInfo *TRI);
255
256 /// Print operand target flags.
257 static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
258
259 /// Print a MCSymbol as an operand.
260 static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
261
262 /// Print a stack object reference.
263 static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
264 bool IsFixed, StringRef Name);
265
266 /// Print the offset with explicit +/- signs.
267 static void printOperandOffset(raw_ostream &OS, int64_t Offset);
268
269 /// Print an IRSlotNumber.
270 static void printIRSlotNumber(raw_ostream &OS, int Slot);
271
272 /// Print the MachineOperand to \p os.
273 /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
274 /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
275 /// function will try to pick it up from the parent.
276 void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
277 const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
278
279 /// More complex way of printing a MachineOperand.
280 /// \param TypeToPrint specifies the generic type to be printed on uses and
281 /// defs. It can be determined using MachineInstr::getTypeToPrint.
282 /// \param OpIdx - specifies the index of the operand in machine instruction.
283 /// This will be used by target dependent MIR formatter. Could be None if the
284 /// index is unknown, e.g. called by dump().
285 /// \param PrintDef - whether we want to print `def` on an operand which
286 /// isDef. Sometimes, if the operand is printed before '=', we don't print
287 /// `def`.
288 /// \param IsStandalone - whether we want a verbose output of the MO. This
289 /// prints extra information that can be easily inferred when printing the
290 /// whole function, but not when printing only a fragment of it.
291 /// \param ShouldPrintRegisterTies - whether we want to print register ties.
292 /// Sometimes they are easily determined by the instruction's descriptor
293 /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
294 /// \param TiedOperandIdx - if we need to print register ties this needs to
295 /// provide the index of the tied register. If not, it will be ignored.
296 /// \param TRI - provide more target-specific information to the printer.
297 /// Unlike the previous function, this one will not try and get the
298 /// information from it's parent.
299 /// \param IntrinsicInfo - same as \p TRI.
300 void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
301 Optional<unsigned> OpIdx, bool PrintDef, bool IsStandalone,
302 bool ShouldPrintRegisterTies, unsigned TiedOperandIdx,
303 const TargetRegisterInfo *TRI,
304 const TargetIntrinsicInfo *IntrinsicInfo) const;
305
306 /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
307 /// type to be printed the same way the full version of print(...) does it.
308 void print(raw_ostream &os, LLT TypeToPrint,
309 const TargetRegisterInfo *TRI = nullptr,
310 const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
311
312 void dump() const;
313
314 //===--------------------------------------------------------------------===//
315 // Accessors that tell you what kind of MachineOperand you're looking at.
316 //===--------------------------------------------------------------------===//
317
318 /// isReg - Tests if this is a MO_Register operand.
319 bool isReg() const { return OpKind
5.1
Field 'OpKind' is not equal to MO_Register
13.1
Field 'OpKind' is not equal to MO_Register
5.1
Field 'OpKind' is not equal to MO_Register
13.1
Field 'OpKind' is not equal to MO_Register
== MO_Register
; }
6
Returning zero, which participates in a condition later
14
Returning zero, which participates in a condition later
29
Returning zero, which participates in a condition later
320 /// isImm - Tests if this is a MO_Immediate operand.
321 bool isImm() const { return OpKind == MO_Immediate; }
9
Assuming field 'OpKind' is equal to MO_Immediate
10
Returning the value 1, which participates in a condition later
17
Assuming field 'OpKind' is equal to MO_Immediate
18
Returning the value 1, which participates in a condition later
36
Returning the value 1, which participates in a condition later
39
Returning the value 1, which participates in a condition later
322 /// isCImm - Test if this is a MO_CImmediate operand.
323 bool isCImm() const { return OpKind == MO_CImmediate; }
324 /// isFPImm - Tests if this is a MO_FPImmediate operand.
325 bool isFPImm() const { return OpKind == MO_FPImmediate; }
326 /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
327 bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
328 /// isFI - Tests if this is a MO_FrameIndex operand.
329 bool isFI() const { return OpKind == MO_FrameIndex; }
330 /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
331 bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
332 /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
333 bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
334 /// isJTI - Tests if this is a MO_JumpTableIndex operand.
335 bool isJTI() const { return OpKind == MO_JumpTableIndex; }
336 /// isGlobal - Tests if this is a MO_GlobalAddress operand.
337 bool isGlobal() const { return OpKind == MO_GlobalAddress; }
338 /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
339 bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
340 /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
341 bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
342 /// isRegMask - Tests if this is a MO_RegisterMask operand.
343 bool isRegMask() const { return OpKind == MO_RegisterMask; }
344 /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
345 bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
346 /// isMetadata - Tests if this is a MO_Metadata operand.
347 bool isMetadata() const { return OpKind == MO_Metadata; }
348 bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
349 bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
350 bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
351 bool isPredicate() const { return OpKind == MO_Predicate; }
352 bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
353 //===--------------------------------------------------------------------===//
354 // Accessors for Register Operands
355 //===--------------------------------------------------------------------===//
356
357 /// getReg - Returns the register number.
358 Register getReg() const {
359 assert(isReg() && "This is not a register operand!")((isReg() && "This is not a register operand!") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"This is not a register operand!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 359, __PRETTY_FUNCTION__))
;
360 return Register(SmallContents.RegNo);
361 }
362
363 unsigned getSubReg() const {
364 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 364, __PRETTY_FUNCTION__))
;
365 return SubReg_TargetFlags;
366 }
367
368 bool isUse() const {
369 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 369, __PRETTY_FUNCTION__))
;
370 return !IsDef;
371 }
372
373 bool isDef() const {
374 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 374, __PRETTY_FUNCTION__))
;
375 return IsDef;
376 }
377
378 bool isImplicit() const {
379 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 379, __PRETTY_FUNCTION__))
;
380 return IsImp;
381 }
382
383 bool isDead() const {
384 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 384, __PRETTY_FUNCTION__))
;
385 return IsDeadOrKill & IsDef;
386 }
387
388 bool isKill() const {
389 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 389, __PRETTY_FUNCTION__))
;
390 return IsDeadOrKill & !IsDef;
391 }
392
393 bool isUndef() const {
394 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 394, __PRETTY_FUNCTION__))
;
395 return IsUndef;
396 }
397
398 /// isRenamable - Returns true if this register may be renamed, i.e. it does
399 /// not generate a value that is somehow read in a way that is not represented
400 /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
401 /// valid on physical register operands. Virtual registers are assumed to
402 /// always be renamable regardless of the value of this field.
403 ///
404 /// Operands that are renamable can freely be changed to any other register
405 /// that is a member of the register class returned by
406 /// MI->getRegClassConstraint().
407 ///
408 /// isRenamable can return false for several different reasons:
409 ///
410 /// - ABI constraints (since liveness is not always precisely modeled). We
411 /// conservatively handle these cases by setting all physical register
412 /// operands that didn’t start out as virtual regs to not be renamable.
413 /// Also any physical register operands created after register allocation or
414 /// whose register is changed after register allocation will not be
415 /// renamable. This state is tracked in the MachineOperand::IsRenamable
416 /// bit.
417 ///
418 /// - Opcode/target constraints: for opcodes that have complex register class
419 /// requirements (e.g. that depend on other operands/instructions), we set
420 /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
421 /// description. Operands belonging to instructions with opcodes that are
422 /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
423 /// isRenamable(). Additionally, the AllowRegisterRenaming target property
424 /// prevents any operands from being marked renamable for targets that don't
425 /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
426 /// values.
427 bool isRenamable() const;
428
429 bool isInternalRead() const {
430 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 430, __PRETTY_FUNCTION__))
;
431 return IsInternalRead;
432 }
433
434 bool isEarlyClobber() const {
435 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 435, __PRETTY_FUNCTION__))
;
436 return IsEarlyClobber;
437 }
438
439 bool isTied() const {
440 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 440, __PRETTY_FUNCTION__))
;
441 return TiedTo;
442 }
443
444 bool isDebug() const {
445 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 445, __PRETTY_FUNCTION__))
;
446 return IsDebug;
447 }
448
449 /// readsReg - Returns true if this operand reads the previous value of its
450 /// register. A use operand with the <undef> flag set doesn't read its
451 /// register. A sub-register def implicitly reads the other parts of the
452 /// register being redefined unless the <undef> flag is set.
453 ///
454 /// This refers to reading the register value from before the current
455 /// instruction or bundle. Internal bundle reads are not included.
456 bool readsReg() const {
457 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 457, __PRETTY_FUNCTION__))
;
458 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
459 }
460
461 //===--------------------------------------------------------------------===//
462 // Mutators for Register Operands
463 //===--------------------------------------------------------------------===//
464
465 /// Change the register this operand corresponds to.
466 ///
467 void setReg(Register Reg);
468
469 void setSubReg(unsigned subReg) {
470 assert(isReg() && "Wrong MachineOperand mutator")((isReg() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 470, __PRETTY_FUNCTION__))
;
471 SubReg_TargetFlags = subReg;
472 assert(SubReg_TargetFlags == subReg && "SubReg out of range")((SubReg_TargetFlags == subReg && "SubReg out of range"
) ? static_cast<void> (0) : __assert_fail ("SubReg_TargetFlags == subReg && \"SubReg out of range\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 472, __PRETTY_FUNCTION__))
;
473 }
474
475 /// substVirtReg - Substitute the current register with the virtual
476 /// subregister Reg:SubReg. Take any existing SubReg index into account,
477 /// using TargetRegisterInfo to compose the subreg indices if necessary.
478 /// Reg must be a virtual register, SubIdx can be 0.
479 ///
480 void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
481
482 /// substPhysReg - Substitute the current register with the physical register
483 /// Reg, taking any existing SubReg into account. For instance,
484 /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
485 ///
486 void substPhysReg(MCRegister Reg, const TargetRegisterInfo&);
487
488 void setIsUse(bool Val = true) { setIsDef(!Val); }
489
490 /// Change a def to a use, or a use to a def.
491 void setIsDef(bool Val = true);
492
493 void setImplicit(bool Val = true) {
494 assert(isReg() && "Wrong MachineOperand mutator")((isReg() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 494, __PRETTY_FUNCTION__))
;
495 IsImp = Val;
496 }
497
498 void setIsKill(bool Val = true) {
499 assert(isReg() && !IsDef && "Wrong MachineOperand mutator")((isReg() && !IsDef && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("isReg() && !IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 499, __PRETTY_FUNCTION__))
;
500 assert((!Val || !isDebug()) && "Marking a debug operation as kill")(((!Val || !isDebug()) && "Marking a debug operation as kill"
) ? static_cast<void> (0) : __assert_fail ("(!Val || !isDebug()) && \"Marking a debug operation as kill\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 500, __PRETTY_FUNCTION__))
;
501 IsDeadOrKill = Val;
502 }
503
504 void setIsDead(bool Val = true) {
505 assert(isReg() && IsDef && "Wrong MachineOperand mutator")((isReg() && IsDef && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("isReg() && IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 505, __PRETTY_FUNCTION__))
;
506 IsDeadOrKill = Val;
507 }
508
509 void setIsUndef(bool Val = true) {
510 assert(isReg() && "Wrong MachineOperand mutator")((isReg() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 510, __PRETTY_FUNCTION__))
;
511 IsUndef = Val;
512 }
513
514 void setIsRenamable(bool Val = true);
515
516 void setIsInternalRead(bool Val = true) {
517 assert(isReg() && "Wrong MachineOperand mutator")((isReg() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 517, __PRETTY_FUNCTION__))
;
518 IsInternalRead = Val;
519 }
520
521 void setIsEarlyClobber(bool Val = true) {
522 assert(isReg() && IsDef && "Wrong MachineOperand mutator")((isReg() && IsDef && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("isReg() && IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 522, __PRETTY_FUNCTION__))
;
523 IsEarlyClobber = Val;
524 }
525
526 void setIsDebug(bool Val = true) {
527 assert(isReg() && !IsDef && "Wrong MachineOperand mutator")((isReg() && !IsDef && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("isReg() && !IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 527, __PRETTY_FUNCTION__))
;
528 IsDebug = Val;
529 }
530
531 //===--------------------------------------------------------------------===//
532 // Accessors for various operand types.
533 //===--------------------------------------------------------------------===//
534
535 int64_t getImm() const {
536 assert(isImm() && "Wrong MachineOperand accessor")((isImm() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isImm() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 536, __PRETTY_FUNCTION__))
;
537 return Contents.ImmVal;
538 }
539
540 const ConstantInt *getCImm() const {
541 assert(isCImm() && "Wrong MachineOperand accessor")((isCImm() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isCImm() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 541, __PRETTY_FUNCTION__))
;
542 return Contents.CI;
543 }
544
545 const ConstantFP *getFPImm() const {
546 assert(isFPImm() && "Wrong MachineOperand accessor")((isFPImm() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isFPImm() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 546, __PRETTY_FUNCTION__))
;
547 return Contents.CFP;
548 }
549
550 MachineBasicBlock *getMBB() const {
551 assert(isMBB() && "Wrong MachineOperand accessor")((isMBB() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isMBB() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 551, __PRETTY_FUNCTION__))
;
552 return Contents.MBB;
553 }
554
555 int getIndex() const {
556 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&(((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
"Wrong MachineOperand accessor") ? static_cast<void> (
0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 557, __PRETTY_FUNCTION__))
557 "Wrong MachineOperand accessor")(((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
"Wrong MachineOperand accessor") ? static_cast<void> (
0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 557, __PRETTY_FUNCTION__))
;
558 return Contents.OffsetedInfo.Val.Index;
559 }
560
561 const GlobalValue *getGlobal() const {
562 assert(isGlobal() && "Wrong MachineOperand accessor")((isGlobal() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isGlobal() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 562, __PRETTY_FUNCTION__))
;
563 return Contents.OffsetedInfo.Val.GV;
564 }
565
566 const BlockAddress *getBlockAddress() const {
567 assert(isBlockAddress() && "Wrong MachineOperand accessor")((isBlockAddress() && "Wrong MachineOperand accessor"
) ? static_cast<void> (0) : __assert_fail ("isBlockAddress() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 567, __PRETTY_FUNCTION__))
;
568 return Contents.OffsetedInfo.Val.BA;
569 }
570
571 MCSymbol *getMCSymbol() const {
572 assert(isMCSymbol() && "Wrong MachineOperand accessor")((isMCSymbol() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isMCSymbol() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 572, __PRETTY_FUNCTION__))
;
573 return Contents.Sym;
574 }
575
576 unsigned getCFIIndex() const {
577 assert(isCFIIndex() && "Wrong MachineOperand accessor")((isCFIIndex() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isCFIIndex() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 577, __PRETTY_FUNCTION__))
;
578 return Contents.CFIIndex;
579 }
580
581 Intrinsic::ID getIntrinsicID() const {
582 assert(isIntrinsicID() && "Wrong MachineOperand accessor")((isIntrinsicID() && "Wrong MachineOperand accessor")
? static_cast<void> (0) : __assert_fail ("isIntrinsicID() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 582, __PRETTY_FUNCTION__))
;
583 return Contents.IntrinsicID;
584 }
585
586 unsigned getPredicate() const {
587 assert(isPredicate() && "Wrong MachineOperand accessor")((isPredicate() && "Wrong MachineOperand accessor") ?
static_cast<void> (0) : __assert_fail ("isPredicate() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 587, __PRETTY_FUNCTION__))
;
588 return Contents.Pred;
589 }
590
591 ArrayRef<int> getShuffleMask() const {
592 assert(isShuffleMask() && "Wrong MachineOperand accessor")((isShuffleMask() && "Wrong MachineOperand accessor")
? static_cast<void> (0) : __assert_fail ("isShuffleMask() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 592, __PRETTY_FUNCTION__))
;
593 return Contents.ShuffleMask;
594 }
595
596 /// Return the offset from the symbol in this operand. This always returns 0
597 /// for ExternalSymbol operands.
598 int64_t getOffset() const {
599 assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand accessor"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 601, __PRETTY_FUNCTION__))
600 isTargetIndex() || isBlockAddress()) &&(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand accessor"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 601, __PRETTY_FUNCTION__))
601 "Wrong MachineOperand accessor")(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand accessor"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 601, __PRETTY_FUNCTION__))
;
602 return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
603 SmallContents.OffsetLo;
604 }
605
606 const char *getSymbolName() const {
607 assert(isSymbol() && "Wrong MachineOperand accessor")((isSymbol() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isSymbol() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 607, __PRETTY_FUNCTION__))
;
608 return Contents.OffsetedInfo.Val.SymbolName;
609 }
610
611 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
612 /// It is sometimes necessary to detach the register mask pointer from its
613 /// machine operand. This static method can be used for such detached bit
614 /// mask pointers.
615 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
616 // See TargetRegisterInfo.h.
617 assert(PhysReg < (1u << 30) && "Not a physical register")((PhysReg < (1u << 30) && "Not a physical register"
) ? static_cast<void> (0) : __assert_fail ("PhysReg < (1u << 30) && \"Not a physical register\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 617, __PRETTY_FUNCTION__))
;
618 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
619 }
620
621 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
622 bool clobbersPhysReg(unsigned PhysReg) const {
623 return clobbersPhysReg(getRegMask(), PhysReg);
624 }
625
626 /// getRegMask - Returns a bit mask of registers preserved by this RegMask
627 /// operand.
628 const uint32_t *getRegMask() const {
629 assert(isRegMask() && "Wrong MachineOperand accessor")((isRegMask() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isRegMask() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 629, __PRETTY_FUNCTION__))
;
630 return Contents.RegMask;
631 }
632
633 /// Returns number of elements needed for a regmask array.
634 static unsigned getRegMaskSize(unsigned NumRegs) {
635 return (NumRegs + 31) / 32;
636 }
637
638 /// getRegLiveOut - Returns a bit mask of live-out registers.
639 const uint32_t *getRegLiveOut() const {
640 assert(isRegLiveOut() && "Wrong MachineOperand accessor")((isRegLiveOut() && "Wrong MachineOperand accessor") ?
static_cast<void> (0) : __assert_fail ("isRegLiveOut() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 640, __PRETTY_FUNCTION__))
;
641 return Contents.RegMask;
642 }
643
644 const MDNode *getMetadata() const {
645 assert(isMetadata() && "Wrong MachineOperand accessor")((isMetadata() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isMetadata() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 645, __PRETTY_FUNCTION__))
;
646 return Contents.MD;
647 }
648
649 //===--------------------------------------------------------------------===//
650 // Mutators for various operand types.
651 //===--------------------------------------------------------------------===//
652
653 void setImm(int64_t immVal) {
654 assert(isImm() && "Wrong MachineOperand mutator")((isImm() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isImm() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 654, __PRETTY_FUNCTION__))
;
655 Contents.ImmVal = immVal;
656 }
657
658 void setCImm(const ConstantInt *CI) {
659 assert(isCImm() && "Wrong MachineOperand mutator")((isCImm() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isCImm() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 659, __PRETTY_FUNCTION__))
;
660 Contents.CI = CI;
661 }
662
663 void setFPImm(const ConstantFP *CFP) {
664 assert(isFPImm() && "Wrong MachineOperand mutator")((isFPImm() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isFPImm() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 664, __PRETTY_FUNCTION__))
;
665 Contents.CFP = CFP;
666 }
667
668 void setOffset(int64_t Offset) {
669 assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 671, __PRETTY_FUNCTION__))
670 isTargetIndex() || isBlockAddress()) &&(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 671, __PRETTY_FUNCTION__))
671 "Wrong MachineOperand mutator")(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 671, __PRETTY_FUNCTION__))
;
672 SmallContents.OffsetLo = unsigned(Offset);
673 Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
674 }
675
676 void setIndex(int Idx) {
677 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&(((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
"Wrong MachineOperand mutator") ? static_cast<void> (0
) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 678, __PRETTY_FUNCTION__))
678 "Wrong MachineOperand mutator")(((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
"Wrong MachineOperand mutator") ? static_cast<void> (0
) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 678, __PRETTY_FUNCTION__))
;
679 Contents.OffsetedInfo.Val.Index = Idx;
680 }
681
682 void setMetadata(const MDNode *MD) {
683 assert(isMetadata() && "Wrong MachineOperand mutator")((isMetadata() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isMetadata() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 683, __PRETTY_FUNCTION__))
;
684 Contents.MD = MD;
685 }
686
687 void setMBB(MachineBasicBlock *MBB) {
688 assert(isMBB() && "Wrong MachineOperand mutator")((isMBB() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isMBB() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 688, __PRETTY_FUNCTION__))
;
689 Contents.MBB = MBB;
690 }
691
692 /// Sets value of register mask operand referencing Mask. The
693 /// operand does not take ownership of the memory referenced by Mask, it must
694 /// remain valid for the lifetime of the operand. See CreateRegMask().
695 /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
696 void setRegMask(const uint32_t *RegMaskPtr) {
697 assert(isRegMask() && "Wrong MachineOperand mutator")((isRegMask() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isRegMask() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 697, __PRETTY_FUNCTION__))
;
698 Contents.RegMask = RegMaskPtr;
699 }
700
701 void setPredicate(unsigned Predicate) {
702 assert(isPredicate() && "Wrong MachineOperand mutator")((isPredicate() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isPredicate() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 702, __PRETTY_FUNCTION__))
;
703 Contents.Pred = Predicate;
704 }
705
706 //===--------------------------------------------------------------------===//
707 // Other methods.
708 //===--------------------------------------------------------------------===//
709
710 /// Returns true if this operand is identical to the specified operand except
711 /// for liveness related flags (isKill, isUndef and isDead). Note that this
712 /// should stay in sync with the hash_value overload below.
713 bool isIdenticalTo(const MachineOperand &Other) const;
714
715 /// MachineOperand hash_value overload.
716 ///
717 /// Note that this includes the same information in the hash that
718 /// isIdenticalTo uses for comparison. It is thus suited for use in hash
719 /// tables which use that function for equality comparisons only. This must
720 /// stay exactly in sync with isIdenticalTo above.
721 friend hash_code hash_value(const MachineOperand &MO);
722
723 /// ChangeToImmediate - Replace this operand with a new immediate operand of
724 /// the specified value. If an operand is known to be an immediate already,
725 /// the setImm method should be used.
726 void ChangeToImmediate(int64_t ImmVal);
727
728 /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
729 /// of the specified value. If an operand is known to be an FP immediate
730 /// already, the setFPImm method should be used.
731 void ChangeToFPImmediate(const ConstantFP *FPImm);
732
733 /// ChangeToES - Replace this operand with a new external symbol operand.
734 void ChangeToES(const char *SymName, unsigned TargetFlags = 0);
735
736 /// ChangeToGA - Replace this operand with a new global address operand.
737 void ChangeToGA(const GlobalValue *GV, int64_t Offset,
738 unsigned TargetFlags = 0);
739
740 /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
741 void ChangeToMCSymbol(MCSymbol *Sym);
742
743 /// Replace this operand with a frame index.
744 void ChangeToFrameIndex(int Idx);
745
746 /// Replace this operand with a target index.
747 void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
748 unsigned TargetFlags = 0);
749
750 /// ChangeToRegister - Replace this operand with a new register operand of
751 /// the specified value. If an operand is known to be an register already,
752 /// the setReg method should be used.
753 void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
754 bool isKill = false, bool isDead = false,
755 bool isUndef = false, bool isDebug = false);
756
757 //===--------------------------------------------------------------------===//
758 // Construction methods.
759 //===--------------------------------------------------------------------===//
760
761 static MachineOperand CreateImm(int64_t Val) {
762 MachineOperand Op(MachineOperand::MO_Immediate);
763 Op.setImm(Val);
764 return Op;
765 }
766
767 static MachineOperand CreateCImm(const ConstantInt *CI) {
768 MachineOperand Op(MachineOperand::MO_CImmediate);
769 Op.Contents.CI = CI;
770 return Op;
771 }
772
773 static MachineOperand CreateFPImm(const ConstantFP *CFP) {
774 MachineOperand Op(MachineOperand::MO_FPImmediate);
775 Op.Contents.CFP = CFP;
776 return Op;
777 }
778
779 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
780 bool isKill = false, bool isDead = false,
781 bool isUndef = false,
782 bool isEarlyClobber = false,
783 unsigned SubReg = 0, bool isDebug = false,
784 bool isInternalRead = false,
785 bool isRenamable = false) {
786 assert(!(isDead && !isDef) && "Dead flag on non-def")((!(isDead && !isDef) && "Dead flag on non-def"
) ? static_cast<void> (0) : __assert_fail ("!(isDead && !isDef) && \"Dead flag on non-def\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 786, __PRETTY_FUNCTION__))
;
787 assert(!(isKill && isDef) && "Kill flag on def")((!(isKill && isDef) && "Kill flag on def") ?
static_cast<void> (0) : __assert_fail ("!(isKill && isDef) && \"Kill flag on def\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 787, __PRETTY_FUNCTION__))
;
788 MachineOperand Op(MachineOperand::MO_Register);
789 Op.IsDef = isDef;
790 Op.IsImp = isImp;
791 Op.IsDeadOrKill = isKill | isDead;
792 Op.IsRenamable = isRenamable;
793 Op.IsUndef = isUndef;
794 Op.IsInternalRead = isInternalRead;
795 Op.IsEarlyClobber = isEarlyClobber;
796 Op.TiedTo = 0;
797 Op.IsDebug = isDebug;
798 Op.SmallContents.RegNo = Reg;
799 Op.Contents.Reg.Prev = nullptr;
800 Op.Contents.Reg.Next = nullptr;
801 Op.setSubReg(SubReg);
802 return Op;
803 }
804 static MachineOperand CreateMBB(MachineBasicBlock *MBB,
805 unsigned TargetFlags = 0) {
806 MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
807 Op.setMBB(MBB);
808 Op.setTargetFlags(TargetFlags);
809 return Op;
810 }
811 static MachineOperand CreateFI(int Idx) {
812 MachineOperand Op(MachineOperand::MO_FrameIndex);
813 Op.setIndex(Idx);
814 return Op;
815 }
816 static MachineOperand CreateCPI(unsigned Idx, int Offset,
817 unsigned TargetFlags = 0) {
818 MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
819 Op.setIndex(Idx);
820 Op.setOffset(Offset);
821 Op.setTargetFlags(TargetFlags);
822 return Op;
823 }
824 static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
825 unsigned TargetFlags = 0) {
826 MachineOperand Op(MachineOperand::MO_TargetIndex);
827 Op.setIndex(Idx);
828 Op.setOffset(Offset);
829 Op.setTargetFlags(TargetFlags);
830 return Op;
831 }
832 static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags = 0) {
833 MachineOperand Op(MachineOperand::MO_JumpTableIndex);
834 Op.setIndex(Idx);
835 Op.setTargetFlags(TargetFlags);
836 return Op;
837 }
838 static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
839 unsigned TargetFlags = 0) {
840 MachineOperand Op(MachineOperand::MO_GlobalAddress);
841 Op.Contents.OffsetedInfo.Val.GV = GV;
842 Op.setOffset(Offset);
843 Op.setTargetFlags(TargetFlags);
844 return Op;
845 }
846 static MachineOperand CreateES(const char *SymName,
847 unsigned TargetFlags = 0) {
848 MachineOperand Op(MachineOperand::MO_ExternalSymbol);
849 Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
850 Op.setOffset(0); // Offset is always 0.
851 Op.setTargetFlags(TargetFlags);
852 return Op;
853 }
854 static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
855 unsigned TargetFlags = 0) {
856 MachineOperand Op(MachineOperand::MO_BlockAddress);
857 Op.Contents.OffsetedInfo.Val.BA = BA;
858 Op.setOffset(Offset);
859 Op.setTargetFlags(TargetFlags);
860 return Op;
861 }
862 /// CreateRegMask - Creates a register mask operand referencing Mask. The
863 /// operand does not take ownership of the memory referenced by Mask, it
864 /// must remain valid for the lifetime of the operand.
865 ///
866 /// A RegMask operand represents a set of non-clobbered physical registers
867 /// on an instruction that clobbers many registers, typically a call. The
868 /// bit mask has a bit set for each physreg that is preserved by this
869 /// instruction, as described in the documentation for
870 /// TargetRegisterInfo::getCallPreservedMask().
871 ///
872 /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
873 ///
874 static MachineOperand CreateRegMask(const uint32_t *Mask) {
875 assert(Mask && "Missing register mask")((Mask && "Missing register mask") ? static_cast<void
> (0) : __assert_fail ("Mask && \"Missing register mask\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 875, __PRETTY_FUNCTION__))
;
876 MachineOperand Op(MachineOperand::MO_RegisterMask);
877 Op.Contents.RegMask = Mask;
878 return Op;
879 }
880 static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
881 assert(Mask && "Missing live-out register mask")((Mask && "Missing live-out register mask") ? static_cast
<void> (0) : __assert_fail ("Mask && \"Missing live-out register mask\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 881, __PRETTY_FUNCTION__))
;
882 MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
883 Op.Contents.RegMask = Mask;
884 return Op;
885 }
886 static MachineOperand CreateMetadata(const MDNode *Meta) {
887 MachineOperand Op(MachineOperand::MO_Metadata);
888 Op.Contents.MD = Meta;
889 return Op;
890 }
891
892 static MachineOperand CreateMCSymbol(MCSymbol *Sym,
893 unsigned TargetFlags = 0) {
894 MachineOperand Op(MachineOperand::MO_MCSymbol);
895 Op.Contents.Sym = Sym;
896 Op.setOffset(0);
897 Op.setTargetFlags(TargetFlags);
898 return Op;
899 }
900
901 static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
902 MachineOperand Op(MachineOperand::MO_CFIIndex);
903 Op.Contents.CFIIndex = CFIIndex;
904 return Op;
905 }
906
907 static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
908 MachineOperand Op(MachineOperand::MO_IntrinsicID);
909 Op.Contents.IntrinsicID = ID;
910 return Op;
911 }
912
913 static MachineOperand CreatePredicate(unsigned Pred) {
914 MachineOperand Op(MachineOperand::MO_Predicate);
915 Op.Contents.Pred = Pred;
916 return Op;
917 }
918
919 static MachineOperand CreateShuffleMask(ArrayRef<int> Mask) {
920 MachineOperand Op(MachineOperand::MO_ShuffleMask);
921 Op.Contents.ShuffleMask = Mask;
922 return Op;
923 }
924
925 friend class MachineInstr;
926 friend class MachineRegisterInfo;
927
928private:
929 // If this operand is currently a register operand, and if this is in a
930 // function, deregister the operand from the register's use/def list.
931 void removeRegFromUses();
932
933 /// Artificial kinds for DenseMap usage.
934 enum : unsigned char {
935 MO_Empty = MO_Last + 1,
936 MO_Tombstone,
937 };
938
939 friend struct DenseMapInfo<MachineOperand>;
940
941 //===--------------------------------------------------------------------===//
942 // Methods for handling register use/def lists.
943 //===--------------------------------------------------------------------===//
944
945 /// isOnRegUseList - Return true if this operand is on a register use/def
946 /// list or false if not. This can only be called for register operands
947 /// that are part of a machine instruction.
948 bool isOnRegUseList() const {
949 assert(isReg() && "Can only add reg operand to use lists")((isReg() && "Can only add reg operand to use lists")
? static_cast<void> (0) : __assert_fail ("isReg() && \"Can only add reg operand to use lists\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/MachineOperand.h"
, 949, __PRETTY_FUNCTION__))
;
950 return Contents.Reg.Prev != nullptr;
951 }
952};
953
954template <> struct DenseMapInfo<MachineOperand> {
955 static MachineOperand getEmptyKey() {
956 return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
957 MachineOperand::MO_Empty));
958 }
959 static MachineOperand getTombstoneKey() {
960 return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
961 MachineOperand::MO_Tombstone));
962 }
963 static unsigned getHashValue(const MachineOperand &MO) {
964 return hash_value(MO);
965 }
966 static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
967 if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
968 MachineOperand::MO_Empty) ||
969 LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
970 MachineOperand::MO_Tombstone))
971 return LHS.getType() == RHS.getType();
972 return LHS.isIdenticalTo(RHS);
973 }
974};
975
976inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
977 MO.print(OS);
978 return OS;
979}
980
981// See friend declaration above. This additional declaration is required in
982// order to compile LLVM with IBM xlC compiler.
983hash_code hash_value(const MachineOperand &MO);
984} // namespace llvm
985
986#endif