Bug Summary

File:llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
Warning:line 786, column 24
Division by zero

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name HexagonHardwareLoops.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon -I include -I /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-command-line-argument -Wno-unknown-warning-option -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/build-llvm -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-26-234817-15343-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp

1//===- HexagonHardwareLoops.cpp - Identify and generate hardware loops ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass identifies loops where we can generate the Hexagon hardware
10// loop instruction. The hardware loop can perform loop branches with a
11// zero-cycle overhead.
12//
13// The pattern that defines the induction variable can changed depending on
14// prior optimizations. For example, the IndVarSimplify phase run by 'opt'
15// normalizes induction variables, and the Loop Strength Reduction pass
16// run by 'llc' may also make changes to the induction variable.
17// The pattern detected by this phase is due to running Strength Reduction.
18//
19// Criteria for hardware loops:
20// - Countable loops (w/ ind. var for a trip count)
21// - Assumes loops are normalized by IndVarSimplify
22// - Try inner-most loops first
23// - No function calls in loops.
24//
25//===----------------------------------------------------------------------===//
26
27#include "HexagonInstrInfo.h"
28#include "HexagonSubtarget.h"
29#include "llvm/ADT/ArrayRef.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallSet.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/ADT/StringRef.h"
35#include "llvm/CodeGen/MachineBasicBlock.h"
36#include "llvm/CodeGen/MachineDominators.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineFunctionPass.h"
39#include "llvm/CodeGen/MachineInstr.h"
40#include "llvm/CodeGen/MachineInstrBuilder.h"
41#include "llvm/CodeGen/MachineLoopInfo.h"
42#include "llvm/CodeGen/MachineOperand.h"
43#include "llvm/CodeGen/MachineRegisterInfo.h"
44#include "llvm/CodeGen/TargetRegisterInfo.h"
45#include "llvm/IR/Constants.h"
46#include "llvm/IR/DebugLoc.h"
47#include "llvm/InitializePasses.h"
48#include "llvm/Pass.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Debug.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/MathExtras.h"
53#include "llvm/Support/raw_ostream.h"
54#include <cassert>
55#include <cstdint>
56#include <cstdlib>
57#include <iterator>
58#include <map>
59#include <set>
60#include <string>
61#include <utility>
62#include <vector>
63
64using namespace llvm;
65
66#define DEBUG_TYPE"hwloops" "hwloops"
67
68#ifndef NDEBUG
69static cl::opt<int> HWLoopLimit("hexagon-max-hwloop", cl::Hidden, cl::init(-1));
70
71// Option to create preheader only for a specific function.
72static cl::opt<std::string> PHFn("hexagon-hwloop-phfn", cl::Hidden,
73 cl::init(""));
74#endif
75
76// Option to create a preheader if one doesn't exist.
77static cl::opt<bool> HWCreatePreheader("hexagon-hwloop-preheader",
78 cl::Hidden, cl::init(true),
79 cl::desc("Add a preheader to a hardware loop if one doesn't exist"));
80
81// Turn it off by default. If a preheader block is not created here, the
82// software pipeliner may be unable to find a block suitable to serve as
83// a preheader. In that case SWP will not run.
84static cl::opt<bool> SpecPreheader("hwloop-spec-preheader", cl::init(false),
85 cl::Hidden, cl::ZeroOrMore, cl::desc("Allow speculation of preheader "
86 "instructions"));
87
88STATISTIC(NumHWLoops, "Number of loops converted to hardware loops")static llvm::Statistic NumHWLoops = {"hwloops", "NumHWLoops",
"Number of loops converted to hardware loops"}
;
89
90namespace llvm {
91
92 FunctionPass *createHexagonHardwareLoops();
93 void initializeHexagonHardwareLoopsPass(PassRegistry&);
94
95} // end namespace llvm
96
97namespace {
98
99 class CountValue;
100
101 struct HexagonHardwareLoops : public MachineFunctionPass {
102 MachineLoopInfo *MLI;
103 MachineRegisterInfo *MRI;
104 MachineDominatorTree *MDT;
105 const HexagonInstrInfo *TII;
106 const HexagonRegisterInfo *TRI;
107#ifndef NDEBUG
108 static int Counter;
109#endif
110
111 public:
112 static char ID;
113
114 HexagonHardwareLoops() : MachineFunctionPass(ID) {}
115
116 bool runOnMachineFunction(MachineFunction &MF) override;
117
118 StringRef getPassName() const override { return "Hexagon Hardware Loops"; }
119
120 void getAnalysisUsage(AnalysisUsage &AU) const override {
121 AU.addRequired<MachineDominatorTree>();
122 AU.addRequired<MachineLoopInfo>();
123 MachineFunctionPass::getAnalysisUsage(AU);
124 }
125
126 private:
127 using LoopFeederMap = std::map<unsigned, MachineInstr *>;
128
129 /// Kinds of comparisons in the compare instructions.
130 struct Comparison {
131 enum Kind {
132 EQ = 0x01,
133 NE = 0x02,
134 L = 0x04,
135 G = 0x08,
136 U = 0x40,
137 LTs = L,
138 LEs = L | EQ,
139 GTs = G,
140 GEs = G | EQ,
141 LTu = L | U,
142 LEu = L | EQ | U,
143 GTu = G | U,
144 GEu = G | EQ | U
145 };
146
147 static Kind getSwappedComparison(Kind Cmp) {
148 assert ((!((Cmp & L) && (Cmp & G))) && "Malformed comparison operator")(static_cast <bool> ((!((Cmp & L) && (Cmp &
G))) && "Malformed comparison operator") ? void (0) :
__assert_fail ("(!((Cmp & L) && (Cmp & G))) && \"Malformed comparison operator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 148, __extension__ __PRETTY_FUNCTION__))
;
149 if ((Cmp & L) || (Cmp & G))
150 return (Kind)(Cmp ^ (L|G));
151 return Cmp;
152 }
153
154 static Kind getNegatedComparison(Kind Cmp) {
155 if ((Cmp & L) || (Cmp & G))
156 return (Kind)((Cmp ^ (L | G)) ^ EQ);
157 if ((Cmp & NE) || (Cmp & EQ))
158 return (Kind)(Cmp ^ (EQ | NE));
159 return (Kind)0;
160 }
161
162 static bool isSigned(Kind Cmp) {
163 return (Cmp & (L | G) && !(Cmp & U));
164 }
165
166 static bool isUnsigned(Kind Cmp) {
167 return (Cmp & U);
168 }
169 };
170
171 /// Find the register that contains the loop controlling
172 /// induction variable.
173 /// If successful, it will return true and set the \p Reg, \p IVBump
174 /// and \p IVOp arguments. Otherwise it will return false.
175 /// The returned induction register is the register R that follows the
176 /// following induction pattern:
177 /// loop:
178 /// R = phi ..., [ R.next, LatchBlock ]
179 /// R.next = R + #bump
180 /// if (R.next < #N) goto loop
181 /// IVBump is the immediate value added to R, and IVOp is the instruction
182 /// "R.next = R + #bump".
183 bool findInductionRegister(MachineLoop *L, unsigned &Reg,
184 int64_t &IVBump, MachineInstr *&IVOp) const;
185
186 /// Return the comparison kind for the specified opcode.
187 Comparison::Kind getComparisonKind(unsigned CondOpc,
188 MachineOperand *InitialValue,
189 const MachineOperand *Endvalue,
190 int64_t IVBump) const;
191
192 /// Analyze the statements in a loop to determine if the loop
193 /// has a computable trip count and, if so, return a value that represents
194 /// the trip count expression.
195 CountValue *getLoopTripCount(MachineLoop *L,
196 SmallVectorImpl<MachineInstr *> &OldInsts);
197
198 /// Return the expression that represents the number of times
199 /// a loop iterates. The function takes the operands that represent the
200 /// loop start value, loop end value, and induction value. Based upon
201 /// these operands, the function attempts to compute the trip count.
202 /// If the trip count is not directly available (as an immediate value,
203 /// or a register), the function will attempt to insert computation of it
204 /// to the loop's preheader.
205 CountValue *computeCount(MachineLoop *Loop, const MachineOperand *Start,
206 const MachineOperand *End, unsigned IVReg,
207 int64_t IVBump, Comparison::Kind Cmp) const;
208
209 /// Return true if the instruction is not valid within a hardware
210 /// loop.
211 bool isInvalidLoopOperation(const MachineInstr *MI,
212 bool IsInnerHWLoop) const;
213
214 /// Return true if the loop contains an instruction that inhibits
215 /// using the hardware loop.
216 bool containsInvalidInstruction(MachineLoop *L, bool IsInnerHWLoop) const;
217
218 /// Given a loop, check if we can convert it to a hardware loop.
219 /// If so, then perform the conversion and return true.
220 bool convertToHardwareLoop(MachineLoop *L, bool &L0used, bool &L1used);
221
222 /// Return true if the instruction is now dead.
223 bool isDead(const MachineInstr *MI,
224 SmallVectorImpl<MachineInstr *> &DeadPhis) const;
225
226 /// Remove the instruction if it is now dead.
227 void removeIfDead(MachineInstr *MI);
228
229 /// Make sure that the "bump" instruction executes before the
230 /// compare. We need that for the IV fixup, so that the compare
231 /// instruction would not use a bumped value that has not yet been
232 /// defined. If the instructions are out of order, try to reorder them.
233 bool orderBumpCompare(MachineInstr *BumpI, MachineInstr *CmpI);
234
235 /// Return true if MO and MI pair is visited only once. If visited
236 /// more than once, this indicates there is recursion. In such a case,
237 /// return false.
238 bool isLoopFeeder(MachineLoop *L, MachineBasicBlock *A, MachineInstr *MI,
239 const MachineOperand *MO,
240 LoopFeederMap &LoopFeederPhi) const;
241
242 /// Return true if the Phi may generate a value that may underflow,
243 /// or may wrap.
244 bool phiMayWrapOrUnderflow(MachineInstr *Phi, const MachineOperand *EndVal,
245 MachineBasicBlock *MBB, MachineLoop *L,
246 LoopFeederMap &LoopFeederPhi) const;
247
248 /// Return true if the induction variable may underflow an unsigned
249 /// value in the first iteration.
250 bool loopCountMayWrapOrUnderFlow(const MachineOperand *InitVal,
251 const MachineOperand *EndVal,
252 MachineBasicBlock *MBB, MachineLoop *L,
253 LoopFeederMap &LoopFeederPhi) const;
254
255 /// Check if the given operand has a compile-time known constant
256 /// value. Return true if yes, and false otherwise. When returning true, set
257 /// Val to the corresponding constant value.
258 bool checkForImmediate(const MachineOperand &MO, int64_t &Val) const;
259
260 /// Check if the operand has a compile-time known constant value.
261 bool isImmediate(const MachineOperand &MO) const {
262 int64_t V;
263 return checkForImmediate(MO, V);
264 }
265
266 /// Return the immediate for the specified operand.
267 int64_t getImmediate(const MachineOperand &MO) const {
268 int64_t V;
269 if (!checkForImmediate(MO, V))
270 llvm_unreachable("Invalid operand")::llvm::llvm_unreachable_internal("Invalid operand", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 270)
;
271 return V;
272 }
273
274 /// Reset the given machine operand to now refer to a new immediate
275 /// value. Assumes that the operand was already referencing an immediate
276 /// value, either directly, or via a register.
277 void setImmediate(MachineOperand &MO, int64_t Val);
278
279 /// Fix the data flow of the induction variable.
280 /// The desired flow is: phi ---> bump -+-> comparison-in-latch.
281 /// |
282 /// +-> back to phi
283 /// where "bump" is the increment of the induction variable:
284 /// iv = iv + #const.
285 /// Due to some prior code transformations, the actual flow may look
286 /// like this:
287 /// phi -+-> bump ---> back to phi
288 /// |
289 /// +-> comparison-in-latch (against upper_bound-bump),
290 /// i.e. the comparison that controls the loop execution may be using
291 /// the value of the induction variable from before the increment.
292 ///
293 /// Return true if the loop's flow is the desired one (i.e. it's
294 /// either been fixed, or no fixing was necessary).
295 /// Otherwise, return false. This can happen if the induction variable
296 /// couldn't be identified, or if the value in the latch's comparison
297 /// cannot be adjusted to reflect the post-bump value.
298 bool fixupInductionVariable(MachineLoop *L);
299
300 /// Given a loop, if it does not have a preheader, create one.
301 /// Return the block that is the preheader.
302 MachineBasicBlock *createPreheaderForLoop(MachineLoop *L);
303 };
304
305 char HexagonHardwareLoops::ID = 0;
306#ifndef NDEBUG
307 int HexagonHardwareLoops::Counter = 0;
308#endif
309
310 /// Abstraction for a trip count of a loop. A smaller version
311 /// of the MachineOperand class without the concerns of changing the
312 /// operand representation.
313 class CountValue {
314 public:
315 enum CountValueType {
316 CV_Register,
317 CV_Immediate
318 };
319
320 private:
321 CountValueType Kind;
322 union Values {
323 struct {
324 unsigned Reg;
325 unsigned Sub;
326 } R;
327 unsigned ImmVal;
328 } Contents;
329
330 public:
331 explicit CountValue(CountValueType t, unsigned v, unsigned u = 0) {
332 Kind = t;
333 if (Kind == CV_Register) {
334 Contents.R.Reg = v;
335 Contents.R.Sub = u;
336 } else {
337 Contents.ImmVal = v;
338 }
339 }
340
341 bool isReg() const { return Kind == CV_Register; }
342 bool isImm() const { return Kind == CV_Immediate; }
343
344 unsigned getReg() const {
345 assert(isReg() && "Wrong CountValue accessor")(static_cast <bool> (isReg() && "Wrong CountValue accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong CountValue accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 345, __extension__ __PRETTY_FUNCTION__))
;
346 return Contents.R.Reg;
347 }
348
349 unsigned getSubReg() const {
350 assert(isReg() && "Wrong CountValue accessor")(static_cast <bool> (isReg() && "Wrong CountValue accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong CountValue accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 350, __extension__ __PRETTY_FUNCTION__))
;
351 return Contents.R.Sub;
352 }
353
354 unsigned getImm() const {
355 assert(isImm() && "Wrong CountValue accessor")(static_cast <bool> (isImm() && "Wrong CountValue accessor"
) ? void (0) : __assert_fail ("isImm() && \"Wrong CountValue accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 355, __extension__ __PRETTY_FUNCTION__))
;
356 return Contents.ImmVal;
357 }
358
359 void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {
360 if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }
361 if (isImm()) { OS << Contents.ImmVal; }
362 }
363 };
364
365} // end anonymous namespace
366
367INITIALIZE_PASS_BEGIN(HexagonHardwareLoops, "hwloops",static void *initializeHexagonHardwareLoopsPassOnce(PassRegistry
&Registry) {
368 "Hexagon Hardware Loops", false, false)static void *initializeHexagonHardwareLoopsPassOnce(PassRegistry
&Registry) {
369INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)initializeMachineDominatorTreePass(Registry);
370INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)initializeMachineLoopInfoPass(Registry);
371INITIALIZE_PASS_END(HexagonHardwareLoops, "hwloops",PassInfo *PI = new PassInfo( "Hexagon Hardware Loops", "hwloops"
, &HexagonHardwareLoops::ID, PassInfo::NormalCtor_t(callDefaultCtor
<HexagonHardwareLoops>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeHexagonHardwareLoopsPassFlag
; void llvm::initializeHexagonHardwareLoopsPass(PassRegistry &
Registry) { llvm::call_once(InitializeHexagonHardwareLoopsPassFlag
, initializeHexagonHardwareLoopsPassOnce, std::ref(Registry))
; }
372 "Hexagon Hardware Loops", false, false)PassInfo *PI = new PassInfo( "Hexagon Hardware Loops", "hwloops"
, &HexagonHardwareLoops::ID, PassInfo::NormalCtor_t(callDefaultCtor
<HexagonHardwareLoops>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeHexagonHardwareLoopsPassFlag
; void llvm::initializeHexagonHardwareLoopsPass(PassRegistry &
Registry) { llvm::call_once(InitializeHexagonHardwareLoopsPassFlag
, initializeHexagonHardwareLoopsPassOnce, std::ref(Registry))
; }
373
374FunctionPass *llvm::createHexagonHardwareLoops() {
375 return new HexagonHardwareLoops();
376}
377
378bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) {
379 LLVM_DEBUG(dbgs() << "********* Hexagon Hardware Loops *********\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "********* Hexagon Hardware Loops *********\n"
; } } while (false)
;
380 if (skipFunction(MF.getFunction()))
381 return false;
382
383 bool Changed = false;
384
385 MLI = &getAnalysis<MachineLoopInfo>();
386 MRI = &MF.getRegInfo();
387 MDT = &getAnalysis<MachineDominatorTree>();
388 const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>();
389 TII = HST.getInstrInfo();
390 TRI = HST.getRegisterInfo();
391
392 for (auto &L : *MLI)
393 if (L->isOutermost()) {
394 bool L0Used = false;
395 bool L1Used = false;
396 Changed |= convertToHardwareLoop(L, L0Used, L1Used);
397 }
398
399 return Changed;
400}
401
402bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L,
403 unsigned &Reg,
404 int64_t &IVBump,
405 MachineInstr *&IVOp
406 ) const {
407 MachineBasicBlock *Header = L->getHeader();
408 MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);
409 MachineBasicBlock *Latch = L->getLoopLatch();
410 MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
411 if (!Header || !Preheader || !Latch || !ExitingBlock)
412 return false;
413
414 // This pair represents an induction register together with an immediate
415 // value that will be added to it in each loop iteration.
416 using RegisterBump = std::pair<unsigned, int64_t>;
417
418 // Mapping: R.next -> (R, bump), where R, R.next and bump are derived
419 // from an induction operation
420 // R.next = R + bump
421 // where bump is an immediate value.
422 using InductionMap = std::map<unsigned, RegisterBump>;
423
424 InductionMap IndMap;
425
426 using instr_iterator = MachineBasicBlock::instr_iterator;
427
428 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
429 I != E && I->isPHI(); ++I) {
430 MachineInstr *Phi = &*I;
431
432 // Have a PHI instruction. Get the operand that corresponds to the
433 // latch block, and see if is a result of an addition of form "reg+imm",
434 // where the "reg" is defined by the PHI node we are looking at.
435 for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
436 if (Phi->getOperand(i+1).getMBB() != Latch)
437 continue;
438
439 Register PhiOpReg = Phi->getOperand(i).getReg();
440 MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
441
442 if (DI->getDesc().isAdd()) {
443 // If the register operand to the add is the PHI we're looking at, this
444 // meets the induction pattern.
445 Register IndReg = DI->getOperand(1).getReg();
446 MachineOperand &Opnd2 = DI->getOperand(2);
447 int64_t V;
448 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
449 Register UpdReg = DI->getOperand(0).getReg();
450 IndMap.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
451 }
452 }
453 } // for (i)
454 } // for (instr)
455
456 SmallVector<MachineOperand,2> Cond;
457 MachineBasicBlock *TB = nullptr, *FB = nullptr;
458 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
459 if (NotAnalyzed)
460 return false;
461
462 unsigned PredR, PredPos, PredRegFlags;
463 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags))
464 return false;
465
466 MachineInstr *PredI = MRI->getVRegDef(PredR);
467 if (!PredI->isCompare())
468 return false;
469
470 Register CmpReg1, CmpReg2;
471 int64_t CmpImm = 0, CmpMask = 0;
472 bool CmpAnalyzed =
473 TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm);
474 // Fail if the compare was not analyzed, or it's not comparing a register
475 // with an immediate value. Not checking the mask here, since we handle
476 // the individual compare opcodes (including A4_cmpb*) later on.
477 if (!CmpAnalyzed)
478 return false;
479
480 // Exactly one of the input registers to the comparison should be among
481 // the induction registers.
482 InductionMap::iterator IndMapEnd = IndMap.end();
483 InductionMap::iterator F = IndMapEnd;
484 if (CmpReg1 != 0) {
485 InductionMap::iterator F1 = IndMap.find(CmpReg1);
486 if (F1 != IndMapEnd)
487 F = F1;
488 }
489 if (CmpReg2 != 0) {
490 InductionMap::iterator F2 = IndMap.find(CmpReg2);
491 if (F2 != IndMapEnd) {
492 if (F != IndMapEnd)
493 return false;
494 F = F2;
495 }
496 }
497 if (F == IndMapEnd)
498 return false;
499
500 Reg = F->second.first;
501 IVBump = F->second.second;
502 IVOp = MRI->getVRegDef(F->first);
503 return true;
504}
505
506// Return the comparison kind for the specified opcode.
507HexagonHardwareLoops::Comparison::Kind
508HexagonHardwareLoops::getComparisonKind(unsigned CondOpc,
509 MachineOperand *InitialValue,
510 const MachineOperand *EndValue,
511 int64_t IVBump) const {
512 Comparison::Kind Cmp = (Comparison::Kind)0;
513 switch (CondOpc) {
514 case Hexagon::C2_cmpeq:
515 case Hexagon::C2_cmpeqi:
516 case Hexagon::C2_cmpeqp:
517 Cmp = Comparison::EQ;
518 break;
519 case Hexagon::C4_cmpneq:
520 case Hexagon::C4_cmpneqi:
521 Cmp = Comparison::NE;
522 break;
523 case Hexagon::C2_cmplt:
524 Cmp = Comparison::LTs;
525 break;
526 case Hexagon::C2_cmpltu:
527 Cmp = Comparison::LTu;
528 break;
529 case Hexagon::C4_cmplte:
530 case Hexagon::C4_cmpltei:
531 Cmp = Comparison::LEs;
532 break;
533 case Hexagon::C4_cmplteu:
534 case Hexagon::C4_cmplteui:
535 Cmp = Comparison::LEu;
536 break;
537 case Hexagon::C2_cmpgt:
538 case Hexagon::C2_cmpgti:
539 case Hexagon::C2_cmpgtp:
540 Cmp = Comparison::GTs;
541 break;
542 case Hexagon::C2_cmpgtu:
543 case Hexagon::C2_cmpgtui:
544 case Hexagon::C2_cmpgtup:
545 Cmp = Comparison::GTu;
546 break;
547 case Hexagon::C2_cmpgei:
548 Cmp = Comparison::GEs;
549 break;
550 case Hexagon::C2_cmpgeui:
551 Cmp = Comparison::GEs;
552 break;
553 default:
554 return (Comparison::Kind)0;
555 }
556 return Cmp;
557}
558
559/// Analyze the statements in a loop to determine if the loop has
560/// a computable trip count and, if so, return a value that represents
561/// the trip count expression.
562///
563/// This function iterates over the phi nodes in the loop to check for
564/// induction variable patterns that are used in the calculation for
565/// the number of time the loop is executed.
566CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
567 SmallVectorImpl<MachineInstr *> &OldInsts) {
568 MachineBasicBlock *TopMBB = L->getTopBlock();
569 MachineBasicBlock::pred_iterator PI = TopMBB->pred_begin();
570 assert(PI != TopMBB->pred_end() &&(static_cast <bool> (PI != TopMBB->pred_end() &&
"Loop must have more than one incoming edge!") ? void (0) : __assert_fail
("PI != TopMBB->pred_end() && \"Loop must have more than one incoming edge!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 571, __extension__ __PRETTY_FUNCTION__))
571 "Loop must have more than one incoming edge!")(static_cast <bool> (PI != TopMBB->pred_end() &&
"Loop must have more than one incoming edge!") ? void (0) : __assert_fail
("PI != TopMBB->pred_end() && \"Loop must have more than one incoming edge!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 571, __extension__ __PRETTY_FUNCTION__))
;
572 MachineBasicBlock *Backedge = *PI++;
573 if (PI == TopMBB->pred_end()) // dead loop?
574 return nullptr;
575 MachineBasicBlock *Incoming = *PI++;
576 if (PI != TopMBB->pred_end()) // multiple backedges?
577 return nullptr;
578
579 // Make sure there is one incoming and one backedge and determine which
580 // is which.
581 if (L->contains(Incoming)) {
582 if (L->contains(Backedge))
583 return nullptr;
584 std::swap(Incoming, Backedge);
585 } else if (!L->contains(Backedge))
586 return nullptr;
587
588 // Look for the cmp instruction to determine if we can get a useful trip
589 // count. The trip count can be either a register or an immediate. The
590 // location of the value depends upon the type (reg or imm).
591 MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
592 if (!ExitingBlock)
593 return nullptr;
594
595 unsigned IVReg = 0;
596 int64_t IVBump = 0;
597 MachineInstr *IVOp;
598 bool FoundIV = findInductionRegister(L, IVReg, IVBump, IVOp);
599 if (!FoundIV)
600 return nullptr;
601
602 MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);
603
604 MachineOperand *InitialValue = nullptr;
605 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg);
606 MachineBasicBlock *Latch = L->getLoopLatch();
607 for (unsigned i = 1, n = IV_Phi->getNumOperands(); i < n; i += 2) {
608 MachineBasicBlock *MBB = IV_Phi->getOperand(i+1).getMBB();
609 if (MBB == Preheader)
610 InitialValue = &IV_Phi->getOperand(i);
611 else if (MBB == Latch)
612 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump.
613 }
614 if (!InitialValue)
615 return nullptr;
616
617 SmallVector<MachineOperand,2> Cond;
618 MachineBasicBlock *TB = nullptr, *FB = nullptr;
619 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
620 if (NotAnalyzed)
621 return nullptr;
622
623 MachineBasicBlock *Header = L->getHeader();
624 // TB must be non-null. If FB is also non-null, one of them must be
625 // the header. Otherwise, branch to TB could be exiting the loop, and
626 // the fall through can go to the header.
627 assert (TB && "Exit block without a branch?")(static_cast <bool> (TB && "Exit block without a branch?"
) ? void (0) : __assert_fail ("TB && \"Exit block without a branch?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 627, __extension__ __PRETTY_FUNCTION__))
;
628 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) {
629 MachineBasicBlock *LTB = nullptr, *LFB = nullptr;
630 SmallVector<MachineOperand,2> LCond;
631 bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false);
632 if (NotAnalyzed)
633 return nullptr;
634 if (TB == Latch)
635 TB = (LTB == Header) ? LTB : LFB;
636 else
637 FB = (LTB == Header) ? LTB: LFB;
638 }
639 assert ((!FB || TB == Header || FB == Header) && "Branches not to header?")(static_cast <bool> ((!FB || TB == Header || FB == Header
) && "Branches not to header?") ? void (0) : __assert_fail
("(!FB || TB == Header || FB == Header) && \"Branches not to header?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 639, __extension__ __PRETTY_FUNCTION__))
;
640 if (!TB || (FB && TB != Header && FB != Header))
641 return nullptr;
642
643 // Branches of form "if (!P) ..." cause HexagonInstrInfo::analyzeBranch
644 // to put imm(0), followed by P in the vector Cond.
645 // If TB is not the header, it means that the "not-taken" path must lead
646 // to the header.
647 bool Negated = TII->predOpcodeHasNot(Cond) ^ (TB != Header);
648 unsigned PredReg, PredPos, PredRegFlags;
649 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags))
650 return nullptr;
651 MachineInstr *CondI = MRI->getVRegDef(PredReg);
652 unsigned CondOpc = CondI->getOpcode();
653
654 Register CmpReg1, CmpReg2;
655 int64_t Mask = 0, ImmValue = 0;
656 bool AnalyzedCmp =
657 TII->analyzeCompare(*CondI, CmpReg1, CmpReg2, Mask, ImmValue);
658 if (!AnalyzedCmp)
659 return nullptr;
660
661 // The comparison operator type determines how we compute the loop
662 // trip count.
663 OldInsts.push_back(CondI);
664 OldInsts.push_back(IVOp);
665
666 // Sadly, the following code gets information based on the position
667 // of the operands in the compare instruction. This has to be done
668 // this way, because the comparisons check for a specific relationship
669 // between the operands (e.g. is-less-than), rather than to find out
670 // what relationship the operands are in (as on PPC).
671 Comparison::Kind Cmp;
672 bool isSwapped = false;
673 const MachineOperand &Op1 = CondI->getOperand(1);
674 const MachineOperand &Op2 = CondI->getOperand(2);
675 const MachineOperand *EndValue = nullptr;
676
677 if (Op1.isReg()) {
678 if (Op2.isImm() || Op1.getReg() == IVReg)
679 EndValue = &Op2;
680 else {
681 EndValue = &Op1;
682 isSwapped = true;
683 }
684 }
685
686 if (!EndValue)
687 return nullptr;
688
689 Cmp = getComparisonKind(CondOpc, InitialValue, EndValue, IVBump);
690 if (!Cmp)
691 return nullptr;
692 if (Negated)
693 Cmp = Comparison::getNegatedComparison(Cmp);
694 if (isSwapped)
695 Cmp = Comparison::getSwappedComparison(Cmp);
696
697 if (InitialValue->isReg()) {
698 Register R = InitialValue->getReg();
699 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
700 if (!MDT->properlyDominates(DefBB, Header)) {
701 int64_t V;
702 if (!checkForImmediate(*InitialValue, V))
703 return nullptr;
704 }
705 OldInsts.push_back(MRI->getVRegDef(R));
706 }
707 if (EndValue->isReg()) {
708 Register R = EndValue->getReg();
709 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
710 if (!MDT->properlyDominates(DefBB, Header)) {
711 int64_t V;
712 if (!checkForImmediate(*EndValue, V))
713 return nullptr;
714 }
715 OldInsts.push_back(MRI->getVRegDef(R));
716 }
717
718 return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);
719}
720
721/// Helper function that returns the expression that represents the
722/// number of times a loop iterates. The function takes the operands that
723/// represent the loop start value, loop end value, and induction value.
724/// Based upon these operands, the function attempts to compute the trip count.
725CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
726 const MachineOperand *Start,
727 const MachineOperand *End,
728 unsigned IVReg,
729 int64_t IVBump,
730 Comparison::Kind Cmp) const {
731 // Cannot handle comparison EQ, i.e. while (A == B).
732 if (Cmp == Comparison::EQ)
1
Assuming 'Cmp' is not equal to EQ
2
Taking false branch
733 return nullptr;
734
735 // Check if either the start or end values are an assignment of an immediate.
736 // If so, use the immediate value rather than the register.
737 if (Start->isReg()) {
3
Taking false branch
738 const MachineInstr *StartValInstr = MRI->getVRegDef(Start->getReg());
739 if (StartValInstr && (StartValInstr->getOpcode() == Hexagon::A2_tfrsi ||
740 StartValInstr->getOpcode() == Hexagon::A2_tfrpi))
741 Start = &StartValInstr->getOperand(1);
742 }
743 if (End->isReg()) {
744 const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
745 if (EndValInstr && (EndValInstr->getOpcode() == Hexagon::A2_tfrsi ||
746 EndValInstr->getOpcode() == Hexagon::A2_tfrpi))
747 End = &EndValInstr->getOperand(1);
748 }
749
750 if (!Start->isReg() && !Start->isImm())
4
Calling 'MachineOperand::isReg'
6
Returning from 'MachineOperand::isReg'
7
Calling 'MachineOperand::isImm'
10
Returning from 'MachineOperand::isImm'
751 return nullptr;
752 if (!End->isReg() && !End->isImm())
11
Calling 'MachineOperand::isReg'
13
Returning from 'MachineOperand::isReg'
14
Calling 'MachineOperand::isImm'
17
Returning from 'MachineOperand::isImm'
18
Taking false branch
753 return nullptr;
754
755 bool CmpLess = Cmp & Comparison::L;
756 bool CmpGreater = Cmp & Comparison::G;
757 bool CmpHasEqual = Cmp & Comparison::EQ;
758
759 // Avoid certain wrap-arounds. This doesn't detect all wrap-arounds.
760 if (CmpLess && IVBump < 0)
19
Assuming 'CmpLess' is true
20
Assuming 'IVBump' is >= 0
761 // Loop going while iv is "less" with the iv value going down. Must wrap.
762 return nullptr;
763
764 if (CmpGreater && IVBump > 0)
21
Assuming 'CmpGreater' is true
22
Assuming 'IVBump' is <= 0
23
Taking false branch
765 // Loop going while iv is "greater" with the iv value going up. Must wrap.
766 return nullptr;
767
768 // Phis that may feed into the loop.
769 LoopFeederMap LoopFeederPhi;
770
771 // Check if the initial value may be zero and can be decremented in the first
772 // iteration. If the value is zero, the endloop instruction will not decrement
773 // the loop counter, so we shouldn't generate a hardware loop in this case.
774 if (loopCountMayWrapOrUnderFlow(Start, End, Loop->getLoopPreheader(), Loop,
24
Calling 'HexagonHardwareLoops::loopCountMayWrapOrUnderFlow'
30
Returning from 'HexagonHardwareLoops::loopCountMayWrapOrUnderFlow'
775 LoopFeederPhi))
776 return nullptr;
777
778 if (Start->isImm() && End->isImm()) {
31
Calling 'MachineOperand::isImm'
33
Returning from 'MachineOperand::isImm'
34
Calling 'MachineOperand::isImm'
36
Returning from 'MachineOperand::isImm'
37
Taking true branch
779 // Both, start and end are immediates.
780 int64_t StartV = Start->getImm();
781 int64_t EndV = End->getImm();
782 int64_t Dist = EndV - StartV;
783 if (Dist == 0)
38
Assuming 'Dist' is not equal to 0
39
Taking false branch
784 return nullptr;
785
786 bool Exact = (Dist % IVBump) == 0;
40
Division by zero
787
788 if (Cmp == Comparison::NE) {
789 if (!Exact)
790 return nullptr;
791 if ((Dist < 0) ^ (IVBump < 0))
792 return nullptr;
793 }
794
795 // For comparisons that include the final value (i.e. include equality
796 // with the final value), we need to increase the distance by 1.
797 if (CmpHasEqual)
798 Dist = Dist > 0 ? Dist+1 : Dist-1;
799
800 // For the loop to iterate, CmpLess should imply Dist > 0. Similarly,
801 // CmpGreater should imply Dist < 0. These conditions could actually
802 // fail, for example, in unreachable code (which may still appear to be
803 // reachable in the CFG).
804 if ((CmpLess && Dist < 0) || (CmpGreater && Dist > 0))
805 return nullptr;
806
807 // "Normalized" distance, i.e. with the bump set to +-1.
808 int64_t Dist1 = (IVBump > 0) ? (Dist + (IVBump - 1)) / IVBump
809 : (-Dist + (-IVBump - 1)) / (-IVBump);
810 assert (Dist1 > 0 && "Fishy thing. Both operands have the same sign.")(static_cast <bool> (Dist1 > 0 && "Fishy thing. Both operands have the same sign."
) ? void (0) : __assert_fail ("Dist1 > 0 && \"Fishy thing. Both operands have the same sign.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 810, __extension__ __PRETTY_FUNCTION__))
;
811
812 uint64_t Count = Dist1;
813
814 if (Count > 0xFFFFFFFFULL)
815 return nullptr;
816
817 return new CountValue(CountValue::CV_Immediate, Count);
818 }
819
820 // A general case: Start and End are some values, but the actual
821 // iteration count may not be available. If it is not, insert
822 // a computation of it into the preheader.
823
824 // If the induction variable bump is not a power of 2, quit.
825 // Othwerise we'd need a general integer division.
826 if (!isPowerOf2_64(std::abs(IVBump)))
827 return nullptr;
828
829 MachineBasicBlock *PH = MLI->findLoopPreheader(Loop, SpecPreheader);
830 assert (PH && "Should have a preheader by now")(static_cast <bool> (PH && "Should have a preheader by now"
) ? void (0) : __assert_fail ("PH && \"Should have a preheader by now\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 830, __extension__ __PRETTY_FUNCTION__))
;
831 MachineBasicBlock::iterator InsertPos = PH->getFirstTerminator();
832 DebugLoc DL;
833 if (InsertPos != PH->end())
834 DL = InsertPos->getDebugLoc();
835
836 // If Start is an immediate and End is a register, the trip count
837 // will be "reg - imm". Hexagon's "subtract immediate" instruction
838 // is actually "reg + -imm".
839
840 // If the loop IV is going downwards, i.e. if the bump is negative,
841 // then the iteration count (computed as End-Start) will need to be
842 // negated. To avoid the negation, just swap Start and End.
843 if (IVBump < 0) {
844 std::swap(Start, End);
845 IVBump = -IVBump;
846 }
847 // Cmp may now have a wrong direction, e.g. LEs may now be GEs.
848 // Signedness, and "including equality" are preserved.
849
850 bool RegToImm = Start->isReg() && End->isImm(); // for (reg..imm)
851 bool RegToReg = Start->isReg() && End->isReg(); // for (reg..reg)
852
853 int64_t StartV = 0, EndV = 0;
854 if (Start->isImm())
855 StartV = Start->getImm();
856 if (End->isImm())
857 EndV = End->getImm();
858
859 int64_t AdjV = 0;
860 // To compute the iteration count, we would need this computation:
861 // Count = (End - Start + (IVBump-1)) / IVBump
862 // or, when CmpHasEqual:
863 // Count = (End - Start + (IVBump-1)+1) / IVBump
864 // The "IVBump-1" part is the adjustment (AdjV). We can avoid
865 // generating an instruction specifically to add it if we can adjust
866 // the immediate values for Start or End.
867
868 if (CmpHasEqual) {
869 // Need to add 1 to the total iteration count.
870 if (Start->isImm())
871 StartV--;
872 else if (End->isImm())
873 EndV++;
874 else
875 AdjV += 1;
876 }
877
878 if (Cmp != Comparison::NE) {
879 if (Start->isImm())
880 StartV -= (IVBump-1);
881 else if (End->isImm())
882 EndV += (IVBump-1);
883 else
884 AdjV += (IVBump-1);
885 }
886
887 unsigned R = 0, SR = 0;
888 if (Start->isReg()) {
889 R = Start->getReg();
890 SR = Start->getSubReg();
891 } else {
892 R = End->getReg();
893 SR = End->getSubReg();
894 }
895 const TargetRegisterClass *RC = MRI->getRegClass(R);
896 // Hardware loops cannot handle 64-bit registers. If it's a double
897 // register, it has to have a subregister.
898 if (!SR && RC == &Hexagon::DoubleRegsRegClass)
899 return nullptr;
900 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
901
902 // Compute DistR (register with the distance between Start and End).
903 unsigned DistR, DistSR;
904
905 // Avoid special case, where the start value is an imm(0).
906 if (Start->isImm() && StartV == 0) {
907 DistR = End->getReg();
908 DistSR = End->getSubReg();
909 } else {
910 const MCInstrDesc &SubD = RegToReg ? TII->get(Hexagon::A2_sub) :
911 (RegToImm ? TII->get(Hexagon::A2_subri) :
912 TII->get(Hexagon::A2_addi));
913 if (RegToReg || RegToImm) {
914 Register SubR = MRI->createVirtualRegister(IntRC);
915 MachineInstrBuilder SubIB =
916 BuildMI(*PH, InsertPos, DL, SubD, SubR);
917
918 if (RegToReg)
919 SubIB.addReg(End->getReg(), 0, End->getSubReg())
920 .addReg(Start->getReg(), 0, Start->getSubReg());
921 else
922 SubIB.addImm(EndV)
923 .addReg(Start->getReg(), 0, Start->getSubReg());
924 DistR = SubR;
925 } else {
926 // If the loop has been unrolled, we should use the original loop count
927 // instead of recalculating the value. This will avoid additional
928 // 'Add' instruction.
929 const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
930 if (EndValInstr->getOpcode() == Hexagon::A2_addi &&
931 EndValInstr->getOperand(1).getSubReg() == 0 &&
932 EndValInstr->getOperand(2).getImm() == StartV) {
933 DistR = EndValInstr->getOperand(1).getReg();
934 } else {
935 Register SubR = MRI->createVirtualRegister(IntRC);
936 MachineInstrBuilder SubIB =
937 BuildMI(*PH, InsertPos, DL, SubD, SubR);
938 SubIB.addReg(End->getReg(), 0, End->getSubReg())
939 .addImm(-StartV);
940 DistR = SubR;
941 }
942 }
943 DistSR = 0;
944 }
945
946 // From DistR, compute AdjR (register with the adjusted distance).
947 unsigned AdjR, AdjSR;
948
949 if (AdjV == 0) {
950 AdjR = DistR;
951 AdjSR = DistSR;
952 } else {
953 // Generate CountR = ADD DistR, AdjVal
954 Register AddR = MRI->createVirtualRegister(IntRC);
955 MCInstrDesc const &AddD = TII->get(Hexagon::A2_addi);
956 BuildMI(*PH, InsertPos, DL, AddD, AddR)
957 .addReg(DistR, 0, DistSR)
958 .addImm(AdjV);
959
960 AdjR = AddR;
961 AdjSR = 0;
962 }
963
964 // From AdjR, compute CountR (register with the final count).
965 unsigned CountR, CountSR;
966
967 if (IVBump == 1) {
968 CountR = AdjR;
969 CountSR = AdjSR;
970 } else {
971 // The IV bump is a power of two. Log_2(IV bump) is the shift amount.
972 unsigned Shift = Log2_32(IVBump);
973
974 // Generate NormR = LSR DistR, Shift.
975 Register LsrR = MRI->createVirtualRegister(IntRC);
976 const MCInstrDesc &LsrD = TII->get(Hexagon::S2_lsr_i_r);
977 BuildMI(*PH, InsertPos, DL, LsrD, LsrR)
978 .addReg(AdjR, 0, AdjSR)
979 .addImm(Shift);
980
981 CountR = LsrR;
982 CountSR = 0;
983 }
984
985 return new CountValue(CountValue::CV_Register, CountR, CountSR);
986}
987
988/// Return true if the operation is invalid within hardware loop.
989bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI,
990 bool IsInnerHWLoop) const {
991 // Call is not allowed because the callee may use a hardware loop except for
992 // the case when the call never returns.
993 if (MI->getDesc().isCall())
994 return !TII->doesNotReturn(*MI);
995
996 // Check if the instruction defines a hardware loop register.
997 using namespace Hexagon;
998
999 static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 };
1000 static const unsigned Regs1[] = { LC1, SA1 };
1001 auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, array_lengthof(Regs01))
1002 : makeArrayRef(Regs1, array_lengthof(Regs1));
1003 for (unsigned R : CheckRegs)
1004 if (MI->modifiesRegister(R, TRI))
1005 return true;
1006
1007 return false;
1008}
1009
1010/// Return true if the loop contains an instruction that inhibits
1011/// the use of the hardware loop instruction.
1012bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L,
1013 bool IsInnerHWLoop) const {
1014 LLVM_DEBUG(dbgs() << "\nhw_loop head, "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nhw_loop head, " << printMBBReference
(**L->block_begin()); } } while (false)
1015 << printMBBReference(**L->block_begin()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nhw_loop head, " << printMBBReference
(**L->block_begin()); } } while (false)
;
1016 for (MachineBasicBlock *MBB : L->getBlocks()) {
1017 for (MachineBasicBlock::iterator
1018 MII = MBB->begin(), E = MBB->end(); MII != E; ++MII) {
1019 const MachineInstr *MI = &*MII;
1020 if (isInvalidLoopOperation(MI, IsInnerHWLoop)) {
1021 LLVM_DEBUG(dbgs() << "\nCannot convert to hw_loop due to:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nCannot convert to hw_loop due to:"
; MI->dump();; } } while (false)
1022 MI->dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nCannot convert to hw_loop due to:"
; MI->dump();; } } while (false)
;
1023 return true;
1024 }
1025 }
1026 }
1027 return false;
1028}
1029
1030/// Returns true if the instruction is dead. This was essentially
1031/// copied from DeadMachineInstructionElim::isDead, but with special cases
1032/// for inline asm, physical registers and instructions with side effects
1033/// removed.
1034bool HexagonHardwareLoops::isDead(const MachineInstr *MI,
1035 SmallVectorImpl<MachineInstr *> &DeadPhis) const {
1036 // Examine each operand.
1037 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1038 const MachineOperand &MO = MI->getOperand(i);
1039 if (!MO.isReg() || !MO.isDef())
1040 continue;
1041
1042 Register Reg = MO.getReg();
1043 if (MRI->use_nodbg_empty(Reg))
1044 continue;
1045
1046 using use_nodbg_iterator = MachineRegisterInfo::use_nodbg_iterator;
1047
1048 // This instruction has users, but if the only user is the phi node for the
1049 // parent block, and the only use of that phi node is this instruction, then
1050 // this instruction is dead: both it (and the phi node) can be removed.
1051 use_nodbg_iterator I = MRI->use_nodbg_begin(Reg);
1052 use_nodbg_iterator End = MRI->use_nodbg_end();
1053 if (std::next(I) != End || !I->getParent()->isPHI())
1054 return false;
1055
1056 MachineInstr *OnePhi = I->getParent();
1057 for (unsigned j = 0, f = OnePhi->getNumOperands(); j != f; ++j) {
1058 const MachineOperand &OPO = OnePhi->getOperand(j);
1059 if (!OPO.isReg() || !OPO.isDef())
1060 continue;
1061
1062 Register OPReg = OPO.getReg();
1063 use_nodbg_iterator nextJ;
1064 for (use_nodbg_iterator J = MRI->use_nodbg_begin(OPReg);
1065 J != End; J = nextJ) {
1066 nextJ = std::next(J);
1067 MachineOperand &Use = *J;
1068 MachineInstr *UseMI = Use.getParent();
1069
1070 // If the phi node has a user that is not MI, bail.
1071 if (MI != UseMI)
1072 return false;
1073 }
1074 }
1075 DeadPhis.push_back(OnePhi);
1076 }
1077
1078 // If there are no defs with uses, the instruction is dead.
1079 return true;
1080}
1081
1082void HexagonHardwareLoops::removeIfDead(MachineInstr *MI) {
1083 // This procedure was essentially copied from DeadMachineInstructionElim.
1084
1085 SmallVector<MachineInstr*, 1> DeadPhis;
1086 if (isDead(MI, DeadPhis)) {
1087 LLVM_DEBUG(dbgs() << "HW looping will remove: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "HW looping will remove: " <<
*MI; } } while (false)
;
1088
1089 // It is possible that some DBG_VALUE instructions refer to this
1090 // instruction. Examine each def operand for such references;
1091 // if found, mark the DBG_VALUE as undef (but don't delete it).
1092 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1093 const MachineOperand &MO = MI->getOperand(i);
1094 if (!MO.isReg() || !MO.isDef())
1095 continue;
1096 Register Reg = MO.getReg();
1097 MachineRegisterInfo::use_iterator nextI;
1098 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
1099 E = MRI->use_end(); I != E; I = nextI) {
1100 nextI = std::next(I); // I is invalidated by the setReg
1101 MachineInstr *UseMI = I->getParent();
1102 if (UseMI == MI)
1103 continue;
1104 if (I->isDebug())
1105 I->setReg(0U);
1106 }
1107 }
1108
1109 MI->eraseFromParent();
1110 for (unsigned i = 0; i < DeadPhis.size(); ++i)
1111 DeadPhis[i]->eraseFromParent();
1112 }
1113}
1114
1115/// Check if the loop is a candidate for converting to a hardware
1116/// loop. If so, then perform the transformation.
1117///
1118/// This function works on innermost loops first. A loop can be converted
1119/// if it is a counting loop; either a register value or an immediate.
1120///
1121/// The code makes several assumptions about the representation of the loop
1122/// in llvm.
1123bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L,
1124 bool &RecL0used,
1125 bool &RecL1used) {
1126 // This is just for sanity.
1127 assert(L->getHeader() && "Loop without a header?")(static_cast <bool> (L->getHeader() && "Loop without a header?"
) ? void (0) : __assert_fail ("L->getHeader() && \"Loop without a header?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1127, __extension__ __PRETTY_FUNCTION__))
;
1128
1129 bool Changed = false;
1130 bool L0Used = false;
1131 bool L1Used = false;
1132
1133 // Process nested loops first.
1134 for (MachineLoop::iterator I = L->begin(), E = L->end(); I != E; ++I) {
1135 Changed |= convertToHardwareLoop(*I, RecL0used, RecL1used);
1136 L0Used |= RecL0used;
1137 L1Used |= RecL1used;
1138 }
1139
1140 // If a nested loop has been converted, then we can't convert this loop.
1141 if (Changed && L0Used && L1Used)
1142 return Changed;
1143
1144 unsigned LOOP_i;
1145 unsigned LOOP_r;
1146 unsigned ENDLOOP;
1147
1148 // Flag used to track loopN instruction:
1149 // 1 - Hardware loop is being generated for the inner most loop.
1150 // 0 - Hardware loop is being generated for the outer loop.
1151 unsigned IsInnerHWLoop = 1;
1152
1153 if (L0Used) {
1154 LOOP_i = Hexagon::J2_loop1i;
1155 LOOP_r = Hexagon::J2_loop1r;
1156 ENDLOOP = Hexagon::ENDLOOP1;
1157 IsInnerHWLoop = 0;
1158 } else {
1159 LOOP_i = Hexagon::J2_loop0i;
1160 LOOP_r = Hexagon::J2_loop0r;
1161 ENDLOOP = Hexagon::ENDLOOP0;
1162 }
1163
1164#ifndef NDEBUG
1165 // Stop trying after reaching the limit (if any).
1166 int Limit = HWLoopLimit;
1167 if (Limit >= 0) {
1168 if (Counter >= HWLoopLimit)
1169 return false;
1170 Counter++;
1171 }
1172#endif
1173
1174 // Does the loop contain any invalid instructions?
1175 if (containsInvalidInstruction(L, IsInnerHWLoop))
1176 return false;
1177
1178 MachineBasicBlock *LastMBB = L->findLoopControlBlock();
1179 // Don't generate hw loop if the loop has more than one exit.
1180 if (!LastMBB)
1181 return false;
1182
1183 MachineBasicBlock::iterator LastI = LastMBB->getFirstTerminator();
1184 if (LastI == LastMBB->end())
1185 return false;
1186
1187 // Is the induction variable bump feeding the latch condition?
1188 if (!fixupInductionVariable(L))
1189 return false;
1190
1191 // Ensure the loop has a preheader: the loop instruction will be
1192 // placed there.
1193 MachineBasicBlock *Preheader = MLI->findLoopPreheader(L, SpecPreheader);
1194 if (!Preheader) {
1195 Preheader = createPreheaderForLoop(L);
1196 if (!Preheader)
1197 return false;
1198 }
1199
1200 MachineBasicBlock::iterator InsertPos = Preheader->getFirstTerminator();
1201
1202 SmallVector<MachineInstr*, 2> OldInsts;
1203 // Are we able to determine the trip count for the loop?
1204 CountValue *TripCount = getLoopTripCount(L, OldInsts);
1205 if (!TripCount)
1206 return false;
1207
1208 // Is the trip count available in the preheader?
1209 if (TripCount->isReg()) {
1210 // There will be a use of the register inserted into the preheader,
1211 // so make sure that the register is actually defined at that point.
1212 MachineInstr *TCDef = MRI->getVRegDef(TripCount->getReg());
1213 MachineBasicBlock *BBDef = TCDef->getParent();
1214 if (!MDT->dominates(BBDef, Preheader))
1215 return false;
1216 }
1217
1218 // Determine the loop start.
1219 MachineBasicBlock *TopBlock = L->getTopBlock();
1220 MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
1221 MachineBasicBlock *LoopStart = nullptr;
1222 if (ExitingBlock != L->getLoopLatch()) {
1223 MachineBasicBlock *TB = nullptr, *FB = nullptr;
1224 SmallVector<MachineOperand, 2> Cond;
1225
1226 if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false))
1227 return false;
1228
1229 if (L->contains(TB))
1230 LoopStart = TB;
1231 else if (L->contains(FB))
1232 LoopStart = FB;
1233 else
1234 return false;
1235 }
1236 else
1237 LoopStart = TopBlock;
1238
1239 // Convert the loop to a hardware loop.
1240 LLVM_DEBUG(dbgs() << "Change to hardware loop at "; L->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "Change to hardware loop at ";
L->dump(); } } while (false)
;
1241 DebugLoc DL;
1242 if (InsertPos != Preheader->end())
1243 DL = InsertPos->getDebugLoc();
1244
1245 if (TripCount->isReg()) {
1246 // Create a copy of the loop count register.
1247 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1248 BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg)
1249 .addReg(TripCount->getReg(), 0, TripCount->getSubReg());
1250 // Add the Loop instruction to the beginning of the loop.
1251 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart)
1252 .addReg(CountReg);
1253 } else {
1254 assert(TripCount->isImm() && "Expecting immediate value for trip count")(static_cast <bool> (TripCount->isImm() && "Expecting immediate value for trip count"
) ? void (0) : __assert_fail ("TripCount->isImm() && \"Expecting immediate value for trip count\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1254, __extension__ __PRETTY_FUNCTION__))
;
1255 // Add the Loop immediate instruction to the beginning of the loop,
1256 // if the immediate fits in the instructions. Otherwise, we need to
1257 // create a new virtual register.
1258 int64_t CountImm = TripCount->getImm();
1259 if (!TII->isValidOffset(LOOP_i, CountImm, TRI)) {
1260 Register CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
1261 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg)
1262 .addImm(CountImm);
1263 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r))
1264 .addMBB(LoopStart).addReg(CountReg);
1265 } else
1266 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_i))
1267 .addMBB(LoopStart).addImm(CountImm);
1268 }
1269
1270 // Make sure the loop start always has a reference in the CFG. We need
1271 // to create a BlockAddress operand to get this mechanism to work both the
1272 // MachineBasicBlock and BasicBlock objects need the flag set.
1273 LoopStart->setHasAddressTaken();
1274 // This line is needed to set the hasAddressTaken flag on the BasicBlock
1275 // object.
1276 BlockAddress::get(const_cast<BasicBlock *>(LoopStart->getBasicBlock()));
1277
1278 // Replace the loop branch with an endloop instruction.
1279 DebugLoc LastIDL = LastI->getDebugLoc();
1280 BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart);
1281
1282 // The loop ends with either:
1283 // - a conditional branch followed by an unconditional branch, or
1284 // - a conditional branch to the loop start.
1285 if (LastI->getOpcode() == Hexagon::J2_jumpt ||
1286 LastI->getOpcode() == Hexagon::J2_jumpf) {
1287 // Delete one and change/add an uncond. branch to out of the loop.
1288 MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB();
1289 LastI = LastMBB->erase(LastI);
1290 if (!L->contains(BranchTarget)) {
1291 if (LastI != LastMBB->end())
1292 LastI = LastMBB->erase(LastI);
1293 SmallVector<MachineOperand, 0> Cond;
1294 TII->insertBranch(*LastMBB, BranchTarget, nullptr, Cond, LastIDL);
1295 }
1296 } else {
1297 // Conditional branch to loop start; just delete it.
1298 LastMBB->erase(LastI);
1299 }
1300 delete TripCount;
1301
1302 // The induction operation and the comparison may now be
1303 // unneeded. If these are unneeded, then remove them.
1304 for (unsigned i = 0; i < OldInsts.size(); ++i)
1305 removeIfDead(OldInsts[i]);
1306
1307 ++NumHWLoops;
1308
1309 // Set RecL1used and RecL0used only after hardware loop has been
1310 // successfully generated. Doing it earlier can cause wrong loop instruction
1311 // to be used.
1312 if (L0Used) // Loop0 was already used. So, the correct loop must be loop1.
1313 RecL1used = true;
1314 else
1315 RecL0used = true;
1316
1317 return true;
1318}
1319
1320bool HexagonHardwareLoops::orderBumpCompare(MachineInstr *BumpI,
1321 MachineInstr *CmpI) {
1322 assert (BumpI != CmpI && "Bump and compare in the same instruction?")(static_cast <bool> (BumpI != CmpI && "Bump and compare in the same instruction?"
) ? void (0) : __assert_fail ("BumpI != CmpI && \"Bump and compare in the same instruction?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1322, __extension__ __PRETTY_FUNCTION__))
;
1323
1324 MachineBasicBlock *BB = BumpI->getParent();
1325 if (CmpI->getParent() != BB)
1326 return false;
1327
1328 using instr_iterator = MachineBasicBlock::instr_iterator;
1329
1330 // Check if things are in order to begin with.
1331 for (instr_iterator I(BumpI), E = BB->instr_end(); I != E; ++I)
1332 if (&*I == CmpI)
1333 return true;
1334
1335 // Out of order.
1336 Register PredR = CmpI->getOperand(0).getReg();
1337 bool FoundBump = false;
1338 instr_iterator CmpIt = CmpI->getIterator(), NextIt = std::next(CmpIt);
1339 for (instr_iterator I = NextIt, E = BB->instr_end(); I != E; ++I) {
1340 MachineInstr *In = &*I;
1341 for (unsigned i = 0, n = In->getNumOperands(); i < n; ++i) {
1342 MachineOperand &MO = In->getOperand(i);
1343 if (MO.isReg() && MO.isUse()) {
1344 if (MO.getReg() == PredR) // Found an intervening use of PredR.
1345 return false;
1346 }
1347 }
1348
1349 if (In == BumpI) {
1350 BB->splice(++BumpI->getIterator(), BB, CmpI->getIterator());
1351 FoundBump = true;
1352 break;
1353 }
1354 }
1355 assert (FoundBump && "Cannot determine instruction order")(static_cast <bool> (FoundBump && "Cannot determine instruction order"
) ? void (0) : __assert_fail ("FoundBump && \"Cannot determine instruction order\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1355, __extension__ __PRETTY_FUNCTION__))
;
1356 return FoundBump;
1357}
1358
1359/// This function is required to break recursion. Visiting phis in a loop may
1360/// result in recursion during compilation. We break the recursion by making
1361/// sure that we visit a MachineOperand and its definition in a
1362/// MachineInstruction only once. If we attempt to visit more than once, then
1363/// there is recursion, and will return false.
1364bool HexagonHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A,
1365 MachineInstr *MI,
1366 const MachineOperand *MO,
1367 LoopFeederMap &LoopFeederPhi) const {
1368 if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) {
1369 LLVM_DEBUG(dbgs() << "\nhw_loop head, "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nhw_loop head, " << printMBBReference
(**L->block_begin()); } } while (false)
1370 << printMBBReference(**L->block_begin()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\nhw_loop head, " << printMBBReference
(**L->block_begin()); } } while (false)
;
1371 // Ignore all BBs that form Loop.
1372 if (llvm::is_contained(L->getBlocks(), A))
1373 return false;
1374 MachineInstr *Def = MRI->getVRegDef(MO->getReg());
1375 LoopFeederPhi.insert(std::make_pair(MO->getReg(), Def));
1376 return true;
1377 } else
1378 // Already visited node.
1379 return false;
1380}
1381
1382/// Return true if a Phi may generate a value that can underflow.
1383/// This function calls loopCountMayWrapOrUnderFlow for each Phi operand.
1384bool HexagonHardwareLoops::phiMayWrapOrUnderflow(
1385 MachineInstr *Phi, const MachineOperand *EndVal, MachineBasicBlock *MBB,
1386 MachineLoop *L, LoopFeederMap &LoopFeederPhi) const {
1387 assert(Phi->isPHI() && "Expecting a Phi.")(static_cast <bool> (Phi->isPHI() && "Expecting a Phi."
) ? void (0) : __assert_fail ("Phi->isPHI() && \"Expecting a Phi.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1387, __extension__ __PRETTY_FUNCTION__))
;
1388 // Walk through each Phi, and its used operands. Make sure that
1389 // if there is recursion in Phi, we won't generate hardware loops.
1390 for (int i = 1, n = Phi->getNumOperands(); i < n; i += 2)
1391 if (isLoopFeeder(L, MBB, Phi, &(Phi->getOperand(i)), LoopFeederPhi))
1392 if (loopCountMayWrapOrUnderFlow(&(Phi->getOperand(i)), EndVal,
1393 Phi->getParent(), L, LoopFeederPhi))
1394 return true;
1395 return false;
1396}
1397
1398/// Return true if the induction variable can underflow in the first iteration.
1399/// An example, is an initial unsigned value that is 0 and is decrement in the
1400/// first itertion of a do-while loop. In this case, we cannot generate a
1401/// hardware loop because the endloop instruction does not decrement the loop
1402/// counter if it is <= 1. We only need to perform this analysis if the
1403/// initial value is a register.
1404///
1405/// This function assumes the initial value may underfow unless proven
1406/// otherwise. If the type is signed, then we don't care because signed
1407/// underflow is undefined. We attempt to prove the initial value is not
1408/// zero by perfoming a crude analysis of the loop counter. This function
1409/// checks if the initial value is used in any comparison prior to the loop
1410/// and, if so, assumes the comparison is a range check. This is inexact,
1411/// but will catch the simple cases.
1412bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow(
1413 const MachineOperand *InitVal, const MachineOperand *EndVal,
1414 MachineBasicBlock *MBB, MachineLoop *L,
1415 LoopFeederMap &LoopFeederPhi) const {
1416 // Only check register values since they are unknown.
1417 if (!InitVal->isReg())
25
Calling 'MachineOperand::isReg'
27
Returning from 'MachineOperand::isReg'
28
Taking true branch
1418 return false;
29
Returning zero, which participates in a condition later
1419
1420 if (!EndVal->isImm())
1421 return false;
1422
1423 // A register value that is assigned an immediate is a known value, and it
1424 // won't underflow in the first iteration.
1425 int64_t Imm;
1426 if (checkForImmediate(*InitVal, Imm))
1427 return (EndVal->getImm() == Imm);
1428
1429 Register Reg = InitVal->getReg();
1430
1431 // We don't know the value of a physical register.
1432 if (!Reg.isVirtual())
1433 return true;
1434
1435 MachineInstr *Def = MRI->getVRegDef(Reg);
1436 if (!Def)
1437 return true;
1438
1439 // If the initial value is a Phi or copy and the operands may not underflow,
1440 // then the definition cannot be underflow either.
1441 if (Def->isPHI() && !phiMayWrapOrUnderflow(Def, EndVal, Def->getParent(),
1442 L, LoopFeederPhi))
1443 return false;
1444 if (Def->isCopy() && !loopCountMayWrapOrUnderFlow(&(Def->getOperand(1)),
1445 EndVal, Def->getParent(),
1446 L, LoopFeederPhi))
1447 return false;
1448
1449 // Iterate over the uses of the initial value. If the initial value is used
1450 // in a compare, then we assume this is a range check that ensures the loop
1451 // doesn't underflow. This is not an exact test and should be improved.
1452 for (MachineRegisterInfo::use_instr_nodbg_iterator I = MRI->use_instr_nodbg_begin(Reg),
1453 E = MRI->use_instr_nodbg_end(); I != E; ++I) {
1454 MachineInstr *MI = &*I;
1455 Register CmpReg1, CmpReg2;
1456 int64_t CmpMask = 0, CmpValue = 0;
1457
1458 if (!TII->analyzeCompare(*MI, CmpReg1, CmpReg2, CmpMask, CmpValue))
1459 continue;
1460
1461 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
1462 SmallVector<MachineOperand, 2> Cond;
1463 if (TII->analyzeBranch(*MI->getParent(), TBB, FBB, Cond, false))
1464 continue;
1465
1466 Comparison::Kind Cmp =
1467 getComparisonKind(MI->getOpcode(), nullptr, nullptr, 0);
1468 if (Cmp == 0)
1469 continue;
1470 if (TII->predOpcodeHasNot(Cond) ^ (TBB != MBB))
1471 Cmp = Comparison::getNegatedComparison(Cmp);
1472 if (CmpReg2 != 0 && CmpReg2 == Reg)
1473 Cmp = Comparison::getSwappedComparison(Cmp);
1474
1475 // Signed underflow is undefined.
1476 if (Comparison::isSigned(Cmp))
1477 return false;
1478
1479 // Check if there is a comparison of the initial value. If the initial value
1480 // is greater than or not equal to another value, then assume this is a
1481 // range check.
1482 if ((Cmp & Comparison::G) || Cmp == Comparison::NE)
1483 return false;
1484 }
1485
1486 // OK - this is a hack that needs to be improved. We really need to analyze
1487 // the instructions performed on the initial value. This works on the simplest
1488 // cases only.
1489 if (!Def->isCopy() && !Def->isPHI())
1490 return false;
1491
1492 return true;
1493}
1494
1495bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO,
1496 int64_t &Val) const {
1497 if (MO.isImm()) {
1498 Val = MO.getImm();
1499 return true;
1500 }
1501 if (!MO.isReg())
1502 return false;
1503
1504 // MO is a register. Check whether it is defined as an immediate value,
1505 // and if so, get the value of it in TV. That value will then need to be
1506 // processed to handle potential subregisters in MO.
1507 int64_t TV;
1508
1509 Register R = MO.getReg();
1510 if (!R.isVirtual())
1511 return false;
1512 MachineInstr *DI = MRI->getVRegDef(R);
1513 unsigned DOpc = DI->getOpcode();
1514 switch (DOpc) {
1515 case TargetOpcode::COPY:
1516 case Hexagon::A2_tfrsi:
1517 case Hexagon::A2_tfrpi:
1518 case Hexagon::CONST32:
1519 case Hexagon::CONST64:
1520 // Call recursively to avoid an extra check whether operand(1) is
1521 // indeed an immediate (it could be a global address, for example),
1522 // plus we can handle COPY at the same time.
1523 if (!checkForImmediate(DI->getOperand(1), TV))
1524 return false;
1525 break;
1526 case Hexagon::A2_combineii:
1527 case Hexagon::A4_combineir:
1528 case Hexagon::A4_combineii:
1529 case Hexagon::A4_combineri:
1530 case Hexagon::A2_combinew: {
1531 const MachineOperand &S1 = DI->getOperand(1);
1532 const MachineOperand &S2 = DI->getOperand(2);
1533 int64_t V1, V2;
1534 if (!checkForImmediate(S1, V1) || !checkForImmediate(S2, V2))
1535 return false;
1536 TV = V2 | (static_cast<uint64_t>(V1) << 32);
1537 break;
1538 }
1539 case TargetOpcode::REG_SEQUENCE: {
1540 const MachineOperand &S1 = DI->getOperand(1);
1541 const MachineOperand &S3 = DI->getOperand(3);
1542 int64_t V1, V3;
1543 if (!checkForImmediate(S1, V1) || !checkForImmediate(S3, V3))
1544 return false;
1545 unsigned Sub2 = DI->getOperand(2).getImm();
1546 unsigned Sub4 = DI->getOperand(4).getImm();
1547 if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi)
1548 TV = V1 | (V3 << 32);
1549 else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo)
1550 TV = V3 | (V1 << 32);
1551 else
1552 llvm_unreachable("Unexpected form of REG_SEQUENCE")::llvm::llvm_unreachable_internal("Unexpected form of REG_SEQUENCE"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1552)
;
1553 break;
1554 }
1555
1556 default:
1557 return false;
1558 }
1559
1560 // By now, we should have successfully obtained the immediate value defining
1561 // the register referenced in MO. Handle a potential use of a subregister.
1562 switch (MO.getSubReg()) {
1563 case Hexagon::isub_lo:
1564 Val = TV & 0xFFFFFFFFULL;
1565 break;
1566 case Hexagon::isub_hi:
1567 Val = (TV >> 32) & 0xFFFFFFFFULL;
1568 break;
1569 default:
1570 Val = TV;
1571 break;
1572 }
1573 return true;
1574}
1575
1576void HexagonHardwareLoops::setImmediate(MachineOperand &MO, int64_t Val) {
1577 if (MO.isImm()) {
1578 MO.setImm(Val);
1579 return;
1580 }
1581
1582 assert(MO.isReg())(static_cast <bool> (MO.isReg()) ? void (0) : __assert_fail
("MO.isReg()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1582, __extension__ __PRETTY_FUNCTION__))
;
1583 Register R = MO.getReg();
1584 MachineInstr *DI = MRI->getVRegDef(R);
1585
1586 const TargetRegisterClass *RC = MRI->getRegClass(R);
1587 Register NewR = MRI->createVirtualRegister(RC);
1588 MachineBasicBlock &B = *DI->getParent();
1589 DebugLoc DL = DI->getDebugLoc();
1590 BuildMI(B, DI, DL, TII->get(DI->getOpcode()), NewR).addImm(Val);
1591 MO.setReg(NewR);
1592}
1593
1594static bool isImmValidForOpcode(unsigned CmpOpc, int64_t Imm) {
1595 // These two instructions are not extendable.
1596 if (CmpOpc == Hexagon::A4_cmpbeqi)
1597 return isUInt<8>(Imm);
1598 if (CmpOpc == Hexagon::A4_cmpbgti)
1599 return isInt<8>(Imm);
1600 // The rest of the comparison-with-immediate instructions are extendable.
1601 return true;
1602}
1603
1604bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
1605 MachineBasicBlock *Header = L->getHeader();
1606 MachineBasicBlock *Latch = L->getLoopLatch();
1607 MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
1608
1609 if (!(Header && Latch && ExitingBlock))
1610 return false;
1611
1612 // These data structures follow the same concept as the corresponding
1613 // ones in findInductionRegister (where some comments are).
1614 using RegisterBump = std::pair<unsigned, int64_t>;
1615 using RegisterInduction = std::pair<unsigned, RegisterBump>;
1616 using RegisterInductionSet = std::set<RegisterInduction>;
1617
1618 // Register candidates for induction variables, with their associated bumps.
1619 RegisterInductionSet IndRegs;
1620
1621 // Look for induction patterns:
1622 // %1 = PHI ..., [ latch, %2 ]
1623 // %2 = ADD %1, imm
1624 using instr_iterator = MachineBasicBlock::instr_iterator;
1625
1626 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1627 I != E && I->isPHI(); ++I) {
1628 MachineInstr *Phi = &*I;
1629
1630 // Have a PHI instruction.
1631 for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
1632 if (Phi->getOperand(i+1).getMBB() != Latch)
1633 continue;
1634
1635 Register PhiReg = Phi->getOperand(i).getReg();
1636 MachineInstr *DI = MRI->getVRegDef(PhiReg);
1637
1638 if (DI->getDesc().isAdd()) {
1639 // If the register operand to the add/sub is the PHI we are looking
1640 // at, this meets the induction pattern.
1641 Register IndReg = DI->getOperand(1).getReg();
1642 MachineOperand &Opnd2 = DI->getOperand(2);
1643 int64_t V;
1644 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
1645 Register UpdReg = DI->getOperand(0).getReg();
1646 IndRegs.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
1647 }
1648 }
1649 } // for (i)
1650 } // for (instr)
1651
1652 if (IndRegs.empty())
1653 return false;
1654
1655 MachineBasicBlock *TB = nullptr, *FB = nullptr;
1656 SmallVector<MachineOperand,2> Cond;
1657 // analyzeBranch returns true if it fails to analyze branch.
1658 bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
1659 if (NotAnalyzed || Cond.empty())
1660 return false;
1661
1662 if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) {
1663 MachineBasicBlock *LTB = nullptr, *LFB = nullptr;
1664 SmallVector<MachineOperand,2> LCond;
1665 bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false);
1666 if (NotAnalyzed)
1667 return false;
1668
1669 // Since latch is not the exiting block, the latch branch should be an
1670 // unconditional branch to the loop header.
1671 if (TB == Latch)
1672 TB = (LTB == Header) ? LTB : LFB;
1673 else
1674 FB = (LTB == Header) ? LTB : LFB;
1675 }
1676 if (TB != Header) {
1677 if (FB != Header) {
1678 // The latch/exit block does not go back to the header.
1679 return false;
1680 }
1681 // FB is the header (i.e., uncond. jump to branch header)
1682 // In this case, the LoopBody -> TB should not be a back edge otherwise
1683 // it could result in an infinite loop after conversion to hw_loop.
1684 // This case can happen when the Latch has two jumps like this:
1685 // Jmp_c OuterLoopHeader <-- TB
1686 // Jmp InnerLoopHeader <-- FB
1687 if (MDT->dominates(TB, FB))
1688 return false;
1689 }
1690
1691 // Expecting a predicate register as a condition. It won't be a hardware
1692 // predicate register at this point yet, just a vreg.
1693 // HexagonInstrInfo::analyzeBranch for negated branches inserts imm(0)
1694 // into Cond, followed by the predicate register. For non-negated branches
1695 // it's just the register.
1696 unsigned CSz = Cond.size();
1697 if (CSz != 1 && CSz != 2)
1698 return false;
1699
1700 if (!Cond[CSz-1].isReg())
1701 return false;
1702
1703 Register P = Cond[CSz - 1].getReg();
1704 MachineInstr *PredDef = MRI->getVRegDef(P);
1705
1706 if (!PredDef->isCompare())
1707 return false;
1708
1709 SmallSet<unsigned,2> CmpRegs;
1710 MachineOperand *CmpImmOp = nullptr;
1711
1712 // Go over all operands to the compare and look for immediate and register
1713 // operands. Assume that if the compare has a single register use and a
1714 // single immediate operand, then the register is being compared with the
1715 // immediate value.
1716 for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
1717 MachineOperand &MO = PredDef->getOperand(i);
1718 if (MO.isReg()) {
1719 // Skip all implicit references. In one case there was:
1720 // %140 = FCMPUGT32_rr %138, %139, implicit %usr
1721 if (MO.isImplicit())
1722 continue;
1723 if (MO.isUse()) {
1724 if (!isImmediate(MO)) {
1725 CmpRegs.insert(MO.getReg());
1726 continue;
1727 }
1728 // Consider the register to be the "immediate" operand.
1729 if (CmpImmOp)
1730 return false;
1731 CmpImmOp = &MO;
1732 }
1733 } else if (MO.isImm()) {
1734 if (CmpImmOp) // A second immediate argument? Confusing. Bail out.
1735 return false;
1736 CmpImmOp = &MO;
1737 }
1738 }
1739
1740 if (CmpRegs.empty())
1741 return false;
1742
1743 // Check if the compared register follows the order we want. Fix if needed.
1744 for (RegisterInductionSet::iterator I = IndRegs.begin(), E = IndRegs.end();
1745 I != E; ++I) {
1746 // This is a success. If the register used in the comparison is one that
1747 // we have identified as a bumped (updated) induction register, there is
1748 // nothing to do.
1749 if (CmpRegs.count(I->first))
1750 return true;
1751
1752 // Otherwise, if the register being compared comes out of a PHI node,
1753 // and has been recognized as following the induction pattern, and is
1754 // compared against an immediate, we can fix it.
1755 const RegisterBump &RB = I->second;
1756 if (CmpRegs.count(RB.first)) {
1757 if (!CmpImmOp) {
1758 // If both operands to the compare instruction are registers, see if
1759 // it can be changed to use induction register as one of the operands.
1760 MachineInstr *IndI = nullptr;
1761 MachineInstr *nonIndI = nullptr;
1762 MachineOperand *IndMO = nullptr;
1763 MachineOperand *nonIndMO = nullptr;
1764
1765 for (unsigned i = 1, n = PredDef->getNumOperands(); i < n; ++i) {
1766 MachineOperand &MO = PredDef->getOperand(i);
1767 if (MO.isReg() && MO.getReg() == RB.first) {
1768 LLVM_DEBUG(dbgs() << "\n DefMI(" << ido { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\n DefMI(" << i <<
") = " << *(MRI->getVRegDef(I->first)); } } while
(false)
1769 << ") = " << *(MRI->getVRegDef(I->first)))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\n DefMI(" << i <<
") = " << *(MRI->getVRegDef(I->first)); } } while
(false)
;
1770 if (IndI)
1771 return false;
1772
1773 IndI = MRI->getVRegDef(I->first);
1774 IndMO = &MO;
1775 } else if (MO.isReg()) {
1776 LLVM_DEBUG(dbgs() << "\n DefMI(" << ido { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\n DefMI(" << i <<
") = " << *(MRI->getVRegDef(MO.getReg())); } } while
(false)
1777 << ") = " << *(MRI->getVRegDef(MO.getReg())))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hwloops")) { dbgs() << "\n DefMI(" << i <<
") = " << *(MRI->getVRegDef(MO.getReg())); } } while
(false)
;
1778 if (nonIndI)
1779 return false;
1780
1781 nonIndI = MRI->getVRegDef(MO.getReg());
1782 nonIndMO = &MO;
1783 }
1784 }
1785 if (IndI && nonIndI &&
1786 nonIndI->getOpcode() == Hexagon::A2_addi &&
1787 nonIndI->getOperand(2).isImm() &&
1788 nonIndI->getOperand(2).getImm() == - RB.second) {
1789 bool Order = orderBumpCompare(IndI, PredDef);
1790 if (Order) {
1791 IndMO->setReg(I->first);
1792 nonIndMO->setReg(nonIndI->getOperand(1).getReg());
1793 return true;
1794 }
1795 }
1796 return false;
1797 }
1798
1799 // It is not valid to do this transformation on an unsigned comparison
1800 // because it may underflow.
1801 Comparison::Kind Cmp =
1802 getComparisonKind(PredDef->getOpcode(), nullptr, nullptr, 0);
1803 if (!Cmp || Comparison::isUnsigned(Cmp))
1804 return false;
1805
1806 // If the register is being compared against an immediate, try changing
1807 // the compare instruction to use induction register and adjust the
1808 // immediate operand.
1809 int64_t CmpImm = getImmediate(*CmpImmOp);
1810 int64_t V = RB.second;
1811 // Handle Overflow (64-bit).
1812 if (((V > 0) && (CmpImm > INT64_MAX(9223372036854775807L) - V)) ||
1813 ((V < 0) && (CmpImm < INT64_MIN(-9223372036854775807L -1) - V)))
1814 return false;
1815 CmpImm += V;
1816 // Most comparisons of register against an immediate value allow
1817 // the immediate to be constant-extended. There are some exceptions
1818 // though. Make sure the new combination will work.
1819 if (CmpImmOp->isImm())
1820 if (!isImmValidForOpcode(PredDef->getOpcode(), CmpImm))
1821 return false;
1822
1823 // Make sure that the compare happens after the bump. Otherwise,
1824 // after the fixup, the compare would use a yet-undefined register.
1825 MachineInstr *BumpI = MRI->getVRegDef(I->first);
1826 bool Order = orderBumpCompare(BumpI, PredDef);
1827 if (!Order)
1828 return false;
1829
1830 // Finally, fix the compare instruction.
1831 setImmediate(*CmpImmOp, CmpImm);
1832 for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
1833 MachineOperand &MO = PredDef->getOperand(i);
1834 if (MO.isReg() && MO.getReg() == RB.first) {
1835 MO.setReg(I->first);
1836 return true;
1837 }
1838 }
1839 }
1840 }
1841
1842 return false;
1843}
1844
1845/// createPreheaderForLoop - Create a preheader for a given loop.
1846MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
1847 MachineLoop *L) {
1848 if (MachineBasicBlock *TmpPH = MLI->findLoopPreheader(L, SpecPreheader))
1849 return TmpPH;
1850 if (!HWCreatePreheader)
1851 return nullptr;
1852
1853 MachineBasicBlock *Header = L->getHeader();
1854 MachineBasicBlock *Latch = L->getLoopLatch();
1855 MachineBasicBlock *ExitingBlock = L->findLoopControlBlock();
1856 MachineFunction *MF = Header->getParent();
1857 DebugLoc DL;
1858
1859#ifndef NDEBUG
1860 if ((!PHFn.empty()) && (PHFn != MF->getName()))
1861 return nullptr;
1862#endif
1863
1864 if (!Latch || !ExitingBlock || Header->hasAddressTaken())
1865 return nullptr;
1866
1867 using instr_iterator = MachineBasicBlock::instr_iterator;
1868
1869 // Verify that all existing predecessors have analyzable branches
1870 // (or no branches at all).
1871 using MBBVector = std::vector<MachineBasicBlock *>;
1872
1873 MBBVector Preds(Header->pred_begin(), Header->pred_end());
1874 SmallVector<MachineOperand,2> Tmp1;
1875 MachineBasicBlock *TB = nullptr, *FB = nullptr;
1876
1877 if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false))
1878 return nullptr;
1879
1880 for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
1881 MachineBasicBlock *PB = *I;
1882 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false);
1883 if (NotAnalyzed)
1884 return nullptr;
1885 }
1886
1887 MachineBasicBlock *NewPH = MF->CreateMachineBasicBlock();
1888 MF->insert(Header->getIterator(), NewPH);
1889
1890 if (Header->pred_size() > 2) {
1891 // Ensure that the header has only two predecessors: the preheader and
1892 // the loop latch. Any additional predecessors of the header should
1893 // join at the newly created preheader. Inspect all PHI nodes from the
1894 // header and create appropriate corresponding PHI nodes in the preheader.
1895
1896 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1897 I != E && I->isPHI(); ++I) {
1898 MachineInstr *PN = &*I;
1899
1900 const MCInstrDesc &PD = TII->get(TargetOpcode::PHI);
1901 MachineInstr *NewPN = MF->CreateMachineInstr(PD, DL);
1902 NewPH->insert(NewPH->end(), NewPN);
1903
1904 Register PR = PN->getOperand(0).getReg();
1905 const TargetRegisterClass *RC = MRI->getRegClass(PR);
1906 Register NewPR = MRI->createVirtualRegister(RC);
1907 NewPN->addOperand(MachineOperand::CreateReg(NewPR, true));
1908
1909 // Copy all non-latch operands of a header's PHI node to the newly
1910 // created PHI node in the preheader.
1911 for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
1912 Register PredR = PN->getOperand(i).getReg();
1913 unsigned PredRSub = PN->getOperand(i).getSubReg();
1914 MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
1915 if (PredB == Latch)
1916 continue;
1917
1918 MachineOperand MO = MachineOperand::CreateReg(PredR, false);
1919 MO.setSubReg(PredRSub);
1920 NewPN->addOperand(MO);
1921 NewPN->addOperand(MachineOperand::CreateMBB(PredB));
1922 }
1923
1924 // Remove copied operands from the old PHI node and add the value
1925 // coming from the preheader's PHI.
1926 for (int i = PN->getNumOperands()-2; i > 0; i -= 2) {
1927 MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
1928 if (PredB != Latch) {
1929 PN->RemoveOperand(i+1);
1930 PN->RemoveOperand(i);
1931 }
1932 }
1933 PN->addOperand(MachineOperand::CreateReg(NewPR, false));
1934 PN->addOperand(MachineOperand::CreateMBB(NewPH));
1935 }
1936 } else {
1937 assert(Header->pred_size() == 2)(static_cast <bool> (Header->pred_size() == 2) ? void
(0) : __assert_fail ("Header->pred_size() == 2", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1937, __extension__ __PRETTY_FUNCTION__))
;
1938
1939 // The header has only two predecessors, but the non-latch predecessor
1940 // is not a preheader (e.g. it has other successors, etc.)
1941 // In such a case we don't need any extra PHI nodes in the new preheader,
1942 // all we need is to adjust existing PHIs in the header to now refer to
1943 // the new preheader.
1944 for (instr_iterator I = Header->instr_begin(), E = Header->instr_end();
1945 I != E && I->isPHI(); ++I) {
1946 MachineInstr *PN = &*I;
1947 for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
1948 MachineOperand &MO = PN->getOperand(i+1);
1949 if (MO.getMBB() != Latch)
1950 MO.setMBB(NewPH);
1951 }
1952 }
1953 }
1954
1955 // "Reroute" the CFG edges to link in the new preheader.
1956 // If any of the predecessors falls through to the header, insert a branch
1957 // to the new preheader in that place.
1958 SmallVector<MachineOperand,1> Tmp2;
1959 SmallVector<MachineOperand,1> EmptyCond;
1960
1961 TB = FB = nullptr;
1962
1963 for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) {
1964 MachineBasicBlock *PB = *I;
1965 if (PB != Latch) {
1966 Tmp2.clear();
1967 bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false);
1968 (void)NotAnalyzed; // suppress compiler warning
1969 assert (!NotAnalyzed && "Should be analyzable!")(static_cast <bool> (!NotAnalyzed && "Should be analyzable!"
) ? void (0) : __assert_fail ("!NotAnalyzed && \"Should be analyzable!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1969, __extension__ __PRETTY_FUNCTION__))
;
1970 if (TB != Header && (Tmp2.empty() || FB != Header))
1971 TII->insertBranch(*PB, NewPH, nullptr, EmptyCond, DL);
1972 PB->ReplaceUsesOfBlockWith(Header, NewPH);
1973 }
1974 }
1975
1976 // It can happen that the latch block will fall through into the header.
1977 // Insert an unconditional branch to the header.
1978 TB = FB = nullptr;
1979 bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false);
1980 (void)LatchNotAnalyzed; // suppress compiler warning
1981 assert (!LatchNotAnalyzed && "Should be analyzable!")(static_cast <bool> (!LatchNotAnalyzed && "Should be analyzable!"
) ? void (0) : __assert_fail ("!LatchNotAnalyzed && \"Should be analyzable!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp"
, 1981, __extension__ __PRETTY_FUNCTION__))
;
1982 if (!TB && !FB)
1983 TII->insertBranch(*Latch, Header, nullptr, EmptyCond, DL);
1984
1985 // Finally, the branch from the preheader to the header.
1986 TII->insertBranch(*NewPH, Header, nullptr, EmptyCond, DL);
1987 NewPH->addSuccessor(Header);
1988
1989 MachineLoop *ParentLoop = L->getParentLoop();
1990 if (ParentLoop)
1991 ParentLoop->addBasicBlockToLoop(NewPH, MLI->getBase());
1992
1993 // Update the dominator information with the new preheader.
1994 if (MDT) {
1995 if (MachineDomTreeNode *HN = MDT->getNode(Header)) {
1996 if (MachineDomTreeNode *DHN = HN->getIDom()) {
1997 MDT->addNewBlock(NewPH, DHN->getBlock());
1998 MDT->changeImmediateDominator(Header, NewPH);
1999 }
2000 }
2001 }
2002
2003 return NewPH;
2004}

/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h

1//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineOperand class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEOPERAND_H
14#define LLVM_CODEGEN_MACHINEOPERAND_H
15
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/CodeGen/Register.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/DataTypes.h"
20#include "llvm/Support/LowLevelTypeImpl.h"
21#include <cassert>
22
23namespace llvm {
24
25class BlockAddress;
26class Constant;
27class ConstantFP;
28class ConstantInt;
29class GlobalValue;
30class MachineBasicBlock;
31class MachineInstr;
32class MachineRegisterInfo;
33class MCCFIInstruction;
34class MDNode;
35class ModuleSlotTracker;
36class TargetIntrinsicInfo;
37class TargetRegisterInfo;
38class hash_code;
39class raw_ostream;
40class MCSymbol;
41
42/// MachineOperand class - Representation of each machine instruction operand.
43///
44/// This class isn't a POD type because it has a private constructor, but its
45/// destructor must be trivial. Functions like MachineInstr::addOperand(),
46/// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
47/// not having to call the MachineOperand destructor.
48///
49class MachineOperand {
50public:
51 enum MachineOperandType : unsigned char {
52 MO_Register, ///< Register operand.
53 MO_Immediate, ///< Immediate operand
54 MO_CImmediate, ///< Immediate >64bit operand
55 MO_FPImmediate, ///< Floating-point immediate operand
56 MO_MachineBasicBlock, ///< MachineBasicBlock reference
57 MO_FrameIndex, ///< Abstract Stack Frame Index
58 MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
59 MO_TargetIndex, ///< Target-dependent index+offset operand.
60 MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
61 MO_ExternalSymbol, ///< Name of external global symbol
62 MO_GlobalAddress, ///< Address of a global value
63 MO_BlockAddress, ///< Address of a basic block
64 MO_RegisterMask, ///< Mask of preserved registers.
65 MO_RegisterLiveOut, ///< Mask of live-out registers.
66 MO_Metadata, ///< Metadata reference (for debug info)
67 MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
68 MO_CFIIndex, ///< MCCFIInstruction index.
69 MO_IntrinsicID, ///< Intrinsic ID for ISel
70 MO_Predicate, ///< Generic predicate for ISel
71 MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
72 MO_Last = MO_ShuffleMask
73 };
74
75private:
76 /// OpKind - Specify what kind of operand this is. This discriminates the
77 /// union.
78 unsigned OpKind : 8;
79
80 /// Subregister number for MO_Register. A value of 0 indicates the
81 /// MO_Register has no subReg.
82 ///
83 /// For all other kinds of operands, this field holds target-specific flags.
84 unsigned SubReg_TargetFlags : 12;
85
86 /// TiedTo - Non-zero when this register operand is tied to another register
87 /// operand. The encoding of this field is described in the block comment
88 /// before MachineInstr::tieOperands().
89 unsigned TiedTo : 4;
90
91 /// IsDef - True if this is a def, false if this is a use of the register.
92 /// This is only valid on register operands.
93 ///
94 unsigned IsDef : 1;
95
96 /// IsImp - True if this is an implicit def or use, false if it is explicit.
97 /// This is only valid on register opderands.
98 ///
99 unsigned IsImp : 1;
100
101 /// IsDeadOrKill
102 /// For uses: IsKill - Conservatively indicates the last use of a register
103 /// on this path through the function. A register operand with true value of
104 /// this flag must be the last use of the register, a register operand with
105 /// false value may or may not be the last use of the register. After regalloc
106 /// we can use recomputeLivenessFlags to get precise kill flags.
107 /// For defs: IsDead - True if this register is never used by a subsequent
108 /// instruction.
109 /// This is only valid on register operands.
110 unsigned IsDeadOrKill : 1;
111
112 /// See isRenamable().
113 unsigned IsRenamable : 1;
114
115 /// IsUndef - True if this register operand reads an "undef" value, i.e. the
116 /// read value doesn't matter. This flag can be set on both use and def
117 /// operands. On a sub-register def operand, it refers to the part of the
118 /// register that isn't written. On a full-register def operand, it is a
119 /// noop. See readsReg().
120 ///
121 /// This is only valid on registers.
122 ///
123 /// Note that an instruction may have multiple <undef> operands referring to
124 /// the same register. In that case, the instruction may depend on those
125 /// operands reading the same dont-care value. For example:
126 ///
127 /// %1 = XOR undef %2, undef %2
128 ///
129 /// Any register can be used for %2, and its value doesn't matter, but
130 /// the two operands must be the same register.
131 ///
132 unsigned IsUndef : 1;
133
134 /// IsInternalRead - True if this operand reads a value that was defined
135 /// inside the same instruction or bundle. This flag can be set on both use
136 /// and def operands. On a sub-register def operand, it refers to the part
137 /// of the register that isn't written. On a full-register def operand, it
138 /// is a noop.
139 ///
140 /// When this flag is set, the instruction bundle must contain at least one
141 /// other def of the register. If multiple instructions in the bundle define
142 /// the register, the meaning is target-defined.
143 unsigned IsInternalRead : 1;
144
145 /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
146 /// by the MachineInstr before all input registers are read. This is used to
147 /// model the GCC inline asm '&' constraint modifier.
148 unsigned IsEarlyClobber : 1;
149
150 /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
151 /// not a real instruction. Such uses should be ignored during codegen.
152 unsigned IsDebug : 1;
153
154 /// SmallContents - This really should be part of the Contents union, but
155 /// lives out here so we can get a better packed struct.
156 /// MO_Register: Register number.
157 /// OffsetedInfo: Low bits of offset.
158 union {
159 unsigned RegNo; // For MO_Register.
160 unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
161 } SmallContents;
162
163 /// ParentMI - This is the instruction that this operand is embedded into.
164 /// This is valid for all operand types, when the operand is in an instr.
165 MachineInstr *ParentMI;
166
167 /// Contents union - This contains the payload for the various operand types.
168 union ContentsUnion {
169 ContentsUnion() {}
170 MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
171 const ConstantFP *CFP; // For MO_FPImmediate.
172 const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
173 int64_t ImmVal; // For MO_Immediate.
174 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
175 const MDNode *MD; // For MO_Metadata.
176 MCSymbol *Sym; // For MO_MCSymbol.
177 unsigned CFIIndex; // For MO_CFI.
178 Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
179 unsigned Pred; // For MO_Predicate
180 ArrayRef<int> ShuffleMask; // For MO_ShuffleMask
181
182 struct { // For MO_Register.
183 // Register number is in SmallContents.RegNo.
184 MachineOperand *Prev; // Access list for register. See MRI.
185 MachineOperand *Next;
186 } Reg;
187
188 /// OffsetedInfo - This struct contains the offset and an object identifier.
189 /// this represent the object as with an optional offset from it.
190 struct {
191 union {
192 int Index; // For MO_*Index - The index itself.
193 const char *SymbolName; // For MO_ExternalSymbol.
194 const GlobalValue *GV; // For MO_GlobalAddress.
195 const BlockAddress *BA; // For MO_BlockAddress.
196 } Val;
197 // Low bits of offset are in SmallContents.OffsetLo.
198 int OffsetHi; // An offset from the object, high 32 bits.
199 } OffsetedInfo;
200 } Contents;
201
202 explicit MachineOperand(MachineOperandType K)
203 : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
204 // Assert that the layout is what we expect. It's easy to grow this object.
205 static_assert(alignof(MachineOperand) <= alignof(int64_t),
206 "MachineOperand shouldn't be more than 8 byte aligned");
207 static_assert(sizeof(Contents) <= 2 * sizeof(void *),
208 "Contents should be at most two pointers");
209 static_assert(sizeof(MachineOperand) <=
210 alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
211 3 * sizeof(void *)),
212 "MachineOperand too big. Should be Kind, SmallContents, "
213 "ParentMI, and Contents");
214 }
215
216public:
217 /// getType - Returns the MachineOperandType for this operand.
218 ///
219 MachineOperandType getType() const { return (MachineOperandType)OpKind; }
220
221 unsigned getTargetFlags() const {
222 return isReg() ? 0 : SubReg_TargetFlags;
223 }
224 void setTargetFlags(unsigned F) {
225 assert(!isReg() && "Register operands can't have target flags")(static_cast <bool> (!isReg() && "Register operands can't have target flags"
) ? void (0) : __assert_fail ("!isReg() && \"Register operands can't have target flags\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 225, __extension__ __PRETTY_FUNCTION__))
;
226 SubReg_TargetFlags = F;
227 assert(SubReg_TargetFlags == F && "Target flags out of range")(static_cast <bool> (SubReg_TargetFlags == F &&
"Target flags out of range") ? void (0) : __assert_fail ("SubReg_TargetFlags == F && \"Target flags out of range\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 227, __extension__ __PRETTY_FUNCTION__))
;
228 }
229 void addTargetFlag(unsigned F) {
230 assert(!isReg() && "Register operands can't have target flags")(static_cast <bool> (!isReg() && "Register operands can't have target flags"
) ? void (0) : __assert_fail ("!isReg() && \"Register operands can't have target flags\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 230, __extension__ __PRETTY_FUNCTION__))
;
231 SubReg_TargetFlags |= F;
232 assert((SubReg_TargetFlags & F) && "Target flags out of range")(static_cast <bool> ((SubReg_TargetFlags & F) &&
"Target flags out of range") ? void (0) : __assert_fail ("(SubReg_TargetFlags & F) && \"Target flags out of range\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 232, __extension__ __PRETTY_FUNCTION__))
;
233 }
234
235
236 /// getParent - Return the instruction that this operand belongs to.
237 ///
238 MachineInstr *getParent() { return ParentMI; }
239 const MachineInstr *getParent() const { return ParentMI; }
240
241 /// clearParent - Reset the parent pointer.
242 ///
243 /// The MachineOperand copy constructor also copies ParentMI, expecting the
244 /// original to be deleted. If a MachineOperand is ever stored outside a
245 /// MachineInstr, the parent pointer must be cleared.
246 ///
247 /// Never call clearParent() on an operand in a MachineInstr.
248 ///
249 void clearParent() { ParentMI = nullptr; }
250
251 /// Print a subreg index operand.
252 /// MO_Immediate operands can also be subreg idices. If it's the case, the
253 /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
254 /// called to check this.
255 static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
256 const TargetRegisterInfo *TRI);
257
258 /// Print operand target flags.
259 static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
260
261 /// Print a MCSymbol as an operand.
262 static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
263
264 /// Print a stack object reference.
265 static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
266 bool IsFixed, StringRef Name);
267
268 /// Print the offset with explicit +/- signs.
269 static void printOperandOffset(raw_ostream &OS, int64_t Offset);
270
271 /// Print an IRSlotNumber.
272 static void printIRSlotNumber(raw_ostream &OS, int Slot);
273
274 /// Print the MachineOperand to \p os.
275 /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
276 /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
277 /// function will try to pick it up from the parent.
278 void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
279 const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
280
281 /// More complex way of printing a MachineOperand.
282 /// \param TypeToPrint specifies the generic type to be printed on uses and
283 /// defs. It can be determined using MachineInstr::getTypeToPrint.
284 /// \param OpIdx - specifies the index of the operand in machine instruction.
285 /// This will be used by target dependent MIR formatter. Could be None if the
286 /// index is unknown, e.g. called by dump().
287 /// \param PrintDef - whether we want to print `def` on an operand which
288 /// isDef. Sometimes, if the operand is printed before '=', we don't print
289 /// `def`.
290 /// \param IsStandalone - whether we want a verbose output of the MO. This
291 /// prints extra information that can be easily inferred when printing the
292 /// whole function, but not when printing only a fragment of it.
293 /// \param ShouldPrintRegisterTies - whether we want to print register ties.
294 /// Sometimes they are easily determined by the instruction's descriptor
295 /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
296 /// \param TiedOperandIdx - if we need to print register ties this needs to
297 /// provide the index of the tied register. If not, it will be ignored.
298 /// \param TRI - provide more target-specific information to the printer.
299 /// Unlike the previous function, this one will not try and get the
300 /// information from it's parent.
301 /// \param IntrinsicInfo - same as \p TRI.
302 void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
303 Optional<unsigned> OpIdx, bool PrintDef, bool IsStandalone,
304 bool ShouldPrintRegisterTies, unsigned TiedOperandIdx,
305 const TargetRegisterInfo *TRI,
306 const TargetIntrinsicInfo *IntrinsicInfo) const;
307
308 /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
309 /// type to be printed the same way the full version of print(...) does it.
310 void print(raw_ostream &os, LLT TypeToPrint,
311 const TargetRegisterInfo *TRI = nullptr,
312 const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
313
314 void dump() const;
315
316 //===--------------------------------------------------------------------===//
317 // Accessors that tell you what kind of MachineOperand you're looking at.
318 //===--------------------------------------------------------------------===//
319
320 /// isReg - Tests if this is a MO_Register operand.
321 bool isReg() const { return OpKind
4.1
Field 'OpKind' is not equal to MO_Register
11.1
Field 'OpKind' is not equal to MO_Register
4.1
Field 'OpKind' is not equal to MO_Register
11.1
Field 'OpKind' is not equal to MO_Register
== MO_Register
; }
5
Returning zero, which participates in a condition later
12
Returning zero, which participates in a condition later
26
Returning zero, which participates in a condition later
322 /// isImm - Tests if this is a MO_Immediate operand.
323 bool isImm() const { return OpKind == MO_Immediate; }
8
Assuming field 'OpKind' is equal to MO_Immediate
9
Returning the value 1, which participates in a condition later
15
Assuming field 'OpKind' is equal to MO_Immediate
16
Returning the value 1, which participates in a condition later
32
Returning the value 1, which participates in a condition later
35
Returning the value 1, which participates in a condition later
324 /// isCImm - Test if this is a MO_CImmediate operand.
325 bool isCImm() const { return OpKind == MO_CImmediate; }
326 /// isFPImm - Tests if this is a MO_FPImmediate operand.
327 bool isFPImm() const { return OpKind == MO_FPImmediate; }
328 /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
329 bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
330 /// isFI - Tests if this is a MO_FrameIndex operand.
331 bool isFI() const { return OpKind == MO_FrameIndex; }
332 /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
333 bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
334 /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
335 bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
336 /// isJTI - Tests if this is a MO_JumpTableIndex operand.
337 bool isJTI() const { return OpKind == MO_JumpTableIndex; }
338 /// isGlobal - Tests if this is a MO_GlobalAddress operand.
339 bool isGlobal() const { return OpKind == MO_GlobalAddress; }
340 /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
341 bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
342 /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
343 bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
344 /// isRegMask - Tests if this is a MO_RegisterMask operand.
345 bool isRegMask() const { return OpKind == MO_RegisterMask; }
346 /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
347 bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
348 /// isMetadata - Tests if this is a MO_Metadata operand.
349 bool isMetadata() const { return OpKind == MO_Metadata; }
350 bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
351 bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
352 bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
353 bool isPredicate() const { return OpKind == MO_Predicate; }
354 bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
355 //===--------------------------------------------------------------------===//
356 // Accessors for Register Operands
357 //===--------------------------------------------------------------------===//
358
359 /// getReg - Returns the register number.
360 Register getReg() const {
361 assert(isReg() && "This is not a register operand!")(static_cast <bool> (isReg() && "This is not a register operand!"
) ? void (0) : __assert_fail ("isReg() && \"This is not a register operand!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 361, __extension__ __PRETTY_FUNCTION__))
;
362 return Register(SmallContents.RegNo);
363 }
364
365 unsigned getSubReg() const {
366 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 366, __extension__ __PRETTY_FUNCTION__))
;
367 return SubReg_TargetFlags;
368 }
369
370 bool isUse() const {
371 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 371, __extension__ __PRETTY_FUNCTION__))
;
372 return !IsDef;
373 }
374
375 bool isDef() const {
376 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 376, __extension__ __PRETTY_FUNCTION__))
;
377 return IsDef;
378 }
379
380 bool isImplicit() const {
381 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 381, __extension__ __PRETTY_FUNCTION__))
;
382 return IsImp;
383 }
384
385 bool isDead() const {
386 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 386, __extension__ __PRETTY_FUNCTION__))
;
387 return IsDeadOrKill & IsDef;
388 }
389
390 bool isKill() const {
391 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 391, __extension__ __PRETTY_FUNCTION__))
;
392 return IsDeadOrKill & !IsDef;
393 }
394
395 bool isUndef() const {
396 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 396, __extension__ __PRETTY_FUNCTION__))
;
397 return IsUndef;
398 }
399
400 /// isRenamable - Returns true if this register may be renamed, i.e. it does
401 /// not generate a value that is somehow read in a way that is not represented
402 /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
403 /// valid on physical register operands. Virtual registers are assumed to
404 /// always be renamable regardless of the value of this field.
405 ///
406 /// Operands that are renamable can freely be changed to any other register
407 /// that is a member of the register class returned by
408 /// MI->getRegClassConstraint().
409 ///
410 /// isRenamable can return false for several different reasons:
411 ///
412 /// - ABI constraints (since liveness is not always precisely modeled). We
413 /// conservatively handle these cases by setting all physical register
414 /// operands that didn’t start out as virtual regs to not be renamable.
415 /// Also any physical register operands created after register allocation or
416 /// whose register is changed after register allocation will not be
417 /// renamable. This state is tracked in the MachineOperand::IsRenamable
418 /// bit.
419 ///
420 /// - Opcode/target constraints: for opcodes that have complex register class
421 /// requirements (e.g. that depend on other operands/instructions), we set
422 /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
423 /// description. Operands belonging to instructions with opcodes that are
424 /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
425 /// isRenamable(). Additionally, the AllowRegisterRenaming target property
426 /// prevents any operands from being marked renamable for targets that don't
427 /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
428 /// values.
429 bool isRenamable() const;
430
431 bool isInternalRead() const {
432 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 432, __extension__ __PRETTY_FUNCTION__))
;
433 return IsInternalRead;
434 }
435
436 bool isEarlyClobber() const {
437 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 437, __extension__ __PRETTY_FUNCTION__))
;
438 return IsEarlyClobber;
439 }
440
441 bool isTied() const {
442 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 442, __extension__ __PRETTY_FUNCTION__))
;
443 return TiedTo;
444 }
445
446 bool isDebug() const {
447 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 447, __extension__ __PRETTY_FUNCTION__))
;
448 return IsDebug;
449 }
450
451 /// readsReg - Returns true if this operand reads the previous value of its
452 /// register. A use operand with the <undef> flag set doesn't read its
453 /// register. A sub-register def implicitly reads the other parts of the
454 /// register being redefined unless the <undef> flag is set.
455 ///
456 /// This refers to reading the register value from before the current
457 /// instruction or bundle. Internal bundle reads are not included.
458 bool readsReg() const {
459 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 459, __extension__ __PRETTY_FUNCTION__))
;
460 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
461 }
462
463 //===--------------------------------------------------------------------===//
464 // Mutators for Register Operands
465 //===--------------------------------------------------------------------===//
466
467 /// Change the register this operand corresponds to.
468 ///
469 void setReg(Register Reg);
470
471 void setSubReg(unsigned subReg) {
472 assert(isReg() && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 472, __extension__ __PRETTY_FUNCTION__))
;
473 SubReg_TargetFlags = subReg;
474 assert(SubReg_TargetFlags == subReg && "SubReg out of range")(static_cast <bool> (SubReg_TargetFlags == subReg &&
"SubReg out of range") ? void (0) : __assert_fail ("SubReg_TargetFlags == subReg && \"SubReg out of range\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 474, __extension__ __PRETTY_FUNCTION__))
;
475 }
476
477 /// substVirtReg - Substitute the current register with the virtual
478 /// subregister Reg:SubReg. Take any existing SubReg index into account,
479 /// using TargetRegisterInfo to compose the subreg indices if necessary.
480 /// Reg must be a virtual register, SubIdx can be 0.
481 ///
482 void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
483
484 /// substPhysReg - Substitute the current register with the physical register
485 /// Reg, taking any existing SubReg into account. For instance,
486 /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
487 ///
488 void substPhysReg(MCRegister Reg, const TargetRegisterInfo&);
489
490 void setIsUse(bool Val = true) { setIsDef(!Val); }
491
492 /// Change a def to a use, or a use to a def.
493 void setIsDef(bool Val = true);
494
495 void setImplicit(bool Val = true) {
496 assert(isReg() && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 496, __extension__ __PRETTY_FUNCTION__))
;
497 IsImp = Val;
498 }
499
500 void setIsKill(bool Val = true) {
501 assert(isReg() && !IsDef && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && !IsDef &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"isReg() && !IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 501, __extension__ __PRETTY_FUNCTION__))
;
502 assert((!Val || !isDebug()) && "Marking a debug operation as kill")(static_cast <bool> ((!Val || !isDebug()) && "Marking a debug operation as kill"
) ? void (0) : __assert_fail ("(!Val || !isDebug()) && \"Marking a debug operation as kill\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 502, __extension__ __PRETTY_FUNCTION__))
;
503 IsDeadOrKill = Val;
504 }
505
506 void setIsDead(bool Val = true) {
507 assert(isReg() && IsDef && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && IsDef &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"isReg() && IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 507, __extension__ __PRETTY_FUNCTION__))
;
508 IsDeadOrKill = Val;
509 }
510
511 void setIsUndef(bool Val = true) {
512 assert(isReg() && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 512, __extension__ __PRETTY_FUNCTION__))
;
513 IsUndef = Val;
514 }
515
516 void setIsRenamable(bool Val = true);
517
518 void setIsInternalRead(bool Val = true) {
519 assert(isReg() && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 519, __extension__ __PRETTY_FUNCTION__))
;
520 IsInternalRead = Val;
521 }
522
523 void setIsEarlyClobber(bool Val = true) {
524 assert(isReg() && IsDef && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && IsDef &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"isReg() && IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 524, __extension__ __PRETTY_FUNCTION__))
;
525 IsEarlyClobber = Val;
526 }
527
528 void setIsDebug(bool Val = true) {
529 assert(isReg() && !IsDef && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && !IsDef &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"isReg() && !IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 529, __extension__ __PRETTY_FUNCTION__))
;
530 IsDebug = Val;
531 }
532
533 //===--------------------------------------------------------------------===//
534 // Accessors for various operand types.
535 //===--------------------------------------------------------------------===//
536
537 int64_t getImm() const {
538 assert(isImm() && "Wrong MachineOperand accessor")(static_cast <bool> (isImm() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isImm() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 538, __extension__ __PRETTY_FUNCTION__))
;
539 return Contents.ImmVal;
540 }
541
542 const ConstantInt *getCImm() const {
543 assert(isCImm() && "Wrong MachineOperand accessor")(static_cast <bool> (isCImm() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isCImm() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 543, __extension__ __PRETTY_FUNCTION__))
;
544 return Contents.CI;
545 }
546
547 const ConstantFP *getFPImm() const {
548 assert(isFPImm() && "Wrong MachineOperand accessor")(static_cast <bool> (isFPImm() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isFPImm() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 548, __extension__ __PRETTY_FUNCTION__))
;
549 return Contents.CFP;
550 }
551
552 MachineBasicBlock *getMBB() const {
553 assert(isMBB() && "Wrong MachineOperand accessor")(static_cast <bool> (isMBB() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isMBB() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 553, __extension__ __PRETTY_FUNCTION__))
;
554 return Contents.MBB;
555 }
556
557 int getIndex() const {
558 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&(static_cast <bool> ((isFI() || isCPI() || isTargetIndex
() || isJTI()) && "Wrong MachineOperand accessor") ? void
(0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 559, __extension__ __PRETTY_FUNCTION__))
559 "Wrong MachineOperand accessor")(static_cast <bool> ((isFI() || isCPI() || isTargetIndex
() || isJTI()) && "Wrong MachineOperand accessor") ? void
(0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 559, __extension__ __PRETTY_FUNCTION__))
;
560 return Contents.OffsetedInfo.Val.Index;
561 }
562
563 const GlobalValue *getGlobal() const {
564 assert(isGlobal() && "Wrong MachineOperand accessor")(static_cast <bool> (isGlobal() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isGlobal() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 564, __extension__ __PRETTY_FUNCTION__))
;
565 return Contents.OffsetedInfo.Val.GV;
566 }
567
568 const BlockAddress *getBlockAddress() const {
569 assert(isBlockAddress() && "Wrong MachineOperand accessor")(static_cast <bool> (isBlockAddress() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isBlockAddress() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 569, __extension__ __PRETTY_FUNCTION__))
;
570 return Contents.OffsetedInfo.Val.BA;
571 }
572
573 MCSymbol *getMCSymbol() const {
574 assert(isMCSymbol() && "Wrong MachineOperand accessor")(static_cast <bool> (isMCSymbol() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isMCSymbol() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 574, __extension__ __PRETTY_FUNCTION__))
;
575 return Contents.Sym;
576 }
577
578 unsigned getCFIIndex() const {
579 assert(isCFIIndex() && "Wrong MachineOperand accessor")(static_cast <bool> (isCFIIndex() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isCFIIndex() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 579, __extension__ __PRETTY_FUNCTION__))
;
580 return Contents.CFIIndex;
581 }
582
583 Intrinsic::ID getIntrinsicID() const {
584 assert(isIntrinsicID() && "Wrong MachineOperand accessor")(static_cast <bool> (isIntrinsicID() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isIntrinsicID() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 584, __extension__ __PRETTY_FUNCTION__))
;
585 return Contents.IntrinsicID;
586 }
587
588 unsigned getPredicate() const {
589 assert(isPredicate() && "Wrong MachineOperand accessor")(static_cast <bool> (isPredicate() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isPredicate() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 589, __extension__ __PRETTY_FUNCTION__))
;
590 return Contents.Pred;
591 }
592
593 ArrayRef<int> getShuffleMask() const {
594 assert(isShuffleMask() && "Wrong MachineOperand accessor")(static_cast <bool> (isShuffleMask() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isShuffleMask() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 594, __extension__ __PRETTY_FUNCTION__))
;
595 return Contents.ShuffleMask;
596 }
597
598 /// Return the offset from the symbol in this operand. This always returns 0
599 /// for ExternalSymbol operands.
600 int64_t getOffset() const {
601 assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand accessor") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 603, __extension__ __PRETTY_FUNCTION__))
602 isTargetIndex() || isBlockAddress()) &&(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand accessor") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 603, __extension__ __PRETTY_FUNCTION__))
603 "Wrong MachineOperand accessor")(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand accessor") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 603, __extension__ __PRETTY_FUNCTION__))
;
604 return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
605 SmallContents.OffsetLo;
606 }
607
608 const char *getSymbolName() const {
609 assert(isSymbol() && "Wrong MachineOperand accessor")(static_cast <bool> (isSymbol() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isSymbol() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 609, __extension__ __PRETTY_FUNCTION__))
;
610 return Contents.OffsetedInfo.Val.SymbolName;
611 }
612
613 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
614 /// It is sometimes necessary to detach the register mask pointer from its
615 /// machine operand. This static method can be used for such detached bit
616 /// mask pointers.
617 static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) {
618 // See TargetRegisterInfo.h.
619 assert(PhysReg < (1u << 30) && "Not a physical register")(static_cast <bool> (PhysReg < (1u << 30) &&
"Not a physical register") ? void (0) : __assert_fail ("PhysReg < (1u << 30) && \"Not a physical register\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 619, __extension__ __PRETTY_FUNCTION__))
;
620 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
621 }
622
623 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
624 bool clobbersPhysReg(MCRegister PhysReg) const {
625 return clobbersPhysReg(getRegMask(), PhysReg);
626 }
627
628 /// getRegMask - Returns a bit mask of registers preserved by this RegMask
629 /// operand.
630 const uint32_t *getRegMask() const {
631 assert(isRegMask() && "Wrong MachineOperand accessor")(static_cast <bool> (isRegMask() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isRegMask() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 631, __extension__ __PRETTY_FUNCTION__))
;
632 return Contents.RegMask;
633 }
634
635 /// Returns number of elements needed for a regmask array.
636 static unsigned getRegMaskSize(unsigned NumRegs) {
637 return (NumRegs + 31) / 32;
638 }
639
640 /// getRegLiveOut - Returns a bit mask of live-out registers.
641 const uint32_t *getRegLiveOut() const {
642 assert(isRegLiveOut() && "Wrong MachineOperand accessor")(static_cast <bool> (isRegLiveOut() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isRegLiveOut() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 642, __extension__ __PRETTY_FUNCTION__))
;
643 return Contents.RegMask;
644 }
645
646 const MDNode *getMetadata() const {
647 assert(isMetadata() && "Wrong MachineOperand accessor")(static_cast <bool> (isMetadata() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isMetadata() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 647, __extension__ __PRETTY_FUNCTION__))
;
648 return Contents.MD;
649 }
650
651 //===--------------------------------------------------------------------===//
652 // Mutators for various operand types.
653 //===--------------------------------------------------------------------===//
654
655 void setImm(int64_t immVal) {
656 assert(isImm() && "Wrong MachineOperand mutator")(static_cast <bool> (isImm() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isImm() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 656, __extension__ __PRETTY_FUNCTION__))
;
657 Contents.ImmVal = immVal;
658 }
659
660 void setCImm(const ConstantInt *CI) {
661 assert(isCImm() && "Wrong MachineOperand mutator")(static_cast <bool> (isCImm() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isCImm() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 661, __extension__ __PRETTY_FUNCTION__))
;
662 Contents.CI = CI;
663 }
664
665 void setFPImm(const ConstantFP *CFP) {
666 assert(isFPImm() && "Wrong MachineOperand mutator")(static_cast <bool> (isFPImm() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isFPImm() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 666, __extension__ __PRETTY_FUNCTION__))
;
667 Contents.CFP = CFP;
668 }
669
670 void setOffset(int64_t Offset) {
671 assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 673, __extension__ __PRETTY_FUNCTION__))
672 isTargetIndex() || isBlockAddress()) &&(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 673, __extension__ __PRETTY_FUNCTION__))
673 "Wrong MachineOperand mutator")(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 673, __extension__ __PRETTY_FUNCTION__))
;
674 SmallContents.OffsetLo = unsigned(Offset);
675 Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
676 }
677
678 void setIndex(int Idx) {
679 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&(static_cast <bool> ((isFI() || isCPI() || isTargetIndex
() || isJTI()) && "Wrong MachineOperand mutator") ? void
(0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 680, __extension__ __PRETTY_FUNCTION__))
680 "Wrong MachineOperand mutator")(static_cast <bool> ((isFI() || isCPI() || isTargetIndex
() || isJTI()) && "Wrong MachineOperand mutator") ? void
(0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 680, __extension__ __PRETTY_FUNCTION__))
;
681 Contents.OffsetedInfo.Val.Index = Idx;
682 }
683
684 void setMetadata(const MDNode *MD) {
685 assert(isMetadata() && "Wrong MachineOperand mutator")(static_cast <bool> (isMetadata() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isMetadata() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 685, __extension__ __PRETTY_FUNCTION__))
;
686 Contents.MD = MD;
687 }
688
689 void setMBB(MachineBasicBlock *MBB) {
690 assert(isMBB() && "Wrong MachineOperand mutator")(static_cast <bool> (isMBB() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isMBB() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 690, __extension__ __PRETTY_FUNCTION__))
;
691 Contents.MBB = MBB;
692 }
693
694 /// Sets value of register mask operand referencing Mask. The
695 /// operand does not take ownership of the memory referenced by Mask, it must
696 /// remain valid for the lifetime of the operand. See CreateRegMask().
697 /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
698 void setRegMask(const uint32_t *RegMaskPtr) {
699 assert(isRegMask() && "Wrong MachineOperand mutator")(static_cast <bool> (isRegMask() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isRegMask() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 699, __extension__ __PRETTY_FUNCTION__))
;
700 Contents.RegMask = RegMaskPtr;
701 }
702
703 void setIntrinsicID(Intrinsic::ID IID) {
704 assert(isIntrinsicID() && "Wrong MachineOperand mutator")(static_cast <bool> (isIntrinsicID() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isIntrinsicID() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 704, __extension__ __PRETTY_FUNCTION__))
;
705 Contents.IntrinsicID = IID;
706 }
707
708 void setPredicate(unsigned Predicate) {
709 assert(isPredicate() && "Wrong MachineOperand mutator")(static_cast <bool> (isPredicate() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isPredicate() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 709, __extension__ __PRETTY_FUNCTION__))
;
710 Contents.Pred = Predicate;
711 }
712
713 //===--------------------------------------------------------------------===//
714 // Other methods.
715 //===--------------------------------------------------------------------===//
716
717 /// Returns true if this operand is identical to the specified operand except
718 /// for liveness related flags (isKill, isUndef and isDead). Note that this
719 /// should stay in sync with the hash_value overload below.
720 bool isIdenticalTo(const MachineOperand &Other) const;
721
722 /// MachineOperand hash_value overload.
723 ///
724 /// Note that this includes the same information in the hash that
725 /// isIdenticalTo uses for comparison. It is thus suited for use in hash
726 /// tables which use that function for equality comparisons only. This must
727 /// stay exactly in sync with isIdenticalTo above.
728 friend hash_code hash_value(const MachineOperand &MO);
729
730 /// ChangeToImmediate - Replace this operand with a new immediate operand of
731 /// the specified value. If an operand is known to be an immediate already,
732 /// the setImm method should be used.
733 void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags = 0);
734
735 /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
736 /// of the specified value. If an operand is known to be an FP immediate
737 /// already, the setFPImm method should be used.
738 void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags = 0);
739
740 /// ChangeToES - Replace this operand with a new external symbol operand.
741 void ChangeToES(const char *SymName, unsigned TargetFlags = 0);
742
743 /// ChangeToGA - Replace this operand with a new global address operand.
744 void ChangeToGA(const GlobalValue *GV, int64_t Offset,
745 unsigned TargetFlags = 0);
746
747 /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
748 void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags = 0);
749
750 /// Replace this operand with a frame index.
751 void ChangeToFrameIndex(int Idx, unsigned TargetFlags = 0);
752
753 /// Replace this operand with a target index.
754 void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
755 unsigned TargetFlags = 0);
756
757 /// ChangeToRegister - Replace this operand with a new register operand of
758 /// the specified value. If an operand is known to be an register already,
759 /// the setReg method should be used.
760 void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
761 bool isKill = false, bool isDead = false,
762 bool isUndef = false, bool isDebug = false);
763
764 /// getTargetIndexName - If this MachineOperand is a TargetIndex that has a
765 /// name, attempt to get the name. Returns nullptr if the TargetIndex does not
766 /// have a name. Asserts if MO is not a TargetIndex.
767 const char *getTargetIndexName() const;
768
769 //===--------------------------------------------------------------------===//
770 // Construction methods.
771 //===--------------------------------------------------------------------===//
772
773 static MachineOperand CreateImm(int64_t Val) {
774 MachineOperand Op(MachineOperand::MO_Immediate);
775 Op.setImm(Val);
776 return Op;
777 }
778
779 static MachineOperand CreateCImm(const ConstantInt *CI) {
780 MachineOperand Op(MachineOperand::MO_CImmediate);
781 Op.Contents.CI = CI;
782 return Op;
783 }
784
785 static MachineOperand CreateFPImm(const ConstantFP *CFP) {
786 MachineOperand Op(MachineOperand::MO_FPImmediate);
787 Op.Contents.CFP = CFP;
788 return Op;
789 }
790
791 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
792 bool isKill = false, bool isDead = false,
793 bool isUndef = false,
794 bool isEarlyClobber = false,
795 unsigned SubReg = 0, bool isDebug = false,
796 bool isInternalRead = false,
797 bool isRenamable = false) {
798 assert(!(isDead && !isDef) && "Dead flag on non-def")(static_cast <bool> (!(isDead && !isDef) &&
"Dead flag on non-def") ? void (0) : __assert_fail ("!(isDead && !isDef) && \"Dead flag on non-def\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 798, __extension__ __PRETTY_FUNCTION__))
;
799 assert(!(isKill && isDef) && "Kill flag on def")(static_cast <bool> (!(isKill && isDef) &&
"Kill flag on def") ? void (0) : __assert_fail ("!(isKill && isDef) && \"Kill flag on def\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 799, __extension__ __PRETTY_FUNCTION__))
;
800 MachineOperand Op(MachineOperand::MO_Register);
801 Op.IsDef = isDef;
802 Op.IsImp = isImp;
803 Op.IsDeadOrKill = isKill | isDead;
804 Op.IsRenamable = isRenamable;
805 Op.IsUndef = isUndef;
806 Op.IsInternalRead = isInternalRead;
807 Op.IsEarlyClobber = isEarlyClobber;
808 Op.TiedTo = 0;
809 Op.IsDebug = isDebug;
810 Op.SmallContents.RegNo = Reg;
811 Op.Contents.Reg.Prev = nullptr;
812 Op.Contents.Reg.Next = nullptr;
813 Op.setSubReg(SubReg);
814 return Op;
815 }
816 static MachineOperand CreateMBB(MachineBasicBlock *MBB,
817 unsigned TargetFlags = 0) {
818 MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
819 Op.setMBB(MBB);
820 Op.setTargetFlags(TargetFlags);
821 return Op;
822 }
823 static MachineOperand CreateFI(int Idx) {
824 MachineOperand Op(MachineOperand::MO_FrameIndex);
825 Op.setIndex(Idx);
826 return Op;
827 }
828 static MachineOperand CreateCPI(unsigned Idx, int Offset,
829 unsigned TargetFlags = 0) {
830 MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
831 Op.setIndex(Idx);
832 Op.setOffset(Offset);
833 Op.setTargetFlags(TargetFlags);
834 return Op;
835 }
836 static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
837 unsigned TargetFlags = 0) {
838 MachineOperand Op(MachineOperand::MO_TargetIndex);
839 Op.setIndex(Idx);
840 Op.setOffset(Offset);
841 Op.setTargetFlags(TargetFlags);
842 return Op;
843 }
844 static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags = 0) {
845 MachineOperand Op(MachineOperand::MO_JumpTableIndex);
846 Op.setIndex(Idx);
847 Op.setTargetFlags(TargetFlags);
848 return Op;
849 }
850 static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
851 unsigned TargetFlags = 0) {
852 MachineOperand Op(MachineOperand::MO_GlobalAddress);
853 Op.Contents.OffsetedInfo.Val.GV = GV;
854 Op.setOffset(Offset);
855 Op.setTargetFlags(TargetFlags);
856 return Op;
857 }
858 static MachineOperand CreateES(const char *SymName,
859 unsigned TargetFlags = 0) {
860 MachineOperand Op(MachineOperand::MO_ExternalSymbol);
861 Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
862 Op.setOffset(0); // Offset is always 0.
863 Op.setTargetFlags(TargetFlags);
864 return Op;
865 }
866 static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
867 unsigned TargetFlags = 0) {
868 MachineOperand Op(MachineOperand::MO_BlockAddress);
869 Op.Contents.OffsetedInfo.Val.BA = BA;
870 Op.setOffset(Offset);
871 Op.setTargetFlags(TargetFlags);
872 return Op;
873 }
874 /// CreateRegMask - Creates a register mask operand referencing Mask. The
875 /// operand does not take ownership of the memory referenced by Mask, it
876 /// must remain valid for the lifetime of the operand.
877 ///
878 /// A RegMask operand represents a set of non-clobbered physical registers
879 /// on an instruction that clobbers many registers, typically a call. The
880 /// bit mask has a bit set for each physreg that is preserved by this
881 /// instruction, as described in the documentation for
882 /// TargetRegisterInfo::getCallPreservedMask().
883 ///
884 /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
885 ///
886 static MachineOperand CreateRegMask(const uint32_t *Mask) {
887 assert(Mask && "Missing register mask")(static_cast <bool> (Mask && "Missing register mask"
) ? void (0) : __assert_fail ("Mask && \"Missing register mask\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 887, __extension__ __PRETTY_FUNCTION__))
;
888 MachineOperand Op(MachineOperand::MO_RegisterMask);
889 Op.Contents.RegMask = Mask;
890 return Op;
891 }
892 static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
893 assert(Mask && "Missing live-out register mask")(static_cast <bool> (Mask && "Missing live-out register mask"
) ? void (0) : __assert_fail ("Mask && \"Missing live-out register mask\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 893, __extension__ __PRETTY_FUNCTION__))
;
894 MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
895 Op.Contents.RegMask = Mask;
896 return Op;
897 }
898 static MachineOperand CreateMetadata(const MDNode *Meta) {
899 MachineOperand Op(MachineOperand::MO_Metadata);
900 Op.Contents.MD = Meta;
901 return Op;
902 }
903
904 static MachineOperand CreateMCSymbol(MCSymbol *Sym,
905 unsigned TargetFlags = 0) {
906 MachineOperand Op(MachineOperand::MO_MCSymbol);
907 Op.Contents.Sym = Sym;
908 Op.setOffset(0);
909 Op.setTargetFlags(TargetFlags);
910 return Op;
911 }
912
913 static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
914 MachineOperand Op(MachineOperand::MO_CFIIndex);
915 Op.Contents.CFIIndex = CFIIndex;
916 return Op;
917 }
918
919 static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
920 MachineOperand Op(MachineOperand::MO_IntrinsicID);
921 Op.Contents.IntrinsicID = ID;
922 return Op;
923 }
924
925 static MachineOperand CreatePredicate(unsigned Pred) {
926 MachineOperand Op(MachineOperand::MO_Predicate);
927 Op.Contents.Pred = Pred;
928 return Op;
929 }
930
931 static MachineOperand CreateShuffleMask(ArrayRef<int> Mask) {
932 MachineOperand Op(MachineOperand::MO_ShuffleMask);
933 Op.Contents.ShuffleMask = Mask;
934 return Op;
935 }
936
937 friend class MachineInstr;
938 friend class MachineRegisterInfo;
939
940private:
941 // If this operand is currently a register operand, and if this is in a
942 // function, deregister the operand from the register's use/def list.
943 void removeRegFromUses();
944
945 /// Artificial kinds for DenseMap usage.
946 enum : unsigned char {
947 MO_Empty = MO_Last + 1,
948 MO_Tombstone,
949 };
950
951 friend struct DenseMapInfo<MachineOperand>;
952
953 //===--------------------------------------------------------------------===//
954 // Methods for handling register use/def lists.
955 //===--------------------------------------------------------------------===//
956
957 /// isOnRegUseList - Return true if this operand is on a register use/def
958 /// list or false if not. This can only be called for register operands
959 /// that are part of a machine instruction.
960 bool isOnRegUseList() const {
961 assert(isReg() && "Can only add reg operand to use lists")(static_cast <bool> (isReg() && "Can only add reg operand to use lists"
) ? void (0) : __assert_fail ("isReg() && \"Can only add reg operand to use lists\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include/llvm/CodeGen/MachineOperand.h"
, 961, __extension__ __PRETTY_FUNCTION__))
;
962 return Contents.Reg.Prev != nullptr;
963 }
964};
965
966template <> struct DenseMapInfo<MachineOperand> {
967 static MachineOperand getEmptyKey() {
968 return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
969 MachineOperand::MO_Empty));
970 }
971 static MachineOperand getTombstoneKey() {
972 return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
973 MachineOperand::MO_Tombstone));
974 }
975 static unsigned getHashValue(const MachineOperand &MO) {
976 return hash_value(MO);
977 }
978 static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
979 if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
980 MachineOperand::MO_Empty) ||
981 LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
982 MachineOperand::MO_Tombstone))
983 return LHS.getType() == RHS.getType();
984 return LHS.isIdenticalTo(RHS);
985 }
986};
987
988inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
989 MO.print(OS);
990 return OS;
991}
992
993// See friend declaration above. This additional declaration is required in
994// order to compile LLVM with IBM xlC compiler.
995hash_code hash_value(const MachineOperand &MO);
996} // namespace llvm
997
998#endif