Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1150, column 10
Called C++ object pointer is null

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name HexagonISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/include -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/Hexagon -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-01-13-084841-49055-1 -x c++ /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

1//===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that Hexagon uses to lower LLVM code
10// into a selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonISelLowering.h"
15#include "Hexagon.h"
16#include "HexagonMachineFunctionInfo.h"
17#include "HexagonRegisterInfo.h"
18#include "HexagonSubtarget.h"
19#include "HexagonTargetMachine.h"
20#include "HexagonTargetObjectFile.h"
21#include "llvm/ADT/APInt.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/ADT/StringSwitch.h"
25#include "llvm/CodeGen/CallingConvLower.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/RuntimeLibcalls.h"
31#include "llvm/CodeGen/SelectionDAG.h"
32#include "llvm/CodeGen/TargetCallingConv.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/BasicBlock.h"
35#include "llvm/IR/CallingConv.h"
36#include "llvm/IR/DataLayout.h"
37#include "llvm/IR/DerivedTypes.h"
38#include "llvm/IR/Function.h"
39#include "llvm/IR/GlobalValue.h"
40#include "llvm/IR/InlineAsm.h"
41#include "llvm/IR/Instructions.h"
42#include "llvm/IR/IntrinsicInst.h"
43#include "llvm/IR/Intrinsics.h"
44#include "llvm/IR/IntrinsicsHexagon.h"
45#include "llvm/IR/Module.h"
46#include "llvm/IR/Type.h"
47#include "llvm/IR/Value.h"
48#include "llvm/MC/MCRegisterInfo.h"
49#include "llvm/Support/Casting.h"
50#include "llvm/Support/CodeGen.h"
51#include "llvm/Support/CommandLine.h"
52#include "llvm/Support/Debug.h"
53#include "llvm/Support/ErrorHandling.h"
54#include "llvm/Support/MathExtras.h"
55#include "llvm/Support/raw_ostream.h"
56#include "llvm/Target/TargetMachine.h"
57#include <algorithm>
58#include <cassert>
59#include <cstddef>
60#include <cstdint>
61#include <limits>
62#include <utility>
63
64using namespace llvm;
65
66#define DEBUG_TYPE"hexagon-lowering" "hexagon-lowering"
67
68static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
69 cl::init(true), cl::Hidden,
70 cl::desc("Control jump table emission on Hexagon target"));
71
72static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
73 cl::Hidden, cl::ZeroOrMore, cl::init(false),
74 cl::desc("Enable Hexagon SDNode scheduling"));
75
76static cl::opt<bool> EnableFastMath("ffast-math",
77 cl::Hidden, cl::ZeroOrMore, cl::init(false),
78 cl::desc("Enable Fast Math processing"));
79
80static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
81 cl::Hidden, cl::ZeroOrMore, cl::init(5),
82 cl::desc("Set minimum jump tables"));
83
84static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
85 cl::Hidden, cl::ZeroOrMore, cl::init(6),
86 cl::desc("Max #stores to inline memcpy"));
87
88static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
89 cl::Hidden, cl::ZeroOrMore, cl::init(4),
90 cl::desc("Max #stores to inline memcpy"));
91
92static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
93 cl::Hidden, cl::ZeroOrMore, cl::init(6),
94 cl::desc("Max #stores to inline memmove"));
95
96static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
97 cl::Hidden, cl::ZeroOrMore, cl::init(4),
98 cl::desc("Max #stores to inline memmove"));
99
100static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
101 cl::Hidden, cl::ZeroOrMore, cl::init(8),
102 cl::desc("Max #stores to inline memset"));
103
104static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
105 cl::Hidden, cl::ZeroOrMore, cl::init(4),
106 cl::desc("Max #stores to inline memset"));
107
108static cl::opt<bool> AlignLoads("hexagon-align-loads",
109 cl::Hidden, cl::init(false),
110 cl::desc("Rewrite unaligned loads as a pair of aligned loads"));
111
112
113namespace {
114
115 class HexagonCCState : public CCState {
116 unsigned NumNamedVarArgParams = 0;
117
118 public:
119 HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
120 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
121 unsigned NumNamedArgs)
122 : CCState(CC, IsVarArg, MF, locs, C),
123 NumNamedVarArgParams(NumNamedArgs) {}
124 unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
125 };
126
127} // end anonymous namespace
128
129
130// Implement calling convention for Hexagon.
131
132static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
133 CCValAssign::LocInfo &LocInfo,
134 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
135 static const MCPhysReg ArgRegs[] = {
136 Hexagon::R0, Hexagon::R1, Hexagon::R2,
137 Hexagon::R3, Hexagon::R4, Hexagon::R5
138 };
139 const unsigned NumArgRegs = array_lengthof(ArgRegs);
140 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
141
142 // RegNum is an index into ArgRegs: skip a register if RegNum is odd.
143 if (RegNum != NumArgRegs && RegNum % 2 == 1)
144 State.AllocateReg(ArgRegs[RegNum]);
145
146 // Always return false here, as this function only makes sure that the first
147 // unallocated register has an even register number and does not actually
148 // allocate a register for the current argument.
149 return false;
150}
151
152#include "HexagonGenCallingConv.inc"
153
154
155SDValue
156HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
157 const {
158 return SDValue();
159}
160
161/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
162/// by "Src" to address "Dst" of size "Size". Alignment information is
163/// specified by the specific parameter attribute. The copy will be passed as
164/// a byval function parameter. Sometimes what we are copying is the end of a
165/// larger object, the part that does not fit in registers.
166static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
167 SDValue Chain, ISD::ArgFlagsTy Flags,
168 SelectionDAG &DAG, const SDLoc &dl) {
169 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
170 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
171 /*isVolatile=*/false, /*AlwaysInline=*/false,
172 /*isTailCall=*/false,
173 MachinePointerInfo(), MachinePointerInfo());
174}
175
176bool
177HexagonTargetLowering::CanLowerReturn(
178 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
179 const SmallVectorImpl<ISD::OutputArg> &Outs,
180 LLVMContext &Context) const {
181 SmallVector<CCValAssign, 16> RVLocs;
182 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
183
184 if (MF.getSubtarget<HexagonSubtarget>().useHVXOps())
185 return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
186 return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
187}
188
189// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
190// passed by value, the function prototype is modified to return void and
191// the value is stored in memory pointed by a pointer passed by caller.
192SDValue
193HexagonTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
194 bool IsVarArg,
195 const SmallVectorImpl<ISD::OutputArg> &Outs,
196 const SmallVectorImpl<SDValue> &OutVals,
197 const SDLoc &dl, SelectionDAG &DAG) const {
198 // CCValAssign - represent the assignment of the return value to locations.
199 SmallVector<CCValAssign, 16> RVLocs;
200
201 // CCState - Info about the registers and stack slot.
202 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
203 *DAG.getContext());
204
205 // Analyze return values of ISD::RET
206 if (Subtarget.useHVXOps())
207 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
208 else
209 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
210
211 SDValue Flag;
212 SmallVector<SDValue, 4> RetOps(1, Chain);
213
214 // Copy the result values into the output registers.
215 for (unsigned i = 0; i != RVLocs.size(); ++i) {
216 CCValAssign &VA = RVLocs[i];
217
218 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
219
220 // Guarantee that all emitted copies are stuck together with flags.
221 Flag = Chain.getValue(1);
222 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
223 }
224
225 RetOps[0] = Chain; // Update chain.
226
227 // Add the flag if we have it.
228 if (Flag.getNode())
229 RetOps.push_back(Flag);
230
231 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
232}
233
234bool HexagonTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
235 // If either no tail call or told not to tail call at all, don't.
236 return CI->isTailCall();
237}
238
239Register HexagonTargetLowering::getRegisterByName(
240 const char* RegName, LLT VT, const MachineFunction &) const {
241 // Just support r19, the linux kernel uses it.
242 Register Reg = StringSwitch<Register>(RegName)
243 .Case("r0", Hexagon::R0)
244 .Case("r1", Hexagon::R1)
245 .Case("r2", Hexagon::R2)
246 .Case("r3", Hexagon::R3)
247 .Case("r4", Hexagon::R4)
248 .Case("r5", Hexagon::R5)
249 .Case("r6", Hexagon::R6)
250 .Case("r7", Hexagon::R7)
251 .Case("r8", Hexagon::R8)
252 .Case("r9", Hexagon::R9)
253 .Case("r10", Hexagon::R10)
254 .Case("r11", Hexagon::R11)
255 .Case("r12", Hexagon::R12)
256 .Case("r13", Hexagon::R13)
257 .Case("r14", Hexagon::R14)
258 .Case("r15", Hexagon::R15)
259 .Case("r16", Hexagon::R16)
260 .Case("r17", Hexagon::R17)
261 .Case("r18", Hexagon::R18)
262 .Case("r19", Hexagon::R19)
263 .Case("r20", Hexagon::R20)
264 .Case("r21", Hexagon::R21)
265 .Case("r22", Hexagon::R22)
266 .Case("r23", Hexagon::R23)
267 .Case("r24", Hexagon::R24)
268 .Case("r25", Hexagon::R25)
269 .Case("r26", Hexagon::R26)
270 .Case("r27", Hexagon::R27)
271 .Case("r28", Hexagon::R28)
272 .Case("r29", Hexagon::R29)
273 .Case("r30", Hexagon::R30)
274 .Case("r31", Hexagon::R31)
275 .Case("r1:0", Hexagon::D0)
276 .Case("r3:2", Hexagon::D1)
277 .Case("r5:4", Hexagon::D2)
278 .Case("r7:6", Hexagon::D3)
279 .Case("r9:8", Hexagon::D4)
280 .Case("r11:10", Hexagon::D5)
281 .Case("r13:12", Hexagon::D6)
282 .Case("r15:14", Hexagon::D7)
283 .Case("r17:16", Hexagon::D8)
284 .Case("r19:18", Hexagon::D9)
285 .Case("r21:20", Hexagon::D10)
286 .Case("r23:22", Hexagon::D11)
287 .Case("r25:24", Hexagon::D12)
288 .Case("r27:26", Hexagon::D13)
289 .Case("r29:28", Hexagon::D14)
290 .Case("r31:30", Hexagon::D15)
291 .Case("sp", Hexagon::R29)
292 .Case("fp", Hexagon::R30)
293 .Case("lr", Hexagon::R31)
294 .Case("p0", Hexagon::P0)
295 .Case("p1", Hexagon::P1)
296 .Case("p2", Hexagon::P2)
297 .Case("p3", Hexagon::P3)
298 .Case("sa0", Hexagon::SA0)
299 .Case("lc0", Hexagon::LC0)
300 .Case("sa1", Hexagon::SA1)
301 .Case("lc1", Hexagon::LC1)
302 .Case("m0", Hexagon::M0)
303 .Case("m1", Hexagon::M1)
304 .Case("usr", Hexagon::USR)
305 .Case("ugp", Hexagon::UGP)
306 .Default(Register());
307 if (Reg)
308 return Reg;
309
310 report_fatal_error("Invalid register name global variable");
311}
312
313/// LowerCallResult - Lower the result values of an ISD::CALL into the
314/// appropriate copies out of appropriate physical registers. This assumes that
315/// Chain/Glue are the input chain/glue to use, and that TheCall is the call
316/// being lowered. Returns a SDNode with the same number of values as the
317/// ISD::CALL.
318SDValue HexagonTargetLowering::LowerCallResult(
319 SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg,
320 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
321 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
322 const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
323 // Assign locations to each value returned by this call.
324 SmallVector<CCValAssign, 16> RVLocs;
325
326 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
327 *DAG.getContext());
328
329 if (Subtarget.useHVXOps())
330 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
331 else
332 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
333
334 // Copy all of the result registers out of their specified physreg.
335 for (unsigned i = 0; i != RVLocs.size(); ++i) {
336 SDValue RetVal;
337 if (RVLocs[i].getValVT() == MVT::i1) {
338 // Return values of type MVT::i1 require special handling. The reason
339 // is that MVT::i1 is associated with the PredRegs register class, but
340 // values of that type are still returned in R0. Generate an explicit
341 // copy into a predicate register from R0, and treat the value of the
342 // predicate register as the call result.
343 auto &MRI = DAG.getMachineFunction().getRegInfo();
344 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
345 MVT::i32, Glue);
346 // FR0 = (Value, Chain, Glue)
347 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
348 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
349 FR0.getValue(0), FR0.getValue(2));
350 // TPR = (Chain, Glue)
351 // Don't glue this CopyFromReg, because it copies from a virtual
352 // register. If it is glued to the call, InstrEmitter will add it
353 // as an implicit def to the call (EmitMachineNode).
354 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
355 Glue = TPR.getValue(1);
356 Chain = TPR.getValue(0);
357 } else {
358 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
359 RVLocs[i].getValVT(), Glue);
360 Glue = RetVal.getValue(2);
361 Chain = RetVal.getValue(1);
362 }
363 InVals.push_back(RetVal.getValue(0));
364 }
365
366 return Chain;
367}
368
369/// LowerCall - Functions arguments are copied from virtual regs to
370/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
371SDValue
372HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
373 SmallVectorImpl<SDValue> &InVals) const {
374 SelectionDAG &DAG = CLI.DAG;
375 SDLoc &dl = CLI.DL;
376 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
377 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
378 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
379 SDValue Chain = CLI.Chain;
380 SDValue Callee = CLI.Callee;
381 CallingConv::ID CallConv = CLI.CallConv;
382 bool IsVarArg = CLI.IsVarArg;
383 bool DoesNotReturn = CLI.DoesNotReturn;
384
385 bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
386 MachineFunction &MF = DAG.getMachineFunction();
387 MachineFrameInfo &MFI = MF.getFrameInfo();
388 auto PtrVT = getPointerTy(MF.getDataLayout());
389
390 unsigned NumParams = CLI.CS.getInstruction()
391 ? CLI.CS.getFunctionType()->getNumParams()
392 : 0;
393 if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee))
394 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);
395
396 // Analyze operands of the call, assigning locations to each operand.
397 SmallVector<CCValAssign, 16> ArgLocs;
398 HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
399 NumParams);
400
401 if (Subtarget.useHVXOps())
402 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
403 else
404 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
405
406 if (CLI.IsTailCall) {
407 bool StructAttrFlag = MF.getFunction().hasStructRetAttr();
408 CLI.IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
409 IsVarArg, IsStructRet, StructAttrFlag, Outs,
410 OutVals, Ins, DAG);
411 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
412 CCValAssign &VA = ArgLocs[i];
413 if (VA.isMemLoc()) {
414 CLI.IsTailCall = false;
415 break;
416 }
417 }
418 LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
419 : "Argument must be passed on stack. "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
420 "Not eligible for Tail Call\n"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
;
421 }
422 // Get a count of how many bytes are to be pushed on the stack.
423 unsigned NumBytes = CCInfo.getNextStackOffset();
424 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
425 SmallVector<SDValue, 8> MemOpChains;
426
427 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
428 SDValue StackPtr =
429 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
430
431 bool NeedsArgAlign = false;
432 unsigned LargestAlignSeen = 0;
433 // Walk the register/memloc assignments, inserting copies/loads.
434 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
435 CCValAssign &VA = ArgLocs[i];
436 SDValue Arg = OutVals[i];
437 ISD::ArgFlagsTy Flags = Outs[i].Flags;
438 // Record if we need > 8 byte alignment on an argument.
439 bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
440 NeedsArgAlign |= ArgAlign;
441
442 // Promote the value if needed.
443 switch (VA.getLocInfo()) {
444 default:
445 // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
446 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 446)
;
447 case CCValAssign::Full:
448 break;
449 case CCValAssign::BCvt:
450 Arg = DAG.getBitcast(VA.getLocVT(), Arg);
451 break;
452 case CCValAssign::SExt:
453 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
454 break;
455 case CCValAssign::ZExt:
456 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
457 break;
458 case CCValAssign::AExt:
459 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
460 break;
461 }
462
463 if (VA.isMemLoc()) {
464 unsigned LocMemOffset = VA.getLocMemOffset();
465 SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
466 StackPtr.getValueType());
467 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
468 if (ArgAlign)
469 LargestAlignSeen = std::max(LargestAlignSeen,
470 (unsigned)VA.getLocVT().getStoreSizeInBits() >> 3);
471 if (Flags.isByVal()) {
472 // The argument is a struct passed by value. According to LLVM, "Arg"
473 // is a pointer.
474 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
475 Flags, DAG, dl));
476 } else {
477 MachinePointerInfo LocPI = MachinePointerInfo::getStack(
478 DAG.getMachineFunction(), LocMemOffset);
479 SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
480 MemOpChains.push_back(S);
481 }
482 continue;
483 }
484
485 // Arguments that can be passed on register must be kept at RegsToPass
486 // vector.
487 if (VA.isRegLoc())
488 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
489 }
490
491 if (NeedsArgAlign && Subtarget.hasV60Ops()) {
492 LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << "Function needs byte stack align due to call args\n"
; } } while (false)
;
493 unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
494 LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
495 MFI.ensureMaxAlignment(LargestAlignSeen);
496 }
497 // Transform all store nodes into one single node because all store
498 // nodes are independent of each other.
499 if (!MemOpChains.empty())
500 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
501
502 SDValue Glue;
503 if (!CLI.IsTailCall) {
504 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
505 Glue = Chain.getValue(1);
506 }
507
508 // Build a sequence of copy-to-reg nodes chained together with token
509 // chain and flag operands which copy the outgoing args into registers.
510 // The Glue is necessary since all emitted instructions must be
511 // stuck together.
512 if (!CLI.IsTailCall) {
513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
514 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
515 RegsToPass[i].second, Glue);
516 Glue = Chain.getValue(1);
517 }
518 } else {
519 // For tail calls lower the arguments to the 'real' stack slot.
520 //
521 // Force all the incoming stack arguments to be loaded from the stack
522 // before any new outgoing arguments are stored to the stack, because the
523 // outgoing stack slots may alias the incoming argument stack slots, and
524 // the alias isn't otherwise explicit. This is slightly more conservative
525 // than necessary, because it means that each store effectively depends
526 // on every argument instead of just those arguments it would clobber.
527 //
528 // Do not flag preceding copytoreg stuff together with the following stuff.
529 Glue = SDValue();
530 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
531 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
532 RegsToPass[i].second, Glue);
533 Glue = Chain.getValue(1);
534 }
535 Glue = SDValue();
536 }
537
538 bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
539 unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
540
541 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
542 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
543 // node so that legalize doesn't hack it.
544 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
545 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
546 } else if (ExternalSymbolSDNode *S =
547 dyn_cast<ExternalSymbolSDNode>(Callee)) {
548 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
549 }
550
551 // Returns a chain & a flag for retval copy to use.
552 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
553 SmallVector<SDValue, 8> Ops;
554 Ops.push_back(Chain);
555 Ops.push_back(Callee);
556
557 // Add argument registers to the end of the list so that they are
558 // known live into the call.
559 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
560 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
561 RegsToPass[i].second.getValueType()));
562 }
563
564 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
565 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 565, __PRETTY_FUNCTION__))
;
566 Ops.push_back(DAG.getRegisterMask(Mask));
567
568 if (Glue.getNode())
569 Ops.push_back(Glue);
570
571 if (CLI.IsTailCall) {
572 MFI.setHasTailCall();
573 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
574 }
575
576 // Set this here because we need to know this for "hasFP" in frame lowering.
577 // The target-independent code calls getFrameRegister before setting it, and
578 // getFrameRegister uses hasFP to determine whether the function has FP.
579 MFI.setHasCalls(true);
580
581 unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
582 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
583 Glue = Chain.getValue(1);
584
585 // Create the CALLSEQ_END node.
586 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
587 DAG.getIntPtrConstant(0, dl, true), Glue, dl);
588 Glue = Chain.getValue(1);
589
590 // Handle result values, copying them out of physregs into vregs that we
591 // return.
592 return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
593 InVals, OutVals, Callee);
594}
595
596/// Returns true by value, base pointer and offset pointer and addressing
597/// mode by reference if this node can be combined with a load / store to
598/// form a post-indexed load / store.
599bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
600 SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM,
601 SelectionDAG &DAG) const {
602 LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(N);
603 if (!LSN)
604 return false;
605 EVT VT = LSN->getMemoryVT();
606 if (!VT.isSimple())
607 return false;
608 bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
609 VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
610 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
611 VT == MVT::v4i16 || VT == MVT::v8i8 ||
612 Subtarget.isHVXVectorType(VT.getSimpleVT());
613 if (!IsLegalType)
614 return false;
615
616 if (Op->getOpcode() != ISD::ADD)
617 return false;
618 Base = Op->getOperand(0);
619 Offset = Op->getOperand(1);
620 if (!isa<ConstantSDNode>(Offset.getNode()))
621 return false;
622 AM = ISD::POST_INC;
623
624 int32_t V = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
625 return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
626}
627
628SDValue
629HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
630 MachineFunction &MF = DAG.getMachineFunction();
631 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
632 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
633 unsigned LR = HRI.getRARegister();
634
635 if ((Op.getOpcode() != ISD::INLINEASM &&
636 Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR())
637 return Op;
638
639 unsigned NumOps = Op.getNumOperands();
640 if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
641 --NumOps; // Ignore the flag operand.
642
643 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
644 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
645 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
646 ++i; // Skip the ID value.
647
648 switch (InlineAsm::getKind(Flags)) {
649 default:
650 llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 650)
;
651 case InlineAsm::Kind_RegUse:
652 case InlineAsm::Kind_Imm:
653 case InlineAsm::Kind_Mem:
654 i += NumVals;
655 break;
656 case InlineAsm::Kind_Clobber:
657 case InlineAsm::Kind_RegDef:
658 case InlineAsm::Kind_RegDefEarlyClobber: {
659 for (; NumVals; --NumVals, ++i) {
660 unsigned Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
661 if (Reg != LR)
662 continue;
663 HMFI.setHasClobberLR(true);
664 return Op;
665 }
666 break;
667 }
668 }
669 }
670
671 return Op;
672}
673
674// Need to transform ISD::PREFETCH into something that doesn't inherit
675// all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
676// SDNPMayStore.
677SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op,
678 SelectionDAG &DAG) const {
679 SDValue Chain = Op.getOperand(0);
680 SDValue Addr = Op.getOperand(1);
681 // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
682 // if the "reg" is fed by an "add".
683 SDLoc DL(Op);
684 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
685 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
686}
687
688// Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
689// is marked as having side-effects, while the register read on Hexagon does
690// not have any. TableGen refuses to accept the direct pattern from that node
691// to the A4_tfrcpp.
692SDValue HexagonTargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
693 SelectionDAG &DAG) const {
694 SDValue Chain = Op.getOperand(0);
695 SDLoc dl(Op);
696 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
697 return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
698}
699
700SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
701 SelectionDAG &DAG) const {
702 SDValue Chain = Op.getOperand(0);
703 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
704 // Lower the hexagon_prefetch builtin to DCFETCH, as above.
705 if (IntNo == Intrinsic::hexagon_prefetch) {
706 SDValue Addr = Op.getOperand(2);
707 SDLoc DL(Op);
708 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
709 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
710 }
711 return SDValue();
712}
713
714SDValue
715HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
716 SelectionDAG &DAG) const {
717 SDValue Chain = Op.getOperand(0);
718 SDValue Size = Op.getOperand(1);
719 SDValue Align = Op.getOperand(2);
720 SDLoc dl(Op);
721
722 ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
723 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC")((AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC"
) ? static_cast<void> (0) : __assert_fail ("AlignConst && \"Non-constant Align in LowerDYNAMIC_STACKALLOC\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 723, __PRETTY_FUNCTION__))
;
724
725 unsigned A = AlignConst->getSExtValue();
726 auto &HFI = *Subtarget.getFrameLowering();
727 // "Zero" means natural stack alignment.
728 if (A == 0)
729 A = HFI.getStackAlignment();
730
731 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
732 dbgs () << __func__ << " Align: " << A << " Size: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
733 Size.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
734 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
735 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
;
736
737 SDValue AC = DAG.getConstant(A, dl, MVT::i32);
738 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
739 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
740
741 DAG.ReplaceAllUsesOfValueWith(Op, AA);
742 return AA;
743}
744
745SDValue HexagonTargetLowering::LowerFormalArguments(
746 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
747 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
748 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
749 MachineFunction &MF = DAG.getMachineFunction();
750 MachineFrameInfo &MFI = MF.getFrameInfo();
751 MachineRegisterInfo &MRI = MF.getRegInfo();
752
753 // Assign locations to all of the incoming arguments.
754 SmallVector<CCValAssign, 16> ArgLocs;
755 HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
756 MF.getFunction().getFunctionType()->getNumParams());
757
758 if (Subtarget.useHVXOps())
759 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
760 else
761 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
762
763 // For LLVM, in the case when returning a struct by value (>8byte),
764 // the first argument is a pointer that points to the location on caller's
765 // stack where the return value will be stored. For Hexagon, the location on
766 // caller's stack is passed only when the struct size is smaller than (and
767 // equal to) 8 bytes. If not, no address will be passed into callee and
768 // callee return the result direclty through R0/R1.
769
770 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
771
772 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
773 CCValAssign &VA = ArgLocs[i];
774 ISD::ArgFlagsTy Flags = Ins[i].Flags;
775 bool ByVal = Flags.isByVal();
776
777 // Arguments passed in registers:
778 // 1. 32- and 64-bit values and HVX vectors are passed directly,
779 // 2. Large structs are passed via an address, and the address is
780 // passed in a register.
781 if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8)
782 llvm_unreachable("ByValSize must be bigger than 8 bytes")::llvm::llvm_unreachable_internal("ByValSize must be bigger than 8 bytes"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 782)
;
783
784 bool InReg = VA.isRegLoc() &&
785 (!ByVal || (ByVal && Flags.getByValSize() > 8));
786
787 if (InReg) {
788 MVT RegVT = VA.getLocVT();
789 if (VA.getLocInfo() == CCValAssign::BCvt)
790 RegVT = VA.getValVT();
791
792 const TargetRegisterClass *RC = getRegClassFor(RegVT);
793 Register VReg = MRI.createVirtualRegister(RC);
794 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
795
796 // Treat values of type MVT::i1 specially: they are passed in
797 // registers of type i32, but they need to remain as values of
798 // type i1 for consistency of the argument lowering.
799 if (VA.getValVT() == MVT::i1) {
800 assert(RegVT.getSizeInBits() <= 32)((RegVT.getSizeInBits() <= 32) ? static_cast<void> (
0) : __assert_fail ("RegVT.getSizeInBits() <= 32", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 800, __PRETTY_FUNCTION__))
;
801 SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
802 Copy, DAG.getConstant(1, dl, RegVT));
803 Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
804 ISD::SETNE);
805 } else {
806#ifndef NDEBUG
807 unsigned RegSize = RegVT.getSizeInBits();
808 assert(RegSize == 32 || RegSize == 64 ||((RegSize == 32 || RegSize == 64 || Subtarget.isHVXVectorType
(RegVT)) ? static_cast<void> (0) : __assert_fail ("RegSize == 32 || RegSize == 64 || Subtarget.isHVXVectorType(RegVT)"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 809, __PRETTY_FUNCTION__))
809 Subtarget.isHVXVectorType(RegVT))((RegSize == 32 || RegSize == 64 || Subtarget.isHVXVectorType
(RegVT)) ? static_cast<void> (0) : __assert_fail ("RegSize == 32 || RegSize == 64 || Subtarget.isHVXVectorType(RegVT)"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 809, __PRETTY_FUNCTION__))
;
810#endif
811 }
812 InVals.push_back(Copy);
813 MRI.addLiveIn(VA.getLocReg(), VReg);
814 } else {
815 assert(VA.isMemLoc() && "Argument should be passed in memory")((VA.isMemLoc() && "Argument should be passed in memory"
) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"Argument should be passed in memory\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 815, __PRETTY_FUNCTION__))
;
816
817 // If it's a byval parameter, then we need to compute the
818 // "real" size, not the size of the pointer.
819 unsigned ObjSize = Flags.isByVal()
820 ? Flags.getByValSize()
821 : VA.getLocVT().getStoreSizeInBits() / 8;
822
823 // Create the frame index object for this incoming parameter.
824 int Offset = HEXAGON_LRFP_SIZE8 + VA.getLocMemOffset();
825 int FI = MFI.CreateFixedObject(ObjSize, Offset, true);
826 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
827
828 if (Flags.isByVal()) {
829 // If it's a pass-by-value aggregate, then do not dereference the stack
830 // location. Instead, we should generate a reference to the stack
831 // location.
832 InVals.push_back(FIN);
833 } else {
834 SDValue L = DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
835 MachinePointerInfo::getFixedStack(MF, FI, 0));
836 InVals.push_back(L);
837 }
838 }
839 }
840
841
842 if (IsVarArg) {
843 // This will point to the next argument passed via stack.
844 int Offset = HEXAGON_LRFP_SIZE8 + CCInfo.getNextStackOffset();
845 int FI = MFI.CreateFixedObject(Hexagon_PointerSize(4), Offset, true);
846 HMFI.setVarArgsFrameIndex(FI);
847 }
848
849 return Chain;
850}
851
852SDValue
853HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
854 // VASTART stores the address of the VarArgsFrameIndex slot into the
855 // memory location argument.
856 MachineFunction &MF = DAG.getMachineFunction();
857 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
858 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
859 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
860 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
861 MachinePointerInfo(SV));
862}
863
864SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
865 const SDLoc &dl(Op);
866 SDValue LHS = Op.getOperand(0);
867 SDValue RHS = Op.getOperand(1);
868 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
869 MVT ResTy = ty(Op);
870 MVT OpTy = ty(LHS);
871
872 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
8
Taking false branch
873 MVT ElemTy = OpTy.getVectorElementType();
874 assert(ElemTy.isScalarInteger())((ElemTy.isScalarInteger()) ? static_cast<void> (0) : __assert_fail
("ElemTy.isScalarInteger()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 874, __PRETTY_FUNCTION__))
;
875 MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
876 OpTy.getVectorNumElements());
877 return DAG.getSetCC(dl, ResTy,
878 DAG.getSExtOrTrunc(LHS, SDLoc(LHS), WideTy),
879 DAG.getSExtOrTrunc(RHS, SDLoc(RHS), WideTy), CC);
880 }
881
882 // Treat all other vector types as legal.
883 if (ResTy.isVector())
9
Taking false branch
884 return Op;
885
886 // Comparisons of short integers should use sign-extend, not zero-extend,
887 // since we can represent small negative values in the compare instructions.
888 // The LLVM default is to use zero-extend arbitrarily in these cases.
889 auto isSExtFree = [this](SDValue N) {
890 switch (N.getOpcode()) {
14
Calling 'SDValue::getOpcode'
891 case ISD::TRUNCATE: {
892 // A sign-extend of a truncate of a sign-extend is free.
893 SDValue Op = N.getOperand(0);
894 if (Op.getOpcode() != ISD::AssertSext)
895 return false;
896 EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
897 unsigned ThisBW = ty(N).getSizeInBits();
898 unsigned OrigBW = OrigTy.getSizeInBits();
899 // The type that was sign-extended to get the AssertSext must be
900 // narrower than the type of N (so that N has still the same value
901 // as the original).
902 return ThisBW >= OrigBW;
903 }
904 case ISD::LOAD:
905 // We have sign-extended loads.
906 return true;
907 }
908 return false;
909 };
910
911 if (OpTy == MVT::i8 || OpTy == MVT::i16) {
10
Taking true branch
912 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
913 bool IsNegative = C && C->getAPIntValue().isNegative();
11
Assuming 'C' is null
914 if (IsNegative
11.1
'IsNegative' is false
11.1
'IsNegative' is false
|| isSExtFree(LHS) || isSExtFree(RHS))
12
Value assigned to 'N.Node'
13
Calling 'operator()'
915 return DAG.getSetCC(dl, ResTy,
916 DAG.getSExtOrTrunc(LHS, SDLoc(LHS), MVT::i32),
917 DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC);
918 }
919
920 return SDValue();
921}
922
923SDValue
924HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
925 SDValue PredOp = Op.getOperand(0);
926 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
927 MVT OpTy = ty(Op1);
928 const SDLoc &dl(Op);
929
930 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
931 MVT ElemTy = OpTy.getVectorElementType();
932 assert(ElemTy.isScalarInteger())((ElemTy.isScalarInteger()) ? static_cast<void> (0) : __assert_fail
("ElemTy.isScalarInteger()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 932, __PRETTY_FUNCTION__))
;
933 MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
934 OpTy.getVectorNumElements());
935 // Generate (trunc (select (_, sext, sext))).
936 return DAG.getSExtOrTrunc(
937 DAG.getSelect(dl, WideTy, PredOp,
938 DAG.getSExtOrTrunc(Op1, dl, WideTy),
939 DAG.getSExtOrTrunc(Op2, dl, WideTy)),
940 dl, OpTy);
941 }
942
943 return SDValue();
944}
945
946static Constant *convert_i1_to_i8(const Constant *ConstVal) {
947 SmallVector<Constant *, 128> NewConst;
948 const ConstantVector *CV = dyn_cast<ConstantVector>(ConstVal);
949 if (!CV)
950 return nullptr;
951
952 LLVMContext &Ctx = ConstVal->getContext();
953 IRBuilder<> IRB(Ctx);
954 unsigned NumVectorElements = CV->getNumOperands();
955 assert(isPowerOf2_32(NumVectorElements) &&((isPowerOf2_32(NumVectorElements) && "conversion only supported for pow2 VectorSize!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumVectorElements) && \"conversion only supported for pow2 VectorSize!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 956, __PRETTY_FUNCTION__))
956 "conversion only supported for pow2 VectorSize!")((isPowerOf2_32(NumVectorElements) && "conversion only supported for pow2 VectorSize!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumVectorElements) && \"conversion only supported for pow2 VectorSize!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 956, __PRETTY_FUNCTION__))
;
957
958 for (unsigned i = 0; i < NumVectorElements / 8; ++i) {
959 uint8_t x = 0;
960 for (unsigned j = 0; j < 8; ++j) {
961 uint8_t y = CV->getOperand(i * 8 + j)->getUniqueInteger().getZExtValue();
962 x |= y << (7 - j);
963 }
964 assert((x == 0 || x == 255) && "Either all 0's or all 1's expected!")(((x == 0 || x == 255) && "Either all 0's or all 1's expected!"
) ? static_cast<void> (0) : __assert_fail ("(x == 0 || x == 255) && \"Either all 0's or all 1's expected!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 964, __PRETTY_FUNCTION__))
;
965 NewConst.push_back(IRB.getInt8(x));
966 }
967 return ConstantVector::get(NewConst);
968}
969
970SDValue
971HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
972 EVT ValTy = Op.getValueType();
973 ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
974 Constant *CVal = nullptr;
975 bool isVTi1Type = false;
976 if (const Constant *ConstVal = dyn_cast<Constant>(CPN->getConstVal())) {
977 Type *CValTy = ConstVal->getType();
978 if (CValTy->isVectorTy() &&
979 CValTy->getVectorElementType()->isIntegerTy(1)) {
980 CVal = convert_i1_to_i8(ConstVal);
981 isVTi1Type = (CVal != nullptr);
982 }
983 }
984 unsigned Align = CPN->getAlignment();
985 bool IsPositionIndependent = isPositionIndependent();
986 unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
987
988 unsigned Offset = 0;
989 SDValue T;
990 if (CPN->isMachineConstantPoolEntry())
991 T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
992 TF);
993 else if (isVTi1Type)
994 T = DAG.getTargetConstantPool(CVal, ValTy, Align, Offset, TF);
995 else
996 T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset, TF);
997
998 assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&((cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF
&& "Inconsistent target flag encountered") ? static_cast
<void> (0) : __assert_fail ("cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && \"Inconsistent target flag encountered\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 999, __PRETTY_FUNCTION__))
999 "Inconsistent target flag encountered")((cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF
&& "Inconsistent target flag encountered") ? static_cast
<void> (0) : __assert_fail ("cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && \"Inconsistent target flag encountered\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 999, __PRETTY_FUNCTION__))
;
1000
1001 if (IsPositionIndependent)
1002 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1003 return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1004}
1005
1006SDValue
1007HexagonTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1008 EVT VT = Op.getValueType();
1009 int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1010 if (isPositionIndependent()) {
1011 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
1012 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1013 }
1014
1015 SDValue T = DAG.getTargetJumpTable(Idx, VT);
1016 return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1017}
1018
1019SDValue
1020HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
1021 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1022 MachineFunction &MF = DAG.getMachineFunction();
1023 MachineFrameInfo &MFI = MF.getFrameInfo();
1024 MFI.setReturnAddressIsTaken(true);
1025
1026 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1027 return SDValue();
1028
1029 EVT VT = Op.getValueType();
1030 SDLoc dl(Op);
1031 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1032 if (Depth) {
1033 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1034 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1035 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1036 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1037 MachinePointerInfo());
1038 }
1039
1040 // Return LR, which contains the return address. Mark it an implicit live-in.
1041 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1042 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1043}
1044
1045SDValue
1046HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1047 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1048 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1049 MFI.setFrameAddressIsTaken(true);
1050
1051 EVT VT = Op.getValueType();
1052 SDLoc dl(Op);
1053 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1054 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1055 HRI.getFrameRegister(), VT);
1056 while (Depth--)
1057 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1058 MachinePointerInfo());
1059 return FrameAddr;
1060}
1061
1062SDValue
1063HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const {
1064 SDLoc dl(Op);
1065 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1066}
1067
1068SDValue
1069HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const {
1070 SDLoc dl(Op);
1071 auto *GAN = cast<GlobalAddressSDNode>(Op);
1072 auto PtrVT = getPointerTy(DAG.getDataLayout());
1073 auto *GV = GAN->getGlobal();
1074 int64_t Offset = GAN->getOffset();
1075
1076 auto &HLOF = *HTM.getObjFileLowering();
1077 Reloc::Model RM = HTM.getRelocationModel();
1078
1079 if (RM == Reloc::Static) {
1080 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1081 const GlobalObject *GO = GV->getBaseObject();
1082 if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
1083 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1084 return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1085 }
1086
1087 bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1088 if (UsePCRel) {
1089 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1090 HexagonII::MO_PCREL);
1091 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1092 }
1093
1094 // Use GOT index.
1095 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1096 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1097 SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1098 return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1099}
1100
1101// Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1102SDValue
1103HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1104 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1105 SDLoc dl(Op);
1106 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1107
1108 Reloc::Model RM = HTM.getRelocationModel();
1109 if (RM == Reloc::Static) {
1110 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1111 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1112 }
1113
1114 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1115 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1116}
1117
1118SDValue
1119HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG)
1120 const {
1121 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1122 SDValue GOTSym = DAG.getTargetExternalSymbol(HEXAGON_GOT_SYM_NAME"_GLOBAL_OFFSET_TABLE_", PtrVT,
1123 HexagonII::MO_PCREL);
1124 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1125}
1126
1127SDValue
1128HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
1129 GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1130 unsigned char OperandFlags) const {
1131 MachineFunction &MF = DAG.getMachineFunction();
1132 MachineFrameInfo &MFI = MF.getFrameInfo();
1133 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1134 SDLoc dl(GA);
1135 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1136 GA->getValueType(0),
1137 GA->getOffset(),
1138 OperandFlags);
1139 // Create Operands for the call.The Operands should have the following:
1140 // 1. Chain SDValue
1141 // 2. Callee which in this case is the Global address value.
1142 // 3. Registers live into the call.In this case its R0, as we
1143 // have just one argument to be passed.
1144 // 4. Glue.
1145 // Note: The order is important.
1146
1147 const auto &HRI = *Subtarget.getRegisterInfo();
1148 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1149 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1149, __PRETTY_FUNCTION__))
;
1150 SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1151 DAG.getRegisterMask(Mask), Glue };
1152 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1153
1154 // Inform MFI that function has calls.
1155 MFI.setAdjustsStack(true);
1156
1157 Glue = Chain.getValue(1);
1158 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1159}
1160
1161//
1162// Lower using the intial executable model for TLS addresses
1163//
1164SDValue
1165HexagonTargetLowering::LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
1166 SelectionDAG &DAG) const {
1167 SDLoc dl(GA);
1168 int64_t Offset = GA->getOffset();
1169 auto PtrVT = getPointerTy(DAG.getDataLayout());
1170
1171 // Get the thread pointer.
1172 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1173
1174 bool IsPositionIndependent = isPositionIndependent();
1175 unsigned char TF =
1176 IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1177
1178 // First generate the TLS symbol address
1179 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1180 Offset, TF);
1181
1182 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1183
1184 if (IsPositionIndependent) {
1185 // Generate the GOT pointer in case of position independent code
1186 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1187
1188 // Add the TLS Symbol address to GOT pointer.This gives
1189 // GOT relative relocation for the symbol.
1190 Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1191 }
1192
1193 // Load the offset value for TLS symbol.This offset is relative to
1194 // thread pointer.
1195 SDValue LoadOffset =
1196 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1197
1198 // Address of the thread local variable is the add of thread
1199 // pointer and the offset of the variable.
1200 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1201}
1202
1203//
1204// Lower using the local executable model for TLS addresses
1205//
1206SDValue
1207HexagonTargetLowering::LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
1208 SelectionDAG &DAG) const {
1209 SDLoc dl(GA);
1210 int64_t Offset = GA->getOffset();
1211 auto PtrVT = getPointerTy(DAG.getDataLayout());
1212
1213 // Get the thread pointer.
1214 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1215 // Generate the TLS symbol address
1216 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1217 HexagonII::MO_TPREL);
1218 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1219
1220 // Address of the thread local variable is the add of thread
1221 // pointer and the offset of the variable.
1222 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1223}
1224
1225//
1226// Lower using the general dynamic model for TLS addresses
1227//
1228SDValue
1229HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1230 SelectionDAG &DAG) const {
1231 SDLoc dl(GA);
1232 int64_t Offset = GA->getOffset();
1233 auto PtrVT = getPointerTy(DAG.getDataLayout());
1234
1235 // First generate the TLS symbol address
1236 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1237 HexagonII::MO_GDGOT);
1238
1239 // Then, generate the GOT pointer
1240 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1241
1242 // Add the TLS symbol and the GOT pointer
1243 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1244 SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1245
1246 // Copy over the argument to R0
1247 SDValue InFlag;
1248 Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1249 InFlag = Chain.getValue(1);
1250
1251 unsigned Flags =
1252 static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
1253 ? HexagonII::MO_GDPLT | HexagonII::HMOTF_ConstExtended
1254 : HexagonII::MO_GDPLT;
1255
1256 return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1257 Hexagon::R0, Flags);
1258}
1259
1260//
1261// Lower TLS addresses.
1262//
1263// For now for dynamic models, we only support the general dynamic model.
1264//
1265SDValue
1266HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1267 SelectionDAG &DAG) const {
1268 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1269
1270 switch (HTM.getTLSModel(GA->getGlobal())) {
1271 case TLSModel::GeneralDynamic:
1272 case TLSModel::LocalDynamic:
1273 return LowerToTLSGeneralDynamicModel(GA, DAG);
1274 case TLSModel::InitialExec:
1275 return LowerToTLSInitialExecModel(GA, DAG);
1276 case TLSModel::LocalExec:
1277 return LowerToTLSLocalExecModel(GA, DAG);
1278 }
1279 llvm_unreachable("Bogus TLS model")::llvm::llvm_unreachable_internal("Bogus TLS model", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1279)
;
1280}
1281
1282//===----------------------------------------------------------------------===//
1283// TargetLowering Implementation
1284//===----------------------------------------------------------------------===//
1285
1286HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
1287 const HexagonSubtarget &ST)
1288 : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1289 Subtarget(ST) {
1290 auto &HRI = *Subtarget.getRegisterInfo();
1291
1292 setPrefLoopAlignment(Align(16));
1293 setMinFunctionAlignment(Align(4));
1294 setPrefFunctionAlignment(Align(16));
1295 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1296 setBooleanContents(TargetLoweringBase::UndefinedBooleanContent);
1297 setBooleanVectorContents(TargetLoweringBase::UndefinedBooleanContent);
1298
1299 setMaxAtomicSizeInBitsSupported(64);
1300 setMinCmpXchgSizeInBits(32);
1301
1302 if (EnableHexSDNodeSched)
1303 setSchedulingPreference(Sched::VLIW);
1304 else
1305 setSchedulingPreference(Sched::Source);
1306
1307 // Limits for inline expansion of memcpy/memmove
1308 MaxStoresPerMemcpy = MaxStoresPerMemcpyCL;
1309 MaxStoresPerMemcpyOptSize = MaxStoresPerMemcpyOptSizeCL;
1310 MaxStoresPerMemmove = MaxStoresPerMemmoveCL;
1311 MaxStoresPerMemmoveOptSize = MaxStoresPerMemmoveOptSizeCL;
1312 MaxStoresPerMemset = MaxStoresPerMemsetCL;
1313 MaxStoresPerMemsetOptSize = MaxStoresPerMemsetOptSizeCL;
1314
1315 //
1316 // Set up register classes.
1317 //
1318
1319 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1320 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1321 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1322 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1323 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1324 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1325 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1326 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1327 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1328 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1329 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1330
1331 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1332 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1333
1334 //
1335 // Handling of scalar operations.
1336 //
1337 // All operations default to "legal", except:
1338 // - indexed loads and stores (pre-/post-incremented),
1339 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1340 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1341 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1342 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1343 // which default to "expand" for at least one type.
1344
1345 // Misc operations.
1346 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
1347 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
1348 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1349 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1350 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
1351 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1352 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1353 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1354 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom);
1355 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1356 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1357 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1358 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1359 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
1360 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1361 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1362
1363 // Custom legalize GlobalAddress nodes into CONST32.
1364 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1365 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1366 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1367
1368 // Hexagon needs to optimize cases with negative constants.
1369 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1370 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1371 setOperationAction(ISD::SETCC, MVT::v4i8, Custom);
1372 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1373
1374 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1375 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1376 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1377 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1378 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1379
1380 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1381 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1382 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1383
1384 if (EmitJumpTables)
1385 setMinimumJumpTableEntries(MinimumJumpTables);
1386 else
1387 setMinimumJumpTableEntries(std::numeric_limits<unsigned>::max());
1388 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1389
1390 setOperationAction(ISD::ABS, MVT::i32, Legal);
1391 setOperationAction(ISD::ABS, MVT::i64, Legal);
1392
1393 // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
1394 // but they only operate on i64.
1395 for (MVT VT : MVT::integer_valuetypes()) {
1396 setOperationAction(ISD::UADDO, VT, Custom);
1397 setOperationAction(ISD::USUBO, VT, Custom);
1398 setOperationAction(ISD::SADDO, VT, Expand);
1399 setOperationAction(ISD::SSUBO, VT, Expand);
1400 setOperationAction(ISD::ADDCARRY, VT, Expand);
1401 setOperationAction(ISD::SUBCARRY, VT, Expand);
1402 }
1403 setOperationAction(ISD::ADDCARRY, MVT::i64, Custom);
1404 setOperationAction(ISD::SUBCARRY, MVT::i64, Custom);
1405
1406 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1407 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1408 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1409 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1410
1411 // Popcount can count # of 1s in i64 but returns i32.
1412 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1413 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1414 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1415 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
1416
1417 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1418 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
1419 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
1420 setOperationAction(ISD::BSWAP, MVT::i64, Legal);
1421
1422 setOperationAction(ISD::FSHL, MVT::i32, Legal);
1423 setOperationAction(ISD::FSHL, MVT::i64, Legal);
1424 setOperationAction(ISD::FSHR, MVT::i32, Legal);
1425 setOperationAction(ISD::FSHR, MVT::i64, Legal);
1426
1427 for (unsigned IntExpOp :
1428 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1429 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1430 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
1431 ISD::SMUL_LOHI, ISD::UMUL_LOHI}) {
1432 for (MVT VT : MVT::integer_valuetypes())
1433 setOperationAction(IntExpOp, VT, Expand);
1434 }
1435
1436 for (unsigned FPExpOp :
1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1438 ISD::FPOW, ISD::FCOPYSIGN}) {
1439 for (MVT VT : MVT::fp_valuetypes())
1440 setOperationAction(FPExpOp, VT, Expand);
1441 }
1442
1443 // No extending loads from i32.
1444 for (MVT VT : MVT::integer_valuetypes()) {
1445 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1446 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1447 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1448 }
1449 // Turn FP truncstore into trunc + store.
1450 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1451 // Turn FP extload into load/fpextend.
1452 for (MVT VT : MVT::fp_valuetypes())
1453 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1454
1455 // Expand BR_CC and SELECT_CC for all integer and fp types.
1456 for (MVT VT : MVT::integer_valuetypes()) {
1457 setOperationAction(ISD::BR_CC, VT, Expand);
1458 setOperationAction(ISD::SELECT_CC, VT, Expand);
1459 }
1460 for (MVT VT : MVT::fp_valuetypes()) {
1461 setOperationAction(ISD::BR_CC, VT, Expand);
1462 setOperationAction(ISD::SELECT_CC, VT, Expand);
1463 }
1464 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1465
1466 //
1467 // Handling of vector operations.
1468 //
1469
1470 // Set the action for vector operations to "expand", then override it with
1471 // either "custom" or "legal" for specific cases.
1472 static const unsigned VectExpOps[] = {
1473 // Integer arithmetic:
1474 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1475 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO,
1476 ISD::UADDO, ISD::SSUBO, ISD::USUBO, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1477 // Logical/bit:
1478 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1479 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
1480 // Floating point arithmetic/math functions:
1481 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1482 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
1483 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
1484 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
1485 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1486 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1487 // Misc:
1488 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
1489 // Vector:
1490 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
1491 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1492 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1493 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
1494 };
1495
1496 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1497 for (unsigned VectExpOp : VectExpOps)
1498 setOperationAction(VectExpOp, VT, Expand);
1499
1500 // Expand all extending loads and truncating stores:
1501 for (MVT TargetVT : MVT::fixedlen_vector_valuetypes()) {
1502 if (TargetVT == VT)
1503 continue;
1504 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1505 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1506 setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1507 setTruncStoreAction(VT, TargetVT, Expand);
1508 }
1509
1510 // Normalize all inputs to SELECT to be vectors of i32.
1511 if (VT.getVectorElementType() != MVT::i32) {
1512 MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
1513 setOperationAction(ISD::SELECT, VT, Promote);
1514 AddPromotedToType(ISD::SELECT, VT, VT32);
1515 }
1516 setOperationAction(ISD::SRA, VT, Custom);
1517 setOperationAction(ISD::SHL, VT, Custom);
1518 setOperationAction(ISD::SRL, VT, Custom);
1519 }
1520
1521 // Extending loads from (native) vectors of i8 into (native) vectors of i16
1522 // are legal.
1523 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1524 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1525 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1526 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1527 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1528 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1529
1530 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
1531 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1532 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
1533
1534 // Types natively supported:
1535 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1536 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1537 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
1538 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
1539 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
1540 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
1541 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
1542 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
1543
1544 setOperationAction(ISD::ADD, NativeVT, Legal);
1545 setOperationAction(ISD::SUB, NativeVT, Legal);
1546 setOperationAction(ISD::MUL, NativeVT, Legal);
1547 setOperationAction(ISD::AND, NativeVT, Legal);
1548 setOperationAction(ISD::OR, NativeVT, Legal);
1549 setOperationAction(ISD::XOR, NativeVT, Legal);
1550 }
1551
1552 // Custom lower unaligned loads.
1553 // Also, for both loads and stores, verify the alignment of the address
1554 // in case it is a compile-time constant. This is a usability feature to
1555 // provide a meaningful error message to users.
1556 for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
1557 MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1558 setOperationAction(ISD::LOAD, VT, Custom);
1559 setOperationAction(ISD::STORE, VT, Custom);
1560 }
1561
1562 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
1563 MVT::v2i32}) {
1564 setCondCodeAction(ISD::SETNE, VT, Expand);
1565 setCondCodeAction(ISD::SETLE, VT, Expand);
1566 setCondCodeAction(ISD::SETGE, VT, Expand);
1567 setCondCodeAction(ISD::SETLT, VT, Expand);
1568 setCondCodeAction(ISD::SETULE, VT, Expand);
1569 setCondCodeAction(ISD::SETUGE, VT, Expand);
1570 setCondCodeAction(ISD::SETULT, VT, Expand);
1571 }
1572
1573 // Custom-lower bitcasts from i8 to v8i1.
1574 setOperationAction(ISD::BITCAST, MVT::i8, Custom);
1575 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1576 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom);
1577 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
1578 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom);
1579 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1580 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1581
1582 // V5+.
1583 setOperationAction(ISD::FMA, MVT::f64, Expand);
1584 setOperationAction(ISD::FADD, MVT::f64, Expand);
1585 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1586 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1587
1588 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1589 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1590
1591 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1592 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1593 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1594 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1595 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1596 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1597 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1598 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1599 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1600 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1601 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1602 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1603
1604 // Handling of indexed loads/stores: default is "expand".
1605 //
1606 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64,
1607 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
1608 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
1609 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
1610 }
1611
1612 // Subtarget-specific operation actions.
1613 //
1614 if (Subtarget.hasV60Ops()) {
1615 setOperationAction(ISD::ROTL, MVT::i32, Legal);
1616 setOperationAction(ISD::ROTL, MVT::i64, Legal);
1617 setOperationAction(ISD::ROTR, MVT::i32, Legal);
1618 setOperationAction(ISD::ROTR, MVT::i64, Legal);
1619 }
1620 if (Subtarget.hasV66Ops()) {
1621 setOperationAction(ISD::FADD, MVT::f64, Legal);
1622 setOperationAction(ISD::FSUB, MVT::f64, Legal);
1623 }
1624
1625 setTargetDAGCombine(ISD::VSELECT);
1626
1627 if (Subtarget.useHVXOps())
1628 initializeHVXLowering();
1629
1630 computeRegisterProperties(&HRI);
1631
1632 //
1633 // Library calls for unsupported operations
1634 //
1635 bool FastMath = EnableFastMath;
1636
1637 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1638 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1639 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1640 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1641 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1642 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1643 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1644 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1645
1646 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1647 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1648 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1649 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1650 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1651 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1652
1653 // This is the only fast library function for sqrtd.
1654 if (FastMath)
1655 setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1656
1657 // Prefix is: nothing for "slow-math",
1658 // "fast2_" for V5+ fast-math double-precision
1659 // (actually, keep fast-math and fast-math2 separate for now)
1660 if (FastMath) {
1661 setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1662 setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1663 setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1664 setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1665 setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1666 } else {
1667 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1668 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1669 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1670 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1671 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1672 }
1673
1674 if (FastMath)
1675 setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1676 else
1677 setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1678
1679 // These cause problems when the shift amount is non-constant.
1680 setLibcallName(RTLIB::SHL_I128, nullptr);
1681 setLibcallName(RTLIB::SRL_I128, nullptr);
1682 setLibcallName(RTLIB::SRA_I128, nullptr);
1683}
1684
1685const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
1686 switch ((HexagonISD::NodeType)Opcode) {
1687 case HexagonISD::ADDC: return "HexagonISD::ADDC";
1688 case HexagonISD::SUBC: return "HexagonISD::SUBC";
1689 case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
1690 case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
1691 case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
1692 case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
1693 case HexagonISD::CALL: return "HexagonISD::CALL";
1694 case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
1695 case HexagonISD::CALLR: return "HexagonISD::CALLR";
1696 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
1697 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
1698 case HexagonISD::CONST32: return "HexagonISD::CONST32";
1699 case HexagonISD::CP: return "HexagonISD::CP";
1700 case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
1701 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
1702 case HexagonISD::TSTBIT: return "HexagonISD::TSTBIT";
1703 case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
1704 case HexagonISD::INSERT: return "HexagonISD::INSERT";
1705 case HexagonISD::JT: return "HexagonISD::JT";
1706 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
1707 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
1708 case HexagonISD::VASL: return "HexagonISD::VASL";
1709 case HexagonISD::VASR: return "HexagonISD::VASR";
1710 case HexagonISD::VLSR: return "HexagonISD::VLSR";
1711 case HexagonISD::VSPLAT: return "HexagonISD::VSPLAT";
1712 case HexagonISD::VEXTRACTW: return "HexagonISD::VEXTRACTW";
1713 case HexagonISD::VINSERTW0: return "HexagonISD::VINSERTW0";
1714 case HexagonISD::VROR: return "HexagonISD::VROR";
1715 case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
1716 case HexagonISD::PTRUE: return "HexagonISD::PTRUE";
1717 case HexagonISD::PFALSE: return "HexagonISD::PFALSE";
1718 case HexagonISD::VZERO: return "HexagonISD::VZERO";
1719 case HexagonISD::VSPLATW: return "HexagonISD::VSPLATW";
1720 case HexagonISD::D2P: return "HexagonISD::D2P";
1721 case HexagonISD::P2D: return "HexagonISD::P2D";
1722 case HexagonISD::V2Q: return "HexagonISD::V2Q";
1723 case HexagonISD::Q2V: return "HexagonISD::Q2V";
1724 case HexagonISD::QCAT: return "HexagonISD::QCAT";
1725 case HexagonISD::QTRUE: return "HexagonISD::QTRUE";
1726 case HexagonISD::QFALSE: return "HexagonISD::QFALSE";
1727 case HexagonISD::TYPECAST: return "HexagonISD::TYPECAST";
1728 case HexagonISD::VALIGN: return "HexagonISD::VALIGN";
1729 case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR";
1730 case HexagonISD::OP_END: break;
1731 }
1732 return nullptr;
1733}
1734
1735void
1736HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl,
1737 unsigned NeedAlign) const {
1738 auto *CA = dyn_cast<ConstantSDNode>(Ptr);
1739 if (!CA)
1740 return;
1741 unsigned Addr = CA->getZExtValue();
1742 unsigned HaveAlign = Addr != 0 ? 1u << countTrailingZeros(Addr) : NeedAlign;
1743 if (HaveAlign < NeedAlign) {
1744 std::string ErrMsg;
1745 raw_string_ostream O(ErrMsg);
1746 O << "Misaligned constant address: " << format_hex(Addr, 10)
1747 << " has alignment " << HaveAlign
1748 << ", but the memory access requires " << NeedAlign;
1749 if (DebugLoc DL = dl.getDebugLoc())
1750 DL.print(O << ", at ");
1751 report_fatal_error(O.str());
1752 }
1753}
1754
1755// Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
1756// intrinsic.
1757static bool isBrevLdIntrinsic(const Value *Inst) {
1758 unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
1759 return (ID == Intrinsic::hexagon_L2_loadrd_pbr ||
1760 ID == Intrinsic::hexagon_L2_loadri_pbr ||
1761 ID == Intrinsic::hexagon_L2_loadrh_pbr ||
1762 ID == Intrinsic::hexagon_L2_loadruh_pbr ||
1763 ID == Intrinsic::hexagon_L2_loadrb_pbr ||
1764 ID == Intrinsic::hexagon_L2_loadrub_pbr);
1765}
1766
1767// Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
1768// instruction. So far we only handle bitcast, extract value and bit reverse
1769// load intrinsic instructions. Should we handle CGEP ?
1770static Value *getBrevLdObject(Value *V) {
1771 if (Operator::getOpcode(V) == Instruction::ExtractValue ||
1772 Operator::getOpcode(V) == Instruction::BitCast)
1773 V = cast<Operator>(V)->getOperand(0);
1774 else if (isa<IntrinsicInst>(V) && isBrevLdIntrinsic(V))
1775 V = cast<Instruction>(V)->getOperand(0);
1776 return V;
1777}
1778
1779// Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
1780// a back edge. If the back edge comes from the intrinsic itself, the incoming
1781// edge is returned.
1782static Value *returnEdge(const PHINode *PN, Value *IntrBaseVal) {
1783 const BasicBlock *Parent = PN->getParent();
1784 int Idx = -1;
1785 for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
1786 BasicBlock *Blk = PN->getIncomingBlock(i);
1787 // Determine if the back edge is originated from intrinsic.
1788 if (Blk == Parent) {
1789 Value *BackEdgeVal = PN->getIncomingValue(i);
1790 Value *BaseVal;
1791 // Loop over till we return the same Value or we hit the IntrBaseVal.
1792 do {
1793 BaseVal = BackEdgeVal;
1794 BackEdgeVal = getBrevLdObject(BackEdgeVal);
1795 } while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
1796 // If the getBrevLdObject returns IntrBaseVal, we should return the
1797 // incoming edge.
1798 if (IntrBaseVal == BackEdgeVal)
1799 continue;
1800 Idx = i;
1801 break;
1802 } else // Set the node to incoming edge.
1803 Idx = i;
1804 }
1805 assert(Idx >= 0 && "Unexpected index to incoming argument in PHI")((Idx >= 0 && "Unexpected index to incoming argument in PHI"
) ? static_cast<void> (0) : __assert_fail ("Idx >= 0 && \"Unexpected index to incoming argument in PHI\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1805, __PRETTY_FUNCTION__))
;
1806 return PN->getIncomingValue(Idx);
1807}
1808
1809// Bit-reverse Load Intrinsic: Figure out the underlying object the base
1810// pointer points to, for the bit-reverse load intrinsic. Setting this to
1811// memoperand might help alias analysis to figure out the dependencies.
1812static Value *getUnderLyingObjectForBrevLdIntr(Value *V) {
1813 Value *IntrBaseVal = V;
1814 Value *BaseVal;
1815 // Loop over till we return the same Value, implies we either figure out
1816 // the object or we hit a PHI
1817 do {
1818 BaseVal = V;
1819 V = getBrevLdObject(V);
1820 } while (BaseVal != V);
1821
1822 // Identify the object from PHINode.
1823 if (const PHINode *PN = dyn_cast<PHINode>(V))
1824 return returnEdge(PN, IntrBaseVal);
1825 // For non PHI nodes, the object is the last value returned by getBrevLdObject
1826 else
1827 return V;
1828}
1829
1830/// Given an intrinsic, checks if on the target the intrinsic will need to map
1831/// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1832/// true and store the intrinsic information into the IntrinsicInfo that was
1833/// passed to the function.
1834bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1835 const CallInst &I,
1836 MachineFunction &MF,
1837 unsigned Intrinsic) const {
1838 switch (Intrinsic) {
1839 case Intrinsic::hexagon_L2_loadrd_pbr:
1840 case Intrinsic::hexagon_L2_loadri_pbr:
1841 case Intrinsic::hexagon_L2_loadrh_pbr:
1842 case Intrinsic::hexagon_L2_loadruh_pbr:
1843 case Intrinsic::hexagon_L2_loadrb_pbr:
1844 case Intrinsic::hexagon_L2_loadrub_pbr: {
1845 Info.opc = ISD::INTRINSIC_W_CHAIN;
1846 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
1847 auto &Cont = I.getCalledFunction()->getParent()->getContext();
1848 // The intrinsic function call is of the form { ElTy, i8* }
1849 // @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type
1850 // should be derived from ElTy.
1851 Type *ElTy = I.getCalledFunction()->getReturnType()->getStructElementType(0);
1852 Info.memVT = MVT::getVT(ElTy);
1853 llvm::Value *BasePtrVal = I.getOperand(0);
1854 Info.ptrVal = getUnderLyingObjectForBrevLdIntr(BasePtrVal);
1855 // The offset value comes through Modifier register. For now, assume the
1856 // offset is 0.
1857 Info.offset = 0;
1858 Info.align =
1859 MaybeAlign(DL.getABITypeAlignment(Info.memVT.getTypeForEVT(Cont)));
1860 Info.flags = MachineMemOperand::MOLoad;
1861 return true;
1862 }
1863 case Intrinsic::hexagon_V6_vgathermw:
1864 case Intrinsic::hexagon_V6_vgathermw_128B:
1865 case Intrinsic::hexagon_V6_vgathermh:
1866 case Intrinsic::hexagon_V6_vgathermh_128B:
1867 case Intrinsic::hexagon_V6_vgathermhw:
1868 case Intrinsic::hexagon_V6_vgathermhw_128B:
1869 case Intrinsic::hexagon_V6_vgathermwq:
1870 case Intrinsic::hexagon_V6_vgathermwq_128B:
1871 case Intrinsic::hexagon_V6_vgathermhq:
1872 case Intrinsic::hexagon_V6_vgathermhq_128B:
1873 case Intrinsic::hexagon_V6_vgathermhwq:
1874 case Intrinsic::hexagon_V6_vgathermhwq_128B: {
1875 const Module &M = *I.getParent()->getParent()->getParent();
1876 Info.opc = ISD::INTRINSIC_W_CHAIN;
1877 Type *VecTy = I.getArgOperand(1)->getType();
1878 Info.memVT = MVT::getVT(VecTy);
1879 Info.ptrVal = I.getArgOperand(0);
1880 Info.offset = 0;
1881 Info.align =
1882 MaybeAlign(M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8);
1883 Info.flags = MachineMemOperand::MOLoad |
1884 MachineMemOperand::MOStore |
1885 MachineMemOperand::MOVolatile;
1886 return true;
1887 }
1888 default:
1889 break;
1890 }
1891 return false;
1892}
1893
1894bool HexagonTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
1895 return X.getValueType().isScalarInteger(); // 'tstbit'
1896}
1897
1898bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
1899 return isTruncateFree(EVT::getEVT(Ty1), EVT::getEVT(Ty2));
1900}
1901
1902bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1903 if (!VT1.isSimple() || !VT2.isSimple())
1904 return false;
1905 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
1906}
1907
1908bool HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(
1909 const MachineFunction &MF, EVT VT) const {
1910 return isOperationLegalOrCustom(ISD::FMA, VT);
1911}
1912
1913// Should we expand the build vector with shuffles?
1914bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
1915 unsigned DefinedValues) const {
1916 return false;
1917}
1918
1919bool HexagonTargetLowering::isShuffleMaskLegal(ArrayRef<int> Mask,
1920 EVT VT) const {
1921 return true;
1922}
1923
1924TargetLoweringBase::LegalizeTypeAction
1925HexagonTargetLowering::getPreferredVectorAction(MVT VT) const {
1926 unsigned VecLen = VT.getVectorNumElements();
1927 MVT ElemTy = VT.getVectorElementType();
1928
1929 if (VecLen == 1 || VT.isScalableVector())
1930 return TargetLoweringBase::TypeScalarizeVector;
1931
1932 if (Subtarget.useHVXOps()) {
1933 unsigned HwLen = Subtarget.getVectorLength();
1934 // If the size of VT is at least half of the vector length,
1935 // widen the vector. Note: the threshold was not selected in
1936 // any scientific way.
1937 ArrayRef<MVT> Tys = Subtarget.getHVXElementTypes();
1938 if (llvm::find(Tys, ElemTy) != Tys.end()) {
1939 unsigned HwWidth = 8*HwLen;
1940 unsigned VecWidth = VT.getSizeInBits();
1941 if (VecWidth >= HwWidth/2 && VecWidth < HwWidth)
1942 return TargetLoweringBase::TypeWidenVector;
1943 }
1944 // Split vectors of i1 that correspond to (byte) vector pairs.
1945 if (ElemTy == MVT::i1 && VecLen == 2*HwLen)
1946 return TargetLoweringBase::TypeSplitVector;
1947 }
1948
1949 // Always widen (remaining) vectors of i1.
1950 if (ElemTy == MVT::i1)
1951 return TargetLoweringBase::TypeWidenVector;
1952
1953 return TargetLoweringBase::TypeSplitVector;
1954}
1955
1956std::pair<SDValue, int>
1957HexagonTargetLowering::getBaseAndOffset(SDValue Addr) const {
1958 if (Addr.getOpcode() == ISD::ADD) {
1959 SDValue Op1 = Addr.getOperand(1);
1960 if (auto *CN = dyn_cast<const ConstantSDNode>(Op1.getNode()))
1961 return { Addr.getOperand(0), CN->getSExtValue() };
1962 }
1963 return { Addr, 0 };
1964}
1965
1966// Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
1967// to select data from, V3 is the permutation.
1968SDValue
1969HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
1970 const {
1971 const auto *SVN = cast<ShuffleVectorSDNode>(Op);
1972 ArrayRef<int> AM = SVN->getMask();
1973 assert(AM.size() <= 8 && "Unexpected shuffle mask")((AM.size() <= 8 && "Unexpected shuffle mask") ? static_cast
<void> (0) : __assert_fail ("AM.size() <= 8 && \"Unexpected shuffle mask\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1973, __PRETTY_FUNCTION__))
;
1974 unsigned VecLen = AM.size();
1975
1976 MVT VecTy = ty(Op);
1977 assert(!Subtarget.isHVXVectorType(VecTy, true) &&((!Subtarget.isHVXVectorType(VecTy, true) && "HVX shuffles should be legal"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.isHVXVectorType(VecTy, true) && \"HVX shuffles should be legal\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1978, __PRETTY_FUNCTION__))
1978 "HVX shuffles should be legal")((!Subtarget.isHVXVectorType(VecTy, true) && "HVX shuffles should be legal"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.isHVXVectorType(VecTy, true) && \"HVX shuffles should be legal\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1978, __PRETTY_FUNCTION__))
;
1979 assert(VecTy.getSizeInBits() <= 64 && "Unexpected vector length")((VecTy.getSizeInBits() <= 64 && "Unexpected vector length"
) ? static_cast<void> (0) : __assert_fail ("VecTy.getSizeInBits() <= 64 && \"Unexpected vector length\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1979, __PRETTY_FUNCTION__))
;
1980
1981 SDValue Op0 = Op.getOperand(0);
1982 SDValue Op1 = Op.getOperand(1);
1983 const SDLoc &dl(Op);
1984
1985 // If the inputs are not the same as the output, bail. This is not an
1986 // error situation, but complicates the handling and the default expansion
1987 // (into BUILD_VECTOR) should be adequate.
1988 if (ty(Op0) != VecTy || ty(Op1) != VecTy)
1989 return SDValue();
1990
1991 // Normalize the mask so that the first non-negative index comes from
1992 // the first operand.
1993 SmallVector<int,8> Mask(AM.begin(), AM.end());
1994 unsigned F = llvm::find_if(AM, [](int M) { return M >= 0; }) - AM.data();
1995 if (F == AM.size())
1996 return DAG.getUNDEF(VecTy);
1997 if (AM[F] >= int(VecLen)) {
1998 ShuffleVectorSDNode::commuteMask(Mask);
1999 std::swap(Op0, Op1);
2000 }
2001
2002 // Express the shuffle mask in terms of bytes.
2003 SmallVector<int,8> ByteMask;
2004 unsigned ElemBytes = VecTy.getVectorElementType().getSizeInBits() / 8;
2005 for (unsigned i = 0, e = Mask.size(); i != e; ++i) {
2006 int M = Mask[i];
2007 if (M < 0) {
2008 for (unsigned j = 0; j != ElemBytes; ++j)
2009 ByteMask.push_back(-1);
2010 } else {
2011 for (unsigned j = 0; j != ElemBytes; ++j)
2012 ByteMask.push_back(M*ElemBytes + j);
2013 }
2014 }
2015 assert(ByteMask.size() <= 8)((ByteMask.size() <= 8) ? static_cast<void> (0) : __assert_fail
("ByteMask.size() <= 8", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2015, __PRETTY_FUNCTION__))
;
2016
2017 // All non-undef (non-negative) indexes are well within [0..127], so they
2018 // fit in a single byte. Build two 64-bit words:
2019 // - MaskIdx where each byte is the corresponding index (for non-negative
2020 // indexes), and 0xFF for negative indexes, and
2021 // - MaskUnd that has 0xFF for each negative index.
2022 uint64_t MaskIdx = 0;
2023 uint64_t MaskUnd = 0;
2024 for (unsigned i = 0, e = ByteMask.size(); i != e; ++i) {
2025 unsigned S = 8*i;
2026 uint64_t M = ByteMask[i] & 0xFF;
2027 if (M == 0xFF)
2028 MaskUnd |= M << S;
2029 MaskIdx |= M << S;
2030 }
2031
2032 if (ByteMask.size() == 4) {
2033 // Identity.
2034 if (MaskIdx == (0x03020100 | MaskUnd))
2035 return Op0;
2036 // Byte swap.
2037 if (MaskIdx == (0x00010203 | MaskUnd)) {
2038 SDValue T0 = DAG.getBitcast(MVT::i32, Op0);
2039 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
2040 return DAG.getBitcast(VecTy, T1);
2041 }
2042
2043 // Byte packs.
2044 SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl,
2045 typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0});
2046 if (MaskIdx == (0x06040200 | MaskUnd))
2047 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
2048 if (MaskIdx == (0x07050301 | MaskUnd))
2049 return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
2050
2051 SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl,
2052 typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1});
2053 if (MaskIdx == (0x02000604 | MaskUnd))
2054 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
2055 if (MaskIdx == (0x03010705 | MaskUnd))
2056 return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
2057 }
2058
2059 if (ByteMask.size() == 8) {
2060 // Identity.
2061 if (MaskIdx == (0x0706050403020100ull | MaskUnd))
2062 return Op0;
2063 // Byte swap.
2064 if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
2065 SDValue T0 = DAG.getBitcast(MVT::i64, Op0);
2066 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
2067 return DAG.getBitcast(VecTy, T1);
2068 }
2069
2070 // Halfword picks.
2071 if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
2072 return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
2073 if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
2074 return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
2075 if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
2076 return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
2077 if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
2078 return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
2079 if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
2080 VectorPair P = opSplit(Op0, dl, DAG);
2081 return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
2082 }
2083
2084 // Byte packs.
2085 if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
2086 return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
2087 if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
2088 return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2089 }
2090
2091 return SDValue();
2092}
2093
2094// Create a Hexagon-specific node for shifting a vector by an integer.
2095SDValue
2096HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG)
2097 const {
2098 if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode())) {
2099 if (SDValue S = BVN->getSplatValue()) {
2100 unsigned NewOpc;
2101 switch (Op.getOpcode()) {
2102 case ISD::SHL:
2103 NewOpc = HexagonISD::VASL;
2104 break;
2105 case ISD::SRA:
2106 NewOpc = HexagonISD::VASR;
2107 break;
2108 case ISD::SRL:
2109 NewOpc = HexagonISD::VLSR;
2110 break;
2111 default:
2112 llvm_unreachable("Unexpected shift opcode")::llvm::llvm_unreachable_internal("Unexpected shift opcode", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2112)
;
2113 }
2114 return DAG.getNode(NewOpc, SDLoc(Op), ty(Op), Op.getOperand(0), S);
2115 }
2116 }
2117
2118 return SDValue();
2119}
2120
2121SDValue
2122HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
2123 return getVectorShiftByInt(Op, DAG);
2124}
2125
2126SDValue
2127HexagonTargetLowering::LowerROTL(SDValue Op, SelectionDAG &DAG) const {
2128 if (isa<ConstantSDNode>(Op.getOperand(1).getNode()))
2129 return Op;
2130 return SDValue();
2131}
2132
2133SDValue
2134HexagonTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
2135 MVT ResTy = ty(Op);
2136 SDValue InpV = Op.getOperand(0);
2137 MVT InpTy = ty(InpV);
2138 assert(ResTy.getSizeInBits() == InpTy.getSizeInBits())((ResTy.getSizeInBits() == InpTy.getSizeInBits()) ? static_cast
<void> (0) : __assert_fail ("ResTy.getSizeInBits() == InpTy.getSizeInBits()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2138, __PRETTY_FUNCTION__))
;
2139 const SDLoc &dl(Op);
2140
2141 // Handle conversion from i8 to v8i1.
2142 if (ResTy == MVT::v8i1) {
2143 SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
2144 SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
2145 return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2146 }
2147
2148 return SDValue();
2149}
2150
2151bool
2152HexagonTargetLowering::getBuildVectorConstInts(ArrayRef<SDValue> Values,
2153 MVT VecTy, SelectionDAG &DAG,
2154 MutableArrayRef<ConstantInt*> Consts) const {
2155 MVT ElemTy = VecTy.getVectorElementType();
2156 unsigned ElemWidth = ElemTy.getSizeInBits();
2157 IntegerType *IntTy = IntegerType::get(*DAG.getContext(), ElemWidth);
2158 bool AllConst = true;
2159
2160 for (unsigned i = 0, e = Values.size(); i != e; ++i) {
2161 SDValue V = Values[i];
2162 if (V.isUndef()) {
2163 Consts[i] = ConstantInt::get(IntTy, 0);
2164 continue;
2165 }
2166 // Make sure to always cast to IntTy.
2167 if (auto *CN = dyn_cast<ConstantSDNode>(V.getNode())) {
2168 const ConstantInt *CI = CN->getConstantIntValue();
2169 Consts[i] = ConstantInt::get(IntTy, CI->getValue().getSExtValue());
2170 } else if (auto *CN = dyn_cast<ConstantFPSDNode>(V.getNode())) {
2171 const ConstantFP *CF = CN->getConstantFPValue();
2172 APInt A = CF->getValueAPF().bitcastToAPInt();
2173 Consts[i] = ConstantInt::get(IntTy, A.getZExtValue());
2174 } else {
2175 AllConst = false;
2176 }
2177 }
2178 return AllConst;
2179}
2180
2181SDValue
2182HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
2183 MVT VecTy, SelectionDAG &DAG) const {
2184 MVT ElemTy = VecTy.getVectorElementType();
2185 assert(VecTy.getVectorNumElements() == Elem.size())((VecTy.getVectorNumElements() == Elem.size()) ? static_cast<
void> (0) : __assert_fail ("VecTy.getVectorNumElements() == Elem.size()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2185, __PRETTY_FUNCTION__))
;
2186
2187 SmallVector<ConstantInt*,4> Consts(Elem.size());
2188 bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2189
2190 unsigned First, Num = Elem.size();
2191 for (First = 0; First != Num; ++First)
2192 if (!isUndef(Elem[First]))
2193 break;
2194 if (First == Num)
2195 return DAG.getUNDEF(VecTy);
2196
2197 if (AllConst &&
2198 llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2199 return getZero(dl, VecTy, DAG);
2200
2201 if (ElemTy == MVT::i16) {
2202 assert(Elem.size() == 2)((Elem.size() == 2) ? static_cast<void> (0) : __assert_fail
("Elem.size() == 2", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2202, __PRETTY_FUNCTION__))
;
2203 if (AllConst) {
2204 uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
2205 Consts[1]->getZExtValue() << 16;
2206 return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32));
2207 }
2208 SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32,
2209 {Elem[1], Elem[0]}, DAG);
2210 return DAG.getBitcast(MVT::v2i16, N);
2211 }
2212
2213 if (ElemTy == MVT::i8) {
2214 // First try generating a constant.
2215 if (AllConst) {
2216 int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
2217 (Consts[1]->getZExtValue() & 0xFF) << 8 |
2218 (Consts[1]->getZExtValue() & 0xFF) << 16 |
2219 Consts[2]->getZExtValue() << 24;
2220 return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
2221 }
2222
2223 // Then try splat.
2224 bool IsSplat = true;
2225 for (unsigned i = 0; i != Num; ++i) {
2226 if (i == First)
2227 continue;
2228 if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2229 continue;
2230 IsSplat = false;
2231 break;
2232 }
2233 if (IsSplat) {
2234 // Legalize the operand to VSPLAT.
2235 SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2236 return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
2237 }
2238
2239 // Generate
2240 // (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
2241 // (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
2242 assert(Elem.size() == 4)((Elem.size() == 4) ? static_cast<void> (0) : __assert_fail
("Elem.size() == 4", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2242, __PRETTY_FUNCTION__))
;
2243 SDValue Vs[4];
2244 for (unsigned i = 0; i != 4; ++i) {
2245 Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
2246 Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
2247 }
2248 SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
2249 SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2250 SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
2251 SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2252 SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
2253
2254 SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2255 return DAG.getBitcast(MVT::v4i8, R);
2256 }
2257
2258#ifndef NDEBUG
2259 dbgs() << "VecTy: " << EVT(VecTy).getEVTString() << '\n';
2260#endif
2261 llvm_unreachable("Unexpected vector element type")::llvm::llvm_unreachable_internal("Unexpected vector element type"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2261)
;
2262}
2263
2264SDValue
2265HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
2266 MVT VecTy, SelectionDAG &DAG) const {
2267 MVT ElemTy = VecTy.getVectorElementType();
2268 assert(VecTy.getVectorNumElements() == Elem.size())((VecTy.getVectorNumElements() == Elem.size()) ? static_cast<
void> (0) : __assert_fail ("VecTy.getVectorNumElements() == Elem.size()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2268, __PRETTY_FUNCTION__))
;
2269
2270 SmallVector<ConstantInt*,8> Consts(Elem.size());
2271 bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2272
2273 unsigned First, Num = Elem.size();
2274 for (First = 0; First != Num; ++First)
2275 if (!isUndef(Elem[First]))
2276 break;
2277 if (First == Num)
2278 return DAG.getUNDEF(VecTy);
2279
2280 if (AllConst &&
2281 llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
2282 return getZero(dl, VecTy, DAG);
2283
2284 // First try splat if possible.
2285 if (ElemTy == MVT::i16) {
2286 bool IsSplat = true;
2287 for (unsigned i = 0; i != Num; ++i) {
2288 if (i == First)
2289 continue;
2290 if (Elem[i] == Elem[First] || isUndef(Elem[i]))
2291 continue;
2292 IsSplat = false;
2293 break;
2294 }
2295 if (IsSplat) {
2296 // Legalize the operand to VSPLAT.
2297 SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
2298 return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
2299 }
2300 }
2301
2302 // Then try constant.
2303 if (AllConst) {
2304 uint64_t Val = 0;
2305 unsigned W = ElemTy.getSizeInBits();
2306 uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull
2307 : (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
2308 for (unsigned i = 0; i != Num; ++i)
2309 Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
2310 SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
2311 return DAG.getBitcast(VecTy, V0);
2312 }
2313
2314 // Build two 32-bit vectors and concatenate.
2315 MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
2316 SDValue L = (ElemTy == MVT::i32)
2317 ? Elem[0]
2318 : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
2319 SDValue H = (ElemTy == MVT::i32)
2320 ? Elem[1]
2321 : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG);
2322 return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L});
2323}
2324
2325SDValue
2326HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
2327 const SDLoc &dl, MVT ValTy, MVT ResTy,
2328 SelectionDAG &DAG) const {
2329 MVT VecTy = ty(VecV);
2330 assert(!ValTy.isVector() ||((!ValTy.isVector() || VecTy.getVectorElementType() == ValTy.
getVectorElementType()) ? static_cast<void> (0) : __assert_fail
("!ValTy.isVector() || VecTy.getVectorElementType() == ValTy.getVectorElementType()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2331, __PRETTY_FUNCTION__))
2331 VecTy.getVectorElementType() == ValTy.getVectorElementType())((!ValTy.isVector() || VecTy.getVectorElementType() == ValTy.
getVectorElementType()) ? static_cast<void> (0) : __assert_fail
("!ValTy.isVector() || VecTy.getVectorElementType() == ValTy.getVectorElementType()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2331, __PRETTY_FUNCTION__))
;
2332 unsigned VecWidth = VecTy.getSizeInBits();
2333 unsigned ValWidth = ValTy.getSizeInBits();
2334 unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
2335 assert((VecWidth % ElemWidth) == 0)(((VecWidth % ElemWidth) == 0) ? static_cast<void> (0) :
__assert_fail ("(VecWidth % ElemWidth) == 0", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2335, __PRETTY_FUNCTION__))
;
2336 auto *IdxN = dyn_cast<ConstantSDNode>(IdxV);
2337
2338 // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
2339 // without any coprocessors).
2340 if (ElemWidth == 1) {
2341 assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure")((VecWidth == VecTy.getVectorNumElements() && "Sanity failure"
) ? static_cast<void> (0) : __assert_fail ("VecWidth == VecTy.getVectorNumElements() && \"Sanity failure\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2341, __PRETTY_FUNCTION__))
;
2342 assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2)((VecWidth == 8 || VecWidth == 4 || VecWidth == 2) ? static_cast
<void> (0) : __assert_fail ("VecWidth == 8 || VecWidth == 4 || VecWidth == 2"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2342, __PRETTY_FUNCTION__))
;
2343 // Check if this is an extract of the lowest bit.
2344 if (IdxN) {
2345 // Extracting the lowest bit is a no-op, but it changes the type,
2346 // so it must be kept as an operation to avoid errors related to
2347 // type mismatches.
2348 if (IdxN->isNullValue() && ValTy.getSizeInBits() == 1)
2349 return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV);
2350 }
2351
2352 // If the value extracted is a single bit, use tstbit.
2353 if (ValWidth == 1) {
2354 SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2355 SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
2356 SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
2357 return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
2358 }
2359
2360 // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
2361 // a predicate register. The elements of the vector are repeated
2362 // in the register (if necessary) so that the total number is 8.
2363 // The extracted subvector will need to be expanded in such a way.
2364 unsigned Scale = VecWidth / ValWidth;
2365
2366 // Generate (p2d VecV) >> 8*Idx to move the interesting bytes to
2367 // position 0.
2368 assert(ty(IdxV) == MVT::i32)((ty(IdxV) == MVT::i32) ? static_cast<void> (0) : __assert_fail
("ty(IdxV) == MVT::i32", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2368, __PRETTY_FUNCTION__))
;
2369 unsigned VecRep = 8 / VecWidth;
2370 SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2371 DAG.getConstant(8*VecRep, dl, MVT::i32));
2372 SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2373 SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
2374 while (Scale > 1) {
2375 // The longest possible subvector is at most 32 bits, so it is always
2376 // contained in the low subregister.
2377 T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1);
2378 T1 = expandPredicate(T1, dl, DAG);
2379 Scale /= 2;
2380 }
2381
2382 return DAG.getNode(HexagonISD::D2P, dl, ResTy, T1);
2383 }
2384
2385 assert(VecWidth == 32 || VecWidth == 64)((VecWidth == 32 || VecWidth == 64) ? static_cast<void>
(0) : __assert_fail ("VecWidth == 32 || VecWidth == 64", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2385, __PRETTY_FUNCTION__))
;
2386
2387 // Cast everything to scalar integer types.
2388 MVT ScalarTy = tyScalar(VecTy);
2389 VecV = DAG.getBitcast(ScalarTy, VecV);
2390
2391 SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2392 SDValue ExtV;
2393
2394 if (IdxN) {
2395 unsigned Off = IdxN->getZExtValue() * ElemWidth;
2396 if (VecWidth == 64 && ValWidth == 32) {
2397 assert(Off == 0 || Off == 32)((Off == 0 || Off == 32) ? static_cast<void> (0) : __assert_fail
("Off == 0 || Off == 32", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2397, __PRETTY_FUNCTION__))
;
2398 unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
2399 ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV);
2400 } else if (Off == 0 && (ValWidth % 8) == 0) {
2401 ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
2402 } else {
2403 SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
2404 // The return type of EXTRACTU must be the same as the type of the
2405 // input vector.
2406 ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2407 {VecV, WidthV, OffV});
2408 }
2409 } else {
2410 if (ty(IdxV) != MVT::i32)
2411 IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2412 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2413 DAG.getConstant(ElemWidth, dl, MVT::i32));
2414 ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2415 {VecV, WidthV, OffV});
2416 }
2417
2418 // Cast ExtV to the requested result type.
2419 ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
2420 ExtV = DAG.getBitcast(ResTy, ExtV);
2421 return ExtV;
2422}
2423
2424SDValue
2425HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
2426 const SDLoc &dl, MVT ValTy,
2427 SelectionDAG &DAG) const {
2428 MVT VecTy = ty(VecV);
2429 if (VecTy.getVectorElementType() == MVT::i1) {
2430 MVT ValTy = ty(ValV);
2431 assert(ValTy.getVectorElementType() == MVT::i1)((ValTy.getVectorElementType() == MVT::i1) ? static_cast<void
> (0) : __assert_fail ("ValTy.getVectorElementType() == MVT::i1"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2431, __PRETTY_FUNCTION__))
;
2432 SDValue ValR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV);
2433 unsigned VecLen = VecTy.getVectorNumElements();
2434 unsigned Scale = VecLen / ValTy.getVectorNumElements();
2435 assert(Scale > 1)((Scale > 1) ? static_cast<void> (0) : __assert_fail
("Scale > 1", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2435, __PRETTY_FUNCTION__))
;
2436
2437 for (unsigned R = Scale; R > 1; R /= 2) {
2438 ValR = contractPredicate(ValR, dl, DAG);
2439 ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2440 DAG.getUNDEF(MVT::i32), ValR);
2441 }
2442 // The longest possible subvector is at most 32 bits, so it is always
2443 // contained in the low subregister.
2444 ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR);
2445
2446 unsigned ValBytes = 64 / Scale;
2447 SDValue Width = DAG.getConstant(ValBytes*8, dl, MVT::i32);
2448 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
2449 DAG.getConstant(8, dl, MVT::i32));
2450 SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2451 SDValue Ins = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32,
2452 {VecR, ValR, Width, Idx});
2453 return DAG.getNode(HexagonISD::D2P, dl, VecTy, Ins);
2454 }
2455
2456 unsigned VecWidth = VecTy.getSizeInBits();
2457 unsigned ValWidth = ValTy.getSizeInBits();
2458 assert(VecWidth == 32 || VecWidth == 64)((VecWidth == 32 || VecWidth == 64) ? static_cast<void>
(0) : __assert_fail ("VecWidth == 32 || VecWidth == 64", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2458, __PRETTY_FUNCTION__))
;
2459 assert((VecWidth % ValWidth) == 0)(((VecWidth % ValWidth) == 0) ? static_cast<void> (0) :
__assert_fail ("(VecWidth % ValWidth) == 0", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2459, __PRETTY_FUNCTION__))
;
2460
2461 // Cast everything to scalar integer types.
2462 MVT ScalarTy = MVT::getIntegerVT(VecWidth);
2463 // The actual type of ValV may be different than ValTy (which is related
2464 // to the vector type).
2465 unsigned VW = ty(ValV).getSizeInBits();
2466 ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
2467 VecV = DAG.getBitcast(ScalarTy, VecV);
2468 if (VW != VecWidth)
2469 ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);
2470
2471 SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
2472 SDValue InsV;
2473
2474 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
2475 unsigned W = C->getZExtValue() * ValWidth;
2476 SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
2477 InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2478 {VecV, ValV, WidthV, OffV});
2479 } else {
2480 if (ty(IdxV) != MVT::i32)
2481 IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
2482 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
2483 InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
2484 {VecV, ValV, WidthV, OffV});
2485 }
2486
2487 return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
2488}
2489
2490SDValue
2491HexagonTargetLowering::expandPredicate(SDValue Vec32, const SDLoc &dl,
2492 SelectionDAG &DAG) const {
2493 assert(ty(Vec32).getSizeInBits() == 32)((ty(Vec32).getSizeInBits() == 32) ? static_cast<void> (
0) : __assert_fail ("ty(Vec32).getSizeInBits() == 32", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2493, __PRETTY_FUNCTION__))
;
2494 if (isUndef(Vec32))
2495 return DAG.getUNDEF(MVT::i64);
2496 return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
2497}
2498
2499SDValue
2500HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl,
2501 SelectionDAG &DAG) const {
2502 assert(ty(Vec64).getSizeInBits() == 64)((ty(Vec64).getSizeInBits() == 64) ? static_cast<void> (
0) : __assert_fail ("ty(Vec64).getSizeInBits() == 64", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2502, __PRETTY_FUNCTION__))
;
2503 if (isUndef(Vec64))
2504 return DAG.getUNDEF(MVT::i32);
2505 return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
2506}
2507
2508SDValue
2509HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
2510 const {
2511 if (Ty.isVector()) {
2512 assert(Ty.isInteger() && "Only integer vectors are supported here")((Ty.isInteger() && "Only integer vectors are supported here"
) ? static_cast<void> (0) : __assert_fail ("Ty.isInteger() && \"Only integer vectors are supported here\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2512, __PRETTY_FUNCTION__))
;
2513 unsigned W = Ty.getSizeInBits();
2514 if (W <= 64)
2515 return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W)));
2516 return DAG.getNode(HexagonISD::VZERO, dl, Ty);
2517 }
2518
2519 if (Ty.isInteger())
2520 return DAG.getConstant(0, dl, Ty);
2521 if (Ty.isFloatingPoint())
2522 return DAG.getConstantFP(0.0, dl, Ty);
2523 llvm_unreachable("Invalid type for zero")::llvm::llvm_unreachable_internal("Invalid type for zero", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2523)
;
2524}
2525
2526SDValue
2527HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
2528 MVT VecTy = ty(Op);
2529 unsigned BW = VecTy.getSizeInBits();
2530 const SDLoc &dl(Op);
2531 SmallVector<SDValue,8> Ops;
2532 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
2533 Ops.push_back(Op.getOperand(i));
2534
2535 if (BW == 32)
2536 return buildVector32(Ops, dl, VecTy, DAG);
2537 if (BW == 64)
2538 return buildVector64(Ops, dl, VecTy, DAG);
2539
2540 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2541 // Check if this is a special case or all-0 or all-1.
2542 bool All0 = true, All1 = true;
2543 for (SDValue P : Ops) {
2544 auto *CN = dyn_cast<ConstantSDNode>(P.getNode());
2545 if (CN == nullptr) {
2546 All0 = All1 = false;
2547 break;
2548 }
2549 uint32_t C = CN->getZExtValue();
2550 All0 &= (C == 0);
2551 All1 &= (C == 1);
2552 }
2553 if (All0)
2554 return DAG.getNode(HexagonISD::PFALSE, dl, VecTy);
2555 if (All1)
2556 return DAG.getNode(HexagonISD::PTRUE, dl, VecTy);
2557
2558 // For each i1 element in the resulting predicate register, put 1
2559 // shifted by the index of the element into a general-purpose register,
2560 // then or them together and transfer it back into a predicate register.
2561 SDValue Rs[8];
2562 SDValue Z = getZero(dl, MVT::i32, DAG);
2563 // Always produce 8 bits, repeat inputs if necessary.
2564 unsigned Rep = 8 / VecTy.getVectorNumElements();
2565 for (unsigned i = 0; i != 8; ++i) {
2566 SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32);
2567 Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
2568 }
2569 for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
2570 for (unsigned i = 0, e = A.size()/2; i != e; ++i)
2571 Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
2572 }
2573 // Move the value directly to a predicate register.
2574 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
2575 }
2576
2577 return SDValue();
2578}
2579
2580SDValue
2581HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
2582 SelectionDAG &DAG) const {
2583 MVT VecTy = ty(Op);
2584 const SDLoc &dl(Op);
2585 if (VecTy.getSizeInBits() == 64) {
2586 assert(Op.getNumOperands() == 2)((Op.getNumOperands() == 2) ? static_cast<void> (0) : __assert_fail
("Op.getNumOperands() == 2", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2586, __PRETTY_FUNCTION__))
;
2587 return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1),
2588 Op.getOperand(0));
2589 }
2590
2591 MVT ElemTy = VecTy.getVectorElementType();
2592 if (ElemTy == MVT::i1) {
2593 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1)((VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1
) ? static_cast<void> (0) : __assert_fail ("VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2593, __PRETTY_FUNCTION__))
;
2594 MVT OpTy = ty(Op.getOperand(0));
2595 // Scale is how many times the operands need to be contracted to match
2596 // the representation in the target register.
2597 unsigned Scale = VecTy.getVectorNumElements() / OpTy.getVectorNumElements();
2598 assert(Scale == Op.getNumOperands() && Scale > 1)((Scale == Op.getNumOperands() && Scale > 1) ? static_cast
<void> (0) : __assert_fail ("Scale == Op.getNumOperands() && Scale > 1"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2598, __PRETTY_FUNCTION__))
;
2599
2600 // First, convert all bool vectors to integers, then generate pairwise
2601 // inserts to form values of doubled length. Up until there are only
2602 // two values left to concatenate, all of these values will fit in a
2603 // 32-bit integer, so keep them as i32 to use 32-bit inserts.
2604 SmallVector<SDValue,4> Words[2];
2605 unsigned IdxW = 0;
2606
2607 for (SDValue P : Op.getNode()->op_values()) {
2608 SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P);
2609 for (unsigned R = Scale; R > 1; R /= 2) {
2610 W = contractPredicate(W, dl, DAG);
2611 W = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2612 DAG.getUNDEF(MVT::i32), W);
2613 }
2614 W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W);
2615 Words[IdxW].push_back(W);
2616 }
2617
2618 while (Scale > 2) {
2619 SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32);
2620 Words[IdxW ^ 1].clear();
2621
2622 for (unsigned i = 0, e = Words[IdxW].size(); i != e; i += 2) {
2623 SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
2624 // Insert W1 into W0 right next to the significant bits of W0.
2625 SDValue T = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32,
2626 {W0, W1, WidthV, WidthV});
2627 Words[IdxW ^ 1].push_back(T);
2628 }
2629 IdxW ^= 1;
2630 Scale /= 2;
2631 }
2632
2633 // Another sanity check. At this point there should only be two words
2634 // left, and Scale should be 2.
2635 assert(Scale == 2 && Words[IdxW].size() == 2)((Scale == 2 && Words[IdxW].size() == 2) ? static_cast
<void> (0) : __assert_fail ("Scale == 2 && Words[IdxW].size() == 2"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2635, __PRETTY_FUNCTION__))
;
2636
2637 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
2638 Words[IdxW][1], Words[IdxW][0]);
2639 return DAG.getNode(HexagonISD::D2P, dl, VecTy, WW);
2640 }
2641
2642 return SDValue();
2643}
2644
2645SDValue
2646HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
2647 SelectionDAG &DAG) const {
2648 SDValue Vec = Op.getOperand(0);
2649 MVT ElemTy = ty(Vec).getVectorElementType();
2650 return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
2651}
2652
2653SDValue
2654HexagonTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
2655 SelectionDAG &DAG) const {
2656 return extractVector(Op.getOperand(0), Op.getOperand(1), SDLoc(Op),
2657 ty(Op), ty(Op), DAG);
2658}
2659
2660SDValue
2661HexagonTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
2662 SelectionDAG &DAG) const {
2663 return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
2664 SDLoc(Op), ty(Op).getVectorElementType(), DAG);
2665}
2666
2667SDValue
2668HexagonTargetLowering::LowerINSERT_SUBVECTOR(SDValue Op,
2669 SelectionDAG &DAG) const {
2670 SDValue ValV = Op.getOperand(1);
2671 return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
2672 SDLoc(Op), ty(ValV), DAG);
2673}
2674
2675bool
2676HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
2677 // Assuming the caller does not have either a signext or zeroext modifier, and
2678 // only one value is accepted, any reasonable truncation is allowed.
2679 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2680 return false;
2681
2682 // FIXME: in principle up to 64-bit could be made safe, but it would be very
2683 // fragile at the moment: any support for multiple value returns would be
2684 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2685 return Ty1->getPrimitiveSizeInBits() <= 32;
2686}
2687
2688SDValue
2689HexagonTargetLowering::LowerLoad(SDValue Op, SelectionDAG &DAG) const {
2690 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2691 unsigned ClaimAlign = LN->getAlignment();
2692 validateConstPtrAlignment(LN->getBasePtr(), SDLoc(Op), ClaimAlign);
2693 // Call LowerUnalignedLoad for all loads, it recognizes loads that
2694 // don't need extra aligning.
2695 return LowerUnalignedLoad(Op, DAG);
2696}
2697
2698SDValue
2699HexagonTargetLowering::LowerStore(SDValue Op, SelectionDAG &DAG) const {
2700 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
2701 unsigned ClaimAlign = SN->getAlignment();
2702 SDValue Ptr = SN->getBasePtr();
2703 const SDLoc &dl(Op);
2704 validateConstPtrAlignment(Ptr, dl, ClaimAlign);
2705
2706 MVT StoreTy = SN->getMemoryVT().getSimpleVT();
2707 unsigned NeedAlign = Subtarget.getTypeAlignment(StoreTy);
2708 if (ClaimAlign < NeedAlign)
2709 return expandUnalignedStore(SN, DAG);
2710 return Op;
2711}
2712
2713SDValue
2714HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG)
2715 const {
2716 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
2717 MVT LoadTy = ty(Op);
2718 unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy);
2719 unsigned HaveAlign = LN->getAlignment();
2720 if (HaveAlign >= NeedAlign)
2721 return Op;
2722
2723 const SDLoc &dl(Op);
2724 const DataLayout &DL = DAG.getDataLayout();
2725 LLVMContext &Ctx = *DAG.getContext();
2726
2727 // If the load aligning is disabled or the load can be broken up into two
2728 // smaller legal loads, do the default (target-independent) expansion.
2729 bool DoDefault = false;
2730 // Handle it in the default way if this is an indexed load.
2731 if (!LN->isUnindexed())
2732 DoDefault = true;
2733
2734 if (!AlignLoads) {
2735 if (allowsMemoryAccessForAlignment(Ctx, DL, LN->getMemoryVT(),
2736 *LN->getMemOperand()))
2737 return Op;
2738 DoDefault = true;
2739 }
2740 if (!DoDefault && (2 * HaveAlign) == NeedAlign) {
2741 // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)".
2742 MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign)
2743 : MVT::getVectorVT(MVT::i8, HaveAlign);
2744 DoDefault =
2745 allowsMemoryAccessForAlignment(Ctx, DL, PartTy, *LN->getMemOperand());
2746 }
2747 if (DoDefault) {
2748 std::pair<SDValue, SDValue> P = expandUnalignedLoad(LN, DAG);
2749 return DAG.getMergeValues({P.first, P.second}, dl);
2750 }
2751
2752 // The code below generates two loads, both aligned as NeedAlign, and
2753 // with the distance of NeedAlign between them. For that to cover the
2754 // bits that need to be loaded (and without overlapping), the size of
2755 // the loads should be equal to NeedAlign. This is true for all loadable
2756 // types, but add an assertion in case something changes in the future.
2757 assert(LoadTy.getSizeInBits() == 8*NeedAlign)((LoadTy.getSizeInBits() == 8*NeedAlign) ? static_cast<void
> (0) : __assert_fail ("LoadTy.getSizeInBits() == 8*NeedAlign"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2757, __PRETTY_FUNCTION__))
;
2758
2759 unsigned LoadLen = NeedAlign;
2760 SDValue Base = LN->getBasePtr();
2761 SDValue Chain = LN->getChain();
2762 auto BO = getBaseAndOffset(Base);
2763 unsigned BaseOpc = BO.first.getOpcode();
2764 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0)
2765 return Op;
2766
2767 if (BO.second % LoadLen != 0) {
2768 BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
2769 DAG.getConstant(BO.second % LoadLen, dl, MVT::i32));
2770 BO.second -= BO.second % LoadLen;
2771 }
2772 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
2773 ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
2774 DAG.getConstant(NeedAlign, dl, MVT::i32))
2775 : BO.first;
2776 SDValue Base0 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second, dl);
2777 SDValue Base1 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second+LoadLen, dl);
2778
2779 MachineMemOperand *WideMMO = nullptr;
2780 if (MachineMemOperand *MMO = LN->getMemOperand()) {
2781 MachineFunction &MF = DAG.getMachineFunction();
2782 WideMMO = MF.getMachineMemOperand(MMO->getPointerInfo(), MMO->getFlags(),
2783 2*LoadLen, LoadLen, MMO->getAAInfo(), MMO->getRanges(),
2784 MMO->getSyncScopeID(), MMO->getOrdering(),
2785 MMO->getFailureOrdering());
2786 }
2787
2788 SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO);
2789 SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO);
2790
2791 SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy,
2792 {Load1, Load0, BaseNoOff.getOperand(0)});
2793 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2794 Load0.getValue(1), Load1.getValue(1));
2795 SDValue M = DAG.getMergeValues({Aligned, NewChain}, dl);
2796 return M;
2797}
2798
2799SDValue
2800HexagonTargetLowering::LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const {
2801 SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
2802 auto *CY = dyn_cast<ConstantSDNode>(Y);
2803 if (!CY)
2804 return SDValue();
2805
2806 const SDLoc &dl(Op);
2807 SDVTList VTs = Op.getNode()->getVTList();
2808 assert(VTs.NumVTs == 2)((VTs.NumVTs == 2) ? static_cast<void> (0) : __assert_fail
("VTs.NumVTs == 2", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2808, __PRETTY_FUNCTION__))
;
2809 assert(VTs.VTs[1] == MVT::i1)((VTs.VTs[1] == MVT::i1) ? static_cast<void> (0) : __assert_fail
("VTs.VTs[1] == MVT::i1", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2809, __PRETTY_FUNCTION__))
;
2810 unsigned Opc = Op.getOpcode();
2811
2812 if (CY) {
2813 uint32_t VY = CY->getZExtValue();
2814 assert(VY != 0 && "This should have been folded")((VY != 0 && "This should have been folded") ? static_cast
<void> (0) : __assert_fail ("VY != 0 && \"This should have been folded\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2814, __PRETTY_FUNCTION__))
;
2815 // X +/- 1
2816 if (VY != 1)
2817 return SDValue();
2818
2819 if (Opc == ISD::UADDO) {
2820 SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y});
2821 SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, getZero(dl, ty(Op), DAG),
2822 ISD::SETEQ);
2823 return DAG.getMergeValues({Op, Ov}, dl);
2824 }
2825 if (Opc == ISD::USUBO) {
2826 SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});
2827 SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op,
2828 DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ);
2829 return DAG.getMergeValues({Op, Ov}, dl);
2830 }
2831 }
2832
2833 return SDValue();
2834}
2835
2836SDValue
2837HexagonTargetLowering::LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const {
2838 const SDLoc &dl(Op);
2839 unsigned Opc = Op.getOpcode();
2840 SDValue X = Op.getOperand(0), Y = Op.getOperand(1), C = Op.getOperand(2);
2841
2842 if (Opc == ISD::ADDCARRY)
2843 return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
2844 { X, Y, C });
2845
2846 EVT CarryTy = C.getValueType();
2847 SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(),
2848 { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
2849 SDValue Out[] = { SubC.getValue(0),
2850 DAG.getLogicalNOT(dl, SubC.getValue(1), CarryTy) };
2851 return DAG.getMergeValues(Out, dl);
2852}
2853
2854SDValue
2855HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
2856 SDValue Chain = Op.getOperand(0);
2857 SDValue Offset = Op.getOperand(1);
2858 SDValue Handler = Op.getOperand(2);
2859 SDLoc dl(Op);
2860 auto PtrVT = getPointerTy(DAG.getDataLayout());
2861
2862 // Mark function as containing a call to EH_RETURN.
2863 HexagonMachineFunctionInfo *FuncInfo =
2864 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
2865 FuncInfo->setHasEHReturn();
2866
2867 unsigned OffsetReg = Hexagon::R28;
2868
2869 SDValue StoreAddr =
2870 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2871 DAG.getIntPtrConstant(4, dl));
2872 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2873 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2874
2875 // Not needed we already use it as explict input to EH_RETURN.
2876 // MF.getRegInfo().addLiveOut(OffsetReg);
2877
2878 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2879}
2880
2881SDValue
2882HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2883 unsigned Opc = Op.getOpcode();
2884
2885 // Handle INLINEASM first.
2886 if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
1
Assuming 'Opc' is not equal to INLINEASM
2
Assuming 'Opc' is not equal to INLINEASM_BR
3
Taking false branch
2887 return LowerINLINEASM(Op, DAG);
2888
2889 if (isHvxOperation(Op)) {
4
Assuming the condition is false
5
Taking false branch
2890 // If HVX lowering returns nothing, try the default lowering.
2891 if (SDValue V = LowerHvxOperation(Op, DAG))
2892 return V;
2893 }
2894
2895 switch (Opc) {
6
Control jumps to 'case SETCC:' at line 2933
2896 default:
2897#ifndef NDEBUG
2898 Op.getNode()->dumpr(&DAG);
2899 if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2900 errs() << "Error: check for a non-legal type in this operation\n";
2901#endif
2902 llvm_unreachable("Should not custom lower this!")::llvm::llvm_unreachable_internal("Should not custom lower this!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2902)
;
2903 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2904 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
2905 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
2906 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
2907 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2908 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2909 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2910 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
2911 case ISD::LOAD: return LowerLoad(Op, DAG);
2912 case ISD::STORE: return LowerStore(Op, DAG);
2913 case ISD::UADDO:
2914 case ISD::USUBO: return LowerUAddSubO(Op, DAG);
2915 case ISD::ADDCARRY:
2916 case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG);
2917 case ISD::SRA:
2918 case ISD::SHL:
2919 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2920 case ISD::ROTL: return LowerROTL(Op, DAG);
2921 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2922 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2923 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2924 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2925 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2926 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2927 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2928 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2929 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2930 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2931 case ISD::VASTART: return LowerVASTART(Op, DAG);
2932 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2933 case ISD::SETCC: return LowerSETCC(Op, DAG);
7
Calling 'HexagonTargetLowering::LowerSETCC'
2934 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2935 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2936 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
2937 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
2938 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
2939 break;
2940 }
2941
2942 return SDValue();
2943}
2944
2945void
2946HexagonTargetLowering::LowerOperationWrapper(SDNode *N,
2947 SmallVectorImpl<SDValue> &Results,
2948 SelectionDAG &DAG) const {
2949 // We are only custom-lowering stores to verify the alignment of the
2950 // address if it is a compile-time constant. Since a store can be modified
2951 // during type-legalization (the value being stored may need legalization),
2952 // return empty Results here to indicate that we don't really make any
2953 // changes in the custom lowering.
2954 if (N->getOpcode() != ISD::STORE)
2955 return TargetLowering::LowerOperationWrapper(N, Results, DAG);
2956}
2957
2958void
2959HexagonTargetLowering::ReplaceNodeResults(SDNode *N,
2960 SmallVectorImpl<SDValue> &Results,
2961 SelectionDAG &DAG) const {
2962 const SDLoc &dl(N);
2963 switch (N->getOpcode()) {
2964 case ISD::SRL:
2965 case ISD::SRA:
2966 case ISD::SHL:
2967 return;
2968 case ISD::BITCAST:
2969 // Handle a bitcast from v8i1 to i8.
2970 if (N->getValueType(0) == MVT::i8) {
2971 SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
2972 N->getOperand(0), DAG);
2973 SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8);
2974 Results.push_back(T);
2975 }
2976 break;
2977 }
2978}
2979
2980SDValue
2981HexagonTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
2982 const {
2983 SDValue Op(N, 0);
2984 if (isHvxOperation(Op)) {
2985 if (SDValue V = PerformHvxDAGCombine(N, DCI))
2986 return V;
2987 return SDValue();
2988 }
2989
2990 const SDLoc &dl(Op);
2991 unsigned Opc = Op.getOpcode();
2992
2993 if (Opc == HexagonISD::P2D) {
2994 SDValue P = Op.getOperand(0);
2995 switch (P.getOpcode()) {
2996 case HexagonISD::PTRUE:
2997 return DCI.DAG.getConstant(-1, dl, ty(Op));
2998 case HexagonISD::PFALSE:
2999 return getZero(dl, ty(Op), DCI.DAG);
3000 default:
3001 break;
3002 }
3003 } else if (Opc == ISD::VSELECT) {
3004 // This is pretty much duplicated in HexagonISelLoweringHVX...
3005 //
3006 // (vselect (xor x, ptrue), v0, v1) -> (vselect x, v1, v0)
3007 SDValue Cond = Op.getOperand(0);
3008 if (Cond->getOpcode() == ISD::XOR) {
3009 SDValue C0 = Cond.getOperand(0), C1 = Cond.getOperand(1);
3010 if (C1->getOpcode() == HexagonISD::PTRUE) {
3011 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
3012 Op.getOperand(2), Op.getOperand(1));
3013 return VSel;
3014 }
3015 }
3016 }
3017
3018 return SDValue();
3019}
3020
3021/// Returns relocation base for the given PIC jumptable.
3022SDValue
3023HexagonTargetLowering::getPICJumpTableRelocBase(SDValue Table,
3024 SelectionDAG &DAG) const {
3025 int Idx = cast<JumpTableSDNode>(Table)->getIndex();
3026 EVT VT = Table.getValueType();
3027 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
3028 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
3029}
3030
3031//===----------------------------------------------------------------------===//
3032// Inline Assembly Support
3033//===----------------------------------------------------------------------===//
3034
3035TargetLowering::ConstraintType
3036HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
3037 if (Constraint.size() == 1) {
3038 switch (Constraint[0]) {
3039 case 'q':
3040 case 'v':
3041 if (Subtarget.useHVXOps())
3042 return C_RegisterClass;
3043 break;
3044 case 'a':
3045 return C_RegisterClass;
3046 default:
3047 break;
3048 }
3049 }
3050 return TargetLowering::getConstraintType(Constraint);
3051}
3052
3053std::pair<unsigned, const TargetRegisterClass*>
3054HexagonTargetLowering::getRegForInlineAsmConstraint(
3055 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
3056
3057 if (Constraint.size() == 1) {
3058 switch (Constraint[0]) {
3059 case 'r': // R0-R31
3060 switch (VT.SimpleTy) {
3061 default:
3062 return {0u, nullptr};
3063 case MVT::i1:
3064 case MVT::i8:
3065 case MVT::i16:
3066 case MVT::i32:
3067 case MVT::f32:
3068 return {0u, &Hexagon::IntRegsRegClass};
3069 case MVT::i64:
3070 case MVT::f64:
3071 return {0u, &Hexagon::DoubleRegsRegClass};
3072 }
3073 break;
3074 case 'a': // M0-M1
3075 if (VT != MVT::i32)
3076 return {0u, nullptr};
3077 return {0u, &Hexagon::ModRegsRegClass};
3078 case 'q': // q0-q3
3079 switch (VT.getSizeInBits()) {
3080 default:
3081 return {0u, nullptr};
3082 case 512:
3083 case 1024:
3084 return {0u, &Hexagon::HvxQRRegClass};
3085 }
3086 break;
3087 case 'v': // V0-V31
3088 switch (VT.getSizeInBits()) {
3089 default:
3090 return {0u, nullptr};
3091 case 512:
3092 return {0u, &Hexagon::HvxVRRegClass};
3093 case 1024:
3094 if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps())
3095 return {0u, &Hexagon::HvxVRRegClass};
3096 return {0u, &Hexagon::HvxWRRegClass};
3097 case 2048:
3098 return {0u, &Hexagon::HvxWRRegClass};
3099 }
3100 break;
3101 default:
3102 return {0u, nullptr};
3103 }
3104 }
3105
3106 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3107}
3108
3109/// isFPImmLegal - Returns true if the target can instruction select the
3110/// specified FP immediate natively. If false, the legalizer will
3111/// materialize the FP immediate as a load from a constant pool.
3112bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
3113 bool ForCodeSize) const {
3114 return true;
3115}
3116
3117/// isLegalAddressingMode - Return true if the addressing mode represented by
3118/// AM is legal for this target, for a load/store of the specified type.
3119bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3120 const AddrMode &AM, Type *Ty,
3121 unsigned AS, Instruction *I) const {
3122 if (Ty->isSized()) {
3123 // When LSR detects uses of the same base address to access different
3124 // types (e.g. unions), it will assume a conservative type for these
3125 // uses:
3126 // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3127 // The type Ty passed here would then be "void". Skip the alignment
3128 // checks, but do not return false right away, since that confuses
3129 // LSR into crashing.
3130 unsigned A = DL.getABITypeAlignment(Ty);
3131 // The base offset must be a multiple of the alignment.
3132 if ((AM.BaseOffs % A) != 0)
3133 return false;
3134 // The shifted offset must fit in 11 bits.
3135 if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
3136 return false;
3137 }
3138
3139 // No global is ever allowed as a base.
3140 if (AM.BaseGV)
3141 return false;
3142
3143 int Scale = AM.Scale;
3144 if (Scale < 0)
3145 Scale = -Scale;
3146 switch (Scale) {
3147 case 0: // No scale reg, "r+i", "r", or just "i".
3148 break;
3149 default: // No scaled addressing mode.
3150 return false;
3151 }
3152 return true;
3153}
3154
3155/// Return true if folding a constant offset with the given GlobalAddress is
3156/// legal. It is frequently not legal in PIC relocation models.
3157bool HexagonTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA)
3158 const {
3159 return HTM.getRelocationModel() == Reloc::Static;
3160}
3161
3162/// isLegalICmpImmediate - Return true if the specified immediate is legal
3163/// icmp immediate, that is the target has icmp instructions which can compare
3164/// a register against the immediate without having to materialize the
3165/// immediate into a register.
3166bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
3167 return Imm >= -512 && Imm <= 511;
3168}
3169
3170/// IsEligibleForTailCallOptimization - Check whether the call is eligible
3171/// for tail call optimization. Targets which want to do tail call
3172/// optimization should implement this function.
3173bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
3174 SDValue Callee,
3175 CallingConv::ID CalleeCC,
3176 bool IsVarArg,
3177 bool IsCalleeStructRet,
3178 bool IsCallerStructRet,
3179 const SmallVectorImpl<ISD::OutputArg> &Outs,
3180 const SmallVectorImpl<SDValue> &OutVals,
3181 const SmallVectorImpl<ISD::InputArg> &Ins,
3182 SelectionDAG& DAG) const {
3183 const Function &CallerF = DAG.getMachineFunction().getFunction();
3184 CallingConv::ID CallerCC = CallerF.getCallingConv();
3185 bool CCMatch = CallerCC == CalleeCC;
3186
3187 // ***************************************************************************
3188 // Look for obvious safe cases to perform tail call optimization that do not
3189 // require ABI changes.
3190 // ***************************************************************************
3191
3192 // If this is a tail call via a function pointer, then don't do it!
3193 if (!isa<GlobalAddressSDNode>(Callee) &&
3194 !isa<ExternalSymbolSDNode>(Callee)) {
3195 return false;
3196 }
3197
3198 // Do not optimize if the calling conventions do not match and the conventions
3199 // used are not C or Fast.
3200 if (!CCMatch) {
3201 bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3202 bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3203 // If R & E, then ok.
3204 if (!R || !E)
3205 return false;
3206 }
3207
3208 // Do not tail call optimize vararg calls.
3209 if (IsVarArg)
3210 return false;
3211
3212 // Also avoid tail call optimization if either caller or callee uses struct
3213 // return semantics.
3214 if (IsCalleeStructRet || IsCallerStructRet)
3215 return false;
3216
3217 // In addition to the cases above, we also disable Tail Call Optimization if
3218 // the calling convention code that at least one outgoing argument needs to
3219 // go on the stack. We cannot check that here because at this point that
3220 // information is not available.
3221 return true;
3222}
3223
3224/// Returns the target specific optimal type for load and store operations as
3225/// a result of memset, memcpy, and memmove lowering.
3226///
3227/// If DstAlign is zero that means it's safe to destination alignment can
3228/// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3229/// a need to check it against alignment requirement, probably because the
3230/// source does not need to be loaded. If 'IsMemset' is true, that means it's
3231/// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3232/// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3233/// does not need to be loaded. It returns EVT::Other if the type should be
3234/// determined using generic target-independent logic.
3235EVT HexagonTargetLowering::getOptimalMemOpType(uint64_t Size,
3236 unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3237 bool MemcpyStrSrc, const AttributeList &FuncAttributes) const {
3238
3239 auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3240 return (GivenA % MinA) == 0;
3241 };
3242
3243 if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3244 return MVT::i64;
3245 if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3246 return MVT::i32;
3247 if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3248 return MVT::i16;
3249
3250 return MVT::Other;
3251}
3252
3253bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(
3254 EVT VT, unsigned AS, unsigned Align, MachineMemOperand::Flags Flags,
3255 bool *Fast) const {
3256 if (Fast)
3257 *Fast = false;
3258 return Subtarget.isHVXVectorType(VT.getSimpleVT());
3259}
3260
3261std::pair<const TargetRegisterClass*, uint8_t>
3262HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3263 MVT VT) const {
3264 if (Subtarget.isHVXVectorType(VT, true)) {
3265 unsigned BitWidth = VT.getSizeInBits();
3266 unsigned VecWidth = Subtarget.getVectorLength() * 8;
3267
3268 if (VT.getVectorElementType() == MVT::i1)
3269 return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3270 if (BitWidth == VecWidth)
3271 return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3272 assert(BitWidth == 2 * VecWidth)((BitWidth == 2 * VecWidth) ? static_cast<void> (0) : __assert_fail
("BitWidth == 2 * VecWidth", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3272, __PRETTY_FUNCTION__))
;
3273 return std::make_pair(&Hexagon::HvxWRRegClass, 1);
3274 }
3275
3276 return TargetLowering::findRepresentativeClass(TRI, VT);
3277}
3278
3279bool HexagonTargetLowering::shouldReduceLoadWidth(SDNode *Load,
3280 ISD::LoadExtType ExtTy, EVT NewVT) const {
3281 // TODO: This may be worth removing. Check regression tests for diffs.
3282 if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
3283 return false;
3284
3285 auto *L = cast<LoadSDNode>(Load);
3286 std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
3287 // Small-data object, do not shrink.
3288 if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
3289 return false;
3290 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(BO.first)) {
3291 auto &HTM = static_cast<const HexagonTargetMachine&>(getTargetMachine());
3292 const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
3293 return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
3294 }
3295 return true;
3296}
3297
3298Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
3299 AtomicOrdering Ord) const {
3300 BasicBlock *BB = Builder.GetInsertBlock();
3301 Module *M = BB->getParent()->getParent();
3302 auto PT = cast<PointerType>(Addr->getType());
3303 Type *Ty = PT->getElementType();
3304 unsigned SZ = Ty->getPrimitiveSizeInBits();
3305 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported")(((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported"
) ? static_cast<void> (0) : __assert_fail ("(SZ == 32 || SZ == 64) && \"Only 32/64-bit atomic loads supported\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3305, __PRETTY_FUNCTION__))
;
3306 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3307 : Intrinsic::hexagon_L4_loadd_locked;
3308 Function *Fn = Intrinsic::getDeclaration(M, IntID);
3309
3310 PointerType *NewPtrTy
3311 = Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace());
3312 Addr = Builder.CreateBitCast(Addr, NewPtrTy);
3313
3314 Value *Call = Builder.CreateCall(Fn, Addr, "larx");
3315
3316 return Builder.CreateBitCast(Call, Ty);
3317}
3318
3319/// Perform a store-conditional operation to Addr. Return the status of the
3320/// store. This should be 0 if the store succeeded, non-zero otherwise.
3321Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
3322 Value *Val, Value *Addr, AtomicOrdering Ord) const {
3323 BasicBlock *BB = Builder.GetInsertBlock();
3324 Module *M = BB->getParent()->getParent();
3325 Type *Ty = Val->getType();
3326 unsigned SZ = Ty->getPrimitiveSizeInBits();
3327
3328 Type *CastTy = Builder.getIntNTy(SZ);
3329 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported")(((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported"
) ? static_cast<void> (0) : __assert_fail ("(SZ == 32 || SZ == 64) && \"Only 32/64-bit atomic stores supported\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3329, __PRETTY_FUNCTION__))
;
3330 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3331 : Intrinsic::hexagon_S4_stored_locked;
3332 Function *Fn = Intrinsic::getDeclaration(M, IntID);
3333
3334 unsigned AS = Addr->getType()->getPointerAddressSpace();
3335 Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
3336 Val = Builder.CreateBitCast(Val, CastTy);
3337
3338 Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3339 Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3340 Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3341 return Ext;
3342}
3343
3344TargetLowering::AtomicExpansionKind
3345HexagonTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
3346 // Do not expand loads and stores that don't exceed 64 bits.
3347 return LI->getType()->getPrimitiveSizeInBits() > 64
3348 ? AtomicExpansionKind::LLOnly
3349 : AtomicExpansionKind::None;
3350}
3351
3352bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
3353 // Do not expand loads and stores that don't exceed 64 bits.
3354 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3355}
3356
3357TargetLowering::AtomicExpansionKind
3358HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR(
3359 AtomicCmpXchgInst *AI) const {
3360 const DataLayout &DL = AI->getModule()->getDataLayout();
3361 unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3362 if (Size >= 4 && Size <= 8)
3363 return AtomicExpansionKind::LLSC;
3364 return AtomicExpansionKind::None;
3365}

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/Constants.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Instruction.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/Metadata.h"
39#include "llvm/IR/Operator.h"
40#include "llvm/Support/AlignOf.h"
41#include "llvm/Support/AtomicOrdering.h"
42#include "llvm/Support/Casting.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MachineValueType.h"
45#include "llvm/Support/TypeSize.h"
46#include <algorithm>
47#include <cassert>
48#include <climits>
49#include <cstddef>
50#include <cstdint>
51#include <cstring>
52#include <iterator>
53#include <string>
54#include <tuple>
55
56namespace llvm {
57
58class APInt;
59class Constant;
60template <typename T> struct DenseMapInfo;
61class GlobalValue;
62class MachineBasicBlock;
63class MachineConstantPoolValue;
64class MCSymbol;
65class raw_ostream;
66class SDNode;
67class SelectionDAG;
68class Type;
69class Value;
70
71void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
72 bool force = false);
73
74/// This represents a list of ValueType's that has been intern'd by
75/// a SelectionDAG. Instances of this simple value class are returned by
76/// SelectionDAG::getVTList(...).
77///
78struct SDVTList {
79 const EVT *VTs;
80 unsigned int NumVTs;
81};
82
83namespace ISD {
84
85 /// Node predicates
86
87 /// If N is a BUILD_VECTOR node whose elements are all the same constant or
88 /// undefined, return true and return the constant value in \p SplatValue.
89 bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
90
91 /// Return true if the specified node is a BUILD_VECTOR where all of the
92 /// elements are ~0 or undef.
93 bool isBuildVectorAllOnes(const SDNode *N);
94
95 /// Return true if the specified node is a BUILD_VECTOR where all of the
96 /// elements are 0 or undef.
97 bool isBuildVectorAllZeros(const SDNode *N);
98
99 /// Return true if the specified node is a BUILD_VECTOR node of all
100 /// ConstantSDNode or undef.
101 bool isBuildVectorOfConstantSDNodes(const SDNode *N);
102
103 /// Return true if the specified node is a BUILD_VECTOR node of all
104 /// ConstantFPSDNode or undef.
105 bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
106
107 /// Return true if the node has at least one operand and all operands of the
108 /// specified node are ISD::UNDEF.
109 bool allOperandsUndef(const SDNode *N);
110
111} // end namespace ISD
112
113//===----------------------------------------------------------------------===//
114/// Unlike LLVM values, Selection DAG nodes may return multiple
115/// values as the result of a computation. Many nodes return multiple values,
116/// from loads (which define a token and a return value) to ADDC (which returns
117/// a result and a carry value), to calls (which may return an arbitrary number
118/// of values).
119///
120/// As such, each use of a SelectionDAG computation must indicate the node that
121/// computes it as well as which return value to use from that node. This pair
122/// of information is represented with the SDValue value type.
123///
124class SDValue {
125 friend struct DenseMapInfo<SDValue>;
126
127 SDNode *Node = nullptr; // The node defining the value we are using.
128 unsigned ResNo = 0; // Which return value of the node we are using.
129
130public:
131 SDValue() = default;
132 SDValue(SDNode *node, unsigned resno);
133
134 /// get the index which selects a specific result in the SDNode
135 unsigned getResNo() const { return ResNo; }
136
137 /// get the SDNode which holds the desired result
138 SDNode *getNode() const { return Node; }
139
140 /// set the SDNode
141 void setNode(SDNode *N) { Node = N; }
142
143 inline SDNode *operator->() const { return Node; }
144
145 bool operator==(const SDValue &O) const {
146 return Node == O.Node && ResNo == O.ResNo;
147 }
148 bool operator!=(const SDValue &O) const {
149 return !operator==(O);
150 }
151 bool operator<(const SDValue &O) const {
152 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
153 }
154 explicit operator bool() const {
155 return Node != nullptr;
156 }
157
158 SDValue getValue(unsigned R) const {
159 return SDValue(Node, R);
160 }
161
162 /// Return true if this node is an operand of N.
163 bool isOperandOf(const SDNode *N) const;
164
165 /// Return the ValueType of the referenced return value.
166 inline EVT getValueType() const;
167
168 /// Return the simple ValueType of the referenced return value.
169 MVT getSimpleValueType() const {
170 return getValueType().getSimpleVT();
171 }
172
173 /// Returns the size of the value in bits.
174 ///
175 /// If the value type is a scalable vector type, the scalable property will
176 /// be set and the runtime size will be a positive integer multiple of the
177 /// base size.
178 TypeSize getValueSizeInBits() const {
179 return getValueType().getSizeInBits();
180 }
181
182 TypeSize getScalarValueSizeInBits() const {
183 return getValueType().getScalarType().getSizeInBits();
184 }
185
186 // Forwarding methods - These forward to the corresponding methods in SDNode.
187 inline unsigned getOpcode() const;
188 inline unsigned getNumOperands() const;
189 inline const SDValue &getOperand(unsigned i) const;
190 inline uint64_t getConstantOperandVal(unsigned i) const;
191 inline const APInt &getConstantOperandAPInt(unsigned i) const;
192 inline bool isTargetMemoryOpcode() const;
193 inline bool isTargetOpcode() const;
194 inline bool isMachineOpcode() const;
195 inline bool isUndef() const;
196 inline unsigned getMachineOpcode() const;
197 inline const DebugLoc &getDebugLoc() const;
198 inline void dump() const;
199 inline void dump(const SelectionDAG *G) const;
200 inline void dumpr() const;
201 inline void dumpr(const SelectionDAG *G) const;
202
203 /// Return true if this operand (which must be a chain) reaches the
204 /// specified operand without crossing any side-effecting instructions.
205 /// In practice, this looks through token factors and non-volatile loads.
206 /// In order to remain efficient, this only
207 /// looks a couple of nodes in, it does not do an exhaustive search.
208 bool reachesChainWithoutSideEffects(SDValue Dest,
209 unsigned Depth = 2) const;
210
211 /// Return true if there are no nodes using value ResNo of Node.
212 inline bool use_empty() const;
213
214 /// Return true if there is exactly one node using value ResNo of Node.
215 inline bool hasOneUse() const;
216};
217
218template<> struct DenseMapInfo<SDValue> {
219 static inline SDValue getEmptyKey() {
220 SDValue V;
221 V.ResNo = -1U;
222 return V;
223 }
224
225 static inline SDValue getTombstoneKey() {
226 SDValue V;
227 V.ResNo = -2U;
228 return V;
229 }
230
231 static unsigned getHashValue(const SDValue &Val) {
232 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
233 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
234 }
235
236 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
237 return LHS == RHS;
238 }
239};
240
241/// Allow casting operators to work directly on
242/// SDValues as if they were SDNode*'s.
243template<> struct simplify_type<SDValue> {
244 using SimpleType = SDNode *;
245
246 static SimpleType getSimplifiedValue(SDValue &Val) {
247 return Val.getNode();
248 }
249};
250template<> struct simplify_type<const SDValue> {
251 using SimpleType = /*const*/ SDNode *;
252
253 static SimpleType getSimplifiedValue(const SDValue &Val) {
254 return Val.getNode();
255 }
256};
257
258/// Represents a use of a SDNode. This class holds an SDValue,
259/// which records the SDNode being used and the result number, a
260/// pointer to the SDNode using the value, and Next and Prev pointers,
261/// which link together all the uses of an SDNode.
262///
263class SDUse {
264 /// Val - The value being used.
265 SDValue Val;
266 /// User - The user of this value.
267 SDNode *User = nullptr;
268 /// Prev, Next - Pointers to the uses list of the SDNode referred by
269 /// this operand.
270 SDUse **Prev = nullptr;
271 SDUse *Next = nullptr;
272
273public:
274 SDUse() = default;
275 SDUse(const SDUse &U) = delete;
276 SDUse &operator=(const SDUse &) = delete;
277
278 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
279 operator const SDValue&() const { return Val; }
280
281 /// If implicit conversion to SDValue doesn't work, the get() method returns
282 /// the SDValue.
283 const SDValue &get() const { return Val; }
284
285 /// This returns the SDNode that contains this Use.
286 SDNode *getUser() { return User; }
287
288 /// Get the next SDUse in the use list.
289 SDUse *getNext() const { return Next; }
290
291 /// Convenience function for get().getNode().
292 SDNode *getNode() const { return Val.getNode(); }
293 /// Convenience function for get().getResNo().
294 unsigned getResNo() const { return Val.getResNo(); }
295 /// Convenience function for get().getValueType().
296 EVT getValueType() const { return Val.getValueType(); }
297
298 /// Convenience function for get().operator==
299 bool operator==(const SDValue &V) const {
300 return Val == V;
301 }
302
303 /// Convenience function for get().operator!=
304 bool operator!=(const SDValue &V) const {
305 return Val != V;
306 }
307
308 /// Convenience function for get().operator<
309 bool operator<(const SDValue &V) const {
310 return Val < V;
311 }
312
313private:
314 friend class SelectionDAG;
315 friend class SDNode;
316 // TODO: unfriend HandleSDNode once we fix its operand handling.
317 friend class HandleSDNode;
318
319 void setUser(SDNode *p) { User = p; }
320
321 /// Remove this use from its existing use list, assign it the
322 /// given value, and add it to the new value's node's use list.
323 inline void set(const SDValue &V);
324 /// Like set, but only supports initializing a newly-allocated
325 /// SDUse with a non-null value.
326 inline void setInitial(const SDValue &V);
327 /// Like set, but only sets the Node portion of the value,
328 /// leaving the ResNo portion unmodified.
329 inline void setNode(SDNode *N);
330
331 void addToList(SDUse **List) {
332 Next = *List;
333 if (Next) Next->Prev = &Next;
334 Prev = List;
335 *List = this;
336 }
337
338 void removeFromList() {
339 *Prev = Next;
340 if (Next) Next->Prev = Prev;
341 }
342};
343
344/// simplify_type specializations - Allow casting operators to work directly on
345/// SDValues as if they were SDNode*'s.
346template<> struct simplify_type<SDUse> {
347 using SimpleType = SDNode *;
348
349 static SimpleType getSimplifiedValue(SDUse &Val) {
350 return Val.getNode();
351 }
352};
353
354/// These are IR-level optimization flags that may be propagated to SDNodes.
355/// TODO: This data structure should be shared by the IR optimizer and the
356/// the backend.
357struct SDNodeFlags {
358private:
359 // This bit is used to determine if the flags are in a defined state.
360 // Flag bits can only be masked out during intersection if the masking flags
361 // are defined.
362 bool AnyDefined : 1;
363
364 bool NoUnsignedWrap : 1;
365 bool NoSignedWrap : 1;
366 bool Exact : 1;
367 bool NoNaNs : 1;
368 bool NoInfs : 1;
369 bool NoSignedZeros : 1;
370 bool AllowReciprocal : 1;
371 bool VectorReduction : 1;
372 bool AllowContract : 1;
373 bool ApproximateFuncs : 1;
374 bool AllowReassociation : 1;
375
376 // We assume instructions do not raise floating-point exceptions by default,
377 // and only those marked explicitly may do so. We could choose to represent
378 // this via a positive "FPExcept" flags like on the MI level, but having a
379 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
380 // intersection logic more straightforward.
381 bool NoFPExcept : 1;
382
383public:
384 /// Default constructor turns off all optimization flags.
385 SDNodeFlags()
386 : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
387 Exact(false), NoNaNs(false), NoInfs(false),
388 NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
389 AllowContract(false), ApproximateFuncs(false),
390 AllowReassociation(false), NoFPExcept(false) {}
391
392 /// Propagate the fast-math-flags from an IR FPMathOperator.
393 void copyFMF(const FPMathOperator &FPMO) {
394 setNoNaNs(FPMO.hasNoNaNs());
395 setNoInfs(FPMO.hasNoInfs());
396 setNoSignedZeros(FPMO.hasNoSignedZeros());
397 setAllowReciprocal(FPMO.hasAllowReciprocal());
398 setAllowContract(FPMO.hasAllowContract());
399 setApproximateFuncs(FPMO.hasApproxFunc());
400 setAllowReassociation(FPMO.hasAllowReassoc());
401 }
402
403 /// Sets the state of the flags to the defined state.
404 void setDefined() { AnyDefined = true; }
405 /// Returns true if the flags are in a defined state.
406 bool isDefined() const { return AnyDefined; }
407
408 // These are mutators for each flag.
409 void setNoUnsignedWrap(bool b) {
410 setDefined();
411 NoUnsignedWrap = b;
412 }
413 void setNoSignedWrap(bool b) {
414 setDefined();
415 NoSignedWrap = b;
416 }
417 void setExact(bool b) {
418 setDefined();
419 Exact = b;
420 }
421 void setNoNaNs(bool b) {
422 setDefined();
423 NoNaNs = b;
424 }
425 void setNoInfs(bool b) {
426 setDefined();
427 NoInfs = b;
428 }
429 void setNoSignedZeros(bool b) {
430 setDefined();
431 NoSignedZeros = b;
432 }
433 void setAllowReciprocal(bool b) {
434 setDefined();
435 AllowReciprocal = b;
436 }
437 void setVectorReduction(bool b) {
438 setDefined();
439 VectorReduction = b;
440 }
441 void setAllowContract(bool b) {
442 setDefined();
443 AllowContract = b;
444 }
445 void setApproximateFuncs(bool b) {
446 setDefined();
447 ApproximateFuncs = b;
448 }
449 void setAllowReassociation(bool b) {
450 setDefined();
451 AllowReassociation = b;
452 }
453 void setNoFPExcept(bool b) {
454 setDefined();
455 NoFPExcept = b;
456 }
457
458 // These are accessors for each flag.
459 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
460 bool hasNoSignedWrap() const { return NoSignedWrap; }
461 bool hasExact() const { return Exact; }
462 bool hasNoNaNs() const { return NoNaNs; }
463 bool hasNoInfs() const { return NoInfs; }
464 bool hasNoSignedZeros() const { return NoSignedZeros; }
465 bool hasAllowReciprocal() const { return AllowReciprocal; }
466 bool hasVectorReduction() const { return VectorReduction; }
467 bool hasAllowContract() const { return AllowContract; }
468 bool hasApproximateFuncs() const { return ApproximateFuncs; }
469 bool hasAllowReassociation() const { return AllowReassociation; }
470 bool hasNoFPExcept() const { return NoFPExcept; }
471
472 bool isFast() const {
473 return NoSignedZeros && AllowReciprocal && NoNaNs && NoInfs && NoFPExcept &&
474 AllowContract && ApproximateFuncs && AllowReassociation;
475 }
476
477 /// Clear any flags in this flag set that aren't also set in Flags.
478 /// If the given Flags are undefined then don't do anything.
479 void intersectWith(const SDNodeFlags Flags) {
480 if (!Flags.isDefined())
481 return;
482 NoUnsignedWrap &= Flags.NoUnsignedWrap;
483 NoSignedWrap &= Flags.NoSignedWrap;
484 Exact &= Flags.Exact;
485 NoNaNs &= Flags.NoNaNs;
486 NoInfs &= Flags.NoInfs;
487 NoSignedZeros &= Flags.NoSignedZeros;
488 AllowReciprocal &= Flags.AllowReciprocal;
489 VectorReduction &= Flags.VectorReduction;
490 AllowContract &= Flags.AllowContract;
491 ApproximateFuncs &= Flags.ApproximateFuncs;
492 AllowReassociation &= Flags.AllowReassociation;
493 NoFPExcept &= Flags.NoFPExcept;
494 }
495};
496
497/// Represents one node in the SelectionDAG.
498///
499class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
500private:
501 /// The operation that this node performs.
502 int16_t NodeType;
503
504protected:
505 // We define a set of mini-helper classes to help us interpret the bits in our
506 // SubclassData. These are designed to fit within a uint16_t so they pack
507 // with NodeType.
508
509#if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__))
510// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
511// and give the `pack` pragma push semantics.
512#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
513#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
514#else
515#define BEGIN_TWO_BYTE_PACK()
516#define END_TWO_BYTE_PACK()
517#endif
518
519BEGIN_TWO_BYTE_PACK()
520 class SDNodeBitfields {
521 friend class SDNode;
522 friend class MemIntrinsicSDNode;
523 friend class MemSDNode;
524 friend class SelectionDAG;
525
526 uint16_t HasDebugValue : 1;
527 uint16_t IsMemIntrinsic : 1;
528 uint16_t IsDivergent : 1;
529 };
530 enum { NumSDNodeBits = 3 };
531
532 class ConstantSDNodeBitfields {
533 friend class ConstantSDNode;
534
535 uint16_t : NumSDNodeBits;
536
537 uint16_t IsOpaque : 1;
538 };
539
540 class MemSDNodeBitfields {
541 friend class MemSDNode;
542 friend class MemIntrinsicSDNode;
543 friend class AtomicSDNode;
544
545 uint16_t : NumSDNodeBits;
546
547 uint16_t IsVolatile : 1;
548 uint16_t IsNonTemporal : 1;
549 uint16_t IsDereferenceable : 1;
550 uint16_t IsInvariant : 1;
551 };
552 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
553
554 class LSBaseSDNodeBitfields {
555 friend class LSBaseSDNode;
556 friend class MaskedLoadStoreSDNode;
557 friend class MaskedGatherScatterSDNode;
558
559 uint16_t : NumMemSDNodeBits;
560
561 // This storage is shared between disparate class hierarchies to hold an
562 // enumeration specific to the class hierarchy in use.
563 // LSBaseSDNode => enum ISD::MemIndexedMode
564 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
565 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
566 uint16_t AddressingMode : 3;
567 };
568 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
569
570 class LoadSDNodeBitfields {
571 friend class LoadSDNode;
572 friend class MaskedLoadSDNode;
573
574 uint16_t : NumLSBaseSDNodeBits;
575
576 uint16_t ExtTy : 2; // enum ISD::LoadExtType
577 uint16_t IsExpanding : 1;
578 };
579
580 class StoreSDNodeBitfields {
581 friend class StoreSDNode;
582 friend class MaskedStoreSDNode;
583
584 uint16_t : NumLSBaseSDNodeBits;
585
586 uint16_t IsTruncating : 1;
587 uint16_t IsCompressing : 1;
588 };
589
590 union {
591 char RawSDNodeBits[sizeof(uint16_t)];
592 SDNodeBitfields SDNodeBits;
593 ConstantSDNodeBitfields ConstantSDNodeBits;
594 MemSDNodeBitfields MemSDNodeBits;
595 LSBaseSDNodeBitfields LSBaseSDNodeBits;
596 LoadSDNodeBitfields LoadSDNodeBits;
597 StoreSDNodeBitfields StoreSDNodeBits;
598 };
599END_TWO_BYTE_PACK()
600#undef BEGIN_TWO_BYTE_PACK
601#undef END_TWO_BYTE_PACK
602
603 // RawSDNodeBits must cover the entirety of the union. This means that all of
604 // the union's members must have size <= RawSDNodeBits. We write the RHS as
605 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
606 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
607 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
608 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
609 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
610 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
611 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
612
613private:
614 friend class SelectionDAG;
615 // TODO: unfriend HandleSDNode once we fix its operand handling.
616 friend class HandleSDNode;
617
618 /// Unique id per SDNode in the DAG.
619 int NodeId = -1;
620
621 /// The values that are used by this operation.
622 SDUse *OperandList = nullptr;
623
624 /// The types of the values this node defines. SDNode's may
625 /// define multiple values simultaneously.
626 const EVT *ValueList;
627
628 /// List of uses for this SDNode.
629 SDUse *UseList = nullptr;
630
631 /// The number of entries in the Operand/Value list.
632 unsigned short NumOperands = 0;
633 unsigned short NumValues;
634
635 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
636 // original LLVM instructions.
637 // This is used for turning off scheduling, because we'll forgo
638 // the normal scheduling algorithms and output the instructions according to
639 // this ordering.
640 unsigned IROrder;
641
642 /// Source line information.
643 DebugLoc debugLoc;
644
645 /// Return a pointer to the specified value type.
646 static const EVT *getValueTypeList(EVT VT);
647
648 SDNodeFlags Flags;
649
650public:
651 /// Unique and persistent id per SDNode in the DAG.
652 /// Used for debug printing.
653 uint16_t PersistentId;
654
655 //===--------------------------------------------------------------------===//
656 // Accessors
657 //
658
659 /// Return the SelectionDAG opcode value for this node. For
660 /// pre-isel nodes (those for which isMachineOpcode returns false), these
661 /// are the opcode values in the ISD and <target>ISD namespaces. For
662 /// post-isel opcodes, see getMachineOpcode.
663 unsigned getOpcode() const { return (unsigned short)NodeType; }
664
665 /// Test if this node has a target-specific opcode (in the
666 /// \<target\>ISD namespace).
667 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
668
669 /// Test if this node has a target-specific opcode that may raise
670 /// FP exceptions (in the \<target\>ISD namespace and greater than
671 /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
672 /// opcode are currently automatically considered to possibly raise
673 /// FP exceptions as well.
674 bool isTargetStrictFPOpcode() const {
675 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
676 }
677
678 /// Test if this node has a target-specific
679 /// memory-referencing opcode (in the \<target\>ISD namespace and
680 /// greater than FIRST_TARGET_MEMORY_OPCODE).
681 bool isTargetMemoryOpcode() const {
682 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
683 }
684
685 /// Return true if the type of the node type undefined.
686 bool isUndef() const { return NodeType == ISD::UNDEF; }
687
688 /// Test if this node is a memory intrinsic (with valid pointer information).
689 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
690 /// non-memory intrinsics (with chains) that are not really instances of
691 /// MemSDNode. For such nodes, we need some extra state to determine the
692 /// proper classof relationship.
693 bool isMemIntrinsic() const {
694 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
695 NodeType == ISD::INTRINSIC_VOID) &&
696 SDNodeBits.IsMemIntrinsic;
697 }
698
699 /// Test if this node is a strict floating point pseudo-op.
700 bool isStrictFPOpcode() {
701 switch (NodeType) {
702 default:
703 return false;
704#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
705 case ISD::STRICT_##DAGN:
706#include "llvm/IR/ConstrainedOps.def"
707 return true;
708 }
709 }
710
711 /// Test if this node has a post-isel opcode, directly
712 /// corresponding to a MachineInstr opcode.
713 bool isMachineOpcode() const { return NodeType < 0; }
714
715 /// This may only be called if isMachineOpcode returns
716 /// true. It returns the MachineInstr opcode value that the node's opcode
717 /// corresponds to.
718 unsigned getMachineOpcode() const {
719 assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 719, __PRETTY_FUNCTION__))
;
720 return ~NodeType;
721 }
722
723 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
724 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
725
726 bool isDivergent() const { return SDNodeBits.IsDivergent; }
727
728 /// Return true if there are no uses of this node.
729 bool use_empty() const { return UseList == nullptr; }
730
731 /// Return true if there is exactly one use of this node.
732 bool hasOneUse() const {
733 return !use_empty() && std::next(use_begin()) == use_end();
734 }
735
736 /// Return the number of uses of this node. This method takes
737 /// time proportional to the number of uses.
738 size_t use_size() const { return std::distance(use_begin(), use_end()); }
739
740 /// Return the unique node id.
741 int getNodeId() const { return NodeId; }
742
743 /// Set unique node id.
744 void setNodeId(int Id) { NodeId = Id; }
745
746 /// Return the node ordering.
747 unsigned getIROrder() const { return IROrder; }
748
749 /// Set the node ordering.
750 void setIROrder(unsigned Order) { IROrder = Order; }
751
752 /// Return the source location info.
753 const DebugLoc &getDebugLoc() const { return debugLoc; }
754
755 /// Set source location info. Try to avoid this, putting
756 /// it in the constructor is preferable.
757 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
758
759 /// This class provides iterator support for SDUse
760 /// operands that use a specific SDNode.
761 class use_iterator
762 : public std::iterator<std::forward_iterator_tag, SDUse, ptrdiff_t> {
763 friend class SDNode;
764
765 SDUse *Op = nullptr;
766
767 explicit use_iterator(SDUse *op) : Op(op) {}
768
769 public:
770 using reference = std::iterator<std::forward_iterator_tag,
771 SDUse, ptrdiff_t>::reference;
772 using pointer = std::iterator<std::forward_iterator_tag,
773 SDUse, ptrdiff_t>::pointer;
774
775 use_iterator() = default;
776 use_iterator(const use_iterator &I) : Op(I.Op) {}
777
778 bool operator==(const use_iterator &x) const {
779 return Op == x.Op;
780 }
781 bool operator!=(const use_iterator &x) const {
782 return !operator==(x);
783 }
784
785 /// Return true if this iterator is at the end of uses list.
786 bool atEnd() const { return Op == nullptr; }
787
788 // Iterator traversal: forward iteration only.
789 use_iterator &operator++() { // Preincrement
790 assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 790, __PRETTY_FUNCTION__))
;
791 Op = Op->getNext();
792 return *this;
793 }
794
795 use_iterator operator++(int) { // Postincrement
796 use_iterator tmp = *this; ++*this; return tmp;
797 }
798
799 /// Retrieve a pointer to the current user node.
800 SDNode *operator*() const {
801 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 801, __PRETTY_FUNCTION__))
;
802 return Op->getUser();
803 }
804
805 SDNode *operator->() const { return operator*(); }
806
807 SDUse &getUse() const { return *Op; }
808
809 /// Retrieve the operand # of this use in its user.
810 unsigned getOperandNo() const {
811 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 811, __PRETTY_FUNCTION__))
;
812 return (unsigned)(Op - Op->getUser()->OperandList);
813 }
814 };
815
816 /// Provide iteration support to walk over all uses of an SDNode.
817 use_iterator use_begin() const {
818 return use_iterator(UseList);
819 }
820
821 static use_iterator use_end() { return use_iterator(nullptr); }
822
823 inline iterator_range<use_iterator> uses() {
824 return make_range(use_begin(), use_end());
825 }
826 inline iterator_range<use_iterator> uses() const {
827 return make_range(use_begin(), use_end());
828 }
829
830 /// Return true if there are exactly NUSES uses of the indicated value.
831 /// This method ignores uses of other values defined by this operation.
832 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
833
834 /// Return true if there are any use of the indicated value.
835 /// This method ignores uses of other values defined by this operation.
836 bool hasAnyUseOfValue(unsigned Value) const;
837
838 /// Return true if this node is the only use of N.
839 bool isOnlyUserOf(const SDNode *N) const;
840
841 /// Return true if this node is an operand of N.
842 bool isOperandOf(const SDNode *N) const;
843
844 /// Return true if this node is a predecessor of N.
845 /// NOTE: Implemented on top of hasPredecessor and every bit as
846 /// expensive. Use carefully.
847 bool isPredecessorOf(const SDNode *N) const {
848 return N->hasPredecessor(this);
849 }
850
851 /// Return true if N is a predecessor of this node.
852 /// N is either an operand of this node, or can be reached by recursively
853 /// traversing up the operands.
854 /// NOTE: This is an expensive method. Use it carefully.
855 bool hasPredecessor(const SDNode *N) const;
856
857 /// Returns true if N is a predecessor of any node in Worklist. This
858 /// helper keeps Visited and Worklist sets externally to allow unions
859 /// searches to be performed in parallel, caching of results across
860 /// queries and incremental addition to Worklist. Stops early if N is
861 /// found but will resume. Remember to clear Visited and Worklists
862 /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
863 /// giving up. The TopologicalPrune flag signals that positive NodeIds are
864 /// topologically ordered (Operands have strictly smaller node id) and search
865 /// can be pruned leveraging this.
866 static bool hasPredecessorHelper(const SDNode *N,
867 SmallPtrSetImpl<const SDNode *> &Visited,
868 SmallVectorImpl<const SDNode *> &Worklist,
869 unsigned int MaxSteps = 0,
870 bool TopologicalPrune = false) {
871 SmallVector<const SDNode *, 8> DeferredNodes;
872 if (Visited.count(N))
873 return true;
874
875 // Node Id's are assigned in three places: As a topological
876 // ordering (> 0), during legalization (results in values set to
877 // 0), new nodes (set to -1). If N has a topolgical id then we
878 // know that all nodes with ids smaller than it cannot be
879 // successors and we need not check them. Filter out all node
880 // that can't be matches. We add them to the worklist before exit
881 // in case of multiple calls. Note that during selection the topological id
882 // may be violated if a node's predecessor is selected before it. We mark
883 // this at selection negating the id of unselected successors and
884 // restricting topological pruning to positive ids.
885
886 int NId = N->getNodeId();
887 // If we Invalidated the Id, reconstruct original NId.
888 if (NId < -1)
889 NId = -(NId + 1);
890
891 bool Found = false;
892 while (!Worklist.empty()) {
893 const SDNode *M = Worklist.pop_back_val();
894 int MId = M->getNodeId();
895 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
896 (MId > 0) && (MId < NId)) {
897 DeferredNodes.push_back(M);
898 continue;
899 }
900 for (const SDValue &OpV : M->op_values()) {
901 SDNode *Op = OpV.getNode();
902 if (Visited.insert(Op).second)
903 Worklist.push_back(Op);
904 if (Op == N)
905 Found = true;
906 }
907 if (Found)
908 break;
909 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
910 break;
911 }
912 // Push deferred nodes back on worklist.
913 Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
914 // If we bailed early, conservatively return found.
915 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
916 return true;
917 return Found;
918 }
919
920 /// Return true if all the users of N are contained in Nodes.
921 /// NOTE: Requires at least one match, but doesn't require them all.
922 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
923
924 /// Return the number of values used by this operation.
925 unsigned getNumOperands() const { return NumOperands; }
926
927 /// Return the maximum number of operands that a SDNode can hold.
928 static constexpr size_t getMaxNumOperands() {
929 return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
930 }
931
932 /// Helper method returns the integer value of a ConstantSDNode operand.
933 inline uint64_t getConstantOperandVal(unsigned Num) const;
934
935 /// Helper method returns the APInt of a ConstantSDNode operand.
936 inline const APInt &getConstantOperandAPInt(unsigned Num) const;
937
938 const SDValue &getOperand(unsigned Num) const {
939 assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 939, __PRETTY_FUNCTION__))
;
940 return OperandList[Num];
941 }
942
943 using op_iterator = SDUse *;
944
945 op_iterator op_begin() const { return OperandList; }
946 op_iterator op_end() const { return OperandList+NumOperands; }
947 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
948
949 /// Iterator for directly iterating over the operand SDValue's.
950 struct value_op_iterator
951 : iterator_adaptor_base<value_op_iterator, op_iterator,
952 std::random_access_iterator_tag, SDValue,
953 ptrdiff_t, value_op_iterator *,
954 value_op_iterator *> {
955 explicit value_op_iterator(SDUse *U = nullptr)
956 : iterator_adaptor_base(U) {}
957
958 const SDValue &operator*() const { return I->get(); }
959 };
960
961 iterator_range<value_op_iterator> op_values() const {
962 return make_range(value_op_iterator(op_begin()),
963 value_op_iterator(op_end()));
964 }
965
966 SDVTList getVTList() const {
967 SDVTList X = { ValueList, NumValues };
968 return X;
969 }
970
971 /// If this node has a glue operand, return the node
972 /// to which the glue operand points. Otherwise return NULL.
973 SDNode *getGluedNode() const {
974 if (getNumOperands() != 0 &&
975 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
976 return getOperand(getNumOperands()-1).getNode();
977 return nullptr;
978 }
979
980 /// If this node has a glue value with a user, return
981 /// the user (there is at most one). Otherwise return NULL.
982 SDNode *getGluedUser() const {
983 for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
984 if (UI.getUse().get().getValueType() == MVT::Glue)
985 return *UI;
986 return nullptr;
987 }
988
989 const SDNodeFlags getFlags() const { return Flags; }
990 void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
991 bool isFast() { return Flags.isFast(); }
992
993 /// Clear any flags in this node that aren't also set in Flags.
994 /// If Flags is not in a defined state then this has no effect.
995 void intersectFlagsWith(const SDNodeFlags Flags);
996
997 /// Return the number of values defined/returned by this operator.
998 unsigned getNumValues() const { return NumValues; }
999
1000 /// Return the type of a specified result.
1001 EVT getValueType(unsigned ResNo) const {
1002 assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ?
static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1002, __PRETTY_FUNCTION__))
;
1003 return ValueList[ResNo];
1004 }
1005
1006 /// Return the type of a specified result as a simple type.
1007 MVT getSimpleValueType(unsigned ResNo) const {
1008 return getValueType(ResNo).getSimpleVT();
1009 }
1010
1011 /// Returns MVT::getSizeInBits(getValueType(ResNo)).
1012 ///
1013 /// If the value type is a scalable vector type, the scalable property will
1014 /// be set and the runtime size will be a positive integer multiple of the
1015 /// base size.
1016 TypeSize getValueSizeInBits(unsigned ResNo) const {
1017 return getValueType(ResNo).getSizeInBits();
1018 }
1019
1020 using value_iterator = const EVT *;
1021
1022 value_iterator value_begin() const { return ValueList; }
1023 value_iterator value_end() const { return ValueList+NumValues; }
1024
1025 /// Return the opcode of this operation for printing.
1026 std::string getOperationName(const SelectionDAG *G = nullptr) const;
1027 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1028 void print_types(raw_ostream &OS, const SelectionDAG *G) const;
1029 void print_details(raw_ostream &OS, const SelectionDAG *G) const;
1030 void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1031 void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1032
1033 /// Print a SelectionDAG node and all children down to
1034 /// the leaves. The given SelectionDAG allows target-specific nodes
1035 /// to be printed in human-readable form. Unlike printr, this will
1036 /// print the whole DAG, including children that appear multiple
1037 /// times.
1038 ///
1039 void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;
1040
1041 /// Print a SelectionDAG node and children up to
1042 /// depth "depth." The given SelectionDAG allows target-specific
1043 /// nodes to be printed in human-readable form. Unlike printr, this
1044 /// will print children that appear multiple times wherever they are
1045 /// used.
1046 ///
1047 void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
1048 unsigned depth = 100) const;
1049
1050 /// Dump this node, for debugging.
1051 void dump() const;
1052
1053 /// Dump (recursively) this node and its use-def subgraph.
1054 void dumpr() const;
1055
1056 /// Dump this node, for debugging.
1057 /// The given SelectionDAG allows target-specific nodes to be printed
1058 /// in human-readable form.
1059 void dump(const SelectionDAG *G) const;
1060
1061 /// Dump (recursively) this node and its use-def subgraph.
1062 /// The given SelectionDAG allows target-specific nodes to be printed
1063 /// in human-readable form.
1064 void dumpr(const SelectionDAG *G) const;
1065
1066 /// printrFull to dbgs(). The given SelectionDAG allows
1067 /// target-specific nodes to be printed in human-readable form.
1068 /// Unlike dumpr, this will print the whole DAG, including children
1069 /// that appear multiple times.
1070 void dumprFull(const SelectionDAG *G = nullptr) const;
1071
1072 /// printrWithDepth to dbgs(). The given
1073 /// SelectionDAG allows target-specific nodes to be printed in
1074 /// human-readable form. Unlike dumpr, this will print children
1075 /// that appear multiple times wherever they are used.
1076 ///
1077 void dumprWithDepth(const SelectionDAG *G = nullptr,
1078 unsigned depth = 100) const;
1079
1080 /// Gather unique data for the node.
1081 void Profile(FoldingSetNodeID &ID) const;
1082
1083 /// This method should only be used by the SDUse class.
1084 void addUse(SDUse &U) { U.addToList(&UseList); }
1085
1086protected:
1087 static SDVTList getSDVTList(EVT VT) {
1088 SDVTList Ret = { getValueTypeList(VT), 1 };
1089 return Ret;
1090 }
1091
1092 /// Create an SDNode.
1093 ///
1094 /// SDNodes are created without any operands, and never own the operand
1095 /// storage. To add operands, see SelectionDAG::createOperands.
1096 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1097 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1098 IROrder(Order), debugLoc(std::move(dl)) {
1099 memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
1100 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1100, __PRETTY_FUNCTION__))
;
1101 assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1102, __PRETTY_FUNCTION__))
1102 "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1102, __PRETTY_FUNCTION__))
;
1103 }
1104
1105 /// Release the operands and set this node to have zero operands.
1106 void DropOperands();
1107};
1108
1109/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1110/// into SDNode creation functions.
1111/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1112/// from the original Instruction, and IROrder is the ordinal position of
1113/// the instruction.
1114/// When an SDNode is created after the DAG is being built, both DebugLoc and
1115/// the IROrder are propagated from the original SDNode.
1116/// So SDLoc class provides two constructors besides the default one, one to
1117/// be used by the DAGBuilder, the other to be used by others.
1118class SDLoc {
1119private:
1120 DebugLoc DL;
1121 int IROrder = 0;
1122
1123public:
1124 SDLoc() = default;
1125 SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
1126 SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
1127 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1128 assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void
> (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1128, __PRETTY_FUNCTION__))
;
1129 if (I)
1130 DL = I->getDebugLoc();
1131 }
1132
1133 unsigned getIROrder() const { return IROrder; }
1134 const DebugLoc &getDebugLoc() const { return DL; }
1135};
1136
1137// Define inline functions from the SDValue class.
1138
1139inline SDValue::SDValue(SDNode *node, unsigned resno)
1140 : Node(node), ResNo(resno) {
1141 // Explicitly check for !ResNo to avoid use-after-free, because there are
1142 // callers that use SDValue(N, 0) with a deleted N to indicate successful
1143 // combines.
1144 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1145, __PRETTY_FUNCTION__))
1145 "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1145, __PRETTY_FUNCTION__))
;
1146 assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1146, __PRETTY_FUNCTION__))
;
1147}
1148
1149inline unsigned SDValue::getOpcode() const {
1150 return Node->getOpcode();
15
Called C++ object pointer is null
1151}
1152
1153inline EVT SDValue::getValueType() const {
1154 return Node->getValueType(ResNo);
1155}
1156
1157inline unsigned SDValue::getNumOperands() const {
1158 return Node->getNumOperands();
1159}
1160
1161inline const SDValue &SDValue::getOperand(unsigned i) const {
1162 return Node->getOperand(i);
1163}
1164
1165inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
1166 return Node->getConstantOperandVal(i);
1167}
1168
1169inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
1170 return Node->getConstantOperandAPInt(i);
1171}
1172
1173inline bool SDValue::isTargetOpcode() const {
1174 return Node->isTargetOpcode();
1175}
1176
1177inline bool SDValue::isTargetMemoryOpcode() const {
1178 return Node->isTargetMemoryOpcode();
1179}
1180
1181inline bool SDValue::isMachineOpcode() const {
1182 return Node->isMachineOpcode();
1183}
1184
1185inline unsigned SDValue::getMachineOpcode() const {
1186 return Node->getMachineOpcode();
1187}
1188
1189inline bool SDValue::isUndef() const {
1190 return Node->isUndef();
1191}
1192
1193inline bool SDValue::use_empty() const {
1194 return !Node->hasAnyUseOfValue(ResNo);
1195}
1196
1197inline bool SDValue::hasOneUse() const {
1198 return Node->hasNUsesOfValue(1, ResNo);
1199}
1200
1201inline const DebugLoc &SDValue::getDebugLoc() const {
1202 return Node->getDebugLoc();
1203}
1204
1205inline void SDValue::dump() const {
1206 return Node->dump();
1207}
1208
1209inline void SDValue::dump(const SelectionDAG *G) const {
1210 return Node->dump(G);
1211}
1212
1213inline void SDValue::dumpr() const {
1214 return Node->dumpr();
1215}
1216
1217inline void SDValue::dumpr(const SelectionDAG *G) const {
1218 return Node->dumpr(G);
1219}
1220
1221// Define inline functions from the SDUse class.
1222
1223inline void SDUse::set(const SDValue &V) {
1224 if (Val.getNode()) removeFromList();
1225 Val = V;
1226 if (V.getNode()) V.getNode()->addUse(*this);
1227}
1228
1229inline void SDUse::setInitial(const SDValue &V) {
1230 Val = V;
1231 V.getNode()->addUse(*this);
1232}
1233
1234inline void SDUse::setNode(SDNode *N) {
1235 if (Val.getNode()) removeFromList();
1236 Val.setNode(N);
1237 if (N) N->addUse(*this);
1238}
1239
1240/// This class is used to form a handle around another node that
1241/// is persistent and is updated across invocations of replaceAllUsesWith on its
1242/// operand. This node should be directly created by end-users and not added to
1243/// the AllNodes list.
1244class HandleSDNode : public SDNode {
1245 SDUse Op;
1246
1247public:
1248 explicit HandleSDNode(SDValue X)
1249 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
1250 // HandleSDNodes are never inserted into the DAG, so they won't be
1251 // auto-numbered. Use ID 65535 as a sentinel.
1252 PersistentId = 0xffff;
1253
1254 // Manually set up the operand list. This node type is special in that it's
1255 // always stack allocated and SelectionDAG does not manage its operands.
1256 // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
1257 // be so special.
1258 Op.setUser(this);
1259 Op.setInitial(X);
1260 NumOperands = 1;
1261 OperandList = &Op;
1262 }
1263 ~HandleSDNode();
1264
1265 const SDValue &getValue() const { return Op; }
1266};
1267
1268class AddrSpaceCastSDNode : public SDNode {
1269private:
1270 unsigned SrcAddrSpace;
1271 unsigned DestAddrSpace;
1272
1273public:
1274 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1275 unsigned SrcAS, unsigned DestAS);
1276
1277 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
1278 unsigned getDestAddressSpace() const { return DestAddrSpace; }
1279
1280 static bool classof(const SDNode *N) {
1281 return N->getOpcode() == ISD::ADDRSPACECAST;
1282 }
1283};
1284
1285/// This is an abstract virtual class for memory operations.
1286class MemSDNode : public SDNode {
1287private:
1288 // VT of in-memory value.
1289 EVT MemoryVT;
1290
1291protected:
1292 /// Memory reference information.
1293 MachineMemOperand *MMO;
1294
1295public:
1296 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1297 EVT memvt, MachineMemOperand *MMO);
1298
1299 bool readMem() const { return MMO->isLoad(); }
1300 bool writeMem() const { return MMO->isStore(); }
1301
1302 /// Returns alignment and volatility of the memory access
1303 unsigned getOriginalAlignment() const {
1304 return MMO->getBaseAlignment();
1305 }
1306 unsigned getAlignment() const {
1307 return MMO->getAlignment();
1308 }
1309
1310 /// Return the SubclassData value, without HasDebugValue. This contains an
1311 /// encoding of the volatile flag, as well as bits used by subclasses. This
1312 /// function should only be used to compute a FoldingSetNodeID value.
1313 /// The HasDebugValue bit is masked out because CSE map needs to match
1314 /// nodes with debug info with nodes without debug info. Same is about
1315 /// isDivergent bit.
1316 unsigned getRawSubclassData() const {
1317 uint16_t Data;
1318 union {
1319 char RawSDNodeBits[sizeof(uint16_t)];
1320 SDNodeBitfields SDNodeBits;
1321 };
1322 memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
1323 SDNodeBits.HasDebugValue = 0;
1324 SDNodeBits.IsDivergent = false;
1325 memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
1326 return Data;
1327 }
1328
1329 bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
1330 bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
1331 bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
1332 bool isInvariant() const { return MemSDNodeBits.IsInvariant; }
1333
1334 // Returns the offset from the location of the access.
1335 int64_t getSrcValueOffset() const { return MMO->getOffset(); }
1336
1337 /// Returns the AA info that describes the dereference.
1338 AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }
1339
1340 /// Returns the Ranges that describes the dereference.
1341 const MDNode *getRanges() const { return MMO->getRanges(); }
1342
1343 /// Returns the synchronization scope ID for this memory operation.
1344 SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }
1345
1346 /// Return the atomic ordering requirements for this memory operation. For
1347 /// cmpxchg atomic operations, return the atomic ordering requirements when
1348 /// store occurs.
1349 AtomicOrdering getOrdering() const { return MMO->getOrdering(); }
1350
1351 /// Return true if the memory operation ordering is Unordered or higher.
1352 bool isAtomic() const { return MMO->isAtomic(); }
1353
1354 /// Returns true if the memory operation doesn't imply any ordering
1355 /// constraints on surrounding memory operations beyond the normal memory
1356 /// aliasing rules.
1357 bool isUnordered() const { return MMO->isUnordered(); }
1358
1359 /// Returns true if the memory operation is neither atomic or volatile.
1360 bool isSimple() const { return !isAtomic() && !isVolatile(); }
1361
1362 /// Return the type of the in-memory value.
1363 EVT getMemoryVT() const { return MemoryVT; }
1364
1365 /// Return a MachineMemOperand object describing the memory
1366 /// reference performed by operation.
1367 MachineMemOperand *getMemOperand() const { return MMO; }
1368
1369 const MachinePointerInfo &getPointerInfo() const {
1370 return MMO->getPointerInfo();
1371 }
1372
1373 /// Return the address space for the associated pointer
1374 unsigned getAddressSpace() const {
1375 return getPointerInfo().getAddrSpace();
1376 }
1377
1378 /// Update this MemSDNode's MachineMemOperand information
1379 /// to reflect the alignment of NewMMO, if it has a greater alignment.
1380 /// This must only be used when the new alignment applies to all users of
1381 /// this MachineMemOperand.
1382 void refineAlignment(const MachineMemOperand *NewMMO) {
1383 MMO->refineAlignment(NewMMO);
1384 }
1385
1386 const SDValue &getChain() const { return getOperand(0); }
1387 const SDValue &getBasePtr() const {
1388 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1389 }
1390
1391 // Methods to support isa and dyn_cast
1392 static bool classof(const SDNode *N) {
1393 // For some targets, we lower some target intrinsics to a MemIntrinsicNode
1394 // with either an intrinsic or a target opcode.
1395 return N->getOpcode() == ISD::LOAD ||
1396 N->getOpcode() == ISD::STORE ||
1397 N->getOpcode() == ISD::PREFETCH ||
1398 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1399 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1400 N->getOpcode() == ISD::ATOMIC_SWAP ||
1401 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1402 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1403 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1404 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1405 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1406 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1407 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1408 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1409 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1410 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1411 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1412 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1413 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1414 N->getOpcode() == ISD::ATOMIC_LOAD ||
1415 N->getOpcode() == ISD::ATOMIC_STORE ||
1416 N->getOpcode() == ISD::MLOAD ||
1417 N->getOpcode() == ISD::MSTORE ||
1418 N->getOpcode() == ISD::MGATHER ||
1419 N->getOpcode() == ISD::MSCATTER ||
1420 N->isMemIntrinsic() ||
1421 N->isTargetMemoryOpcode();
1422 }
1423};
1424
1425/// This is an SDNode representing atomic operations.
1426class AtomicSDNode : public MemSDNode {
1427public:
1428 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
1429 EVT MemVT, MachineMemOperand *MMO)
1430 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
1431 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1432, __PRETTY_FUNCTION__))
1432 MMO->isAtomic()) && "then why are we using an AtomicSDNode?")((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1432, __PRETTY_FUNCTION__))
;
1433 }
1434
1435 const SDValue &getBasePtr() const { return getOperand(1); }
1436 const SDValue &getVal() const { return getOperand(2); }
1437
1438 /// Returns true if this SDNode represents cmpxchg atomic operation, false
1439 /// otherwise.
1440 bool isCompareAndSwap() const {
1441 unsigned Op = getOpcode();
1442 return Op == ISD::ATOMIC_CMP_SWAP ||
1443 Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
1444 }
1445
1446 /// For cmpxchg atomic operations, return the atomic ordering requirements
1447 /// when store does not occur.
1448 AtomicOrdering getFailureOrdering() const {
1449 assert(isCompareAndSwap() && "Must be cmpxchg operation")((isCompareAndSwap() && "Must be cmpxchg operation") ?
static_cast<void> (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1449, __PRETTY_FUNCTION__))
;
1450 return MMO->getFailureOrdering();
1451 }
1452
1453 // Methods to support isa and dyn_cast
1454 static bool classof(const SDNode *N) {
1455 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1456 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1457 N->getOpcode() == ISD::ATOMIC_SWAP ||
1458 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1459 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1460 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1461 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1462 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1463 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1464 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1465 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1466 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1467 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1468 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1469 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1470 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1471 N->getOpcode() == ISD::ATOMIC_LOAD ||
1472 N->getOpcode() == ISD::ATOMIC_STORE;
1473 }
1474};
1475
1476/// This SDNode is used for target intrinsics that touch
1477/// memory and need an associated MachineMemOperand. Its opcode may be
1478/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1479/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1480class MemIntrinsicSDNode : public MemSDNode {
1481public:
1482 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1483 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
1484 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
1485 SDNodeBits.IsMemIntrinsic = true;
1486 }
1487
1488 // Methods to support isa and dyn_cast
1489 static bool classof(const SDNode *N) {
1490 // We lower some target intrinsics to their target opcode
1491 // early a node with a target opcode can be of this class
1492 return N->isMemIntrinsic() ||
1493 N->getOpcode() == ISD::PREFETCH ||
1494 N->isTargetMemoryOpcode();
1495 }
1496};
1497
1498/// This SDNode is used to implement the code generator
1499/// support for the llvm IR shufflevector instruction. It combines elements
1500/// from two input vectors into a new input vector, with the selection and
1501/// ordering of elements determined by an array of integers, referred to as
1502/// the shuffle mask. For input vectors of width N, mask indices of 0..N-1
1503/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1504/// An index of -1 is treated as undef, such that the code generator may put
1505/// any value in the corresponding element of the result.
1506class ShuffleVectorSDNode : public SDNode {
1507 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
1508 // is freed when the SelectionDAG object is destroyed.
1509 const int *Mask;
1510
1511protected:
1512 friend class SelectionDAG;
1513
1514 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
1515 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1516
1517public:
1518 ArrayRef<int> getMask() const {
1519 EVT VT = getValueType(0);
1520 return makeArrayRef(Mask, VT.getVectorNumElements());
1521 }
1522
1523 int getMaskElt(unsigned Idx) const {
1524 assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")((Idx < getValueType(0).getVectorNumElements() && "Idx out of range!"
) ? static_cast<void> (0) : __assert_fail ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1524, __PRETTY_FUNCTION__))
;
1525 return Mask[Idx];
1526 }
1527
1528 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
1529
1530 int getSplatIndex() const {
1531 assert(isSplat() && "Cannot get splat index for non-splat!")((isSplat() && "Cannot get splat index for non-splat!"
) ? static_cast<void> (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1531, __PRETTY_FUNCTION__))
;
1532 EVT VT = getValueType(0);
1533 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
1534 if (Mask[i] >= 0)
1535 return Mask[i];
1536
1537 // We can choose any index value here and be correct because all elements
1538 // are undefined. Return 0 for better potential for callers to simplify.
1539 return 0;
1540 }
1541
1542 static bool isSplatMask(const int *Mask, EVT VT);
1543
1544 /// Change values in a shuffle permute mask assuming
1545 /// the two vector operands have swapped position.
1546 static void commuteMask(MutableArrayRef<int> Mask) {
1547 unsigned NumElems = Mask.size();
1548 for (unsigned i = 0; i != NumElems; ++i) {
1549 int idx = Mask[i];
1550 if (idx < 0)
1551 continue;
1552 else if (idx < (int)NumElems)
1553 Mask[i] = idx + NumElems;
1554 else
1555 Mask[i] = idx - NumElems;
1556 }
1557 }
1558
1559 static bool classof(const SDNode *N) {
1560 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
1561 }
1562};
1563
1564class ConstantSDNode : public SDNode {
1565 friend class SelectionDAG;
1566
1567 const ConstantInt *Value;
1568
1569 ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
1570 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
1571 getSDVTList(VT)),
1572 Value(val) {
1573 ConstantSDNodeBits.IsOpaque = isOpaque;
1574 }
1575
1576public:
1577 const ConstantInt *getConstantIntValue() const { return Value; }
1578 const APInt &getAPIntValue() const { return Value->getValue(); }
1579 uint64_t getZExtValue() const { return Value->getZExtValue(); }
1580 int64_t getSExtValue() const { return Value->getSExtValue(); }
1581 uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) {
1582 return Value->getLimitedValue(Limit);
1583 }
1584
1585 bool isOne() const { return Value->isOne(); }
1586 bool isNullValue() const { return Value->isZero(); }
1587 bool isAllOnesValue() const { return Value->isMinusOne(); }
1588
1589 bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }
1590
1591 static bool classof(const SDNode *N) {
1592 return N->getOpcode() == ISD::Constant ||
1593 N->getOpcode() == ISD::TargetConstant;
1594 }
1595};
1596
1597uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
1598 return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1599}
1600
1601const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
1602 return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
1603}
1604
1605class ConstantFPSDNode : public SDNode {
1606 friend class SelectionDAG;
1607
1608 const ConstantFP *Value;
1609
1610 ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
1611 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
1612 DebugLoc(), getSDVTList(VT)),
1613 Value(val) {}
1614
1615public:
1616 const APFloat& getValueAPF() const { return Value->getValueAPF(); }
1617 const ConstantFP *getConstantFPValue() const { return Value; }
1618
1619 /// Return true if the value is positive or negative zero.
1620 bool isZero() const { return Value->isZero(); }
1621
1622 /// Return true if the value is a NaN.
1623 bool isNaN() const { return Value->isNaN(); }
1624
1625 /// Return true if the value is an infinity
1626 bool isInfinity() const { return Value->isInfinity(); }
1627
1628 /// Return true if the value is negative.
1629 bool isNegative() const { return Value->isNegative(); }
1630
1631 /// We don't rely on operator== working on double values, as
1632 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
1633 /// As such, this method can be used to do an exact bit-for-bit comparison of
1634 /// two floating point values.
1635
1636 /// We leave the version with the double argument here because it's just so
1637 /// convenient to write "2.0" and the like. Without this function we'd
1638 /// have to duplicate its logic everywhere it's called.
1639 bool isExactlyValue(double V) const {
1640 return Value->getValueAPF().isExactlyValue(V);
1641 }
1642 bool isExactlyValue(const APFloat& V) const;
1643
1644 static bool isValueValidForType(EVT VT, const APFloat& Val);
1645
1646 static bool classof(const SDNode *N) {
1647 return N->getOpcode() == ISD::ConstantFP ||
1648 N->getOpcode() == ISD::TargetConstantFP;
1649 }
1650};
1651
1652/// Returns true if \p V is a constant integer zero.
1653bool isNullConstant(SDValue V);
1654
1655/// Returns true if \p V is an FP constant with a value of positive zero.
1656bool isNullFPConstant(SDValue V);
1657
1658/// Returns true if \p V is an integer constant with all bits set.
1659bool isAllOnesConstant(SDValue V);
1660
1661/// Returns true if \p V is a constant integer one.
1662bool isOneConstant(SDValue V);
1663
1664/// Return the non-bitcasted source operand of \p V if it exists.
1665/// If \p V is not a bitcasted value, it is returned as-is.
1666SDValue peekThroughBitcasts(SDValue V);
1667
1668/// Return the non-bitcasted and one-use source operand of \p V if it exists.
1669/// If \p V is not a bitcasted one-use value, it is returned as-is.
1670SDValue peekThroughOneUseBitcasts(SDValue V);
1671
1672/// Return the non-extracted vector source operand of \p V if it exists.
1673/// If \p V is not an extracted subvector, it is returned as-is.
1674SDValue peekThroughExtractSubvectors(SDValue V);
1675
1676/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1677/// constant is canonicalized to be operand 1.
1678bool isBitwiseNot(SDValue V, bool AllowUndefs = false);
1679
1680/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1681ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false,
1682 bool AllowTruncation = false);
1683
1684/// Returns the SDNode if it is a demanded constant splat BuildVector or
1685/// constant int.
1686ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
1687 bool AllowUndefs = false,
1688 bool AllowTruncation = false);
1689
1690/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1691ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false);
1692
1693/// Returns the SDNode if it is a demanded constant splat BuildVector or
1694/// constant float.
1695ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts,
1696 bool AllowUndefs = false);
1697
1698/// Return true if the value is a constant 0 integer or a splatted vector of
1699/// a constant 0 integer (with no undefs by default).
1700/// Build vector implicit truncation is not an issue for null values.
1701bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false);
1702
1703/// Return true if the value is a constant 1 integer or a splatted vector of a
1704/// constant 1 integer (with no undefs).
1705/// Does not permit build vector implicit truncation.
1706bool isOneOrOneSplat(SDValue V);
1707
1708/// Return true if the value is a constant -1 integer or a splatted vector of a
1709/// constant -1 integer (with no undefs).
1710/// Does not permit build vector implicit truncation.
1711bool isAllOnesOrAllOnesSplat(SDValue V);
1712
1713class GlobalAddressSDNode : public SDNode {
1714 friend class SelectionDAG;
1715
1716 const GlobalValue *TheGlobal;
1717 int64_t Offset;
1718 unsigned TargetFlags;
1719
1720 GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
1721 const GlobalValue *GA, EVT VT, int64_t o,
1722 unsigned TF);
1723
1724public:
1725 const GlobalValue *getGlobal() const { return TheGlobal; }
1726 int64_t getOffset() const { return Offset; }
1727 unsigned getTargetFlags() const { return TargetFlags; }
1728 // Return the address space this GlobalAddress belongs to.
1729 unsigned getAddressSpace() const;
1730
1731 static bool classof(const SDNode *N) {
1732 return N->getOpcode() == ISD::GlobalAddress ||
1733 N->getOpcode() == ISD::TargetGlobalAddress ||
1734 N->getOpcode() == ISD::GlobalTLSAddress ||
1735 N->getOpcode() == ISD::TargetGlobalTLSAddress;
1736 }
1737};
1738
1739class FrameIndexSDNode : public SDNode {
1740 friend class SelectionDAG;
1741
1742 int FI;
1743
1744 FrameIndexSDNode(int fi, EVT VT, bool isTarg)
1745 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1746 0, DebugLoc(), getSDVTList(VT)), FI(fi) {
1747 }
1748
1749public:
1750 int getIndex() const { return FI; }
1751
1752 static bool classof(const SDNode *N) {
1753 return N->getOpcode() == ISD::FrameIndex ||
1754 N->getOpcode() == ISD::TargetFrameIndex;
1755 }
1756};
1757
1758/// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate
1759/// the offet and size that are started/ended in the underlying FrameIndex.
1760class LifetimeSDNode : public SDNode {
1761 friend class SelectionDAG;
1762 int64_t Size;
1763 int64_t Offset; // -1 if offset is unknown.
1764
1765 LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
1766 SDVTList VTs, int64_t Size, int64_t Offset)
1767 : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {}
1768public:
1769 int64_t getFrameIndex() const {
1770 return cast<FrameIndexSDNode>(getOperand(1))->getIndex();
1771 }
1772
1773 bool hasOffset() const { return Offset >= 0; }
1774 int64_t getOffset() const {
1775 assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1775, __PRETTY_FUNCTION__))
;
1776 return Offset;
1777 }
1778 int64_t getSize() const {
1779 assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1779, __PRETTY_FUNCTION__))
;
1780 return Size;
1781 }
1782
1783 // Methods to support isa and dyn_cast
1784 static bool classof(const SDNode *N) {
1785 return N->getOpcode() == ISD::LIFETIME_START ||
1786 N->getOpcode() == ISD::LIFETIME_END;
1787 }
1788};
1789
1790class JumpTableSDNode : public SDNode {
1791 friend class SelectionDAG;
1792
1793 int JTI;
1794 unsigned TargetFlags;
1795
1796 JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF)
1797 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
1798 0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
1799 }
1800
1801public:
1802 int getIndex() const { return JTI; }
1803 unsigned getTargetFlags() const { return TargetFlags; }
1804
1805 static bool classof(const SDNode *N) {
1806 return N->getOpcode() == ISD::JumpTable ||
1807 N->getOpcode() == ISD::TargetJumpTable;
1808 }
1809};
1810
1811class ConstantPoolSDNode : public SDNode {
1812 friend class SelectionDAG;
1813
1814 union {
1815 const Constant *ConstVal;
1816 MachineConstantPoolValue *MachineCPVal;
1817 } Val;
1818 int Offset; // It's a MachineConstantPoolValue if top bit is set.
1819 unsigned Alignment; // Minimum alignment requirement of CP (not log2 value).
1820 unsigned TargetFlags;
1821
1822 ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
1823 unsigned Align, unsigned TF)
1824 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1825 DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
1826 TargetFlags(TF) {
1827 assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1827, __PRETTY_FUNCTION__))
;
1828 Val.ConstVal = c;
1829 }
1830
1831 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
1832 EVT VT, int o, unsigned Align, unsigned TF)
1833 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1834 DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
1835 TargetFlags(TF) {
1836 assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1836, __PRETTY_FUNCTION__))
;
1837 Val.MachineCPVal = v;
1838 Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
1839 }
1840
1841public:
1842 bool isMachineConstantPoolEntry() const {
1843 return Offset < 0;
1844 }
1845
1846 const Constant *getConstVal() const {
1847 assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")((!isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1847, __PRETTY_FUNCTION__))
;
1848 return Val.ConstVal;
1849 }
1850
1851 MachineConstantPoolValue *getMachineCPVal() const {
1852 assert(isMachineConstantPoolEntry() && "Wrong constantpool type")((isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1852, __PRETTY_FUNCTION__))
;
1853 return Val.MachineCPVal;
1854 }
1855
1856 int getOffset() const {
1857 return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
1858 }
1859
1860 // Return the alignment of this constant pool object, which is either 0 (for
1861 // default alignment) or the desired value.
1862 unsigned getAlignment() const { return Alignment; }
1863 unsigned getTargetFlags() const { return TargetFlags; }
1864
1865 Type *getType() const;
1866
1867 static bool classof(const SDNode *N) {
1868 return N->getOpcode() == ISD::ConstantPool ||
1869 N->getOpcode() == ISD::TargetConstantPool;
1870 }
1871};
1872
1873/// Completely target-dependent object reference.
1874class TargetIndexSDNode : public SDNode {
1875 friend class SelectionDAG;
1876
1877 unsigned TargetFlags;
1878 int Index;
1879 int64_t Offset;
1880
1881public:
1882 TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF)
1883 : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
1884 TargetFlags(TF), Index(Idx), Offset(Ofs) {}
1885
1886 unsigned getTargetFlags() const { return TargetFlags; }
1887 int getIndex() const { return Index; }
1888 int64_t getOffset() const { return Offset; }
1889
1890 static bool classof(const SDNode *N) {
1891 return N->getOpcode() == ISD::TargetIndex;
1892 }
1893};
1894
1895class BasicBlockSDNode : public SDNode {
1896 friend class SelectionDAG;
1897
1898 MachineBasicBlock *MBB;
1899
1900 /// Debug info is meaningful and potentially useful here, but we create
1901 /// blocks out of order when they're jumped to, which makes it a bit
1902 /// harder. Let's see if we need it first.
1903 explicit BasicBlockSDNode(MachineBasicBlock *mbb)
1904 : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
1905 {}
1906
1907public:
1908 MachineBasicBlock *getBasicBlock() const { return MBB; }
1909
1910 static bool classof(const SDNode *N) {
1911 return N->getOpcode() == ISD::BasicBlock;
1912 }
1913};
1914
1915/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1916class BuildVectorSDNode : public SDNode {
1917public:
1918 // These are constructed as SDNodes and then cast to BuildVectorSDNodes.
1919 explicit BuildVectorSDNode() = delete;
1920
1921 /// Check if this is a constant splat, and if so, find the
1922 /// smallest element size that splats the vector. If MinSplatBits is
1923 /// nonzero, the element size must be at least that large. Note that the
1924 /// splat element may be the entire vector (i.e., a one element vector).
1925 /// Returns the splat element value in SplatValue. Any undefined bits in
1926 /// that value are zero, and the corresponding bits in the SplatUndef mask
1927 /// are set. The SplatBitSize value is set to the splat element size in
1928 /// bits. HasAnyUndefs is set to true if any bits in the vector are
1929 /// undefined. isBigEndian describes the endianness of the target.
1930 bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
1931 unsigned &SplatBitSize, bool &HasAnyUndefs,
1932 unsigned MinSplatBits = 0,
1933 bool isBigEndian = false) const;
1934
1935 /// Returns the demanded splatted value or a null value if this is not a
1936 /// splat.
1937 ///
1938 /// The DemandedElts mask indicates the elements that must be in the splat.
1939 /// If passed a non-null UndefElements bitvector, it will resize it to match
1940 /// the vector width and set the bits where elements are undef.
1941 SDValue getSplatValue(const APInt &DemandedElts,
1942 BitVector *UndefElements = nullptr) const;
1943
1944 /// Returns the splatted value or a null value if this is not a splat.
1945 ///
1946 /// If passed a non-null UndefElements bitvector, it will resize it to match
1947 /// the vector width and set the bits where elements are undef.
1948 SDValue getSplatValue(BitVector *UndefElements = nullptr) const;
1949
1950 /// Returns the demanded splatted constant or null if this is not a constant
1951 /// splat.
1952 ///
1953 /// The DemandedElts mask indicates the elements that must be in the splat.
1954 /// If passed a non-null UndefElements bitvector, it will resize it to match
1955 /// the vector width and set the bits where elements are undef.
1956 ConstantSDNode *
1957 getConstantSplatNode(const APInt &DemandedElts,
1958 BitVector *UndefElements = nullptr) const;
1959
1960 /// Returns the splatted constant or null if this is not a constant
1961 /// splat.
1962 ///
1963 /// If passed a non-null UndefElements bitvector, it will resize it to match
1964 /// the vector width and set the bits where elements are undef.
1965 ConstantSDNode *
1966 getConstantSplatNode(BitVector *UndefElements = nullptr) const;
1967
1968 /// Returns the demanded splatted constant FP or null if this is not a
1969 /// constant FP splat.
1970 ///
1971 /// The DemandedElts mask indicates the elements that must be in the splat.
1972 /// If passed a non-null UndefElements bitvector, it will resize it to match
1973 /// the vector width and set the bits where elements are undef.
1974 ConstantFPSDNode *
1975 getConstantFPSplatNode(const APInt &DemandedElts,
1976 BitVector *UndefElements = nullptr) const;
1977
1978 /// Returns the splatted constant FP or null if this is not a constant
1979 /// FP splat.
1980 ///
1981 /// If passed a non-null UndefElements bitvector, it will resize it to match
1982 /// the vector width and set the bits where elements are undef.
1983 ConstantFPSDNode *
1984 getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;
1985
1986 /// If this is a constant FP splat and the splatted constant FP is an
1987 /// exact power or 2, return the log base 2 integer value. Otherwise,
1988 /// return -1.
1989 ///
1990 /// The BitWidth specifies the necessary bit precision.
1991 int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
1992 uint32_t BitWidth) const;
1993
1994 bool isConstant() const;
1995
1996 static bool classof(const SDNode *N) {
1997 return N->getOpcode() == ISD::BUILD_VECTOR;
1998 }
1999};
2000
2001/// An SDNode that holds an arbitrary LLVM IR Value. This is
2002/// used when the SelectionDAG needs to make a simple reference to something
2003/// in the LLVM IR representation.
2004///
2005class SrcValueSDNode : public SDNode {
2006 friend class SelectionDAG;
2007
2008 const Value *V;
2009
2010 /// Create a SrcValue for a general value.
2011 explicit SrcValueSDNode(const Value *v)
2012 : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}
2013
2014public:
2015 /// Return the contained Value.
2016 const Value *getValue() const { return V; }
2017
2018 static bool classof(const SDNode *N) {
2019 return N->getOpcode() == ISD::SRCVALUE;
2020 }
2021};
2022
2023class MDNodeSDNode : public SDNode {
2024 friend class SelectionDAG;
2025
2026 const MDNode *MD;
2027
2028 explicit MDNodeSDNode(const MDNode *md)
2029 : SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
2030 {}
2031
2032public:
2033 const MDNode *getMD() const { return MD; }
2034
2035 static bool classof(const SDNode *N) {
2036 return N->getOpcode() == ISD::MDNODE_SDNODE;
2037 }
2038};
2039
2040class RegisterSDNode : public SDNode {
2041 friend class SelectionDAG;
2042
2043 unsigned Reg;
2044
2045 RegisterSDNode(unsigned reg, EVT VT)
2046 : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}
2047
2048public:
2049 unsigned getReg() const { return Reg; }
2050
2051 static bool classof(const SDNode *N) {
2052 return N->getOpcode() == ISD::Register;
2053 }
2054};
2055
2056class RegisterMaskSDNode : public SDNode {
2057 friend class SelectionDAG;
2058
2059 // The memory for RegMask is not owned by the node.
2060 const uint32_t *RegMask;
2061
2062 RegisterMaskSDNode(const uint32_t *mask)
2063 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
2064 RegMask(mask) {}
2065
2066public:
2067 const uint32_t *getRegMask() const { return RegMask; }
2068
2069 static bool classof(const SDNode *N) {
2070 return N->getOpcode() == ISD::RegisterMask;
2071 }
2072};
2073
2074class BlockAddressSDNode : public SDNode {
2075 friend class SelectionDAG;
2076
2077 const BlockAddress *BA;
2078 int64_t Offset;
2079 unsigned TargetFlags;
2080
2081 BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
2082 int64_t o, unsigned Flags)
2083 : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
2084 BA(ba), Offset(o), TargetFlags(Flags) {}
2085
2086public:
2087 const BlockAddress *getBlockAddress() const { return BA; }
2088 int64_t getOffset() const { return Offset; }
2089 unsigned getTargetFlags() const { return TargetFlags; }
2090
2091 static bool classof(const SDNode *N) {
2092 return N->getOpcode() == ISD::BlockAddress ||
2093 N->getOpcode() == ISD::TargetBlockAddress;
2094 }
2095};
2096
2097class LabelSDNode : public SDNode {
2098 friend class SelectionDAG;
2099
2100 MCSymbol *Label;
2101
2102 LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L)
2103 : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) {
2104 assert(LabelSDNode::classof(this) && "not a label opcode")((LabelSDNode::classof(this) && "not a label opcode")
? static_cast<void> (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2104, __PRETTY_FUNCTION__))
;
2105 }
2106
2107public:
2108 MCSymbol *getLabel() const { return Label; }
2109
2110 static bool classof(const SDNode *N) {
2111 return N->getOpcode() == ISD::EH_LABEL ||
2112 N->getOpcode() == ISD::ANNOTATION_LABEL;
2113 }
2114};
2115
2116class ExternalSymbolSDNode : public SDNode {
2117 friend class SelectionDAG;
2118
2119 const char *Symbol;
2120 unsigned TargetFlags;
2121
2122 ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT)
2123 : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0,
2124 DebugLoc(), getSDVTList(VT)),
2125 Symbol(Sym), TargetFlags(TF) {}
2126
2127public:
2128 const char *getSymbol() const { return Symbol; }
2129 unsigned getTargetFlags() const { return TargetFlags; }
2130
2131 static bool classof(const SDNode *N) {
2132 return N->getOpcode() == ISD::ExternalSymbol ||
2133 N->getOpcode() == ISD::TargetExternalSymbol;
2134 }
2135};
2136
2137class MCSymbolSDNode : public SDNode {
2138 friend class SelectionDAG;
2139
2140 MCSymbol *Symbol;
2141
2142 MCSymbolSDNode(MCSymbol *Symbol, EVT VT)
2143 : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {}
2144
2145public:
2146 MCSymbol *getMCSymbol() const { return Symbol; }
2147
2148 static bool classof(const SDNode *N) {
2149 return N->getOpcode() == ISD::MCSymbol;
2150 }
2151};
2152
2153class CondCodeSDNode : public SDNode {
2154 friend class SelectionDAG;
2155
2156 ISD::CondCode Condition;
2157
2158 explicit CondCodeSDNode(ISD::CondCode Cond)
2159 : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2160 Condition(Cond) {}
2161
2162public:
2163 ISD::CondCode get() const { return Condition; }
2164
2165 static bool classof(const SDNode *N) {
2166 return N->getOpcode() == ISD::CONDCODE;
2167 }
2168};
2169
2170/// This class is used to represent EVT's, which are used
2171/// to parameterize some operations.
2172class VTSDNode : public SDNode {
2173 friend class SelectionDAG;
2174
2175 EVT ValueType;
2176
2177 explicit VTSDNode(EVT VT)
2178 : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2179 ValueType(VT) {}
2180
2181public:
2182 EVT getVT() const { return ValueType; }
2183
2184 static bool classof(const SDNode *N) {
2185 return N->getOpcode() == ISD::VALUETYPE;
2186 }
2187};
2188
2189/// Base class for LoadSDNode and StoreSDNode
2190class LSBaseSDNode : public MemSDNode {
2191public:
2192 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
2193 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2194 MachineMemOperand *MMO)
2195 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2196 LSBaseSDNodeBits.AddressingMode = AM;
2197 assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2197, __PRETTY_FUNCTION__))
;
2198 }
2199
2200 const SDValue &getOffset() const {
2201 return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
2202 }
2203
2204 /// Return the addressing mode for this load or store:
2205 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2206 ISD::MemIndexedMode getAddressingMode() const {
2207 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2208 }
2209
2210 /// Return true if this is a pre/post inc/dec load/store.
2211 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2212
2213 /// Return true if this is NOT a pre/post inc/dec load/store.
2214 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2215
2216 static bool classof(const SDNode *N) {
2217 return N->getOpcode() == ISD::LOAD ||
2218 N->getOpcode() == ISD::STORE;
2219 }
2220};
2221
2222/// This class is used to represent ISD::LOAD nodes.
2223class LoadSDNode : public LSBaseSDNode {
2224 friend class SelectionDAG;
2225
2226 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2227 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2228 MachineMemOperand *MMO)
2229 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2230 LoadSDNodeBits.ExtTy = ETy;
2231 assert(readMem() && "Load MachineMemOperand is not a load!")((readMem() && "Load MachineMemOperand is not a load!"
) ? static_cast<void> (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2231, __PRETTY_FUNCTION__))
;
2232 assert(!writeMem() && "Load MachineMemOperand is a store!")((!writeMem() && "Load MachineMemOperand is a store!"
) ? static_cast<void> (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2232, __PRETTY_FUNCTION__))
;
2233 }
2234
2235public:
2236 /// Return whether this is a plain node,
2237 /// or one of the varieties of value-extending loads.
2238 ISD::LoadExtType getExtensionType() const {
2239 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2240 }
2241
2242 const SDValue &getBasePtr() const { return getOperand(1); }
2243 const SDValue &getOffset() const { return getOperand(2); }
2244
2245 static bool classof(const SDNode *N) {
2246 return N->getOpcode() == ISD::LOAD;
2247 }
2248};
2249
2250/// This class is used to represent ISD::STORE nodes.
2251class StoreSDNode : public LSBaseSDNode {
2252 friend class SelectionDAG;
2253
2254 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2255 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2256 MachineMemOperand *MMO)
2257 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2258 StoreSDNodeBits.IsTruncating = isTrunc;
2259 assert(!readMem() && "Store MachineMemOperand is a load!")((!readMem() && "Store MachineMemOperand is a load!")
? static_cast<void> (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2259, __PRETTY_FUNCTION__))
;
2260 assert(writeMem() && "Store MachineMemOperand is not a store!")((writeMem() && "Store MachineMemOperand is not a store!"
) ? static_cast<void> (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2260, __PRETTY_FUNCTION__))
;
2261 }
2262
2263public:
2264 /// Return true if the op does a truncation before store.
2265 /// For integers this is the same as doing a TRUNCATE and storing the result.
2266 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2267 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2268 void setTruncatingStore(bool Truncating) {
2269 StoreSDNodeBits.IsTruncating = Truncating;
2270 }
2271
2272 const SDValue &getValue() const { return getOperand(1); }
2273 const SDValue &getBasePtr() const { return getOperand(2); }
2274 const SDValue &getOffset() const { return getOperand(3); }
2275
2276 static bool classof(const SDNode *N) {
2277 return N->getOpcode() == ISD::STORE;
2278 }
2279};
2280
2281/// This base class is used to represent MLOAD and MSTORE nodes
2282class MaskedLoadStoreSDNode : public MemSDNode {
2283public:
2284 friend class SelectionDAG;
2285
2286 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
2287 const DebugLoc &dl, SDVTList VTs,
2288 ISD::MemIndexedMode AM, EVT MemVT,
2289 MachineMemOperand *MMO)
2290 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2291 LSBaseSDNodeBits.AddressingMode = AM;
2292 assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2292, __PRETTY_FUNCTION__))
;
2293 }
2294
2295 // MaskedLoadSDNode (Chain, ptr, offset, mask, passthru)
2296 // MaskedStoreSDNode (Chain, data, ptr, offset, mask)
2297 // Mask is a vector of i1 elements
2298 const SDValue &getBasePtr() const {
2299 return getOperand(getOpcode() == ISD::MLOAD ? 1 : 2);
2300 }
2301 const SDValue &getOffset() const {
2302 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2303 }
2304 const SDValue &getMask() const {
2305 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2306 }
2307
2308 /// Return the addressing mode for this load or store:
2309 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2310 ISD::MemIndexedMode getAddressingMode() const {
2311 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2312 }
2313
2314 /// Return true if this is a pre/post inc/dec load/store.
2315 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2316
2317 /// Return true if this is NOT a pre/post inc/dec load/store.
2318 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2319
2320 static bool classof(const SDNode *N) {
2321 return N->getOpcode() == ISD::MLOAD ||
2322 N->getOpcode() == ISD::MSTORE;
2323 }
2324};
2325
2326/// This class is used to represent an MLOAD node
2327class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
2328public:
2329 friend class SelectionDAG;
2330
2331 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2332 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
2333 bool IsExpanding, EVT MemVT, MachineMemOperand *MMO)
2334 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2335 LoadSDNodeBits.ExtTy = ETy;
2336 LoadSDNodeBits.IsExpanding = IsExpanding;
2337 }
2338
2339 ISD::LoadExtType getExtensionType() const {
2340 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2341 }
2342
2343 const SDValue &getBasePtr() const { return getOperand(1); }
2344 const SDValue &getOffset() const { return getOperand(2); }
2345 const SDValue &getMask() const { return getOperand(3); }
2346 const SDValue &getPassThru() const { return getOperand(4); }
2347
2348 static bool classof(const SDNode *N) {
2349 return N->getOpcode() == ISD::MLOAD;
2350 }
2351
2352 bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2353};
2354
2355/// This class is used to represent an MSTORE node
2356class MaskedStoreSDNode : public MaskedLoadStoreSDNode {
2357public:
2358 friend class SelectionDAG;
2359
2360 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2361 ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing,
2362 EVT MemVT, MachineMemOperand *MMO)
2363 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
2364 StoreSDNodeBits.IsTruncating = isTrunc;
2365 StoreSDNodeBits.IsCompressing = isCompressing;
2366 }
2367
2368 /// Return true if the op does a truncation before store.
2369 /// For integers this is the same as doing a TRUNCATE and storing the result.
2370 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2371 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2372
2373 /// Returns true if the op does a compression to the vector before storing.
2374 /// The node contiguously stores the active elements (integers or floats)
2375 /// in src (those with their respective bit set in writemask k) to unaligned
2376 /// memory at base_addr.
2377 bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }
2378
2379 const SDValue &getValue() const { return getOperand(1); }
2380 const SDValue &getBasePtr() const { return getOperand(2); }
2381 const SDValue &getOffset() const { return getOperand(3); }
2382 const SDValue &getMask() const { return getOperand(4); }
2383
2384 static bool classof(const SDNode *N) {
2385 return N->getOpcode() == ISD::MSTORE;
2386 }
2387};
2388
2389/// This is a base class used to represent
2390/// MGATHER and MSCATTER nodes
2391///
2392class MaskedGatherScatterSDNode : public MemSDNode {
2393public:
2394 friend class SelectionDAG;
2395
2396 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
2397 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2398 MachineMemOperand *MMO, ISD::MemIndexType IndexType)
2399 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2400 LSBaseSDNodeBits.AddressingMode = IndexType;
2401 assert(getIndexType() == IndexType && "Value truncated")((getIndexType() == IndexType && "Value truncated") ?
static_cast<void> (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2401, __PRETTY_FUNCTION__))
;
2402 }
2403
2404 /// How is Index applied to BasePtr when computing addresses.
2405 ISD::MemIndexType getIndexType() const {
2406 return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);
2407 }
2408 bool isIndexScaled() const {
2409 return (getIndexType() == ISD::SIGNED_SCALED) ||
2410 (getIndexType() == ISD::UNSIGNED_SCALED);
2411 }
2412 bool isIndexSigned() const {
2413 return (getIndexType() == ISD::SIGNED_SCALED) ||
2414 (getIndexType() == ISD::SIGNED_UNSCALED);
2415 }
2416
2417 // In the both nodes address is Op1, mask is Op2:
2418 // MaskedGatherSDNode (Chain, passthru, mask, base, index, scale)
2419 // MaskedScatterSDNode (Chain, value, mask, base, index, scale)
2420 // Mask is a vector of i1 elements
2421 const SDValue &getBasePtr() const { return getOperand(3); }
2422 const SDValue &getIndex() const { return getOperand(4); }
2423 const SDValue &getMask() const { return getOperand(2); }
2424 const SDValue &getScale() const { return getOperand(5); }
2425
2426 static bool classof(const SDNode *N) {
2427 return N->getOpcode() == ISD::MGATHER ||
2428 N->getOpcode() == ISD::MSCATTER;
2429 }
2430};
2431
2432/// This class is used to represent an MGATHER node
2433///
2434class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
2435public:
2436 friend class SelectionDAG;
2437
2438 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2439 EVT MemVT, MachineMemOperand *MMO,
2440 ISD::MemIndexType IndexType)
2441 : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
2442 IndexType) {}
2443
2444 const SDValue &getPassThru() const { return getOperand(1); }
2445
2446 static bool classof(const SDNode *N) {
2447 return N->getOpcode() == ISD::MGATHER;
2448 }
2449};
2450
2451/// This class is used to represent an MSCATTER node
2452///
2453class MaskedScatterSDNode : public MaskedGatherScatterSDNode {
2454public:
2455 friend class SelectionDAG;
2456
2457 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2458 EVT MemVT, MachineMemOperand *MMO,
2459 ISD::MemIndexType IndexType)
2460 : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO,
2461 IndexType) {}
2462
2463 const SDValue &getValue() const { return getOperand(1); }
2464
2465 static bool classof(const SDNode *N) {
2466 return N->getOpcode() == ISD::MSCATTER;
2467 }
2468};
2469
2470/// An SDNode that represents everything that will be needed
2471/// to construct a MachineInstr. These nodes are created during the
2472/// instruction selection proper phase.
2473///
2474/// Note that the only supported way to set the `memoperands` is by calling the
2475/// `SelectionDAG::setNodeMemRefs` function as the memory management happens
2476/// inside the DAG rather than in the node.
2477class MachineSDNode : public SDNode {
2478private:
2479 friend class SelectionDAG;
2480
2481 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
2482 : SDNode(Opc, Order, DL, VTs) {}
2483
2484 // We use a pointer union between a single `MachineMemOperand` pointer and
2485 // a pointer to an array of `MachineMemOperand` pointers. This is null when
2486 // the number of these is zero, the single pointer variant used when the
2487 // number is one, and the array is used for larger numbers.
2488 //
2489 // The array is allocated via the `SelectionDAG`'s allocator and so will
2490 // always live until the DAG is cleaned up and doesn't require ownership here.
2491 //
2492 // We can't use something simpler like `TinyPtrVector` here because `SDNode`
2493 // subclasses aren't managed in a conforming C++ manner. See the comments on
2494 // `SelectionDAG::MorphNodeTo` which details what all goes on, but the
2495 // constraint here is that these don't manage memory with their constructor or
2496 // destructor and can be initialized to a good state even if they start off
2497 // uninitialized.
2498 PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {};
2499
2500 // Note that this could be folded into the above `MemRefs` member if doing so
2501 // is advantageous at some point. We don't need to store this in most cases.
2502 // However, at the moment this doesn't appear to make the allocation any
2503 // smaller and makes the code somewhat simpler to read.
2504 int NumMemRefs = 0;
2505
2506public:
2507 using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator;
2508
2509 ArrayRef<MachineMemOperand *> memoperands() const {
2510 // Special case the common cases.
2511 if (NumMemRefs == 0)
2512 return {};
2513 if (NumMemRefs == 1)
2514 return makeArrayRef(MemRefs.getAddrOfPtr1(), 1);
2515
2516 // Otherwise we have an actual array.
2517 return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs);
2518 }
2519 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
2520 mmo_iterator memoperands_end() const { return memoperands().end(); }
2521 bool memoperands_empty() const { return memoperands().empty(); }
2522
2523 /// Clear out the memory reference descriptor list.
2524 void clearMemRefs() {
2525 MemRefs = nullptr;
2526 NumMemRefs = 0;
2527 }
2528
2529 static bool classof(const SDNode *N) {
2530 return N->isMachineOpcode();
2531 }
2532};
2533
2534class SDNodeIterator : public std::iterator<std::forward_iterator_tag,
2535 SDNode, ptrdiff_t> {
2536 const SDNode *Node;
2537 unsigned Operand;
2538
2539 SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}
2540
2541public:
2542 bool operator==(const SDNodeIterator& x) const {
2543 return Operand == x.Operand;
2544 }
2545 bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }
2546
2547 pointer operator*() const {
2548 return Node->getOperand(Operand).getNode();
2549 }
2550 pointer operator->() const { return operator*(); }
2551
2552 SDNodeIterator& operator++() { // Preincrement
2553 ++Operand;
2554 return *this;
2555 }
2556 SDNodeIterator