Bug Summary

File:lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
Warning:line 183, column 3
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name HexagonMCInstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/Hexagon/MCTargetDesc -I /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc -I /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn350071/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/Target/Hexagon/MCTargetDesc -fdebug-prefix-map=/build/llvm-toolchain-snapshot-8~svn350071=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-12-27-042839-1215-1 -x c++ /build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp -faddrsig
1//===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/HexagonMCInstrInfo.h"
15#include "Hexagon.h"
16#include "MCTargetDesc/HexagonBaseInfo.h"
17#include "MCTargetDesc/HexagonMCChecker.h"
18#include "MCTargetDesc/HexagonMCExpr.h"
19#include "MCTargetDesc/HexagonMCShuffler.h"
20#include "MCTargetDesc/HexagonMCTargetDesc.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCExpr.h"
24#include "llvm/MC/MCInst.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCInstrItineraries.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/Support/Casting.h"
29#include "llvm/Support/ErrorHandling.h"
30#include <cassert>
31#include <cstdint>
32#include <limits>
33
34using namespace llvm;
35
36bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const {
37 return Register != Hexagon::NoRegister;
38}
39
40Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
41 MCInst const &Inst)
42 : MCII(MCII), BundleCurrent(Inst.begin() +
43 HexagonMCInstrInfo::bundleInstructionsOffset),
44 BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
45
46Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
47 MCInst const &Inst, std::nullptr_t)
48 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
49 DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
50
51Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
52 if (DuplexCurrent != DuplexEnd) {
53 ++DuplexCurrent;
54 if (DuplexCurrent == DuplexEnd) {
55 DuplexCurrent = BundleEnd;
56 DuplexEnd = BundleEnd;
57 ++BundleCurrent;
58 }
59 return *this;
60 }
61 ++BundleCurrent;
62 if (BundleCurrent != BundleEnd) {
63 MCInst const &Inst = *BundleCurrent->getInst();
64 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
65 DuplexCurrent = Inst.begin();
66 DuplexEnd = Inst.end();
67 }
68 }
69 return *this;
70}
71
72MCInst const &Hexagon::PacketIterator::operator*() const {
73 if (DuplexCurrent != DuplexEnd)
74 return *DuplexCurrent->getInst();
75 return *BundleCurrent->getInst();
76}
77
78bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const {
79 return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
80 DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
81}
82
83void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
84 MCContext &Context) {
85 MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
86}
87
88void HexagonMCInstrInfo::addConstExtender(MCContext &Context,
89 MCInstrInfo const &MCII, MCInst &MCB,
90 MCInst const &MCI) {
91 assert(HexagonMCInstrInfo::isBundle(MCB))((HexagonMCInstrInfo::isBundle(MCB)) ? static_cast<void>
(0) : __assert_fail ("HexagonMCInstrInfo::isBundle(MCB)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 91, __PRETTY_FUNCTION__));
92 MCOperand const &exOp =
93 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
94
95 // Create the extender.
96 MCInst *XMCI =
97 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
98 XMCI->setLoc(MCI.getLoc());
99
100 MCB.addOperand(MCOperand::createInst(XMCI));
101}
102
103iterator_range<Hexagon::PacketIterator>
104HexagonMCInstrInfo::bundleInstructions(MCInstrInfo const &MCII,
105 MCInst const &MCI) {
106 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 106, __PRETTY_FUNCTION__));
107 return make_range(Hexagon::PacketIterator(MCII, MCI),
108 Hexagon::PacketIterator(MCII, MCI, nullptr));
109}
110
111iterator_range<MCInst::const_iterator>
112HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
113 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 113, __PRETTY_FUNCTION__));
114 return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
115}
116
117size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
118 if (HexagonMCInstrInfo::isBundle(MCI))
119 return (MCI.size() - bundleInstructionsOffset);
120 else
121 return (1);
122}
123
124bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
125 MCSubtargetInfo const &STI,
126 MCContext &Context, MCInst &MCB,
127 HexagonMCChecker *Check) {
128 // Check the bundle for errors.
129 bool CheckOk = Check ? Check->check(false) : true;
130 if (!CheckOk)
131 return false;
132 // Examine the packet and convert pairs of instructions to compound
133 // instructions when possible.
134 if (!HexagonDisableCompound)
135 HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
136 HexagonMCShuffle(Context, false, MCII, STI, MCB);
137 // Examine the packet and convert pairs of instructions to duplex
138 // instructions when possible.
139 MCInst InstBundlePreDuplex = MCInst(MCB);
140 if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) {
141 SmallVector<DuplexCandidate, 8> possibleDuplexes;
142 possibleDuplexes =
143 HexagonMCInstrInfo::getDuplexPossibilties(MCII, STI, MCB);
144 HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
145 }
146 // Examines packet and pad the packet, if needed, when an
147 // end-loop is in the bundle.
148 HexagonMCInstrInfo::padEndloop(MCB, Context);
149 // If compounding and duplexing didn't reduce the size below
150 // 4 or less we have a packet that is too big.
151 if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE4)
152 return false;
153 // Check the bundle for errors.
154 CheckOk = Check ? Check->check(true) : true;
155 if (!CheckOk)
156 return false;
157 HexagonMCShuffle(Context, true, MCII, STI, MCB);
158 return true;
159}
160
161MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
162 MCInst const &Inst,
163 MCOperand const &MO) {
164 assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||((HexagonMCInstrInfo::isExtendable(MCII, Inst) || HexagonMCInstrInfo
::isExtended(MCII, Inst)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, Inst) || HexagonMCInstrInfo::isExtended(MCII, Inst)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 165, __PRETTY_FUNCTION__))
165 HexagonMCInstrInfo::isExtended(MCII, Inst))((HexagonMCInstrInfo::isExtendable(MCII, Inst) || HexagonMCInstrInfo
::isExtended(MCII, Inst)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, Inst) || HexagonMCInstrInfo::isExtended(MCII, Inst)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 165, __PRETTY_FUNCTION__));
166
167 MCInst XMI;
168 XMI.setOpcode(Hexagon::A4_ext);
169 if (MO.isImm())
170 XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
171 else if (MO.isExpr())
172 XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
173 else
174 llvm_unreachable("invalid extendable operand")::llvm::llvm_unreachable_internal("invalid extendable operand"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 174);
175 return XMI;
176}
177
178MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
179 MCInst const &inst0,
180 MCInst const &inst1) {
181 assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf")(((iClass <= 0xf) && "iClass must have range of 0 to 0xf"
) ? static_cast<void> (0) : __assert_fail ("(iClass <= 0xf) && \"iClass must have range of 0 to 0xf\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 181, __PRETTY_FUNCTION__));
7
←
Assuming 'iClass' is <= 15
→
8
←
'?' condition is true
→
182 MCInst *duplexInst = new (Context) MCInst;
9
←
'duplexInst' initialized to a null pointer value
→
183 duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
10
←
Called C++ object pointer is null
184
185 MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
186 MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
187 duplexInst->addOperand(MCOperand::createInst(SubInst0));
188 duplexInst->addOperand(MCOperand::createInst(SubInst1));
189 return duplexInst;
190}
191
192MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
193 size_t Index) {
194 assert(Index <= bundleSize(MCB))((Index <= bundleSize(MCB)) ? static_cast<void> (0) :
__assert_fail ("Index <= bundleSize(MCB)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 194, __PRETTY_FUNCTION__));
195 if (Index == 0)
196 return nullptr;
197 MCInst const *Inst =
198 MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
199 if (isImmext(*Inst))
200 return Inst;
201 return nullptr;
202}
203
204void HexagonMCInstrInfo::extendIfNeeded(MCContext &Context,
205 MCInstrInfo const &MCII, MCInst &MCB,
206 MCInst const &MCI) {
207 if (isConstExtended(MCII, MCI))
208 addConstExtender(Context, MCII, MCB, MCI);
209}
210
211unsigned HexagonMCInstrInfo::getMemAccessSize(MCInstrInfo const &MCII,
212 MCInst const &MCI) {
213 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
214 unsigned S = (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
215 return HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(S));
216}
217
218unsigned HexagonMCInstrInfo::getAddrMode(MCInstrInfo const &MCII,
219 MCInst const &MCI) {
220 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
221 return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
222 HexagonII::AddrModeMask);
223}
224
225MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
226 MCInst const &MCI) {
227 return MCII.get(MCI.getOpcode());
228}
229
230unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(unsigned Reg) {
231 using namespace Hexagon;
232
233 switch (Reg) {
234 default:
235 llvm_unreachable("unknown duplex register")::llvm::llvm_unreachable_internal("unknown duplex register", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 235);
236 // Rs Rss
237 case R0:
238 case D0:
239 return 0;
240 case R1:
241 case D1:
242 return 1;
243 case R2:
244 case D2:
245 return 2;
246 case R3:
247 case D3:
248 return 3;
249 case R4:
250 case D8:
251 return 4;
252 case R5:
253 case D9:
254 return 5;
255 case R6:
256 case D10:
257 return 6;
258 case R7:
259 case D11:
260 return 7;
261 case R16:
262 return 8;
263 case R17:
264 return 9;
265 case R18:
266 return 10;
267 case R19:
268 return 11;
269 case R20:
270 return 12;
271 case R21:
272 return 13;
273 case R22:
274 return 14;
275 case R23:
276 return 15;
277 }
278}
279
280MCExpr const &HexagonMCInstrInfo::getExpr(MCExpr const &Expr) {
281 const auto &HExpr = cast<HexagonMCExpr>(Expr);
282 assert(HExpr.getExpr())((HExpr.getExpr()) ? static_cast<void> (0) : __assert_fail
("HExpr.getExpr()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 282, __PRETTY_FUNCTION__));
283 return *HExpr.getExpr();
284}
285
286unsigned short HexagonMCInstrInfo::getExtendableOp(MCInstrInfo const &MCII,
287 MCInst const &MCI) {
288 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
289 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
290}
291
292MCOperand const &
293HexagonMCInstrInfo::getExtendableOperand(MCInstrInfo const &MCII,
294 MCInst const &MCI) {
295 unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
296 MCOperand const &MO = MCI.getOperand(O);
297
298 assert((HexagonMCInstrInfo::isExtendable(MCII, MCI) ||(((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr(
))) ? static_cast<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr())"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 300, __PRETTY_FUNCTION__))
299 HexagonMCInstrInfo::isExtended(MCII, MCI)) &&(((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr(
))) ? static_cast<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr())"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 300, __PRETTY_FUNCTION__))
300 (MO.isImm() || MO.isExpr()))(((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr(
))) ? static_cast<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr())"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 300, __PRETTY_FUNCTION__));
301 return (MO);
302}
303
304unsigned HexagonMCInstrInfo::getExtentAlignment(MCInstrInfo const &MCII,
305 MCInst const &MCI) {
306 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
307 return ((F >> HexagonII::ExtentAlignPos) & HexagonII::ExtentAlignMask);
308}
309
310unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
311 MCInst const &MCI) {
312 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
313 return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
314}
315
316bool HexagonMCInstrInfo::isExtentSigned(MCInstrInfo const &MCII,
317 MCInst const &MCI) {
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
319 return (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
320}
321
322/// Return the maximum value of an extendable operand.
323int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
324 MCInst const &MCI) {
325 assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 326, __PRETTY_FUNCTION__))
326 HexagonMCInstrInfo::isExtended(MCII, MCI))((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 326, __PRETTY_FUNCTION__));
327
328 if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
329 return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
330 return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
331}
332
333/// Return the minimum value of an extendable operand.
334int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII,
335 MCInst const &MCI) {
336 assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 337, __PRETTY_FUNCTION__))
337 HexagonMCInstrInfo::isExtended(MCII, MCI))((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 337, __PRETTY_FUNCTION__));
338
339 if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
340 return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
341 return 0;
342}
343
344StringRef HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
345 MCInst const &MCI) {
346 return MCII.getName(MCI.getOpcode());
347}
348
349unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
350 MCInst const &MCI) {
351 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
352 return ((F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask);
353}
354
355MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
356 MCInst const &MCI) {
357 if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
358 // VTMP doesn't actually exist in the encodings for these 184
359 // 3 instructions so go ahead and create it here.
360 static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
361 return (MCO);
362 } else {
363 unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
364 MCOperand const &MCO = MCI.getOperand(O);
365
366 assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 368, __PRETTY_FUNCTION__))
367 HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 368, __PRETTY_FUNCTION__))
368 MCO.isReg())(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 368, __PRETTY_FUNCTION__));
369 return (MCO);
370 }
371}
372
373/// Return the new value or the newly produced value.
374unsigned short HexagonMCInstrInfo::getNewValueOp2(MCInstrInfo const &MCII,
375 MCInst const &MCI) {
376 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
377 return ((F >> HexagonII::NewValueOpPos2) & HexagonII::NewValueOpMask2);
378}
379
380MCOperand const &
381HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII,
382 MCInst const &MCI) {
383 unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
384 MCOperand const &MCO = MCI.getOperand(O);
385
386 assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue2(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 388, __PRETTY_FUNCTION__))
387 HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue2(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 388, __PRETTY_FUNCTION__))
388 MCO.isReg())(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue2(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 388, __PRETTY_FUNCTION__));
389 return (MCO);
390}
391
392/// Return the Hexagon ISA class for the insn.
393unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
394 MCInst const &MCI) {
395 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
396 return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
397}
398
399/// Return the slots this instruction can execute out of
400unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
401 MCSubtargetInfo const &STI,
402 MCInst const &MCI) {
403 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
404 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
405 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
406}
407
408/// Return the slots this instruction consumes in addition to
409/// the slot(s) it can execute out of
410
411unsigned HexagonMCInstrInfo::getOtherReservedSlots(MCInstrInfo const &MCII,
412 MCSubtargetInfo const &STI,
413 MCInst const &MCI) {
414 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
415 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
416 unsigned Slots = 0;
417
418 // FirstStage are slots that this instruction can execute in.
419 // FirstStage+1 are slots that are also consumed by this instruction.
420 // For example: vmemu can only execute in slot 0 but also consumes slot 1.
421 for (unsigned Stage = II[SchedClass].FirstStage + 1;
422 Stage < II[SchedClass].LastStage; ++Stage) {
423 unsigned Units = (Stage + HexagonStages)->getUnits();
424 if (Units > HexagonGetLastSlot())
425 break;
426 // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
427 Slots |= Units;
428 }
429
430 // if 0 is returned, then no additional slots are consumed by this inst.
431 return Slots;
432}
433
434bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
435 if (!HexagonMCInstrInfo::isBundle(MCI))
436 return false;
437
438 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
439 if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
440 return true;
441 }
442
443 return false;
444}
445
446bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
447 return extenderForIndex(MCB, Index) != nullptr;
448}
449
450bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
451 if (!HexagonMCInstrInfo::isBundle(MCI))
452 return false;
453
454 for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
455 if (isImmext(*I.getInst()))
456 return true;
457 }
458
459 return false;
460}
461
462/// Return whether the insn produces a value.
463bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
464 MCInst const &MCI) {
465 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
466 return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
467}
468
469/// Return whether the insn produces a second value.
470bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII,
471 MCInst const &MCI) {
472 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
473 return ((F >> HexagonII::hasNewValuePos2) & HexagonII::hasNewValueMask2);
474}
475
476MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
477 assert(isBundle(MCB))((isBundle(MCB)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCB)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 477, __PRETTY_FUNCTION__));
478 assert(Index < HEXAGON_PACKET_SIZE)((Index < 4) ? static_cast<void> (0) : __assert_fail
("Index < HEXAGON_PACKET_SIZE", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 478, __PRETTY_FUNCTION__));
479 return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
480}
481
482/// Return where the instruction is an accumulator.
483bool HexagonMCInstrInfo::isAccumulator(MCInstrInfo const &MCII,
484 MCInst const &MCI) {
485 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
486 return ((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
487}
488
489bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
490 auto Result = Hexagon::BUNDLE == MCI.getOpcode();
491 assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()))((!Result || (MCI.size() > 0 && MCI.getOperand(0).
isImm())) ? static_cast<void> (0) : __assert_fail ("!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm())"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 491, __PRETTY_FUNCTION__));
492 return Result;
493}
494
495bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
496 MCInst const &MCI) {
497 if (HexagonMCInstrInfo::isExtended(MCII, MCI))
498 return true;
499 if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
500 return false;
501 MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
502 if (isa<HexagonMCExpr>(MO.getExpr()) &&
503 HexagonMCInstrInfo::mustExtend(*MO.getExpr()))
504 return true;
505 // Branch insns are handled as necessary by relaxation.
506 if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
507 (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCJ &&
508 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
509 (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNCJ &&
510 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))
511 return false;
512 // Otherwise loop instructions and other CR insts are handled by relaxation
513 else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
514 (MCI.getOpcode() != Hexagon::C4_addipc))
515 return false;
516
517 assert(!MO.isImm())((!MO.isImm()) ? static_cast<void> (0) : __assert_fail (
"!MO.isImm()", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 517, __PRETTY_FUNCTION__));
518 if (isa<HexagonMCExpr>(MO.getExpr()) &&
519 HexagonMCInstrInfo::mustNotExtend(*MO.getExpr()))
520 return false;
521 int64_t Value;
522 if (!MO.getExpr()->evaluateAsAbsolute(Value))
523 return true;
524 int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
525 int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
526 return (MinValue > Value || Value > MaxValue);
527}
528
529bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
530 return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
531 !HexagonMCInstrInfo::isPrefix(MCII, MCI);
532}
533
534bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
535 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
536 return ((F >> HexagonII::CofMax1Pos) & HexagonII::CofMax1Mask);
537}
538
539bool HexagonMCInstrInfo::isCofRelax1(MCInstrInfo const &MCII,
540 MCInst const &MCI) {
541 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
542 return ((F >> HexagonII::CofRelax1Pos) & HexagonII::CofRelax1Mask);
543}
544
545bool HexagonMCInstrInfo::isCofRelax2(MCInstrInfo const &MCII,
546 MCInst const &MCI) {
547 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
548 return ((F >> HexagonII::CofRelax2Pos) & HexagonII::CofRelax2Mask);
549}
550
551bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
552 MCInst const &MCI) {
553 return (getType(MCII, MCI) == HexagonII::TypeCJ);
554}
555
556bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
557 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
558 return ((F >> HexagonII::CVINewPos) & HexagonII::CVINewMask);
559}
560
561bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
562 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
563 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
564}
565
566bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
567 return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI);
568}
569
570bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII,
571 MCInst const &MCI) {
572 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
573 return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
574}
575
576bool HexagonMCInstrInfo::isExtended(MCInstrInfo const &MCII,
577 MCInst const &MCI) {
578 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
579 return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
580}
581
582bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
583 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
584 return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
585}
586
587bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
588 const uint64_t V = getType(MCII, MCI);
589 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
590}
591
592bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
593 return MCI.getOpcode() == Hexagon::A4_ext;
594}
595
596bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
597 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 597, __PRETTY_FUNCTION__));
598 int64_t Flags = MCI.getOperand(0).getImm();
599 return (Flags & innerLoopMask) != 0;
600}
601
602bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
603 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
604}
605
606bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
607 return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
608 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
609}
610
611/// Return whether the insn expects newly produced value.
612bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
613 MCInst const &MCI) {
614 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
615 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
616}
617
618/// Return whether the operand is extendable.
619bool HexagonMCInstrInfo::isOpExtendable(MCInstrInfo const &MCII,
620 MCInst const &MCI, unsigned short O) {
621 return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
622}
623
624bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
625 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 625, __PRETTY_FUNCTION__));
626 int64_t Flags = MCI.getOperand(0).getImm();
627 return (Flags & outerLoopMask) != 0;
628}
629
630bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
631 MCInst const &MCI) {
632 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
633 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
634}
635
636bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
637 return HexagonII::TypeEXTENDER == HexagonMCInstrInfo::getType(MCII, MCI);
638}
639
640bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,
641 MCInst const &MCI) {
642 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
643 return (F >> HexagonII::PredicateLatePos & HexagonII::PredicateLateMask);
644}
645
646/// Return whether the insn is newly predicated.
647bool HexagonMCInstrInfo::isPredicatedNew(MCInstrInfo const &MCII,
648 MCInst const &MCI) {
649 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
650 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
651}
652
653bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
654 MCInst const &MCI) {
655 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
656 return (
657 !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
658}
659
660bool HexagonMCInstrInfo::isPredReg(unsigned Reg) {
661 return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
662}
663
664/// Return whether the insn can be packaged only with A and X-type insns.
665bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
666 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
667 return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask);
668}
669
670/// Return whether the insn can be packaged only with an A-type insn in slot #1.
671bool HexagonMCInstrInfo::isRestrictSlot1AOK(MCInstrInfo const &MCII,
672 MCInst const &MCI) {
673 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
674 return ((F >> HexagonII::RestrictSlot1AOKPos) &
675 HexagonII::RestrictSlot1AOKMask);
676}
677
678bool HexagonMCInstrInfo::isRestrictNoSlot1Store(MCInstrInfo const &MCII,
679 MCInst const &MCI) {
680 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
681 return ((F >> HexagonII::RestrictNoSlot1StorePos) &
682 HexagonII::RestrictNoSlot1StoreMask);
683}
684
685/// Return whether the insn is solo, i.e., cannot be in a packet.
686bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
687 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
688 return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
689}
690
691bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
692 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 692, __PRETTY_FUNCTION__));
693 auto Flags = MCI.getOperand(0).getImm();
694 return (Flags & memReorderDisabledMask) != 0;
695}
696
697bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) {
698 switch (MCI.getOpcode()) {
699 default:
700 return false;
701 case Hexagon::SA1_addi:
702 case Hexagon::SA1_addrx:
703 case Hexagon::SA1_addsp:
704 case Hexagon::SA1_and1:
705 case Hexagon::SA1_clrf:
706 case Hexagon::SA1_clrfnew:
707 case Hexagon::SA1_clrt:
708 case Hexagon::SA1_clrtnew:
709 case Hexagon::SA1_cmpeqi:
710 case Hexagon::SA1_combine0i:
711 case Hexagon::SA1_combine1i:
712 case Hexagon::SA1_combine2i:
713 case Hexagon::SA1_combine3i:
714 case Hexagon::SA1_combinerz:
715 case Hexagon::SA1_combinezr:
716 case Hexagon::SA1_dec:
717 case Hexagon::SA1_inc:
718 case Hexagon::SA1_seti:
719 case Hexagon::SA1_setin1:
720 case Hexagon::SA1_sxtb:
721 case Hexagon::SA1_sxth:
722 case Hexagon::SA1_tfr:
723 case Hexagon::SA1_zxtb:
724 case Hexagon::SA1_zxth:
725 case Hexagon::SL1_loadri_io:
726 case Hexagon::SL1_loadrub_io:
727 case Hexagon::SL2_deallocframe:
728 case Hexagon::SL2_jumpr31:
729 case Hexagon::SL2_jumpr31_f:
730 case Hexagon::SL2_jumpr31_fnew:
731 case Hexagon::SL2_jumpr31_t:
732 case Hexagon::SL2_jumpr31_tnew:
733 case Hexagon::SL2_loadrb_io:
734 case Hexagon::SL2_loadrd_sp:
735 case Hexagon::SL2_loadrh_io:
736 case Hexagon::SL2_loadri_sp:
737 case Hexagon::SL2_loadruh_io:
738 case Hexagon::SL2_return:
739 case Hexagon::SL2_return_f:
740 case Hexagon::SL2_return_fnew:
741 case Hexagon::SL2_return_t:
742 case Hexagon::SL2_return_tnew:
743 case Hexagon::SS1_storeb_io:
744 case Hexagon::SS1_storew_io:
745 case Hexagon::SS2_allocframe:
746 case Hexagon::SS2_storebi0:
747 case Hexagon::SS2_storebi1:
748 case Hexagon::SS2_stored_sp:
749 case Hexagon::SS2_storeh_io:
750 case Hexagon::SS2_storew_sp:
751 case Hexagon::SS2_storewi0:
752 case Hexagon::SS2_storewi1:
753 return true;
754 }
755}
756
757bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
758 if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
759 (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
760 return true;
761 return false;
762}
763
764int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
765 auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
766 << 8;
767 if (MCI.size() <= Index)
768 return Sentinal;
769 MCOperand const &MCO = MCI.getOperand(Index);
770 if (!MCO.isExpr())
771 return Sentinal;
772 int64_t Value;
773 if (!MCO.getExpr()->evaluateAsAbsolute(Value))
774 return Sentinal;
775 return Value;
776}
777
778void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
779 HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
780 HExpr.setMustExtend(Val);
781}
782
783bool HexagonMCInstrInfo::mustExtend(MCExpr const &Expr) {
784 HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
785 return HExpr.mustExtend();
786}
787void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
788 HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
789 HExpr.setMustNotExtend(Val);
790}
791bool HexagonMCInstrInfo::mustNotExtend(MCExpr const &Expr) {
792 HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
793 return HExpr.mustNotExtend();
794}
795void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
796 HexagonMCExpr &HExpr =
797 const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
798 HExpr.setS27_2_reloc(Val);
799}
800bool HexagonMCInstrInfo::s27_2_reloc(MCExpr const &Expr) {
801 HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
802 if (!HExpr)
803 return false;
804 return HExpr->s27_2_reloc();
805}
806
807void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) {
808 MCInst Nop;
809 Nop.setOpcode(Hexagon::A2_nop);
810 assert(isBundle(MCB))((isBundle(MCB)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCB)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 810, __PRETTY_FUNCTION__));
811 while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
812 (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_INNER_SIZE2)) ||
813 ((HexagonMCInstrInfo::isOuterLoop(MCB) &&
814 (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_OUTER_SIZE3))))
815 MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
816}
817
818HexagonMCInstrInfo::PredicateInfo
819HexagonMCInstrInfo::predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI) {
820 if (!isPredicated(MCII, MCI))
821 return {0, 0, false};
822 MCInstrDesc const &Desc = getDesc(MCII, MCI);
823 for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
824 if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
825 return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
826 return {0, 0, false};
827}
828
829bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
830 MCInst const &MCI) {
831 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
832 return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask;
833}
834
835/// return true if instruction has hasTmpDst attribute.
836bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
837 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
838 return (F >> HexagonII::HasTmpDstPos) & HexagonII::HasTmpDstMask;
839}
840
841void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
842 DuplexCandidate Candidate) {
843 assert(Candidate.packetIndexI < MCB.size())((Candidate.packetIndexI < MCB.size()) ? static_cast<void
> (0) : __assert_fail ("Candidate.packetIndexI < MCB.size()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 843, __PRETTY_FUNCTION__));
1
Assuming the condition is true
→
2
←
'?' condition is true
→
844 assert(Candidate.packetIndexJ < MCB.size())((Candidate.packetIndexJ < MCB.size()) ? static_cast<void
> (0) : __assert_fail ("Candidate.packetIndexJ < MCB.size()"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 844, __PRETTY_FUNCTION__));
3
←
Assuming the condition is true
→
4
←
'?' condition is true
→
845 assert(isBundle(MCB))((isBundle(MCB)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCB)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 845, __PRETTY_FUNCTION__));
5
←
'?' condition is true
→
846 MCInst *Duplex =
847 deriveDuplex(Context, Candidate.iClass,
6
←
Calling 'deriveDuplex'
→
848 *MCB.getOperand(Candidate.packetIndexJ).getInst(),
849 *MCB.getOperand(Candidate.packetIndexI).getInst());
850 assert(Duplex != nullptr)((Duplex != nullptr) ? static_cast<void> (0) : __assert_fail
("Duplex != nullptr", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 850, __PRETTY_FUNCTION__));
851 MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
852 MCB.erase(MCB.begin() + Candidate.packetIndexJ);
853}
854
855void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
856 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 856, __PRETTY_FUNCTION__));
857 MCOperand &Operand = MCI.getOperand(0);
858 Operand.setImm(Operand.getImm() | innerLoopMask);
859}
860
861void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
862 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 862, __PRETTY_FUNCTION__));
863 MCOperand &Operand = MCI.getOperand(0);
864 Operand.setImm(Operand.getImm() | memReorderDisabledMask);
865 assert(isMemReorderDisabled(MCI))((isMemReorderDisabled(MCI)) ? static_cast<void> (0) : __assert_fail
("isMemReorderDisabled(MCI)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 865, __PRETTY_FUNCTION__));
866}
867
868void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
869 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-8~svn350071/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 869, __PRETTY_FUNCTION__));
870 MCOperand &Operand = MCI.getOperand(0);
871 Operand.setImm(Operand.getImm() | outerLoopMask);
872}
873
874unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
875 unsigned Producer,
876 unsigned Producer2) {
877 // If we're a single vector consumer of a double producer, set subreg bit
878 // based on if we're accessing the lower or upper register component
879 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
880 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
881 return (Consumer - Hexagon::V0) & 0x1;
882 if (Producer2 != Hexagon::NoRegister)
883 return Consumer == Producer;
884 return 0;
885}