Bug Summary

File:lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
Warning:line 182, column 3
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name HexagonMCInstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-9/lib/clang/9.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-9~svn358860/build-llvm/lib/Target/Hexagon/MCTargetDesc -I /build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc -I /build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-9~svn358860/build-llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-9~svn358860/build-llvm/include -I /build/llvm-toolchain-snapshot-9~svn358860/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/9.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-9/lib/clang/9.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-9~svn358860/build-llvm/lib/Target/Hexagon/MCTargetDesc -fdebug-prefix-map=/build/llvm-toolchain-snapshot-9~svn358860=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2019-04-22-050718-5320-1 -x c++ /build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp -faddrsig
1//===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/HexagonMCInstrInfo.h"
14#include "Hexagon.h"
15#include "MCTargetDesc/HexagonBaseInfo.h"
16#include "MCTargetDesc/HexagonMCChecker.h"
17#include "MCTargetDesc/HexagonMCExpr.h"
18#include "MCTargetDesc/HexagonMCShuffler.h"
19#include "MCTargetDesc/HexagonMCTargetDesc.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCExpr.h"
23#include "llvm/MC/MCInst.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCInstrItineraries.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/Support/Casting.h"
28#include "llvm/Support/ErrorHandling.h"
29#include <cassert>
30#include <cstdint>
31#include <limits>
32
33using namespace llvm;
34
35bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const {
36 return Register != Hexagon::NoRegister;
37}
38
39Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
40 MCInst const &Inst)
41 : MCII(MCII), BundleCurrent(Inst.begin() +
42 HexagonMCInstrInfo::bundleInstructionsOffset),
43 BundleEnd(Inst.end()), DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
44
45Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII,
46 MCInst const &Inst, std::nullptr_t)
47 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()),
48 DuplexCurrent(Inst.end()), DuplexEnd(Inst.end()) {}
49
50Hexagon::PacketIterator &Hexagon::PacketIterator::operator++() {
51 if (DuplexCurrent != DuplexEnd) {
52 ++DuplexCurrent;
53 if (DuplexCurrent == DuplexEnd) {
54 DuplexCurrent = BundleEnd;
55 DuplexEnd = BundleEnd;
56 ++BundleCurrent;
57 }
58 return *this;
59 }
60 ++BundleCurrent;
61 if (BundleCurrent != BundleEnd) {
62 MCInst const &Inst = *BundleCurrent->getInst();
63 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
64 DuplexCurrent = Inst.begin();
65 DuplexEnd = Inst.end();
66 }
67 }
68 return *this;
69}
70
71MCInst const &Hexagon::PacketIterator::operator*() const {
72 if (DuplexCurrent != DuplexEnd)
73 return *DuplexCurrent->getInst();
74 return *BundleCurrent->getInst();
75}
76
77bool Hexagon::PacketIterator::operator==(PacketIterator const &Other) const {
78 return BundleCurrent == Other.BundleCurrent && BundleEnd == Other.BundleEnd &&
79 DuplexCurrent == Other.DuplexCurrent && DuplexEnd == Other.DuplexEnd;
80}
81
82void HexagonMCInstrInfo::addConstant(MCInst &MI, uint64_t Value,
83 MCContext &Context) {
84 MI.addOperand(MCOperand::createExpr(MCConstantExpr::create(Value, Context)));
85}
86
87void HexagonMCInstrInfo::addConstExtender(MCContext &Context,
88 MCInstrInfo const &MCII, MCInst &MCB,
89 MCInst const &MCI) {
90 assert(HexagonMCInstrInfo::isBundle(MCB))((HexagonMCInstrInfo::isBundle(MCB)) ? static_cast<void>
(0) : __assert_fail ("HexagonMCInstrInfo::isBundle(MCB)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 90, __PRETTY_FUNCTION__))
;
91 MCOperand const &exOp =
92 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
93
94 // Create the extender.
95 MCInst *XMCI =
96 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp));
97 XMCI->setLoc(MCI.getLoc());
98
99 MCB.addOperand(MCOperand::createInst(XMCI));
100}
101
102iterator_range<Hexagon::PacketIterator>
103HexagonMCInstrInfo::bundleInstructions(MCInstrInfo const &MCII,
104 MCInst const &MCI) {
105 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 105, __PRETTY_FUNCTION__))
;
106 return make_range(Hexagon::PacketIterator(MCII, MCI),
107 Hexagon::PacketIterator(MCII, MCI, nullptr));
108}
109
110iterator_range<MCInst::const_iterator>
111HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
112 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 112, __PRETTY_FUNCTION__))
;
113 return make_range(MCI.begin() + bundleInstructionsOffset, MCI.end());
114}
115
116size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
117 if (HexagonMCInstrInfo::isBundle(MCI))
118 return (MCI.size() - bundleInstructionsOffset);
119 else
120 return (1);
121}
122
123bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII,
124 MCSubtargetInfo const &STI,
125 MCContext &Context, MCInst &MCB,
126 HexagonMCChecker *Check) {
127 // Check the bundle for errors.
128 bool CheckOk = Check ? Check->check(false) : true;
129 if (!CheckOk)
130 return false;
131 // Examine the packet and convert pairs of instructions to compound
132 // instructions when possible.
133 if (!HexagonDisableCompound)
134 HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB);
135 HexagonMCShuffle(Context, false, MCII, STI, MCB);
136 // Examine the packet and convert pairs of instructions to duplex
137 // instructions when possible.
138 MCInst InstBundlePreDuplex = MCInst(MCB);
139 if (STI.getFeatureBits() [Hexagon::FeatureDuplex]) {
140 SmallVector<DuplexCandidate, 8> possibleDuplexes;
141 possibleDuplexes =
142 HexagonMCInstrInfo::getDuplexPossibilties(MCII, STI, MCB);
143 HexagonMCShuffle(Context, MCII, STI, MCB, possibleDuplexes);
144 }
145 // Examines packet and pad the packet, if needed, when an
146 // end-loop is in the bundle.
147 HexagonMCInstrInfo::padEndloop(MCB, Context);
148 // If compounding and duplexing didn't reduce the size below
149 // 4 or less we have a packet that is too big.
150 if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE4)
151 return false;
152 // Check the bundle for errors.
153 CheckOk = Check ? Check->check(true) : true;
154 if (!CheckOk)
155 return false;
156 HexagonMCShuffle(Context, true, MCII, STI, MCB);
157 return true;
158}
159
160MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII,
161 MCInst const &Inst,
162 MCOperand const &MO) {
163 assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) ||((HexagonMCInstrInfo::isExtendable(MCII, Inst) || HexagonMCInstrInfo
::isExtended(MCII, Inst)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, Inst) || HexagonMCInstrInfo::isExtended(MCII, Inst)"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 164, __PRETTY_FUNCTION__))
164 HexagonMCInstrInfo::isExtended(MCII, Inst))((HexagonMCInstrInfo::isExtendable(MCII, Inst) || HexagonMCInstrInfo
::isExtended(MCII, Inst)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, Inst) || HexagonMCInstrInfo::isExtended(MCII, Inst)"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 164, __PRETTY_FUNCTION__))
;
165
166 MCInst XMI;
167 XMI.setOpcode(Hexagon::A4_ext);
168 if (MO.isImm())
169 XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f)));
170 else if (MO.isExpr())
171 XMI.addOperand(MCOperand::createExpr(MO.getExpr()));
172 else
173 llvm_unreachable("invalid extendable operand")::llvm::llvm_unreachable_internal("invalid extendable operand"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 173)
;
174 return XMI;
175}
176
177MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
178 MCInst const &inst0,
179 MCInst const &inst1) {
180 assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf")(((iClass <= 0xf) && "iClass must have range of 0 to 0xf"
) ? static_cast<void> (0) : __assert_fail ("(iClass <= 0xf) && \"iClass must have range of 0 to 0xf\""
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 180, __PRETTY_FUNCTION__))
;
7
Assuming 'iClass' is <= 15
8
'?' condition is true
181 MCInst *duplexInst = new (Context) MCInst;
9
'duplexInst' initialized to a null pointer value
182 duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
10
Called C++ object pointer is null
183
184 MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
185 MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
186 duplexInst->addOperand(MCOperand::createInst(SubInst0));
187 duplexInst->addOperand(MCOperand::createInst(SubInst1));
188 return duplexInst;
189}
190
191MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
192 size_t Index) {
193 assert(Index <= bundleSize(MCB))((Index <= bundleSize(MCB)) ? static_cast<void> (0) :
__assert_fail ("Index <= bundleSize(MCB)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 193, __PRETTY_FUNCTION__))
;
194 if (Index == 0)
195 return nullptr;
196 MCInst const *Inst =
197 MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
198 if (isImmext(*Inst))
199 return Inst;
200 return nullptr;
201}
202
203void HexagonMCInstrInfo::extendIfNeeded(MCContext &Context,
204 MCInstrInfo const &MCII, MCInst &MCB,
205 MCInst const &MCI) {
206 if (isConstExtended(MCII, MCI))
207 addConstExtender(Context, MCII, MCB, MCI);
208}
209
210unsigned HexagonMCInstrInfo::getMemAccessSize(MCInstrInfo const &MCII,
211 MCInst const &MCI) {
212 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
213 unsigned S = (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
214 return HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(S));
215}
216
217unsigned HexagonMCInstrInfo::getAddrMode(MCInstrInfo const &MCII,
218 MCInst const &MCI) {
219 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
220 return static_cast<unsigned>((F >> HexagonII::AddrModePos) &
221 HexagonII::AddrModeMask);
222}
223
224MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
225 MCInst const &MCI) {
226 return MCII.get(MCI.getOpcode());
227}
228
229unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(unsigned Reg) {
230 using namespace Hexagon;
231
232 switch (Reg) {
233 default:
234 llvm_unreachable("unknown duplex register")::llvm::llvm_unreachable_internal("unknown duplex register", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 234)
;
235 // Rs Rss
236 case R0:
237 case D0:
238 return 0;
239 case R1:
240 case D1:
241 return 1;
242 case R2:
243 case D2:
244 return 2;
245 case R3:
246 case D3:
247 return 3;
248 case R4:
249 case D8:
250 return 4;
251 case R5:
252 case D9:
253 return 5;
254 case R6:
255 case D10:
256 return 6;
257 case R7:
258 case D11:
259 return 7;
260 case R16:
261 return 8;
262 case R17:
263 return 9;
264 case R18:
265 return 10;
266 case R19:
267 return 11;
268 case R20:
269 return 12;
270 case R21:
271 return 13;
272 case R22:
273 return 14;
274 case R23:
275 return 15;
276 }
277}
278
279MCExpr const &HexagonMCInstrInfo::getExpr(MCExpr const &Expr) {
280 const auto &HExpr = cast<HexagonMCExpr>(Expr);
281 assert(HExpr.getExpr())((HExpr.getExpr()) ? static_cast<void> (0) : __assert_fail
("HExpr.getExpr()", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 281, __PRETTY_FUNCTION__))
;
282 return *HExpr.getExpr();
283}
284
285unsigned short HexagonMCInstrInfo::getExtendableOp(MCInstrInfo const &MCII,
286 MCInst const &MCI) {
287 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
288 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
289}
290
291MCOperand const &
292HexagonMCInstrInfo::getExtendableOperand(MCInstrInfo const &MCII,
293 MCInst const &MCI) {
294 unsigned O = HexagonMCInstrInfo::getExtendableOp(MCII, MCI);
295 MCOperand const &MO = MCI.getOperand(O);
296
297 assert((HexagonMCInstrInfo::isExtendable(MCII, MCI) ||(((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr(
))) ? static_cast<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr())"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 299, __PRETTY_FUNCTION__))
298 HexagonMCInstrInfo::isExtended(MCII, MCI)) &&(((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr(
))) ? static_cast<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr())"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 299, __PRETTY_FUNCTION__))
299 (MO.isImm() || MO.isExpr()))(((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr(
))) ? static_cast<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)) && (MO.isImm() || MO.isExpr())"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 299, __PRETTY_FUNCTION__))
;
300 return (MO);
301}
302
303unsigned HexagonMCInstrInfo::getExtentAlignment(MCInstrInfo const &MCII,
304 MCInst const &MCI) {
305 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
306 return ((F >> HexagonII::ExtentAlignPos) & HexagonII::ExtentAlignMask);
307}
308
309unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
310 MCInst const &MCI) {
311 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
312 return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
313}
314
315bool HexagonMCInstrInfo::isExtentSigned(MCInstrInfo const &MCII,
316 MCInst const &MCI) {
317 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
318 return (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
319}
320
321/// Return the maximum value of an extendable operand.
322int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
323 MCInst const &MCI) {
324 assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 325, __PRETTY_FUNCTION__))
325 HexagonMCInstrInfo::isExtended(MCII, MCI))((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 325, __PRETTY_FUNCTION__))
;
326
327 if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
328 return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1;
329 return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1;
330}
331
332/// Return the minimum value of an extendable operand.
333int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII,
334 MCInst const &MCI) {
335 assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) ||((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 336, __PRETTY_FUNCTION__))
336 HexagonMCInstrInfo::isExtended(MCII, MCI))((HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo
::isExtended(MCII, MCI)) ? static_cast<void> (0) : __assert_fail
("HexagonMCInstrInfo::isExtendable(MCII, MCI) || HexagonMCInstrInfo::isExtended(MCII, MCI)"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 336, __PRETTY_FUNCTION__))
;
337
338 if (HexagonMCInstrInfo::isExtentSigned(MCII, MCI)) // if value is signed
339 return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1));
340 return 0;
341}
342
343StringRef HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
344 MCInst const &MCI) {
345 return MCII.getName(MCI.getOpcode());
346}
347
348unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
349 MCInst const &MCI) {
350 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
351 return ((F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask);
352}
353
354MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
355 MCInst const &MCI) {
356 if (HexagonMCInstrInfo::hasTmpDst(MCII, MCI)) {
357 // VTMP doesn't actually exist in the encodings for these 184
358 // 3 instructions so go ahead and create it here.
359 static MCOperand MCO = MCOperand::createReg(Hexagon::VTMP);
360 return (MCO);
361 } else {
362 unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI);
363 MCOperand const &MCO = MCI.getOperand(O);
364
365 assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 367, __PRETTY_FUNCTION__))
366 HexagonMCInstrInfo::hasNewValue(MCII, MCI)) &&(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 367, __PRETTY_FUNCTION__))
367 MCO.isReg())(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 367, __PRETTY_FUNCTION__))
;
368 return (MCO);
369 }
370}
371
372/// Return the new value or the newly produced value.
373unsigned short HexagonMCInstrInfo::getNewValueOp2(MCInstrInfo const &MCII,
374 MCInst const &MCI) {
375 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
376 return ((F >> HexagonII::NewValueOpPos2) & HexagonII::NewValueOpMask2);
377}
378
379MCOperand const &
380HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII,
381 MCInst const &MCI) {
382 unsigned O = HexagonMCInstrInfo::getNewValueOp2(MCII, MCI);
383 MCOperand const &MCO = MCI.getOperand(O);
384
385 assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) ||(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue2(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 387, __PRETTY_FUNCTION__))
386 HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) &&(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue2(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 387, __PRETTY_FUNCTION__))
387 MCO.isReg())(((HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo
::hasNewValue2(MCII, MCI)) && MCO.isReg()) ? static_cast
<void> (0) : __assert_fail ("(HexagonMCInstrInfo::isNewValue(MCII, MCI) || HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) && MCO.isReg()"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 387, __PRETTY_FUNCTION__))
;
388 return (MCO);
389}
390
391/// Return the Hexagon ISA class for the insn.
392unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII,
393 MCInst const &MCI) {
394 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
395 return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
396}
397
398/// Return the slots this instruction can execute out of
399unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII,
400 MCSubtargetInfo const &STI,
401 MCInst const &MCI) {
402 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
403 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
404 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits());
405}
406
407/// Return the slots this instruction consumes in addition to
408/// the slot(s) it can execute out of
409
410unsigned HexagonMCInstrInfo::getOtherReservedSlots(MCInstrInfo const &MCII,
411 MCSubtargetInfo const &STI,
412 MCInst const &MCI) {
413 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
414 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
415 unsigned Slots = 0;
416
417 // FirstStage are slots that this instruction can execute in.
418 // FirstStage+1 are slots that are also consumed by this instruction.
419 // For example: vmemu can only execute in slot 0 but also consumes slot 1.
420 for (unsigned Stage = II[SchedClass].FirstStage + 1;
421 Stage < II[SchedClass].LastStage; ++Stage) {
422 unsigned Units = (Stage + HexagonStages)->getUnits();
423 if (Units > HexagonGetLastSlot())
424 break;
425 // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8
426 Slots |= Units;
427 }
428
429 // if 0 is returned, then no additional slots are consumed by this inst.
430 return Slots;
431}
432
433bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
434 if (!HexagonMCInstrInfo::isBundle(MCI))
435 return false;
436
437 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
438 if (HexagonMCInstrInfo::isDuplex(MCII, *I.getInst()))
439 return true;
440 }
441
442 return false;
443}
444
445bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
446 return extenderForIndex(MCB, Index) != nullptr;
447}
448
449bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
450 if (!HexagonMCInstrInfo::isBundle(MCI))
451 return false;
452
453 for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) {
454 if (isImmext(*I.getInst()))
455 return true;
456 }
457
458 return false;
459}
460
461/// Return whether the insn produces a value.
462bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
463 MCInst const &MCI) {
464 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
465 return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
466}
467
468/// Return whether the insn produces a second value.
469bool HexagonMCInstrInfo::hasNewValue2(MCInstrInfo const &MCII,
470 MCInst const &MCI) {
471 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
472 return ((F >> HexagonII::hasNewValuePos2) & HexagonII::hasNewValueMask2);
473}
474
475MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) {
476 assert(isBundle(MCB))((isBundle(MCB)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCB)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 476, __PRETTY_FUNCTION__))
;
477 assert(Index < HEXAGON_PACKET_SIZE)((Index < 4) ? static_cast<void> (0) : __assert_fail
("Index < HEXAGON_PACKET_SIZE", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 477, __PRETTY_FUNCTION__))
;
478 return *MCB.getOperand(bundleInstructionsOffset + Index).getInst();
479}
480
481/// Return where the instruction is an accumulator.
482bool HexagonMCInstrInfo::isAccumulator(MCInstrInfo const &MCII,
483 MCInst const &MCI) {
484 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
485 return ((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
486}
487
488bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
489 auto Result = Hexagon::BUNDLE == MCI.getOpcode();
490 assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()))((!Result || (MCI.size() > 0 && MCI.getOperand(0).
isImm())) ? static_cast<void> (0) : __assert_fail ("!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm())"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 490, __PRETTY_FUNCTION__))
;
491 return Result;
492}
493
494bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
495 MCInst const &MCI) {
496 if (HexagonMCInstrInfo::isExtended(MCII, MCI))
497 return true;
498 if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
499 return false;
500 MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
501 if (isa<HexagonMCExpr>(MO.getExpr()) &&
502 HexagonMCInstrInfo::mustExtend(*MO.getExpr()))
503 return true;
504 // Branch insns are handled as necessary by relaxation.
505 if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
506 (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCJ &&
507 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
508 (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNCJ &&
509 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))
510 return false;
511 // Otherwise loop instructions and other CR insts are handled by relaxation
512 else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
513 (MCI.getOpcode() != Hexagon::C4_addipc))
514 return false;
515
516 assert(!MO.isImm())((!MO.isImm()) ? static_cast<void> (0) : __assert_fail (
"!MO.isImm()", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 516, __PRETTY_FUNCTION__))
;
517 if (isa<HexagonMCExpr>(MO.getExpr()) &&
518 HexagonMCInstrInfo::mustNotExtend(*MO.getExpr()))
519 return false;
520 int64_t Value;
521 if (!MO.getExpr()->evaluateAsAbsolute(Value))
522 return true;
523 int MinValue = HexagonMCInstrInfo::getMinValue(MCII, MCI);
524 int MaxValue = HexagonMCInstrInfo::getMaxValue(MCII, MCI);
525 return (MinValue > Value || Value > MaxValue);
526}
527
528bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
529 return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
530 !HexagonMCInstrInfo::isPrefix(MCII, MCI);
531}
532
533bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
534 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
535 return ((F >> HexagonII::CofMax1Pos) & HexagonII::CofMax1Mask);
536}
537
538bool HexagonMCInstrInfo::isCofRelax1(MCInstrInfo const &MCII,
539 MCInst const &MCI) {
540 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
541 return ((F >> HexagonII::CofRelax1Pos) & HexagonII::CofRelax1Mask);
542}
543
544bool HexagonMCInstrInfo::isCofRelax2(MCInstrInfo const &MCII,
545 MCInst const &MCI) {
546 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
547 return ((F >> HexagonII::CofRelax2Pos) & HexagonII::CofRelax2Mask);
548}
549
550bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
551 MCInst const &MCI) {
552 return (getType(MCII, MCI) == HexagonII::TypeCJ);
553}
554
555bool HexagonMCInstrInfo::isCVINew(MCInstrInfo const &MCII, MCInst const &MCI) {
556 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
557 return ((F >> HexagonII::CVINewPos) & HexagonII::CVINewMask);
558}
559
560bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
561 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
562 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
563}
564
565bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
566 return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI);
567}
568
569bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII,
570 MCInst const &MCI) {
571 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
572 return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
573}
574
575bool HexagonMCInstrInfo::isExtended(MCInstrInfo const &MCII,
576 MCInst const &MCI) {
577 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
578 return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
579}
580
581bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) {
582 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
583 return ((F >> HexagonII::FPPos) & HexagonII::FPMask);
584}
585
586bool HexagonMCInstrInfo::isHVX(MCInstrInfo const &MCII, MCInst const &MCI) {
587 const uint64_t V = getType(MCII, MCI);
588 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
589}
590
591bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
592 return MCI.getOpcode() == Hexagon::A4_ext;
593}
594
595bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
596 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 596, __PRETTY_FUNCTION__))
;
597 int64_t Flags = MCI.getOperand(0).getImm();
598 return (Flags & innerLoopMask) != 0;
599}
600
601bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
602 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
603}
604
605bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
606 return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
607 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
608}
609
610/// Return whether the insn expects newly produced value.
611bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
612 MCInst const &MCI) {
613 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
614 return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
615}
616
617/// Return whether the operand is extendable.
618bool HexagonMCInstrInfo::isOpExtendable(MCInstrInfo const &MCII,
619 MCInst const &MCI, unsigned short O) {
620 return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI));
621}
622
623bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
624 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 624, __PRETTY_FUNCTION__))
;
625 int64_t Flags = MCI.getOperand(0).getImm();
626 return (Flags & outerLoopMask) != 0;
627}
628
629bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
630 MCInst const &MCI) {
631 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
632 return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
633}
634
635bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
636 return HexagonII::TypeEXTENDER == HexagonMCInstrInfo::getType(MCII, MCI);
637}
638
639bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII,
640 MCInst const &MCI) {
641 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
642 return (F >> HexagonII::PredicateLatePos & HexagonII::PredicateLateMask);
643}
644
645/// Return whether the insn is newly predicated.
646bool HexagonMCInstrInfo::isPredicatedNew(MCInstrInfo const &MCII,
647 MCInst const &MCI) {
648 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
649 return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
650}
651
652bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
653 MCInst const &MCI) {
654 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
655 return (
656 !((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
657}
658
659bool HexagonMCInstrInfo::isPredReg(unsigned Reg) {
660 return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
661}
662
663/// Return whether the insn can be packaged only with A and X-type insns.
664bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) {
665 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
666 return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask);
667}
668
669/// Return whether the insn can be packaged only with an A-type insn in slot #1.
670bool HexagonMCInstrInfo::isRestrictSlot1AOK(MCInstrInfo const &MCII,
671 MCInst const &MCI) {
672 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
673 return ((F >> HexagonII::RestrictSlot1AOKPos) &
674 HexagonII::RestrictSlot1AOKMask);
675}
676
677bool HexagonMCInstrInfo::isRestrictNoSlot1Store(MCInstrInfo const &MCII,
678 MCInst const &MCI) {
679 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
680 return ((F >> HexagonII::RestrictNoSlot1StorePos) &
681 HexagonII::RestrictNoSlot1StoreMask);
682}
683
684/// Return whether the insn is solo, i.e., cannot be in a packet.
685bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
686 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
687 return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
688}
689
690bool HexagonMCInstrInfo::isMemReorderDisabled(MCInst const &MCI) {
691 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 691, __PRETTY_FUNCTION__))
;
692 auto Flags = MCI.getOperand(0).getImm();
693 return (Flags & memReorderDisabledMask) != 0;
694}
695
696bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) {
697 switch (MCI.getOpcode()) {
698 default:
699 return false;
700 case Hexagon::SA1_addi:
701 case Hexagon::SA1_addrx:
702 case Hexagon::SA1_addsp:
703 case Hexagon::SA1_and1:
704 case Hexagon::SA1_clrf:
705 case Hexagon::SA1_clrfnew:
706 case Hexagon::SA1_clrt:
707 case Hexagon::SA1_clrtnew:
708 case Hexagon::SA1_cmpeqi:
709 case Hexagon::SA1_combine0i:
710 case Hexagon::SA1_combine1i:
711 case Hexagon::SA1_combine2i:
712 case Hexagon::SA1_combine3i:
713 case Hexagon::SA1_combinerz:
714 case Hexagon::SA1_combinezr:
715 case Hexagon::SA1_dec:
716 case Hexagon::SA1_inc:
717 case Hexagon::SA1_seti:
718 case Hexagon::SA1_setin1:
719 case Hexagon::SA1_sxtb:
720 case Hexagon::SA1_sxth:
721 case Hexagon::SA1_tfr:
722 case Hexagon::SA1_zxtb:
723 case Hexagon::SA1_zxth:
724 case Hexagon::SL1_loadri_io:
725 case Hexagon::SL1_loadrub_io:
726 case Hexagon::SL2_deallocframe:
727 case Hexagon::SL2_jumpr31:
728 case Hexagon::SL2_jumpr31_f:
729 case Hexagon::SL2_jumpr31_fnew:
730 case Hexagon::SL2_jumpr31_t:
731 case Hexagon::SL2_jumpr31_tnew:
732 case Hexagon::SL2_loadrb_io:
733 case Hexagon::SL2_loadrd_sp:
734 case Hexagon::SL2_loadrh_io:
735 case Hexagon::SL2_loadri_sp:
736 case Hexagon::SL2_loadruh_io:
737 case Hexagon::SL2_return:
738 case Hexagon::SL2_return_f:
739 case Hexagon::SL2_return_fnew:
740 case Hexagon::SL2_return_t:
741 case Hexagon::SL2_return_tnew:
742 case Hexagon::SS1_storeb_io:
743 case Hexagon::SS1_storew_io:
744 case Hexagon::SS2_allocframe:
745 case Hexagon::SS2_storebi0:
746 case Hexagon::SS2_storebi1:
747 case Hexagon::SS2_stored_sp:
748 case Hexagon::SS2_storeh_io:
749 case Hexagon::SS2_storew_sp:
750 case Hexagon::SS2_storewi0:
751 case Hexagon::SS2_storewi1:
752 return true;
753 }
754}
755
756bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) {
757 if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) &&
758 (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST))
759 return true;
760 return false;
761}
762
763int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
764 auto Sentinal = static_cast<int64_t>(std::numeric_limits<uint32_t>::max())
765 << 8;
766 if (MCI.size() <= Index)
767 return Sentinal;
768 MCOperand const &MCO = MCI.getOperand(Index);
769 if (!MCO.isExpr())
770 return Sentinal;
771 int64_t Value;
772 if (!MCO.getExpr()->evaluateAsAbsolute(Value))
773 return Sentinal;
774 return Value;
775}
776
777void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
778 HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
779 HExpr.setMustExtend(Val);
780}
781
782bool HexagonMCInstrInfo::mustExtend(MCExpr const &Expr) {
783 HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
784 return HExpr.mustExtend();
785}
786void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) {
787 HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
788 HExpr.setMustNotExtend(Val);
789}
790bool HexagonMCInstrInfo::mustNotExtend(MCExpr const &Expr) {
791 HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr);
792 return HExpr.mustNotExtend();
793}
794void HexagonMCInstrInfo::setS27_2_reloc(MCExpr const &Expr, bool Val) {
795 HexagonMCExpr &HExpr =
796 const_cast<HexagonMCExpr &>(*cast<HexagonMCExpr>(&Expr));
797 HExpr.setS27_2_reloc(Val);
798}
799bool HexagonMCInstrInfo::s27_2_reloc(MCExpr const &Expr) {
800 HexagonMCExpr const *HExpr = dyn_cast<HexagonMCExpr>(&Expr);
801 if (!HExpr)
802 return false;
803 return HExpr->s27_2_reloc();
804}
805
806void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) {
807 MCInst Nop;
808 Nop.setOpcode(Hexagon::A2_nop);
809 assert(isBundle(MCB))((isBundle(MCB)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCB)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 809, __PRETTY_FUNCTION__))
;
810 while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
811 (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_INNER_SIZE2)) ||
812 ((HexagonMCInstrInfo::isOuterLoop(MCB) &&
813 (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_OUTER_SIZE3))))
814 MCB.addOperand(MCOperand::createInst(new (Context) MCInst(Nop)));
815}
816
817HexagonMCInstrInfo::PredicateInfo
818HexagonMCInstrInfo::predicateInfo(MCInstrInfo const &MCII, MCInst const &MCI) {
819 if (!isPredicated(MCII, MCI))
820 return {0, 0, false};
821 MCInstrDesc const &Desc = getDesc(MCII, MCI);
822 for (auto I = Desc.getNumDefs(), N = Desc.getNumOperands(); I != N; ++I)
823 if (Desc.OpInfo[I].RegClass == Hexagon::PredRegsRegClassID)
824 return {MCI.getOperand(I).getReg(), I, isPredicatedTrue(MCII, MCI)};
825 return {0, 0, false};
826}
827
828bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
829 MCInst const &MCI) {
830 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
831 return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask;
832}
833
834/// return true if instruction has hasTmpDst attribute.
835bool HexagonMCInstrInfo::hasTmpDst(MCInstrInfo const &MCII, MCInst const &MCI) {
836 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
837 return (F >> HexagonII::HasTmpDstPos) & HexagonII::HasTmpDstMask;
838}
839
840void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
841 DuplexCandidate Candidate) {
842 assert(Candidate.packetIndexI < MCB.size())((Candidate.packetIndexI < MCB.size()) ? static_cast<void
> (0) : __assert_fail ("Candidate.packetIndexI < MCB.size()"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 842, __PRETTY_FUNCTION__))
;
1
Assuming the condition is true
2
'?' condition is true
843 assert(Candidate.packetIndexJ < MCB.size())((Candidate.packetIndexJ < MCB.size()) ? static_cast<void
> (0) : __assert_fail ("Candidate.packetIndexJ < MCB.size()"
, "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 843, __PRETTY_FUNCTION__))
;
3
Assuming the condition is true
4
'?' condition is true
844 assert(isBundle(MCB))((isBundle(MCB)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCB)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 844, __PRETTY_FUNCTION__))
;
5
'?' condition is true
845 MCInst *Duplex =
846 deriveDuplex(Context, Candidate.iClass,
6
Calling 'deriveDuplex'
847 *MCB.getOperand(Candidate.packetIndexJ).getInst(),
848 *MCB.getOperand(Candidate.packetIndexI).getInst());
849 assert(Duplex != nullptr)((Duplex != nullptr) ? static_cast<void> (0) : __assert_fail
("Duplex != nullptr", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 849, __PRETTY_FUNCTION__))
;
850 MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
851 MCB.erase(MCB.begin() + Candidate.packetIndexJ);
852}
853
854void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
855 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 855, __PRETTY_FUNCTION__))
;
856 MCOperand &Operand = MCI.getOperand(0);
857 Operand.setImm(Operand.getImm() | innerLoopMask);
858}
859
860void HexagonMCInstrInfo::setMemReorderDisabled(MCInst &MCI) {
861 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 861, __PRETTY_FUNCTION__))
;
862 MCOperand &Operand = MCI.getOperand(0);
863 Operand.setImm(Operand.getImm() | memReorderDisabledMask);
864 assert(isMemReorderDisabled(MCI))((isMemReorderDisabled(MCI)) ? static_cast<void> (0) : __assert_fail
("isMemReorderDisabled(MCI)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 864, __PRETTY_FUNCTION__))
;
865}
866
867void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
868 assert(isBundle(MCI))((isBundle(MCI)) ? static_cast<void> (0) : __assert_fail
("isBundle(MCI)", "/build/llvm-toolchain-snapshot-9~svn358860/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp"
, 868, __PRETTY_FUNCTION__))
;
869 MCOperand &Operand = MCI.getOperand(0);
870 Operand.setImm(Operand.getImm() | outerLoopMask);
871}
872
873unsigned HexagonMCInstrInfo::SubregisterBit(unsigned Consumer,
874 unsigned Producer,
875 unsigned Producer2) {
876 // If we're a single vector consumer of a double producer, set subreg bit
877 // based on if we're accessing the lower or upper register component
878 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
879 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
880 return (Consumer - Hexagon::V0) & 0x1;
881 if (Producer2 != Hexagon::NoRegister)
882 return Consumer == Producer;
883 return 0;
884}