/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp

Bug Summary

File:	llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
Warning:	line 977, column 7 Called C++ object pointer is null

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/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp

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1//===- HexagonMachineScheduler.cpp - MI Scheduler for Hexagon -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// MachineScheduler schedules machine instructions after phi elimination. It
10// preserves LiveIntervals so it can be invoked before register allocation.
11//
12//===----------------------------------------------------------------------===//

14#include "HexagonMachineScheduler.h"
15#include "HexagonInstrInfo.h"
16#include "HexagonSubtarget.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/CodeGen/DFAPacketizer.h"
19#include "llvm/CodeGen/MachineBasicBlock.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstr.h"
22#include "llvm/CodeGen/MachineLoopInfo.h"
23#include "llvm/CodeGen/RegisterClassInfo.h"
24#include "llvm/CodeGen/RegisterPressure.h"
25#include "llvm/CodeGen/ScheduleDAG.h"
26#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include "llvm/CodeGen/TargetOpcodes.h"
29#include "llvm/CodeGen/TargetRegisterInfo.h"
30#include "llvm/CodeGen/TargetSchedule.h"
31#include "llvm/CodeGen/TargetSubtargetInfo.h"
32#include "llvm/IR/Function.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/raw_ostream.h"
36#include <algorithm>
37#include <cassert>
38#include <iomanip>
39#include <limits>
40#include <memory>
41#include <sstream>

43using namespace llvm;

45#define DEBUG_TYPE"machine-scheduler" "machine-scheduler"

47static cl::opt<bool> IgnoreBBRegPressure("ignore-bb-reg-pressure",
  cl::Hidden, cl::ZeroOrMore, cl::init(false));

50static cl::opt<bool> UseNewerCandidate("use-newer-candidate",
  cl::Hidden, cl::ZeroOrMore, cl::init(true));

53static cl::opt<unsigned> SchedDebugVerboseLevel("misched-verbose-level",
  cl::Hidden, cl::ZeroOrMore, cl::init(1));

56// Check if the scheduler should penalize instructions that are available to
57// early due to a zero-latency dependence.
58static cl::opt<bool> CheckEarlyAvail("check-early-avail", cl::Hidden,
  cl::ZeroOrMore, cl::init(true));

61// This value is used to determine if a register class is a high pressure set.
62// We compute the maximum number of registers needed and divided by the total
63// available. Then, we compare the result to this value.
64static cl::opt<float> RPThreshold("hexagon-reg-pressure", cl::Hidden,
  cl::init(0.75f), cl::desc("High register pressure threhold."));

67/// Return true if there is a dependence between SUd and SUu.
68static bool hasDependence(const SUnit *SUd, const SUnit *SUu,
                        const HexagonInstrInfo &QII) {
if (SUd->Succs.size() == 0)
  return false;

// Enable .cur formation.
if (QII.mayBeCurLoad(*SUd->getInstr()))
  return false;

if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr()))
  return false;

for (const auto &S : SUd->Succs) {
  // Since we do not add pseudos to packets, might as well
  // ignore order dependencies.
  if (S.isCtrl())
    continue;

  if (S.getSUnit() == SUu && S.getLatency() > 0)
    return true;
}
return false;
90}

92/// Check if scheduling of this SU is possible
93/// in the current packet.
94/// It is _not_ precise (statefull), it is more like
95/// another heuristic. Many corner cases are figured
96/// empirically.
97bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) {
if (!SU || !SU->getInstr())
  return false;

// First see if the pipeline could receive this instruction
// in the current cycle.
switch (SU->getInstr()->getOpcode()) {
default:
  if (!ResourcesModel->canReserveResources(*SU->getInstr()))
    return false;
  break;
case TargetOpcode::EXTRACT_SUBREG:
case TargetOpcode::INSERT_SUBREG:
case TargetOpcode::SUBREG_TO_REG:
case TargetOpcode::REG_SEQUENCE:
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::COPY:
case TargetOpcode::INLINEASM:
case TargetOpcode::INLINEASM_BR:
  break;
}

MachineBasicBlock *MBB = SU->getInstr()->getParent();
auto &QST = MBB->getParent()->getSubtarget<HexagonSubtarget>();
const auto &QII = *QST.getInstrInfo();

// Now see if there are no other dependencies to instructions already
// in the packet.
if (IsTop) {
  for (unsigned i = 0, e = Packet.size(); i != e; ++i)
    if (hasDependence(Packet[i], SU, QII))
      return false;
} else {
  for (unsigned i = 0, e = Packet.size(); i != e; ++i)
    if (hasDependence(SU, Packet[i], QII))
      return false;
}
return true;
135}

137/// Keep track of available resources.
138bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) {
bool startNewCycle = false;
// Artificially reset state.
if (!SU) {
  ResourcesModel->clearResources();
  Packet.clear();
  TotalPackets++;
  return false;
}
// If this SU does not fit in the packet or the packet is now full
// start a new one.
if (!isResourceAvailable(SU, IsTop) ||
    Packet.size() >= SchedModel->getIssueWidth()) {
  ResourcesModel->clearResources();
  Packet.clear();
  TotalPackets++;
  startNewCycle = true;
}

switch (SU->getInstr()->getOpcode()) {
default:
  ResourcesModel->reserveResources(*SU->getInstr());
  break;
case TargetOpcode::EXTRACT_SUBREG:
case TargetOpcode::INSERT_SUBREG:
case TargetOpcode::SUBREG_TO_REG:
case TargetOpcode::REG_SEQUENCE:
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
case TargetOpcode::CFI_INSTRUCTION:
case TargetOpcode::EH_LABEL:
case TargetOpcode::COPY:
case TargetOpcode::INLINEASM:
case TargetOpcode::INLINEASM_BR:
  break;
}
Packet.push_back(SU);

176#ifndef NDEBUG1
LLVM_DEBUG(dbgs() << "Packet[" << TotalPackets << "]:\n")do { } while (false);
for (unsigned i = 0, e = Packet.size(); i != e; ++i) {
  LLVM_DEBUG(dbgs() << "\t[" << i << "] SU(")do { } while (false);
  LLVM_DEBUG(dbgs() << Packet[i]->NodeNum << ")\t")do { } while (false);
  LLVM_DEBUG(Packet[i]->getInstr()->dump())do { } while (false);
}
183#endif

return startNewCycle;
186}

188/// schedule - Called back from MachineScheduler::runOnMachineFunction
189/// after setting up the current scheduling region. [RegionBegin, RegionEnd)
190/// only includes instructions that have DAG nodes, not scheduling boundaries.
191void VLIWMachineScheduler::schedule() {
LLVM_DEBUG(dbgs() << "********** MI Converging Scheduling VLIW "do { } while (false)
                  << printMBBReference(*BB) << " " << BB->getName()do { } while (false)
                  << " in_func " << BB->getParent()->getName()do { } while (false)
                  << " at loop depth " << MLI->getLoopDepth(BB) << " \n")do { } while (false);

buildDAGWithRegPressure();

Topo.InitDAGTopologicalSorting();

// Postprocess the DAG to add platform-specific artificial dependencies.
postprocessDAG();

SmallVector<SUnit*, 8> TopRoots, BotRoots;
findRootsAndBiasEdges(TopRoots, BotRoots);

// Initialize the strategy before modifying the DAG.
SchedImpl->initialize(this);

LLVM_DEBUG(unsigned maxH = 0;do { } while (false)
           for (unsigned su = 0, e = SUnits.size(); su != e;do { } while (false)
                ++su) if (SUnits[su].getHeight() > maxH) maxH =do { } while (false)
               SUnits[su].getHeight();do { } while (false)
           dbgs() << "Max Height " << maxH << "\n";)do { } while (false);
LLVM_DEBUG(unsigned maxD = 0;do { } while (false)
           for (unsigned su = 0, e = SUnits.size(); su != e;do { } while (false)
                ++su) if (SUnits[su].getDepth() > maxD) maxD =do { } while (false)
               SUnits[su].getDepth();do { } while (false)
           dbgs() << "Max Depth " << maxD << "\n";)do { } while (false);
LLVM_DEBUG(dump())do { } while (false);

initQueues(TopRoots, BotRoots);

bool IsTopNode = false;
while (true) {
  LLVM_DEBUG(do { } while (false)
      dbgs() << "** VLIWMachineScheduler::schedule picking next node\n")do { } while (false);
  SUnit *SU = SchedImpl->pickNode(IsTopNode);
  if (!SU) break;

  if (!checkSchedLimit())
    break;

  scheduleMI(SU, IsTopNode);

  // Notify the scheduling strategy after updating the DAG.
  SchedImpl->schedNode(SU, IsTopNode);

  updateQueues(SU, IsTopNode);
}
assert(CurrentTop == CurrentBottom && "Nonempty unscheduled zone.")(static_cast<void> (0));

placeDebugValues();

LLVM_DEBUG({do { } while (false)
  dbgs() << "*** Final schedule for "do { } while (false)
         << printMBBReference(*begin()->getParent()) << " ***\n";do { } while (false)
  dumpSchedule();do { } while (false)
  dbgs() << '\n';do { } while (false)
})do { } while (false);
251}

253void ConvergingVLIWScheduler::initialize(ScheduleDAGMI *dag) {
DAG = static_cast<VLIWMachineScheduler*>(dag);
SchedModel = DAG->getSchedModel();

Top.init(DAG, SchedModel);
Bot.init(DAG, SchedModel);

// Initialize the HazardRecognizers. If itineraries don't exist, are empty, or
// are disabled, then these HazardRecs will be disabled.
const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries();
const TargetSubtargetInfo &STI = DAG->MF.getSubtarget();
const TargetInstrInfo *TII = STI.getInstrInfo();
delete Top.HazardRec;
delete Bot.HazardRec;
Top.HazardRec = TII->CreateTargetMIHazardRecognizer(Itin, DAG);
Bot.HazardRec = TII->CreateTargetMIHazardRecognizer(Itin, DAG);

delete Top.ResourceModel;
delete Bot.ResourceModel;
Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());

const std::vector<unsigned> &MaxPressure =
  DAG->getRegPressure().MaxSetPressure;
HighPressureSets.assign(MaxPressure.size(), 0);
for (unsigned i = 0, e = MaxPressure.size(); i < e; ++i) {
  unsigned Limit = DAG->getRegClassInfo()->getRegPressureSetLimit(i);
  HighPressureSets[i] =
    ((float) MaxPressure[i] > ((float) Limit * RPThreshold));
}

assert((!ForceTopDown || !ForceBottomUp) &&(static_cast<void> (0))
       "-misched-topdown incompatible with -misched-bottomup")(static_cast<void> (0));
286}

288void ConvergingVLIWScheduler::releaseTopNode(SUnit *SU) {
if (SU->isScheduled)
  return;

for (const SDep &PI : SU->Preds) {
  unsigned PredReadyCycle = PI.getSUnit()->TopReadyCycle;
  unsigned MinLatency = PI.getLatency();
295#ifndef NDEBUG1
  Top.MaxMinLatency = std::max(MinLatency, Top.MaxMinLatency);
297#endif
  if (SU->TopReadyCycle < PredReadyCycle + MinLatency)
    SU->TopReadyCycle = PredReadyCycle + MinLatency;
}
Top.releaseNode(SU, SU->TopReadyCycle);
302}

304void ConvergingVLIWScheduler::releaseBottomNode(SUnit *SU) {
if (SU->isScheduled)
  return;

assert(SU->getInstr() && "Scheduled SUnit must have instr")(static_cast<void> (0));

for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
     I != E; ++I) {
  unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
  unsigned MinLatency = I->getLatency();
314#ifndef NDEBUG1
  Bot.MaxMinLatency = std::max(MinLatency, Bot.MaxMinLatency);
316#endif
  if (SU->BotReadyCycle < SuccReadyCycle + MinLatency)
    SU->BotReadyCycle = SuccReadyCycle + MinLatency;
}
Bot.releaseNode(SU, SU->BotReadyCycle);
321}

323/// Does this SU have a hazard within the current instruction group.
324///
325/// The scheduler supports two modes of hazard recognition. The first is the
326/// ScheduleHazardRecognizer API. It is a fully general hazard recognizer that
327/// supports highly complicated in-order reservation tables
328/// (ScoreboardHazardRecognizer) and arbitrary target-specific logic.
329///
330/// The second is a streamlined mechanism that checks for hazards based on
331/// simple counters that the scheduler itself maintains. It explicitly checks
332/// for instruction dispatch limitations, including the number of micro-ops that
333/// can dispatch per cycle.
334///
335/// TODO: Also check whether the SU must start a new group.
336bool ConvergingVLIWScheduler::VLIWSchedBoundary::checkHazard(SUnit *SU) {
if (HazardRec->isEnabled())
  return HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard;

unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
if (IssueCount + uops > SchedModel->getIssueWidth())
  return true;

return false;
345}

347void ConvergingVLIWScheduler::VLIWSchedBoundary::releaseNode(SUnit *SU,
                                                   unsigned ReadyCycle) {
if (ReadyCycle < MinReadyCycle)
  MinReadyCycle = ReadyCycle;

// Check for interlocks first. For the purpose of other heuristics, an
// instruction that cannot issue appears as if it's not in the ReadyQueue.
if (ReadyCycle > CurrCycle || checkHazard(SU))

  Pending.push(SU);
else
  Available.push(SU);
359}

361/// Move the boundary of scheduled code by one cycle.
362void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpCycle() {
unsigned Width = SchedModel->getIssueWidth();
IssueCount = (IssueCount <= Width) ? 0 : IssueCount - Width;

assert(MinReadyCycle < std::numeric_limits<unsigned>::max() &&(static_cast<void> (0))
       "MinReadyCycle uninitialized")(static_cast<void> (0));
unsigned NextCycle = std::max(CurrCycle + 1, MinReadyCycle);

if (!HazardRec->isEnabled()) {
  // Bypass HazardRec virtual calls.
  CurrCycle = NextCycle;
} else {
  // Bypass getHazardType calls in case of long latency.
  for (; CurrCycle != NextCycle; ++CurrCycle) {
    if (isTop())
      HazardRec->AdvanceCycle();
    else
      HazardRec->RecedeCycle();
  }
}
CheckPending = true;

LLVM_DEBUG(dbgs() << "*** Next cycle " << Available.getName() << " cycle "do { } while (false)
                  << CurrCycle << '\n')do { } while (false);
386}

388/// Move the boundary of scheduled code by one SUnit.
389void ConvergingVLIWScheduler::VLIWSchedBoundary::bumpNode(SUnit *SU) {
bool startNewCycle = false;

// Update the reservation table.
if (HazardRec->isEnabled()) {
  if (!isTop() && SU->isCall) {
    // Calls are scheduled with their preceding instructions. For bottom-up
    // scheduling, clear the pipeline state before emitting.
    HazardRec->Reset();
  }
  HazardRec->EmitInstruction(SU);
}

// Update DFA model.
startNewCycle = ResourceModel->reserveResources(SU, isTop());

// Check the instruction group dispatch limit.
// TODO: Check if this SU must end a dispatch group.
IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
if (startNewCycle) {
  LLVM_DEBUG(dbgs() << "*** Max instrs at cycle " << CurrCycle << '\n')do { } while (false);
  bumpCycle();
}
else
  LLVM_DEBUG(dbgs() << "*** IssueCount " << IssueCount << " at cycle "do { } while (false)
                    << CurrCycle << '\n')do { } while (false);
415}

417/// Release pending ready nodes in to the available queue. This makes them
418/// visible to heuristics.
419void ConvergingVLIWScheduler::VLIWSchedBoundary::releasePending() {
// If the available queue is empty, it is safe to reset MinReadyCycle.
if (Available.empty())
  MinReadyCycle = std::numeric_limits<unsigned>::max();

// Check to see if any of the pending instructions are ready to issue.  If
// so, add them to the available queue.
for (unsigned i = 0, e = Pending.size(); i != e; ++i) {
  SUnit *SU = *(Pending.begin()+i);
  unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;

  if (ReadyCycle < MinReadyCycle)
    MinReadyCycle = ReadyCycle;

  if (ReadyCycle > CurrCycle)
    continue;

  if (checkHazard(SU))
    continue;

  Available.push(SU);
  Pending.remove(Pending.begin()+i);
  --i; --e;
}
CheckPending = false;
444}

446/// Remove SU from the ready set for this boundary.
447void ConvergingVLIWScheduler::VLIWSchedBoundary::removeReady(SUnit *SU) {
if (Available.isInQueue(SU))
  Available.remove(Available.find(SU));
else {
  assert(Pending.isInQueue(SU) && "bad ready count")(static_cast<void> (0));
  Pending.remove(Pending.find(SU));
}
454}

456/// If this queue only has one ready candidate, return it. As a side effect,
457/// advance the cycle until at least one node is ready. If multiple instructions
458/// are ready, return NULL.
459SUnit *ConvergingVLIWScheduler::VLIWSchedBoundary::pickOnlyChoice() {
if (CheckPending)
12
←
Assuming field 'CheckPending' is false→
13
←
Taking false branch→
  releasePending();

auto AdvanceCycle = [this]() {
  if (Available.empty())
    return true;
  if (Available.size() == 1 && Pending.size() > 0)
    return !ResourceModel->isResourceAvailable(*Available.begin(), isTop()) ||
      getWeakLeft(*Available.begin(), isTop()) != 0;
  return false;
};
for (unsigned i = 0; AdvanceCycle(); ++i) {
14
←
Loop condition is false. Execution continues on line 478→
  assert(i <= (HazardRec->getMaxLookAhead() + MaxMinLatency) &&(static_cast<void> (0))
         "permanent hazard")(static_cast<void> (0)); (void)i;
  ResourceModel->reserveResources(nullptr, isTop());
  bumpCycle();
  releasePending();
}
if (Available.size() == 1)
15
←
Assuming the condition is false→
16
←
Taking false branch→
  return *Available.begin();
return nullptr;
17
←
Returning null pointer, which participates in a condition later→
481}

483#ifndef NDEBUG1
484void ConvergingVLIWScheduler::traceCandidate(const char *Label,
    const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P) {
dbgs() << Label << " " << Q.getName() << " ";
if (P.isValid())
  dbgs() << DAG->TRI->getRegPressureSetName(P.getPSet()) << ":"
         << P.getUnitInc() << " ";
else
  dbgs() << "     ";
dbgs() << "cost(" << Cost << ")\t";
DAG->dumpNode(*SU);
494}

496// Very detailed queue dump, to be used with higher verbosity levels.
497void ConvergingVLIWScheduler::readyQueueVerboseDump(
    const RegPressureTracker &RPTracker, SchedCandidate &Candidate,
    ReadyQueue &Q) {
RegPressureTracker &TempTracker = const_cast<RegPressureTracker &>(RPTracker);

dbgs() << ">>> " << Q.getName() << "\n";
for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
  RegPressureDelta RPDelta;
  TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta,
                                  DAG->getRegionCriticalPSets(),
                                  DAG->getRegPressure().MaxSetPressure);
  std::stringstream dbgstr;
  dbgstr << "SU(" << std::setw(3) << (*I)->NodeNum << ")";
  dbgs() << dbgstr.str();
  SchedulingCost(Q, *I, Candidate, RPDelta, true);
  dbgs() << "\t";
  (*I)->getInstr()->dump();
}
dbgs() << "\n";
516}
517#endif

519/// isSingleUnscheduledPred - If SU2 is the only unscheduled predecessor
520/// of SU, return true (we may have duplicates)
521static inline bool isSingleUnscheduledPred(SUnit *SU, SUnit *SU2) {
if (SU->NumPredsLeft == 0)
  return false;

for (auto &Pred : SU->Preds) {
  // We found an available, but not scheduled, predecessor.
  if (!Pred.getSUnit()->isScheduled && (Pred.getSUnit() != SU2))
    return false;
}

return true;
532}

534/// isSingleUnscheduledSucc - If SU2 is the only unscheduled successor
535/// of SU, return true (we may have duplicates)
536static inline bool isSingleUnscheduledSucc(SUnit *SU, SUnit *SU2) {
if (SU->NumSuccsLeft == 0)
  return false;

for (auto &Succ : SU->Succs) {
  // We found an available, but not scheduled, successor.
  if (!Succ.getSUnit()->isScheduled && (Succ.getSUnit() != SU2))
    return false;
}
return true;
546}

548/// Check if the instruction changes the register pressure of a register in the
549/// high pressure set. The function returns a negative value if the pressure
550/// decreases and a positive value is the pressure increases. If the instruction
551/// doesn't use a high pressure register or doesn't change the register
552/// pressure, then return 0.
553int ConvergingVLIWScheduler::pressureChange(const SUnit *SU, bool isBotUp) {
PressureDiff &PD = DAG->getPressureDiff(SU);
for (auto &P : PD) {
  if (!P.isValid())
    continue;
  // The pressure differences are computed bottom-up, so the comparision for
  // an increase is positive in the bottom direction, but negative in the
  //  top-down direction.
  if (HighPressureSets[P.getPSet()])
    return (isBotUp ? P.getUnitInc() : -P.getUnitInc());
}
return 0;
565}

567// Constants used to denote relative importance of
568// heuristic components for cost computation.
569static const unsigned PriorityOne = 200;
570static const unsigned PriorityTwo = 50;
571static const unsigned PriorityThree = 75;
572static const unsigned ScaleTwo = 10;

574/// Single point to compute overall scheduling cost.
575/// TODO: More heuristics will be used soon.
576int ConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU,
                                          SchedCandidate &Candidate,
                                          RegPressureDelta &Delta,
                                          bool verbose) {
// Initial trivial priority.
int ResCount = 1;

// Do not waste time on a node that is already scheduled.
if (!SU || SU->isScheduled)
  return ResCount;

LLVM_DEBUG(if (verbose) dbgs()do { } while (false)
           << ((Q.getID() == TopQID) ? "(top|" : "(bot|"))do { } while (false);
// Forced priority is high.
if (SU->isScheduleHigh) {
  ResCount += PriorityOne;
  LLVM_DEBUG(dbgs() << "H|")do { } while (false);
}

unsigned IsAvailableAmt = 0;
// Critical path first.
if (Q.getID() == TopQID) {
  if (Top.isLatencyBound(SU)) {
    LLVM_DEBUG(if (verbose) dbgs() << "LB|")do { } while (false);
    ResCount += (SU->getHeight() * ScaleTwo);
  }

  LLVM_DEBUG(if (verbose) {do { } while (false)
    std::stringstream dbgstr;do { } while (false)
    dbgstr << "h" << std::setw(3) << SU->getHeight() << "|";do { } while (false)
    dbgs() << dbgstr.str();do { } while (false)
  })do { } while (false);

  // If resources are available for it, multiply the
  // chance of scheduling.
  if (Top.ResourceModel->isResourceAvailable(SU, true)) {
    IsAvailableAmt = (PriorityTwo + PriorityThree);
    ResCount += IsAvailableAmt;
    LLVM_DEBUG(if (verbose) dbgs() << "A|")do { } while (false);
  } else
    LLVM_DEBUG(if (verbose) dbgs() << " |")do { } while (false);
} else {
  if (Bot.isLatencyBound(SU)) {
    LLVM_DEBUG(if (verbose) dbgs() << "LB|")do { } while (false);
    ResCount += (SU->getDepth() * ScaleTwo);
  }

  LLVM_DEBUG(if (verbose) {do { } while (false)
    std::stringstream dbgstr;do { } while (false)
    dbgstr << "d" << std::setw(3) << SU->getDepth() << "|";do { } while (false)
    dbgs() << dbgstr.str();do { } while (false)
  })do { } while (false);

  // If resources are available for it, multiply the
  // chance of scheduling.
  if (Bot.ResourceModel->isResourceAvailable(SU, false)) {
    IsAvailableAmt = (PriorityTwo + PriorityThree);
    ResCount += IsAvailableAmt;
    LLVM_DEBUG(if (verbose) dbgs() << "A|")do { } while (false);
  } else
    LLVM_DEBUG(if (verbose) dbgs() << " |")do { } while (false);
}

unsigned NumNodesBlocking = 0;
if (Q.getID() == TopQID) {
  // How many SUs does it block from scheduling?
  // Look at all of the successors of this node.
  // Count the number of nodes that
  // this node is the sole unscheduled node for.
  if (Top.isLatencyBound(SU))
    for (const SDep &SI : SU->Succs)
      if (isSingleUnscheduledPred(SI.getSUnit(), SU))
        ++NumNodesBlocking;
} else {
  // How many unscheduled predecessors block this node?
  if (Bot.isLatencyBound(SU))
    for (const SDep &PI : SU->Preds)
      if (isSingleUnscheduledSucc(PI.getSUnit(), SU))
        ++NumNodesBlocking;
}
ResCount += (NumNodesBlocking * ScaleTwo);

LLVM_DEBUG(if (verbose) {do { } while (false)
  std::stringstream dbgstr;do { } while (false)
  dbgstr << "blk " << std::setw(2) << NumNodesBlocking << ")|";do { } while (false)
  dbgs() << dbgstr.str();do { } while (false)
})do { } while (false);

// Factor in reg pressure as a heuristic.
if (!IgnoreBBRegPressure) {
  // Decrease priority by the amount that register pressure exceeds the limit.
  ResCount -= (Delta.Excess.getUnitInc()*PriorityOne);
  // Decrease priority if register pressure exceeds the limit.
  ResCount -= (Delta.CriticalMax.getUnitInc()*PriorityOne);
  // Decrease priority slightly if register pressure would increase over the
  // current maximum.
  ResCount -= (Delta.CurrentMax.getUnitInc()*PriorityTwo);
  // If there are register pressure issues, then we remove the value added for
  // the instruction being available. The rationale is that we really don't
  // want to schedule an instruction that causes a spill.
  if (IsAvailableAmt && pressureChange(SU, Q.getID() != TopQID) > 0 &&
      (Delta.Excess.getUnitInc() || Delta.CriticalMax.getUnitInc() ||
       Delta.CurrentMax.getUnitInc()))
    ResCount -= IsAvailableAmt;
  LLVM_DEBUG(if (verbose) {do { } while (false)
    dbgs() << "RP " << Delta.Excess.getUnitInc() << "/"do { } while (false)
           << Delta.CriticalMax.getUnitInc() << "/"do { } while (false)
           << Delta.CurrentMax.getUnitInc() << ")|";do { } while (false)
  })do { } while (false);
}

// Give a little extra priority to a .cur instruction if there is a resource
// available for it.
auto &QST = DAG->MF.getSubtarget<HexagonSubtarget>();
auto &QII = *QST.getInstrInfo();
if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) {
  if (Q.getID() == TopQID &&
      Top.ResourceModel->isResourceAvailable(SU, true)) {
    ResCount += PriorityTwo;
    LLVM_DEBUG(if (verbose) dbgs() << "C|")do { } while (false);
  } else if (Q.getID() == BotQID &&
             Bot.ResourceModel->isResourceAvailable(SU, false)) {
    ResCount += PriorityTwo;
    LLVM_DEBUG(if (verbose) dbgs() << "C|")do { } while (false);
  }
}

// Give preference to a zero latency instruction if the dependent
// instruction is in the current packet.
if (Q.getID() == TopQID && getWeakLeft(SU, true) == 0) {
  for (const SDep &PI : SU->Preds) {
    if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() &&
        PI.getLatency() == 0 &&
        Top.ResourceModel->isInPacket(PI.getSUnit())) {
      ResCount += PriorityThree;
      LLVM_DEBUG(if (verbose) dbgs() << "Z|")do { } while (false);
    }
  }
} else if (Q.getID() == BotQID && getWeakLeft(SU, false) == 0) {
  for (const SDep &SI : SU->Succs) {
    if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() &&
        SI.getLatency() == 0 &&
        Bot.ResourceModel->isInPacket(SI.getSUnit())) {
      ResCount += PriorityThree;
      LLVM_DEBUG(if (verbose) dbgs() << "Z|")do { } while (false);
    }
  }
}

// If the instruction has a non-zero latency dependence with an instruction in
// the current packet, then it should not be scheduled yet. The case occurs
// when the dependent instruction is scheduled in a new packet, so the
// scheduler updates the current cycle and pending instructions become
// available.
if (CheckEarlyAvail) {
  if (Q.getID() == TopQID) {
    for (const auto &PI : SU->Preds) {
      if (PI.getLatency() > 0 &&
          Top.ResourceModel->isInPacket(PI.getSUnit())) {
        ResCount -= PriorityOne;
        LLVM_DEBUG(if (verbose) dbgs() << "D|")do { } while (false);
      }
    }
  } else {
    for (const auto &SI : SU->Succs) {
      if (SI.getLatency() > 0 &&
          Bot.ResourceModel->isInPacket(SI.getSUnit())) {
        ResCount -= PriorityOne;
        LLVM_DEBUG(if (verbose) dbgs() << "D|")do { } while (false);
      }
    }
  }
}

LLVM_DEBUG(if (verbose) {do { } while (false)
  std::stringstream dbgstr;do { } while (false)
  dbgstr << "Total " << std::setw(4) << ResCount << ")";do { } while (false)
  dbgs() << dbgstr.str();do { } while (false)
})do { } while (false);

return ResCount;
757}

759/// Pick the best candidate from the top queue.
760///
761/// TODO: getMaxPressureDelta results can be mostly cached for each SUnit during
762/// DAG building. To adjust for the current scheduling location we need to
763/// maintain the number of vreg uses remaining to be top-scheduled.
764ConvergingVLIWScheduler::CandResult ConvergingVLIWScheduler::
765pickNodeFromQueue(VLIWSchedBoundary &Zone, const RegPressureTracker &RPTracker,
                SchedCandidate &Candidate) {
ReadyQueue &Q = Zone.Available;
LLVM_DEBUG(if (SchedDebugVerboseLevel > 1)do { } while (false)
24
←
Loop condition is false.  Exiting loop→
               readyQueueVerboseDump(RPTracker, Candidate, Q);do { } while (false)
           else Q.dump();)do { } while (false);

// getMaxPressureDelta temporarily modifies the tracker.
RegPressureTracker &TempTracker = const_cast<RegPressureTracker&>(RPTracker);

// BestSU remains NULL if no top candidates beat the best existing candidate.
CandResult FoundCandidate = NoCand;
for (ReadyQueue::iterator I = Q.begin(), E = Q.end(); I != E; ++I) {
25
←
Loop condition is false. Execution continues on line 875→
  RegPressureDelta RPDelta;
  TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta,
                                  DAG->getRegionCriticalPSets(),
                                  DAG->getRegPressure().MaxSetPressure);

  int CurrentCost = SchedulingCost(Q, *I, Candidate, RPDelta, false);

  // Initialize the candidate if needed.
  if (!Candidate.SU) {
    LLVM_DEBUG(traceCandidate("DCAND", Q, *I, CurrentCost))do { } while (false);
    Candidate.SU = *I;
    Candidate.RPDelta = RPDelta;
    Candidate.SCost = CurrentCost;
    FoundCandidate = NodeOrder;
    continue;
  }

  // Choose node order for negative cost candidates. There is no good
  // candidate in this case.
  if (CurrentCost < 0 && Candidate.SCost < 0) {
    if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum)
        || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) {
      LLVM_DEBUG(traceCandidate("NCAND", Q, *I, CurrentCost))do { } while (false);
      Candidate.SU = *I;
      Candidate.RPDelta = RPDelta;
      Candidate.SCost = CurrentCost;
      FoundCandidate = NodeOrder;
    }
    continue;
  }

  // Best cost.
  if (CurrentCost > Candidate.SCost) {
    LLVM_DEBUG(traceCandidate("CCAND", Q, *I, CurrentCost))do { } while (false);
    Candidate.SU = *I;
    Candidate.RPDelta = RPDelta;
    Candidate.SCost = CurrentCost;
    FoundCandidate = BestCost;
    continue;
  }

  // Choose an instruction that does not depend on an artificial edge.
  unsigned CurrWeak = getWeakLeft(*I, (Q.getID() == TopQID));
  unsigned CandWeak = getWeakLeft(Candidate.SU, (Q.getID() == TopQID));
  if (CurrWeak != CandWeak) {
    if (CurrWeak < CandWeak) {
      LLVM_DEBUG(traceCandidate("WCAND", Q, *I, CurrentCost))do { } while (false);
      Candidate.SU = *I;
      Candidate.RPDelta = RPDelta;
      Candidate.SCost = CurrentCost;
      FoundCandidate = Weak;
    }
    continue;
  }

  if (CurrentCost == Candidate.SCost && Zone.isLatencyBound(*I)) {
    unsigned CurrSize, CandSize;
    if (Q.getID() == TopQID) {
      CurrSize = (*I)->Succs.size();
      CandSize = Candidate.SU->Succs.size();
    } else {
      CurrSize = (*I)->Preds.size();
      CandSize = Candidate.SU->Preds.size();
    }
    if (CurrSize > CandSize) {
      LLVM_DEBUG(traceCandidate("SPCAND", Q, *I, CurrentCost))do { } while (false);
      Candidate.SU = *I;
      Candidate.RPDelta = RPDelta;
      Candidate.SCost = CurrentCost;
      FoundCandidate = BestCost;
    }
    // Keep the old candidate if it's a better candidate. That is, don't use
    // the subsequent tie breaker.
    if (CurrSize != CandSize)
      continue;
  }

  // Tie breaker.
  // To avoid scheduling indeterminism, we need a tie breaker
  // for the case when cost is identical for two nodes.
  if (UseNewerCandidate && CurrentCost == Candidate.SCost) {
    if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum)
        || (Q.getID() == BotQID && (*I)->NodeNum > Candidate.SU->NodeNum)) {
      LLVM_DEBUG(traceCandidate("TCAND", Q, *I, CurrentCost))do { } while (false);
      Candidate.SU = *I;
      Candidate.RPDelta = RPDelta;
      Candidate.SCost = CurrentCost;
      FoundCandidate = NodeOrder;
      continue;
    }
  }

  // Fall through to original instruction order.
  // Only consider node order if Candidate was chosen from this Q.
  if (FoundCandidate == NoCand)
    continue;
}
return FoundCandidate;
26
←
Returning without writing to 'Candidate.SU'→
876}

878/// Pick the best candidate node from either the top or bottom queue.
879SUnit *ConvergingVLIWScheduler::pickNodeBidrectional(bool &IsTopNode) {
// Schedule as far as possible in the direction of no choice. This is most
// efficient, but also provides the best heuristics for CriticalPSets.
if (SUnit *SU = Bot.pickOnlyChoice()) {
  LLVM_DEBUG(dbgs() << "Picked only Bottom\n")do { } while (false);
  IsTopNode = false;
  return SU;
}
if (SUnit *SU = Top.pickOnlyChoice()) {
  LLVM_DEBUG(dbgs() << "Picked only Top\n")do { } while (false);
  IsTopNode = true;
  return SU;
}
SchedCandidate BotCand;
// Prefer bottom scheduling when heuristics are silent.
CandResult BotResult = pickNodeFromQueue(Bot,
                                         DAG->getBotRPTracker(), BotCand);
assert(BotResult != NoCand && "failed to find the first candidate")(static_cast<void> (0));

// If either Q has a single candidate that provides the least increase in
// Excess pressure, we can immediately schedule from that Q.
//
// RegionCriticalPSets summarizes the pressure within the scheduled region and
// affects picking from either Q. If scheduling in one direction must
// increase pressure for one of the excess PSets, then schedule in that
// direction first to provide more freedom in the other direction.
if (BotResult == SingleExcess || BotResult == SingleCritical) {
  LLVM_DEBUG(dbgs() << "Prefered Bottom Node\n")do { } while (false);
  IsTopNode = false;
  return BotCand.SU;
}
// Check if the top Q has a better candidate.
SchedCandidate TopCand;
CandResult TopResult = pickNodeFromQueue(Top,
                                         DAG->getTopRPTracker(), TopCand);
assert(TopResult != NoCand && "failed to find the first candidate")(static_cast<void> (0));

if (TopResult == SingleExcess || TopResult == SingleCritical) {
  LLVM_DEBUG(dbgs() << "Prefered Top Node\n")do { } while (false);
  IsTopNode = true;
  return TopCand.SU;
}
// If either Q has a single candidate that minimizes pressure above the
// original region's pressure pick it.
if (BotResult == SingleMax) {
  LLVM_DEBUG(dbgs() << "Prefered Bottom Node SingleMax\n")do { } while (false);
  IsTopNode = false;
  return BotCand.SU;
}
if (TopResult == SingleMax) {
  LLVM_DEBUG(dbgs() << "Prefered Top Node SingleMax\n")do { } while (false);
  IsTopNode = true;
  return TopCand.SU;
}
if (TopCand.SCost > BotCand.SCost) {
  LLVM_DEBUG(dbgs() << "Prefered Top Node Cost\n")do { } while (false);
  IsTopNode = true;
  return TopCand.SU;
}
// Otherwise prefer the bottom candidate in node order.
LLVM_DEBUG(dbgs() << "Prefered Bottom in Node order\n")do { } while (false);
IsTopNode = false;
return BotCand.SU;
942}

944/// Pick the best node to balance the schedule. Implements MachineSchedStrategy.
945SUnit *ConvergingVLIWScheduler::pickNode(bool &IsTopNode) {
if (DAG->top() == DAG->bottom()) {
1
Calling 'operator=='→
7
←
Returning from 'operator=='→
8
←
Taking false branch→
  assert(Top.Available.empty() && Top.Pending.empty() &&(static_cast<void> (0))
         Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage")(static_cast<void> (0));
  return nullptr;
}
SUnit *SU;
if (ForceTopDown) {
9
←
Assuming the condition is true→
10
←
Taking true branch→
  SU = Top.pickOnlyChoice();
11
←
Calling 'VLIWSchedBoundary::pickOnlyChoice'→
18
←
Returning from 'VLIWSchedBoundary::pickOnlyChoice'→
  if (!SU18.1
'SU' is null
1
'SU' is null
1
'SU' is null
1
'SU' is null
) {
19
←
Taking true branch→
    SchedCandidate TopCand;
20
←
Calling defaulted default constructor for 'SchedCandidate'→
22
←
Returning from default constructor for 'SchedCandidate'→
    CandResult TopResult =
      pickNodeFromQueue(Top, DAG->getTopRPTracker(), TopCand);
23
←
Calling 'ConvergingVLIWScheduler::pickNodeFromQueue'→
27
←
Returning from 'ConvergingVLIWScheduler::pickNodeFromQueue'→
    assert(TopResult != NoCand && "failed to find the first candidate")(static_cast<void> (0));
    (void)TopResult;
    SU = TopCand.SU;
28
←
Null pointer value stored to 'SU'→
  }
  IsTopNode = true;
} else if (ForceBottomUp) {
  SU = Bot.pickOnlyChoice();
  if (!SU) {
    SchedCandidate BotCand;
    CandResult BotResult =
      pickNodeFromQueue(Bot, DAG->getBotRPTracker(), BotCand);
    assert(BotResult != NoCand && "failed to find the first candidate")(static_cast<void> (0));
    (void)BotResult;
    SU = BotCand.SU;
  }
  IsTopNode = false;
} else {
  SU = pickNodeBidrectional(IsTopNode);
}
if (SU->isTopReady())
29
←
Called C++ object pointer is null
  Top.removeReady(SU);
if (SU->isBottomReady())
  Bot.removeReady(SU);

LLVM_DEBUG(dbgs() << "*** " << (IsTopNode ? "Top" : "Bottom")do { } while (false)
                  << " Scheduling instruction in cycle "do { } while (false)
                  << (IsTopNode ? Top.CurrCycle : Bot.CurrCycle) << " ("do { } while (false)
                  << reportPackets() << ")\n";do { } while (false)
           DAG->dumpNode(*SU))do { } while (false);
return SU;
988}

990/// Update the scheduler's state after scheduling a node. This is the same node
991/// that was just returned by pickNode(). However, VLIWMachineScheduler needs
992/// to update it's state based on the current cycle before MachineSchedStrategy
993/// does.
994void ConvergingVLIWScheduler::schedNode(SUnit *SU, bool IsTopNode) {
if (IsTopNode) {
  Top.bumpNode(SU);
  SU->TopReadyCycle = Top.CurrCycle;
} else {
  Bot.bumpNode(SU);
  SU->BotReadyCycle = Bot.CurrCycle;
}
1002}

←

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h

→

1//===- llvm/CodeGen/MachineInstrBundleIterator.h ----------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Defines an iterator class that bundles MachineInstr.
10//
11//===----------------------------------------------------------------------===//

13#ifndef LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H
14#define LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H

16#include "llvm/ADT/ilist.h"
17#include "llvm/ADT/simple_ilist.h"
18#include <cassert>
19#include <iterator>
20#include <type_traits>

22namespace llvm {

24template <class T, bool IsReverse> struct MachineInstrBundleIteratorTraits;
25template <class T> struct MachineInstrBundleIteratorTraits<T, false> {
using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
using instr_iterator = typename list_type::iterator;
using nonconst_instr_iterator = typename list_type::iterator;
using const_instr_iterator = typename list_type::const_iterator;
30};
31template <class T> struct MachineInstrBundleIteratorTraits<T, true> {
using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
using instr_iterator = typename list_type::reverse_iterator;
using nonconst_instr_iterator = typename list_type::reverse_iterator;
using const_instr_iterator = typename list_type::const_reverse_iterator;
36};
37template <class T> struct MachineInstrBundleIteratorTraits<const T, false> {
using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
using instr_iterator = typename list_type::const_iterator;
using nonconst_instr_iterator = typename list_type::iterator;
using const_instr_iterator = typename list_type::const_iterator;
42};
43template <class T> struct MachineInstrBundleIteratorTraits<const T, true> {
using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
using instr_iterator = typename list_type::const_reverse_iterator;
using nonconst_instr_iterator = typename list_type::reverse_iterator;
using const_instr_iterator = typename list_type::const_reverse_iterator;
48};

50template <bool IsReverse> struct MachineInstrBundleIteratorHelper;
51template <> struct MachineInstrBundleIteratorHelper<false> {
/// Get the beginning of the current bundle.
template <class Iterator> static Iterator getBundleBegin(Iterator I) {
  if (!I.isEnd())
    while (I->isBundledWithPred())
      --I;
  return I;
}

/// Get the final node of the current bundle.
template <class Iterator> static Iterator getBundleFinal(Iterator I) {
  if (!I.isEnd())
    while (I->isBundledWithSucc())
      ++I;
  return I;
}

/// Increment forward ilist iterator.
template <class Iterator> static void increment(Iterator &I) {
  I = std::next(getBundleFinal(I));
}

/// Decrement forward ilist iterator.
template <class Iterator> static void decrement(Iterator &I) {
  I = getBundleBegin(std::prev(I));
}
77};

79template <> struct MachineInstrBundleIteratorHelper<true> {
/// Get the beginning of the current bundle.
template <class Iterator> static Iterator getBundleBegin(Iterator I) {
  return MachineInstrBundleIteratorHelper<false>::getBundleBegin(
             I.getReverse())
      .getReverse();
}

/// Get the final node of the current bundle.
template <class Iterator> static Iterator getBundleFinal(Iterator I) {
  return MachineInstrBundleIteratorHelper<false>::getBundleFinal(
             I.getReverse())
      .getReverse();
}

/// Increment reverse ilist iterator.
template <class Iterator> static void increment(Iterator &I) {
  I = getBundleBegin(std::next(I));
}

/// Decrement reverse ilist iterator.
template <class Iterator> static void decrement(Iterator &I) {
  I = std::prev(getBundleFinal(I));
}
103};

105/// MachineBasicBlock iterator that automatically skips over MIs that are
106/// inside bundles (i.e. walk top level MIs only).
107template <typename Ty, bool IsReverse = false>
108class MachineInstrBundleIterator : MachineInstrBundleIteratorHelper<IsReverse> {
using Traits = MachineInstrBundleIteratorTraits<Ty, IsReverse>;
using instr_iterator = typename Traits::instr_iterator;

instr_iterator MII;

114public:
using value_type = typename instr_iterator::value_type;
using difference_type = typename instr_iterator::difference_type;
using pointer = typename instr_iterator::pointer;
using reference = typename instr_iterator::reference;
using const_pointer = typename instr_iterator::const_pointer;
using const_reference = typename instr_iterator::const_reference;
using iterator_category = std::bidirectional_iterator_tag;

123private:
using nonconst_instr_iterator = typename Traits::nonconst_instr_iterator;
using const_instr_iterator = typename Traits::const_instr_iterator;
using nonconst_iterator =
    MachineInstrBundleIterator<typename nonconst_instr_iterator::value_type,
                               IsReverse>;
using reverse_iterator = MachineInstrBundleIterator<Ty, !IsReverse>;

131public:
MachineInstrBundleIterator(instr_iterator MI) : MII(MI) {
  assert((!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) &&(static_cast<void> (0))
         "It's not legal to initialize MachineInstrBundleIterator with a "(static_cast<void> (0))
         "bundled MI")(static_cast<void> (0));
}

MachineInstrBundleIterator(reference MI) : MII(MI) {
  assert(!MI.isBundledWithPred() && "It's not legal to initialize "(static_cast<void> (0))
                                    "MachineInstrBundleIterator with a "(static_cast<void> (0))
                                    "bundled MI")(static_cast<void> (0));
}

MachineInstrBundleIterator(pointer MI) : MII(MI) {
  // FIXME: This conversion should be explicit.
  assert((!MI || !MI->isBundledWithPred()) && "It's not legal to initialize "(static_cast<void> (0))
                                              "MachineInstrBundleIterator "(static_cast<void> (0))
                                              "with a bundled MI")(static_cast<void> (0));
}

// Template allows conversion from const to nonconst.
template <class OtherTy>
MachineInstrBundleIterator(
    const MachineInstrBundleIterator<OtherTy, IsReverse> &I,
    std::enable_if_t<std::is_convertible<OtherTy *, Ty *>::value, void *> =
        nullptr)
    : MII(I.getInstrIterator()) {}

MachineInstrBundleIterator() : MII(nullptr) {}

/// Explicit conversion between forward/reverse iterators.
///
/// Translate between forward and reverse iterators without changing range
/// boundaries.  The resulting iterator will dereference (and have a handle)
/// to the previous node, which is somewhat unexpected; but converting the
/// two endpoints in a range will give the same range in reverse.
///
/// This matches std::reverse_iterator conversions.
explicit MachineInstrBundleIterator(
    const MachineInstrBundleIterator<Ty, !IsReverse> &I)
    : MachineInstrBundleIterator(++I.getReverse()) {}

/// Get the bundle iterator for the given instruction's bundle.
static MachineInstrBundleIterator getAtBundleBegin(instr_iterator MI) {
  return MachineInstrBundleIteratorHelper<IsReverse>::getBundleBegin(MI);
}

reference operator*() const { return *MII; }
pointer operator->() const { return &operator*(); }

/// Check for null.
bool isValid() const { return MII.getNodePtr(); }

friend bool operator==(const MachineInstrBundleIterator &L,
                       const MachineInstrBundleIterator &R) {
  return L.MII == R.MII;
2
←
Calling 'operator=='→
5
←
Returning from 'operator=='→
6
←
Returning zero, which participates in a condition later→
}
friend bool operator==(const MachineInstrBundleIterator &L,
                       const const_instr_iterator &R) {
  return L.MII == R; // Avoid assertion about validity of R.
}
friend bool operator==(const const_instr_iterator &L,
                       const MachineInstrBundleIterator &R) {
  return L == R.MII; // Avoid assertion about validity of L.
}
friend bool operator==(const MachineInstrBundleIterator &L,
                       const nonconst_instr_iterator &R) {
  return L.MII == R; // Avoid assertion about validity of R.
}
friend bool operator==(const nonconst_instr_iterator &L,
                       const MachineInstrBundleIterator &R) {
  return L == R.MII; // Avoid assertion about validity of L.
}
friend bool operator==(const MachineInstrBundleIterator &L, const_pointer R) {
  return L == const_instr_iterator(R); // Avoid assertion about validity of R.
}
friend bool operator==(const_pointer L, const MachineInstrBundleIterator &R) {
  return const_instr_iterator(L) == R; // Avoid assertion about validity of L.
}
friend bool operator==(const MachineInstrBundleIterator &L,
                       const_reference R) {
  return L == &R; // Avoid assertion about validity of R.
}
friend bool operator==(const_reference L,
                       const MachineInstrBundleIterator &R) {
  return &L == R; // Avoid assertion about validity of L.
}

friend bool operator!=(const MachineInstrBundleIterator &L,
                       const MachineInstrBundleIterator &R) {
  return !(L == R);
}
friend bool operator!=(const MachineInstrBundleIterator &L,
                       const const_instr_iterator &R) {
  return !(L == R);
}
friend bool operator!=(const const_instr_iterator &L,
                       const MachineInstrBundleIterator &R) {
  return !(L == R);
}
friend bool operator!=(const MachineInstrBundleIterator &L,
                       const nonconst_instr_iterator &R) {
  return !(L == R);
}
friend bool operator!=(const nonconst_instr_iterator &L,
                       const MachineInstrBundleIterator &R) {
  return !(L == R);
}
friend bool operator!=(const MachineInstrBundleIterator &L, const_pointer R) {
  return !(L == R);
}
friend bool operator!=(const_pointer L, const MachineInstrBundleIterator &R) {
  return !(L == R);
}
friend bool operator!=(const MachineInstrBundleIterator &L,
                       const_reference R) {
  return !(L == R);
}
friend bool operator!=(const_reference L,
                       const MachineInstrBundleIterator &R) {
  return !(L == R);
}

// Increment and decrement operators...
MachineInstrBundleIterator &operator--() {
  this->decrement(MII);
  return *this;
}
MachineInstrBundleIterator &operator++() {
  this->increment(MII);
  return *this;
}
MachineInstrBundleIterator operator--(int) {
  MachineInstrBundleIterator Temp = *this;
  --*this;
  return Temp;
}
MachineInstrBundleIterator operator++(int) {
  MachineInstrBundleIterator Temp = *this;
  ++*this;
  return Temp;
}

instr_iterator getInstrIterator() const { return MII; }

nonconst_iterator getNonConstIterator() const { return MII.getNonConst(); }

/// Get a reverse iterator to the same node.
///
/// Gives a reverse iterator that will dereference (and have a handle) to the
/// same node.  Converting the endpoint iterators in a range will give a
/// different range; for range operations, use the explicit conversions.
reverse_iterator getReverse() const { return MII.getReverse(); }
284};

286} // end namespace llvm

288#endif // LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H

←

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include/llvm/ADT/ilist_iterator.h

→

1//===- llvm/ADT/ilist_iterator.h - Intrusive List Iterator ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//

9#ifndef LLVM_ADT_ILIST_ITERATOR_H
10#define LLVM_ADT_ILIST_ITERATOR_H

12#include "llvm/ADT/ilist_node.h"
13#include <cassert>
14#include <cstddef>
15#include <iterator>
16#include <type_traits>

18namespace llvm {

20namespace ilist_detail {

22/// Find const-correct node types.
23template <class OptionsT, bool IsConst> struct IteratorTraits;
24template <class OptionsT> struct IteratorTraits<OptionsT, false> {
using value_type = typename OptionsT::value_type;
using pointer = typename OptionsT::pointer;
using reference = typename OptionsT::reference;
using node_pointer = ilist_node_impl<OptionsT> *;
using node_reference = ilist_node_impl<OptionsT> &;
30};
31template <class OptionsT> struct IteratorTraits<OptionsT, true> {
using value_type = const typename OptionsT::value_type;
using pointer = typename OptionsT::const_pointer;
using reference = typename OptionsT::const_reference;
using node_pointer = const ilist_node_impl<OptionsT> *;
using node_reference = const ilist_node_impl<OptionsT> &;
37};

39template <bool IsReverse> struct IteratorHelper;
40template <> struct IteratorHelper<false> : ilist_detail::NodeAccess {
using Access = ilist_detail::NodeAccess;

template <class T> static void increment(T *&I) { I = Access::getNext(*I); }
template <class T> static void decrement(T *&I) { I = Access::getPrev(*I); }
45};
46template <> struct IteratorHelper<true> : ilist_detail::NodeAccess {
using Access = ilist_detail::NodeAccess;

template <class T> static void increment(T *&I) { I = Access::getPrev(*I); }
template <class T> static void decrement(T *&I) { I = Access::getNext(*I); }
51};

53} // end namespace ilist_detail

55/// Iterator for intrusive lists  based on ilist_node.
56template <class OptionsT, bool IsReverse, bool IsConst>
57class ilist_iterator : ilist_detail::SpecificNodeAccess<OptionsT> {
friend ilist_iterator<OptionsT, IsReverse, !IsConst>;
friend ilist_iterator<OptionsT, !IsReverse, IsConst>;
friend ilist_iterator<OptionsT, !IsReverse, !IsConst>;

using Traits = ilist_detail::IteratorTraits<OptionsT, IsConst>;
using Access = ilist_detail::SpecificNodeAccess<OptionsT>;

65public:
using value_type = typename Traits::value_type;
using pointer = typename Traits::pointer;
using reference = typename Traits::reference;
using difference_type = ptrdiff_t;
using iterator_category = std::bidirectional_iterator_tag;
using const_pointer = typename OptionsT::const_pointer;
using const_reference = typename OptionsT::const_reference;

74private:
using node_pointer = typename Traits::node_pointer;
using node_reference = typename Traits::node_reference;

node_pointer NodePtr = nullptr;

80public:
/// Create from an ilist_node.
explicit ilist_iterator(node_reference N) : NodePtr(&N) {}

explicit ilist_iterator(pointer NP) : NodePtr(Access::getNodePtr(NP)) {}
explicit ilist_iterator(reference NR) : NodePtr(Access::getNodePtr(&NR)) {}
ilist_iterator() = default;

// This is templated so that we can allow constructing a const iterator from
// a nonconst iterator...
template <bool RHSIsConst>
ilist_iterator(const ilist_iterator<OptionsT, IsReverse, RHSIsConst> &RHS,
               std::enable_if_t<IsConst || !RHSIsConst, void *> = nullptr)
    : NodePtr(RHS.NodePtr) {}

// This is templated so that we can allow assigning to a const iterator from
// a nonconst iterator...
template <bool RHSIsConst>
std::enable_if_t<IsConst || !RHSIsConst, ilist_iterator &>
operator=(const ilist_iterator<OptionsT, IsReverse, RHSIsConst> &RHS) {
  NodePtr = RHS.NodePtr;
  return *this;
}

/// Explicit conversion between forward/reverse iterators.
///
/// Translate between forward and reverse iterators without changing range
/// boundaries.  The resulting iterator will dereference (and have a handle)
/// to the previous node, which is somewhat unexpected; but converting the
/// two endpoints in a range will give the same range in reverse.
///
/// This matches std::reverse_iterator conversions.
explicit ilist_iterator(
    const ilist_iterator<OptionsT, !IsReverse, IsConst> &RHS)
    : ilist_iterator(++RHS.getReverse()) {}

/// Get a reverse iterator to the same node.
///
/// Gives a reverse iterator that will dereference (and have a handle) to the
/// same node.  Converting the endpoint iterators in a range will give a
/// different range; for range operations, use the explicit conversions.
ilist_iterator<OptionsT, !IsReverse, IsConst> getReverse() const {
  if (NodePtr)
    return ilist_iterator<OptionsT, !IsReverse, IsConst>(*NodePtr);
  return ilist_iterator<OptionsT, !IsReverse, IsConst>();
}

/// Const-cast.
ilist_iterator<OptionsT, IsReverse, false> getNonConst() const {
  if (NodePtr)
    return ilist_iterator<OptionsT, IsReverse, false>(
        const_cast<typename ilist_iterator<OptionsT, IsReverse,
                                           false>::node_reference>(*NodePtr));
  return ilist_iterator<OptionsT, IsReverse, false>();
}

// Accessors...
reference operator*() const {
  assert(!NodePtr->isKnownSentinel())(static_cast<void> (0));
  return *Access::getValuePtr(NodePtr);
}
pointer operator->() const { return &operator*(); }

// Comparison operators
friend bool operator==(const ilist_iterator &LHS, const ilist_iterator &RHS) {
  return LHS.NodePtr == RHS.NodePtr;
3
←
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'→
4
←
Returning zero, which participates in a condition later→
}
friend bool operator!=(const ilist_iterator &LHS, const ilist_iterator &RHS) {
  return LHS.NodePtr != RHS.NodePtr;
}

// Increment and decrement operators...
ilist_iterator &operator--() {
  NodePtr = IsReverse ? NodePtr->getNext() : NodePtr->getPrev();
  return *this;
}
ilist_iterator &operator++() {
  NodePtr = IsReverse ? NodePtr->getPrev() : NodePtr->getNext();
  return *this;
}
ilist_iterator operator--(int) {
  ilist_iterator tmp = *this;
  --*this;
  return tmp;
}
ilist_iterator operator++(int) {
  ilist_iterator tmp = *this;
  ++*this;
  return tmp;
}

/// Get the underlying ilist_node.
node_pointer getNodePtr() const { return static_cast<node_pointer>(NodePtr); }

/// Check for end.  Only valid if ilist_sentinel_tracking<true>.
bool isEnd() const { return NodePtr ? NodePtr->isSentinel() : false; }
176};

178template <typename From> struct simplify_type;

180/// Allow ilist_iterators to convert into pointers to a node automatically when
181/// used by the dyn_cast, cast, isa mechanisms...
182///
183/// FIXME: remove this, since there is no implicit conversion to NodeTy.
184template <class OptionsT, bool IsConst>
185struct simplify_type<ilist_iterator<OptionsT, false, IsConst>> {
using iterator = ilist_iterator<OptionsT, false, IsConst>;
using SimpleType = typename iterator::pointer;

static SimpleType getSimplifiedValue(const iterator &Node) { return &*Node; }
190};
191template <class OptionsT, bool IsConst>
192struct simplify_type<const ilist_iterator<OptionsT, false, IsConst>>
  : simplify_type<ilist_iterator<OptionsT, false, IsConst>> {};

195} // end namespace llvm

197#endif // LLVM_ADT_ILIST_ITERATOR_H

←

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h

1//===- HexagonMachineScheduler.h - Custom Hexagon MI scheduler --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Custom Hexagon MI scheduler.
10//
11//===----------------------------------------------------------------------===//

13#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
14#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H

16#include "llvm/ADT/STLExtras.h"
17#include "llvm/ADT/Twine.h"
18#include "llvm/CodeGen/DFAPacketizer.h"
19#include "llvm/CodeGen/MachineScheduler.h"
20#include "llvm/CodeGen/RegisterPressure.h"
21#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
22#include "llvm/CodeGen/TargetInstrInfo.h"
23#include "llvm/CodeGen/TargetSchedule.h"
24#include "llvm/CodeGen/TargetSubtargetInfo.h"
25#include <algorithm>
26#include <cassert>
27#include <limits>
28#include <memory>
29#include <vector>

31namespace llvm {

33class SUnit;

35class VLIWResourceModel {
/// ResourcesModel - Represents VLIW state.
/// Not limited to VLIW targets per se, but assumes
/// definition of DFA by a target.
DFAPacketizer *ResourcesModel;

const TargetSchedModel *SchedModel;

/// Local packet/bundle model. Purely
/// internal to the MI schedulre at the time.
std::vector<SUnit *> Packet;

/// Total packets created.
unsigned TotalPackets = 0;

50public:
VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
    : SchedModel(SM) {
  ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI);

  // This hard requirement could be relaxed,
  // but for now do not let it proceed.
  assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.")(static_cast<void> (0));

  Packet.resize(SchedModel->getIssueWidth());
  Packet.clear();
  ResourcesModel->clearResources();
}

~VLIWResourceModel() {
  delete ResourcesModel;
}

void resetPacketState() {
  Packet.clear();
}

void resetDFA() {
  ResourcesModel->clearResources();
}

void reset() {
  Packet.clear();
  ResourcesModel->clearResources();
}

bool isResourceAvailable(SUnit *SU, bool IsTop);
bool reserveResources(SUnit *SU, bool IsTop);
unsigned getTotalPackets() const { return TotalPackets; }
bool isInPacket(SUnit *SU) const { return is_contained(Packet, SU); }
85};

87/// Extend the standard ScheduleDAGMI to provide more context and override the
88/// top-level schedule() driver.
89class VLIWMachineScheduler : public ScheduleDAGMILive {
90public:
VLIWMachineScheduler(MachineSchedContext *C,
                     std::unique_ptr<MachineSchedStrategy> S)
    : ScheduleDAGMILive(C, std::move(S)) {}

/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
/// time to do some work.
void schedule() override;

RegisterClassInfo *getRegClassInfo() { return RegClassInfo; }
int getBBSize() { return BB->size(); }
101};

103//===----------------------------------------------------------------------===//
104// ConvergingVLIWScheduler - Implementation of the standard
105// MachineSchedStrategy.
106//===----------------------------------------------------------------------===//

108/// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics
109/// to balance the schedule.
110class ConvergingVLIWScheduler : public MachineSchedStrategy {
/// Store the state used by ConvergingVLIWScheduler heuristics, required
///  for the lifetime of one invocation of pickNode().
struct SchedCandidate {
  // The best SUnit candidate.
  SUnit *SU = nullptr;
21
←
Null pointer value stored to 'TopCand.SU'→

  // Register pressure values for the best candidate.
  RegPressureDelta RPDelta;

  // Best scheduling cost.
  int SCost = 0;

  SchedCandidate() = default;
};
/// Represent the type of SchedCandidate found within a single queue.
enum CandResult {
  NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure,
  BestCost, Weak};

/// Each Scheduling boundary is associated with ready queues. It tracks the
/// current cycle in whichever direction at has moved, and maintains the state
/// of "hazards" and other interlocks at the current cycle.
struct VLIWSchedBoundary {
  VLIWMachineScheduler *DAG = nullptr;
  const TargetSchedModel *SchedModel = nullptr;

  ReadyQueue Available;
  ReadyQueue Pending;
  bool CheckPending = false;

  ScheduleHazardRecognizer *HazardRec = nullptr;
  VLIWResourceModel *ResourceModel = nullptr;

  unsigned CurrCycle = 0;
  unsigned IssueCount = 0;
  unsigned CriticalPathLength = 0;

  /// MinReadyCycle - Cycle of the soonest available instruction.
  unsigned MinReadyCycle = std::numeric_limits<unsigned>::max();

  // Remember the greatest min operand latency.
  unsigned MaxMinLatency = 0;

  /// Pending queues extend the ready queues with the same ID and the
  /// PendingFlag set.
  VLIWSchedBoundary(unsigned ID, const Twine &Name)
      : Available(ID, Name+".A"),
        Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P") {}

  ~VLIWSchedBoundary() {
    delete ResourceModel;
    delete HazardRec;
  }

  void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
    DAG = dag;
    SchedModel = smodel;
    CurrCycle = 0;
    IssueCount = 0;
    // Initialize the critical path length limit, which used by the scheduling
    // cost model to determine the value for scheduling an instruction. We use
    // a slightly different heuristic for small and large functions. For small
    // functions, it's important to use the height/depth of the instruction.
    // For large functions, prioritizing by height or depth increases spills.
    CriticalPathLength = DAG->getBBSize() / SchedModel->getIssueWidth();
    if (DAG->getBBSize() < 50)
      // We divide by two as a cheap and simple heuristic to reduce the
      // critcal path length, which increases the priority of using the graph
      // height/depth in the scheduler's cost computation.
      CriticalPathLength >>= 1;
    else {
      // For large basic blocks, we prefer a larger critical path length to
      // decrease the priority of using the graph height/depth.
      unsigned MaxPath = 0;
      for (auto &SU : DAG->SUnits)
        MaxPath = std::max(MaxPath, isTop() ? SU.getHeight() : SU.getDepth());
      CriticalPathLength = std::max(CriticalPathLength, MaxPath) + 1;
    }
  }

  bool isTop() const {
    return Available.getID() == ConvergingVLIWScheduler::TopQID;
  }

  bool checkHazard(SUnit *SU);

  void releaseNode(SUnit *SU, unsigned ReadyCycle);

  void bumpCycle();

  void bumpNode(SUnit *SU);

  void releasePending();

  void removeReady(SUnit *SU);

  SUnit *pickOnlyChoice();

  bool isLatencyBound(SUnit *SU) {
    if (CurrCycle >= CriticalPathLength)
      return true;
    unsigned PathLength = isTop() ? SU->getHeight() : SU->getDepth();
    return CriticalPathLength - CurrCycle <= PathLength;
  }
};

VLIWMachineScheduler *DAG = nullptr;
const TargetSchedModel *SchedModel = nullptr;

// State of the top and bottom scheduled instruction boundaries.
VLIWSchedBoundary Top;
VLIWSchedBoundary Bot;

/// List of pressure sets that have a high pressure level in the region.
std::vector<bool> HighPressureSets;

227public:
/// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
enum {
  TopQID = 1,
  BotQID = 2,
  LogMaxQID = 2
};

ConvergingVLIWScheduler() : Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}

void initialize(ScheduleDAGMI *dag) override;

SUnit *pickNode(bool &IsTopNode) override;

void schedNode(SUnit *SU, bool IsTopNode) override;

void releaseTopNode(SUnit *SU) override;

void releaseBottomNode(SUnit *SU) override;

unsigned reportPackets() {
  return Top.ResourceModel->getTotalPackets() +
         Bot.ResourceModel->getTotalPackets();
}

252protected:
SUnit *pickNodeBidrectional(bool &IsTopNode);

int pressureChange(const SUnit *SU, bool isBotUp);

int SchedulingCost(ReadyQueue &Q,
                   SUnit *SU, SchedCandidate &Candidate,
                   RegPressureDelta &Delta, bool verbose);

CandResult pickNodeFromQueue(VLIWSchedBoundary &Zone,
                             const RegPressureTracker &RPTracker,
                             SchedCandidate &Candidate);
264#ifndef NDEBUG1
void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU,
                    int Cost, PressureChange P = PressureChange());

void readyQueueVerboseDump(const RegPressureTracker &RPTracker,
                           SchedCandidate &Candidate, ReadyQueue &Q);
270#endif
271};

273} // end namespace llvm

275#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H