/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp

Bug Summary

File:	llvm/lib/CodeGen/IfConversion.cpp
Warning:	line 797, column 7 The expression is an uninitialized value. The computed value will also be garbage

Annotated Source Code

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/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp

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1//===- IfConversion.cpp - Machine code if conversion pass -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the machine instruction level if-conversion pass, which
10// tries to convert conditional branches into predicated instructions.
11//
12//===----------------------------------------------------------------------===//

14#include "BranchFolding.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/ADT/ScopeExit.h"
17#include "llvm/ADT/SmallSet.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/ADT/SparseSet.h"
20#include "llvm/ADT/Statistic.h"
21#include "llvm/ADT/iterator_range.h"
22#include "llvm/Analysis/ProfileSummaryInfo.h"
23#include "llvm/CodeGen/LivePhysRegs.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
26#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineInstr.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineModuleInfo.h"
32#include "llvm/CodeGen/MachineOperand.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34#include "llvm/CodeGen/MBFIWrapper.h"
35#include "llvm/CodeGen/TargetInstrInfo.h"
36#include "llvm/CodeGen/TargetLowering.h"
37#include "llvm/CodeGen/TargetRegisterInfo.h"
38#include "llvm/CodeGen/TargetSchedule.h"
39#include "llvm/CodeGen/TargetSubtargetInfo.h"
40#include "llvm/IR/Attributes.h"
41#include "llvm/IR/DebugLoc.h"
42#include "llvm/InitializePasses.h"
43#include "llvm/MC/MCRegisterInfo.h"
44#include "llvm/Pass.h"
45#include "llvm/Support/BranchProbability.h"
46#include "llvm/Support/CommandLine.h"
47#include "llvm/Support/Debug.h"
48#include "llvm/Support/ErrorHandling.h"
49#include "llvm/Support/raw_ostream.h"
50#include <algorithm>
51#include <cassert>
52#include <functional>
53#include <iterator>
54#include <memory>
55#include <utility>
56#include <vector>

58using namespace llvm;

60#define DEBUG_TYPE"if-converter" "if-converter"

62// Hidden options for help debugging.
63static cl::opt<int> IfCvtFnStart("ifcvt-fn-start", cl::init(-1), cl::Hidden);
64static cl::opt<int> IfCvtFnStop("ifcvt-fn-stop", cl::init(-1), cl::Hidden);
65static cl::opt<int> IfCvtLimit("ifcvt-limit", cl::init(-1), cl::Hidden);
66static cl::opt<bool> DisableSimple("disable-ifcvt-simple",
                                 cl::init(false), cl::Hidden);
68static cl::opt<bool> DisableSimpleF("disable-ifcvt-simple-false",
                                  cl::init(false), cl::Hidden);
70static cl::opt<bool> DisableTriangle("disable-ifcvt-triangle",
                                   cl::init(false), cl::Hidden);
72static cl::opt<bool> DisableTriangleR("disable-ifcvt-triangle-rev",
                                    cl::init(false), cl::Hidden);
74static cl::opt<bool> DisableTriangleF("disable-ifcvt-triangle-false",
                                    cl::init(false), cl::Hidden);
76static cl::opt<bool> DisableTriangleFR("disable-ifcvt-triangle-false-rev",
                                     cl::init(false), cl::Hidden);
78static cl::opt<bool> DisableDiamond("disable-ifcvt-diamond",
                                  cl::init(false), cl::Hidden);
80static cl::opt<bool> DisableForkedDiamond("disable-ifcvt-forked-diamond",
                                      cl::init(false), cl::Hidden);
82static cl::opt<bool> IfCvtBranchFold("ifcvt-branch-fold",
                                   cl::init(true), cl::Hidden);

85STATISTIC(NumSimple,       "Number of simple if-conversions performed")static llvm::Statistic NumSimple = {"if-converter", "NumSimple"
, "Number of simple if-conversions performed"};
86STATISTIC(NumSimpleFalse,  "Number of simple (F) if-conversions performed")static llvm::Statistic NumSimpleFalse = {"if-converter", "NumSimpleFalse"
, "Number of simple (F) if-conversions performed"};
87STATISTIC(NumTriangle,     "Number of triangle if-conversions performed")static llvm::Statistic NumTriangle = {"if-converter", "NumTriangle"
, "Number of triangle if-conversions performed"};
88STATISTIC(NumTriangleRev,  "Number of triangle (R) if-conversions performed")static llvm::Statistic NumTriangleRev = {"if-converter", "NumTriangleRev"
, "Number of triangle (R) if-conversions performed"};
89STATISTIC(NumTriangleFalse,"Number of triangle (F) if-conversions performed")static llvm::Statistic NumTriangleFalse = {"if-converter", "NumTriangleFalse"
, "Number of triangle (F) if-conversions performed"};
90STATISTIC(NumTriangleFRev, "Number of triangle (F/R) if-conversions performed")static llvm::Statistic NumTriangleFRev = {"if-converter", "NumTriangleFRev"
, "Number of triangle (F/R) if-conversions performed"};
91STATISTIC(NumDiamonds,     "Number of diamond if-conversions performed")static llvm::Statistic NumDiamonds = {"if-converter", "NumDiamonds"
, "Number of diamond if-conversions performed"};
92STATISTIC(NumForkedDiamonds, "Number of forked-diamond if-conversions performed")static llvm::Statistic NumForkedDiamonds = {"if-converter", "NumForkedDiamonds"
, "Number of forked-diamond if-conversions performed"};
93STATISTIC(NumIfConvBBs,    "Number of if-converted blocks")static llvm::Statistic NumIfConvBBs = {"if-converter", "NumIfConvBBs"
, "Number of if-converted blocks"};
94STATISTIC(NumDupBBs,       "Number of duplicated blocks")static llvm::Statistic NumDupBBs = {"if-converter", "NumDupBBs"
, "Number of duplicated blocks"};
95STATISTIC(NumUnpred,       "Number of true blocks of diamonds unpredicated")static llvm::Statistic NumUnpred = {"if-converter", "NumUnpred"
, "Number of true blocks of diamonds unpredicated"};

97namespace {

class IfConverter : public MachineFunctionPass {
  enum IfcvtKind {
    ICNotClassfied,  // BB data valid, but not classified.
    ICSimpleFalse,   // Same as ICSimple, but on the false path.
    ICSimple,        // BB is entry of an one split, no rejoin sub-CFG.
    ICTriangleFRev,  // Same as ICTriangleFalse, but false path rev condition.
    ICTriangleRev,   // Same as ICTriangle, but true path rev condition.
    ICTriangleFalse, // Same as ICTriangle, but on the false path.
    ICTriangle,      // BB is entry of a triangle sub-CFG.
    ICDiamond,       // BB is entry of a diamond sub-CFG.
    ICForkedDiamond  // BB is entry of an almost diamond sub-CFG, with a
                     // common tail that can be shared.
  };

  /// One per MachineBasicBlock, this is used to cache the result
  /// if-conversion feasibility analysis. This includes results from
  /// TargetInstrInfo::analyzeBranch() (i.e. TBB, FBB, and Cond), and its
  /// classification, and common tail block of its successors (if it's a
  /// diamond shape), its size, whether it's predicable, and whether any
  /// instruction can clobber the 'would-be' predicate.
  ///
  /// IsDone          - True if BB is not to be considered for ifcvt.
  /// IsBeingAnalyzed - True if BB is currently being analyzed.
  /// IsAnalyzed      - True if BB has been analyzed (info is still valid).
  /// IsEnqueued      - True if BB has been enqueued to be ifcvt'ed.
  /// IsBrAnalyzable  - True if analyzeBranch() returns false.
  /// HasFallThrough  - True if BB may fallthrough to the following BB.
  /// IsUnpredicable  - True if BB is known to be unpredicable.
  /// ClobbersPred    - True if BB could modify predicates (e.g. has
  ///                   cmp, call, etc.)
  /// NonPredSize     - Number of non-predicated instructions.
  /// ExtraCost       - Extra cost for multi-cycle instructions.
  /// ExtraCost2      - Some instructions are slower when predicated
  /// BB              - Corresponding MachineBasicBlock.
  /// TrueBB / FalseBB- See analyzeBranch().
  /// BrCond          - Conditions for end of block conditional branches.
  /// Predicate       - Predicate used in the BB.
  struct BBInfo {
    bool IsDone          : 1;
    bool IsBeingAnalyzed : 1;
    bool IsAnalyzed      : 1;
    bool IsEnqueued      : 1;
    bool IsBrAnalyzable  : 1;
    bool IsBrReversible  : 1;
    bool HasFallThrough  : 1;
    bool IsUnpredicable  : 1;
    bool CannotBeCopied  : 1;
    bool ClobbersPred    : 1;
    unsigned NonPredSize = 0;
    unsigned ExtraCost = 0;
    unsigned ExtraCost2 = 0;
    MachineBasicBlock *BB = nullptr;
    MachineBasicBlock *TrueBB = nullptr;
    MachineBasicBlock *FalseBB = nullptr;
    SmallVector<MachineOperand, 4> BrCond;
    SmallVector<MachineOperand, 4> Predicate;

    BBInfo() : IsDone(false), IsBeingAnalyzed(false),
               IsAnalyzed(false), IsEnqueued(false), IsBrAnalyzable(false),
               IsBrReversible(false), HasFallThrough(false),
               IsUnpredicable(false), CannotBeCopied(false),
               ClobbersPred(false) {}
  };

  /// Record information about pending if-conversions to attempt:
  /// BBI             - Corresponding BBInfo.
  /// Kind            - Type of block. See IfcvtKind.
  /// NeedSubsumption - True if the to-be-predicated BB has already been
  ///                   predicated.
  /// NumDups      - Number of instructions that would be duplicated due
  ///                   to this if-conversion. (For diamonds, the number of
  ///                   identical instructions at the beginnings of both
  ///                   paths).
  /// NumDups2     - For diamonds, the number of identical instructions
  ///                   at the ends of both paths.
  struct IfcvtToken {
    BBInfo &BBI;
    IfcvtKind Kind;
    unsigned NumDups;
    unsigned NumDups2;
    bool NeedSubsumption : 1;
    bool TClobbersPred : 1;
    bool FClobbersPred : 1;

    IfcvtToken(BBInfo &b, IfcvtKind k, bool s, unsigned d, unsigned d2 = 0,
               bool tc = false, bool fc = false)
      : BBI(b), Kind(k), NumDups(d), NumDups2(d2), NeedSubsumption(s),
        TClobbersPred(tc), FClobbersPred(fc) {}
  };

  /// Results of if-conversion feasibility analysis indexed by basic block
  /// number.
  std::vector<BBInfo> BBAnalysis;
  TargetSchedModel SchedModel;

  const TargetLoweringBase *TLI;
  const TargetInstrInfo *TII;
  const TargetRegisterInfo *TRI;
  const MachineBranchProbabilityInfo *MBPI;
  MachineRegisterInfo *MRI;

  LivePhysRegs Redefs;

  bool PreRegAlloc;
  bool MadeChange;
  int FnNum = -1;
  std::function<bool(const MachineFunction &)> PredicateFtor;

public:
  static char ID;

  IfConverter(std::function<bool(const MachineFunction &)> Ftor = nullptr)
      : MachineFunctionPass(ID), PredicateFtor(std::move(Ftor)) {
    initializeIfConverterPass(*PassRegistry::getPassRegistry());
  }

  void getAnalysisUsage(AnalysisUsage &AU) const override {
    AU.addRequired<MachineBlockFrequencyInfo>();
    AU.addRequired<MachineBranchProbabilityInfo>();
    AU.addRequired<ProfileSummaryInfoWrapperPass>();
    MachineFunctionPass::getAnalysisUsage(AU);
  }

  bool runOnMachineFunction(MachineFunction &MF) override;

  MachineFunctionProperties getRequiredProperties() const override {
    return MachineFunctionProperties().set(
        MachineFunctionProperties::Property::NoVRegs);
  }

private:
  bool reverseBranchCondition(BBInfo &BBI) const;
  bool ValidSimple(BBInfo &TrueBBI, unsigned &Dups,
                   BranchProbability Prediction) const;
  bool ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI,
                     bool FalseBranch, unsigned &Dups,
                     BranchProbability Prediction) const;
  bool CountDuplicatedInstructions(
      MachineBasicBlock::iterator &TIB, MachineBasicBlock::iterator &FIB,
      MachineBasicBlock::iterator &TIE, MachineBasicBlock::iterator &FIE,
      unsigned &Dups1, unsigned &Dups2,
      MachineBasicBlock &TBB, MachineBasicBlock &FBB,
      bool SkipUnconditionalBranches) const;
  bool ValidDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,
                    unsigned &Dups1, unsigned &Dups2,
                    BBInfo &TrueBBICalc, BBInfo &FalseBBICalc) const;
  bool ValidForkedDiamond(BBInfo &TrueBBI, BBInfo &FalseBBI,
                          unsigned &Dups1, unsigned &Dups2,
                          BBInfo &TrueBBICalc, BBInfo &FalseBBICalc) const;
  void AnalyzeBranches(BBInfo &BBI);
  void ScanInstructions(BBInfo &BBI,
                        MachineBasicBlock::iterator &Begin,
                        MachineBasicBlock::iterator &End,
                        bool BranchUnpredicable = false) const;
  bool RescanInstructions(
      MachineBasicBlock::iterator &TIB, MachineBasicBlock::iterator &FIB,
      MachineBasicBlock::iterator &TIE, MachineBasicBlock::iterator &FIE,
      BBInfo &TrueBBI, BBInfo &FalseBBI) const;
  void AnalyzeBlock(MachineBasicBlock &MBB,
                    std::vector<std::unique_ptr<IfcvtToken>> &Tokens);
  bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl<MachineOperand> &Pred,
                           bool isTriangle = false, bool RevBranch = false,
                           bool hasCommonTail = false);
  void AnalyzeBlocks(MachineFunction &MF,
                     std::vector<std::unique_ptr<IfcvtToken>> &Tokens);
  void InvalidatePreds(MachineBasicBlock &MBB);
  bool IfConvertSimple(BBInfo &BBI, IfcvtKind Kind);
  bool IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind);
  bool IfConvertDiamondCommon(BBInfo &BBI, BBInfo &TrueBBI, BBInfo &FalseBBI,
                              unsigned NumDups1, unsigned NumDups2,
                              bool TClobbersPred, bool FClobbersPred,
                              bool RemoveBranch, bool MergeAddEdges);
  bool IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
                        unsigned NumDups1, unsigned NumDups2,
                        bool TClobbers, bool FClobbers);
  bool IfConvertForkedDiamond(BBInfo &BBI, IfcvtKind Kind,
                            unsigned NumDups1, unsigned NumDups2,
                            bool TClobbers, bool FClobbers);
  void PredicateBlock(BBInfo &BBI,
                      MachineBasicBlock::iterator E,
                      SmallVectorImpl<MachineOperand> &Cond,
                      SmallSet<MCPhysReg, 4> *LaterRedefs = nullptr);
  void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
                             SmallVectorImpl<MachineOperand> &Cond,
                             bool IgnoreBr = false);
  void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges = true);

  bool MeetIfcvtSizeLimit(MachineBasicBlock &BB,
                          unsigned Cycle, unsigned Extra,
                          BranchProbability Prediction) const {
    return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra,
                                                 Prediction);
  }

  bool MeetIfcvtSizeLimit(BBInfo &TBBInfo, BBInfo &FBBInfo,
                          MachineBasicBlock &CommBB, unsigned Dups,
                          BranchProbability Prediction, bool Forked) const {
    const MachineFunction &MF = *TBBInfo.BB->getParent();
    if (MF.getFunction().hasMinSize()) {
1
Assuming the condition is true→
2
←
Taking true branch→
      MachineBasicBlock::iterator TIB = TBBInfo.BB->begin();
      MachineBasicBlock::iterator FIB = FBBInfo.BB->begin();
      MachineBasicBlock::iterator TIE = TBBInfo.BB->end();
      MachineBasicBlock::iterator FIE = FBBInfo.BB->end();

      unsigned Dups1, Dups2;
3
←
'Dups2' declared without an initial value→
      if (!CountDuplicatedInstructions(TIB, FIB, TIE, FIE, Dups1, Dups2,
4
←
Passing value via 6th parameter 'Dups2'→
5
←
Calling 'IfConverter::CountDuplicatedInstructions'→
                                       *TBBInfo.BB, *FBBInfo.BB,
                                       /*SkipUnconditionalBranches*/ true))
        llvm_unreachable("should already have been checked by ValidDiamond")::llvm::llvm_unreachable_internal("should already have been checked by ValidDiamond"
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 307);

      unsigned BranchBytes = 0;
      unsigned CommonBytes = 0;

      // Count common instructions at the start of the true and false blocks.
      for (auto &I : make_range(TBBInfo.BB->begin(), TIB)) {
        LLVM_DEBUG(dbgs() << "Common inst: " << I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Common inst: " << I
; } } while (false);
        CommonBytes += TII->getInstSizeInBytes(I);
      }
      for (auto &I : make_range(FBBInfo.BB->begin(), FIB)) {
        LLVM_DEBUG(dbgs() << "Common inst: " << I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Common inst: " << I
; } } while (false);
        CommonBytes += TII->getInstSizeInBytes(I);
      }

      // Count instructions at the end of the true and false blocks, after
      // the ones we plan to predicate. Analyzable branches will be removed
      // (unless this is a forked diamond), and all other instructions are
      // common between the two blocks.
      for (auto &I : make_range(TIE, TBBInfo.BB->end())) {
        if (I.isBranch() && TBBInfo.IsBrAnalyzable && !Forked) {
          LLVM_DEBUG(dbgs() << "Saving branch: " << I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Saving branch: " <<
 I; } } while (false);
          BranchBytes += TII->predictBranchSizeForIfCvt(I);
        } else {
          LLVM_DEBUG(dbgs() << "Common inst: " << I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Common inst: " << I
; } } while (false);
          CommonBytes += TII->getInstSizeInBytes(I);
        }
      }
      for (auto &I : make_range(FIE, FBBInfo.BB->end())) {
        if (I.isBranch() && FBBInfo.IsBrAnalyzable && !Forked) {
          LLVM_DEBUG(dbgs() << "Saving branch: " << I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Saving branch: " <<
 I; } } while (false);
          BranchBytes += TII->predictBranchSizeForIfCvt(I);
        } else {
          LLVM_DEBUG(dbgs() << "Common inst: " << I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Common inst: " << I
; } } while (false);
          CommonBytes += TII->getInstSizeInBytes(I);
        }
      }
      for (auto &I : CommBB.terminators()) {
        if (I.isBranch()) {
          LLVM_DEBUG(dbgs() << "Saving branch: " << I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Saving branch: " <<
 I; } } while (false);
          BranchBytes += TII->predictBranchSizeForIfCvt(I);
        }
      }

      // The common instructions in one branch will be eliminated, halving
      // their code size.
      CommonBytes /= 2;

      // Count the instructions which we need to predicate.
      unsigned NumPredicatedInstructions = 0;
      for (auto &I : make_range(TIB, TIE)) {
        if (!I.isDebugInstr()) {
          LLVM_DEBUG(dbgs() << "Predicating: " << I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Predicating: " << I
; } } while (false);
          NumPredicatedInstructions++;
        }
      }
      for (auto &I : make_range(FIB, FIE)) {
        if (!I.isDebugInstr()) {
          LLVM_DEBUG(dbgs() << "Predicating: " << I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Predicating: " << I
; } } while (false);
          NumPredicatedInstructions++;
        }
      }

      // Even though we're optimising for size at the expense of performance,
      // avoid creating really long predicated blocks.
      if (NumPredicatedInstructions > 15)
        return false;

      // Some targets (e.g. Thumb2) need to insert extra instructions to
      // start predicated blocks.
      unsigned ExtraPredicateBytes = TII->extraSizeToPredicateInstructions(
          MF, NumPredicatedInstructions);

      LLVM_DEBUG(dbgs() << "MeetIfcvtSizeLimit(BranchBytes=" << BranchBytesdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "MeetIfcvtSizeLimit(BranchBytes="
 << BranchBytes << ", CommonBytes=" << CommonBytes
 << ", NumPredicatedInstructions=" << NumPredicatedInstructions
 << ", ExtraPredicateBytes=" << ExtraPredicateBytes
 << ")\n"; } } while (false)
                        << ", CommonBytes=" << CommonBytesdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "MeetIfcvtSizeLimit(BranchBytes="
 << BranchBytes << ", CommonBytes=" << CommonBytes
 << ", NumPredicatedInstructions=" << NumPredicatedInstructions
 << ", ExtraPredicateBytes=" << ExtraPredicateBytes
 << ")\n"; } } while (false)
                        << ", NumPredicatedInstructions="do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "MeetIfcvtSizeLimit(BranchBytes="
 << BranchBytes << ", CommonBytes=" << CommonBytes
 << ", NumPredicatedInstructions=" << NumPredicatedInstructions
 << ", ExtraPredicateBytes=" << ExtraPredicateBytes
 << ")\n"; } } while (false)
                        << NumPredicatedInstructionsdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "MeetIfcvtSizeLimit(BranchBytes="
 << BranchBytes << ", CommonBytes=" << CommonBytes
 << ", NumPredicatedInstructions=" << NumPredicatedInstructions
 << ", ExtraPredicateBytes=" << ExtraPredicateBytes
 << ")\n"; } } while (false)
                        << ", ExtraPredicateBytes=" << ExtraPredicateBytesdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "MeetIfcvtSizeLimit(BranchBytes="
 << BranchBytes << ", CommonBytes=" << CommonBytes
 << ", NumPredicatedInstructions=" << NumPredicatedInstructions
 << ", ExtraPredicateBytes=" << ExtraPredicateBytes
 << ")\n"; } } while (false)
                        << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "MeetIfcvtSizeLimit(BranchBytes="
 << BranchBytes << ", CommonBytes=" << CommonBytes
 << ", NumPredicatedInstructions=" << NumPredicatedInstructions
 << ", ExtraPredicateBytes=" << ExtraPredicateBytes
 << ")\n"; } } while (false);
      return (BranchBytes + CommonBytes) > ExtraPredicateBytes;
    } else {
      unsigned TCycle = TBBInfo.NonPredSize + TBBInfo.ExtraCost - Dups;
      unsigned FCycle = FBBInfo.NonPredSize + FBBInfo.ExtraCost - Dups;
      bool Res = TCycle > 0 && FCycle > 0 &&
                 TII->isProfitableToIfCvt(
                     *TBBInfo.BB, TCycle, TBBInfo.ExtraCost2, *FBBInfo.BB,
                     FCycle, FBBInfo.ExtraCost2, Prediction);
      LLVM_DEBUG(dbgs() << "MeetIfcvtSizeLimit(TCycle=" << TCycledo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "MeetIfcvtSizeLimit(TCycle="
 << TCycle << ", FCycle=" << FCycle <<
 ", TExtra=" << TBBInfo.ExtraCost2 << ", FExtra="
 << FBBInfo.ExtraCost2 << ") = " << Res <<
 "\n"; } } while (false)
                        << ", FCycle=" << FCycledo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "MeetIfcvtSizeLimit(TCycle="
 << TCycle << ", FCycle=" << FCycle <<
 ", TExtra=" << TBBInfo.ExtraCost2 << ", FExtra="
 << FBBInfo.ExtraCost2 << ") = " << Res <<
 "\n"; } } while (false)
                        << ", TExtra=" << TBBInfo.ExtraCost2 << ", FExtra="do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "MeetIfcvtSizeLimit(TCycle="
 << TCycle << ", FCycle=" << FCycle <<
 ", TExtra=" << TBBInfo.ExtraCost2 << ", FExtra="
 << FBBInfo.ExtraCost2 << ") = " << Res <<
 "\n"; } } while (false)
                        << FBBInfo.ExtraCost2 << ") = " << Res << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "MeetIfcvtSizeLimit(TCycle="
 << TCycle << ", FCycle=" << FCycle <<
 ", TExtra=" << TBBInfo.ExtraCost2 << ", FExtra="
 << FBBInfo.ExtraCost2 << ") = " << Res <<
 "\n"; } } while (false);
      return Res;
    }
  }

  /// Returns true if Block ends without a terminator.
  bool blockAlwaysFallThrough(BBInfo &BBI) const {
    return BBI.IsBrAnalyzable && BBI.TrueBB == nullptr;
  }

  /// Used to sort if-conversion candidates.
  static bool IfcvtTokenCmp(const std::unique_ptr<IfcvtToken> &C1,
                            const std::unique_ptr<IfcvtToken> &C2) {
    int Incr1 = (C1->Kind == ICDiamond)
      ? -(int)(C1->NumDups + C1->NumDups2) : (int)C1->NumDups;
    int Incr2 = (C2->Kind == ICDiamond)
      ? -(int)(C2->NumDups + C2->NumDups2) : (int)C2->NumDups;
    if (Incr1 > Incr2)
      return true;
    else if (Incr1 == Incr2) {
      // Favors subsumption.
      if (!C1->NeedSubsumption && C2->NeedSubsumption)
        return true;
      else if (C1->NeedSubsumption == C2->NeedSubsumption) {
        // Favors diamond over triangle, etc.
        if ((unsigned)C1->Kind < (unsigned)C2->Kind)
          return true;
        else if (C1->Kind == C2->Kind)
          return C1->BBI.BB->getNumber() < C2->BBI.BB->getNumber();
      }
    }
    return false;
  }
};

432} // end anonymous namespace

434char IfConverter::ID = 0;

436char &llvm::IfConverterID = IfConverter::ID;

438INITIALIZE_PASS_BEGIN(IfConverter, DEBUG_TYPE, "If Converter", false, false)static void *initializeIfConverterPassOnce(PassRegistry &
Registry) {
439INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)initializeMachineBranchProbabilityInfoPass(Registry);
440INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)initializeProfileSummaryInfoWrapperPassPass(Registry);
441INITIALIZE_PASS_END(IfConverter, DEBUG_TYPE, "If Converter", false, false)PassInfo *PI = new PassInfo( "If Converter", "if-converter", &
IfConverter::ID, PassInfo::NormalCtor_t(callDefaultCtor<IfConverter
>), false, false); Registry.registerPass(*PI, true); return
 PI; } static llvm::once_flag InitializeIfConverterPassFlag; void
 llvm::initializeIfConverterPass(PassRegistry &Registry) {
 llvm::call_once(InitializeIfConverterPassFlag, initializeIfConverterPassOnce
, std::ref(Registry)); }

443bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()) || (PredicateFtor && !PredicateFtor(MF)))
  return false;

const TargetSubtargetInfo &ST = MF.getSubtarget();
TLI = ST.getTargetLowering();
TII = ST.getInstrInfo();
TRI = ST.getRegisterInfo();
MBFIWrapper MBFI(getAnalysis<MachineBlockFrequencyInfo>());
MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
ProfileSummaryInfo *PSI =
    &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
MRI = &MF.getRegInfo();
SchedModel.init(&ST);

if (!TII) return false;

PreRegAlloc = MRI->isSSA();

bool BFChange = false;
if (!PreRegAlloc) {
  // Tail merge tend to expose more if-conversion opportunities.
  BranchFolder BF(true, false, MBFI, *MBPI, PSI);
  BFChange = BF.OptimizeFunction(MF, TII, ST.getRegisterInfo());
}

LLVM_DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "\nIfcvt: function (" <<
 ++FnNum << ") \'" << MF.getName() << "\'";
 } } while (false)
                  << MF.getName() << "\'")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "\nIfcvt: function (" <<
 ++FnNum << ") \'" << MF.getName() << "\'";
 } } while (false);

if (FnNum < IfCvtFnStart || (IfCvtFnStop != -1 && FnNum > IfCvtFnStop)) {
  LLVM_DEBUG(dbgs() << " skipped\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << " skipped\n"; } } while (
false);
  return false;
}
LLVM_DEBUG(dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "\n"; } } while (false);

MF.RenumberBlocks();
BBAnalysis.resize(MF.getNumBlockIDs());

std::vector<std::unique_ptr<IfcvtToken>> Tokens;
MadeChange = false;
unsigned NumIfCvts = NumSimple + NumSimpleFalse + NumTriangle +
  NumTriangleRev + NumTriangleFalse + NumTriangleFRev + NumDiamonds;
while (IfCvtLimit == -1 || (int)NumIfCvts < IfCvtLimit) {
  // Do an initial analysis for each basic block and find all the potential
  // candidates to perform if-conversion.
  bool Change = false;
  AnalyzeBlocks(MF, Tokens);
  while (!Tokens.empty()) {
    std::unique_ptr<IfcvtToken> Token = std::move(Tokens.back());
    Tokens.pop_back();
    BBInfo &BBI = Token->BBI;
    IfcvtKind Kind = Token->Kind;
    unsigned NumDups = Token->NumDups;
    unsigned NumDups2 = Token->NumDups2;

    // If the block has been evicted out of the queue or it has already been
    // marked dead (due to it being predicated), then skip it.
    if (BBI.IsDone)
      BBI.IsEnqueued = false;
    if (!BBI.IsEnqueued)
      continue;

    BBI.IsEnqueued = false;

    bool RetVal = false;
    switch (Kind) {
    default: llvm_unreachable("Unexpected!")::llvm::llvm_unreachable_internal("Unexpected!", "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 509);
    case ICSimple:
    case ICSimpleFalse: {
      bool isFalse = Kind == ICSimpleFalse;
      if ((isFalse && DisableSimpleF) || (!isFalse && DisableSimple)) break;
      LLVM_DEBUG(dbgs() << "Ifcvt (Simple"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Simple" << (
Kind == ICSimpleFalse ? " false" : "") << "): " <<
 printMBBReference(*BBI.BB) << " (" << ((Kind == ICSimpleFalse
) ? BBI.FalseBB->getNumber() : BBI.TrueBB->getNumber())
 << ") "; } } while (false)
                        << (Kind == ICSimpleFalse ? " false" : "")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Simple" << (
Kind == ICSimpleFalse ? " false" : "") << "): " <<
 printMBBReference(*BBI.BB) << " (" << ((Kind == ICSimpleFalse
) ? BBI.FalseBB->getNumber() : BBI.TrueBB->getNumber())
 << ") "; } } while (false)
                        << "): " << printMBBReference(*BBI.BB) << " ("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Simple" << (
Kind == ICSimpleFalse ? " false" : "") << "): " <<
 printMBBReference(*BBI.BB) << " (" << ((Kind == ICSimpleFalse
) ? BBI.FalseBB->getNumber() : BBI.TrueBB->getNumber())
 << ") "; } } while (false)
                        << ((Kind == ICSimpleFalse) ? BBI.FalseBB->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Simple" << (
Kind == ICSimpleFalse ? " false" : "") << "): " <<
 printMBBReference(*BBI.BB) << " (" << ((Kind == ICSimpleFalse
) ? BBI.FalseBB->getNumber() : BBI.TrueBB->getNumber())
 << ") "; } } while (false)
                                                    : BBI.TrueBB->getNumber())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Simple" << (
Kind == ICSimpleFalse ? " false" : "") << "): " <<
 printMBBReference(*BBI.BB) << " (" << ((Kind == ICSimpleFalse
) ? BBI.FalseBB->getNumber() : BBI.TrueBB->getNumber())
 << ") "; } } while (false)
                        << ") ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Simple" << (
Kind == ICSimpleFalse ? " false" : "") << "): " <<
 printMBBReference(*BBI.BB) << " (" << ((Kind == ICSimpleFalse
) ? BBI.FalseBB->getNumber() : BBI.TrueBB->getNumber())
 << ") "; } } while (false);
      RetVal = IfConvertSimple(BBI, Kind);
      LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << (RetVal ? "succeeded!" : "failed!"
) << "\n"; } } while (false);
      if (RetVal) {
        if (isFalse) ++NumSimpleFalse;
        else         ++NumSimple;
      }
     break;
    }
    case ICTriangle:
    case ICTriangleRev:
    case ICTriangleFalse:
    case ICTriangleFRev: {
      bool isFalse = Kind == ICTriangleFalse;
      bool isRev   = (Kind == ICTriangleRev || Kind == ICTriangleFRev);
      if (DisableTriangle && !isFalse && !isRev) break;
      if (DisableTriangleR && !isFalse && isRev) break;
      if (DisableTriangleF && isFalse && !isRev) break;
      if (DisableTriangleFR && isFalse && isRev) break;
      LLVM_DEBUG(dbgs() << "Ifcvt (Triangle")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Triangle"; } } while
 (false);
      if (isFalse)
        LLVM_DEBUG(dbgs() << " false")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << " false"; } } while (false
);
      if (isRev)
        LLVM_DEBUG(dbgs() << " rev")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << " rev"; } } while (false);
      LLVM_DEBUG(dbgs() << "): " << printMBBReference(*BBI.BB)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "): " << printMBBReference
(*BBI.BB) << " (T:" << BBI.TrueBB->getNumber()
 << ",F:" << BBI.FalseBB->getNumber() <<
 ") "; } } while (false)
                        << " (T:" << BBI.TrueBB->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "): " << printMBBReference
(*BBI.BB) << " (T:" << BBI.TrueBB->getNumber()
 << ",F:" << BBI.FalseBB->getNumber() <<
 ") "; } } while (false)
                        << ",F:" << BBI.FalseBB->getNumber() << ") ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "): " << printMBBReference
(*BBI.BB) << " (T:" << BBI.TrueBB->getNumber()
 << ",F:" << BBI.FalseBB->getNumber() <<
 ") "; } } while (false);
      RetVal = IfConvertTriangle(BBI, Kind);
      LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << (RetVal ? "succeeded!" : "failed!"
) << "\n"; } } while (false);
      if (RetVal) {
        if (isFalse) {
          if (isRev) ++NumTriangleFRev;
          else       ++NumTriangleFalse;
        } else {
          if (isRev) ++NumTriangleRev;
          else       ++NumTriangle;
        }
      }
      break;
    }
    case ICDiamond:
      if (DisableDiamond) break;
      LLVM_DEBUG(dbgs() << "Ifcvt (Diamond): " << printMBBReference(*BBI.BB)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Diamond): " <<
 printMBBReference(*BBI.BB) << " (T:" << BBI.TrueBB
->getNumber() << ",F:" << BBI.FalseBB->getNumber
() << ") "; } } while (false)
                        << " (T:" << BBI.TrueBB->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Diamond): " <<
 printMBBReference(*BBI.BB) << " (T:" << BBI.TrueBB
->getNumber() << ",F:" << BBI.FalseBB->getNumber
() << ") "; } } while (false)
                        << ",F:" << BBI.FalseBB->getNumber() << ") ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Diamond): " <<
 printMBBReference(*BBI.BB) << " (T:" << BBI.TrueBB
->getNumber() << ",F:" << BBI.FalseBB->getNumber
() << ") "; } } while (false);
      RetVal = IfConvertDiamond(BBI, Kind, NumDups, NumDups2,
                                Token->TClobbersPred,
                                Token->FClobbersPred);
      LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << (RetVal ? "succeeded!" : "failed!"
) << "\n"; } } while (false);
      if (RetVal) ++NumDiamonds;
      break;
    case ICForkedDiamond:
      if (DisableForkedDiamond) break;
      LLVM_DEBUG(dbgs() << "Ifcvt (Forked Diamond): "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Forked Diamond): "
 << printMBBReference(*BBI.BB) << " (T:" <<
 BBI.TrueBB->getNumber() << ",F:" << BBI.FalseBB
->getNumber() << ") "; } } while (false)
                        << printMBBReference(*BBI.BB)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Forked Diamond): "
 << printMBBReference(*BBI.BB) << " (T:" <<
 BBI.TrueBB->getNumber() << ",F:" << BBI.FalseBB
->getNumber() << ") "; } } while (false)
                        << " (T:" << BBI.TrueBB->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Forked Diamond): "
 << printMBBReference(*BBI.BB) << " (T:" <<
 BBI.TrueBB->getNumber() << ",F:" << BBI.FalseBB
->getNumber() << ") "; } } while (false)
                        << ",F:" << BBI.FalseBB->getNumber() << ") ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << "Ifcvt (Forked Diamond): "
 << printMBBReference(*BBI.BB) << " (T:" <<
 BBI.TrueBB->getNumber() << ",F:" << BBI.FalseBB
->getNumber() << ") "; } } while (false);
      RetVal = IfConvertForkedDiamond(BBI, Kind, NumDups, NumDups2,
                                    Token->TClobbersPred,
                                    Token->FClobbersPred);
      LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("if-converter")) { dbgs() << (RetVal ? "succeeded!" : "failed!"
) << "\n"; } } while (false);
      if (RetVal) ++NumForkedDiamonds;
      break;
    }

    if (RetVal && MRI->tracksLiveness())
      recomputeLivenessFlags(*BBI.BB);

    Change |= RetVal;

    NumIfCvts = NumSimple + NumSimpleFalse + NumTriangle + NumTriangleRev +
      NumTriangleFalse + NumTriangleFRev + NumDiamonds;
    if (IfCvtLimit != -1 && (int)NumIfCvts >= IfCvtLimit)
      break;
  }

  if (!Change)
    break;
  MadeChange |= Change;
}

Tokens.clear();
BBAnalysis.clear();

if (MadeChange && IfCvtBranchFold) {
  BranchFolder BF(false, false, MBFI, *MBPI, PSI);
  BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo());
}

MadeChange |= BFChange;
return MadeChange;
610}

612/// BB has a fallthrough. Find its 'false' successor given its 'true' successor.
613static MachineBasicBlock *findFalseBlock(MachineBasicBlock *BB,
                                       MachineBasicBlock *TrueBB) {
for (MachineBasicBlock *SuccBB : BB->successors()) {
  if (SuccBB != TrueBB)
    return SuccBB;
}
return nullptr;
620}

622/// Reverse the condition of the end of the block branch. Swap block's 'true'
623/// and 'false' successors.
624bool IfConverter::reverseBranchCondition(BBInfo &BBI) const {
DebugLoc dl;  // FIXME: this is nowhere
if (!TII->reverseBranchCondition(BBI.BrCond)) {
  TII->removeBranch(*BBI.BB);
  TII->insertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
  std::swap(BBI.TrueBB, BBI.FalseBB);
  return true;
}
return false;
633}

635/// Returns the next block in the function blocks ordering. If it is the end,
636/// returns NULL.
637static inline MachineBasicBlock *getNextBlock(MachineBasicBlock &MBB) {
MachineFunction::iterator I = MBB.getIterator();
MachineFunction::iterator E = MBB.getParent()->end();
if (++I == E)
  return nullptr;
return &*I;
643}

645/// Returns true if the 'true' block (along with its predecessor) forms a valid
646/// simple shape for ifcvt. It also returns the number of instructions that the
647/// ifcvt would need to duplicate if performed in Dups.
648bool IfConverter::ValidSimple(BBInfo &TrueBBI, unsigned &Dups,
                            BranchProbability Prediction) const {
Dups = 0;
if (TrueBBI.IsBeingAnalyzed || TrueBBI.IsDone)
  return false;

if (TrueBBI.IsBrAnalyzable)
  return false;

if (TrueBBI.BB->pred_size() > 1) {
  if (TrueBBI.CannotBeCopied ||
      !TII->isProfitableToDupForIfCvt(*TrueBBI.BB, TrueBBI.NonPredSize,
                                      Prediction))
    return false;
  Dups = TrueBBI.NonPredSize;
}

return true;
666}

668/// Returns true if the 'true' and 'false' blocks (along with their common
669/// predecessor) forms a valid triangle shape for ifcvt. If 'FalseBranch' is
670/// true, it checks if 'true' block's false branch branches to the 'false' block
671/// rather than the other way around. It also returns the number of instructions
672/// that the ifcvt would need to duplicate if performed in 'Dups'.
673bool IfConverter::ValidTriangle(BBInfo &TrueBBI, BBInfo &FalseBBI,
                              bool FalseBranch, unsigned &Dups,
                              BranchProbability Prediction) const {
Dups = 0;
if (TrueBBI.BB == FalseBBI.BB)
  return false;

if (TrueBBI.IsBeingAnalyzed || TrueBBI.IsDone)
  return false;

if (TrueBBI.BB->pred_size() > 1) {
  if (TrueBBI.CannotBeCopied)
    return false;

  unsigned Size = TrueBBI.NonPredSize;
  if (TrueBBI.IsBrAnalyzable) {
    if (TrueBBI.TrueBB && TrueBBI.BrCond.empty())
      // Ends with an unconditional branch. It will be removed.
      --Size;
    else {
      MachineBasicBlock *FExit = FalseBranch
        ? TrueBBI.TrueBB : TrueBBI.FalseBB;
      if (FExit)
        // Require a conditional branch
        ++Size;
    }
  }
  if (!TII->isProfitableToDupForIfCvt(*TrueBBI.BB, Size, Prediction))
    return false;
  Dups = Size;
}

MachineBasicBlock *TExit = FalseBranch ? TrueBBI.FalseBB : TrueBBI.TrueBB;
if (!TExit && blockAlwaysFallThrough(TrueBBI)) {
  MachineFunction::iterator I = TrueBBI.BB->getIterator();
  if (++I == TrueBBI.BB->getParent()->end())
    return false;
  TExit = &*I;
}
return TExit && TExit == FalseBBI.BB;
713}

715/// Count duplicated instructions and move the iterators to show where they
716/// are.
717/// @param TIB True Iterator Begin
718/// @param FIB False Iterator Begin
719/// These two iterators initially point to the first instruction of the two
720/// blocks, and finally point to the first non-shared instruction.
721/// @param TIE True Iterator End
722/// @param FIE False Iterator End
723/// These two iterators initially point to End() for the two blocks() and
724/// finally point to the first shared instruction in the tail.
725/// Upon return [TIB, TIE), and [FIB, FIE) mark the un-duplicated portions of
726/// two blocks.
727/// @param Dups1 count of duplicated instructions at the beginning of the 2
728/// blocks.
729/// @param Dups2 count of duplicated instructions at the end of the 2 blocks.
730/// @param SkipUnconditionalBranches if true, Don't make sure that
731/// unconditional branches at the end of the blocks are the same. True is
732/// passed when the blocks are analyzable to allow for fallthrough to be
733/// handled.
734/// @return false if the shared portion prevents if conversion.
735bool IfConverter::CountDuplicatedInstructions(
  MachineBasicBlock::iterator &TIB,
  MachineBasicBlock::iterator &FIB,
  MachineBasicBlock::iterator &TIE,
  MachineBasicBlock::iterator &FIE,
  unsigned &Dups1, unsigned &Dups2,
  MachineBasicBlock &TBB, MachineBasicBlock &FBB,
  bool SkipUnconditionalBranches) const {
while (TIB != TIE && FIB != FIE) {
6
←
Calling 'operator!='→
15
←
Returning from 'operator!='→
16
←
Calling 'operator!='→
25
←
Returning from 'operator!='→
26
←
Loop condition is true.  Entering loop body→
  // Skip dbg_value instructions. These do not count.
  TIB = skipDebugInstructionsForward(TIB, TIE, false);
  FIB = skipDebugInstructionsForward(FIB, FIE, false);
  if (TIB == TIE || FIB == FIE)
27
←
Calling 'operator=='→
32
←
Returning from 'operator=='→
33
←
Calling 'operator=='→
38
←
Returning from 'operator=='→
39
←
Taking false branch→
    break;
  if (!TIB->isIdenticalTo(*FIB))
40
←
Assuming the condition is true→
41
←
Taking true branch→
    break;
42
←
 Execution continues on line 764→
  // A pred-clobbering instruction in the shared portion prevents
  // if-conversion.
  std::vector<MachineOperand> PredDefs;
  if (TII->ClobbersPredicate(*TIB, PredDefs, false))
    return false;
  // If we get all the way to the branch instructions, don't count them.
  if (!TIB->isBranch())
    ++Dups1;
  ++TIB;
  ++FIB;
}

// Check for already containing all of the block.
if (TIB == TIE || FIB == FIE)
43
←
Calling 'operator=='→
48
←
Returning from 'operator=='→
49
←
Calling 'operator=='→
54
←
Returning from 'operator=='→
55
←
Taking false branch→
  return true;
// Now, in preparation for counting duplicate instructions at the ends of the
// blocks, switch to reverse_iterators. Note that getReverse() returns an
// iterator that points to the same instruction, unlike std::reverse_iterator.
// We have to do our own shifting so that we get the same range.
MachineBasicBlock::reverse_iterator RTIE = std::next(TIE.getReverse());
MachineBasicBlock::reverse_iterator RFIE = std::next(FIE.getReverse());
const MachineBasicBlock::reverse_iterator RTIB = std::next(TIB.getReverse());
const MachineBasicBlock::reverse_iterator RFIB = std::next(FIB.getReverse());

if (!TBB.succ_empty() || !FBB.succ_empty()) {
56
←
Assuming the condition is false→
57
←
Assuming the condition is false→
58
←
Taking false branch→
  if (SkipUnconditionalBranches) {
    while (RTIE != RTIB && RTIE->isUnconditionalBranch())
      ++RTIE;
    while (RFIE != RFIB && RFIE->isUnconditionalBranch())
      ++RFIE;
  }
}

// Count duplicate instructions at the ends of the blocks.
while (RTIE != RTIB && RFIE != RFIB) {
59
←
Calling 'operator!='→
68
←
Returning from 'operator!='→
69
←
Calling 'operator!='→
78
←
Returning from 'operator!='→
79
←
Loop condition is true.  Entering loop body→
  // Skip dbg_value instructions. These do not count.
  // Note that these are reverse iterators going forward.
  RTIE = skipDebugInstructionsForward(RTIE, RTIB, false);
  RFIE = skipDebugInstructionsForward(RFIE, RFIB, false);
  if (RTIE == RTIB || RFIE == RFIB)
80
←
Calling 'operator=='→
86
←
Returning from 'operator=='→
87
←
Calling 'operator=='→
93
←
Returning from 'operator=='→
94
←
Taking false branch→
    break;
  if (!RTIE->isIdenticalTo(*RFIE))
95
←
Assuming the condition is false→
96
←
Taking false branch→
    break;
  // We have to verify that any branch instructions are the same, and then we
  // don't count them toward the # of duplicate instructions.
  if (!RTIE->isBranch())
97
←
Calling 'MachineInstr::isBranch'→
104
←
Returning from 'MachineInstr::isBranch'→
105
←
Assuming the condition is true→
106
←
Taking true branch→
    ++Dups2;
107
←
The expression is an uninitialized value. The computed value will also be garbage
  ++RTIE;
  ++RFIE;
}
TIE = std::next(RTIE.getReverse());
FIE = std::next(RFIE.getReverse());
return true;
804}

806/// RescanInstructions - Run ScanInstructions on a pair of blocks.
807/// @param TIB - True Iterator Begin, points to first non-shared instruction
808/// @param FIB - False Iterator Begin, points to first non-shared instruction
809/// @param TIE - True Iterator End, points past last non-shared instruction
810/// @param FIE - False Iterator End, points past last non-shared instruction
811/// @param TrueBBI  - BBInfo to update for the true block.
812/// @param FalseBBI - BBInfo to update for the false block.
813/// @returns - false if either block cannot be predicated or if both blocks end
814///   with a predicate-clobbering instruction.
815bool IfConverter::RescanInstructions(
  MachineBasicBlock::iterator &TIB, MachineBasicBlock::iterator &FIB,
  MachineBasicBlock::iterator &TIE, MachineBasicBlock::iterator &FIE,
  BBInfo &TrueBBI, BBInfo &FalseBBI) const {
bool BranchUnpredicable = true;
TrueBBI.IsUnpredicable = FalseBBI.IsUnpredicable = false;
ScanInstructions(TrueBBI, TIB, TIE, BranchUnpredicable);
if (TrueBBI.IsUnpredicable)
  return false;
ScanInstructions(FalseBBI, FIB, FIE, BranchUnpredicable);
if (FalseBBI.IsUnpredicable)
  return false;
if (TrueBBI.ClobbersPred && FalseBBI.ClobbersPred)
  return false;
return true;
830}

832#ifndef NDEBUG
833static void verifySameBranchInstructions(
  MachineBasicBlock *MBB1,
  MachineBasicBlock *MBB2) {
const MachineBasicBlock::reverse_iterator B1 = MBB1->rend();
const MachineBasicBlock::reverse_iterator B2 = MBB2->rend();
MachineBasicBlock::reverse_iterator E1 = MBB1->rbegin();
MachineBasicBlock::reverse_iterator E2 = MBB2->rbegin();
while (E1 != B1 && E2 != B2) {
  skipDebugInstructionsForward(E1, B1, false);
  skipDebugInstructionsForward(E2, B2, false);
  if (E1 == B1 && E2 == B2)
    break;

  if (E1 == B1) {
    assert(!E2->isBranch() && "Branch mis-match, one block is empty.")(static_cast <bool> (!E2->isBranch() && "Branch mis-match, one block is empty."
) ? void (0) : __assert_fail ("!E2->isBranch() && \"Branch mis-match, one block is empty.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 847, __extension__ __PRETTY_FUNCTION__));
    break;
  }
  if (E2 == B2) {
    assert(!E1->isBranch() && "Branch mis-match, one block is empty.")(static_cast <bool> (!E1->isBranch() && "Branch mis-match, one block is empty."
) ? void (0) : __assert_fail ("!E1->isBranch() && \"Branch mis-match, one block is empty.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 851, __extension__ __PRETTY_FUNCTION__));
    break;
  }

  if (E1->isBranch() || E2->isBranch())
    assert(E1->isIdenticalTo(*E2) &&(static_cast <bool> (E1->isIdenticalTo(*E2) &&
 "Branch mis-match, branch instructions don't match.") ? void
 (0) : __assert_fail ("E1->isIdenticalTo(*E2) && \"Branch mis-match, branch instructions don't match.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 857, __extension__ __PRETTY_FUNCTION__))
           "Branch mis-match, branch instructions don't match.")(static_cast <bool> (E1->isIdenticalTo(*E2) &&
 "Branch mis-match, branch instructions don't match.") ? void
 (0) : __assert_fail ("E1->isIdenticalTo(*E2) && \"Branch mis-match, branch instructions don't match.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 857, __extension__ __PRETTY_FUNCTION__));
  else
    break;
  ++E1;
  ++E2;
}
863}
864#endif

866/// ValidForkedDiamond - Returns true if the 'true' and 'false' blocks (along
867/// with their common predecessor) form a diamond if a common tail block is
868/// extracted.
869/// While not strictly a diamond, this pattern would form a diamond if
870/// tail-merging had merged the shared tails.
871///           EBB
872///         _/   \_
873///         |     |
874///        TBB   FBB
875///        /  \ /   \
876///  FalseBB TrueBB FalseBB
877/// Currently only handles analyzable branches.
878/// Specifically excludes actual diamonds to avoid overlap.
879bool IfConverter::ValidForkedDiamond(
  BBInfo &TrueBBI, BBInfo &FalseBBI,
  unsigned &Dups1, unsigned &Dups2,
  BBInfo &TrueBBICalc, BBInfo &FalseBBICalc) const {
Dups1 = Dups2 = 0;
if (TrueBBI.IsBeingAnalyzed || TrueBBI.IsDone ||
    FalseBBI.IsBeingAnalyzed || FalseBBI.IsDone)
  return false;

if (!TrueBBI.IsBrAnalyzable || !FalseBBI.IsBrAnalyzable)
  return false;
// Don't IfConvert blocks that can't be folded into their predecessor.
if  (TrueBBI.BB->pred_size() > 1 || FalseBBI.BB->pred_size() > 1)
  return false;

// This function is specifically looking for conditional tails, as
// unconditional tails are already handled by the standard diamond case.
if (TrueBBI.BrCond.size() == 0 ||
    FalseBBI.BrCond.size() == 0)
  return false;

MachineBasicBlock *TT = TrueBBI.TrueBB;
MachineBasicBlock *TF = TrueBBI.FalseBB;
MachineBasicBlock *FT = FalseBBI.TrueBB;
MachineBasicBlock *FF = FalseBBI.FalseBB;

if (!TT)
  TT = getNextBlock(*TrueBBI.BB);
if (!TF)
  TF = getNextBlock(*TrueBBI.BB);
if (!FT)
  FT = getNextBlock(*FalseBBI.BB);
if (!FF)
  FF = getNextBlock(*FalseBBI.BB);

if (!TT || !TF)
  return false;

// Check successors. If they don't match, bail.
if (!((TT == FT && TF == FF) || (TF == FT && TT == FF)))
  return false;

bool FalseReversed = false;
if (TF == FT && TT == FF) {
  // If the branches are opposing, but we can't reverse, don't do it.
  if (!FalseBBI.IsBrReversible)
    return false;
  FalseReversed = true;
  reverseBranchCondition(FalseBBI);
}
auto UnReverseOnExit = make_scope_exit([&]() {
  if (FalseReversed)
    reverseBranchCondition(FalseBBI);
});

// Count duplicate instructions at the beginning of the true and false blocks.
MachineBasicBlock::iterator TIB = TrueBBI.BB->begin();
MachineBasicBlock::iterator FIB = FalseBBI.BB->begin();
MachineBasicBlock::iterator TIE = TrueBBI.BB->end();
MachineBasicBlock::iterator FIE = FalseBBI.BB->end();
if(!CountDuplicatedInstructions(TIB, FIB, TIE, FIE, Dups1, Dups2,
                                *TrueBBI.BB, *FalseBBI.BB,
                                /* SkipUnconditionalBranches */ true))
  return false;

TrueBBICalc.BB = TrueBBI.BB;
FalseBBICalc.BB = FalseBBI.BB;
TrueBBICalc.IsBrAnalyzable = TrueBBI.IsBrAnalyzable;
FalseBBICalc.IsBrAnalyzable = FalseBBI.IsBrAnalyzable;
if (!RescanInstructions(TIB, FIB, TIE, FIE, TrueBBICalc, FalseBBICalc))
  return false;

// The size is used to decide whether to if-convert, and the shared portions
// are subtracted off. Because of the subtraction, we just use the size that
// was calculated by the original ScanInstructions, as it is correct.
TrueBBICalc.NonPredSize = TrueBBI.NonPredSize;
FalseBBICalc.NonPredSize = FalseBBI.NonPredSize;
return true;
957}

959/// ValidDiamond - Returns true if the 'true' and 'false' blocks (along
960/// with their common predecessor) forms a valid diamond shape for ifcvt.
961bool IfConverter::ValidDiamond(
  BBInfo &TrueBBI, BBInfo &FalseBBI,
  unsigned &Dups1, unsigned &Dups2,
  BBInfo &TrueBBICalc, BBInfo &FalseBBICalc) const {
Dups1 = Dups2 = 0;
if (TrueBBI.IsBeingAnalyzed || TrueBBI.IsDone ||
    FalseBBI.IsBeingAnalyzed || FalseBBI.IsDone)
  return false;

// If the True and False BBs are equal we're dealing with a degenerate case
// that we don't treat as a diamond.
if (TrueBBI.BB == FalseBBI.BB)
  return false;

MachineBasicBlock *TT = TrueBBI.TrueBB;
MachineBasicBlock *FT = FalseBBI.TrueBB;

if (!TT && blockAlwaysFallThrough(TrueBBI))
  TT = getNextBlock(*TrueBBI.BB);
if (!FT && blockAlwaysFallThrough(FalseBBI))
  FT = getNextBlock(*FalseBBI.BB);
if (TT != FT)
  return false;
if (!TT && (TrueBBI.IsBrAnalyzable || FalseBBI.IsBrAnalyzable))
  return false;
if  (TrueBBI.BB->pred_size() > 1 || FalseBBI.BB->pred_size() > 1)
  return false;

// FIXME: Allow true block to have an early exit?
if (TrueBBI.FalseBB || FalseBBI.FalseBB)
  return false;

// Count duplicate instructions at the beginning and end of the true and
// false blocks.
// Skip unconditional branches only if we are considering an analyzable
// diamond. Otherwise the branches must be the same.
bool SkipUnconditionalBranches =
    TrueBBI.IsBrAnalyzable && FalseBBI.IsBrAnalyzable;
MachineBasicBlock::iterator TIB = TrueBBI.BB->begin();
MachineBasicBlock::iterator FIB = FalseBBI.BB->begin();
MachineBasicBlock::iterator TIE = TrueBBI.BB->end();
MachineBasicBlock::iterator FIE = FalseBBI.BB->end();
if(!CountDuplicatedInstructions(TIB, FIB, TIE, FIE, Dups1, Dups2,
                                *TrueBBI.BB, *FalseBBI.BB,
                                SkipUnconditionalBranches))
  return false;

TrueBBICalc.BB = TrueBBI.BB;
FalseBBICalc.BB = FalseBBI.BB;
TrueBBICalc.IsBrAnalyzable = TrueBBI.IsBrAnalyzable;
FalseBBICalc.IsBrAnalyzable = FalseBBI.IsBrAnalyzable;
if (!RescanInstructions(TIB, FIB, TIE, FIE, TrueBBICalc, FalseBBICalc))
  return false;
// The size is used to decide whether to if-convert, and the shared portions
// are subtracted off. Because of the subtraction, we just use the size that
// was calculated by the original ScanInstructions, as it is correct.
TrueBBICalc.NonPredSize = TrueBBI.NonPredSize;
FalseBBICalc.NonPredSize = FalseBBI.NonPredSize;
return true;
1020}

1022/// AnalyzeBranches - Look at the branches at the end of a block to determine if
1023/// the block is predicable.
1024void IfConverter::AnalyzeBranches(BBInfo &BBI) {
if (BBI.IsDone)
  return;

BBI.TrueBB = BBI.FalseBB = nullptr;
BBI.BrCond.clear();
BBI.IsBrAnalyzable =
    !TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond);
if (!BBI.IsBrAnalyzable) {
  BBI.TrueBB = nullptr;
  BBI.FalseBB = nullptr;
  BBI.BrCond.clear();
}

SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
BBI.IsBrReversible = (RevCond.size() == 0) ||
    !TII->reverseBranchCondition(RevCond);
BBI.HasFallThrough = BBI.IsBrAnalyzable && BBI.FalseBB == nullptr;

if (BBI.BrCond.size()) {
  // No false branch. This BB must end with a conditional branch and a
  // fallthrough.
  if (!BBI.FalseBB)
    BBI.FalseBB = findFalseBlock(BBI.BB, BBI.TrueBB);
  if (!BBI.FalseBB) {
    // Malformed bcc? True and false blocks are the same?
    BBI.IsUnpredicable = true;
  }
}
1053}

1055/// ScanInstructions - Scan all the instructions in the block to determine if
1056/// the block is predicable. In most cases, that means all the instructions
1057/// in the block are isPredicable(). Also checks if the block contains any
1058/// instruction which can clobber a predicate (e.g. condition code register).
1059/// If so, the block is not predicable unless it's the last instruction.
1060void IfConverter::ScanInstructions(BBInfo &BBI,
                                 MachineBasicBlock::iterator &Begin,
                                 MachineBasicBlock::iterator &End,
                                 bool BranchUnpredicable) const {
if (BBI.IsDone || BBI.IsUnpredicable)
  return;

bool AlreadyPredicated = !BBI.Predicate.empty();

BBI.NonPredSize = 0;
BBI.ExtraCost = 0;
BBI.ExtraCost2 = 0;
BBI.ClobbersPred = false;
for (MachineInstr &MI : make_range(Begin, End)) {
  if (MI.isDebugInstr())
    continue;

  // It's unsafe to duplicate convergent instructions in this context, so set
  // BBI.CannotBeCopied to true if MI is convergent.  To see why, consider the
  // following CFG, which is subject to our "simple" transformation.
  //
  //    BB0     // if (c1) goto BB1; else goto BB2;
  //   /   \
  //  BB1   |
  //   |   BB2  // if (c2) goto TBB; else goto FBB;
  //   |   / |
  //   |  /  |
  //   TBB   |
  //    |    |
  //    |   FBB
  //    |
  //    exit
  //
  // Suppose we want to move TBB's contents up into BB1 and BB2 (in BB1 they'd
  // be unconditional, and in BB2, they'd be predicated upon c2), and suppose
  // TBB contains a convergent instruction.  This is safe iff doing so does
  // not add a control-flow dependency to the convergent instruction -- i.e.,
  // it's safe iff the set of control flows that leads us to the convergent
  // instruction does not get smaller after the transformation.
  //
  // Originally we executed TBB if c1 || c2.  After the transformation, there
  // are two copies of TBB's instructions.  We get to the first if c1, and we
  // get to the second if !c1 && c2.
  //
  // There are clearly fewer ways to satisfy the condition "c1" than
  // "c1 || c2".  Since we've shrunk the set of control flows which lead to
  // our convergent instruction, the transformation is unsafe.
  if (MI.isNotDuplicable() || MI.isConvergent())
    BBI.CannotBeCopied = true;

  bool isPredicated = TII->isPredicated(MI);
  bool isCondBr = BBI.IsBrAnalyzable && MI.isConditionalBranch();

  if (BranchUnpredicable && MI.isBranch()) {
    BBI.IsUnpredicable = true;
    return;
  }

  // A conditional branch is not predicable, but it may be eliminated.
  if (isCondBr)
    continue;

  if (!isPredicated) {
    BBI.NonPredSize++;
    unsigned ExtraPredCost = TII->getPredicationCost(MI);
    unsigned NumCycles = SchedModel.computeInstrLatency(&MI, false);
    if (NumCycles > 1)
      BBI.ExtraCost += NumCycles-1;
    BBI.ExtraCost2 += ExtraPredCost;
  } else if (!AlreadyPredicated) {
    // FIXME: This instruction is already predicated before the
    // if-conversion pass. It's probably something like a conditional move.
    // Mark this block unpredicable for now.
    BBI.IsUnpredicable = true;
    return;
  }

  if (BBI.ClobbersPred && !isPredicated) {
    // Predicate modification instruction should end the block (except for
    // already predicated instructions and end of block branches).
    // Predicate may have been modified, the subsequent (currently)
    // unpredicated instructions cannot be correctly predicated.
    BBI.IsUnpredicable = true;
    return;
  }

  // FIXME: Make use of PredDefs? e.g. ADDC, SUBC sets predicates but are
  // still potentially predicable.
  std::vector<MachineOperand> PredDefs;
  if (TII->ClobbersPredicate(MI, PredDefs, true))
    BBI.ClobbersPred = true;

  if (!TII->isPredicable(MI)) {
    BBI.IsUnpredicable = true;
    return;
  }
}
1157}

1159/// Determine if the block is a suitable candidate to be predicated by the
1160/// specified predicate.
1161/// @param BBI BBInfo for the block to check
1162/// @param Pred Predicate array for the branch that leads to BBI
1163/// @param isTriangle true if the Analysis is for a triangle
1164/// @param RevBranch true if Reverse(Pred) leads to BBI (e.g. BBI is the false
1165///        case
1166/// @param hasCommonTail true if BBI shares a tail with a sibling block that
1167///        contains any instruction that would make the block unpredicable.
1168bool IfConverter::FeasibilityAnalysis(BBInfo &BBI,
                                    SmallVectorImpl<MachineOperand> &Pred,
                                    bool isTriangle, bool RevBranch,
                                    bool hasCommonTail) {
// If the block is dead or unpredicable, then it cannot be predicated.
// Two blocks may share a common unpredicable tail, but this doesn't prevent
// them from being if-converted. The non-shared portion is assumed to have
// been checked
if (BBI.IsDone || (BBI.IsUnpredicable && !hasCommonTail))
  return false;

// If it is already predicated but we couldn't analyze its terminator, the
// latter might fallthrough, but we can't determine where to.
// Conservatively avoid if-converting again.
if (BBI.Predicate.size() && !BBI.IsBrAnalyzable)
  return false;

// If it is already predicated, check if the new predicate subsumes
// its predicate.
if (BBI.Predicate.size() && !TII->SubsumesPredicate(Pred, BBI.Predicate))
  return false;

if (!hasCommonTail && BBI.BrCond.size()) {
  if (!isTriangle)
    return false;

  // Test predicate subsumption.
  SmallVector<MachineOperand, 4> RevPred(Pred.begin(), Pred.end());
  SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
  if (RevBranch) {
    if (TII->reverseBranchCondition(Cond))
      return false;
  }
  if (TII->reverseBranchCondition(RevPred) ||
      !TII->SubsumesPredicate(Cond, RevPred))
    return false;
}

return true;
1207}

1209/// Analyze the structure of the sub-CFG starting from the specified block.
1210/// Record its successors and whether it looks like an if-conversion candidate.
1211void IfConverter::AnalyzeBlock(
  MachineBasicBlock &MBB, std::vector<std::unique_ptr<IfcvtToken>> &Tokens) {
struct BBState {
  BBState(MachineBasicBlock &MBB) : MBB(&MBB), SuccsAnalyzed(false) {}
  MachineBasicBlock *MBB;

  /// This flag is true if MBB's successors have been analyzed.
  bool SuccsAnalyzed;
};

// Push MBB to the stack.
SmallVector<BBState, 16> BBStack(1, MBB);

while (!BBStack.empty()) {
  BBState &State = BBStack.back();
  MachineBasicBlock *BB = State.MBB;
  BBInfo &BBI = BBAnalysis[BB->getNumber()];

  if (!State.SuccsAnalyzed) {
    if (BBI.IsAnalyzed || BBI.IsBeingAnalyzed) {
      BBStack.pop_back();
      continue;
    }

    BBI.BB = BB;
    BBI.IsBeingAnalyzed = true;

    AnalyzeBranches(BBI);
    MachineBasicBlock::iterator Begin = BBI.BB->begin();
    MachineBasicBlock::iterator End = BBI.BB->end();
    ScanInstructions(BBI, Begin, End);

    // Unanalyzable or ends with fallthrough or unconditional branch, or if is
    // not considered for ifcvt anymore.
    if (!BBI.IsBrAnalyzable || BBI.BrCond.empty() || BBI.IsDone) {
      BBI.IsBeingAnalyzed = false;
      BBI.IsAnalyzed = true;
      BBStack.pop_back();
      continue;
    }

    // Do not ifcvt if either path is a back edge to the entry block.
    if (BBI.TrueBB == BB || BBI.FalseBB == BB) {
      BBI.IsBeingAnalyzed = false;
      BBI.IsAnalyzed = true;
      BBStack.pop_back();
      continue;
    }

    // Do not ifcvt if true and false fallthrough blocks are the same.
    if (!BBI.FalseBB) {
      BBI.IsBeingAnalyzed = false;
      BBI.IsAnalyzed = true;
      BBStack.pop_back();
      continue;
    }

    // Push the False and True blocks to the stack.
    State.SuccsAnalyzed = true;
    BBStack.push_back(*BBI.FalseBB);
    BBStack.push_back(*BBI.TrueBB);
    continue;
  }

  BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()];
  BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];

  if (TrueBBI.IsDone && FalseBBI.IsDone) {
    BBI.IsBeingAnalyzed = false;
    BBI.IsAnalyzed = true;
    BBStack.pop_back();
    continue;
  }

  SmallVector<MachineOperand, 4>
      RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
  bool CanRevCond = !TII->reverseBranchCondition(RevCond);

  unsigned Dups = 0;
  unsigned Dups2 = 0;
  bool TNeedSub = !TrueBBI.Predicate.empty();
  bool FNeedSub = !FalseBBI.Predicate.empty();
  bool Enqueued = false;

  BranchProbability Prediction = MBPI->getEdgeProbability(BB, TrueBBI.BB);

  if (CanRevCond) {
    BBInfo TrueBBICalc, FalseBBICalc;
    auto feasibleDiamond = [&](bool Forked) {
      bool MeetsSize = MeetIfcvtSizeLimit(TrueBBICalc, FalseBBICalc, *BB,
                                          Dups + Dups2, Prediction, Forked);
      bool TrueFeasible = FeasibilityAnalysis(TrueBBI, BBI.BrCond,
                                              /* IsTriangle */ false, /* RevCond */ false,
                                              /* hasCommonTail */ true);
      bool FalseFeasible = FeasibilityAnalysis(FalseBBI, RevCond,
                                               /* IsTriangle */ false, /* RevCond */ false,
                                               /* hasCommonTail */ true);
      return MeetsSize && TrueFeasible && FalseFeasible;
    };

    if (ValidDiamond(TrueBBI, FalseBBI, Dups, Dups2,
                     TrueBBICalc, FalseBBICalc)) {
      if (feasibleDiamond(false)) {
        // Diamond:
        //   EBB
        //   / \_
        //  |   |
        // TBB FBB
        //   \ /
        //  TailBB
        // Note TailBB can be empty.
        Tokens.push_back(std::make_unique<IfcvtToken>(
            BBI, ICDiamond, TNeedSub | FNeedSub, Dups, Dups2,
            (bool) TrueBBICalc.ClobbersPred, (bool) FalseBBICalc.ClobbersPred));
        Enqueued = true;
      }
    } else if (ValidForkedDiamond(TrueBBI, FalseBBI, Dups, Dups2,
                                  TrueBBICalc, FalseBBICalc)) {
      if (feasibleDiamond(true)) {
        // ForkedDiamond:
        // if TBB and FBB have a common tail that includes their conditional
        // branch instructions, then we can If Convert this pattern.
        //          EBB
        //         _/ \_
        //         |   |
        //        TBB  FBB
        //        / \ /   \
        //  FalseBB TrueBB FalseBB
        //
        Tokens.push_back(std::make_unique<IfcvtToken>(
            BBI, ICForkedDiamond, TNeedSub | FNeedSub, Dups, Dups2,
            (bool) TrueBBICalc.ClobbersPred, (bool) FalseBBICalc.ClobbersPred));
        Enqueued = true;
      }
    }
  }

  if (ValidTriangle(TrueBBI, FalseBBI, false, Dups, Prediction) &&
      MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost,
                         TrueBBI.ExtraCost2, Prediction) &&
      FeasibilityAnalysis(TrueBBI, BBI.BrCond, true)) {
    // Triangle:
    //   EBB
    //   | \_
    //   |  |
    //   | TBB
    //   |  /
    //   FBB
    Tokens.push_back(
        std::make_unique<IfcvtToken>(BBI, ICTriangle, TNeedSub, Dups));
    Enqueued = true;
  }

  if (ValidTriangle(TrueBBI, FalseBBI, true, Dups, Prediction) &&
      MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost,
                         TrueBBI.ExtraCost2, Prediction) &&
      FeasibilityAnalysis(TrueBBI, BBI.BrCond, true, true)) {
    Tokens.push_back(
        std::make_unique<IfcvtToken>(BBI, ICTriangleRev, TNeedSub, Dups));
    Enqueued = true;
  }

  if (ValidSimple(TrueBBI, Dups, Prediction) &&
      MeetIfcvtSizeLimit(*TrueBBI.BB, TrueBBI.NonPredSize + TrueBBI.ExtraCost,
                         TrueBBI.ExtraCost2, Prediction) &&
      FeasibilityAnalysis(TrueBBI, BBI.BrCond)) {
    // Simple (split, no rejoin):
    //   EBB
    //   | \_
    //   |  |
    //   | TBB---> exit
    //   |
    //   FBB
    Tokens.push_back(
        std::make_unique<IfcvtToken>(BBI, ICSimple, TNeedSub, Dups));
    Enqueued = true;
  }

  if (CanRevCond) {
    // Try the other path...
    if (ValidTriangle(FalseBBI, TrueBBI, false, Dups,
                      Prediction.getCompl()) &&
        MeetIfcvtSizeLimit(*FalseBBI.BB,
                           FalseBBI.NonPredSize + FalseBBI.ExtraCost,
                           FalseBBI.ExtraCost2, Prediction.getCompl()) &&
        FeasibilityAnalysis(FalseBBI, RevCond, true)) {
      Tokens.push_back(std::make_unique<IfcvtToken>(BBI, ICTriangleFalse,
                                                     FNeedSub, Dups));
      Enqueued = true;
    }

    if (ValidTriangle(FalseBBI, TrueBBI, true, Dups,
                      Prediction.getCompl()) &&
        MeetIfcvtSizeLimit(*FalseBBI.BB,
                           FalseBBI.NonPredSize + FalseBBI.ExtraCost,
                         FalseBBI.ExtraCost2, Prediction.getCompl()) &&
      FeasibilityAnalysis(FalseBBI, RevCond, true, true)) {
      Tokens.push_back(
          std::make_unique<IfcvtToken>(BBI, ICTriangleFRev, FNeedSub, Dups));
      Enqueued = true;
    }

    if (ValidSimple(FalseBBI, Dups, Prediction.getCompl()) &&
        MeetIfcvtSizeLimit(*FalseBBI.BB,
                           FalseBBI.NonPredSize + FalseBBI.ExtraCost,
                           FalseBBI.ExtraCost2, Prediction.getCompl()) &&
        FeasibilityAnalysis(FalseBBI, RevCond)) {
      Tokens.push_back(
          std::make_unique<IfcvtToken>(BBI, ICSimpleFalse, FNeedSub, Dups));
      Enqueued = true;
    }
  }

  BBI.IsEnqueued = Enqueued;
  BBI.IsBeingAnalyzed = false;
  BBI.IsAnalyzed = true;
  BBStack.pop_back();
}
1429}

1431/// Analyze all blocks and find entries for all if-conversion candidates.
1432void IfConverter::AnalyzeBlocks(
  MachineFunction &MF, std::vector<std::unique_ptr<IfcvtToken>> &Tokens) {
for (MachineBasicBlock &MBB : MF)
  AnalyzeBlock(MBB, Tokens);

// Sort to favor more complex ifcvt scheme.
llvm::stable_sort(Tokens, IfcvtTokenCmp);
1439}

1441/// Returns true either if ToMBB is the next block after MBB or that all the
1442/// intervening blocks are empty (given MBB can fall through to its next block).
1443static bool canFallThroughTo(MachineBasicBlock &MBB, MachineBasicBlock &ToMBB) {
MachineFunction::iterator PI = MBB.getIterator();
MachineFunction::iterator I = std::next(PI);
MachineFunction::iterator TI = ToMBB.getIterator();
MachineFunction::iterator E = MBB.getParent()->end();
while (I != TI) {
  // Check isSuccessor to avoid case where the next block is empty, but
  // it's not a successor.
  if (I == E || !I->empty() || !PI->isSuccessor(&*I))
    return false;
  PI = I++;
}
// Finally see if the last I is indeed a successor to PI.
return PI->isSuccessor(&*I);
1457}

1459/// Invalidate predecessor BB info so it would be re-analyzed to determine if it
1460/// can be if-converted. If predecessor is already enqueued, dequeue it!
1461void IfConverter::InvalidatePreds(MachineBasicBlock &MBB) {
for (const MachineBasicBlock *Predecessor : MBB.predecessors()) {
  BBInfo &PBBI = BBAnalysis[Predecessor->getNumber()];
  if (PBBI.IsDone || PBBI.BB == &MBB)
    continue;
  PBBI.IsAnalyzed = false;
  PBBI.IsEnqueued = false;
}
1469}

1471/// Inserts an unconditional branch from \p MBB to \p ToMBB.
1472static void InsertUncondBranch(MachineBasicBlock &MBB, MachineBasicBlock &ToMBB,
                             const TargetInstrInfo *TII) {
DebugLoc dl;  // FIXME: this is nowhere
SmallVector<MachineOperand, 0> NoCond;
TII->insertBranch(MBB, &ToMBB, nullptr, NoCond, dl);
1477}

1479/// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
1480/// values defined in MI which are also live/used by MI.
1481static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
const TargetRegisterInfo *TRI = MI.getMF()->getSubtarget().getRegisterInfo();

// Before stepping forward past MI, remember which regs were live
// before MI. This is needed to set the Undef flag only when reg is
// dead.
SparseSet<MCPhysReg, identity<MCPhysReg>> LiveBeforeMI;
LiveBeforeMI.setUniverse(TRI->getNumRegs());
for (unsigned Reg : Redefs)
  LiveBeforeMI.insert(Reg);

SmallVector<std::pair<MCPhysReg, const MachineOperand*>, 4> Clobbers;
Redefs.stepForward(MI, Clobbers);

// Now add the implicit uses for each of the clobbered values.
for (auto Clobber : Clobbers) {
  // FIXME: Const cast here is nasty, but better than making StepForward
  // take a mutable instruction instead of const.
  unsigned Reg = Clobber.first;
  MachineOperand &Op = const_cast<MachineOperand&>(*Clobber.second);
  MachineInstr *OpMI = Op.getParent();
  MachineInstrBuilder MIB(*OpMI->getMF(), OpMI);
  if (Op.isRegMask()) {
    // First handle regmasks.  They clobber any entries in the mask which
    // means that we need a def for those registers.
    if (LiveBeforeMI.count(Reg))
      MIB.addReg(Reg, RegState::Implicit);

    // We also need to add an implicit def of this register for the later
    // use to read from.
    // For the register allocator to have allocated a register clobbered
    // by the call which is used later, it must be the case that
    // the call doesn't return.
    MIB.addReg(Reg, RegState::Implicit | RegState::Define);
    continue;
  }
  if (LiveBeforeMI.count(Reg))
    MIB.addReg(Reg, RegState::Implicit);
  else {
    bool HasLiveSubReg = false;
    for (MCSubRegIterator S(Reg, TRI); S.isValid(); ++S) {
      if (!LiveBeforeMI.count(*S))
        continue;
      HasLiveSubReg = true;
      break;
    }
    if (HasLiveSubReg)
      MIB.addReg(Reg, RegState::Implicit);
  }
}
1531}

1533/// If convert a simple (split, no rejoin) sub-CFG.
1534bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) {
BBInfo &TrueBBI  = BBAnalysis[BBI.TrueBB->getNumber()];
BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];
BBInfo *CvtBBI = &TrueBBI;
BBInfo *NextBBI = &FalseBBI;

SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
if (Kind == ICSimpleFalse)
  std::swap(CvtBBI, NextBBI);

MachineBasicBlock &CvtMBB = *CvtBBI->BB;
MachineBasicBlock &NextMBB = *NextBBI->BB;
if (CvtBBI->IsDone ||
    (CvtBBI->CannotBeCopied && CvtMBB.pred_size() > 1)) {
  // Something has changed. It's no longer safe to predicate this block.
  BBI.IsAnalyzed = false;
  CvtBBI->IsAnalyzed = false;
  return false;
}

if (CvtMBB.hasAddressTaken())
  // Conservatively abort if-conversion if BB's address is taken.
  return false;

if (Kind == ICSimpleFalse)
  if (TII->reverseBranchCondition(Cond))
    llvm_unreachable("Unable to reverse branch condition!")::llvm::llvm_unreachable_internal("Unable to reverse branch condition!"
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 1560);

Redefs.init(*TRI);

if (MRI->tracksLiveness()) {
  // Initialize liveins to the first BB. These are potentially redefined by
  // predicated instructions.
  Redefs.addLiveIns(CvtMBB);
  Redefs.addLiveIns(NextMBB);
}

// Remove the branches from the entry so we can add the contents of the true
// block to it.
BBI.NonPredSize -= TII->removeBranch(*BBI.BB);

if (CvtMBB.pred_size() > 1) {
  // Copy instructions in the true block, predicate them, and add them to
  // the entry block.
  CopyAndPredicateBlock(BBI, *CvtBBI, Cond);

  // Keep the CFG updated.
  BBI.BB->removeSuccessor(&CvtMBB, true);
} else {
  // Predicate the instructions in the true block.
  PredicateBlock(*CvtBBI, CvtMBB.end(), Cond);

  // Merge converted block into entry block. The BB to Cvt edge is removed
  // by MergeBlocks.
  MergeBlocks(BBI, *CvtBBI);
}

bool IterIfcvt = true;
if (!canFallThroughTo(*BBI.BB, NextMBB)) {
  InsertUncondBranch(*BBI.BB, NextMBB, TII);
  BBI.HasFallThrough = false;
  // Now ifcvt'd block will look like this:
  // BB:
  // ...
  // t, f = cmp
  // if t op
  // b BBf
  //
  // We cannot further ifcvt this block because the unconditional branch
  // will have to be predicated on the new condition, that will not be
  // available if cmp executes.
  IterIfcvt = false;
}

// Update block info. BB can be iteratively if-converted.
if (!IterIfcvt)
  BBI.IsDone = true;
InvalidatePreds(*BBI.BB);
CvtBBI->IsDone = true;

// FIXME: Must maintain LiveIns.
return true;
1616}

1618/// If convert a triangle sub-CFG.
1619bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()];
BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];
BBInfo *CvtBBI = &TrueBBI;
BBInfo *NextBBI = &FalseBBI;
DebugLoc dl;  // FIXME: this is nowhere

SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
  std::swap(CvtBBI, NextBBI);

MachineBasicBlock &CvtMBB = *CvtBBI->BB;
MachineBasicBlock &NextMBB = *NextBBI->BB;
if (CvtBBI->IsDone ||
    (CvtBBI->CannotBeCopied && CvtMBB.pred_size() > 1)) {
  // Something has changed. It's no longer safe to predicate this block.
  BBI.IsAnalyzed = false;
  CvtBBI->IsAnalyzed = false;
  return false;
}

if (CvtMBB.hasAddressTaken())
  // Conservatively abort if-conversion if BB's address is taken.
  return false;

if (Kind == ICTriangleFalse || Kind == ICTriangleFRev)
  if (TII->reverseBranchCondition(Cond))
    llvm_unreachable("Unable to reverse branch condition!")::llvm::llvm_unreachable_internal("Unable to reverse branch condition!"
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 1646);

if (Kind == ICTriangleRev || Kind == ICTriangleFRev) {
  if (reverseBranchCondition(*CvtBBI)) {
    // BB has been changed, modify its predecessors (except for this
    // one) so they don't get ifcvt'ed based on bad intel.
    for (MachineBasicBlock *PBB : CvtMBB.predecessors()) {
      if (PBB == BBI.BB)
        continue;
      BBInfo &PBBI = BBAnalysis[PBB->getNumber()];
      if (PBBI.IsEnqueued) {
        PBBI.IsAnalyzed = false;
        PBBI.IsEnqueued = false;
      }
    }
  }
}

// Initialize liveins to the first BB. These are potentially redefined by
// predicated instructions.
Redefs.init(*TRI);
if (MRI->tracksLiveness()) {
  Redefs.addLiveIns(CvtMBB);
  Redefs.addLiveIns(NextMBB);
}

bool HasEarlyExit = CvtBBI->FalseBB != nullptr;
BranchProbability CvtNext, CvtFalse, BBNext, BBCvt;

if (HasEarlyExit) {
  // Get probabilities before modifying CvtMBB and BBI.BB.
  CvtNext = MBPI->getEdgeProbability(&CvtMBB, &NextMBB);
  CvtFalse = MBPI->getEdgeProbability(&CvtMBB, CvtBBI->FalseBB);
  BBNext = MBPI->getEdgeProbability(BBI.BB, &NextMBB);
  BBCvt = MBPI->getEdgeProbability(BBI.BB, &CvtMBB);
}

// Remove the branches from the entry so we can add the contents of the true
// block to it.
BBI.NonPredSize -= TII->removeBranch(*BBI.BB);

if (CvtMBB.pred_size() > 1) {
  // Copy instructions in the true block, predicate them, and add them to
  // the entry block.
  CopyAndPredicateBlock(BBI, *CvtBBI, Cond, true);
} else {
  // Predicate the 'true' block after removing its branch.
  CvtBBI->NonPredSize -= TII->removeBranch(CvtMBB);
  PredicateBlock(*CvtBBI, CvtMBB.end(), Cond);

  // Now merge the entry of the triangle with the true block.
  MergeBlocks(BBI, *CvtBBI, false);
}

// Keep the CFG updated.
BBI.BB->removeSuccessor(&CvtMBB, true);

// If 'true' block has a 'false' successor, add an exit branch to it.
if (HasEarlyExit) {
  SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(),
                                         CvtBBI->BrCond.end());
  if (TII->reverseBranchCondition(RevCond))
    llvm_unreachable("Unable to reverse branch condition!")::llvm::llvm_unreachable_internal("Unable to reverse branch condition!"
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 1708);

  // Update the edge probability for both CvtBBI->FalseBB and NextBBI.
  // NewNext = New_Prob(BBI.BB, NextMBB) =
  //   Prob(BBI.BB, NextMBB) +
  //   Prob(BBI.BB, CvtMBB) * Prob(CvtMBB, NextMBB)
  // NewFalse = New_Prob(BBI.BB, CvtBBI->FalseBB) =
  //   Prob(BBI.BB, CvtMBB) * Prob(CvtMBB, CvtBBI->FalseBB)
  auto NewTrueBB = getNextBlock(*BBI.BB);
  auto NewNext = BBNext + BBCvt * CvtNext;
  auto NewTrueBBIter = find(BBI.BB->successors(), NewTrueBB);
  if (NewTrueBBIter != BBI.BB->succ_end())
    BBI.BB->setSuccProbability(NewTrueBBIter, NewNext);

  auto NewFalse = BBCvt * CvtFalse;
  TII->insertBranch(*BBI.BB, CvtBBI->FalseBB, nullptr, RevCond, dl);
  BBI.BB->addSuccessor(CvtBBI->FalseBB, NewFalse);
}

// Merge in the 'false' block if the 'false' block has no other
// predecessors. Otherwise, add an unconditional branch to 'false'.
bool FalseBBDead = false;
bool IterIfcvt = true;
bool isFallThrough = canFallThroughTo(*BBI.BB, NextMBB);
if (!isFallThrough) {
  // Only merge them if the true block does not fallthrough to the false
  // block. By not merging them, we make it possible to iteratively
  // ifcvt the blocks.
  if (!HasEarlyExit &&
      NextMBB.pred_size() == 1 && !NextBBI->HasFallThrough &&
      !NextMBB.hasAddressTaken()) {
    MergeBlocks(BBI, *NextBBI);
    FalseBBDead = true;
  } else {
    InsertUncondBranch(*BBI.BB, NextMBB, TII);
    BBI.HasFallThrough = false;
  }
  // Mixed predicated and unpredicated code. This cannot be iteratively
  // predicated.
  IterIfcvt = false;
}

// Update block info. BB can be iteratively if-converted.
if (!IterIfcvt)
  BBI.IsDone = true;
InvalidatePreds(*BBI.BB);
CvtBBI->IsDone = true;
if (FalseBBDead)
  NextBBI->IsDone = true;

// FIXME: Must maintain LiveIns.
return true;
1760}

1762/// Common code shared between diamond conversions.
1763/// \p BBI, \p TrueBBI, and \p FalseBBI form the diamond shape.
1764/// \p NumDups1 - number of shared instructions at the beginning of \p TrueBBI
1765///               and FalseBBI
1766/// \p NumDups2 - number of shared instructions at the end of \p TrueBBI
1767///               and \p FalseBBI
1768/// \p RemoveBranch - Remove the common branch of the two blocks before
1769///                   predicating. Only false for unanalyzable fallthrough
1770///                   cases. The caller will replace the branch if necessary.
1771/// \p MergeAddEdges - Add successor edges when merging blocks. Only false for
1772///                    unanalyzable fallthrough
1773bool IfConverter::IfConvertDiamondCommon(
  BBInfo &BBI, BBInfo &TrueBBI, BBInfo &FalseBBI,
  unsigned NumDups1, unsigned NumDups2,
  bool TClobbersPred, bool FClobbersPred,
  bool RemoveBranch, bool MergeAddEdges) {

if (TrueBBI.IsDone || FalseBBI.IsDone ||
    TrueBBI.BB->pred_size() > 1 || FalseBBI.BB->pred_size() > 1) {
  // Something has changed. It's no longer safe to predicate these blocks.
  BBI.IsAnalyzed = false;
  TrueBBI.IsAnalyzed = false;
  FalseBBI.IsAnalyzed = false;
  return false;
}

if (TrueBBI.BB->hasAddressTaken() || FalseBBI.BB->hasAddressTaken())
  // Conservatively abort if-conversion if either BB has its address taken.
  return false;

// Put the predicated instructions from the 'true' block before the
// instructions from the 'false' block, unless the true block would clobber
// the predicate, in which case, do the opposite.
BBInfo *BBI1 = &TrueBBI;
BBInfo *BBI2 = &FalseBBI;
SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
if (TII->reverseBranchCondition(RevCond))
  llvm_unreachable("Unable to reverse branch condition!")::llvm::llvm_unreachable_internal("Unable to reverse branch condition!"
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 1799);
SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond;
SmallVector<MachineOperand, 4> *Cond2 = &RevCond;

// Figure out the more profitable ordering.
bool DoSwap = false;
if (TClobbersPred && !FClobbersPred)
  DoSwap = true;
else if (!TClobbersPred && !FClobbersPred) {
  if (TrueBBI.NonPredSize > FalseBBI.NonPredSize)
    DoSwap = true;
} else if (TClobbersPred && FClobbersPred)
  llvm_unreachable("Predicate info cannot be clobbered by both sides.")::llvm::llvm_unreachable_internal("Predicate info cannot be clobbered by both sides."
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 1811);
if (DoSwap) {
  std::swap(BBI1, BBI2);
  std::swap(Cond1, Cond2);
}

// Remove the conditional branch from entry to the blocks.
BBI.NonPredSize -= TII->removeBranch(*BBI.BB);

MachineBasicBlock &MBB1 = *BBI1->BB;
MachineBasicBlock &MBB2 = *BBI2->BB;

// Initialize the Redefs:
// - BB2 live-in regs need implicit uses before being redefined by BB1
//   instructions.
// - BB1 live-out regs need implicit uses before being redefined by BB2
//   instructions. We start with BB1 live-ins so we have the live-out regs
//   after tracking the BB1 instructions.
Redefs.init(*TRI);
if (MRI->tracksLiveness()) {
  Redefs.addLiveIns(MBB1);
  Redefs.addLiveIns(MBB2);
}

// Remove the duplicated instructions at the beginnings of both paths.
// Skip dbg_value instructions.
MachineBasicBlock::iterator DI1 = MBB1.getFirstNonDebugInstr(false);
MachineBasicBlock::iterator DI2 = MBB2.getFirstNonDebugInstr(false);
BBI1->NonPredSize -= NumDups1;
BBI2->NonPredSize -= NumDups1;

// Skip past the dups on each side separately since there may be
// differing dbg_value entries. NumDups1 can include a "return"
// instruction, if it's not marked as "branch".
for (unsigned i = 0; i < NumDups1; ++DI1) {
  if (DI1 == MBB1.end())
    break;
  if (!DI1->isDebugInstr())
    ++i;
}
while (NumDups1 != 0) {
  // Since this instruction is going to be deleted, update call
  // site info state if the instruction is call instruction.
  if (DI2->shouldUpdateCallSiteInfo())
    MBB2.getParent()->eraseCallSiteInfo(&*DI2);

  ++DI2;
  if (DI2 == MBB2.end())
    break;
  if (!DI2->isDebugInstr())
    --NumDups1;
}

if (MRI->tracksLiveness()) {
  for (const MachineInstr &MI : make_range(MBB1.begin(), DI1)) {
    SmallVector<std::pair<MCPhysReg, const MachineOperand*>, 4> Dummy;
    Redefs.stepForward(MI, Dummy);
  }
}

BBI.BB->splice(BBI.BB->end(), &MBB1, MBB1.begin(), DI1);
MBB2.erase(MBB2.begin(), DI2);

// The branches have been checked to match, so it is safe to remove the
// branch in BB1 and rely on the copy in BB2. The complication is that
// the blocks may end with a return instruction, which may or may not
// be marked as "branch". If it's not, then it could be included in
// "dups1", leaving the blocks potentially empty after moving the common
// duplicates.
1880#ifndef NDEBUG
// Unanalyzable branches must match exactly. Check that now.
if (!BBI1->IsBrAnalyzable)
  verifySameBranchInstructions(&MBB1, &MBB2);
1884#endif
// Remove duplicated instructions from the tail of MBB1: any branch
// instructions, and the common instructions counted by NumDups2.
DI1 = MBB1.end();
while (DI1 != MBB1.begin()) {
  MachineBasicBlock::iterator Prev = std::prev(DI1);
  if (!Prev->isBranch() && !Prev->isDebugInstr())
    break;
  DI1 = Prev;
}
for (unsigned i = 0; i != NumDups2; ) {
  // NumDups2 only counted non-dbg_value instructions, so this won't
  // run off the head of the list.
  assert(DI1 != MBB1.begin())(static_cast <bool> (DI1 != MBB1.begin()) ? void (0) : __assert_fail
 ("DI1 != MBB1.begin()", "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 1897, __extension__ __PRETTY_FUNCTION__));

  --DI1;

  // Since this instruction is going to be deleted, update call
  // site info state if the instruction is call instruction.
  if (DI1->shouldUpdateCallSiteInfo())
    MBB1.getParent()->eraseCallSiteInfo(&*DI1);

  // skip dbg_value instructions
  if (!DI1->isDebugInstr())
    ++i;
}
MBB1.erase(DI1, MBB1.end());

DI2 = BBI2->BB->end();
// The branches have been checked to match. Skip over the branch in the false
// block so that we don't try to predicate it.
if (RemoveBranch)
  BBI2->NonPredSize -= TII->removeBranch(*BBI2->BB);
else {
  // Make DI2 point to the end of the range where the common "tail"
  // instructions could be found.
  while (DI2 != MBB2.begin()) {
    MachineBasicBlock::iterator Prev = std::prev(DI2);
    if (!Prev->isBranch() && !Prev->isDebugInstr())
      break;
    DI2 = Prev;
  }
}
while (NumDups2 != 0) {
  // NumDups2 only counted non-dbg_value instructions, so this won't
  // run off the head of the list.
  assert(DI2 != MBB2.begin())(static_cast <bool> (DI2 != MBB2.begin()) ? void (0) : __assert_fail
 ("DI2 != MBB2.begin()", "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 1930, __extension__ __PRETTY_FUNCTION__));
  --DI2;
  // skip dbg_value instructions
  if (!DI2->isDebugInstr())
    --NumDups2;
}

// Remember which registers would later be defined by the false block.
// This allows us not to predicate instructions in the true block that would
// later be re-defined. That is, rather than
//   subeq  r0, r1, #1
//   addne  r0, r1, #1
// generate:
//   sub    r0, r1, #1
//   addne  r0, r1, #1
SmallSet<MCPhysReg, 4> RedefsByFalse;
SmallSet<MCPhysReg, 4> ExtUses;
if (TII->isProfitableToUnpredicate(MBB1, MBB2)) {
  for (const MachineInstr &FI : make_range(MBB2.begin(), DI2)) {
    if (FI.isDebugInstr())
      continue;
    SmallVector<MCPhysReg, 4> Defs;
    for (const MachineOperand &MO : FI.operands()) {
      if (!MO.isReg())
        continue;
      Register Reg = MO.getReg();
      if (!Reg)
        continue;
      if (MO.isDef()) {
        Defs.push_back(Reg);
      } else if (!RedefsByFalse.count(Reg)) {
        // These are defined before ctrl flow reach the 'false' instructions.
        // They cannot be modified by the 'true' instructions.
        for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
             SubRegs.isValid(); ++SubRegs)
          ExtUses.insert(*SubRegs);
      }
    }

    for (MCPhysReg Reg : Defs) {
      if (!ExtUses.count(Reg)) {
        for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
             SubRegs.isValid(); ++SubRegs)
          RedefsByFalse.insert(*SubRegs);
      }
    }
  }
}

// Predicate the 'true' block.
PredicateBlock(*BBI1, MBB1.end(), *Cond1, &RedefsByFalse);

// After predicating BBI1, if there is a predicated terminator in BBI1 and
// a non-predicated in BBI2, then we don't want to predicate the one from
// BBI2. The reason is that if we merged these blocks, we would end up with
// two predicated terminators in the same block.
// Also, if the branches in MBB1 and MBB2 were non-analyzable, then don't
// predicate them either. They were checked to be identical, and so the
// same branch would happen regardless of which path was taken.
if (!MBB2.empty() && (DI2 == MBB2.end())) {
  MachineBasicBlock::iterator BBI1T = MBB1.getFirstTerminator();
  MachineBasicBlock::iterator BBI2T = MBB2.getFirstTerminator();
  bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T);
  bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T);
  if (BB2NonPredicated && (BB1Predicated || !BBI2->IsBrAnalyzable))
    --DI2;
}

// Predicate the 'false' block.
PredicateBlock(*BBI2, DI2, *Cond2);

// Merge the true block into the entry of the diamond.
MergeBlocks(BBI, *BBI1, MergeAddEdges);
MergeBlocks(BBI, *BBI2, MergeAddEdges);
return true;
2005}

2007/// If convert an almost-diamond sub-CFG where the true
2008/// and false blocks share a common tail.
2009bool IfConverter::IfConvertForkedDiamond(
  BBInfo &BBI, IfcvtKind Kind,
  unsigned NumDups1, unsigned NumDups2,
  bool TClobbersPred, bool FClobbersPred) {
BBInfo &TrueBBI  = BBAnalysis[BBI.TrueBB->getNumber()];
BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];

// Save the debug location for later.
DebugLoc dl;
MachineBasicBlock::iterator TIE = TrueBBI.BB->getFirstTerminator();
if (TIE != TrueBBI.BB->end())
  dl = TIE->getDebugLoc();
// Removing branches from both blocks is safe, because we have already
// determined that both blocks have the same branch instructions. The branch
// will be added back at the end, unpredicated.
if (!IfConvertDiamondCommon(
    BBI, TrueBBI, FalseBBI,
    NumDups1, NumDups2,
    TClobbersPred, FClobbersPred,
    /* RemoveBranch */ true, /* MergeAddEdges */ true))
  return false;

// Add back the branch.
// Debug location saved above when removing the branch from BBI2
TII->insertBranch(*BBI.BB, TrueBBI.TrueBB, TrueBBI.FalseBB,
                  TrueBBI.BrCond, dl);

// Update block info.
BBI.IsDone = TrueBBI.IsDone = FalseBBI.IsDone = true;
InvalidatePreds(*BBI.BB);

// FIXME: Must maintain LiveIns.
return true;
2042}

2044/// If convert a diamond sub-CFG.
2045bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
                                 unsigned NumDups1, unsigned NumDups2,
                                 bool TClobbersPred, bool FClobbersPred) {
BBInfo &TrueBBI  = BBAnalysis[BBI.TrueBB->getNumber()];
BBInfo &FalseBBI = BBAnalysis[BBI.FalseBB->getNumber()];
MachineBasicBlock *TailBB = TrueBBI.TrueBB;

// True block must fall through or end with an unanalyzable terminator.
if (!TailBB) {
  if (blockAlwaysFallThrough(TrueBBI))
    TailBB = FalseBBI.TrueBB;
  assert((TailBB || !TrueBBI.IsBrAnalyzable) && "Unexpected!")(static_cast <bool> ((TailBB || !TrueBBI.IsBrAnalyzable
) && "Unexpected!") ? void (0) : __assert_fail ("(TailBB || !TrueBBI.IsBrAnalyzable) && \"Unexpected!\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 2056, __extension__ __PRETTY_FUNCTION__));
}

if (!IfConvertDiamondCommon(
    BBI, TrueBBI, FalseBBI,
    NumDups1, NumDups2,
    TClobbersPred, FClobbersPred,
    /* RemoveBranch */ TrueBBI.IsBrAnalyzable,
    /* MergeAddEdges */ TailBB == nullptr))
  return false;

// If the if-converted block falls through or unconditionally branches into
// the tail block, and the tail block does not have other predecessors, then
// fold the tail block in as well. Otherwise, unless it falls through to the
// tail, add a unconditional branch to it.
if (TailBB) {
  // We need to remove the edges to the true and false blocks manually since
  // we didn't let IfConvertDiamondCommon update the CFG.
  BBI.BB->removeSuccessor(TrueBBI.BB);
  BBI.BB->removeSuccessor(FalseBBI.BB, true);

  BBInfo &TailBBI = BBAnalysis[TailBB->getNumber()];
  bool CanMergeTail = !TailBBI.HasFallThrough &&
    !TailBBI.BB->hasAddressTaken();
  // The if-converted block can still have a predicated terminator
  // (e.g. a predicated return). If that is the case, we cannot merge
  // it with the tail block.
  MachineBasicBlock::const_iterator TI = BBI.BB->getFirstTerminator();
  if (TI != BBI.BB->end() && TII->isPredicated(*TI))
    CanMergeTail = false;
  // There may still be a fall-through edge from BBI1 or BBI2 to TailBB;
  // check if there are any other predecessors besides those.
  unsigned NumPreds = TailBB->pred_size();
  if (NumPreds > 1)
    CanMergeTail = false;
  else if (NumPreds == 1 && CanMergeTail) {
    MachineBasicBlock::pred_iterator PI = TailBB->pred_begin();
    if (*PI != TrueBBI.BB && *PI != FalseBBI.BB)
      CanMergeTail = false;
  }
  if (CanMergeTail) {
    MergeBlocks(BBI, TailBBI);
    TailBBI.IsDone = true;
  } else {
    BBI.BB->addSuccessor(TailBB, BranchProbability::getOne());
    InsertUncondBranch(*BBI.BB, *TailBB, TII);
    BBI.HasFallThrough = false;
  }
}

// Update block info.
BBI.IsDone = TrueBBI.IsDone = FalseBBI.IsDone = true;
InvalidatePreds(*BBI.BB);

// FIXME: Must maintain LiveIns.
return true;
2112}

2114static bool MaySpeculate(const MachineInstr &MI,
                       SmallSet<MCPhysReg, 4> &LaterRedefs) {
bool SawStore = true;
if (!MI.isSafeToMove(nullptr, SawStore))
  return false;

for (const MachineOperand &MO : MI.operands()) {
  if (!MO.isReg())
    continue;
  Register Reg = MO.getReg();
  if (!Reg)
    continue;
  if (MO.isDef() && !LaterRedefs.count(Reg))
    return false;
}

return true;
2131}

2133/// Predicate instructions from the start of the block to the specified end with
2134/// the specified condition.
2135void IfConverter::PredicateBlock(BBInfo &BBI,
                               MachineBasicBlock::iterator E,
                               SmallVectorImpl<MachineOperand> &Cond,
                               SmallSet<MCPhysReg, 4> *LaterRedefs) {
bool AnyUnpred = false;
bool MaySpec = LaterRedefs != nullptr;
for (MachineInstr &I : make_range(BBI.BB->begin(), E)) {
  if (I.isDebugInstr() || TII->isPredicated(I))
    continue;
  // It may be possible not to predicate an instruction if it's the 'true'
  // side of a diamond and the 'false' side may re-define the instruction's
  // defs.
  if (MaySpec && MaySpeculate(I, *LaterRedefs)) {
    AnyUnpred = true;
    continue;
  }
  // If any instruction is predicated, then every instruction after it must
  // be predicated.
  MaySpec = false;
  if (!TII->PredicateInstruction(I, Cond)) {
2155#ifndef NDEBUG
    dbgs() << "Unable to predicate " << I << "!\n";
2157#endif
    llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 2158);
  }

  // If the predicated instruction now redefines a register as the result of
  // if-conversion, add an implicit kill.
  UpdatePredRedefs(I, Redefs);
}

BBI.Predicate.append(Cond.begin(), Cond.end());

BBI.IsAnalyzed = false;
BBI.NonPredSize = 0;

++NumIfConvBBs;
if (AnyUnpred)
  ++NumUnpred;
2174}

2176/// Copy and predicate instructions from source BB to the destination block.
2177/// Skip end of block branches if IgnoreBr is true.
2178void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
                                      SmallVectorImpl<MachineOperand> &Cond,
                                      bool IgnoreBr) {
MachineFunction &MF = *ToBBI.BB->getParent();

MachineBasicBlock &FromMBB = *FromBBI.BB;
for (MachineInstr &I : FromMBB) {
  // Do not copy the end of the block branches.
  if (IgnoreBr && I.isBranch())
    break;

  MachineInstr *MI = MF.CloneMachineInstr(&I);
  // Make a copy of the call site info.
  if (I.isCandidateForCallSiteEntry())
    MF.copyCallSiteInfo(&I, MI);

  ToBBI.BB->insert(ToBBI.BB->end(), MI);
  ToBBI.NonPredSize++;
  unsigned ExtraPredCost = TII->getPredicationCost(I);
  unsigned NumCycles = SchedModel.computeInstrLatency(&I, false);
  if (NumCycles > 1)
    ToBBI.ExtraCost += NumCycles-1;
  ToBBI.ExtraCost2 += ExtraPredCost;

  if (!TII->isPredicated(I) && !MI->isDebugInstr()) {
    if (!TII->PredicateInstruction(*MI, Cond)) {
2204#ifndef NDEBUG
      dbgs() << "Unable to predicate " << I << "!\n";
2206#endif
      llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 2207);
    }
  }

  // If the predicated instruction now redefines a register as the result of
  // if-conversion, add an implicit kill.
  UpdatePredRedefs(*MI, Redefs);
}

if (!IgnoreBr) {
  std::vector<MachineBasicBlock *> Succs(FromMBB.succ_begin(),
                                         FromMBB.succ_end());
  MachineBasicBlock *NBB = getNextBlock(FromMBB);
  MachineBasicBlock *FallThrough = FromBBI.HasFallThrough ? NBB : nullptr;

  for (MachineBasicBlock *Succ : Succs) {
    // Fallthrough edge can't be transferred.
    if (Succ == FallThrough)
      continue;
    ToBBI.BB->addSuccessor(Succ);
  }
}

ToBBI.Predicate.append(FromBBI.Predicate.begin(), FromBBI.Predicate.end());
ToBBI.Predicate.append(Cond.begin(), Cond.end());

ToBBI.ClobbersPred |= FromBBI.ClobbersPred;
ToBBI.IsAnalyzed = false;

++NumDupBBs;
2237}

2239/// Move all instructions from FromBB to the end of ToBB.  This will leave
2240/// FromBB as an empty block, so remove all of its successor edges and move it
2241/// to the end of the function.  If AddEdges is true, i.e., when FromBBI's
2242/// branch is being moved, add those successor edges to ToBBI and remove the old
2243/// edge from ToBBI to FromBBI.
2244void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges) {
MachineBasicBlock &FromMBB = *FromBBI.BB;
assert(!FromMBB.hasAddressTaken() &&(static_cast <bool> (!FromMBB.hasAddressTaken() &&
 "Removing a BB whose address is taken!") ? void (0) : __assert_fail
 ("!FromMBB.hasAddressTaken() && \"Removing a BB whose address is taken!\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 2247, __extension__ __PRETTY_FUNCTION__))
       "Removing a BB whose address is taken!")(static_cast <bool> (!FromMBB.hasAddressTaken() &&
 "Removing a BB whose address is taken!") ? void (0) : __assert_fail
 ("!FromMBB.hasAddressTaken() && \"Removing a BB whose address is taken!\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/lib/CodeGen/IfConversion.cpp"
, 2247, __extension__ __PRETTY_FUNCTION__));

// In case FromMBB contains terminators (e.g. return instruction),
// first move the non-terminator instructions, then the terminators.
MachineBasicBlock::iterator FromTI = FromMBB.getFirstTerminator();
MachineBasicBlock::iterator ToTI = ToBBI.BB->getFirstTerminator();
ToBBI.BB->splice(ToTI, &FromMBB, FromMBB.begin(), FromTI);

// If FromBB has non-predicated terminator we should copy it at the end.
if (FromTI != FromMBB.end() && !TII->isPredicated(*FromTI))
  ToTI = ToBBI.BB->end();
ToBBI.BB->splice(ToTI, &FromMBB, FromTI, FromMBB.end());

// Force normalizing the successors' probabilities of ToBBI.BB to convert all
// unknown probabilities into known ones.
// FIXME: This usage is too tricky and in the future we would like to
// eliminate all unknown probabilities in MBB.
if (ToBBI.IsBrAnalyzable)
  ToBBI.BB->normalizeSuccProbs();

SmallVector<MachineBasicBlock *, 4> FromSuccs(FromMBB.successors());
MachineBasicBlock *NBB = getNextBlock(FromMBB);
MachineBasicBlock *FallThrough = FromBBI.HasFallThrough ? NBB : nullptr;
// The edge probability from ToBBI.BB to FromMBB, which is only needed when
// AddEdges is true and FromMBB is a successor of ToBBI.BB.
auto To2FromProb = BranchProbability::getZero();
if (AddEdges && ToBBI.BB->isSuccessor(&FromMBB)) {
  // Remove the old edge but remember the edge probability so we can calculate
  // the correct weights on the new edges being added further down.
  To2FromProb = MBPI->getEdgeProbability(ToBBI.BB, &FromMBB);
  ToBBI.BB->removeSuccessor(&FromMBB);
}

for (MachineBasicBlock *Succ : FromSuccs) {
  // Fallthrough edge can't be transferred.
  if (Succ == FallThrough) {
    FromMBB.removeSuccessor(Succ);
    continue;
  }

  auto NewProb = BranchProbability::getZero();
  if (AddEdges) {
    // Calculate the edge probability for the edge from ToBBI.BB to Succ,
    // which is a portion of the edge probability from FromMBB to Succ. The
    // portion ratio is the edge probability from ToBBI.BB to FromMBB (if
    // FromBBI is a successor of ToBBI.BB. See comment below for exception).
    NewProb = MBPI->getEdgeProbability(&FromMBB, Succ);

    // To2FromProb is 0 when FromMBB is not a successor of ToBBI.BB. This
    // only happens when if-converting a diamond CFG and FromMBB is the
    // tail BB.  In this case FromMBB post-dominates ToBBI.BB and hence we
    // could just use the probabilities on FromMBB's out-edges when adding
    // new successors.
    if (!To2FromProb.isZero())
      NewProb *= To2FromProb;
  }

  FromMBB.removeSuccessor(Succ);

  if (AddEdges) {
    // If the edge from ToBBI.BB to Succ already exists, update the
    // probability of this edge by adding NewProb to it. An example is shown
    // below, in which A is ToBBI.BB and B is FromMBB. In this case we
    // don't have to set C as A's successor as it already is. We only need to
    // update the edge probability on A->C. Note that B will not be
    // immediately removed from A's successors. It is possible that B->D is
    // not removed either if D is a fallthrough of B. Later the edge A->D
    // (generated here) and B->D will be combined into one edge. To maintain
    // correct edge probability of this combined edge, we need to set the edge
    // probability of A->B to zero, which is already done above. The edge
    // probability on A->D is calculated by scaling the original probability
    // on A->B by the probability of B->D.
    //
    // Before ifcvt:      After ifcvt (assume B->D is kept):
    //
    //       A                A
    //      /|               /|\
    //     / B              / B|
    //    | /|             |  ||
    //    |/ |             |  |/
    //    C  D             C  D
    //
    if (ToBBI.BB->isSuccessor(Succ))
      ToBBI.BB->setSuccProbability(
          find(ToBBI.BB->successors(), Succ),
          MBPI->getEdgeProbability(ToBBI.BB, Succ) + NewProb);
    else
      ToBBI.BB->addSuccessor(Succ, NewProb);
  }
}

// Move the now empty FromMBB out of the way to the end of the function so
// it doesn't interfere with fallthrough checks done by canFallThroughTo().
MachineBasicBlock *Last = &*FromMBB.getParent()->rbegin();
if (Last != &FromMBB)
  FromMBB.moveAfter(Last);

// Normalize the probabilities of ToBBI.BB's successors with all adjustment
// we've done above.
if (ToBBI.IsBrAnalyzable && FromBBI.IsBrAnalyzable)
  ToBBI.BB->normalizeSuccProbs();

ToBBI.Predicate.append(FromBBI.Predicate.begin(), FromBBI.Predicate.end());
FromBBI.Predicate.clear();

ToBBI.NonPredSize += FromBBI.NonPredSize;
ToBBI.ExtraCost += FromBBI.ExtraCost;
ToBBI.ExtraCost2 += FromBBI.ExtraCost2;
FromBBI.NonPredSize = 0;
FromBBI.ExtraCost = 0;
FromBBI.ExtraCost2 = 0;

ToBBI.ClobbersPred |= FromBBI.ClobbersPred;
ToBBI.HasFallThrough = FromBBI.HasFallThrough;
ToBBI.IsAnalyzed = false;
FromBBI.IsAnalyzed = false;
2363}

2365FunctionPass *
2366llvm::createIfConverter(std::function<bool(const MachineFunction &)> Ftor) {
return new IfConverter(std::move(Ftor));
2368}

←

/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h

→

1//===- llvm/CodeGen/MachineInstrBundleIterator.h ----------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Defines an iterator class that bundles MachineInstr.
10//
11//===----------------------------------------------------------------------===//
12 
13#ifndef LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H
14#define LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H
15 
16#include "llvm/ADT/ilist.h"
17#include "llvm/ADT/simple_ilist.h"
18#include <cassert>
19#include <iterator>
20#include <type_traits>
21 
22namespace llvm {
23 
24template <class T, bool IsReverse> struct MachineInstrBundleIteratorTraits;
25template <class T> struct MachineInstrBundleIteratorTraits<T, false> {
26  using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
27  using instr_iterator = typename list_type::iterator;
28  using nonconst_instr_iterator = typename list_type::iterator;
29  using const_instr_iterator = typename list_type::const_iterator;
30};
31template <class T> struct MachineInstrBundleIteratorTraits<T, true> {
32  using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
33  using instr_iterator = typename list_type::reverse_iterator;
34  using nonconst_instr_iterator = typename list_type::reverse_iterator;
35  using const_instr_iterator = typename list_type::const_reverse_iterator;
36};
37template <class T> struct MachineInstrBundleIteratorTraits<const T, false> {
38  using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
39  using instr_iterator = typename list_type::const_iterator;
40  using nonconst_instr_iterator = typename list_type::iterator;
41  using const_instr_iterator = typename list_type::const_iterator;
42};
43template <class T> struct MachineInstrBundleIteratorTraits<const T, true> {
44  using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
45  using instr_iterator = typename list_type::const_reverse_iterator;
46  using nonconst_instr_iterator = typename list_type::reverse_iterator;
47  using const_instr_iterator = typename list_type::const_reverse_iterator;
48};
49 
50template <bool IsReverse> struct MachineInstrBundleIteratorHelper;
51template <> struct MachineInstrBundleIteratorHelper<false> {
52  /// Get the beginning of the current bundle.
53  template <class Iterator> static Iterator getBundleBegin(Iterator I) {
54    if (!I.isEnd())
55      while (I->isBundledWithPred())
56        --I;
57    return I;
58  }
59 
60  /// Get the final node of the current bundle.
61  template <class Iterator> static Iterator getBundleFinal(Iterator I) {
62    if (!I.isEnd())
63      while (I->isBundledWithSucc())
64        ++I;
65    return I;
66  }
67 
68  /// Increment forward ilist iterator.
69  template <class Iterator> static void increment(Iterator &I) {
70    I = std::next(getBundleFinal(I));
71  }
72 
73  /// Decrement forward ilist iterator.
74  template <class Iterator> static void decrement(Iterator &I) {
75    I = getBundleBegin(std::prev(I));
76  }
77};
78 
79template <> struct MachineInstrBundleIteratorHelper<true> {
80  /// Get the beginning of the current bundle.
81  template <class Iterator> static Iterator getBundleBegin(Iterator I) {
82    return MachineInstrBundleIteratorHelper<false>::getBundleBegin(
83               I.getReverse())
84        .getReverse();
85  }
86 
87  /// Get the final node of the current bundle.
88  template <class Iterator> static Iterator getBundleFinal(Iterator I) {
89    return MachineInstrBundleIteratorHelper<false>::getBundleFinal(
90               I.getReverse())
91        .getReverse();
92  }
93 
94  /// Increment reverse ilist iterator.
95  template <class Iterator> static void increment(Iterator &I) {
96    I = getBundleBegin(std::next(I));
97  }
98 
99  /// Decrement reverse ilist iterator.
100  template <class Iterator> static void decrement(Iterator &I) {
101    I = std::prev(getBundleFinal(I));
102  }
103};
104 
105/// MachineBasicBlock iterator that automatically skips over MIs that are
106/// inside bundles (i.e. walk top level MIs only).
107template <typename Ty, bool IsReverse = false>
108class MachineInstrBundleIterator : MachineInstrBundleIteratorHelper<IsReverse> {
109  using Traits = MachineInstrBundleIteratorTraits<Ty, IsReverse>;
110  using instr_iterator = typename Traits::instr_iterator;
111 
112  instr_iterator MII;
113 
114public:
115  using value_type = typename instr_iterator::value_type;
116  using difference_type = typename instr_iterator::difference_type;
117  using pointer = typename instr_iterator::pointer;
118  using reference = typename instr_iterator::reference;
119  using const_pointer = typename instr_iterator::const_pointer;
120  using const_reference = typename instr_iterator::const_reference;
121  using iterator_category = std::bidirectional_iterator_tag;
122 
123private:
124  using nonconst_instr_iterator = typename Traits::nonconst_instr_iterator;
125  using const_instr_iterator = typename Traits::const_instr_iterator;
126  using nonconst_iterator =
127      MachineInstrBundleIterator<typename nonconst_instr_iterator::value_type,
128                                 IsReverse>;
129  using reverse_iterator = MachineInstrBundleIterator<Ty, !IsReverse>;
130 
131public:
132  MachineInstrBundleIterator(instr_iterator MI) : MII(MI) {
133    assert((!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) &&(static_cast <bool> ((!MI.getNodePtr() || MI.isEnd() ||
 !MI->isBundledWithPred()) && "It's not legal to initialize MachineInstrBundleIterator with a "
 "bundled MI") ? void (0) : __assert_fail ("(!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) && \"It's not legal to initialize MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 135, __extension__ __PRETTY_FUNCTION__))
134           "It's not legal to initialize MachineInstrBundleIterator with a "(static_cast <bool> ((!MI.getNodePtr() || MI.isEnd() ||
 !MI->isBundledWithPred()) && "It's not legal to initialize MachineInstrBundleIterator with a "
 "bundled MI") ? void (0) : __assert_fail ("(!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) && \"It's not legal to initialize MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 135, __extension__ __PRETTY_FUNCTION__))
135           "bundled MI")(static_cast <bool> ((!MI.getNodePtr() || MI.isEnd() ||
 !MI->isBundledWithPred()) && "It's not legal to initialize MachineInstrBundleIterator with a "
 "bundled MI") ? void (0) : __assert_fail ("(!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) && \"It's not legal to initialize MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 135, __extension__ __PRETTY_FUNCTION__));
136  }
137 
138  MachineInstrBundleIterator(reference MI) : MII(MI) {
139    assert(!MI.isBundledWithPred() && "It's not legal to initialize "(static_cast <bool> (!MI.isBundledWithPred() &&
 "It's not legal to initialize " "MachineInstrBundleIterator with a "
 "bundled MI") ? void (0) : __assert_fail ("!MI.isBundledWithPred() && \"It's not legal to initialize \" \"MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 141, __extension__ __PRETTY_FUNCTION__))
140                                      "MachineInstrBundleIterator with a "(static_cast <bool> (!MI.isBundledWithPred() &&
 "It's not legal to initialize " "MachineInstrBundleIterator with a "
 "bundled MI") ? void (0) : __assert_fail ("!MI.isBundledWithPred() && \"It's not legal to initialize \" \"MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 141, __extension__ __PRETTY_FUNCTION__))
141                                      "bundled MI")(static_cast <bool> (!MI.isBundledWithPred() &&
 "It's not legal to initialize " "MachineInstrBundleIterator with a "
 "bundled MI") ? void (0) : __assert_fail ("!MI.isBundledWithPred() && \"It's not legal to initialize \" \"MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 141, __extension__ __PRETTY_FUNCTION__));
142  }
143 
144  MachineInstrBundleIterator(pointer MI) : MII(MI) {
145    // FIXME: This conversion should be explicit.
146    assert((!MI || !MI->isBundledWithPred()) && "It's not legal to initialize "(static_cast <bool> ((!MI || !MI->isBundledWithPred(
)) && "It's not legal to initialize " "MachineInstrBundleIterator "
 "with a bundled MI") ? void (0) : __assert_fail ("(!MI || !MI->isBundledWithPred()) && \"It's not legal to initialize \" \"MachineInstrBundleIterator \" \"with a bundled MI\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 148, __extension__ __PRETTY_FUNCTION__))
147                                                "MachineInstrBundleIterator "(static_cast <bool> ((!MI || !MI->isBundledWithPred(
)) && "It's not legal to initialize " "MachineInstrBundleIterator "
 "with a bundled MI") ? void (0) : __assert_fail ("(!MI || !MI->isBundledWithPred()) && \"It's not legal to initialize \" \"MachineInstrBundleIterator \" \"with a bundled MI\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 148, __extension__ __PRETTY_FUNCTION__))
148                                                "with a bundled MI")(static_cast <bool> ((!MI || !MI->isBundledWithPred(
)) && "It's not legal to initialize " "MachineInstrBundleIterator "
 "with a bundled MI") ? void (0) : __assert_fail ("(!MI || !MI->isBundledWithPred()) && \"It's not legal to initialize \" \"MachineInstrBundleIterator \" \"with a bundled MI\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 148, __extension__ __PRETTY_FUNCTION__));
149  }
150 
151  // Template allows conversion from const to nonconst.
152  template <class OtherTy>
153  MachineInstrBundleIterator(
154      const MachineInstrBundleIterator<OtherTy, IsReverse> &I,
155      std::enable_if_t<std::is_convertible<OtherTy *, Ty *>::value, void *> =
156          nullptr)
157      : MII(I.getInstrIterator()) {}
158 
159  MachineInstrBundleIterator() : MII(nullptr) {}
160 
161  /// Explicit conversion between forward/reverse iterators.
162  ///
163  /// Translate between forward and reverse iterators without changing range
164  /// boundaries.  The resulting iterator will dereference (and have a handle)
165  /// to the previous node, which is somewhat unexpected; but converting the
166  /// two endpoints in a range will give the same range in reverse.
167  ///
168  /// This matches std::reverse_iterator conversions.
169  explicit MachineInstrBundleIterator(
170      const MachineInstrBundleIterator<Ty, !IsReverse> &I)
171      : MachineInstrBundleIterator(++I.getReverse()) {}
172 
173  /// Get the bundle iterator for the given instruction's bundle.
174  static MachineInstrBundleIterator getAtBundleBegin(instr_iterator MI) {
175    return MachineInstrBundleIteratorHelper<IsReverse>::getBundleBegin(MI);
176  }
177 
178  reference operator*() const { return *MII; }
179  pointer operator->() const { return &operator*(); }
180 
181  /// Check for null.
182  bool isValid() const { return MII.getNodePtr(); }
183 
184  friend bool operator==(const MachineInstrBundleIterator &L,
185                         const MachineInstrBundleIterator &R) {
186    return L.MII == R.MII;
8
←
Calling 'operator=='→
11
←
Returning from 'operator=='→
12
←
Returning zero, which participates in a condition later→
18
←
Calling 'operator=='→
21
←
Returning from 'operator=='→
22
←
Returning zero, which participates in a condition later→
28
←
Calling 'operator=='→
30
←
Returning from 'operator=='→
31
←
Returning zero, which participates in a condition later→
34
←
Calling 'operator=='→
36
←
Returning from 'operator=='→
37
←
Returning zero, which participates in a condition later→
44
←
Calling 'operator=='→
46
←
Returning from 'operator=='→
47
←
Returning zero, which participates in a condition later→
50
←
Calling 'operator=='→
52
←
Returning from 'operator=='→
53
←
Returning zero, which participates in a condition later→
61
←
Calling 'operator=='→
64
←
Returning from 'operator=='→
65
←
Returning zero, which participates in a condition later→
71
←
Calling 'operator=='→
74
←
Returning from 'operator=='→
75
←
Returning zero, which participates in a condition later→
81
←
Calling 'operator=='→
84
←
Returning from 'operator=='→
85
←
Returning zero, which participates in a condition later→
88
←
Calling 'operator=='→
91
←
Returning from 'operator=='→
92
←
Returning zero, which participates in a condition later→
187  }
188  friend bool operator==(const MachineInstrBundleIterator &L,
189                         const const_instr_iterator &R) {
190    return L.MII == R; // Avoid assertion about validity of R.
191  }
192  friend bool operator==(const const_instr_iterator &L,
193                         const MachineInstrBundleIterator &R) {
194    return L == R.MII; // Avoid assertion about validity of L.
195  }
196  friend bool operator==(const MachineInstrBundleIterator &L,
197                         const nonconst_instr_iterator &R) {
198    return L.MII == R; // Avoid assertion about validity of R.
199  }
200  friend bool operator==(const nonconst_instr_iterator &L,
201                         const MachineInstrBundleIterator &R) {
202    return L == R.MII; // Avoid assertion about validity of L.
203  }
204  friend bool operator==(const MachineInstrBundleIterator &L, const_pointer R) {
205    return L == const_instr_iterator(R); // Avoid assertion about validity of R.
206  }
207  friend bool operator==(const_pointer L, const MachineInstrBundleIterator &R) {
208    return const_instr_iterator(L) == R; // Avoid assertion about validity of L.
209  }
210  friend bool operator==(const MachineInstrBundleIterator &L,
211                         const_reference R) {
212    return L == &R; // Avoid assertion about validity of R.
213  }
214  friend bool operator==(const_reference L,
215                         const MachineInstrBundleIterator &R) {
216    return &L == R; // Avoid assertion about validity of L.
217  }
218 
219  friend bool operator!=(const MachineInstrBundleIterator &L,
220                         const MachineInstrBundleIterator &R) {
221    return !(L == R);
7
←
Calling 'operator=='→
13
←
Returning from 'operator=='→
14
←
Returning the value 1, which participates in a condition later→
17
←
Calling 'operator=='→
23
←
Returning from 'operator=='→
24
←
Returning the value 1, which participates in a condition later→
60
←
Calling 'operator=='→
66
←
Returning from 'operator=='→
67
←
Returning the value 1, which participates in a condition later→
70
←
Calling 'operator=='→
76
←
Returning from 'operator=='→
77
←
Returning the value 1, which participates in a condition later→
222  }
223  friend bool operator!=(const MachineInstrBundleIterator &L,
224                         const const_instr_iterator &R) {
225    return !(L == R);
226  }
227  friend bool operator!=(const const_instr_iterator &L,
228                         const MachineInstrBundleIterator &R) {
229    return !(L == R);
230  }
231  friend bool operator!=(const MachineInstrBundleIterator &L,
232                         const nonconst_instr_iterator &R) {
233    return !(L == R);
234  }
235  friend bool operator!=(const nonconst_instr_iterator &L,
236                         const MachineInstrBundleIterator &R) {
237    return !(L == R);
238  }
239  friend bool operator!=(const MachineInstrBundleIterator &L, const_pointer R) {
240    return !(L == R);
241  }
242  friend bool operator!=(const_pointer L, const MachineInstrBundleIterator &R) {
243    return !(L == R);
244  }
245  friend bool operator!=(const MachineInstrBundleIterator &L,
246                         const_reference R) {
247    return !(L == R);
248  }
249  friend bool operator!=(const_reference L,
250                         const MachineInstrBundleIterator &R) {
251    return !(L == R);
252  }
253 
254  // Increment and decrement operators...
255  MachineInstrBundleIterator &operator--() {
256    this->decrement(MII);
257    return *this;
258  }
259  MachineInstrBundleIterator &operator++() {
260    this->increment(MII);
261    return *this;
262  }
263  MachineInstrBundleIterator operator--(int) {
264    MachineInstrBundleIterator Temp = *this;
265    --*this;
266    return Temp;
267  }
268  MachineInstrBundleIterator operator++(int) {
269    MachineInstrBundleIterator Temp = *this;
270    ++*this;
271    return Temp;
272  }
273 
274  instr_iterator getInstrIterator() const { return MII; }
275 
276  nonconst_iterator getNonConstIterator() const { return MII.getNonConst(); }
277 
278  /// Get a reverse iterator to the same node.
279  ///
280  /// Gives a reverse iterator that will dereference (and have a handle) to the
281  /// same node.  Converting the endpoint iterators in a range will give a
282  /// different range; for range operations, use the explicit conversions.
283  reverse_iterator getReverse() const { return MII.getReverse(); }
284};
285 
286} // end namespace llvm
287 
288#endif // LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H

←

/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/ADT/ilist_iterator.h

→

1//===- llvm/ADT/ilist_iterator.h - Intrusive List Iterator ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8 
9#ifndef LLVM_ADT_ILIST_ITERATOR_H
10#define LLVM_ADT_ILIST_ITERATOR_H
11 
12#include "llvm/ADT/ilist_node.h"
13#include <cassert>
14#include <cstddef>
15#include <iterator>
16#include <type_traits>
17 
18namespace llvm {
19 
20namespace ilist_detail {
21 
22/// Find const-correct node types.
23template <class OptionsT, bool IsConst> struct IteratorTraits;
24template <class OptionsT> struct IteratorTraits<OptionsT, false> {
25  using value_type = typename OptionsT::value_type;
26  using pointer = typename OptionsT::pointer;
27  using reference = typename OptionsT::reference;
28  using node_pointer = ilist_node_impl<OptionsT> *;
29  using node_reference = ilist_node_impl<OptionsT> &;
30};
31template <class OptionsT> struct IteratorTraits<OptionsT, true> {
32  using value_type = const typename OptionsT::value_type;
33  using pointer = typename OptionsT::const_pointer;
34  using reference = typename OptionsT::const_reference;
35  using node_pointer = const ilist_node_impl<OptionsT> *;
36  using node_reference = const ilist_node_impl<OptionsT> &;
37};
38 
39template <bool IsReverse> struct IteratorHelper;
40template <> struct IteratorHelper<false> : ilist_detail::NodeAccess {
41  using Access = ilist_detail::NodeAccess;
42 
43  template <class T> static void increment(T *&I) { I = Access::getNext(*I); }
44  template <class T> static void decrement(T *&I) { I = Access::getPrev(*I); }
45};
46template <> struct IteratorHelper<true> : ilist_detail::NodeAccess {
47  using Access = ilist_detail::NodeAccess;
48 
49  template <class T> static void increment(T *&I) { I = Access::getPrev(*I); }
50  template <class T> static void decrement(T *&I) { I = Access::getNext(*I); }
51};
52 
53} // end namespace ilist_detail
54 
55/// Iterator for intrusive lists  based on ilist_node.
56template <class OptionsT, bool IsReverse, bool IsConst>
57class ilist_iterator : ilist_detail::SpecificNodeAccess<OptionsT> {
58  friend ilist_iterator<OptionsT, IsReverse, !IsConst>;
59  friend ilist_iterator<OptionsT, !IsReverse, IsConst>;
60  friend ilist_iterator<OptionsT, !IsReverse, !IsConst>;
61 
62  using Traits = ilist_detail::IteratorTraits<OptionsT, IsConst>;
63  using Access = ilist_detail::SpecificNodeAccess<OptionsT>;
64 
65public:
66  using value_type = typename Traits::value_type;
67  using pointer = typename Traits::pointer;
68  using reference = typename Traits::reference;
69  using difference_type = ptrdiff_t;
70  using iterator_category = std::bidirectional_iterator_tag;
71  using const_pointer = typename OptionsT::const_pointer;
72  using const_reference = typename OptionsT::const_reference;
73 
74private:
75  using node_pointer = typename Traits::node_pointer;
76  using node_reference = typename Traits::node_reference;
77 
78  node_pointer NodePtr = nullptr;
79 
80public:
81  /// Create from an ilist_node.
82  explicit ilist_iterator(node_reference N) : NodePtr(&N) {}
83 
84  explicit ilist_iterator(pointer NP) : NodePtr(Access::getNodePtr(NP)) {}
85  explicit ilist_iterator(reference NR) : NodePtr(Access::getNodePtr(&NR)) {}
86  ilist_iterator() = default;
87 
88  // This is templated so that we can allow constructing a const iterator from
89  // a nonconst iterator...
90  template <bool RHSIsConst>
91  ilist_iterator(const ilist_iterator<OptionsT, IsReverse, RHSIsConst> &RHS,
92                 std::enable_if_t<IsConst || !RHSIsConst, void *> = nullptr)
93      : NodePtr(RHS.NodePtr) {}
94 
95  // This is templated so that we can allow assigning to a const iterator from
96  // a nonconst iterator...
97  template <bool RHSIsConst>
98  std::enable_if_t<IsConst || !RHSIsConst, ilist_iterator &>
99  operator=(const ilist_iterator<OptionsT, IsReverse, RHSIsConst> &RHS) {
100    NodePtr = RHS.NodePtr;
101    return *this;
102  }
103 
104  /// Explicit conversion between forward/reverse iterators.
105  ///
106  /// Translate between forward and reverse iterators without changing range
107  /// boundaries.  The resulting iterator will dereference (and have a handle)
108  /// to the previous node, which is somewhat unexpected; but converting the
109  /// two endpoints in a range will give the same range in reverse.
110  ///
111  /// This matches std::reverse_iterator conversions.
112  explicit ilist_iterator(
113      const ilist_iterator<OptionsT, !IsReverse, IsConst> &RHS)
114      : ilist_iterator(++RHS.getReverse()) {}
115 
116  /// Get a reverse iterator to the same node.
117  ///
118  /// Gives a reverse iterator that will dereference (and have a handle) to the
119  /// same node.  Converting the endpoint iterators in a range will give a
120  /// different range; for range operations, use the explicit conversions.
121  ilist_iterator<OptionsT, !IsReverse, IsConst> getReverse() const {
122    if (NodePtr)
123      return ilist_iterator<OptionsT, !IsReverse, IsConst>(*NodePtr);
124    return ilist_iterator<OptionsT, !IsReverse, IsConst>();
125  }
126 
127  /// Const-cast.
128  ilist_iterator<OptionsT, IsReverse, false> getNonConst() const {
129    if (NodePtr)
130      return ilist_iterator<OptionsT, IsReverse, false>(
131          const_cast<typename ilist_iterator<OptionsT, IsReverse,
132                                             false>::node_reference>(*NodePtr));
133    return ilist_iterator<OptionsT, IsReverse, false>();
134  }
135 
136  // Accessors...
137  reference operator*() const {
138    assert(!NodePtr->isKnownSentinel())(static_cast <bool> (!NodePtr->isKnownSentinel()) ? void
 (0) : __assert_fail ("!NodePtr->isKnownSentinel()", "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/ADT/ilist_iterator.h"
, 138, __extension__ __PRETTY_FUNCTION__));
139    return *Access::getValuePtr(NodePtr);
140  }
141  pointer operator->() const { return &operator*(); }
142 
143  // Comparison operators
144  friend bool operator==(const ilist_iterator &LHS, const ilist_iterator &RHS) {
145    return LHS.NodePtr28.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
34.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
44.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
50.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
28.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
34.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
44.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
50.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
28.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
34.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
44.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
50.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
28.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
34.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
44.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
50.1
'LHS.NodePtr' is not equal to 'RHS.NodePtr'
 == RHS.NodePtr;
9
←
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'→
10
←
Returning zero, which participates in a condition later→
19
←
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'→
20
←
Returning zero, which participates in a condition later→
29
←
Returning zero, which participates in a condition later→
35
←
Returning zero, which participates in a condition later→
45
←
Returning zero, which participates in a condition later→
51
←
Returning zero, which participates in a condition later→
62
←
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'→
63
←
Returning zero, which participates in a condition later→
72
←
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'→
73
←
Returning zero, which participates in a condition later→
82
←
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'→
83
←
Returning zero, which participates in a condition later→
89
←
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'→
90
←
Returning zero, which participates in a condition later→
146  }
147  friend bool operator!=(const ilist_iterator &LHS, const ilist_iterator &RHS) {
148    return LHS.NodePtr != RHS.NodePtr;
149  }
150 
151  // Increment and decrement operators...
152  ilist_iterator &operator--() {
153    NodePtr = IsReverse ? NodePtr->getNext() : NodePtr->getPrev();
154    return *this;
155  }
156  ilist_iterator &operator++() {
157    NodePtr = IsReverse ? NodePtr->getPrev() : NodePtr->getNext();
158    return *this;
159  }
160  ilist_iterator operator--(int) {
161    ilist_iterator tmp = *this;
162    --*this;
163    return tmp;
164  }
165  ilist_iterator operator++(int) {
166    ilist_iterator tmp = *this;
167    ++*this;
168    return tmp;
169  }
170 
171  /// Get the underlying ilist_node.
172  node_pointer getNodePtr() const { return static_cast<node_pointer>(NodePtr); }
173 
174  /// Check for end.  Only valid if ilist_sentinel_tracking<true>.
175  bool isEnd() const { return NodePtr ? NodePtr->isSentinel() : false; }
176};
177 
178template <typename From> struct simplify_type;
179 
180/// Allow ilist_iterators to convert into pointers to a node automatically when
181/// used by the dyn_cast, cast, isa mechanisms...
182///
183/// FIXME: remove this, since there is no implicit conversion to NodeTy.
184template <class OptionsT, bool IsConst>
185struct simplify_type<ilist_iterator<OptionsT, false, IsConst>> {
186  using iterator = ilist_iterator<OptionsT, false, IsConst>;
187  using SimpleType = typename iterator::pointer;
188 
189  static SimpleType getSimplifiedValue(const iterator &Node) { return &*Node; }
190};
191template <class OptionsT, bool IsConst>
192struct simplify_type<const ilist_iterator<OptionsT, false, IsConst>>
193    : simplify_type<ilist_iterator<OptionsT, false, IsConst>> {};
194 
195} // end namespace llvm
196 
197#endif // LLVM_ADT_ILIST_ITERATOR_H

←

/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h

1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//

15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H

18#include "llvm/ADT/DenseMapInfo.h"
19#include "llvm/ADT/PointerSumType.h"
20#include "llvm/ADT/SmallSet.h"
21#include "llvm/ADT/ilist.h"
22#include "llvm/ADT/ilist_node.h"
23#include "llvm/ADT/iterator_range.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineOperand.h"
26#include "llvm/CodeGen/TargetOpcodes.h"
27#include "llvm/IR/DebugLoc.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/IR/PseudoProbe.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Support/ArrayRecycler.h"
33#include "llvm/Support/TrailingObjects.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <utility>

39namespace llvm {

41class AAResults;
42template <typename T> class ArrayRef;
43class DIExpression;
44class DILocalVariable;
45class MachineBasicBlock;
46class MachineFunction;
47class MachineRegisterInfo;
48class ModuleSlotTracker;
49class raw_ostream;
50template <typename T> class SmallVectorImpl;
51class SmallBitVector;
52class StringRef;
53class TargetInstrInfo;
54class TargetRegisterClass;
55class TargetRegisterInfo;

57//===----------------------------------------------------------------------===//
58/// Representation of each machine instruction.
59///
60/// This class isn't a POD type, but it must have a trivial destructor. When a
61/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
62/// without having their destructor called.
63///
64class MachineInstr
  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
                                  ilist_sentinel_tracking<true>> {
67public:
using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;

/// Flags to specify different kinds of comments to output in
/// assembly code.  These flags carry semantic information not
/// otherwise easily derivable from the IR text.
///
enum CommentFlag {
  ReloadReuse = 0x1,    // higher bits are reserved for target dep comments.
  NoSchedComment = 0x2,
  TAsmComments = 0x4    // Target Asm comments should start from this value.
};

enum MIFlag {
  NoFlags      = 0,
  FrameSetup   = 1 << 0,              // Instruction is used as a part of
                                      // function frame setup code.
  FrameDestroy = 1 << 1,              // Instruction is used as a part of
                                      // function frame destruction code.
  BundledPred  = 1 << 2,              // Instruction has bundled predecessors.
  BundledSucc  = 1 << 3,              // Instruction has bundled successors.
  FmNoNans     = 1 << 4,              // Instruction does not support Fast
                                      // math nan values.
  FmNoInfs     = 1 << 5,              // Instruction does not support Fast
                                      // math infinity values.
  FmNsz        = 1 << 6,              // Instruction is not required to retain
                                      // signed zero values.
  FmArcp       = 1 << 7,              // Instruction supports Fast math
                                      // reciprocal approximations.
  FmContract   = 1 << 8,              // Instruction supports Fast math
                                      // contraction operations like fma.
  FmAfn        = 1 << 9,              // Instruction may map to Fast math
                                      // instrinsic approximation.
  FmReassoc    = 1 << 10,             // Instruction supports Fast math
                                      // reassociation of operand order.
  NoUWrap      = 1 << 11,             // Instruction supports binary operator
                                      // no unsigned wrap.
  NoSWrap      = 1 << 12,             // Instruction supports binary operator
                                      // no signed wrap.
  IsExact      = 1 << 13,             // Instruction supports division is
                                      // known to be exact.
  NoFPExcept   = 1 << 14,             // Instruction does not raise
                                      // floatint-point exceptions.
  NoMerge      = 1 << 15,             // Passes that drop source location info
                                      // (e.g. branch folding) should skip
                                      // this instruction.
};

115private:
const MCInstrDesc *MCID;              // Instruction descriptor.
MachineBasicBlock *Parent = nullptr;  // Pointer to the owning basic block.

// Operands are allocated by an ArrayRecycler.
MachineOperand *Operands = nullptr;   // Pointer to the first operand.
unsigned NumOperands = 0;             // Number of operands on instruction.

uint16_t Flags = 0;                   // Various bits of additional
                                      // information about machine
                                      // instruction.

uint8_t AsmPrinterFlags = 0;          // Various bits of information used by
                                      // the AsmPrinter to emit helpful
                                      // comments.  This is *not* semantic
                                      // information.  Do not use this for
                                      // anything other than to convey comment
                                      // information to AsmPrinter.

// OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
// to properly pack.
using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
OperandCapacity CapOperands;          // Capacity of the Operands array.

/// Internal implementation detail class that provides out-of-line storage for
/// extra info used by the machine instruction when this info cannot be stored
/// in-line within the instruction itself.
///
/// This has to be defined eagerly due to the implementation constraints of
/// `PointerSumType` where it is used.
class ExtraInfo final
    : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> {
public:
  static ExtraInfo *create(BumpPtrAllocator &Allocator,
                           ArrayRef<MachineMemOperand *> MMOs,
                           MCSymbol *PreInstrSymbol = nullptr,
                           MCSymbol *PostInstrSymbol = nullptr,
                           MDNode *HeapAllocMarker = nullptr) {
    bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
    bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
    bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
    auto *Result = new (Allocator.Allocate(
        totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>(
            MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
            HasHeapAllocMarker),
        alignof(ExtraInfo)))
        ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
                  HasHeapAllocMarker);

    // Copy the actual data into the trailing objects.
    std::copy(MMOs.begin(), MMOs.end(),
              Result->getTrailingObjects<MachineMemOperand *>());

    if (HasPreInstrSymbol)
      Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
    if (HasPostInstrSymbol)
      Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
          PostInstrSymbol;
    if (HasHeapAllocMarker)
      Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;

    return Result;
  }

  ArrayRef<MachineMemOperand *> getMMOs() const {
    return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
  }

  MCSymbol *getPreInstrSymbol() const {
    return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
  }

  MCSymbol *getPostInstrSymbol() const {
    return HasPostInstrSymbol
               ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
               : nullptr;
  }

  MDNode *getHeapAllocMarker() const {
    return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
  }

private:
  friend TrailingObjects;

  // Description of the extra info, used to interpret the actual optional
  // data appended.
  //
  // Note that this is not terribly space optimized. This leaves a great deal
  // of flexibility to fit more in here later.
  const int NumMMOs;
  const bool HasPreInstrSymbol;
  const bool HasPostInstrSymbol;
  const bool HasHeapAllocMarker;

  // Implement the `TrailingObjects` internal API.
  size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
    return NumMMOs;
  }
  size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
    return HasPreInstrSymbol + HasPostInstrSymbol;
  }
  size_t numTrailingObjects(OverloadToken<MDNode *>) const {
    return HasHeapAllocMarker;
  }

  // Just a boring constructor to allow us to initialize the sizes. Always use
  // the `create` routine above.
  ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
            bool HasHeapAllocMarker)
      : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
        HasPostInstrSymbol(HasPostInstrSymbol),
        HasHeapAllocMarker(HasHeapAllocMarker) {}
};

/// Enumeration of the kinds of inline extra info available. It is important
/// that the `MachineMemOperand` inline kind has a tag value of zero to make
/// it accessible as an `ArrayRef`.
enum ExtraInfoInlineKinds {
  EIIK_MMO = 0,
  EIIK_PreInstrSymbol,
  EIIK_PostInstrSymbol,
  EIIK_OutOfLine
};

// We store extra information about the instruction here. The common case is
// expected to be nothing or a single pointer (typically a MMO or a symbol).
// We work to optimize this common case by storing it inline here rather than
// requiring a separate allocation, but we fall back to an allocation when
// multiple pointers are needed.
PointerSumType<ExtraInfoInlineKinds,
               PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
               PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
               PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
               PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
    Info;

DebugLoc debugLoc;                    // Source line information.

/// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
/// defined by this instruction.
unsigned DebugInstrNum;

// Intrusive list support
friend struct ilist_traits<MachineInstr>;
friend struct ilist_callback_traits<MachineBasicBlock>;
void setParent(MachineBasicBlock *P) { Parent = P; }

/// This constructor creates a copy of the given
/// MachineInstr in the given MachineFunction.
MachineInstr(MachineFunction &, const MachineInstr &);

/// This constructor create a MachineInstr and add the implicit operands.
/// It reserves space for number of operands specified by
/// MCInstrDesc.  An explicit DebugLoc is supplied.
MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
             bool NoImp = false);

// MachineInstrs are pool-allocated and owned by MachineFunction.
friend class MachineFunction;

void
dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
          SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;

280public:
MachineInstr(const MachineInstr &) = delete;
MachineInstr &operator=(const MachineInstr &) = delete;
// Use MachineFunction::DeleteMachineInstr() instead.
~MachineInstr() = delete;

const MachineBasicBlock* getParent() const { return Parent; }
MachineBasicBlock* getParent() { return Parent; }

/// Move the instruction before \p MovePos.
void moveBefore(MachineInstr *MovePos);

/// Return the function that contains the basic block that this instruction
/// belongs to.
///
/// Note: this is undefined behaviour if the instruction does not have a
/// parent.
const MachineFunction *getMF() const;
MachineFunction *getMF() {
  return const_cast<MachineFunction *>(
      static_cast<const MachineInstr *>(this)->getMF());
}

/// Return the asm printer flags bitvector.
uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }

/// Clear the AsmPrinter bitvector.
void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }

/// Return whether an AsmPrinter flag is set.
bool getAsmPrinterFlag(CommentFlag Flag) const {
  return AsmPrinterFlags & Flag;
}

/// Set a flag for the AsmPrinter.
void setAsmPrinterFlag(uint8_t Flag) {
  AsmPrinterFlags |= Flag;
}

/// Clear specific AsmPrinter flags.
void clearAsmPrinterFlag(CommentFlag Flag) {
  AsmPrinterFlags &= ~Flag;
}

/// Return the MI flags bitvector.
uint16_t getFlags() const {
  return Flags;
}

/// Return whether an MI flag is set.
bool getFlag(MIFlag Flag) const {
  return Flags & Flag;
}

/// Set a MI flag.
void setFlag(MIFlag Flag) {
  Flags |= (uint16_t)Flag;
}

void setFlags(unsigned flags) {
  // Filter out the automatically maintained flags.
  unsigned Mask = BundledPred | BundledSucc;
  Flags = (Flags & Mask) | (flags & ~Mask);
}

/// clearFlag - Clear a MI flag.
void clearFlag(MIFlag Flag) {
  Flags &= ~((uint16_t)Flag);
}

/// Return true if MI is in a bundle (but not the first MI in a bundle).
///
/// A bundle looks like this before it's finalized:
///   ----------------
///   |      MI      |
///   ----------------
///          |
///   ----------------
///   |      MI    * |
///   ----------------
///          |
///   ----------------
///   |      MI    * |
///   ----------------
/// In this case, the first MI starts a bundle but is not inside a bundle, the
/// next 2 MIs are considered "inside" the bundle.
///
/// After a bundle is finalized, it looks like this:
///   ----------------
///   |    Bundle    |
///   ----------------
///          |
///   ----------------
///   |      MI    * |
///   ----------------
///          |
///   ----------------
///   |      MI    * |
///   ----------------
///          |
///   ----------------
///   |      MI    * |
///   ----------------
/// The first instruction has the special opcode "BUNDLE". It's not "inside"
/// a bundle, but the next three MIs are.
bool isInsideBundle() const {
  return getFlag(BundledPred);
}

/// Return true if this instruction part of a bundle. This is true
/// if either itself or its following instruction is marked "InsideBundle".
bool isBundled() const {
  return isBundledWithPred() || isBundledWithSucc();
}

/// Return true if this instruction is part of a bundle, and it is not the
/// first instruction in the bundle.
bool isBundledWithPred() const { return getFlag(BundledPred); }

/// Return true if this instruction is part of a bundle, and it is not the
/// last instruction in the bundle.
bool isBundledWithSucc() const { return getFlag(BundledSucc); }

/// Bundle this instruction with its predecessor. This can be an unbundled
/// instruction, or it can be the first instruction in a bundle.
void bundleWithPred();

/// Bundle this instruction with its successor. This can be an unbundled
/// instruction, or it can be the last instruction in a bundle.
void bundleWithSucc();

/// Break bundle above this instruction.
void unbundleFromPred();

/// Break bundle below this instruction.
void unbundleFromSucc();

/// Returns the debug location id of this MachineInstr.
const DebugLoc &getDebugLoc() const { return debugLoc; }

/// Return the operand containing the offset to be used if this DBG_VALUE
/// instruction is indirect; will be an invalid register if this value is
/// not indirect, and an immediate with value 0 otherwise.
const MachineOperand &getDebugOffset() const {
  assert(isNonListDebugValue() && "not a DBG_VALUE")(static_cast <bool> (isNonListDebugValue() && "not a DBG_VALUE"
) ? void (0) : __assert_fail ("isNonListDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 424, __extension__ __PRETTY_FUNCTION__));
  return getOperand(1);
}
MachineOperand &getDebugOffset() {
  assert(isNonListDebugValue() && "not a DBG_VALUE")(static_cast <bool> (isNonListDebugValue() && "not a DBG_VALUE"
) ? void (0) : __assert_fail ("isNonListDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 428, __extension__ __PRETTY_FUNCTION__));
  return getOperand(1);
}

/// Return the operand for the debug variable referenced by
/// this DBG_VALUE instruction.
const MachineOperand &getDebugVariableOp() const;
MachineOperand &getDebugVariableOp();

/// Return the debug variable referenced by
/// this DBG_VALUE instruction.
const DILocalVariable *getDebugVariable() const;

/// Return the operand for the complex address expression referenced by
/// this DBG_VALUE instruction.
const MachineOperand &getDebugExpressionOp() const;
MachineOperand &getDebugExpressionOp();

/// Return the complex address expression referenced by
/// this DBG_VALUE instruction.
const DIExpression *getDebugExpression() const;

/// Return the debug label referenced by
/// this DBG_LABEL instruction.
const DILabel *getDebugLabel() const;

/// Fetch the instruction number of this MachineInstr. If it does not have
/// one already, a new and unique number will be assigned.
unsigned getDebugInstrNum();

/// Examine the instruction number of this MachineInstr. May be zero if
/// it hasn't been assigned a number yet.
unsigned peekDebugInstrNum() const { return DebugInstrNum; }

/// Set instruction number of this MachineInstr. Avoid using unless you're
/// deserializing this information.
void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }

/// Emit an error referring to the source location of this instruction.
/// This should only be used for inline assembly that is somehow
/// impossible to compile. Other errors should have been handled much
/// earlier.
///
/// If this method returns, the caller should try to recover from the error.
void emitError(StringRef Msg) const;

/// Returns the target instruction descriptor of this MachineInstr.
const MCInstrDesc &getDesc() const { return *MCID; }

/// Returns the opcode of this MachineInstr.
unsigned getOpcode() const { return MCID->Opcode; }

/// Retuns the total number of operands.
unsigned getNumOperands() const { return NumOperands; }

/// Returns the total number of operands which are debug locations.
unsigned getNumDebugOperands() const {
  return std::distance(debug_operands().begin(), debug_operands().end());
}

const MachineOperand& getOperand(unsigned i) const {
  assert(i < getNumOperands() && "getOperand() out of range!")(static_cast <bool> (i < getNumOperands() &&
 "getOperand() out of range!") ? void (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 489, __extension__ __PRETTY_FUNCTION__));
  return Operands[i];
}
MachineOperand& getOperand(unsigned i) {
  assert(i < getNumOperands() && "getOperand() out of range!")(static_cast <bool> (i < getNumOperands() &&
 "getOperand() out of range!") ? void (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 493, __extension__ __PRETTY_FUNCTION__));
  return Operands[i];
}

MachineOperand &getDebugOperand(unsigned Index) {
  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!")(static_cast <bool> (Index < getNumDebugOperands() &&
 "getDebugOperand() out of range!") ? void (0) : __assert_fail
 ("Index < getNumDebugOperands() && \"getDebugOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 498, __extension__ __PRETTY_FUNCTION__));
  return *(debug_operands().begin() + Index);
}
const MachineOperand &getDebugOperand(unsigned Index) const {
  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!")(static_cast <bool> (Index < getNumDebugOperands() &&
 "getDebugOperand() out of range!") ? void (0) : __assert_fail
 ("Index < getNumDebugOperands() && \"getDebugOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 502, __extension__ __PRETTY_FUNCTION__));
  return *(debug_operands().begin() + Index);
}

SmallSet<Register, 4> getUsedDebugRegs() const {
  assert(isDebugValue() && "not a DBG_VALUE*")(static_cast <bool> (isDebugValue() && "not a DBG_VALUE*"
) ? void (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE*\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 507, __extension__ __PRETTY_FUNCTION__));
  SmallSet<Register, 4> UsedRegs;
  for (auto MO : debug_operands())
    if (MO.isReg() && MO.getReg())
      UsedRegs.insert(MO.getReg());
  return UsedRegs;
}

/// Returns whether this debug value has at least one debug operand with the
/// register \p Reg.
bool hasDebugOperandForReg(Register Reg) const {
  return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
    return Op.isReg() && Op.getReg() == Reg;
  });
}

/// Returns a range of all of the operands that correspond to a debug use of
/// \p Reg.
template <typename Operand, typename Instruction>
static iterator_range<
    filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
getDebugOperandsForReg(Instruction *MI, Register Reg) {
  std::function<bool(Operand & Op)> OpUsesReg(
      [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
  return make_filter_range(MI->debug_operands(), OpUsesReg);
}
iterator_range<filter_iterator<const MachineOperand *,
                               std::function<bool(const MachineOperand &Op)>>>
getDebugOperandsForReg(Register Reg) const {
  return MachineInstr::getDebugOperandsForReg<const MachineOperand,
                                              const MachineInstr>(this, Reg);
}
iterator_range<filter_iterator<MachineOperand *,
                               std::function<bool(MachineOperand &Op)>>>
getDebugOperandsForReg(Register Reg) {
  return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
      this, Reg);
}

bool isDebugOperand(const MachineOperand *Op) const {
  return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
}

unsigned getDebugOperandIndex(const MachineOperand *Op) const {
  assert(isDebugOperand(Op) && "Expected a debug operand.")(static_cast <bool> (isDebugOperand(Op) && "Expected a debug operand."
) ? void (0) : __assert_fail ("isDebugOperand(Op) && \"Expected a debug operand.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 551, __extension__ __PRETTY_FUNCTION__));
  return std::distance(adl_begin(debug_operands()), Op);
}

/// Returns the total number of definitions.
unsigned getNumDefs() const {
  return getNumExplicitDefs() + MCID->getNumImplicitDefs();
}

/// Returns true if the instruction has implicit definition.
bool hasImplicitDef() const {
  for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
    I != E; ++I) {
    const MachineOperand &MO = getOperand(I);
    if (MO.isDef() && MO.isImplicit())
      return true;
  }
  return false;
}

/// Returns the implicit operands number.
unsigned getNumImplicitOperands() const {
  return getNumOperands() - getNumExplicitOperands();
}

/// Return true if operand \p OpIdx is a subregister index.
bool isOperandSubregIdx(unsigned OpIdx) const {
  assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&(static_cast <bool> (getOperand(OpIdx).getType() == MachineOperand
::MO_Immediate && "Expected MO_Immediate operand type."
) ? void (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 579, __extension__ __PRETTY_FUNCTION__))
         "Expected MO_Immediate operand type.")(static_cast <bool> (getOperand(OpIdx).getType() == MachineOperand
::MO_Immediate && "Expected MO_Immediate operand type."
) ? void (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 579, __extension__ __PRETTY_FUNCTION__));
  if (isExtractSubreg() && OpIdx == 2)
    return true;
  if (isInsertSubreg() && OpIdx == 3)
    return true;
  if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
    return true;
  if (isSubregToReg() && OpIdx == 3)
    return true;
  return false;
}

/// Returns the number of non-implicit operands.
unsigned getNumExplicitOperands() const;

/// Returns the number of non-implicit definitions.
unsigned getNumExplicitDefs() const;

/// iterator/begin/end - Iterate over all operands of a machine instruction.
using mop_iterator = MachineOperand *;
using const_mop_iterator = const MachineOperand *;

mop_iterator operands_begin() { return Operands; }
mop_iterator operands_end() { return Operands + NumOperands; }

const_mop_iterator operands_begin() const { return Operands; }
const_mop_iterator operands_end() const { return Operands + NumOperands; }

iterator_range<mop_iterator> operands() {
  return make_range(operands_begin(), operands_end());
}
iterator_range<const_mop_iterator> operands() const {
  return make_range(operands_begin(), operands_end());
}
iterator_range<mop_iterator> explicit_operands() {
  return make_range(operands_begin(),
                    operands_begin() + getNumExplicitOperands());
}
iterator_range<const_mop_iterator> explicit_operands() const {
  return make_range(operands_begin(),
                    operands_begin() + getNumExplicitOperands());
}
iterator_range<mop_iterator> implicit_operands() {
  return make_range(explicit_operands().end(), operands_end());
}
iterator_range<const_mop_iterator> implicit_operands() const {
  return make_range(explicit_operands().end(), operands_end());
}
/// Returns a range over all operands that are used to determine the variable
/// location for this DBG_VALUE instruction.
iterator_range<mop_iterator> debug_operands() {
  assert(isDebugValue() && "Must be a debug value instruction.")(static_cast <bool> (isDebugValue() && "Must be a debug value instruction."
) ? void (0) : __assert_fail ("isDebugValue() && \"Must be a debug value instruction.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 630, __extension__ __PRETTY_FUNCTION__));
  return isDebugValueList()
             ? make_range(operands_begin() + 2, operands_end())
             : make_range(operands_begin(), operands_begin() + 1);
}
/// \copydoc debug_operands()
iterator_range<const_mop_iterator> debug_operands() const {
  assert(isDebugValue() && "Must be a debug value instruction.")(static_cast <bool> (isDebugValue() && "Must be a debug value instruction."
) ? void (0) : __assert_fail ("isDebugValue() && \"Must be a debug value instruction.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 637, __extension__ __PRETTY_FUNCTION__));
  return isDebugValueList()
             ? make_range(operands_begin() + 2, operands_end())
             : make_range(operands_begin(), operands_begin() + 1);
}
/// Returns a range over all explicit operands that are register definitions.
/// Implicit definition are not included!
iterator_range<mop_iterator> defs() {
  return make_range(operands_begin(),
                    operands_begin() + getNumExplicitDefs());
}
/// \copydoc defs()
iterator_range<const_mop_iterator> defs() const {
  return make_range(operands_begin(),
                    operands_begin() + getNumExplicitDefs());
}
/// Returns a range that includes all operands that are register uses.
/// This may include unrelated operands which are not register uses.
iterator_range<mop_iterator> uses() {
  return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
}
/// \copydoc uses()
iterator_range<const_mop_iterator> uses() const {
  return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
}
iterator_range<mop_iterator> explicit_uses() {
  return make_range(operands_begin() + getNumExplicitDefs(),
                    operands_begin() + getNumExplicitOperands());
}
iterator_range<const_mop_iterator> explicit_uses() const {
  return make_range(operands_begin() + getNumExplicitDefs(),
                    operands_begin() + getNumExplicitOperands());
}

/// Returns the number of the operand iterator \p I points to.
unsigned getOperandNo(const_mop_iterator I) const {
  return I - operands_begin();
}

/// Access to memory operands of the instruction. If there are none, that does
/// not imply anything about whether the function accesses memory. Instead,
/// the caller must behave conservatively.
ArrayRef<MachineMemOperand *> memoperands() const {
  if (!Info)
    return {};

  if (Info.is<EIIK_MMO>())
    return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);

  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
    return EI->getMMOs();

  return {};
}

/// Access to memory operands of the instruction.
///
/// If `memoperands_begin() == memoperands_end()`, that does not imply
/// anything about whether the function accesses memory. Instead, the caller
/// must behave conservatively.
mmo_iterator memoperands_begin() const { return memoperands().begin(); }

/// Access to memory operands of the instruction.
///
/// If `memoperands_begin() == memoperands_end()`, that does not imply
/// anything about whether the function accesses memory. Instead, the caller
/// must behave conservatively.
mmo_iterator memoperands_end() const { return memoperands().end(); }

/// Return true if we don't have any memory operands which described the
/// memory access done by this instruction.  If this is true, calling code
/// must be conservative.
bool memoperands_empty() const { return memoperands().empty(); }

/// Return true if this instruction has exactly one MachineMemOperand.
bool hasOneMemOperand() const { return memoperands().size() == 1; }

/// Return the number of memory operands.
unsigned getNumMemOperands() const { return memoperands().size(); }

/// Helper to extract a pre-instruction symbol if one has been added.
MCSymbol *getPreInstrSymbol() const {
  if (!Info)
    return nullptr;
  if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
    return S;
  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
    return EI->getPreInstrSymbol();

  return nullptr;
}

/// Helper to extract a post-instruction symbol if one has been added.
MCSymbol *getPostInstrSymbol() const {
  if (!Info)
    return nullptr;
  if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
    return S;
  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
    return EI->getPostInstrSymbol();

  return nullptr;
}

/// Helper to extract a heap alloc marker if one has been added.
MDNode *getHeapAllocMarker() const {
  if (!Info)
    return nullptr;
  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
    return EI->getHeapAllocMarker();

  return nullptr;
}

/// API for querying MachineInstr properties. They are the same as MCInstrDesc
/// queries but they are bundle aware.

enum QueryType {
  IgnoreBundle,    // Ignore bundles
  AnyInBundle,     // Return true if any instruction in bundle has property
  AllInBundle      // Return true if all instructions in bundle have property
};

/// Return true if the instruction (or in the case of a bundle,
/// the instructions inside the bundle) has the specified property.
/// The first argument is the property being queried.
/// The second argument indicates whether the query should look inside
/// instruction bundles.
bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
  assert(MCFlag < 64 &&(static_cast <bool> (MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."
) ? void (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 767, __extension__ __PRETTY_FUNCTION__))
99
←
'?' condition is true→
         "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.")(static_cast <bool> (MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."
) ? void (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 767, __extension__ __PRETTY_FUNCTION__));
  // Inline the fast path for unbundled or bundle-internal instructions.
  if (Type99.1
'Type' is not equal to IgnoreBundle
1
'Type' is not equal to IgnoreBundle
1
'Type' is not equal to IgnoreBundle
1
'Type' is not equal to IgnoreBundle
 == IgnoreBundle || !isBundled() || isBundledWithPred())
100
←
Taking true branch→
    return getDesc().getFlags() & (1ULL << MCFlag);
101
←
Returning value, which participates in a condition later→

  // If this is the first instruction in a bundle, take the slow path.
  return hasPropertyInBundle(1ULL << MCFlag, Type);
}

/// Return true if this is an instruction that should go through the usual
/// legalization steps.
bool isPreISelOpcode(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::PreISelOpcode, Type);
}

/// Return true if this instruction can have a variable number of operands.
/// In this case, the variable operands will be after the normal
/// operands but before the implicit definitions and uses (if any are
/// present).
bool isVariadic(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Variadic, Type);
}

/// Set if this instruction has an optional definition, e.g.
/// ARM instructions which can set condition code if 's' bit is set.
bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::HasOptionalDef, Type);
}

/// Return true if this is a pseudo instruction that doesn't
/// correspond to a real machine instruction.
bool isPseudo(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Pseudo, Type);
}

bool isReturn(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::Return, Type);
}

/// Return true if this is an instruction that marks the end of an EH scope,
/// i.e., a catchpad or a cleanuppad instruction.
bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::EHScopeReturn, Type);
}

bool isCall(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::Call, Type);
}

/// Return true if this is a call instruction that may have an associated
/// call site entry in the debug info.
bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const;
/// Return true if copying, moving, or erasing this instruction requires
/// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
/// \ref eraseCallSiteInfo).
bool shouldUpdateCallSiteInfo() const;

/// Returns true if the specified instruction stops control flow
/// from executing the instruction immediately following it.  Examples include
/// unconditional branches and return instructions.
bool isBarrier(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::Barrier, Type);
}

/// Returns true if this instruction part of the terminator for a basic block.
/// Typically this is things like return and branch instructions.
///
/// Various passes use this to insert code into the bottom of a basic block,
/// but before control flow occurs.
bool isTerminator(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::Terminator, Type);
}

/// Returns true if this is a conditional, unconditional, or indirect branch.
/// Predicates below can be used to discriminate between
/// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
/// get more information.
bool isBranch(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::Branch, Type);
98
←
Calling 'MachineInstr::hasProperty'→
102
←
Returning from 'MachineInstr::hasProperty'→
103
←
Returning value, which participates in a condition later→
}

/// Return true if this is an indirect branch, such as a
/// branch through a register.
bool isIndirectBranch(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::IndirectBranch, Type);
}

/// Return true if this is a branch which may fall
/// through to the next instruction or may transfer control flow to some other
/// block.  The TargetInstrInfo::analyzeBranch method can be used to get more
/// information about this branch.
bool isConditionalBranch(QueryType Type = AnyInBundle) const {
  return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
}

/// Return true if this is a branch which always
/// transfers control flow to some other block.  The
/// TargetInstrInfo::analyzeBranch method can be used to get more information
/// about this branch.
bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
  return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
}

/// Return true if this instruction has a predicate operand that
/// controls execution.  It may be set to 'always', or may be set to other
/// values.   There are various methods in TargetInstrInfo that can be used to
/// control and modify the predicate in this instruction.
bool isPredicable(QueryType Type = AllInBundle) const {
  // If it's a bundle than all bundled instructions must be predicable for this
  // to return true.
  return hasProperty(MCID::Predicable, Type);
}

/// Return true if this instruction is a comparison.
bool isCompare(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Compare, Type);
}

/// Return true if this instruction is a move immediate
/// (including conditional moves) instruction.
bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::MoveImm, Type);
}

/// Return true if this instruction is a register move.
/// (including moving values from subreg to reg)
bool isMoveReg(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::MoveReg, Type);
}

/// Return true if this instruction is a bitcast instruction.
bool isBitcast(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Bitcast, Type);
}

/// Return true if this instruction is a select instruction.
bool isSelect(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Select, Type);
}

/// Return true if this instruction cannot be safely duplicated.
/// For example, if the instruction has a unique labels attached
/// to it, duplicating it would cause multiple definition errors.
bool isNotDuplicable(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::NotDuplicable, Type);
}

/// Return true if this instruction is convergent.
/// Convergent instructions can not be made control-dependent on any
/// additional values.
bool isConvergent(QueryType Type = AnyInBundle) const {
  if (isInlineAsm()) {
    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    if (ExtraInfo & InlineAsm::Extra_IsConvergent)
      return true;
  }
  return hasProperty(MCID::Convergent, Type);
}

/// Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator.
bool hasDelaySlot(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::DelaySlot, Type);
}

/// Return true for instructions that can be folded as
/// memory operands in other instructions. The most common use for this
/// is instructions that are simple loads from memory that don't modify
/// the loaded value in any way, but it can also be used for instructions
/// that can be expressed as constant-pool loads, such as V_SETALLONES
/// on x86, to allow them to be folded when it is beneficial.
/// This should only be set on instructions that return a value in their
/// only virtual register definition.
bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::FoldableAsLoad, Type);
}

/// Return true if this instruction behaves
/// the same way as the generic REG_SEQUENCE instructions.
/// E.g., on ARM,
/// dX VMOVDRR rY, rZ
/// is equivalent to
/// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
///
/// Note that for the optimizers to be able to take advantage of
/// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
/// override accordingly.
bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::RegSequence, Type);
}

/// Return true if this instruction behaves
/// the same way as the generic EXTRACT_SUBREG instructions.
/// E.g., on ARM,
/// rX, rY VMOVRRD dZ
/// is equivalent to two EXTRACT_SUBREG:
/// rX = EXTRACT_SUBREG dZ, ssub_0
/// rY = EXTRACT_SUBREG dZ, ssub_1
///
/// Note that for the optimizers to be able to take advantage of
/// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
/// override accordingly.
bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::ExtractSubreg, Type);
}

/// Return true if this instruction behaves
/// the same way as the generic INSERT_SUBREG instructions.
/// E.g., on ARM,
/// dX = VSETLNi32 dY, rZ, Imm
/// is equivalent to a INSERT_SUBREG:
/// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
///
/// Note that for the optimizers to be able to take advantage of
/// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
/// override accordingly.
bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::InsertSubreg, Type);
}

//===--------------------------------------------------------------------===//
// Side Effect Analysis
//===--------------------------------------------------------------------===//

/// Return true if this instruction could possibly read memory.
/// Instructions with this flag set are not necessarily simple load
/// instructions, they may load a value and modify it, for example.
bool mayLoad(QueryType Type = AnyInBundle) const {
  if (isInlineAsm()) {
    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    if (ExtraInfo & InlineAsm::Extra_MayLoad)
      return true;
  }
  return hasProperty(MCID::MayLoad, Type);
}

/// Return true if this instruction could possibly modify memory.
/// Instructions with this flag set are not necessarily simple store
/// instructions, they may store a modified value based on their operands, or
/// may not actually modify anything, for example.
bool mayStore(QueryType Type = AnyInBundle) const {
  if (isInlineAsm()) {
    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    if (ExtraInfo & InlineAsm::Extra_MayStore)
      return true;
  }
  return hasProperty(MCID::MayStore, Type);
}

/// Return true if this instruction could possibly read or modify memory.
bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
  return mayLoad(Type) || mayStore(Type);
}

/// Return true if this instruction could possibly raise a floating-point
/// exception.  This is the case if the instruction is a floating-point
/// instruction that can in principle raise an exception, as indicated
/// by the MCID::MayRaiseFPException property, *and* at the same time,
/// the instruction is used in a context where we expect floating-point
/// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
bool mayRaiseFPException() const {
  return hasProperty(MCID::MayRaiseFPException) &&
         !getFlag(MachineInstr::MIFlag::NoFPExcept);
}

//===--------------------------------------------------------------------===//
// Flags that indicate whether an instruction can be modified by a method.
//===--------------------------------------------------------------------===//

/// Return true if this may be a 2- or 3-address
/// instruction (of the form "X = op Y, Z, ..."), which produces the same
/// result if Y and Z are exchanged.  If this flag is set, then the
/// TargetInstrInfo::commuteInstruction method may be used to hack on the
/// instruction.
///
/// Note that this flag may be set on instructions that are only commutable
/// sometimes.  In these cases, the call to commuteInstruction will fail.
/// Also note that some instructions require non-trivial modification to
/// commute them.
bool isCommutable(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Commutable, Type);
}

/// Return true if this is a 2-address instruction
/// which can be changed into a 3-address instruction if needed.  Doing this
/// transformation can be profitable in the register allocator, because it
/// means that the instruction can use a 2-address form if possible, but
/// degrade into a less efficient form if the source and dest register cannot
/// be assigned to the same register.  For example, this allows the x86
/// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
/// is the same speed as the shift but has bigger code size.
///
/// If this returns true, then the target must implement the
/// TargetInstrInfo::convertToThreeAddress method for this instruction, which
/// is allowed to fail if the transformation isn't valid for this specific
/// instruction (e.g. shl reg, 4 on x86).
///
bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::ConvertibleTo3Addr, Type);
}

/// Return true if this instruction requires
/// custom insertion support when the DAG scheduler is inserting it into a
/// machine basic block.  If this is true for the instruction, it basically
/// means that it is a pseudo instruction used at SelectionDAG time that is
/// expanded out into magic code by the target when MachineInstrs are formed.
///
/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
/// is used to insert this into the MachineBasicBlock.
bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::UsesCustomInserter, Type);
}

/// Return true if this instruction requires *adjustment*
/// after instruction selection by calling a target hook. For example, this
/// can be used to fill in ARM 's' optional operand depending on whether
/// the conditional flag register is used.
bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::HasPostISelHook, Type);
}

/// Returns true if this instruction is a candidate for remat.
/// This flag is deprecated, please don't use it anymore.  If this
/// flag is set, the isReallyTriviallyReMaterializable() method is called to
/// verify the instruction is really rematable.
bool isRematerializable(QueryType Type = AllInBundle) const {
  // It's only possible to re-mat a bundle if all bundled instructions are
  // re-materializable.
  return hasProperty(MCID::Rematerializable, Type);
}

/// Returns true if this instruction has the same cost (or less) than a move
/// instruction. This is useful during certain types of optimizations
/// (e.g., remat during two-address conversion or machine licm)
/// where we would like to remat or hoist the instruction, but not if it costs
/// more than moving the instruction into the appropriate register. Note, we
/// are not marking copies from and to the same register class with this flag.
bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
  // Only returns true for a bundle if all bundled instructions are cheap.
  return hasProperty(MCID::CheapAsAMove, Type);
}

/// Returns true if this instruction source operands
/// have special register allocation requirements that are not captured by the
/// operand register classes. e.g. ARM::STRD's two source registers must be an
/// even / odd pair, ARM::STM registers have to be in ascending order.
/// Post-register allocation passes should not attempt to change allocations
/// for sources of instructions with this flag.
bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
}

/// Returns true if this instruction def operands
/// have special register allocation requirements that are not captured by the
/// operand register classes. e.g. ARM::LDRD's two def registers must be an
/// even / odd pair, ARM::LDM registers have to be in ascending order.
/// Post-register allocation passes should not attempt to change allocations
/// for definitions of instructions with this flag.
bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::ExtraDefRegAllocReq, Type);
}

enum MICheckType {
  CheckDefs,      // Check all operands for equality
  CheckKillDead,  // Check all operands including kill / dead markers
  IgnoreDefs,     // Ignore all definitions
  IgnoreVRegDefs  // Ignore virtual register definitions
};

/// Return true if this instruction is identical to \p Other.
/// Two instructions are identical if they have the same opcode and all their
/// operands are identical (with respect to MachineOperand::isIdenticalTo()).
/// Note that this means liveness related flags (dead, undef, kill) do not
/// affect the notion of identical.
bool isIdenticalTo(const MachineInstr &Other,
                   MICheckType Check = CheckDefs) const;

/// Unlink 'this' from the containing basic block, and return it without
/// deleting it.
///
/// This function can not be used on bundled instructions, use
/// removeFromBundle() to remove individual instructions from a bundle.
MachineInstr *removeFromParent();

/// Unlink this instruction from its basic block and return it without
/// deleting it.
///
/// If the instruction is part of a bundle, the other instructions in the
/// bundle remain bundled.
MachineInstr *removeFromBundle();

/// Unlink 'this' from the containing basic block and delete it.
///
/// If this instruction is the header of a bundle, the whole bundle is erased.
/// This function can not be used for instructions inside a bundle, use
/// eraseFromBundle() to erase individual bundled instructions.
void eraseFromParent();

/// Unlink 'this' from the containing basic block and delete it.
///
/// For all definitions mark their uses in DBG_VALUE nodes
/// as undefined. Otherwise like eraseFromParent().
void eraseFromParentAndMarkDBGValuesForRemoval();

/// Unlink 'this' form its basic block and delete it.
///
/// If the instruction is part of a bundle, the other instructions in the
/// bundle remain bundled.
void eraseFromBundle();

bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
bool isAnnotationLabel() const {
  return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
}

/// Returns true if the MachineInstr represents a label.
bool isLabel() const {
  return isEHLabel() || isGCLabel() || isAnnotationLabel();
}

bool isCFIInstruction() const {
  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
}

bool isPseudoProbe() const {
  return getOpcode() == TargetOpcode::PSEUDO_PROBE;
}

// True if the instruction represents a position in the function.
bool isPosition() const { return isLabel() || isCFIInstruction(); }

bool isNonListDebugValue() const {
  return getOpcode() == TargetOpcode::DBG_VALUE;
}
bool isDebugValueList() const {
  return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
}
bool isDebugValue() const {
  return isNonListDebugValue() || isDebugValueList();
}
bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
bool isDebugInstr() const {
  return isDebugValue() || isDebugLabel() || isDebugRef();
}
bool isDebugOrPseudoInstr() const {
  return isDebugInstr() || isPseudoProbe();
}

bool isDebugOffsetImm() const {
  return isNonListDebugValue() && getDebugOffset().isImm();
}

/// A DBG_VALUE is indirect iff the location operand is a register and
/// the offset operand is an immediate.
bool isIndirectDebugValue() const {
  return isDebugOffsetImm() && getDebugOperand(0).isReg();
}

/// A DBG_VALUE is an entry value iff its debug expression contains the
/// DW_OP_LLVM_entry_value operation.
bool isDebugEntryValue() const;

/// Return true if the instruction is a debug value which describes a part of
/// a variable as unavailable.
bool isUndefDebugValue() const {
  if (!isDebugValue())
    return false;
  // If any $noreg locations are given, this DV is undef.
  for (const MachineOperand &Op : debug_operands())
    if (Op.isReg() && !Op.getReg().isValid())
      return true;
  return false;
}

bool isPHI() const {
  return getOpcode() == TargetOpcode::PHI ||
         getOpcode() == TargetOpcode::G_PHI;
}
bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
bool isInlineAsm() const {
  return getOpcode() == TargetOpcode::INLINEASM ||
         getOpcode() == TargetOpcode::INLINEASM_BR;
}

/// FIXME: Seems like a layering violation that the AsmDialect, which is X86
/// specific, be attached to a generic MachineInstr.
bool isMSInlineAsm() const {
  return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
}

bool isStackAligningInlineAsm() const;
InlineAsm::AsmDialect getInlineAsmDialect() const;

bool isInsertSubreg() const {
  return getOpcode() == TargetOpcode::INSERT_SUBREG;
}

bool isSubregToReg() const {
  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
}

bool isRegSequence() const {
  return getOpcode() == TargetOpcode::REG_SEQUENCE;
}

bool isBundle() const {
  return getOpcode() == TargetOpcode::BUNDLE;
}

bool isCopy() const {
  return getOpcode() == TargetOpcode::COPY;
}

bool isFullCopy() const {
  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
}

bool isExtractSubreg() const {
  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
}

/// Return true if the instruction behaves like a copy.
/// This does not include native copy instructions.
bool isCopyLike() const {
  return isCopy() || isSubregToReg();
}

/// Return true is the instruction is an identity copy.
bool isIdentityCopy() const {
  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
    getOperand(0).getSubReg() == getOperand(1).getSubReg();
}

/// Return true if this instruction doesn't produce any output in the form of
/// executable instructions.
bool isMetaInstruction() const {
  switch (getOpcode()) {
  default:
    return false;
  case TargetOpcode::IMPLICIT_DEF:
  case TargetOpcode::KILL:
  case TargetOpcode::CFI_INSTRUCTION:
  case TargetOpcode::EH_LABEL:
  case TargetOpcode::GC_LABEL:
  case TargetOpcode::DBG_VALUE:
  case TargetOpcode::DBG_VALUE_LIST:
  case TargetOpcode::DBG_INSTR_REF:
  case TargetOpcode::DBG_LABEL:
  case TargetOpcode::LIFETIME_START:
  case TargetOpcode::LIFETIME_END:
  case TargetOpcode::PSEUDO_PROBE:
    return true;
  }
}

/// Return true if this is a transient instruction that is either very likely
/// to be eliminated during register allocation (such as copy-like
/// instructions), or if this instruction doesn't have an execution-time cost.
bool isTransient() const {
  switch (getOpcode()) {
  default:
    return isMetaInstruction();
  // Copy-like instructions are usually eliminated during register allocation.
  case TargetOpcode::PHI:
  case TargetOpcode::G_PHI:
  case TargetOpcode::COPY:
  case TargetOpcode::INSERT_SUBREG:
  case TargetOpcode::SUBREG_TO_REG:
  case TargetOpcode::REG_SEQUENCE:
    return true;
  }
}

/// Return the number of instructions inside the MI bundle, excluding the
/// bundle header.
///
/// This is the number of instructions that MachineBasicBlock::iterator
/// skips, 0 for unbundled instructions.
unsigned getBundleSize() const;

/// Return true if the MachineInstr reads the specified register.
/// If TargetRegisterInfo is passed, then it also checks if there
/// is a read of a super-register.
/// This does not count partial redefines of virtual registers as reads:
///   %reg1024:6 = OP.
bool readsRegister(Register Reg,
                   const TargetRegisterInfo *TRI = nullptr) const {
  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
}

/// Return true if the MachineInstr reads the specified virtual register.
/// Take into account that a partial define is a
/// read-modify-write operation.
bool readsVirtualRegister(Register Reg) const {
  return readsWritesVirtualRegister(Reg).first;
}

/// Return a pair of bools (reads, writes) indicating if this instruction
/// reads or writes Reg. This also considers partial defines.
/// If Ops is not null, all operand indices for Reg are added.
std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
                              SmallVectorImpl<unsigned> *Ops = nullptr) const;

/// Return true if the MachineInstr kills the specified register.
/// If TargetRegisterInfo is passed, then it also checks if there is
/// a kill of a super-register.
bool killsRegister(Register Reg,
                   const TargetRegisterInfo *TRI = nullptr) const {
  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
}

/// Return true if the MachineInstr fully defines the specified register.
/// If TargetRegisterInfo is passed, then it also checks
/// if there is a def of a super-register.
/// NOTE: It's ignoring subreg indices on virtual registers.
bool definesRegister(Register Reg,
                     const TargetRegisterInfo *TRI = nullptr) const {
  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
}

/// Return true if the MachineInstr modifies (fully define or partially
/// define) the specified register.
/// NOTE: It's ignoring subreg indices on virtual registers.
bool modifiesRegister(Register Reg,
                      const TargetRegisterInfo *TRI = nullptr) const {
  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
}

/// Returns true if the register is dead in this machine instruction.
/// If TargetRegisterInfo is passed, then it also checks
/// if there is a dead def of a super-register.
bool registerDefIsDead(Register Reg,
                       const TargetRegisterInfo *TRI = nullptr) const {
  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
}

/// Returns true if the MachineInstr has an implicit-use operand of exactly
/// the given register (not considering sub/super-registers).
bool hasRegisterImplicitUseOperand(Register Reg) const;

/// Returns the operand index that is a use of the specific register or -1
/// if it is not found. It further tightens the search criteria to a use
/// that kills the register if isKill is true.
int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
                              const TargetRegisterInfo *TRI = nullptr) const;

/// Wrapper for findRegisterUseOperandIdx, it returns
/// a pointer to the MachineOperand rather than an index.
MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
                                    const TargetRegisterInfo *TRI = nullptr) {
  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
  return (Idx == -1) ? nullptr : &getOperand(Idx);
}

const MachineOperand *findRegisterUseOperand(
  Register Reg, bool isKill = false,
  const TargetRegisterInfo *TRI = nullptr) const {
  return const_cast<MachineInstr *>(this)->
    findRegisterUseOperand(Reg, isKill, TRI);
}

/// Returns the operand index that is a def of the specified register or
/// -1 if it is not found. If isDead is true, defs that are not dead are
/// skipped. If Overlap is true, then it also looks for defs that merely
/// overlap the specified register. If TargetRegisterInfo is non-null,
/// then it also checks if there is a def of a super-register.
/// This may also return a register mask operand when Overlap is true.
int findRegisterDefOperandIdx(Register Reg,
                              bool isDead = false, bool Overlap = false,
                              const TargetRegisterInfo *TRI = nullptr) const;

/// Wrapper for findRegisterDefOperandIdx, it returns
/// a pointer to the MachineOperand rather than an index.
MachineOperand *
findRegisterDefOperand(Register Reg, bool isDead = false,
                       bool Overlap = false,
                       const TargetRegisterInfo *TRI = nullptr) {
  int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
  return (Idx == -1) ? nullptr : &getOperand(Idx);
}

const MachineOperand *
findRegisterDefOperand(Register Reg, bool isDead = false,
                       bool Overlap = false,
                       const TargetRegisterInfo *TRI = nullptr) const {
  return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
      Reg, isDead, Overlap, TRI);
}

/// Find the index of the first operand in the
/// operand list that is used to represent the predicate. It returns -1 if
/// none is found.
int findFirstPredOperandIdx() const;

/// Find the index of the flag word operand that
/// corresponds to operand OpIdx on an inline asm instruction.  Returns -1 if
/// getOperand(OpIdx) does not belong to an inline asm operand group.
///
/// If GroupNo is not NULL, it will receive the number of the operand group
/// containing OpIdx.
///
/// The flag operand is an immediate that can be decoded with methods like
/// InlineAsm::hasRegClassConstraint().
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;

/// Compute the static register class constraint for operand OpIdx.
/// For normal instructions, this is derived from the MCInstrDesc.
/// For inline assembly it is derived from the flag words.
///
/// Returns NULL if the static register class constraint cannot be
/// determined.
const TargetRegisterClass*
getRegClassConstraint(unsigned OpIdx,
                      const TargetInstrInfo *TII,
                      const TargetRegisterInfo *TRI) const;

/// Applies the constraints (def/use) implied by this MI on \p Reg to
/// the given \p CurRC.
/// If \p ExploreBundle is set and MI is part of a bundle, all the
/// instructions inside the bundle will be taken into account. In other words,
/// this method accumulates all the constraints of the operand of this MI and
/// the related bundle if MI is a bundle or inside a bundle.
///
/// Returns the register class that satisfies both \p CurRC and the
/// constraints set by MI. Returns NULL if such a register class does not
/// exist.
///
/// \pre CurRC must not be NULL.
const TargetRegisterClass *getRegClassConstraintEffectForVReg(
    Register Reg, const TargetRegisterClass *CurRC,
    const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
    bool ExploreBundle = false) const;

/// Applies the constraints (def/use) implied by the \p OpIdx operand
/// to the given \p CurRC.
///
/// Returns the register class that satisfies both \p CurRC and the
/// constraints set by \p OpIdx MI. Returns NULL if such a register class
/// does not exist.
///
/// \pre CurRC must not be NULL.
/// \pre The operand at \p OpIdx must be a register.
const TargetRegisterClass *
getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
                            const TargetInstrInfo *TII,
                            const TargetRegisterInfo *TRI) const;

/// Add a tie between the register operands at DefIdx and UseIdx.
/// The tie will cause the register allocator to ensure that the two
/// operands are assigned the same physical register.
///
/// Tied operands are managed automatically for explicit operands in the
/// MCInstrDesc. This method is for exceptional cases like inline asm.
void tieOperands(unsigned DefIdx, unsigned UseIdx);

/// Given the index of a tied register operand, find the
/// operand it is tied to. Defs are tied to uses and vice versa. Returns the
/// index of the tied operand which must exist.
unsigned findTiedOperandIdx(unsigned OpIdx) const;

/// Given the index of a register def operand,
/// check if the register def is tied to a source operand, due to either
/// two-address elimination or inline assembly constraints. Returns the
/// first tied use operand index by reference if UseOpIdx is not null.
bool isRegTiedToUseOperand(unsigned DefOpIdx,
                           unsigned *UseOpIdx = nullptr) const {
  const MachineOperand &MO = getOperand(DefOpIdx);
  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
    return false;
  if (UseOpIdx)
    *UseOpIdx = findTiedOperandIdx(DefOpIdx);
  return true;
}

/// Return true if the use operand of the specified index is tied to a def
/// operand. It also returns the def operand index by reference if DefOpIdx
/// is not null.
bool isRegTiedToDefOperand(unsigned UseOpIdx,
                           unsigned *DefOpIdx = nullptr) const {
  const MachineOperand &MO = getOperand(UseOpIdx);
  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
    return false;
  if (DefOpIdx)
    *DefOpIdx = findTiedOperandIdx(UseOpIdx);
  return true;
}

/// Clears kill flags on all operands.
void clearKillInfo();

/// Replace all occurrences of FromReg with ToReg:SubIdx,
/// properly composing subreg indices where necessary.
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
                        const TargetRegisterInfo &RegInfo);

/// We have determined MI kills a register. Look for the
/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
/// add a implicit operand if it's not found. Returns true if the operand
/// exists / is added.
bool addRegisterKilled(Register IncomingReg,
                       const TargetRegisterInfo *RegInfo,
                       bool AddIfNotFound = false);

/// Clear all kill flags affecting Reg.  If RegInfo is provided, this includes
/// all aliasing registers.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);

/// We have determined MI defined a register without a use.
/// Look for the operand that defines it and mark it as IsDead. If
/// AddIfNotFound is true, add a implicit operand if it's not found. Returns
/// true if the operand exists / is added.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
                     bool AddIfNotFound = false);

/// Clear all dead flags on operands defining register @p Reg.
void clearRegisterDeads(Register Reg);

/// Mark all subregister defs of register @p Reg with the undef flag.
/// This function is used when we determined to have a subregister def in an
/// otherwise undefined super register.
void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);

/// We have determined MI defines a register. Make sure there is an operand
/// defining Reg.
void addRegisterDefined(Register Reg,
                        const TargetRegisterInfo *RegInfo = nullptr);

/// Mark every physreg used by this instruction as
/// dead except those in the UsedRegs list.
///
/// On instructions with register mask operands, also add implicit-def
/// operands for all registers in UsedRegs.
void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
                           const TargetRegisterInfo &TRI);

/// Return true if it is safe to move this instruction. If
/// SawStore is set to true, it means that there is a store (or call) between
/// the instruction's location and its intended destination.
bool isSafeToMove(AAResults *AA, bool &SawStore) const;

/// Returns true if this instruction's memory access aliases the memory
/// access of Other.
//
/// Assumes any physical registers used to compute addresses
/// have the same value for both instructions.  Returns false if neither
/// instruction writes to memory.
///
/// @param AA Optional alias analysis, used to compare memory operands.
/// @param Other MachineInstr to check aliasing against.
/// @param UseTBAA Whether to pass TBAA information to alias analysis.
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;

/// Return true if this instruction may have an ordered
/// or volatile memory reference, or if the information describing the memory
/// reference is not available. Return false if it is known to have no
/// ordered or volatile memory references.
bool hasOrderedMemoryRef() const;

/// Return true if this load instruction never traps and points to a memory
/// location whose value doesn't change during the execution of this function.
///
/// Examples include loading a value from the constant pool or from the
/// argument area of a function (if it does not change).  If the instruction
/// does multiple loads, this returns true only if all of the loads are
/// dereferenceable and invariant.
bool isDereferenceableInvariantLoad(AAResults *AA) const;

/// If the specified instruction is a PHI that always merges together the
/// same virtual register, return the register, otherwise return 0.
unsigned isConstantValuePHI() const;

/// Return true if this instruction has side effects that are not modeled
/// by mayLoad / mayStore, etc.
/// For all instructions, the property is encoded in MCInstrDesc::Flags
/// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
/// INLINEASM instruction, in which case the side effect property is encoded
/// in one of its operands (see InlineAsm::Extra_HasSideEffect).
///
bool hasUnmodeledSideEffects() const;

/// Returns true if it is illegal to fold a load across this instruction.
bool isLoadFoldBarrier() const;

/// Return true if all the defs of this instruction are dead.
bool allDefsAreDead() const;

/// Return a valid size if the instruction is a spill instruction.
Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;

/// Return a valid size if the instruction is a folded spill instruction.
Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;

/// Return a valid size if the instruction is a restore instruction.
Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;

/// Return a valid size if the instruction is a folded restore instruction.
Optional<unsigned>
getFoldedRestoreSize(const TargetInstrInfo *TII) const;

/// Copy implicit register operands from specified
/// instruction to this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);

/// Debugging support
/// @{
/// Determine the generic type to be printed (if needed) on uses and defs.
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
                   const MachineRegisterInfo &MRI) const;

/// Return true when an instruction has tied register that can't be determined
/// by the instruction's descriptor. This is useful for MIR printing, to
/// determine whether we need to print the ties or not.
bool hasComplexRegisterTies() const;

/// Print this MI to \p OS.
/// Don't print information that can be inferred from other instructions if
/// \p IsStandalone is false. It is usually true when only a fragment of the
/// function is printed.
/// Only print the defs and the opcode if \p SkipOpers is true.
/// Otherwise, also print operands if \p SkipDebugLoc is true.
/// Otherwise, also print the debug loc, with a terminating newline.
/// \p TII is used to print the opcode name.  If it's not present, but the
/// MI is in a function, the opcode will be printed using the function's TII.
void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
           bool SkipDebugLoc = false, bool AddNewLine = true,
           const TargetInstrInfo *TII = nullptr) const;
void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
           bool SkipOpers = false, bool SkipDebugLoc = false,
           bool AddNewLine = true,
           const TargetInstrInfo *TII = nullptr) const;
void dump() const;
/// Print on dbgs() the current instruction and the instructions defining its
/// operands and so on until we reach \p MaxDepth.
void dumpr(const MachineRegisterInfo &MRI,
           unsigned MaxDepth = UINT_MAX(2147483647 *2U +1U)) const;
/// @}

//===--------------------------------------------------------------------===//
// Accessors used to build up machine instructions.

/// Add the specified operand to the instruction.  If it is an implicit
/// operand, it is added to the end of the operand list.  If it is an
/// explicit operand it is added at the end of the explicit operand list
/// (before the first implicit operand).
///
/// MF must be the machine function that was used to allocate this
/// instruction.
///
/// MachineInstrBuilder provides a more convenient interface for creating
/// instructions and adding operands.
void addOperand(MachineFunction &MF, const MachineOperand &Op);

/// Add an operand without providing an MF reference. This only works for
/// instructions that are inserted in a basic block.
///
/// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
/// preferred.
void addOperand(const MachineOperand &Op);

/// Replace the instruction descriptor (thus opcode) of
/// the current instruction with a new one.
void setDesc(const MCInstrDesc &tid) { MCID = &tid; }

/// Replace current source information with new such.
/// Avoid using this, the constructor argument is preferable.
void setDebugLoc(DebugLoc dl) {
  debugLoc = std::move(dl);
  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (debugLoc.hasTrivialDestructor() &&
 "Expected trivial destructor") ? void (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 1737, __extension__ __PRETTY_FUNCTION__));
}

/// Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with.
void RemoveOperand(unsigned OpNo);

/// Clear this MachineInstr's memory reference descriptor list.  This resets
/// the memrefs to their most conservative state.  This should be used only
/// as a last resort since it greatly pessimizes our knowledge of the memory
/// access performed by the instruction.
void dropMemRefs(MachineFunction &MF);

/// Assign this MachineInstr's memory reference descriptor list.
///
/// Unlike other methods, this *will* allocate them into a new array
/// associated with the provided `MachineFunction`.
void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);

/// Add a MachineMemOperand to the machine instruction.
/// This function should be used only occasionally. The setMemRefs function
/// is the primary method for setting up a MachineInstr's MemRefs list.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);

/// Clone another MachineInstr's memory reference descriptor list and replace
/// ours with it.
///
/// Note that `*this` may be the incoming MI!
///
/// Prefer this API whenever possible as it can avoid allocations in common
/// cases.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);

/// Clone the merge of multiple MachineInstrs' memory reference descriptors
/// list and replace ours with it.
///
/// Note that `*this` may be one of the incoming MIs!
///
/// Prefer this API whenever possible as it can avoid allocations in common
/// cases.
void cloneMergedMemRefs(MachineFunction &MF,
                        ArrayRef<const MachineInstr *> MIs);

/// Set a symbol that will be emitted just prior to the instruction itself.
///
/// Setting this to a null pointer will remove any such symbol.
///
/// FIXME: This is not fully implemented yet.
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);

/// Set a symbol that will be emitted just after the instruction itself.
///
/// Setting this to a null pointer will remove any such symbol.
///
/// FIXME: This is not fully implemented yet.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);

/// Clone another MachineInstr's pre- and post- instruction symbols and
/// replace ours with it.
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);

/// Set a marker on instructions that denotes where we should create and emit
/// heap alloc site labels. This waits until after instruction selection and
/// optimizations to create the label, so it should still work if the
/// instruction is removed or duplicated.
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);

/// Return the MIFlags which represent both MachineInstrs. This
/// should be used when merging two MachineInstrs into one. This routine does
/// not modify the MIFlags of this MachineInstr.
uint16_t mergeFlagsWith(const MachineInstr& Other) const;

static uint16_t copyFlagsFromInstruction(const Instruction &I);

/// Copy all flags to MachineInst MIFlags
void copyIRFlags(const Instruction &I);

/// Break any tie involving OpIdx.
void untieRegOperand(unsigned OpIdx) {
  MachineOperand &MO = getOperand(OpIdx);
  if (MO.isReg() && MO.isTied()) {
    getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
    MO.TiedTo = 0;
  }
}

/// Add all implicit def and use operands to this instruction.
void addImplicitDefUseOperands(MachineFunction &MF);

/// Scan instructions immediately following MI and collect any matching
/// DBG_VALUEs.
void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);

/// Find all DBG_VALUEs that point to the register def in this instruction
/// and point them to \p Reg instead.
void changeDebugValuesDefReg(Register Reg);

/// Returns the Intrinsic::ID for this instruction.
/// \pre Must have an intrinsic ID operand.
unsigned getIntrinsicID() const {
  return getOperand(getNumExplicitDefs()).getIntrinsicID();
}

/// Sets all register debug operands in this debug value instruction to be
/// undef.
void setDebugValueUndef() {
  assert(isDebugValue() && "Must be a debug value instruction.")(static_cast <bool> (isDebugValue() && "Must be a debug value instruction."
) ? void (0) : __assert_fail ("isDebugValue() && \"Must be a debug value instruction.\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 1843, __extension__ __PRETTY_FUNCTION__));
  for (MachineOperand &MO : debug_operands()) {
    if (MO.isReg()) {
      MO.setReg(0);
      MO.setSubReg(0);
    }
  }
}

PseudoProbeAttributes getPseudoProbeAttribute() const {
  assert(isPseudoProbe() && "Must be a pseudo probe instruction")(static_cast <bool> (isPseudoProbe() && "Must be a pseudo probe instruction"
) ? void (0) : __assert_fail ("isPseudoProbe() && \"Must be a pseudo probe instruction\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 1853, __extension__ __PRETTY_FUNCTION__));
  return (PseudoProbeAttributes)getOperand(3).getImm();
}

void addPseudoProbeAttribute(PseudoProbeAttributes Attr) {
  assert(isPseudoProbe() && "Must be a pseudo probe instruction")(static_cast <bool> (isPseudoProbe() && "Must be a pseudo probe instruction"
) ? void (0) : __assert_fail ("isPseudoProbe() && \"Must be a pseudo probe instruction\""
, "/build/llvm-toolchain-snapshot-13~++20210506100649+6304c0836a4d/llvm/include/llvm/CodeGen/MachineInstr.h"
, 1858, __extension__ __PRETTY_FUNCTION__));
  MachineOperand &AttrOperand = getOperand(3);
  AttrOperand.setImm(AttrOperand.getImm() | (uint32_t)Attr);
}

1863private:
/// If this instruction is embedded into a MachineFunction, return the
/// MachineRegisterInfo object for the current function, otherwise
/// return null.
MachineRegisterInfo *getRegInfo();

/// Unlink all of the register operands in this instruction from their
/// respective use lists.  This requires that the operands already be on their
/// use lists.
void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);

/// Add all of the register operands in this instruction from their
/// respective use lists.  This requires that the operands not be on their
/// use lists yet.
void AddRegOperandsToUseLists(MachineRegisterInfo&);

/// Slow path for hasProperty when we're dealing with a bundle.
bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;

/// Implements the logic of getRegClassConstraintEffectForVReg for the
/// this MI and the given operand index \p OpIdx.
/// If the related operand does not constrained Reg, this returns CurRC.
const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
    unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
    const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;

/// Stores extra instruction information inline or allocates as ExtraInfo
/// based on the number of pointers.
void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
                  MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
                  MDNode *HeapAllocMarker);
1894};

1896/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1897/// instruction rather than by pointer value.
1898/// The hashing and equality testing functions ignore definitions so this is
1899/// useful for CSE, etc.
1900struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
static inline MachineInstr *getEmptyKey() {
  return nullptr;
}

static inline MachineInstr *getTombstoneKey() {
  return reinterpret_cast<MachineInstr*>(-1);
}

static unsigned getHashValue(const MachineInstr* const &MI);

static bool isEqual(const MachineInstr* const &LHS,
                    const MachineInstr* const &RHS) {
  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
      LHS == getEmptyKey() || LHS == getTombstoneKey())
    return LHS == RHS;
  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
}
1918};

1920//===----------------------------------------------------------------------===//
1921// Debugging Support

1923inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
MI.print(OS);
return OS;
1926}

1928} // end namespace llvm

1930#endif // LLVM_CODEGEN_MACHINEINSTR_H