Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1181, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name InstrEmitter.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-11/lib/clang/11.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/include -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-11/lib/clang/11.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-03-09-184146-41876-1 -x c++ /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the Emit routines for the SelectionDAG class, which creates
10// MachineInstrs based on the decisions of the SelectionDAG instruction
11// selection.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrEmitter.h"
16#include "SDNodeDbgValue.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/CodeGen/MachineConstantPool.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/StackMaps.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/CodeGen/TargetLowering.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/IR/DebugInfo.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/MathExtras.h"
31using namespace llvm;
32
33#define DEBUG_TYPE"instr-emitter" "instr-emitter"
34
35/// MinRCSize - Smallest register class we allow when constraining virtual
36/// registers. If satisfying all register class constraints would require
37/// using a smaller register class, emit a COPY to a new virtual register
38/// instead.
39const unsigned MinRCSize = 4;
40
41/// CountResults - The results of target nodes have register or immediate
42/// operands first, then an optional chain, and optional glue operands (which do
43/// not go into the resulting MachineInstr).
44unsigned InstrEmitter::CountResults(SDNode *Node) {
45 unsigned N = Node->getNumValues();
46 while (N && Node->getValueType(N - 1) == MVT::Glue)
47 --N;
48 if (N && Node->getValueType(N - 1) == MVT::Other)
49 --N; // Skip over chain result.
50 return N;
51}
52
53/// countOperands - The inputs to target nodes have any actual inputs first,
54/// followed by an optional chain operand, then an optional glue operand.
55/// Compute the number of actual operands that will go into the resulting
56/// MachineInstr.
57///
58/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
59/// the chain and glue. These operands may be implicit on the machine instr.
60static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
61 unsigned &NumImpUses) {
62 unsigned N = Node->getNumOperands();
63 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
64 --N;
65 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
66 --N; // Ignore chain if it exists.
67
68 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
69 NumImpUses = N - NumExpUses;
70 for (unsigned I = N; I > NumExpUses; --I) {
71 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
72 continue;
73 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
74 if (Register::isPhysicalRegister(RN->getReg()))
75 continue;
76 NumImpUses = N - I;
77 break;
78 }
79
80 return N;
81}
82
83/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
84/// implicit physical register output.
85void InstrEmitter::
86EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
87 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
88 unsigned VRBase = 0;
89 if (Register::isVirtualRegister(SrcReg)) {
90 // Just use the input register directly!
91 SDValue Op(Node, ResNo);
92 if (IsClone)
93 VRBaseMap.erase(Op);
94 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
95 (void)isNew; // Silence compiler warning.
96 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 96, __PRETTY_FUNCTION__))
;
97 return;
98 }
99
100 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101 // the CopyToReg'd destination register instead of creating a new vreg.
102 bool MatchReg = true;
103 const TargetRegisterClass *UseRC = nullptr;
104 MVT VT = Node->getSimpleValueType(ResNo);
105
106 // Stick to the preferred register classes for legal types.
107 if (TLI->isTypeLegal(VT))
108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
109
110 if (!IsClone && !IsCloned)
111 for (SDNode *User : Node->uses()) {
112 bool Match = true;
113 if (User->getOpcode() == ISD::CopyToReg &&
114 User->getOperand(2).getNode() == Node &&
115 User->getOperand(2).getResNo() == ResNo) {
116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117 if (Register::isVirtualRegister(DestReg)) {
118 VRBase = DestReg;
119 Match = false;
120 } else if (DestReg != SrcReg)
121 Match = false;
122 } else {
123 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
124 SDValue Op = User->getOperand(i);
125 if (Op.getNode() != Node || Op.getResNo() != ResNo)
126 continue;
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
129 continue;
130 Match = false;
131 if (User->isMachineOpcode()) {
132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133 const TargetRegisterClass *RC = nullptr;
134 if (i+II.getNumDefs() < II.getNumOperands()) {
135 RC = TRI->getAllocatableClass(
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
137 }
138 if (!UseRC)
139 UseRC = RC;
140 else if (RC) {
141 const TargetRegisterClass *ComRC =
142 TRI->getCommonSubClass(UseRC, RC);
143 // If multiple uses expect disjoint register classes, we emit
144 // copies in AddRegisterOperand.
145 if (ComRC)
146 UseRC = ComRC;
147 }
148 }
149 }
150 }
151 MatchReg &= Match;
152 if (VRBase)
153 break;
154 }
155
156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
158
159 // Figure out the register class to create for the destreg.
160 if (VRBase) {
161 DstRC = MRI->getRegClass(VRBase);
162 } else if (UseRC) {
163 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&((TRI->isTypeLegalForClass(*UseRC, VT) && "Incompatible phys register def and uses!"
) ? static_cast<void> (0) : __assert_fail ("TRI->isTypeLegalForClass(*UseRC, VT) && \"Incompatible phys register def and uses!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 164, __PRETTY_FUNCTION__))
164 "Incompatible phys register def and uses!")((TRI->isTypeLegalForClass(*UseRC, VT) && "Incompatible phys register def and uses!"
) ? static_cast<void> (0) : __assert_fail ("TRI->isTypeLegalForClass(*UseRC, VT) && \"Incompatible phys register def and uses!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 164, __PRETTY_FUNCTION__))
;
165 DstRC = UseRC;
166 } else {
167 DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
168 }
169
170 // If all uses are reading from the src physical register and copying the
171 // register is either impossible or very expensive, then don't create a copy.
172 if (MatchReg && SrcRC->getCopyCost() < 0) {
173 VRBase = SrcReg;
174 } else {
175 // Create the reg, emit the copy.
176 VRBase = MRI->createVirtualRegister(DstRC);
177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178 VRBase).addReg(SrcReg);
179 }
180
181 SDValue Op(Node, ResNo);
182 if (IsClone)
183 VRBaseMap.erase(Op);
184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185 (void)isNew; // Silence compiler warning.
186 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 186, __PRETTY_FUNCTION__))
;
187}
188
189void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
190 MachineInstrBuilder &MIB,
191 const MCInstrDesc &II,
192 bool IsClone, bool IsCloned,
193 DenseMap<SDValue, unsigned> &VRBaseMap) {
194 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&((Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!"
) ? static_cast<void> (0) : __assert_fail ("Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && \"IMPLICIT_DEF should have been handled as a special case elsewhere!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 195, __PRETTY_FUNCTION__))
195 "IMPLICIT_DEF should have been handled as a special case elsewhere!")((Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!"
) ? static_cast<void> (0) : __assert_fail ("Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && \"IMPLICIT_DEF should have been handled as a special case elsewhere!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 195, __PRETTY_FUNCTION__))
;
196
197 unsigned NumResults = CountResults(Node);
198 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
199 II.isVariadic() && II.variadicOpsAreDefs();
200 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs();
201 for (unsigned i = 0; i < NumVRegs; ++i) {
202 // If the specific node value is only used by a CopyToReg and the dest reg
203 // is a vreg in the same register class, use the CopyToReg'd destination
204 // register instead of creating a new vreg.
205 unsigned VRBase = 0;
206 const TargetRegisterClass *RC =
207 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
208 // Always let the value type influence the used register class. The
209 // constraints on the instruction may be too lax to represent the value
210 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
211 // the 32-bit float super-class (X86::FR32).
212 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
213 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
214 Node->getSimpleValueType(i),
215 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
216 if (RC)
217 VTRC = TRI->getCommonSubClass(RC, VTRC);
218 if (VTRC)
219 RC = VTRC;
220 }
221
222 if (II.OpInfo != nullptr && II.OpInfo[i].isOptionalDef()) {
223 // Optional def must be a physical register.
224 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
225 assert(Register::isPhysicalRegister(VRBase))((Register::isPhysicalRegister(VRBase)) ? static_cast<void
> (0) : __assert_fail ("Register::isPhysicalRegister(VRBase)"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 225, __PRETTY_FUNCTION__))
;
226 MIB.addReg(VRBase, RegState::Define);
227 }
228
229 if (!VRBase && !IsClone && !IsCloned)
230 for (SDNode *User : Node->uses()) {
231 if (User->getOpcode() == ISD::CopyToReg &&
232 User->getOperand(2).getNode() == Node &&
233 User->getOperand(2).getResNo() == i) {
234 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
235 if (Register::isVirtualRegister(Reg)) {
236 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
237 if (RegRC == RC) {
238 VRBase = Reg;
239 MIB.addReg(VRBase, RegState::Define);
240 break;
241 }
242 }
243 }
244 }
245
246 // Create the result registers for this node and add the result regs to
247 // the machine instruction.
248 if (VRBase == 0) {
249 assert(RC && "Isn't a register operand!")((RC && "Isn't a register operand!") ? static_cast<
void> (0) : __assert_fail ("RC && \"Isn't a register operand!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 249, __PRETTY_FUNCTION__))
;
250 VRBase = MRI->createVirtualRegister(RC);
251 MIB.addReg(VRBase, RegState::Define);
252 }
253
254 // If this def corresponds to a result of the SDNode insert the VRBase into
255 // the lookup map.
256 if (i < NumResults) {
257 SDValue Op(Node, i);
258 if (IsClone)
259 VRBaseMap.erase(Op);
260 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
261 (void)isNew; // Silence compiler warning.
262 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 262, __PRETTY_FUNCTION__))
;
263 }
264 }
265}
266
267/// getVR - Return the virtual register corresponding to the specified result
268/// of the specified node.
269unsigned InstrEmitter::getVR(SDValue Op,
270 DenseMap<SDValue, unsigned> &VRBaseMap) {
271 if (Op.isMachineOpcode() &&
6
Calling 'SDValue::isMachineOpcode'
272 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
273 // Add an IMPLICIT_DEF instruction before every use.
274 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
275 // does not include operand register class info.
276 const TargetRegisterClass *RC = TLI->getRegClassFor(
277 Op.getSimpleValueType(), Op.getNode()->isDivergent());
278 Register VReg = MRI->createVirtualRegister(RC);
279 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
280 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
281 return VReg;
282 }
283
284 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
285 assert(I != VRBaseMap.end() && "Node emitted out of order - late")((I != VRBaseMap.end() && "Node emitted out of order - late"
) ? static_cast<void> (0) : __assert_fail ("I != VRBaseMap.end() && \"Node emitted out of order - late\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 285, __PRETTY_FUNCTION__))
;
286 return I->second;
287}
288
289
290/// AddRegisterOperand - Add the specified register as an operand to the
291/// specified machine instr. Insert register copies if the register is
292/// not in the required register class.
293void
294InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
295 SDValue Op,
296 unsigned IIOpNum,
297 const MCInstrDesc *II,
298 DenseMap<SDValue, unsigned> &VRBaseMap,
299 bool IsDebug, bool IsClone, bool IsCloned) {
300 assert(Op.getValueType() != MVT::Other &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 302, __PRETTY_FUNCTION__))
301 Op.getValueType() != MVT::Glue &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 302, __PRETTY_FUNCTION__))
302 "Chain and glue operands should occur at end of operand list!")((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 302, __PRETTY_FUNCTION__))
;
303 // Get/emit the operand.
304 unsigned VReg = getVR(Op, VRBaseMap);
305
306 const MCInstrDesc &MCID = MIB->getDesc();
307 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
308 MCID.OpInfo[IIOpNum].isOptionalDef();
309
310 // If the instruction requires a register in a different class, create
311 // a new virtual register and copy the value into it, but first attempt to
312 // shrink VReg's register class within reason. For example, if VReg == GR32
313 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
314 if (II) {
315 const TargetRegisterClass *OpRC = nullptr;
316 if (IIOpNum < II->getNumOperands())
317 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
318
319 if (OpRC) {
320 const TargetRegisterClass *ConstrainedRC
321 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
322 if (!ConstrainedRC) {
323 OpRC = TRI->getAllocatableClass(OpRC);
324 assert(OpRC && "Constraints cannot be fulfilled for allocation")((OpRC && "Constraints cannot be fulfilled for allocation"
) ? static_cast<void> (0) : __assert_fail ("OpRC && \"Constraints cannot be fulfilled for allocation\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 324, __PRETTY_FUNCTION__))
;
325 Register NewVReg = MRI->createVirtualRegister(OpRC);
326 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
327 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
328 VReg = NewVReg;
329 } else {
330 assert(ConstrainedRC->isAllocatable() &&((ConstrainedRC->isAllocatable() && "Constraining an allocatable VReg produced an unallocatable class?"
) ? static_cast<void> (0) : __assert_fail ("ConstrainedRC->isAllocatable() && \"Constraining an allocatable VReg produced an unallocatable class?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 331, __PRETTY_FUNCTION__))
331 "Constraining an allocatable VReg produced an unallocatable class?")((ConstrainedRC->isAllocatable() && "Constraining an allocatable VReg produced an unallocatable class?"
) ? static_cast<void> (0) : __assert_fail ("ConstrainedRC->isAllocatable() && \"Constraining an allocatable VReg produced an unallocatable class?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 331, __PRETTY_FUNCTION__))
;
332 }
333 }
334 }
335
336 // If this value has only one use, that use is a kill. This is a
337 // conservative approximation. InstrEmitter does trivial coalescing
338 // with CopyFromReg nodes, so don't emit kill flags for them.
339 // Avoid kill flags on Schedule cloned nodes, since there will be
340 // multiple uses.
341 // Tied operands are never killed, so we need to check that. And that
342 // means we need to determine the index of the operand.
343 bool isKill = Op.hasOneUse() &&
344 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
345 !IsDebug &&
346 !(IsClone || IsCloned);
347 if (isKill) {
348 unsigned Idx = MIB->getNumOperands();
349 while (Idx > 0 &&
350 MIB->getOperand(Idx-1).isReg() &&
351 MIB->getOperand(Idx-1).isImplicit())
352 --Idx;
353 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
354 if (isTied)
355 isKill = false;
356 }
357
358 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
359 getDebugRegState(IsDebug));
360}
361
362/// AddOperand - Add the specified operand to the specified machine instr. II
363/// specifies the instruction information for the node, and IIOpNum is the
364/// operand number (in the II) that we are adding.
365void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
366 SDValue Op,
367 unsigned IIOpNum,
368 const MCInstrDesc *II,
369 DenseMap<SDValue, unsigned> &VRBaseMap,
370 bool IsDebug, bool IsClone, bool IsCloned) {
371 if (Op.isMachineOpcode()) {
372 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
373 IsDebug, IsClone, IsCloned);
374 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
375 MIB.addImm(C->getSExtValue());
376 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
377 MIB.addFPImm(F->getConstantFPValue());
378 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
379 unsigned VReg = R->getReg();
380 MVT OpVT = Op.getSimpleValueType();
381 const TargetRegisterClass *IIRC =
382 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
383 : nullptr;
384 const TargetRegisterClass *OpRC =
385 TLI->isTypeLegal(OpVT)
386 ? TLI->getRegClassFor(OpVT,
387 Op.getNode()->isDivergent() ||
388 (IIRC && TRI->isDivergentRegClass(IIRC)))
389 : nullptr;
390
391 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
392 Register NewVReg = MRI->createVirtualRegister(IIRC);
393 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
394 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
395 VReg = NewVReg;
396 }
397 // Turn additional physreg operands into implicit uses on non-variadic
398 // instructions. This is used by call and return instructions passing
399 // arguments in registers.
400 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
401 MIB.addReg(VReg, getImplRegState(Imp));
402 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
403 MIB.addRegMask(RM->getRegMask());
404 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
405 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
406 TGA->getTargetFlags());
407 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
408 MIB.addMBB(BBNode->getBasicBlock());
409 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
410 MIB.addFrameIndex(FI->getIndex());
411 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
412 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
413 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
414 int Offset = CP->getOffset();
415 unsigned Align = CP->getAlignment();
416 Type *Type = CP->getType();
417 // MachineConstantPool wants an explicit alignment.
418 if (Align == 0) {
419 Align = MF->getDataLayout().getPrefTypeAlignment(Type);
420 if (Align == 0) {
421 // Alignment of vector types. FIXME!
422 Align = MF->getDataLayout().getTypeAllocSize(Type);
423 }
424 }
425
426 unsigned Idx;
427 MachineConstantPool *MCP = MF->getConstantPool();
428 if (CP->isMachineConstantPoolEntry())
429 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
430 else
431 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
432 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
433 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
434 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
435 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
436 MIB.addSym(SymNode->getMCSymbol());
437 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
438 MIB.addBlockAddress(BA->getBlockAddress(),
439 BA->getOffset(),
440 BA->getTargetFlags());
441 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
442 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
443 } else {
444 assert(Op.getValueType() != MVT::Other &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 446, __PRETTY_FUNCTION__))
445 Op.getValueType() != MVT::Glue &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 446, __PRETTY_FUNCTION__))
446 "Chain and glue operands should occur at end of operand list!")((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 446, __PRETTY_FUNCTION__))
;
447 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
448 IsDebug, IsClone, IsCloned);
449 }
450}
451
452unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
453 MVT VT, bool isDivergent, const DebugLoc &DL) {
454 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
455 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
456
457 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
458 // within reason.
459 if (RC && RC != VRC)
460 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
461
462 // VReg has been adjusted. It can be used with SubIdx operands now.
463 if (RC)
464 return VReg;
465
466 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
467 // register instead.
468 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
469 assert(RC && "No legal register class for VT supports that SubIdx")((RC && "No legal register class for VT supports that SubIdx"
) ? static_cast<void> (0) : __assert_fail ("RC && \"No legal register class for VT supports that SubIdx\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 469, __PRETTY_FUNCTION__))
;
470 Register NewReg = MRI->createVirtualRegister(RC);
471 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
472 .addReg(VReg);
473 return NewReg;
474}
475
476/// EmitSubregNode - Generate machine code for subreg nodes.
477///
478void InstrEmitter::EmitSubregNode(SDNode *Node,
479 DenseMap<SDValue, unsigned> &VRBaseMap,
480 bool IsClone, bool IsCloned) {
481 unsigned VRBase = 0;
482 unsigned Opc = Node->getMachineOpcode();
483
484 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
485 // the CopyToReg'd destination register instead of creating a new vreg.
486 for (SDNode *User : Node->uses()) {
487 if (User->getOpcode() == ISD::CopyToReg &&
488 User->getOperand(2).getNode() == Node) {
489 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
490 if (Register::isVirtualRegister(DestReg)) {
491 VRBase = DestReg;
492 break;
493 }
494 }
495 }
496
497 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
498 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
499 // constraints on the %dst register, COPY can target all legal register
500 // classes.
501 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
502 const TargetRegisterClass *TRC =
503 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
504
505 unsigned Reg;
506 MachineInstr *DefMI;
507 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
508 if (R && Register::isPhysicalRegister(R->getReg())) {
509 Reg = R->getReg();
510 DefMI = nullptr;
511 } else {
512 Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
513 DefMI = MRI->getVRegDef(Reg);
514 }
515
516 unsigned SrcReg, DstReg, DefSubIdx;
517 if (DefMI &&
518 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
519 SubIdx == DefSubIdx &&
520 TRC == MRI->getRegClass(SrcReg)) {
521 // Optimize these:
522 // r1025 = s/zext r1024, 4
523 // r1026 = extract_subreg r1025, 4
524 // to a copy
525 // r1026 = copy r1024
526 VRBase = MRI->createVirtualRegister(TRC);
527 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
528 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
529 MRI->clearKillFlags(SrcReg);
530 } else {
531 // Reg may not support a SubIdx sub-register, and we may need to
532 // constrain its register class or issue a COPY to a compatible register
533 // class.
534 if (Register::isVirtualRegister(Reg))
535 Reg = ConstrainForSubReg(Reg, SubIdx,
536 Node->getOperand(0).getSimpleValueType(),
537 Node->isDivergent(), Node->getDebugLoc());
538 // Create the destreg if it is missing.
539 if (VRBase == 0)
540 VRBase = MRI->createVirtualRegister(TRC);
541
542 // Create the extract_subreg machine instruction.
543 MachineInstrBuilder CopyMI =
544 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
545 TII->get(TargetOpcode::COPY), VRBase);
546 if (Register::isVirtualRegister(Reg))
547 CopyMI.addReg(Reg, 0, SubIdx);
548 else
549 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
550 }
551 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
552 Opc == TargetOpcode::SUBREG_TO_REG) {
553 SDValue N0 = Node->getOperand(0);
554 SDValue N1 = Node->getOperand(1);
555 SDValue N2 = Node->getOperand(2);
556 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
557
558 // Figure out the register class to create for the destreg. It should be
559 // the largest legal register class supporting SubIdx sub-registers.
560 // RegisterCoalescer will constrain it further if it decides to eliminate
561 // the INSERT_SUBREG instruction.
562 //
563 // %dst = INSERT_SUBREG %src, %sub, SubIdx
564 //
565 // is lowered by TwoAddressInstructionPass to:
566 //
567 // %dst = COPY %src
568 // %dst:SubIdx = COPY %sub
569 //
570 // There is no constraint on the %src register class.
571 //
572 const TargetRegisterClass *SRC =
573 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
574 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
575 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG")((SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"
) ? static_cast<void> (0) : __assert_fail ("SRC && \"No register class supports VT and SubIdx for INSERT_SUBREG\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 575, __PRETTY_FUNCTION__))
;
576
577 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
578 VRBase = MRI->createVirtualRegister(SRC);
579
580 // Create the insert_subreg or subreg_to_reg machine instruction.
581 MachineInstrBuilder MIB =
582 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
583
584 // If creating a subreg_to_reg, then the first input operand
585 // is an implicit value immediate, otherwise it's a register
586 if (Opc == TargetOpcode::SUBREG_TO_REG) {
587 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
588 MIB.addImm(SD->getZExtValue());
589 } else
590 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
591 IsClone, IsCloned);
592 // Add the subregister being inserted
593 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
594 IsClone, IsCloned);
595 MIB.addImm(SubIdx);
596 MBB->insert(InsertPos, MIB);
597 } else
598 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg")::llvm::llvm_unreachable_internal("Node is not insert_subreg, extract_subreg, or subreg_to_reg"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 598)
;
599
600 SDValue Op(Node, 0);
601 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
602 (void)isNew; // Silence compiler warning.
603 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 603, __PRETTY_FUNCTION__))
;
604}
605
606/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
607/// COPY_TO_REGCLASS is just a normal copy, except that the destination
608/// register is constrained to be in a particular register class.
609///
610void
611InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
612 DenseMap<SDValue, unsigned> &VRBaseMap) {
613 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
614
615 // Create the new VReg in the destination class and emit a copy.
616 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
617 const TargetRegisterClass *DstRC =
618 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
619 Register NewVReg = MRI->createVirtualRegister(DstRC);
620 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
621 NewVReg).addReg(VReg);
622
623 SDValue Op(Node, 0);
624 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
625 (void)isNew; // Silence compiler warning.
626 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 626, __PRETTY_FUNCTION__))
;
627}
628
629/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
630///
631void InstrEmitter::EmitRegSequence(SDNode *Node,
632 DenseMap<SDValue, unsigned> &VRBaseMap,
633 bool IsClone, bool IsCloned) {
634 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
635 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
636 Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
637 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
638 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
639 unsigned NumOps = Node->getNumOperands();
640 // If the input pattern has a chain, then the root of the corresponding
641 // output pattern will get a chain as well. This can happen to be a
642 // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
643 if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
644 --NumOps; // Ignore chain if it exists.
645
646 assert((NumOps & 1) == 1 &&(((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"
) ? static_cast<void> (0) : __assert_fail ("(NumOps & 1) == 1 && \"REG_SEQUENCE must have an odd number of operands!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 647, __PRETTY_FUNCTION__))
647 "REG_SEQUENCE must have an odd number of operands!")(((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"
) ? static_cast<void> (0) : __assert_fail ("(NumOps & 1) == 1 && \"REG_SEQUENCE must have an odd number of operands!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 647, __PRETTY_FUNCTION__))
;
648 for (unsigned i = 1; i != NumOps; ++i) {
649 SDValue Op = Node->getOperand(i);
650 if ((i & 1) == 0) {
651 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
652 // Skip physical registers as they don't have a vreg to get and we'll
653 // insert copies for them in TwoAddressInstructionPass anyway.
654 if (!R || !Register::isPhysicalRegister(R->getReg())) {
655 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
656 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
657 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
658 const TargetRegisterClass *SRC =
659 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
660 if (SRC && SRC != RC) {
661 MRI->setRegClass(NewVReg, SRC);
662 RC = SRC;
663 }
664 }
665 }
666 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
667 IsClone, IsCloned);
668 }
669
670 MBB->insert(InsertPos, MIB);
671 SDValue Op(Node, 0);
672 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
673 (void)isNew; // Silence compiler warning.
674 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 674, __PRETTY_FUNCTION__))
;
675}
676
677/// EmitDbgValue - Generate machine instruction for a dbg_value node.
678///
679MachineInstr *
680InstrEmitter::EmitDbgValue(SDDbgValue *SD,
681 DenseMap<SDValue, unsigned> &VRBaseMap) {
682 MDNode *Var = SD->getVariable();
683 MDNode *Expr = SD->getExpression();
684 DebugLoc DL = SD->getDebugLoc();
685 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Var)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 686, __PRETTY_FUNCTION__))
686 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Var)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 686, __PRETTY_FUNCTION__))
;
687
688 SD->setIsEmitted();
689
690 if (SD->isInvalidated()) {
691 // An invalidated SDNode must generate an undef DBG_VALUE: although the
692 // original value is no longer computed, earlier DBG_VALUEs live ranges
693 // must not leak into later code.
694 auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
695 MIB.addReg(0U);
696 MIB.addReg(0U, RegState::Debug);
697 MIB.addMetadata(Var);
698 MIB.addMetadata(Expr);
699 return &*MIB;
700 }
701
702 if (SD->getKind() == SDDbgValue::FRAMEIX) {
703 // Stack address; this needs to be lowered in target-dependent fashion.
704 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
705 auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
706 .addFrameIndex(SD->getFrameIx());
707 if (SD->isIndirect())
708 // Push [fi + 0] onto the DIExpression stack.
709 FrameMI.addImm(0);
710 else
711 // Push fi onto the DIExpression stack.
712 FrameMI.addReg(0);
713 return FrameMI.addMetadata(Var).addMetadata(Expr);
714 }
715 // Otherwise, we're going to create an instruction here.
716 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
717 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
718 if (SD->getKind() == SDDbgValue::SDNODE) {
719 SDNode *Node = SD->getSDNode();
720 SDValue Op = SDValue(Node, SD->getResNo());
721 // It's possible we replaced this SDNode with other(s) and therefore
722 // didn't generate code for it. It's better to catch these cases where
723 // they happen and transfer the debug info, but trying to guarantee that
724 // in all cases would be very fragile; this is a safeguard for any
725 // that were missed.
726 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
727 if (I==VRBaseMap.end())
728 MIB.addReg(0U); // undef
729 else
730 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
731 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
732 } else if (SD->getKind() == SDDbgValue::VREG) {
733 MIB.addReg(SD->getVReg(), RegState::Debug);
734 } else if (SD->getKind() == SDDbgValue::CONST) {
735 const Value *V = SD->getConst();
736 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
737 if (CI->getBitWidth() > 64)
738 MIB.addCImm(CI);
739 else
740 MIB.addImm(CI->getSExtValue());
741 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
742 MIB.addFPImm(CF);
743 } else if (isa<ConstantPointerNull>(V)) {
744 // Note: This assumes that all nullptr constants are zero-valued.
745 MIB.addImm(0);
746 } else {
747 // Could be an Undef. In any case insert an Undef so we can see what we
748 // dropped.
749 MIB.addReg(0U);
750 }
751 } else {
752 // Insert an Undef so we can see what we dropped.
753 MIB.addReg(0U);
754 }
755
756 // Indirect addressing is indicated by an Imm as the second parameter.
757 if (SD->isIndirect())
758 MIB.addImm(0U);
759 else
760 MIB.addReg(0U, RegState::Debug);
761
762 MIB.addMetadata(Var);
763 MIB.addMetadata(Expr);
764
765 return &*MIB;
766}
767
768MachineInstr *
769InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
770 MDNode *Label = SD->getLabel();
771 DebugLoc DL = SD->getDebugLoc();
772 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&((cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 773, __PRETTY_FUNCTION__))
773 "Expected inlined-at fields to agree")((cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 773, __PRETTY_FUNCTION__))
;
774
775 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
776 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
777 MIB.addMetadata(Label);
778
779 return &*MIB;
780}
781
782/// EmitMachineNode - Generate machine code for a target-specific node and
783/// needed dependencies.
784///
785void InstrEmitter::
786EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
787 DenseMap<SDValue, unsigned> &VRBaseMap) {
788 unsigned Opc = Node->getMachineOpcode();
789
790 // Handle subreg insert/extract specially
791 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
792 Opc == TargetOpcode::INSERT_SUBREG ||
793 Opc == TargetOpcode::SUBREG_TO_REG) {
794 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
795 return;
796 }
797
798 // Handle COPY_TO_REGCLASS specially.
799 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
800 EmitCopyToRegClassNode(Node, VRBaseMap);
801 return;
802 }
803
804 // Handle REG_SEQUENCE specially.
805 if (Opc == TargetOpcode::REG_SEQUENCE) {
806 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
807 return;
808 }
809
810 if (Opc == TargetOpcode::IMPLICIT_DEF)
811 // We want a unique VR for each IMPLICIT_DEF use.
812 return;
813
814 const MCInstrDesc &II = TII->get(Opc);
815 unsigned NumResults = CountResults(Node);
816 unsigned NumDefs = II.getNumDefs();
817 const MCPhysReg *ScratchRegs = nullptr;
818
819 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
820 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
821 // Stackmaps do not have arguments and do not preserve their calling
822 // convention. However, to simplify runtime support, they clobber the same
823 // scratch registers as AnyRegCC.
824 unsigned CC = CallingConv::AnyReg;
825 if (Opc == TargetOpcode::PATCHPOINT) {
826 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
827 NumDefs = NumResults;
828 }
829 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
830 }
831
832 unsigned NumImpUses = 0;
833 unsigned NodeOperands =
834 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
835 bool HasVRegVariadicDefs = !MF->getTarget().usesPhysRegsForValues() &&
836 II.isVariadic() && II.variadicOpsAreDefs();
837 bool HasPhysRegOuts = NumResults > NumDefs &&
838 II.getImplicitDefs() != nullptr && !HasVRegVariadicDefs;
839#ifndef NDEBUG
840 unsigned NumMIOperands = NodeOperands + NumResults;
841 if (II.isVariadic())
842 assert(NumMIOperands >= II.getNumOperands() &&((NumMIOperands >= II.getNumOperands() && "Too few operands for a variadic node!"
) ? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && \"Too few operands for a variadic node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 843, __PRETTY_FUNCTION__))
843 "Too few operands for a variadic node!")((NumMIOperands >= II.getNumOperands() && "Too few operands for a variadic node!"
) ? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && \"Too few operands for a variadic node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 843, __PRETTY_FUNCTION__))
;
844 else
845 assert(NumMIOperands >= II.getNumOperands() &&((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 848, __PRETTY_FUNCTION__))
846 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 848, __PRETTY_FUNCTION__))
847 NumImpUses &&((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 848, __PRETTY_FUNCTION__))
848 "#operands for dag node doesn't match .td file!")((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 848, __PRETTY_FUNCTION__))
;
849#endif
850
851 // Create the new machine instruction.
852 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
853
854 // Add result register values for things that are defined by this
855 // instruction.
856 if (NumResults) {
857 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
858
859 // Transfer any IR flags from the SDNode to the MachineInstr
860 MachineInstr *MI = MIB.getInstr();
861 const SDNodeFlags Flags = Node->getFlags();
862 if (Flags.hasNoSignedZeros())
863 MI->setFlag(MachineInstr::MIFlag::FmNsz);
864
865 if (Flags.hasAllowReciprocal())
866 MI->setFlag(MachineInstr::MIFlag::FmArcp);
867
868 if (Flags.hasNoNaNs())
869 MI->setFlag(MachineInstr::MIFlag::FmNoNans);
870
871 if (Flags.hasNoInfs())
872 MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
873
874 if (Flags.hasAllowContract())
875 MI->setFlag(MachineInstr::MIFlag::FmContract);
876
877 if (Flags.hasApproximateFuncs())
878 MI->setFlag(MachineInstr::MIFlag::FmAfn);
879
880 if (Flags.hasAllowReassociation())
881 MI->setFlag(MachineInstr::MIFlag::FmReassoc);
882
883 if (Flags.hasNoUnsignedWrap())
884 MI->setFlag(MachineInstr::MIFlag::NoUWrap);
885
886 if (Flags.hasNoSignedWrap())
887 MI->setFlag(MachineInstr::MIFlag::NoSWrap);
888
889 if (Flags.hasExact())
890 MI->setFlag(MachineInstr::MIFlag::IsExact);
891
892 if (Flags.hasNoFPExcept())
893 MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
894 }
895
896 // Emit all of the actual operands of this instruction, adding them to the
897 // instruction as appropriate.
898 bool HasOptPRefs = NumDefs > NumResults;
899 assert((!HasOptPRefs || !HasPhysRegOuts) &&(((!HasOptPRefs || !HasPhysRegOuts) && "Unable to cope with optional defs and phys regs defs!"
) ? static_cast<void> (0) : __assert_fail ("(!HasOptPRefs || !HasPhysRegOuts) && \"Unable to cope with optional defs and phys regs defs!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 900, __PRETTY_FUNCTION__))
900 "Unable to cope with optional defs and phys regs defs!")(((!HasOptPRefs || !HasPhysRegOuts) && "Unable to cope with optional defs and phys regs defs!"
) ? static_cast<void> (0) : __assert_fail ("(!HasOptPRefs || !HasPhysRegOuts) && \"Unable to cope with optional defs and phys regs defs!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 900, __PRETTY_FUNCTION__))
;
901 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
902 for (unsigned i = NumSkip; i != NodeOperands; ++i)
903 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
904 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
905
906 // Add scratch registers as implicit def and early clobber
907 if (ScratchRegs)
908 for (unsigned i = 0; ScratchRegs[i]; ++i)
909 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
910 RegState::EarlyClobber);
911
912 // Set the memory reference descriptions of this instruction now that it is
913 // part of the function.
914 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
915
916 // Insert the instruction into position in the block. This needs to
917 // happen before any custom inserter hook is called so that the
918 // hook knows where in the block to insert the replacement code.
919 MBB->insert(InsertPos, MIB);
920
921 // The MachineInstr may also define physregs instead of virtregs. These
922 // physreg values can reach other instructions in different ways:
923 //
924 // 1. When there is a use of a Node value beyond the explicitly defined
925 // virtual registers, we emit a CopyFromReg for one of the implicitly
926 // defined physregs. This only happens when HasPhysRegOuts is true.
927 //
928 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
929 //
930 // 3. A glued instruction may implicitly use a physreg.
931 //
932 // 4. A glued instruction may use a RegisterSDNode operand.
933 //
934 // Collect all the used physreg defs, and make sure that any unused physreg
935 // defs are marked as dead.
936 SmallVector<Register, 8> UsedRegs;
937
938 // Additional results must be physical register defs.
939 if (HasPhysRegOuts) {
940 for (unsigned i = NumDefs; i < NumResults; ++i) {
941 Register Reg = II.getImplicitDefs()[i - NumDefs];
942 if (!Node->hasAnyUseOfValue(i))
943 continue;
944 // This implicitly defined physreg has a use.
945 UsedRegs.push_back(Reg);
946 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
947 }
948 }
949
950 // Scan the glue chain for any used physregs.
951 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
952 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
953 if (F->getOpcode() == ISD::CopyFromReg) {
954 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
955 continue;
956 } else if (F->getOpcode() == ISD::CopyToReg) {
957 // Skip CopyToReg nodes that are internal to the glue chain.
958 continue;
959 }
960 // Collect declared implicit uses.
961 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
962 UsedRegs.append(MCID.getImplicitUses(),
963 MCID.getImplicitUses() + MCID.getNumImplicitUses());
964 // In addition to declared implicit uses, we must also check for
965 // direct RegisterSDNode operands.
966 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
967 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
968 Register Reg = R->getReg();
969 if (Reg.isPhysical())
970 UsedRegs.push_back(Reg);
971 }
972 }
973 }
974
975 // Finally mark unused registers as dead.
976 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
977 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
978
979 // Run post-isel target hook to adjust this instruction if needed.
980 if (II.hasPostISelHook())
981 TLI->AdjustInstrPostInstrSelection(*MIB, Node);
982}
983
984/// EmitSpecialNode - Generate machine code for a target-independent node and
985/// needed dependencies.
986void InstrEmitter::
987EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
988 DenseMap<SDValue, unsigned> &VRBaseMap) {
989 switch (Node->getOpcode()) {
1
Control jumps to 'case CopyToReg:' at line 1000
990 default:
991#ifndef NDEBUG
992 Node->dump();
993#endif
994 llvm_unreachable("This target-independent node should have been selected!")::llvm::llvm_unreachable_internal("This target-independent node should have been selected!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 994)
;
995 case ISD::EntryToken:
996 llvm_unreachable("EntryToken should have been excluded from the schedule!")::llvm::llvm_unreachable_internal("EntryToken should have been excluded from the schedule!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 996)
;
997 case ISD::MERGE_VALUES:
998 case ISD::TokenFactor: // fall thru
999 break;
1000 case ISD::CopyToReg: {
1001 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1002 SDValue SrcVal = Node->getOperand(2);
1003 if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
1004 SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
1005 // Instead building a COPY to that vreg destination, build an
1006 // IMPLICIT_DEF instruction instead.
1007 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1008 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1009 break;
1010 }
1011 unsigned SrcReg;
1012 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
2
Assuming 'R' is null
3
Taking false branch
1013 SrcReg = R->getReg();
1014 else
1015 SrcReg = getVR(SrcVal, VRBaseMap);
4
Value assigned to 'Op.Node'
5
Calling 'InstrEmitter::getVR'
1016
1017 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1018 break;
1019
1020 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1021 DestReg).addReg(SrcReg);
1022 break;
1023 }
1024 case ISD::CopyFromReg: {
1025 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1026 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1027 break;
1028 }
1029 case ISD::EH_LABEL:
1030 case ISD::ANNOTATION_LABEL: {
1031 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1032 ? TargetOpcode::EH_LABEL
1033 : TargetOpcode::ANNOTATION_LABEL;
1034 MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1035 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1036 TII->get(Opc)).addSym(S);
1037 break;
1038 }
1039
1040 case ISD::LIFETIME_START:
1041 case ISD::LIFETIME_END: {
1042 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1043 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
1044
1045 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
1046 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1047 .addFrameIndex(FI->getIndex());
1048 break;
1049 }
1050
1051 case ISD::INLINEASM:
1052 case ISD::INLINEASM_BR: {
1053 unsigned NumOps = Node->getNumOperands();
1054 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1055 --NumOps; // Ignore the glue operand.
1056
1057 // Create the inline asm machine instruction.
1058 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1059 ? TargetOpcode::INLINEASM_BR
1060 : TargetOpcode::INLINEASM;
1061 MachineInstrBuilder MIB =
1062 BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1063
1064 // Add the asm string as an external symbol operand.
1065 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1066 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1067 MIB.addExternalSymbol(AsmStr);
1068
1069 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1070 // bits.
1071 int64_t ExtraInfo =
1072 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1073 getZExtValue();
1074 MIB.addImm(ExtraInfo);
1075
1076 // Remember to operand index of the group flags.
1077 SmallVector<unsigned, 8> GroupIdx;
1078
1079 // Remember registers that are part of early-clobber defs.
1080 SmallVector<unsigned, 8> ECRegs;
1081
1082 // Add all of the operand registers to the instruction.
1083 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1084 unsigned Flags =
1085 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1086 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1087
1088 GroupIdx.push_back(MIB->getNumOperands());
1089 MIB.addImm(Flags);
1090 ++i; // Skip the ID value.
1091
1092 switch (InlineAsm::getKind(Flags)) {
1093 default: llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1093)
;
1094 case InlineAsm::Kind_RegDef:
1095 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1096 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1097 // FIXME: Add dead flags for physical and virtual registers defined.
1098 // For now, mark physical register defs as implicit to help fast
1099 // regalloc. This makes inline asm look a lot like calls.
1100 MIB.addReg(Reg,
1101 RegState::Define |
1102 getImplRegState(Register::isPhysicalRegister(Reg)));
1103 }
1104 break;
1105 case InlineAsm::Kind_RegDefEarlyClobber:
1106 case InlineAsm::Kind_Clobber:
1107 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1108 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1109 MIB.addReg(Reg,
1110 RegState::Define | RegState::EarlyClobber |
1111 getImplRegState(Register::isPhysicalRegister(Reg)));
1112 ECRegs.push_back(Reg);
1113 }
1114 break;
1115 case InlineAsm::Kind_RegUse: // Use of register.
1116 case InlineAsm::Kind_Imm: // Immediate.
1117 case InlineAsm::Kind_Mem: // Addressing mode.
1118 // The addressing mode has been selected, just add all of the
1119 // operands to the machine instruction.
1120 for (unsigned j = 0; j != NumVals; ++j, ++i)
1121 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1122 /*IsDebug=*/false, IsClone, IsCloned);
1123
1124 // Manually set isTied bits.
1125 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
1126 unsigned DefGroup = 0;
1127 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1128 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1129 unsigned UseIdx = GroupIdx.back() + 1;
1130 for (unsigned j = 0; j != NumVals; ++j)
1131 MIB->tieOperands(DefIdx + j, UseIdx + j);
1132 }
1133 }
1134 break;
1135 }
1136 }
1137
1138 // GCC inline assembly allows input operands to also be early-clobber
1139 // output operands (so long as the operand is written only after it's
1140 // used), but this does not match the semantics of our early-clobber flag.
1141 // If an early-clobber operand register is also an input operand register,
1142 // then remove the early-clobber flag.
1143 for (unsigned Reg : ECRegs) {
1144 if (MIB->readsRegister(Reg, TRI)) {
1145 MachineOperand *MO =
1146 MIB->findRegisterDefOperand(Reg, false, false, TRI);
1147 assert(MO && "No def operand for clobbered register?")((MO && "No def operand for clobbered register?") ? static_cast
<void> (0) : __assert_fail ("MO && \"No def operand for clobbered register?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1147, __PRETTY_FUNCTION__))
;
1148 MO->setIsEarlyClobber(false);
1149 }
1150 }
1151
1152 // Get the mdnode from the asm if it exists and add it to the instruction.
1153 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1154 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1155 if (MD)
1156 MIB.addMetadata(MD);
1157
1158 MBB->insert(InsertPos, MIB);
1159 break;
1160 }
1161 }
1162}
1163
1164/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1165/// at the given position in the given block.
1166InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1167 MachineBasicBlock::iterator insertpos)
1168 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1169 TII(MF->getSubtarget().getInstrInfo()),
1170 TRI(MF->getSubtarget().getRegisterInfo()),
1171 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1172 InsertPos(insertpos) {}

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/Constants.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Instruction.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/Metadata.h"
39#include "llvm/IR/Operator.h"
40#include "llvm/Support/AlignOf.h"
41#include "llvm/Support/AtomicOrdering.h"
42#include "llvm/Support/Casting.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MachineValueType.h"
45#include "llvm/Support/TypeSize.h"
46#include <algorithm>
47#include <cassert>
48#include <climits>
49#include <cstddef>
50#include <cstdint>
51#include <cstring>
52#include <iterator>
53#include <string>
54#include <tuple>
55
56namespace llvm {
57
58class APInt;
59class Constant;
60template <typename T> struct DenseMapInfo;
61class GlobalValue;
62class MachineBasicBlock;
63class MachineConstantPoolValue;
64class MCSymbol;
65class raw_ostream;
66class SDNode;
67class SelectionDAG;
68class Type;
69class Value;
70
71void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
72 bool force = false);
73
74/// This represents a list of ValueType's that has been intern'd by
75/// a SelectionDAG. Instances of this simple value class are returned by
76/// SelectionDAG::getVTList(...).
77///
78struct SDVTList {
79 const EVT *VTs;
80 unsigned int NumVTs;
81};
82
83namespace ISD {
84
85 /// Node predicates
86
87 /// If N is a BUILD_VECTOR node whose elements are all the same constant or
88 /// undefined, return true and return the constant value in \p SplatValue.
89 bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
90
91 /// Return true if the specified node is a BUILD_VECTOR where all of the
92 /// elements are ~0 or undef.
93 bool isBuildVectorAllOnes(const SDNode *N);
94
95 /// Return true if the specified node is a BUILD_VECTOR where all of the
96 /// elements are 0 or undef.
97 bool isBuildVectorAllZeros(const SDNode *N);
98
99 /// Return true if the specified node is a BUILD_VECTOR node of all
100 /// ConstantSDNode or undef.
101 bool isBuildVectorOfConstantSDNodes(const SDNode *N);
102
103 /// Return true if the specified node is a BUILD_VECTOR node of all
104 /// ConstantFPSDNode or undef.
105 bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
106
107 /// Return true if the node has at least one operand and all operands of the
108 /// specified node are ISD::UNDEF.
109 bool allOperandsUndef(const SDNode *N);
110
111} // end namespace ISD
112
113//===----------------------------------------------------------------------===//
114/// Unlike LLVM values, Selection DAG nodes may return multiple
115/// values as the result of a computation. Many nodes return multiple values,
116/// from loads (which define a token and a return value) to ADDC (which returns
117/// a result and a carry value), to calls (which may return an arbitrary number
118/// of values).
119///
120/// As such, each use of a SelectionDAG computation must indicate the node that
121/// computes it as well as which return value to use from that node. This pair
122/// of information is represented with the SDValue value type.
123///
124class SDValue {
125 friend struct DenseMapInfo<SDValue>;
126
127 SDNode *Node = nullptr; // The node defining the value we are using.
128 unsigned ResNo = 0; // Which return value of the node we are using.
129
130public:
131 SDValue() = default;
132 SDValue(SDNode *node, unsigned resno);
133
134 /// get the index which selects a specific result in the SDNode
135 unsigned getResNo() const { return ResNo; }
136
137 /// get the SDNode which holds the desired result
138 SDNode *getNode() const { return Node; }
139
140 /// set the SDNode
141 void setNode(SDNode *N) { Node = N; }
142
143 inline SDNode *operator->() const { return Node; }
144
145 bool operator==(const SDValue &O) const {
146 return Node == O.Node && ResNo == O.ResNo;
147 }
148 bool operator!=(const SDValue &O) const {
149 return !operator==(O);
150 }
151 bool operator<(const SDValue &O) const {
152 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
153 }
154 explicit operator bool() const {
155 return Node != nullptr;
156 }
157
158 SDValue getValue(unsigned R) const {
159 return SDValue(Node, R);
160 }
161
162 /// Return true if this node is an operand of N.
163 bool isOperandOf(const SDNode *N) const;
164
165 /// Return the ValueType of the referenced return value.
166 inline EVT getValueType() const;
167
168 /// Return the simple ValueType of the referenced return value.
169 MVT getSimpleValueType() const {
170 return getValueType().getSimpleVT();
171 }
172
173 /// Returns the size of the value in bits.
174 ///
175 /// If the value type is a scalable vector type, the scalable property will
176 /// be set and the runtime size will be a positive integer multiple of the
177 /// base size.
178 TypeSize getValueSizeInBits() const {
179 return getValueType().getSizeInBits();
180 }
181
182 TypeSize getScalarValueSizeInBits() const {
183 return getValueType().getScalarType().getSizeInBits();
184 }
185
186 // Forwarding methods - These forward to the corresponding methods in SDNode.
187 inline unsigned getOpcode() const;
188 inline unsigned getNumOperands() const;
189 inline const SDValue &getOperand(unsigned i) const;
190 inline uint64_t getConstantOperandVal(unsigned i) const;
191 inline const APInt &getConstantOperandAPInt(unsigned i) const;
192 inline bool isTargetMemoryOpcode() const;
193 inline bool isTargetOpcode() const;
194 inline bool isMachineOpcode() const;
195 inline bool isUndef() const;
196 inline unsigned getMachineOpcode() const;
197 inline const DebugLoc &getDebugLoc() const;
198 inline void dump() const;
199 inline void dump(const SelectionDAG *G) const;
200 inline void dumpr() const;
201 inline void dumpr(const SelectionDAG *G) const;
202
203 /// Return true if this operand (which must be a chain) reaches the
204 /// specified operand without crossing any side-effecting instructions.
205 /// In practice, this looks through token factors and non-volatile loads.
206 /// In order to remain efficient, this only
207 /// looks a couple of nodes in, it does not do an exhaustive search.
208 bool reachesChainWithoutSideEffects(SDValue Dest,
209 unsigned Depth = 2) const;
210
211 /// Return true if there are no nodes using value ResNo of Node.
212 inline bool use_empty() const;
213
214 /// Return true if there is exactly one node using value ResNo of Node.
215 inline bool hasOneUse() const;
216};
217
218template<> struct DenseMapInfo<SDValue> {
219 static inline SDValue getEmptyKey() {
220 SDValue V;
221 V.ResNo = -1U;
222 return V;
223 }
224
225 static inline SDValue getTombstoneKey() {
226 SDValue V;
227 V.ResNo = -2U;
228 return V;
229 }
230
231 static unsigned getHashValue(const SDValue &Val) {
232 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
233 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
234 }
235
236 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
237 return LHS == RHS;
238 }
239};
240
241/// Allow casting operators to work directly on
242/// SDValues as if they were SDNode*'s.
243template<> struct simplify_type<SDValue> {
244 using SimpleType = SDNode *;
245
246 static SimpleType getSimplifiedValue(SDValue &Val) {
247 return Val.getNode();
248 }
249};
250template<> struct simplify_type<const SDValue> {
251 using SimpleType = /*const*/ SDNode *;
252
253 static SimpleType getSimplifiedValue(const SDValue &Val) {
254 return Val.getNode();
255 }
256};
257
258/// Represents a use of a SDNode. This class holds an SDValue,
259/// which records the SDNode being used and the result number, a
260/// pointer to the SDNode using the value, and Next and Prev pointers,
261/// which link together all the uses of an SDNode.
262///
263class SDUse {
264 /// Val - The value being used.
265 SDValue Val;
266 /// User - The user of this value.
267 SDNode *User = nullptr;
268 /// Prev, Next - Pointers to the uses list of the SDNode referred by
269 /// this operand.
270 SDUse **Prev = nullptr;
271 SDUse *Next = nullptr;
272
273public:
274 SDUse() = default;
275 SDUse(const SDUse &U) = delete;
276 SDUse &operator=(const SDUse &) = delete;
277
278 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
279 operator const SDValue&() const { return Val; }
280
281 /// If implicit conversion to SDValue doesn't work, the get() method returns
282 /// the SDValue.
283 const SDValue &get() const { return Val; }
284
285 /// This returns the SDNode that contains this Use.
286 SDNode *getUser() { return User; }
287
288 /// Get the next SDUse in the use list.
289 SDUse *getNext() const { return Next; }
290
291 /// Convenience function for get().getNode().
292 SDNode *getNode() const { return Val.getNode(); }
293 /// Convenience function for get().getResNo().
294 unsigned getResNo() const { return Val.getResNo(); }
295 /// Convenience function for get().getValueType().
296 EVT getValueType() const { return Val.getValueType(); }
297
298 /// Convenience function for get().operator==
299 bool operator==(const SDValue &V) const {
300 return Val == V;
301 }
302
303 /// Convenience function for get().operator!=
304 bool operator!=(const SDValue &V) const {
305 return Val != V;
306 }
307
308 /// Convenience function for get().operator<
309 bool operator<(const SDValue &V) const {
310 return Val < V;
311 }
312
313private:
314 friend class SelectionDAG;
315 friend class SDNode;
316 // TODO: unfriend HandleSDNode once we fix its operand handling.
317 friend class HandleSDNode;
318
319 void setUser(SDNode *p) { User = p; }
320
321 /// Remove this use from its existing use list, assign it the
322 /// given value, and add it to the new value's node's use list.
323 inline void set(const SDValue &V);
324 /// Like set, but only supports initializing a newly-allocated
325 /// SDUse with a non-null value.
326 inline void setInitial(const SDValue &V);
327 /// Like set, but only sets the Node portion of the value,
328 /// leaving the ResNo portion unmodified.
329 inline void setNode(SDNode *N);
330
331 void addToList(SDUse **List) {
332 Next = *List;
333 if (Next) Next->Prev = &Next;
334 Prev = List;
335 *List = this;
336 }
337
338 void removeFromList() {
339 *Prev = Next;
340 if (Next) Next->Prev = Prev;
341 }
342};
343
344/// simplify_type specializations - Allow casting operators to work directly on
345/// SDValues as if they were SDNode*'s.
346template<> struct simplify_type<SDUse> {
347 using SimpleType = SDNode *;
348
349 static SimpleType getSimplifiedValue(SDUse &Val) {
350 return Val.getNode();
351 }
352};
353
354/// These are IR-level optimization flags that may be propagated to SDNodes.
355/// TODO: This data structure should be shared by the IR optimizer and the
356/// the backend.
357struct SDNodeFlags {
358private:
359 // This bit is used to determine if the flags are in a defined state.
360 // Flag bits can only be masked out during intersection if the masking flags
361 // are defined.
362 bool AnyDefined : 1;
363
364 bool NoUnsignedWrap : 1;
365 bool NoSignedWrap : 1;
366 bool Exact : 1;
367 bool NoNaNs : 1;
368 bool NoInfs : 1;
369 bool NoSignedZeros : 1;
370 bool AllowReciprocal : 1;
371 bool VectorReduction : 1;
372 bool AllowContract : 1;
373 bool ApproximateFuncs : 1;
374 bool AllowReassociation : 1;
375
376 // We assume instructions do not raise floating-point exceptions by default,
377 // and only those marked explicitly may do so. We could choose to represent
378 // this via a positive "FPExcept" flags like on the MI level, but having a
379 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
380 // intersection logic more straightforward.
381 bool NoFPExcept : 1;
382
383public:
384 /// Default constructor turns off all optimization flags.
385 SDNodeFlags()
386 : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
387 Exact(false), NoNaNs(false), NoInfs(false),
388 NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
389 AllowContract(false), ApproximateFuncs(false),
390 AllowReassociation(false), NoFPExcept(false) {}
391
392 /// Propagate the fast-math-flags from an IR FPMathOperator.
393 void copyFMF(const FPMathOperator &FPMO) {
394 setNoNaNs(FPMO.hasNoNaNs());
395 setNoInfs(FPMO.hasNoInfs());
396 setNoSignedZeros(FPMO.hasNoSignedZeros());
397 setAllowReciprocal(FPMO.hasAllowReciprocal());
398 setAllowContract(FPMO.hasAllowContract());
399 setApproximateFuncs(FPMO.hasApproxFunc());
400 setAllowReassociation(FPMO.hasAllowReassoc());
401 }
402
403 /// Sets the state of the flags to the defined state.
404 void setDefined() { AnyDefined = true; }
405 /// Returns true if the flags are in a defined state.
406 bool isDefined() const { return AnyDefined; }
407
408 // These are mutators for each flag.
409 void setNoUnsignedWrap(bool b) {
410 setDefined();
411 NoUnsignedWrap = b;
412 }
413 void setNoSignedWrap(bool b) {
414 setDefined();
415 NoSignedWrap = b;
416 }
417 void setExact(bool b) {
418 setDefined();
419 Exact = b;
420 }
421 void setNoNaNs(bool b) {
422 setDefined();
423 NoNaNs = b;
424 }
425 void setNoInfs(bool b) {
426 setDefined();
427 NoInfs = b;
428 }
429 void setNoSignedZeros(bool b) {
430 setDefined();
431 NoSignedZeros = b;
432 }
433 void setAllowReciprocal(bool b) {
434 setDefined();
435 AllowReciprocal = b;
436 }
437 void setVectorReduction(bool b) {
438 setDefined();
439 VectorReduction = b;
440 }
441 void setAllowContract(bool b) {
442 setDefined();
443 AllowContract = b;
444 }
445 void setApproximateFuncs(bool b) {
446 setDefined();
447 ApproximateFuncs = b;
448 }
449 void setAllowReassociation(bool b) {
450 setDefined();
451 AllowReassociation = b;
452 }
453 void setNoFPExcept(bool b) {
454 setDefined();
455 NoFPExcept = b;
456 }
457
458 // These are accessors for each flag.
459 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
460 bool hasNoSignedWrap() const { return NoSignedWrap; }
461 bool hasExact() const { return Exact; }
462 bool hasNoNaNs() const { return NoNaNs; }
463 bool hasNoInfs() const { return NoInfs; }
464 bool hasNoSignedZeros() const { return NoSignedZeros; }
465 bool hasAllowReciprocal() const { return AllowReciprocal; }
466 bool hasVectorReduction() const { return VectorReduction; }
467 bool hasAllowContract() const { return AllowContract; }
468 bool hasApproximateFuncs() const { return ApproximateFuncs; }
469 bool hasAllowReassociation() const { return AllowReassociation; }
470 bool hasNoFPExcept() const { return NoFPExcept; }
471
472 /// Clear any flags in this flag set that aren't also set in Flags.
473 /// If the given Flags are undefined then don't do anything.
474 void intersectWith(const SDNodeFlags Flags) {
475 if (!Flags.isDefined())
476 return;
477 NoUnsignedWrap &= Flags.NoUnsignedWrap;
478 NoSignedWrap &= Flags.NoSignedWrap;
479 Exact &= Flags.Exact;
480 NoNaNs &= Flags.NoNaNs;
481 NoInfs &= Flags.NoInfs;
482 NoSignedZeros &= Flags.NoSignedZeros;
483 AllowReciprocal &= Flags.AllowReciprocal;
484 VectorReduction &= Flags.VectorReduction;
485 AllowContract &= Flags.AllowContract;
486 ApproximateFuncs &= Flags.ApproximateFuncs;
487 AllowReassociation &= Flags.AllowReassociation;
488 NoFPExcept &= Flags.NoFPExcept;
489 }
490};
491
492/// Represents one node in the SelectionDAG.
493///
494class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
495private:
496 /// The operation that this node performs.
497 int16_t NodeType;
498
499protected:
500 // We define a set of mini-helper classes to help us interpret the bits in our
501 // SubclassData. These are designed to fit within a uint16_t so they pack
502 // with NodeType.
503
504#if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__))
505// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
506// and give the `pack` pragma push semantics.
507#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
508#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
509#else
510#define BEGIN_TWO_BYTE_PACK()
511#define END_TWO_BYTE_PACK()
512#endif
513
514BEGIN_TWO_BYTE_PACK()
515 class SDNodeBitfields {
516 friend class SDNode;
517 friend class MemIntrinsicSDNode;
518 friend class MemSDNode;
519 friend class SelectionDAG;
520
521 uint16_t HasDebugValue : 1;
522 uint16_t IsMemIntrinsic : 1;
523 uint16_t IsDivergent : 1;
524 };
525 enum { NumSDNodeBits = 3 };
526
527 class ConstantSDNodeBitfields {
528 friend class ConstantSDNode;
529
530 uint16_t : NumSDNodeBits;
531
532 uint16_t IsOpaque : 1;
533 };
534
535 class MemSDNodeBitfields {
536 friend class MemSDNode;
537 friend class MemIntrinsicSDNode;
538 friend class AtomicSDNode;
539
540 uint16_t : NumSDNodeBits;
541
542 uint16_t IsVolatile : 1;
543 uint16_t IsNonTemporal : 1;
544 uint16_t IsDereferenceable : 1;
545 uint16_t IsInvariant : 1;
546 };
547 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
548
549 class LSBaseSDNodeBitfields {
550 friend class LSBaseSDNode;
551 friend class MaskedLoadStoreSDNode;
552 friend class MaskedGatherScatterSDNode;
553
554 uint16_t : NumMemSDNodeBits;
555
556 // This storage is shared between disparate class hierarchies to hold an
557 // enumeration specific to the class hierarchy in use.
558 // LSBaseSDNode => enum ISD::MemIndexedMode
559 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
560 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
561 uint16_t AddressingMode : 3;
562 };
563 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
564
565 class LoadSDNodeBitfields {
566 friend class LoadSDNode;
567 friend class MaskedLoadSDNode;
568
569 uint16_t : NumLSBaseSDNodeBits;
570
571 uint16_t ExtTy : 2; // enum ISD::LoadExtType
572 uint16_t IsExpanding : 1;
573 };
574
575 class StoreSDNodeBitfields {
576 friend class StoreSDNode;
577 friend class MaskedStoreSDNode;
578
579 uint16_t : NumLSBaseSDNodeBits;
580
581 uint16_t IsTruncating : 1;
582 uint16_t IsCompressing : 1;
583 };
584
585 union {
586 char RawSDNodeBits[sizeof(uint16_t)];
587 SDNodeBitfields SDNodeBits;
588 ConstantSDNodeBitfields ConstantSDNodeBits;
589 MemSDNodeBitfields MemSDNodeBits;
590 LSBaseSDNodeBitfields LSBaseSDNodeBits;
591 LoadSDNodeBitfields LoadSDNodeBits;
592 StoreSDNodeBitfields StoreSDNodeBits;
593 };
594END_TWO_BYTE_PACK()
595#undef BEGIN_TWO_BYTE_PACK
596#undef END_TWO_BYTE_PACK
597
598 // RawSDNodeBits must cover the entirety of the union. This means that all of
599 // the union's members must have size <= RawSDNodeBits. We write the RHS as
600 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
601 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
602 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
603 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
604 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
605 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
606 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
607
608private:
609 friend class SelectionDAG;
610 // TODO: unfriend HandleSDNode once we fix its operand handling.
611 friend class HandleSDNode;
612
613 /// Unique id per SDNode in the DAG.
614 int NodeId = -1;
615
616 /// The values that are used by this operation.
617 SDUse *OperandList = nullptr;
618
619 /// The types of the values this node defines. SDNode's may
620 /// define multiple values simultaneously.
621 const EVT *ValueList;
622
623 /// List of uses for this SDNode.
624 SDUse *UseList = nullptr;
625
626 /// The number of entries in the Operand/Value list.
627 unsigned short NumOperands = 0;
628 unsigned short NumValues;
629
630 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
631 // original LLVM instructions.
632 // This is used for turning off scheduling, because we'll forgo
633 // the normal scheduling algorithms and output the instructions according to
634 // this ordering.
635 unsigned IROrder;
636
637 /// Source line information.
638 DebugLoc debugLoc;
639
640 /// Return a pointer to the specified value type.
641 static const EVT *getValueTypeList(EVT VT);
642
643 SDNodeFlags Flags;
644
645public:
646 /// Unique and persistent id per SDNode in the DAG.
647 /// Used for debug printing.
648 uint16_t PersistentId;
649
650 //===--------------------------------------------------------------------===//
651 // Accessors
652 //
653
654 /// Return the SelectionDAG opcode value for this node. For
655 /// pre-isel nodes (those for which isMachineOpcode returns false), these
656 /// are the opcode values in the ISD and <target>ISD namespaces. For
657 /// post-isel opcodes, see getMachineOpcode.
658 unsigned getOpcode() const { return (unsigned short)NodeType; }
659
660 /// Test if this node has a target-specific opcode (in the
661 /// \<target\>ISD namespace).
662 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
663
664 /// Test if this node has a target-specific opcode that may raise
665 /// FP exceptions (in the \<target\>ISD namespace and greater than
666 /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
667 /// opcode are currently automatically considered to possibly raise
668 /// FP exceptions as well.
669 bool isTargetStrictFPOpcode() const {
670 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
671 }
672
673 /// Test if this node has a target-specific
674 /// memory-referencing opcode (in the \<target\>ISD namespace and
675 /// greater than FIRST_TARGET_MEMORY_OPCODE).
676 bool isTargetMemoryOpcode() const {
677 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
678 }
679
680 /// Return true if the type of the node type undefined.
681 bool isUndef() const { return NodeType == ISD::UNDEF; }
682
683 /// Test if this node is a memory intrinsic (with valid pointer information).
684 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
685 /// non-memory intrinsics (with chains) that are not really instances of
686 /// MemSDNode. For such nodes, we need some extra state to determine the
687 /// proper classof relationship.
688 bool isMemIntrinsic() const {
689 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
690 NodeType == ISD::INTRINSIC_VOID) &&
691 SDNodeBits.IsMemIntrinsic;
692 }
693
694 /// Test if this node is a strict floating point pseudo-op.
695 bool isStrictFPOpcode() {
696 switch (NodeType) {
697 default:
698 return false;
699 case ISD::STRICT_FP16_TO_FP:
700 case ISD::STRICT_FP_TO_FP16:
701#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
702 case ISD::STRICT_##DAGN:
703#include "llvm/IR/ConstrainedOps.def"
704 return true;
705 }
706 }
707
708 /// Test if this node has a post-isel opcode, directly
709 /// corresponding to a MachineInstr opcode.
710 bool isMachineOpcode() const { return NodeType < 0; }
711
712 /// This may only be called if isMachineOpcode returns
713 /// true. It returns the MachineInstr opcode value that the node's opcode
714 /// corresponds to.
715 unsigned getMachineOpcode() const {
716 assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 716, __PRETTY_FUNCTION__))
;
717 return ~NodeType;
718 }
719
720 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
721 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
722
723 bool isDivergent() const { return SDNodeBits.IsDivergent; }
724
725 /// Return true if there are no uses of this node.
726 bool use_empty() const { return UseList == nullptr; }
727
728 /// Return true if there is exactly one use of this node.
729 bool hasOneUse() const {
730 return !use_empty() && std::next(use_begin()) == use_end();
731 }
732
733 /// Return the number of uses of this node. This method takes
734 /// time proportional to the number of uses.
735 size_t use_size() const { return std::distance(use_begin(), use_end()); }
736
737 /// Return the unique node id.
738 int getNodeId() const { return NodeId; }
739
740 /// Set unique node id.
741 void setNodeId(int Id) { NodeId = Id; }
742
743 /// Return the node ordering.
744 unsigned getIROrder() const { return IROrder; }
745
746 /// Set the node ordering.
747 void setIROrder(unsigned Order) { IROrder = Order; }
748
749 /// Return the source location info.
750 const DebugLoc &getDebugLoc() const { return debugLoc; }
751
752 /// Set source location info. Try to avoid this, putting
753 /// it in the constructor is preferable.
754 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
755
756 /// This class provides iterator support for SDUse
757 /// operands that use a specific SDNode.
758 class use_iterator
759 : public std::iterator<std::forward_iterator_tag, SDUse, ptrdiff_t> {
760 friend class SDNode;
761
762 SDUse *Op = nullptr;
763
764 explicit use_iterator(SDUse *op) : Op(op) {}
765
766 public:
767 using reference = std::iterator<std::forward_iterator_tag,
768 SDUse, ptrdiff_t>::reference;
769 using pointer = std::iterator<std::forward_iterator_tag,
770 SDUse, ptrdiff_t>::pointer;
771
772 use_iterator() = default;
773 use_iterator(const use_iterator &I) : Op(I.Op) {}
774
775 bool operator==(const use_iterator &x) const {
776 return Op == x.Op;
777 }
778 bool operator!=(const use_iterator &x) const {
779 return !operator==(x);
780 }
781
782 /// Return true if this iterator is at the end of uses list.
783 bool atEnd() const { return Op == nullptr; }
784
785 // Iterator traversal: forward iteration only.
786 use_iterator &operator++() { // Preincrement
787 assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 787, __PRETTY_FUNCTION__))
;
788 Op = Op->getNext();
789 return *this;
790 }
791
792 use_iterator operator++(int) { // Postincrement
793 use_iterator tmp = *this; ++*this; return tmp;
794 }
795
796 /// Retrieve a pointer to the current user node.
797 SDNode *operator*() const {
798 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 798, __PRETTY_FUNCTION__))
;
799 return Op->getUser();
800 }
801
802 SDNode *operator->() const { return operator*(); }
803
804 SDUse &getUse() const { return *Op; }
805
806 /// Retrieve the operand # of this use in its user.
807 unsigned getOperandNo() const {
808 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 808, __PRETTY_FUNCTION__))
;
809 return (unsigned)(Op - Op->getUser()->OperandList);
810 }
811 };
812
813 /// Provide iteration support to walk over all uses of an SDNode.
814 use_iterator use_begin() const {
815 return use_iterator(UseList);
816 }
817
818 static use_iterator use_end() { return use_iterator(nullptr); }
819
820 inline iterator_range<use_iterator> uses() {
821 return make_range(use_begin(), use_end());
822 }
823 inline iterator_range<use_iterator> uses() const {
824 return make_range(use_begin(), use_end());
825 }
826
827 /// Return true if there are exactly NUSES uses of the indicated value.
828 /// This method ignores uses of other values defined by this operation.
829 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
830
831 /// Return true if there are any use of the indicated value.
832 /// This method ignores uses of other values defined by this operation.
833 bool hasAnyUseOfValue(unsigned Value) const;
834
835 /// Return true if this node is the only use of N.
836 bool isOnlyUserOf(const SDNode *N) const;
837
838 /// Return true if this node is an operand of N.
839 bool isOperandOf(const SDNode *N) const;
840
841 /// Return true if this node is a predecessor of N.
842 /// NOTE: Implemented on top of hasPredecessor and every bit as
843 /// expensive. Use carefully.
844 bool isPredecessorOf(const SDNode *N) const {
845 return N->hasPredecessor(this);
846 }
847
848 /// Return true if N is a predecessor of this node.
849 /// N is either an operand of this node, or can be reached by recursively
850 /// traversing up the operands.
851 /// NOTE: This is an expensive method. Use it carefully.
852 bool hasPredecessor(const SDNode *N) const;
853
854 /// Returns true if N is a predecessor of any node in Worklist. This
855 /// helper keeps Visited and Worklist sets externally to allow unions
856 /// searches to be performed in parallel, caching of results across
857 /// queries and incremental addition to Worklist. Stops early if N is
858 /// found but will resume. Remember to clear Visited and Worklists
859 /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
860 /// giving up. The TopologicalPrune flag signals that positive NodeIds are
861 /// topologically ordered (Operands have strictly smaller node id) and search
862 /// can be pruned leveraging this.
863 static bool hasPredecessorHelper(const SDNode *N,
864 SmallPtrSetImpl<const SDNode *> &Visited,
865 SmallVectorImpl<const SDNode *> &Worklist,
866 unsigned int MaxSteps = 0,
867 bool TopologicalPrune = false) {
868 SmallVector<const SDNode *, 8> DeferredNodes;
869 if (Visited.count(N))
870 return true;
871
872 // Node Id's are assigned in three places: As a topological
873 // ordering (> 0), during legalization (results in values set to
874 // 0), new nodes (set to -1). If N has a topolgical id then we
875 // know that all nodes with ids smaller than it cannot be
876 // successors and we need not check them. Filter out all node
877 // that can't be matches. We add them to the worklist before exit
878 // in case of multiple calls. Note that during selection the topological id
879 // may be violated if a node's predecessor is selected before it. We mark
880 // this at selection negating the id of unselected successors and
881 // restricting topological pruning to positive ids.
882
883 int NId = N->getNodeId();
884 // If we Invalidated the Id, reconstruct original NId.
885 if (NId < -1)
886 NId = -(NId + 1);
887
888 bool Found = false;
889 while (!Worklist.empty()) {
890 const SDNode *M = Worklist.pop_back_val();
891 int MId = M->getNodeId();
892 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
893 (MId > 0) && (MId < NId)) {
894 DeferredNodes.push_back(M);
895 continue;
896 }
897 for (const SDValue &OpV : M->op_values()) {
898 SDNode *Op = OpV.getNode();
899 if (Visited.insert(Op).second)
900 Worklist.push_back(Op);
901 if (Op == N)
902 Found = true;
903 }
904 if (Found)
905 break;
906 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
907 break;
908 }
909 // Push deferred nodes back on worklist.
910 Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
911 // If we bailed early, conservatively return found.
912 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
913 return true;
914 return Found;
915 }
916
917 /// Return true if all the users of N are contained in Nodes.
918 /// NOTE: Requires at least one match, but doesn't require them all.
919 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
920
921 /// Return the number of values used by this operation.
922 unsigned getNumOperands() const { return NumOperands; }
923
924 /// Return the maximum number of operands that a SDNode can hold.
925 static constexpr size_t getMaxNumOperands() {
926 return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
927 }
928
929 /// Helper method returns the integer value of a ConstantSDNode operand.
930 inline uint64_t getConstantOperandVal(unsigned Num) const;
931
932 /// Helper method returns the APInt of a ConstantSDNode operand.
933 inline const APInt &getConstantOperandAPInt(unsigned Num) const;
934
935 const SDValue &getOperand(unsigned Num) const {
936 assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 936, __PRETTY_FUNCTION__))
;
937 return OperandList[Num];
938 }
939
940 using op_iterator = SDUse *;
941
942 op_iterator op_begin() const { return OperandList; }
943 op_iterator op_end() const { return OperandList+NumOperands; }
944 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
945
946 /// Iterator for directly iterating over the operand SDValue's.
947 struct value_op_iterator
948 : iterator_adaptor_base<value_op_iterator, op_iterator,
949 std::random_access_iterator_tag, SDValue,
950 ptrdiff_t, value_op_iterator *,
951 value_op_iterator *> {
952 explicit value_op_iterator(SDUse *U = nullptr)
953 : iterator_adaptor_base(U) {}
954
955 const SDValue &operator*() const { return I->get(); }
956 };
957
958 iterator_range<value_op_iterator> op_values() const {
959 return make_range(value_op_iterator(op_begin()),
960 value_op_iterator(op_end()));
961 }
962
963 SDVTList getVTList() const {
964 SDVTList X = { ValueList, NumValues };
965 return X;
966 }
967
968 /// If this node has a glue operand, return the node
969 /// to which the glue operand points. Otherwise return NULL.
970 SDNode *getGluedNode() const {
971 if (getNumOperands() != 0 &&
972 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
973 return getOperand(getNumOperands()-1).getNode();
974 return nullptr;
975 }
976
977 /// If this node has a glue value with a user, return
978 /// the user (there is at most one). Otherwise return NULL.
979 SDNode *getGluedUser() const {
980 for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
981 if (UI.getUse().get().getValueType() == MVT::Glue)
982 return *UI;
983 return nullptr;
984 }
985
986 const SDNodeFlags getFlags() const { return Flags; }
987 void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
988
989 /// Clear any flags in this node that aren't also set in Flags.
990 /// If Flags is not in a defined state then this has no effect.
991 void intersectFlagsWith(const SDNodeFlags Flags);
992
993 /// Return the number of values defined/returned by this operator.
994 unsigned getNumValues() const { return NumValues; }
995
996 /// Return the type of a specified result.
997 EVT getValueType(unsigned ResNo) const {
998 assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ?
static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 998, __PRETTY_FUNCTION__))
;
999 return ValueList[ResNo];
1000 }
1001
1002 /// Return the type of a specified result as a simple type.
1003 MVT getSimpleValueType(unsigned ResNo) const {
1004 return getValueType(ResNo).getSimpleVT();
1005 }
1006
1007 /// Returns MVT::getSizeInBits(getValueType(ResNo)).
1008 ///
1009 /// If the value type is a scalable vector type, the scalable property will
1010 /// be set and the runtime size will be a positive integer multiple of the
1011 /// base size.
1012 TypeSize getValueSizeInBits(unsigned ResNo) const {
1013 return getValueType(ResNo).getSizeInBits();
1014 }
1015
1016 using value_iterator = const EVT *;
1017
1018 value_iterator value_begin() const { return ValueList; }
1019 value_iterator value_end() const { return ValueList+NumValues; }
1020 iterator_range<value_iterator> values() const {
1021 return llvm::make_range(value_begin(), value_end());
1022 }
1023
1024 /// Return the opcode of this operation for printing.
1025 std::string getOperationName(const SelectionDAG *G = nullptr) const;
1026 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1027 void print_types(raw_ostream &OS, const SelectionDAG *G) const;
1028 void print_details(raw_ostream &OS, const SelectionDAG *G) const;
1029 void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1030 void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1031
1032 /// Print a SelectionDAG node and all children down to
1033 /// the leaves. The given SelectionDAG allows target-specific nodes
1034 /// to be printed in human-readable form. Unlike printr, this will
1035 /// print the whole DAG, including children that appear multiple
1036 /// times.
1037 ///
1038 void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;
1039
1040 /// Print a SelectionDAG node and children up to
1041 /// depth "depth." The given SelectionDAG allows target-specific
1042 /// nodes to be printed in human-readable form. Unlike printr, this
1043 /// will print children that appear multiple times wherever they are
1044 /// used.
1045 ///
1046 void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
1047 unsigned depth = 100) const;
1048
1049 /// Dump this node, for debugging.
1050 void dump() const;
1051
1052 /// Dump (recursively) this node and its use-def subgraph.
1053 void dumpr() const;
1054
1055 /// Dump this node, for debugging.
1056 /// The given SelectionDAG allows target-specific nodes to be printed
1057 /// in human-readable form.
1058 void dump(const SelectionDAG *G) const;
1059
1060 /// Dump (recursively) this node and its use-def subgraph.
1061 /// The given SelectionDAG allows target-specific nodes to be printed
1062 /// in human-readable form.
1063 void dumpr(const SelectionDAG *G) const;
1064
1065 /// printrFull to dbgs(). The given SelectionDAG allows
1066 /// target-specific nodes to be printed in human-readable form.
1067 /// Unlike dumpr, this will print the whole DAG, including children
1068 /// that appear multiple times.
1069 void dumprFull(const SelectionDAG *G = nullptr) const;
1070
1071 /// printrWithDepth to dbgs(). The given
1072 /// SelectionDAG allows target-specific nodes to be printed in
1073 /// human-readable form. Unlike dumpr, this will print children
1074 /// that appear multiple times wherever they are used.
1075 ///
1076 void dumprWithDepth(const SelectionDAG *G = nullptr,
1077 unsigned depth = 100) const;
1078
1079 /// Gather unique data for the node.
1080 void Profile(FoldingSetNodeID &ID) const;
1081
1082 /// This method should only be used by the SDUse class.
1083 void addUse(SDUse &U) { U.addToList(&UseList); }
1084
1085protected:
1086 static SDVTList getSDVTList(EVT VT) {
1087 SDVTList Ret = { getValueTypeList(VT), 1 };
1088 return Ret;
1089 }
1090
1091 /// Create an SDNode.
1092 ///
1093 /// SDNodes are created without any operands, and never own the operand
1094 /// storage. To add operands, see SelectionDAG::createOperands.
1095 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1096 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1097 IROrder(Order), debugLoc(std::move(dl)) {
1098 memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
1099 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1099, __PRETTY_FUNCTION__))
;
1100 assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1101, __PRETTY_FUNCTION__))
1101 "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1101, __PRETTY_FUNCTION__))
;
1102 }
1103
1104 /// Release the operands and set this node to have zero operands.
1105 void DropOperands();
1106};
1107
1108/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1109/// into SDNode creation functions.
1110/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1111/// from the original Instruction, and IROrder is the ordinal position of
1112/// the instruction.
1113/// When an SDNode is created after the DAG is being built, both DebugLoc and
1114/// the IROrder are propagated from the original SDNode.
1115/// So SDLoc class provides two constructors besides the default one, one to
1116/// be used by the DAGBuilder, the other to be used by others.
1117class SDLoc {
1118private:
1119 DebugLoc DL;
1120 int IROrder = 0;
1121
1122public:
1123 SDLoc() = default;
1124 SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
1125 SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
1126 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1127 assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void
> (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1127, __PRETTY_FUNCTION__))
;
1128 if (I)
1129 DL = I->getDebugLoc();
1130 }
1131
1132 unsigned getIROrder() const { return IROrder; }
1133 const DebugLoc &getDebugLoc() const { return DL; }
1134};
1135
1136// Define inline functions from the SDValue class.
1137
1138inline SDValue::SDValue(SDNode *node, unsigned resno)
1139 : Node(node), ResNo(resno) {
1140 // Explicitly check for !ResNo to avoid use-after-free, because there are
1141 // callers that use SDValue(N, 0) with a deleted N to indicate successful
1142 // combines.
1143 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1144, __PRETTY_FUNCTION__))
1144 "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1144, __PRETTY_FUNCTION__))
;
1145 assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1145, __PRETTY_FUNCTION__))
;
1146}
1147
1148inline unsigned SDValue::getOpcode() const {
1149 return Node->getOpcode();
1150}
1151
1152inline EVT SDValue::getValueType() const {
1153 return Node->getValueType(ResNo);
1154}
1155
1156inline unsigned SDValue::getNumOperands() const {
1157 return Node->getNumOperands();
1158}
1159
1160inline const SDValue &SDValue::getOperand(unsigned i) const {
1161 return Node->getOperand(i);
1162}
1163
1164inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
1165 return Node->getConstantOperandVal(i);
1166}
1167
1168inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
1169 return Node->getConstantOperandAPInt(i);
1170}
1171
1172inline bool SDValue::isTargetOpcode() const {
1173 return Node->isTargetOpcode();
1174}
1175
1176inline bool SDValue::isTargetMemoryOpcode() const {
1177 return Node->isTargetMemoryOpcode();
1178}
1179
1180inline bool SDValue::isMachineOpcode() const {
1181 return Node->isMachineOpcode();
7
Called C++ object pointer is null
1182}
1183
1184inline unsigned SDValue::getMachineOpcode() const {
1185 return Node->getMachineOpcode();
1186}
1187
1188inline bool SDValue::isUndef() const {
1189 return Node->isUndef();
1190}
1191
1192inline bool SDValue::use_empty() const {
1193 return !Node->hasAnyUseOfValue(ResNo);
1194}
1195
1196inline bool SDValue::hasOneUse() const {
1197 return Node->hasNUsesOfValue(1, ResNo);
1198}
1199
1200inline const DebugLoc &SDValue::getDebugLoc() const {
1201 return Node->getDebugLoc();
1202}
1203
1204inline void SDValue::dump() const {
1205 return Node->dump();
1206}
1207
1208inline void SDValue::dump(const SelectionDAG *G) const {
1209 return Node->dump(G);
1210}
1211
1212inline void SDValue::dumpr() const {
1213 return Node->dumpr();
1214}
1215
1216inline void SDValue::dumpr(const SelectionDAG *G) const {
1217 return Node->dumpr(G);
1218}
1219
1220// Define inline functions from the SDUse class.
1221
1222inline void SDUse::set(const SDValue &V) {
1223 if (Val.getNode()) removeFromList();
1224 Val = V;
1225 if (V.getNode()) V.getNode()->addUse(*this);
1226}
1227
1228inline void SDUse::setInitial(const SDValue &V) {
1229 Val = V;
1230 V.getNode()->addUse(*this);
1231}
1232
1233inline void SDUse::setNode(SDNode *N) {
1234 if (Val.getNode()) removeFromList();
1235 Val.setNode(N);
1236 if (N) N->addUse(*this);
1237}
1238
1239/// This class is used to form a handle around another node that
1240/// is persistent and is updated across invocations of replaceAllUsesWith on its
1241/// operand. This node should be directly created by end-users and not added to
1242/// the AllNodes list.
1243class HandleSDNode : public SDNode {
1244 SDUse Op;
1245
1246public:
1247 explicit HandleSDNode(SDValue X)
1248 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
1249 // HandleSDNodes are never inserted into the DAG, so they won't be
1250 // auto-numbered. Use ID 65535 as a sentinel.
1251 PersistentId = 0xffff;
1252
1253 // Manually set up the operand list. This node type is special in that it's
1254 // always stack allocated and SelectionDAG does not manage its operands.
1255 // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
1256 // be so special.
1257 Op.setUser(this);
1258 Op.setInitial(X);
1259 NumOperands = 1;
1260 OperandList = &Op;
1261 }
1262 ~HandleSDNode();
1263
1264 const SDValue &getValue() const { return Op; }
1265};
1266
1267class AddrSpaceCastSDNode : public SDNode {
1268private:
1269 unsigned SrcAddrSpace;
1270 unsigned DestAddrSpace;
1271
1272public:
1273 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1274 unsigned SrcAS, unsigned DestAS);
1275
1276 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
1277 unsigned getDestAddressSpace() const { return DestAddrSpace; }
1278
1279 static bool classof(const SDNode *N) {
1280 return N->getOpcode() == ISD::ADDRSPACECAST;
1281 }
1282};
1283
1284/// This is an abstract virtual class for memory operations.
1285class MemSDNode : public SDNode {
1286private:
1287 // VT of in-memory value.
1288 EVT MemoryVT;
1289
1290protected:
1291 /// Memory reference information.
1292 MachineMemOperand *MMO;
1293
1294public:
1295 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1296 EVT memvt, MachineMemOperand *MMO);
1297
1298 bool readMem() const { return MMO->isLoad(); }
1299 bool writeMem() const { return MMO->isStore(); }
1300
1301 /// Returns alignment and volatility of the memory access
1302 unsigned getOriginalAlignment() const {
1303 return MMO->getBaseAlignment();
1304 }
1305 unsigned getAlignment() const {
1306 return MMO->getAlignment();
1307 }
1308
1309 /// Return the SubclassData value, without HasDebugValue. This contains an
1310 /// encoding of the volatile flag, as well as bits used by subclasses. This
1311 /// function should only be used to compute a FoldingSetNodeID value.
1312 /// The HasDebugValue bit is masked out because CSE map needs to match
1313 /// nodes with debug info with nodes without debug info. Same is about
1314 /// isDivergent bit.
1315 unsigned getRawSubclassData() const {
1316 uint16_t Data;
1317 union {
1318 char RawSDNodeBits[sizeof(uint16_t)];
1319 SDNodeBitfields SDNodeBits;
1320 };
1321 memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
1322 SDNodeBits.HasDebugValue = 0;
1323 SDNodeBits.IsDivergent = false;
1324 memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
1325 return Data;
1326 }
1327
1328 bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
1329 bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
1330 bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
1331 bool isInvariant() const { return MemSDNodeBits.IsInvariant; }
1332
1333 // Returns the offset from the location of the access.
1334 int64_t getSrcValueOffset() const { return MMO->getOffset(); }
1335
1336 /// Returns the AA info that describes the dereference.
1337 AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }
1338
1339 /// Returns the Ranges that describes the dereference.
1340 const MDNode *getRanges() const { return MMO->getRanges(); }
1341
1342 /// Returns the synchronization scope ID for this memory operation.
1343 SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }
1344
1345 /// Return the atomic ordering requirements for this memory operation. For
1346 /// cmpxchg atomic operations, return the atomic ordering requirements when
1347 /// store occurs.
1348 AtomicOrdering getOrdering() const { return MMO->getOrdering(); }
1349
1350 /// Return true if the memory operation ordering is Unordered or higher.
1351 bool isAtomic() const { return MMO->isAtomic(); }
1352
1353 /// Returns true if the memory operation doesn't imply any ordering
1354 /// constraints on surrounding memory operations beyond the normal memory
1355 /// aliasing rules.
1356 bool isUnordered() const { return MMO->isUnordered(); }
1357
1358 /// Returns true if the memory operation is neither atomic or volatile.
1359 bool isSimple() const { return !isAtomic() && !isVolatile(); }
1360
1361 /// Return the type of the in-memory value.
1362 EVT getMemoryVT() const { return MemoryVT; }
1363
1364 /// Return a MachineMemOperand object describing the memory
1365 /// reference performed by operation.
1366 MachineMemOperand *getMemOperand() const { return MMO; }
1367
1368 const MachinePointerInfo &getPointerInfo() const {
1369 return MMO->getPointerInfo();
1370 }
1371
1372 /// Return the address space for the associated pointer
1373 unsigned getAddressSpace() const {
1374 return getPointerInfo().getAddrSpace();
1375 }
1376
1377 /// Update this MemSDNode's MachineMemOperand information
1378 /// to reflect the alignment of NewMMO, if it has a greater alignment.
1379 /// This must only be used when the new alignment applies to all users of
1380 /// this MachineMemOperand.
1381 void refineAlignment(const MachineMemOperand *NewMMO) {
1382 MMO->refineAlignment(NewMMO);
1383 }
1384
1385 const SDValue &getChain() const { return getOperand(0); }
1386 const SDValue &getBasePtr() const {
1387 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1388 }
1389
1390 // Methods to support isa and dyn_cast
1391 static bool classof(const SDNode *N) {
1392 // For some targets, we lower some target intrinsics to a MemIntrinsicNode
1393 // with either an intrinsic or a target opcode.
1394 return N->getOpcode() == ISD::LOAD ||
1395 N->getOpcode() == ISD::STORE ||
1396 N->getOpcode() == ISD::PREFETCH ||
1397 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1398 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1399 N->getOpcode() == ISD::ATOMIC_SWAP ||
1400 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1401 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1402 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1403 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1404 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1405 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1406 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1407 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1408 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1409 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1410 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1411 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1412 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1413 N->getOpcode() == ISD::ATOMIC_LOAD ||
1414 N->getOpcode() == ISD::ATOMIC_STORE ||
1415 N->getOpcode() == ISD::MLOAD ||
1416 N->getOpcode() == ISD::MSTORE ||
1417 N->getOpcode() == ISD::MGATHER ||
1418 N->getOpcode() == ISD::MSCATTER ||
1419 N->isMemIntrinsic() ||
1420 N->isTargetMemoryOpcode();
1421 }
1422};
1423
1424/// This is an SDNode representing atomic operations.
1425class AtomicSDNode : public MemSDNode {
1426public:
1427 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
1428 EVT MemVT, MachineMemOperand *MMO)
1429 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
1430 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1431, __PRETTY_FUNCTION__))
1431 MMO->isAtomic()) && "then why are we using an AtomicSDNode?")((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1431, __PRETTY_FUNCTION__))
;
1432 }
1433
1434 const SDValue &getBasePtr() const { return getOperand(1); }
1435 const SDValue &getVal() const { return getOperand(2); }
1436
1437 /// Returns true if this SDNode represents cmpxchg atomic operation, false
1438 /// otherwise.
1439 bool isCompareAndSwap() const {
1440 unsigned Op = getOpcode();
1441 return Op == ISD::ATOMIC_CMP_SWAP ||
1442 Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
1443 }
1444
1445 /// For cmpxchg atomic operations, return the atomic ordering requirements
1446 /// when store does not occur.
1447 AtomicOrdering getFailureOrdering() const {
1448 assert(isCompareAndSwap() && "Must be cmpxchg operation")((isCompareAndSwap() && "Must be cmpxchg operation") ?
static_cast<void> (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1448, __PRETTY_FUNCTION__))
;
1449 return MMO->getFailureOrdering();
1450 }
1451
1452 // Methods to support isa and dyn_cast
1453 static bool classof(const SDNode *N) {
1454 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1455 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1456 N->getOpcode() == ISD::ATOMIC_SWAP ||
1457 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1458 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1459 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1460 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1461 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1462 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1463 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1464 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1465 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1466 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1467 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1468 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1469 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1470 N->getOpcode() == ISD::ATOMIC_LOAD ||
1471 N->getOpcode() == ISD::ATOMIC_STORE;
1472 }
1473};
1474
1475/// This SDNode is used for target intrinsics that touch
1476/// memory and need an associated MachineMemOperand. Its opcode may be
1477/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1478/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1479class MemIntrinsicSDNode : public MemSDNode {
1480public:
1481 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1482 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
1483 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
1484 SDNodeBits.IsMemIntrinsic = true;
1485 }
1486
1487 // Methods to support isa and dyn_cast
1488 static bool classof(const SDNode *N) {
1489 // We lower some target intrinsics to their target opcode
1490 // early a node with a target opcode can be of this class
1491 return N->isMemIntrinsic() ||
1492 N->getOpcode() == ISD::PREFETCH ||
1493 N->isTargetMemoryOpcode();
1494 }
1495};
1496
1497/// This SDNode is used to implement the code generator
1498/// support for the llvm IR shufflevector instruction. It combines elements
1499/// from two input vectors into a new input vector, with the selection and
1500/// ordering of elements determined by an array of integers, referred to as
1501/// the shuffle mask. For input vectors of width N, mask indices of 0..N-1
1502/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1503/// An index of -1 is treated as undef, such that the code generator may put
1504/// any value in the corresponding element of the result.
1505class ShuffleVectorSDNode : public SDNode {
1506 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
1507 // is freed when the SelectionDAG object is destroyed.
1508 const int *Mask;
1509
1510protected:
1511 friend class SelectionDAG;
1512
1513 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
1514 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1515
1516public:
1517 ArrayRef<int> getMask() const {
1518 EVT VT = getValueType(0);
1519 return makeArrayRef(Mask, VT.getVectorNumElements());
1520 }
1521
1522 int getMaskElt(unsigned Idx) const {
1523 assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")((Idx < getValueType(0).getVectorNumElements() && "Idx out of range!"
) ? static_cast<void> (0) : __assert_fail ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1523, __PRETTY_FUNCTION__))
;
1524 return Mask[Idx];
1525 }
1526
1527 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
1528
1529 int getSplatIndex() const {
1530 assert(isSplat() && "Cannot get splat index for non-splat!")((isSplat() && "Cannot get splat index for non-splat!"
) ? static_cast<void> (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1530, __PRETTY_FUNCTION__))
;
1531 EVT VT = getValueType(0);
1532 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
1533 if (Mask[i] >= 0)
1534 return Mask[i];
1535
1536 // We can choose any index value here and be correct because all elements
1537 // are undefined. Return 0 for better potential for callers to simplify.
1538 return 0;
1539 }
1540
1541 static bool isSplatMask(const int *Mask, EVT VT);
1542
1543 /// Change values in a shuffle permute mask assuming
1544 /// the two vector operands have swapped position.
1545 static void commuteMask(MutableArrayRef<int> Mask) {
1546 unsigned NumElems = Mask.size();
1547 for (unsigned i = 0; i != NumElems; ++i) {
1548 int idx = Mask[i];
1549 if (idx < 0)
1550 continue;
1551 else if (idx < (int)NumElems)
1552 Mask[i] = idx + NumElems;
1553 else
1554 Mask[i] = idx - NumElems;
1555 }
1556 }
1557
1558 static bool classof(const SDNode *N) {
1559 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
1560 }
1561};
1562
1563class ConstantSDNode : public SDNode {
1564 friend class SelectionDAG;
1565
1566 const ConstantInt *Value;
1567
1568 ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
1569 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
1570 getSDVTList(VT)),
1571 Value(val) {
1572 ConstantSDNodeBits.IsOpaque = isOpaque;
1573 }
1574
1575public:
1576 const ConstantInt *getConstantIntValue() const { return Value; }
1577 const APInt &getAPIntValue() const { return Value->getValue(); }
1578 uint64_t getZExtValue() const { return Value->getZExtValue(); }
1579 int64_t getSExtValue() const { return Value->getSExtValue(); }
1580 uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) {
1581 return Value->getLimitedValue(Limit);
1582 }
1583
1584 bool isOne() const { return Value->isOne(); }
1585 bool isNullValue() const { return Value->isZero(); }
1586 bool isAllOnesValue() const { return Value->isMinusOne(); }
1587
1588 bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }
1589
1590 static bool classof(const SDNode *N) {
1591 return N->getOpcode() == ISD::Constant ||
1592 N->getOpcode() == ISD::TargetConstant;
1593 }
1594};
1595
1596uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
1597 return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1598}
1599
1600const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
1601 return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
1602}
1603
1604class ConstantFPSDNode : public SDNode {
1605 friend class SelectionDAG;
1606
1607 const ConstantFP *Value;
1608
1609 ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
1610 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
1611 DebugLoc(), getSDVTList(VT)),
1612 Value(val) {}
1613
1614public:
1615 const APFloat& getValueAPF() const { return Value->getValueAPF(); }
1616 const ConstantFP *getConstantFPValue() const { return Value; }
1617
1618 /// Return true if the value is positive or negative zero.
1619 bool isZero() const { return Value->isZero(); }
1620
1621 /// Return true if the value is a NaN.
1622 bool isNaN() const { return Value->isNaN(); }
1623
1624 /// Return true if the value is an infinity
1625 bool isInfinity() const { return Value->isInfinity(); }
1626
1627 /// Return true if the value is negative.
1628 bool isNegative() const { return Value->isNegative(); }
1629
1630 /// We don't rely on operator== working on double values, as
1631 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
1632 /// As such, this method can be used to do an exact bit-for-bit comparison of
1633 /// two floating point values.
1634
1635 /// We leave the version with the double argument here because it's just so
1636 /// convenient to write "2.0" and the like. Without this function we'd
1637 /// have to duplicate its logic everywhere it's called.
1638 bool isExactlyValue(double V) const {
1639 return Value->getValueAPF().isExactlyValue(V);
1640 }
1641 bool isExactlyValue(const APFloat& V) const;
1642
1643 static bool isValueValidForType(EVT VT, const APFloat& Val);
1644
1645 static bool classof(const SDNode *N) {
1646 return N->getOpcode() == ISD::ConstantFP ||
1647 N->getOpcode() == ISD::TargetConstantFP;
1648 }
1649};
1650
1651/// Returns true if \p V is a constant integer zero.
1652bool isNullConstant(SDValue V);
1653
1654/// Returns true if \p V is an FP constant with a value of positive zero.
1655bool isNullFPConstant(SDValue V);
1656
1657/// Returns true if \p V is an integer constant with all bits set.
1658bool isAllOnesConstant(SDValue V);
1659
1660/// Returns true if \p V is a constant integer one.
1661bool isOneConstant(SDValue V);
1662
1663/// Return the non-bitcasted source operand of \p V if it exists.
1664/// If \p V is not a bitcasted value, it is returned as-is.
1665SDValue peekThroughBitcasts(SDValue V);
1666
1667/// Return the non-bitcasted and one-use source operand of \p V if it exists.
1668/// If \p V is not a bitcasted one-use value, it is returned as-is.
1669SDValue peekThroughOneUseBitcasts(SDValue V);
1670
1671/// Return the non-extracted vector source operand of \p V if it exists.
1672/// If \p V is not an extracted subvector, it is returned as-is.
1673SDValue peekThroughExtractSubvectors(SDValue V);
1674
1675/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1676/// constant is canonicalized to be operand 1.
1677bool isBitwiseNot(SDValue V, bool AllowUndefs = false);
1678
1679/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1680ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false,
1681 bool AllowTruncation = false);
1682
1683/// Returns the SDNode if it is a demanded constant splat BuildVector or
1684/// constant int.
1685ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
1686 bool AllowUndefs = false,
1687 bool AllowTruncation = false);
1688
1689/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1690ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false);
1691
1692/// Returns the SDNode if it is a demanded constant splat BuildVector or
1693/// constant float.
1694ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts,
1695 bool AllowUndefs = false);
1696
1697/// Return true if the value is a constant 0 integer or a splatted vector of
1698/// a constant 0 integer (with no undefs by default).
1699/// Build vector implicit truncation is not an issue for null values.
1700bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false);
1701
1702/// Return true if the value is a constant 1 integer or a splatted vector of a
1703/// constant 1 integer (with no undefs).
1704/// Does not permit build vector implicit truncation.
1705bool isOneOrOneSplat(SDValue V);
1706
1707/// Return true if the value is a constant -1 integer or a splatted vector of a
1708/// constant -1 integer (with no undefs).
1709/// Does not permit build vector implicit truncation.
1710bool isAllOnesOrAllOnesSplat(SDValue V);
1711
1712class GlobalAddressSDNode : public SDNode {
1713 friend class SelectionDAG;
1714
1715 const GlobalValue *TheGlobal;
1716 int64_t Offset;
1717 unsigned TargetFlags;
1718
1719 GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
1720 const GlobalValue *GA, EVT VT, int64_t o,
1721 unsigned TF);
1722
1723public:
1724 const GlobalValue *getGlobal() const { return TheGlobal; }
1725 int64_t getOffset() const { return Offset; }
1726 unsigned getTargetFlags() const { return TargetFlags; }
1727 // Return the address space this GlobalAddress belongs to.
1728 unsigned getAddressSpace() const;
1729
1730 static bool classof(const SDNode *N) {
1731 return N->getOpcode() == ISD::GlobalAddress ||
1732 N->getOpcode() == ISD::TargetGlobalAddress ||
1733 N->getOpcode() == ISD::GlobalTLSAddress ||
1734 N->getOpcode() == ISD::TargetGlobalTLSAddress;
1735 }
1736};
1737
1738class FrameIndexSDNode : public SDNode {
1739 friend class SelectionDAG;
1740
1741 int FI;
1742
1743 FrameIndexSDNode(int fi, EVT VT, bool isTarg)
1744 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1745 0, DebugLoc(), getSDVTList(VT)), FI(fi) {
1746 }
1747
1748public:
1749 int getIndex() const { return FI; }
1750
1751 static bool classof(const SDNode *N) {
1752 return N->getOpcode() == ISD::FrameIndex ||
1753 N->getOpcode() == ISD::TargetFrameIndex;
1754 }
1755};
1756
1757/// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate
1758/// the offet and size that are started/ended in the underlying FrameIndex.
1759class LifetimeSDNode : public SDNode {
1760 friend class SelectionDAG;
1761 int64_t Size;
1762 int64_t Offset; // -1 if offset is unknown.
1763
1764 LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
1765 SDVTList VTs, int64_t Size, int64_t Offset)
1766 : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {}
1767public:
1768 int64_t getFrameIndex() const {
1769 return cast<FrameIndexSDNode>(getOperand(1))->getIndex();
1770 }
1771
1772 bool hasOffset() const { return Offset >= 0; }
1773 int64_t getOffset() const {
1774 assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1774, __PRETTY_FUNCTION__))
;
1775 return Offset;
1776 }
1777 int64_t getSize() const {
1778 assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1778, __PRETTY_FUNCTION__))
;
1779 return Size;
1780 }
1781
1782 // Methods to support isa and dyn_cast
1783 static bool classof(const SDNode *N) {
1784 return N->getOpcode() == ISD::LIFETIME_START ||
1785 N->getOpcode() == ISD::LIFETIME_END;
1786 }
1787};
1788
1789class JumpTableSDNode : public SDNode {
1790 friend class SelectionDAG;
1791
1792 int JTI;
1793 unsigned TargetFlags;
1794
1795 JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF)
1796 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
1797 0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
1798 }
1799
1800public:
1801 int getIndex() const { return JTI; }
1802 unsigned getTargetFlags() const { return TargetFlags; }
1803
1804 static bool classof(const SDNode *N) {
1805 return N->getOpcode() == ISD::JumpTable ||
1806 N->getOpcode() == ISD::TargetJumpTable;
1807 }
1808};
1809
1810class ConstantPoolSDNode : public SDNode {
1811 friend class SelectionDAG;
1812
1813 union {
1814 const Constant *ConstVal;
1815 MachineConstantPoolValue *MachineCPVal;
1816 } Val;
1817 int Offset; // It's a MachineConstantPoolValue if top bit is set.
1818 unsigned Alignment; // Minimum alignment requirement of CP (not log2 value).
1819 unsigned TargetFlags;
1820
1821 ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
1822 unsigned Align, unsigned TF)
1823 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1824 DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
1825 TargetFlags(TF) {
1826 assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1826, __PRETTY_FUNCTION__))
;
1827 Val.ConstVal = c;
1828 }
1829
1830 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
1831 EVT VT, int o, unsigned Align, unsigned TF)
1832 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1833 DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
1834 TargetFlags(TF) {
1835 assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1835, __PRETTY_FUNCTION__))
;
1836 Val.MachineCPVal = v;
1837 Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
1838 }
1839
1840public:
1841 bool isMachineConstantPoolEntry() const {
1842 return Offset < 0;
1843 }
1844
1845 const Constant *getConstVal() const {
1846 assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")((!isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1846, __PRETTY_FUNCTION__))
;
1847 return Val.ConstVal;
1848 }
1849
1850 MachineConstantPoolValue *getMachineCPVal() const {
1851 assert(isMachineConstantPoolEntry() && "Wrong constantpool type")((isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1851, __PRETTY_FUNCTION__))
;
1852 return Val.MachineCPVal;
1853 }
1854
1855 int getOffset() const {
1856 return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
1857 }
1858
1859 // Return the alignment of this constant pool object, which is either 0 (for
1860 // default alignment) or the desired value.
1861 unsigned getAlignment() const { return Alignment; }
1862 unsigned getTargetFlags() const { return TargetFlags; }
1863
1864 Type *getType() const;
1865
1866 static bool classof(const SDNode *N) {
1867 return N->getOpcode() == ISD::ConstantPool ||
1868 N->getOpcode() == ISD::TargetConstantPool;
1869 }
1870};
1871
1872/// Completely target-dependent object reference.
1873class TargetIndexSDNode : public SDNode {
1874 friend class SelectionDAG;
1875
1876 unsigned TargetFlags;
1877 int Index;
1878 int64_t Offset;
1879
1880public:
1881 TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF)
1882 : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
1883 TargetFlags(TF), Index(Idx), Offset(Ofs) {}
1884
1885 unsigned getTargetFlags() const { return TargetFlags; }
1886 int getIndex() const { return Index; }
1887 int64_t getOffset() const { return Offset; }
1888
1889 static bool classof(const SDNode *N) {
1890 return N->getOpcode() == ISD::TargetIndex;
1891 }
1892};
1893
1894class BasicBlockSDNode : public SDNode {
1895 friend class SelectionDAG;
1896
1897 MachineBasicBlock *MBB;
1898
1899 /// Debug info is meaningful and potentially useful here, but we create
1900 /// blocks out of order when they're jumped to, which makes it a bit
1901 /// harder. Let's see if we need it first.
1902 explicit BasicBlockSDNode(MachineBasicBlock *mbb)
1903 : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
1904 {}
1905
1906public:
1907 MachineBasicBlock *getBasicBlock() const { return MBB; }
1908
1909 static bool classof(const SDNode *N) {
1910 return N->getOpcode() == ISD::BasicBlock;
1911 }
1912};
1913
1914/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1915class BuildVectorSDNode : public SDNode {
1916public:
1917 // These are constructed as SDNodes and then cast to BuildVectorSDNodes.
1918 explicit BuildVectorSDNode() = delete;
1919
1920 /// Check if this is a constant splat, and if so, find the
1921 /// smallest element size that splats the vector. If MinSplatBits is
1922 /// nonzero, the element size must be at least that large. Note that the
1923 /// splat element may be the entire vector (i.e., a one element vector).
1924 /// Returns the splat element value in SplatValue. Any undefined bits in
1925 /// that value are zero, and the corresponding bits in the SplatUndef mask
1926 /// are set. The SplatBitSize value is set to the splat element size in
1927 /// bits. HasAnyUndefs is set to true if any bits in the vector are
1928 /// undefined. isBigEndian describes the endianness of the target.
1929 bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
1930 unsigned &SplatBitSize, bool &HasAnyUndefs,
1931 unsigned MinSplatBits = 0,
1932 bool isBigEndian = false) const;
1933
1934 /// Returns the demanded splatted value or a null value if this is not a
1935 /// splat.
1936 ///
1937 /// The DemandedElts mask indicates the elements that must be in the splat.
1938 /// If passed a non-null UndefElements bitvector, it will resize it to match
1939 /// the vector width and set the bits where elements are undef.
1940 SDValue getSplatValue(const APInt &DemandedElts,
1941 BitVector *UndefElements = nullptr) const;
1942
1943 /// Returns the splatted value or a null value if this is not a splat.
1944 ///
1945 /// If passed a non-null UndefElements bitvector, it will resize it to match
1946 /// the vector width and set the bits where elements are undef.
1947 SDValue getSplatValue(BitVector *UndefElements = nullptr) const;
1948
1949 /// Returns the demanded splatted constant or null if this is not a constant
1950 /// splat.
1951 ///
1952 /// The DemandedElts mask indicates the elements that must be in the splat.
1953 /// If passed a non-null UndefElements bitvector, it will resize it to match
1954 /// the vector width and set the bits where elements are undef.
1955 ConstantSDNode *
1956 getConstantSplatNode(const APInt &DemandedElts,
1957 BitVector *UndefElements = nullptr) const;
1958
1959 /// Returns the splatted constant or null if this is not a constant
1960 /// splat.
1961 ///
1962 /// If passed a non-null UndefElements bitvector, it will resize it to match
1963 /// the vector width and set the bits where elements are undef.
1964 ConstantSDNode *
1965 getConstantSplatNode(BitVector *UndefElements = nullptr) const;
1966
1967 /// Returns the demanded splatted constant FP or null if this is not a
1968 /// constant FP splat.
1969 ///
1970 /// The DemandedElts mask indicates the elements that must be in the splat.
1971 /// If passed a non-null UndefElements bitvector, it will resize it to match
1972 /// the vector width and set the bits where elements are undef.
1973 ConstantFPSDNode *
1974 getConstantFPSplatNode(const APInt &DemandedElts,
1975 BitVector *UndefElements = nullptr) const;
1976
1977 /// Returns the splatted constant FP or null if this is not a constant
1978 /// FP splat.
1979 ///
1980 /// If passed a non-null UndefElements bitvector, it will resize it to match
1981 /// the vector width and set the bits where elements are undef.
1982 ConstantFPSDNode *
1983 getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;
1984
1985 /// If this is a constant FP splat and the splatted constant FP is an
1986 /// exact power or 2, return the log base 2 integer value. Otherwise,
1987 /// return -1.
1988 ///
1989 /// The BitWidth specifies the necessary bit precision.
1990 int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
1991 uint32_t BitWidth) const;
1992
1993 bool isConstant() const;
1994
1995 static bool classof(const SDNode *N) {
1996 return N->getOpcode() == ISD::BUILD_VECTOR;
1997 }
1998};
1999
2000/// An SDNode that holds an arbitrary LLVM IR Value. This is
2001/// used when the SelectionDAG needs to make a simple reference to something
2002/// in the LLVM IR representation.
2003///
2004class SrcValueSDNode : public SDNode {
2005 friend class SelectionDAG;
2006
2007 const Value *V;
2008
2009 /// Create a SrcValue for a general value.
2010 explicit SrcValueSDNode(const Value *v)
2011 : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}
2012
2013public:
2014 /// Return the contained Value.
2015 const Value *getValue() const { return V; }
2016
2017 static bool classof(const SDNode *N) {
2018 return N->getOpcode() == ISD::SRCVALUE;
2019 }
2020};
2021
2022class MDNodeSDNode : public SDNode {
2023 friend class SelectionDAG;
2024
2025 const MDNode *MD;
2026
2027 explicit MDNodeSDNode(const MDNode *md)
2028 : SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
2029 {}
2030
2031public:
2032 const MDNode *getMD() const { return MD; }
2033
2034 static bool classof(const SDNode *N) {
2035 return N->getOpcode() == ISD::MDNODE_SDNODE;
2036 }
2037};
2038
2039class RegisterSDNode : public SDNode {
2040 friend class SelectionDAG;
2041
2042 unsigned Reg;
2043
2044 RegisterSDNode(unsigned reg, EVT VT)
2045 : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}
2046
2047public:
2048 unsigned getReg() const { return Reg; }
2049
2050 static bool classof(const SDNode *N) {
2051 return N->getOpcode() == ISD::Register;
2052 }
2053};
2054
2055class RegisterMaskSDNode : public SDNode {
2056 friend class SelectionDAG;
2057
2058 // The memory for RegMask is not owned by the node.
2059 const uint32_t *RegMask;
2060
2061 RegisterMaskSDNode(const uint32_t *mask)
2062 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
2063 RegMask(mask) {}
2064
2065public:
2066 const uint32_t *getRegMask() const { return RegMask; }
2067
2068 static bool classof(const SDNode *N) {
2069 return N->getOpcode() == ISD::RegisterMask;
2070 }
2071};
2072
2073class BlockAddressSDNode : public SDNode {
2074 friend class SelectionDAG;
2075
2076 const BlockAddress *BA;
2077 int64_t Offset;
2078 unsigned TargetFlags;
2079
2080 BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
2081 int64_t o, unsigned Flags)
2082 : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
2083 BA(ba), Offset(o), TargetFlags(Flags) {}
2084
2085public:
2086 const BlockAddress *getBlockAddress() const { return BA; }
2087 int64_t getOffset() const { return Offset; }
2088 unsigned getTargetFlags() const { return TargetFlags; }
2089
2090 static bool classof(const SDNode *N) {
2091 return N->getOpcode() == ISD::BlockAddress ||
2092 N->getOpcode() == ISD::TargetBlockAddress;
2093 }
2094};
2095
2096class LabelSDNode : public SDNode {
2097 friend class SelectionDAG;
2098
2099 MCSymbol *Label;
2100
2101 LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L)
2102 : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) {
2103 assert(LabelSDNode::classof(this) && "not a label opcode")((LabelSDNode::classof(this) && "not a label opcode")
? static_cast<void> (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2103, __PRETTY_FUNCTION__))
;
2104 }
2105
2106public:
2107 MCSymbol *getLabel() const { return Label; }
2108
2109 static bool classof(const SDNode *N) {
2110 return N->getOpcode() == ISD::EH_LABEL ||
2111 N->getOpcode() == ISD::ANNOTATION_LABEL;
2112 }
2113};
2114
2115class ExternalSymbolSDNode : public SDNode {
2116 friend class SelectionDAG;
2117
2118 const char *Symbol;
2119 unsigned TargetFlags;
2120
2121 ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT)
2122 : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0,
2123 DebugLoc(), getSDVTList(VT)),
2124 Symbol(Sym), TargetFlags(TF) {}
2125
2126public:
2127 const char *getSymbol() const { return Symbol; }
2128 unsigned getTargetFlags() const { return TargetFlags; }
2129
2130 static bool classof(const SDNode *N) {
2131 return N->getOpcode() == ISD::ExternalSymbol ||
2132 N->getOpcode() == ISD::TargetExternalSymbol;
2133 }
2134};
2135
2136class MCSymbolSDNode : public SDNode {
2137 friend class SelectionDAG;
2138
2139 MCSymbol *Symbol;
2140
2141 MCSymbolSDNode(MCSymbol *Symbol, EVT VT)
2142 : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {}
2143
2144public:
2145 MCSymbol *getMCSymbol() const { return Symbol; }
2146
2147 static bool classof(const SDNode *N) {
2148 return N->getOpcode() == ISD::MCSymbol;
2149 }
2150};
2151
2152class CondCodeSDNode : public SDNode {
2153 friend class SelectionDAG;
2154
2155 ISD::CondCode Condition;
2156
2157 explicit CondCodeSDNode(ISD::CondCode Cond)
2158 : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2159 Condition(Cond) {}
2160
2161public:
2162 ISD::CondCode get() const { return Condition; }
2163
2164 static bool classof(const SDNode *N) {
2165 return N->getOpcode() == ISD::CONDCODE;
2166 }
2167};
2168
2169/// This class is used to represent EVT's, which are used
2170/// to parameterize some operations.
2171class VTSDNode : public SDNode {
2172 friend class SelectionDAG;
2173
2174 EVT ValueType;
2175
2176 explicit VTSDNode(EVT VT)
2177 : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2178 ValueType(VT) {}
2179
2180public:
2181 EVT getVT() const { return ValueType; }
2182
2183 static bool classof(const SDNode *N) {
2184 return N->getOpcode() == ISD::VALUETYPE;
2185 }
2186};
2187
2188/// Base class for LoadSDNode and StoreSDNode
2189class LSBaseSDNode : public MemSDNode {
2190public:
2191 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
2192 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2193 MachineMemOperand *MMO)
2194 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2195 LSBaseSDNodeBits.AddressingMode = AM;
2196 assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2196, __PRETTY_FUNCTION__))
;
2197 }
2198
2199 const SDValue &getOffset() const {
2200 return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
2201 }
2202
2203 /// Return the addressing mode for this load or store:
2204 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2205 ISD::MemIndexedMode getAddressingMode() const {
2206 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2207 }
2208
2209 /// Return true if this is a pre/post inc/dec load/store.
2210 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2211
2212 /// Return true if this is NOT a pre/post inc/dec load/store.
2213 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2214
2215 static bool classof(const SDNode *N) {
2216 return N->getOpcode() == ISD::LOAD ||
2217 N->getOpcode() == ISD::STORE;
2218 }
2219};
2220
2221/// This class is used to represent ISD::LOAD nodes.
2222class LoadSDNode : public LSBaseSDNode {
2223 friend class SelectionDAG;
2224
2225 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2226 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2227 MachineMemOperand *MMO)
2228 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2229 LoadSDNodeBits.ExtTy = ETy;
2230 assert(readMem() && "Load MachineMemOperand is not a load!")((readMem() && "Load MachineMemOperand is not a load!"
) ? static_cast<void> (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2230, __PRETTY_FUNCTION__))
;
2231 assert(!writeMem() && "Load MachineMemOperand is a store!")((!writeMem() && "Load MachineMemOperand is a store!"
) ? static_cast<void> (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2231, __PRETTY_FUNCTION__))
;
2232 }
2233
2234public:
2235 /// Return whether this is a plain node,
2236 /// or one of the varieties of value-extending loads.
2237 ISD::LoadExtType getExtensionType() const {
2238 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2239 }
2240
2241 const SDValue &getBasePtr() const { return getOperand(1); }
2242 const SDValue &getOffset() const { return getOperand(2); }
2243
2244 static bool classof(const SDNode *N) {
2245 return N->getOpcode() == ISD::LOAD;
2246 }
2247};
2248
2249/// This class is used to represent ISD::STORE nodes.
2250class StoreSDNode : public LSBaseSDNode {
2251 friend class SelectionDAG;
2252
2253 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2254 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2255 MachineMemOperand *MMO)
2256 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2257 StoreSDNodeBits.IsTruncating = isTrunc;
2258 assert(!readMem() && "Store MachineMemOperand is a load!")((!readMem() && "Store MachineMemOperand is a load!")
? static_cast<void> (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2258, __PRETTY_FUNCTION__))
;
2259 assert(writeMem() && "Store MachineMemOperand is not a store!")((writeMem() && "Store MachineMemOperand is not a store!"
) ? static_cast<void> (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2259, __PRETTY_FUNCTION__))
;
2260 }
2261
2262public:
2263 /// Return true if the op does a truncation before store.
2264 /// For integers this is the same as doing a TRUNCATE and storing the result.
2265 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2266 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2267 void setTruncatingStore(bool Truncating) {
2268 StoreSDNodeBits.IsTruncating = Truncating;
2269 }
2270
2271 const SDValue &getValue() const { return getOperand(1); }
2272 const SDValue &getBasePtr() const { return getOperand(2); }
2273 const SDValue &getOffset() const { return getOperand(3); }
2274
2275 static bool classof(const SDNode *N) {
2276 return N->getOpcode() == ISD::STORE;
2277 }
2278};
2279
2280/// This base class is used to represent MLOAD and MSTORE nodes
2281class MaskedLoadStoreSDNode : public MemSDNode {
2282public:
2283 friend class SelectionDAG;
2284
2285 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
2286 const DebugLoc &dl, SDVTList VTs,
2287 ISD::MemIndexedMode AM, EVT MemVT,
2288 MachineMemOperand *MMO)
2289 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2290 LSBaseSDNodeBits.AddressingMode = AM;
2291 assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2291, __PRETTY_FUNCTION__))
;
2292 }
2293
2294 // MaskedLoadSDNode (Chain, ptr, offset, mask, passthru)
2295 // MaskedStoreSDNode (Chain, data, ptr, offset, mask)
2296 // Mask is a vector of i1 elements
2297 const SDValue &getBasePtr() const {
2298 return getOperand(getOpcode() == ISD::MLOAD ? 1 : 2);
2299 }
2300 const SDValue &getOffset() const {
2301 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2302 }
2303 const SDValue &getMask() const {
2304 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2305 }
2306
2307 /// Return the addressing mode for this load or store:
2308 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2309 ISD::MemIndexedMode getAddressingMode() const {
2310 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2311 }
2312
2313 /// Return true if this is a pre/post inc/dec load/store.
2314 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2315
2316 /// Return true if this is NOT a pre/post inc/dec load/store.
2317 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2318
2319 static bool classof(const SDNode *N) {
2320 return N->getOpcode() == ISD::MLOAD ||
2321 N->getOpcode() == ISD::MSTORE;
2322 }
2323};
2324
2325/// This class is used to represent an MLOAD node
2326class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
2327public:
2328 friend class SelectionDAG;
2329
2330 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2331 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
2332 bool IsExpanding, EVT MemVT, MachineMemOperand *MMO)
2333 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2334 LoadSDNodeBits.ExtTy = ETy;
2335 LoadSDNodeBits.IsExpanding = IsExpanding;
2336 }
2337
2338 ISD::LoadExtType getExtensionType() const {
2339 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2340 }
2341
2342 const SDValue &getBasePtr() const { return getOperand(1); }
2343 const SDValue &getOffset() const { return getOperand(2); }
2344 const SDValue &getMask() const { return getOperand(3); }
2345 const SDValue &getPassThru() const { return getOperand(4); }
2346
2347 static bool classof(const SDNode *N) {
2348 return N->getOpcode() == ISD::MLOAD;
2349 }
2350
2351 bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2352};
2353
2354/// This class is used to represent an MSTORE node
2355class MaskedStoreSDNode : public MaskedLoadStoreSDNode {
2356public:
2357 friend class SelectionDAG;
2358
2359 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2360 ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing,
2361 EVT MemVT, MachineMemOperand *MMO)
2362 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
2363 StoreSDNodeBits.IsTruncating = isTrunc;
2364 StoreSDNodeBits.IsCompressing = isCompressing;
2365 }
2366
2367 /// Return true if the op does a truncation before store.
2368 /// For integers this is the same as doing a TRUNCATE and storing the result.
2369 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2370 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2371
2372 /// Returns true if the op does a compression to the vector before storing.
2373 /// The node contiguously stores the active elements (integers or floats)
2374 /// in src (those with their respective bit set in writemask k) to unaligned
2375 /// memory at base_addr.
2376 bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }
2377
2378 const SDValue &getValue() const { return getOperand(1); }
2379 const SDValue &getBasePtr() const { return getOperand(2); }
2380 const SDValue &getOffset() const { return getOperand(3); }
2381 const SDValue &getMask() const { return getOperand(4); }
2382
2383 static bool classof(const SDNode *N) {
2384 return N->getOpcode() == ISD::MSTORE;
2385 }
2386};
2387
2388/// This is a base class used to represent
2389/// MGATHER and MSCATTER nodes
2390///
2391class MaskedGatherScatterSDNode : public MemSDNode {
2392public:
2393 friend class SelectionDAG;
2394
2395 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
2396 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2397 MachineMemOperand *MMO, ISD::MemIndexType IndexType)
2398 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2399 LSBaseSDNodeBits.AddressingMode = IndexType;
2400 assert(getIndexType() == IndexType && "Value truncated")((getIndexType() == IndexType && "Value truncated") ?
static_cast<void> (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2400, __PRETTY_FUNCTION__))
;
2401 }
2402
2403 /// How is Index applied to BasePtr when computing addresses.
2404 ISD::MemIndexType getIndexType() const {
2405 return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);
2406 }
2407 bool isIndexScaled() const {
2408 return (getIndexType() == ISD::SIGNED_SCALED) ||
2409 (getIndexType() == ISD::UNSIGNED_SCALED);
2410 }
2411 bool isIndexSigned() const {
2412 return (getIndexType() == ISD::SIGNED_SCALED) ||
2413 (getIndexType() == ISD::SIGNED_UNSCALED);
2414 }
2415
2416 // In the both nodes address is Op1, mask is Op2:
2417 // MaskedGatherSDNode (Chain, passthru, mask, base, index, scale)
2418 // MaskedScatterSDNode (Chain, value, mask, base, index, scale)
2419 // Mask is a vector of i1 elements
2420 const SDValue &getBasePtr() const { return getOperand(3); }
2421 const SDValue &getIndex() const { return getOperand(4); }
2422 const SDValue &getMask() const { return getOperand(2); }
2423 const SDValue &getScale() const { return getOperand(5); }
2424
2425 static bool classof(const SDNode *N) {
2426 return N->getOpcode() == ISD::MGATHER ||
2427 N->getOpcode() == ISD::MSCATTER;
2428 }
2429};
2430
2431/// This class is used to represent an MGATHER node
2432///
2433class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
2434public:
2435 friend class SelectionDAG;
2436
2437 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2438 EVT MemVT, MachineMemOperand *MMO,
2439 ISD::MemIndexType IndexType)
2440 : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
2441 IndexType) {}
2442
2443 const SDValue &getPassThru() const { return getOperand(1); }
2444
2445 static bool classof(const SDNode *N) {
2446 return N->getOpcode() == ISD::MGATHER;
2447 }
2448};
2449
2450/// This class is used to represent an MSCATTER node
2451///
2452class MaskedScatterSDNode : public MaskedGatherScatterSDNode {
2453public:
2454 friend class SelectionDAG;
2455
2456 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2457 EVT MemVT, MachineMemOperand *MMO,
2458 ISD::MemIndexType IndexType)
2459 : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO,
2460 IndexType) {}
2461
2462 const SDValue &getValue() const { return getOperand(1); }
2463
2464 static bool classof(const SDNode *N) {
2465 return N->getOpcode() == ISD::MSCATTER;
2466 }
2467};
2468
2469/// An SDNode that represents everything that will be needed
2470/// to construct a MachineInstr. These nodes are created during the
2471/// instruction selection proper phase.
2472///
2473/// Note that the only supported way to set the `memoperands` is by calling the
2474/// `SelectionDAG::setNodeMemRefs` function as the memory management happens
2475/// inside the DAG rather than in the node.
2476class MachineSDNode : public SDNode {
2477private:
2478 friend class SelectionDAG;
2479
2480 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
2481 : SDNode(Opc, Order, DL, VTs) {}
2482
2483 // We use a pointer union between a single `MachineMemOperand` pointer and
2484 // a pointer to an array of `MachineMemOperand` pointers. This is null when
2485 // the number of these is zero, the single pointer variant used when the
2486 // number is one, and the array is used for larger numbers.
2487 //
2488 // The array is allocated via the `SelectionDAG`'s allocator and so will
2489 // always live until the DAG is cleaned up and doesn't require ownership here.
2490 //
2491 // We can't use something simpler like `TinyPtrVector` here because `SDNode`
2492 // subclasses aren't managed in a conforming C++ manner. See the comments on
2493 // `SelectionDAG::MorphNodeTo` which details what all goes on, but the
2494 // constraint here is that these don't manage memory with their constructor or
2495 // destructor and can be initialized to a good state even if they start off
2496 // uninitialized.
2497 PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {};
2498
2499 // Note that this could be folded into the above `MemRefs` member if doing so
2500 // is advantageous at some point. We don't need to store this in most cases.
2501 // However, at the moment this doesn't appear to make the allocation any
2502 // smaller and makes the code somewhat simpler to read.
2503 int NumMemRefs = 0;
2504
2505public:
2506 using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator;
2507
2508 ArrayRef<MachineMemOperand *> memoperands() const {
2509 // Special case the common cases.
2510 if (NumMemRefs == 0)
2511 return {};
2512 if (NumMemRefs == 1)
2513 return makeArrayRef(MemRefs.getAddrOfPtr1(), 1);
2514
2515 // Otherwise we have an actual array.
2516 return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs);
2517 }
2518 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
2519 mmo_iterator memoperands_end() const { return memoperands().end(); }
2520 bool memoperands_empty() const { return memoperands().empty(); }
2521
2522 /// Clear out the memory reference descriptor list.
2523 void clearMemRefs() {
2524 MemRefs = nullptr;
2525 NumMemRefs = 0;
2526 }
2527
2528 static bool classof(const SDNode *N) {
2529 return N->isMachineOpcode();
2530 }
2531};
2532
2533class SDNodeIterator : public std::iterator<std::forward_iterator_tag,
2534 SDNode, ptrdiff_t> {
2535 const SDNode *Node;
2536 unsigned Operand;
2537
2538 SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}
2539
2540public:
2541 bool operator==(const SDNodeIterator& x) const {
2542 return Operand == x.Operand;
2543 }
2544 bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }
2545
2546 pointer operator*() const {
2547 return Node->getOperand(Operand).getNode();
2548 }
2549 pointer operator->() const { return operator*(); }
2550
2551 SDNodeIterator& operator++() { // Preincrement
2552 ++Operand;
2553 return *this;
2554 }
2555 SDNodeIterator operator++(int) { // Postincrement
2556 SDNodeIterator tmp = *this; ++*this; return tmp;
2557 }
2558 size_t operator-(SDNodeIterator Other) const {
2559 assert(Node == Other.Node &&((Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2560, __PRETTY_FUNCTION__))
2560 "Cannot compare iterators of two different nodes!")((Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2560, __PRETTY_FUNCTION__))
;
2561 return Operand - Other.Operand;
2562 }
2563
2564 static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); }
2565 static SDNodeIterator end (const SDNode *N) {
2566 return SDNodeIterator(N, N->getNumOperands());
2567 }
2568
2569 unsigned getOperand() const { return Operand; }
2570 const SDNode *getNode() const { return Node; }
2571};
2572
2573template <> struct GraphTraits<SDNode*> {
2574 using NodeRef = SDNode *;
2575 using ChildIteratorType = SDNodeIterator;
2576
2577 static NodeRef getEntryNode(SDNode *N) { return N; }
2578
2579 static ChildIteratorType child_begin(NodeRef N) {
2580 return SDNodeIterator::begin(N);
2581 }
2582
2583 static ChildIteratorType child_end(NodeRef N) {
2584 return SDNodeIterator::end(N);
2585 }
2586};
2587
2588/// A representation of the largest SDNode, for use in sizeof().
2589///
2590/// This needs to be a union because the largest node differs on 32 bit systems
2591/// with 4 and 8 byte pointer alignment, respectively.
2592using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode,
2593 BlockAddressSDNode,
2594 GlobalAddressSDNode>;
2595
2596/// The SDNode class with the greatest alignment requirement.
2597using MostAlignedSDNode = GlobalAddressSDNode;
2598
2599namespace ISD {
2600
2601 /// Returns true if the specified node is a non-extending and unindexed load.
2602 inline bool isNormalLoad(const SDNode *N) {
2603 const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N);
2604 return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
2605 Ld->getAddressingMode() == ISD::UNINDEXED;
2606 }
2607
2608 /// Returns true if the specified node is a non-extending load.
2609 inline bool isNON_EXTLoad(const SDNode *N) {
2610 return isa<LoadSDNode>(N) &&
2611 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
2612 }
2613
2614 /// Returns true if the specified node is a EXTLOAD.
2615 inline bool isEXTLoad(const SDNode *N) {
2616 return isa<LoadSDNode>(N) &&
2617 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
2618 }
2619
2620 /// Returns true if the specified node is a SEXTLOAD.
2621 inline bool isSEXTLoad(const SDNode *N) {
2622 return isa<LoadSDNode>(N) &&
2623 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
2624 }
2625
2626 /// Returns true if the specified node is a ZEXTLOAD.
2627 inline bool isZEXTLoad(const SDNode *N) {
2628 return isa<LoadSDNode>(N) &&
2629 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
2630 }
2631
2632 /// Returns true if the specified node is an unindexed load.
2633 inline bool isUNINDEXEDLoad(const SDNode *N) {
2634 return isa<LoadSDNode>(N) &&
2635 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2636 }
2637
2638 /// Returns true if the specified node is a non-truncating
2639 /// and unindexed store.
2640 inline bool isNormalStore(const SDNode *N) {
2641 const StoreSDNode *St = dyn_cast<StoreSDNode>(N);
2642 return St && !St->isTruncatingStore() &&
2643 St->getAddressingMode() == ISD::UNINDEXED;
2644 }
2645
2646 /// Returns true if the specified node is a non-truncating store.
2647 inline bool isNON_TRUNCStore(const SDNode *N) {
2648 return isa<StoreSDNode>(N) && !cast<StoreSDNode>(N)->isTruncatingStore();
2649 }
2650
2651 /// Returns true if the specified node is a truncating store.
2652 inline bool isTRUNCStore(const SDNode *N) {
2653 return isa<StoreSDNode>(N) && cast<StoreSDNode>(N)->isTruncatingStore();
2654 }
2655
2656 /// Returns true if the specified node is an unindexed store.
2657 inline bool isUNINDEXEDStore(const SDNode *N) {
2658 return isa<StoreSDNode>(N) &&
2659 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2660 }
2661
2662 /// Attempt to match a unary predicate against a scalar/splat constant or
2663 /// every element of a constant BUILD_VECTOR.
2664 /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
2665 bool matchUnaryPredicate(SDValue Op,
2666 std::function<bool(ConstantSDNode *)> Match,
2667 bool AllowUndefs = false);
2668
2669 /// Attempt to match a binary predicate against a pair of scalar/splat
2670 /// constants or every element of a pair of constant BUILD_VECTORs.
2671 /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
2672 /// If AllowTypeMismatch is true then RetType + ArgTypes don't need to match.
2673 bool matchBinaryPredicate(
2674 SDValue LHS, SDValue RHS,
2675 std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match,
2676 bool AllowUndefs = false, bool AllowTypeMismatch = false);
2677
2678 /// Returns true if the specified value is the overflow result from one
2679 /// of the overflow intrinsic nodes.
2680 inline bool isOverflowIntrOpRes(SDValue Op) {
2681 unsigned Opc = Op.getOpcode();
2682 return (Op.getResNo() == 1 &&
2683 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2684 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
2685 }
2686
2687} // end namespace ISD
2688
2689} // end namespace llvm
2690
2691#endif // LLVM_CODEGEN_SELECTIONDAGNODES_H