Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1182, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name InstrEmitter.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/include -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-01-13-084841-49055-1 -x c++ /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the Emit routines for the SelectionDAG class, which creates
10// MachineInstrs based on the decisions of the SelectionDAG instruction
11// selection.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrEmitter.h"
16#include "SDNodeDbgValue.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/CodeGen/MachineConstantPool.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/StackMaps.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/CodeGen/TargetLowering.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/IR/DebugInfo.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/MathExtras.h"
31using namespace llvm;
32
33#define DEBUG_TYPE"instr-emitter" "instr-emitter"
34
35/// MinRCSize - Smallest register class we allow when constraining virtual
36/// registers. If satisfying all register class constraints would require
37/// using a smaller register class, emit a COPY to a new virtual register
38/// instead.
39const unsigned MinRCSize = 4;
40
41/// CountResults - The results of target nodes have register or immediate
42/// operands first, then an optional chain, and optional glue operands (which do
43/// not go into the resulting MachineInstr).
44unsigned InstrEmitter::CountResults(SDNode *Node) {
45 unsigned N = Node->getNumValues();
46 while (N && Node->getValueType(N - 1) == MVT::Glue)
47 --N;
48 if (N && Node->getValueType(N - 1) == MVT::Other)
49 --N; // Skip over chain result.
50 return N;
51}
52
53/// countOperands - The inputs to target nodes have any actual inputs first,
54/// followed by an optional chain operand, then an optional glue operand.
55/// Compute the number of actual operands that will go into the resulting
56/// MachineInstr.
57///
58/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
59/// the chain and glue. These operands may be implicit on the machine instr.
60static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
61 unsigned &NumImpUses) {
62 unsigned N = Node->getNumOperands();
63 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
64 --N;
65 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
66 --N; // Ignore chain if it exists.
67
68 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
69 NumImpUses = N - NumExpUses;
70 for (unsigned I = N; I > NumExpUses; --I) {
71 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
72 continue;
73 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
74 if (Register::isPhysicalRegister(RN->getReg()))
75 continue;
76 NumImpUses = N - I;
77 break;
78 }
79
80 return N;
81}
82
83/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
84/// implicit physical register output.
85void InstrEmitter::
86EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
87 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
88 unsigned VRBase = 0;
89 if (Register::isVirtualRegister(SrcReg)) {
90 // Just use the input register directly!
91 SDValue Op(Node, ResNo);
92 if (IsClone)
93 VRBaseMap.erase(Op);
94 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
95 (void)isNew; // Silence compiler warning.
96 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 96, __PRETTY_FUNCTION__))
;
97 return;
98 }
99
100 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101 // the CopyToReg'd destination register instead of creating a new vreg.
102 bool MatchReg = true;
103 const TargetRegisterClass *UseRC = nullptr;
104 MVT VT = Node->getSimpleValueType(ResNo);
105
106 // Stick to the preferred register classes for legal types.
107 if (TLI->isTypeLegal(VT))
108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
109
110 if (!IsClone && !IsCloned)
111 for (SDNode *User : Node->uses()) {
112 bool Match = true;
113 if (User->getOpcode() == ISD::CopyToReg &&
114 User->getOperand(2).getNode() == Node &&
115 User->getOperand(2).getResNo() == ResNo) {
116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117 if (Register::isVirtualRegister(DestReg)) {
118 VRBase = DestReg;
119 Match = false;
120 } else if (DestReg != SrcReg)
121 Match = false;
122 } else {
123 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
124 SDValue Op = User->getOperand(i);
125 if (Op.getNode() != Node || Op.getResNo() != ResNo)
126 continue;
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
129 continue;
130 Match = false;
131 if (User->isMachineOpcode()) {
132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133 const TargetRegisterClass *RC = nullptr;
134 if (i+II.getNumDefs() < II.getNumOperands()) {
135 RC = TRI->getAllocatableClass(
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
137 }
138 if (!UseRC)
139 UseRC = RC;
140 else if (RC) {
141 const TargetRegisterClass *ComRC =
142 TRI->getCommonSubClass(UseRC, RC);
143 // If multiple uses expect disjoint register classes, we emit
144 // copies in AddRegisterOperand.
145 if (ComRC)
146 UseRC = ComRC;
147 }
148 }
149 }
150 }
151 MatchReg &= Match;
152 if (VRBase)
153 break;
154 }
155
156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
158
159 // Figure out the register class to create for the destreg.
160 if (VRBase) {
161 DstRC = MRI->getRegClass(VRBase);
162 } else if (UseRC) {
163 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&((TRI->isTypeLegalForClass(*UseRC, VT) && "Incompatible phys register def and uses!"
) ? static_cast<void> (0) : __assert_fail ("TRI->isTypeLegalForClass(*UseRC, VT) && \"Incompatible phys register def and uses!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 164, __PRETTY_FUNCTION__))
164 "Incompatible phys register def and uses!")((TRI->isTypeLegalForClass(*UseRC, VT) && "Incompatible phys register def and uses!"
) ? static_cast<void> (0) : __assert_fail ("TRI->isTypeLegalForClass(*UseRC, VT) && \"Incompatible phys register def and uses!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 164, __PRETTY_FUNCTION__))
;
165 DstRC = UseRC;
166 } else {
167 DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
168 }
169
170 // If all uses are reading from the src physical register and copying the
171 // register is either impossible or very expensive, then don't create a copy.
172 if (MatchReg && SrcRC->getCopyCost() < 0) {
173 VRBase = SrcReg;
174 } else {
175 // Create the reg, emit the copy.
176 VRBase = MRI->createVirtualRegister(DstRC);
177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178 VRBase).addReg(SrcReg);
179 }
180
181 SDValue Op(Node, ResNo);
182 if (IsClone)
183 VRBaseMap.erase(Op);
184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185 (void)isNew; // Silence compiler warning.
186 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 186, __PRETTY_FUNCTION__))
;
187}
188
189void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
190 MachineInstrBuilder &MIB,
191 const MCInstrDesc &II,
192 bool IsClone, bool IsCloned,
193 DenseMap<SDValue, unsigned> &VRBaseMap) {
194 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&((Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!"
) ? static_cast<void> (0) : __assert_fail ("Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && \"IMPLICIT_DEF should have been handled as a special case elsewhere!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 195, __PRETTY_FUNCTION__))
195 "IMPLICIT_DEF should have been handled as a special case elsewhere!")((Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!"
) ? static_cast<void> (0) : __assert_fail ("Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && \"IMPLICIT_DEF should have been handled as a special case elsewhere!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 195, __PRETTY_FUNCTION__))
;
196
197 unsigned NumResults = CountResults(Node);
198 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
199 // If the specific node value is only used by a CopyToReg and the dest reg
200 // is a vreg in the same register class, use the CopyToReg'd destination
201 // register instead of creating a new vreg.
202 unsigned VRBase = 0;
203 const TargetRegisterClass *RC =
204 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
205 // Always let the value type influence the used register class. The
206 // constraints on the instruction may be too lax to represent the value
207 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
208 // the 32-bit float super-class (X86::FR32).
209 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
210 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
211 Node->getSimpleValueType(i),
212 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
213 if (RC)
214 VTRC = TRI->getCommonSubClass(RC, VTRC);
215 if (VTRC)
216 RC = VTRC;
217 }
218
219 if (II.OpInfo[i].isOptionalDef()) {
220 // Optional def must be a physical register.
221 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
222 assert(Register::isPhysicalRegister(VRBase))((Register::isPhysicalRegister(VRBase)) ? static_cast<void
> (0) : __assert_fail ("Register::isPhysicalRegister(VRBase)"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 222, __PRETTY_FUNCTION__))
;
223 MIB.addReg(VRBase, RegState::Define);
224 }
225
226 if (!VRBase && !IsClone && !IsCloned)
227 for (SDNode *User : Node->uses()) {
228 if (User->getOpcode() == ISD::CopyToReg &&
229 User->getOperand(2).getNode() == Node &&
230 User->getOperand(2).getResNo() == i) {
231 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
232 if (Register::isVirtualRegister(Reg)) {
233 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
234 if (RegRC == RC) {
235 VRBase = Reg;
236 MIB.addReg(VRBase, RegState::Define);
237 break;
238 }
239 }
240 }
241 }
242
243 // Create the result registers for this node and add the result regs to
244 // the machine instruction.
245 if (VRBase == 0) {
246 assert(RC && "Isn't a register operand!")((RC && "Isn't a register operand!") ? static_cast<
void> (0) : __assert_fail ("RC && \"Isn't a register operand!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 246, __PRETTY_FUNCTION__))
;
247 VRBase = MRI->createVirtualRegister(RC);
248 MIB.addReg(VRBase, RegState::Define);
249 }
250
251 // If this def corresponds to a result of the SDNode insert the VRBase into
252 // the lookup map.
253 if (i < NumResults) {
254 SDValue Op(Node, i);
255 if (IsClone)
256 VRBaseMap.erase(Op);
257 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
258 (void)isNew; // Silence compiler warning.
259 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 259, __PRETTY_FUNCTION__))
;
260 }
261 }
262}
263
264/// getVR - Return the virtual register corresponding to the specified result
265/// of the specified node.
266unsigned InstrEmitter::getVR(SDValue Op,
267 DenseMap<SDValue, unsigned> &VRBaseMap) {
268 if (Op.isMachineOpcode() &&
6
Calling 'SDValue::isMachineOpcode'
269 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
270 // Add an IMPLICIT_DEF instruction before every use.
271 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
272 // does not include operand register class info.
273 const TargetRegisterClass *RC = TLI->getRegClassFor(
274 Op.getSimpleValueType(), Op.getNode()->isDivergent());
275 Register VReg = MRI->createVirtualRegister(RC);
276 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
277 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
278 return VReg;
279 }
280
281 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
282 assert(I != VRBaseMap.end() && "Node emitted out of order - late")((I != VRBaseMap.end() && "Node emitted out of order - late"
) ? static_cast<void> (0) : __assert_fail ("I != VRBaseMap.end() && \"Node emitted out of order - late\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 282, __PRETTY_FUNCTION__))
;
283 return I->second;
284}
285
286
287/// AddRegisterOperand - Add the specified register as an operand to the
288/// specified machine instr. Insert register copies if the register is
289/// not in the required register class.
290void
291InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
292 SDValue Op,
293 unsigned IIOpNum,
294 const MCInstrDesc *II,
295 DenseMap<SDValue, unsigned> &VRBaseMap,
296 bool IsDebug, bool IsClone, bool IsCloned) {
297 assert(Op.getValueType() != MVT::Other &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 299, __PRETTY_FUNCTION__))
298 Op.getValueType() != MVT::Glue &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 299, __PRETTY_FUNCTION__))
299 "Chain and glue operands should occur at end of operand list!")((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 299, __PRETTY_FUNCTION__))
;
300 // Get/emit the operand.
301 unsigned VReg = getVR(Op, VRBaseMap);
302
303 const MCInstrDesc &MCID = MIB->getDesc();
304 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
305 MCID.OpInfo[IIOpNum].isOptionalDef();
306
307 // If the instruction requires a register in a different class, create
308 // a new virtual register and copy the value into it, but first attempt to
309 // shrink VReg's register class within reason. For example, if VReg == GR32
310 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
311 if (II) {
312 const TargetRegisterClass *OpRC = nullptr;
313 if (IIOpNum < II->getNumOperands())
314 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
315
316 if (OpRC) {
317 const TargetRegisterClass *ConstrainedRC
318 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
319 if (!ConstrainedRC) {
320 OpRC = TRI->getAllocatableClass(OpRC);
321 assert(OpRC && "Constraints cannot be fulfilled for allocation")((OpRC && "Constraints cannot be fulfilled for allocation"
) ? static_cast<void> (0) : __assert_fail ("OpRC && \"Constraints cannot be fulfilled for allocation\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 321, __PRETTY_FUNCTION__))
;
322 Register NewVReg = MRI->createVirtualRegister(OpRC);
323 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
324 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
325 VReg = NewVReg;
326 } else {
327 assert(ConstrainedRC->isAllocatable() &&((ConstrainedRC->isAllocatable() && "Constraining an allocatable VReg produced an unallocatable class?"
) ? static_cast<void> (0) : __assert_fail ("ConstrainedRC->isAllocatable() && \"Constraining an allocatable VReg produced an unallocatable class?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 328, __PRETTY_FUNCTION__))
328 "Constraining an allocatable VReg produced an unallocatable class?")((ConstrainedRC->isAllocatable() && "Constraining an allocatable VReg produced an unallocatable class?"
) ? static_cast<void> (0) : __assert_fail ("ConstrainedRC->isAllocatable() && \"Constraining an allocatable VReg produced an unallocatable class?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 328, __PRETTY_FUNCTION__))
;
329 }
330 }
331 }
332
333 // If this value has only one use, that use is a kill. This is a
334 // conservative approximation. InstrEmitter does trivial coalescing
335 // with CopyFromReg nodes, so don't emit kill flags for them.
336 // Avoid kill flags on Schedule cloned nodes, since there will be
337 // multiple uses.
338 // Tied operands are never killed, so we need to check that. And that
339 // means we need to determine the index of the operand.
340 bool isKill = Op.hasOneUse() &&
341 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
342 !IsDebug &&
343 !(IsClone || IsCloned);
344 if (isKill) {
345 unsigned Idx = MIB->getNumOperands();
346 while (Idx > 0 &&
347 MIB->getOperand(Idx-1).isReg() &&
348 MIB->getOperand(Idx-1).isImplicit())
349 --Idx;
350 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
351 if (isTied)
352 isKill = false;
353 }
354
355 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
356 getDebugRegState(IsDebug));
357}
358
359/// AddOperand - Add the specified operand to the specified machine instr. II
360/// specifies the instruction information for the node, and IIOpNum is the
361/// operand number (in the II) that we are adding.
362void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
363 SDValue Op,
364 unsigned IIOpNum,
365 const MCInstrDesc *II,
366 DenseMap<SDValue, unsigned> &VRBaseMap,
367 bool IsDebug, bool IsClone, bool IsCloned) {
368 if (Op.isMachineOpcode()) {
369 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
370 IsDebug, IsClone, IsCloned);
371 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
372 MIB.addImm(C->getSExtValue());
373 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
374 MIB.addFPImm(F->getConstantFPValue());
375 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
376 unsigned VReg = R->getReg();
377 MVT OpVT = Op.getSimpleValueType();
378 const TargetRegisterClass *IIRC =
379 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
380 : nullptr;
381 const TargetRegisterClass *OpRC =
382 TLI->isTypeLegal(OpVT)
383 ? TLI->getRegClassFor(OpVT,
384 Op.getNode()->isDivergent() ||
385 (IIRC && TRI->isDivergentRegClass(IIRC)))
386 : nullptr;
387
388 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
389 Register NewVReg = MRI->createVirtualRegister(IIRC);
390 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
391 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
392 VReg = NewVReg;
393 }
394 // Turn additional physreg operands into implicit uses on non-variadic
395 // instructions. This is used by call and return instructions passing
396 // arguments in registers.
397 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
398 MIB.addReg(VReg, getImplRegState(Imp));
399 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
400 MIB.addRegMask(RM->getRegMask());
401 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
402 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
403 TGA->getTargetFlags());
404 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
405 MIB.addMBB(BBNode->getBasicBlock());
406 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
407 MIB.addFrameIndex(FI->getIndex());
408 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
409 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
410 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
411 int Offset = CP->getOffset();
412 unsigned Align = CP->getAlignment();
413 Type *Type = CP->getType();
414 // MachineConstantPool wants an explicit alignment.
415 if (Align == 0) {
416 Align = MF->getDataLayout().getPrefTypeAlignment(Type);
417 if (Align == 0) {
418 // Alignment of vector types. FIXME!
419 Align = MF->getDataLayout().getTypeAllocSize(Type);
420 }
421 }
422
423 unsigned Idx;
424 MachineConstantPool *MCP = MF->getConstantPool();
425 if (CP->isMachineConstantPoolEntry())
426 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
427 else
428 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
429 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
430 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
431 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
432 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
433 MIB.addSym(SymNode->getMCSymbol());
434 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
435 MIB.addBlockAddress(BA->getBlockAddress(),
436 BA->getOffset(),
437 BA->getTargetFlags());
438 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
439 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
440 } else {
441 assert(Op.getValueType() != MVT::Other &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 443, __PRETTY_FUNCTION__))
442 Op.getValueType() != MVT::Glue &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 443, __PRETTY_FUNCTION__))
443 "Chain and glue operands should occur at end of operand list!")((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 443, __PRETTY_FUNCTION__))
;
444 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
445 IsDebug, IsClone, IsCloned);
446 }
447}
448
449unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
450 MVT VT, bool isDivergent, const DebugLoc &DL) {
451 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
452 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
453
454 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
455 // within reason.
456 if (RC && RC != VRC)
457 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
458
459 // VReg has been adjusted. It can be used with SubIdx operands now.
460 if (RC)
461 return VReg;
462
463 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
464 // register instead.
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
466 assert(RC && "No legal register class for VT supports that SubIdx")((RC && "No legal register class for VT supports that SubIdx"
) ? static_cast<void> (0) : __assert_fail ("RC && \"No legal register class for VT supports that SubIdx\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 466, __PRETTY_FUNCTION__))
;
467 Register NewReg = MRI->createVirtualRegister(RC);
468 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
469 .addReg(VReg);
470 return NewReg;
471}
472
473/// EmitSubregNode - Generate machine code for subreg nodes.
474///
475void InstrEmitter::EmitSubregNode(SDNode *Node,
476 DenseMap<SDValue, unsigned> &VRBaseMap,
477 bool IsClone, bool IsCloned) {
478 unsigned VRBase = 0;
479 unsigned Opc = Node->getMachineOpcode();
480
481 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
482 // the CopyToReg'd destination register instead of creating a new vreg.
483 for (SDNode *User : Node->uses()) {
484 if (User->getOpcode() == ISD::CopyToReg &&
485 User->getOperand(2).getNode() == Node) {
486 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
487 if (Register::isVirtualRegister(DestReg)) {
488 VRBase = DestReg;
489 break;
490 }
491 }
492 }
493
494 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
495 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
496 // constraints on the %dst register, COPY can target all legal register
497 // classes.
498 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
499 const TargetRegisterClass *TRC =
500 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
501
502 unsigned Reg;
503 MachineInstr *DefMI;
504 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
505 if (R && Register::isPhysicalRegister(R->getReg())) {
506 Reg = R->getReg();
507 DefMI = nullptr;
508 } else {
509 Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
510 DefMI = MRI->getVRegDef(Reg);
511 }
512
513 unsigned SrcReg, DstReg, DefSubIdx;
514 if (DefMI &&
515 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
516 SubIdx == DefSubIdx &&
517 TRC == MRI->getRegClass(SrcReg)) {
518 // Optimize these:
519 // r1025 = s/zext r1024, 4
520 // r1026 = extract_subreg r1025, 4
521 // to a copy
522 // r1026 = copy r1024
523 VRBase = MRI->createVirtualRegister(TRC);
524 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
525 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
526 MRI->clearKillFlags(SrcReg);
527 } else {
528 // Reg may not support a SubIdx sub-register, and we may need to
529 // constrain its register class or issue a COPY to a compatible register
530 // class.
531 if (Register::isVirtualRegister(Reg))
532 Reg = ConstrainForSubReg(Reg, SubIdx,
533 Node->getOperand(0).getSimpleValueType(),
534 Node->isDivergent(), Node->getDebugLoc());
535 // Create the destreg if it is missing.
536 if (VRBase == 0)
537 VRBase = MRI->createVirtualRegister(TRC);
538
539 // Create the extract_subreg machine instruction.
540 MachineInstrBuilder CopyMI =
541 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
542 TII->get(TargetOpcode::COPY), VRBase);
543 if (Register::isVirtualRegister(Reg))
544 CopyMI.addReg(Reg, 0, SubIdx);
545 else
546 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
547 }
548 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
549 Opc == TargetOpcode::SUBREG_TO_REG) {
550 SDValue N0 = Node->getOperand(0);
551 SDValue N1 = Node->getOperand(1);
552 SDValue N2 = Node->getOperand(2);
553 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
554
555 // Figure out the register class to create for the destreg. It should be
556 // the largest legal register class supporting SubIdx sub-registers.
557 // RegisterCoalescer will constrain it further if it decides to eliminate
558 // the INSERT_SUBREG instruction.
559 //
560 // %dst = INSERT_SUBREG %src, %sub, SubIdx
561 //
562 // is lowered by TwoAddressInstructionPass to:
563 //
564 // %dst = COPY %src
565 // %dst:SubIdx = COPY %sub
566 //
567 // There is no constraint on the %src register class.
568 //
569 const TargetRegisterClass *SRC =
570 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
571 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
572 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG")((SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"
) ? static_cast<void> (0) : __assert_fail ("SRC && \"No register class supports VT and SubIdx for INSERT_SUBREG\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 572, __PRETTY_FUNCTION__))
;
573
574 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
575 VRBase = MRI->createVirtualRegister(SRC);
576
577 // Create the insert_subreg or subreg_to_reg machine instruction.
578 MachineInstrBuilder MIB =
579 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
580
581 // If creating a subreg_to_reg, then the first input operand
582 // is an implicit value immediate, otherwise it's a register
583 if (Opc == TargetOpcode::SUBREG_TO_REG) {
584 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
585 MIB.addImm(SD->getZExtValue());
586 } else
587 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
588 IsClone, IsCloned);
589 // Add the subregister being inserted
590 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
591 IsClone, IsCloned);
592 MIB.addImm(SubIdx);
593 MBB->insert(InsertPos, MIB);
594 } else
595 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg")::llvm::llvm_unreachable_internal("Node is not insert_subreg, extract_subreg, or subreg_to_reg"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 595)
;
596
597 SDValue Op(Node, 0);
598 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
599 (void)isNew; // Silence compiler warning.
600 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 600, __PRETTY_FUNCTION__))
;
601}
602
603/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
604/// COPY_TO_REGCLASS is just a normal copy, except that the destination
605/// register is constrained to be in a particular register class.
606///
607void
608InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
609 DenseMap<SDValue, unsigned> &VRBaseMap) {
610 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
611
612 // Create the new VReg in the destination class and emit a copy.
613 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
614 const TargetRegisterClass *DstRC =
615 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
616 Register NewVReg = MRI->createVirtualRegister(DstRC);
617 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
618 NewVReg).addReg(VReg);
619
620 SDValue Op(Node, 0);
621 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
622 (void)isNew; // Silence compiler warning.
623 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 623, __PRETTY_FUNCTION__))
;
624}
625
626/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
627///
628void InstrEmitter::EmitRegSequence(SDNode *Node,
629 DenseMap<SDValue, unsigned> &VRBaseMap,
630 bool IsClone, bool IsCloned) {
631 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
632 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
633 Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
634 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
635 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
636 unsigned NumOps = Node->getNumOperands();
637 // If the input pattern has a chain, then the root of the corresponding
638 // output pattern will get a chain as well. This can happen to be a
639 // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
640 if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
641 --NumOps; // Ignore chain if it exists.
642
643 assert((NumOps & 1) == 1 &&(((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"
) ? static_cast<void> (0) : __assert_fail ("(NumOps & 1) == 1 && \"REG_SEQUENCE must have an odd number of operands!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 644, __PRETTY_FUNCTION__))
644 "REG_SEQUENCE must have an odd number of operands!")(((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"
) ? static_cast<void> (0) : __assert_fail ("(NumOps & 1) == 1 && \"REG_SEQUENCE must have an odd number of operands!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 644, __PRETTY_FUNCTION__))
;
645 for (unsigned i = 1; i != NumOps; ++i) {
646 SDValue Op = Node->getOperand(i);
647 if ((i & 1) == 0) {
648 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
649 // Skip physical registers as they don't have a vreg to get and we'll
650 // insert copies for them in TwoAddressInstructionPass anyway.
651 if (!R || !Register::isPhysicalRegister(R->getReg())) {
652 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
653 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
655 const TargetRegisterClass *SRC =
656 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
657 if (SRC && SRC != RC) {
658 MRI->setRegClass(NewVReg, SRC);
659 RC = SRC;
660 }
661 }
662 }
663 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
664 IsClone, IsCloned);
665 }
666
667 MBB->insert(InsertPos, MIB);
668 SDValue Op(Node, 0);
669 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
670 (void)isNew; // Silence compiler warning.
671 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 671, __PRETTY_FUNCTION__))
;
672}
673
674/// EmitDbgValue - Generate machine instruction for a dbg_value node.
675///
676MachineInstr *
677InstrEmitter::EmitDbgValue(SDDbgValue *SD,
678 DenseMap<SDValue, unsigned> &VRBaseMap) {
679 MDNode *Var = SD->getVariable();
680 const DIExpression *Expr = SD->getExpression();
681 DebugLoc DL = SD->getDebugLoc();
682 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Var)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 683, __PRETTY_FUNCTION__))
683 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Var)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 683, __PRETTY_FUNCTION__))
;
684
685 SD->setIsEmitted();
686
687 if (SD->isInvalidated()) {
688 // An invalidated SDNode must generate an undef DBG_VALUE: although the
689 // original value is no longer computed, earlier DBG_VALUEs live ranges
690 // must not leak into later code.
691 auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
692 MIB.addReg(0U);
693 MIB.addReg(0U, RegState::Debug);
694 MIB.addMetadata(Var);
695 MIB.addMetadata(Expr);
696 return &*MIB;
697 }
698
699 if (SD->getKind() == SDDbgValue::FRAMEIX) {
700 // Stack address; this needs to be lowered in target-dependent fashion.
701 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
702 auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
703 .addFrameIndex(SD->getFrameIx());
704
705 if (SD->isIndirect())
706 Expr = DIExpression::append(Expr, {dwarf::DW_OP_deref});
707
708 FrameMI.addReg(0);
709 return FrameMI.addMetadata(Var).addMetadata(Expr);
710 }
711 // Otherwise, we're going to create an instruction here.
712 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
713 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
714 if (SD->getKind() == SDDbgValue::SDNODE) {
715 SDNode *Node = SD->getSDNode();
716 SDValue Op = SDValue(Node, SD->getResNo());
717 // It's possible we replaced this SDNode with other(s) and therefore
718 // didn't generate code for it. It's better to catch these cases where
719 // they happen and transfer the debug info, but trying to guarantee that
720 // in all cases would be very fragile; this is a safeguard for any
721 // that were missed.
722 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
723 if (I==VRBaseMap.end())
724 MIB.addReg(0U); // undef
725 else
726 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
727 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
728 } else if (SD->getKind() == SDDbgValue::VREG) {
729 MIB.addReg(SD->getVReg(), RegState::Debug);
730 } else if (SD->getKind() == SDDbgValue::CONST) {
731 const Value *V = SD->getConst();
732 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
733 if (CI->getBitWidth() > 64)
734 MIB.addCImm(CI);
735 else
736 MIB.addImm(CI->getSExtValue());
737 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
738 MIB.addFPImm(CF);
739 } else if (isa<ConstantPointerNull>(V)) {
740 // Note: This assumes that all nullptr constants are zero-valued.
741 MIB.addImm(0);
742 } else {
743 // Could be an Undef. In any case insert an Undef so we can see what we
744 // dropped.
745 MIB.addReg(0U);
746 }
747 } else {
748 // Insert an Undef so we can see what we dropped.
749 MIB.addReg(0U);
750 }
751
752 // Indirect addressing is indicated by an Imm as the second parameter.
753 if (SD->isIndirect())
754 Expr = DIExpression::append(Expr, {dwarf::DW_OP_deref});
755
756 MIB.addReg(0U, RegState::Debug);
757
758 MIB.addMetadata(Var);
759 MIB.addMetadata(Expr);
760
761 return &*MIB;
762}
763
764MachineInstr *
765InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
766 MDNode *Label = SD->getLabel();
767 DebugLoc DL = SD->getDebugLoc();
768 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&((cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 769, __PRETTY_FUNCTION__))
769 "Expected inlined-at fields to agree")((cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 769, __PRETTY_FUNCTION__))
;
770
771 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
772 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
773 MIB.addMetadata(Label);
774
775 return &*MIB;
776}
777
778/// EmitMachineNode - Generate machine code for a target-specific node and
779/// needed dependencies.
780///
781void InstrEmitter::
782EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
783 DenseMap<SDValue, unsigned> &VRBaseMap) {
784 unsigned Opc = Node->getMachineOpcode();
785
786 // Handle subreg insert/extract specially
787 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
788 Opc == TargetOpcode::INSERT_SUBREG ||
789 Opc == TargetOpcode::SUBREG_TO_REG) {
790 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
791 return;
792 }
793
794 // Handle COPY_TO_REGCLASS specially.
795 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
796 EmitCopyToRegClassNode(Node, VRBaseMap);
797 return;
798 }
799
800 // Handle REG_SEQUENCE specially.
801 if (Opc == TargetOpcode::REG_SEQUENCE) {
802 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
803 return;
804 }
805
806 if (Opc == TargetOpcode::IMPLICIT_DEF)
807 // We want a unique VR for each IMPLICIT_DEF use.
808 return;
809
810 const MCInstrDesc &II = TII->get(Opc);
811 unsigned NumResults = CountResults(Node);
812 unsigned NumDefs = II.getNumDefs();
813 const MCPhysReg *ScratchRegs = nullptr;
814
815 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
816 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
817 // Stackmaps do not have arguments and do not preserve their calling
818 // convention. However, to simplify runtime support, they clobber the same
819 // scratch registers as AnyRegCC.
820 unsigned CC = CallingConv::AnyReg;
821 if (Opc == TargetOpcode::PATCHPOINT) {
822 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
823 NumDefs = NumResults;
824 }
825 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
826 }
827
828 unsigned NumImpUses = 0;
829 unsigned NodeOperands =
830 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
831 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
832#ifndef NDEBUG
833 unsigned NumMIOperands = NodeOperands + NumResults;
834 if (II.isVariadic())
835 assert(NumMIOperands >= II.getNumOperands() &&((NumMIOperands >= II.getNumOperands() && "Too few operands for a variadic node!"
) ? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && \"Too few operands for a variadic node!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 836, __PRETTY_FUNCTION__))
836 "Too few operands for a variadic node!")((NumMIOperands >= II.getNumOperands() && "Too few operands for a variadic node!"
) ? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && \"Too few operands for a variadic node!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 836, __PRETTY_FUNCTION__))
;
837 else
838 assert(NumMIOperands >= II.getNumOperands() &&((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 841, __PRETTY_FUNCTION__))
839 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 841, __PRETTY_FUNCTION__))
840 NumImpUses &&((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 841, __PRETTY_FUNCTION__))
841 "#operands for dag node doesn't match .td file!")((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 841, __PRETTY_FUNCTION__))
;
842#endif
843
844 // Create the new machine instruction.
845 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
846
847 // Add result register values for things that are defined by this
848 // instruction.
849 if (NumResults) {
850 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
851
852 // Transfer any IR flags from the SDNode to the MachineInstr
853 MachineInstr *MI = MIB.getInstr();
854 const SDNodeFlags Flags = Node->getFlags();
855 if (Flags.hasNoSignedZeros())
856 MI->setFlag(MachineInstr::MIFlag::FmNsz);
857
858 if (Flags.hasAllowReciprocal())
859 MI->setFlag(MachineInstr::MIFlag::FmArcp);
860
861 if (Flags.hasNoNaNs())
862 MI->setFlag(MachineInstr::MIFlag::FmNoNans);
863
864 if (Flags.hasNoInfs())
865 MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
866
867 if (Flags.hasAllowContract())
868 MI->setFlag(MachineInstr::MIFlag::FmContract);
869
870 if (Flags.hasApproximateFuncs())
871 MI->setFlag(MachineInstr::MIFlag::FmAfn);
872
873 if (Flags.hasAllowReassociation())
874 MI->setFlag(MachineInstr::MIFlag::FmReassoc);
875
876 if (Flags.hasNoUnsignedWrap())
877 MI->setFlag(MachineInstr::MIFlag::NoUWrap);
878
879 if (Flags.hasNoSignedWrap())
880 MI->setFlag(MachineInstr::MIFlag::NoSWrap);
881
882 if (Flags.hasExact())
883 MI->setFlag(MachineInstr::MIFlag::IsExact);
884
885 if (Flags.hasNoFPExcept())
886 MI->setFlag(MachineInstr::MIFlag::NoFPExcept);
887 }
888
889 // Emit all of the actual operands of this instruction, adding them to the
890 // instruction as appropriate.
891 bool HasOptPRefs = NumDefs > NumResults;
892 assert((!HasOptPRefs || !HasPhysRegOuts) &&(((!HasOptPRefs || !HasPhysRegOuts) && "Unable to cope with optional defs and phys regs defs!"
) ? static_cast<void> (0) : __assert_fail ("(!HasOptPRefs || !HasPhysRegOuts) && \"Unable to cope with optional defs and phys regs defs!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 893, __PRETTY_FUNCTION__))
893 "Unable to cope with optional defs and phys regs defs!")(((!HasOptPRefs || !HasPhysRegOuts) && "Unable to cope with optional defs and phys regs defs!"
) ? static_cast<void> (0) : __assert_fail ("(!HasOptPRefs || !HasPhysRegOuts) && \"Unable to cope with optional defs and phys regs defs!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 893, __PRETTY_FUNCTION__))
;
894 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
895 for (unsigned i = NumSkip; i != NodeOperands; ++i)
896 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
897 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
898
899 // Add scratch registers as implicit def and early clobber
900 if (ScratchRegs)
901 for (unsigned i = 0; ScratchRegs[i]; ++i)
902 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
903 RegState::EarlyClobber);
904
905 // Set the memory reference descriptions of this instruction now that it is
906 // part of the function.
907 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
908
909 // Insert the instruction into position in the block. This needs to
910 // happen before any custom inserter hook is called so that the
911 // hook knows where in the block to insert the replacement code.
912 MBB->insert(InsertPos, MIB);
913
914 // The MachineInstr may also define physregs instead of virtregs. These
915 // physreg values can reach other instructions in different ways:
916 //
917 // 1. When there is a use of a Node value beyond the explicitly defined
918 // virtual registers, we emit a CopyFromReg for one of the implicitly
919 // defined physregs. This only happens when HasPhysRegOuts is true.
920 //
921 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
922 //
923 // 3. A glued instruction may implicitly use a physreg.
924 //
925 // 4. A glued instruction may use a RegisterSDNode operand.
926 //
927 // Collect all the used physreg defs, and make sure that any unused physreg
928 // defs are marked as dead.
929 SmallVector<Register, 8> UsedRegs;
930
931 // Additional results must be physical register defs.
932 if (HasPhysRegOuts) {
933 for (unsigned i = NumDefs; i < NumResults; ++i) {
934 Register Reg = II.getImplicitDefs()[i - NumDefs];
935 if (!Node->hasAnyUseOfValue(i))
936 continue;
937 // This implicitly defined physreg has a use.
938 UsedRegs.push_back(Reg);
939 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
940 }
941 }
942
943 // Scan the glue chain for any used physregs.
944 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
945 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
946 if (F->getOpcode() == ISD::CopyFromReg) {
947 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
948 continue;
949 } else if (F->getOpcode() == ISD::CopyToReg) {
950 // Skip CopyToReg nodes that are internal to the glue chain.
951 continue;
952 }
953 // Collect declared implicit uses.
954 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
955 UsedRegs.append(MCID.getImplicitUses(),
956 MCID.getImplicitUses() + MCID.getNumImplicitUses());
957 // In addition to declared implicit uses, we must also check for
958 // direct RegisterSDNode operands.
959 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
960 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
961 Register Reg = R->getReg();
962 if (Reg.isPhysical())
963 UsedRegs.push_back(Reg);
964 }
965 }
966 }
967
968 // Finally mark unused registers as dead.
969 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
970 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
971
972 // Run post-isel target hook to adjust this instruction if needed.
973 if (II.hasPostISelHook())
974 TLI->AdjustInstrPostInstrSelection(*MIB, Node);
975}
976
977/// EmitSpecialNode - Generate machine code for a target-independent node and
978/// needed dependencies.
979void InstrEmitter::
980EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
981 DenseMap<SDValue, unsigned> &VRBaseMap) {
982 switch (Node->getOpcode()) {
1
Control jumps to 'case CopyToReg:' at line 993
983 default:
984#ifndef NDEBUG
985 Node->dump();
986#endif
987 llvm_unreachable("This target-independent node should have been selected!")::llvm::llvm_unreachable_internal("This target-independent node should have been selected!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 987)
;
988 case ISD::EntryToken:
989 llvm_unreachable("EntryToken should have been excluded from the schedule!")::llvm::llvm_unreachable_internal("EntryToken should have been excluded from the schedule!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 989)
;
990 case ISD::MERGE_VALUES:
991 case ISD::TokenFactor: // fall thru
992 break;
993 case ISD::CopyToReg: {
994 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
995 SDValue SrcVal = Node->getOperand(2);
996 if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
997 SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
998 // Instead building a COPY to that vreg destination, build an
999 // IMPLICIT_DEF instruction instead.
1000 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1001 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1002 break;
1003 }
1004 unsigned SrcReg;
1005 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
2
Assuming 'R' is null
3
Taking false branch
1006 SrcReg = R->getReg();
1007 else
1008 SrcReg = getVR(SrcVal, VRBaseMap);
4
Value assigned to 'Op.Node'
5
Calling 'InstrEmitter::getVR'
1009
1010 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1011 break;
1012
1013 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1014 DestReg).addReg(SrcReg);
1015 break;
1016 }
1017 case ISD::CopyFromReg: {
1018 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1019 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1020 break;
1021 }
1022 case ISD::EH_LABEL:
1023 case ISD::ANNOTATION_LABEL: {
1024 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1025 ? TargetOpcode::EH_LABEL
1026 : TargetOpcode::ANNOTATION_LABEL;
1027 MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1028 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1029 TII->get(Opc)).addSym(S);
1030 break;
1031 }
1032
1033 case ISD::LIFETIME_START:
1034 case ISD::LIFETIME_END: {
1035 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1036 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
1037
1038 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
1039 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1040 .addFrameIndex(FI->getIndex());
1041 break;
1042 }
1043
1044 case ISD::INLINEASM:
1045 case ISD::INLINEASM_BR: {
1046 unsigned NumOps = Node->getNumOperands();
1047 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1048 --NumOps; // Ignore the glue operand.
1049
1050 // Create the inline asm machine instruction.
1051 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1052 ? TargetOpcode::INLINEASM_BR
1053 : TargetOpcode::INLINEASM;
1054 MachineInstrBuilder MIB =
1055 BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1056
1057 // Add the asm string as an external symbol operand.
1058 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1059 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1060 MIB.addExternalSymbol(AsmStr);
1061
1062 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1063 // bits.
1064 int64_t ExtraInfo =
1065 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1066 getZExtValue();
1067 MIB.addImm(ExtraInfo);
1068
1069 // Remember to operand index of the group flags.
1070 SmallVector<unsigned, 8> GroupIdx;
1071
1072 // Remember registers that are part of early-clobber defs.
1073 SmallVector<unsigned, 8> ECRegs;
1074
1075 // Add all of the operand registers to the instruction.
1076 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1077 unsigned Flags =
1078 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1079 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1080
1081 GroupIdx.push_back(MIB->getNumOperands());
1082 MIB.addImm(Flags);
1083 ++i; // Skip the ID value.
1084
1085 switch (InlineAsm::getKind(Flags)) {
1086 default: llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1086)
;
1087 case InlineAsm::Kind_RegDef:
1088 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1089 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1090 // FIXME: Add dead flags for physical and virtual registers defined.
1091 // For now, mark physical register defs as implicit to help fast
1092 // regalloc. This makes inline asm look a lot like calls.
1093 MIB.addReg(Reg,
1094 RegState::Define |
1095 getImplRegState(Register::isPhysicalRegister(Reg)));
1096 }
1097 break;
1098 case InlineAsm::Kind_RegDefEarlyClobber:
1099 case InlineAsm::Kind_Clobber:
1100 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1101 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1102 MIB.addReg(Reg,
1103 RegState::Define | RegState::EarlyClobber |
1104 getImplRegState(Register::isPhysicalRegister(Reg)));
1105 ECRegs.push_back(Reg);
1106 }
1107 break;
1108 case InlineAsm::Kind_RegUse: // Use of register.
1109 case InlineAsm::Kind_Imm: // Immediate.
1110 case InlineAsm::Kind_Mem: // Addressing mode.
1111 // The addressing mode has been selected, just add all of the
1112 // operands to the machine instruction.
1113 for (unsigned j = 0; j != NumVals; ++j, ++i)
1114 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1115 /*IsDebug=*/false, IsClone, IsCloned);
1116
1117 // Manually set isTied bits.
1118 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
1119 unsigned DefGroup = 0;
1120 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1121 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1122 unsigned UseIdx = GroupIdx.back() + 1;
1123 for (unsigned j = 0; j != NumVals; ++j)
1124 MIB->tieOperands(DefIdx + j, UseIdx + j);
1125 }
1126 }
1127 break;
1128 }
1129 }
1130
1131 // GCC inline assembly allows input operands to also be early-clobber
1132 // output operands (so long as the operand is written only after it's
1133 // used), but this does not match the semantics of our early-clobber flag.
1134 // If an early-clobber operand register is also an input operand register,
1135 // then remove the early-clobber flag.
1136 for (unsigned Reg : ECRegs) {
1137 if (MIB->readsRegister(Reg, TRI)) {
1138 MachineOperand *MO =
1139 MIB->findRegisterDefOperand(Reg, false, false, TRI);
1140 assert(MO && "No def operand for clobbered register?")((MO && "No def operand for clobbered register?") ? static_cast
<void> (0) : __assert_fail ("MO && \"No def operand for clobbered register?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1140, __PRETTY_FUNCTION__))
;
1141 MO->setIsEarlyClobber(false);
1142 }
1143 }
1144
1145 // Get the mdnode from the asm if it exists and add it to the instruction.
1146 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1147 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1148 if (MD)
1149 MIB.addMetadata(MD);
1150
1151 MBB->insert(InsertPos, MIB);
1152 break;
1153 }
1154 }
1155}
1156
1157/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1158/// at the given position in the given block.
1159InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1160 MachineBasicBlock::iterator insertpos)
1161 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1162 TII(MF->getSubtarget().getInstrInfo()),
1163 TRI(MF->getSubtarget().getRegisterInfo()),
1164 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1165 InsertPos(insertpos) {}

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/Constants.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Instruction.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/Metadata.h"
39#include "llvm/IR/Operator.h"
40#include "llvm/Support/AlignOf.h"
41#include "llvm/Support/AtomicOrdering.h"
42#include "llvm/Support/Casting.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MachineValueType.h"
45#include "llvm/Support/TypeSize.h"
46#include <algorithm>
47#include <cassert>
48#include <climits>
49#include <cstddef>
50#include <cstdint>
51#include <cstring>
52#include <iterator>
53#include <string>
54#include <tuple>
55
56namespace llvm {
57
58class APInt;
59class Constant;
60template <typename T> struct DenseMapInfo;
61class GlobalValue;
62class MachineBasicBlock;
63class MachineConstantPoolValue;
64class MCSymbol;
65class raw_ostream;
66class SDNode;
67class SelectionDAG;
68class Type;
69class Value;
70
71void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
72 bool force = false);
73
74/// This represents a list of ValueType's that has been intern'd by
75/// a SelectionDAG. Instances of this simple value class are returned by
76/// SelectionDAG::getVTList(...).
77///
78struct SDVTList {
79 const EVT *VTs;
80 unsigned int NumVTs;
81};
82
83namespace ISD {
84
85 /// Node predicates
86
87 /// If N is a BUILD_VECTOR node whose elements are all the same constant or
88 /// undefined, return true and return the constant value in \p SplatValue.
89 bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
90
91 /// Return true if the specified node is a BUILD_VECTOR where all of the
92 /// elements are ~0 or undef.
93 bool isBuildVectorAllOnes(const SDNode *N);
94
95 /// Return true if the specified node is a BUILD_VECTOR where all of the
96 /// elements are 0 or undef.
97 bool isBuildVectorAllZeros(const SDNode *N);
98
99 /// Return true if the specified node is a BUILD_VECTOR node of all
100 /// ConstantSDNode or undef.
101 bool isBuildVectorOfConstantSDNodes(const SDNode *N);
102
103 /// Return true if the specified node is a BUILD_VECTOR node of all
104 /// ConstantFPSDNode or undef.
105 bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
106
107 /// Return true if the node has at least one operand and all operands of the
108 /// specified node are ISD::UNDEF.
109 bool allOperandsUndef(const SDNode *N);
110
111} // end namespace ISD
112
113//===----------------------------------------------------------------------===//
114/// Unlike LLVM values, Selection DAG nodes may return multiple
115/// values as the result of a computation. Many nodes return multiple values,
116/// from loads (which define a token and a return value) to ADDC (which returns
117/// a result and a carry value), to calls (which may return an arbitrary number
118/// of values).
119///
120/// As such, each use of a SelectionDAG computation must indicate the node that
121/// computes it as well as which return value to use from that node. This pair
122/// of information is represented with the SDValue value type.
123///
124class SDValue {
125 friend struct DenseMapInfo<SDValue>;
126
127 SDNode *Node = nullptr; // The node defining the value we are using.
128 unsigned ResNo = 0; // Which return value of the node we are using.
129
130public:
131 SDValue() = default;
132 SDValue(SDNode *node, unsigned resno);
133
134 /// get the index which selects a specific result in the SDNode
135 unsigned getResNo() const { return ResNo; }
136
137 /// get the SDNode which holds the desired result
138 SDNode *getNode() const { return Node; }
139
140 /// set the SDNode
141 void setNode(SDNode *N) { Node = N; }
142
143 inline SDNode *operator->() const { return Node; }
144
145 bool operator==(const SDValue &O) const {
146 return Node == O.Node && ResNo == O.ResNo;
147 }
148 bool operator!=(const SDValue &O) const {
149 return !operator==(O);
150 }
151 bool operator<(const SDValue &O) const {
152 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
153 }
154 explicit operator bool() const {
155 return Node != nullptr;
156 }
157
158 SDValue getValue(unsigned R) const {
159 return SDValue(Node, R);
160 }
161
162 /// Return true if this node is an operand of N.
163 bool isOperandOf(const SDNode *N) const;
164
165 /// Return the ValueType of the referenced return value.
166 inline EVT getValueType() const;
167
168 /// Return the simple ValueType of the referenced return value.
169 MVT getSimpleValueType() const {
170 return getValueType().getSimpleVT();
171 }
172
173 /// Returns the size of the value in bits.
174 ///
175 /// If the value type is a scalable vector type, the scalable property will
176 /// be set and the runtime size will be a positive integer multiple of the
177 /// base size.
178 TypeSize getValueSizeInBits() const {
179 return getValueType().getSizeInBits();
180 }
181
182 TypeSize getScalarValueSizeInBits() const {
183 return getValueType().getScalarType().getSizeInBits();
184 }
185
186 // Forwarding methods - These forward to the corresponding methods in SDNode.
187 inline unsigned getOpcode() const;
188 inline unsigned getNumOperands() const;
189 inline const SDValue &getOperand(unsigned i) const;
190 inline uint64_t getConstantOperandVal(unsigned i) const;
191 inline const APInt &getConstantOperandAPInt(unsigned i) const;
192 inline bool isTargetMemoryOpcode() const;
193 inline bool isTargetOpcode() const;
194 inline bool isMachineOpcode() const;
195 inline bool isUndef() const;
196 inline unsigned getMachineOpcode() const;
197 inline const DebugLoc &getDebugLoc() const;
198 inline void dump() const;
199 inline void dump(const SelectionDAG *G) const;
200 inline void dumpr() const;
201 inline void dumpr(const SelectionDAG *G) const;
202
203 /// Return true if this operand (which must be a chain) reaches the
204 /// specified operand without crossing any side-effecting instructions.
205 /// In practice, this looks through token factors and non-volatile loads.
206 /// In order to remain efficient, this only
207 /// looks a couple of nodes in, it does not do an exhaustive search.
208 bool reachesChainWithoutSideEffects(SDValue Dest,
209 unsigned Depth = 2) const;
210
211 /// Return true if there are no nodes using value ResNo of Node.
212 inline bool use_empty() const;
213
214 /// Return true if there is exactly one node using value ResNo of Node.
215 inline bool hasOneUse() const;
216};
217
218template<> struct DenseMapInfo<SDValue> {
219 static inline SDValue getEmptyKey() {
220 SDValue V;
221 V.ResNo = -1U;
222 return V;
223 }
224
225 static inline SDValue getTombstoneKey() {
226 SDValue V;
227 V.ResNo = -2U;
228 return V;
229 }
230
231 static unsigned getHashValue(const SDValue &Val) {
232 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
233 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
234 }
235
236 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
237 return LHS == RHS;
238 }
239};
240
241/// Allow casting operators to work directly on
242/// SDValues as if they were SDNode*'s.
243template<> struct simplify_type<SDValue> {
244 using SimpleType = SDNode *;
245
246 static SimpleType getSimplifiedValue(SDValue &Val) {
247 return Val.getNode();
248 }
249};
250template<> struct simplify_type<const SDValue> {
251 using SimpleType = /*const*/ SDNode *;
252
253 static SimpleType getSimplifiedValue(const SDValue &Val) {
254 return Val.getNode();
255 }
256};
257
258/// Represents a use of a SDNode. This class holds an SDValue,
259/// which records the SDNode being used and the result number, a
260/// pointer to the SDNode using the value, and Next and Prev pointers,
261/// which link together all the uses of an SDNode.
262///
263class SDUse {
264 /// Val - The value being used.
265 SDValue Val;
266 /// User - The user of this value.
267 SDNode *User = nullptr;
268 /// Prev, Next - Pointers to the uses list of the SDNode referred by
269 /// this operand.
270 SDUse **Prev = nullptr;
271 SDUse *Next = nullptr;
272
273public:
274 SDUse() = default;
275 SDUse(const SDUse &U) = delete;
276 SDUse &operator=(const SDUse &) = delete;
277
278 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
279 operator const SDValue&() const { return Val; }
280
281 /// If implicit conversion to SDValue doesn't work, the get() method returns
282 /// the SDValue.
283 const SDValue &get() const { return Val; }
284
285 /// This returns the SDNode that contains this Use.
286 SDNode *getUser() { return User; }
287
288 /// Get the next SDUse in the use list.
289 SDUse *getNext() const { return Next; }
290
291 /// Convenience function for get().getNode().
292 SDNode *getNode() const { return Val.getNode(); }
293 /// Convenience function for get().getResNo().
294 unsigned getResNo() const { return Val.getResNo(); }
295 /// Convenience function for get().getValueType().
296 EVT getValueType() const { return Val.getValueType(); }
297
298 /// Convenience function for get().operator==
299 bool operator==(const SDValue &V) const {
300 return Val == V;
301 }
302
303 /// Convenience function for get().operator!=
304 bool operator!=(const SDValue &V) const {
305 return Val != V;
306 }
307
308 /// Convenience function for get().operator<
309 bool operator<(const SDValue &V) const {
310 return Val < V;
311 }
312
313private:
314 friend class SelectionDAG;
315 friend class SDNode;
316 // TODO: unfriend HandleSDNode once we fix its operand handling.
317 friend class HandleSDNode;
318
319 void setUser(SDNode *p) { User = p; }
320
321 /// Remove this use from its existing use list, assign it the
322 /// given value, and add it to the new value's node's use list.
323 inline void set(const SDValue &V);
324 /// Like set, but only supports initializing a newly-allocated
325 /// SDUse with a non-null value.
326 inline void setInitial(const SDValue &V);
327 /// Like set, but only sets the Node portion of the value,
328 /// leaving the ResNo portion unmodified.
329 inline void setNode(SDNode *N);
330
331 void addToList(SDUse **List) {
332 Next = *List;
333 if (Next) Next->Prev = &Next;
334 Prev = List;
335 *List = this;
336 }
337
338 void removeFromList() {
339 *Prev = Next;
340 if (Next) Next->Prev = Prev;
341 }
342};
343
344/// simplify_type specializations - Allow casting operators to work directly on
345/// SDValues as if they were SDNode*'s.
346template<> struct simplify_type<SDUse> {
347 using SimpleType = SDNode *;
348
349 static SimpleType getSimplifiedValue(SDUse &Val) {
350 return Val.getNode();
351 }
352};
353
354/// These are IR-level optimization flags that may be propagated to SDNodes.
355/// TODO: This data structure should be shared by the IR optimizer and the
356/// the backend.
357struct SDNodeFlags {
358private:
359 // This bit is used to determine if the flags are in a defined state.
360 // Flag bits can only be masked out during intersection if the masking flags
361 // are defined.
362 bool AnyDefined : 1;
363
364 bool NoUnsignedWrap : 1;
365 bool NoSignedWrap : 1;
366 bool Exact : 1;
367 bool NoNaNs : 1;
368 bool NoInfs : 1;
369 bool NoSignedZeros : 1;
370 bool AllowReciprocal : 1;
371 bool VectorReduction : 1;
372 bool AllowContract : 1;
373 bool ApproximateFuncs : 1;
374 bool AllowReassociation : 1;
375
376 // We assume instructions do not raise floating-point exceptions by default,
377 // and only those marked explicitly may do so. We could choose to represent
378 // this via a positive "FPExcept" flags like on the MI level, but having a
379 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
380 // intersection logic more straightforward.
381 bool NoFPExcept : 1;
382
383public:
384 /// Default constructor turns off all optimization flags.
385 SDNodeFlags()
386 : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
387 Exact(false), NoNaNs(false), NoInfs(false),
388 NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
389 AllowContract(false), ApproximateFuncs(false),
390 AllowReassociation(false), NoFPExcept(false) {}
391
392 /// Propagate the fast-math-flags from an IR FPMathOperator.
393 void copyFMF(const FPMathOperator &FPMO) {
394 setNoNaNs(FPMO.hasNoNaNs());
395 setNoInfs(FPMO.hasNoInfs());
396 setNoSignedZeros(FPMO.hasNoSignedZeros());
397 setAllowReciprocal(FPMO.hasAllowReciprocal());
398 setAllowContract(FPMO.hasAllowContract());
399 setApproximateFuncs(FPMO.hasApproxFunc());
400 setAllowReassociation(FPMO.hasAllowReassoc());
401 }
402
403 /// Sets the state of the flags to the defined state.
404 void setDefined() { AnyDefined = true; }
405 /// Returns true if the flags are in a defined state.
406 bool isDefined() const { return AnyDefined; }
407
408 // These are mutators for each flag.
409 void setNoUnsignedWrap(bool b) {
410 setDefined();
411 NoUnsignedWrap = b;
412 }
413 void setNoSignedWrap(bool b) {
414 setDefined();
415 NoSignedWrap = b;
416 }
417 void setExact(bool b) {
418 setDefined();
419 Exact = b;
420 }
421 void setNoNaNs(bool b) {
422 setDefined();
423 NoNaNs = b;
424 }
425 void setNoInfs(bool b) {
426 setDefined();
427 NoInfs = b;
428 }
429 void setNoSignedZeros(bool b) {
430 setDefined();
431 NoSignedZeros = b;
432 }
433 void setAllowReciprocal(bool b) {
434 setDefined();
435 AllowReciprocal = b;
436 }
437 void setVectorReduction(bool b) {
438 setDefined();
439 VectorReduction = b;
440 }
441 void setAllowContract(bool b) {
442 setDefined();
443 AllowContract = b;
444 }
445 void setApproximateFuncs(bool b) {
446 setDefined();
447 ApproximateFuncs = b;
448 }
449 void setAllowReassociation(bool b) {
450 setDefined();
451 AllowReassociation = b;
452 }
453 void setNoFPExcept(bool b) {
454 setDefined();
455 NoFPExcept = b;
456 }
457
458 // These are accessors for each flag.
459 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
460 bool hasNoSignedWrap() const { return NoSignedWrap; }
461 bool hasExact() const { return Exact; }
462 bool hasNoNaNs() const { return NoNaNs; }
463 bool hasNoInfs() const { return NoInfs; }
464 bool hasNoSignedZeros() const { return NoSignedZeros; }
465 bool hasAllowReciprocal() const { return AllowReciprocal; }
466 bool hasVectorReduction() const { return VectorReduction; }
467 bool hasAllowContract() const { return AllowContract; }
468 bool hasApproximateFuncs() const { return ApproximateFuncs; }
469 bool hasAllowReassociation() const { return AllowReassociation; }
470 bool hasNoFPExcept() const { return NoFPExcept; }
471
472 bool isFast() const {
473 return NoSignedZeros && AllowReciprocal && NoNaNs && NoInfs && NoFPExcept &&
474 AllowContract && ApproximateFuncs && AllowReassociation;
475 }
476
477 /// Clear any flags in this flag set that aren't also set in Flags.
478 /// If the given Flags are undefined then don't do anything.
479 void intersectWith(const SDNodeFlags Flags) {
480 if (!Flags.isDefined())
481 return;
482 NoUnsignedWrap &= Flags.NoUnsignedWrap;
483 NoSignedWrap &= Flags.NoSignedWrap;
484 Exact &= Flags.Exact;
485 NoNaNs &= Flags.NoNaNs;
486 NoInfs &= Flags.NoInfs;
487 NoSignedZeros &= Flags.NoSignedZeros;
488 AllowReciprocal &= Flags.AllowReciprocal;
489 VectorReduction &= Flags.VectorReduction;
490 AllowContract &= Flags.AllowContract;
491 ApproximateFuncs &= Flags.ApproximateFuncs;
492 AllowReassociation &= Flags.AllowReassociation;
493 NoFPExcept &= Flags.NoFPExcept;
494 }
495};
496
497/// Represents one node in the SelectionDAG.
498///
499class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
500private:
501 /// The operation that this node performs.
502 int16_t NodeType;
503
504protected:
505 // We define a set of mini-helper classes to help us interpret the bits in our
506 // SubclassData. These are designed to fit within a uint16_t so they pack
507 // with NodeType.
508
509#if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__))
510// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
511// and give the `pack` pragma push semantics.
512#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
513#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
514#else
515#define BEGIN_TWO_BYTE_PACK()
516#define END_TWO_BYTE_PACK()
517#endif
518
519BEGIN_TWO_BYTE_PACK()
520 class SDNodeBitfields {
521 friend class SDNode;
522 friend class MemIntrinsicSDNode;
523 friend class MemSDNode;
524 friend class SelectionDAG;
525
526 uint16_t HasDebugValue : 1;
527 uint16_t IsMemIntrinsic : 1;
528 uint16_t IsDivergent : 1;
529 };
530 enum { NumSDNodeBits = 3 };
531
532 class ConstantSDNodeBitfields {
533 friend class ConstantSDNode;
534
535 uint16_t : NumSDNodeBits;
536
537 uint16_t IsOpaque : 1;
538 };
539
540 class MemSDNodeBitfields {
541 friend class MemSDNode;
542 friend class MemIntrinsicSDNode;
543 friend class AtomicSDNode;
544
545 uint16_t : NumSDNodeBits;
546
547 uint16_t IsVolatile : 1;
548 uint16_t IsNonTemporal : 1;
549 uint16_t IsDereferenceable : 1;
550 uint16_t IsInvariant : 1;
551 };
552 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
553
554 class LSBaseSDNodeBitfields {
555 friend class LSBaseSDNode;
556 friend class MaskedLoadStoreSDNode;
557 friend class MaskedGatherScatterSDNode;
558
559 uint16_t : NumMemSDNodeBits;
560
561 // This storage is shared between disparate class hierarchies to hold an
562 // enumeration specific to the class hierarchy in use.
563 // LSBaseSDNode => enum ISD::MemIndexedMode
564 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
565 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
566 uint16_t AddressingMode : 3;
567 };
568 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
569
570 class LoadSDNodeBitfields {
571 friend class LoadSDNode;
572 friend class MaskedLoadSDNode;
573
574 uint16_t : NumLSBaseSDNodeBits;
575
576 uint16_t ExtTy : 2; // enum ISD::LoadExtType
577 uint16_t IsExpanding : 1;
578 };
579
580 class StoreSDNodeBitfields {
581 friend class StoreSDNode;
582 friend class MaskedStoreSDNode;
583
584 uint16_t : NumLSBaseSDNodeBits;
585
586 uint16_t IsTruncating : 1;
587 uint16_t IsCompressing : 1;
588 };
589
590 union {
591 char RawSDNodeBits[sizeof(uint16_t)];
592 SDNodeBitfields SDNodeBits;
593 ConstantSDNodeBitfields ConstantSDNodeBits;
594 MemSDNodeBitfields MemSDNodeBits;
595 LSBaseSDNodeBitfields LSBaseSDNodeBits;
596 LoadSDNodeBitfields LoadSDNodeBits;
597 StoreSDNodeBitfields StoreSDNodeBits;
598 };
599END_TWO_BYTE_PACK()
600#undef BEGIN_TWO_BYTE_PACK
601#undef END_TWO_BYTE_PACK
602
603 // RawSDNodeBits must cover the entirety of the union. This means that all of
604 // the union's members must have size <= RawSDNodeBits. We write the RHS as
605 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
606 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
607 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
608 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
609 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
610 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
611 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
612
613private:
614 friend class SelectionDAG;
615 // TODO: unfriend HandleSDNode once we fix its operand handling.
616 friend class HandleSDNode;
617
618 /// Unique id per SDNode in the DAG.
619 int NodeId = -1;
620
621 /// The values that are used by this operation.
622 SDUse *OperandList = nullptr;
623
624 /// The types of the values this node defines. SDNode's may
625 /// define multiple values simultaneously.
626 const EVT *ValueList;
627
628 /// List of uses for this SDNode.
629 SDUse *UseList = nullptr;
630
631 /// The number of entries in the Operand/Value list.
632 unsigned short NumOperands = 0;
633 unsigned short NumValues;
634
635 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
636 // original LLVM instructions.
637 // This is used for turning off scheduling, because we'll forgo
638 // the normal scheduling algorithms and output the instructions according to
639 // this ordering.
640 unsigned IROrder;
641
642 /// Source line information.
643 DebugLoc debugLoc;
644
645 /// Return a pointer to the specified value type.
646 static const EVT *getValueTypeList(EVT VT);
647
648 SDNodeFlags Flags;
649
650public:
651 /// Unique and persistent id per SDNode in the DAG.
652 /// Used for debug printing.
653 uint16_t PersistentId;
654
655 //===--------------------------------------------------------------------===//
656 // Accessors
657 //
658
659 /// Return the SelectionDAG opcode value for this node. For
660 /// pre-isel nodes (those for which isMachineOpcode returns false), these
661 /// are the opcode values in the ISD and <target>ISD namespaces. For
662 /// post-isel opcodes, see getMachineOpcode.
663 unsigned getOpcode() const { return (unsigned short)NodeType; }
664
665 /// Test if this node has a target-specific opcode (in the
666 /// \<target\>ISD namespace).
667 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
668
669 /// Test if this node has a target-specific opcode that may raise
670 /// FP exceptions (in the \<target\>ISD namespace and greater than
671 /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
672 /// opcode are currently automatically considered to possibly raise
673 /// FP exceptions as well.
674 bool isTargetStrictFPOpcode() const {
675 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
676 }
677
678 /// Test if this node has a target-specific
679 /// memory-referencing opcode (in the \<target\>ISD namespace and
680 /// greater than FIRST_TARGET_MEMORY_OPCODE).
681 bool isTargetMemoryOpcode() const {
682 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
683 }
684
685 /// Return true if the type of the node type undefined.
686 bool isUndef() const { return NodeType == ISD::UNDEF; }
687
688 /// Test if this node is a memory intrinsic (with valid pointer information).
689 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
690 /// non-memory intrinsics (with chains) that are not really instances of
691 /// MemSDNode. For such nodes, we need some extra state to determine the
692 /// proper classof relationship.
693 bool isMemIntrinsic() const {
694 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
695 NodeType == ISD::INTRINSIC_VOID) &&
696 SDNodeBits.IsMemIntrinsic;
697 }
698
699 /// Test if this node is a strict floating point pseudo-op.
700 bool isStrictFPOpcode() {
701 switch (NodeType) {
702 default:
703 return false;
704#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
705 case ISD::STRICT_##DAGN:
706#include "llvm/IR/ConstrainedOps.def"
707 return true;
708 }
709 }
710
711 /// Test if this node has a post-isel opcode, directly
712 /// corresponding to a MachineInstr opcode.
713 bool isMachineOpcode() const { return NodeType < 0; }
714
715 /// This may only be called if isMachineOpcode returns
716 /// true. It returns the MachineInstr opcode value that the node's opcode
717 /// corresponds to.
718 unsigned getMachineOpcode() const {
719 assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 719, __PRETTY_FUNCTION__))
;
720 return ~NodeType;
721 }
722
723 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
724 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
725
726 bool isDivergent() const { return SDNodeBits.IsDivergent; }
727
728 /// Return true if there are no uses of this node.
729 bool use_empty() const { return UseList == nullptr; }
730
731 /// Return true if there is exactly one use of this node.
732 bool hasOneUse() const {
733 return !use_empty() && std::next(use_begin()) == use_end();
734 }
735
736 /// Return the number of uses of this node. This method takes
737 /// time proportional to the number of uses.
738 size_t use_size() const { return std::distance(use_begin(), use_end()); }
739
740 /// Return the unique node id.
741 int getNodeId() const { return NodeId; }
742
743 /// Set unique node id.
744 void setNodeId(int Id) { NodeId = Id; }
745
746 /// Return the node ordering.
747 unsigned getIROrder() const { return IROrder; }
748
749 /// Set the node ordering.
750 void setIROrder(unsigned Order) { IROrder = Order; }
751
752 /// Return the source location info.
753 const DebugLoc &getDebugLoc() const { return debugLoc; }
754
755 /// Set source location info. Try to avoid this, putting
756 /// it in the constructor is preferable.
757 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
758
759 /// This class provides iterator support for SDUse
760 /// operands that use a specific SDNode.
761 class use_iterator
762 : public std::iterator<std::forward_iterator_tag, SDUse, ptrdiff_t> {
763 friend class SDNode;
764
765 SDUse *Op = nullptr;
766
767 explicit use_iterator(SDUse *op) : Op(op) {}
768
769 public:
770 using reference = std::iterator<std::forward_iterator_tag,
771 SDUse, ptrdiff_t>::reference;
772 using pointer = std::iterator<std::forward_iterator_tag,
773 SDUse, ptrdiff_t>::pointer;
774
775 use_iterator() = default;
776 use_iterator(const use_iterator &I) : Op(I.Op) {}
777
778 bool operator==(const use_iterator &x) const {
779 return Op == x.Op;
780 }
781 bool operator!=(const use_iterator &x) const {
782 return !operator==(x);
783 }
784
785 /// Return true if this iterator is at the end of uses list.
786 bool atEnd() const { return Op == nullptr; }
787
788 // Iterator traversal: forward iteration only.
789 use_iterator &operator++() { // Preincrement
790 assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 790, __PRETTY_FUNCTION__))
;
791 Op = Op->getNext();
792 return *this;
793 }
794
795 use_iterator operator++(int) { // Postincrement
796 use_iterator tmp = *this; ++*this; return tmp;
797 }
798
799 /// Retrieve a pointer to the current user node.
800 SDNode *operator*() const {
801 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 801, __PRETTY_FUNCTION__))
;
802 return Op->getUser();
803 }
804
805 SDNode *operator->() const { return operator*(); }
806
807 SDUse &getUse() const { return *Op; }
808
809 /// Retrieve the operand # of this use in its user.
810 unsigned getOperandNo() const {
811 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 811, __PRETTY_FUNCTION__))
;
812 return (unsigned)(Op - Op->getUser()->OperandList);
813 }
814 };
815
816 /// Provide iteration support to walk over all uses of an SDNode.
817 use_iterator use_begin() const {
818 return use_iterator(UseList);
819 }
820
821 static use_iterator use_end() { return use_iterator(nullptr); }
822
823 inline iterator_range<use_iterator> uses() {
824 return make_range(use_begin(), use_end());
825 }
826 inline iterator_range<use_iterator> uses() const {
827 return make_range(use_begin(), use_end());
828 }
829
830 /// Return true if there are exactly NUSES uses of the indicated value.
831 /// This method ignores uses of other values defined by this operation.
832 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
833
834 /// Return true if there are any use of the indicated value.
835 /// This method ignores uses of other values defined by this operation.
836 bool hasAnyUseOfValue(unsigned Value) const;
837
838 /// Return true if this node is the only use of N.
839 bool isOnlyUserOf(const SDNode *N) const;
840
841 /// Return true if this node is an operand of N.
842 bool isOperandOf(const SDNode *N) const;
843
844 /// Return true if this node is a predecessor of N.
845 /// NOTE: Implemented on top of hasPredecessor and every bit as
846 /// expensive. Use carefully.
847 bool isPredecessorOf(const SDNode *N) const {
848 return N->hasPredecessor(this);
849 }
850
851 /// Return true if N is a predecessor of this node.
852 /// N is either an operand of this node, or can be reached by recursively
853 /// traversing up the operands.
854 /// NOTE: This is an expensive method. Use it carefully.
855 bool hasPredecessor(const SDNode *N) const;
856
857 /// Returns true if N is a predecessor of any node in Worklist. This
858 /// helper keeps Visited and Worklist sets externally to allow unions
859 /// searches to be performed in parallel, caching of results across
860 /// queries and incremental addition to Worklist. Stops early if N is
861 /// found but will resume. Remember to clear Visited and Worklists
862 /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
863 /// giving up. The TopologicalPrune flag signals that positive NodeIds are
864 /// topologically ordered (Operands have strictly smaller node id) and search
865 /// can be pruned leveraging this.
866 static bool hasPredecessorHelper(const SDNode *N,
867 SmallPtrSetImpl<const SDNode *> &Visited,
868 SmallVectorImpl<const SDNode *> &Worklist,
869 unsigned int MaxSteps = 0,
870 bool TopologicalPrune = false) {
871 SmallVector<const SDNode *, 8> DeferredNodes;
872 if (Visited.count(N))
873 return true;
874
875 // Node Id's are assigned in three places: As a topological
876 // ordering (> 0), during legalization (results in values set to
877 // 0), new nodes (set to -1). If N has a topolgical id then we
878 // know that all nodes with ids smaller than it cannot be
879 // successors and we need not check them. Filter out all node
880 // that can't be matches. We add them to the worklist before exit
881 // in case of multiple calls. Note that during selection the topological id
882 // may be violated if a node's predecessor is selected before it. We mark
883 // this at selection negating the id of unselected successors and
884 // restricting topological pruning to positive ids.
885
886 int NId = N->getNodeId();
887 // If we Invalidated the Id, reconstruct original NId.
888 if (NId < -1)
889 NId = -(NId + 1);
890
891 bool Found = false;
892 while (!Worklist.empty()) {
893 const SDNode *M = Worklist.pop_back_val();
894 int MId = M->getNodeId();
895 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
896 (MId > 0) && (MId < NId)) {
897 DeferredNodes.push_back(M);
898 continue;
899 }
900 for (const SDValue &OpV : M->op_values()) {
901 SDNode *Op = OpV.getNode();
902 if (Visited.insert(Op).second)
903 Worklist.push_back(Op);
904 if (Op == N)
905 Found = true;
906 }
907 if (Found)
908 break;
909 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
910 break;
911 }
912 // Push deferred nodes back on worklist.
913 Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
914 // If we bailed early, conservatively return found.
915 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
916 return true;
917 return Found;
918 }
919
920 /// Return true if all the users of N are contained in Nodes.
921 /// NOTE: Requires at least one match, but doesn't require them all.
922 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
923
924 /// Return the number of values used by this operation.
925 unsigned getNumOperands() const { return NumOperands; }
926
927 /// Return the maximum number of operands that a SDNode can hold.
928 static constexpr size_t getMaxNumOperands() {
929 return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
930 }
931
932 /// Helper method returns the integer value of a ConstantSDNode operand.
933 inline uint64_t getConstantOperandVal(unsigned Num) const;
934
935 /// Helper method returns the APInt of a ConstantSDNode operand.
936 inline const APInt &getConstantOperandAPInt(unsigned Num) const;
937
938 const SDValue &getOperand(unsigned Num) const {
939 assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 939, __PRETTY_FUNCTION__))
;
940 return OperandList[Num];
941 }
942
943 using op_iterator = SDUse *;
944
945 op_iterator op_begin() const { return OperandList; }
946 op_iterator op_end() const { return OperandList+NumOperands; }
947 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
948
949 /// Iterator for directly iterating over the operand SDValue's.
950 struct value_op_iterator
951 : iterator_adaptor_base<value_op_iterator, op_iterator,
952 std::random_access_iterator_tag, SDValue,
953 ptrdiff_t, value_op_iterator *,
954 value_op_iterator *> {
955 explicit value_op_iterator(SDUse *U = nullptr)
956 : iterator_adaptor_base(U) {}
957
958 const SDValue &operator*() const { return I->get(); }
959 };
960
961 iterator_range<value_op_iterator> op_values() const {
962 return make_range(value_op_iterator(op_begin()),
963 value_op_iterator(op_end()));
964 }
965
966 SDVTList getVTList() const {
967 SDVTList X = { ValueList, NumValues };
968 return X;
969 }
970
971 /// If this node has a glue operand, return the node
972 /// to which the glue operand points. Otherwise return NULL.
973 SDNode *getGluedNode() const {
974 if (getNumOperands() != 0 &&
975 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
976 return getOperand(getNumOperands()-1).getNode();
977 return nullptr;
978 }
979
980 /// If this node has a glue value with a user, return
981 /// the user (there is at most one). Otherwise return NULL.
982 SDNode *getGluedUser() const {
983 for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
984 if (UI.getUse().get().getValueType() == MVT::Glue)
985 return *UI;
986 return nullptr;
987 }
988
989 const SDNodeFlags getFlags() const { return Flags; }
990 void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
991 bool isFast() { return Flags.isFast(); }
992
993 /// Clear any flags in this node that aren't also set in Flags.
994 /// If Flags is not in a defined state then this has no effect.
995 void intersectFlagsWith(const SDNodeFlags Flags);
996
997 /// Return the number of values defined/returned by this operator.
998 unsigned getNumValues() const { return NumValues; }
999
1000 /// Return the type of a specified result.
1001 EVT getValueType(unsigned ResNo) const {
1002 assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ?
static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1002, __PRETTY_FUNCTION__))
;
1003 return ValueList[ResNo];
1004 }
1005
1006 /// Return the type of a specified result as a simple type.
1007 MVT getSimpleValueType(unsigned ResNo) const {
1008 return getValueType(ResNo).getSimpleVT();
1009 }
1010
1011 /// Returns MVT::getSizeInBits(getValueType(ResNo)).
1012 ///
1013 /// If the value type is a scalable vector type, the scalable property will
1014 /// be set and the runtime size will be a positive integer multiple of the
1015 /// base size.
1016 TypeSize getValueSizeInBits(unsigned ResNo) const {
1017 return getValueType(ResNo).getSizeInBits();
1018 }
1019
1020 using value_iterator = const EVT *;
1021
1022 value_iterator value_begin() const { return ValueList; }
1023 value_iterator value_end() const { return ValueList+NumValues; }
1024
1025 /// Return the opcode of this operation for printing.
1026 std::string getOperationName(const SelectionDAG *G = nullptr) const;
1027 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1028 void print_types(raw_ostream &OS, const SelectionDAG *G) const;
1029 void print_details(raw_ostream &OS, const SelectionDAG *G) const;
1030 void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1031 void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1032
1033 /// Print a SelectionDAG node and all children down to
1034 /// the leaves. The given SelectionDAG allows target-specific nodes
1035 /// to be printed in human-readable form. Unlike printr, this will
1036 /// print the whole DAG, including children that appear multiple
1037 /// times.
1038 ///
1039 void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;
1040
1041 /// Print a SelectionDAG node and children up to
1042 /// depth "depth." The given SelectionDAG allows target-specific
1043 /// nodes to be printed in human-readable form. Unlike printr, this
1044 /// will print children that appear multiple times wherever they are
1045 /// used.
1046 ///
1047 void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
1048 unsigned depth = 100) const;
1049
1050 /// Dump this node, for debugging.
1051 void dump() const;
1052
1053 /// Dump (recursively) this node and its use-def subgraph.
1054 void dumpr() const;
1055
1056 /// Dump this node, for debugging.
1057 /// The given SelectionDAG allows target-specific nodes to be printed
1058 /// in human-readable form.
1059 void dump(const SelectionDAG *G) const;
1060
1061 /// Dump (recursively) this node and its use-def subgraph.
1062 /// The given SelectionDAG allows target-specific nodes to be printed
1063 /// in human-readable form.
1064 void dumpr(const SelectionDAG *G) const;
1065
1066 /// printrFull to dbgs(). The given SelectionDAG allows
1067 /// target-specific nodes to be printed in human-readable form.
1068 /// Unlike dumpr, this will print the whole DAG, including children
1069 /// that appear multiple times.
1070 void dumprFull(const SelectionDAG *G = nullptr) const;
1071
1072 /// printrWithDepth to dbgs(). The given
1073 /// SelectionDAG allows target-specific nodes to be printed in
1074 /// human-readable form. Unlike dumpr, this will print children
1075 /// that appear multiple times wherever they are used.
1076 ///
1077 void dumprWithDepth(const SelectionDAG *G = nullptr,
1078 unsigned depth = 100) const;
1079
1080 /// Gather unique data for the node.
1081 void Profile(FoldingSetNodeID &ID) const;
1082
1083 /// This method should only be used by the SDUse class.
1084 void addUse(SDUse &U) { U.addToList(&UseList); }
1085
1086protected:
1087 static SDVTList getSDVTList(EVT VT) {
1088 SDVTList Ret = { getValueTypeList(VT), 1 };
1089 return Ret;
1090 }
1091
1092 /// Create an SDNode.
1093 ///
1094 /// SDNodes are created without any operands, and never own the operand
1095 /// storage. To add operands, see SelectionDAG::createOperands.
1096 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1097 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1098 IROrder(Order), debugLoc(std::move(dl)) {
1099 memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
1100 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1100, __PRETTY_FUNCTION__))
;
1101 assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1102, __PRETTY_FUNCTION__))
1102 "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1102, __PRETTY_FUNCTION__))
;
1103 }
1104
1105 /// Release the operands and set this node to have zero operands.
1106 void DropOperands();
1107};
1108
1109/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1110/// into SDNode creation functions.
1111/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1112/// from the original Instruction, and IROrder is the ordinal position of
1113/// the instruction.
1114/// When an SDNode is created after the DAG is being built, both DebugLoc and
1115/// the IROrder are propagated from the original SDNode.
1116/// So SDLoc class provides two constructors besides the default one, one to
1117/// be used by the DAGBuilder, the other to be used by others.
1118class SDLoc {
1119private:
1120 DebugLoc DL;
1121 int IROrder = 0;
1122
1123public:
1124 SDLoc() = default;
1125 SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
1126 SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
1127 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1128 assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void
> (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1128, __PRETTY_FUNCTION__))
;
1129 if (I)
1130 DL = I->getDebugLoc();
1131 }
1132
1133 unsigned getIROrder() const { return IROrder; }
1134 const DebugLoc &getDebugLoc() const { return DL; }
1135};
1136
1137// Define inline functions from the SDValue class.
1138
1139inline SDValue::SDValue(SDNode *node, unsigned resno)
1140 : Node(node), ResNo(resno) {
1141 // Explicitly check for !ResNo to avoid use-after-free, because there are
1142 // callers that use SDValue(N, 0) with a deleted N to indicate successful
1143 // combines.
1144 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1145, __PRETTY_FUNCTION__))
1145 "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1145, __PRETTY_FUNCTION__))
;
1146 assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1146, __PRETTY_FUNCTION__))
;
1147}
1148
1149inline unsigned SDValue::getOpcode() const {
1150 return Node->getOpcode();
1151}
1152
1153inline EVT SDValue::getValueType() const {
1154 return Node->getValueType(ResNo);
1155}
1156
1157inline unsigned SDValue::getNumOperands() const {
1158 return Node->getNumOperands();
1159}
1160
1161inline const SDValue &SDValue::getOperand(unsigned i) const {
1162 return Node->getOperand(i);
1163}
1164
1165inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
1166 return Node->getConstantOperandVal(i);
1167}
1168
1169inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
1170 return Node->getConstantOperandAPInt(i);
1171}
1172
1173inline bool SDValue::isTargetOpcode() const {
1174 return Node->isTargetOpcode();
1175}
1176
1177inline bool SDValue::isTargetMemoryOpcode() const {
1178 return Node->isTargetMemoryOpcode();
1179}
1180
1181inline bool SDValue::isMachineOpcode() const {
1182 return Node->isMachineOpcode();
7
Called C++ object pointer is null
1183}
1184
1185inline unsigned SDValue::getMachineOpcode() const {
1186 return Node->getMachineOpcode();
1187}
1188
1189inline bool SDValue::isUndef() const {
1190 return Node->isUndef();
1191}
1192
1193inline bool SDValue::use_empty() const {
1194 return !Node->hasAnyUseOfValue(ResNo);
1195}
1196
1197inline bool SDValue::hasOneUse() const {
1198 return Node->hasNUsesOfValue(1, ResNo);
1199}
1200
1201inline const DebugLoc &SDValue::getDebugLoc() const {
1202 return Node->getDebugLoc();
1203}
1204
1205inline void SDValue::dump() const {
1206 return Node->dump();
1207}
1208
1209inline void SDValue::dump(const SelectionDAG *G) const {
1210 return Node->dump(G);
1211}
1212
1213inline void SDValue::dumpr() const {
1214 return Node->dumpr();
1215}
1216
1217inline void SDValue::dumpr(const SelectionDAG *G) const {
1218 return Node->dumpr(G);
1219}
1220
1221// Define inline functions from the SDUse class.
1222
1223inline void SDUse::set(const SDValue &V) {
1224 if (Val.getNode()) removeFromList();
1225 Val = V;
1226 if (V.getNode()) V.getNode()->addUse(*this);
1227}
1228
1229inline void SDUse::setInitial(const SDValue &V) {
1230 Val = V;
1231 V.getNode()->addUse(*this);
1232}
1233
1234inline void SDUse::setNode(SDNode *N) {
1235 if (Val.getNode()) removeFromList();
1236 Val.setNode(N);
1237 if (N) N->addUse(*this);
1238}
1239
1240/// This class is used to form a handle around another node that
1241/// is persistent and is updated across invocations of replaceAllUsesWith on its
1242/// operand. This node should be directly created by end-users and not added to
1243/// the AllNodes list.
1244class HandleSDNode : public SDNode {
1245 SDUse Op;
1246
1247public:
1248 explicit HandleSDNode(SDValue X)
1249 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
1250 // HandleSDNodes are never inserted into the DAG, so they won't be
1251 // auto-numbered. Use ID 65535 as a sentinel.
1252 PersistentId = 0xffff;
1253
1254 // Manually set up the operand list. This node type is special in that it's
1255 // always stack allocated and SelectionDAG does not manage its operands.
1256 // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
1257 // be so special.
1258 Op.setUser(this);
1259 Op.setInitial(X);
1260 NumOperands = 1;
1261 OperandList = &Op;
1262 }
1263 ~HandleSDNode();
1264
1265 const SDValue &getValue() const { return Op; }
1266};
1267
1268class AddrSpaceCastSDNode : public SDNode {
1269private:
1270 unsigned SrcAddrSpace;
1271 unsigned DestAddrSpace;
1272
1273public:
1274 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1275 unsigned SrcAS, unsigned DestAS);
1276
1277 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
1278 unsigned getDestAddressSpace() const { return DestAddrSpace; }
1279
1280 static bool classof(const SDNode *N) {
1281 return N->getOpcode() == ISD::ADDRSPACECAST;
1282 }
1283};
1284
1285/// This is an abstract virtual class for memory operations.
1286class MemSDNode : public SDNode {
1287private:
1288 // VT of in-memory value.
1289 EVT MemoryVT;
1290
1291protected:
1292 /// Memory reference information.
1293 MachineMemOperand *MMO;
1294
1295public:
1296 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1297 EVT memvt, MachineMemOperand *MMO);
1298
1299 bool readMem() const { return MMO->isLoad(); }
1300 bool writeMem() const { return MMO->isStore(); }
1301
1302 /// Returns alignment and volatility of the memory access
1303 unsigned getOriginalAlignment() const {
1304 return MMO->getBaseAlignment();
1305 }
1306 unsigned getAlignment() const {
1307 return MMO->getAlignment();
1308 }
1309
1310 /// Return the SubclassData value, without HasDebugValue. This contains an
1311 /// encoding of the volatile flag, as well as bits used by subclasses. This
1312 /// function should only be used to compute a FoldingSetNodeID value.
1313 /// The HasDebugValue bit is masked out because CSE map needs to match
1314 /// nodes with debug info with nodes without debug info. Same is about
1315 /// isDivergent bit.
1316 unsigned getRawSubclassData() const {
1317 uint16_t Data;
1318 union {
1319 char RawSDNodeBits[sizeof(uint16_t)];
1320 SDNodeBitfields SDNodeBits;
1321 };
1322 memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
1323 SDNodeBits.HasDebugValue = 0;
1324 SDNodeBits.IsDivergent = false;
1325 memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
1326 return Data;
1327 }
1328
1329 bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
1330 bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
1331 bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
1332 bool isInvariant() const { return MemSDNodeBits.IsInvariant; }
1333
1334 // Returns the offset from the location of the access.
1335 int64_t getSrcValueOffset() const { return MMO->getOffset(); }
1336
1337 /// Returns the AA info that describes the dereference.
1338 AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }
1339
1340 /// Returns the Ranges that describes the dereference.
1341 const MDNode *getRanges() const { return MMO->getRanges(); }
1342
1343 /// Returns the synchronization scope ID for this memory operation.
1344 SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }
1345
1346 /// Return the atomic ordering requirements for this memory operation. For
1347 /// cmpxchg atomic operations, return the atomic ordering requirements when
1348 /// store occurs.
1349 AtomicOrdering getOrdering() const { return MMO->getOrdering(); }
1350
1351 /// Return true if the memory operation ordering is Unordered or higher.
1352 bool isAtomic() const { return MMO->isAtomic(); }
1353
1354 /// Returns true if the memory operation doesn't imply any ordering
1355 /// constraints on surrounding memory operations beyond the normal memory
1356 /// aliasing rules.
1357 bool isUnordered() const { return MMO->isUnordered(); }
1358
1359 /// Returns true if the memory operation is neither atomic or volatile.
1360 bool isSimple() const { return !isAtomic() && !isVolatile(); }
1361
1362 /// Return the type of the in-memory value.
1363 EVT getMemoryVT() const { return MemoryVT; }
1364
1365 /// Return a MachineMemOperand object describing the memory
1366 /// reference performed by operation.
1367 MachineMemOperand *getMemOperand() const { return MMO; }
1368
1369 const MachinePointerInfo &getPointerInfo() const {
1370 return MMO->getPointerInfo();
1371 }
1372
1373 /// Return the address space for the associated pointer
1374 unsigned getAddressSpace() const {
1375 return getPointerInfo().getAddrSpace();
1376 }
1377
1378 /// Update this MemSDNode's MachineMemOperand information
1379 /// to reflect the alignment of NewMMO, if it has a greater alignment.
1380 /// This must only be used when the new alignment applies to all users of
1381 /// this MachineMemOperand.
1382 void refineAlignment(const MachineMemOperand *NewMMO) {
1383 MMO->refineAlignment(NewMMO);
1384 }
1385
1386 const SDValue &getChain() const { return getOperand(0); }
1387 const SDValue &getBasePtr() const {
1388 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1389 }
1390
1391 // Methods to support isa and dyn_cast
1392 static bool classof(const SDNode *N) {
1393 // For some targets, we lower some target intrinsics to a MemIntrinsicNode
1394 // with either an intrinsic or a target opcode.
1395 return N->getOpcode() == ISD::LOAD ||
1396 N->getOpcode() == ISD::STORE ||
1397 N->getOpcode() == ISD::PREFETCH ||
1398 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1399 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1400 N->getOpcode() == ISD::ATOMIC_SWAP ||
1401 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1402 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1403 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1404 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1405 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1406 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1407 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1408 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1409 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1410 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1411 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1412 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1413 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1414 N->getOpcode() == ISD::ATOMIC_LOAD ||
1415 N->getOpcode() == ISD::ATOMIC_STORE ||
1416 N->getOpcode() == ISD::MLOAD ||
1417 N->getOpcode() == ISD::MSTORE ||
1418 N->getOpcode() == ISD::MGATHER ||
1419 N->getOpcode() == ISD::MSCATTER ||
1420 N->isMemIntrinsic() ||
1421 N->isTargetMemoryOpcode();
1422 }
1423};
1424
1425/// This is an SDNode representing atomic operations.
1426class AtomicSDNode : public MemSDNode {
1427public:
1428 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
1429 EVT MemVT, MachineMemOperand *MMO)
1430 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
1431 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1432, __PRETTY_FUNCTION__))
1432 MMO->isAtomic()) && "then why are we using an AtomicSDNode?")((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1432, __PRETTY_FUNCTION__))
;
1433 }
1434
1435 const SDValue &getBasePtr() const { return getOperand(1); }
1436 const SDValue &getVal() const { return getOperand(2); }
1437
1438 /// Returns true if this SDNode represents cmpxchg atomic operation, false
1439 /// otherwise.
1440 bool isCompareAndSwap() const {
1441 unsigned Op = getOpcode();
1442 return Op == ISD::ATOMIC_CMP_SWAP ||
1443 Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
1444 }
1445
1446 /// For cmpxchg atomic operations, return the atomic ordering requirements
1447 /// when store does not occur.
1448 AtomicOrdering getFailureOrdering() const {
1449 assert(isCompareAndSwap() && "Must be cmpxchg operation")((isCompareAndSwap() && "Must be cmpxchg operation") ?
static_cast<void> (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1449, __PRETTY_FUNCTION__))
;
1450 return MMO->getFailureOrdering();
1451 }
1452
1453 // Methods to support isa and dyn_cast
1454 static bool classof(const SDNode *N) {
1455 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1456 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1457 N->getOpcode() == ISD::ATOMIC_SWAP ||
1458 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1459 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1460 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1461 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1462 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1463 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1464 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1465 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1466 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1467 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1468 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1469 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1470 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1471 N->getOpcode() == ISD::ATOMIC_LOAD ||
1472 N->getOpcode() == ISD::ATOMIC_STORE;
1473 }
1474};
1475
1476/// This SDNode is used for target intrinsics that touch
1477/// memory and need an associated MachineMemOperand. Its opcode may be
1478/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1479/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1480class MemIntrinsicSDNode : public MemSDNode {
1481public:
1482 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1483 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
1484 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
1485 SDNodeBits.IsMemIntrinsic = true;
1486 }
1487
1488 // Methods to support isa and dyn_cast
1489 static bool classof(const SDNode *N) {
1490 // We lower some target intrinsics to their target opcode
1491 // early a node with a target opcode can be of this class
1492 return N->isMemIntrinsic() ||
1493 N->getOpcode() == ISD::PREFETCH ||
1494 N->isTargetMemoryOpcode();
1495 }
1496};
1497
1498/// This SDNode is used to implement the code generator
1499/// support for the llvm IR shufflevector instruction. It combines elements
1500/// from two input vectors into a new input vector, with the selection and
1501/// ordering of elements determined by an array of integers, referred to as
1502/// the shuffle mask. For input vectors of width N, mask indices of 0..N-1
1503/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1504/// An index of -1 is treated as undef, such that the code generator may put
1505/// any value in the corresponding element of the result.
1506class ShuffleVectorSDNode : public SDNode {
1507 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
1508 // is freed when the SelectionDAG object is destroyed.
1509 const int *Mask;
1510
1511protected:
1512 friend class SelectionDAG;
1513
1514 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
1515 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1516
1517public:
1518 ArrayRef<int> getMask() const {
1519 EVT VT = getValueType(0);
1520 return makeArrayRef(Mask, VT.getVectorNumElements());
1521 }
1522
1523 int getMaskElt(unsigned Idx) const {
1524 assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")((Idx < getValueType(0).getVectorNumElements() && "Idx out of range!"
) ? static_cast<void> (0) : __assert_fail ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1524, __PRETTY_FUNCTION__))
;
1525 return Mask[Idx];
1526 }
1527
1528 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
1529
1530 int getSplatIndex() const {
1531 assert(isSplat() && "Cannot get splat index for non-splat!")((isSplat() && "Cannot get splat index for non-splat!"
) ? static_cast<void> (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1531, __PRETTY_FUNCTION__))
;
1532 EVT VT = getValueType(0);
1533 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
1534 if (Mask[i] >= 0)
1535 return Mask[i];
1536
1537 // We can choose any index value here and be correct because all elements
1538 // are undefined. Return 0 for better potential for callers to simplify.
1539 return 0;
1540 }
1541
1542 static bool isSplatMask(const int *Mask, EVT VT);
1543
1544 /// Change values in a shuffle permute mask assuming
1545 /// the two vector operands have swapped position.
1546 static void commuteMask(MutableArrayRef<int> Mask) {
1547 unsigned NumElems = Mask.size();
1548 for (unsigned i = 0; i != NumElems; ++i) {
1549 int idx = Mask[i];
1550 if (idx < 0)
1551 continue;
1552 else if (idx < (int)NumElems)
1553 Mask[i] = idx + NumElems;
1554 else
1555 Mask[i] = idx - NumElems;
1556 }
1557 }
1558
1559 static bool classof(const SDNode *N) {
1560 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
1561 }
1562};
1563
1564class ConstantSDNode : public SDNode {
1565 friend class SelectionDAG;
1566
1567 const ConstantInt *Value;
1568
1569 ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
1570 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
1571 getSDVTList(VT)),
1572 Value(val) {
1573 ConstantSDNodeBits.IsOpaque = isOpaque;
1574 }
1575
1576public:
1577 const ConstantInt *getConstantIntValue() const { return Value; }
1578 const APInt &getAPIntValue() const { return Value->getValue(); }
1579 uint64_t getZExtValue() const { return Value->getZExtValue(); }
1580 int64_t getSExtValue() const { return Value->getSExtValue(); }
1581 uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) {
1582 return Value->getLimitedValue(Limit);
1583 }
1584
1585 bool isOne() const { return Value->isOne(); }
1586 bool isNullValue() const { return Value->isZero(); }
1587 bool isAllOnesValue() const { return Value->isMinusOne(); }
1588
1589 bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }
1590
1591 static bool classof(const SDNode *N) {
1592 return N->getOpcode() == ISD::Constant ||
1593 N->getOpcode() == ISD::TargetConstant;
1594 }
1595};
1596
1597uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
1598 return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1599}
1600
1601const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
1602 return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
1603}
1604
1605class ConstantFPSDNode : public SDNode {
1606 friend class SelectionDAG;
1607
1608 const ConstantFP *Value;
1609
1610 ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
1611 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
1612 DebugLoc(), getSDVTList(VT)),
1613 Value(val) {}
1614
1615public:
1616 const APFloat& getValueAPF() const { return Value->getValueAPF(); }
1617 const ConstantFP *getConstantFPValue() const { return Value; }
1618
1619 /// Return true if the value is positive or negative zero.
1620 bool isZero() const { return Value->isZero(); }
1621
1622 /// Return true if the value is a NaN.
1623 bool isNaN() const { return Value->isNaN(); }
1624
1625 /// Return true if the value is an infinity
1626 bool isInfinity() const { return Value->isInfinity(); }
1627
1628 /// Return true if the value is negative.
1629 bool isNegative() const { return Value->isNegative(); }
1630
1631 /// We don't rely on operator== working on double values, as
1632 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
1633 /// As such, this method can be used to do an exact bit-for-bit comparison of
1634 /// two floating point values.
1635
1636 /// We leave the version with the double argument here because it's just so
1637 /// convenient to write "2.0" and the like. Without this function we'd
1638 /// have to duplicate its logic everywhere it's called.
1639 bool isExactlyValue(double V) const {
1640 return Value->getValueAPF().isExactlyValue(V);
1641 }
1642 bool isExactlyValue(const APFloat& V) const;
1643
1644 static bool isValueValidForType(EVT VT, const APFloat& Val);
1645
1646 static bool classof(const SDNode *N) {
1647 return N->getOpcode() == ISD::ConstantFP ||
1648 N->getOpcode() == ISD::TargetConstantFP;
1649 }
1650};
1651
1652/// Returns true if \p V is a constant integer zero.
1653bool isNullConstant(SDValue V);
1654
1655/// Returns true if \p V is an FP constant with a value of positive zero.
1656bool isNullFPConstant(SDValue V);
1657
1658/// Returns true if \p V is an integer constant with all bits set.
1659bool isAllOnesConstant(SDValue V);
1660
1661/// Returns true if \p V is a constant integer one.
1662bool isOneConstant(SDValue V);
1663
1664/// Return the non-bitcasted source operand of \p V if it exists.
1665/// If \p V is not a bitcasted value, it is returned as-is.
1666SDValue peekThroughBitcasts(SDValue V);
1667
1668/// Return the non-bitcasted and one-use source operand of \p V if it exists.
1669/// If \p V is not a bitcasted one-use value, it is returned as-is.
1670SDValue peekThroughOneUseBitcasts(SDValue V);
1671
1672/// Return the non-extracted vector source operand of \p V if it exists.
1673/// If \p V is not an extracted subvector, it is returned as-is.
1674SDValue peekThroughExtractSubvectors(SDValue V);
1675
1676/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1677/// constant is canonicalized to be operand 1.
1678bool isBitwiseNot(SDValue V, bool AllowUndefs = false);
1679
1680/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1681ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false,
1682 bool AllowTruncation = false);
1683
1684/// Returns the SDNode if it is a demanded constant splat BuildVector or
1685/// constant int.
1686ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
1687 bool AllowUndefs = false,
1688 bool AllowTruncation = false);
1689
1690/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1691ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false);
1692
1693/// Returns the SDNode if it is a demanded constant splat BuildVector or
1694/// constant float.
1695ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts,
1696 bool AllowUndefs = false);
1697
1698/// Return true if the value is a constant 0 integer or a splatted vector of
1699/// a constant 0 integer (with no undefs by default).
1700/// Build vector implicit truncation is not an issue for null values.
1701bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false);
1702
1703/// Return true if the value is a constant 1 integer or a splatted vector of a
1704/// constant 1 integer (with no undefs).
1705/// Does not permit build vector implicit truncation.
1706bool isOneOrOneSplat(SDValue V);
1707
1708/// Return true if the value is a constant -1 integer or a splatted vector of a
1709/// constant -1 integer (with no undefs).
1710/// Does not permit build vector implicit truncation.
1711bool isAllOnesOrAllOnesSplat(SDValue V);
1712
1713class GlobalAddressSDNode : public SDNode {
1714 friend class SelectionDAG;
1715
1716 const GlobalValue *TheGlobal;
1717 int64_t Offset;
1718 unsigned TargetFlags;
1719
1720 GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
1721 const GlobalValue *GA, EVT VT, int64_t o,
1722 unsigned TF);
1723
1724public:
1725 const GlobalValue *getGlobal() const { return TheGlobal; }
1726 int64_t getOffset() const { return Offset; }
1727 unsigned getTargetFlags() const { return TargetFlags; }
1728 // Return the address space this GlobalAddress belongs to.
1729 unsigned getAddressSpace() const;
1730
1731 static bool classof(const SDNode *N) {
1732 return N->getOpcode() == ISD::GlobalAddress ||
1733 N->getOpcode() == ISD::TargetGlobalAddress ||
1734 N->getOpcode() == ISD::GlobalTLSAddress ||
1735 N->getOpcode() == ISD::TargetGlobalTLSAddress;
1736 }
1737};
1738
1739class FrameIndexSDNode : public SDNode {
1740 friend class SelectionDAG;
1741
1742 int FI;
1743
1744 FrameIndexSDNode(int fi, EVT VT, bool isTarg)
1745 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1746 0, DebugLoc(), getSDVTList(VT)), FI(fi) {
1747 }
1748
1749public:
1750 int getIndex() const { return FI; }
1751
1752 static bool classof(const SDNode *N) {
1753 return N->getOpcode() == ISD::FrameIndex ||
1754 N->getOpcode() == ISD::TargetFrameIndex;
1755 }
1756};
1757
1758/// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate
1759/// the offet and size that are started/ended in the underlying FrameIndex.
1760class LifetimeSDNode : public SDNode {
1761 friend class SelectionDAG;
1762 int64_t Size;
1763 int64_t Offset; // -1 if offset is unknown.
1764
1765 LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
1766 SDVTList VTs, int64_t Size, int64_t Offset)
1767 : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {}
1768public:
1769 int64_t getFrameIndex() const {
1770 return cast<FrameIndexSDNode>(getOperand(1))->getIndex();
1771 }
1772
1773 bool hasOffset() const { return Offset >= 0; }
1774 int64_t getOffset() const {
1775 assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1775, __PRETTY_FUNCTION__))
;
1776 return Offset;
1777 }
1778 int64_t getSize() const {
1779 assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1779, __PRETTY_FUNCTION__))
;
1780 return Size;
1781 }
1782
1783 // Methods to support isa and dyn_cast
1784 static bool classof(const SDNode *N) {
1785 return N->getOpcode() == ISD::LIFETIME_START ||
1786 N->getOpcode() == ISD::LIFETIME_END;
1787 }
1788};
1789
1790class JumpTableSDNode : public SDNode {
1791 friend class SelectionDAG;
1792
1793 int JTI;
1794 unsigned TargetFlags;
1795
1796 JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF)
1797 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
1798 0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
1799 }
1800
1801public:
1802 int getIndex() const { return JTI; }
1803 unsigned getTargetFlags() const { return TargetFlags; }
1804
1805 static bool classof(const SDNode *N) {
1806 return N->getOpcode() == ISD::JumpTable ||
1807 N->getOpcode() == ISD::TargetJumpTable;
1808 }
1809};
1810
1811class ConstantPoolSDNode : public SDNode {
1812 friend class SelectionDAG;
1813
1814 union {
1815 const Constant *ConstVal;
1816 MachineConstantPoolValue *MachineCPVal;
1817 } Val;
1818 int Offset; // It's a MachineConstantPoolValue if top bit is set.
1819 unsigned Alignment; // Minimum alignment requirement of CP (not log2 value).
1820 unsigned TargetFlags;
1821
1822 ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
1823 unsigned Align, unsigned TF)
1824 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1825 DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
1826 TargetFlags(TF) {
1827 assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1827, __PRETTY_FUNCTION__))
;
1828 Val.ConstVal = c;
1829 }
1830
1831 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
1832 EVT VT, int o, unsigned Align, unsigned TF)
1833 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1834 DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
1835 TargetFlags(TF) {
1836 assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1836, __PRETTY_FUNCTION__))
;
1837 Val.MachineCPVal = v;
1838 Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
1839 }
1840
1841public:
1842 bool isMachineConstantPoolEntry() const {
1843 return Offset < 0;
1844 }
1845
1846 const Constant *getConstVal() const {
1847 assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")((!isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1847, __PRETTY_FUNCTION__))
;
1848 return Val.ConstVal;
1849 }
1850
1851 MachineConstantPoolValue *getMachineCPVal() const {
1852 assert(isMachineConstantPoolEntry() && "Wrong constantpool type")((isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1852, __PRETTY_FUNCTION__))
;
1853 return Val.MachineCPVal;
1854 }
1855
1856 int getOffset() const {
1857 return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
1858 }
1859
1860 // Return the alignment of this constant pool object, which is either 0 (for
1861 // default alignment) or the desired value.
1862 unsigned getAlignment() const { return Alignment; }
1863 unsigned getTargetFlags() const { return TargetFlags; }
1864
1865 Type *getType() const;
1866
1867 static bool classof(const SDNode *N) {
1868 return N->getOpcode() == ISD::ConstantPool ||
1869 N->getOpcode() == ISD::TargetConstantPool;
1870 }
1871};
1872
1873/// Completely target-dependent object reference.
1874class TargetIndexSDNode : public SDNode {
1875 friend class SelectionDAG;
1876
1877 unsigned TargetFlags;
1878 int Index;
1879 int64_t Offset;
1880
1881public:
1882 TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF)
1883 : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
1884 TargetFlags(TF), Index(Idx), Offset(Ofs) {}
1885
1886 unsigned getTargetFlags() const { return TargetFlags; }
1887 int getIndex() const { return Index; }
1888 int64_t getOffset() const { return Offset; }
1889
1890 static bool classof(const SDNode *N) {
1891 return N->getOpcode() == ISD::TargetIndex;
1892 }
1893};
1894
1895class BasicBlockSDNode : public SDNode {
1896 friend class SelectionDAG;
1897
1898 MachineBasicBlock *MBB;
1899
1900 /// Debug info is meaningful and potentially useful here, but we create
1901 /// blocks out of order when they're jumped to, which makes it a bit
1902 /// harder. Let's see if we need it first.
1903 explicit BasicBlockSDNode(MachineBasicBlock *mbb)
1904 : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
1905 {}
1906
1907public:
1908 MachineBasicBlock *getBasicBlock() const { return MBB; }
1909
1910 static bool classof(const SDNode *N) {
1911 return N->getOpcode() == ISD::BasicBlock;
1912 }
1913};
1914
1915/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1916class BuildVectorSDNode : public SDNode {
1917public:
1918 // These are constructed as SDNodes and then cast to BuildVectorSDNodes.
1919 explicit BuildVectorSDNode() = delete;
1920
1921 /// Check if this is a constant splat, and if so, find the
1922 /// smallest element size that splats the vector. If MinSplatBits is
1923 /// nonzero, the element size must be at least that large. Note that the
1924 /// splat element may be the entire vector (i.e., a one element vector).
1925 /// Returns the splat element value in SplatValue. Any undefined bits in
1926 /// that value are zero, and the corresponding bits in the SplatUndef mask
1927 /// are set. The SplatBitSize value is set to the splat element size in
1928 /// bits. HasAnyUndefs is set to true if any bits in the vector are
1929 /// undefined. isBigEndian describes the endianness of the target.
1930 bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
1931 unsigned &SplatBitSize, bool &HasAnyUndefs,
1932 unsigned MinSplatBits = 0,
1933 bool isBigEndian = false) const;
1934
1935 /// Returns the demanded splatted value or a null value if this is not a
1936 /// splat.
1937 ///
1938 /// The DemandedElts mask indicates the elements that must be in the splat.
1939 /// If passed a non-null UndefElements bitvector, it will resize it to match
1940 /// the vector width and set the bits where elements are undef.
1941 SDValue getSplatValue(const APInt &DemandedElts,
1942 BitVector *UndefElements = nullptr) const;
1943
1944 /// Returns the splatted value or a null value if this is not a splat.
1945 ///
1946 /// If passed a non-null UndefElements bitvector, it will resize it to match
1947 /// the vector width and set the bits where elements are undef.
1948 SDValue getSplatValue(BitVector *UndefElements = nullptr) const;
1949
1950 /// Returns the demanded splatted constant or null if this is not a constant
1951 /// splat.
1952 ///
1953 /// The DemandedElts mask indicates the elements that must be in the splat.
1954 /// If passed a non-null UndefElements bitvector, it will resize it to match
1955 /// the vector width and set the bits where elements are undef.
1956 ConstantSDNode *
1957 getConstantSplatNode(const APInt &DemandedElts,
1958 BitVector *UndefElements = nullptr) const;
1959
1960 /// Returns the splatted constant or null if this is not a constant
1961 /// splat.
1962 ///
1963 /// If passed a non-null UndefElements bitvector, it will resize it to match
1964 /// the vector width and set the bits where elements are undef.
1965 ConstantSDNode *
1966 getConstantSplatNode(BitVector *UndefElements = nullptr) const;
1967
1968 /// Returns the demanded splatted constant FP or null if this is not a
1969 /// constant FP splat.
1970 ///
1971 /// The DemandedElts mask indicates the elements that must be in the splat.
1972 /// If passed a non-null UndefElements bitvector, it will resize it to match
1973 /// the vector width and set the bits where elements are undef.
1974 ConstantFPSDNode *
1975 getConstantFPSplatNode(const APInt &DemandedElts,
1976 BitVector *UndefElements = nullptr) const;
1977
1978 /// Returns the splatted constant FP or null if this is not a constant
1979 /// FP splat.
1980 ///
1981 /// If passed a non-null UndefElements bitvector, it will resize it to match
1982 /// the vector width and set the bits where elements are undef.
1983 ConstantFPSDNode *
1984 getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;
1985
1986 /// If this is a constant FP splat and the splatted constant FP is an
1987 /// exact power or 2, return the log base 2 integer value. Otherwise,
1988 /// return -1.
1989 ///
1990 /// The BitWidth specifies the necessary bit precision.
1991 int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
1992 uint32_t BitWidth) const;
1993
1994 bool isConstant() const;
1995
1996 static bool classof(const SDNode *N) {
1997 return N->getOpcode() == ISD::BUILD_VECTOR;
1998 }
1999};
2000
2001/// An SDNode that holds an arbitrary LLVM IR Value. This is
2002/// used when the SelectionDAG needs to make a simple reference to something
2003/// in the LLVM IR representation.
2004///
2005class SrcValueSDNode : public SDNode {
2006 friend class SelectionDAG;
2007
2008 const Value *V;
2009
2010 /// Create a SrcValue for a general value.
2011 explicit SrcValueSDNode(const Value *v)
2012 : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}
2013
2014public:
2015 /// Return the contained Value.
2016 const Value *getValue() const { return V; }
2017
2018 static bool classof(const SDNode *N) {
2019 return N->getOpcode() == ISD::SRCVALUE;
2020 }
2021};
2022
2023class MDNodeSDNode : public SDNode {
2024 friend class SelectionDAG;
2025
2026 const MDNode *MD;
2027
2028 explicit MDNodeSDNode(const MDNode *md)
2029 : SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
2030 {}
2031
2032public:
2033 const MDNode *getMD() const { return MD; }
2034
2035 static bool classof(const SDNode *N) {
2036 return N->getOpcode() == ISD::MDNODE_SDNODE;
2037 }
2038};
2039
2040class RegisterSDNode : public SDNode {
2041 friend class SelectionDAG;
2042
2043 unsigned Reg;
2044
2045 RegisterSDNode(unsigned reg, EVT VT)
2046 : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}
2047
2048public:
2049 unsigned getReg() const { return Reg; }
2050
2051 static bool classof(const SDNode *N) {
2052 return N->getOpcode() == ISD::Register;
2053 }
2054};
2055
2056class RegisterMaskSDNode : public SDNode {
2057 friend class SelectionDAG;
2058
2059 // The memory for RegMask is not owned by the node.
2060 const uint32_t *RegMask;
2061
2062 RegisterMaskSDNode(const uint32_t *mask)
2063 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
2064 RegMask(mask) {}
2065
2066public:
2067 const uint32_t *getRegMask() const { return RegMask; }
2068
2069 static bool classof(const SDNode *N) {
2070 return N->getOpcode() == ISD::RegisterMask;
2071 }
2072};
2073
2074class BlockAddressSDNode : public SDNode {
2075 friend class SelectionDAG;
2076
2077 const BlockAddress *BA;
2078 int64_t Offset;
2079 unsigned TargetFlags;
2080
2081 BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
2082 int64_t o, unsigned Flags)
2083 : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
2084 BA(ba), Offset(o), TargetFlags(Flags) {}
2085
2086public:
2087 const BlockAddress *getBlockAddress() const { return BA; }
2088 int64_t getOffset() const { return Offset; }
2089 unsigned getTargetFlags() const { return TargetFlags; }
2090
2091 static bool classof(const SDNode *N) {
2092 return N->getOpcode() == ISD::BlockAddress ||
2093 N->getOpcode() == ISD::TargetBlockAddress;
2094 }
2095};
2096
2097class LabelSDNode : public SDNode {
2098 friend class SelectionDAG;
2099
2100 MCSymbol *Label;
2101
2102 LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L)
2103 : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) {
2104 assert(LabelSDNode::classof(this) && "not a label opcode")((LabelSDNode::classof(this) && "not a label opcode")
? static_cast<void> (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2104, __PRETTY_FUNCTION__))
;
2105 }
2106
2107public:
2108 MCSymbol *getLabel() const { return Label; }
2109
2110 static bool classof(const SDNode *N) {
2111 return N->getOpcode() == ISD::EH_LABEL ||
2112 N->getOpcode() == ISD::ANNOTATION_LABEL;
2113 }
2114};
2115
2116class ExternalSymbolSDNode : public SDNode {
2117 friend class SelectionDAG;
2118
2119 const char *Symbol;
2120 unsigned TargetFlags;
2121
2122 ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT)
2123 : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0,
2124 DebugLoc(), getSDVTList(VT)),
2125 Symbol(Sym), TargetFlags(TF) {}
2126
2127public:
2128 const char *getSymbol() const { return Symbol; }
2129 unsigned getTargetFlags() const { return TargetFlags; }
2130
2131 static bool classof(const SDNode *N) {
2132 return N->getOpcode() == ISD::ExternalSymbol ||
2133 N->getOpcode() == ISD::TargetExternalSymbol;
2134 }
2135};
2136
2137class MCSymbolSDNode : public SDNode {
2138 friend class SelectionDAG;
2139
2140 MCSymbol *Symbol;
2141
2142 MCSymbolSDNode(MCSymbol *Symbol, EVT VT)
2143 : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {}
2144
2145public:
2146 MCSymbol *getMCSymbol() const { return Symbol; }
2147
2148 static bool classof(const SDNode *N) {
2149 return N->getOpcode() == ISD::MCSymbol;
2150 }
2151};
2152
2153class CondCodeSDNode : public SDNode {
2154 friend class SelectionDAG;
2155
2156 ISD::CondCode Condition;
2157
2158 explicit CondCodeSDNode(ISD::CondCode Cond)
2159 : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2160 Condition(Cond) {}
2161
2162public:
2163 ISD::CondCode get() const { return Condition; }
2164
2165 static bool classof(const SDNode *N) {
2166 return N->getOpcode() == ISD::CONDCODE;
2167 }
2168};
2169
2170/// This class is used to represent EVT's, which are used
2171/// to parameterize some operations.
2172class VTSDNode : public SDNode {
2173 friend class SelectionDAG;
2174
2175 EVT ValueType;
2176
2177 explicit VTSDNode(EVT VT)
2178 : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2179 ValueType(VT) {}
2180
2181public:
2182 EVT getVT() const { return ValueType; }
2183
2184 static bool classof(const SDNode *N) {
2185 return N->getOpcode() == ISD::VALUETYPE;
2186 }
2187};
2188
2189/// Base class for LoadSDNode and StoreSDNode
2190class LSBaseSDNode : public MemSDNode {
2191public:
2192 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
2193 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2194 MachineMemOperand *MMO)
2195 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2196 LSBaseSDNodeBits.AddressingMode = AM;
2197 assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2197, __PRETTY_FUNCTION__))
;
2198 }
2199
2200 const SDValue &getOffset() const {
2201 return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
2202 }
2203
2204 /// Return the addressing mode for this load or store:
2205 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2206 ISD::MemIndexedMode getAddressingMode() const {
2207 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2208 }
2209
2210 /// Return true if this is a pre/post inc/dec load/store.
2211 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2212
2213 /// Return true if this is NOT a pre/post inc/dec load/store.
2214 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2215
2216 static bool classof(const SDNode *N) {
2217 return N->getOpcode() == ISD::LOAD ||
2218 N->getOpcode() == ISD::STORE;
2219 }
2220};
2221
2222/// This class is used to represent ISD::LOAD nodes.
2223class LoadSDNode : public LSBaseSDNode {
2224 friend class SelectionDAG;
2225
2226 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2227 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2228 MachineMemOperand *MMO)
2229 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2230 LoadSDNodeBits.ExtTy = ETy;
2231 assert(readMem() && "Load MachineMemOperand is not a load!")((readMem() && "Load MachineMemOperand is not a load!"
) ? static_cast<void> (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2231, __PRETTY_FUNCTION__))
;
2232 assert(!writeMem() && "Load MachineMemOperand is a store!")((!writeMem() && "Load MachineMemOperand is a store!"
) ? static_cast<void> (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2232, __PRETTY_FUNCTION__))
;
2233 }
2234
2235public:
2236 /// Return whether this is a plain node,
2237 /// or one of the varieties of value-extending loads.
2238 ISD::LoadExtType getExtensionType() const {
2239 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2240 }
2241
2242 const SDValue &getBasePtr() const { return getOperand(1); }
2243 const SDValue &getOffset() const { return getOperand(2); }
2244
2245 static bool classof(const SDNode *N) {
2246 return N->getOpcode() == ISD::LOAD;
2247 }
2248};
2249
2250/// This class is used to represent ISD::STORE nodes.
2251class StoreSDNode : public LSBaseSDNode {
2252 friend class SelectionDAG;
2253
2254 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2255 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2256 MachineMemOperand *MMO)
2257 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2258 StoreSDNodeBits.IsTruncating = isTrunc;
2259 assert(!readMem() && "Store MachineMemOperand is a load!")((!readMem() && "Store MachineMemOperand is a load!")
? static_cast<void> (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2259, __PRETTY_FUNCTION__))
;
2260 assert(writeMem() && "Store MachineMemOperand is not a store!")((writeMem() && "Store MachineMemOperand is not a store!"
) ? static_cast<void> (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2260, __PRETTY_FUNCTION__))
;
2261 }
2262
2263public:
2264 /// Return true if the op does a truncation before store.
2265 /// For integers this is the same as doing a TRUNCATE and storing the result.
2266 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2267 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2268 void setTruncatingStore(bool Truncating) {
2269 StoreSDNodeBits.IsTruncating = Truncating;
2270 }
2271
2272 const SDValue &getValue() const { return getOperand(1); }
2273 const SDValue &getBasePtr() const { return getOperand(2); }
2274 const SDValue &getOffset() const { return getOperand(3); }
2275
2276 static bool classof(const SDNode *N) {
2277 return N->getOpcode() == ISD::STORE;
2278 }
2279};
2280
2281/// This base class is used to represent MLOAD and MSTORE nodes
2282class MaskedLoadStoreSDNode : public MemSDNode {
2283public:
2284 friend class SelectionDAG;
2285
2286 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
2287 const DebugLoc &dl, SDVTList VTs,
2288 ISD::MemIndexedMode AM, EVT MemVT,
2289 MachineMemOperand *MMO)
2290 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2291 LSBaseSDNodeBits.AddressingMode = AM;
2292 assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2292, __PRETTY_FUNCTION__))
;
2293 }
2294
2295 // MaskedLoadSDNode (Chain, ptr, offset, mask, passthru)
2296 // MaskedStoreSDNode (Chain, data, ptr, offset, mask)
2297 // Mask is a vector of i1 elements
2298 const SDValue &getBasePtr() const {
2299 return getOperand(getOpcode() == ISD::MLOAD ? 1 : 2);
2300 }
2301 const SDValue &getOffset() const {
2302 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2303 }
2304 const SDValue &getMask() const {
2305 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2306 }
2307
2308 /// Return the addressing mode for this load or store:
2309 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2310 ISD::MemIndexedMode getAddressingMode() const {
2311 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2312 }
2313
2314 /// Return true if this is a pre/post inc/dec load/store.
2315 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2316
2317 /// Return true if this is NOT a pre/post inc/dec load/store.
2318 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2319
2320 static bool classof(const SDNode *N) {
2321 return N->getOpcode() == ISD::MLOAD ||
2322 N->getOpcode() == ISD::MSTORE;
2323 }
2324};
2325
2326/// This class is used to represent an MLOAD node
2327class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
2328public:
2329 friend class SelectionDAG;
2330
2331 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2332 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
2333 bool IsExpanding, EVT MemVT, MachineMemOperand *MMO)
2334 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2335 LoadSDNodeBits.ExtTy = ETy;
2336 LoadSDNodeBits.IsExpanding = IsExpanding;
2337 }
2338
2339 ISD::LoadExtType getExtensionType() const {
2340 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2341 }
2342
2343 const SDValue &getBasePtr() const { return getOperand(1); }
2344 const SDValue &getOffset() const { return getOperand(2); }
2345 const SDValue &getMask() const { return getOperand(3); }
2346 const SDValue &getPassThru() const { return getOperand(4); }
2347
2348 static bool classof(const SDNode *N) {
2349 return N->getOpcode() == ISD::MLOAD;
2350 }
2351
2352 bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2353};
2354
2355/// This class is used to represent an MSTORE node
2356class MaskedStoreSDNode : public MaskedLoadStoreSDNode {
2357public:
2358 friend class SelectionDAG;
2359
2360 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2361 ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing,
2362 EVT MemVT, MachineMemOperand *MMO)
2363 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
2364 StoreSDNodeBits.IsTruncating = isTrunc;
2365 StoreSDNodeBits.IsCompressing = isCompressing;
2366 }
2367
2368 /// Return true if the op does a truncation before store.
2369 /// For integers this is the same as doing a TRUNCATE and storing the result.
2370 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2371 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2372
2373 /// Returns true if the op does a compression to the vector before storing.
2374 /// The node contiguously stores the active elements (integers or floats)
2375 /// in src (those with their respective bit set in writemask k) to unaligned
2376 /// memory at base_addr.
2377 bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }
2378
2379 const SDValue &getValue() const { return getOperand(1); }
2380 const SDValue &getBasePtr() const { return getOperand(2); }
2381 const SDValue &getOffset() const { return getOperand(3); }
2382 const SDValue &getMask() const { return getOperand(4); }
2383
2384 static bool classof(const SDNode *N) {
2385 return N->getOpcode() == ISD::MSTORE;
2386 }
2387};
2388
2389/// This is a base class used to represent
2390/// MGATHER and MSCATTER nodes
2391///
2392class MaskedGatherScatterSDNode : public MemSDNode {
2393public:
2394 friend class SelectionDAG;
2395
2396 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
2397 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2398 MachineMemOperand *MMO, ISD::MemIndexType IndexType)
2399 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2400 LSBaseSDNodeBits.AddressingMode = IndexType;
2401 assert(getIndexType() == IndexType && "Value truncated")((getIndexType() == IndexType && "Value truncated") ?
static_cast<void> (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2401, __PRETTY_FUNCTION__))
;
2402 }
2403
2404 /// How is Index applied to BasePtr when computing addresses.
2405 ISD::MemIndexType getIndexType() const {
2406 return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);
2407 }
2408 bool isIndexScaled() const {
2409 return (getIndexType() == ISD::SIGNED_SCALED) ||
2410 (getIndexType() == ISD::UNSIGNED_SCALED);
2411 }
2412 bool isIndexSigned() const {
2413 return (getIndexType() == ISD::SIGNED_SCALED) ||
2414 (getIndexType() == ISD::SIGNED_UNSCALED);
2415 }
2416
2417 // In the both nodes address is Op1, mask is Op2:
2418 // MaskedGatherSDNode (Chain, passthru, mask, base, index, scale)
2419 // MaskedScatterSDNode (Chain, value, mask, base, index, scale)
2420 // Mask is a vector of i1 elements
2421 const SDValue &getBasePtr() const { return getOperand(3); }
2422 const SDValue &getIndex() const { return getOperand(4); }
2423 const SDValue &getMask() const { return getOperand(2); }
2424 const SDValue &getScale() const { return getOperand(5); }
2425
2426 static bool classof(const SDNode *N) {
2427 return N->getOpcode() == ISD::MGATHER ||
2428 N->getOpcode() == ISD::MSCATTER;
2429 }
2430};
2431
2432/// This class is used to represent an MGATHER node
2433///
2434class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
2435public:
2436 friend class SelectionDAG;
2437
2438 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2439 EVT MemVT, MachineMemOperand *MMO,
2440 ISD::MemIndexType IndexType)
2441 : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
2442 IndexType) {}
2443
2444 const SDValue &getPassThru() const { return getOperand(1); }
2445
2446 static bool classof(const SDNode *N) {
2447 return N->getOpcode() == ISD::MGATHER;
2448 }
2449};
2450
2451/// This class is used to represent an MSCATTER node
2452///
2453class MaskedScatterSDNode : public MaskedGatherScatterSDNode {
2454public:
2455 friend class SelectionDAG;
2456
2457 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2458 EVT MemVT, MachineMemOperand *MMO,
2459 ISD::MemIndexType IndexType)
2460 : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO,
2461 IndexType) {}
2462
2463 const SDValue &getValue() const { return getOperand(1); }
2464
2465 static bool classof(const SDNode *N) {
2466 return N->getOpcode() == ISD::MSCATTER;
2467 }
2468};
2469
2470/// An SDNode that represents everything that will be needed
2471/// to construct a MachineInstr. These nodes are created during the
2472/// instruction selection proper phase.
2473///
2474/// Note that the only supported way to set the `memoperands` is by calling the
2475/// `SelectionDAG::setNodeMemRefs` function as the memory management happens
2476/// inside the DAG rather than in the node.
2477class MachineSDNode : public SDNode {
2478private:
2479 friend class SelectionDAG;
2480
2481 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
2482 : SDNode(Opc, Order, DL, VTs) {}
2483
2484 // We use a pointer union between a single `MachineMemOperand` pointer and
2485 // a pointer to an array of `MachineMemOperand` pointers. This is null when
2486 // the number of these is zero, the single pointer variant used when the
2487 // number is one, and the array is used for larger numbers.
2488 //
2489 // The array is allocated via the `SelectionDAG`'s allocator and so will
2490 // always live until the DAG is cleaned up and doesn't require ownership here.
2491 //
2492 // We can't use something simpler like `TinyPtrVector` here because `SDNode`
2493 // subclasses aren't managed in a conforming C++ manner. See the comments on
2494 // `SelectionDAG::MorphNodeTo` which details what all goes on, but the
2495 // constraint here is that these don't manage memory with their constructor or
2496 // destructor and can be initialized to a good state even if they start off
2497 // uninitialized.
2498 PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {};
2499
2500 // Note that this could be folded into the above `MemRefs` member if doing so
2501 // is advantageous at some point. We don't need to store this in most cases.
2502 // However, at the moment this doesn't appear to make the allocation any
2503 // smaller and makes the code somewhat simpler to read.
2504 int NumMemRefs = 0;
2505
2506public:
2507 using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator;
2508
2509 ArrayRef<MachineMemOperand *> memoperands() const {
2510 // Special case the common cases.
2511 if (NumMemRefs == 0)
2512 return {};
2513 if (NumMemRefs == 1)
2514 return makeArrayRef(MemRefs.getAddrOfPtr1(), 1);
2515
2516 // Otherwise we have an actual array.
2517 return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs);
2518 }
2519 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
2520 mmo_iterator memoperands_end() const { return memoperands().end(); }
2521 bool memoperands_empty() const { return memoperands().empty(); }
2522
2523 /// Clear out the memory reference descriptor list.
2524 void clearMemRefs() {
2525 MemRefs = nullptr;
2526 NumMemRefs = 0;
2527 }
2528
2529 static bool classof(const SDNode *N) {
2530 return N->isMachineOpcode();
2531 }
2532};
2533
2534class SDNodeIterator : public std::iterator<std::forward_iterator_tag,
2535 SDNode, ptrdiff_t> {
2536 const SDNode *Node;
2537 unsigned Operand;
2538
2539 SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}
2540
2541public:
2542 bool operator==(const SDNodeIterator& x) const {
2543 return Operand == x.Operand;
2544 }
2545 bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }
2546
2547 pointer operator*() const {
2548 return Node->getOperand(Operand).getNode();
2549 }
2550 pointer operator->() const { return operator*(); }
2551
2552 SDNodeIterator& operator++() { // Preincrement
2553 ++Operand;
2554 return *this;
2555 }
2556 SDNodeIterator operator++(int) { // Postincrement
2557 SDNodeIterator tmp = *this; ++*this; return tmp;
2558 }
2559 size_t operator-(SDNodeIterator Other) const {
2560 assert(Node == Other.Node &&((Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2561, __PRETTY_FUNCTION__))
2561 "Cannot compare iterators of two different nodes!")((Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2561, __PRETTY_FUNCTION__))
;
2562 return Operand - Other.Operand;
2563 }
2564
2565 static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); }
2566 static SDNodeIterator end (const SDNode *N) {
2567 return SDNodeIterator(N, N->getNumOperands());
2568 }
2569
2570 unsigned getOperand() const { return Operand; }
2571 const SDNode *getNode() const { return Node; }
2572};
2573
2574template <> struct GraphTraits<SDNode*> {
2575 using NodeRef = SDNode *;
2576 using ChildIteratorType = SDNodeIterator;
2577
2578 static NodeRef getEntryNode(SDNode *N) { return N; }
2579
2580 static ChildIteratorType child_begin(NodeRef N) {
2581 return SDNodeIterator::begin(N);
2582 }
2583
2584 static ChildIteratorType child_end(NodeRef N) {
2585 return SDNodeIterator::end(N);
2586 }
2587};
2588
2589/// A representation of the largest SDNode, for use in sizeof().
2590///
2591/// This needs to be a union because the largest node differs on 32 bit systems
2592/// with 4 and 8 byte pointer alignment, respectively.
2593using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode,
2594 BlockAddressSDNode,
2595 GlobalAddressSDNode>;
2596
2597/// The SDNode class with the greatest alignment requirement.
2598using MostAlignedSDNode = GlobalAddressSDNode;
2599
2600namespace ISD {
2601
2602 /// Returns true if the specified node is a non-extending and unindexed load.
2603 inline bool isNormalLoad(const SDNode *N) {
2604 const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N);
2605 return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
2606 Ld->getAddressingMode() == ISD::UNINDEXED;
2607 }
2608
2609 /// Returns true if the specified node is a non-extending load.
2610 inline bool isNON_EXTLoad(const SDNode *N) {
2611 return isa<LoadSDNode>(N) &&
2612 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
2613 }
2614
2615 /// Returns true if the specified node is a EXTLOAD.
2616 inline bool isEXTLoad(const SDNode *N) {
2617 return isa<LoadSDNode>(N) &&
2618 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
2619 }
2620
2621 /// Returns true if the specified node is a SEXTLOAD.
2622 inline bool isSEXTLoad(const SDNode *N) {
2623 return isa<LoadSDNode>(N) &&
2624 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
2625 }
2626
2627 /// Returns true if the specified node is a ZEXTLOAD.
2628 inline bool isZEXTLoad(const SDNode *N) {
2629 return isa<LoadSDNode>(N) &&
2630 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
2631 }
2632
2633 /// Returns true if the specified node is an unindexed load.
2634 inline bool isUNINDEXEDLoad(const SDNode *N) {
2635 return isa<LoadSDNode>(N) &&
2636 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2637 }
2638
2639 /// Returns true if the specified node is a non-truncating
2640 /// and unindexed store.
2641 inline bool isNormalStore(const SDNode *N) {
2642 const StoreSDNode *St = dyn_cast<StoreSDNode>(N);
2643 return St && !St->isTruncatingStore() &&
2644 St->getAddressingMode() == ISD::UNINDEXED;
2645 }
2646
2647 /// Returns true if the specified node is a non-truncating store.
2648 inline bool isNON_TRUNCStore(const SDNode *N) {
2649 return isa<StoreSDNode>(N) && !cast<StoreSDNode>(N)->isTruncatingStore();
2650 }
2651
2652 /// Returns true if the specified node is a truncating store.
2653 inline bool isTRUNCStore(const SDNode *N) {
2654 return isa<StoreSDNode>(N) && cast<StoreSDNode>(N)->isTruncatingStore();
2655 }
2656
2657 /// Returns true if the specified node is an unindexed store.
2658 inline bool isUNINDEXEDStore(const SDNode *N) {
2659 return isa<StoreSDNode>(N) &&
2660 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2661 }
2662
2663 /// Attempt to match a unary predicate against a scalar/splat constant or
2664 /// every element of a constant BUILD_VECTOR.
2665 /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
2666 bool matchUnaryPredicate(SDValue Op,
2667 std::function<bool(ConstantSDNode *)> Match,
2668 bool AllowUndefs = false);
2669
2670 /// Attempt to match a binary predicate against a pair of scalar/splat
2671 /// constants or every element of a pair of constant BUILD_VECTORs.
2672 /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
2673 /// If AllowTypeMismatch is true then RetType + ArgTypes don't need to match.
2674 bool matchBinaryPredicate(
2675 SDValue LHS, SDValue RHS,
2676 std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match,
2677 bool AllowUndefs = false, bool AllowTypeMismatch = false);
2678} // end namespace ISD
2679
2680} // end namespace llvm
2681
2682#endif // LLVM_CODEGEN_SELECTIONDAGNODES_H