Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1191, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name InstrEmitter.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/include -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-12-07-102640-14763-1 -x c++ /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements the Emit routines for the SelectionDAG class, which creates
10// MachineInstrs based on the decisions of the SelectionDAG instruction
11// selection.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstrEmitter.h"
16#include "SDNodeDbgValue.h"
17#include "llvm/ADT/Statistic.h"
18#include "llvm/CodeGen/MachineConstantPool.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/StackMaps.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/CodeGen/TargetLowering.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/IR/DebugInfo.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/MathExtras.h"
31using namespace llvm;
32
33#define DEBUG_TYPE"instr-emitter" "instr-emitter"
34
35/// MinRCSize - Smallest register class we allow when constraining virtual
36/// registers. If satisfying all register class constraints would require
37/// using a smaller register class, emit a COPY to a new virtual register
38/// instead.
39const unsigned MinRCSize = 4;
40
41/// CountResults - The results of target nodes have register or immediate
42/// operands first, then an optional chain, and optional glue operands (which do
43/// not go into the resulting MachineInstr).
44unsigned InstrEmitter::CountResults(SDNode *Node) {
45 unsigned N = Node->getNumValues();
46 while (N && Node->getValueType(N - 1) == MVT::Glue)
47 --N;
48 if (N && Node->getValueType(N - 1) == MVT::Other)
49 --N; // Skip over chain result.
50 return N;
51}
52
53/// countOperands - The inputs to target nodes have any actual inputs first,
54/// followed by an optional chain operand, then an optional glue operand.
55/// Compute the number of actual operands that will go into the resulting
56/// MachineInstr.
57///
58/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
59/// the chain and glue. These operands may be implicit on the machine instr.
60static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
61 unsigned &NumImpUses) {
62 unsigned N = Node->getNumOperands();
63 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
64 --N;
65 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
66 --N; // Ignore chain if it exists.
67
68 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
69 NumImpUses = N - NumExpUses;
70 for (unsigned I = N; I > NumExpUses; --I) {
71 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
72 continue;
73 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
74 if (Register::isPhysicalRegister(RN->getReg()))
75 continue;
76 NumImpUses = N - I;
77 break;
78 }
79
80 return N;
81}
82
83/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
84/// implicit physical register output.
85void InstrEmitter::
86EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
87 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
88 unsigned VRBase = 0;
89 if (Register::isVirtualRegister(SrcReg)) {
90 // Just use the input register directly!
91 SDValue Op(Node, ResNo);
92 if (IsClone)
93 VRBaseMap.erase(Op);
94 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
95 (void)isNew; // Silence compiler warning.
96 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 96, __PRETTY_FUNCTION__))
;
97 return;
98 }
99
100 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101 // the CopyToReg'd destination register instead of creating a new vreg.
102 bool MatchReg = true;
103 const TargetRegisterClass *UseRC = nullptr;
104 MVT VT = Node->getSimpleValueType(ResNo);
105
106 // Stick to the preferred register classes for legal types.
107 if (TLI->isTypeLegal(VT))
108 UseRC = TLI->getRegClassFor(VT, Node->isDivergent());
109
110 if (!IsClone && !IsCloned)
111 for (SDNode *User : Node->uses()) {
112 bool Match = true;
113 if (User->getOpcode() == ISD::CopyToReg &&
114 User->getOperand(2).getNode() == Node &&
115 User->getOperand(2).getResNo() == ResNo) {
116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117 if (Register::isVirtualRegister(DestReg)) {
118 VRBase = DestReg;
119 Match = false;
120 } else if (DestReg != SrcReg)
121 Match = false;
122 } else {
123 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
124 SDValue Op = User->getOperand(i);
125 if (Op.getNode() != Node || Op.getResNo() != ResNo)
126 continue;
127 MVT VT = Node->getSimpleValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
129 continue;
130 Match = false;
131 if (User->isMachineOpcode()) {
132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133 const TargetRegisterClass *RC = nullptr;
134 if (i+II.getNumDefs() < II.getNumOperands()) {
135 RC = TRI->getAllocatableClass(
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
137 }
138 if (!UseRC)
139 UseRC = RC;
140 else if (RC) {
141 const TargetRegisterClass *ComRC =
142 TRI->getCommonSubClass(UseRC, RC);
143 // If multiple uses expect disjoint register classes, we emit
144 // copies in AddRegisterOperand.
145 if (ComRC)
146 UseRC = ComRC;
147 }
148 }
149 }
150 }
151 MatchReg &= Match;
152 if (VRBase)
153 break;
154 }
155
156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
158
159 // Figure out the register class to create for the destreg.
160 if (VRBase) {
161 DstRC = MRI->getRegClass(VRBase);
162 } else if (UseRC) {
163 assert(TRI->isTypeLegalForClass(*UseRC, VT) &&((TRI->isTypeLegalForClass(*UseRC, VT) && "Incompatible phys register def and uses!"
) ? static_cast<void> (0) : __assert_fail ("TRI->isTypeLegalForClass(*UseRC, VT) && \"Incompatible phys register def and uses!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 164, __PRETTY_FUNCTION__))
164 "Incompatible phys register def and uses!")((TRI->isTypeLegalForClass(*UseRC, VT) && "Incompatible phys register def and uses!"
) ? static_cast<void> (0) : __assert_fail ("TRI->isTypeLegalForClass(*UseRC, VT) && \"Incompatible phys register def and uses!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 164, __PRETTY_FUNCTION__))
;
165 DstRC = UseRC;
166 } else {
167 DstRC = TLI->getRegClassFor(VT, Node->isDivergent());
168 }
169
170 // If all uses are reading from the src physical register and copying the
171 // register is either impossible or very expensive, then don't create a copy.
172 if (MatchReg && SrcRC->getCopyCost() < 0) {
173 VRBase = SrcReg;
174 } else {
175 // Create the reg, emit the copy.
176 VRBase = MRI->createVirtualRegister(DstRC);
177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
178 VRBase).addReg(SrcReg);
179 }
180
181 SDValue Op(Node, ResNo);
182 if (IsClone)
183 VRBaseMap.erase(Op);
184 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
185 (void)isNew; // Silence compiler warning.
186 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 186, __PRETTY_FUNCTION__))
;
187}
188
189void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
190 MachineInstrBuilder &MIB,
191 const MCInstrDesc &II,
192 bool IsClone, bool IsCloned,
193 DenseMap<SDValue, unsigned> &VRBaseMap) {
194 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&((Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!"
) ? static_cast<void> (0) : __assert_fail ("Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && \"IMPLICIT_DEF should have been handled as a special case elsewhere!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 195, __PRETTY_FUNCTION__))
195 "IMPLICIT_DEF should have been handled as a special case elsewhere!")((Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!"
) ? static_cast<void> (0) : __assert_fail ("Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && \"IMPLICIT_DEF should have been handled as a special case elsewhere!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 195, __PRETTY_FUNCTION__))
;
196
197 unsigned NumResults = CountResults(Node);
198 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
199 // If the specific node value is only used by a CopyToReg and the dest reg
200 // is a vreg in the same register class, use the CopyToReg'd destination
201 // register instead of creating a new vreg.
202 unsigned VRBase = 0;
203 const TargetRegisterClass *RC =
204 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
205 // Always let the value type influence the used register class. The
206 // constraints on the instruction may be too lax to represent the value
207 // type correctly. For example, a 64-bit float (X86::FR64) can't live in
208 // the 32-bit float super-class (X86::FR32).
209 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) {
210 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
211 Node->getSimpleValueType(i),
212 (Node->isDivergent() || (RC && TRI->isDivergentRegClass(RC))));
213 if (RC)
214 VTRC = TRI->getCommonSubClass(RC, VTRC);
215 if (VTRC)
216 RC = VTRC;
217 }
218
219 if (II.OpInfo[i].isOptionalDef()) {
220 // Optional def must be a physical register.
221 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
222 assert(Register::isPhysicalRegister(VRBase))((Register::isPhysicalRegister(VRBase)) ? static_cast<void
> (0) : __assert_fail ("Register::isPhysicalRegister(VRBase)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 222, __PRETTY_FUNCTION__))
;
223 MIB.addReg(VRBase, RegState::Define);
224 }
225
226 if (!VRBase && !IsClone && !IsCloned)
227 for (SDNode *User : Node->uses()) {
228 if (User->getOpcode() == ISD::CopyToReg &&
229 User->getOperand(2).getNode() == Node &&
230 User->getOperand(2).getResNo() == i) {
231 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
232 if (Register::isVirtualRegister(Reg)) {
233 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
234 if (RegRC == RC) {
235 VRBase = Reg;
236 MIB.addReg(VRBase, RegState::Define);
237 break;
238 }
239 }
240 }
241 }
242
243 // Create the result registers for this node and add the result regs to
244 // the machine instruction.
245 if (VRBase == 0) {
246 assert(RC && "Isn't a register operand!")((RC && "Isn't a register operand!") ? static_cast<
void> (0) : __assert_fail ("RC && \"Isn't a register operand!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 246, __PRETTY_FUNCTION__))
;
247 VRBase = MRI->createVirtualRegister(RC);
248 MIB.addReg(VRBase, RegState::Define);
249 }
250
251 // If this def corresponds to a result of the SDNode insert the VRBase into
252 // the lookup map.
253 if (i < NumResults) {
254 SDValue Op(Node, i);
255 if (IsClone)
256 VRBaseMap.erase(Op);
257 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
258 (void)isNew; // Silence compiler warning.
259 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 259, __PRETTY_FUNCTION__))
;
260 }
261 }
262}
263
264/// getVR - Return the virtual register corresponding to the specified result
265/// of the specified node.
266unsigned InstrEmitter::getVR(SDValue Op,
267 DenseMap<SDValue, unsigned> &VRBaseMap) {
268 if (Op.isMachineOpcode() &&
6
Calling 'SDValue::isMachineOpcode'
269 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
270 // Add an IMPLICIT_DEF instruction before every use.
271 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
272 // does not include operand register class info.
273 const TargetRegisterClass *RC = TLI->getRegClassFor(
274 Op.getSimpleValueType(), Op.getNode()->isDivergent());
275 Register VReg = MRI->createVirtualRegister(RC);
276 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
277 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
278 return VReg;
279 }
280
281 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
282 assert(I != VRBaseMap.end() && "Node emitted out of order - late")((I != VRBaseMap.end() && "Node emitted out of order - late"
) ? static_cast<void> (0) : __assert_fail ("I != VRBaseMap.end() && \"Node emitted out of order - late\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 282, __PRETTY_FUNCTION__))
;
283 return I->second;
284}
285
286
287/// AddRegisterOperand - Add the specified register as an operand to the
288/// specified machine instr. Insert register copies if the register is
289/// not in the required register class.
290void
291InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
292 SDValue Op,
293 unsigned IIOpNum,
294 const MCInstrDesc *II,
295 DenseMap<SDValue, unsigned> &VRBaseMap,
296 bool IsDebug, bool IsClone, bool IsCloned) {
297 assert(Op.getValueType() != MVT::Other &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 299, __PRETTY_FUNCTION__))
298 Op.getValueType() != MVT::Glue &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 299, __PRETTY_FUNCTION__))
299 "Chain and glue operands should occur at end of operand list!")((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 299, __PRETTY_FUNCTION__))
;
300 // Get/emit the operand.
301 unsigned VReg = getVR(Op, VRBaseMap);
302
303 const MCInstrDesc &MCID = MIB->getDesc();
304 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
305 MCID.OpInfo[IIOpNum].isOptionalDef();
306
307 // If the instruction requires a register in a different class, create
308 // a new virtual register and copy the value into it, but first attempt to
309 // shrink VReg's register class within reason. For example, if VReg == GR32
310 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
311 if (II) {
312 const TargetRegisterClass *OpRC = nullptr;
313 if (IIOpNum < II->getNumOperands())
314 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
315
316 if (OpRC) {
317 const TargetRegisterClass *ConstrainedRC
318 = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
319 if (!ConstrainedRC) {
320 OpRC = TRI->getAllocatableClass(OpRC);
321 assert(OpRC && "Constraints cannot be fulfilled for allocation")((OpRC && "Constraints cannot be fulfilled for allocation"
) ? static_cast<void> (0) : __assert_fail ("OpRC && \"Constraints cannot be fulfilled for allocation\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 321, __PRETTY_FUNCTION__))
;
322 Register NewVReg = MRI->createVirtualRegister(OpRC);
323 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
324 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
325 VReg = NewVReg;
326 } else {
327 assert(ConstrainedRC->isAllocatable() &&((ConstrainedRC->isAllocatable() && "Constraining an allocatable VReg produced an unallocatable class?"
) ? static_cast<void> (0) : __assert_fail ("ConstrainedRC->isAllocatable() && \"Constraining an allocatable VReg produced an unallocatable class?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 328, __PRETTY_FUNCTION__))
328 "Constraining an allocatable VReg produced an unallocatable class?")((ConstrainedRC->isAllocatable() && "Constraining an allocatable VReg produced an unallocatable class?"
) ? static_cast<void> (0) : __assert_fail ("ConstrainedRC->isAllocatable() && \"Constraining an allocatable VReg produced an unallocatable class?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 328, __PRETTY_FUNCTION__))
;
329 }
330 }
331 }
332
333 // If this value has only one use, that use is a kill. This is a
334 // conservative approximation. InstrEmitter does trivial coalescing
335 // with CopyFromReg nodes, so don't emit kill flags for them.
336 // Avoid kill flags on Schedule cloned nodes, since there will be
337 // multiple uses.
338 // Tied operands are never killed, so we need to check that. And that
339 // means we need to determine the index of the operand.
340 bool isKill = Op.hasOneUse() &&
341 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
342 !IsDebug &&
343 !(IsClone || IsCloned);
344 if (isKill) {
345 unsigned Idx = MIB->getNumOperands();
346 while (Idx > 0 &&
347 MIB->getOperand(Idx-1).isReg() &&
348 MIB->getOperand(Idx-1).isImplicit())
349 --Idx;
350 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
351 if (isTied)
352 isKill = false;
353 }
354
355 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
356 getDebugRegState(IsDebug));
357}
358
359/// AddOperand - Add the specified operand to the specified machine instr. II
360/// specifies the instruction information for the node, and IIOpNum is the
361/// operand number (in the II) that we are adding.
362void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
363 SDValue Op,
364 unsigned IIOpNum,
365 const MCInstrDesc *II,
366 DenseMap<SDValue, unsigned> &VRBaseMap,
367 bool IsDebug, bool IsClone, bool IsCloned) {
368 if (Op.isMachineOpcode()) {
369 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
370 IsDebug, IsClone, IsCloned);
371 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
372 MIB.addImm(C->getSExtValue());
373 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
374 MIB.addFPImm(F->getConstantFPValue());
375 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
376 unsigned VReg = R->getReg();
377 MVT OpVT = Op.getSimpleValueType();
378 const TargetRegisterClass *IIRC =
379 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF))
380 : nullptr;
381 const TargetRegisterClass *OpRC =
382 TLI->isTypeLegal(OpVT)
383 ? TLI->getRegClassFor(OpVT,
384 Op.getNode()->isDivergent() ||
385 (IIRC && TRI->isDivergentRegClass(IIRC)))
386 : nullptr;
387
388 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
389 Register NewVReg = MRI->createVirtualRegister(IIRC);
390 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
391 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
392 VReg = NewVReg;
393 }
394 // Turn additional physreg operands into implicit uses on non-variadic
395 // instructions. This is used by call and return instructions passing
396 // arguments in registers.
397 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
398 MIB.addReg(VReg, getImplRegState(Imp));
399 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
400 MIB.addRegMask(RM->getRegMask());
401 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
402 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(),
403 TGA->getTargetFlags());
404 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
405 MIB.addMBB(BBNode->getBasicBlock());
406 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
407 MIB.addFrameIndex(FI->getIndex());
408 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
409 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags());
410 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
411 int Offset = CP->getOffset();
412 unsigned Align = CP->getAlignment();
413 Type *Type = CP->getType();
414 // MachineConstantPool wants an explicit alignment.
415 if (Align == 0) {
416 Align = MF->getDataLayout().getPrefTypeAlignment(Type);
417 if (Align == 0) {
418 // Alignment of vector types. FIXME!
419 Align = MF->getDataLayout().getTypeAllocSize(Type);
420 }
421 }
422
423 unsigned Idx;
424 MachineConstantPool *MCP = MF->getConstantPool();
425 if (CP->isMachineConstantPoolEntry())
426 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
427 else
428 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
429 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags());
430 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
431 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags());
432 } else if (auto *SymNode = dyn_cast<MCSymbolSDNode>(Op)) {
433 MIB.addSym(SymNode->getMCSymbol());
434 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
435 MIB.addBlockAddress(BA->getBlockAddress(),
436 BA->getOffset(),
437 BA->getTargetFlags());
438 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
439 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags());
440 } else {
441 assert(Op.getValueType() != MVT::Other &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 443, __PRETTY_FUNCTION__))
442 Op.getValueType() != MVT::Glue &&((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 443, __PRETTY_FUNCTION__))
443 "Chain and glue operands should occur at end of operand list!")((Op.getValueType() != MVT::Other && Op.getValueType(
) != MVT::Glue && "Chain and glue operands should occur at end of operand list!"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() != MVT::Other && Op.getValueType() != MVT::Glue && \"Chain and glue operands should occur at end of operand list!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 443, __PRETTY_FUNCTION__))
;
444 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
445 IsDebug, IsClone, IsCloned);
446 }
447}
448
449unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
450 MVT VT, bool isDivergent, const DebugLoc &DL) {
451 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
452 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
453
454 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
455 // within reason.
456 if (RC && RC != VRC)
457 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
458
459 // VReg has been adjusted. It can be used with SubIdx operands now.
460 if (RC)
461 return VReg;
462
463 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
464 // register instead.
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
466 assert(RC && "No legal register class for VT supports that SubIdx")((RC && "No legal register class for VT supports that SubIdx"
) ? static_cast<void> (0) : __assert_fail ("RC && \"No legal register class for VT supports that SubIdx\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 466, __PRETTY_FUNCTION__))
;
467 Register NewReg = MRI->createVirtualRegister(RC);
468 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
469 .addReg(VReg);
470 return NewReg;
471}
472
473/// EmitSubregNode - Generate machine code for subreg nodes.
474///
475void InstrEmitter::EmitSubregNode(SDNode *Node,
476 DenseMap<SDValue, unsigned> &VRBaseMap,
477 bool IsClone, bool IsCloned) {
478 unsigned VRBase = 0;
479 unsigned Opc = Node->getMachineOpcode();
480
481 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
482 // the CopyToReg'd destination register instead of creating a new vreg.
483 for (SDNode *User : Node->uses()) {
484 if (User->getOpcode() == ISD::CopyToReg &&
485 User->getOperand(2).getNode() == Node) {
486 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
487 if (Register::isVirtualRegister(DestReg)) {
488 VRBase = DestReg;
489 break;
490 }
491 }
492 }
493
494 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
495 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
496 // constraints on the %dst register, COPY can target all legal register
497 // classes.
498 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
499 const TargetRegisterClass *TRC =
500 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
501
502 unsigned Reg;
503 MachineInstr *DefMI;
504 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(0));
505 if (R && Register::isPhysicalRegister(R->getReg())) {
506 Reg = R->getReg();
507 DefMI = nullptr;
508 } else {
509 Reg = R ? R->getReg() : getVR(Node->getOperand(0), VRBaseMap);
510 DefMI = MRI->getVRegDef(Reg);
511 }
512
513 unsigned SrcReg, DstReg, DefSubIdx;
514 if (DefMI &&
515 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
516 SubIdx == DefSubIdx &&
517 TRC == MRI->getRegClass(SrcReg)) {
518 // Optimize these:
519 // r1025 = s/zext r1024, 4
520 // r1026 = extract_subreg r1025, 4
521 // to a copy
522 // r1026 = copy r1024
523 VRBase = MRI->createVirtualRegister(TRC);
524 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
525 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
526 MRI->clearKillFlags(SrcReg);
527 } else {
528 // Reg may not support a SubIdx sub-register, and we may need to
529 // constrain its register class or issue a COPY to a compatible register
530 // class.
531 if (Register::isVirtualRegister(Reg))
532 Reg = ConstrainForSubReg(Reg, SubIdx,
533 Node->getOperand(0).getSimpleValueType(),
534 Node->isDivergent(), Node->getDebugLoc());
535 // Create the destreg if it is missing.
536 if (VRBase == 0)
537 VRBase = MRI->createVirtualRegister(TRC);
538
539 // Create the extract_subreg machine instruction.
540 MachineInstrBuilder CopyMI =
541 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
542 TII->get(TargetOpcode::COPY), VRBase);
543 if (Register::isVirtualRegister(Reg))
544 CopyMI.addReg(Reg, 0, SubIdx);
545 else
546 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
547 }
548 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
549 Opc == TargetOpcode::SUBREG_TO_REG) {
550 SDValue N0 = Node->getOperand(0);
551 SDValue N1 = Node->getOperand(1);
552 SDValue N2 = Node->getOperand(2);
553 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
554
555 // Figure out the register class to create for the destreg. It should be
556 // the largest legal register class supporting SubIdx sub-registers.
557 // RegisterCoalescer will constrain it further if it decides to eliminate
558 // the INSERT_SUBREG instruction.
559 //
560 // %dst = INSERT_SUBREG %src, %sub, SubIdx
561 //
562 // is lowered by TwoAddressInstructionPass to:
563 //
564 // %dst = COPY %src
565 // %dst:SubIdx = COPY %sub
566 //
567 // There is no constraint on the %src register class.
568 //
569 const TargetRegisterClass *SRC =
570 TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
571 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
572 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG")((SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"
) ? static_cast<void> (0) : __assert_fail ("SRC && \"No register class supports VT and SubIdx for INSERT_SUBREG\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 572, __PRETTY_FUNCTION__))
;
573
574 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
575 VRBase = MRI->createVirtualRegister(SRC);
576
577 // Create the insert_subreg or subreg_to_reg machine instruction.
578 MachineInstrBuilder MIB =
579 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
580
581 // If creating a subreg_to_reg, then the first input operand
582 // is an implicit value immediate, otherwise it's a register
583 if (Opc == TargetOpcode::SUBREG_TO_REG) {
584 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
585 MIB.addImm(SD->getZExtValue());
586 } else
587 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
588 IsClone, IsCloned);
589 // Add the subregister being inserted
590 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
591 IsClone, IsCloned);
592 MIB.addImm(SubIdx);
593 MBB->insert(InsertPos, MIB);
594 } else
595 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg")::llvm::llvm_unreachable_internal("Node is not insert_subreg, extract_subreg, or subreg_to_reg"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 595)
;
596
597 SDValue Op(Node, 0);
598 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
599 (void)isNew; // Silence compiler warning.
600 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 600, __PRETTY_FUNCTION__))
;
601}
602
603/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
604/// COPY_TO_REGCLASS is just a normal copy, except that the destination
605/// register is constrained to be in a particular register class.
606///
607void
608InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
609 DenseMap<SDValue, unsigned> &VRBaseMap) {
610 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
611
612 // Create the new VReg in the destination class and emit a copy.
613 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
614 const TargetRegisterClass *DstRC =
615 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
616 Register NewVReg = MRI->createVirtualRegister(DstRC);
617 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
618 NewVReg).addReg(VReg);
619
620 SDValue Op(Node, 0);
621 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
622 (void)isNew; // Silence compiler warning.
623 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 623, __PRETTY_FUNCTION__))
;
624}
625
626/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
627///
628void InstrEmitter::EmitRegSequence(SDNode *Node,
629 DenseMap<SDValue, unsigned> &VRBaseMap,
630 bool IsClone, bool IsCloned) {
631 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
632 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
633 Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
634 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
635 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
636 unsigned NumOps = Node->getNumOperands();
637 // If the input pattern has a chain, then the root of the corresponding
638 // output pattern will get a chain as well. This can happen to be a
639 // REG_SEQUENCE (which is not "guarded" by countOperands/CountResults).
640 if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other)
641 --NumOps; // Ignore chain if it exists.
642
643 assert((NumOps & 1) == 1 &&(((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"
) ? static_cast<void> (0) : __assert_fail ("(NumOps & 1) == 1 && \"REG_SEQUENCE must have an odd number of operands!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 644, __PRETTY_FUNCTION__))
644 "REG_SEQUENCE must have an odd number of operands!")(((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"
) ? static_cast<void> (0) : __assert_fail ("(NumOps & 1) == 1 && \"REG_SEQUENCE must have an odd number of operands!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 644, __PRETTY_FUNCTION__))
;
645 for (unsigned i = 1; i != NumOps; ++i) {
646 SDValue Op = Node->getOperand(i);
647 if ((i & 1) == 0) {
648 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
649 // Skip physical registers as they don't have a vreg to get and we'll
650 // insert copies for them in TwoAddressInstructionPass anyway.
651 if (!R || !Register::isPhysicalRegister(R->getReg())) {
652 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
653 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
655 const TargetRegisterClass *SRC =
656 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
657 if (SRC && SRC != RC) {
658 MRI->setRegClass(NewVReg, SRC);
659 RC = SRC;
660 }
661 }
662 }
663 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
664 IsClone, IsCloned);
665 }
666
667 MBB->insert(InsertPos, MIB);
668 SDValue Op(Node, 0);
669 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
670 (void)isNew; // Silence compiler warning.
671 assert(isNew && "Node emitted out of order - early")((isNew && "Node emitted out of order - early") ? static_cast
<void> (0) : __assert_fail ("isNew && \"Node emitted out of order - early\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 671, __PRETTY_FUNCTION__))
;
672}
673
674/// EmitDbgValue - Generate machine instruction for a dbg_value node.
675///
676MachineInstr *
677InstrEmitter::EmitDbgValue(SDDbgValue *SD,
678 DenseMap<SDValue, unsigned> &VRBaseMap) {
679 MDNode *Var = SD->getVariable();
680 const DIExpression *Expr = SD->getExpression();
681 DebugLoc DL = SD->getDebugLoc();
682 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Var)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 683, __PRETTY_FUNCTION__))
683 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Var)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 683, __PRETTY_FUNCTION__))
;
684
685 SD->setIsEmitted();
686
687 if (SD->isInvalidated()) {
688 // An invalidated SDNode must generate an undef DBG_VALUE: although the
689 // original value is no longer computed, earlier DBG_VALUEs live ranges
690 // must not leak into later code.
691 auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
692 MIB.addReg(0U);
693 MIB.addReg(0U, RegState::Debug);
694 MIB.addMetadata(Var);
695 MIB.addMetadata(Expr);
696 return &*MIB;
697 }
698
699 if (SD->getKind() == SDDbgValue::FRAMEIX) {
700 // Stack address; this needs to be lowered in target-dependent fashion.
701 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
702 auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
703 .addFrameIndex(SD->getFrameIx());
704
705 if (SD->isIndirect())
706 Expr = DIExpression::append(Expr, {dwarf::DW_OP_deref});
707
708 FrameMI.addReg(0);
709 return FrameMI.addMetadata(Var).addMetadata(Expr);
710 }
711 // Otherwise, we're going to create an instruction here.
712 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
713 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
714 if (SD->getKind() == SDDbgValue::SDNODE) {
715 SDNode *Node = SD->getSDNode();
716 SDValue Op = SDValue(Node, SD->getResNo());
717 // It's possible we replaced this SDNode with other(s) and therefore
718 // didn't generate code for it. It's better to catch these cases where
719 // they happen and transfer the debug info, but trying to guarantee that
720 // in all cases would be very fragile; this is a safeguard for any
721 // that were missed.
722 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
723 if (I==VRBaseMap.end())
724 MIB.addReg(0U); // undef
725 else
726 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
727 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
728 } else if (SD->getKind() == SDDbgValue::VREG) {
729 MIB.addReg(SD->getVReg(), RegState::Debug);
730 } else if (SD->getKind() == SDDbgValue::CONST) {
731 const Value *V = SD->getConst();
732 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
733 if (CI->getBitWidth() > 64)
734 MIB.addCImm(CI);
735 else
736 MIB.addImm(CI->getSExtValue());
737 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
738 MIB.addFPImm(CF);
739 } else if (isa<ConstantPointerNull>(V)) {
740 // Note: This assumes that all nullptr constants are zero-valued.
741 MIB.addImm(0);
742 } else {
743 // Could be an Undef. In any case insert an Undef so we can see what we
744 // dropped.
745 MIB.addReg(0U);
746 }
747 } else {
748 // Insert an Undef so we can see what we dropped.
749 MIB.addReg(0U);
750 }
751
752 // Indirect addressing is indicated by an Imm as the second parameter.
753 if (SD->isIndirect())
754 Expr = DIExpression::append(Expr, {dwarf::DW_OP_deref});
755
756 MIB.addReg(0U, RegState::Debug);
757
758 MIB.addMetadata(Var);
759 MIB.addMetadata(Expr);
760
761 return &*MIB;
762}
763
764MachineInstr *
765InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
766 MDNode *Label = SD->getLabel();
767 DebugLoc DL = SD->getDebugLoc();
768 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) &&((cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 769, __PRETTY_FUNCTION__))
769 "Expected inlined-at fields to agree")((cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILabel>(Label)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 769, __PRETTY_FUNCTION__))
;
770
771 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL);
772 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
773 MIB.addMetadata(Label);
774
775 return &*MIB;
776}
777
778/// EmitMachineNode - Generate machine code for a target-specific node and
779/// needed dependencies.
780///
781void InstrEmitter::
782EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
783 DenseMap<SDValue, unsigned> &VRBaseMap) {
784 unsigned Opc = Node->getMachineOpcode();
785
786 // Handle subreg insert/extract specially
787 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
788 Opc == TargetOpcode::INSERT_SUBREG ||
789 Opc == TargetOpcode::SUBREG_TO_REG) {
790 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
791 return;
792 }
793
794 // Handle COPY_TO_REGCLASS specially.
795 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
796 EmitCopyToRegClassNode(Node, VRBaseMap);
797 return;
798 }
799
800 // Handle REG_SEQUENCE specially.
801 if (Opc == TargetOpcode::REG_SEQUENCE) {
802 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
803 return;
804 }
805
806 if (Opc == TargetOpcode::IMPLICIT_DEF)
807 // We want a unique VR for each IMPLICIT_DEF use.
808 return;
809
810 const MCInstrDesc &II = TII->get(Opc);
811 unsigned NumResults = CountResults(Node);
812 unsigned NumDefs = II.getNumDefs();
813 const MCPhysReg *ScratchRegs = nullptr;
814
815 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
816 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
817 // Stackmaps do not have arguments and do not preserve their calling
818 // convention. However, to simplify runtime support, they clobber the same
819 // scratch registers as AnyRegCC.
820 unsigned CC = CallingConv::AnyReg;
821 if (Opc == TargetOpcode::PATCHPOINT) {
822 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos);
823 NumDefs = NumResults;
824 }
825 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC);
826 }
827
828 unsigned NumImpUses = 0;
829 unsigned NodeOperands =
830 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses);
831 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr;
832#ifndef NDEBUG
833 unsigned NumMIOperands = NodeOperands + NumResults;
834 if (II.isVariadic())
835 assert(NumMIOperands >= II.getNumOperands() &&((NumMIOperands >= II.getNumOperands() && "Too few operands for a variadic node!"
) ? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && \"Too few operands for a variadic node!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 836, __PRETTY_FUNCTION__))
836 "Too few operands for a variadic node!")((NumMIOperands >= II.getNumOperands() && "Too few operands for a variadic node!"
) ? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && \"Too few operands for a variadic node!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 836, __PRETTY_FUNCTION__))
;
837 else
838 assert(NumMIOperands >= II.getNumOperands() &&((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 841, __PRETTY_FUNCTION__))
839 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 841, __PRETTY_FUNCTION__))
840 NumImpUses &&((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 841, __PRETTY_FUNCTION__))
841 "#operands for dag node doesn't match .td file!")((NumMIOperands >= II.getNumOperands() && NumMIOperands
<= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses
&& "#operands for dag node doesn't match .td file!")
? static_cast<void> (0) : __assert_fail ("NumMIOperands >= II.getNumOperands() && NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + NumImpUses && \"#operands for dag node doesn't match .td file!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 841, __PRETTY_FUNCTION__))
;
842#endif
843
844 // Create the new machine instruction.
845 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
846
847 // Add result register values for things that are defined by this
848 // instruction.
849 if (NumResults) {
850 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap);
851
852 // Transfer any IR flags from the SDNode to the MachineInstr
853 MachineInstr *MI = MIB.getInstr();
854 const SDNodeFlags Flags = Node->getFlags();
855 if (Flags.hasNoSignedZeros())
856 MI->setFlag(MachineInstr::MIFlag::FmNsz);
857
858 if (Flags.hasAllowReciprocal())
859 MI->setFlag(MachineInstr::MIFlag::FmArcp);
860
861 if (Flags.hasNoNaNs())
862 MI->setFlag(MachineInstr::MIFlag::FmNoNans);
863
864 if (Flags.hasNoInfs())
865 MI->setFlag(MachineInstr::MIFlag::FmNoInfs);
866
867 if (Flags.hasAllowContract())
868 MI->setFlag(MachineInstr::MIFlag::FmContract);
869
870 if (Flags.hasApproximateFuncs())
871 MI->setFlag(MachineInstr::MIFlag::FmAfn);
872
873 if (Flags.hasAllowReassociation())
874 MI->setFlag(MachineInstr::MIFlag::FmReassoc);
875
876 if (Flags.hasNoUnsignedWrap())
877 MI->setFlag(MachineInstr::MIFlag::NoUWrap);
878
879 if (Flags.hasNoSignedWrap())
880 MI->setFlag(MachineInstr::MIFlag::NoSWrap);
881
882 if (Flags.hasExact())
883 MI->setFlag(MachineInstr::MIFlag::IsExact);
884
885 if (Flags.hasFPExcept())
886 MI->setFlag(MachineInstr::MIFlag::FPExcept);
887 }
888
889 // Emit all of the actual operands of this instruction, adding them to the
890 // instruction as appropriate.
891 bool HasOptPRefs = NumDefs > NumResults;
892 assert((!HasOptPRefs || !HasPhysRegOuts) &&(((!HasOptPRefs || !HasPhysRegOuts) && "Unable to cope with optional defs and phys regs defs!"
) ? static_cast<void> (0) : __assert_fail ("(!HasOptPRefs || !HasPhysRegOuts) && \"Unable to cope with optional defs and phys regs defs!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 893, __PRETTY_FUNCTION__))
893 "Unable to cope with optional defs and phys regs defs!")(((!HasOptPRefs || !HasPhysRegOuts) && "Unable to cope with optional defs and phys regs defs!"
) ? static_cast<void> (0) : __assert_fail ("(!HasOptPRefs || !HasPhysRegOuts) && \"Unable to cope with optional defs and phys regs defs!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 893, __PRETTY_FUNCTION__))
;
894 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0;
895 for (unsigned i = NumSkip; i != NodeOperands; ++i)
896 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II,
897 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
898
899 // Add scratch registers as implicit def and early clobber
900 if (ScratchRegs)
901 for (unsigned i = 0; ScratchRegs[i]; ++i)
902 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
903 RegState::EarlyClobber);
904
905 // Set the memory reference descriptions of this instruction now that it is
906 // part of the function.
907 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands());
908
909 // Insert the instruction into position in the block. This needs to
910 // happen before any custom inserter hook is called so that the
911 // hook knows where in the block to insert the replacement code.
912 MBB->insert(InsertPos, MIB);
913
914 // The MachineInstr may also define physregs instead of virtregs. These
915 // physreg values can reach other instructions in different ways:
916 //
917 // 1. When there is a use of a Node value beyond the explicitly defined
918 // virtual registers, we emit a CopyFromReg for one of the implicitly
919 // defined physregs. This only happens when HasPhysRegOuts is true.
920 //
921 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
922 //
923 // 3. A glued instruction may implicitly use a physreg.
924 //
925 // 4. A glued instruction may use a RegisterSDNode operand.
926 //
927 // Collect all the used physreg defs, and make sure that any unused physreg
928 // defs are marked as dead.
929 SmallVector<Register, 8> UsedRegs;
930
931 // Additional results must be physical register defs.
932 if (HasPhysRegOuts) {
933 for (unsigned i = NumDefs; i < NumResults; ++i) {
934 Register Reg = II.getImplicitDefs()[i - NumDefs];
935 if (!Node->hasAnyUseOfValue(i))
936 continue;
937 // This implicitly defined physreg has a use.
938 UsedRegs.push_back(Reg);
939 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
940 }
941 }
942
943 // Scan the glue chain for any used physregs.
944 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
945 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
946 if (F->getOpcode() == ISD::CopyFromReg) {
947 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
948 continue;
949 } else if (F->getOpcode() == ISD::CopyToReg) {
950 // Skip CopyToReg nodes that are internal to the glue chain.
951 continue;
952 }
953 // Collect declared implicit uses.
954 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
955 UsedRegs.append(MCID.getImplicitUses(),
956 MCID.getImplicitUses() + MCID.getNumImplicitUses());
957 // In addition to declared implicit uses, we must also check for
958 // direct RegisterSDNode operands.
959 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
960 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
961 Register Reg = R->getReg();
962 if (Reg.isPhysical())
963 UsedRegs.push_back(Reg);
964 }
965 }
966 }
967
968 // Finally mark unused registers as dead.
969 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef())
970 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI);
971
972 // Run post-isel target hook to adjust this instruction if needed.
973 if (II.hasPostISelHook())
974 TLI->AdjustInstrPostInstrSelection(*MIB, Node);
975}
976
977/// EmitSpecialNode - Generate machine code for a target-independent node and
978/// needed dependencies.
979void InstrEmitter::
980EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
981 DenseMap<SDValue, unsigned> &VRBaseMap) {
982 switch (Node->getOpcode()) {
1
Control jumps to 'case CopyToReg:' at line 993
983 default:
984#ifndef NDEBUG
985 Node->dump();
986#endif
987 llvm_unreachable("This target-independent node should have been selected!")::llvm::llvm_unreachable_internal("This target-independent node should have been selected!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 987)
;
988 case ISD::EntryToken:
989 llvm_unreachable("EntryToken should have been excluded from the schedule!")::llvm::llvm_unreachable_internal("EntryToken should have been excluded from the schedule!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 989)
;
990 case ISD::MERGE_VALUES:
991 case ISD::TokenFactor: // fall thru
992 break;
993 case ISD::CopyToReg: {
994 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
995 SDValue SrcVal = Node->getOperand(2);
996 if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
997 SrcVal.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
998 // Instead building a COPY to that vreg destination, build an
999 // IMPLICIT_DEF instruction instead.
1000 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1001 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
1002 break;
1003 }
1004 unsigned SrcReg;
1005 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
2
Assuming 'R' is null
3
Taking false branch
1006 SrcReg = R->getReg();
1007 else
1008 SrcReg = getVR(SrcVal, VRBaseMap);
4
Value assigned to 'Op.Node'
5
Calling 'InstrEmitter::getVR'
1009
1010 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
1011 break;
1012
1013 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1014 DestReg).addReg(SrcReg);
1015 break;
1016 }
1017 case ISD::CopyFromReg: {
1018 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1019 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
1020 break;
1021 }
1022 case ISD::EH_LABEL:
1023 case ISD::ANNOTATION_LABEL: {
1024 unsigned Opc = (Node->getOpcode() == ISD::EH_LABEL)
1025 ? TargetOpcode::EH_LABEL
1026 : TargetOpcode::ANNOTATION_LABEL;
1027 MCSymbol *S = cast<LabelSDNode>(Node)->getLabel();
1028 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1029 TII->get(Opc)).addSym(S);
1030 break;
1031 }
1032
1033 case ISD::LIFETIME_START:
1034 case ISD::LIFETIME_END: {
1035 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
1036 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
1037
1038 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
1039 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
1040 .addFrameIndex(FI->getIndex());
1041 break;
1042 }
1043
1044 case ISD::INLINEASM:
1045 case ISD::INLINEASM_BR: {
1046 unsigned NumOps = Node->getNumOperands();
1047 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1048 --NumOps; // Ignore the glue operand.
1049
1050 // Create the inline asm machine instruction.
1051 unsigned TgtOpc = Node->getOpcode() == ISD::INLINEASM_BR
1052 ? TargetOpcode::INLINEASM_BR
1053 : TargetOpcode::INLINEASM;
1054 MachineInstrBuilder MIB =
1055 BuildMI(*MF, Node->getDebugLoc(), TII->get(TgtOpc));
1056
1057 // Add the asm string as an external symbol operand.
1058 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
1059 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
1060 MIB.addExternalSymbol(AsmStr);
1061
1062 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
1063 // bits.
1064 int64_t ExtraInfo =
1065 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
1066 getZExtValue();
1067 MIB.addImm(ExtraInfo);
1068
1069 // Remember to operand index of the group flags.
1070 SmallVector<unsigned, 8> GroupIdx;
1071
1072 // Remember registers that are part of early-clobber defs.
1073 SmallVector<unsigned, 8> ECRegs;
1074
1075 // Add all of the operand registers to the instruction.
1076 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1077 unsigned Flags =
1078 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1079 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1080
1081 GroupIdx.push_back(MIB->getNumOperands());
1082 MIB.addImm(Flags);
1083 ++i; // Skip the ID value.
1084
1085 switch (InlineAsm::getKind(Flags)) {
1086 default: llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1086)
;
1087 case InlineAsm::Kind_RegDef:
1088 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1089 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1090 // FIXME: Add dead flags for physical and virtual registers defined.
1091 // For now, mark physical register defs as implicit to help fast
1092 // regalloc. This makes inline asm look a lot like calls.
1093 MIB.addReg(Reg,
1094 RegState::Define |
1095 getImplRegState(Register::isPhysicalRegister(Reg)));
1096 }
1097 break;
1098 case InlineAsm::Kind_RegDefEarlyClobber:
1099 case InlineAsm::Kind_Clobber:
1100 for (unsigned j = 0; j != NumVals; ++j, ++i) {
1101 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1102 MIB.addReg(Reg,
1103 RegState::Define | RegState::EarlyClobber |
1104 getImplRegState(Register::isPhysicalRegister(Reg)));
1105 ECRegs.push_back(Reg);
1106 }
1107 break;
1108 case InlineAsm::Kind_RegUse: // Use of register.
1109 case InlineAsm::Kind_Imm: // Immediate.
1110 case InlineAsm::Kind_Mem: // Addressing mode.
1111 // The addressing mode has been selected, just add all of the
1112 // operands to the machine instruction.
1113 for (unsigned j = 0; j != NumVals; ++j, ++i)
1114 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap,
1115 /*IsDebug=*/false, IsClone, IsCloned);
1116
1117 // Manually set isTied bits.
1118 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
1119 unsigned DefGroup = 0;
1120 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
1121 unsigned DefIdx = GroupIdx[DefGroup] + 1;
1122 unsigned UseIdx = GroupIdx.back() + 1;
1123 for (unsigned j = 0; j != NumVals; ++j)
1124 MIB->tieOperands(DefIdx + j, UseIdx + j);
1125 }
1126 }
1127 break;
1128 }
1129 }
1130
1131 // GCC inline assembly allows input operands to also be early-clobber
1132 // output operands (so long as the operand is written only after it's
1133 // used), but this does not match the semantics of our early-clobber flag.
1134 // If an early-clobber operand register is also an input operand register,
1135 // then remove the early-clobber flag.
1136 for (unsigned Reg : ECRegs) {
1137 if (MIB->readsRegister(Reg, TRI)) {
1138 MachineOperand *MO =
1139 MIB->findRegisterDefOperand(Reg, false, false, TRI);
1140 assert(MO && "No def operand for clobbered register?")((MO && "No def operand for clobbered register?") ? static_cast
<void> (0) : __assert_fail ("MO && \"No def operand for clobbered register?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp"
, 1140, __PRETTY_FUNCTION__))
;
1141 MO->setIsEarlyClobber(false);
1142 }
1143 }
1144
1145 // Get the mdnode from the asm if it exists and add it to the instruction.
1146 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
1147 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
1148 if (MD)
1149 MIB.addMetadata(MD);
1150
1151 MBB->insert(InsertPos, MIB);
1152 break;
1153 }
1154 }
1155}
1156
1157/// InstrEmitter - Construct an InstrEmitter and set it to start inserting
1158/// at the given position in the given block.
1159InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
1160 MachineBasicBlock::iterator insertpos)
1161 : MF(mbb->getParent()), MRI(&MF->getRegInfo()),
1162 TII(MF->getSubtarget().getInstrInfo()),
1163 TRI(MF->getSubtarget().getRegisterInfo()),
1164 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb),
1165 InsertPos(insertpos) {}

/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/Constants.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Instruction.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/Metadata.h"
39#include "llvm/IR/Operator.h"
40#include "llvm/Support/AlignOf.h"
41#include "llvm/Support/AtomicOrdering.h"
42#include "llvm/Support/Casting.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MachineValueType.h"
45#include <algorithm>
46#include <cassert>
47#include <climits>
48#include <cstddef>
49#include <cstdint>
50#include <cstring>
51#include <iterator>
52#include <string>
53#include <tuple>
54
55namespace llvm {
56
57class APInt;
58class Constant;
59template <typename T> struct DenseMapInfo;
60class GlobalValue;
61class MachineBasicBlock;
62class MachineConstantPoolValue;
63class MCSymbol;
64class raw_ostream;
65class SDNode;
66class SelectionDAG;
67class Type;
68class Value;
69
70void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
71 bool force = false);
72
73/// This represents a list of ValueType's that has been intern'd by
74/// a SelectionDAG. Instances of this simple value class are returned by
75/// SelectionDAG::getVTList(...).
76///
77struct SDVTList {
78 const EVT *VTs;
79 unsigned int NumVTs;
80};
81
82namespace ISD {
83
84 /// Node predicates
85
86 /// If N is a BUILD_VECTOR node whose elements are all the same constant or
87 /// undefined, return true and return the constant value in \p SplatValue.
88 bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
89
90 /// Return true if the specified node is a BUILD_VECTOR where all of the
91 /// elements are ~0 or undef.
92 bool isBuildVectorAllOnes(const SDNode *N);
93
94 /// Return true if the specified node is a BUILD_VECTOR where all of the
95 /// elements are 0 or undef.
96 bool isBuildVectorAllZeros(const SDNode *N);
97
98 /// Return true if the specified node is a BUILD_VECTOR node of all
99 /// ConstantSDNode or undef.
100 bool isBuildVectorOfConstantSDNodes(const SDNode *N);
101
102 /// Return true if the specified node is a BUILD_VECTOR node of all
103 /// ConstantFPSDNode or undef.
104 bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
105
106 /// Return true if the node has at least one operand and all operands of the
107 /// specified node are ISD::UNDEF.
108 bool allOperandsUndef(const SDNode *N);
109
110} // end namespace ISD
111
112//===----------------------------------------------------------------------===//
113/// Unlike LLVM values, Selection DAG nodes may return multiple
114/// values as the result of a computation. Many nodes return multiple values,
115/// from loads (which define a token and a return value) to ADDC (which returns
116/// a result and a carry value), to calls (which may return an arbitrary number
117/// of values).
118///
119/// As such, each use of a SelectionDAG computation must indicate the node that
120/// computes it as well as which return value to use from that node. This pair
121/// of information is represented with the SDValue value type.
122///
123class SDValue {
124 friend struct DenseMapInfo<SDValue>;
125
126 SDNode *Node = nullptr; // The node defining the value we are using.
127 unsigned ResNo = 0; // Which return value of the node we are using.
128
129public:
130 SDValue() = default;
131 SDValue(SDNode *node, unsigned resno);
132
133 /// get the index which selects a specific result in the SDNode
134 unsigned getResNo() const { return ResNo; }
135
136 /// get the SDNode which holds the desired result
137 SDNode *getNode() const { return Node; }
138
139 /// set the SDNode
140 void setNode(SDNode *N) { Node = N; }
141
142 inline SDNode *operator->() const { return Node; }
143
144 bool operator==(const SDValue &O) const {
145 return Node == O.Node && ResNo == O.ResNo;
146 }
147 bool operator!=(const SDValue &O) const {
148 return !operator==(O);
149 }
150 bool operator<(const SDValue &O) const {
151 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
152 }
153 explicit operator bool() const {
154 return Node != nullptr;
155 }
156
157 SDValue getValue(unsigned R) const {
158 return SDValue(Node, R);
159 }
160
161 /// Return true if this node is an operand of N.
162 bool isOperandOf(const SDNode *N) const;
163
164 /// Return the ValueType of the referenced return value.
165 inline EVT getValueType() const;
166
167 /// Return the simple ValueType of the referenced return value.
168 MVT getSimpleValueType() const {
169 return getValueType().getSimpleVT();
170 }
171
172 /// Returns the size of the value in bits.
173 unsigned getValueSizeInBits() const {
174 return getValueType().getSizeInBits();
175 }
176
177 unsigned getScalarValueSizeInBits() const {
178 return getValueType().getScalarType().getSizeInBits();
179 }
180
181 // Forwarding methods - These forward to the corresponding methods in SDNode.
182 inline unsigned getOpcode() const;
183 inline unsigned getNumOperands() const;
184 inline const SDValue &getOperand(unsigned i) const;
185 inline uint64_t getConstantOperandVal(unsigned i) const;
186 inline const APInt &getConstantOperandAPInt(unsigned i) const;
187 inline bool isTargetMemoryOpcode() const;
188 inline bool isTargetOpcode() const;
189 inline bool isMachineOpcode() const;
190 inline bool isUndef() const;
191 inline unsigned getMachineOpcode() const;
192 inline const DebugLoc &getDebugLoc() const;
193 inline void dump() const;
194 inline void dump(const SelectionDAG *G) const;
195 inline void dumpr() const;
196 inline void dumpr(const SelectionDAG *G) const;
197
198 /// Return true if this operand (which must be a chain) reaches the
199 /// specified operand without crossing any side-effecting instructions.
200 /// In practice, this looks through token factors and non-volatile loads.
201 /// In order to remain efficient, this only
202 /// looks a couple of nodes in, it does not do an exhaustive search.
203 bool reachesChainWithoutSideEffects(SDValue Dest,
204 unsigned Depth = 2) const;
205
206 /// Return true if there are no nodes using value ResNo of Node.
207 inline bool use_empty() const;
208
209 /// Return true if there is exactly one node using value ResNo of Node.
210 inline bool hasOneUse() const;
211};
212
213template<> struct DenseMapInfo<SDValue> {
214 static inline SDValue getEmptyKey() {
215 SDValue V;
216 V.ResNo = -1U;
217 return V;
218 }
219
220 static inline SDValue getTombstoneKey() {
221 SDValue V;
222 V.ResNo = -2U;
223 return V;
224 }
225
226 static unsigned getHashValue(const SDValue &Val) {
227 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
228 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
229 }
230
231 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
232 return LHS == RHS;
233 }
234};
235
236/// Allow casting operators to work directly on
237/// SDValues as if they were SDNode*'s.
238template<> struct simplify_type<SDValue> {
239 using SimpleType = SDNode *;
240
241 static SimpleType getSimplifiedValue(SDValue &Val) {
242 return Val.getNode();
243 }
244};
245template<> struct simplify_type<const SDValue> {
246 using SimpleType = /*const*/ SDNode *;
247
248 static SimpleType getSimplifiedValue(const SDValue &Val) {
249 return Val.getNode();
250 }
251};
252
253/// Represents a use of a SDNode. This class holds an SDValue,
254/// which records the SDNode being used and the result number, a
255/// pointer to the SDNode using the value, and Next and Prev pointers,
256/// which link together all the uses of an SDNode.
257///
258class SDUse {
259 /// Val - The value being used.
260 SDValue Val;
261 /// User - The user of this value.
262 SDNode *User = nullptr;
263 /// Prev, Next - Pointers to the uses list of the SDNode referred by
264 /// this operand.
265 SDUse **Prev = nullptr;
266 SDUse *Next = nullptr;
267
268public:
269 SDUse() = default;
270 SDUse(const SDUse &U) = delete;
271 SDUse &operator=(const SDUse &) = delete;
272
273 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
274 operator const SDValue&() const { return Val; }
275
276 /// If implicit conversion to SDValue doesn't work, the get() method returns
277 /// the SDValue.
278 const SDValue &get() const { return Val; }
279
280 /// This returns the SDNode that contains this Use.
281 SDNode *getUser() { return User; }
282
283 /// Get the next SDUse in the use list.
284 SDUse *getNext() const { return Next; }
285
286 /// Convenience function for get().getNode().
287 SDNode *getNode() const { return Val.getNode(); }
288 /// Convenience function for get().getResNo().
289 unsigned getResNo() const { return Val.getResNo(); }
290 /// Convenience function for get().getValueType().
291 EVT getValueType() const { return Val.getValueType(); }
292
293 /// Convenience function for get().operator==
294 bool operator==(const SDValue &V) const {
295 return Val == V;
296 }
297
298 /// Convenience function for get().operator!=
299 bool operator!=(const SDValue &V) const {
300 return Val != V;
301 }
302
303 /// Convenience function for get().operator<
304 bool operator<(const SDValue &V) const {
305 return Val < V;
306 }
307
308private:
309 friend class SelectionDAG;
310 friend class SDNode;
311 // TODO: unfriend HandleSDNode once we fix its operand handling.
312 friend class HandleSDNode;
313
314 void setUser(SDNode *p) { User = p; }
315
316 /// Remove this use from its existing use list, assign it the
317 /// given value, and add it to the new value's node's use list.
318 inline void set(const SDValue &V);
319 /// Like set, but only supports initializing a newly-allocated
320 /// SDUse with a non-null value.
321 inline void setInitial(const SDValue &V);
322 /// Like set, but only sets the Node portion of the value,
323 /// leaving the ResNo portion unmodified.
324 inline void setNode(SDNode *N);
325
326 void addToList(SDUse **List) {
327 Next = *List;
328 if (Next) Next->Prev = &Next;
329 Prev = List;
330 *List = this;
331 }
332
333 void removeFromList() {
334 *Prev = Next;
335 if (Next) Next->Prev = Prev;
336 }
337};
338
339/// simplify_type specializations - Allow casting operators to work directly on
340/// SDValues as if they were SDNode*'s.
341template<> struct simplify_type<SDUse> {
342 using SimpleType = SDNode *;
343
344 static SimpleType getSimplifiedValue(SDUse &Val) {
345 return Val.getNode();
346 }
347};
348
349/// These are IR-level optimization flags that may be propagated to SDNodes.
350/// TODO: This data structure should be shared by the IR optimizer and the
351/// the backend.
352struct SDNodeFlags {
353private:
354 // This bit is used to determine if the flags are in a defined state.
355 // Flag bits can only be masked out during intersection if the masking flags
356 // are defined.
357 bool AnyDefined : 1;
358
359 bool NoUnsignedWrap : 1;
360 bool NoSignedWrap : 1;
361 bool Exact : 1;
362 bool NoNaNs : 1;
363 bool NoInfs : 1;
364 bool NoSignedZeros : 1;
365 bool AllowReciprocal : 1;
366 bool VectorReduction : 1;
367 bool AllowContract : 1;
368 bool ApproximateFuncs : 1;
369 bool AllowReassociation : 1;
370
371 // We assume instructions do not raise floating-point exceptions by default,
372 // and only those marked explicitly may do so. We could choose to represent
373 // this via a positive "FPExcept" flags like on the MI level, but having a
374 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
375 // intersection logic more straightforward.
376 bool NoFPExcept : 1;
377
378public:
379 /// Default constructor turns off all optimization flags.
380 SDNodeFlags()
381 : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
382 Exact(false), NoNaNs(false), NoInfs(false),
383 NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
384 AllowContract(false), ApproximateFuncs(false),
385 AllowReassociation(false), NoFPExcept(true) {}
386
387 /// Propagate the fast-math-flags from an IR FPMathOperator.
388 void copyFMF(const FPMathOperator &FPMO) {
389 setNoNaNs(FPMO.hasNoNaNs());
390 setNoInfs(FPMO.hasNoInfs());
391 setNoSignedZeros(FPMO.hasNoSignedZeros());
392 setAllowReciprocal(FPMO.hasAllowReciprocal());
393 setAllowContract(FPMO.hasAllowContract());
394 setApproximateFuncs(FPMO.hasApproxFunc());
395 setAllowReassociation(FPMO.hasAllowReassoc());
396 }
397
398 /// Sets the state of the flags to the defined state.
399 void setDefined() { AnyDefined = true; }
400 /// Returns true if the flags are in a defined state.
401 bool isDefined() const { return AnyDefined; }
402
403 // These are mutators for each flag.
404 void setNoUnsignedWrap(bool b) {
405 setDefined();
406 NoUnsignedWrap = b;
407 }
408 void setNoSignedWrap(bool b) {
409 setDefined();
410 NoSignedWrap = b;
411 }
412 void setExact(bool b) {
413 setDefined();
414 Exact = b;
415 }
416 void setNoNaNs(bool b) {
417 setDefined();
418 NoNaNs = b;
419 }
420 void setNoInfs(bool b) {
421 setDefined();
422 NoInfs = b;
423 }
424 void setNoSignedZeros(bool b) {
425 setDefined();
426 NoSignedZeros = b;
427 }
428 void setAllowReciprocal(bool b) {
429 setDefined();
430 AllowReciprocal = b;
431 }
432 void setVectorReduction(bool b) {
433 setDefined();
434 VectorReduction = b;
435 }
436 void setAllowContract(bool b) {
437 setDefined();
438 AllowContract = b;
439 }
440 void setApproximateFuncs(bool b) {
441 setDefined();
442 ApproximateFuncs = b;
443 }
444 void setAllowReassociation(bool b) {
445 setDefined();
446 AllowReassociation = b;
447 }
448 void setFPExcept(bool b) {
449 setDefined();
450 NoFPExcept = !b;
451 }
452
453 // These are accessors for each flag.
454 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
455 bool hasNoSignedWrap() const { return NoSignedWrap; }
456 bool hasExact() const { return Exact; }
457 bool hasNoNaNs() const { return NoNaNs; }
458 bool hasNoInfs() const { return NoInfs; }
459 bool hasNoSignedZeros() const { return NoSignedZeros; }
460 bool hasAllowReciprocal() const { return AllowReciprocal; }
461 bool hasVectorReduction() const { return VectorReduction; }
462 bool hasAllowContract() const { return AllowContract; }
463 bool hasApproximateFuncs() const { return ApproximateFuncs; }
464 bool hasAllowReassociation() const { return AllowReassociation; }
465 bool hasFPExcept() const { return !NoFPExcept; }
466
467 bool isFast() const {
468 return NoSignedZeros && AllowReciprocal && NoNaNs && NoInfs && NoFPExcept &&
469 AllowContract && ApproximateFuncs && AllowReassociation;
470 }
471
472 /// Clear any flags in this flag set that aren't also set in Flags.
473 /// If the given Flags are undefined then don't do anything.
474 void intersectWith(const SDNodeFlags Flags) {
475 if (!Flags.isDefined())
476 return;
477 NoUnsignedWrap &= Flags.NoUnsignedWrap;
478 NoSignedWrap &= Flags.NoSignedWrap;
479 Exact &= Flags.Exact;
480 NoNaNs &= Flags.NoNaNs;
481 NoInfs &= Flags.NoInfs;
482 NoSignedZeros &= Flags.NoSignedZeros;
483 AllowReciprocal &= Flags.AllowReciprocal;
484 VectorReduction &= Flags.VectorReduction;
485 AllowContract &= Flags.AllowContract;
486 ApproximateFuncs &= Flags.ApproximateFuncs;
487 AllowReassociation &= Flags.AllowReassociation;
488 NoFPExcept &= Flags.NoFPExcept;
489 }
490};
491
492/// Represents one node in the SelectionDAG.
493///
494class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
495private:
496 /// The operation that this node performs.
497 int16_t NodeType;
498
499protected:
500 // We define a set of mini-helper classes to help us interpret the bits in our
501 // SubclassData. These are designed to fit within a uint16_t so they pack
502 // with NodeType.
503
504#if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__))
505// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
506// and give the `pack` pragma push semantics.
507#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
508#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
509#else
510#define BEGIN_TWO_BYTE_PACK()
511#define END_TWO_BYTE_PACK()
512#endif
513
514BEGIN_TWO_BYTE_PACK()
515 class SDNodeBitfields {
516 friend class SDNode;
517 friend class MemIntrinsicSDNode;
518 friend class MemSDNode;
519 friend class SelectionDAG;
520
521 uint16_t HasDebugValue : 1;
522 uint16_t IsMemIntrinsic : 1;
523 uint16_t IsDivergent : 1;
524 };
525 enum { NumSDNodeBits = 3 };
526
527 class ConstantSDNodeBitfields {
528 friend class ConstantSDNode;
529
530 uint16_t : NumSDNodeBits;
531
532 uint16_t IsOpaque : 1;
533 };
534
535 class MemSDNodeBitfields {
536 friend class MemSDNode;
537 friend class MemIntrinsicSDNode;
538 friend class AtomicSDNode;
539
540 uint16_t : NumSDNodeBits;
541
542 uint16_t IsVolatile : 1;
543 uint16_t IsNonTemporal : 1;
544 uint16_t IsDereferenceable : 1;
545 uint16_t IsInvariant : 1;
546 };
547 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
548
549 class LSBaseSDNodeBitfields {
550 friend class LSBaseSDNode;
551 friend class MaskedGatherScatterSDNode;
552
553 uint16_t : NumMemSDNodeBits;
554
555 // This storage is shared between disparate class hierarchies to hold an
556 // enumeration specific to the class hierarchy in use.
557 // LSBaseSDNode => enum ISD::MemIndexedMode
558 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
559 uint16_t AddressingMode : 3;
560 };
561 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
562
563 class LoadSDNodeBitfields {
564 friend class LoadSDNode;
565 friend class MaskedLoadSDNode;
566
567 uint16_t : NumLSBaseSDNodeBits;
568
569 uint16_t ExtTy : 2; // enum ISD::LoadExtType
570 uint16_t IsExpanding : 1;
571 };
572
573 class StoreSDNodeBitfields {
574 friend class StoreSDNode;
575 friend class MaskedStoreSDNode;
576
577 uint16_t : NumLSBaseSDNodeBits;
578
579 uint16_t IsTruncating : 1;
580 uint16_t IsCompressing : 1;
581 };
582
583 union {
584 char RawSDNodeBits[sizeof(uint16_t)];
585 SDNodeBitfields SDNodeBits;
586 ConstantSDNodeBitfields ConstantSDNodeBits;
587 MemSDNodeBitfields MemSDNodeBits;
588 LSBaseSDNodeBitfields LSBaseSDNodeBits;
589 LoadSDNodeBitfields LoadSDNodeBits;
590 StoreSDNodeBitfields StoreSDNodeBits;
591 };
592END_TWO_BYTE_PACK()
593#undef BEGIN_TWO_BYTE_PACK
594#undef END_TWO_BYTE_PACK
595
596 // RawSDNodeBits must cover the entirety of the union. This means that all of
597 // the union's members must have size <= RawSDNodeBits. We write the RHS as
598 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
599 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
600 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
601 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
602 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
603 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
604 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
605
606private:
607 friend class SelectionDAG;
608 // TODO: unfriend HandleSDNode once we fix its operand handling.
609 friend class HandleSDNode;
610
611 /// Unique id per SDNode in the DAG.
612 int NodeId = -1;
613
614 /// The values that are used by this operation.
615 SDUse *OperandList = nullptr;
616
617 /// The types of the values this node defines. SDNode's may
618 /// define multiple values simultaneously.
619 const EVT *ValueList;
620
621 /// List of uses for this SDNode.
622 SDUse *UseList = nullptr;
623
624 /// The number of entries in the Operand/Value list.
625 unsigned short NumOperands = 0;
626 unsigned short NumValues;
627
628 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
629 // original LLVM instructions.
630 // This is used for turning off scheduling, because we'll forgo
631 // the normal scheduling algorithms and output the instructions according to
632 // this ordering.
633 unsigned IROrder;
634
635 /// Source line information.
636 DebugLoc debugLoc;
637
638 /// Return a pointer to the specified value type.
639 static const EVT *getValueTypeList(EVT VT);
640
641 SDNodeFlags Flags;
642
643public:
644 /// Unique and persistent id per SDNode in the DAG.
645 /// Used for debug printing.
646 uint16_t PersistentId;
647
648 //===--------------------------------------------------------------------===//
649 // Accessors
650 //
651
652 /// Return the SelectionDAG opcode value for this node. For
653 /// pre-isel nodes (those for which isMachineOpcode returns false), these
654 /// are the opcode values in the ISD and <target>ISD namespaces. For
655 /// post-isel opcodes, see getMachineOpcode.
656 unsigned getOpcode() const { return (unsigned short)NodeType; }
657
658 /// Test if this node has a target-specific opcode (in the
659 /// \<target\>ISD namespace).
660 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
661
662 /// Test if this node has a target-specific
663 /// memory-referencing opcode (in the \<target\>ISD namespace and
664 /// greater than FIRST_TARGET_MEMORY_OPCODE).
665 bool isTargetMemoryOpcode() const {
666 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
667 }
668
669 /// Return true if the type of the node type undefined.
670 bool isUndef() const { return NodeType == ISD::UNDEF; }
671
672 /// Test if this node is a memory intrinsic (with valid pointer information).
673 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
674 /// non-memory intrinsics (with chains) that are not really instances of
675 /// MemSDNode. For such nodes, we need some extra state to determine the
676 /// proper classof relationship.
677 bool isMemIntrinsic() const {
678 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
679 NodeType == ISD::INTRINSIC_VOID) &&
680 SDNodeBits.IsMemIntrinsic;
681 }
682
683 /// Test if this node is a strict floating point pseudo-op.
684 bool isStrictFPOpcode() {
685 switch (NodeType) {
686 default:
687 return false;
688 case ISD::STRICT_FADD:
689 case ISD::STRICT_FSUB:
690 case ISD::STRICT_FMUL:
691 case ISD::STRICT_FDIV:
692 case ISD::STRICT_FREM:
693 case ISD::STRICT_FMA:
694 case ISD::STRICT_FSQRT:
695 case ISD::STRICT_FPOW:
696 case ISD::STRICT_FPOWI:
697 case ISD::STRICT_FSIN:
698 case ISD::STRICT_FCOS:
699 case ISD::STRICT_FEXP:
700 case ISD::STRICT_FEXP2:
701 case ISD::STRICT_FLOG:
702 case ISD::STRICT_FLOG10:
703 case ISD::STRICT_FLOG2:
704 case ISD::STRICT_LRINT:
705 case ISD::STRICT_LLRINT:
706 case ISD::STRICT_FRINT:
707 case ISD::STRICT_FNEARBYINT:
708 case ISD::STRICT_FMAXNUM:
709 case ISD::STRICT_FMINNUM:
710 case ISD::STRICT_FCEIL:
711 case ISD::STRICT_FFLOOR:
712 case ISD::STRICT_LROUND:
713 case ISD::STRICT_LLROUND:
714 case ISD::STRICT_FROUND:
715 case ISD::STRICT_FTRUNC:
716 case ISD::STRICT_FP_TO_SINT:
717 case ISD::STRICT_FP_TO_UINT:
718 case ISD::STRICT_FP_ROUND:
719 case ISD::STRICT_FP_EXTEND:
720 return true;
721 }
722 }
723
724 /// Test if this node has a post-isel opcode, directly
725 /// corresponding to a MachineInstr opcode.
726 bool isMachineOpcode() const { return NodeType < 0; }
727
728 /// This may only be called if isMachineOpcode returns
729 /// true. It returns the MachineInstr opcode value that the node's opcode
730 /// corresponds to.
731 unsigned getMachineOpcode() const {
732 assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 732, __PRETTY_FUNCTION__))
;
733 return ~NodeType;
734 }
735
736 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
737 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
738
739 bool isDivergent() const { return SDNodeBits.IsDivergent; }
740
741 /// Return true if there are no uses of this node.
742 bool use_empty() const { return UseList == nullptr; }
743
744 /// Return true if there is exactly one use of this node.
745 bool hasOneUse() const {
746 return !use_empty() && std::next(use_begin()) == use_end();
747 }
748
749 /// Return the number of uses of this node. This method takes
750 /// time proportional to the number of uses.
751 size_t use_size() const { return std::distance(use_begin(), use_end()); }
752
753 /// Return the unique node id.
754 int getNodeId() const { return NodeId; }
755
756 /// Set unique node id.
757 void setNodeId(int Id) { NodeId = Id; }
758
759 /// Return the node ordering.
760 unsigned getIROrder() const { return IROrder; }
761
762 /// Set the node ordering.
763 void setIROrder(unsigned Order) { IROrder = Order; }
764
765 /// Return the source location info.
766 const DebugLoc &getDebugLoc() const { return debugLoc; }
767
768 /// Set source location info. Try to avoid this, putting
769 /// it in the constructor is preferable.
770 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
771
772 /// This class provides iterator support for SDUse
773 /// operands that use a specific SDNode.
774 class use_iterator
775 : public std::iterator<std::forward_iterator_tag, SDUse, ptrdiff_t> {
776 friend class SDNode;
777
778 SDUse *Op = nullptr;
779
780 explicit use_iterator(SDUse *op) : Op(op) {}
781
782 public:
783 using reference = std::iterator<std::forward_iterator_tag,
784 SDUse, ptrdiff_t>::reference;
785 using pointer = std::iterator<std::forward_iterator_tag,
786 SDUse, ptrdiff_t>::pointer;
787
788 use_iterator() = default;
789 use_iterator(const use_iterator &I) : Op(I.Op) {}
790
791 bool operator==(const use_iterator &x) const {
792 return Op == x.Op;
793 }
794 bool operator!=(const use_iterator &x) const {
795 return !operator==(x);
796 }
797
798 /// Return true if this iterator is at the end of uses list.
799 bool atEnd() const { return Op == nullptr; }
800
801 // Iterator traversal: forward iteration only.
802 use_iterator &operator++() { // Preincrement
803 assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 803, __PRETTY_FUNCTION__))
;
804 Op = Op->getNext();
805 return *this;
806 }
807
808 use_iterator operator++(int) { // Postincrement
809 use_iterator tmp = *this; ++*this; return tmp;
810 }
811
812 /// Retrieve a pointer to the current user node.
813 SDNode *operator*() const {
814 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 814, __PRETTY_FUNCTION__))
;
815 return Op->getUser();
816 }
817
818 SDNode *operator->() const { return operator*(); }
819
820 SDUse &getUse() const { return *Op; }
821
822 /// Retrieve the operand # of this use in its user.
823 unsigned getOperandNo() const {
824 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 824, __PRETTY_FUNCTION__))
;
825 return (unsigned)(Op - Op->getUser()->OperandList);
826 }
827 };
828
829 /// Provide iteration support to walk over all uses of an SDNode.
830 use_iterator use_begin() const {
831 return use_iterator(UseList);
832 }
833
834 static use_iterator use_end() { return use_iterator(nullptr); }
835
836 inline iterator_range<use_iterator> uses() {
837 return make_range(use_begin(), use_end());
838 }
839 inline iterator_range<use_iterator> uses() const {
840 return make_range(use_begin(), use_end());
841 }
842
843 /// Return true if there are exactly NUSES uses of the indicated value.
844 /// This method ignores uses of other values defined by this operation.
845 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
846
847 /// Return true if there are any use of the indicated value.
848 /// This method ignores uses of other values defined by this operation.
849 bool hasAnyUseOfValue(unsigned Value) const;
850
851 /// Return true if this node is the only use of N.
852 bool isOnlyUserOf(const SDNode *N) const;
853
854 /// Return true if this node is an operand of N.
855 bool isOperandOf(const SDNode *N) const;
856
857 /// Return true if this node is a predecessor of N.
858 /// NOTE: Implemented on top of hasPredecessor and every bit as
859 /// expensive. Use carefully.
860 bool isPredecessorOf(const SDNode *N) const {
861 return N->hasPredecessor(this);
862 }
863
864 /// Return true if N is a predecessor of this node.
865 /// N is either an operand of this node, or can be reached by recursively
866 /// traversing up the operands.
867 /// NOTE: This is an expensive method. Use it carefully.
868 bool hasPredecessor(const SDNode *N) const;
869
870 /// Returns true if N is a predecessor of any node in Worklist. This
871 /// helper keeps Visited and Worklist sets externally to allow unions
872 /// searches to be performed in parallel, caching of results across
873 /// queries and incremental addition to Worklist. Stops early if N is
874 /// found but will resume. Remember to clear Visited and Worklists
875 /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
876 /// giving up. The TopologicalPrune flag signals that positive NodeIds are
877 /// topologically ordered (Operands have strictly smaller node id) and search
878 /// can be pruned leveraging this.
879 static bool hasPredecessorHelper(const SDNode *N,
880 SmallPtrSetImpl<const SDNode *> &Visited,
881 SmallVectorImpl<const SDNode *> &Worklist,
882 unsigned int MaxSteps = 0,
883 bool TopologicalPrune = false) {
884 SmallVector<const SDNode *, 8> DeferredNodes;
885 if (Visited.count(N))
886 return true;
887
888 // Node Id's are assigned in three places: As a topological
889 // ordering (> 0), during legalization (results in values set to
890 // 0), new nodes (set to -1). If N has a topolgical id then we
891 // know that all nodes with ids smaller than it cannot be
892 // successors and we need not check them. Filter out all node
893 // that can't be matches. We add them to the worklist before exit
894 // in case of multiple calls. Note that during selection the topological id
895 // may be violated if a node's predecessor is selected before it. We mark
896 // this at selection negating the id of unselected successors and
897 // restricting topological pruning to positive ids.
898
899 int NId = N->getNodeId();
900 // If we Invalidated the Id, reconstruct original NId.
901 if (NId < -1)
902 NId = -(NId + 1);
903
904 bool Found = false;
905 while (!Worklist.empty()) {
906 const SDNode *M = Worklist.pop_back_val();
907 int MId = M->getNodeId();
908 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
909 (MId > 0) && (MId < NId)) {
910 DeferredNodes.push_back(M);
911 continue;
912 }
913 for (const SDValue &OpV : M->op_values()) {
914 SDNode *Op = OpV.getNode();
915 if (Visited.insert(Op).second)
916 Worklist.push_back(Op);
917 if (Op == N)
918 Found = true;
919 }
920 if (Found)
921 break;
922 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
923 break;
924 }
925 // Push deferred nodes back on worklist.
926 Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
927 // If we bailed early, conservatively return found.
928 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
929 return true;
930 return Found;
931 }
932
933 /// Return true if all the users of N are contained in Nodes.
934 /// NOTE: Requires at least one match, but doesn't require them all.
935 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
936
937 /// Return the number of values used by this operation.
938 unsigned getNumOperands() const { return NumOperands; }
939
940 /// Return the maximum number of operands that a SDNode can hold.
941 static constexpr size_t getMaxNumOperands() {
942 return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
943 }
944
945 /// Helper method returns the integer value of a ConstantSDNode operand.
946 inline uint64_t getConstantOperandVal(unsigned Num) const;
947
948 /// Helper method returns the APInt of a ConstantSDNode operand.
949 inline const APInt &getConstantOperandAPInt(unsigned Num) const;
950
951 const SDValue &getOperand(unsigned Num) const {
952 assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 952, __PRETTY_FUNCTION__))
;
953 return OperandList[Num];
954 }
955
956 using op_iterator = SDUse *;
957
958 op_iterator op_begin() const { return OperandList; }
959 op_iterator op_end() const { return OperandList+NumOperands; }
960 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
961
962 /// Iterator for directly iterating over the operand SDValue's.
963 struct value_op_iterator
964 : iterator_adaptor_base<value_op_iterator, op_iterator,
965 std::random_access_iterator_tag, SDValue,
966 ptrdiff_t, value_op_iterator *,
967 value_op_iterator *> {
968 explicit value_op_iterator(SDUse *U = nullptr)
969 : iterator_adaptor_base(U) {}
970
971 const SDValue &operator*() const { return I->get(); }
972 };
973
974 iterator_range<value_op_iterator> op_values() const {
975 return make_range(value_op_iterator(op_begin()),
976 value_op_iterator(op_end()));
977 }
978
979 SDVTList getVTList() const {
980 SDVTList X = { ValueList, NumValues };
981 return X;
982 }
983
984 /// If this node has a glue operand, return the node
985 /// to which the glue operand points. Otherwise return NULL.
986 SDNode *getGluedNode() const {
987 if (getNumOperands() != 0 &&
988 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
989 return getOperand(getNumOperands()-1).getNode();
990 return nullptr;
991 }
992
993 /// If this node has a glue value with a user, return
994 /// the user (there is at most one). Otherwise return NULL.
995 SDNode *getGluedUser() const {
996 for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
997 if (UI.getUse().get().getValueType() == MVT::Glue)
998 return *UI;
999 return nullptr;
1000 }
1001
1002 const SDNodeFlags getFlags() const { return Flags; }
1003 void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
1004 bool isFast() { return Flags.isFast(); }
1005
1006 /// Clear any flags in this node that aren't also set in Flags.
1007 /// If Flags is not in a defined state then this has no effect.
1008 void intersectFlagsWith(const SDNodeFlags Flags);
1009
1010 /// Return the number of values defined/returned by this operator.
1011 unsigned getNumValues() const { return NumValues; }
1012
1013 /// Return the type of a specified result.
1014 EVT getValueType(unsigned ResNo) const {
1015 assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ?
static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1015, __PRETTY_FUNCTION__))
;
1016 return ValueList[ResNo];
1017 }
1018
1019 /// Return the type of a specified result as a simple type.
1020 MVT getSimpleValueType(unsigned ResNo) const {
1021 return getValueType(ResNo).getSimpleVT();
1022 }
1023
1024 /// Returns MVT::getSizeInBits(getValueType(ResNo)).
1025 unsigned getValueSizeInBits(unsigned ResNo) const {
1026 return getValueType(ResNo).getSizeInBits();
1027 }
1028
1029 using value_iterator = const EVT *;
1030
1031 value_iterator value_begin() const { return ValueList; }
1032 value_iterator value_end() const { return ValueList+NumValues; }
1033
1034 /// Return the opcode of this operation for printing.
1035 std::string getOperationName(const SelectionDAG *G = nullptr) const;
1036 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1037 void print_types(raw_ostream &OS, const SelectionDAG *G) const;
1038 void print_details(raw_ostream &OS, const SelectionDAG *G) const;
1039 void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1040 void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1041
1042 /// Print a SelectionDAG node and all children down to
1043 /// the leaves. The given SelectionDAG allows target-specific nodes
1044 /// to be printed in human-readable form. Unlike printr, this will
1045 /// print the whole DAG, including children that appear multiple
1046 /// times.
1047 ///
1048 void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;
1049
1050 /// Print a SelectionDAG node and children up to
1051 /// depth "depth." The given SelectionDAG allows target-specific
1052 /// nodes to be printed in human-readable form. Unlike printr, this
1053 /// will print children that appear multiple times wherever they are
1054 /// used.
1055 ///
1056 void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
1057 unsigned depth = 100) const;
1058
1059 /// Dump this node, for debugging.
1060 void dump() const;
1061
1062 /// Dump (recursively) this node and its use-def subgraph.
1063 void dumpr() const;
1064
1065 /// Dump this node, for debugging.
1066 /// The given SelectionDAG allows target-specific nodes to be printed
1067 /// in human-readable form.
1068 void dump(const SelectionDAG *G) const;
1069
1070 /// Dump (recursively) this node and its use-def subgraph.
1071 /// The given SelectionDAG allows target-specific nodes to be printed
1072 /// in human-readable form.
1073 void dumpr(const SelectionDAG *G) const;
1074
1075 /// printrFull to dbgs(). The given SelectionDAG allows
1076 /// target-specific nodes to be printed in human-readable form.
1077 /// Unlike dumpr, this will print the whole DAG, including children
1078 /// that appear multiple times.
1079 void dumprFull(const SelectionDAG *G = nullptr) const;
1080
1081 /// printrWithDepth to dbgs(). The given
1082 /// SelectionDAG allows target-specific nodes to be printed in
1083 /// human-readable form. Unlike dumpr, this will print children
1084 /// that appear multiple times wherever they are used.
1085 ///
1086 void dumprWithDepth(const SelectionDAG *G = nullptr,
1087 unsigned depth = 100) const;
1088
1089 /// Gather unique data for the node.
1090 void Profile(FoldingSetNodeID &ID) const;
1091
1092 /// This method should only be used by the SDUse class.
1093 void addUse(SDUse &U) { U.addToList(&UseList); }
1094
1095protected:
1096 static SDVTList getSDVTList(EVT VT) {
1097 SDVTList Ret = { getValueTypeList(VT), 1 };
1098 return Ret;
1099 }
1100
1101 /// Create an SDNode.
1102 ///
1103 /// SDNodes are created without any operands, and never own the operand
1104 /// storage. To add operands, see SelectionDAG::createOperands.
1105 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1106 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1107 IROrder(Order), debugLoc(std::move(dl)) {
1108 memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
1109 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1109, __PRETTY_FUNCTION__))
;
1110 assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1111, __PRETTY_FUNCTION__))
1111 "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1111, __PRETTY_FUNCTION__))
;
1112 }
1113
1114 /// Release the operands and set this node to have zero operands.
1115 void DropOperands();
1116};
1117
1118/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1119/// into SDNode creation functions.
1120/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1121/// from the original Instruction, and IROrder is the ordinal position of
1122/// the instruction.
1123/// When an SDNode is created after the DAG is being built, both DebugLoc and
1124/// the IROrder are propagated from the original SDNode.
1125/// So SDLoc class provides two constructors besides the default one, one to
1126/// be used by the DAGBuilder, the other to be used by others.
1127class SDLoc {
1128private:
1129 DebugLoc DL;
1130 int IROrder = 0;
1131
1132public:
1133 SDLoc() = default;
1134 SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
1135 SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
1136 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1137 assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void
> (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1137, __PRETTY_FUNCTION__))
;
1138 if (I)
1139 DL = I->getDebugLoc();
1140 }
1141
1142 unsigned getIROrder() const { return IROrder; }
1143 const DebugLoc &getDebugLoc() const { return DL; }
1144};
1145
1146// Define inline functions from the SDValue class.
1147
1148inline SDValue::SDValue(SDNode *node, unsigned resno)
1149 : Node(node), ResNo(resno) {
1150 // Explicitly check for !ResNo to avoid use-after-free, because there are
1151 // callers that use SDValue(N, 0) with a deleted N to indicate successful
1152 // combines.
1153 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1154, __PRETTY_FUNCTION__))
1154 "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1154, __PRETTY_FUNCTION__))
;
1155 assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1155, __PRETTY_FUNCTION__))
;
1156}
1157
1158inline unsigned SDValue::getOpcode() const {
1159 return Node->getOpcode();
1160}
1161
1162inline EVT SDValue::getValueType() const {
1163 return Node->getValueType(ResNo);
1164}
1165
1166inline unsigned SDValue::getNumOperands() const {
1167 return Node->getNumOperands();
1168}
1169
1170inline const SDValue &SDValue::getOperand(unsigned i) const {
1171 return Node->getOperand(i);
1172}
1173
1174inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
1175 return Node->getConstantOperandVal(i);
1176}
1177
1178inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
1179 return Node->getConstantOperandAPInt(i);
1180}
1181
1182inline bool SDValue::isTargetOpcode() const {
1183 return Node->isTargetOpcode();
1184}
1185
1186inline bool SDValue::isTargetMemoryOpcode() const {
1187 return Node->isTargetMemoryOpcode();
1188}
1189
1190inline bool SDValue::isMachineOpcode() const {
1191 return Node->isMachineOpcode();
7
Called C++ object pointer is null
1192}
1193
1194inline unsigned SDValue::getMachineOpcode() const {
1195 return Node->getMachineOpcode();
1196}
1197
1198inline bool SDValue::isUndef() const {
1199 return Node->isUndef();
1200}
1201
1202inline bool SDValue::use_empty() const {
1203 return !Node->hasAnyUseOfValue(ResNo);
1204}
1205
1206inline bool SDValue::hasOneUse() const {
1207 return Node->hasNUsesOfValue(1, ResNo);
1208}
1209
1210inline const DebugLoc &SDValue::getDebugLoc() const {
1211 return Node->getDebugLoc();
1212}
1213
1214inline void SDValue::dump() const {
1215 return Node->dump();
1216}
1217
1218inline void SDValue::dump(const SelectionDAG *G) const {
1219 return Node->dump(G);
1220}
1221
1222inline void SDValue::dumpr() const {
1223 return Node->dumpr();
1224}
1225
1226inline void SDValue::dumpr(const SelectionDAG *G) const {
1227 return Node->dumpr(G);
1228}
1229
1230// Define inline functions from the SDUse class.
1231
1232inline void SDUse::set(const SDValue &V) {
1233 if (Val.getNode()) removeFromList();
1234 Val = V;
1235 if (V.getNode()) V.getNode()->addUse(*this);
1236}
1237
1238inline void SDUse::setInitial(const SDValue &V) {
1239 Val = V;
1240 V.getNode()->addUse(*this);
1241}
1242
1243inline void SDUse::setNode(SDNode *N) {
1244 if (Val.getNode()) removeFromList();
1245 Val.setNode(N);
1246 if (N) N->addUse(*this);
1247}
1248
1249/// This class is used to form a handle around another node that
1250/// is persistent and is updated across invocations of replaceAllUsesWith on its
1251/// operand. This node should be directly created by end-users and not added to
1252/// the AllNodes list.
1253class HandleSDNode : public SDNode {
1254 SDUse Op;
1255
1256public:
1257 explicit HandleSDNode(SDValue X)
1258 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
1259 // HandleSDNodes are never inserted into the DAG, so they won't be
1260 // auto-numbered. Use ID 65535 as a sentinel.
1261 PersistentId = 0xffff;
1262
1263 // Manually set up the operand list. This node type is special in that it's
1264 // always stack allocated and SelectionDAG does not manage its operands.
1265 // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
1266 // be so special.
1267 Op.setUser(this);
1268 Op.setInitial(X);
1269 NumOperands = 1;
1270 OperandList = &Op;
1271 }
1272 ~HandleSDNode();
1273
1274 const SDValue &getValue() const { return Op; }
1275};
1276
1277class AddrSpaceCastSDNode : public SDNode {
1278private:
1279 unsigned SrcAddrSpace;
1280 unsigned DestAddrSpace;
1281
1282public:
1283 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1284 unsigned SrcAS, unsigned DestAS);
1285
1286 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
1287 unsigned getDestAddressSpace() const { return DestAddrSpace; }
1288
1289 static bool classof(const SDNode *N) {
1290 return N->getOpcode() == ISD::ADDRSPACECAST;
1291 }
1292};
1293
1294/// This is an abstract virtual class for memory operations.
1295class MemSDNode : public SDNode {
1296private:
1297 // VT of in-memory value.
1298 EVT MemoryVT;
1299
1300protected:
1301 /// Memory reference information.
1302 MachineMemOperand *MMO;
1303
1304public:
1305 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1306 EVT memvt, MachineMemOperand *MMO);
1307
1308 bool readMem() const { return MMO->isLoad(); }
1309 bool writeMem() const { return MMO->isStore(); }
1310
1311 /// Returns alignment and volatility of the memory access
1312 unsigned getOriginalAlignment() const {
1313 return MMO->getBaseAlignment();
1314 }
1315 unsigned getAlignment() const {
1316 return MMO->getAlignment();
1317 }
1318
1319 /// Return the SubclassData value, without HasDebugValue. This contains an
1320 /// encoding of the volatile flag, as well as bits used by subclasses. This
1321 /// function should only be used to compute a FoldingSetNodeID value.
1322 /// The HasDebugValue bit is masked out because CSE map needs to match
1323 /// nodes with debug info with nodes without debug info. Same is about
1324 /// isDivergent bit.
1325 unsigned getRawSubclassData() const {
1326 uint16_t Data;
1327 union {
1328 char RawSDNodeBits[sizeof(uint16_t)];
1329 SDNodeBitfields SDNodeBits;
1330 };
1331 memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
1332 SDNodeBits.HasDebugValue = 0;
1333 SDNodeBits.IsDivergent = false;
1334 memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
1335 return Data;
1336 }
1337
1338 bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
1339 bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
1340 bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
1341 bool isInvariant() const { return MemSDNodeBits.IsInvariant; }
1342
1343 // Returns the offset from the location of the access.
1344 int64_t getSrcValueOffset() const { return MMO->getOffset(); }
1345
1346 /// Returns the AA info that describes the dereference.
1347 AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }
1348
1349 /// Returns the Ranges that describes the dereference.
1350 const MDNode *getRanges() const { return MMO->getRanges(); }
1351
1352 /// Returns the synchronization scope ID for this memory operation.
1353 SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }
1354
1355 /// Return the atomic ordering requirements for this memory operation. For
1356 /// cmpxchg atomic operations, return the atomic ordering requirements when
1357 /// store occurs.
1358 AtomicOrdering getOrdering() const { return MMO->getOrdering(); }
1359
1360 /// Return true if the memory operation ordering is Unordered or higher.
1361 bool isAtomic() const { return MMO->isAtomic(); }
1362
1363 /// Returns true if the memory operation doesn't imply any ordering
1364 /// constraints on surrounding memory operations beyond the normal memory
1365 /// aliasing rules.
1366 bool isUnordered() const { return MMO->isUnordered(); }
1367
1368 /// Returns true if the memory operation is neither atomic or volatile.
1369 bool isSimple() const { return !isAtomic() && !isVolatile(); }
1370
1371 /// Return the type of the in-memory value.
1372 EVT getMemoryVT() const { return MemoryVT; }
1373
1374 /// Return a MachineMemOperand object describing the memory
1375 /// reference performed by operation.
1376 MachineMemOperand *getMemOperand() const { return MMO; }
1377
1378 const MachinePointerInfo &getPointerInfo() const {
1379 return MMO->getPointerInfo();
1380 }
1381
1382 /// Return the address space for the associated pointer
1383 unsigned getAddressSpace() const {
1384 return getPointerInfo().getAddrSpace();
1385 }
1386
1387 /// Update this MemSDNode's MachineMemOperand information
1388 /// to reflect the alignment of NewMMO, if it has a greater alignment.
1389 /// This must only be used when the new alignment applies to all users of
1390 /// this MachineMemOperand.
1391 void refineAlignment(const MachineMemOperand *NewMMO) {
1392 MMO->refineAlignment(NewMMO);
1393 }
1394
1395 const SDValue &getChain() const { return getOperand(0); }
1396 const SDValue &getBasePtr() const {
1397 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1398 }
1399
1400 // Methods to support isa and dyn_cast
1401 static bool classof(const SDNode *N) {
1402 // For some targets, we lower some target intrinsics to a MemIntrinsicNode
1403 // with either an intrinsic or a target opcode.
1404 return N->getOpcode() == ISD::LOAD ||
1405 N->getOpcode() == ISD::STORE ||
1406 N->getOpcode() == ISD::PREFETCH ||
1407 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1408 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1409 N->getOpcode() == ISD::ATOMIC_SWAP ||
1410 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1411 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1412 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1413 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1414 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1415 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1416 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1417 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1418 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1419 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1420 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1421 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1422 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1423 N->getOpcode() == ISD::ATOMIC_LOAD ||
1424 N->getOpcode() == ISD::ATOMIC_STORE ||
1425 N->getOpcode() == ISD::MLOAD ||
1426 N->getOpcode() == ISD::MSTORE ||
1427 N->getOpcode() == ISD::MGATHER ||
1428 N->getOpcode() == ISD::MSCATTER ||
1429 N->isMemIntrinsic() ||
1430 N->isTargetMemoryOpcode();
1431 }
1432};
1433
1434/// This is an SDNode representing atomic operations.
1435class AtomicSDNode : public MemSDNode {
1436public:
1437 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
1438 EVT MemVT, MachineMemOperand *MMO)
1439 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
1440 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1441, __PRETTY_FUNCTION__))
1441 MMO->isAtomic()) && "then why are we using an AtomicSDNode?")((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1441, __PRETTY_FUNCTION__))
;
1442 }
1443
1444 const SDValue &getBasePtr() const { return getOperand(1); }
1445 const SDValue &getVal() const { return getOperand(2); }
1446
1447 /// Returns true if this SDNode represents cmpxchg atomic operation, false
1448 /// otherwise.
1449 bool isCompareAndSwap() const {
1450 unsigned Op = getOpcode();
1451 return Op == ISD::ATOMIC_CMP_SWAP ||
1452 Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
1453 }
1454
1455 /// For cmpxchg atomic operations, return the atomic ordering requirements
1456 /// when store does not occur.
1457 AtomicOrdering getFailureOrdering() const {
1458 assert(isCompareAndSwap() && "Must be cmpxchg operation")((isCompareAndSwap() && "Must be cmpxchg operation") ?
static_cast<void> (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1458, __PRETTY_FUNCTION__))
;
1459 return MMO->getFailureOrdering();
1460 }
1461
1462 // Methods to support isa and dyn_cast
1463 static bool classof(const SDNode *N) {
1464 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1465 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1466 N->getOpcode() == ISD::ATOMIC_SWAP ||
1467 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1468 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1469 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1470 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1471 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1472 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1473 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1474 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1475 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1476 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1477 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1478 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1479 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1480 N->getOpcode() == ISD::ATOMIC_LOAD ||
1481 N->getOpcode() == ISD::ATOMIC_STORE;
1482 }
1483};
1484
1485/// This SDNode is used for target intrinsics that touch
1486/// memory and need an associated MachineMemOperand. Its opcode may be
1487/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1488/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1489class MemIntrinsicSDNode : public MemSDNode {
1490public:
1491 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1492 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
1493 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
1494 SDNodeBits.IsMemIntrinsic = true;
1495 }
1496
1497 // Methods to support isa and dyn_cast
1498 static bool classof(const SDNode *N) {
1499 // We lower some target intrinsics to their target opcode
1500 // early a node with a target opcode can be of this class
1501 return N->isMemIntrinsic() ||
1502 N->getOpcode() == ISD::PREFETCH ||
1503 N->isTargetMemoryOpcode();
1504 }
1505};
1506
1507/// This SDNode is used to implement the code generator
1508/// support for the llvm IR shufflevector instruction. It combines elements
1509/// from two input vectors into a new input vector, with the selection and
1510/// ordering of elements determined by an array of integers, referred to as
1511/// the shuffle mask. For input vectors of width N, mask indices of 0..N-1
1512/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1513/// An index of -1 is treated as undef, such that the code generator may put
1514/// any value in the corresponding element of the result.
1515class ShuffleVectorSDNode : public SDNode {
1516 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
1517 // is freed when the SelectionDAG object is destroyed.
1518 const int *Mask;
1519
1520protected:
1521 friend class SelectionDAG;
1522
1523 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
1524 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1525
1526public:
1527 ArrayRef<int> getMask() const {
1528 EVT VT = getValueType(0);
1529 return makeArrayRef(Mask, VT.getVectorNumElements());
1530 }
1531
1532 int getMaskElt(unsigned Idx) const {
1533 assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")((Idx < getValueType(0).getVectorNumElements() && "Idx out of range!"
) ? static_cast<void> (0) : __assert_fail ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1533, __PRETTY_FUNCTION__))
;
1534 return Mask[Idx];
1535 }
1536
1537 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
1538
1539 int getSplatIndex() const {
1540 assert(isSplat() && "Cannot get splat index for non-splat!")((isSplat() && "Cannot get splat index for non-splat!"
) ? static_cast<void> (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1540, __PRETTY_FUNCTION__))
;
1541 EVT VT = getValueType(0);
1542 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
1543 if (Mask[i] >= 0)
1544 return Mask[i];
1545
1546 // We can choose any index value here and be correct because all elements
1547 // are undefined. Return 0 for better potential for callers to simplify.
1548 return 0;
1549 }
1550
1551 static bool isSplatMask(const int *Mask, EVT VT);
1552
1553 /// Change values in a shuffle permute mask assuming
1554 /// the two vector operands have swapped position.
1555 static void commuteMask(MutableArrayRef<int> Mask) {
1556 unsigned NumElems = Mask.size();
1557 for (unsigned i = 0; i != NumElems; ++i) {
1558 int idx = Mask[i];
1559 if (idx < 0)
1560 continue;
1561 else if (idx < (int)NumElems)
1562 Mask[i] = idx + NumElems;
1563 else
1564 Mask[i] = idx - NumElems;
1565 }
1566 }
1567
1568 static bool classof(const SDNode *N) {
1569 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
1570 }
1571};
1572
1573class ConstantSDNode : public SDNode {
1574 friend class SelectionDAG;
1575
1576 const ConstantInt *Value;
1577
1578 ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
1579 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
1580 getSDVTList(VT)),
1581 Value(val) {
1582 ConstantSDNodeBits.IsOpaque = isOpaque;
1583 }
1584
1585public:
1586 const ConstantInt *getConstantIntValue() const { return Value; }
1587 const APInt &getAPIntValue() const { return Value->getValue(); }
1588 uint64_t getZExtValue() const { return Value->getZExtValue(); }
1589 int64_t getSExtValue() const { return Value->getSExtValue(); }
1590 uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) {
1591 return Value->getLimitedValue(Limit);
1592 }
1593
1594 bool isOne() const { return Value->isOne(); }
1595 bool isNullValue() const { return Value->isZero(); }
1596 bool isAllOnesValue() const { return Value->isMinusOne(); }
1597
1598 bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }
1599
1600 static bool classof(const SDNode *N) {
1601 return N->getOpcode() == ISD::Constant ||
1602 N->getOpcode() == ISD::TargetConstant;
1603 }
1604};
1605
1606uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
1607 return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1608}
1609
1610const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
1611 return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
1612}
1613
1614class ConstantFPSDNode : public SDNode {
1615 friend class SelectionDAG;
1616
1617 const ConstantFP *Value;
1618
1619 ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
1620 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
1621 DebugLoc(), getSDVTList(VT)),
1622 Value(val) {}
1623
1624public:
1625 const APFloat& getValueAPF() const { return Value->getValueAPF(); }
1626 const ConstantFP *getConstantFPValue() const { return Value; }
1627
1628 /// Return true if the value is positive or negative zero.
1629 bool isZero() const { return Value->isZero(); }
1630
1631 /// Return true if the value is a NaN.
1632 bool isNaN() const { return Value->isNaN(); }
1633
1634 /// Return true if the value is an infinity
1635 bool isInfinity() const { return Value->isInfinity(); }
1636
1637 /// Return true if the value is negative.
1638 bool isNegative() const { return Value->isNegative(); }
1639
1640 /// We don't rely on operator== working on double values, as
1641 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
1642 /// As such, this method can be used to do an exact bit-for-bit comparison of
1643 /// two floating point values.
1644
1645 /// We leave the version with the double argument here because it's just so
1646 /// convenient to write "2.0" and the like. Without this function we'd
1647 /// have to duplicate its logic everywhere it's called.
1648 bool isExactlyValue(double V) const {
1649 return Value->getValueAPF().isExactlyValue(V);
1650 }
1651 bool isExactlyValue(const APFloat& V) const;
1652
1653 static bool isValueValidForType(EVT VT, const APFloat& Val);
1654
1655 static bool classof(const SDNode *N) {
1656 return N->getOpcode() == ISD::ConstantFP ||
1657 N->getOpcode() == ISD::TargetConstantFP;
1658 }
1659};
1660
1661/// Returns true if \p V is a constant integer zero.
1662bool isNullConstant(SDValue V);
1663
1664/// Returns true if \p V is an FP constant with a value of positive zero.
1665bool isNullFPConstant(SDValue V);
1666
1667/// Returns true if \p V is an integer constant with all bits set.
1668bool isAllOnesConstant(SDValue V);
1669
1670/// Returns true if \p V is a constant integer one.
1671bool isOneConstant(SDValue V);
1672
1673/// Return the non-bitcasted source operand of \p V if it exists.
1674/// If \p V is not a bitcasted value, it is returned as-is.
1675SDValue peekThroughBitcasts(SDValue V);
1676
1677/// Return the non-bitcasted and one-use source operand of \p V if it exists.
1678/// If \p V is not a bitcasted one-use value, it is returned as-is.
1679SDValue peekThroughOneUseBitcasts(SDValue V);
1680
1681/// Return the non-extracted vector source operand of \p V if it exists.
1682/// If \p V is not an extracted subvector, it is returned as-is.
1683SDValue peekThroughExtractSubvectors(SDValue V);
1684
1685/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1686/// constant is canonicalized to be operand 1.
1687bool isBitwiseNot(SDValue V, bool AllowUndefs = false);
1688
1689/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1690ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false,
1691 bool AllowTruncation = false);
1692
1693/// Returns the SDNode if it is a demanded constant splat BuildVector or
1694/// constant int.
1695ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
1696 bool AllowUndefs = false,
1697 bool AllowTruncation = false);
1698
1699/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1700ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false);
1701
1702/// Returns the SDNode if it is a demanded constant splat BuildVector or
1703/// constant float.
1704ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts,
1705 bool AllowUndefs = false);
1706
1707/// Return true if the value is a constant 0 integer or a splatted vector of
1708/// a constant 0 integer (with no undefs by default).
1709/// Build vector implicit truncation is not an issue for null values.
1710bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false);
1711
1712/// Return true if the value is a constant 1 integer or a splatted vector of a
1713/// constant 1 integer (with no undefs).
1714/// Does not permit build vector implicit truncation.
1715bool isOneOrOneSplat(SDValue V);
1716
1717/// Return true if the value is a constant -1 integer or a splatted vector of a
1718/// constant -1 integer (with no undefs).
1719/// Does not permit build vector implicit truncation.
1720bool isAllOnesOrAllOnesSplat(SDValue V);
1721
1722class GlobalAddressSDNode : public SDNode {
1723 friend class SelectionDAG;
1724
1725 const GlobalValue *TheGlobal;
1726 int64_t Offset;
1727 unsigned TargetFlags;
1728
1729 GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
1730 const GlobalValue *GA, EVT VT, int64_t o,
1731 unsigned TF);
1732
1733public:
1734 const GlobalValue *getGlobal() const { return TheGlobal; }
1735 int64_t getOffset() const { return Offset; }
1736 unsigned getTargetFlags() const { return TargetFlags; }
1737 // Return the address space this GlobalAddress belongs to.
1738 unsigned getAddressSpace() const;
1739
1740 static bool classof(const SDNode *N) {
1741 return N->getOpcode() == ISD::GlobalAddress ||
1742 N->getOpcode() == ISD::TargetGlobalAddress ||
1743 N->getOpcode() == ISD::GlobalTLSAddress ||
1744 N->getOpcode() == ISD::TargetGlobalTLSAddress;
1745 }
1746};
1747
1748class FrameIndexSDNode : public SDNode {
1749 friend class SelectionDAG;
1750
1751 int FI;
1752
1753 FrameIndexSDNode(int fi, EVT VT, bool isTarg)
1754 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1755 0, DebugLoc(), getSDVTList(VT)), FI(fi) {
1756 }
1757
1758public:
1759 int getIndex() const { return FI; }
1760
1761 static bool classof(const SDNode *N) {
1762 return N->getOpcode() == ISD::FrameIndex ||
1763 N->getOpcode() == ISD::TargetFrameIndex;
1764 }
1765};
1766
1767/// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate
1768/// the offet and size that are started/ended in the underlying FrameIndex.
1769class LifetimeSDNode : public SDNode {
1770 friend class SelectionDAG;
1771 int64_t Size;
1772 int64_t Offset; // -1 if offset is unknown.
1773
1774 LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
1775 SDVTList VTs, int64_t Size, int64_t Offset)
1776 : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {}
1777public:
1778 int64_t getFrameIndex() const {
1779 return cast<FrameIndexSDNode>(getOperand(1))->getIndex();
1780 }
1781
1782 bool hasOffset() const { return Offset >= 0; }
1783 int64_t getOffset() const {
1784 assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1784, __PRETTY_FUNCTION__))
;
1785 return Offset;
1786 }
1787 int64_t getSize() const {
1788 assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1788, __PRETTY_FUNCTION__))
;
1789 return Size;
1790 }
1791
1792 // Methods to support isa and dyn_cast
1793 static bool classof(const SDNode *N) {
1794 return N->getOpcode() == ISD::LIFETIME_START ||
1795 N->getOpcode() == ISD::LIFETIME_END;
1796 }
1797};
1798
1799class JumpTableSDNode : public SDNode {
1800 friend class SelectionDAG;
1801
1802 int JTI;
1803 unsigned TargetFlags;
1804
1805 JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF)
1806 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
1807 0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
1808 }
1809
1810public:
1811 int getIndex() const { return JTI; }
1812 unsigned getTargetFlags() const { return TargetFlags; }
1813
1814 static bool classof(const SDNode *N) {
1815 return N->getOpcode() == ISD::JumpTable ||
1816 N->getOpcode() == ISD::TargetJumpTable;
1817 }
1818};
1819
1820class ConstantPoolSDNode : public SDNode {
1821 friend class SelectionDAG;
1822
1823 union {
1824 const Constant *ConstVal;
1825 MachineConstantPoolValue *MachineCPVal;
1826 } Val;
1827 int Offset; // It's a MachineConstantPoolValue if top bit is set.
1828 unsigned Alignment; // Minimum alignment requirement of CP (not log2 value).
1829 unsigned TargetFlags;
1830
1831 ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
1832 unsigned Align, unsigned TF)
1833 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1834 DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
1835 TargetFlags(TF) {
1836 assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1836, __PRETTY_FUNCTION__))
;
1837 Val.ConstVal = c;
1838 }
1839
1840 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
1841 EVT VT, int o, unsigned Align, unsigned TF)
1842 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1843 DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
1844 TargetFlags(TF) {
1845 assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1845, __PRETTY_FUNCTION__))
;
1846 Val.MachineCPVal = v;
1847 Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
1848 }
1849
1850public:
1851 bool isMachineConstantPoolEntry() const {
1852 return Offset < 0;
1853 }
1854
1855 const Constant *getConstVal() const {
1856 assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")((!isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1856, __PRETTY_FUNCTION__))
;
1857 return Val.ConstVal;
1858 }
1859
1860 MachineConstantPoolValue *getMachineCPVal() const {
1861 assert(isMachineConstantPoolEntry() && "Wrong constantpool type")((isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1861, __PRETTY_FUNCTION__))
;
1862 return Val.MachineCPVal;
1863 }
1864
1865 int getOffset() const {
1866 return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
1867 }
1868
1869 // Return the alignment of this constant pool object, which is either 0 (for
1870 // default alignment) or the desired value.
1871 unsigned getAlignment() const { return Alignment; }
1872 unsigned getTargetFlags() const { return TargetFlags; }
1873
1874 Type *getType() const;
1875
1876 static bool classof(const SDNode *N) {
1877 return N->getOpcode() == ISD::ConstantPool ||
1878 N->getOpcode() == ISD::TargetConstantPool;
1879 }
1880};
1881
1882/// Completely target-dependent object reference.
1883class TargetIndexSDNode : public SDNode {
1884 friend class SelectionDAG;
1885
1886 unsigned TargetFlags;
1887 int Index;
1888 int64_t Offset;
1889
1890public:
1891 TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF)
1892 : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
1893 TargetFlags(TF), Index(Idx), Offset(Ofs) {}
1894
1895 unsigned getTargetFlags() const { return TargetFlags; }
1896 int getIndex() const { return Index; }
1897 int64_t getOffset() const { return Offset; }
1898
1899 static bool classof(const SDNode *N) {
1900 return N->getOpcode() == ISD::TargetIndex;
1901 }
1902};
1903
1904class BasicBlockSDNode : public SDNode {
1905 friend class SelectionDAG;
1906
1907 MachineBasicBlock *MBB;
1908
1909 /// Debug info is meaningful and potentially useful here, but we create
1910 /// blocks out of order when they're jumped to, which makes it a bit
1911 /// harder. Let's see if we need it first.
1912 explicit BasicBlockSDNode(MachineBasicBlock *mbb)
1913 : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
1914 {}
1915
1916public:
1917 MachineBasicBlock *getBasicBlock() const { return MBB; }
1918
1919 static bool classof(const SDNode *N) {
1920 return N->getOpcode() == ISD::BasicBlock;
1921 }
1922};
1923
1924/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1925class BuildVectorSDNode : public SDNode {
1926public:
1927 // These are constructed as SDNodes and then cast to BuildVectorSDNodes.
1928 explicit BuildVectorSDNode() = delete;
1929
1930 /// Check if this is a constant splat, and if so, find the
1931 /// smallest element size that splats the vector. If MinSplatBits is
1932 /// nonzero, the element size must be at least that large. Note that the
1933 /// splat element may be the entire vector (i.e., a one element vector).
1934 /// Returns the splat element value in SplatValue. Any undefined bits in
1935 /// that value are zero, and the corresponding bits in the SplatUndef mask
1936 /// are set. The SplatBitSize value is set to the splat element size in
1937 /// bits. HasAnyUndefs is set to true if any bits in the vector are
1938 /// undefined. isBigEndian describes the endianness of the target.
1939 bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
1940 unsigned &SplatBitSize, bool &HasAnyUndefs,
1941 unsigned MinSplatBits = 0,
1942 bool isBigEndian = false) const;
1943
1944 /// Returns the demanded splatted value or a null value if this is not a
1945 /// splat.
1946 ///
1947 /// The DemandedElts mask indicates the elements that must be in the splat.
1948 /// If passed a non-null UndefElements bitvector, it will resize it to match
1949 /// the vector width and set the bits where elements are undef.
1950 SDValue getSplatValue(const APInt &DemandedElts,
1951 BitVector *UndefElements = nullptr) const;
1952
1953 /// Returns the splatted value or a null value if this is not a splat.
1954 ///
1955 /// If passed a non-null UndefElements bitvector, it will resize it to match
1956 /// the vector width and set the bits where elements are undef.
1957 SDValue getSplatValue(BitVector *UndefElements = nullptr) const;
1958
1959 /// Returns the demanded splatted constant or null if this is not a constant
1960 /// splat.
1961 ///
1962 /// The DemandedElts mask indicates the elements that must be in the splat.
1963 /// If passed a non-null UndefElements bitvector, it will resize it to match
1964 /// the vector width and set the bits where elements are undef.
1965 ConstantSDNode *
1966 getConstantSplatNode(const APInt &DemandedElts,
1967 BitVector *UndefElements = nullptr) const;
1968
1969 /// Returns the splatted constant or null if this is not a constant
1970 /// splat.
1971 ///
1972 /// If passed a non-null UndefElements bitvector, it will resize it to match
1973 /// the vector width and set the bits where elements are undef.
1974 ConstantSDNode *
1975 getConstantSplatNode(BitVector *UndefElements = nullptr) const;
1976
1977 /// Returns the demanded splatted constant FP or null if this is not a
1978 /// constant FP splat.
1979 ///
1980 /// The DemandedElts mask indicates the elements that must be in the splat.
1981 /// If passed a non-null UndefElements bitvector, it will resize it to match
1982 /// the vector width and set the bits where elements are undef.
1983 ConstantFPSDNode *
1984 getConstantFPSplatNode(const APInt &DemandedElts,
1985 BitVector *UndefElements = nullptr) const;
1986
1987 /// Returns the splatted constant FP or null if this is not a constant
1988 /// FP splat.
1989 ///
1990 /// If passed a non-null UndefElements bitvector, it will resize it to match
1991 /// the vector width and set the bits where elements are undef.
1992 ConstantFPSDNode *
1993 getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;
1994
1995 /// If this is a constant FP splat and the splatted constant FP is an
1996 /// exact power or 2, return the log base 2 integer value. Otherwise,
1997 /// return -1.
1998 ///
1999 /// The BitWidth specifies the necessary bit precision.
2000 int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
2001 uint32_t BitWidth) const;
2002
2003 bool isConstant() const;
2004
2005 static bool classof(const SDNode *N) {
2006 return N->getOpcode() == ISD::BUILD_VECTOR;
2007 }
2008};
2009
2010/// An SDNode that holds an arbitrary LLVM IR Value. This is
2011/// used when the SelectionDAG needs to make a simple reference to something
2012/// in the LLVM IR representation.
2013///
2014class SrcValueSDNode : public SDNode {
2015 friend class SelectionDAG;
2016
2017 const Value *V;
2018
2019 /// Create a SrcValue for a general value.
2020 explicit SrcValueSDNode(const Value *v)
2021 : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}
2022
2023public:
2024 /// Return the contained Value.
2025 const Value *getValue() const { return V; }
2026
2027 static bool classof(const SDNode *N) {
2028 return N->getOpcode() == ISD::SRCVALUE;
2029 }
2030};
2031
2032class MDNodeSDNode : public SDNode {
2033 friend class SelectionDAG;
2034
2035 const MDNode *MD;
2036
2037 explicit MDNodeSDNode(const MDNode *md)
2038 : SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
2039 {}
2040
2041public:
2042 const MDNode *getMD() const { return MD; }
2043
2044 static bool classof(const SDNode *N) {
2045 return N->getOpcode() == ISD::MDNODE_SDNODE;
2046 }
2047};
2048
2049class RegisterSDNode : public SDNode {
2050 friend class SelectionDAG;
2051
2052 unsigned Reg;
2053
2054 RegisterSDNode(unsigned reg, EVT VT)
2055 : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}
2056
2057public:
2058 unsigned getReg() const { return Reg; }
2059
2060 static bool classof(const SDNode *N) {
2061 return N->getOpcode() == ISD::Register;
2062 }
2063};
2064
2065class RegisterMaskSDNode : public SDNode {
2066 friend class SelectionDAG;
2067
2068 // The memory for RegMask is not owned by the node.
2069 const uint32_t *RegMask;
2070
2071 RegisterMaskSDNode(const uint32_t *mask)
2072 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
2073 RegMask(mask) {}
2074
2075public:
2076 const uint32_t *getRegMask() const { return RegMask; }
2077
2078 static bool classof(const SDNode *N) {
2079 return N->getOpcode() == ISD::RegisterMask;
2080 }
2081};
2082
2083class BlockAddressSDNode : public SDNode {
2084 friend class SelectionDAG;
2085
2086 const BlockAddress *BA;
2087 int64_t Offset;
2088 unsigned TargetFlags;
2089
2090 BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
2091 int64_t o, unsigned Flags)
2092 : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
2093 BA(ba), Offset(o), TargetFlags(Flags) {}
2094
2095public:
2096 const BlockAddress *getBlockAddress() const { return BA; }
2097 int64_t getOffset() const { return Offset; }
2098 unsigned getTargetFlags() const { return TargetFlags; }
2099
2100 static bool classof(const SDNode *N) {
2101 return N->getOpcode() == ISD::BlockAddress ||
2102 N->getOpcode() == ISD::TargetBlockAddress;
2103 }
2104};
2105
2106class LabelSDNode : public SDNode {
2107 friend class SelectionDAG;
2108
2109 MCSymbol *Label;
2110
2111 LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L)
2112 : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) {
2113 assert(LabelSDNode::classof(this) && "not a label opcode")((LabelSDNode::classof(this) && "not a label opcode")
? static_cast<void> (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2113, __PRETTY_FUNCTION__))
;
2114 }
2115
2116public:
2117 MCSymbol *getLabel() const { return Label; }
2118
2119 static bool classof(const SDNode *N) {
2120 return N->getOpcode() == ISD::EH_LABEL ||
2121 N->getOpcode() == ISD::ANNOTATION_LABEL;
2122 }
2123};
2124
2125class ExternalSymbolSDNode : public SDNode {
2126 friend class SelectionDAG;
2127
2128 const char *Symbol;
2129 unsigned TargetFlags;
2130
2131 ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT)
2132 : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0,
2133 DebugLoc(), getSDVTList(VT)),
2134 Symbol(Sym), TargetFlags(TF) {}
2135
2136public:
2137 const char *getSymbol() const { return Symbol; }
2138 unsigned getTargetFlags() const { return TargetFlags; }
2139
2140 static bool classof(const SDNode *N) {
2141 return N->getOpcode() == ISD::ExternalSymbol ||
2142 N->getOpcode() == ISD::TargetExternalSymbol;
2143 }
2144};
2145
2146class MCSymbolSDNode : public SDNode {
2147 friend class SelectionDAG;
2148
2149 MCSymbol *Symbol;
2150
2151 MCSymbolSDNode(MCSymbol *Symbol, EVT VT)
2152 : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {}
2153
2154public:
2155 MCSymbol *getMCSymbol() const { return Symbol; }
2156
2157 static bool classof(const SDNode *N) {
2158 return N->getOpcode() == ISD::MCSymbol;
2159 }
2160};
2161
2162class CondCodeSDNode : public SDNode {
2163 friend class SelectionDAG;
2164
2165 ISD::CondCode Condition;
2166
2167 explicit CondCodeSDNode(ISD::CondCode Cond)
2168 : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2169 Condition(Cond) {}
2170
2171public:
2172 ISD::CondCode get() const { return Condition; }
2173
2174 static bool classof(const SDNode *N) {
2175 return N->getOpcode() == ISD::CONDCODE;
2176 }
2177};
2178
2179/// This class is used to represent EVT's, which are used
2180/// to parameterize some operations.
2181class VTSDNode : public SDNode {
2182 friend class SelectionDAG;
2183
2184 EVT ValueType;
2185
2186 explicit VTSDNode(EVT VT)
2187 : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2188 ValueType(VT) {}
2189
2190public:
2191 EVT getVT() const { return ValueType; }
2192
2193 static bool classof(const SDNode *N) {
2194 return N->getOpcode() == ISD::VALUETYPE;
2195 }
2196};
2197
2198/// Base class for LoadSDNode and StoreSDNode
2199class LSBaseSDNode : public MemSDNode {
2200public:
2201 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
2202 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2203 MachineMemOperand *MMO)
2204 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2205 LSBaseSDNodeBits.AddressingMode = AM;
2206 assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2206, __PRETTY_FUNCTION__))
;
2207 }
2208
2209 const SDValue &getOffset() const {
2210 return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
2211 }
2212
2213 /// Return the addressing mode for this load or store:
2214 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2215 ISD::MemIndexedMode getAddressingMode() const {
2216 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2217 }
2218
2219 /// Return true if this is a pre/post inc/dec load/store.
2220 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2221
2222 /// Return true if this is NOT a pre/post inc/dec load/store.
2223 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2224
2225 static bool classof(const SDNode *N) {
2226 return N->getOpcode() == ISD::LOAD ||
2227 N->getOpcode() == ISD::STORE;
2228 }
2229};
2230
2231/// This class is used to represent ISD::LOAD nodes.
2232class LoadSDNode : public LSBaseSDNode {
2233 friend class SelectionDAG;
2234
2235 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2236 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2237 MachineMemOperand *MMO)
2238 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2239 LoadSDNodeBits.ExtTy = ETy;
2240 assert(readMem() && "Load MachineMemOperand is not a load!")((readMem() && "Load MachineMemOperand is not a load!"
) ? static_cast<void> (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2240, __PRETTY_FUNCTION__))
;
2241 assert(!writeMem() && "Load MachineMemOperand is a store!")((!writeMem() && "Load MachineMemOperand is a store!"
) ? static_cast<void> (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2241, __PRETTY_FUNCTION__))
;
2242 }
2243
2244public:
2245 /// Return whether this is a plain node,
2246 /// or one of the varieties of value-extending loads.
2247 ISD::LoadExtType getExtensionType() const {
2248 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2249 }
2250
2251 const SDValue &getBasePtr() const { return getOperand(1); }
2252 const SDValue &getOffset() const { return getOperand(2); }
2253
2254 static bool classof(const SDNode *N) {
2255 return N->getOpcode() == ISD::LOAD;
2256 }
2257};
2258
2259/// This class is used to represent ISD::STORE nodes.
2260class StoreSDNode : public LSBaseSDNode {
2261 friend class SelectionDAG;
2262
2263 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2264 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2265 MachineMemOperand *MMO)
2266 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2267 StoreSDNodeBits.IsTruncating = isTrunc;
2268 assert(!readMem() && "Store MachineMemOperand is a load!")((!readMem() && "Store MachineMemOperand is a load!")
? static_cast<void> (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2268, __PRETTY_FUNCTION__))
;
2269 assert(writeMem() && "Store MachineMemOperand is not a store!")((writeMem() && "Store MachineMemOperand is not a store!"
) ? static_cast<void> (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2269, __PRETTY_FUNCTION__))
;
2270 }
2271
2272public:
2273 /// Return true if the op does a truncation before store.
2274 /// For integers this is the same as doing a TRUNCATE and storing the result.
2275 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2276 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2277 void setTruncatingStore(bool Truncating) {
2278 StoreSDNodeBits.IsTruncating = Truncating;
2279 }
2280
2281 const SDValue &getValue() const { return getOperand(1); }
2282 const SDValue &getBasePtr() const { return getOperand(2); }
2283 const SDValue &getOffset() const { return getOperand(3); }
2284
2285 static bool classof(const SDNode *N) {
2286 return N->getOpcode() == ISD::STORE;
2287 }
2288};
2289
2290/// This base class is used to represent MLOAD and MSTORE nodes
2291class MaskedLoadStoreSDNode : public MemSDNode {
2292public:
2293 friend class SelectionDAG;
2294
2295 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
2296 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2297 MachineMemOperand *MMO)
2298 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {}
2299
2300 // MaskedLoadSDNode (Chain, ptr, mask, passthru)
2301 // MaskedStoreSDNode (Chain, data, ptr, mask)
2302 // Mask is a vector of i1 elements
2303 const SDValue &getBasePtr() const {
2304 return getOperand(getOpcode() == ISD::MLOAD ? 1 : 2);
2305 }
2306 const SDValue &getMask() const {
2307 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2308 }
2309
2310 static bool classof(const SDNode *N) {
2311 return N->getOpcode() == ISD::MLOAD ||
2312 N->getOpcode() == ISD::MSTORE;
2313 }
2314};
2315
2316/// This class is used to represent an MLOAD node
2317class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
2318public:
2319 friend class SelectionDAG;
2320
2321 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2322 ISD::LoadExtType ETy, bool IsExpanding, EVT MemVT,
2323 MachineMemOperand *MMO)
2324 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, MemVT, MMO) {
2325 LoadSDNodeBits.ExtTy = ETy;
2326 LoadSDNodeBits.IsExpanding = IsExpanding;
2327 }
2328
2329 ISD::LoadExtType getExtensionType() const {
2330 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2331 }
2332
2333 const SDValue &getBasePtr() const { return getOperand(1); }
2334 const SDValue &getMask() const { return getOperand(2); }
2335 const SDValue &getPassThru() const { return getOperand(3); }
2336
2337 static bool classof(const SDNode *N) {
2338 return N->getOpcode() == ISD::MLOAD;
2339 }
2340
2341 bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2342};
2343
2344/// This class is used to represent an MSTORE node
2345class MaskedStoreSDNode : public MaskedLoadStoreSDNode {
2346public:
2347 friend class SelectionDAG;
2348
2349 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2350 bool isTrunc, bool isCompressing, EVT MemVT,
2351 MachineMemOperand *MMO)
2352 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, MemVT, MMO) {
2353 StoreSDNodeBits.IsTruncating = isTrunc;
2354 StoreSDNodeBits.IsCompressing = isCompressing;
2355 }
2356
2357 /// Return true if the op does a truncation before store.
2358 /// For integers this is the same as doing a TRUNCATE and storing the result.
2359 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2360 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2361
2362 /// Returns true if the op does a compression to the vector before storing.
2363 /// The node contiguously stores the active elements (integers or floats)
2364 /// in src (those with their respective bit set in writemask k) to unaligned
2365 /// memory at base_addr.
2366 bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }
2367
2368 const SDValue &getValue() const { return getOperand(1); }
2369 const SDValue &getBasePtr() const { return getOperand(2); }
2370 const SDValue &getMask() const { return getOperand(3); }
2371
2372 static bool classof(const SDNode *N) {
2373 return N->getOpcode() == ISD::MSTORE;
2374 }
2375};
2376
2377/// This is a base class used to represent
2378/// MGATHER and MSCATTER nodes
2379///
2380class MaskedGatherScatterSDNode : public MemSDNode {
2381public:
2382 friend class SelectionDAG;
2383
2384 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
2385 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2386 MachineMemOperand *MMO, ISD::MemIndexType IndexType)
2387 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2388 LSBaseSDNodeBits.AddressingMode = IndexType;
2389 assert(getIndexType() == IndexType && "Value truncated")((getIndexType() == IndexType && "Value truncated") ?
static_cast<void> (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2389, __PRETTY_FUNCTION__))
;
2390 }
2391
2392 /// How is Index applied to BasePtr when computing addresses.
2393 ISD::MemIndexType getIndexType() const {
2394 return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);
2395 }
2396 bool isIndexScaled() const {
2397 return (getIndexType() == ISD::SIGNED_SCALED) ||
2398 (getIndexType() == ISD::UNSIGNED_SCALED);
2399 }
2400 bool isIndexSigned() const {
2401 return (getIndexType() == ISD::SIGNED_SCALED) ||
2402 (getIndexType() == ISD::SIGNED_UNSCALED);
2403 }
2404
2405 // In the both nodes address is Op1, mask is Op2:
2406 // MaskedGatherSDNode (Chain, passthru, mask, base, index, scale)
2407 // MaskedScatterSDNode (Chain, value, mask, base, index, scale)
2408 // Mask is a vector of i1 elements
2409 const SDValue &getBasePtr() const { return getOperand(3); }
2410 const SDValue &getIndex() const { return getOperand(4); }
2411 const SDValue &getMask() const { return getOperand(2); }
2412 const SDValue &getScale() const { return getOperand(5); }
2413
2414 static bool classof(const SDNode *N) {
2415 return N->getOpcode() == ISD::MGATHER ||
2416 N->getOpcode() == ISD::MSCATTER;
2417 }
2418};
2419
2420/// This class is used to represent an MGATHER node
2421///
2422class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
2423public:
2424 friend class SelectionDAG;
2425
2426 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2427 EVT MemVT, MachineMemOperand *MMO,
2428 ISD::MemIndexType IndexType)
2429 : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
2430 IndexType) {}
2431
2432 const SDValue &getPassThru() const { return getOperand(1); }
2433
2434 static bool classof(const SDNode *N) {
2435 return N->getOpcode() == ISD::MGATHER;
2436 }
2437};
2438
2439/// This class is used to represent an MSCATTER node
2440///
2441class MaskedScatterSDNode : public MaskedGatherScatterSDNode {
2442public:
2443 friend class SelectionDAG;
2444
2445 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2446 EVT MemVT, MachineMemOperand *MMO,
2447 ISD::MemIndexType IndexType)
2448 : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO,
2449 IndexType) {}
2450
2451 const SDValue &getValue() const { return getOperand(1); }
2452
2453 static bool classof(const SDNode *N) {
2454 return N->getOpcode() == ISD::MSCATTER;
2455 }
2456};
2457
2458/// An SDNode that represents everything that will be needed
2459/// to construct a MachineInstr. These nodes are created during the
2460/// instruction selection proper phase.
2461///
2462/// Note that the only supported way to set the `memoperands` is by calling the
2463/// `SelectionDAG::setNodeMemRefs` function as the memory management happens
2464/// inside the DAG rather than in the node.
2465class MachineSDNode : public SDNode {
2466private:
2467 friend class SelectionDAG;
2468
2469 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
2470 : SDNode(Opc, Order, DL, VTs) {}
2471
2472 // We use a pointer union between a single `MachineMemOperand` pointer and
2473 // a pointer to an array of `MachineMemOperand` pointers. This is null when
2474 // the number of these is zero, the single pointer variant used when the
2475 // number is one, and the array is used for larger numbers.
2476 //
2477 // The array is allocated via the `SelectionDAG`'s allocator and so will
2478 // always live until the DAG is cleaned up and doesn't require ownership here.
2479 //
2480 // We can't use something simpler like `TinyPtrVector` here because `SDNode`
2481 // subclasses aren't managed in a conforming C++ manner. See the comments on
2482 // `SelectionDAG::MorphNodeTo` which details what all goes on, but the
2483 // constraint here is that these don't manage memory with their constructor or
2484 // destructor and can be initialized to a good state even if they start off
2485 // uninitialized.
2486 PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {};
2487
2488 // Note that this could be folded into the above `MemRefs` member if doing so
2489 // is advantageous at some point. We don't need to store this in most cases.
2490 // However, at the moment this doesn't appear to make the allocation any
2491 // smaller and makes the code somewhat simpler to read.
2492 int NumMemRefs = 0;
2493
2494public:
2495 using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator;
2496
2497 ArrayRef<MachineMemOperand *> memoperands() const {
2498 // Special case the common cases.
2499 if (NumMemRefs == 0)
2500 return {};
2501 if (NumMemRefs == 1)
2502 return makeArrayRef(MemRefs.getAddrOfPtr1(), 1);
2503
2504 // Otherwise we have an actual array.
2505 return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs);
2506 }
2507 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
2508 mmo_iterator memoperands_end() const { return memoperands().end(); }
2509 bool memoperands_empty() const { return memoperands().empty(); }
2510
2511 /// Clear out the memory reference descriptor list.
2512 void clearMemRefs() {
2513 MemRefs = nullptr;
2514 NumMemRefs = 0;
2515 }
2516
2517 static bool classof(const SDNode *N) {
2518 return N->isMachineOpcode();
2519 }
2520};
2521
2522class SDNodeIterator : public std::iterator<std::forward_iterator_tag,
2523 SDNode, ptrdiff_t> {
2524 const SDNode *Node;
2525 unsigned Operand;
2526
2527 SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}
2528
2529public:
2530 bool operator==(const SDNodeIterator& x) const {
2531 return Operand == x.Operand;
2532 }
2533 bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }
2534
2535 pointer operator*() const {
2536 return Node->getOperand(Operand).getNode();
2537 }
2538 pointer operator->() const { return operator*(); }
2539
2540 SDNodeIterator& operator++() { // Preincrement
2541 ++Operand;
2542 return *this;
2543 }
2544 SDNodeIterator operator++(int) { // Postincrement
2545 SDNodeIterator tmp = *this; ++*this; return tmp;
2546 }
2547 size_t operator-(SDNodeIterator Other) const {
2548 assert(Node == Other.Node &&((Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2549, __PRETTY_FUNCTION__))
2549 "Cannot compare iterators of two different nodes!")((Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2549, __PRETTY_FUNCTION__))
;
2550 return Operand - Other.Operand;
2551 }
2552
2553 static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); }
2554 static SDNodeIterator end (const SDNode *N) {
2555 return SDNodeIterator(N, N->getNumOperands());
2556 }
2557
2558 unsigned getOperand() const { return Operand; }
2559 const SDNode *getNode() const { return Node; }
2560};
2561
2562template <> struct GraphTraits<SDNode*> {
2563 using NodeRef = SDNode *;
2564 using ChildIteratorType = SDNodeIterator;
2565
2566 static NodeRef getEntryNode(SDNode *N) { return N; }
2567
2568 static ChildIteratorType child_begin(NodeRef N) {
2569 return SDNodeIterator::begin(N);
2570 }
2571
2572 static ChildIteratorType child_end(NodeRef N) {
2573 return SDNodeIterator::end(N);
2574 }
2575};
2576
2577/// A representation of the largest SDNode, for use in sizeof().
2578///
2579/// This needs to be a union because the largest node differs on 32 bit systems
2580/// with 4 and 8 byte pointer alignment, respectively.
2581using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode,
2582 BlockAddressSDNode,
2583 GlobalAddressSDNode>;
2584
2585/// The SDNode class with the greatest alignment requirement.
2586using MostAlignedSDNode = GlobalAddressSDNode;
2587
2588namespace ISD {
2589
2590 /// Returns true if the specified node is a non-extending and unindexed load.
2591 inline bool isNormalLoad(const SDNode *N) {
2592 const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N);
2593 return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
2594 Ld->getAddressingMode() == ISD::UNINDEXED;
2595 }
2596
2597 /// Returns true if the specified node is a non-extending load.
2598 inline bool isNON_EXTLoad(const SDNode *N) {
2599 return isa<LoadSDNode>(N) &&
2600 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
2601 }
2602
2603 /// Returns true if the specified node is a EXTLOAD.
2604 inline bool isEXTLoad(const SDNode *N) {
2605 return isa<LoadSDNode>(N) &&
2606 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
2607 }
2608
2609 /// Returns true if the specified node is a SEXTLOAD.
2610 inline bool isSEXTLoad(const SDNode *N) {
2611 return isa<LoadSDNode>(N) &&
2612 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
2613 }
2614
2615 /// Returns true if the specified node is a ZEXTLOAD.
2616 inline bool isZEXTLoad(const SDNode *N) {
2617 return isa<LoadSDNode>(N) &&
2618 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
2619 }
2620
2621 /// Returns true if the specified node is an unindexed load.
2622 inline bool isUNINDEXEDLoad(const SDNode *N) {
2623 return isa<LoadSDNode>(N) &&
2624 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2625 }
2626
2627 /// Returns true if the specified node is a non-truncating
2628 /// and unindexed store.
2629 inline bool isNormalStore(const SDNode *N) {
2630 const StoreSDNode *St = dyn_cast<StoreSDNode>(N);
2631 return St && !St->isTruncatingStore() &&
2632 St->getAddressingMode() == ISD::UNINDEXED;
2633 }
2634
2635 /// Returns true if the specified node is a non-truncating store.
2636 inline bool isNON_TRUNCStore(const SDNode *N) {
2637 return isa<StoreSDNode>(N) && !cast<StoreSDNode>(N)->isTruncatingStore();
2638 }
2639
2640 /// Returns true if the specified node is a truncating store.
2641 inline bool isTRUNCStore(const SDNode *N) {
2642 return isa<StoreSDNode>(N) && cast<StoreSDNode>(N)->isTruncatingStore();
2643 }
2644
2645 /// Returns true if the specified node is an unindexed store.
2646 inline bool isUNINDEXEDStore(const SDNode *N) {
2647 return isa<StoreSDNode>(N) &&
2648 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2649 }
2650
2651 /// Attempt to match a unary predicate against a scalar/splat constant or
2652 /// every element of a constant BUILD_VECTOR.
2653 /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
2654 bool matchUnaryPredicate(SDValue Op,
2655 std::function<bool(ConstantSDNode *)> Match,
2656 bool AllowUndefs = false);
2657
2658 /// Attempt to match a binary predicate against a pair of scalar/splat
2659 /// constants or every element of a pair of constant BUILD_VECTORs.
2660 /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
2661 /// If AllowTypeMismatch is true then RetType + ArgTypes don't need to match.
2662 bool matchBinaryPredicate(
2663 SDValue LHS, SDValue RHS,
2664 std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match,
2665 bool AllowUndefs = false, bool AllowTypeMismatch = false);
2666} // end namespace ISD
2667
2668} // end namespace llvm
2669
2670#endif // LLVM_CODEGEN_SELECTIONDAGNODES_H