Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1114, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name LegalizeIntegerTypes.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/CodeGen/SelectionDAG -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/include -I /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0=. -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-08-28-193554-24367-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/Analysis/TargetLibraryInfo.h"
22#include "llvm/IR/DerivedTypes.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/KnownBits.h"
25#include "llvm/Support/raw_ostream.h"
26using namespace llvm;
27
28#define DEBUG_TYPE"legalize-types" "legalize-types"
29
30//===----------------------------------------------------------------------===//
31// Integer Result Promotion
32//===----------------------------------------------------------------------===//
33
34/// PromoteIntegerResult - This method is called when a result of a node is
35/// found to be in need of promotion to a larger type. At this point, the node
36/// may also have invalid operands or may have other results that need
37/// expansion, we just know that (at least) one result needs promotion.
38void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
39 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
40 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
41 SDValue Res = SDValue();
42
43 // See if the target wants to custom expand this node.
44 if (CustomLowerNode(N, N->getValueType(ResNo), true)) {
45 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Node has been custom expanded, done\n"
; } } while (false)
;
46 return;
47 }
48
49 switch (N->getOpcode()) {
50 default:
51#ifndef NDEBUG
52 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
53 N->dump(&DAG); dbgs() << "\n";
54#endif
55 llvm_unreachable("Do not know how to promote this operator!")::llvm::llvm_unreachable_internal("Do not know how to promote this operator!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 55)
;
56 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
57 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
58 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
59 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
60 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
61 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
62 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
63 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
64 case ISD::CTLZ_ZERO_UNDEF:
65 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
66 case ISD::PARITY:
67 case ISD::CTPOP: Res = PromoteIntRes_CTPOP_PARITY(N); break;
68 case ISD::CTTZ_ZERO_UNDEF:
69 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
70 case ISD::EXTRACT_VECTOR_ELT:
71 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
72 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
73 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
74 break;
75 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
76 break;
77 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
78 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
79 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
80 case ISD::STRICT_FSETCC:
81 case ISD::STRICT_FSETCCS:
82 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
83 case ISD::SMIN:
84 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
85 case ISD::UMIN:
86 case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
87
88 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
89 case ISD::SIGN_EXTEND_INREG:
90 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
91 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
92 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
93 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
94 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
95 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
96 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
97
98 case ISD::EXTRACT_SUBVECTOR:
99 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
100 case ISD::INSERT_SUBVECTOR:
101 Res = PromoteIntRes_INSERT_SUBVECTOR(N); break;
102 case ISD::VECTOR_REVERSE:
103 Res = PromoteIntRes_VECTOR_REVERSE(N); break;
104 case ISD::VECTOR_SHUFFLE:
105 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
106 case ISD::VECTOR_SPLICE:
107 Res = PromoteIntRes_VECTOR_SPLICE(N); break;
108 case ISD::INSERT_VECTOR_ELT:
109 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
110 case ISD::BUILD_VECTOR:
111 Res = PromoteIntRes_BUILD_VECTOR(N); break;
112 case ISD::SCALAR_TO_VECTOR:
113 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
114 case ISD::SPLAT_VECTOR:
115 Res = PromoteIntRes_SPLAT_VECTOR(N); break;
116 case ISD::STEP_VECTOR: Res = PromoteIntRes_STEP_VECTOR(N); break;
117 case ISD::CONCAT_VECTORS:
118 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
119
120 case ISD::ANY_EXTEND_VECTOR_INREG:
121 case ISD::SIGN_EXTEND_VECTOR_INREG:
122 case ISD::ZERO_EXTEND_VECTOR_INREG:
123 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
124
125 case ISD::SIGN_EXTEND:
126 case ISD::ZERO_EXTEND:
127 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
128
129 case ISD::STRICT_FP_TO_SINT:
130 case ISD::STRICT_FP_TO_UINT:
131 case ISD::FP_TO_SINT:
132 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
133
134 case ISD::FP_TO_SINT_SAT:
135 case ISD::FP_TO_UINT_SAT:
136 Res = PromoteIntRes_FP_TO_XINT_SAT(N); break;
137
138 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
139
140 case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break;
141
142 case ISD::ISNAN: Res = PromoteIntRes_ISNAN(N); break;
143
144 case ISD::AND:
145 case ISD::OR:
146 case ISD::XOR:
147 case ISD::ADD:
148 case ISD::SUB:
149 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
150
151 case ISD::SDIV:
152 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
153
154 case ISD::UDIV:
155 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
156
157 case ISD::SADDO:
158 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
159 case ISD::UADDO:
160 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
161 case ISD::SMULO:
162 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
163
164 case ISD::ADDE:
165 case ISD::SUBE:
166 case ISD::ADDCARRY:
167 case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
168
169 case ISD::SADDO_CARRY:
170 case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break;
171
172 case ISD::SADDSAT:
173 case ISD::UADDSAT:
174 case ISD::SSUBSAT:
175 case ISD::USUBSAT:
176 case ISD::SSHLSAT:
177 case ISD::USHLSAT: Res = PromoteIntRes_ADDSUBSHLSAT(N); break;
178
179 case ISD::SMULFIX:
180 case ISD::SMULFIXSAT:
181 case ISD::UMULFIX:
182 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
183
184 case ISD::SDIVFIX:
185 case ISD::SDIVFIXSAT:
186 case ISD::UDIVFIX:
187 case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
188
189 case ISD::ABS: Res = PromoteIntRes_ABS(N); break;
190
191 case ISD::ATOMIC_LOAD:
192 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
193
194 case ISD::ATOMIC_LOAD_ADD:
195 case ISD::ATOMIC_LOAD_SUB:
196 case ISD::ATOMIC_LOAD_AND:
197 case ISD::ATOMIC_LOAD_CLR:
198 case ISD::ATOMIC_LOAD_OR:
199 case ISD::ATOMIC_LOAD_XOR:
200 case ISD::ATOMIC_LOAD_NAND:
201 case ISD::ATOMIC_LOAD_MIN:
202 case ISD::ATOMIC_LOAD_MAX:
203 case ISD::ATOMIC_LOAD_UMIN:
204 case ISD::ATOMIC_LOAD_UMAX:
205 case ISD::ATOMIC_SWAP:
206 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
207
208 case ISD::ATOMIC_CMP_SWAP:
209 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
210 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
211 break;
212
213 case ISD::VECREDUCE_ADD:
214 case ISD::VECREDUCE_MUL:
215 case ISD::VECREDUCE_AND:
216 case ISD::VECREDUCE_OR:
217 case ISD::VECREDUCE_XOR:
218 case ISD::VECREDUCE_SMAX:
219 case ISD::VECREDUCE_SMIN:
220 case ISD::VECREDUCE_UMAX:
221 case ISD::VECREDUCE_UMIN:
222 Res = PromoteIntRes_VECREDUCE(N);
223 break;
224
225 case ISD::FREEZE:
226 Res = PromoteIntRes_FREEZE(N);
227 break;
228
229 case ISD::ROTL:
230 case ISD::ROTR:
231 Res = PromoteIntRes_Rotate(N);
232 break;
233
234 case ISD::FSHL:
235 case ISD::FSHR:
236 Res = PromoteIntRes_FunnelShift(N);
237 break;
238 }
239
240 // If the result is null then the sub-method took care of registering it.
241 if (Res.getNode())
242 SetPromotedInteger(SDValue(N, ResNo), Res);
243}
244
245SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
246 unsigned ResNo) {
247 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
248 return GetPromotedInteger(Op);
249}
250
251SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
252 // Sign-extend the new bits, and continue the assertion.
253 SDValue Op = SExtPromotedInteger(N->getOperand(0));
254 return DAG.getNode(ISD::AssertSext, SDLoc(N),
255 Op.getValueType(), Op, N->getOperand(1));
256}
257
258SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
259 // Zero the new bits, and continue the assertion.
260 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
261 return DAG.getNode(ISD::AssertZext, SDLoc(N),
262 Op.getValueType(), Op, N->getOperand(1));
263}
264
265SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
266 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
267 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
268 N->getMemoryVT(), ResVT,
269 N->getChain(), N->getBasePtr(),
270 N->getMemOperand());
271 // Legalize the chain result - switch anything that used the old chain to
272 // use the new one.
273 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
274 return Res;
275}
276
277SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
278 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
279 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
280 N->getMemoryVT(),
281 N->getChain(), N->getBasePtr(),
282 Op2, N->getMemOperand());
283 // Legalize the chain result - switch anything that used the old chain to
284 // use the new one.
285 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
286 return Res;
287}
288
289SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
290 unsigned ResNo) {
291 if (ResNo == 1) {
292 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS)(static_cast <bool> (N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS
) ? void (0) : __assert_fail ("N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 292, __extension__ __PRETTY_FUNCTION__))
;
293 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
294 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
295
296 // Only use the result of getSetCCResultType if it is legal,
297 // otherwise just use the promoted result type (NVT).
298 if (!TLI.isTypeLegal(SVT))
299 SVT = NVT;
300
301 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
302 SDValue Res = DAG.getAtomicCmpSwap(
303 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
304 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
305 N->getMemOperand());
306 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
307 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
308 return Res.getValue(1);
309 }
310
311 // Op2 is used for the comparison and thus must be extended according to the
312 // target's atomic operations. Op3 is merely stored and so can be left alone.
313 SDValue Op2 = N->getOperand(2);
314 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
315 switch (TLI.getExtendForAtomicCmpSwapArg()) {
316 case ISD::SIGN_EXTEND:
317 Op2 = SExtPromotedInteger(Op2);
318 break;
319 case ISD::ZERO_EXTEND:
320 Op2 = ZExtPromotedInteger(Op2);
321 break;
322 case ISD::ANY_EXTEND:
323 Op2 = GetPromotedInteger(Op2);
324 break;
325 default:
326 llvm_unreachable("Invalid atomic op extension")::llvm::llvm_unreachable_internal("Invalid atomic op extension"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 326)
;
327 }
328
329 SDVTList VTs =
330 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
331 SDValue Res = DAG.getAtomicCmpSwap(
332 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
333 N->getBasePtr(), Op2, Op3, N->getMemOperand());
334 // Update the use to N with the newly created Res.
335 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
336 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
337 return Res;
338}
339
340SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
341 SDValue InOp = N->getOperand(0);
342 EVT InVT = InOp.getValueType();
343 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
344 EVT OutVT = N->getValueType(0);
345 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
346 SDLoc dl(N);
347
348 switch (getTypeAction(InVT)) {
349 case TargetLowering::TypeLegal:
350 break;
351 case TargetLowering::TypePromoteInteger:
352 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
353 // The input promotes to the same size. Convert the promoted value.
354 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
355 break;
356 case TargetLowering::TypeSoftenFloat:
357 // Promote the integer operand by hand.
358 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
359 case TargetLowering::TypeSoftPromoteHalf:
360 // Promote the integer operand by hand.
361 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp));
362 case TargetLowering::TypePromoteFloat: {
363 // Convert the promoted float by hand.
364 if (!NOutVT.isVector())
365 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
366 break;
367 }
368 case TargetLowering::TypeExpandInteger:
369 case TargetLowering::TypeExpandFloat:
370 break;
371 case TargetLowering::TypeScalarizeVector:
372 // Convert the element to an integer and promote it by hand.
373 if (!NOutVT.isVector())
374 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
375 BitConvertToInteger(GetScalarizedVector(InOp)));
376 break;
377 case TargetLowering::TypeScalarizeScalableVector:
378 report_fatal_error("Scalarization of scalable vectors is not supported.");
379 case TargetLowering::TypeSplitVector: {
380 if (!NOutVT.isVector()) {
381 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
382 // pieces of the input into integers and reassemble in the final type.
383 SDValue Lo, Hi;
384 GetSplitVector(N->getOperand(0), Lo, Hi);
385 Lo = BitConvertToInteger(Lo);
386 Hi = BitConvertToInteger(Hi);
387
388 if (DAG.getDataLayout().isBigEndian())
389 std::swap(Lo, Hi);
390
391 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
392 EVT::getIntegerVT(*DAG.getContext(),
393 NOutVT.getSizeInBits()),
394 JoinIntegers(Lo, Hi));
395 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
396 }
397 break;
398 }
399 case TargetLowering::TypeWidenVector:
400 // The input is widened to the same size. Convert to the widened value.
401 // Make sure that the outgoing value is not a vector, because this would
402 // make us bitcast between two vectors which are legalized in different ways.
403 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) {
404 SDValue Res =
405 DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
406
407 // For big endian targets we need to shift the casted value or the
408 // interesting bits will end up at the wrong place.
409 if (DAG.getDataLayout().isBigEndian()) {
410 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
411 EVT ShiftAmtTy = TLI.getShiftAmountTy(NOutVT, DAG.getDataLayout());
412 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!")(static_cast <bool> (ShiftAmt < NOutVT.getSizeInBits
() && "Too large shift amount!") ? void (0) : __assert_fail
("ShiftAmt < NOutVT.getSizeInBits() && \"Too large shift amount!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 412, __extension__ __PRETTY_FUNCTION__))
;
413 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res,
414 DAG.getConstant(ShiftAmt, dl, ShiftAmtTy));
415 }
416 return Res;
417 }
418 // If the output type is also a vector and widening it to the same size
419 // as the widened input type would be a legal type, we can widen the bitcast
420 // and handle the promotion after.
421 if (NOutVT.isVector()) {
422 unsigned WidenInSize = NInVT.getSizeInBits();
423 unsigned OutSize = OutVT.getSizeInBits();
424 if (WidenInSize % OutSize == 0) {
425 unsigned Scale = WidenInSize / OutSize;
426 EVT WideOutVT = EVT::getVectorVT(*DAG.getContext(),
427 OutVT.getVectorElementType(),
428 OutVT.getVectorNumElements() * Scale);
429 if (isTypeLegal(WideOutVT)) {
430 InOp = DAG.getBitcast(WideOutVT, GetWidenedVector(InOp));
431 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp,
432 DAG.getVectorIdxConstant(0, dl));
433 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp);
434 }
435 }
436 }
437 }
438
439 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
440 CreateStackStoreLoad(InOp, OutVT));
441}
442
443// Helper for BSWAP/BITREVERSE promotion to ensure we can fit any shift amount
444// in the VT returned by getShiftAmountTy and to return a safe VT if we can't.
445static EVT getShiftAmountTyForConstant(EVT VT, const TargetLowering &TLI,
446 SelectionDAG &DAG) {
447 EVT ShiftVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
448 // If any possible shift value won't fit in the prefered type, just use
449 // something safe. It will be legalized when the shift is expanded.
450 if (!ShiftVT.isVector() &&
451 ShiftVT.getSizeInBits() < Log2_32_Ceil(VT.getSizeInBits()))
452 ShiftVT = MVT::i32;
453 return ShiftVT;
454}
455
456SDValue DAGTypeLegalizer::PromoteIntRes_FREEZE(SDNode *N) {
457 SDValue V = GetPromotedInteger(N->getOperand(0));
458 return DAG.getNode(ISD::FREEZE, SDLoc(N),
459 V.getValueType(), V);
460}
461
462SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
463 SDValue Op = GetPromotedInteger(N->getOperand(0));
464 EVT OVT = N->getValueType(0);
465 EVT NVT = Op.getValueType();
466 SDLoc dl(N);
467
468 // If the larger BSWAP isn't supported by the target, try to expand now.
469 // If we expand later we'll end up with more operations since we lost the
470 // original type. We only do this for scalars since we have a shuffle
471 // based lowering for vectors in LegalizeVectorOps.
472 if (!OVT.isVector() &&
473 !TLI.isOperationLegalOrCustomOrPromote(ISD::BSWAP, NVT)) {
474 if (SDValue Res = TLI.expandBSWAP(N, DAG))
475 return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
476 }
477
478 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
479 EVT ShiftVT = getShiftAmountTyForConstant(NVT, TLI, DAG);
480 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
481 DAG.getConstant(DiffBits, dl, ShiftVT));
482}
483
484SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
485 SDValue Op = GetPromotedInteger(N->getOperand(0));
486 EVT OVT = N->getValueType(0);
487 EVT NVT = Op.getValueType();
488 SDLoc dl(N);
489
490 // If the larger BITREVERSE isn't supported by the target, try to expand now.
491 // If we expand later we'll end up with more operations since we lost the
492 // original type. We only do this for scalars since we have a shuffle
493 // based lowering for vectors in LegalizeVectorOps.
494 if (!OVT.isVector() && OVT.isSimple() &&
495 !TLI.isOperationLegalOrCustomOrPromote(ISD::BITREVERSE, NVT)) {
496 if (SDValue Res = TLI.expandBITREVERSE(N, DAG))
497 return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res);
498 }
499
500 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
501 EVT ShiftVT = getShiftAmountTyForConstant(NVT, TLI, DAG);
502 return DAG.getNode(ISD::SRL, dl, NVT,
503 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
504 DAG.getConstant(DiffBits, dl, ShiftVT));
505}
506
507SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
508 // The pair element type may be legal, or may not promote to the same type as
509 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
510 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
511 TLI.getTypeToTransformTo(*DAG.getContext(),
512 N->getValueType(0)), JoinIntegers(N->getOperand(0),
513 N->getOperand(1)));
514}
515
516SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
517 EVT VT = N->getValueType(0);
518 // FIXME there is no actual debug info here
519 SDLoc dl(N);
520 // Zero extend things like i1, sign extend everything else. It shouldn't
521 // matter in theory which one we pick, but this tends to give better code?
522 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
523 SDValue Result = DAG.getNode(Opc, dl,
524 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
525 SDValue(N, 0));
526 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?")(static_cast <bool> (isa<ConstantSDNode>(Result) &&
"Didn't constant fold ext?") ? void (0) : __assert_fail ("isa<ConstantSDNode>(Result) && \"Didn't constant fold ext?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 526, __extension__ __PRETTY_FUNCTION__))
;
527 return Result;
528}
529
530SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
531 // Zero extend to the promoted type and do the count there.
532 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
533 SDLoc dl(N);
534 EVT OVT = N->getValueType(0);
535 EVT NVT = Op.getValueType();
536 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
537 // Subtract off the extra leading bits in the bigger type.
538 return DAG.getNode(
539 ISD::SUB, dl, NVT, Op,
540 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
541 NVT));
542}
543
544SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP_PARITY(SDNode *N) {
545 // Zero extend to the promoted type and do the count or parity there.
546 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
547 return DAG.getNode(N->getOpcode(), SDLoc(N), Op.getValueType(), Op);
548}
549
550SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
551 SDValue Op = GetPromotedInteger(N->getOperand(0));
552 EVT OVT = N->getValueType(0);
553 EVT NVT = Op.getValueType();
554 SDLoc dl(N);
555 if (N->getOpcode() == ISD::CTTZ) {
556 // The count is the same in the promoted type except if the original
557 // value was zero. This can be handled by setting the bit just off
558 // the top of the original type.
559 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
560 OVT.getScalarSizeInBits());
561 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
562 }
563 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
564}
565
566SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
567 SDLoc dl(N);
568 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
569
570 SDValue Op0 = N->getOperand(0);
571 SDValue Op1 = N->getOperand(1);
572
573 // If the input also needs to be promoted, do that first so we can get a
574 // get a good idea for the output type.
575 if (TLI.getTypeAction(*DAG.getContext(), Op0.getValueType())
576 == TargetLowering::TypePromoteInteger) {
577 SDValue In = GetPromotedInteger(Op0);
578
579 // If the new type is larger than NVT, use it. We probably won't need to
580 // promote it again.
581 EVT SVT = In.getValueType().getScalarType();
582 if (SVT.bitsGE(NVT)) {
583 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1);
584 return DAG.getAnyExtOrTrunc(Ext, dl, NVT);
585 }
586 }
587
588 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1);
589}
590
591SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
592 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
593 unsigned NewOpc = N->getOpcode();
594 SDLoc dl(N);
595
596 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
597 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
598 // and SINT conversions are Custom, there is no way to tell which is
599 // preferable. We choose SINT because that's the right thing on PPC.)
600 if (N->getOpcode() == ISD::FP_TO_UINT &&
601 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
602 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
603 NewOpc = ISD::FP_TO_SINT;
604
605 if (N->getOpcode() == ISD::STRICT_FP_TO_UINT &&
606 !TLI.isOperationLegal(ISD::STRICT_FP_TO_UINT, NVT) &&
607 TLI.isOperationLegalOrCustom(ISD::STRICT_FP_TO_SINT, NVT))
608 NewOpc = ISD::STRICT_FP_TO_SINT;
609
610 SDValue Res;
611 if (N->isStrictFPOpcode()) {
612 Res = DAG.getNode(NewOpc, dl, {NVT, MVT::Other},
613 {N->getOperand(0), N->getOperand(1)});
614 // Legalize the chain result - switch anything that used the old chain to
615 // use the new one.
616 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
617 } else
618 Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
619
620 // Assert that the converted value fits in the original type. If it doesn't
621 // (eg: because the value being converted is too big), then the result of the
622 // original operation was undefined anyway, so the assert is still correct.
623 //
624 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
625 // before legalization: fp-to-uint16, 65534. -> 0xfffe
626 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
627 return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
628 N->getOpcode() == ISD::STRICT_FP_TO_UINT) ?
629 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
630 DAG.getValueType(N->getValueType(0).getScalarType()));
631}
632
633SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT_SAT(SDNode *N) {
634 // Promote the result type, while keeping the original width in Op1.
635 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
636 SDLoc dl(N);
637 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0),
638 N->getOperand(1));
639}
640
641SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
642 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
643 SDLoc dl(N);
644
645 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
646}
647
648SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) {
649 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
650 SDLoc dl(N);
651
652 SDValue Res =
653 DAG.getNode(N->getOpcode(), dl, {NVT, MVT::Other}, N->getOperand(0));
654
655 // Legalize the chain result - switch anything that used the old chain to
656 // use the new one.
657 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
658 return Res;
659}
660
661SDValue DAGTypeLegalizer::PromoteIntRes_ISNAN(SDNode *N) {
662 SDLoc DL(N);
663 EVT ResultVT = N->getValueType(0);
664 EVT NewResultVT = TLI.getTypeToTransformTo(*DAG.getContext(), ResultVT);
665 return DAG.getNode(N->getOpcode(), DL, NewResultVT, N->getOperand(0),
666 N->getFlags());
667}
668
669SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
670 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
671 SDLoc dl(N);
672
673 if (getTypeAction(N->getOperand(0).getValueType())
674 == TargetLowering::TypePromoteInteger) {
675 SDValue Res = GetPromotedInteger(N->getOperand(0));
676 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!")(static_cast <bool> (Res.getValueType().bitsLE(NVT) &&
"Extension doesn't make sense!") ? void (0) : __assert_fail (
"Res.getValueType().bitsLE(NVT) && \"Extension doesn't make sense!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 676, __extension__ __PRETTY_FUNCTION__))
;
677
678 // If the result and operand types are the same after promotion, simplify
679 // to an in-register extension.
680 if (NVT == Res.getValueType()) {
681 // The high bits are not guaranteed to be anything. Insert an extend.
682 if (N->getOpcode() == ISD::SIGN_EXTEND)
683 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
684 DAG.getValueType(N->getOperand(0).getValueType()));
685 if (N->getOpcode() == ISD::ZERO_EXTEND)
686 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
687 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!")(static_cast <bool> (N->getOpcode() == ISD::ANY_EXTEND
&& "Unknown integer extension!") ? void (0) : __assert_fail
("N->getOpcode() == ISD::ANY_EXTEND && \"Unknown integer extension!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 687, __extension__ __PRETTY_FUNCTION__))
;
688 return Res;
689 }
690 }
691
692 // Otherwise, just extend the original operand all the way to the larger type.
693 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
694}
695
696SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
697 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!")(static_cast <bool> (ISD::isUNINDEXEDLoad(N) &&
"Indexed load during type legalization!") ? void (0) : __assert_fail
("ISD::isUNINDEXEDLoad(N) && \"Indexed load during type legalization!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 697, __extension__ __PRETTY_FUNCTION__))
;
698 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
699 ISD::LoadExtType ExtType =
700 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
701 SDLoc dl(N);
702 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
703 N->getMemoryVT(), N->getMemOperand());
704
705 // Legalize the chain result - switch anything that used the old chain to
706 // use the new one.
707 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
708 return Res;
709}
710
711SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
712 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
713 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
714
715 SDLoc dl(N);
716 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
717 N->getOffset(), N->getMask(), ExtPassThru,
718 N->getMemoryVT(), N->getMemOperand(),
719 N->getAddressingMode(), ISD::EXTLOAD);
720 // Legalize the chain result - switch anything that used the old chain to
721 // use the new one.
722 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
723 return Res;
724}
725
726SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
727 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
728 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
729 assert(NVT == ExtPassThru.getValueType() &&(static_cast <bool> (NVT == ExtPassThru.getValueType() &&
"Gather result type and the passThru argument type should be the same"
) ? void (0) : __assert_fail ("NVT == ExtPassThru.getValueType() && \"Gather result type and the passThru argument type should be the same\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 730, __extension__ __PRETTY_FUNCTION__))
730 "Gather result type and the passThru argument type should be the same")(static_cast <bool> (NVT == ExtPassThru.getValueType() &&
"Gather result type and the passThru argument type should be the same"
) ? void (0) : __assert_fail ("NVT == ExtPassThru.getValueType() && \"Gather result type and the passThru argument type should be the same\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 730, __extension__ __PRETTY_FUNCTION__))
;
731
732 ISD::LoadExtType ExtType = N->getExtensionType();
733 if (ExtType == ISD::NON_EXTLOAD)
734 ExtType = ISD::EXTLOAD;
735
736 SDLoc dl(N);
737 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
738 N->getIndex(), N->getScale() };
739 SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
740 N->getMemoryVT(), dl, Ops,
741 N->getMemOperand(), N->getIndexType(),
742 ExtType);
743 // Legalize the chain result - switch anything that used the old chain to
744 // use the new one.
745 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
746 return Res;
747}
748
749/// Promote the overflow flag of an overflowing arithmetic node.
750SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
751 // Change the return type of the boolean result while obeying
752 // getSetCCResultType.
753 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
754 EVT VT = N->getValueType(0);
755 EVT SVT = getSetCCResultType(VT);
756 SDValue Ops[3] = { N->getOperand(0), N->getOperand(1) };
757 unsigned NumOps = N->getNumOperands();
758 assert(NumOps <= 3 && "Too many operands")(static_cast <bool> (NumOps <= 3 && "Too many operands"
) ? void (0) : __assert_fail ("NumOps <= 3 && \"Too many operands\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 758, __extension__ __PRETTY_FUNCTION__))
;
759 if (NumOps == 3)
760 Ops[2] = N->getOperand(2);
761
762 SDLoc dl(N);
763 SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT),
764 makeArrayRef(Ops, NumOps));
765
766 // Modified the sum result - switch anything that used the old sum to use
767 // the new one.
768 ReplaceValueWith(SDValue(N, 0), Res);
769
770 // Convert to the expected type.
771 return DAG.getBoolExtOrTrunc(Res.getValue(1), dl, NVT, VT);
772}
773
774SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSHLSAT(SDNode *N) {
775 // If the promoted type is legal, we can convert this to:
776 // 1. ANY_EXTEND iN to iM
777 // 2. SHL by M-N
778 // 3. [US][ADD|SUB|SHL]SAT
779 // 4. L/ASHR by M-N
780 // Else it is more efficient to convert this to a min and a max
781 // operation in the higher precision arithmetic.
782 SDLoc dl(N);
783 SDValue Op1 = N->getOperand(0);
784 SDValue Op2 = N->getOperand(1);
785 unsigned OldBits = Op1.getScalarValueSizeInBits();
786
787 unsigned Opcode = N->getOpcode();
788 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT;
789
790 SDValue Op1Promoted, Op2Promoted;
791 if (IsShift) {
792 Op1Promoted = GetPromotedInteger(Op1);
793 Op2Promoted = ZExtPromotedInteger(Op2);
794 } else if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
795 Op1Promoted = ZExtPromotedInteger(Op1);
796 Op2Promoted = ZExtPromotedInteger(Op2);
797 } else {
798 Op1Promoted = SExtPromotedInteger(Op1);
799 Op2Promoted = SExtPromotedInteger(Op2);
800 }
801 EVT PromotedType = Op1Promoted.getValueType();
802 unsigned NewBits = PromotedType.getScalarSizeInBits();
803
804 if (Opcode == ISD::UADDSAT) {
805 APInt MaxVal = APInt::getAllOnesValue(OldBits).zext(NewBits);
806 SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
807 SDValue Add =
808 DAG.getNode(ISD::ADD, dl, PromotedType, Op1Promoted, Op2Promoted);
809 return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
810 }
811
812 // USUBSAT can always be promoted as long as we have zero-extended the args.
813 if (Opcode == ISD::USUBSAT)
814 return DAG.getNode(ISD::USUBSAT, dl, PromotedType, Op1Promoted,
815 Op2Promoted);
816
817 // Shift cannot use a min/max expansion, we can't detect overflow if all of
818 // the bits have been shifted out.
819 if (IsShift || TLI.isOperationLegal(Opcode, PromotedType)) {
820 unsigned ShiftOp;
821 switch (Opcode) {
822 case ISD::SADDSAT:
823 case ISD::SSUBSAT:
824 case ISD::SSHLSAT:
825 ShiftOp = ISD::SRA;
826 break;
827 case ISD::USHLSAT:
828 ShiftOp = ISD::SRL;
829 break;
830 default:
831 llvm_unreachable("Expected opcode to be signed or unsigned saturation "::llvm::llvm_unreachable_internal("Expected opcode to be signed or unsigned saturation "
"addition, subtraction or left shift", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 832)
832 "addition, subtraction or left shift")::llvm::llvm_unreachable_internal("Expected opcode to be signed or unsigned saturation "
"addition, subtraction or left shift", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 832)
;
833 }
834
835 unsigned SHLAmount = NewBits - OldBits;
836 EVT SHVT = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
837 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT);
838 Op1Promoted =
839 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
840 if (!IsShift)
841 Op2Promoted =
842 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
843
844 SDValue Result =
845 DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
846 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
847 }
848
849 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
850 APInt MinVal = APInt::getSignedMinValue(OldBits).sext(NewBits);
851 APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
852 SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
853 SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
854 SDValue Result =
855 DAG.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
856 Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
857 Result = DAG.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
858 return Result;
859}
860
861SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
862 // Can just promote the operands then continue with operation.
863 SDLoc dl(N);
864 SDValue Op1Promoted, Op2Promoted;
865 bool Signed =
866 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
867 bool Saturating =
868 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
869 if (Signed) {
870 Op1Promoted = SExtPromotedInteger(N->getOperand(0));
871 Op2Promoted = SExtPromotedInteger(N->getOperand(1));
872 } else {
873 Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
874 Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
875 }
876 EVT OldType = N->getOperand(0).getValueType();
877 EVT PromotedType = Op1Promoted.getValueType();
878 unsigned DiffSize =
879 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
880
881 if (Saturating) {
882 // Promoting the operand and result values changes the saturation width,
883 // which is extends the values that we clamp to on saturation. This could be
884 // resolved by shifting one of the operands the same amount, which would
885 // also shift the result we compare against, then shifting back.
886 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
887 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
888 DAG.getConstant(DiffSize, dl, ShiftTy));
889 SDValue Result = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
890 Op2Promoted, N->getOperand(2));
891 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
892 return DAG.getNode(ShiftOp, dl, PromotedType, Result,
893 DAG.getConstant(DiffSize, dl, ShiftTy));
894 }
895 return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted,
896 N->getOperand(2));
897}
898
899static SDValue SaturateWidenedDIVFIX(SDValue V, SDLoc &dl,
900 unsigned SatW, bool Signed,
901 const TargetLowering &TLI,
902 SelectionDAG &DAG) {
903 EVT VT = V.getValueType();
904 unsigned VTW = VT.getScalarSizeInBits();
905
906 if (!Signed) {
907 // Saturate to the unsigned maximum by getting the minimum of V and the
908 // maximum.
909 return DAG.getNode(ISD::UMIN, dl, VT, V,
910 DAG.getConstant(APInt::getLowBitsSet(VTW, SatW),
911 dl, VT));
912 }
913
914 // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
915 // signed minimum of it and V.
916 V = DAG.getNode(ISD::SMIN, dl, VT, V,
917 DAG.getConstant(APInt::getLowBitsSet(VTW, SatW - 1),
918 dl, VT));
919 // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
920 // signed maximum of it and V.
921 V = DAG.getNode(ISD::SMAX, dl, VT, V,
922 DAG.getConstant(APInt::getHighBitsSet(VTW, VTW - SatW + 1),
923 dl, VT));
924 return V;
925}
926
927static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
928 unsigned Scale, const TargetLowering &TLI,
929 SelectionDAG &DAG, unsigned SatW = 0) {
930 EVT VT = LHS.getValueType();
931 unsigned VTSize = VT.getScalarSizeInBits();
932 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
933 N->getOpcode() == ISD::SDIVFIXSAT;
934 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
935 N->getOpcode() == ISD::UDIVFIXSAT;
936
937 SDLoc dl(N);
938 // Widen the types by a factor of two. This is guaranteed to expand, since it
939 // will always have enough high bits in the LHS to shift into.
940 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VTSize * 2);
941 if (VT.isVector())
942 WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
943 VT.getVectorElementCount());
944 if (Signed) {
945 LHS = DAG.getSExtOrTrunc(LHS, dl, WideVT);
946 RHS = DAG.getSExtOrTrunc(RHS, dl, WideVT);
947 } else {
948 LHS = DAG.getZExtOrTrunc(LHS, dl, WideVT);
949 RHS = DAG.getZExtOrTrunc(RHS, dl, WideVT);
950 }
951
952 SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, LHS, RHS, Scale,
953 DAG);
954 assert(Res && "Expanding DIVFIX with wide type failed?")(static_cast <bool> (Res && "Expanding DIVFIX with wide type failed?"
) ? void (0) : __assert_fail ("Res && \"Expanding DIVFIX with wide type failed?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 954, __extension__ __PRETTY_FUNCTION__))
;
955 if (Saturating) {
956 // If the caller has told us to saturate at something less, use that width
957 // instead of the type before doubling. However, it cannot be more than
958 // what we just widened!
959 assert(SatW <= VTSize &&(static_cast <bool> (SatW <= VTSize && "Tried to saturate to more than the original type?"
) ? void (0) : __assert_fail ("SatW <= VTSize && \"Tried to saturate to more than the original type?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 960, __extension__ __PRETTY_FUNCTION__))
960 "Tried to saturate to more than the original type?")(static_cast <bool> (SatW <= VTSize && "Tried to saturate to more than the original type?"
) ? void (0) : __assert_fail ("SatW <= VTSize && \"Tried to saturate to more than the original type?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 960, __extension__ __PRETTY_FUNCTION__))
;
961 Res = SaturateWidenedDIVFIX(Res, dl, SatW == 0 ? VTSize : SatW, Signed,
962 TLI, DAG);
963 }
964 return DAG.getZExtOrTrunc(Res, dl, VT);
965}
966
967SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
968 SDLoc dl(N);
969 SDValue Op1Promoted, Op2Promoted;
970 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
971 N->getOpcode() == ISD::SDIVFIXSAT;
972 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
973 N->getOpcode() == ISD::UDIVFIXSAT;
974 if (Signed) {
975 Op1Promoted = SExtPromotedInteger(N->getOperand(0));
976 Op2Promoted = SExtPromotedInteger(N->getOperand(1));
977 } else {
978 Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
979 Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
980 }
981 EVT PromotedType = Op1Promoted.getValueType();
982 unsigned Scale = N->getConstantOperandVal(2);
983
984 // If the type is already legal and the operation is legal in that type, we
985 // should not early expand.
986 if (TLI.isTypeLegal(PromotedType)) {
987 TargetLowering::LegalizeAction Action =
988 TLI.getFixedPointOperationAction(N->getOpcode(), PromotedType, Scale);
989 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
990 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
991 unsigned Diff = PromotedType.getScalarSizeInBits() -
992 N->getValueType(0).getScalarSizeInBits();
993 if (Saturating)
994 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
995 DAG.getConstant(Diff, dl, ShiftTy));
996 SDValue Res = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
997 Op2Promoted, N->getOperand(2));
998 if (Saturating)
999 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res,
1000 DAG.getConstant(Diff, dl, ShiftTy));
1001 return Res;
1002 }
1003 }
1004
1005 // See if we can perform the division in this type without expanding.
1006 if (SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, Op1Promoted,
1007 Op2Promoted, Scale, DAG)) {
1008 if (Saturating)
1009 Res = SaturateWidenedDIVFIX(Res, dl,
1010 N->getValueType(0).getScalarSizeInBits(),
1011 Signed, TLI, DAG);
1012 return Res;
1013 }
1014 // If we cannot, expand it to twice the type width. If we are saturating, give
1015 // it the original width as a saturating width so we don't need to emit
1016 // two saturations.
1017 return earlyExpandDIVFIX(N, Op1Promoted, Op2Promoted, Scale, TLI, DAG,
1018 N->getValueType(0).getScalarSizeInBits());
1019}
1020
1021SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
1022 if (ResNo == 1)
1023 return PromoteIntRes_Overflow(N);
1024
1025 // The operation overflowed iff the result in the larger type is not the
1026 // sign extension of its truncation to the original type.
1027 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1028 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1029 EVT OVT = N->getOperand(0).getValueType();
1030 EVT NVT = LHS.getValueType();
1031 SDLoc dl(N);
1032
1033 // Do the arithmetic in the larger type.
1034 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
1035 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
1036
1037 // Calculate the overflow flag: sign extend the arithmetic result from
1038 // the original type.
1039 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
1040 DAG.getValueType(OVT));
1041 // Overflowed if and only if this is not equal to Res.
1042 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
1043
1044 // Use the calculated overflow everywhere.
1045 ReplaceValueWith(SDValue(N, 1), Ofl);
1046
1047 return Res;
1048}
1049
1050SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
1051 SDValue LHS = GetPromotedInteger(N->getOperand(1));
1052 SDValue RHS = GetPromotedInteger(N->getOperand(2));
1053 return DAG.getSelect(SDLoc(N),
1054 LHS.getValueType(), N->getOperand(0), LHS, RHS);
1055}
1056
1057SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
1058 SDValue Mask = N->getOperand(0);
1059
1060 SDValue LHS = GetPromotedInteger(N->getOperand(1));
1061 SDValue RHS = GetPromotedInteger(N->getOperand(2));
1062 return DAG.getNode(ISD::VSELECT, SDLoc(N),
1063 LHS.getValueType(), Mask, LHS, RHS);
1064}
1065
1066SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
1067 SDValue LHS = GetPromotedInteger(N->getOperand(2));
1068 SDValue RHS = GetPromotedInteger(N->getOperand(3));
1069 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
1070 LHS.getValueType(), N->getOperand(0),
1071 N->getOperand(1), LHS, RHS, N->getOperand(4));
1072}
1073
1074SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
1075 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
1076 EVT InVT = N->getOperand(OpNo).getValueType();
1077 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1078
1079 EVT SVT = getSetCCResultType(InVT);
1080
1081 // If we got back a type that needs to be promoted, this likely means the
1082 // the input type also needs to be promoted. So get the promoted type for
1083 // the input and try the query again.
1084 if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) {
1085 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
1086 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
1087 SVT = getSetCCResultType(InVT);
1088 } else {
1089 // Input type isn't promoted, just use the default promoted type.
1090 SVT = NVT;
1091 }
1092 }
1093
1094 SDLoc dl(N);
1095 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&(static_cast <bool> (SVT.isVector() == N->getOperand
(OpNo).getValueType().isVector() && "Vector compare must return a vector result!"
) ? void (0) : __assert_fail ("SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() && \"Vector compare must return a vector result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1096, __extension__ __PRETTY_FUNCTION__))
1096 "Vector compare must return a vector result!")(static_cast <bool> (SVT.isVector() == N->getOperand
(OpNo).getValueType().isVector() && "Vector compare must return a vector result!"
) ? void (0) : __assert_fail ("SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() && \"Vector compare must return a vector result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1096, __extension__ __PRETTY_FUNCTION__))
;
1097
1098 // Get the SETCC result using the canonical SETCC type.
1099 SDValue SetCC;
1100 if (N->isStrictFPOpcode()) {
1101 EVT VTs[] = {SVT, MVT::Other};
1102 SDValue Opers[] = {N->getOperand(0), N->getOperand(1),
1103 N->getOperand(2), N->getOperand(3)};
1104 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers);
1105 // Legalize the chain result - switch anything that used the old chain to
1106 // use the new one.
1107 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1));
1108 } else
1109 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
1110 N->getOperand(1), N->getOperand(2));
1111
1112 // Convert to the expected type.
1113 return DAG.getSExtOrTrunc(SetCC, dl, NVT);
1114}
1115
1116SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1117 SDValue LHS = GetPromotedInteger(N->getOperand(0));
1118 SDValue RHS = N->getOperand(1);
1119 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1120 RHS = ZExtPromotedInteger(RHS);
1121 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
1122}
1123
1124SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1125 SDValue Op = GetPromotedInteger(N->getOperand(0));
1126 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
1127 Op.getValueType(), Op, N->getOperand(1));
1128}
1129
1130SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1131 // The input may have strange things in the top bits of the registers, but
1132 // these operations don't care. They may have weird bits going out, but
1133 // that too is okay if they are integer operations.
1134 SDValue LHS = GetPromotedInteger(N->getOperand(0));
1135 SDValue RHS = GetPromotedInteger(N->getOperand(1));
1136 return DAG.getNode(N->getOpcode(), SDLoc(N),
1137 LHS.getValueType(), LHS, RHS);
1138}
1139
1140SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1141 // Sign extend the input.
1142 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1143 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1144 return DAG.getNode(N->getOpcode(), SDLoc(N),
1145 LHS.getValueType(), LHS, RHS);
1146}
1147
1148SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1149 // Zero extend the input.
1150 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1151 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1152 return DAG.getNode(N->getOpcode(), SDLoc(N),
1153 LHS.getValueType(), LHS, RHS);
1154}
1155
1156SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1157 // It doesn't matter if we sign extend or zero extend in the inputs. So do
1158 // whatever is best for the target.
1159 SDValue LHS = SExtOrZExtPromotedInteger(N->getOperand(0));
1160 SDValue RHS = SExtOrZExtPromotedInteger(N->getOperand(1));
1161 return DAG.getNode(N->getOpcode(), SDLoc(N),
1162 LHS.getValueType(), LHS, RHS);
1163}
1164
1165SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1166 // The input value must be properly sign extended.
1167 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1168 SDValue RHS = N->getOperand(1);
1169 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1170 RHS = ZExtPromotedInteger(RHS);
1171 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
1172}
1173
1174SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1175 // The input value must be properly zero extended.
1176 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1177 SDValue RHS = N->getOperand(1);
1178 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1179 RHS = ZExtPromotedInteger(RHS);
1180 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
1181}
1182
1183SDValue DAGTypeLegalizer::PromoteIntRes_Rotate(SDNode *N) {
1184 // Lower the rotate to shifts and ORs which can be promoted.
1185 SDValue Res;
1186 TLI.expandROT(N, true /*AllowVectorOps*/, Res, DAG);
1187 ReplaceValueWith(SDValue(N, 0), Res);
1188 return SDValue();
1189}
1190
1191SDValue DAGTypeLegalizer::PromoteIntRes_FunnelShift(SDNode *N) {
1192 SDValue Hi = GetPromotedInteger(N->getOperand(0));
1193 SDValue Lo = GetPromotedInteger(N->getOperand(1));
1194 SDValue Amount = GetPromotedInteger(N->getOperand(2));
1195
1196 SDLoc DL(N);
1197 EVT OldVT = N->getOperand(0).getValueType();
1198 EVT VT = Lo.getValueType();
1199 unsigned Opcode = N->getOpcode();
1200 bool IsFSHR = Opcode == ISD::FSHR;
1201 unsigned OldBits = OldVT.getScalarSizeInBits();
1202 unsigned NewBits = VT.getScalarSizeInBits();
1203
1204 // Amount has to be interpreted modulo the old bit width.
1205 Amount =
1206 DAG.getNode(ISD::UREM, DL, VT, Amount, DAG.getConstant(OldBits, DL, VT));
1207
1208 // If the promoted type is twice the size (or more), then we use the
1209 // traditional funnel 'double' shift codegen. This isn't necessary if the
1210 // shift amount is constant.
1211 // fshl(x,y,z) -> (((aext(x) << bw) | zext(y)) << (z % bw)) >> bw.
1212 // fshr(x,y,z) -> (((aext(x) << bw) | zext(y)) >> (z % bw)).
1213 if (NewBits >= (2 * OldBits) && !isa<ConstantSDNode>(Amount) &&
1214 !TLI.isOperationLegalOrCustom(Opcode, VT)) {
1215 SDValue HiShift = DAG.getConstant(OldBits, DL, VT);
1216 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, HiShift);
1217 Lo = DAG.getZeroExtendInReg(Lo, DL, OldVT);
1218 SDValue Res = DAG.getNode(ISD::OR, DL, VT, Hi, Lo);
1219 Res = DAG.getNode(IsFSHR ? ISD::SRL : ISD::SHL, DL, VT, Res, Amount);
1220 if (!IsFSHR)
1221 Res = DAG.getNode(ISD::SRL, DL, VT, Res, HiShift);
1222 return Res;
1223 }
1224
1225 // Shift Lo up to occupy the upper bits of the promoted type.
1226 SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, VT);
1227 Lo = DAG.getNode(ISD::SHL, DL, VT, Lo, ShiftOffset);
1228
1229 // Increase Amount to shift the result into the lower bits of the promoted
1230 // type.
1231 if (IsFSHR)
1232 Amount = DAG.getNode(ISD::ADD, DL, VT, Amount, ShiftOffset);
1233
1234 return DAG.getNode(Opcode, DL, VT, Hi, Lo, Amount);
1235}
1236
1237SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1238 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1239 SDValue Res;
1240 SDValue InOp = N->getOperand(0);
1241 SDLoc dl(N);
1242
1243 switch (getTypeAction(InOp.getValueType())) {
1244 default: llvm_unreachable("Unknown type action!")::llvm::llvm_unreachable_internal("Unknown type action!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1244)
;
1245 case TargetLowering::TypeLegal:
1246 case TargetLowering::TypeExpandInteger:
1247 Res = InOp;
1248 break;
1249 case TargetLowering::TypePromoteInteger:
1250 Res = GetPromotedInteger(InOp);
1251 break;
1252 case TargetLowering::TypeSplitVector: {
1253 EVT InVT = InOp.getValueType();
1254 assert(InVT.isVector() && "Cannot split scalar types")(static_cast <bool> (InVT.isVector() && "Cannot split scalar types"
) ? void (0) : __assert_fail ("InVT.isVector() && \"Cannot split scalar types\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1254, __extension__ __PRETTY_FUNCTION__))
;
1255 ElementCount NumElts = InVT.getVectorElementCount();
1256 assert(NumElts == NVT.getVectorElementCount() &&(static_cast <bool> (NumElts == NVT.getVectorElementCount
() && "Dst and Src must have the same number of elements"
) ? void (0) : __assert_fail ("NumElts == NVT.getVectorElementCount() && \"Dst and Src must have the same number of elements\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1257, __extension__ __PRETTY_FUNCTION__))
1257 "Dst and Src must have the same number of elements")(static_cast <bool> (NumElts == NVT.getVectorElementCount
() && "Dst and Src must have the same number of elements"
) ? void (0) : __assert_fail ("NumElts == NVT.getVectorElementCount() && \"Dst and Src must have the same number of elements\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1257, __extension__ __PRETTY_FUNCTION__))
;
1258 assert(isPowerOf2_32(NumElts.getKnownMinValue()) &&(static_cast <bool> (isPowerOf2_32(NumElts.getKnownMinValue
()) && "Promoted vector type must be a power of two")
? void (0) : __assert_fail ("isPowerOf2_32(NumElts.getKnownMinValue()) && \"Promoted vector type must be a power of two\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1259, __extension__ __PRETTY_FUNCTION__))
1259 "Promoted vector type must be a power of two")(static_cast <bool> (isPowerOf2_32(NumElts.getKnownMinValue
()) && "Promoted vector type must be a power of two")
? void (0) : __assert_fail ("isPowerOf2_32(NumElts.getKnownMinValue()) && \"Promoted vector type must be a power of two\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1259, __extension__ __PRETTY_FUNCTION__))
;
1260
1261 SDValue EOp1, EOp2;
1262 GetSplitVector(InOp, EOp1, EOp2);
1263
1264 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
1265 NumElts.divideCoefficientBy(2));
1266 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
1267 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
1268
1269 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
1270 }
1271 case TargetLowering::TypeWidenVector: {
1272 SDValue WideInOp = GetWidenedVector(InOp);
1273
1274 // Truncate widened InOp.
1275 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1276 EVT TruncVT = EVT::getVectorVT(*DAG.getContext(),
1277 N->getValueType(0).getScalarType(), NumElem);
1278 SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp);
1279
1280 // Zero extend so that the elements are of same type as those of NVT
1281 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(),
1282 NumElem);
1283 SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
1284
1285 // Extract the low NVT subvector.
1286 SDValue ZeroIdx = DAG.getVectorIdxConstant(0, dl);
1287 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
1288 }
1289 }
1290
1291 // Truncate to NVT instead of VT
1292 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
1293}
1294
1295SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1296 if (ResNo == 1)
1297 return PromoteIntRes_Overflow(N);
1298
1299 // The operation overflowed iff the result in the larger type is not the
1300 // zero extension of its truncation to the original type.
1301 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1302 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1303 EVT OVT = N->getOperand(0).getValueType();
1304 EVT NVT = LHS.getValueType();
1305 SDLoc dl(N);
1306
1307 // Do the arithmetic in the larger type.
1308 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1309 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
1310
1311 // Calculate the overflow flag: zero extend the arithmetic result from
1312 // the original type.
1313 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
1314 // Overflowed if and only if this is not equal to Res.
1315 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
1316
1317 // Use the calculated overflow everywhere.
1318 ReplaceValueWith(SDValue(N, 1), Ofl);
1319
1320 return Res;
1321}
1322
1323// Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
1324// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1325// the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
1326SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
1327 if (ResNo == 1)
1328 return PromoteIntRes_Overflow(N);
1329
1330 // We need to sign-extend the operands so the carry value computed by the
1331 // wide operation will be equivalent to the carry value computed by the
1332 // narrow operation.
1333 // An ADDCARRY can generate carry only if any of the operands has its
1334 // most significant bit set. Sign extension propagates the most significant
1335 // bit into the higher bits which means the extra bit that the narrow
1336 // addition would need (i.e. the carry) will be propagated through the higher
1337 // bits of the wide addition.
1338 // A SUBCARRY can generate borrow only if LHS < RHS and this property will be
1339 // preserved by sign extension.
1340 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1341 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1342
1343 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)};
1344
1345 // Do the arithmetic in the wide type.
1346 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
1347 LHS, RHS, N->getOperand(2));
1348
1349 // Update the users of the original carry/borrow value.
1350 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
1351
1352 return SDValue(Res.getNode(), 0);
1353}
1354
1355SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO_CARRY(SDNode *N,
1356 unsigned ResNo) {
1357 assert(ResNo == 1 && "Don't know how to promote other results yet.")(static_cast <bool> (ResNo == 1 && "Don't know how to promote other results yet."
) ? void (0) : __assert_fail ("ResNo == 1 && \"Don't know how to promote other results yet.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1357, __extension__ __PRETTY_FUNCTION__))
;
1358 return PromoteIntRes_Overflow(N);
1359}
1360
1361SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1362 SDValue Op0 = SExtPromotedInteger(N->getOperand(0));
1363 return DAG.getNode(ISD::ABS, SDLoc(N), Op0.getValueType(), Op0);
1364}
1365
1366SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1367 // Promote the overflow bit trivially.
1368 if (ResNo == 1)
1369 return PromoteIntRes_Overflow(N);
1370
1371 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
1372 SDLoc DL(N);
1373 EVT SmallVT = LHS.getValueType();
1374
1375 // To determine if the result overflowed in a larger type, we extend the
1376 // input to the larger type, do the multiply (checking if it overflows),
1377 // then also check the high bits of the result to see if overflow happened
1378 // there.
1379 if (N->getOpcode() == ISD::SMULO) {
1380 LHS = SExtPromotedInteger(LHS);
1381 RHS = SExtPromotedInteger(RHS);
1382 } else {
1383 LHS = ZExtPromotedInteger(LHS);
1384 RHS = ZExtPromotedInteger(RHS);
1385 }
1386 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
1387 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
1388
1389 // Overflow occurred if it occurred in the larger type, or if the high part
1390 // of the result does not zero/sign-extend the low part. Check this second
1391 // possibility first.
1392 SDValue Overflow;
1393 if (N->getOpcode() == ISD::UMULO) {
1394 // Unsigned overflow occurred if the high part is non-zero.
1395 unsigned Shift = SmallVT.getScalarSizeInBits();
1396 EVT ShiftTy = getShiftAmountTyForConstant(Mul.getValueType(), TLI, DAG);
1397 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
1398 DAG.getConstant(Shift, DL, ShiftTy));
1399 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
1400 DAG.getConstant(0, DL, Hi.getValueType()),
1401 ISD::SETNE);
1402 } else {
1403 // Signed overflow occurred if the high part does not sign extend the low.
1404 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
1405 Mul, DAG.getValueType(SmallVT));
1406 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
1407 }
1408
1409 // The only other way for overflow to occur is if the multiplication in the
1410 // larger type itself overflowed.
1411 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
1412 SDValue(Mul.getNode(), 1));
1413
1414 // Use the calculated overflow everywhere.
1415 ReplaceValueWith(SDValue(N, 1), Overflow);
1416 return Mul;
1417}
1418
1419SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1420 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
1421 N->getValueType(0)));
1422}
1423
1424SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
1425 EVT VT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1426
1427 APInt MulImm = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
1428 return DAG.getVScale(SDLoc(N), VT, MulImm.sextOrSelf(VT.getSizeInBits()));
1429}
1430
1431SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1432 SDValue Chain = N->getOperand(0); // Get the chain.
1433 SDValue Ptr = N->getOperand(1); // Get the pointer.
1434 EVT VT = N->getValueType(0);
1435 SDLoc dl(N);
1436
1437 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
1438 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
1439 // The argument is passed as NumRegs registers of type RegVT.
1440
1441 SmallVector<SDValue, 8> Parts(NumRegs);
1442 for (unsigned i = 0; i < NumRegs; ++i) {
1443 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
1444 N->getConstantOperandVal(3));
1445 Chain = Parts[i].getValue(1);
1446 }
1447
1448 // Handle endianness of the load.
1449 if (DAG.getDataLayout().isBigEndian())
1450 std::reverse(Parts.begin(), Parts.end());
1451
1452 // Assemble the parts in the promoted type.
1453 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1454 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
1455 for (unsigned i = 1; i < NumRegs; ++i) {
1456 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
1457 // Shift it to the right position and "or" it in.
1458 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1459 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
1460 TLI.getPointerTy(DAG.getDataLayout())));
1461 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
1462 }
1463
1464 // Modified the chain result - switch anything that used the old chain to
1465 // use the new one.
1466 ReplaceValueWith(SDValue(N, 1), Chain);
1467
1468 return Res;
1469}
1470
1471//===----------------------------------------------------------------------===//
1472// Integer Operand Promotion
1473//===----------------------------------------------------------------------===//
1474
1475/// PromoteIntegerOperand - This method is called when the specified operand of
1476/// the specified node is found to need promotion. At this point, all of the
1477/// result types of the node are known to be legal, but other operands of the
1478/// node may need promotion or expansion as well as the specified one.
1479bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1480 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1481 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1482 SDValue Res = SDValue();
1483 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
1484 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Node has been custom lowered, done\n"
; } } while (false)
;
1485 return false;
1486 }
1487
1488 switch (N->getOpcode()) {
1489 default:
1490 #ifndef NDEBUG
1491 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
1492 N->dump(&DAG); dbgs() << "\n";
1493 #endif
1494 llvm_unreachable("Do not know how to promote this operator's operand!")::llvm::llvm_unreachable_internal("Do not know how to promote this operator's operand!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1494)
;
1495
1496 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
1497 case ISD::ATOMIC_STORE:
1498 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
1499 break;
1500 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
1501 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1502 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
1503 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
1504 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
1505 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
1506 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
1507 case ISD::INSERT_VECTOR_ELT:
1508 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
1509 case ISD::SCALAR_TO_VECTOR:
1510 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
1511 case ISD::SPLAT_VECTOR:
1512 Res = PromoteIntOp_SPLAT_VECTOR(N); break;
1513 case ISD::VSELECT:
1514 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1515 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
1516 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
1517 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1518 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
1519 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
1520 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
1521 OpNo); break;
1522 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
1523 OpNo); break;
1524 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
1525 OpNo); break;
1526 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
1527 OpNo); break;
1528 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
1529 OpNo); break;
1530 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
1531 case ISD::FP16_TO_FP:
1532 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
1533 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
1534 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
1535 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
1536
1537 case ISD::SHL:
1538 case ISD::SRA:
1539 case ISD::SRL:
1540 case ISD::ROTL:
1541 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
1542
1543 case ISD::SADDO_CARRY:
1544 case ISD::SSUBO_CARRY:
1545 case ISD::ADDCARRY:
1546 case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
1547
1548 case ISD::FRAMEADDR:
1549 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
1550
1551 case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break;
1552
1553 case ISD::SMULFIX:
1554 case ISD::SMULFIXSAT:
1555 case ISD::UMULFIX:
1556 case ISD::UMULFIXSAT:
1557 case ISD::SDIVFIX:
1558 case ISD::SDIVFIXSAT:
1559 case ISD::UDIVFIX:
1560 case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
1561
1562 case ISD::FPOWI: Res = PromoteIntOp_FPOWI(N); break;
1563
1564 case ISD::VECREDUCE_ADD:
1565 case ISD::VECREDUCE_MUL:
1566 case ISD::VECREDUCE_AND:
1567 case ISD::VECREDUCE_OR:
1568 case ISD::VECREDUCE_XOR:
1569 case ISD::VECREDUCE_SMAX:
1570 case ISD::VECREDUCE_SMIN:
1571 case ISD::VECREDUCE_UMAX:
1572 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
1573
1574 case ISD::SET_ROUNDING: Res = PromoteIntOp_SET_ROUNDING(N); break;
1575 }
1576
1577 // If the result is null, the sub-method took care of registering results etc.
1578 if (!Res.getNode()) return false;
1579
1580 // If the result is N, the sub-method updated N in place. Tell the legalizer
1581 // core about this.
1582 if (Res.getNode() == N)
1583 return true;
1584
1585 const bool IsStrictFp = N->isStrictFPOpcode();
1586 assert(Res.getValueType() == N->getValueType(0) &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) &&
"Invalid operand expansion") ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1588, __extension__ __PRETTY_FUNCTION__))
1587 N->getNumValues() == (IsStrictFp ? 2 : 1) &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) &&
"Invalid operand expansion") ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1588, __extension__ __PRETTY_FUNCTION__))
1588 "Invalid operand expansion")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) &&
"Invalid operand expansion") ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1588, __extension__ __PRETTY_FUNCTION__))
;
1589 LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Replacing: "; N->dump
(&DAG); dbgs() << " with: "; Res.dump(); } } while
(false)
1590 Res.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Replacing: "; N->dump
(&DAG); dbgs() << " with: "; Res.dump(); } } while
(false)
;
1591
1592 ReplaceValueWith(SDValue(N, 0), Res);
1593 if (IsStrictFp)
1594 ReplaceValueWith(SDValue(N, 1), SDValue(Res.getNode(), 1));
1595
1596 return false;
1597}
1598
1599/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1600/// shared among BR_CC, SELECT_CC, and SETCC handlers.
1601void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
1602 ISD::CondCode CCCode) {
1603 // We have to insert explicit sign or zero extends. Note that we could
1604 // insert sign extends for ALL conditions. For those operations where either
1605 // zero or sign extension would be valid, use SExtOrZExtPromotedInteger
1606 // which will choose the cheapest for the target.
1607 switch (CCCode) {
1608 default: llvm_unreachable("Unknown integer comparison!")::llvm::llvm_unreachable_internal("Unknown integer comparison!"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1608)
;
1609 case ISD::SETEQ:
1610 case ISD::SETNE: {
1611 SDValue OpL = GetPromotedInteger(NewLHS);
1612 SDValue OpR = GetPromotedInteger(NewRHS);
1613
1614 // We would prefer to promote the comparison operand with sign extension.
1615 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
1616 // than the width of NewLHS/NewRH, we can avoid inserting real truncate
1617 // instruction, which is redundant eventually.
1618 unsigned OpLEffectiveBits =
1619 OpL.getScalarValueSizeInBits() - DAG.ComputeNumSignBits(OpL) + 1;
1620 unsigned OpREffectiveBits =
1621 OpR.getScalarValueSizeInBits() - DAG.ComputeNumSignBits(OpR) + 1;
1622 if (OpLEffectiveBits <= NewLHS.getScalarValueSizeInBits() &&
1623 OpREffectiveBits <= NewRHS.getScalarValueSizeInBits()) {
1624 NewLHS = OpL;
1625 NewRHS = OpR;
1626 } else {
1627 NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1628 NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1629 }
1630 break;
1631 }
1632 case ISD::SETUGE:
1633 case ISD::SETUGT:
1634 case ISD::SETULE:
1635 case ISD::SETULT:
1636 NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1637 NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1638 break;
1639 case ISD::SETGE:
1640 case ISD::SETGT:
1641 case ISD::SETLT:
1642 case ISD::SETLE:
1643 NewLHS = SExtPromotedInteger(NewLHS);
1644 NewRHS = SExtPromotedInteger(NewRHS);
1645 break;
1646 }
1647}
1648
1649SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
1650 SDValue Op = GetPromotedInteger(N->getOperand(0));
1651 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
1652}
1653
1654SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
1655 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
1656 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
1657 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand());
1658}
1659
1660SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1661 // This should only occur in unusual situations like bitcasting to an
1662 // x86_fp80, so just turn it into a store+load
1663 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1664}
1665
1666SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1667 assert(OpNo == 2 && "Don't know how to promote this operand!")(static_cast <bool> (OpNo == 2 && "Don't know how to promote this operand!"
) ? void (0) : __assert_fail ("OpNo == 2 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1667, __extension__ __PRETTY_FUNCTION__))
;
1668
1669 SDValue LHS = N->getOperand(2);
1670 SDValue RHS = N->getOperand(3);
1671 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1672
1673 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1674 // legal types.
1675 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1676 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1677 0);
1678}
1679
1680SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1681 assert(OpNo == 1 && "only know how to promote condition")(static_cast <bool> (OpNo == 1 && "only know how to promote condition"
) ? void (0) : __assert_fail ("OpNo == 1 && \"only know how to promote condition\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1681, __extension__ __PRETTY_FUNCTION__))
;
1682
1683 // Promote all the way up to the canonical SetCC type.
1684 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1685
1686 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1687 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1688 N->getOperand(2)), 0);
1689}
1690
1691SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1692 // Since the result type is legal, the operands must promote to it.
1693 EVT OVT = N->getOperand(0).getValueType();
1694 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1695 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1696 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?")(static_cast <bool> (Lo.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Lo.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1696, __extension__ __PRETTY_FUNCTION__))
;
1697 SDLoc dl(N);
1698
1699 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1700 DAG.getConstant(OVT.getSizeInBits(), dl,
1701 TLI.getPointerTy(DAG.getDataLayout())));
1702 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1703}
1704
1705SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1706 // The vector type is legal but the element type is not. This implies
1707 // that the vector is a power-of-two in length and that the element
1708 // type does not have a strange size (eg: it is not i1).
1709 EVT VecVT = N->getValueType(0);
1710 unsigned NumElts = VecVT.getVectorNumElements();
1711 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&(static_cast <bool> (!((NumElts & 1) && (!TLI
.isTypeLegal(VecVT))) && "Legal vector of one illegal element?"
) ? void (0) : __assert_fail ("!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && \"Legal vector of one illegal element?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1712, __extension__ __PRETTY_FUNCTION__))
1712 "Legal vector of one illegal element?")(static_cast <bool> (!((NumElts & 1) && (!TLI
.isTypeLegal(VecVT))) && "Legal vector of one illegal element?"
) ? void (0) : __assert_fail ("!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && \"Legal vector of one illegal element?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1712, __extension__ __PRETTY_FUNCTION__))
;
1713
1714 // Promote the inserted value. The type does not need to match the
1715 // vector element type. Check that any extra bits introduced will be
1716 // truncated away.
1717 assert(N->getOperand(0).getValueSizeInBits() >=(static_cast <bool> (N->getOperand(0).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1719, __extension__ __PRETTY_FUNCTION__))
1718 N->getValueType(0).getScalarSizeInBits() &&(static_cast <bool> (N->getOperand(0).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1719, __extension__ __PRETTY_FUNCTION__))
1719 "Type of inserted value narrower than vector element type!")(static_cast <bool> (N->getOperand(0).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1719, __extension__ __PRETTY_FUNCTION__))
;
1720
1721 SmallVector<SDValue, 16> NewOps;
1722 for (unsigned i = 0; i < NumElts; ++i)
1723 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1724
1725 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1726}
1727
1728SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1729 unsigned OpNo) {
1730 if (OpNo == 1) {
1731 // Promote the inserted value. This is valid because the type does not
1732 // have to match the vector element type.
1733
1734 // Check that any extra bits introduced will be truncated away.
1735 assert(N->getOperand(1).getValueSizeInBits() >=(static_cast <bool> (N->getOperand(1).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1737, __extension__ __PRETTY_FUNCTION__))
1736 N->getValueType(0).getScalarSizeInBits() &&(static_cast <bool> (N->getOperand(1).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1737, __extension__ __PRETTY_FUNCTION__))
1737 "Type of inserted value narrower than vector element type!")(static_cast <bool> (N->getOperand(1).getValueSizeInBits
() >= N->getValueType(0).getScalarSizeInBits() &&
"Type of inserted value narrower than vector element type!")
? void (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1737, __extension__ __PRETTY_FUNCTION__))
;
1738 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1739 GetPromotedInteger(N->getOperand(1)),
1740 N->getOperand(2)),
1741 0);
1742 }
1743
1744 assert(OpNo == 2 && "Different operand and result vector types?")(static_cast <bool> (OpNo == 2 && "Different operand and result vector types?"
) ? void (0) : __assert_fail ("OpNo == 2 && \"Different operand and result vector types?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1744, __extension__ __PRETTY_FUNCTION__))
;
1745
1746 // Promote the index.
1747 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1748 TLI.getVectorIdxTy(DAG.getDataLayout()));
1749 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1750 N->getOperand(1), Idx), 0);
1751}
1752
1753SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1754 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1755 // the operand in place.
1756 return SDValue(DAG.UpdateNodeOperands(N,
1757 GetPromotedInteger(N->getOperand(0))), 0);
1758}
1759
1760SDValue DAGTypeLegalizer::PromoteIntOp_SPLAT_VECTOR(SDNode *N) {
1761 // Integer SPLAT_VECTOR operands are implicitly truncated, so just promote the
1762 // operand in place.
1763 return SDValue(
1764 DAG.UpdateNodeOperands(N, GetPromotedInteger(N->getOperand(0))), 0);
1765}
1766
1767SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1768 assert(OpNo == 0 && "Only know how to promote the condition!")(static_cast <bool> (OpNo == 0 && "Only know how to promote the condition!"
) ? void (0) : __assert_fail ("OpNo == 0 && \"Only know how to promote the condition!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1768, __extension__ __PRETTY_FUNCTION__))
;
1769 SDValue Cond = N->getOperand(0);
1770 EVT OpTy = N->getOperand(1).getValueType();
1771
1772 if (N->getOpcode() == ISD::VSELECT)
1773 if (SDValue Res = WidenVSELECTMask(N))
1774 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
1775 Res, N->getOperand(1), N->getOperand(2));
1776
1777 // Promote all the way up to the canonical SetCC type.
1778 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1779 Cond = PromoteTargetBoolean(Cond, OpVT);
1780
1781 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1782 N->getOperand(2)), 0);
1783}
1784
1785SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1786 assert(OpNo == 0 && "Don't know how to promote this operand!")(static_cast <bool> (OpNo == 0 && "Don't know how to promote this operand!"
) ? void (0) : __assert_fail ("OpNo == 0 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1786, __extension__ __PRETTY_FUNCTION__))
;
1787
1788 SDValue LHS = N->getOperand(0);
1789 SDValue RHS = N->getOperand(1);
1790 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1791
1792 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1793 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1794 N->getOperand(3), N->getOperand(4)), 0);
1795}
1796
1797SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1798 assert(OpNo == 0 && "Don't know how to promote this operand!")(static_cast <bool> (OpNo == 0 && "Don't know how to promote this operand!"
) ? void (0) : __assert_fail ("OpNo == 0 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1798, __extension__ __PRETTY_FUNCTION__))
;
1799
1800 SDValue LHS = N->getOperand(0);
1801 SDValue RHS = N->getOperand(1);
1802 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1803
1804 // The CC (#2) is always legal.
1805 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1806}
1807
1808SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1809 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1810 ZExtPromotedInteger(N->getOperand(1))), 0);
1811}
1812
1813SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1814 SDValue Op = GetPromotedInteger(N->getOperand(0));
1815 SDLoc dl(N);
1816 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1817 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1818 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1819}
1820
1821SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1822 return SDValue(DAG.UpdateNodeOperands(N,
1823 SExtPromotedInteger(N->getOperand(0))), 0);
1824}
1825
1826SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
1827 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1828 SExtPromotedInteger(N->getOperand(1))), 0);
1829}
1830
1831SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1832 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!")(static_cast <bool> (ISD::isUNINDEXEDStore(N) &&
"Indexed store during type legalization!") ? void (0) : __assert_fail
("ISD::isUNINDEXEDStore(N) && \"Indexed store during type legalization!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1832, __extension__ __PRETTY_FUNCTION__))
;
1833 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1834 SDLoc dl(N);
1835
1836 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1837
1838 // Truncate the value and store the result.
1839 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1840 N->getMemoryVT(), N->getMemOperand());
1841}
1842
1843SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
1844 unsigned OpNo) {
1845 SDValue DataOp = N->getValue();
1846 SDValue Mask = N->getMask();
1847
1848 if (OpNo == 4) {
1849 // The Mask. Update in place.
1850 EVT DataVT = DataOp.getValueType();
1851 Mask = PromoteTargetBoolean(Mask, DataVT);
1852 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1853 NewOps[4] = Mask;
1854 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1855 }
1856
1857 assert(OpNo == 1 && "Unexpected operand for promotion")(static_cast <bool> (OpNo == 1 && "Unexpected operand for promotion"
) ? void (0) : __assert_fail ("OpNo == 1 && \"Unexpected operand for promotion\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1857, __extension__ __PRETTY_FUNCTION__))
;
1858 DataOp = GetPromotedInteger(DataOp);
1859
1860 return DAG.getMaskedStore(N->getChain(), SDLoc(N), DataOp, N->getBasePtr(),
1861 N->getOffset(), Mask, N->getMemoryVT(),
1862 N->getMemOperand(), N->getAddressingMode(),
1863 /*IsTruncating*/ true, N->isCompressingStore());
1864}
1865
1866SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
1867 unsigned OpNo) {
1868 assert(OpNo == 3 && "Only know how to promote the mask!")(static_cast <bool> (OpNo == 3 && "Only know how to promote the mask!"
) ? void (0) : __assert_fail ("OpNo == 3 && \"Only know how to promote the mask!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1868, __extension__ __PRETTY_FUNCTION__))
;
1869 EVT DataVT = N->getValueType(0);
1870 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1871 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1872 NewOps[OpNo] = Mask;
1873 SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
1874 if (Res == N)
1875 return SDValue(Res, 0);
1876
1877 // Update triggered CSE, do our own replacement since caller can't.
1878 ReplaceValueWith(SDValue(N, 0), SDValue(Res, 0));
1879 ReplaceValueWith(SDValue(N, 1), SDValue(Res, 1));
1880 return SDValue();
1881}
1882
1883SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
1884 unsigned OpNo) {
1885
1886 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1887 if (OpNo == 2) {
1888 // The Mask
1889 EVT DataVT = N->getValueType(0);
1890 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1891 } else if (OpNo == 4) {
1892 // The Index
1893 if (N->isIndexSigned())
1894 // Need to sign extend the index since the bits will likely be used.
1895 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1896 else
1897 NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
1898 } else
1899 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1900
1901 SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
1902 if (Res == N)
1903 return SDValue(Res, 0);
1904
1905 // Update triggered CSE, do our own replacement since caller can't.
1906 ReplaceValueWith(SDValue(N, 0), SDValue(Res, 0));
1907 ReplaceValueWith(SDValue(N, 1), SDValue(Res, 1));
1908 return SDValue();
1909}
1910
1911SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
1912 unsigned OpNo) {
1913 bool TruncateStore = N->isTruncatingStore();
1914 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1915 if (OpNo == 2) {
1916 // The Mask
1917 EVT DataVT = N->getValue().getValueType();
1918 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1919 } else if (OpNo == 4) {
1920 // The Index
1921 if (N->isIndexSigned())
1922 // Need to sign extend the index since the bits will likely be used.
1923 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1924 else
1925 NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
1926
1927 N->setIndexType(TLI.getCanonicalIndexType(N->getIndexType(),
1928 N->getMemoryVT(), NewOps[OpNo]));
1929 } else {
1930 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1931 TruncateStore = true;
1932 }
1933
1934 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), N->getMemoryVT(),
1935 SDLoc(N), NewOps, N->getMemOperand(),
1936 N->getIndexType(), TruncateStore);
1937}
1938
1939SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1940 SDValue Op = GetPromotedInteger(N->getOperand(0));
1941 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1942}
1943
1944SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1945 return SDValue(DAG.UpdateNodeOperands(N,
1946 ZExtPromotedInteger(N->getOperand(0))), 0);
1947}
1948
1949SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
1950 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1951 ZExtPromotedInteger(N->getOperand(1))), 0);
1952}
1953
1954SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1955 SDLoc dl(N);
1956 SDValue Op = GetPromotedInteger(N->getOperand(0));
1957 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1958 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
1959}
1960
1961SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) {
1962 assert(OpNo == 2 && "Don't know how to promote this operand!")(static_cast <bool> (OpNo == 2 && "Don't know how to promote this operand!"
) ? void (0) : __assert_fail ("OpNo == 2 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1962, __extension__ __PRETTY_FUNCTION__))
;
1963
1964 SDValue LHS = N->getOperand(0);
1965 SDValue RHS = N->getOperand(1);
1966 SDValue Carry = N->getOperand(2);
1967 SDLoc DL(N);
1968
1969 Carry = PromoteTargetBoolean(Carry, LHS.getValueType());
1970
1971 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, Carry), 0);
1972}
1973
1974SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
1975 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
1976 return SDValue(
1977 DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0);
1978}
1979
1980SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
1981 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
1982 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
1983 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
1984}
1985
1986SDValue DAGTypeLegalizer::PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo) {
1987 assert(OpNo > 1 && "Don't know how to promote this operand!")(static_cast <bool> (OpNo > 1 && "Don't know how to promote this operand!"
) ? void (0) : __assert_fail ("OpNo > 1 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1987, __extension__ __PRETTY_FUNCTION__))
;
1988 // Promote the rw, locality, and cache type arguments to a supported integer
1989 // width.
1990 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
1991 SDValue Op3 = ZExtPromotedInteger(N->getOperand(3));
1992 SDValue Op4 = ZExtPromotedInteger(N->getOperand(4));
1993 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
1994 Op2, Op3, Op4),
1995 0);
1996}
1997
1998SDValue DAGTypeLegalizer::PromoteIntOp_FPOWI(SDNode *N) {
1999 // FIXME: Support for promotion of STRICT_FPOWI is not implemented yet.
2000 assert(N->getOpcode() == ISD::FPOWI && "No STRICT_FPOWI support here yet.")(static_cast <bool> (N->getOpcode() == ISD::FPOWI &&
"No STRICT_FPOWI support here yet.") ? void (0) : __assert_fail
("N->getOpcode() == ISD::FPOWI && \"No STRICT_FPOWI support here yet.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2000, __extension__ __PRETTY_FUNCTION__))
;
2001
2002 // The integer operand is the last operand in FPOWI (so the result and
2003 // floating point operand is already type legalized).
2004
2005 // We can't just promote the exponent type in FPOWI, since we want to lower
2006 // the node to a libcall and we if we promote to a type larger than
2007 // sizeof(int) the libcall might not be according to the targets ABI. Instead
2008 // we rewrite to a libcall here directly, letting makeLibCall handle promotion
2009 // if the target accepts it according to shouldSignExtendTypeInLibCall.
2010 RTLIB::Libcall LC = RTLIB::getPOWI(N->getValueType(0));
2011 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fpowi.")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected fpowi.") ? void (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fpowi.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2011, __extension__ __PRETTY_FUNCTION__))
;
2012 if (!TLI.getLibcallName(LC)) {
2013 // Some targets don't have a powi libcall; use pow instead.
2014 // FIXME: Implement this if some target needs it.
2015 DAG.getContext()->emitError("Don't know how to promote fpowi to fpow");
2016 return DAG.getUNDEF(N->getValueType(0));
2017 }
2018 // The exponent should fit in a sizeof(int) type for the libcall to be valid.
2019 assert(DAG.getLibInfo().getIntSize() ==(static_cast <bool> (DAG.getLibInfo().getIntSize() == N
->getOperand(1).getValueType().getSizeInBits() && "POWI exponent should match with sizeof(int) when doing the libcall."
) ? void (0) : __assert_fail ("DAG.getLibInfo().getIntSize() == N->getOperand(1).getValueType().getSizeInBits() && \"POWI exponent should match with sizeof(int) when doing the libcall.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2021, __extension__ __PRETTY_FUNCTION__))
2020 N->getOperand(1).getValueType().getSizeInBits() &&(static_cast <bool> (DAG.getLibInfo().getIntSize() == N
->getOperand(1).getValueType().getSizeInBits() && "POWI exponent should match with sizeof(int) when doing the libcall."
) ? void (0) : __assert_fail ("DAG.getLibInfo().getIntSize() == N->getOperand(1).getValueType().getSizeInBits() && \"POWI exponent should match with sizeof(int) when doing the libcall.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2021, __extension__ __PRETTY_FUNCTION__))
2021 "POWI exponent should match with sizeof(int) when doing the libcall.")(static_cast <bool> (DAG.getLibInfo().getIntSize() == N
->getOperand(1).getValueType().getSizeInBits() && "POWI exponent should match with sizeof(int) when doing the libcall."
) ? void (0) : __assert_fail ("DAG.getLibInfo().getIntSize() == N->getOperand(1).getValueType().getSizeInBits() && \"POWI exponent should match with sizeof(int) when doing the libcall.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2021, __extension__ __PRETTY_FUNCTION__))
;
2022 TargetLowering::MakeLibCallOptions CallOptions;
2023 CallOptions.setSExt(true);
2024 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2025 std::pair<SDValue, SDValue> Tmp =
2026 TLI.makeLibCall(DAG, LC, N->getValueType(0), Ops,
2027 CallOptions, SDLoc(N), SDValue());
2028 ReplaceValueWith(SDValue(N, 0), Tmp.first);
2029 return SDValue();
2030}
2031
2032SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
2033 SDLoc dl(N);
2034 SDValue Op;
2035 switch (N->getOpcode()) {
2036 default: llvm_unreachable("Expected integer vector reduction")::llvm::llvm_unreachable_internal("Expected integer vector reduction"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2036)
;
2037 case ISD::VECREDUCE_ADD:
2038 case ISD::VECREDUCE_MUL:
2039 case ISD::VECREDUCE_AND:
2040 case ISD::VECREDUCE_OR:
2041 case ISD::VECREDUCE_XOR:
2042 Op = GetPromotedInteger(N->getOperand(0));
2043 break;
2044 case ISD::VECREDUCE_SMAX:
2045 case ISD::VECREDUCE_SMIN:
2046 Op = SExtPromotedInteger(N->getOperand(0));
2047 break;
2048 case ISD::VECREDUCE_UMAX:
2049 case ISD::VECREDUCE_UMIN:
2050 Op = ZExtPromotedInteger(N->getOperand(0));
2051 break;
2052 }
2053
2054 EVT EltVT = Op.getValueType().getVectorElementType();
2055 EVT VT = N->getValueType(0);
2056 if (VT.bitsGE(EltVT))
2057 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, Op);
2058
2059 // Result size must be >= element size. If this is not the case after
2060 // promotion, also promote the result type and then truncate.
2061 SDValue Reduce = DAG.getNode(N->getOpcode(), dl, EltVT, Op);
2062 return DAG.getNode(ISD::TRUNCATE, dl, VT, Reduce);
2063}
2064
2065SDValue DAGTypeLegalizer::PromoteIntOp_SET_ROUNDING(SDNode *N) {
2066 SDValue Op = ZExtPromotedInteger(N->getOperand(1));
2067 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op), 0);
2068}
2069
2070//===----------------------------------------------------------------------===//
2071// Integer Result Expansion
2072//===----------------------------------------------------------------------===//
2073
2074/// ExpandIntegerResult - This method is called when the specified result of the
2075/// specified node is found to need expansion. At this point, the node may also
2076/// have invalid operands or may have other results that need promotion, we just
2077/// know that (at least) one result needs expansion.
2078void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
2079 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1
Assuming 'DebugFlag' is false
2
Loop condition is false. Exiting loop
2080 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
2081 SDValue Lo, Hi;
2082 Lo = Hi = SDValue();
2083
2084 // See if the target wants to custom expand this node.
2085 if (CustomLowerNode(N, N->getValueType(ResNo), true))
3
Assuming the condition is false
4
Taking false branch
2086 return;
2087
2088 switch (N->getOpcode()) {
5
Control jumps to 'case SHL:' at line 2208
2089 default:
2090#ifndef NDEBUG
2091 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
2092 N->dump(&DAG); dbgs() << "\n";
2093#endif
2094 report_fatal_error("Do not know how to expand the result of this "
2095 "operator!");
2096
2097 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
2098 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
2099 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
2100 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
2101 case ISD::FREEZE: SplitRes_FREEZE(N, Lo, Hi); break;
2102
2103 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
2104 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
2105 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
2106 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
2107 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
2108
2109 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
2110 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
2111 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
2112 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
2113 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
2114 case ISD::PARITY: ExpandIntRes_PARITY(N, Lo, Hi); break;
2115 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
2116 case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
2117 case ISD::CTLZ_ZERO_UNDEF:
2118 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
2119 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
2120 case ISD::CTTZ_ZERO_UNDEF:
2121 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
2122 case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
2123 case ISD::STRICT_FP_TO_SINT:
2124 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
2125 case ISD::STRICT_FP_TO_UINT:
2126 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
2127 case ISD::FP_TO_SINT_SAT:
2128 case ISD::FP_TO_UINT_SAT: ExpandIntRes_FP_TO_XINT_SAT(N, Lo, Hi); break;
2129 case ISD::STRICT_LLROUND:
2130 case ISD::STRICT_LLRINT:
2131 case ISD::LLROUND:
2132 case ISD::LLRINT: ExpandIntRes_LLROUND_LLRINT(N, Lo, Hi); break;
2133 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
2134 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
2135 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
2136 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
2137 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
2138 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
2139 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
2140 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
2141 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
2142 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
2143 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
2144 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
2145
2146 case ISD::ATOMIC_LOAD_ADD:
2147 case ISD::ATOMIC_LOAD_SUB:
2148 case ISD::ATOMIC_LOAD_AND:
2149 case ISD::ATOMIC_LOAD_CLR:
2150 case ISD::ATOMIC_LOAD_OR:
2151 case ISD::ATOMIC_LOAD_XOR:
2152 case ISD::ATOMIC_LOAD_NAND:
2153 case ISD::ATOMIC_LOAD_MIN:
2154 case ISD::ATOMIC_LOAD_MAX:
2155 case ISD::ATOMIC_LOAD_UMIN:
2156 case ISD::ATOMIC_LOAD_UMAX:
2157 case ISD::ATOMIC_SWAP:
2158 case ISD::ATOMIC_CMP_SWAP: {
2159 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
2160 SplitInteger(Tmp.first, Lo, Hi);
2161 ReplaceValueWith(SDValue(N, 1), Tmp.second);
2162 break;
2163 }
2164 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2165 AtomicSDNode *AN = cast<AtomicSDNode>(N);
2166 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
2167 SDValue Tmp = DAG.getAtomicCmpSwap(
2168 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
2169 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
2170 AN->getMemOperand());
2171
2172 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
2173 // success simply by comparing the loaded value against the ingoing
2174 // comparison.
2175 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
2176 N->getOperand(2), ISD::SETEQ);
2177
2178 SplitInteger(Tmp, Lo, Hi);
2179 ReplaceValueWith(SDValue(N, 1), Success);
2180 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
2181 break;
2182 }
2183
2184 case ISD::AND:
2185 case ISD::OR:
2186 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
2187
2188 case ISD::UMAX:
2189 case ISD::SMAX:
2190 case ISD::UMIN:
2191 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
2192
2193 case ISD::ADD:
2194 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
2195
2196 case ISD::ADDC:
2197 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
2198
2199 case ISD::ADDE:
2200 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
2201
2202 case ISD::ADDCARRY:
2203 case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
2204
2205 case ISD::SADDO_CARRY:
2206 case ISD::SSUBO_CARRY: ExpandIntRes_SADDSUBO_CARRY(N, Lo, Hi); break;
2207
2208 case ISD::SHL:
2209 case ISD::SRA:
2210 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
6
Calling 'DAGTypeLegalizer::ExpandIntRes_Shift'
2211
2212 case ISD::SADDO:
2213 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
2214 case ISD::UADDO:
2215 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
2216 case ISD::UMULO:
2217 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
2218
2219 case ISD::SADDSAT:
2220 case ISD::UADDSAT:
2221 case ISD::SSUBSAT:
2222 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
2223
2224 case ISD::SSHLSAT:
2225 case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break;
2226
2227 case ISD::SMULFIX:
2228 case ISD::SMULFIXSAT:
2229 case ISD::UMULFIX:
2230 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
2231
2232 case ISD::SDIVFIX:
2233 case ISD::SDIVFIXSAT:
2234 case ISD::UDIVFIX:
2235 case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
2236
2237 case ISD::VECREDUCE_ADD:
2238 case ISD::VECREDUCE_MUL:
2239 case ISD::VECREDUCE_AND:
2240 case ISD::VECREDUCE_OR:
2241 case ISD::VECREDUCE_XOR:
2242 case ISD::VECREDUCE_SMAX:
2243 case ISD::VECREDUCE_SMIN:
2244 case ISD::VECREDUCE_UMAX:
2245 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
2246
2247 case ISD::ROTL:
2248 case ISD::ROTR:
2249 ExpandIntRes_Rotate(N, Lo, Hi);
2250 break;
2251
2252 case ISD::FSHL:
2253 case ISD::FSHR:
2254 ExpandIntRes_FunnelShift(N, Lo, Hi);
2255 break;
2256
2257 case ISD::VSCALE:
2258 ExpandIntRes_VSCALE(N, Lo, Hi);
2259 break;
2260 }
2261
2262 // If Lo/Hi is null, the sub-method took care of registering results etc.
2263 if (Lo.getNode())
2264 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
2265}
2266
2267/// Lower an atomic node to the appropriate builtin call.
2268std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
2269 unsigned Opc = Node->getOpcode();
2270 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2271 AtomicOrdering order = cast<AtomicSDNode>(Node)->getMergedOrdering();
2272 // Lower to outline atomic libcall if outline atomics enabled,
2273 // or to sync libcall otherwise
2274 RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, order, VT);
2275 EVT RetVT = Node->getValueType(0);
2276 TargetLowering::MakeLibCallOptions CallOptions;
2277 SmallVector<SDValue, 4> Ops;
2278 if (TLI.getLibcallName(LC)) {
2279 Ops.append(Node->op_begin() + 2, Node->op_end());
2280 Ops.push_back(Node->getOperand(1));
2281 } else {
2282 LC = RTLIB::getSYNC(Opc, VT);
2283 assert(LC != RTLIB::UNKNOWN_LIBCALL &&(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected atomic op or value type!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected atomic op or value type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2284, __extension__ __PRETTY_FUNCTION__))
2284 "Unexpected atomic op or value type!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected atomic op or value type!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected atomic op or value type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2284, __extension__ __PRETTY_FUNCTION__))
;
2285 Ops.append(Node->op_begin() + 1, Node->op_end());
2286 }
2287 return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, SDLoc(Node),
2288 Node->getOperand(0));
2289}
2290
2291/// N is a shift by a value that needs to be expanded,
2292/// and the shift amount is a constant 'Amt'. Expand the operation.
2293void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
2294 SDValue &Lo, SDValue &Hi) {
2295 SDLoc DL(N);
2296 // Expand the incoming operand to be shifted, so that we have its parts
2297 SDValue InL, InH;
2298 GetExpandedInteger(N->getOperand(0), InL, InH);
2299
2300 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
2301 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
2302 if (!Amt) {
2303 Lo = InL;
2304 Hi = InH;
2305 return;
2306 }
2307
2308 EVT NVT = InL.getValueType();
2309 unsigned VTBits = N->getValueType(0).getSizeInBits();
2310 unsigned NVTBits = NVT.getSizeInBits();
2311 EVT ShTy = N->getOperand(1).getValueType();
2312
2313 if (N->getOpcode() == ISD::SHL) {
2314 if (Amt.ugt(VTBits)) {
2315 Lo = Hi = DAG.getConstant(0, DL, NVT);
2316 } else if (Amt.ugt(NVTBits)) {
2317 Lo = DAG.getConstant(0, DL, NVT);
2318 Hi = DAG.getNode(ISD::SHL, DL,
2319 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2320 } else if (Amt == NVTBits) {
2321 Lo = DAG.getConstant(0, DL, NVT);
2322 Hi = InL;
2323 } else {
2324 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
2325 Hi = DAG.getNode(ISD::OR, DL, NVT,
2326 DAG.getNode(ISD::SHL, DL, NVT, InH,
2327 DAG.getConstant(Amt, DL, ShTy)),
2328 DAG.getNode(ISD::SRL, DL, NVT, InL,
2329 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2330 }
2331 return;
2332 }
2333
2334 if (N->getOpcode() == ISD::SRL) {
2335 if (Amt.ugt(VTBits)) {
2336 Lo = Hi = DAG.getConstant(0, DL, NVT);
2337 } else if (Amt.ugt(NVTBits)) {
2338 Lo = DAG.getNode(ISD::SRL, DL,
2339 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2340 Hi = DAG.getConstant(0, DL, NVT);
2341 } else if (Amt == NVTBits) {
2342 Lo = InH;
2343 Hi = DAG.getConstant(0, DL, NVT);
2344 } else {
2345 Lo = DAG.getNode(ISD::OR, DL, NVT,
2346 DAG.getNode(ISD::SRL, DL, NVT, InL,
2347 DAG.getConstant(Amt, DL, ShTy)),
2348 DAG.getNode(ISD::SHL, DL, NVT, InH,
2349 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2350 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2351 }
2352 return;
2353 }
2354
2355 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")(static_cast <bool> (N->getOpcode() == ISD::SRA &&
"Unknown shift!") ? void (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2355, __extension__ __PRETTY_FUNCTION__))
;
2356 if (Amt.ugt(VTBits)) {
2357 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2358 DAG.getConstant(NVTBits - 1, DL, ShTy));
2359 } else if (Amt.ugt(NVTBits)) {
2360 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2361 DAG.getConstant(Amt - NVTBits, DL, ShTy));
2362 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2363 DAG.getConstant(NVTBits - 1, DL, ShTy));
2364 } else if (Amt == NVTBits) {
2365 Lo = InH;
2366 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2367 DAG.getConstant(NVTBits - 1, DL, ShTy));
2368 } else {
2369 Lo = DAG.getNode(ISD::OR, DL, NVT,
2370 DAG.getNode(ISD::SRL, DL, NVT, InL,
2371 DAG.getConstant(Amt, DL, ShTy)),
2372 DAG.getNode(ISD::SHL, DL, NVT, InH,
2373 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2374 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2375 }
2376}
2377
2378/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
2379/// this shift based on knowledge of the high bit of the shift amount. If we
2380/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
2381/// shift amount.
2382bool DAGTypeLegalizer::
2383ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2384 SDValue Amt = N->getOperand(1);
10
Value assigned to 'Amt.Node'
2385 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2386 EVT ShTy = Amt.getValueType();
11
Calling 'SDValue::getValueType'
2387 unsigned ShBits = ShTy.getScalarSizeInBits();
2388 unsigned NVTBits = NVT.getScalarSizeInBits();
2389 assert(isPowerOf2_32(NVTBits) &&(static_cast <bool> (isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? void (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2390, __extension__ __PRETTY_FUNCTION__))
2390 "Expanded integer type size not a power of two!")(static_cast <bool> (isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? void (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2390, __extension__ __PRETTY_FUNCTION__))
;
2391 SDLoc dl(N);
2392
2393 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
2394 KnownBits Known = DAG.computeKnownBits(N->getOperand(1));
2395
2396 // If we don't know anything about the high bits, exit.
2397 if (((Known.Zero|Known.One) & HighBitMask) == 0)
2398 return false;
2399
2400 // Get the incoming operand to be shifted.
2401 SDValue InL, InH;
2402 GetExpandedInteger(N->getOperand(0), InL, InH);
2403
2404 // If we know that any of the high bits of the shift amount are one, then we
2405 // can do this as a couple of simple shifts.
2406 if (Known.One.intersects(HighBitMask)) {
2407 // Mask out the high bit, which we know is set.
2408 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
2409 DAG.getConstant(~HighBitMask, dl, ShTy));
2410
2411 switch (N->getOpcode()) {
2412 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2412)
;
2413 case ISD::SHL:
2414 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
2415 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
2416 return true;
2417 case ISD::SRL:
2418 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2419 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
2420 return true;
2421 case ISD::SRA:
2422 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
2423 DAG.getConstant(NVTBits - 1, dl, ShTy));
2424 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
2425 return true;
2426 }
2427 }
2428
2429 // If we know that all of the high bits of the shift amount are zero, then we
2430 // can do this as a couple of simple shifts.
2431 if (HighBitMask.isSubsetOf(Known.Zero)) {
2432 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
2433 // shift if x is zero. We can use XOR here because x is known to be smaller
2434 // than 32.
2435 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
2436 DAG.getConstant(NVTBits - 1, dl, ShTy));
2437
2438 unsigned Op1, Op2;
2439 switch (N->getOpcode()) {
2440 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2440)
;
2441 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
2442 case ISD::SRL:
2443 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
2444 }
2445
2446 // When shifting right the arithmetic for Lo and Hi is swapped.
2447 if (N->getOpcode() != ISD::SHL)
2448 std::swap(InL, InH);
2449
2450 // Use a little trick to get the bits that move from Lo to Hi. First
2451 // shift by one bit.
2452 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
2453 // Then compute the remaining shift with amount-1.
2454 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
2455
2456 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
2457 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
2458
2459 if (N->getOpcode() != ISD::SHL)
2460 std::swap(Hi, Lo);
2461 return true;
2462 }
2463
2464 return false;
2465}
2466
2467/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
2468/// of any size.
2469bool DAGTypeLegalizer::
2470ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2471 SDValue Amt = N->getOperand(1);
2472 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2473 EVT ShTy = Amt.getValueType();
2474 unsigned NVTBits = NVT.getSizeInBits();
2475 assert(isPowerOf2_32(NVTBits) &&(static_cast <bool> (isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? void (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2476, __extension__ __PRETTY_FUNCTION__))
2476 "Expanded integer type size not a power of two!")(static_cast <bool> (isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? void (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2476, __extension__ __PRETTY_FUNCTION__))
;
2477 SDLoc dl(N);
2478
2479 // Get the incoming operand to be shifted.
2480 SDValue InL, InH;
2481 GetExpandedInteger(N->getOperand(0), InL, InH);
2482
2483 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
2484 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
2485 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
2486 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2487 Amt, NVBitsNode, ISD::SETULT);
2488 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2489 Amt, DAG.getConstant(0, dl, ShTy),
2490 ISD::SETEQ);
2491
2492 SDValue LoS, HiS, LoL, HiL;
2493 switch (N->getOpcode()) {
2494 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2494)
;
2495 case ISD::SHL:
2496 // Short: ShAmt < NVTBits
2497 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
2498 HiS = DAG.getNode(ISD::OR, dl, NVT,
2499 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
2500 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
2501
2502 // Long: ShAmt >= NVTBits
2503 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
2504 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
2505
2506 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
2507 Hi = DAG.getSelect(dl, NVT, isZero, InH,
2508 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
2509 return true;
2510 case ISD::SRL:
2511 // Short: ShAmt < NVTBits
2512 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
2513 LoS = DAG.getNode(ISD::OR, dl, NVT,
2514 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2515 // FIXME: If Amt is zero, the following shift generates an undefined result
2516 // on some architectures.
2517 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2518
2519 // Long: ShAmt >= NVTBits
2520 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2521 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2522
2523 Lo = DAG.getSelect(dl, NVT, isZero, InL,
2524 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2525 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2526 return true;
2527 case ISD::SRA:
2528 // Short: ShAmt < NVTBits
2529 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
2530 LoS = DAG.getNode(ISD::OR, dl, NVT,
2531 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2532 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2533
2534 // Long: ShAmt >= NVTBits
2535 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
2536 DAG.getConstant(NVTBits - 1, dl, ShTy));
2537 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2538
2539 Lo = DAG.getSelect(dl, NVT, isZero, InL,
2540 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2541 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2542 return true;
2543 }
2544}
2545
2546static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
2547
2548 switch (Op) {
2549 default: llvm_unreachable("invalid min/max opcode")::llvm::llvm_unreachable_internal("invalid min/max opcode", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2549)
;
2550 case ISD::SMAX:
2551 return std::make_pair(ISD::SETGT, ISD::UMAX);
2552 case ISD::UMAX:
2553 return std::make_pair(ISD::SETUGT, ISD::UMAX);
2554 case ISD::SMIN:
2555 return std::make_pair(ISD::SETLT, ISD::UMIN);
2556 case ISD::UMIN:
2557 return std::make_pair(ISD::SETULT, ISD::UMIN);
2558 }
2559}
2560
2561void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
2562 SDValue &Lo, SDValue &Hi) {
2563 SDLoc DL(N);
2564 ISD::NodeType LoOpc;
2565 ISD::CondCode CondC;
2566 std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode());
2567
2568 // Expand the subcomponents.
2569 SDValue LHSL, LHSH, RHSL, RHSH;
2570 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2571 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2572
2573 // Value types
2574 EVT NVT = LHSL.getValueType();
2575 EVT CCT = getSetCCResultType(NVT);
2576
2577 // Hi part is always the same op
2578 Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
2579
2580 // We need to know whether to select Lo part that corresponds to 'winning'
2581 // Hi part or if Hi parts are equal.
2582 SDValue IsHiLeft = DAG.getSetCC(DL, CCT, LHSH, RHSH, CondC);
2583 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ);
2584
2585 // Lo part corresponding to the 'winning' Hi part
2586 SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
2587
2588 // Recursed Lo part if Hi parts are equal, this uses unsigned version
2589 SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
2590
2591 Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
2592}
2593
2594void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
2595 SDValue &Lo, SDValue &Hi) {
2596 SDLoc dl(N);
2597 // Expand the subcomponents.
2598 SDValue LHSL, LHSH, RHSL, RHSH;
2599 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2600 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2601
2602 EVT NVT = LHSL.getValueType();
2603 SDValue LoOps[2] = { LHSL, RHSL };
2604 SDValue HiOps[3] = { LHSH, RHSH };
2605
2606 bool HasOpCarry = TLI.isOperationLegalOrCustom(
2607 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
2608 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2609 if (HasOpCarry) {
2610 SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
2611 if (N->getOpcode() == ISD::ADD) {
2612 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2613 HiOps[2] = Lo.getValue(1);
2614 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps);
2615 } else {
2616 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2617 HiOps[2] = Lo.getValue(1);
2618 Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
2619 }
2620 return;
2621 }
2622
2623 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
2624 // them. TODO: Teach operation legalization how to expand unsupported
2625 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
2626 // a carry of type MVT::Glue, but there doesn't seem to be any way to
2627 // generate a value of this type in the expanded code sequence.
2628 bool hasCarry =
2629 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2630 ISD::ADDC : ISD::SUBC,
2631 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2632
2633 if (hasCarry) {
2634 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
2635 if (N->getOpcode() == ISD::ADD) {
2636 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2637 HiOps[2] = Lo.getValue(1);
2638 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2639 } else {
2640 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2641 HiOps[2] = Lo.getValue(1);
2642 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2643 }
2644 return;
2645 }
2646
2647 bool hasOVF =
2648 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2649 ISD::UADDO : ISD::USUBO,
2650 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2651 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
2652
2653 if (hasOVF) {
2654 EVT OvfVT = getSetCCResultType(NVT);
2655 SDVTList VTList = DAG.getVTList(NVT, OvfVT);
2656 int RevOpc;
2657 if (N->getOpcode() == ISD::ADD) {
2658 RevOpc = ISD::SUB;
2659 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2660 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2661 } else {
2662 RevOpc = ISD::ADD;
2663 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2664 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2665 }
2666 SDValue OVF = Lo.getValue(1);
2667
2668 switch (BoolType) {
2669 case TargetLoweringBase::UndefinedBooleanContent:
2670 OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF);
2671 LLVM_FALLTHROUGH[[gnu::fallthrough]];
2672 case TargetLoweringBase::ZeroOrOneBooleanContent:
2673 OVF = DAG.getZExtOrTrunc(OVF, dl, NVT);
2674 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
2675 break;
2676 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2677 OVF = DAG.getSExtOrTrunc(OVF, dl, NVT);
2678 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
2679 }
2680 return;
2681 }
2682
2683 if (N->getOpcode() == ISD::ADD) {
2684 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
2685 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2686 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
2687 ISD::SETULT);
2688
2689 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent) {
2690 SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT);
2691 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
2692 return;
2693 }
2694
2695 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
2696 DAG.getConstant(1, dl, NVT),
2697 DAG.getConstant(0, dl, NVT));
2698 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
2699 ISD::SETULT);
2700 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
2701 DAG.getConstant(1, dl, NVT), Carry1);
2702 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
2703 } else {
2704 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
2705 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2706 SDValue Cmp =
2707 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
2708 LoOps[0], LoOps[1], ISD::SETULT);
2709
2710 SDValue Borrow;
2711 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
2712 Borrow = DAG.getZExtOrTrunc(Cmp, dl, NVT);
2713 else
2714 Borrow = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT),
2715 DAG.getConstant(0, dl, NVT));
2716
2717 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
2718 }
2719}
2720
2721void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
2722 SDValue &Lo, SDValue &Hi) {
2723 // Expand the subcomponents.
2724 SDValue LHSL, LHSH, RHSL, RHSH;
2725 SDLoc dl(N);
2726 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2727 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2728 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2729 SDValue LoOps[2] = { LHSL, RHSL };
2730 SDValue HiOps[3] = { LHSH, RHSH };
2731
2732 if (N->getOpcode() == ISD::ADDC) {
2733 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2734 HiOps[2] = Lo.getValue(1);
2735 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2736 } else {
2737 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2738 HiOps[2] = Lo.getValue(1);
2739 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2740 }
2741
2742 // Legalized the flag result - switch anything that used the old flag to
2743 // use the new one.
2744 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2745}
2746
2747void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
2748 SDValue &Lo, SDValue &Hi) {
2749 // Expand the subcomponents.
2750 SDValue LHSL, LHSH, RHSL, RHSH;
2751 SDLoc dl(N);
2752 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2753 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2754 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2755 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2756 SDValue HiOps[3] = { LHSH, RHSH };
2757
2758 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2759 HiOps[2] = Lo.getValue(1);
2760 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2761
2762 // Legalized the flag result - switch anything that used the old flag to
2763 // use the new one.
2764 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2765}
2766
2767void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2768 SDValue &Lo, SDValue &Hi) {
2769 SDValue LHS = N->getOperand(0);
2770 SDValue RHS = N->getOperand(1);
2771 SDLoc dl(N);
2772
2773 SDValue Ovf;
2774
2775 unsigned CarryOp, NoCarryOp;
2776 ISD::CondCode Cond;
2777 switch(N->getOpcode()) {
2778 case ISD::UADDO:
2779 CarryOp = ISD::ADDCARRY;
2780 NoCarryOp = ISD::ADD;
2781 Cond = ISD::SETULT;
2782 break;
2783 case ISD::USUBO:
2784 CarryOp = ISD::SUBCARRY;
2785 NoCarryOp = ISD::SUB;
2786 Cond = ISD::SETUGT;
2787 break;
2788 default:
2789 llvm_unreachable("Node has unexpected Opcode")::llvm::llvm_unreachable_internal("Node has unexpected Opcode"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2789)
;
2790 }
2791
2792 bool HasCarryOp = TLI.isOperationLegalOrCustom(
2793 CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
2794
2795 if (HasCarryOp) {
2796 // Expand the subcomponents.
2797 SDValue LHSL, LHSH, RHSL, RHSH;
2798 GetExpandedInteger(LHS, LHSL, LHSH);
2799 GetExpandedInteger(RHS, RHSL, RHSH);
2800 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2801 SDValue LoOps[2] = { LHSL, RHSL };
2802 SDValue HiOps[3] = { LHSH, RHSH };
2803
2804 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2805 HiOps[2] = Lo.getValue(1);
2806 Hi = DAG.getNode(CarryOp, dl, VTList, HiOps);
2807
2808 Ovf = Hi.getValue(1);
2809 } else {
2810 // Expand the result by simply replacing it with the equivalent
2811 // non-overflow-checking operation.
2812 SDValue Sum = DAG.getNode(NoCarryOp, dl, LHS.getValueType(), LHS, RHS);
2813 SplitInteger(Sum, Lo, Hi);
2814
2815 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2816 // overflows iff a - b > a.
2817 Ovf = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, Cond);
2818 }
2819
2820 // Legalized the flag result - switch anything that used the old flag to
2821 // use the new one.
2822 ReplaceValueWith(SDValue(N, 1), Ovf);
2823}
2824
2825void DAGTypeLegalizer::ExpandIntRes_ADDSUBCARRY(SDNode *N,
2826 SDValue &Lo, SDValue &Hi) {
2827 // Expand the subcomponents.
2828 SDValue LHSL, LHSH, RHSL, RHSH;
2829 SDLoc dl(N);
2830 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2831 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2832 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2833 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2834 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
2835
2836 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2837 HiOps[2] = Lo.getValue(1);
2838 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2839
2840 // Legalized the flag result - switch anything that used the old flag to
2841 // use the new one.
2842 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2843}
2844
2845void DAGTypeLegalizer::ExpandIntRes_SADDSUBO_CARRY(SDNode *N,
2846 SDValue &Lo, SDValue &Hi) {
2847 // Expand the subcomponents.
2848 SDValue LHSL, LHSH, RHSL, RHSH;
2849 SDLoc dl(N);
2850 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2851 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2852 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2853
2854 // We need to use an unsigned carry op for the lo part.
2855 unsigned CarryOp = N->getOpcode() == ISD::SADDO_CARRY ? ISD::ADDCARRY
2856 : ISD::SUBCARRY;
2857 Lo = DAG.getNode(CarryOp, dl, VTList, { LHSL, RHSL, N->getOperand(2) });
2858 Hi = DAG.getNode(N->getOpcode(), dl, VTList, { LHSH, RHSH, Lo.getValue(1) });
2859
2860 // Legalized the flag result - switch anything that used the old flag to
2861 // use the new one.
2862 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2863}
2864
2865void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
2866 SDValue &Lo, SDValue &Hi) {
2867 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2868 SDLoc dl(N);
2869 SDValue Op = N->getOperand(0);
2870 if (Op.getValueType().bitsLE(NVT)) {
2871 // The low part is any extension of the input (which degenerates to a copy).
2872 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
2873 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
2874 } else {
2875 // For example, extension of an i48 to an i64. The operand type necessarily
2876 // promotes to the result type, so will end up being expanded too.
2877 assert(getTypeAction(Op.getValueType()) ==(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2879, __extension__ __PRETTY_FUNCTION__))
2878 TargetLowering::TypePromoteInteger &&(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2879, __extension__ __PRETTY_FUNCTION__))
2879 "Only know how to promote this result!")(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2879, __extension__ __PRETTY_FUNCTION__))
;
2880 SDValue Res = GetPromotedInteger(Op);
2881 assert(Res.getValueType() == N->getValueType(0) &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2882, __extension__ __PRETTY_FUNCTION__))
2882 "Operand over promoted?")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2882, __extension__ __PRETTY_FUNCTION__))
;
2883 // Split the promoted operand. This will simplify when it is expanded.
2884 SplitInteger(Res, Lo, Hi);
2885 }
2886}
2887
2888void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
2889 SDValue &Lo, SDValue &Hi) {
2890 SDLoc dl(N);
2891 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2892 EVT NVT = Lo.getValueType();
2893 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2894 unsigned NVTBits = NVT.getSizeInBits();
2895 unsigned EVTBits = EVT.getSizeInBits();
2896
2897 if (NVTBits < EVTBits) {
2898 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
2899 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2900 EVTBits - NVTBits)));
2901 } else {
2902 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
2903 // The high part replicates the sign bit of Lo, make it explicit.
2904 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2905 DAG.getConstant(NVTBits - 1, dl,
2906 TLI.getPointerTy(DAG.getDataLayout())));
2907 }
2908}
2909
2910void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
2911 SDValue &Lo, SDValue &Hi) {
2912 SDLoc dl(N);
2913 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2914 EVT NVT = Lo.getValueType();
2915 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2916 unsigned NVTBits = NVT.getSizeInBits();
2917 unsigned EVTBits = EVT.getSizeInBits();
2918
2919 if (NVTBits < EVTBits) {
2920 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
2921 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2922 EVTBits - NVTBits)));
2923 } else {
2924 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
2925 // The high part must be zero, make it explicit.
2926 Hi = DAG.getConstant(0, dl, NVT);
2927 }
2928}
2929
2930void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
2931 SDValue &Lo, SDValue &Hi) {
2932 SDLoc dl(N);
2933 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
2934 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
2935 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
2936}
2937
2938void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
2939 SDValue &Lo, SDValue &Hi) {
2940 SDLoc dl(N);
2941 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
2942 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
2943 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
2944}
2945
2946void DAGTypeLegalizer::ExpandIntRes_PARITY(SDNode *N, SDValue &Lo,
2947 SDValue &Hi) {
2948 SDLoc dl(N);
2949 // parity(HiLo) -> parity(Lo^Hi)
2950 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2951 EVT NVT = Lo.getValueType();
2952 Lo =
2953 DAG.getNode(ISD::PARITY, dl, NVT, DAG.getNode(ISD::XOR, dl, NVT, Lo, Hi));
2954 Hi = DAG.getConstant(0, dl, NVT);
2955}
2956
2957void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
2958 SDValue &Lo, SDValue &Hi) {
2959 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2960 unsigned NBitWidth = NVT.getSizeInBits();
2961 auto Constant = cast<ConstantSDNode>(N);
2962 const APInt &Cst = Constant->getAPIntValue();
2963 bool IsTarget = Constant->isTargetOpcode();
2964 bool IsOpaque = Constant->isOpaque();
2965 SDLoc dl(N);
2966 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
2967 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
2968 IsOpaque);
2969}
2970
2971void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
2972 SDLoc dl(N);
2973
2974 SDValue N0 = N->getOperand(0);
2975 GetExpandedInteger(N0, Lo, Hi);
2976 EVT NVT = Lo.getValueType();
2977
2978 // If we have ADDCARRY, use the expanded form of the sra+add+xor sequence we
2979 // use in LegalizeDAG. The ADD part of the expansion is based on
2980 // ExpandIntRes_ADDSUB which also uses ADDCARRY/UADDO after checking that
2981 // ADDCARRY is LegalOrCustom. Each of the pieces here can be further expanded
2982 // if needed. Shift expansion has a special case for filling with sign bits
2983 // so that we will only end up with one SRA.
2984 bool HasAddCarry = TLI.isOperationLegalOrCustom(
2985 ISD::ADDCARRY, TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2986 if (HasAddCarry) {
2987 EVT ShiftAmtTy = getShiftAmountTyForConstant(NVT, TLI, DAG);
2988 SDValue Sign =
2989 DAG.getNode(ISD::SRA, dl, NVT, Hi,
2990 DAG.getConstant(NVT.getSizeInBits() - 1, dl, ShiftAmtTy));
2991 SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
2992 Lo = DAG.getNode(ISD::UADDO, dl, VTList, Lo, Sign);
2993 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, Hi, Sign, Lo.getValue(1));
2994 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Sign);
2995 Hi = DAG.getNode(ISD::XOR, dl, NVT, Hi, Sign);
2996 return;
2997 }
2998
2999 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
3000 EVT VT = N->getValueType(0);
3001 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT,
3002 DAG.getConstant(0, dl, VT), N0);
3003 SDValue NegLo, NegHi;
3004 SplitInteger(Neg, NegLo, NegHi);
3005
3006 SDValue HiIsNeg = DAG.getSetCC(dl, getSetCCResultType(NVT),
3007 DAG.getConstant(0, dl, NVT), Hi, ISD::SETGT);
3008 Lo = DAG.getSelect(dl, NVT, HiIsNeg, NegLo, Lo);
3009 Hi = DAG.getSelect(dl, NVT, HiIsNeg, NegHi, Hi);
3010}
3011
3012void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
3013 SDValue &Lo, SDValue &Hi) {
3014 SDLoc dl(N);
3015 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
3016 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3017 EVT NVT = Lo.getValueType();
3018
3019 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
3020 DAG.getConstant(0, dl, NVT), ISD::SETNE);
3021
3022 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
3023 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
3024
3025 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
3026 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
3027 DAG.getConstant(NVT.getSizeInBits(), dl,
3028 NVT)));
3029 Hi = DAG.getConstant(0, dl, NVT);
3030}
3031
3032void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
3033 SDValue &Lo, SDValue &Hi) {
3034 SDLoc dl(N);
3035 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
3036 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3037 EVT NVT = Lo.getValueType();
3038 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
3039 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
3040 Hi = DAG.getConstant(0, dl, NVT);
3041}
3042
3043void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
3044 SDValue &Lo, SDValue &Hi) {
3045 SDLoc dl(N);
3046 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
3047 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3048 EVT NVT = Lo.getValueType();
3049
3050 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
3051 DAG.getConstant(0, dl, NVT), ISD::SETNE);
3052
3053 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
3054 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
3055
3056 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
3057 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
3058 DAG.getConstant(NVT.getSizeInBits(), dl,
3059 NVT)));
3060 Hi = DAG.getConstant(0, dl, NVT);
3061}
3062
3063void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo,
3064 SDValue &Hi) {
3065 SDLoc dl(N);
3066 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3067 unsigned NBitWidth = NVT.getSizeInBits();
3068
3069 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3070 Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, {NVT, MVT::Other}, N->getOperand(0));
3071 SDValue Chain = Lo.getValue(1);
3072 // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS
3073 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3074 DAG.getConstant(NBitWidth - 1, dl, ShiftAmtTy));
3075
3076 // Legalize the chain result - switch anything that used the old chain to
3077 // use the new one.
3078 ReplaceValueWith(SDValue(N, 1), Chain);
3079}
3080
3081void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
3082 SDValue &Hi) {
3083 SDLoc dl(N);
3084 EVT VT = N->getValueType(0);
3085
3086 bool IsStrict = N->isStrictFPOpcode();
3087 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
3088 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
3089 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
3090 Op = GetPromotedFloat(Op);
3091
3092 if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
3093 EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
3094 Op = GetSoftPromotedHalf(Op);
3095 Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
3096 }
3097
3098 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
3099 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected fp-to-sint conversion!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fp-to-sint conversion!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3099, __extension__ __PRETTY_FUNCTION__))
;
3100 TargetLowering::MakeLibCallOptions CallOptions;
3101 CallOptions.setSExt(true);
3102 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
3103 CallOptions, dl, Chain);
3104 SplitInteger(Tmp.first, Lo, Hi);
3105
3106 if (IsStrict)
3107 ReplaceValueWith(SDValue(N, 1), Tmp.second);
3108}
3109
3110void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
3111 SDValue &Hi) {
3112 SDLoc dl(N);
3113 EVT VT = N->getValueType(0);
3114
3115 bool IsStrict = N->isStrictFPOpcode();
3116 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
3117 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
3118 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
3119 Op = GetPromotedFloat(Op);
3120
3121 if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
3122 EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
3123 Op = GetSoftPromotedHalf(Op);
3124 Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
3125 }
3126
3127 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
3128 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected fp-to-uint conversion!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fp-to-uint conversion!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3128, __extension__ __PRETTY_FUNCTION__))
;
3129 TargetLowering::MakeLibCallOptions CallOptions;
3130 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
3131 CallOptions, dl, Chain);
3132 SplitInteger(Tmp.first, Lo, Hi);
3133
3134 if (IsStrict)
3135 ReplaceValueWith(SDValue(N, 1), Tmp.second);
3136}
3137
3138void DAGTypeLegalizer::ExpandIntRes_FP_TO_XINT_SAT(SDNode *N, SDValue &Lo,
3139 SDValue &Hi) {
3140 SDValue Res = TLI.expandFP_TO_INT_SAT(N, DAG);
3141 SplitInteger(Res, Lo, Hi);
3142}
3143
3144void DAGTypeLegalizer::ExpandIntRes_LLROUND_LLRINT(SDNode *N, SDValue &Lo,
3145 SDValue &Hi) {
3146 SDValue Op = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
3147
3148 assert(getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat &&(static_cast <bool> (getTypeAction(Op.getValueType()) !=
TargetLowering::TypePromoteFloat && "Input type needs to be promoted!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat && \"Input type needs to be promoted!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3149, __extension__ __PRETTY_FUNCTION__))
3149 "Input type needs to be promoted!")(static_cast <bool> (getTypeAction(Op.getValueType()) !=
TargetLowering::TypePromoteFloat && "Input type needs to be promoted!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat && \"Input type needs to be promoted!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3149, __extension__ __PRETTY_FUNCTION__))
;
3150
3151 EVT VT = Op.getValueType();
3152
3153 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3154 if (N->getOpcode() == ISD::LLROUND ||
3155 N->getOpcode() == ISD::STRICT_LLROUND) {
3156 if (VT == MVT::f32)
3157 LC = RTLIB::LLROUND_F32;
3158 else if (VT == MVT::f64)
3159 LC = RTLIB::LLROUND_F64;
3160 else if (VT == MVT::f80)
3161 LC = RTLIB::LLROUND_F80;
3162 else if (VT == MVT::f128)
3163 LC = RTLIB::LLROUND_F128;
3164 else if (VT == MVT::ppcf128)
3165 LC = RTLIB::LLROUND_PPCF128;
3166 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected llround input type!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected llround input type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3166, __extension__ __PRETTY_FUNCTION__))
;
3167 } else if (N->getOpcode() == ISD::LLRINT ||
3168 N->getOpcode() == ISD::STRICT_LLRINT) {
3169 if (VT == MVT::f32)
3170 LC = RTLIB::LLRINT_F32;
3171 else if (VT == MVT::f64)
3172 LC = RTLIB::LLRINT_F64;
3173 else if (VT == MVT::f80)
3174 LC = RTLIB::LLRINT_F80;
3175 else if (VT == MVT::f128)
3176 LC = RTLIB::LLRINT_F128;
3177 else if (VT == MVT::ppcf128)
3178 LC = RTLIB::LLRINT_PPCF128;
3179 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected llrint input type!") ? void (0) : __assert_fail (
"LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected llrint input type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3179, __extension__ __PRETTY_FUNCTION__))
;
3180 } else
3181 llvm_unreachable("Unexpected opcode!")::llvm::llvm_unreachable_internal("Unexpected opcode!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3181)
;
3182
3183 SDLoc dl(N);
3184 EVT RetVT = N->getValueType(0);
3185 SDValue Chain = N->isStrictFPOpcode() ? N->getOperand(0) : SDValue();
3186
3187 TargetLowering::MakeLibCallOptions CallOptions;
3188 CallOptions.setSExt(true);
3189 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
3190 Op, CallOptions, dl,
3191 Chain);
3192 SplitInteger(Tmp.first, Lo, Hi);
3193
3194 if (N->isStrictFPOpcode())
3195 ReplaceValueWith(SDValue(N, 1), Tmp.second);
3196}
3197
3198void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
3199 SDValue &Lo, SDValue &Hi) {
3200 if (N->isAtomic()) {
3201 // It's typical to have larger CAS than atomic load instructions.
3202 SDLoc dl(N);
3203 EVT VT = N->getMemoryVT();
3204 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
3205 SDValue Zero = DAG.getConstant(0, dl, VT);
3206 SDValue Swap = DAG.getAtomicCmpSwap(
3207 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
3208 VT, VTs, N->getOperand(0),
3209 N->getOperand(1), Zero, Zero, N->getMemOperand());
3210 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
3211 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
3212 return;
3213 }
3214
3215 if (ISD::isNormalLoad(N)) {
3216 ExpandRes_NormalLoad(N, Lo, Hi);
3217 return;
3218 }
3219
3220 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!")(static_cast <bool> (ISD::isUNINDEXEDLoad(N) &&
"Indexed load during type legalization!") ? void (0) : __assert_fail
("ISD::isUNINDEXEDLoad(N) && \"Indexed load during type legalization!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3220, __extension__ __PRETTY_FUNCTION__))
;
3221
3222 EVT VT = N->getValueType(0);
3223 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3224 SDValue Ch = N->getChain();
3225 SDValue Ptr = N->getBasePtr();
3226 ISD::LoadExtType ExtType = N->getExtensionType();
3227 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
3228 AAMDNodes AAInfo = N->getAAInfo();
3229 SDLoc dl(N);
3230
3231 assert(NVT.isByteSized() && "Expanded type not byte sized!")(static_cast <bool> (NVT.isByteSized() && "Expanded type not byte sized!"
) ? void (0) : __assert_fail ("NVT.isByteSized() && \"Expanded type not byte sized!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3231, __extension__ __PRETTY_FUNCTION__))
;
3232
3233 if (N->getMemoryVT().bitsLE(NVT)) {
3234 EVT MemVT = N->getMemoryVT();
3235
3236 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
3237 N->getOriginalAlign(), MMOFlags, AAInfo);
3238
3239 // Remember the chain.
3240 Ch = Lo.getValue(1);
3241
3242 if (ExtType == ISD::SEXTLOAD) {
3243 // The high part is obtained by SRA'ing all but one of the bits of the
3244 // lo part.
3245 unsigned LoSize = Lo.getValueSizeInBits();
3246 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
3247 DAG.getConstant(LoSize - 1, dl,
3248 TLI.getPointerTy(DAG.getDataLayout())));
3249 } else if (ExtType == ISD::ZEXTLOAD) {
3250 // The high part is just a zero.
3251 Hi = DAG.getConstant(0, dl, NVT);
3252 } else {
3253 assert(ExtType == ISD::EXTLOAD && "Unknown extload!")(static_cast <bool> (ExtType == ISD::EXTLOAD &&
"Unknown extload!") ? void (0) : __assert_fail ("ExtType == ISD::EXTLOAD && \"Unknown extload!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3253, __extension__ __PRETTY_FUNCTION__))
;
3254 // The high part is undefined.
3255 Hi = DAG.getUNDEF(NVT);
3256 }
3257 } else if (DAG.getDataLayout().isLittleEndian()) {
3258 // Little-endian - low bits are at low addresses.
3259 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
3260 N->getOriginalAlign(), MMOFlags, AAInfo);
3261
3262 unsigned ExcessBits =
3263 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
3264 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
3265
3266 // Increment the pointer to the other half.
3267 unsigned IncrementSize = NVT.getSizeInBits()/8;
3268 Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
3269 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
3270 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
3271 N->getOriginalAlign(), MMOFlags, AAInfo);
3272
3273 // Build a factor node to remember that this load is independent of the
3274 // other one.
3275 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
3276 Hi.getValue(1));
3277 } else {
3278 // Big-endian - high bits are at low addresses. Favor aligned loads at
3279 // the cost of some bit-fiddling.
3280 EVT MemVT = N->getMemoryVT();
3281 unsigned EBytes = MemVT.getStoreSize();
3282 unsigned IncrementSize = NVT.getSizeInBits()/8;
3283 unsigned ExcessBits = (EBytes - IncrementSize)*8;
3284
3285 // Load both the high bits and maybe some of the low bits.
3286 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
3287 EVT::getIntegerVT(*DAG.getContext(),
3288 MemVT.getSizeInBits() - ExcessBits),
3289 N->getOriginalAlign(), MMOFlags, AAInfo);
3290
3291 // Increment the pointer to the other half.
3292 Ptr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(IncrementSize), dl);
3293 // Load the rest of the low bits.
3294 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
3295 N->getPointerInfo().getWithOffset(IncrementSize),
3296 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
3297 N->getOriginalAlign(), MMOFlags, AAInfo);
3298
3299 // Build a factor node to remember that this load is independent of the
3300 // other one.
3301 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
3302 Hi.getValue(1));
3303
3304 if (ExcessBits < NVT.getSizeInBits()) {
3305 // Transfer low bits from the bottom of Hi to the top of Lo.
3306 Lo = DAG.getNode(
3307 ISD::OR, dl, NVT, Lo,
3308 DAG.getNode(ISD::SHL, dl, NVT, Hi,
3309 DAG.getConstant(ExcessBits, dl,
3310 TLI.getPointerTy(DAG.getDataLayout()))));
3311 // Move high bits to the right position in Hi.
3312 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
3313 Hi,
3314 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
3315 TLI.getPointerTy(DAG.getDataLayout())));
3316 }
3317 }
3318
3319 // Legalize the chain result - switch anything that used the old chain to
3320 // use the new one.
3321 ReplaceValueWith(SDValue(N, 1), Ch);
3322}
3323
3324void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
3325 SDValue &Lo, SDValue &Hi) {
3326 SDLoc dl(N);
3327 SDValue LL, LH, RL, RH;
3328 GetExpandedInteger(N->getOperand(0), LL, LH);
3329 GetExpandedInteger(N->getOperand(1), RL, RH);
3330 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
3331 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
3332}
3333
3334void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
3335 SDValue &Lo, SDValue &Hi) {
3336 EVT VT = N->getValueType(0);
3337 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3338 SDLoc dl(N);
3339
3340 SDValue LL, LH, RL, RH;
3341 GetExpandedInteger(N->getOperand(0), LL, LH);
3342 GetExpandedInteger(N->getOperand(1), RL, RH);
3343
3344 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG,
3345 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
3346 LL, LH, RL, RH))
3347 return;
3348
3349 // If nothing else, we can make a libcall.
3350 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3351 if (VT == MVT::i16)
3352 LC = RTLIB::MUL_I16;
3353 else if (VT == MVT::i32)
3354 LC = RTLIB::MUL_I32;
3355 else if (VT == MVT::i64)
3356 LC = RTLIB::MUL_I64;
3357 else if (VT == MVT::i128)
3358 LC = RTLIB::MUL_I128;
3359
3360 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
3361 // We'll expand the multiplication by brute force because we have no other
3362 // options. This is a trivially-generalized version of the code from
3363 // Hacker's Delight (itself derived from Knuth's Algorithm M from section
3364 // 4.3.1).
3365 unsigned Bits = NVT.getSizeInBits();
3366 unsigned HalfBits = Bits >> 1;
3367 SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl,
3368 NVT);
3369 SDValue LLL = DAG.getNode(ISD::AND, dl, NVT, LL, Mask);
3370 SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask);
3371
3372 SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
3373 SDValue TL = DAG.getNode(ISD::AND, dl, NVT, T, Mask);
3374
3375 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3376 if (APInt::getMaxValue(ShiftAmtTy.getSizeInBits()).ult(HalfBits)) {
3377 // The type from TLI is too small to fit the shift amount we want.
3378 // Override it with i32. The shift will have to be legalized.
3379 ShiftAmtTy = MVT::i32;
3380 }
3381 SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy);
3382 SDValue TH = DAG.getNode(ISD::SRL, dl, NVT, T, Shift);
3383 SDValue LLH = DAG.getNode(ISD::SRL, dl, NVT, LL, Shift);
3384 SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);
3385
3386 SDValue U = DAG.getNode(ISD::ADD, dl, NVT,
3387 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
3388 SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);
3389 SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
3390
3391 SDValue V = DAG.getNode(ISD::ADD, dl, NVT,
3392 DAG.getNode(ISD::MUL, dl, NVT, LLL, RLH), UL);
3393 SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);
3394
3395 SDValue W = DAG.getNode(ISD::ADD, dl, NVT,
3396 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
3397 DAG.getNode(ISD::ADD, dl, NVT, UH, VH));
3398 Lo = DAG.getNode(ISD::ADD, dl, NVT, TL,
3399 DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
3400
3401 Hi = DAG.getNode(ISD::ADD, dl, NVT, W,
3402 DAG.getNode(ISD::ADD, dl, NVT,
3403 DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
3404 DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
3405 return;
3406 }
3407
3408 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3409 TargetLowering::MakeLibCallOptions CallOptions;
3410 CallOptions.setSExt(true);
3411 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first,
3412 Lo, Hi);
3413}
3414
3415void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
3416 SDValue &Hi) {
3417 SDLoc DL(N);
3418 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3419 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
3420 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
3421 Lo = R.getValue(0);
3422 Hi = R.getValue(1);
3423 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
3424}
3425
3426void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
3427 SDValue &Hi) {
3428 SDValue Result = TLI.expandAddSubSat(N, DAG);
3429 SplitInteger(Result, Lo, Hi);
3430}
3431
3432void DAGTypeLegalizer::ExpandIntRes_SHLSAT(SDNode *N, SDValue &Lo,
3433 SDValue &Hi) {
3434 SDValue Result = TLI.expandShlSat(N, DAG);
3435 SplitInteger(Result, Lo, Hi);
3436}
3437
3438/// This performs an expansion of the integer result for a fixed point
3439/// multiplication. The default expansion performs rounding down towards
3440/// negative infinity, though targets that do care about rounding should specify
3441/// a target hook for rounding and provide their own expansion or lowering of
3442/// fixed point multiplication to be consistent with rounding.
3443void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
3444 SDValue &Hi) {
3445 SDLoc dl(N);
3446 EVT VT = N->getValueType(0);
3447 unsigned VTSize = VT.getScalarSizeInBits();
3448 SDValue LHS = N->getOperand(0);
3449 SDValue RHS = N->getOperand(1);
3450 uint64_t Scale = N->getConstantOperandVal(2);
3451 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
3452 N->getOpcode() == ISD::UMULFIXSAT);
3453 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
3454 N->getOpcode() == ISD::SMULFIXSAT);
3455
3456 // Handle special case when scale is equal to zero.
3457 if (!Scale) {
3458 SDValue Result;
3459 if (!Saturating) {
3460 Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3461 } else {
3462 EVT BoolVT = getSetCCResultType(VT);
3463 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
3464 Result = DAG.getNode(MulOp, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
3465 SDValue Product = Result.getValue(0);
3466 SDValue Overflow = Result.getValue(1);
3467 if (Signed) {
3468 APInt MinVal = APInt::getSignedMinValue(VTSize);
3469 APInt MaxVal = APInt::getSignedMaxValue(VTSize);
3470 SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
3471 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3472 SDValue Zero = DAG.getConstant(0, dl, VT);
3473 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT);
3474 Result = DAG.getSelect(dl, VT, ProdNeg, SatMax, SatMin);
3475 Result = DAG.getSelect(dl, VT, Overflow, Result, Product);
3476 } else {
3477 // For unsigned multiplication, we only need to check the max since we
3478 // can't really overflow towards zero.
3479 APInt MaxVal = APInt::getMaxValue(VTSize);
3480 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3481 Result = DAG.getSelect(dl, VT, Overflow, SatMax, Product);
3482 }
3483 }
3484 SplitInteger(Result, Lo, Hi);
3485 return;
3486 }
3487
3488 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
3489 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
3490 assert(Scale <= VTSize && "Scale can't be larger than the value type size.")(static_cast <bool> (Scale <= VTSize && "Scale can't be larger than the value type size."
) ? void (0) : __assert_fail ("Scale <= VTSize && \"Scale can't be larger than the value type size.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3490, __extension__ __PRETTY_FUNCTION__))
;
3491
3492 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3493 SDValue LL, LH, RL, RH;
3494 GetExpandedInteger(LHS, LL, LH);
3495 GetExpandedInteger(RHS, RL, RH);
3496 SmallVector<SDValue, 4> Result;
3497
3498 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
3499 if (!TLI.expandMUL_LOHI(LoHiOp, VT, dl, LHS, RHS, Result, NVT, DAG,
3500 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
3501 LL, LH, RL, RH)) {
3502 report_fatal_error("Unable to expand MUL_FIX using MUL_LOHI.");
3503 return;
3504 }
3505
3506 unsigned NVTSize = NVT.getScalarSizeInBits();
3507 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "(static_cast <bool> ((VTSize == NVTSize * 2) &&
"Expected the new value type to be half " "the size of the current value type"
) ? void (0) : __assert_fail ("(VTSize == NVTSize * 2) && \"Expected the new value type to be half \" \"the size of the current value type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3508, __extension__ __PRETTY_FUNCTION__))
3508 "the size of the current value type")(static_cast <bool> ((VTSize == NVTSize * 2) &&
"Expected the new value type to be half " "the size of the current value type"
) ? void (0) : __assert_fail ("(VTSize == NVTSize * 2) && \"Expected the new value type to be half \" \"the size of the current value type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3508, __extension__ __PRETTY_FUNCTION__))
;
3509 EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3510
3511 // After getting the multiplication result in 4 parts, we need to perform a
3512 // shift right by the amount of the scale to get the result in that scale.
3513 //
3514 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
3515 // 128 bits that are cut into 4 32-bit parts:
3516 //
3517 // HH HL LH LL
3518 // |---32---|---32---|---32---|---32---|
3519 // 128 96 64 32 0
3520 //
3521 // |------VTSize-----|
3522 //
3523 // |NVTSize-|
3524 //
3525 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
3526 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
3527 // amount and get Lo and Hi using two funnel shifts. Or for the special case
3528 // when Scale is a multiple of NVTSize we can just pick the result without
3529 // shifting.
3530 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
3531 if (Scale % NVTSize) {
3532 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy);
3533 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0],
3534 ShiftAmount);
3535 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1],
3536 ShiftAmount);
3537 } else {
3538 Lo = Result[Part0];
3539 Hi = Result[Part0 + 1];
3540 }
3541
3542 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
3543 if (!Saturating)
3544 return;
3545
3546 // Can not overflow when there is no integer part.
3547 if (Scale == VTSize)
3548 return;
3549
3550 // To handle saturation we must check for overflow in the multiplication.
3551 //
3552 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
3553 // aren't all zeroes.
3554 //
3555 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
3556 // aren't all ones or all zeroes.
3557 //
3558 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
3559 // highest bit of HH determines saturation direction in the event of signed
3560 // saturation.
3561
3562 SDValue ResultHL = Result[2];
3563 SDValue ResultHH = Result[3];
3564
3565 SDValue SatMax, SatMin;
3566 SDValue NVTZero = DAG.getConstant(0, dl, NVT);
3567 SDValue NVTNeg1 = DAG.getConstant(-1, dl, NVT);
3568 EVT BoolNVT = getSetCCResultType(NVT);
3569
3570 if (!Signed) {
3571 if (Scale < NVTSize) {
3572 // Overflow happened if ((HH | (HL >> Scale)) != 0).
3573 SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3574 DAG.getConstant(Scale, dl, ShiftTy));
3575 SDValue Tmp = DAG.getNode(ISD::OR, dl, NVT, HLAdjusted, ResultHH);
3576 SatMax = DAG.getSetCC(dl, BoolNVT, Tmp, NVTZero, ISD::SETNE);
3577 } else if (Scale == NVTSize) {
3578 // Overflow happened if (HH != 0).
3579 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETNE);
3580 } else if (Scale < VTSize) {
3581 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
3582 SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3583 DAG.getConstant(Scale - NVTSize, dl,
3584 ShiftTy));
3585 SatMax = DAG.getSetCC(dl, BoolNVT, HLAdjusted, NVTZero, ISD::SETNE);
3586 } else
3587 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"::llvm::llvm_unreachable_internal("Scale must be less or equal to VTSize for UMULFIXSAT"
"(and saturation can't happen with Scale==VTSize).", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3588)
3588 "(and saturation can't happen with Scale==VTSize).")::llvm::llvm_unreachable_internal("Scale must be less or equal to VTSize for UMULFIXSAT"
"(and saturation can't happen with Scale==VTSize).", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3588)
;
3589
3590 Hi = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Hi);
3591 Lo = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Lo);
3592 return;
3593 }
3594
3595 if (Scale < NVTSize) {
3596 // The number of overflow bits we can check are VTSize - Scale + 1 (we
3597 // include the sign bit). If these top bits are > 0, then we overflowed past
3598 // the max value. If these top bits are < -1, then we overflowed past the
3599 // min value. Otherwise, we did not overflow.
3600 unsigned OverflowBits = VTSize - Scale + 1;
3601 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&(static_cast <bool> (OverflowBits <= VTSize &&
OverflowBits > NVTSize && "Extent of overflow bits must start within HL"
) ? void (0) : __assert_fail ("OverflowBits <= VTSize && OverflowBits > NVTSize && \"Extent of overflow bits must start within HL\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3602, __extension__ __PRETTY_FUNCTION__))
3602 "Extent of overflow bits must start within HL")(static_cast <bool> (OverflowBits <= VTSize &&
OverflowBits > NVTSize && "Extent of overflow bits must start within HL"
) ? void (0) : __assert_fail ("OverflowBits <= VTSize && OverflowBits > NVTSize && \"Extent of overflow bits must start within HL\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3602, __extension__ __PRETTY_FUNCTION__))
;
3603 SDValue HLHiMask = DAG.getConstant(
3604 APInt::getHighBitsSet(NVTSize, OverflowBits - NVTSize), dl, NVT);
3605 SDValue HLLoMask = DAG.getConstant(
3606 APInt::getLowBitsSet(NVTSize, VTSize - OverflowBits), dl, NVT);
3607 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
3608 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3609 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3610 SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT);
3611 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3612 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLUGT));
3613 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
3614 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3615 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3616 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT);
3617 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3618 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLULT));
3619 } else if (Scale == NVTSize) {
3620 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
3621 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3622 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3623 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT);
3624 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3625 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLNeg));
3626 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
3627 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3628 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3629 SDValue HLPos = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETGE);
3630 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3631 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLPos));
3632 } else if (Scale < VTSize) {
3633 // This is similar to the case when we saturate if Scale < NVTSize, but we
3634 // only need to check HH.
3635 unsigned OverflowBits = VTSize - Scale + 1;
3636 SDValue HHHiMask = DAG.getConstant(
3637 APInt::getHighBitsSet(NVTSize, OverflowBits), dl, NVT);
3638 SDValue HHLoMask = DAG.getConstant(
3639 APInt::getLowBitsSet(NVTSize, NVTSize - OverflowBits), dl, NVT);
3640 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, HHLoMask, ISD::SETGT);
3641 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT);
3642 } else
3643 llvm_unreachable("Illegal scale for signed fixed point mul.")::llvm::llvm_unreachable_internal("Illegal scale for signed fixed point mul."
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3643)
;
3644
3645 // Saturate to signed maximum.
3646 APInt MaxHi = APInt::getSignedMaxValue(NVTSize);
3647 APInt MaxLo = APInt::getAllOnesValue(NVTSize);
3648 Hi = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxHi, dl, NVT), Hi);
3649 Lo = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxLo, dl, NVT), Lo);
3650 // Saturate to signed minimum.
3651 APInt MinHi = APInt::getSignedMinValue(NVTSize);
3652 Hi = DAG.getSelect(dl, NVT, SatMin, DAG.getConstant(MinHi, dl, NVT), Hi);
3653 Lo = DAG.getSelect(dl, NVT, SatMin, NVTZero, Lo);
3654}
3655
3656void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
3657 SDValue &Hi) {
3658 SDLoc dl(N);
3659 // Try expanding in the existing type first.
3660 SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, N->getOperand(0),
3661 N->getOperand(1),
3662 N->getConstantOperandVal(2), DAG);
3663
3664 if (!Res)
3665 Res = earlyExpandDIVFIX(N, N->getOperand(0), N->getOperand(1),
3666 N->getConstantOperandVal(2), TLI, DAG);
3667 SplitInteger(Res, Lo, Hi);
3668}
3669
3670void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
3671 SDValue &Lo, SDValue &Hi) {
3672 assert((Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) &&(static_cast <bool> ((Node->getOpcode() == ISD::SADDO
|| Node->getOpcode() == ISD::SSUBO) && "Node has unexpected Opcode"
) ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) && \"Node has unexpected Opcode\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3673, __extension__ __PRETTY_FUNCTION__))
3673 "Node has unexpected Opcode")(static_cast <bool> ((Node->getOpcode() == ISD::SADDO
|| Node->getOpcode() == ISD::SSUBO) && "Node has unexpected Opcode"
) ? void (0) : __assert_fail ("(Node->getOpcode() == ISD::SADDO || Node->getOpcode() == ISD::SSUBO) && \"Node has unexpected Opcode\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3673, __extension__ __PRETTY_FUNCTION__))
;
3674 SDValue LHS = Node->getOperand(0);
3675 SDValue RHS = Node->getOperand(1);
3676 SDLoc dl(Node);
3677
3678 SDValue Ovf;
3679
3680 bool IsAdd = Node->getOpcode() == ISD::SADDO;
3681 unsigned CarryOp = IsAdd ? ISD::SADDO_CARRY : ISD::SSUBO_CARRY;
3682
3683 bool HasCarryOp = TLI.isOperationLegalOrCustom(
3684 CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
3685
3686 if (HasCarryOp) {
3687 // Expand the subcomponents.
3688 SDValue LHSL, LHSH, RHSL, RHSH;
3689 GetExpandedInteger(LHS, LHSL, LHSH);
3690 GetExpandedInteger(RHS, RHSL, RHSH);
3691 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), Node->getValueType(1));
3692
3693 Lo = DAG.getNode(IsAdd ? ISD::UADDO : ISD::USUBO, dl, VTList, {LHSL, RHSL});
3694 Hi = DAG.getNode(CarryOp, dl, VTList, { LHSH, RHSH, Lo.getValue(1) });
3695
3696 Ovf = Hi.getValue(1);
3697 } else {
3698 // Expand the result by simply replacing it with the equivalent
3699 // non-overflow-checking operation.
3700 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3701 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3702 LHS, RHS);
3703 SplitInteger(Sum, Lo, Hi);
3704
3705 // Compute the overflow.
3706 //
3707 // LHSSign -> LHS < 0
3708 // RHSSign -> RHS < 0
3709 // SumSign -> Sum < 0
3710 //
3711 // Add:
3712 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3713 // Sub:
3714 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3715 //
3716 // To get better codegen we can rewrite this by doing bitwise math on
3717 // the integers and extract the final sign bit at the end. So the
3718 // above becomes:
3719 //
3720 // Add:
3721 // Overflow -> (~(LHS ^ RHS) & (LHS ^ Sum)) < 0
3722 // Sub:
3723 // Overflow -> ((LHS ^ RHS) & (LHS ^ Sum)) < 0
3724 //
3725 // NOTE: This is different than the expansion we do in expandSADDSUBO
3726 // because it is more costly to determine the RHS is > 0 for SSUBO with the
3727 // integers split.
3728 EVT VT = LHS.getValueType();
3729 SDValue SignsMatch = DAG.getNode(ISD::XOR, dl, VT, LHS, RHS);
3730 if (IsAdd)
3731 SignsMatch = DAG.getNOT(dl, SignsMatch, VT);
3732
3733 SDValue SumSignNE = DAG.getNode(ISD::XOR, dl, VT, LHS, Sum);
3734 Ovf = DAG.getNode(ISD::AND, dl, VT, SignsMatch, SumSignNE);
3735 EVT OType = Node->getValueType(1);
3736 Ovf = DAG.getSetCC(dl, OType, Ovf, DAG.getConstant(0, dl, VT), ISD::SETLT);
3737 }
3738
3739 // Use the calculated overflow everywhere.
3740 ReplaceValueWith(SDValue(Node, 1), Ovf);
3741}
3742
3743void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
3744 SDValue &Lo, SDValue &Hi) {
3745 EVT VT = N->getValueType(0);
3746 SDLoc dl(N);
3747 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3748
3749 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3750 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3751 SplitInteger(Res.getValue(0), Lo, Hi);
3752 return;
3753 }
3754
3755 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3756 if (VT == MVT::i16)
3757 LC = RTLIB::SDIV_I16;
3758 else if (VT == MVT::i32)
3759 LC = RTLIB::SDIV_I32;
3760 else if (VT == MVT::i64)
3761 LC = RTLIB::SDIV_I64;
3762 else if (VT == MVT::i128)
3763 LC = RTLIB::SDIV_I128;
3764 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unsupported SDIV!") ? void (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported SDIV!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3764, __extension__ __PRETTY_FUNCTION__))
;
3765
3766 TargetLowering::MakeLibCallOptions CallOptions;
3767 CallOptions.setSExt(true);
3768 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3769}
3770
3771void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
3772 SDValue &Lo, SDValue &Hi) {
3773 EVT VT = N->getValueType(0);
3774 SDLoc dl(N);
3775
3776 // If we can emit an efficient shift operation, do so now. Check to see if
3777 // the RHS is a constant.
3778 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
7
Assuming 'CN' is null
8
Taking false branch
3779 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
3780
3781 // If we can determine that the high bit of the shift is zero or one, even if
3782 // the low bits are variable, emit this shift in an optimized form.
3783 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
9
Calling 'DAGTypeLegalizer::ExpandShiftWithKnownAmountBit'
3784 return;
3785
3786 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
3787 unsigned PartsOpc;
3788 if (N->getOpcode() == ISD::SHL) {
3789 PartsOpc = ISD::SHL_PARTS;
3790 } else if (N->getOpcode() == ISD::SRL) {
3791 PartsOpc = ISD::SRL_PARTS;
3792 } else {
3793 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")(static_cast <bool> (N->getOpcode() == ISD::SRA &&
"Unknown shift!") ? void (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3793, __extension__ __PRETTY_FUNCTION__))
;
3794 PartsOpc = ISD::SRA_PARTS;
3795 }
3796
3797 // Next check to see if the target supports this SHL_PARTS operation or if it
3798 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
3799 // size, but create a libcall instead.
3800 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3801 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
3802 const bool LegalOrCustom =
3803 (Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3804 Action == TargetLowering::Custom;
3805
3806 if (LegalOrCustom && TLI.shouldExpandShift(DAG, N)) {
3807 // Expand the subcomponents.
3808 SDValue LHSL, LHSH;
3809 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
3810 EVT VT = LHSL.getValueType();
3811
3812 // If the shift amount operand is coming from a vector legalization it may
3813 // have an illegal type. Fix that first by casting the operand, otherwise
3814 // the new SHL_PARTS operation would need further legalization.
3815 SDValue ShiftOp = N->getOperand(1);
3816 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3817 assert(ShiftTy.getScalarSizeInBits() >=(static_cast <bool> (ShiftTy.getScalarSizeInBits() >=
Log2_32_Ceil(VT.getScalarSizeInBits()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? void (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3819, __extension__ __PRETTY_FUNCTION__))
3818 Log2_32_Ceil(VT.getScalarSizeInBits()) &&(static_cast <bool> (ShiftTy.getScalarSizeInBits() >=
Log2_32_Ceil(VT.getScalarSizeInBits()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? void (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3819, __extension__ __PRETTY_FUNCTION__))
3819 "ShiftAmountTy is too small to cover the range of this type!")(static_cast <bool> (ShiftTy.getScalarSizeInBits() >=
Log2_32_Ceil(VT.getScalarSizeInBits()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? void (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3819, __extension__ __PRETTY_FUNCTION__))
;
3820 if (ShiftOp.getValueType() != ShiftTy)
3821 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
3822
3823 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
3824 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
3825 Hi = Lo.getValue(1);
3826 return;
3827 }
3828
3829 // Otherwise, emit a libcall.
3830 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3831 bool isSigned;
3832 if (N->getOpcode() == ISD::SHL) {
3833 isSigned = false; /*sign irrelevant*/
3834 if (VT == MVT::i16)
3835 LC = RTLIB::SHL_I16;
3836 else if (VT == MVT::i32)
3837 LC = RTLIB::SHL_I32;
3838 else if (VT == MVT::i64)
3839 LC = RTLIB::SHL_I64;
3840 else if (VT == MVT::i128)
3841 LC = RTLIB::SHL_I128;
3842 } else if (N->getOpcode() == ISD::SRL) {
3843 isSigned = false;
3844 if (VT == MVT::i16)
3845 LC = RTLIB::SRL_I16;
3846 else if (VT == MVT::i32)
3847 LC = RTLIB::SRL_I32;
3848 else if (VT == MVT::i64)
3849 LC = RTLIB::SRL_I64;
3850 else if (VT == MVT::i128)
3851 LC = RTLIB::SRL_I128;
3852 } else {
3853 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")(static_cast <bool> (N->getOpcode() == ISD::SRA &&
"Unknown shift!") ? void (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3853, __extension__ __PRETTY_FUNCTION__))
;
3854 isSigned = true;
3855 if (VT == MVT::i16)
3856 LC = RTLIB::SRA_I16;
3857 else if (VT == MVT::i32)
3858 LC = RTLIB::SRA_I32;
3859 else if (VT == MVT::i64)
3860 LC = RTLIB::SRA_I64;
3861 else if (VT == MVT::i128)
3862 LC = RTLIB::SRA_I128;
3863 }
3864
3865 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
3866 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3867 TargetLowering::MakeLibCallOptions CallOptions;
3868 CallOptions.setSExt(isSigned);
3869 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3870 return;
3871 }
3872
3873 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
3874 llvm_unreachable("Unsupported shift!")::llvm::llvm_unreachable_internal("Unsupported shift!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3874)
;
3875}
3876
3877void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
3878 SDValue &Lo, SDValue &Hi) {
3879 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3880 SDLoc dl(N);
3881 SDValue Op = N->getOperand(0);
3882 if (Op.getValueType().bitsLE(NVT)) {
3883 // The low part is sign extension of the input (degenerates to a copy).
3884 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
3885 // The high part is obtained by SRA'ing all but one of the bits of low part.
3886 unsigned LoSize = NVT.getSizeInBits();
3887 Hi = DAG.getNode(
3888 ISD::SRA, dl, NVT, Lo,
3889 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
3890 } else {
3891 // For example, extension of an i48 to an i64. The operand type necessarily
3892 // promotes to the result type, so will end up being expanded too.
3893 assert(getTypeAction(Op.getValueType()) ==(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3895, __extension__ __PRETTY_FUNCTION__))
3894 TargetLowering::TypePromoteInteger &&(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3895, __extension__ __PRETTY_FUNCTION__))
3895 "Only know how to promote this result!")(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3895, __extension__ __PRETTY_FUNCTION__))
;
3896 SDValue Res = GetPromotedInteger(Op);
3897 assert(Res.getValueType() == N->getValueType(0) &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3898, __extension__ __PRETTY_FUNCTION__))
3898 "Operand over promoted?")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3898, __extension__ __PRETTY_FUNCTION__))
;
3899 // Split the promoted operand. This will simplify when it is expanded.
3900 SplitInteger(Res, Lo, Hi);
3901 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
3902 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
3903 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
3904 ExcessBits)));
3905 }
3906}
3907
3908void DAGTypeLegalizer::
3909ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
3910 SDLoc dl(N);
3911 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3912 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3913
3914 if (EVT.bitsLE(Lo.getValueType())) {
3915 // sext_inreg the low part if needed.
3916 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
3917 N->getOperand(1));
3918
3919 // The high part gets the sign extension from the lo-part. This handles
3920 // things like sextinreg V:i64 from i8.
3921 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
3922 DAG.getConstant(Hi.getValueSizeInBits() - 1, dl,
3923 TLI.getPointerTy(DAG.getDataLayout())));
3924 } else {
3925 // For example, extension of an i48 to an i64. Leave the low part alone,
3926 // sext_inreg the high part.
3927 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
3928 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
3929 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
3930 ExcessBits)));
3931 }
3932}
3933
3934void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
3935 SDValue &Lo, SDValue &Hi) {
3936 EVT VT = N->getValueType(0);
3937 SDLoc dl(N);
3938 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3939
3940 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3941 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3942 SplitInteger(Res.getValue(1), Lo, Hi);
3943 return;
3944 }
3945
3946 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3947 if (VT == MVT::i16)
3948 LC = RTLIB::SREM_I16;
3949 else if (VT == MVT::i32)
3950 LC = RTLIB::SREM_I32;
3951 else if (VT == MVT::i64)
3952 LC = RTLIB::SREM_I64;
3953 else if (VT == MVT::i128)
3954 LC = RTLIB::SREM_I128;
3955 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unsupported SREM!") ? void (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported SREM!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3955, __extension__ __PRETTY_FUNCTION__))
;
3956
3957 TargetLowering::MakeLibCallOptions CallOptions;
3958 CallOptions.setSExt(true);
3959 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3960}
3961
3962void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
3963 SDValue &Lo, SDValue &Hi) {
3964 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3965 SDLoc dl(N);
3966 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
3967 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
3968 N->getOperand(0),
3969 DAG.getConstant(NVT.getSizeInBits(), dl,
3970 TLI.getPointerTy(DAG.getDataLayout())));
3971 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
3972}
3973
3974void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
3975 SDValue &Lo, SDValue &Hi) {
3976 EVT VT = N->getValueType(0);
3977 SDLoc dl(N);
3978
3979 if (N->getOpcode() == ISD::UMULO) {
3980 // This section expands the operation into the following sequence of
3981 // instructions. `iNh` here refers to a type which has half the bit width of
3982 // the type the original operation operated on.
3983 //
3984 // %0 = %LHS.HI != 0 && %RHS.HI != 0
3985 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
3986 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
3987 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
3988 // %4 = add iNh %1.0, %2.0 as iN
3989 // %5 = { iNh, i1 } @uadd.with.overflow.iNh(iNh %4, iNh %3.HIGH)
3990 //
3991 // %lo = %3.LO
3992 // %hi = %5.0
3993 // %ovf = %0 || %1.1 || %2.1 || %5.1
3994 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
3995 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
3996 GetExpandedInteger(LHS, LHSLow, LHSHigh);
3997 GetExpandedInteger(RHS, RHSLow, RHSHigh);
3998 EVT HalfVT = LHSLow.getValueType();
3999 EVT BitVT = N->getValueType(1);
4000 SDVTList VTHalfWithO = DAG.getVTList(HalfVT, BitVT);
4001
4002 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT);
4003 SDValue Overflow = DAG.getNode(ISD::AND, dl, BitVT,
4004 DAG.getSetCC(dl, BitVT, LHSHigh, HalfZero, ISD::SETNE),
4005 DAG.getSetCC(dl, BitVT, RHSHigh, HalfZero, ISD::SETNE));
4006
4007 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfWithO, LHSHigh, RHSLow);
4008 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, One.getValue(1));
4009
4010 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfWithO, RHSHigh, LHSLow);
4011 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Two.getValue(1));
4012
4013 SDValue HighSum = DAG.getNode(ISD::ADD, dl, HalfVT, One, Two);
4014
4015 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
4016 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
4017 // operation recursively legalized?).
4018 //
4019 // Many backends understand this pattern and will convert into LOHI
4020 // themselves, if applicable.
4021 SDValue Three = DAG.getNode(ISD::MUL, dl, VT,
4022 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LHSLow),
4023 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RHSLow));
4024 SplitInteger(Three, Lo, Hi);
4025
4026 Hi = DAG.getNode(ISD::UADDO, dl, VTHalfWithO, Hi, HighSum);
4027 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Hi.getValue(1));
4028 ReplaceValueWith(SDValue(N, 1), Overflow);
4029 return;
4030 }
4031
4032 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
4033 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
4034 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
4035
4036 // Replace this with a libcall that will check overflow.
4037 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4038 if (VT == MVT::i32)
4039 LC = RTLIB::MULO_I32;
4040 else if (VT == MVT::i64)
4041 LC = RTLIB::MULO_I64;
4042 else if (VT == MVT::i128)
4043 LC = RTLIB::MULO_I128;
4044
4045 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
4046 // FIXME: This is not an optimal expansion, but better than crashing.
4047 EVT WideVT =
4048 EVT::getIntegerVT(*DAG.getContext(), VT.getScalarSizeInBits() * 2);
4049 SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, WideVT, N->getOperand(0));
4050 SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, WideVT, N->getOperand(1));
4051 SDValue Mul = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
4052 SDValue MulLo, MulHi;
4053 SplitInteger(Mul, MulLo, MulHi);
4054 SDValue SRA =
4055 DAG.getNode(ISD::SRA, dl, VT, MulLo,
4056 DAG.getConstant(VT.getScalarSizeInBits() - 1, dl, VT));
4057 SDValue Overflow =
4058 DAG.getSetCC(dl, N->getValueType(1), MulHi, SRA, ISD::SETNE);
4059 SplitInteger(MulLo, Lo, Hi);
4060 ReplaceValueWith(SDValue(N, 1), Overflow);
4061 return;
4062 }
4063
4064 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
4065 // Temporary for the overflow value, default it to zero.
4066 SDValue Chain =
4067 DAG.getStore(DAG.getEntryNode(), dl, DAG.getConstant(0, dl, PtrVT), Temp,
4068 MachinePointerInfo());
4069
4070 TargetLowering::ArgListTy Args;
4071 TargetLowering::ArgListEntry Entry;
4072 for (const SDValue &Op : N->op_values()) {
4073 EVT ArgVT = Op.getValueType();
4074 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
4075 Entry.Node = Op;
4076 Entry.Ty = ArgTy;
4077 Entry.IsSExt = true;
4078 Entry.IsZExt = false;
4079 Args.push_back(Entry);
4080 }
4081
4082 // Also pass the address of the overflow check.
4083 Entry.Node = Temp;
4084 Entry.Ty = PtrTy->getPointerTo();
4085 Entry.IsSExt = true;
4086 Entry.IsZExt = false;
4087 Args.push_back(Entry);
4088
4089 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
4090
4091 TargetLowering::CallLoweringInfo CLI(DAG);
4092 CLI.setDebugLoc(dl)
4093 .setChain(Chain)
4094 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args))
4095 .setSExtResult();
4096
4097 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
4098
4099 SplitInteger(CallInfo.first, Lo, Hi);
4100 SDValue Temp2 =
4101 DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, MachinePointerInfo());
4102 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
4103 DAG.getConstant(0, dl, PtrVT),
4104 ISD::SETNE);
4105 // Use the overflow from the libcall everywhere.
4106 ReplaceValueWith(SDValue(N, 1), Ofl);
4107}
4108
4109void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
4110 SDValue &Lo, SDValue &Hi) {
4111 EVT VT = N->getValueType(0);
4112 SDLoc dl(N);
4113 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
4114
4115 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
4116 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
4117 SplitInteger(Res.getValue(0), Lo, Hi);
4118 return;
4119 }
4120
4121 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4122 if (VT == MVT::i16)
4123 LC = RTLIB::UDIV_I16;
4124 else if (VT == MVT::i32)
4125 LC = RTLIB::UDIV_I32;
4126 else if (VT == MVT::i64)
4127 LC = RTLIB::UDIV_I64;
4128 else if (VT == MVT::i128)
4129 LC = RTLIB::UDIV_I128;
4130 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unsupported UDIV!") ? void (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported UDIV!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4130, __extension__ __PRETTY_FUNCTION__))
;
4131
4132 TargetLowering::MakeLibCallOptions CallOptions;
4133 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4134}
4135
4136void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
4137 SDValue &Lo, SDValue &Hi) {
4138 EVT VT = N->getValueType(0);
4139 SDLoc dl(N);
4140 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
4141
4142 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
4143 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
4144 SplitInteger(Res.getValue(1), Lo, Hi);
4145 return;
4146 }
4147
4148 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
4149 if (VT == MVT::i16)
4150 LC = RTLIB::UREM_I16;
4151 else if (VT == MVT::i32)
4152 LC = RTLIB::UREM_I32;
4153 else if (VT == MVT::i64)
4154 LC = RTLIB::UREM_I64;
4155 else if (VT == MVT::i128)
4156 LC = RTLIB::UREM_I128;
4157 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Unsupported UREM!") ? void (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported UREM!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4157, __extension__ __PRETTY_FUNCTION__))
;
4158
4159 TargetLowering::MakeLibCallOptions CallOptions;
4160 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
4161}
4162
4163void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
4164 SDValue &Lo, SDValue &Hi) {
4165 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4166 SDLoc dl(N);
4167 SDValue Op = N->getOperand(0);
4168 if (Op.getValueType().bitsLE(NVT)) {
4169 // The low part is zero extension of the input (degenerates to a copy).
4170 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
4171 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
4172 } else {
4173 // For example, extension of an i48 to an i64. The operand type necessarily
4174 // promotes to the result type, so will end up being expanded too.
4175 assert(getTypeAction(Op.getValueType()) ==(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4177, __extension__ __PRETTY_FUNCTION__))
4176 TargetLowering::TypePromoteInteger &&(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4177, __extension__ __PRETTY_FUNCTION__))
4177 "Only know how to promote this result!")(static_cast <bool> (getTypeAction(Op.getValueType()) ==
TargetLowering::TypePromoteInteger && "Only know how to promote this result!"
) ? void (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4177, __extension__ __PRETTY_FUNCTION__))
;
4178 SDValue Res = GetPromotedInteger(Op);
4179 assert(Res.getValueType() == N->getValueType(0) &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4180, __extension__ __PRETTY_FUNCTION__))
4180 "Operand over promoted?")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && "Operand over promoted?") ? void (0) : __assert_fail
("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4180, __extension__ __PRETTY_FUNCTION__))
;
4181 // Split the promoted operand. This will simplify when it is expanded.
4182 SplitInteger(Res, Lo, Hi);
4183 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
4184 Hi = DAG.getZeroExtendInReg(Hi, dl,
4185 EVT::getIntegerVT(*DAG.getContext(),
4186 ExcessBits));
4187 }
4188}
4189
4190void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
4191 SDValue &Lo, SDValue &Hi) {
4192 SDLoc dl(N);
4193 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
4194 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
4195 SDValue Zero = DAG.getConstant(0, dl, VT);
4196 SDValue Swap = DAG.getAtomicCmpSwap(
4197 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
4198 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
4199 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand());
4200
4201 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
4202 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
4203}
4204
4205void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
4206 SDValue &Lo, SDValue &Hi) {
4207 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
4208 // both halves independently.
4209 SDValue Res = TLI.expandVecReduce(N, DAG);
4210 SplitInteger(Res, Lo, Hi);
4211}
4212
4213void DAGTypeLegalizer::ExpandIntRes_Rotate(SDNode *N,
4214 SDValue &Lo, SDValue &Hi) {
4215 // Lower the rotate to shifts and ORs which can be expanded.
4216 SDValue Res;
4217 TLI.expandROT(N, true /*AllowVectorOps*/, Res, DAG);
4218 SplitInteger(Res, Lo, Hi);
4219}
4220
4221void DAGTypeLegalizer::ExpandIntRes_FunnelShift(SDNode *N,
4222 SDValue &Lo, SDValue &Hi) {
4223 // Lower the funnel shift to shifts and ORs which can be expanded.
4224 SDValue Res;
4225 TLI.expandFunnelShift(N, Res, DAG);
4226 SplitInteger(Res, Lo, Hi);
4227}
4228
4229void DAGTypeLegalizer::ExpandIntRes_VSCALE(SDNode *N, SDValue &Lo,
4230 SDValue &Hi) {
4231 EVT VT = N->getValueType(0);
4232 EVT HalfVT =
4233 EVT::getIntegerVT(*DAG.getContext(), N->getValueSizeInBits(0) / 2);
4234 SDLoc dl(N);
4235
4236 // We assume VSCALE(1) fits into a legal integer.
4237 APInt One(HalfVT.getSizeInBits(), 1);
4238 SDValue VScaleBase = DAG.getVScale(dl, HalfVT, One);
4239 VScaleBase = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, VScaleBase);
4240 SDValue Res = DAG.getNode(ISD::MUL, dl, VT, VScaleBase, N->getOperand(0));
4241 SplitInteger(Res, Lo, Hi);
4242}
4243
4244//===----------------------------------------------------------------------===//
4245// Integer Operand Expansion
4246//===----------------------------------------------------------------------===//
4247
4248/// ExpandIntegerOperand - This method is called when the specified operand of
4249/// the specified node is found to need expansion. At this point, all of the
4250/// result types of the node are known to be legal, but other operands of the
4251/// node may need promotion or expansion as well as the specified one.
4252bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
4253 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
4254 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
4255 SDValue Res = SDValue();
4256
4257 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
4258 return false;
4259
4260 switch (N->getOpcode()) {
4261 default:
4262 #ifndef NDEBUG
4263 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
4264 N->dump(&DAG); dbgs() << "\n";
4265 #endif
4266 report_fatal_error("Do not know how to expand this operator's operand!");
4267
4268 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
4269 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
4270 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
4271 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
4272 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
4273 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
4274 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break;
4275 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
4276 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
4277 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
4278 case ISD::STRICT_SINT_TO_FP:
4279 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
4280 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
4281 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
4282 case ISD::STRICT_UINT_TO_FP:
4283 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
4284
4285 case ISD::SHL:
4286 case ISD::SRA:
4287 case ISD::SRL:
4288 case ISD::ROTL:
4289 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
4290 case ISD::RETURNADDR:
4291 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
4292
4293 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
4294 }
4295
4296 // If the result is null, the sub-method took care of registering results etc.
4297 if (!Res.getNode()) return false;
4298
4299 // If the result is N, the sub-method updated N in place. Tell the legalizer
4300 // core about this.
4301 if (Res.getNode() == N)
4302 return true;
4303
4304 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == 1 && "Invalid operand expansion"
) ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4305, __extension__ __PRETTY_FUNCTION__))
4305 "Invalid operand expansion")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == 1 && "Invalid operand expansion"
) ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4305, __extension__ __PRETTY_FUNCTION__))
;
4306
4307 ReplaceValueWith(SDValue(N, 0), Res);
4308 return false;
4309}
4310
4311/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
4312/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
4313void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
4314 SDValue &NewRHS,
4315 ISD::CondCode &CCCode,
4316 const SDLoc &dl) {
4317 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4318 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
4319 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
4320
4321 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
4322 if (RHSLo == RHSHi) {
4323 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
4324 if (RHSCST->isAllOnesValue()) {
4325 // Equality comparison to -1.
4326 NewLHS = DAG.getNode(ISD::AND, dl,
4327 LHSLo.getValueType(), LHSLo, LHSHi);
4328 NewRHS = RHSLo;
4329 return;
4330 }
4331 }
4332 }
4333
4334 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
4335 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
4336 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
4337 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
4338 return;
4339 }
4340
4341 // If this is a comparison of the sign bit, just look at the top part.
4342 // X > -1, x < 0
4343 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
4344 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
4345 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
4346 NewLHS = LHSHi;
4347 NewRHS = RHSHi;
4348 return;
4349 }
4350
4351 // FIXME: This generated code sucks.
4352 ISD::CondCode LowCC;
4353 switch (CCCode) {
4354 default: llvm_unreachable("Unknown integer setcc!")::llvm::llvm_unreachable_internal("Unknown integer setcc!", "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4354)
;
4355 case ISD::SETLT:
4356 case ISD::SETULT: LowCC = ISD::SETULT; break;
4357 case ISD::SETGT:
4358 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4359 case ISD::SETLE:
4360 case ISD::SETULE: LowCC = ISD::SETULE; break;
4361 case ISD::SETGE:
4362 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4363 }
4364
4365 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
4366 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
4367 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
4368
4369 // NOTE: on targets without efficient SELECT of bools, we can always use
4370 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4371 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
4372 nullptr);
4373 SDValue LoCmp, HiCmp;
4374 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
4375 TLI.isTypeLegal(RHSLo.getValueType()))
4376 LoCmp = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()), LHSLo,
4377 RHSLo, LowCC, false, DagCombineInfo, dl);
4378 if (!LoCmp.getNode())
4379 LoCmp = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo,
4380 RHSLo, LowCC);
4381 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
4382 TLI.isTypeLegal(RHSHi.getValueType()))
4383 HiCmp = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()), LHSHi,
4384 RHSHi, CCCode, false, DagCombineInfo, dl);
4385 if (!HiCmp.getNode())
4386 HiCmp =
4387 DAG.getNode(ISD::SETCC, dl, getSetCCResultType(LHSHi.getValueType()),
4388 LHSHi, RHSHi, DAG.getCondCode(CCCode));
4389
4390 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(LoCmp.getNode());
4391 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(HiCmp.getNode());
4392
4393 bool EqAllowed = (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4394 CCCode == ISD::SETUGE || CCCode == ISD::SETULE);
4395
4396 if ((EqAllowed && (HiCmpC && HiCmpC->isNullValue())) ||
4397 (!EqAllowed && ((HiCmpC && (HiCmpC->getAPIntValue() == 1)) ||
4398 (LoCmpC && LoCmpC->isNullValue())))) {
4399 // For LE / GE, if high part is known false, ignore the low part.
4400 // For LT / GT: if low part is known false, return the high part.
4401 // if high part is known true, ignore the low part.
4402 NewLHS = HiCmp;
4403 NewRHS = SDValue();
4404 return;
4405 }
4406
4407 if (LHSHi == RHSHi) {
4408 // Comparing the low bits is enough.
4409 NewLHS = LoCmp;
4410 NewRHS = SDValue();
4411 return;
4412 }
4413
4414 // Lower with SETCCCARRY if the target supports it.
4415 EVT HiVT = LHSHi.getValueType();
4416 EVT ExpandVT = TLI.getTypeToExpandTo(*DAG.getContext(), HiVT);
4417 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(ISD::SETCCCARRY, ExpandVT);
4418
4419 // FIXME: Make all targets support this, then remove the other lowering.
4420 if (HasSETCCCARRY) {
4421 // SETCCCARRY can detect < and >= directly. For > and <=, flip
4422 // operands and condition code.
4423 bool FlipOperands = false;
4424 switch (CCCode) {
4425 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
4426 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
4427 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
4428 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
4429 default: break;
4430 }
4431 if (FlipOperands) {
4432 std::swap(LHSLo, RHSLo);
4433 std::swap(LHSHi, RHSHi);
4434 }
4435 // Perform a wide subtraction, feeding the carry from the low part into
4436 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
4437 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
4438 // zero or positive iff LHS >= RHS.
4439 EVT LoVT = LHSLo.getValueType();
4440 SDVTList VTList = DAG.getVTList(LoVT, getSetCCResultType(LoVT));
4441 SDValue LowCmp = DAG.getNode(ISD::USUBO, dl, VTList, LHSLo, RHSLo);
4442 SDValue Res = DAG.getNode(ISD::SETCCCARRY, dl, getSetCCResultType(HiVT),
4443 LHSHi, RHSHi, LowCmp.getValue(1),
4444 DAG.getCondCode(CCCode));
4445 NewLHS = Res;
4446 NewRHS = SDValue();
4447 return;
4448 }
4449
4450 NewLHS = TLI.SimplifySetCC(getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ,
4451 false, DagCombineInfo, dl);
4452 if (!NewLHS.getNode())
4453 NewLHS =
4454 DAG.getSetCC(dl, getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ);
4455 NewLHS = DAG.getSelect(dl, LoCmp.getValueType(), NewLHS, LoCmp, HiCmp);
4456 NewRHS = SDValue();
4457}
4458
4459SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
4460 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
4461 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
4462 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
4463
4464 // If ExpandSetCCOperands returned a scalar, we need to compare the result
4465 // against zero to select between true and false values.
4466 if (!NewRHS.getNode()) {
4467 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
4468 CCCode = ISD::SETNE;
4469 }
4470
4471 // Update N to have the operands specified.
4472 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
4473 DAG.getCondCode(CCCode), NewLHS, NewRHS,
4474 N->getOperand(4)), 0);
4475}
4476
4477SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
4478 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
4479 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
4480 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
4481
4482 // If ExpandSetCCOperands returned a scalar, we need to compare the result
4483 // against zero to select between true and false values.
4484 if (!NewRHS.getNode()) {
4485 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
4486 CCCode = ISD::SETNE;
4487 }
4488
4489 // Update N to have the operands specified.
4490 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
4491 N->getOperand(2), N->getOperand(3),
4492 DAG.getCondCode(CCCode)), 0);
4493}
4494
4495SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
4496 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
4497 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
4498 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
4499
4500 // If ExpandSetCCOperands returned a scalar, use it.
4501 if (!NewRHS.getNode()) {
4502 assert(NewLHS.getValueType() == N->getValueType(0) &&(static_cast <bool> (NewLHS.getValueType() == N->getValueType
(0) && "Unexpected setcc expansion!") ? void (0) : __assert_fail
("NewLHS.getValueType() == N->getValueType(0) && \"Unexpected setcc expansion!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4503, __extension__ __PRETTY_FUNCTION__))
4503 "Unexpected setcc expansion!")(static_cast <bool> (NewLHS.getValueType() == N->getValueType
(0) && "Unexpected setcc expansion!") ? void (0) : __assert_fail
("NewLHS.getValueType() == N->getValueType(0) && \"Unexpected setcc expansion!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4503, __extension__ __PRETTY_FUNCTION__))
;
4504 return NewLHS;
4505 }
4506
4507 // Otherwise, update N to have the operands specified.
4508 return SDValue(
4509 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0);
4510}
4511
4512SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
4513 SDValue LHS = N->getOperand(0);
4514 SDValue RHS = N->getOperand(1);
4515 SDValue Carry = N->getOperand(2);
4516 SDValue Cond = N->getOperand(3);
4517 SDLoc dl = SDLoc(N);
4518
4519 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4520 GetExpandedInteger(LHS, LHSLo, LHSHi);
4521 GetExpandedInteger(RHS, RHSLo, RHSHi);
4522
4523 // Expand to a SUBE for the low part and a smaller SETCCCARRY for the high.
4524 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), Carry.getValueType());
4525 SDValue LowCmp = DAG.getNode(ISD::SUBCARRY, dl, VTList, LHSLo, RHSLo, Carry);
4526 return DAG.getNode(ISD::SETCCCARRY, dl, N->getValueType(0), LHSHi, RHSHi,
4527 LowCmp.getValue(1), Cond);
4528}
4529
4530SDValue DAGTypeLegalizer::ExpandIntOp_SPLAT_VECTOR(SDNode *N) {
4531 // Split the operand and replace with SPLAT_VECTOR_PARTS.
4532 SDValue Lo, Hi;
4533 GetExpandedInteger(N->getOperand(0), Lo, Hi);
4534 return DAG.getNode(ISD::SPLAT_VECTOR_PARTS, SDLoc(N), N->getValueType(0), Lo,
4535 Hi);
4536}
4537
4538SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
4539 // The value being shifted is legal, but the shift amount is too big.
4540 // It follows that either the result of the shift is undefined, or the
4541 // upper half of the shift amount is zero. Just use the lower half.
4542 SDValue Lo, Hi;
4543 GetExpandedInteger(N->getOperand(1), Lo, Hi);
4544 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
4545}
4546
4547SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
4548 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
4549 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
4550 // constant to valid type.
4551 SDValue Lo, Hi;
4552 GetExpandedInteger(N->getOperand(0), Lo, Hi);
4553 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
4554}
4555
4556SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
4557 bool IsStrict = N->isStrictFPOpcode();
4558 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
4559 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
4560 EVT DstVT = N->getValueType(0);
4561 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
4562 assert(LC != RTLIB::UNKNOWN_LIBCALL &&(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Don't know how to expand this SINT_TO_FP!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this SINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4563, __extension__ __PRETTY_FUNCTION__))
4563 "Don't know how to expand this SINT_TO_FP!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Don't know how to expand this SINT_TO_FP!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this SINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4563, __extension__ __PRETTY_FUNCTION__))
;
4564 TargetLowering::MakeLibCallOptions CallOptions;
4565 CallOptions.setSExt(true);
4566 std::pair<SDValue, SDValue> Tmp =
4567 TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
4568
4569 if (!IsStrict)
4570 return Tmp.first;
4571
4572 ReplaceValueWith(SDValue(N, 1), Tmp.second);
4573 ReplaceValueWith(SDValue(N, 0), Tmp.first);
4574 return SDValue();
4575}
4576
4577SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
4578 if (N->isAtomic()) {
4579 // It's typical to have larger CAS than atomic store instructions.
4580 SDLoc dl(N);
4581 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
4582 N->getMemoryVT(),
4583 N->getOperand(0), N->getOperand(2),
4584 N->getOperand(1),
4585 N->getMemOperand());
4586 return Swap.getValue(1);
4587 }
4588 if (ISD::isNormalStore(N))
4589 return ExpandOp_NormalStore(N, OpNo);
4590
4591 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!")(static_cast <bool> (ISD::isUNINDEXEDStore(N) &&
"Indexed store during type legalization!") ? void (0) : __assert_fail
("ISD::isUNINDEXEDStore(N) && \"Indexed store during type legalization!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4591, __extension__ __PRETTY_FUNCTION__))
;
4592 assert(OpNo == 1 && "Can only expand the stored value so far")(static_cast <bool> (OpNo == 1 && "Can only expand the stored value so far"
) ? void (0) : __assert_fail ("OpNo == 1 && \"Can only expand the stored value so far\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4592, __extension__ __PRETTY_FUNCTION__))
;
4593
4594 EVT VT = N->getOperand(1).getValueType();
4595 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4596 SDValue Ch = N->getChain();
4597 SDValue Ptr = N->getBasePtr();
4598 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4599 AAMDNodes AAInfo = N->getAAInfo();
4600 SDLoc dl(N);
4601 SDValue Lo, Hi;
4602
4603 assert(NVT.isByteSized() && "Expanded type not byte sized!")(static_cast <bool> (NVT.isByteSized() && "Expanded type not byte sized!"
) ? void (0) : __assert_fail ("NVT.isByteSized() && \"Expanded type not byte sized!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4603, __extension__ __PRETTY_FUNCTION__))
;
4604
4605 if (N->getMemoryVT().bitsLE(NVT)) {
4606 GetExpandedInteger(N->getValue(), Lo, Hi);
4607 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
4608 N->getMemoryVT(), N->getOriginalAlign(), MMOFlags,
4609 AAInfo);
4610 }
4611
4612 if (DAG.getDataLayout().isLittleEndian()) {
4613 // Little-endian - low bits are at low addresses.
4614 GetExpandedInteger(N->getValue(), Lo, Hi);
4615
4616 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
4617 N->getOriginalAlign(), MMOFlags, AAInfo);
4618
4619 unsigned ExcessBits =
4620 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4621 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
4622
4623 // Increment the pointer to the other half.
4624 unsigned IncrementSize = NVT.getSizeInBits()/8;
4625 Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
4626 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
4627 N->getPointerInfo().getWithOffset(IncrementSize),
4628 NEVT, N->getOriginalAlign(), MMOFlags, AAInfo);
4629 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
4630 }
4631
4632 // Big-endian - high bits are at low addresses. Favor aligned stores at
4633 // the cost of some bit-fiddling.
4634 GetExpandedInteger(N->getValue(), Lo, Hi);
4635
4636 EVT ExtVT = N->getMemoryVT();
4637 unsigned EBytes = ExtVT.getStoreSize();
4638 unsigned IncrementSize = NVT.getSizeInBits()/8;
4639 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4640 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
4641 ExtVT.getSizeInBits() - ExcessBits);
4642
4643 if (ExcessBits < NVT.getSizeInBits()) {
4644 // Transfer high bits from the top of Lo to the bottom of Hi.
4645 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
4646 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
4647 TLI.getPointerTy(DAG.getDataLayout())));
4648 Hi = DAG.getNode(
4649 ISD::OR, dl, NVT, Hi,
4650 DAG.getNode(ISD::SRL, dl, NVT, Lo,
4651 DAG.getConstant(ExcessBits, dl,
4652 TLI.getPointerTy(DAG.getDataLayout()))));
4653 }
4654
4655 // Store both the high bits and maybe some of the low bits.
4656 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), HiVT,
4657 N->getOriginalAlign(), MMOFlags, AAInfo);
4658
4659 // Increment the pointer to the other half.
4660 Ptr = DAG.getObjectPtrOffset(dl, Ptr, TypeSize::Fixed(IncrementSize));
4661 // Store the lowest ExcessBits bits in the second half.
4662 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
4663 N->getPointerInfo().getWithOffset(IncrementSize),
4664 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
4665 N->getOriginalAlign(), MMOFlags, AAInfo);
4666 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
4667}
4668
4669SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
4670 SDValue InL, InH;
4671 GetExpandedInteger(N->getOperand(0), InL, InH);
4672 // Just truncate the low part of the source.
4673 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
4674}
4675
4676SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
4677 bool IsStrict = N->isStrictFPOpcode();
4678 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
4679 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
4680 EVT DstVT = N->getValueType(0);
4681 RTLIB::Libcall LC = RTLIB::getUINTTOFP(Op.getValueType(), DstVT);
4682 assert(LC != RTLIB::UNKNOWN_LIBCALL &&(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Don't know how to expand this UINT_TO_FP!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this UINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4683, __extension__ __PRETTY_FUNCTION__))
4683 "Don't know how to expand this UINT_TO_FP!")(static_cast <bool> (LC != RTLIB::UNKNOWN_LIBCALL &&
"Don't know how to expand this UINT_TO_FP!") ? void (0) : __assert_fail
("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this UINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4683, __extension__ __PRETTY_FUNCTION__))
;
4684 TargetLowering::MakeLibCallOptions CallOptions;
4685 CallOptions.setSExt(true);
4686 std::pair<SDValue, SDValue> Tmp =
4687 TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
4688
4689 if (!IsStrict)
4690 return Tmp.first;
4691
4692 ReplaceValueWith(SDValue(N, 1), Tmp.second);
4693 ReplaceValueWith(SDValue(N, 0), Tmp.first);
4694 return SDValue();
4695}
4696
4697SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
4698 SDLoc dl(N);
4699 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
4700 cast<AtomicSDNode>(N)->getMemoryVT(),
4701 N->getOperand(0),
4702 N->getOperand(1), N->getOperand(2),
4703 cast<AtomicSDNode>(N)->getMemOperand());
4704 return Swap.getValue(1);
4705}
4706
4707SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SPLICE(SDNode *N) {
4708 SDLoc dl(N);
4709
4710 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4711 SDValue V1 = GetPromotedInteger(N->getOperand(1));
4712 EVT OutVT = V0.getValueType();
4713
4714 return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2));
4715}
4716
4717SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
4718
4719 EVT OutVT = N->getValueType(0);
4720 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4721 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4721, __extension__ __PRETTY_FUNCTION__))
;
4722 EVT NOutVTElem = NOutVT.getVectorElementType();
4723
4724 SDLoc dl(N);
4725 SDValue BaseIdx = N->getOperand(1);
4726
4727 // TODO: We may be able to use this for types other than scalable
4728 // vectors and fix those tests that expect BUILD_VECTOR to be used
4729 if (OutVT.isScalableVector()) {
4730 SDValue InOp0 = N->getOperand(0);
4731 EVT InVT = InOp0.getValueType();
4732
4733 // Promote operands and see if this is handled by target lowering,
4734 // Otherwise, use the BUILD_VECTOR approach below
4735 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
4736 // Collect the (promoted) operands
4737 SDValue Ops[] = { GetPromotedInteger(InOp0), BaseIdx };
4738
4739 EVT PromEltVT = Ops[0].getValueType().getVectorElementType();
4740 assert(PromEltVT.bitsLE(NOutVTElem) &&(static_cast <bool> (PromEltVT.bitsLE(NOutVTElem) &&
"Promoted operand has an element type greater than result") ?
void (0) : __assert_fail ("PromEltVT.bitsLE(NOutVTElem) && \"Promoted operand has an element type greater than result\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4741, __extension__ __PRETTY_FUNCTION__))
4741 "Promoted operand has an element type greater than result")(static_cast <bool> (PromEltVT.bitsLE(NOutVTElem) &&
"Promoted operand has an element type greater than result") ?
void (0) : __assert_fail ("PromEltVT.bitsLE(NOutVTElem) && \"Promoted operand has an element type greater than result\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4741, __extension__ __PRETTY_FUNCTION__))
;
4742
4743 EVT ExtVT = NOutVT.changeVectorElementType(PromEltVT);
4744 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), ExtVT, Ops);
4745 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, Ext);
4746 }
4747 }
4748
4749 if (OutVT.isScalableVector())
4750 report_fatal_error("Unable to promote scalable types using BUILD_VECTOR");
4751
4752 SDValue InOp0 = N->getOperand(0);
4753 if (getTypeAction(InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
4754 InOp0 = GetPromotedInteger(N->getOperand(0));
4755
4756 EVT InVT = InOp0.getValueType();
4757
4758 unsigned OutNumElems = OutVT.getVectorNumElements();
4759 SmallVector<SDValue, 8> Ops;
4760 Ops.reserve(OutNumElems);
4761 for (unsigned i = 0; i != OutNumElems; ++i) {
4762
4763 // Extract the element from the original vector.
4764 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
4765 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
4766 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4767 InVT.getVectorElementType(), N->getOperand(0), Index);
4768
4769 SDValue Op = DAG.getAnyExtOrTrunc(Ext, dl, NOutVTElem);
4770 // Insert the converted element to the new vector.
4771 Ops.push_back(Op);
4772 }
4773
4774 return DAG.getBuildVector(NOutVT, dl, Ops);
4775}
4776
4777SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_SUBVECTOR(SDNode *N) {
4778 EVT OutVT = N->getValueType(0);
4779 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4780 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4780, __extension__ __PRETTY_FUNCTION__))
;
4781
4782 SDLoc dl(N);
4783 SDValue Vec = N->getOperand(0);
4784 SDValue SubVec = N->getOperand(1);
4785 SDValue Idx = N->getOperand(2);
4786
4787 EVT SubVecVT = SubVec.getValueType();
4788 EVT NSubVT =
4789 EVT::getVectorVT(*DAG.getContext(), NOutVT.getVectorElementType(),
4790 SubVecVT.getVectorElementCount());
4791
4792 Vec = GetPromotedInteger(Vec);
4793 SubVec = DAG.getNode(ISD::ANY_EXTEND, dl, NSubVT, SubVec);
4794
4795 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NOutVT, Vec, SubVec, Idx);
4796}
4797
4798SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_REVERSE(SDNode *N) {
4799 SDLoc dl(N);
4800
4801 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4802 EVT OutVT = V0.getValueType();
4803
4804 return DAG.getNode(ISD::VECTOR_REVERSE, dl, OutVT, V0);
4805}
4806
4807SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
4808 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
4809 EVT VT = N->getValueType(0);
4810 SDLoc dl(N);
4811
4812 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
4813
4814 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4815 SDValue V1 = GetPromotedInteger(N->getOperand(1));
4816 EVT OutVT = V0.getValueType();
4817
4818 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
4819}
4820
4821
4822SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
4823 EVT OutVT = N->getValueType(0);
4824 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4825 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4825, __extension__ __PRETTY_FUNCTION__))
;
4826 unsigned NumElems = N->getNumOperands();
4827 EVT NOutVTElem = NOutVT.getVectorElementType();
4828
4829 SDLoc dl(N);
4830
4831 SmallVector<SDValue, 8> Ops;
4832 Ops.reserve(NumElems);
4833 for (unsigned i = 0; i != NumElems; ++i) {
4834 SDValue Op;
4835 // BUILD_VECTOR integer operand types are allowed to be larger than the
4836 // result's element type. This may still be true after the promotion. For
4837 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
4838 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
4839 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
4840 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
4841 else
4842 Op = N->getOperand(i);
4843 Ops.push_back(Op);
4844 }
4845
4846 return DAG.getBuildVector(NOutVT, dl, Ops);
4847}
4848
4849SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
4850
4851 SDLoc dl(N);
4852
4853 assert(!N->getOperand(0).getValueType().isVector() &&(static_cast <bool> (!N->getOperand(0).getValueType(
).isVector() && "Input must be a scalar") ? void (0) :
__assert_fail ("!N->getOperand(0).getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4854, __extension__ __PRETTY_FUNCTION__))
4854 "Input must be a scalar")(static_cast <bool> (!N->getOperand(0).getValueType(
).isVector() && "Input must be a scalar") ? void (0) :
__assert_fail ("!N->getOperand(0).getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4854, __extension__ __PRETTY_FUNCTION__))
;
4855
4856 EVT OutVT = N->getValueType(0);
4857 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4858 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4858, __extension__ __PRETTY_FUNCTION__))
;
4859 EVT NOutVTElem = NOutVT.getVectorElementType();
4860
4861 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
4862
4863 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
4864}
4865
4866SDValue DAGTypeLegalizer::PromoteIntRes_SPLAT_VECTOR(SDNode *N) {
4867 SDLoc dl(N);
4868
4869 SDValue SplatVal = N->getOperand(0);
4870
4871 assert(!SplatVal.getValueType().isVector() && "Input must be a scalar")(static_cast <bool> (!SplatVal.getValueType().isVector(
) && "Input must be a scalar") ? void (0) : __assert_fail
("!SplatVal.getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4871, __extension__ __PRETTY_FUNCTION__))
;
4872
4873 EVT OutVT = N->getValueType(0);
4874 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4875 assert(NOutVT.isVector() && "Type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "Type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"Type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4875, __extension__ __PRETTY_FUNCTION__))
;
4876 EVT NOutElemVT = NOutVT.getVectorElementType();
4877
4878 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutElemVT, SplatVal);
4879
4880 return DAG.getNode(ISD::SPLAT_VECTOR, dl, NOutVT, Op);
4881}
4882
4883SDValue DAGTypeLegalizer::PromoteIntRes_STEP_VECTOR(SDNode *N) {
4884 SDLoc dl(N);
4885 EVT OutVT = N->getValueType(0);
4886 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4887 assert(NOutVT.isVector() && "Type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "Type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"Type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4887, __extension__ __PRETTY_FUNCTION__))
;
4888 APInt StepVal = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
4889 return DAG.getStepVector(dl, NOutVT,
4890 StepVal.sext(NOutVT.getScalarSizeInBits()));
4891}
4892
4893SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
4894 SDLoc dl(N);
4895
4896 EVT OutVT = N->getValueType(0);
4897 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4898 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4898, __extension__ __PRETTY_FUNCTION__))
;
4899
4900 EVT OutElemTy = NOutVT.getVectorElementType();
4901
4902 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
4903 unsigned NumOutElem = NOutVT.getVectorNumElements();
4904 unsigned NumOperands = N->getNumOperands();
4905 assert(NumElem * NumOperands == NumOutElem &&(static_cast <bool> (NumElem * NumOperands == NumOutElem
&& "Unexpected number of elements") ? void (0) : __assert_fail
("NumElem * NumOperands == NumOutElem && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4906, __extension__ __PRETTY_FUNCTION__))
4906 "Unexpected number of elements")(static_cast <bool> (NumElem * NumOperands == NumOutElem
&& "Unexpected number of elements") ? void (0) : __assert_fail
("NumElem * NumOperands == NumOutElem && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4906, __extension__ __PRETTY_FUNCTION__))
;
4907
4908 // Take the elements from the first vector.
4909 SmallVector<SDValue, 8> Ops(NumOutElem);
4910 for (unsigned i = 0; i < NumOperands; ++i) {
4911 SDValue Op = N->getOperand(i);
4912 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger)
4913 Op = GetPromotedInteger(Op);
4914 EVT SclrTy = Op.getValueType().getVectorElementType();
4915 assert(NumElem == Op.getValueType().getVectorNumElements() &&(static_cast <bool> (NumElem == Op.getValueType().getVectorNumElements
() && "Unexpected number of elements") ? void (0) : __assert_fail
("NumElem == Op.getValueType().getVectorNumElements() && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4916, __extension__ __PRETTY_FUNCTION__))
4916 "Unexpected number of elements")(static_cast <bool> (NumElem == Op.getValueType().getVectorNumElements
() && "Unexpected number of elements") ? void (0) : __assert_fail
("NumElem == Op.getValueType().getVectorNumElements() && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4916, __extension__ __PRETTY_FUNCTION__))
;
4917
4918 for (unsigned j = 0; j < NumElem; ++j) {
4919 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op,
4920 DAG.getVectorIdxConstant(j, dl));
4921 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Ext, dl, OutElemTy);
4922 }
4923 }
4924
4925 return DAG.getBuildVector(NOutVT, dl, Ops);
4926}
4927
4928SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
4929 EVT VT = N->getValueType(0);
4930 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4931 assert(NVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4931, __extension__ __PRETTY_FUNCTION__))
;
4932
4933 SDLoc dl(N);
4934
4935 // For operands whose TypeAction is to promote, extend the promoted node
4936 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
4937 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
4938 // type..
4939 if (getTypeAction(N->getOperand(0).getValueType())
4940 == TargetLowering::TypePromoteInteger) {
4941 SDValue Promoted;
4942
4943 switch(N->getOpcode()) {
4944 case ISD::SIGN_EXTEND_VECTOR_INREG:
4945 Promoted = SExtPromotedInteger(N->getOperand(0));
4946 break;
4947 case ISD::ZERO_EXTEND_VECTOR_INREG:
4948 Promoted = ZExtPromotedInteger(N->getOperand(0));
4949 break;
4950 case ISD::ANY_EXTEND_VECTOR_INREG:
4951 Promoted = GetPromotedInteger(N->getOperand(0));
4952 break;
4953 default:
4954 llvm_unreachable("Node has unexpected Opcode")::llvm::llvm_unreachable_internal("Node has unexpected Opcode"
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4954)
;
4955 }
4956 return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
4957 }
4958
4959 // Directly extend to the appropriate transform-to type.
4960 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
4961}
4962
4963SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
4964 EVT OutVT = N->getValueType(0);
4965 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4966 assert(NOutVT.isVector() && "This type must be promoted to a vector type")(static_cast <bool> (NOutVT.isVector() && "This type must be promoted to a vector type"
) ? void (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4966, __extension__ __PRETTY_FUNCTION__))
;
4967
4968 EVT NOutVTElem = NOutVT.getVectorElementType();
4969
4970 SDLoc dl(N);
4971 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4972
4973 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
4974 NOutVTElem, N->getOperand(1));
4975 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
4976 V0, ConvElem, N->getOperand(2));
4977}
4978
4979SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
4980 // The VECREDUCE result size may be larger than the element size, so
4981 // we can simply change the result type.
4982 SDLoc dl(N);
4983 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4984 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
4985}
4986
4987SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
4988 SDLoc dl(N);
4989 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4990 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
4991 TLI.getVectorIdxTy(DAG.getDataLayout()));
4992 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4993 V0->getValueType(0).getScalarType(), V0, V1);
4994
4995 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
4996 // element types. If this is the case then we need to expand the outgoing
4997 // value and not truncate it.
4998 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
4999}
5000
5001SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
5002 SDLoc dl(N);
5003 SDValue V0 = GetPromotedInteger(N->getOperand(0));
5004 MVT InVT = V0.getValueType().getSimpleVT();
5005 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
5006 N->getValueType(0).getVectorNumElements());
5007 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
5008 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
5009}
5010
5011SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
5012 SDLoc dl(N);
5013
5014 EVT ResVT = N->getValueType(0);
5015 unsigned NumElems = N->getNumOperands();
5016
5017 if (ResVT.isScalableVector()) {
5018 SDValue ResVec = DAG.getUNDEF(ResVT);
5019
5020 for (unsigned OpIdx = 0; OpIdx < NumElems; ++OpIdx) {
5021 SDValue Op = N->getOperand(OpIdx);
5022 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements();
5023 ResVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ResVec, Op,
5024 DAG.getIntPtrConstant(OpIdx * OpNumElts, dl));
5025 }
5026
5027 return ResVec;
5028 }
5029
5030 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
5031
5032 SmallVector<SDValue, 8> NewOps;
5033 NewOps.reserve(NumElems);
5034
5035 // For each incoming vector
5036 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
5037 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
5038 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
5039 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
5040
5041 for (unsigned i=0; i<NumElem; ++i) {
5042 // Extract element from incoming vector
5043 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
5044 DAG.getVectorIdxConstant(i, dl));
5045 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
5046 NewOps.push_back(Tr);
5047 }
5048 }
5049
5050 return DAG.getBuildVector(N->getValueType(0), dl, NewOps);
5051}

/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/Register.h"
34#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/IR/Constants.h"
36#include "llvm/IR/DebugLoc.h"
37#include "llvm/IR/Instruction.h"
38#include "llvm/IR/Instructions.h"
39#include "llvm/IR/Metadata.h"
40#include "llvm/IR/Operator.h"
41#include "llvm/Support/AlignOf.h"
42#include "llvm/Support/AtomicOrdering.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/MachineValueType.h"
46#include "llvm/Support/TypeSize.h"
47#include <algorithm>
48#include <cassert>
49#include <climits>
50#include <cstddef>
51#include <cstdint>
52#include <cstring>
53#include <iterator>
54#include <string>
55#include <tuple>
56
57namespace llvm {
58
59class APInt;
60class Constant;
61template <typename T> struct DenseMapInfo;
62class GlobalValue;
63class MachineBasicBlock;
64class MachineConstantPoolValue;
65class MCSymbol;
66class raw_ostream;
67class SDNode;
68class SelectionDAG;
69class Type;
70class Value;
71
72void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
73 bool force = false);
74
75/// This represents a list of ValueType's that has been intern'd by
76/// a SelectionDAG. Instances of this simple value class are returned by
77/// SelectionDAG::getVTList(...).
78///
79struct SDVTList {
80 const EVT *VTs;
81 unsigned int NumVTs;
82};
83
84namespace ISD {
85
86 /// Node predicates
87
88/// If N is a BUILD_VECTOR or SPLAT_VECTOR node whose elements are all the
89/// same constant or undefined, return true and return the constant value in
90/// \p SplatValue.
91bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
92
93/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
94/// all of the elements are ~0 or undef. If \p BuildVectorOnly is set to
95/// true, it only checks BUILD_VECTOR.
96bool isConstantSplatVectorAllOnes(const SDNode *N,
97 bool BuildVectorOnly = false);
98
99/// Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where
100/// all of the elements are 0 or undef. If \p BuildVectorOnly is set to true, it
101/// only checks BUILD_VECTOR.
102bool isConstantSplatVectorAllZeros(const SDNode *N,
103 bool BuildVectorOnly = false);
104
105/// Return true if the specified node is a BUILD_VECTOR where all of the
106/// elements are ~0 or undef.
107bool isBuildVectorAllOnes(const SDNode *N);
108
109/// Return true if the specified node is a BUILD_VECTOR where all of the
110/// elements are 0 or undef.
111bool isBuildVectorAllZeros(const SDNode *N);
112
113/// Return true if the specified node is a BUILD_VECTOR node of all
114/// ConstantSDNode or undef.
115bool isBuildVectorOfConstantSDNodes(const SDNode *N);
116
117/// Return true if the specified node is a BUILD_VECTOR node of all
118/// ConstantFPSDNode or undef.
119bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
120
121/// Return true if the node has at least one operand and all operands of the
122/// specified node are ISD::UNDEF.
123bool allOperandsUndef(const SDNode *N);
124
125} // end namespace ISD
126
127//===----------------------------------------------------------------------===//
128/// Unlike LLVM values, Selection DAG nodes may return multiple
129/// values as the result of a computation. Many nodes return multiple values,
130/// from loads (which define a token and a return value) to ADDC (which returns
131/// a result and a carry value), to calls (which may return an arbitrary number
132/// of values).
133///
134/// As such, each use of a SelectionDAG computation must indicate the node that
135/// computes it as well as which return value to use from that node. This pair
136/// of information is represented with the SDValue value type.
137///
138class SDValue {
139 friend struct DenseMapInfo<SDValue>;
140
141 SDNode *Node = nullptr; // The node defining the value we are using.
142 unsigned ResNo = 0; // Which return value of the node we are using.
143
144public:
145 SDValue() = default;
146 SDValue(SDNode *node, unsigned resno);
147
148 /// get the index which selects a specific result in the SDNode
149 unsigned getResNo() const { return ResNo; }
150
151 /// get the SDNode which holds the desired result
152 SDNode *getNode() const { return Node; }
153
154 /// set the SDNode
155 void setNode(SDNode *N) { Node = N; }
156
157 inline SDNode *operator->() const { return Node; }
158
159 bool operator==(const SDValue &O) const {
160 return Node == O.Node && ResNo == O.ResNo;
161 }
162 bool operator!=(const SDValue &O) const {
163 return !operator==(O);
164 }
165 bool operator<(const SDValue &O) const {
166 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
167 }
168 explicit operator bool() const {
169 return Node != nullptr;
170 }
171
172 SDValue getValue(unsigned R) const {
173 return SDValue(Node, R);
174 }
175
176 /// Return true if this node is an operand of N.
177 bool isOperandOf(const SDNode *N) const;
178
179 /// Return the ValueType of the referenced return value.
180 inline EVT getValueType() const;
181
182 /// Return the simple ValueType of the referenced return value.
183 MVT getSimpleValueType() const {
184 return getValueType().getSimpleVT();
185 }
186
187 /// Returns the size of the value in bits.
188 ///
189 /// If the value type is a scalable vector type, the scalable property will
190 /// be set and the runtime size will be a positive integer multiple of the
191 /// base size.
192 TypeSize getValueSizeInBits() const {
193 return getValueType().getSizeInBits();
194 }
195
196 uint64_t getScalarValueSizeInBits() const {
197 return getValueType().getScalarType().getFixedSizeInBits();
198 }
199
200 // Forwarding methods - These forward to the corresponding methods in SDNode.
201 inline unsigned getOpcode() const;
202 inline unsigned getNumOperands() const;
203 inline const SDValue &getOperand(unsigned i) const;
204 inline uint64_t getConstantOperandVal(unsigned i) const;
205 inline const APInt &getConstantOperandAPInt(unsigned i) const;
206 inline bool isTargetMemoryOpcode() const;
207 inline bool isTargetOpcode() const;
208 inline bool isMachineOpcode() const;
209 inline bool isUndef() const;
210 inline unsigned getMachineOpcode() const;
211 inline const DebugLoc &getDebugLoc() const;
212 inline void dump() const;
213 inline void dump(const SelectionDAG *G) const;
214 inline void dumpr() const;
215 inline void dumpr(const SelectionDAG *G) const;
216
217 /// Return true if this operand (which must be a chain) reaches the
218 /// specified operand without crossing any side-effecting instructions.
219 /// In practice, this looks through token factors and non-volatile loads.
220 /// In order to remain efficient, this only
221 /// looks a couple of nodes in, it does not do an exhaustive search.
222 bool reachesChainWithoutSideEffects(SDValue Dest,
223 unsigned Depth = 2) const;
224
225 /// Return true if there are no nodes using value ResNo of Node.
226 inline bool use_empty() const;
227
228 /// Return true if there is exactly one node using value ResNo of Node.
229 inline bool hasOneUse() const;
230};
231
232template<> struct DenseMapInfo<SDValue> {
233 static inline SDValue getEmptyKey() {
234 SDValue V;
235 V.ResNo = -1U;
236 return V;
237 }
238
239 static inline SDValue getTombstoneKey() {
240 SDValue V;
241 V.ResNo = -2U;
242 return V;
243 }
244
245 static unsigned getHashValue(const SDValue &Val) {
246 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
247 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
248 }
249
250 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
251 return LHS == RHS;
252 }
253};
254
255/// Allow casting operators to work directly on
256/// SDValues as if they were SDNode*'s.
257template<> struct simplify_type<SDValue> {
258 using SimpleType = SDNode *;
259
260 static SimpleType getSimplifiedValue(SDValue &Val) {
261 return Val.getNode();
262 }
263};
264template<> struct simplify_type<const SDValue> {
265 using SimpleType = /*const*/ SDNode *;
266
267 static SimpleType getSimplifiedValue(const SDValue &Val) {
268 return Val.getNode();
269 }
270};
271
272/// Represents a use of a SDNode. This class holds an SDValue,
273/// which records the SDNode being used and the result number, a
274/// pointer to the SDNode using the value, and Next and Prev pointers,
275/// which link together all the uses of an SDNode.
276///
277class SDUse {
278 /// Val - The value being used.
279 SDValue Val;
280 /// User - The user of this value.
281 SDNode *User = nullptr;
282 /// Prev, Next - Pointers to the uses list of the SDNode referred by
283 /// this operand.
284 SDUse **Prev = nullptr;
285 SDUse *Next = nullptr;
286
287public:
288 SDUse() = default;
289 SDUse(const SDUse &U) = delete;
290 SDUse &operator=(const SDUse &) = delete;
291
292 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
293 operator const SDValue&() const { return Val; }
294
295 /// If implicit conversion to SDValue doesn't work, the get() method returns
296 /// the SDValue.
297 const SDValue &get() const { return Val; }
298
299 /// This returns the SDNode that contains this Use.
300 SDNode *getUser() { return User; }
301
302 /// Get the next SDUse in the use list.
303 SDUse *getNext() const { return Next; }
304
305 /// Convenience function for get().getNode().
306 SDNode *getNode() const { return Val.getNode(); }
307 /// Convenience function for get().getResNo().
308 unsigned getResNo() const { return Val.getResNo(); }
309 /// Convenience function for get().getValueType().
310 EVT getValueType() const { return Val.getValueType(); }
311
312 /// Convenience function for get().operator==
313 bool operator==(const SDValue &V) const {
314 return Val == V;
315 }
316
317 /// Convenience function for get().operator!=
318 bool operator!=(const SDValue &V) const {
319 return Val != V;
320 }
321
322 /// Convenience function for get().operator<
323 bool operator<(const SDValue &V) const {
324 return Val < V;
325 }
326
327private:
328 friend class SelectionDAG;
329 friend class SDNode;
330 // TODO: unfriend HandleSDNode once we fix its operand handling.
331 friend class HandleSDNode;
332
333 void setUser(SDNode *p) { User = p; }
334
335 /// Remove this use from its existing use list, assign it the
336 /// given value, and add it to the new value's node's use list.
337 inline void set(const SDValue &V);
338 /// Like set, but only supports initializing a newly-allocated
339 /// SDUse with a non-null value.
340 inline void setInitial(const SDValue &V);
341 /// Like set, but only sets the Node portion of the value,
342 /// leaving the ResNo portion unmodified.
343 inline void setNode(SDNode *N);
344
345 void addToList(SDUse **List) {
346 Next = *List;
347 if (Next) Next->Prev = &Next;
348 Prev = List;
349 *List = this;
350 }
351
352 void removeFromList() {
353 *Prev = Next;
354 if (Next) Next->Prev = Prev;
355 }
356};
357
358/// simplify_type specializations - Allow casting operators to work directly on
359/// SDValues as if they were SDNode*'s.
360template<> struct simplify_type<SDUse> {
361 using SimpleType = SDNode *;
362
363 static SimpleType getSimplifiedValue(SDUse &Val) {
364 return Val.getNode();
365 }
366};
367
368/// These are IR-level optimization flags that may be propagated to SDNodes.
369/// TODO: This data structure should be shared by the IR optimizer and the
370/// the backend.
371struct SDNodeFlags {
372private:
373 bool NoUnsignedWrap : 1;
374 bool NoSignedWrap : 1;
375 bool Exact : 1;
376 bool NoNaNs : 1;
377 bool NoInfs : 1;
378 bool NoSignedZeros : 1;
379 bool AllowReciprocal : 1;
380 bool AllowContract : 1;
381 bool ApproximateFuncs : 1;
382 bool AllowReassociation : 1;
383
384 // We assume instructions do not raise floating-point exceptions by default,
385 // and only those marked explicitly may do so. We could choose to represent
386 // this via a positive "FPExcept" flags like on the MI level, but having a
387 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
388 // intersection logic more straightforward.
389 bool NoFPExcept : 1;
390
391public:
392 /// Default constructor turns off all optimization flags.
393 SDNodeFlags()
394 : NoUnsignedWrap(false), NoSignedWrap(false), Exact(false), NoNaNs(false),
395 NoInfs(false), NoSignedZeros(false), AllowReciprocal(false),
396 AllowContract(false), ApproximateFuncs(false),
397 AllowReassociation(false), NoFPExcept(false) {}
398
399 /// Propagate the fast-math-flags from an IR FPMathOperator.
400 void copyFMF(const FPMathOperator &FPMO) {
401 setNoNaNs(FPMO.hasNoNaNs());
402 setNoInfs(FPMO.hasNoInfs());
403 setNoSignedZeros(FPMO.hasNoSignedZeros());
404 setAllowReciprocal(FPMO.hasAllowReciprocal());
405 setAllowContract(FPMO.hasAllowContract());
406 setApproximateFuncs(FPMO.hasApproxFunc());
407 setAllowReassociation(FPMO.hasAllowReassoc());
408 }
409
410 // These are mutators for each flag.
411 void setNoUnsignedWrap(bool b) { NoUnsignedWrap = b; }
412 void setNoSignedWrap(bool b) { NoSignedWrap = b; }
413 void setExact(bool b) { Exact = b; }
414 void setNoNaNs(bool b) { NoNaNs = b; }
415 void setNoInfs(bool b) { NoInfs = b; }
416 void setNoSignedZeros(bool b) { NoSignedZeros = b; }
417 void setAllowReciprocal(bool b) { AllowReciprocal = b; }
418 void setAllowContract(bool b) { AllowContract = b; }
419 void setApproximateFuncs(bool b) { ApproximateFuncs = b; }
420 void setAllowReassociation(bool b) { AllowReassociation = b; }
421 void setNoFPExcept(bool b) { NoFPExcept = b; }
422
423 // These are accessors for each flag.
424 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
425 bool hasNoSignedWrap() const { return NoSignedWrap; }
426 bool hasExact() const { return Exact; }
427 bool hasNoNaNs() const { return NoNaNs; }
428 bool hasNoInfs() const { return NoInfs; }
429 bool hasNoSignedZeros() const { return NoSignedZeros; }
430 bool hasAllowReciprocal() const { return AllowReciprocal; }
431 bool hasAllowContract() const { return AllowContract; }
432 bool hasApproximateFuncs() const { return ApproximateFuncs; }
433 bool hasAllowReassociation() const { return AllowReassociation; }
434 bool hasNoFPExcept() const { return NoFPExcept; }
435
436 /// Clear any flags in this flag set that aren't also set in Flags. All
437 /// flags will be cleared if Flags are undefined.
438 void intersectWith(const SDNodeFlags Flags) {
439 NoUnsignedWrap &= Flags.NoUnsignedWrap;
440 NoSignedWrap &= Flags.NoSignedWrap;
441 Exact &= Flags.Exact;
442 NoNaNs &= Flags.NoNaNs;
443 NoInfs &= Flags.NoInfs;
444 NoSignedZeros &= Flags.NoSignedZeros;
445 AllowReciprocal &= Flags.AllowReciprocal;
446 AllowContract &= Flags.AllowContract;
447 ApproximateFuncs &= Flags.ApproximateFuncs;
448 AllowReassociation &= Flags.AllowReassociation;
449 NoFPExcept &= Flags.NoFPExcept;
450 }
451};
452
453/// Represents one node in the SelectionDAG.
454///
455class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
456private:
457 /// The operation that this node performs.
458 int16_t NodeType;
459
460protected:
461 // We define a set of mini-helper classes to help us interpret the bits in our
462 // SubclassData. These are designed to fit within a uint16_t so they pack
463 // with NodeType.
464
465#if defined(_AIX) && (!defined(__GNUC__4) || defined(__clang__1))
466// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
467// and give the `pack` pragma push semantics.
468#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
469#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
470#else
471#define BEGIN_TWO_BYTE_PACK()
472#define END_TWO_BYTE_PACK()
473#endif
474
475BEGIN_TWO_BYTE_PACK()
476 class SDNodeBitfields {
477 friend class SDNode;
478 friend class MemIntrinsicSDNode;
479 friend class MemSDNode;
480 friend class SelectionDAG;
481
482 uint16_t HasDebugValue : 1;
483 uint16_t IsMemIntrinsic : 1;
484 uint16_t IsDivergent : 1;
485 };
486 enum { NumSDNodeBits = 3 };
487
488 class ConstantSDNodeBitfields {
489 friend class ConstantSDNode;
490
491 uint16_t : NumSDNodeBits;
492
493 uint16_t IsOpaque : 1;
494 };
495
496 class MemSDNodeBitfields {
497 friend class MemSDNode;
498 friend class MemIntrinsicSDNode;
499 friend class AtomicSDNode;
500
501 uint16_t : NumSDNodeBits;
502
503 uint16_t IsVolatile : 1;
504 uint16_t IsNonTemporal : 1;
505 uint16_t IsDereferenceable : 1;
506 uint16_t IsInvariant : 1;
507 };
508 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
509
510 class LSBaseSDNodeBitfields {
511 friend class LSBaseSDNode;
512 friend class MaskedLoadStoreSDNode;
513 friend class MaskedGatherScatterSDNode;
514
515 uint16_t : NumMemSDNodeBits;
516
517 // This storage is shared between disparate class hierarchies to hold an
518 // enumeration specific to the class hierarchy in use.
519 // LSBaseSDNode => enum ISD::MemIndexedMode
520 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
521 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
522 uint16_t AddressingMode : 3;
523 };
524 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
525
526 class LoadSDNodeBitfields {
527 friend class LoadSDNode;
528 friend class MaskedLoadSDNode;
529 friend class MaskedGatherSDNode;
530
531 uint16_t : NumLSBaseSDNodeBits;
532
533 uint16_t ExtTy : 2; // enum ISD::LoadExtType
534 uint16_t IsExpanding : 1;
535 };
536
537 class StoreSDNodeBitfields {
538 friend class StoreSDNode;
539 friend class MaskedStoreSDNode;
540 friend class MaskedScatterSDNode;
541
542 uint16_t : NumLSBaseSDNodeBits;
543
544 uint16_t IsTruncating : 1;
545 uint16_t IsCompressing : 1;
546 };
547
548 union {
549 char RawSDNodeBits[sizeof(uint16_t)];
550 SDNodeBitfields SDNodeBits;
551 ConstantSDNodeBitfields ConstantSDNodeBits;
552 MemSDNodeBitfields MemSDNodeBits;
553 LSBaseSDNodeBitfields LSBaseSDNodeBits;
554 LoadSDNodeBitfields LoadSDNodeBits;
555 StoreSDNodeBitfields StoreSDNodeBits;
556 };
557END_TWO_BYTE_PACK()
558#undef BEGIN_TWO_BYTE_PACK
559#undef END_TWO_BYTE_PACK
560
561 // RawSDNodeBits must cover the entirety of the union. This means that all of
562 // the union's members must have size <= RawSDNodeBits. We write the RHS as
563 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
564 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
565 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
566 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
567 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
568 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
569 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
570
571private:
572 friend class SelectionDAG;
573 // TODO: unfriend HandleSDNode once we fix its operand handling.
574 friend class HandleSDNode;
575
576 /// Unique id per SDNode in the DAG.
577 int NodeId = -1;
578
579 /// The values that are used by this operation.
580 SDUse *OperandList = nullptr;
581
582 /// The types of the values this node defines. SDNode's may
583 /// define multiple values simultaneously.
584 const EVT *ValueList;
585
586 /// List of uses for this SDNode.
587 SDUse *UseList = nullptr;
588
589 /// The number of entries in the Operand/Value list.
590 unsigned short NumOperands = 0;
591 unsigned short NumValues;
592
593 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
594 // original LLVM instructions.
595 // This is used for turning off scheduling, because we'll forgo
596 // the normal scheduling algorithms and output the instructions according to
597 // this ordering.
598 unsigned IROrder;
599
600 /// Source line information.
601 DebugLoc debugLoc;
602
603 /// Return a pointer to the specified value type.
604 static const EVT *getValueTypeList(EVT VT);
605
606 SDNodeFlags Flags;
607
608public:
609 /// Unique and persistent id per SDNode in the DAG.
610 /// Used for debug printing.
611 uint16_t PersistentId;
612
613 //===--------------------------------------------------------------------===//
614 // Accessors
615 //
616
617 /// Return the SelectionDAG opcode value for this node. For
618 /// pre-isel nodes (those for which isMachineOpcode returns false), these
619 /// are the opcode values in the ISD and <target>ISD namespaces. For
620 /// post-isel opcodes, see getMachineOpcode.
621 unsigned getOpcode() const { return (unsigned short)NodeType; }
622
623 /// Test if this node has a target-specific opcode (in the
624 /// \<target\>ISD namespace).
625 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
626
627 /// Test if this node has a target-specific opcode that may raise
628 /// FP exceptions (in the \<target\>ISD namespace and greater than
629 /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
630 /// opcode are currently automatically considered to possibly raise
631 /// FP exceptions as well.
632 bool isTargetStrictFPOpcode() const {
633 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
634 }
635
636 /// Test if this node has a target-specific
637 /// memory-referencing opcode (in the \<target\>ISD namespace and
638 /// greater than FIRST_TARGET_MEMORY_OPCODE).
639 bool isTargetMemoryOpcode() const {
640 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
641 }
642
643 /// Return true if the type of the node type undefined.
644 bool isUndef() const { return NodeType == ISD::UNDEF; }
645
646 /// Test if this node is a memory intrinsic (with valid pointer information).
647 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
648 /// non-memory intrinsics (with chains) that are not really instances of
649 /// MemSDNode. For such nodes, we need some extra state to determine the
650 /// proper classof relationship.
651 bool isMemIntrinsic() const {
652 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
653 NodeType == ISD::INTRINSIC_VOID) &&
654 SDNodeBits.IsMemIntrinsic;
655 }
656
657 /// Test if this node is a strict floating point pseudo-op.
658 bool isStrictFPOpcode() {
659 switch (NodeType) {
660 default:
661 return false;
662 case ISD::STRICT_FP16_TO_FP:
663 case ISD::STRICT_FP_TO_FP16:
664#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
665 case ISD::STRICT_##DAGN:
666#include "llvm/IR/ConstrainedOps.def"
667 return true;
668 }
669 }
670
671 /// Test if this node has a post-isel opcode, directly
672 /// corresponding to a MachineInstr opcode.
673 bool isMachineOpcode() const { return NodeType < 0; }
674
675 /// This may only be called if isMachineOpcode returns
676 /// true. It returns the MachineInstr opcode value that the node's opcode
677 /// corresponds to.
678 unsigned getMachineOpcode() const {
679 assert(isMachineOpcode() && "Not a MachineInstr opcode!")(static_cast <bool> (isMachineOpcode() && "Not a MachineInstr opcode!"
) ? void (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 679, __extension__ __PRETTY_FUNCTION__))
;
680 return ~NodeType;
681 }
682
683 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
684 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
685
686 bool isDivergent() const { return SDNodeBits.IsDivergent; }
687
688 /// Return true if there are no uses of this node.
689 bool use_empty() const { return UseList == nullptr; }
690
691 /// Return true if there is exactly one use of this node.
692 bool hasOneUse() const { return hasSingleElement(uses()); }
693
694 /// Return the number of uses of this node. This method takes
695 /// time proportional to the number of uses.
696 size_t use_size() const { return std::distance(use_begin(), use_end()); }
697
698 /// Return the unique node id.
699 int getNodeId() const { return NodeId; }
700
701 /// Set unique node id.
702 void setNodeId(int Id) { NodeId = Id; }
703
704 /// Return the node ordering.
705 unsigned getIROrder() const { return IROrder; }
706
707 /// Set the node ordering.
708 void setIROrder(unsigned Order) { IROrder = Order; }
709
710 /// Return the source location info.
711 const DebugLoc &getDebugLoc() const { return debugLoc; }
712
713 /// Set source location info. Try to avoid this, putting
714 /// it in the constructor is preferable.
715 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
716
717 /// This class provides iterator support for SDUse
718 /// operands that use a specific SDNode.
719 class use_iterator {
720 friend class SDNode;
721
722 SDUse *Op = nullptr;
723
724 explicit use_iterator(SDUse *op) : Op(op) {}
725
726 public:
727 using iterator_category = std::forward_iterator_tag;
728 using value_type = SDUse;
729 using difference_type = std::ptrdiff_t;
730 using pointer = value_type *;
731 using reference = value_type &;
732
733 use_iterator() = default;
734 use_iterator(const use_iterator &I) : Op(I.Op) {}
735
736 bool operator==(const use_iterator &x) const {
737 return Op == x.Op;
738 }
739 bool operator!=(const use_iterator &x) const {
740 return !operator==(x);
741 }
742
743 /// Return true if this iterator is at the end of uses list.
744 bool atEnd() const { return Op == nullptr; }
745
746 // Iterator traversal: forward iteration only.
747 use_iterator &operator++() { // Preincrement
748 assert(Op && "Cannot increment end iterator!")(static_cast <bool> (Op && "Cannot increment end iterator!"
) ? void (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 748, __extension__ __PRETTY_FUNCTION__))
;
749 Op = Op->getNext();
750 return *this;
751 }
752
753 use_iterator operator++(int) { // Postincrement
754 use_iterator tmp = *this; ++*this; return tmp;
755 }
756
757 /// Retrieve a pointer to the current user node.
758 SDNode *operator*() const {
759 assert(Op && "Cannot dereference end iterator!")(static_cast <bool> (Op && "Cannot dereference end iterator!"
) ? void (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 759, __extension__ __PRETTY_FUNCTION__))
;
760 return Op->getUser();
761 }
762
763 SDNode *operator->() const { return operator*(); }
764
765 SDUse &getUse() const { return *Op; }
766
767 /// Retrieve the operand # of this use in its user.
768 unsigned getOperandNo() const {
769 assert(Op && "Cannot dereference end iterator!")(static_cast <bool> (Op && "Cannot dereference end iterator!"
) ? void (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 769, __extension__ __PRETTY_FUNCTION__))
;
770 return (unsigned)(Op - Op->getUser()->OperandList);
771 }
772 };
773
774 /// Provide iteration support to walk over all uses of an SDNode.
775 use_iterator use_begin() const {
776 return use_iterator(UseList);
777 }
778
779 static use_iterator use_end() { return use_iterator(nullptr); }
780
781 inline iterator_range<use_iterator> uses() {
782 return make_range(use_begin(), use_end());
783 }
784 inline iterator_range<use_iterator> uses() const {
785 return make_range(use_begin(), use_end());
786 }
787
788 /// Return true if there are exactly NUSES uses of the indicated value.
789 /// This method ignores uses of other values defined by this operation.
790 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
791
792 /// Return true if there are any use of the indicated value.
793 /// This method ignores uses of other values defined by this operation.
794 bool hasAnyUseOfValue(unsigned Value) const;
795
796 /// Return true if this node is the only use of N.
797 bool isOnlyUserOf(const SDNode *N) const;
798
799 /// Return true if this node is an operand of N.
800 bool isOperandOf(const SDNode *N) const;
801
802 /// Return true if this node is a predecessor of N.
803 /// NOTE: Implemented on top of hasPredecessor and every bit as
804 /// expensive. Use carefully.
805 bool isPredecessorOf(const SDNode *N) const {
806 return N->hasPredecessor(this);
807 }
808
809 /// Return true if N is a predecessor of this node.
810 /// N is either an operand of this node, or can be reached by recursively
811 /// traversing up the operands.
812 /// NOTE: This is an expensive method. Use it carefully.
813 bool hasPredecessor(const SDNode *N) const;
814
815 /// Returns true if N is a predecessor of any node in Worklist. This
816 /// helper keeps Visited and Worklist sets externally to allow unions
817 /// searches to be performed in parallel, caching of results across
818 /// queries and incremental addition to Worklist. Stops early if N is
819 /// found but will resume. Remember to clear Visited and Worklists
820 /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
821 /// giving up. The TopologicalPrune flag signals that positive NodeIds are
822 /// topologically ordered (Operands have strictly smaller node id) and search
823 /// can be pruned leveraging this.
824 static bool hasPredecessorHelper(const SDNode *N,
825 SmallPtrSetImpl<const SDNode *> &Visited,
826 SmallVectorImpl<const SDNode *> &Worklist,
827 unsigned int MaxSteps = 0,
828 bool TopologicalPrune = false) {
829 SmallVector<const SDNode *, 8> DeferredNodes;
830 if (Visited.count(N))
831 return true;
832
833 // Node Id's are assigned in three places: As a topological
834 // ordering (> 0), during legalization (results in values set to
835 // 0), new nodes (set to -1). If N has a topolgical id then we
836 // know that all nodes with ids smaller than it cannot be
837 // successors and we need not check them. Filter out all node
838 // that can't be matches. We add them to the worklist before exit
839 // in case of multiple calls. Note that during selection the topological id
840 // may be violated if a node's predecessor is selected before it. We mark
841 // this at selection negating the id of unselected successors and
842 // restricting topological pruning to positive ids.
843
844 int NId = N->getNodeId();
845 // If we Invalidated the Id, reconstruct original NId.
846 if (NId < -1)
847 NId = -(NId + 1);
848
849 bool Found = false;
850 while (!Worklist.empty()) {
851 const SDNode *M = Worklist.pop_back_val();
852 int MId = M->getNodeId();
853 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
854 (MId > 0) && (MId < NId)) {
855 DeferredNodes.push_back(M);
856 continue;
857 }
858 for (const SDValue &OpV : M->op_values()) {
859 SDNode *Op = OpV.getNode();
860 if (Visited.insert(Op).second)
861 Worklist.push_back(Op);
862 if (Op == N)
863 Found = true;
864 }
865 if (Found)
866 break;
867 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
868 break;
869 }
870 // Push deferred nodes back on worklist.
871 Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
872 // If we bailed early, conservatively return found.
873 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
874 return true;
875 return Found;
876 }
877
878 /// Return true if all the users of N are contained in Nodes.
879 /// NOTE: Requires at least one match, but doesn't require them all.
880 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
881
882 /// Return the number of values used by this operation.
883 unsigned getNumOperands() const { return NumOperands; }
884
885 /// Return the maximum number of operands that a SDNode can hold.
886 static constexpr size_t getMaxNumOperands() {
887 return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
888 }
889
890 /// Helper method returns the integer value of a ConstantSDNode operand.
891 inline uint64_t getConstantOperandVal(unsigned Num) const;
892
893 /// Helper method returns the APInt of a ConstantSDNode operand.
894 inline const APInt &getConstantOperandAPInt(unsigned Num) const;
895
896 const SDValue &getOperand(unsigned Num) const {
897 assert(Num < NumOperands && "Invalid child # of SDNode!")(static_cast <bool> (Num < NumOperands && "Invalid child # of SDNode!"
) ? void (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 897, __extension__ __PRETTY_FUNCTION__))
;
898 return OperandList[Num];
899 }
900
901 using op_iterator = SDUse *;
902
903 op_iterator op_begin() const { return OperandList; }
904 op_iterator op_end() const { return OperandList+NumOperands; }
905 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
906
907 /// Iterator for directly iterating over the operand SDValue's.
908 struct value_op_iterator
909 : iterator_adaptor_base<value_op_iterator, op_iterator,
910 std::random_access_iterator_tag, SDValue,
911 ptrdiff_t, value_op_iterator *,
912 value_op_iterator *> {
913 explicit value_op_iterator(SDUse *U = nullptr)
914 : iterator_adaptor_base(U) {}
915
916 const SDValue &operator*() const { return I->get(); }
917 };
918
919 iterator_range<value_op_iterator> op_values() const {
920 return make_range(value_op_iterator(op_begin()),
921 value_op_iterator(op_end()));
922 }
923
924 SDVTList getVTList() const {
925 SDVTList X = { ValueList, NumValues };
926 return X;
927 }
928
929 /// If this node has a glue operand, return the node
930 /// to which the glue operand points. Otherwise return NULL.
931 SDNode *getGluedNode() const {
932 if (getNumOperands() != 0 &&
933 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
934 return getOperand(getNumOperands()-1).getNode();
935 return nullptr;
936 }
937
938 /// If this node has a glue value with a user, return
939 /// the user (there is at most one). Otherwise return NULL.
940 SDNode *getGluedUser() const {
941 for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
942 if (UI.getUse().get().getValueType() == MVT::Glue)
943 return *UI;
944 return nullptr;
945 }
946
947 SDNodeFlags getFlags() const { return Flags; }
948 void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
949
950 /// Clear any flags in this node that aren't also set in Flags.
951 /// If Flags is not in a defined state then this has no effect.
952 void intersectFlagsWith(const SDNodeFlags Flags);
953
954 /// Return the number of values defined/returned by this operator.
955 unsigned getNumValues() const { return NumValues; }
956
957 /// Return the type of a specified result.
958 EVT getValueType(unsigned ResNo) const {
959 assert(ResNo < NumValues && "Illegal result number!")(static_cast <bool> (ResNo < NumValues && "Illegal result number!"
) ? void (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 959, __extension__ __PRETTY_FUNCTION__))
;
960 return ValueList[ResNo];
961 }
962
963 /// Return the type of a specified result as a simple type.
964 MVT getSimpleValueType(unsigned ResNo) const {
965 return getValueType(ResNo).getSimpleVT();
966 }
967
968 /// Returns MVT::getSizeInBits(getValueType(ResNo)).
969 ///
970 /// If the value type is a scalable vector type, the scalable property will
971 /// be set and the runtime size will be a positive integer multiple of the
972 /// base size.
973 TypeSize getValueSizeInBits(unsigned ResNo) const {
974 return getValueType(ResNo).getSizeInBits();
975 }
976
977 using value_iterator = const EVT *;
978
979 value_iterator value_begin() const { return ValueList; }
980 value_iterator value_end() const { return ValueList+NumValues; }
981 iterator_range<value_iterator> values() const {
982 return llvm::make_range(value_begin(), value_end());
983 }
984
985 /// Return the opcode of this operation for printing.
986 std::string getOperationName(const SelectionDAG *G = nullptr) const;
987 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
988 void print_types(raw_ostream &OS, const SelectionDAG *G) const;
989 void print_details(raw_ostream &OS, const SelectionDAG *G) const;
990 void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
991 void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
992
993 /// Print a SelectionDAG node and all children down to
994 /// the leaves. The given SelectionDAG allows target-specific nodes
995 /// to be printed in human-readable form. Unlike printr, this will
996 /// print the whole DAG, including children that appear multiple
997 /// times.
998 ///
999 void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;
1000
1001 /// Print a SelectionDAG node and children up to
1002 /// depth "depth." The given SelectionDAG allows target-specific
1003 /// nodes to be printed in human-readable form. Unlike printr, this
1004 /// will print children that appear multiple times wherever they are
1005 /// used.
1006 ///
1007 void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
1008 unsigned depth = 100) const;
1009
1010 /// Dump this node, for debugging.
1011 void dump() const;
1012
1013 /// Dump (recursively) this node and its use-def subgraph.
1014 void dumpr() const;
1015
1016 /// Dump this node, for debugging.
1017 /// The given SelectionDAG allows target-specific nodes to be printed
1018 /// in human-readable form.
1019 void dump(const SelectionDAG *G) const;
1020
1021 /// Dump (recursively) this node and its use-def subgraph.
1022 /// The given SelectionDAG allows target-specific nodes to be printed
1023 /// in human-readable form.
1024 void dumpr(const SelectionDAG *G) const;
1025
1026 /// printrFull to dbgs(). The given SelectionDAG allows
1027 /// target-specific nodes to be printed in human-readable form.
1028 /// Unlike dumpr, this will print the whole DAG, including children
1029 /// that appear multiple times.
1030 void dumprFull(const SelectionDAG *G = nullptr) const;
1031
1032 /// printrWithDepth to dbgs(). The given
1033 /// SelectionDAG allows target-specific nodes to be printed in
1034 /// human-readable form. Unlike dumpr, this will print children
1035 /// that appear multiple times wherever they are used.
1036 ///
1037 void dumprWithDepth(const SelectionDAG *G = nullptr,
1038 unsigned depth = 100) const;
1039
1040 /// Gather unique data for the node.
1041 void Profile(FoldingSetNodeID &ID) const;
1042
1043 /// This method should only be used by the SDUse class.
1044 void addUse(SDUse &U) { U.addToList(&UseList); }
1045
1046protected:
1047 static SDVTList getSDVTList(EVT VT) {
1048 SDVTList Ret = { getValueTypeList(VT), 1 };
1049 return Ret;
1050 }
1051
1052 /// Create an SDNode.
1053 ///
1054 /// SDNodes are created without any operands, and never own the operand
1055 /// storage. To add operands, see SelectionDAG::createOperands.
1056 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1057 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1058 IROrder(Order), debugLoc(std::move(dl)) {
1059 memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
1060 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (debugLoc.hasTrivialDestructor() &&
"Expected trivial destructor") ? void (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1060, __extension__ __PRETTY_FUNCTION__))
;
1061 assert(NumValues == VTs.NumVTs &&(static_cast <bool> (NumValues == VTs.NumVTs &&
"NumValues wasn't wide enough for its operands!") ? void (0)
: __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1062, __extension__ __PRETTY_FUNCTION__))
1062 "NumValues wasn't wide enough for its operands!")(static_cast <bool> (NumValues == VTs.NumVTs &&
"NumValues wasn't wide enough for its operands!") ? void (0)
: __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1062, __extension__ __PRETTY_FUNCTION__))
;
1063 }
1064
1065 /// Release the operands and set this node to have zero operands.
1066 void DropOperands();
1067};
1068
1069/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1070/// into SDNode creation functions.
1071/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1072/// from the original Instruction, and IROrder is the ordinal position of
1073/// the instruction.
1074/// When an SDNode is created after the DAG is being built, both DebugLoc and
1075/// the IROrder are propagated from the original SDNode.
1076/// So SDLoc class provides two constructors besides the default one, one to
1077/// be used by the DAGBuilder, the other to be used by others.
1078class SDLoc {
1079private:
1080 DebugLoc DL;
1081 int IROrder = 0;
1082
1083public:
1084 SDLoc() = default;
1085 SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
1086 SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
1087 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1088 assert(Order >= 0 && "bad IROrder")(static_cast <bool> (Order >= 0 && "bad IROrder"
) ? void (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1088, __extension__ __PRETTY_FUNCTION__))
;
1089 if (I)
1090 DL = I->getDebugLoc();
1091 }
1092
1093 unsigned getIROrder() const { return IROrder; }
1094 const DebugLoc &getDebugLoc() const { return DL; }
1095};
1096
1097// Define inline functions from the SDValue class.
1098
1099inline SDValue::SDValue(SDNode *node, unsigned resno)
1100 : Node(node), ResNo(resno) {
1101 // Explicitly check for !ResNo to avoid use-after-free, because there are
1102 // callers that use SDValue(N, 0) with a deleted N to indicate successful
1103 // combines.
1104 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(static_cast <bool> ((!Node || !ResNo || ResNo < Node
->getNumValues()) && "Invalid result number for the given node!"
) ? void (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1105, __extension__ __PRETTY_FUNCTION__))
1105 "Invalid result number for the given node!")(static_cast <bool> ((!Node || !ResNo || ResNo < Node
->getNumValues()) && "Invalid result number for the given node!"
) ? void (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1105, __extension__ __PRETTY_FUNCTION__))
;
1106 assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")(static_cast <bool> (ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? void (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1106, __extension__ __PRETTY_FUNCTION__))
;
1107}
1108
1109inline unsigned SDValue::getOpcode() const {
1110 return Node->getOpcode();
1111}
1112
1113inline EVT SDValue::getValueType() const {
1114 return Node->getValueType(ResNo);
12
Called C++ object pointer is null
1115}
1116
1117inline unsigned SDValue::getNumOperands() const {
1118 return Node->getNumOperands();
1119}
1120
1121inline const SDValue &SDValue::getOperand(unsigned i) const {
1122 return Node->getOperand(i);
1123}
1124
1125inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
1126 return Node->getConstantOperandVal(i);
1127}
1128
1129inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
1130 return Node->getConstantOperandAPInt(i);
1131}
1132
1133inline bool SDValue::isTargetOpcode() const {
1134 return Node->isTargetOpcode();
1135}
1136
1137inline bool SDValue::isTargetMemoryOpcode() const {
1138 return Node->isTargetMemoryOpcode();
1139}
1140
1141inline bool SDValue::isMachineOpcode() const {
1142 return Node->isMachineOpcode();
1143}
1144
1145inline unsigned SDValue::getMachineOpcode() const {
1146 return Node->getMachineOpcode();
1147}
1148
1149inline bool SDValue::isUndef() const {
1150 return Node->isUndef();
1151}
1152
1153inline bool SDValue::use_empty() const {
1154 return !Node->hasAnyUseOfValue(ResNo);
1155}
1156
1157inline bool SDValue::hasOneUse() const {
1158 return Node->hasNUsesOfValue(1, ResNo);
1159}
1160
1161inline const DebugLoc &SDValue::getDebugLoc() const {
1162 return Node->getDebugLoc();
1163}
1164
1165inline void SDValue::dump() const {
1166 return Node->dump();
1167}
1168
1169inline void SDValue::dump(const SelectionDAG *G) const {
1170 return Node->dump(G);
1171}
1172
1173inline void SDValue::dumpr() const {
1174 return Node->dumpr();
1175}
1176
1177inline void SDValue::dumpr(const SelectionDAG *G) const {
1178 return Node->dumpr(G);
1179}
1180
1181// Define inline functions from the SDUse class.
1182
1183inline void SDUse::set(const SDValue &V) {
1184 if (Val.getNode()) removeFromList();
1185 Val = V;
1186 if (V.getNode()) V.getNode()->addUse(*this);
1187}
1188
1189inline void SDUse::setInitial(const SDValue &V) {
1190 Val = V;
1191 V.getNode()->addUse(*this);
1192}
1193
1194inline void SDUse::setNode(SDNode *N) {
1195 if (Val.getNode()) removeFromList();
1196 Val.setNode(N);
1197 if (N) N->addUse(*this);
1198}
1199
1200/// This class is used to form a handle around another node that
1201/// is persistent and is updated across invocations of replaceAllUsesWith on its
1202/// operand. This node should be directly created by end-users and not added to
1203/// the AllNodes list.
1204class HandleSDNode : public SDNode {
1205 SDUse Op;
1206
1207public:
1208 explicit HandleSDNode(SDValue X)
1209 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
1210 // HandleSDNodes are never inserted into the DAG, so they won't be
1211 // auto-numbered. Use ID 65535 as a sentinel.
1212 PersistentId = 0xffff;
1213
1214 // Manually set up the operand list. This node type is special in that it's
1215 // always stack allocated and SelectionDAG does not manage its operands.
1216 // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
1217 // be so special.
1218 Op.setUser(this);
1219 Op.setInitial(X);
1220 NumOperands = 1;
1221 OperandList = &Op;
1222 }
1223 ~HandleSDNode();
1224
1225 const SDValue &getValue() const { return Op; }
1226};
1227
1228class AddrSpaceCastSDNode : public SDNode {
1229private:
1230 unsigned SrcAddrSpace;
1231 unsigned DestAddrSpace;
1232
1233public:
1234 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1235 unsigned SrcAS, unsigned DestAS);
1236
1237 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
1238 unsigned getDestAddressSpace() const { return DestAddrSpace; }
1239
1240 static bool classof(const SDNode *N) {
1241 return N->getOpcode() == ISD::ADDRSPACECAST;
1242 }
1243};
1244
1245/// This is an abstract virtual class for memory operations.
1246class MemSDNode : public SDNode {
1247private:
1248 // VT of in-memory value.
1249 EVT MemoryVT;
1250
1251protected:
1252 /// Memory reference information.
1253 MachineMemOperand *MMO;
1254
1255public:
1256 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1257 EVT memvt, MachineMemOperand *MMO);
1258
1259 bool readMem() const { return MMO->isLoad(); }
1260 bool writeMem() const { return MMO->isStore(); }
1261
1262 /// Returns alignment and volatility of the memory access
1263 Align getOriginalAlign() const { return MMO->getBaseAlign(); }
1264 Align getAlign() const { return MMO->getAlign(); }
1265 // FIXME: Remove once transition to getAlign is over.
1266 unsigned getAlignment() const { return MMO->getAlign().value(); }
1267
1268 /// Return the SubclassData value, without HasDebugValue. This contains an
1269 /// encoding of the volatile flag, as well as bits used by subclasses. This
1270 /// function should only be used to compute a FoldingSetNodeID value.
1271 /// The HasDebugValue bit is masked out because CSE map needs to match
1272 /// nodes with debug info with nodes without debug info. Same is about
1273 /// isDivergent bit.
1274 unsigned getRawSubclassData() const {
1275 uint16_t Data;
1276 union {
1277 char RawSDNodeBits[sizeof(uint16_t)];
1278 SDNodeBitfields SDNodeBits;
1279 };
1280 memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
1281 SDNodeBits.HasDebugValue = 0;
1282 SDNodeBits.IsDivergent = false;
1283 memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
1284 return Data;
1285 }
1286
1287 bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
1288 bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
1289 bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
1290 bool isInvariant() const { return MemSDNodeBits.IsInvariant; }
1291
1292 // Returns the offset from the location of the access.
1293 int64_t getSrcValueOffset() const { return MMO->getOffset(); }
1294
1295 /// Returns the AA info that describes the dereference.
1296 AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }
1297
1298 /// Returns the Ranges that describes the dereference.
1299 const MDNode *getRanges() const { return MMO->getRanges(); }
1300
1301 /// Returns the synchronization scope ID for this memory operation.
1302 SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }
1303
1304 /// Return the atomic ordering requirements for this memory operation. For
1305 /// cmpxchg atomic operations, return the atomic ordering requirements when
1306 /// store occurs.
1307 AtomicOrdering getSuccessOrdering() const {
1308 return MMO->getSuccessOrdering();
1309 }
1310
1311 /// Return a single atomic ordering that is at least as strong as both the
1312 /// success and failure orderings for an atomic operation. (For operations
1313 /// other than cmpxchg, this is equivalent to getSuccessOrdering().)
1314 AtomicOrdering getMergedOrdering() const { return MMO->getMergedOrdering(); }
1315
1316 /// Return true if the memory operation ordering is Unordered or higher.
1317 bool isAtomic() const { return MMO->isAtomic(); }
1318
1319 /// Returns true if the memory operation doesn't imply any ordering
1320 /// constraints on surrounding memory operations beyond the normal memory
1321 /// aliasing rules.
1322 bool isUnordered() const { return MMO->isUnordered(); }
1323
1324 /// Returns true if the memory operation is neither atomic or volatile.
1325 bool isSimple() const { return !isAtomic() && !isVolatile(); }
1326
1327 /// Return the type of the in-memory value.
1328 EVT getMemoryVT() const { return MemoryVT; }
1329
1330 /// Return a MachineMemOperand object describing the memory
1331 /// reference performed by operation.
1332 MachineMemOperand *getMemOperand() const { return MMO; }
1333
1334 const MachinePointerInfo &getPointerInfo() const {
1335 return MMO->getPointerInfo();
1336 }
1337
1338 /// Return the address space for the associated pointer
1339 unsigned getAddressSpace() const {
1340 return getPointerInfo().getAddrSpace();
1341 }
1342
1343 /// Update this MemSDNode's MachineMemOperand information
1344 /// to reflect the alignment of NewMMO, if it has a greater alignment.
1345 /// This must only be used when the new alignment applies to all users of
1346 /// this MachineMemOperand.
1347 void refineAlignment(const MachineMemOperand *NewMMO) {
1348 MMO->refineAlignment(NewMMO);
1349 }
1350
1351 const SDValue &getChain() const { return getOperand(0); }
1352
1353 const SDValue &getBasePtr() const {
1354 switch (getOpcode()) {
1355 case ISD::STORE:
1356 case ISD::MSTORE:
1357 return getOperand(2);
1358 case ISD::MGATHER:
1359 case ISD::MSCATTER:
1360 return getOperand(3);
1361 default:
1362 return getOperand(1);
1363 }
1364 }
1365
1366 // Methods to support isa and dyn_cast
1367 static bool classof(const SDNode *N) {
1368 // For some targets, we lower some target intrinsics to a MemIntrinsicNode
1369 // with either an intrinsic or a target opcode.
1370 switch (N->getOpcode()) {
1371 case ISD::LOAD:
1372 case ISD::STORE:
1373 case ISD::PREFETCH:
1374 case ISD::ATOMIC_CMP_SWAP:
1375 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
1376 case ISD::ATOMIC_SWAP:
1377 case ISD::ATOMIC_LOAD_ADD:
1378 case ISD::ATOMIC_LOAD_SUB:
1379 case ISD::ATOMIC_LOAD_AND:
1380 case ISD::ATOMIC_LOAD_CLR:
1381 case ISD::ATOMIC_LOAD_OR:
1382 case ISD::ATOMIC_LOAD_XOR:
1383 case ISD::ATOMIC_LOAD_NAND:
1384 case ISD::ATOMIC_LOAD_MIN:
1385 case ISD::ATOMIC_LOAD_MAX:
1386 case ISD::ATOMIC_LOAD_UMIN:
1387 case ISD::ATOMIC_LOAD_UMAX:
1388 case ISD::ATOMIC_LOAD_FADD:
1389 case ISD::ATOMIC_LOAD_FSUB:
1390 case ISD::ATOMIC_LOAD:
1391 case ISD::ATOMIC_STORE:
1392 case ISD::MLOAD:
1393 case ISD::MSTORE:
1394 case ISD::MGATHER:
1395 case ISD::MSCATTER:
1396 return true;
1397 default:
1398 return N->isMemIntrinsic() || N->isTargetMemoryOpcode();
1399 }
1400 }
1401};
1402
1403/// This is an SDNode representing atomic operations.
1404class AtomicSDNode : public MemSDNode {
1405public:
1406 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
1407 EVT MemVT, MachineMemOperand *MMO)
1408 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
1409 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||(static_cast <bool> (((Opc != ISD::ATOMIC_LOAD &&
Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? void (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1410, __extension__ __PRETTY_FUNCTION__))
1410 MMO->isAtomic()) && "then why are we using an AtomicSDNode?")(static_cast <bool> (((Opc != ISD::ATOMIC_LOAD &&
Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? void (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1410, __extension__ __PRETTY_FUNCTION__))
;
1411 }
1412
1413 const SDValue &getBasePtr() const { return getOperand(1); }
1414 const SDValue &getVal() const { return getOperand(2); }
1415
1416 /// Returns true if this SDNode represents cmpxchg atomic operation, false
1417 /// otherwise.
1418 bool isCompareAndSwap() const {
1419 unsigned Op = getOpcode();
1420 return Op == ISD::ATOMIC_CMP_SWAP ||
1421 Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
1422 }
1423
1424 /// For cmpxchg atomic operations, return the atomic ordering requirements
1425 /// when store does not occur.
1426 AtomicOrdering getFailureOrdering() const {
1427 assert(isCompareAndSwap() && "Must be cmpxchg operation")(static_cast <bool> (isCompareAndSwap() && "Must be cmpxchg operation"
) ? void (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1427, __extension__ __PRETTY_FUNCTION__))
;
1428 return MMO->getFailureOrdering();
1429 }
1430
1431 // Methods to support isa and dyn_cast
1432 static bool classof(const SDNode *N) {
1433 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1434 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1435 N->getOpcode() == ISD::ATOMIC_SWAP ||
1436 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1437 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1438 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1439 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1440 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1441 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1442 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1443 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1444 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1445 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1446 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1447 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1448 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1449 N->getOpcode() == ISD::ATOMIC_LOAD ||
1450 N->getOpcode() == ISD::ATOMIC_STORE;
1451 }
1452};
1453
1454/// This SDNode is used for target intrinsics that touch
1455/// memory and need an associated MachineMemOperand. Its opcode may be
1456/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1457/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1458class MemIntrinsicSDNode : public MemSDNode {
1459public:
1460 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1461 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
1462 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
1463 SDNodeBits.IsMemIntrinsic = true;
1464 }
1465
1466 // Methods to support isa and dyn_cast
1467 static bool classof(const SDNode *N) {
1468 // We lower some target intrinsics to their target opcode
1469 // early a node with a target opcode can be of this class
1470 return N->isMemIntrinsic() ||
1471 N->getOpcode() == ISD::PREFETCH ||
1472 N->isTargetMemoryOpcode();
1473 }
1474};
1475
1476/// This SDNode is used to implement the code generator
1477/// support for the llvm IR shufflevector instruction. It combines elements
1478/// from two input vectors into a new input vector, with the selection and
1479/// ordering of elements determined by an array of integers, referred to as
1480/// the shuffle mask. For input vectors of width N, mask indices of 0..N-1
1481/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1482/// An index of -1 is treated as undef, such that the code generator may put
1483/// any value in the corresponding element of the result.
1484class ShuffleVectorSDNode : public SDNode {
1485 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
1486 // is freed when the SelectionDAG object is destroyed.
1487 const int *Mask;
1488
1489protected:
1490 friend class SelectionDAG;
1491
1492 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
1493 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1494
1495public:
1496 ArrayRef<int> getMask() const {
1497 EVT VT = getValueType(0);
1498 return makeArrayRef(Mask, VT.getVectorNumElements());
1499 }
1500
1501 int getMaskElt(unsigned Idx) const {
1502 assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")(static_cast <bool> (Idx < getValueType(0).getVectorNumElements
() && "Idx out of range!") ? void (0) : __assert_fail
("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1502, __extension__ __PRETTY_FUNCTION__))
;
1503 return Mask[Idx];
1504 }
1505
1506 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
1507
1508 int getSplatIndex() const {
1509 assert(isSplat() && "Cannot get splat index for non-splat!")(static_cast <bool> (isSplat() && "Cannot get splat index for non-splat!"
) ? void (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1509, __extension__ __PRETTY_FUNCTION__))
;
1510 EVT VT = getValueType(0);
1511 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
1512 if (Mask[i] >= 0)
1513 return Mask[i];
1514
1515 // We can choose any index value here and be correct because all elements
1516 // are undefined. Return 0 for better potential for callers to simplify.
1517 return 0;
1518 }
1519
1520 static bool isSplatMask(const int *Mask, EVT VT);
1521
1522 /// Change values in a shuffle permute mask assuming
1523 /// the two vector operands have swapped position.
1524 static void commuteMask(MutableArrayRef<int> Mask) {
1525 unsigned NumElems = Mask.size();
1526 for (unsigned i = 0; i != NumElems; ++i) {
1527 int idx = Mask[i];
1528 if (idx < 0)
1529 continue;
1530 else if (idx < (int)NumElems)
1531 Mask[i] = idx + NumElems;
1532 else
1533 Mask[i] = idx - NumElems;
1534 }
1535 }
1536
1537 static bool classof(const SDNode *N) {
1538 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
1539 }
1540};
1541
1542class ConstantSDNode : public SDNode {
1543 friend class SelectionDAG;
1544
1545 const ConstantInt *Value;
1546
1547 ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
1548 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
1549 getSDVTList(VT)),
1550 Value(val) {
1551 ConstantSDNodeBits.IsOpaque = isOpaque;
1552 }
1553
1554public:
1555 const ConstantInt *getConstantIntValue() const { return Value; }
1556 const APInt &getAPIntValue() const { return Value->getValue(); }
1557 uint64_t getZExtValue() const { return Value->getZExtValue(); }
1558 int64_t getSExtValue() const { return Value->getSExtValue(); }
1559 uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) {
1560 return Value->getLimitedValue(Limit);
1561 }
1562 MaybeAlign getMaybeAlignValue() const { return Value->getMaybeAlignValue(); }
1563 Align getAlignValue() const { return Value->getAlignValue(); }
1564
1565 bool isOne() const { return Value->isOne(); }
1566 bool isNullValue() const { return Value->isZero(); }
1567 bool isAllOnesValue() const { return Value->isMinusOne(); }
1568 bool isMaxSignedValue() const { return Value->isMaxValue(true); }
1569 bool isMinSignedValue() const { return Value->isMinValue(true); }
1570
1571 bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }
1572
1573 static bool classof(const SDNode *N) {
1574 return N->getOpcode() == ISD::Constant ||
1575 N->getOpcode() == ISD::TargetConstant;
1576 }
1577};
1578
1579uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
1580 return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1581}
1582
1583const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
1584 return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
1585}
1586
1587class ConstantFPSDNode : public SDNode {
1588 friend class SelectionDAG;
1589
1590 const ConstantFP *Value;
1591
1592 ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
1593 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
1594 DebugLoc(), getSDVTList(VT)),
1595 Value(val) {}
1596
1597public:
1598 const APFloat& getValueAPF() const { return Value->getValueAPF(); }
1599 const ConstantFP *getConstantFPValue() const { return Value; }
1600
1601 /// Return true if the value is positive or negative zero.
1602 bool isZero() const { return Value->isZero(); }
1603
1604 /// Return true if the value is a NaN.
1605 bool isNaN() const { return Value->isNaN(); }
1606
1607 /// Return true if the value is an infinity
1608 bool isInfinity() const { return Value->isInfinity(); }
1609
1610 /// Return true if the value is negative.
1611 bool isNegative() const { return Value->isNegative(); }
1612
1613 /// We don't rely on operator== working on double values, as
1614 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
1615 /// As such, this method can be used to do an exact bit-for-bit comparison of
1616 /// two floating point values.
1617
1618 /// We leave the version with the double argument here because it's just so
1619 /// convenient to write "2.0" and the like. Without this function we'd
1620 /// have to duplicate its logic everywhere it's called.
1621 bool isExactlyValue(double V) const {
1622 return Value->getValueAPF().isExactlyValue(V);
1623 }
1624 bool isExactlyValue(const APFloat& V) const;
1625
1626 static bool isValueValidForType(EVT VT, const APFloat& Val);
1627
1628 static bool classof(const SDNode *N) {
1629 return N->getOpcode() == ISD::ConstantFP ||
1630 N->getOpcode() == ISD::TargetConstantFP;
1631 }
1632};
1633
1634/// Returns true if \p V is a constant integer zero.
1635bool isNullConstant(SDValue V);
1636
1637/// Returns true if \p V is an FP constant with a value of positive zero.
1638bool isNullFPConstant(SDValue V);
1639
1640/// Returns true if \p V is an integer constant with all bits set.
1641bool isAllOnesConstant(SDValue V);
1642
1643/// Returns true if \p V is a constant integer one.
1644bool isOneConstant(SDValue V);
1645
1646/// Return the non-bitcasted source operand of \p V if it exists.
1647/// If \p V is not a bitcasted value, it is returned as-is.
1648SDValue peekThroughBitcasts(SDValue V);
1649
1650/// Return the non-bitcasted and one-use source operand of \p V if it exists.
1651/// If \p V is not a bitcasted one-use value, it is returned as-is.
1652SDValue peekThroughOneUseBitcasts(SDValue V);
1653
1654/// Return the non-extracted vector source operand of \p V if it exists.
1655/// If \p V is not an extracted subvector, it is returned as-is.
1656SDValue peekThroughExtractSubvectors(SDValue V);
1657
1658/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1659/// constant is canonicalized to be operand 1.
1660bool isBitwiseNot(SDValue V, bool AllowUndefs = false);
1661
1662/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1663ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false,
1664 bool AllowTruncation = false);
1665
1666/// Returns the SDNode if it is a demanded constant splat BuildVector or
1667/// constant int.
1668ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
1669 bool AllowUndefs = false,
1670 bool AllowTruncation = false);
1671
1672/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1673ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false);
1674
1675/// Returns the SDNode if it is a demanded constant splat BuildVector or
1676/// constant float.
1677ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts,
1678 bool AllowUndefs = false);
1679
1680/// Return true if the value is a constant 0 integer or a splatted vector of
1681/// a constant 0 integer (with no undefs by default).
1682/// Build vector implicit truncation is not an issue for null values.
1683bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false);
1684
1685/// Return true if the value is a constant 1 integer or a splatted vector of a
1686/// constant 1 integer (with no undefs).
1687/// Does not permit build vector implicit truncation.
1688bool isOneOrOneSplat(SDValue V, bool AllowUndefs = false);
1689
1690/// Return true if the value is a constant -1 integer or a splatted vector of a
1691/// constant -1 integer (with no undefs).
1692/// Does not permit build vector implicit truncation.
1693bool isAllOnesOrAllOnesSplat(SDValue V, bool AllowUndefs = false);
1694
1695/// Return true if \p V is either a integer or FP constant.
1696inline bool isIntOrFPConstant(SDValue V) {
1697 return isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V);
1698}
1699
1700class GlobalAddressSDNode : public SDNode {
1701 friend class SelectionDAG;
1702
1703 const GlobalValue *TheGlobal;
1704 int64_t Offset;
1705 unsigned TargetFlags;
1706
1707 GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
1708 const GlobalValue *GA, EVT VT, int64_t o,
1709 unsigned TF);
1710
1711public:
1712 const GlobalValue *getGlobal() const { return TheGlobal; }
1713 int64_t getOffset() const { return Offset; }
1714 unsigned getTargetFlags() const { return TargetFlags; }
1715 // Return the address space this GlobalAddress belongs to.
1716 unsigned getAddressSpace() const;
1717
1718 static bool classof(const SDNode *N) {
1719 return N->getOpcode() == ISD::GlobalAddress ||
1720 N->getOpcode() == ISD::TargetGlobalAddress ||
1721 N->getOpcode() == ISD::GlobalTLSAddress ||
1722 N->getOpcode() == ISD::TargetGlobalTLSAddress;
1723 }
1724};
1725
1726class FrameIndexSDNode : public SDNode {
1727 friend class SelectionDAG;
1728
1729 int FI;
1730
1731 FrameIndexSDNode(int fi, EVT VT, bool isTarg)
1732 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1733 0, DebugLoc(), getSDVTList(VT)), FI(fi) {
1734 }
1735
1736public:
1737 int getIndex() const { return FI; }
1738
1739 static bool classof(const SDNode *N) {
1740 return N->getOpcode() == ISD::FrameIndex ||
1741 N->getOpcode() == ISD::TargetFrameIndex;
1742 }
1743};
1744
1745/// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate
1746/// the offet and size that are started/ended in the underlying FrameIndex.
1747class LifetimeSDNode : public SDNode {
1748 friend class SelectionDAG;
1749 int64_t Size;
1750 int64_t Offset; // -1 if offset is unknown.
1751
1752 LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
1753 SDVTList VTs, int64_t Size, int64_t Offset)
1754 : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {}
1755public:
1756 int64_t getFrameIndex() const {
1757 return cast<FrameIndexSDNode>(getOperand(1))->getIndex();
1758 }
1759
1760 bool hasOffset() const { return Offset >= 0; }
1761 int64_t getOffset() const {
1762 assert(hasOffset() && "offset is unknown")(static_cast <bool> (hasOffset() && "offset is unknown"
) ? void (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1762, __extension__ __PRETTY_FUNCTION__))
;
1763 return Offset;
1764 }
1765 int64_t getSize() const {
1766 assert(hasOffset() && "offset is unknown")(static_cast <bool> (hasOffset() && "offset is unknown"
) ? void (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1766, __extension__ __PRETTY_FUNCTION__))
;
1767 return Size;
1768 }
1769
1770 // Methods to support isa and dyn_cast
1771 static bool classof(const SDNode *N) {
1772 return N->getOpcode() == ISD::LIFETIME_START ||
1773 N->getOpcode() == ISD::LIFETIME_END;
1774 }
1775};
1776
1777/// This SDNode is used for PSEUDO_PROBE values, which are the function guid and
1778/// the index of the basic block being probed. A pseudo probe serves as a place
1779/// holder and will be removed at the end of compilation. It does not have any
1780/// operand because we do not want the instruction selection to deal with any.
1781class PseudoProbeSDNode : public SDNode {
1782 friend class SelectionDAG;
1783 uint64_t Guid;
1784 uint64_t Index;
1785 uint32_t Attributes;
1786
1787 PseudoProbeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &Dl,
1788 SDVTList VTs, uint64_t Guid, uint64_t Index, uint32_t Attr)
1789 : SDNode(Opcode, Order, Dl, VTs), Guid(Guid), Index(Index),
1790 Attributes(Attr) {}
1791
1792public:
1793 uint64_t getGuid() const { return Guid; }
1794 uint64_t getIndex() const { return Index; }
1795 uint32_t getAttributes() const { return Attributes; }
1796
1797 // Methods to support isa and dyn_cast
1798 static bool classof(const SDNode *N) {
1799 return N->getOpcode() == ISD::PSEUDO_PROBE;
1800 }
1801};
1802
1803class JumpTableSDNode : public SDNode {
1804 friend class SelectionDAG;
1805
1806 int JTI;
1807 unsigned TargetFlags;
1808
1809 JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF)
1810 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
1811 0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
1812 }
1813
1814public:
1815 int getIndex() const { return JTI; }
1816 unsigned getTargetFlags() const { return TargetFlags; }
1817
1818 static bool classof(const SDNode *N) {
1819 return N->getOpcode() == ISD::JumpTable ||
1820 N->getOpcode() == ISD::TargetJumpTable;
1821 }
1822};
1823
1824class ConstantPoolSDNode : public SDNode {
1825 friend class SelectionDAG;
1826
1827 union {
1828 const Constant *ConstVal;
1829 MachineConstantPoolValue *MachineCPVal;
1830 } Val;
1831 int Offset; // It's a MachineConstantPoolValue if top bit is set.
1832 Align Alignment; // Minimum alignment requirement of CP.
1833 unsigned TargetFlags;
1834
1835 ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
1836 Align Alignment, unsigned TF)
1837 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1838 DebugLoc(), getSDVTList(VT)),
1839 Offset(o), Alignment(Alignment), TargetFlags(TF) {
1840 assert(Offset >= 0 && "Offset is too large")(static_cast <bool> (Offset >= 0 && "Offset is too large"
) ? void (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1840, __extension__ __PRETTY_FUNCTION__))
;
1841 Val.ConstVal = c;
1842 }
1843
1844 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, EVT VT, int o,
1845 Align Alignment, unsigned TF)
1846 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1847 DebugLoc(), getSDVTList(VT)),
1848 Offset(o), Alignment(Alignment), TargetFlags(TF) {
1849 assert(Offset >= 0 && "Offset is too large")(static_cast <bool> (Offset >= 0 && "Offset is too large"
) ? void (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1849, __extension__ __PRETTY_FUNCTION__))
;
1850 Val.MachineCPVal = v;
1851 Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
1852 }
1853
1854public:
1855 bool isMachineConstantPoolEntry() const {
1856 return Offset < 0;
1857 }
1858
1859 const Constant *getConstVal() const {
1860 assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")(static_cast <bool> (!isMachineConstantPoolEntry() &&
"Wrong constantpool type") ? void (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1860, __extension__ __PRETTY_FUNCTION__))
;
1861 return Val.ConstVal;
1862 }
1863
1864 MachineConstantPoolValue *getMachineCPVal() const {
1865 assert(isMachineConstantPoolEntry() && "Wrong constantpool type")(static_cast <bool> (isMachineConstantPoolEntry() &&
"Wrong constantpool type") ? void (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1865, __extension__ __PRETTY_FUNCTION__))
;
1866 return Val.MachineCPVal;
1867 }
1868
1869 int getOffset() const {
1870 return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
1871 }
1872
1873 // Return the alignment of this constant pool object, which is either 0 (for
1874 // default alignment) or the desired value.
1875 Align getAlign() const { return Alignment; }
1876 unsigned getTargetFlags() const { return TargetFlags; }
1877
1878 Type *getType() const;
1879
1880 static bool classof(const SDNode *N) {
1881 return N->getOpcode() == ISD::ConstantPool ||
1882 N->getOpcode() == ISD::TargetConstantPool;
1883 }
1884};
1885
1886/// Completely target-dependent object reference.
1887class TargetIndexSDNode : public SDNode {
1888 friend class SelectionDAG;
1889
1890 unsigned TargetFlags;
1891 int Index;
1892 int64_t Offset;
1893
1894public:
1895 TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF)
1896 : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
1897 TargetFlags(TF), Index(Idx), Offset(Ofs) {}
1898
1899 unsigned getTargetFlags() const { return TargetFlags; }
1900 int getIndex() const { return Index; }
1901 int64_t getOffset() const { return Offset; }
1902
1903 static bool classof(const SDNode *N) {
1904 return N->getOpcode() == ISD::TargetIndex;
1905 }
1906};
1907
1908class BasicBlockSDNode : public SDNode {
1909 friend class SelectionDAG;
1910
1911 MachineBasicBlock *MBB;
1912
1913 /// Debug info is meaningful and potentially useful here, but we create
1914 /// blocks out of order when they're jumped to, which makes it a bit
1915 /// harder. Let's see if we need it first.
1916 explicit BasicBlockSDNode(MachineBasicBlock *mbb)
1917 : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
1918 {}
1919
1920public:
1921 MachineBasicBlock *getBasicBlock() const { return MBB; }
1922
1923 static bool classof(const SDNode *N) {
1924 return N->getOpcode() == ISD::BasicBlock;
1925 }
1926};
1927
1928/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1929class BuildVectorSDNode : public SDNode {
1930public:
1931 // These are constructed as SDNodes and then cast to BuildVectorSDNodes.
1932 explicit BuildVectorSDNode() = delete;
1933
1934 /// Check if this is a constant splat, and if so, find the
1935 /// smallest element size that splats the vector. If MinSplatBits is
1936 /// nonzero, the element size must be at least that large. Note that the
1937 /// splat element may be the entire vector (i.e., a one element vector).
1938 /// Returns the splat element value in SplatValue. Any undefined bits in
1939 /// that value are zero, and the corresponding bits in the SplatUndef mask
1940 /// are set. The SplatBitSize value is set to the splat element size in
1941 /// bits. HasAnyUndefs is set to true if any bits in the vector are
1942 /// undefined. isBigEndian describes the endianness of the target.
1943 bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
1944 unsigned &SplatBitSize, bool &HasAnyUndefs,
1945 unsigned MinSplatBits = 0,
1946 bool isBigEndian = false) const;
1947
1948 /// Returns the demanded splatted value or a null value if this is not a
1949 /// splat.
1950 ///
1951 /// The DemandedElts mask indicates the elements that must be in the splat.
1952 /// If passed a non-null UndefElements bitvector, it will resize it to match
1953 /// the vector width and set the bits where elements are undef.
1954 SDValue getSplatValue(const APInt &DemandedElts,
1955 BitVector *UndefElements = nullptr) const;
1956
1957 /// Returns the splatted value or a null value if this is not a splat.
1958 ///
1959 /// If passed a non-null UndefElements bitvector, it will resize it to match
1960 /// the vector width and set the bits where elements are undef.
1961 SDValue getSplatValue(BitVector *UndefElements = nullptr) const;
1962
1963 /// Find the shortest repeating sequence of values in the build vector.
1964 ///
1965 /// e.g. { u, X, u, X, u, u, X, u } -> { X }
1966 /// { X, Y, u, Y, u, u, X, u } -> { X, Y }
1967 ///
1968 /// Currently this must be a power-of-2 build vector.
1969 /// The DemandedElts mask indicates the elements that must be present,
1970 /// undemanded elements in Sequence may be null (SDValue()). If passed a
1971 /// non-null UndefElements bitvector, it will resize it to match the original
1972 /// vector width and set the bits where elements are undef. If result is
1973 /// false, Sequence will be empty.
1974 bool getRepeatedSequence(const APInt &DemandedElts,
1975 SmallVectorImpl<SDValue> &Sequence,
1976 BitVector *UndefElements = nullptr) const;
1977
1978 /// Find the shortest repeating sequence of values in the build vector.
1979 ///
1980 /// e.g. { u, X, u, X, u, u, X, u } -> { X }
1981 /// { X, Y, u, Y, u, u, X, u } -> { X, Y }
1982 ///
1983 /// Currently this must be a power-of-2 build vector.
1984 /// If passed a non-null UndefElements bitvector, it will resize it to match
1985 /// the original vector width and set the bits where elements are undef.
1986 /// If result is false, Sequence will be empty.
1987 bool getRepeatedSequence(SmallVectorImpl<SDValue> &Sequence,
1988 BitVector *UndefElements = nullptr) const;
1989
1990 /// Returns the demanded splatted constant or null if this is not a constant
1991 /// splat.
1992 ///
1993 /// The DemandedElts mask indicates the elements that must be in the splat.
1994 /// If passed a non-null UndefElements bitvector, it will resize it to match
1995 /// the vector width and set the bits where elements are undef.
1996 ConstantSDNode *
1997 getConstantSplatNode(const APInt &DemandedElts,
1998 BitVector *UndefElements = nullptr) const;
1999
2000 /// Returns the splatted constant or null if this is not a constant
2001 /// splat.
2002 ///
2003 /// If passed a non-null UndefElements bitvector, it will resize it to match
2004 /// the vector width and set the bits where elements are undef.
2005 ConstantSDNode *
2006 getConstantSplatNode(BitVector *UndefElements = nullptr) const;
2007
2008 /// Returns the demanded splatted constant FP or null if this is not a
2009 /// constant FP splat.
2010 ///
2011 /// The DemandedElts mask indicates the elements that must be in the splat.
2012 /// If passed a non-null UndefElements bitvector, it will resize it to match
2013 /// the vector width and set the bits where elements are undef.
2014 ConstantFPSDNode *
2015 getConstantFPSplatNode(const APInt &DemandedElts,
2016 BitVector *UndefElements = nullptr) const;
2017
2018 /// Returns the splatted constant FP or null if this is not a constant
2019 /// FP splat.
2020 ///
2021 /// If passed a non-null UndefElements bitvector, it will resize it to match
2022 /// the vector width and set the bits where elements are undef.
2023 ConstantFPSDNode *
2024 getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;
2025
2026 /// If this is a constant FP splat and the splatted constant FP is an
2027 /// exact power or 2, return the log base 2 integer value. Otherwise,
2028 /// return -1.
2029 ///
2030 /// The BitWidth specifies the necessary bit precision.
2031 int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
2032 uint32_t BitWidth) const;
2033
2034 bool isConstant() const;
2035
2036 static bool classof(const SDNode *N) {
2037 return N->getOpcode() == ISD::BUILD_VECTOR;
2038 }
2039};
2040
2041/// An SDNode that holds an arbitrary LLVM IR Value. This is
2042/// used when the SelectionDAG needs to make a simple reference to something
2043/// in the LLVM IR representation.
2044///
2045class SrcValueSDNode : public SDNode {
2046 friend class SelectionDAG;
2047
2048 const Value *V;
2049
2050 /// Create a SrcValue for a general value.
2051 explicit SrcValueSDNode(const Value *v)
2052 : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}
2053
2054public:
2055 /// Return the contained Value.
2056 const Value *getValue() const { return V; }
2057
2058 static bool classof(const SDNode *N) {
2059 return N->getOpcode() == ISD::SRCVALUE;
2060 }
2061};
2062
2063class MDNodeSDNode : public SDNode {
2064 friend class SelectionDAG;
2065
2066 const MDNode *MD;
2067
2068 explicit MDNodeSDNode(const MDNode *md)
2069 : SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
2070 {}
2071
2072public:
2073 const MDNode *getMD() const { return MD; }
2074
2075 static bool classof(const SDNode *N) {
2076 return N->getOpcode() == ISD::MDNODE_SDNODE;
2077 }
2078};
2079
2080class RegisterSDNode : public SDNode {
2081 friend class SelectionDAG;
2082
2083 Register Reg;
2084
2085 RegisterSDNode(Register reg, EVT VT)
2086 : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}
2087
2088public:
2089 Register getReg() const { return Reg; }
2090
2091 static bool classof(const SDNode *N) {
2092 return N->getOpcode() == ISD::Register;
2093 }
2094};
2095
2096class RegisterMaskSDNode : public SDNode {
2097 friend class SelectionDAG;
2098
2099 // The memory for RegMask is not owned by the node.
2100 const uint32_t *RegMask;
2101
2102 RegisterMaskSDNode(const uint32_t *mask)
2103 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
2104 RegMask(mask) {}
2105
2106public:
2107 const uint32_t *getRegMask() const { return RegMask; }
2108
2109 static bool classof(const SDNode *N) {
2110 return N->getOpcode() == ISD::RegisterMask;
2111 }
2112};
2113
2114class BlockAddressSDNode : public SDNode {
2115 friend class SelectionDAG;
2116
2117 const BlockAddress *BA;
2118 int64_t Offset;
2119 unsigned TargetFlags;
2120
2121 BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
2122 int64_t o, unsigned Flags)
2123 : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
2124 BA(ba), Offset(o), TargetFlags(Flags) {}
2125
2126public:
2127 const BlockAddress *getBlockAddress() const { return BA; }
2128 int64_t getOffset() const { return Offset; }
2129 unsigned getTargetFlags() const { return TargetFlags; }
2130
2131 static bool classof(const SDNode *N) {
2132 return N->getOpcode() == ISD::BlockAddress ||
2133 N->getOpcode() == ISD::TargetBlockAddress;
2134 }
2135};
2136
2137class LabelSDNode : public SDNode {
2138 friend class SelectionDAG;
2139
2140 MCSymbol *Label;
2141
2142 LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L)
2143 : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) {
2144 assert(LabelSDNode::classof(this) && "not a label opcode")(static_cast <bool> (LabelSDNode::classof(this) &&
"not a label opcode") ? void (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2144, __extension__ __PRETTY_FUNCTION__))
;
2145 }
2146
2147public:
2148 MCSymbol *getLabel() const { return Label; }
2149
2150 static bool classof(const SDNode *N) {
2151 return N->getOpcode() == ISD::EH_LABEL ||
2152 N->getOpcode() == ISD::ANNOTATION_LABEL;
2153 }
2154};
2155
2156class ExternalSymbolSDNode : public SDNode {
2157 friend class SelectionDAG;
2158
2159 const char *Symbol;
2160 unsigned TargetFlags;
2161
2162 ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT)
2163 : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0,
2164 DebugLoc(), getSDVTList(VT)),
2165 Symbol(Sym), TargetFlags(TF) {}
2166
2167public:
2168 const char *getSymbol() const { return Symbol; }
2169 unsigned getTargetFlags() const { return TargetFlags; }
2170
2171 static bool classof(const SDNode *N) {
2172 return N->getOpcode() == ISD::ExternalSymbol ||
2173 N->getOpcode() == ISD::TargetExternalSymbol;
2174 }
2175};
2176
2177class MCSymbolSDNode : public SDNode {
2178 friend class SelectionDAG;
2179
2180 MCSymbol *Symbol;
2181
2182 MCSymbolSDNode(MCSymbol *Symbol, EVT VT)
2183 : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {}
2184
2185public:
2186 MCSymbol *getMCSymbol() const { return Symbol; }
2187
2188 static bool classof(const SDNode *N) {
2189 return N->getOpcode() == ISD::MCSymbol;
2190 }
2191};
2192
2193class CondCodeSDNode : public SDNode {
2194 friend class SelectionDAG;
2195
2196 ISD::CondCode Condition;
2197
2198 explicit CondCodeSDNode(ISD::CondCode Cond)
2199 : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2200 Condition(Cond) {}
2201
2202public:
2203 ISD::CondCode get() const { return Condition; }
2204
2205 static bool classof(const SDNode *N) {
2206 return N->getOpcode() == ISD::CONDCODE;
2207 }
2208};
2209
2210/// This class is used to represent EVT's, which are used
2211/// to parameterize some operations.
2212class VTSDNode : public SDNode {
2213 friend class SelectionDAG;
2214
2215 EVT ValueType;
2216
2217 explicit VTSDNode(EVT VT)
2218 : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
2219 ValueType(VT) {}
2220
2221public:
2222 EVT getVT() const { return ValueType; }
2223
2224 static bool classof(const SDNode *N) {
2225 return N->getOpcode() == ISD::VALUETYPE;
2226 }
2227};
2228
2229/// Base class for LoadSDNode and StoreSDNode
2230class LSBaseSDNode : public MemSDNode {
2231public:
2232 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
2233 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
2234 MachineMemOperand *MMO)
2235 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2236 LSBaseSDNodeBits.AddressingMode = AM;
2237 assert(getAddressingMode() == AM && "Value truncated")(static_cast <bool> (getAddressingMode() == AM &&
"Value truncated") ? void (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2237, __extension__ __PRETTY_FUNCTION__))
;
2238 }
2239
2240 const SDValue &getOffset() const {
2241 return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
2242 }
2243
2244 /// Return the addressing mode for this load or store:
2245 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2246 ISD::MemIndexedMode getAddressingMode() const {
2247 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2248 }
2249
2250 /// Return true if this is a pre/post inc/dec load/store.
2251 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2252
2253 /// Return true if this is NOT a pre/post inc/dec load/store.
2254 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2255
2256 static bool classof(const SDNode *N) {
2257 return N->getOpcode() == ISD::LOAD ||
2258 N->getOpcode() == ISD::STORE;
2259 }
2260};
2261
2262/// This class is used to represent ISD::LOAD nodes.
2263class LoadSDNode : public LSBaseSDNode {
2264 friend class SelectionDAG;
2265
2266 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2267 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
2268 MachineMemOperand *MMO)
2269 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
2270 LoadSDNodeBits.ExtTy = ETy;
2271 assert(readMem() && "Load MachineMemOperand is not a load!")(static_cast <bool> (readMem() && "Load MachineMemOperand is not a load!"
) ? void (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2271, __extension__ __PRETTY_FUNCTION__))
;
2272 assert(!writeMem() && "Load MachineMemOperand is a store!")(static_cast <bool> (!writeMem() && "Load MachineMemOperand is a store!"
) ? void (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2272, __extension__ __PRETTY_FUNCTION__))
;
2273 }
2274
2275public:
2276 /// Return whether this is a plain node,
2277 /// or one of the varieties of value-extending loads.
2278 ISD::LoadExtType getExtensionType() const {
2279 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2280 }
2281
2282 const SDValue &getBasePtr() const { return getOperand(1); }
2283 const SDValue &getOffset() const { return getOperand(2); }
2284
2285 static bool classof(const SDNode *N) {
2286 return N->getOpcode() == ISD::LOAD;
2287 }
2288};
2289
2290/// This class is used to represent ISD::STORE nodes.
2291class StoreSDNode : public LSBaseSDNode {
2292 friend class SelectionDAG;
2293
2294 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2295 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2296 MachineMemOperand *MMO)
2297 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2298 StoreSDNodeBits.IsTruncating = isTrunc;
2299 assert(!readMem() && "Store MachineMemOperand is a load!")(static_cast <bool> (!readMem() && "Store MachineMemOperand is a load!"
) ? void (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2299, __extension__ __PRETTY_FUNCTION__))
;
2300 assert(writeMem() && "Store MachineMemOperand is not a store!")(static_cast <bool> (writeMem() && "Store MachineMemOperand is not a store!"
) ? void (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2300, __extension__ __PRETTY_FUNCTION__))
;
2301 }
2302
2303public:
2304 /// Return true if the op does a truncation before store.
2305 /// For integers this is the same as doing a TRUNCATE and storing the result.
2306 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2307 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2308 void setTruncatingStore(bool Truncating) {
2309 StoreSDNodeBits.IsTruncating = Truncating;
2310 }
2311
2312 const SDValue &getValue() const { return getOperand(1); }
2313 const SDValue &getBasePtr() const { return getOperand(2); }
2314 const SDValue &getOffset() const { return getOperand(3); }
2315
2316 static bool classof(const SDNode *N) {
2317 return N->getOpcode() == ISD::STORE;
2318 }
2319};
2320
2321/// This base class is used to represent MLOAD and MSTORE nodes
2322class MaskedLoadStoreSDNode : public MemSDNode {
2323public:
2324 friend class SelectionDAG;
2325
2326 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
2327 const DebugLoc &dl, SDVTList VTs,
2328 ISD::MemIndexedMode AM, EVT MemVT,
2329 MachineMemOperand *MMO)
2330 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2331 LSBaseSDNodeBits.AddressingMode = AM;
2332 assert(getAddressingMode() == AM && "Value truncated")(static_cast <bool> (getAddressingMode() == AM &&
"Value truncated") ? void (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2332, __extension__ __PRETTY_FUNCTION__))
;
2333 }
2334
2335 // MaskedLoadSDNode (Chain, ptr, offset, mask, passthru)
2336 // MaskedStoreSDNode (Chain, data, ptr, offset, mask)
2337 // Mask is a vector of i1 elements
2338 const SDValue &getOffset() const {
2339 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2340 }
2341 const SDValue &getMask() const {
2342 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2343 }
2344
2345 /// Return the addressing mode for this load or store:
2346 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
2347 ISD::MemIndexedMode getAddressingMode() const {
2348 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
2349 }
2350
2351 /// Return true if this is a pre/post inc/dec load/store.
2352 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
2353
2354 /// Return true if this is NOT a pre/post inc/dec load/store.
2355 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2356
2357 static bool classof(const SDNode *N) {
2358 return N->getOpcode() == ISD::MLOAD ||
2359 N->getOpcode() == ISD::MSTORE;
2360 }
2361};
2362
2363/// This class is used to represent an MLOAD node
2364class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
2365public:
2366 friend class SelectionDAG;
2367
2368 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2369 ISD::MemIndexedMode AM, ISD::LoadExtType ETy,
2370 bool IsExpanding, EVT MemVT, MachineMemOperand *MMO)
2371 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2372 LoadSDNodeBits.ExtTy = ETy;
2373 LoadSDNodeBits.IsExpanding = IsExpanding;
2374 }
2375
2376 ISD::LoadExtType getExtensionType() const {
2377 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2378 }
2379
2380 const SDValue &getBasePtr() const { return getOperand(1); }
2381 const SDValue &getOffset() const { return getOperand(2); }
2382 const SDValue &getMask() const { return getOperand(3); }
2383 const SDValue &getPassThru() const { return getOperand(4); }
2384
2385 static bool classof(const SDNode *N) {
2386 return N->getOpcode() == ISD::MLOAD;
2387 }
2388
2389 bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2390};
2391
2392/// This class is used to represent an MSTORE node
2393class MaskedStoreSDNode : public MaskedLoadStoreSDNode {
2394public:
2395 friend class SelectionDAG;
2396
2397 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2398 ISD::MemIndexedMode AM, bool isTrunc, bool isCompressing,
2399 EVT MemVT, MachineMemOperand *MMO)
2400 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, AM, MemVT, MMO) {
2401 StoreSDNodeBits.IsTruncating = isTrunc;
2402 StoreSDNodeBits.IsCompressing = isCompressing;
2403 }
2404
2405 /// Return true if the op does a truncation before store.
2406 /// For integers this is the same as doing a TRUNCATE and storing the result.
2407 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2408 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2409
2410 /// Returns true if the op does a compression to the vector before storing.
2411 /// The node contiguously stores the active elements (integers or floats)
2412 /// in src (those with their respective bit set in writemask k) to unaligned
2413 /// memory at base_addr.
2414 bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }
2415
2416 const SDValue &getValue() const { return getOperand(1); }
2417 const SDValue &getBasePtr() const { return getOperand(2); }
2418 const SDValue &getOffset() const { return getOperand(3); }
2419 const SDValue &getMask() const { return getOperand(4); }
2420
2421 static bool classof(const SDNode *N) {
2422 return N->getOpcode() == ISD::MSTORE;
2423 }
2424};
2425
2426/// This is a base class used to represent
2427/// MGATHER and MSCATTER nodes
2428///
2429class MaskedGatherScatterSDNode : public MemSDNode {
2430public:
2431 friend class SelectionDAG;
2432
2433 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
2434 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2435 MachineMemOperand *MMO, ISD::MemIndexType IndexType)
2436 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
2437 LSBaseSDNodeBits.AddressingMode = IndexType;
2438 assert(getIndexType() == IndexType && "Value truncated")(static_cast <bool> (getIndexType() == IndexType &&
"Value truncated") ? void (0) : __assert_fail ("getIndexType() == IndexType && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2438, __extension__ __PRETTY_FUNCTION__))
;
2439 }
2440
2441 /// How is Index applied to BasePtr when computing addresses.
2442 ISD::MemIndexType getIndexType() const {
2443 return static_cast<ISD::MemIndexType>(LSBaseSDNodeBits.AddressingMode);
2444 }
2445 void setIndexType(ISD::MemIndexType IndexType) {
2446 LSBaseSDNodeBits.AddressingMode = IndexType;
2447 }
2448 bool isIndexScaled() const {
2449 return (getIndexType() == ISD::SIGNED_SCALED) ||
2450 (getIndexType() == ISD::UNSIGNED_SCALED);
2451 }
2452 bool isIndexSigned() const {
2453 return (getIndexType() == ISD::SIGNED_SCALED) ||
2454 (getIndexType() == ISD::SIGNED_UNSCALED);
2455 }
2456
2457 // In the both nodes address is Op1, mask is Op2:
2458 // MaskedGatherSDNode (Chain, passthru, mask, base, index, scale)
2459 // MaskedScatterSDNode (Chain, value, mask, base, index, scale)
2460 // Mask is a vector of i1 elements
2461 const SDValue &getBasePtr() const { return getOperand(3); }
2462 const SDValue &getIndex() const { return getOperand(4); }
2463 const SDValue &getMask() const { return getOperand(2); }
2464 const SDValue &getScale() const { return getOperand(5); }
2465
2466 static bool classof(const SDNode *N) {
2467 return N->getOpcode() == ISD::MGATHER ||
2468 N->getOpcode() == ISD::MSCATTER;
2469 }
2470};
2471
2472/// This class is used to represent an MGATHER node
2473///
2474class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
2475public:
2476 friend class SelectionDAG;
2477
2478 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2479 EVT MemVT, MachineMemOperand *MMO,
2480 ISD::MemIndexType IndexType, ISD::LoadExtType ETy)
2481 : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO,
2482 IndexType) {
2483 LoadSDNodeBits.ExtTy = ETy;
2484 }
2485
2486 const SDValue &getPassThru() const { return getOperand(1); }
2487
2488 ISD::LoadExtType getExtensionType() const {
2489 return ISD::LoadExtType(LoadSDNodeBits.ExtTy);
2490 }
2491
2492 static bool classof(const SDNode *N) {
2493 return N->getOpcode() == ISD::MGATHER;
2494 }
2495};
2496
2497/// This class is used to represent an MSCATTER node
2498///
2499class MaskedScatterSDNode : public MaskedGatherScatterSDNode {
2500public:
2501 friend class SelectionDAG;
2502
2503 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2504 EVT MemVT, MachineMemOperand *MMO,
2505 ISD::MemIndexType IndexType, bool IsTrunc)
2506 : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO,
2507 IndexType) {
2508 StoreSDNodeBits.IsTruncating = IsTrunc;
2509 }
2510
2511 /// Return true if the op does a truncation before store.
2512 /// For integers this is the same as doing a TRUNCATE and storing the result.
2513 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2514 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2515
2516 const SDValue &getValue() const { return getOperand(1); }
2517
2518 static bool classof(const SDNode *N) {
2519 return N->getOpcode() == ISD::MSCATTER;
2520 }
2521};
2522
2523/// An SDNode that represents everything that will be needed
2524/// to construct a MachineInstr. These nodes are created during the
2525/// instruction selection proper phase.
2526///
2527/// Note that the only supported way to set the `memoperands` is by calling the
2528/// `SelectionDAG::setNodeMemRefs` function as the memory management happens
2529/// inside the DAG rather than in the node.
2530class MachineSDNode : public SDNode {
2531private:
2532 friend class SelectionDAG;
2533
2534 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
2535 : SDNode(Opc, Order, DL, VTs) {}
2536
2537 // We use a pointer union between a single `MachineMemOperand` pointer and
2538 // a pointer to an array of `MachineMemOperand` pointers. This is null when
2539 // the number of these is zero, the single pointer variant used when the
2540 // number is one, and the array is used for larger numbers.
2541 //
2542 // The array is allocated via the `SelectionDAG`'s allocator and so will
2543 // always live until the DAG is cleaned up and doesn't require ownership here.
2544 //
2545 // We can't use something simpler like `TinyPtrVector` here because `SDNode`
2546 // subclasses aren't managed in a conforming C++ manner. See the comments on
2547 // `SelectionDAG::MorphNodeTo` which details what all goes on, but the
2548 // constraint here is that these don't manage memory with their constructor or
2549 // destructor and can be initialized to a good state even if they start off
2550 // uninitialized.
2551 PointerUnion<MachineMemOperand *, MachineMemOperand **> MemRefs = {};
2552
2553 // Note that this could be folded into the above `MemRefs` member if doing so
2554 // is advantageous at some point. We don't need to store this in most cases.
2555 // However, at the moment this doesn't appear to make the allocation any
2556 // smaller and makes the code somewhat simpler to read.
2557 int NumMemRefs = 0;
2558
2559public:
2560 using mmo_iterator = ArrayRef<MachineMemOperand *>::const_iterator;
2561
2562 ArrayRef<MachineMemOperand *> memoperands() const {
2563 // Special case the common cases.
2564 if (NumMemRefs == 0)
2565 return {};
2566 if (NumMemRefs == 1)
2567 return makeArrayRef(MemRefs.getAddrOfPtr1(), 1);
2568
2569 // Otherwise we have an actual array.
2570 return makeArrayRef(MemRefs.get<MachineMemOperand **>(), NumMemRefs);
2571 }
2572 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
2573 mmo_iterator memoperands_end() const { return memoperands().end(); }
2574 bool memoperands_empty() const { return memoperands().empty(); }
2575
2576 /// Clear out the memory reference descriptor list.
2577 void clearMemRefs() {
2578 MemRefs = nullptr;
2579 NumMemRefs = 0;
2580 }
2581
2582 static bool classof(const SDNode *N) {
2583 return N->isMachineOpcode();
2584 }
2585};
2586
2587/// An SDNode that records if a register contains a value that is guaranteed to
2588/// be aligned accordingly.
2589class AssertAlignSDNode : public SDNode {
2590 Align Alignment;
2591
2592public:
2593 AssertAlignSDNode(unsigned Order, const DebugLoc &DL, EVT VT, Align A)
2594 : SDNode(ISD::AssertAlign, Order, DL, getSDVTList(VT)), Alignment(A) {}
2595
2596 Align getAlign() const { return Alignment; }
2597
2598 static bool classof(const SDNode *N) {
2599 return N->getOpcode() == ISD::AssertAlign;
2600 }
2601};
2602
2603class SDNodeIterator {
2604 const SDNode *Node;
2605 unsigned Operand;
2606
2607 SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}
2608
2609public:
2610 using iterator_category = std::forward_iterator_tag;
2611 using value_type = SDNode;
2612 using difference_type = std::ptrdiff_t;
2613 using pointer = value_type *;
2614 using reference = value_type &;
2615
2616 bool operator==(const SDNodeIterator& x) const {
2617 return Operand == x.Operand;
2618 }
2619 bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }
2620
2621 pointer operator*() const {
2622 return Node->getOperand(Operand).getNode();
2623 }
2624 pointer operator->() const { return operator*(); }
2625
2626 SDNodeIterator& operator++() { // Preincrement
2627 ++Operand;
2628 return *this;
2629 }
2630 SDNodeIterator operator++(int) { // Postincrement
2631 SDNodeIterator tmp = *this; ++*this; return tmp;
2632 }
2633 size_t operator-(SDNodeIterator Other) const {
2634 assert(Node == Other.Node &&(static_cast <bool> (Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? void (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2635, __extension__ __PRETTY_FUNCTION__))
2635 "Cannot compare iterators of two different nodes!")(static_cast <bool> (Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? void (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-14~++20210828111110+16086d47c0d0/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2635, __extension__ __PRETTY_FUNCTION__))
;
2636 return Operand - Other.Operand;
2637 }
2638
2639 static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); }
2640 static SDNodeIterator end (const SDNode *N) {
2641 return SDNodeIterator(N, N->getNumOperands());
2642 }
2643
2644 unsigned getOperand() const { return Operand; }
2645 const SDNode *getNode() const { return Node; }
2646};
2647
2648template <> struct GraphTraits<SDNode*> {
2649 using NodeRef = SDNode *;
2650 using ChildIteratorType = SDNodeIterator;
2651
2652 static NodeRef getEntryNode(SDNode *N) { return N; }
2653
2654 static ChildIteratorType child_begin(NodeRef N) {
2655 return SDNodeIterator::begin(N);
2656 }
2657
2658 static ChildIteratorType child_end(NodeRef N) {
2659 return SDNodeIterator::end(N);
2660 }
2661};
2662
2663/// A representation of the largest SDNode, for use in sizeof().
2664///
2665/// This needs to be a union because the largest node differs on 32 bit systems
2666/// with 4 and 8 byte pointer alignment, respectively.
2667using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode,
2668 BlockAddressSDNode,
2669 GlobalAddressSDNode,
2670 PseudoProbeSDNode>;
2671
2672/// The SDNode class with the greatest alignment requirement.
2673using MostAlignedSDNode = GlobalAddressSDNode;
2674
2675namespace ISD {
2676
2677 /// Returns true if the specified node is a non-extending and unindexed load.
2678 inline bool isNormalLoad(const SDNode *N) {
2679 const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N);
2680 return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
2681 Ld->getAddressingMode() == ISD::UNINDEXED;
2682 }
2683
2684 /// Returns true if the specified node is a non-extending load.
2685 inline bool isNON_EXTLoad(const SDNode *N) {
2686 return isa<LoadSDNode>(N) &&
2687 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
2688 }
2689
2690 /// Returns true if the specified node is a EXTLOAD.
2691 inline bool isEXTLoad(const SDNode *N) {
2692 return isa<LoadSDNode>(N) &&
2693 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
2694 }
2695
2696 /// Returns true if the specified node is a SEXTLOAD.
2697 inline bool isSEXTLoad(const SDNode *N) {
2698 return isa<LoadSDNode>(N) &&
2699 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
2700 }
2701
2702 /// Returns true if the specified node is a ZEXTLOAD.
2703 inline bool isZEXTLoad(const SDNode *N) {
2704 return isa<LoadSDNode>(N) &&
2705 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
2706 }
2707
2708 /// Returns true if the specified node is an unindexed load.
2709 inline bool isUNINDEXEDLoad(const SDNode *N) {
2710 return isa<LoadSDNode>(N) &&
2711 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2712 }
2713
2714 /// Returns true if the specified node is a non-truncating
2715 /// and unindexed store.
2716 inline bool isNormalStore(const SDNode *N) {
2717 const StoreSDNode *St = dyn_cast<StoreSDNode>(N);
2718 return St && !St->isTruncatingStore() &&
2719 St->getAddressingMode() == ISD::UNINDEXED;
2720 }
2721
2722 /// Returns true if the specified node is an unindexed store.
2723 inline bool isUNINDEXEDStore(const SDNode *N) {
2724 return isa<StoreSDNode>(N) &&
2725 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2726 }
2727
2728 /// Attempt to match a unary predicate against a scalar/splat constant or
2729 /// every element of a constant BUILD_VECTOR.
2730 /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
2731 bool matchUnaryPredicate(SDValue Op,
2732 std::function<bool(ConstantSDNode *)> Match,
2733 bool AllowUndefs = false);
2734
2735 /// Attempt to match a binary predicate against a pair of scalar/splat
2736 /// constants or every element of a pair of constant BUILD_VECTORs.
2737 /// If AllowUndef is true, then UNDEF elements will pass nullptr to Match.
2738 /// If AllowTypeMismatch is true then RetType + ArgTypes don't need to match.
2739 bool matchBinaryPredicate(
2740 SDValue LHS, SDValue RHS,
2741 std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match,
2742 bool AllowUndefs = false, bool AllowTypeMismatch = false);
2743
2744 /// Returns true if the specified value is the overflow result from one
2745 /// of the overflow intrinsic nodes.
2746 inline bool isOverflowIntrOpRes(SDValue Op) {
2747 unsigned Opc = Op.getOpcode();
2748 return (Op.getResNo() == 1 &&
2749 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2750 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
2751 }
2752
2753} // end namespace ISD
2754
2755} // end namespace llvm
2756
2757#endif // LLVM_CODEGEN_SELECTIONDAGNODES_H