Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1154, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name LegalizeIntegerTypes.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/include -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-01-13-084841-49055-1 -x c++ /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/IR/DerivedTypes.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/KnownBits.h"
24#include "llvm/Support/raw_ostream.h"
25using namespace llvm;
26
27#define DEBUG_TYPE"legalize-types" "legalize-types"
28
29//===----------------------------------------------------------------------===//
30// Integer Result Promotion
31//===----------------------------------------------------------------------===//
32
33/// PromoteIntegerResult - This method is called when a result of a node is
34/// found to be in need of promotion to a larger type. At this point, the node
35/// may also have invalid operands or may have other results that need
36/// expansion, we just know that (at least) one result needs promotion.
37void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
39 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
40 SDValue Res = SDValue();
41
42 // See if the target wants to custom expand this node.
43 if (CustomLowerNode(N, N->getValueType(ResNo), true)) {
44 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Node has been custom expanded, done\n"
; } } while (false)
;
45 return;
46 }
47
48 switch (N->getOpcode()) {
49 default:
50#ifndef NDEBUG
51 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); dbgs() << "\n";
53#endif
54 llvm_unreachable("Do not know how to promote this operator!")::llvm::llvm_unreachable_internal("Do not know how to promote this operator!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 54)
;
55 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
56 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
58 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
60 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
61 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
62 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
63 case ISD::CTLZ_ZERO_UNDEF:
64 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
65 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
66 case ISD::CTTZ_ZERO_UNDEF:
67 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
68 case ISD::EXTRACT_VECTOR_ELT:
69 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
70 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
71 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
72 break;
73 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
74 break;
75 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
76 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
77 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
78 case ISD::STRICT_FSETCC:
79 case ISD::STRICT_FSETCCS:
80 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
81 case ISD::SMIN:
82 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
83 case ISD::UMIN:
84 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break;
85
86 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
87 case ISD::SIGN_EXTEND_INREG:
88 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
89 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
90 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
91 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
92 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
93 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
94
95 case ISD::EXTRACT_SUBVECTOR:
96 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
97 case ISD::VECTOR_SHUFFLE:
98 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
99 case ISD::INSERT_VECTOR_ELT:
100 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
101 case ISD::BUILD_VECTOR:
102 Res = PromoteIntRes_BUILD_VECTOR(N); break;
103 case ISD::SCALAR_TO_VECTOR:
104 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
105 case ISD::SPLAT_VECTOR:
106 Res = PromoteIntRes_SPLAT_VECTOR(N); break;
107 case ISD::CONCAT_VECTORS:
108 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
109
110 case ISD::ANY_EXTEND_VECTOR_INREG:
111 case ISD::SIGN_EXTEND_VECTOR_INREG:
112 case ISD::ZERO_EXTEND_VECTOR_INREG:
113 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
114
115 case ISD::SIGN_EXTEND:
116 case ISD::ZERO_EXTEND:
117 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
118
119 case ISD::STRICT_FP_TO_SINT:
120 case ISD::STRICT_FP_TO_UINT:
121 case ISD::FP_TO_SINT:
122 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
123
124 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
125
126 case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break;
127
128 case ISD::AND:
129 case ISD::OR:
130 case ISD::XOR:
131 case ISD::ADD:
132 case ISD::SUB:
133 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
134
135 case ISD::SDIV:
136 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
137
138 case ISD::UDIV:
139 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
140
141 case ISD::SADDO:
142 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
143 case ISD::UADDO:
144 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
145 case ISD::SMULO:
146 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
147
148 case ISD::ADDE:
149 case ISD::SUBE:
150 case ISD::ADDCARRY:
151 case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
152
153 case ISD::SADDSAT:
154 case ISD::UADDSAT:
155 case ISD::SSUBSAT:
156 case ISD::USUBSAT: Res = PromoteIntRes_ADDSUBSAT(N); break;
157
158 case ISD::SMULFIX:
159 case ISD::SMULFIXSAT:
160 case ISD::UMULFIX:
161 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
162
163 case ISD::SDIVFIX:
164 case ISD::UDIVFIX: Res = PromoteIntRes_DIVFIX(N); break;
165
166 case ISD::ABS: Res = PromoteIntRes_ABS(N); break;
167
168 case ISD::ATOMIC_LOAD:
169 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
170
171 case ISD::ATOMIC_LOAD_ADD:
172 case ISD::ATOMIC_LOAD_SUB:
173 case ISD::ATOMIC_LOAD_AND:
174 case ISD::ATOMIC_LOAD_CLR:
175 case ISD::ATOMIC_LOAD_OR:
176 case ISD::ATOMIC_LOAD_XOR:
177 case ISD::ATOMIC_LOAD_NAND:
178 case ISD::ATOMIC_LOAD_MIN:
179 case ISD::ATOMIC_LOAD_MAX:
180 case ISD::ATOMIC_LOAD_UMIN:
181 case ISD::ATOMIC_LOAD_UMAX:
182 case ISD::ATOMIC_SWAP:
183 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
184
185 case ISD::ATOMIC_CMP_SWAP:
186 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
187 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
188 break;
189
190 case ISD::VECREDUCE_ADD:
191 case ISD::VECREDUCE_MUL:
192 case ISD::VECREDUCE_AND:
193 case ISD::VECREDUCE_OR:
194 case ISD::VECREDUCE_XOR:
195 case ISD::VECREDUCE_SMAX:
196 case ISD::VECREDUCE_SMIN:
197 case ISD::VECREDUCE_UMAX:
198 case ISD::VECREDUCE_UMIN:
199 Res = PromoteIntRes_VECREDUCE(N);
200 break;
201 }
202
203 // If the result is null then the sub-method took care of registering it.
204 if (Res.getNode())
205 SetPromotedInteger(SDValue(N, ResNo), Res);
206}
207
208SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
209 unsigned ResNo) {
210 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
211 return GetPromotedInteger(Op);
212}
213
214SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
215 // Sign-extend the new bits, and continue the assertion.
216 SDValue Op = SExtPromotedInteger(N->getOperand(0));
217 return DAG.getNode(ISD::AssertSext, SDLoc(N),
218 Op.getValueType(), Op, N->getOperand(1));
219}
220
221SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
222 // Zero the new bits, and continue the assertion.
223 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
224 return DAG.getNode(ISD::AssertZext, SDLoc(N),
225 Op.getValueType(), Op, N->getOperand(1));
226}
227
228SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
229 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
230 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
231 N->getMemoryVT(), ResVT,
232 N->getChain(), N->getBasePtr(),
233 N->getMemOperand());
234 // Legalize the chain result - switch anything that used the old chain to
235 // use the new one.
236 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
237 return Res;
238}
239
240SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
241 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
242 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
243 N->getMemoryVT(),
244 N->getChain(), N->getBasePtr(),
245 Op2, N->getMemOperand());
246 // Legalize the chain result - switch anything that used the old chain to
247 // use the new one.
248 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
249 return Res;
250}
251
252SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
253 unsigned ResNo) {
254 if (ResNo == 1) {
255 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS)((N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS) ? static_cast
<void> (0) : __assert_fail ("N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 255, __PRETTY_FUNCTION__))
;
256 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
257 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
258
259 // Only use the result of getSetCCResultType if it is legal,
260 // otherwise just use the promoted result type (NVT).
261 if (!TLI.isTypeLegal(SVT))
262 SVT = NVT;
263
264 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
265 SDValue Res = DAG.getAtomicCmpSwap(
266 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
267 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
268 N->getMemOperand());
269 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
270 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
271 return Res.getValue(1);
272 }
273
274 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
275 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
276 SDVTList VTs =
277 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
278 SDValue Res = DAG.getAtomicCmpSwap(
279 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
280 N->getBasePtr(), Op2, Op3, N->getMemOperand());
281 // Update the use to N with the newly created Res.
282 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
283 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
284 return Res;
285}
286
287SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
288 SDValue InOp = N->getOperand(0);
289 EVT InVT = InOp.getValueType();
290 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
291 EVT OutVT = N->getValueType(0);
292 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
293 SDLoc dl(N);
294
295 switch (getTypeAction(InVT)) {
296 case TargetLowering::TypeLegal:
297 break;
298 case TargetLowering::TypePromoteInteger:
299 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
300 // The input promotes to the same size. Convert the promoted value.
301 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
302 break;
303 case TargetLowering::TypeSoftenFloat:
304 // Promote the integer operand by hand.
305 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
306 case TargetLowering::TypePromoteFloat: {
307 // Convert the promoted float by hand.
308 if (!NOutVT.isVector())
309 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
310 break;
311 }
312 case TargetLowering::TypeExpandInteger:
313 case TargetLowering::TypeExpandFloat:
314 break;
315 case TargetLowering::TypeScalarizeVector:
316 // Convert the element to an integer and promote it by hand.
317 if (!NOutVT.isVector())
318 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
319 BitConvertToInteger(GetScalarizedVector(InOp)));
320 break;
321 case TargetLowering::TypeSplitVector: {
322 if (!NOutVT.isVector()) {
323 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
324 // pieces of the input into integers and reassemble in the final type.
325 SDValue Lo, Hi;
326 GetSplitVector(N->getOperand(0), Lo, Hi);
327 Lo = BitConvertToInteger(Lo);
328 Hi = BitConvertToInteger(Hi);
329
330 if (DAG.getDataLayout().isBigEndian())
331 std::swap(Lo, Hi);
332
333 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
334 EVT::getIntegerVT(*DAG.getContext(),
335 NOutVT.getSizeInBits()),
336 JoinIntegers(Lo, Hi));
337 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
338 }
339 break;
340 }
341 case TargetLowering::TypeWidenVector:
342 // The input is widened to the same size. Convert to the widened value.
343 // Make sure that the outgoing value is not a vector, because this would
344 // make us bitcast between two vectors which are legalized in different ways.
345 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) {
346 SDValue Res =
347 DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
348
349 // For big endian targets we need to shift the casted value or the
350 // interesting bits will end up at the wrong place.
351 if (DAG.getDataLayout().isBigEndian()) {
352 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
353 EVT ShiftAmtTy = TLI.getShiftAmountTy(NOutVT, DAG.getDataLayout());
354 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!")((ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!"
) ? static_cast<void> (0) : __assert_fail ("ShiftAmt < NOutVT.getSizeInBits() && \"Too large shift amount!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 354, __PRETTY_FUNCTION__))
;
355 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res,
356 DAG.getConstant(ShiftAmt, dl, ShiftAmtTy));
357 }
358 return Res;
359 }
360 // If the output type is also a vector and widening it to the same size
361 // as the widened input type would be a legal type, we can widen the bitcast
362 // and handle the promotion after.
363 if (NOutVT.isVector()) {
364 unsigned WidenInSize = NInVT.getSizeInBits();
365 unsigned OutSize = OutVT.getSizeInBits();
366 if (WidenInSize % OutSize == 0) {
367 unsigned Scale = WidenInSize / OutSize;
368 EVT WideOutVT = EVT::getVectorVT(*DAG.getContext(),
369 OutVT.getVectorElementType(),
370 OutVT.getVectorNumElements() * Scale);
371 if (isTypeLegal(WideOutVT)) {
372 InOp = DAG.getBitcast(WideOutVT, GetWidenedVector(InOp));
373 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
374 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp,
375 DAG.getConstant(0, dl, IdxTy));
376 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp);
377 }
378 }
379 }
380 }
381
382 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
383 CreateStackStoreLoad(InOp, OutVT));
384}
385
386// Helper for BSWAP/BITREVERSE promotion to ensure we can fit any shift amount
387// in the VT returned by getShiftAmountTy and to return a safe VT if we can't.
388static EVT getShiftAmountTyForConstant(EVT VT, const TargetLowering &TLI,
389 SelectionDAG &DAG) {
390 EVT ShiftVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
391 // If any possible shift value won't fit in the prefered type, just use
392 // something safe. It will be legalized when the shift is expanded.
393 if (!ShiftVT.isVector() &&
394 ShiftVT.getSizeInBits() < Log2_32_Ceil(VT.getSizeInBits()))
395 ShiftVT = MVT::i32;
396 return ShiftVT;
397}
398
399SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
400 SDValue Op = GetPromotedInteger(N->getOperand(0));
401 EVT OVT = N->getValueType(0);
402 EVT NVT = Op.getValueType();
403 SDLoc dl(N);
404
405 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
406 EVT ShiftVT = getShiftAmountTyForConstant(NVT, TLI, DAG);
407 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
408 DAG.getConstant(DiffBits, dl, ShiftVT));
409}
410
411SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
412 SDValue Op = GetPromotedInteger(N->getOperand(0));
413 EVT OVT = N->getValueType(0);
414 EVT NVT = Op.getValueType();
415 SDLoc dl(N);
416
417 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
418 EVT ShiftVT = getShiftAmountTyForConstant(NVT, TLI, DAG);
419 return DAG.getNode(ISD::SRL, dl, NVT,
420 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
421 DAG.getConstant(DiffBits, dl, ShiftVT));
422}
423
424SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
425 // The pair element type may be legal, or may not promote to the same type as
426 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
427 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
428 TLI.getTypeToTransformTo(*DAG.getContext(),
429 N->getValueType(0)), JoinIntegers(N->getOperand(0),
430 N->getOperand(1)));
431}
432
433SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
434 EVT VT = N->getValueType(0);
435 // FIXME there is no actual debug info here
436 SDLoc dl(N);
437 // Zero extend things like i1, sign extend everything else. It shouldn't
438 // matter in theory which one we pick, but this tends to give better code?
439 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
440 SDValue Result = DAG.getNode(Opc, dl,
441 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
442 SDValue(N, 0));
443 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?")((isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(Result) && \"Didn't constant fold ext?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 443, __PRETTY_FUNCTION__))
;
444 return Result;
445}
446
447SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
448 // Zero extend to the promoted type and do the count there.
449 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
450 SDLoc dl(N);
451 EVT OVT = N->getValueType(0);
452 EVT NVT = Op.getValueType();
453 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
454 // Subtract off the extra leading bits in the bigger type.
455 return DAG.getNode(
456 ISD::SUB, dl, NVT, Op,
457 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
458 NVT));
459}
460
461SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
462 // Zero extend to the promoted type and do the count there.
463 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
464 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
465}
466
467SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
468 SDValue Op = GetPromotedInteger(N->getOperand(0));
469 EVT OVT = N->getValueType(0);
470 EVT NVT = Op.getValueType();
471 SDLoc dl(N);
472 if (N->getOpcode() == ISD::CTTZ) {
473 // The count is the same in the promoted type except if the original
474 // value was zero. This can be handled by setting the bit just off
475 // the top of the original type.
476 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
477 OVT.getScalarSizeInBits());
478 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
479 }
480 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
481}
482
483SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
484 SDLoc dl(N);
485 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
486
487 SDValue Op0 = N->getOperand(0);
488 SDValue Op1 = N->getOperand(1);
489
490 // If the input also needs to be promoted, do that first so we can get a
491 // get a good idea for the output type.
492 if (TLI.getTypeAction(*DAG.getContext(), Op0.getValueType())
493 == TargetLowering::TypePromoteInteger) {
494 SDValue In = GetPromotedInteger(Op0);
495
496 // If the new type is larger than NVT, use it. We probably won't need to
497 // promote it again.
498 EVT SVT = In.getValueType().getScalarType();
499 if (SVT.bitsGE(NVT)) {
500 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1);
501 return DAG.getAnyExtOrTrunc(Ext, dl, NVT);
502 }
503 }
504
505 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1);
506}
507
508SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
509 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
510 unsigned NewOpc = N->getOpcode();
511 SDLoc dl(N);
512
513 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
514 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
515 // and SINT conversions are Custom, there is no way to tell which is
516 // preferable. We choose SINT because that's the right thing on PPC.)
517 if (N->getOpcode() == ISD::FP_TO_UINT &&
518 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
519 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
520 NewOpc = ISD::FP_TO_SINT;
521
522 if (N->getOpcode() == ISD::STRICT_FP_TO_UINT &&
523 !TLI.isOperationLegal(ISD::STRICT_FP_TO_UINT, NVT) &&
524 TLI.isOperationLegalOrCustom(ISD::STRICT_FP_TO_SINT, NVT))
525 NewOpc = ISD::STRICT_FP_TO_SINT;
526
527 SDValue Res;
528 if (N->isStrictFPOpcode()) {
529 Res = DAG.getNode(NewOpc, dl, { NVT, MVT::Other },
530 { N->getOperand(0), N->getOperand(1) });
531 // Legalize the chain result - switch anything that used the old chain to
532 // use the new one.
533 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
534 } else
535 Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
536
537 // Assert that the converted value fits in the original type. If it doesn't
538 // (eg: because the value being converted is too big), then the result of the
539 // original operation was undefined anyway, so the assert is still correct.
540 //
541 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
542 // before legalization: fp-to-uint16, 65534. -> 0xfffe
543 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
544 return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
545 N->getOpcode() == ISD::STRICT_FP_TO_UINT) ?
546 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
547 DAG.getValueType(N->getValueType(0).getScalarType()));
548}
549
550SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
551 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
552 SDLoc dl(N);
553
554 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
555}
556
557SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) {
558 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
559 SDLoc dl(N);
560
561 return DAG.getNode(N->getOpcode(), dl, NVT);
562}
563
564SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
565 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
566 SDLoc dl(N);
567
568 if (getTypeAction(N->getOperand(0).getValueType())
569 == TargetLowering::TypePromoteInteger) {
570 SDValue Res = GetPromotedInteger(N->getOperand(0));
571 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!")((Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType().bitsLE(NVT) && \"Extension doesn't make sense!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 571, __PRETTY_FUNCTION__))
;
572
573 // If the result and operand types are the same after promotion, simplify
574 // to an in-register extension.
575 if (NVT == Res.getValueType()) {
576 // The high bits are not guaranteed to be anything. Insert an extend.
577 if (N->getOpcode() == ISD::SIGN_EXTEND)
578 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
579 DAG.getValueType(N->getOperand(0).getValueType()));
580 if (N->getOpcode() == ISD::ZERO_EXTEND)
581 return DAG.getZeroExtendInReg(Res, dl,
582 N->getOperand(0).getValueType().getScalarType());
583 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!")((N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::ANY_EXTEND && \"Unknown integer extension!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 583, __PRETTY_FUNCTION__))
;
584 return Res;
585 }
586 }
587
588 // Otherwise, just extend the original operand all the way to the larger type.
589 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
590}
591
592SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
593 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!")((ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDLoad(N) && \"Indexed load during type legalization!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 593, __PRETTY_FUNCTION__))
;
594 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
595 ISD::LoadExtType ExtType =
596 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
597 SDLoc dl(N);
598 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
599 N->getMemoryVT(), N->getMemOperand());
600
601 // Legalize the chain result - switch anything that used the old chain to
602 // use the new one.
603 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
604 return Res;
605}
606
607SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
608 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
609 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
610
611 SDLoc dl(N);
612 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
613 N->getOffset(), N->getMask(), ExtPassThru,
614 N->getMemoryVT(), N->getMemOperand(),
615 N->getAddressingMode(), ISD::EXTLOAD);
616 // Legalize the chain result - switch anything that used the old chain to
617 // use the new one.
618 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
619 return Res;
620}
621
622SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
623 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
624 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
625 assert(NVT == ExtPassThru.getValueType() &&((NVT == ExtPassThru.getValueType() && "Gather result type and the passThru argument type should be the same"
) ? static_cast<void> (0) : __assert_fail ("NVT == ExtPassThru.getValueType() && \"Gather result type and the passThru argument type should be the same\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 626, __PRETTY_FUNCTION__))
626 "Gather result type and the passThru argument type should be the same")((NVT == ExtPassThru.getValueType() && "Gather result type and the passThru argument type should be the same"
) ? static_cast<void> (0) : __assert_fail ("NVT == ExtPassThru.getValueType() && \"Gather result type and the passThru argument type should be the same\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 626, __PRETTY_FUNCTION__))
;
627
628 SDLoc dl(N);
629 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
630 N->getIndex(), N->getScale() };
631 SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
632 N->getMemoryVT(), dl, Ops,
633 N->getMemOperand(), N->getIndexType());
634 // Legalize the chain result - switch anything that used the old chain to
635 // use the new one.
636 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
637 return Res;
638}
639
640/// Promote the overflow flag of an overflowing arithmetic node.
641SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
642 // Change the return type of the boolean result while obeying
643 // getSetCCResultType.
644 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
645 EVT VT = N->getValueType(0);
646 EVT SVT = getSetCCResultType(VT);
647 SDValue Ops[3] = { N->getOperand(0), N->getOperand(1) };
648 unsigned NumOps = N->getNumOperands();
649 assert(NumOps <= 3 && "Too many operands")((NumOps <= 3 && "Too many operands") ? static_cast
<void> (0) : __assert_fail ("NumOps <= 3 && \"Too many operands\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 649, __PRETTY_FUNCTION__))
;
650 if (NumOps == 3)
651 Ops[2] = N->getOperand(2);
652
653 SDLoc dl(N);
654 SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT),
655 makeArrayRef(Ops, NumOps));
656
657 // Modified the sum result - switch anything that used the old sum to use
658 // the new one.
659 ReplaceValueWith(SDValue(N, 0), Res);
660
661 // Convert to the expected type.
662 return DAG.getBoolExtOrTrunc(Res.getValue(1), dl, NVT, VT);
663}
664
665SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSAT(SDNode *N) {
666 // If the promoted type is legal, we can convert this to:
667 // 1. ANY_EXTEND iN to iM
668 // 2. SHL by M-N
669 // 3. [US][ADD|SUB]SAT
670 // 4. L/ASHR by M-N
671 // Else it is more efficient to convert this to a min and a max
672 // operation in the higher precision arithmetic.
673 SDLoc dl(N);
674 SDValue Op1 = N->getOperand(0);
675 SDValue Op2 = N->getOperand(1);
676 unsigned OldBits = Op1.getScalarValueSizeInBits();
677
678 unsigned Opcode = N->getOpcode();
679
680 SDValue Op1Promoted, Op2Promoted;
681 if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
682 Op1Promoted = ZExtPromotedInteger(Op1);
683 Op2Promoted = ZExtPromotedInteger(Op2);
684 } else {
685 Op1Promoted = SExtPromotedInteger(Op1);
686 Op2Promoted = SExtPromotedInteger(Op2);
687 }
688 EVT PromotedType = Op1Promoted.getValueType();
689 unsigned NewBits = PromotedType.getScalarSizeInBits();
690
691 if (TLI.isOperationLegalOrCustom(Opcode, PromotedType)) {
692 unsigned ShiftOp;
693 switch (Opcode) {
694 case ISD::SADDSAT:
695 case ISD::SSUBSAT:
696 ShiftOp = ISD::SRA;
697 break;
698 case ISD::UADDSAT:
699 case ISD::USUBSAT:
700 ShiftOp = ISD::SRL;
701 break;
702 default:
703 llvm_unreachable("Expected opcode to be signed or unsigned saturation "::llvm::llvm_unreachable_internal("Expected opcode to be signed or unsigned saturation "
"addition or subtraction", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 704)
704 "addition or subtraction")::llvm::llvm_unreachable_internal("Expected opcode to be signed or unsigned saturation "
"addition or subtraction", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 704)
;
705 }
706
707 unsigned SHLAmount = NewBits - OldBits;
708 EVT SHVT = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
709 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT);
710 Op1Promoted =
711 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
712 Op2Promoted =
713 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
714
715 SDValue Result =
716 DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
717 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
718 } else {
719 if (Opcode == ISD::USUBSAT) {
720 SDValue Max =
721 DAG.getNode(ISD::UMAX, dl, PromotedType, Op1Promoted, Op2Promoted);
722 return DAG.getNode(ISD::SUB, dl, PromotedType, Max, Op2Promoted);
723 }
724
725 if (Opcode == ISD::UADDSAT) {
726 APInt MaxVal = APInt::getAllOnesValue(OldBits).zext(NewBits);
727 SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
728 SDValue Add =
729 DAG.getNode(ISD::ADD, dl, PromotedType, Op1Promoted, Op2Promoted);
730 return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
731 }
732
733 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
734 APInt MinVal = APInt::getSignedMinValue(OldBits).sext(NewBits);
735 APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
736 SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
737 SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
738 SDValue Result =
739 DAG.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
740 Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
741 Result = DAG.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
742 return Result;
743 }
744}
745
746SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
747 // Can just promote the operands then continue with operation.
748 SDLoc dl(N);
749 SDValue Op1Promoted, Op2Promoted;
750 bool Signed =
751 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
752 bool Saturating =
753 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
754 if (Signed) {
755 Op1Promoted = SExtPromotedInteger(N->getOperand(0));
756 Op2Promoted = SExtPromotedInteger(N->getOperand(1));
757 } else {
758 Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
759 Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
760 }
761 EVT OldType = N->getOperand(0).getValueType();
762 EVT PromotedType = Op1Promoted.getValueType();
763 unsigned DiffSize =
764 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
765
766 if (Saturating) {
767 // Promoting the operand and result values changes the saturation width,
768 // which is extends the values that we clamp to on saturation. This could be
769 // resolved by shifting one of the operands the same amount, which would
770 // also shift the result we compare against, then shifting back.
771 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
772 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
773 DAG.getConstant(DiffSize, dl, ShiftTy));
774 SDValue Result = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
775 Op2Promoted, N->getOperand(2));
776 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
777 return DAG.getNode(ShiftOp, dl, PromotedType, Result,
778 DAG.getConstant(DiffSize, dl, ShiftTy));
779 }
780 return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted,
781 N->getOperand(2));
782}
783
784static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
785 unsigned Scale, const TargetLowering &TLI,
786 SelectionDAG &DAG) {
787 EVT VT = LHS.getValueType();
788 bool Signed = N->getOpcode() == ISD::SDIVFIX;
789
790 SDLoc dl(N);
791 // See if we can perform the division in this type without widening.
792 if (SDValue V = TLI.expandFixedPointDiv(N->getOpcode(), dl, LHS, RHS, Scale,
793 DAG))
794 return V;
795
796 // If that didn't work, double the type width and try again. That must work,
797 // or something is wrong.
798 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(),
799 VT.getScalarSizeInBits() * 2);
800 if (Signed) {
801 LHS = DAG.getSExtOrTrunc(LHS, dl, WideVT);
802 RHS = DAG.getSExtOrTrunc(RHS, dl, WideVT);
803 } else {
804 LHS = DAG.getZExtOrTrunc(LHS, dl, WideVT);
805 RHS = DAG.getZExtOrTrunc(RHS, dl, WideVT);
806 }
807
808 // TODO: Saturation.
809
810 SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, LHS, RHS, Scale,
811 DAG);
812 assert(Res && "Expanding DIVFIX with wide type failed?")((Res && "Expanding DIVFIX with wide type failed?") ?
static_cast<void> (0) : __assert_fail ("Res && \"Expanding DIVFIX with wide type failed?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 812, __PRETTY_FUNCTION__))
;
813 return DAG.getZExtOrTrunc(Res, dl, VT);
814}
815
816SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
817 SDLoc dl(N);
818 SDValue Op1Promoted, Op2Promoted;
819 bool Signed = N->getOpcode() == ISD::SDIVFIX;
820 if (Signed) {
821 Op1Promoted = SExtPromotedInteger(N->getOperand(0));
822 Op2Promoted = SExtPromotedInteger(N->getOperand(1));
823 } else {
824 Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
825 Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
826 }
827 EVT PromotedType = Op1Promoted.getValueType();
828 unsigned Scale = N->getConstantOperandVal(2);
829
830 SDValue Res;
831 // If the type is already legal and the operation is legal in that type, we
832 // should not early expand.
833 if (TLI.isTypeLegal(PromotedType)) {
834 TargetLowering::LegalizeAction Action =
835 TLI.getFixedPointOperationAction(N->getOpcode(), PromotedType, Scale);
836 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom)
837 Res = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
838 Op2Promoted, N->getOperand(2));
839 }
840
841 if (!Res)
842 Res = earlyExpandDIVFIX(N, Op1Promoted, Op2Promoted, Scale, TLI, DAG);
843
844 // TODO: Saturation.
845
846 return Res;
847}
848
849SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
850 if (ResNo == 1)
851 return PromoteIntRes_Overflow(N);
852
853 // The operation overflowed iff the result in the larger type is not the
854 // sign extension of its truncation to the original type.
855 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
856 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
857 EVT OVT = N->getOperand(0).getValueType();
858 EVT NVT = LHS.getValueType();
859 SDLoc dl(N);
860
861 // Do the arithmetic in the larger type.
862 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
863 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
864
865 // Calculate the overflow flag: sign extend the arithmetic result from
866 // the original type.
867 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
868 DAG.getValueType(OVT));
869 // Overflowed if and only if this is not equal to Res.
870 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
871
872 // Use the calculated overflow everywhere.
873 ReplaceValueWith(SDValue(N, 1), Ofl);
874
875 return Res;
876}
877
878SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
879 SDValue LHS = GetPromotedInteger(N->getOperand(1));
880 SDValue RHS = GetPromotedInteger(N->getOperand(2));
881 return DAG.getSelect(SDLoc(N),
882 LHS.getValueType(), N->getOperand(0), LHS, RHS);
883}
884
885SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
886 SDValue Mask = N->getOperand(0);
887
888 SDValue LHS = GetPromotedInteger(N->getOperand(1));
889 SDValue RHS = GetPromotedInteger(N->getOperand(2));
890 return DAG.getNode(ISD::VSELECT, SDLoc(N),
891 LHS.getValueType(), Mask, LHS, RHS);
892}
893
894SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
895 SDValue LHS = GetPromotedInteger(N->getOperand(2));
896 SDValue RHS = GetPromotedInteger(N->getOperand(3));
897 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
898 LHS.getValueType(), N->getOperand(0),
899 N->getOperand(1), LHS, RHS, N->getOperand(4));
900}
901
902SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
903 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
904 EVT InVT = N->getOperand(OpNo).getValueType();
905 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
906
907 EVT SVT = getSetCCResultType(InVT);
908
909 // If we got back a type that needs to be promoted, this likely means the
910 // the input type also needs to be promoted. So get the promoted type for
911 // the input and try the query again.
912 if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) {
913 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
914 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
915 SVT = getSetCCResultType(InVT);
916 } else {
917 // Input type isn't promoted, just use the default promoted type.
918 SVT = NVT;
919 }
920 }
921
922 SDLoc dl(N);
923 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&((SVT.isVector() == N->getOperand(OpNo).getValueType().isVector
() && "Vector compare must return a vector result!") ?
static_cast<void> (0) : __assert_fail ("SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() && \"Vector compare must return a vector result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 924, __PRETTY_FUNCTION__))
924 "Vector compare must return a vector result!")((SVT.isVector() == N->getOperand(OpNo).getValueType().isVector
() && "Vector compare must return a vector result!") ?
static_cast<void> (0) : __assert_fail ("SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() && \"Vector compare must return a vector result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 924, __PRETTY_FUNCTION__))
;
925
926 // Get the SETCC result using the canonical SETCC type.
927 SDValue SetCC;
928 if (N->isStrictFPOpcode()) {
929 EVT VTs[] = {SVT, MVT::Other};
930 SDValue Opers[] = {N->getOperand(0), N->getOperand(1),
931 N->getOperand(2), N->getOperand(3)};
932 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers);
933 // Legalize the chain result - switch anything that used the old chain to
934 // use the new one.
935 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1));
936 } else
937 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
938 N->getOperand(1), N->getOperand(2));
939
940 // Convert to the expected type.
941 return DAG.getSExtOrTrunc(SetCC, dl, NVT);
942}
943
944SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
945 SDValue LHS = GetPromotedInteger(N->getOperand(0));
946 SDValue RHS = N->getOperand(1);
947 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
948 RHS = ZExtPromotedInteger(RHS);
949 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
950}
951
952SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
953 SDValue Op = GetPromotedInteger(N->getOperand(0));
954 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
955 Op.getValueType(), Op, N->getOperand(1));
956}
957
958SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
959 // The input may have strange things in the top bits of the registers, but
960 // these operations don't care. They may have weird bits going out, but
961 // that too is okay if they are integer operations.
962 SDValue LHS = GetPromotedInteger(N->getOperand(0));
963 SDValue RHS = GetPromotedInteger(N->getOperand(1));
964 return DAG.getNode(N->getOpcode(), SDLoc(N),
965 LHS.getValueType(), LHS, RHS);
966}
967
968SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
969 // Sign extend the input.
970 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
971 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
972 return DAG.getNode(N->getOpcode(), SDLoc(N),
973 LHS.getValueType(), LHS, RHS);
974}
975
976SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
977 // Zero extend the input.
978 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
979 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
980 return DAG.getNode(N->getOpcode(), SDLoc(N),
981 LHS.getValueType(), LHS, RHS);
982}
983
984SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
985 // The input value must be properly sign extended.
986 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
987 SDValue RHS = N->getOperand(1);
988 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
989 RHS = ZExtPromotedInteger(RHS);
990 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
991}
992
993SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
994 // The input value must be properly zero extended.
995 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
996 SDValue RHS = N->getOperand(1);
997 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
998 RHS = ZExtPromotedInteger(RHS);
999 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
1000}
1001
1002SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1003 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1004 SDValue Res;
1005 SDValue InOp = N->getOperand(0);
1006 SDLoc dl(N);
1007
1008 switch (getTypeAction(InOp.getValueType())) {
1009 default: llvm_unreachable("Unknown type action!")::llvm::llvm_unreachable_internal("Unknown type action!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1009)
;
1010 case TargetLowering::TypeLegal:
1011 case TargetLowering::TypeExpandInteger:
1012 Res = InOp;
1013 break;
1014 case TargetLowering::TypePromoteInteger:
1015 Res = GetPromotedInteger(InOp);
1016 break;
1017 case TargetLowering::TypeSplitVector: {
1018 EVT InVT = InOp.getValueType();
1019 assert(InVT.isVector() && "Cannot split scalar types")((InVT.isVector() && "Cannot split scalar types") ? static_cast
<void> (0) : __assert_fail ("InVT.isVector() && \"Cannot split scalar types\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1019, __PRETTY_FUNCTION__))
;
1020 unsigned NumElts = InVT.getVectorNumElements();
1021 assert(NumElts == NVT.getVectorNumElements() &&((NumElts == NVT.getVectorNumElements() && "Dst and Src must have the same number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElts == NVT.getVectorNumElements() && \"Dst and Src must have the same number of elements\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1022, __PRETTY_FUNCTION__))
1022 "Dst and Src must have the same number of elements")((NumElts == NVT.getVectorNumElements() && "Dst and Src must have the same number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElts == NVT.getVectorNumElements() && \"Dst and Src must have the same number of elements\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1022, __PRETTY_FUNCTION__))
;
1023 assert(isPowerOf2_32(NumElts) &&((isPowerOf2_32(NumElts) && "Promoted vector type must be a power of two"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumElts) && \"Promoted vector type must be a power of two\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1024, __PRETTY_FUNCTION__))
1024 "Promoted vector type must be a power of two")((isPowerOf2_32(NumElts) && "Promoted vector type must be a power of two"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumElts) && \"Promoted vector type must be a power of two\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1024, __PRETTY_FUNCTION__))
;
1025
1026 SDValue EOp1, EOp2;
1027 GetSplitVector(InOp, EOp1, EOp2);
1028
1029 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
1030 NumElts/2);
1031 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
1032 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
1033
1034 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
1035 }
1036 case TargetLowering::TypeWidenVector: {
1037 SDValue WideInOp = GetWidenedVector(InOp);
1038
1039 // Truncate widened InOp.
1040 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1041 EVT TruncVT = EVT::getVectorVT(*DAG.getContext(),
1042 N->getValueType(0).getScalarType(), NumElem);
1043 SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp);
1044
1045 // Zero extend so that the elements are of same type as those of NVT
1046 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(),
1047 NumElem);
1048 SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
1049
1050 // Extract the low NVT subvector.
1051 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
1052 SDValue ZeroIdx = DAG.getConstant(0, dl, IdxTy);
1053 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
1054 }
1055 }
1056
1057 // Truncate to NVT instead of VT
1058 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
1059}
1060
1061SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1062 if (ResNo == 1)
1063 return PromoteIntRes_Overflow(N);
1064
1065 // The operation overflowed iff the result in the larger type is not the
1066 // zero extension of its truncation to the original type.
1067 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1068 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1069 EVT OVT = N->getOperand(0).getValueType();
1070 EVT NVT = LHS.getValueType();
1071 SDLoc dl(N);
1072
1073 // Do the arithmetic in the larger type.
1074 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1075 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
1076
1077 // Calculate the overflow flag: zero extend the arithmetic result from
1078 // the original type.
1079 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT.getScalarType());
1080 // Overflowed if and only if this is not equal to Res.
1081 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
1082
1083 // Use the calculated overflow everywhere.
1084 ReplaceValueWith(SDValue(N, 1), Ofl);
1085
1086 return Res;
1087}
1088
1089// Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
1090// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1091// the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
1092SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
1093 if (ResNo == 1)
1094 return PromoteIntRes_Overflow(N);
1095
1096 // We need to sign-extend the operands so the carry value computed by the
1097 // wide operation will be equivalent to the carry value computed by the
1098 // narrow operation.
1099 // An ADDCARRY can generate carry only if any of the operands has its
1100 // most significant bit set. Sign extension propagates the most significant
1101 // bit into the higher bits which means the extra bit that the narrow
1102 // addition would need (i.e. the carry) will be propagated through the higher
1103 // bits of the wide addition.
1104 // A SUBCARRY can generate borrow only if LHS < RHS and this property will be
1105 // preserved by sign extension.
1106 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1107 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1108
1109 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)};
1110
1111 // Do the arithmetic in the wide type.
1112 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
1113 LHS, RHS, N->getOperand(2));
1114
1115 // Update the users of the original carry/borrow value.
1116 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
1117
1118 return SDValue(Res.getNode(), 0);
1119}
1120
1121SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1122 SDValue Op0 = SExtPromotedInteger(N->getOperand(0));
1123 return DAG.getNode(ISD::ABS, SDLoc(N), Op0.getValueType(), Op0);
1124}
1125
1126SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1127 // Promote the overflow bit trivially.
1128 if (ResNo == 1)
1129 return PromoteIntRes_Overflow(N);
1130
1131 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
1132 SDLoc DL(N);
1133 EVT SmallVT = LHS.getValueType();
1134
1135 // To determine if the result overflowed in a larger type, we extend the
1136 // input to the larger type, do the multiply (checking if it overflows),
1137 // then also check the high bits of the result to see if overflow happened
1138 // there.
1139 if (N->getOpcode() == ISD::SMULO) {
1140 LHS = SExtPromotedInteger(LHS);
1141 RHS = SExtPromotedInteger(RHS);
1142 } else {
1143 LHS = ZExtPromotedInteger(LHS);
1144 RHS = ZExtPromotedInteger(RHS);
1145 }
1146 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
1147 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
1148
1149 // Overflow occurred if it occurred in the larger type, or if the high part
1150 // of the result does not zero/sign-extend the low part. Check this second
1151 // possibility first.
1152 SDValue Overflow;
1153 if (N->getOpcode() == ISD::UMULO) {
1154 // Unsigned overflow occurred if the high part is non-zero.
1155 unsigned Shift = SmallVT.getScalarSizeInBits();
1156 EVT ShiftTy = getShiftAmountTyForConstant(Mul.getValueType(), TLI, DAG);
1157 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
1158 DAG.getConstant(Shift, DL, ShiftTy));
1159 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
1160 DAG.getConstant(0, DL, Hi.getValueType()),
1161 ISD::SETNE);
1162 } else {
1163 // Signed overflow occurred if the high part does not sign extend the low.
1164 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
1165 Mul, DAG.getValueType(SmallVT));
1166 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
1167 }
1168
1169 // The only other way for overflow to occur is if the multiplication in the
1170 // larger type itself overflowed.
1171 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
1172 SDValue(Mul.getNode(), 1));
1173
1174 // Use the calculated overflow everywhere.
1175 ReplaceValueWith(SDValue(N, 1), Overflow);
1176 return Mul;
1177}
1178
1179SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1180 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
1181 N->getValueType(0)));
1182}
1183
1184SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1185 SDValue Chain = N->getOperand(0); // Get the chain.
1186 SDValue Ptr = N->getOperand(1); // Get the pointer.
1187 EVT VT = N->getValueType(0);
1188 SDLoc dl(N);
1189
1190 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
1191 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
1192 // The argument is passed as NumRegs registers of type RegVT.
1193
1194 SmallVector<SDValue, 8> Parts(NumRegs);
1195 for (unsigned i = 0; i < NumRegs; ++i) {
1196 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
1197 N->getConstantOperandVal(3));
1198 Chain = Parts[i].getValue(1);
1199 }
1200
1201 // Handle endianness of the load.
1202 if (DAG.getDataLayout().isBigEndian())
1203 std::reverse(Parts.begin(), Parts.end());
1204
1205 // Assemble the parts in the promoted type.
1206 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1207 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
1208 for (unsigned i = 1; i < NumRegs; ++i) {
1209 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
1210 // Shift it to the right position and "or" it in.
1211 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1212 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
1213 TLI.getPointerTy(DAG.getDataLayout())));
1214 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
1215 }
1216
1217 // Modified the chain result - switch anything that used the old chain to
1218 // use the new one.
1219 ReplaceValueWith(SDValue(N, 1), Chain);
1220
1221 return Res;
1222}
1223
1224//===----------------------------------------------------------------------===//
1225// Integer Operand Promotion
1226//===----------------------------------------------------------------------===//
1227
1228/// PromoteIntegerOperand - This method is called when the specified operand of
1229/// the specified node is found to need promotion. At this point, all of the
1230/// result types of the node are known to be legal, but other operands of the
1231/// node may need promotion or expansion as well as the specified one.
1232bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1233 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1234 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1235 SDValue Res = SDValue();
1236
1237 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
1238 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Node has been custom lowered, done\n"
; } } while (false)
;
1239 return false;
1240 }
1241
1242 switch (N->getOpcode()) {
1243 default:
1244 #ifndef NDEBUG
1245 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
1246 N->dump(&DAG); dbgs() << "\n";
1247 #endif
1248 llvm_unreachable("Do not know how to promote this operator's operand!")::llvm::llvm_unreachable_internal("Do not know how to promote this operator's operand!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1248)
;
1249
1250 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
1251 case ISD::ATOMIC_STORE:
1252 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
1253 break;
1254 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
1255 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1256 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
1257 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
1258 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
1259 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
1260 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
1261 case ISD::INSERT_VECTOR_ELT:
1262 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
1263 case ISD::SCALAR_TO_VECTOR:
1264 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
1265 case ISD::SPLAT_VECTOR:
1266 Res = PromoteIntOp_SPLAT_VECTOR(N); break;
1267 case ISD::VSELECT:
1268 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1269 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
1270 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
1271 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1272 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
1273 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
1274 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
1275 OpNo); break;
1276 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
1277 OpNo); break;
1278 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
1279 OpNo); break;
1280 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
1281 OpNo); break;
1282 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
1283 OpNo); break;
1284 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
1285 case ISD::FP16_TO_FP:
1286 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
1287 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
1288 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
1289 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
1290
1291 case ISD::SHL:
1292 case ISD::SRA:
1293 case ISD::SRL:
1294 case ISD::ROTL:
1295 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
1296
1297 case ISD::ADDCARRY:
1298 case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
1299
1300 case ISD::FRAMEADDR:
1301 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
1302
1303 case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break;
1304
1305 case ISD::SMULFIX:
1306 case ISD::SMULFIXSAT:
1307 case ISD::UMULFIX:
1308 case ISD::UMULFIXSAT:
1309 case ISD::SDIVFIX:
1310 case ISD::UDIVFIX: Res = PromoteIntOp_FIX(N); break;
1311
1312 case ISD::FPOWI: Res = PromoteIntOp_FPOWI(N); break;
1313
1314 case ISD::VECREDUCE_ADD:
1315 case ISD::VECREDUCE_MUL:
1316 case ISD::VECREDUCE_AND:
1317 case ISD::VECREDUCE_OR:
1318 case ISD::VECREDUCE_XOR:
1319 case ISD::VECREDUCE_SMAX:
1320 case ISD::VECREDUCE_SMIN:
1321 case ISD::VECREDUCE_UMAX:
1322 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
1323 }
1324
1325 // If the result is null, the sub-method took care of registering results etc.
1326 if (!Res.getNode()) return false;
1327
1328 // If the result is N, the sub-method updated N in place. Tell the legalizer
1329 // core about this.
1330 if (Res.getNode() == N)
1331 return true;
1332
1333 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1334, __PRETTY_FUNCTION__))
1334 "Invalid operand expansion")((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1334, __PRETTY_FUNCTION__))
;
1335
1336 ReplaceValueWith(SDValue(N, 0), Res);
1337 return false;
1338}
1339
1340/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1341/// shared among BR_CC, SELECT_CC, and SETCC handlers.
1342void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
1343 ISD::CondCode CCCode) {
1344 // We have to insert explicit sign or zero extends. Note that we could
1345 // insert sign extends for ALL conditions. For those operations where either
1346 // zero or sign extension would be valid, use SExtOrZExtPromotedInteger
1347 // which will choose the cheapest for the target.
1348 switch (CCCode) {
1349 default: llvm_unreachable("Unknown integer comparison!")::llvm::llvm_unreachable_internal("Unknown integer comparison!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1349)
;
1350 case ISD::SETEQ:
1351 case ISD::SETNE: {
1352 SDValue OpL = GetPromotedInteger(NewLHS);
1353 SDValue OpR = GetPromotedInteger(NewRHS);
1354
1355 // We would prefer to promote the comparison operand with sign extension.
1356 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
1357 // than the width of NewLHS/NewRH, we can avoid inserting real truncate
1358 // instruction, which is redundant eventually.
1359 unsigned OpLEffectiveBits =
1360 OpL.getScalarValueSizeInBits() - DAG.ComputeNumSignBits(OpL) + 1;
1361 unsigned OpREffectiveBits =
1362 OpR.getScalarValueSizeInBits() - DAG.ComputeNumSignBits(OpR) + 1;
1363 if (OpLEffectiveBits <= NewLHS.getScalarValueSizeInBits() &&
1364 OpREffectiveBits <= NewRHS.getScalarValueSizeInBits()) {
1365 NewLHS = OpL;
1366 NewRHS = OpR;
1367 } else {
1368 NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1369 NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1370 }
1371 break;
1372 }
1373 case ISD::SETUGE:
1374 case ISD::SETUGT:
1375 case ISD::SETULE:
1376 case ISD::SETULT:
1377 NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1378 NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1379 break;
1380 case ISD::SETGE:
1381 case ISD::SETGT:
1382 case ISD::SETLT:
1383 case ISD::SETLE:
1384 NewLHS = SExtPromotedInteger(NewLHS);
1385 NewRHS = SExtPromotedInteger(NewRHS);
1386 break;
1387 }
1388}
1389
1390SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
1391 SDValue Op = GetPromotedInteger(N->getOperand(0));
1392 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
1393}
1394
1395SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
1396 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
1397 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
1398 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand());
1399}
1400
1401SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1402 // This should only occur in unusual situations like bitcasting to an
1403 // x86_fp80, so just turn it into a store+load
1404 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1405}
1406
1407SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1408 assert(OpNo == 2 && "Don't know how to promote this operand!")((OpNo == 2 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 2 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1408, __PRETTY_FUNCTION__))
;
1409
1410 SDValue LHS = N->getOperand(2);
1411 SDValue RHS = N->getOperand(3);
1412 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1413
1414 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1415 // legal types.
1416 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1417 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1418 0);
1419}
1420
1421SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1422 assert(OpNo == 1 && "only know how to promote condition")((OpNo == 1 && "only know how to promote condition") ?
static_cast<void> (0) : __assert_fail ("OpNo == 1 && \"only know how to promote condition\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1422, __PRETTY_FUNCTION__))
;
1423
1424 // Promote all the way up to the canonical SetCC type.
1425 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1426
1427 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1428 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1429 N->getOperand(2)), 0);
1430}
1431
1432SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1433 // Since the result type is legal, the operands must promote to it.
1434 EVT OVT = N->getOperand(0).getValueType();
1435 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1436 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1437 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?")((Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Lo.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1437, __PRETTY_FUNCTION__))
;
1438 SDLoc dl(N);
1439
1440 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1441 DAG.getConstant(OVT.getSizeInBits(), dl,
1442 TLI.getPointerTy(DAG.getDataLayout())));
1443 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1444}
1445
1446SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1447 // The vector type is legal but the element type is not. This implies
1448 // that the vector is a power-of-two in length and that the element
1449 // type does not have a strange size (eg: it is not i1).
1450 EVT VecVT = N->getValueType(0);
1451 unsigned NumElts = VecVT.getVectorNumElements();
1452 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&((!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
"Legal vector of one illegal element?") ? static_cast<void
> (0) : __assert_fail ("!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && \"Legal vector of one illegal element?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1453, __PRETTY_FUNCTION__))
1453 "Legal vector of one illegal element?")((!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
"Legal vector of one illegal element?") ? static_cast<void
> (0) : __assert_fail ("!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && \"Legal vector of one illegal element?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1453, __PRETTY_FUNCTION__))
;
1454
1455 // Promote the inserted value. The type does not need to match the
1456 // vector element type. Check that any extra bits introduced will be
1457 // truncated away.
1458 assert(N->getOperand(0).getValueSizeInBits() >=((N->getOperand(0).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1460, __PRETTY_FUNCTION__))
1459 N->getValueType(0).getScalarSizeInBits() &&((N->getOperand(0).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1460, __PRETTY_FUNCTION__))
1460 "Type of inserted value narrower than vector element type!")((N->getOperand(0).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1460, __PRETTY_FUNCTION__))
;
1461
1462 SmallVector<SDValue, 16> NewOps;
1463 for (unsigned i = 0; i < NumElts; ++i)
1464 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1465
1466 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1467}
1468
1469SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1470 unsigned OpNo) {
1471 if (OpNo == 1) {
1472 // Promote the inserted value. This is valid because the type does not
1473 // have to match the vector element type.
1474
1475 // Check that any extra bits introduced will be truncated away.
1476 assert(N->getOperand(1).getValueSizeInBits() >=((N->getOperand(1).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1478, __PRETTY_FUNCTION__))
1477 N->getValueType(0).getScalarSizeInBits() &&((N->getOperand(1).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1478, __PRETTY_FUNCTION__))
1478 "Type of inserted value narrower than vector element type!")((N->getOperand(1).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1478, __PRETTY_FUNCTION__))
;
1479 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1480 GetPromotedInteger(N->getOperand(1)),
1481 N->getOperand(2)),
1482 0);
1483 }
1484
1485 assert(OpNo == 2 && "Different operand and result vector types?")((OpNo == 2 && "Different operand and result vector types?"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 2 && \"Different operand and result vector types?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1485, __PRETTY_FUNCTION__))
;
1486
1487 // Promote the index.
1488 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1489 TLI.getVectorIdxTy(DAG.getDataLayout()));
1490 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1491 N->getOperand(1), Idx), 0);
1492}
1493
1494SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1495 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1496 // the operand in place.
1497 return SDValue(DAG.UpdateNodeOperands(N,
1498 GetPromotedInteger(N->getOperand(0))), 0);
1499}
1500
1501SDValue DAGTypeLegalizer::PromoteIntOp_SPLAT_VECTOR(SDNode *N) {
1502 // Integer SPLAT_VECTOR operands are implicitly truncated, so just promote the
1503 // operand in place.
1504 return SDValue(
1505 DAG.UpdateNodeOperands(N, GetPromotedInteger(N->getOperand(0))), 0);
1506}
1507
1508SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1509 assert(OpNo == 0 && "Only know how to promote the condition!")((OpNo == 0 && "Only know how to promote the condition!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 0 && \"Only know how to promote the condition!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1509, __PRETTY_FUNCTION__))
;
1510 SDValue Cond = N->getOperand(0);
1511 EVT OpTy = N->getOperand(1).getValueType();
1512
1513 if (N->getOpcode() == ISD::VSELECT)
1514 if (SDValue Res = WidenVSELECTAndMask(N))
1515 return Res;
1516
1517 // Promote all the way up to the canonical SetCC type.
1518 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1519 Cond = PromoteTargetBoolean(Cond, OpVT);
1520
1521 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1522 N->getOperand(2)), 0);
1523}
1524
1525SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1526 assert(OpNo == 0 && "Don't know how to promote this operand!")((OpNo == 0 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 0 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1526, __PRETTY_FUNCTION__))
;
1527
1528 SDValue LHS = N->getOperand(0);
1529 SDValue RHS = N->getOperand(1);
1530 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1531
1532 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1533 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1534 N->getOperand(3), N->getOperand(4)), 0);
1535}
1536
1537SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1538 assert(OpNo == 0 && "Don't know how to promote this operand!")((OpNo == 0 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 0 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1538, __PRETTY_FUNCTION__))
;
1539
1540 SDValue LHS = N->getOperand(0);
1541 SDValue RHS = N->getOperand(1);
1542 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1543
1544 // The CC (#2) is always legal.
1545 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1546}
1547
1548SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1549 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1550 ZExtPromotedInteger(N->getOperand(1))), 0);
1551}
1552
1553SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1554 SDValue Op = GetPromotedInteger(N->getOperand(0));
1555 SDLoc dl(N);
1556 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1557 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1558 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1559}
1560
1561SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1562 return SDValue(DAG.UpdateNodeOperands(N,
1563 SExtPromotedInteger(N->getOperand(0))), 0);
1564}
1565
1566SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
1567 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1568 SExtPromotedInteger(N->getOperand(1))), 0);
1569}
1570
1571SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1572 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!")((ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDStore(N) && \"Indexed store during type legalization!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1572, __PRETTY_FUNCTION__))
;
1573 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1574 SDLoc dl(N);
1575
1576 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1577
1578 // Truncate the value and store the result.
1579 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1580 N->getMemoryVT(), N->getMemOperand());
1581}
1582
1583SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
1584 unsigned OpNo) {
1585
1586 SDValue DataOp = N->getValue();
1587 EVT DataVT = DataOp.getValueType();
1588 SDValue Mask = N->getMask();
1589 SDLoc dl(N);
1590
1591 bool TruncateStore = false;
1592 if (OpNo == 4) {
1593 Mask = PromoteTargetBoolean(Mask, DataVT);
1594 // Update in place.
1595 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1596 NewOps[4] = Mask;
1597 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1598 } else { // Data operand
1599 assert(OpNo == 1 && "Unexpected operand for promotion")((OpNo == 1 && "Unexpected operand for promotion") ? static_cast
<void> (0) : __assert_fail ("OpNo == 1 && \"Unexpected operand for promotion\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1599, __PRETTY_FUNCTION__))
;
1600 DataOp = GetPromotedInteger(DataOp);
1601 TruncateStore = true;
1602 }
1603
1604 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(),
1605 N->getOffset(), Mask, N->getMemoryVT(),
1606 N->getMemOperand(), N->getAddressingMode(),
1607 TruncateStore, N->isCompressingStore());
1608}
1609
1610SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
1611 unsigned OpNo) {
1612 assert(OpNo == 3 && "Only know how to promote the mask!")((OpNo == 3 && "Only know how to promote the mask!") ?
static_cast<void> (0) : __assert_fail ("OpNo == 3 && \"Only know how to promote the mask!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1612, __PRETTY_FUNCTION__))
;
1613 EVT DataVT = N->getValueType(0);
1614 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1615 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1616 NewOps[OpNo] = Mask;
1617 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1618}
1619
1620SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
1621 unsigned OpNo) {
1622
1623 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1624 if (OpNo == 2) {
1625 // The Mask
1626 EVT DataVT = N->getValueType(0);
1627 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1628 } else if (OpNo == 4) {
1629 // The Index
1630 if (N->isIndexSigned())
1631 // Need to sign extend the index since the bits will likely be used.
1632 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1633 else
1634 NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
1635 } else
1636 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1637
1638 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1639}
1640
1641SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
1642 unsigned OpNo) {
1643 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1644 if (OpNo == 2) {
1645 // The Mask
1646 EVT DataVT = N->getValue().getValueType();
1647 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1648 } else if (OpNo == 4) {
1649 // The Index
1650 if (N->isIndexSigned())
1651 // Need to sign extend the index since the bits will likely be used.
1652 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1653 else
1654 NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
1655 } else
1656 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1657 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1658}
1659
1660SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1661 SDValue Op = GetPromotedInteger(N->getOperand(0));
1662 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1663}
1664
1665SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1666 return SDValue(DAG.UpdateNodeOperands(N,
1667 ZExtPromotedInteger(N->getOperand(0))), 0);
1668}
1669
1670SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
1671 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1672 ZExtPromotedInteger(N->getOperand(1))), 0);
1673}
1674
1675SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1676 SDLoc dl(N);
1677 SDValue Op = GetPromotedInteger(N->getOperand(0));
1678 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1679 return DAG.getZeroExtendInReg(Op, dl,
1680 N->getOperand(0).getValueType().getScalarType());
1681}
1682
1683SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) {
1684 assert(OpNo == 2 && "Don't know how to promote this operand!")((OpNo == 2 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 2 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1684, __PRETTY_FUNCTION__))
;
1685
1686 SDValue LHS = N->getOperand(0);
1687 SDValue RHS = N->getOperand(1);
1688 SDValue Carry = N->getOperand(2);
1689 SDLoc DL(N);
1690
1691 Carry = PromoteTargetBoolean(Carry, LHS.getValueType());
1692
1693 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, Carry), 0);
1694}
1695
1696SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
1697 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
1698 return SDValue(
1699 DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0);
1700}
1701
1702SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
1703 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
1704 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
1705 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
1706}
1707
1708SDValue DAGTypeLegalizer::PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo) {
1709 assert(OpNo > 1 && "Don't know how to promote this operand!")((OpNo > 1 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo > 1 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1709, __PRETTY_FUNCTION__))
;
1710 // Promote the rw, locality, and cache type arguments to a supported integer
1711 // width.
1712 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
1713 SDValue Op3 = ZExtPromotedInteger(N->getOperand(3));
1714 SDValue Op4 = ZExtPromotedInteger(N->getOperand(4));
1715 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
1716 Op2, Op3, Op4),
1717 0);
1718}
1719
1720SDValue DAGTypeLegalizer::PromoteIntOp_FPOWI(SDNode *N) {
1721 SDValue Op = SExtPromotedInteger(N->getOperand(1));
1722 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op), 0);
1723}
1724
1725SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
1726 SDLoc dl(N);
1727 SDValue Op;
1728 switch (N->getOpcode()) {
1729 default: llvm_unreachable("Expected integer vector reduction")::llvm::llvm_unreachable_internal("Expected integer vector reduction"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1729)
;
1730 case ISD::VECREDUCE_ADD:
1731 case ISD::VECREDUCE_MUL:
1732 case ISD::VECREDUCE_AND:
1733 case ISD::VECREDUCE_OR:
1734 case ISD::VECREDUCE_XOR:
1735 Op = GetPromotedInteger(N->getOperand(0));
1736 break;
1737 case ISD::VECREDUCE_SMAX:
1738 case ISD::VECREDUCE_SMIN:
1739 Op = SExtPromotedInteger(N->getOperand(0));
1740 break;
1741 case ISD::VECREDUCE_UMAX:
1742 case ISD::VECREDUCE_UMIN:
1743 Op = ZExtPromotedInteger(N->getOperand(0));
1744 break;
1745 }
1746
1747 EVT EltVT = Op.getValueType().getVectorElementType();
1748 EVT VT = N->getValueType(0);
1749 if (VT.bitsGE(EltVT))
1750 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, Op);
1751
1752 // Result size must be >= element size. If this is not the case after
1753 // promotion, also promote the result type and then truncate.
1754 SDValue Reduce = DAG.getNode(N->getOpcode(), dl, EltVT, Op);
1755 return DAG.getNode(ISD::TRUNCATE, dl, VT, Reduce);
1756}
1757
1758//===----------------------------------------------------------------------===//
1759// Integer Result Expansion
1760//===----------------------------------------------------------------------===//
1761
1762/// ExpandIntegerResult - This method is called when the specified result of the
1763/// specified node is found to need expansion. At this point, the node may also
1764/// have invalid operands or may have other results that need promotion, we just
1765/// know that (at least) one result needs expansion.
1766void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1767 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1
Assuming 'DebugFlag' is false
2
Loop condition is false. Exiting loop
1768 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1769 SDValue Lo, Hi;
1770 Lo = Hi = SDValue();
1771
1772 // See if the target wants to custom expand this node.
1773 if (CustomLowerNode(N, N->getValueType(ResNo), true))
3
Assuming the condition is false
4
Taking false branch
1774 return;
1775
1776 switch (N->getOpcode()) {
5
Control jumps to 'case SRL:' at line 1891
1777 default:
1778#ifndef NDEBUG
1779 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1780 N->dump(&DAG); dbgs() << "\n";
1781#endif
1782 report_fatal_error("Do not know how to expand the result of this "
1783 "operator!");
1784
1785 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1786 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1787 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1788 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1789
1790 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1791 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1792 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1793 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1794 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1795
1796 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1797 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1798 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1799 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
1800 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1801 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1802 case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
1803 case ISD::CTLZ_ZERO_UNDEF:
1804 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1805 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1806 case ISD::CTTZ_ZERO_UNDEF:
1807 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1808 case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
1809 case ISD::STRICT_FP_TO_SINT:
1810 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1811 case ISD::STRICT_FP_TO_UINT:
1812 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1813 case ISD::STRICT_LLROUND:
1814 case ISD::STRICT_LLRINT:
1815 case ISD::LLROUND:
1816 case ISD::LLRINT: ExpandIntRes_LLROUND_LLRINT(N, Lo, Hi); break;
1817 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1818 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1819 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
1820 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1821 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1822 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1823 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1824 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1825 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1826 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1827 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1828 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1829
1830 case ISD::ATOMIC_LOAD_ADD:
1831 case ISD::ATOMIC_LOAD_SUB:
1832 case ISD::ATOMIC_LOAD_AND:
1833 case ISD::ATOMIC_LOAD_CLR:
1834 case ISD::ATOMIC_LOAD_OR:
1835 case ISD::ATOMIC_LOAD_XOR:
1836 case ISD::ATOMIC_LOAD_NAND:
1837 case ISD::ATOMIC_LOAD_MIN:
1838 case ISD::ATOMIC_LOAD_MAX:
1839 case ISD::ATOMIC_LOAD_UMIN:
1840 case ISD::ATOMIC_LOAD_UMAX:
1841 case ISD::ATOMIC_SWAP:
1842 case ISD::ATOMIC_CMP_SWAP: {
1843 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1844 SplitInteger(Tmp.first, Lo, Hi);
1845 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1846 break;
1847 }
1848 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1849 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1850 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1851 SDValue Tmp = DAG.getAtomicCmpSwap(
1852 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1853 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1854 AN->getMemOperand());
1855
1856 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1857 // success simply by comparing the loaded value against the ingoing
1858 // comparison.
1859 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1860 N->getOperand(2), ISD::SETEQ);
1861
1862 SplitInteger(Tmp, Lo, Hi);
1863 ReplaceValueWith(SDValue(N, 1), Success);
1864 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1865 break;
1866 }
1867
1868 case ISD::AND:
1869 case ISD::OR:
1870 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1871
1872 case ISD::UMAX:
1873 case ISD::SMAX:
1874 case ISD::UMIN:
1875 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
1876
1877 case ISD::ADD:
1878 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1879
1880 case ISD::ADDC:
1881 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1882
1883 case ISD::ADDE:
1884 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1885
1886 case ISD::ADDCARRY:
1887 case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
1888
1889 case ISD::SHL:
1890 case ISD::SRA:
1891 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
6
Calling 'DAGTypeLegalizer::ExpandIntRes_Shift'
1892
1893 case ISD::SADDO:
1894 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1895 case ISD::UADDO:
1896 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1897 case ISD::UMULO:
1898 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1899
1900 case ISD::SADDSAT:
1901 case ISD::UADDSAT:
1902 case ISD::SSUBSAT:
1903 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
1904
1905 case ISD::SMULFIX:
1906 case ISD::SMULFIXSAT:
1907 case ISD::UMULFIX:
1908 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
1909
1910 case ISD::SDIVFIX:
1911 case ISD::UDIVFIX: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
1912
1913 case ISD::VECREDUCE_ADD:
1914 case ISD::VECREDUCE_MUL:
1915 case ISD::VECREDUCE_AND:
1916 case ISD::VECREDUCE_OR:
1917 case ISD::VECREDUCE_XOR:
1918 case ISD::VECREDUCE_SMAX:
1919 case ISD::VECREDUCE_SMIN:
1920 case ISD::VECREDUCE_UMAX:
1921 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
1922 }
1923
1924 // If Lo/Hi is null, the sub-method took care of registering results etc.
1925 if (Lo.getNode())
1926 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1927}
1928
1929/// Lower an atomic node to the appropriate builtin call.
1930std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1931 unsigned Opc = Node->getOpcode();
1932 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1933 RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
1934 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected atomic op or value type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1934, __PRETTY_FUNCTION__))
;
1935
1936 EVT RetVT = Node->getValueType(0);
1937 SmallVector<SDValue, 4> Ops(Node->op_begin() + 1, Node->op_end());
1938 TargetLowering::MakeLibCallOptions CallOptions;
1939 return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, SDLoc(Node),
1940 Node->getOperand(0));
1941}
1942
1943/// N is a shift by a value that needs to be expanded,
1944/// and the shift amount is a constant 'Amt'. Expand the operation.
1945void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
1946 SDValue &Lo, SDValue &Hi) {
1947 SDLoc DL(N);
1948 // Expand the incoming operand to be shifted, so that we have its parts
1949 SDValue InL, InH;
1950 GetExpandedInteger(N->getOperand(0), InL, InH);
1951
1952 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1953 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1954 if (!Amt) {
1955 Lo = InL;
1956 Hi = InH;
1957 return;
1958 }
1959
1960 EVT NVT = InL.getValueType();
1961 unsigned VTBits = N->getValueType(0).getSizeInBits();
1962 unsigned NVTBits = NVT.getSizeInBits();
1963 EVT ShTy = N->getOperand(1).getValueType();
1964
1965 if (N->getOpcode() == ISD::SHL) {
1966 if (Amt.ugt(VTBits)) {
1967 Lo = Hi = DAG.getConstant(0, DL, NVT);
1968 } else if (Amt.ugt(NVTBits)) {
1969 Lo = DAG.getConstant(0, DL, NVT);
1970 Hi = DAG.getNode(ISD::SHL, DL,
1971 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1972 } else if (Amt == NVTBits) {
1973 Lo = DAG.getConstant(0, DL, NVT);
1974 Hi = InL;
1975 } else {
1976 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1977 Hi = DAG.getNode(ISD::OR, DL, NVT,
1978 DAG.getNode(ISD::SHL, DL, NVT, InH,
1979 DAG.getConstant(Amt, DL, ShTy)),
1980 DAG.getNode(ISD::SRL, DL, NVT, InL,
1981 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1982 }
1983 return;
1984 }
1985
1986 if (N->getOpcode() == ISD::SRL) {
1987 if (Amt.ugt(VTBits)) {
1988 Lo = Hi = DAG.getConstant(0, DL, NVT);
1989 } else if (Amt.ugt(NVTBits)) {
1990 Lo = DAG.getNode(ISD::SRL, DL,
1991 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1992 Hi = DAG.getConstant(0, DL, NVT);
1993 } else if (Amt == NVTBits) {
1994 Lo = InH;
1995 Hi = DAG.getConstant(0, DL, NVT);
1996 } else {
1997 Lo = DAG.getNode(ISD::OR, DL, NVT,
1998 DAG.getNode(ISD::SRL, DL, NVT, InL,
1999 DAG.getConstant(Amt, DL, ShTy)),
2000 DAG.getNode(ISD::SHL, DL, NVT, InH,
2001 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2002 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2003 }
2004 return;
2005 }
2006
2007 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")((N->getOpcode() == ISD::SRA && "Unknown shift!") ?
static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2007, __PRETTY_FUNCTION__))
;
2008 if (Amt.ugt(VTBits)) {
2009 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2010 DAG.getConstant(NVTBits - 1, DL, ShTy));
2011 } else if (Amt.ugt(NVTBits)) {
2012 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2013 DAG.getConstant(Amt - NVTBits, DL, ShTy));
2014 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2015 DAG.getConstant(NVTBits - 1, DL, ShTy));
2016 } else if (Amt == NVTBits) {
2017 Lo = InH;
2018 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2019 DAG.getConstant(NVTBits - 1, DL, ShTy));
2020 } else {
2021 Lo = DAG.getNode(ISD::OR, DL, NVT,
2022 DAG.getNode(ISD::SRL, DL, NVT, InL,
2023 DAG.getConstant(Amt, DL, ShTy)),
2024 DAG.getNode(ISD::SHL, DL, NVT, InH,
2025 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2026 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2027 }
2028}
2029
2030/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
2031/// this shift based on knowledge of the high bit of the shift amount. If we
2032/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
2033/// shift amount.
2034bool DAGTypeLegalizer::
2035ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2036 SDValue Amt = N->getOperand(1);
10
Value assigned to 'Amt.Node'
2037 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2038 EVT ShTy = Amt.getValueType();
11
Calling 'SDValue::getValueType'
2039 unsigned ShBits = ShTy.getScalarSizeInBits();
2040 unsigned NVTBits = NVT.getScalarSizeInBits();
2041 assert(isPowerOf2_32(NVTBits) &&((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2042, __PRETTY_FUNCTION__))
2042 "Expanded integer type size not a power of two!")((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2042, __PRETTY_FUNCTION__))
;
2043 SDLoc dl(N);
2044
2045 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
2046 KnownBits Known = DAG.computeKnownBits(N->getOperand(1));
2047
2048 // If we don't know anything about the high bits, exit.
2049 if (((Known.Zero|Known.One) & HighBitMask) == 0)
2050 return false;
2051
2052 // Get the incoming operand to be shifted.
2053 SDValue InL, InH;
2054 GetExpandedInteger(N->getOperand(0), InL, InH);
2055
2056 // If we know that any of the high bits of the shift amount are one, then we
2057 // can do this as a couple of simple shifts.
2058 if (Known.One.intersects(HighBitMask)) {
2059 // Mask out the high bit, which we know is set.
2060 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
2061 DAG.getConstant(~HighBitMask, dl, ShTy));
2062
2063 switch (N->getOpcode()) {
2064 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2064)
;
2065 case ISD::SHL:
2066 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
2067 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
2068 return true;
2069 case ISD::SRL:
2070 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2071 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
2072 return true;
2073 case ISD::SRA:
2074 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
2075 DAG.getConstant(NVTBits - 1, dl, ShTy));
2076 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
2077 return true;
2078 }
2079 }
2080
2081 // If we know that all of the high bits of the shift amount are zero, then we
2082 // can do this as a couple of simple shifts.
2083 if (HighBitMask.isSubsetOf(Known.Zero)) {
2084 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
2085 // shift if x is zero. We can use XOR here because x is known to be smaller
2086 // than 32.
2087 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
2088 DAG.getConstant(NVTBits - 1, dl, ShTy));
2089
2090 unsigned Op1, Op2;
2091 switch (N->getOpcode()) {
2092 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2092)
;
2093 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
2094 case ISD::SRL:
2095 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
2096 }
2097
2098 // When shifting right the arithmetic for Lo and Hi is swapped.
2099 if (N->getOpcode() != ISD::SHL)
2100 std::swap(InL, InH);
2101
2102 // Use a little trick to get the bits that move from Lo to Hi. First
2103 // shift by one bit.
2104 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
2105 // Then compute the remaining shift with amount-1.
2106 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
2107
2108 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
2109 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
2110
2111 if (N->getOpcode() != ISD::SHL)
2112 std::swap(Hi, Lo);
2113 return true;
2114 }
2115
2116 return false;
2117}
2118
2119/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
2120/// of any size.
2121bool DAGTypeLegalizer::
2122ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2123 SDValue Amt = N->getOperand(1);
2124 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2125 EVT ShTy = Amt.getValueType();
2126 unsigned NVTBits = NVT.getSizeInBits();
2127 assert(isPowerOf2_32(NVTBits) &&((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2128, __PRETTY_FUNCTION__))
2128 "Expanded integer type size not a power of two!")((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2128, __PRETTY_FUNCTION__))
;
2129 SDLoc dl(N);
2130
2131 // Get the incoming operand to be shifted.
2132 SDValue InL, InH;
2133 GetExpandedInteger(N->getOperand(0), InL, InH);
2134
2135 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
2136 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
2137 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
2138 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2139 Amt, NVBitsNode, ISD::SETULT);
2140 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2141 Amt, DAG.getConstant(0, dl, ShTy),
2142 ISD::SETEQ);
2143
2144 SDValue LoS, HiS, LoL, HiL;
2145 switch (N->getOpcode()) {
2146 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2146)
;
2147 case ISD::SHL:
2148 // Short: ShAmt < NVTBits
2149 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
2150 HiS = DAG.getNode(ISD::OR, dl, NVT,
2151 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
2152 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
2153
2154 // Long: ShAmt >= NVTBits
2155 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
2156 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
2157
2158 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
2159 Hi = DAG.getSelect(dl, NVT, isZero, InH,
2160 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
2161 return true;
2162 case ISD::SRL:
2163 // Short: ShAmt < NVTBits
2164 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
2165 LoS = DAG.getNode(ISD::OR, dl, NVT,
2166 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2167 // FIXME: If Amt is zero, the following shift generates an undefined result
2168 // on some architectures.
2169 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2170
2171 // Long: ShAmt >= NVTBits
2172 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2173 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2174
2175 Lo = DAG.getSelect(dl, NVT, isZero, InL,
2176 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2177 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2178 return true;
2179 case ISD::SRA:
2180 // Short: ShAmt < NVTBits
2181 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
2182 LoS = DAG.getNode(ISD::OR, dl, NVT,
2183 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2184 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2185
2186 // Long: ShAmt >= NVTBits
2187 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
2188 DAG.getConstant(NVTBits - 1, dl, ShTy));
2189 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2190
2191 Lo = DAG.getSelect(dl, NVT, isZero, InL,
2192 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2193 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2194 return true;
2195 }
2196}
2197
2198static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
2199
2200 switch (Op) {
2201 default: llvm_unreachable("invalid min/max opcode")::llvm::llvm_unreachable_internal("invalid min/max opcode", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2201)
;
2202 case ISD::SMAX:
2203 return std::make_pair(ISD::SETGT, ISD::UMAX);
2204 case ISD::UMAX:
2205 return std::make_pair(ISD::SETUGT, ISD::UMAX);
2206 case ISD::SMIN:
2207 return std::make_pair(ISD::SETLT, ISD::UMIN);
2208 case ISD::UMIN:
2209 return std::make_pair(ISD::SETULT, ISD::UMIN);
2210 }
2211}
2212
2213void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
2214 SDValue &Lo, SDValue &Hi) {
2215 SDLoc DL(N);
2216 ISD::NodeType LoOpc;
2217 ISD::CondCode CondC;
2218 std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode());
2219
2220 // Expand the subcomponents.
2221 SDValue LHSL, LHSH, RHSL, RHSH;
2222 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2223 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2224
2225 // Value types
2226 EVT NVT = LHSL.getValueType();
2227 EVT CCT = getSetCCResultType(NVT);
2228
2229 // Hi part is always the same op
2230 Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
2231
2232 // We need to know whether to select Lo part that corresponds to 'winning'
2233 // Hi part or if Hi parts are equal.
2234 SDValue IsHiLeft = DAG.getSetCC(DL, CCT, LHSH, RHSH, CondC);
2235 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ);
2236
2237 // Lo part corresponding to the 'winning' Hi part
2238 SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
2239
2240 // Recursed Lo part if Hi parts are equal, this uses unsigned version
2241 SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
2242
2243 Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
2244}
2245
2246void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
2247 SDValue &Lo, SDValue &Hi) {
2248 SDLoc dl(N);
2249 // Expand the subcomponents.
2250 SDValue LHSL, LHSH, RHSL, RHSH;
2251 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2252 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2253
2254 EVT NVT = LHSL.getValueType();
2255 SDValue LoOps[2] = { LHSL, RHSL };
2256 SDValue HiOps[3] = { LHSH, RHSH };
2257
2258 bool HasOpCarry = TLI.isOperationLegalOrCustom(
2259 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
2260 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2261 if (HasOpCarry) {
2262 SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
2263 if (N->getOpcode() == ISD::ADD) {
2264 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2265 HiOps[2] = Lo.getValue(1);
2266 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps);
2267 } else {
2268 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2269 HiOps[2] = Lo.getValue(1);
2270 Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
2271 }
2272 return;
2273 }
2274
2275 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
2276 // them. TODO: Teach operation legalization how to expand unsupported
2277 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
2278 // a carry of type MVT::Glue, but there doesn't seem to be any way to
2279 // generate a value of this type in the expanded code sequence.
2280 bool hasCarry =
2281 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2282 ISD::ADDC : ISD::SUBC,
2283 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2284
2285 if (hasCarry) {
2286 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
2287 if (N->getOpcode() == ISD::ADD) {
2288 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2289 HiOps[2] = Lo.getValue(1);
2290 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2291 } else {
2292 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2293 HiOps[2] = Lo.getValue(1);
2294 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2295 }
2296 return;
2297 }
2298
2299 bool hasOVF =
2300 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2301 ISD::UADDO : ISD::USUBO,
2302 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2303 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
2304
2305 if (hasOVF) {
2306 EVT OvfVT = getSetCCResultType(NVT);
2307 SDVTList VTList = DAG.getVTList(NVT, OvfVT);
2308 int RevOpc;
2309 if (N->getOpcode() == ISD::ADD) {
2310 RevOpc = ISD::SUB;
2311 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2312 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2313 } else {
2314 RevOpc = ISD::ADD;
2315 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2316 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2317 }
2318 SDValue OVF = Lo.getValue(1);
2319
2320 switch (BoolType) {
2321 case TargetLoweringBase::UndefinedBooleanContent:
2322 OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF);
2323 LLVM_FALLTHROUGH[[gnu::fallthrough]];
2324 case TargetLoweringBase::ZeroOrOneBooleanContent:
2325 OVF = DAG.getZExtOrTrunc(OVF, dl, NVT);
2326 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
2327 break;
2328 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2329 OVF = DAG.getSExtOrTrunc(OVF, dl, NVT);
2330 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
2331 }
2332 return;
2333 }
2334
2335 if (N->getOpcode() == ISD::ADD) {
2336 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
2337 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2338 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
2339 ISD::SETULT);
2340
2341 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent) {
2342 SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT);
2343 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
2344 return;
2345 }
2346
2347 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
2348 DAG.getConstant(1, dl, NVT),
2349 DAG.getConstant(0, dl, NVT));
2350 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
2351 ISD::SETULT);
2352 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
2353 DAG.getConstant(1, dl, NVT), Carry1);
2354 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
2355 } else {
2356 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
2357 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2358 SDValue Cmp =
2359 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
2360 LoOps[0], LoOps[1], ISD::SETULT);
2361
2362 SDValue Borrow;
2363 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
2364 Borrow = DAG.getZExtOrTrunc(Cmp, dl, NVT);
2365 else
2366 Borrow = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT),
2367 DAG.getConstant(0, dl, NVT));
2368
2369 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
2370 }
2371}
2372
2373void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
2374 SDValue &Lo, SDValue &Hi) {
2375 // Expand the subcomponents.
2376 SDValue LHSL, LHSH, RHSL, RHSH;
2377 SDLoc dl(N);
2378 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2379 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2380 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2381 SDValue LoOps[2] = { LHSL, RHSL };
2382 SDValue HiOps[3] = { LHSH, RHSH };
2383
2384 if (N->getOpcode() == ISD::ADDC) {
2385 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2386 HiOps[2] = Lo.getValue(1);
2387 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2388 } else {
2389 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2390 HiOps[2] = Lo.getValue(1);
2391 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2392 }
2393
2394 // Legalized the flag result - switch anything that used the old flag to
2395 // use the new one.
2396 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2397}
2398
2399void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
2400 SDValue &Lo, SDValue &Hi) {
2401 // Expand the subcomponents.
2402 SDValue LHSL, LHSH, RHSL, RHSH;
2403 SDLoc dl(N);
2404 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2405 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2406 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2407 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2408 SDValue HiOps[3] = { LHSH, RHSH };
2409
2410 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2411 HiOps[2] = Lo.getValue(1);
2412 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2413
2414 // Legalized the flag result - switch anything that used the old flag to
2415 // use the new one.
2416 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2417}
2418
2419void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2420 SDValue &Lo, SDValue &Hi) {
2421 SDValue LHS = N->getOperand(0);
2422 SDValue RHS = N->getOperand(1);
2423 SDLoc dl(N);
2424
2425 SDValue Ovf;
2426
2427 unsigned CarryOp, NoCarryOp;
2428 ISD::CondCode Cond;
2429 switch(N->getOpcode()) {
2430 case ISD::UADDO:
2431 CarryOp = ISD::ADDCARRY;
2432 NoCarryOp = ISD::ADD;
2433 Cond = ISD::SETULT;
2434 break;
2435 case ISD::USUBO:
2436 CarryOp = ISD::SUBCARRY;
2437 NoCarryOp = ISD::SUB;
2438 Cond = ISD::SETUGT;
2439 break;
2440 default:
2441 llvm_unreachable("Node has unexpected Opcode")::llvm::llvm_unreachable_internal("Node has unexpected Opcode"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2441)
;
2442 }
2443
2444 bool HasCarryOp = TLI.isOperationLegalOrCustom(
2445 CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
2446
2447 if (HasCarryOp) {
2448 // Expand the subcomponents.
2449 SDValue LHSL, LHSH, RHSL, RHSH;
2450 GetExpandedInteger(LHS, LHSL, LHSH);
2451 GetExpandedInteger(RHS, RHSL, RHSH);
2452 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2453 SDValue LoOps[2] = { LHSL, RHSL };
2454 SDValue HiOps[3] = { LHSH, RHSH };
2455
2456 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2457 HiOps[2] = Lo.getValue(1);
2458 Hi = DAG.getNode(CarryOp, dl, VTList, HiOps);
2459
2460 Ovf = Hi.getValue(1);
2461 } else {
2462 // Expand the result by simply replacing it with the equivalent
2463 // non-overflow-checking operation.
2464 SDValue Sum = DAG.getNode(NoCarryOp, dl, LHS.getValueType(), LHS, RHS);
2465 SplitInteger(Sum, Lo, Hi);
2466
2467 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2468 // overflows iff a - b > a.
2469 Ovf = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, Cond);
2470 }
2471
2472 // Legalized the flag result - switch anything that used the old flag to
2473 // use the new one.
2474 ReplaceValueWith(SDValue(N, 1), Ovf);
2475}
2476
2477void DAGTypeLegalizer::ExpandIntRes_ADDSUBCARRY(SDNode *N,
2478 SDValue &Lo, SDValue &Hi) {
2479 // Expand the subcomponents.
2480 SDValue LHSL, LHSH, RHSL, RHSH;
2481 SDLoc dl(N);
2482 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2483 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2484 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2485 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2486 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
2487
2488 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2489 HiOps[2] = Lo.getValue(1);
2490 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2491
2492 // Legalized the flag result - switch anything that used the old flag to
2493 // use the new one.
2494 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2495}
2496
2497void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
2498 SDValue &Lo, SDValue &Hi) {
2499 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2500 SDLoc dl(N);
2501 SDValue Op = N->getOperand(0);
2502 if (Op.getValueType().bitsLE(NVT)) {
2503 // The low part is any extension of the input (which degenerates to a copy).
2504 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
2505 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
2506 } else {
2507 // For example, extension of an i48 to an i64. The operand type necessarily
2508 // promotes to the result type, so will end up being expanded too.
2509 assert(getTypeAction(Op.getValueType()) ==((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2511, __PRETTY_FUNCTION__))
2510 TargetLowering::TypePromoteInteger &&((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2511, __PRETTY_FUNCTION__))
2511 "Only know how to promote this result!")((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2511, __PRETTY_FUNCTION__))
;
2512 SDValue Res = GetPromotedInteger(Op);
2513 assert(Res.getValueType() == N->getValueType(0) &&((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2514, __PRETTY_FUNCTION__))
2514 "Operand over promoted?")((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2514, __PRETTY_FUNCTION__))
;
2515 // Split the promoted operand. This will simplify when it is expanded.
2516 SplitInteger(Res, Lo, Hi);
2517 }
2518}
2519
2520void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
2521 SDValue &Lo, SDValue &Hi) {
2522 SDLoc dl(N);
2523 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2524 EVT NVT = Lo.getValueType();
2525 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2526 unsigned NVTBits = NVT.getSizeInBits();
2527 unsigned EVTBits = EVT.getSizeInBits();
2528
2529 if (NVTBits < EVTBits) {
2530 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
2531 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2532 EVTBits - NVTBits)));
2533 } else {
2534 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
2535 // The high part replicates the sign bit of Lo, make it explicit.
2536 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2537 DAG.getConstant(NVTBits - 1, dl,
2538 TLI.getPointerTy(DAG.getDataLayout())));
2539 }
2540}
2541
2542void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
2543 SDValue &Lo, SDValue &Hi) {
2544 SDLoc dl(N);
2545 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2546 EVT NVT = Lo.getValueType();
2547 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2548 unsigned NVTBits = NVT.getSizeInBits();
2549 unsigned EVTBits = EVT.getSizeInBits();
2550
2551 if (NVTBits < EVTBits) {
2552 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
2553 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2554 EVTBits - NVTBits)));
2555 } else {
2556 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
2557 // The high part must be zero, make it explicit.
2558 Hi = DAG.getConstant(0, dl, NVT);
2559 }
2560}
2561
2562void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
2563 SDValue &Lo, SDValue &Hi) {
2564 SDLoc dl(N);
2565 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
2566 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
2567 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
2568}
2569
2570void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
2571 SDValue &Lo, SDValue &Hi) {
2572 SDLoc dl(N);
2573 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
2574 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
2575 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
2576}
2577
2578void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
2579 SDValue &Lo, SDValue &Hi) {
2580 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2581 unsigned NBitWidth = NVT.getSizeInBits();
2582 auto Constant = cast<ConstantSDNode>(N);
2583 const APInt &Cst = Constant->getAPIntValue();
2584 bool IsTarget = Constant->isTargetOpcode();
2585 bool IsOpaque = Constant->isOpaque();
2586 SDLoc dl(N);
2587 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
2588 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
2589 IsOpaque);
2590}
2591
2592void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
2593 SDLoc dl(N);
2594
2595 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
2596 EVT VT = N->getValueType(0);
2597 SDValue N0 = N->getOperand(0);
2598 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT,
2599 DAG.getConstant(0, dl, VT), N0);
2600 SDValue NegLo, NegHi;
2601 SplitInteger(Neg, NegLo, NegHi);
2602
2603 GetExpandedInteger(N0, Lo, Hi);
2604 EVT NVT = Lo.getValueType();
2605 SDValue HiIsNeg = DAG.getSetCC(dl, getSetCCResultType(NVT),
2606 DAG.getConstant(0, dl, NVT), Hi, ISD::SETGT);
2607 Lo = DAG.getSelect(dl, NVT, HiIsNeg, NegLo, Lo);
2608 Hi = DAG.getSelect(dl, NVT, HiIsNeg, NegHi, Hi);
2609}
2610
2611void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
2612 SDValue &Lo, SDValue &Hi) {
2613 SDLoc dl(N);
2614 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
2615 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2616 EVT NVT = Lo.getValueType();
2617
2618 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
2619 DAG.getConstant(0, dl, NVT), ISD::SETNE);
2620
2621 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
2622 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
2623
2624 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
2625 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
2626 DAG.getConstant(NVT.getSizeInBits(), dl,
2627 NVT)));
2628 Hi = DAG.getConstant(0, dl, NVT);
2629}
2630
2631void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
2632 SDValue &Lo, SDValue &Hi) {
2633 SDLoc dl(N);
2634 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
2635 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2636 EVT NVT = Lo.getValueType();
2637 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
2638 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
2639 Hi = DAG.getConstant(0, dl, NVT);
2640}
2641
2642void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
2643 SDValue &Lo, SDValue &Hi) {
2644 SDLoc dl(N);
2645 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
2646 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2647 EVT NVT = Lo.getValueType();
2648
2649 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
2650 DAG.getConstant(0, dl, NVT), ISD::SETNE);
2651
2652 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
2653 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
2654
2655 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
2656 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
2657 DAG.getConstant(NVT.getSizeInBits(), dl,
2658 NVT)));
2659 Hi = DAG.getConstant(0, dl, NVT);
2660}
2661
2662void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo,
2663 SDValue &Hi) {
2664 SDLoc dl(N);
2665 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2666 unsigned NBitWidth = NVT.getSizeInBits();
2667
2668 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
2669 Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, NVT);
2670 // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS
2671 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2672 DAG.getConstant(NBitWidth - 1, dl, ShiftAmtTy));
2673}
2674
2675void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
2676 SDValue &Hi) {
2677 SDLoc dl(N);
2678 EVT VT = N->getValueType(0);
2679
2680 bool IsStrict = N->isStrictFPOpcode();
2681 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
2682 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
2683 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
2684 Op = GetPromotedFloat(Op);
2685
2686 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
2687 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fp-to-sint conversion!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2687, __PRETTY_FUNCTION__))
;
2688 TargetLowering::MakeLibCallOptions CallOptions;
2689 CallOptions.setSExt(true);
2690 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
2691 CallOptions, dl, Chain);
2692 SplitInteger(Tmp.first, Lo, Hi);
2693
2694 if (IsStrict)
2695 ReplaceValueWith(SDValue(N, 1), Tmp.second);
2696}
2697
2698void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
2699 SDValue &Hi) {
2700 SDLoc dl(N);
2701 EVT VT = N->getValueType(0);
2702
2703 bool IsStrict = N->isStrictFPOpcode();
2704 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
2705 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
2706 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
2707 Op = GetPromotedFloat(Op);
2708
2709 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
2710 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fp-to-uint conversion!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2710, __PRETTY_FUNCTION__))
;
2711 TargetLowering::MakeLibCallOptions CallOptions;
2712 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
2713 CallOptions, dl, Chain);
2714 SplitInteger(Tmp.first, Lo, Hi);
2715
2716 if (IsStrict)
2717 ReplaceValueWith(SDValue(N, 1), Tmp.second);
2718}
2719
2720void DAGTypeLegalizer::ExpandIntRes_LLROUND_LLRINT(SDNode *N, SDValue &Lo,
2721 SDValue &Hi) {
2722 SDValue Op = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
2723
2724 assert(getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat &&((getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat
&& "Input type needs to be promoted!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat && \"Input type needs to be promoted!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2725, __PRETTY_FUNCTION__))
2725 "Input type needs to be promoted!")((getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat
&& "Input type needs to be promoted!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat && \"Input type needs to be promoted!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2725, __PRETTY_FUNCTION__))
;
2726
2727 EVT VT = Op.getValueType();
2728
2729 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2730 if (N->getOpcode() == ISD::LLROUND ||
2731 N->getOpcode() == ISD::STRICT_LLROUND) {
2732 if (VT == MVT::f32)
2733 LC = RTLIB::LLROUND_F32;
2734 else if (VT == MVT::f64)
2735 LC = RTLIB::LLROUND_F64;
2736 else if (VT == MVT::f80)
2737 LC = RTLIB::LLROUND_F80;
2738 else if (VT == MVT::f128)
2739 LC = RTLIB::LLROUND_F128;
2740 else if (VT == MVT::ppcf128)
2741 LC = RTLIB::LLROUND_PPCF128;
2742 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected llround input type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2742, __PRETTY_FUNCTION__))
;
2743 } else if (N->getOpcode() == ISD::LLRINT ||
2744 N->getOpcode() == ISD::STRICT_LLRINT) {
2745 if (VT == MVT::f32)
2746 LC = RTLIB::LLRINT_F32;
2747 else if (VT == MVT::f64)
2748 LC = RTLIB::LLRINT_F64;
2749 else if (VT == MVT::f80)
2750 LC = RTLIB::LLRINT_F80;
2751 else if (VT == MVT::f128)
2752 LC = RTLIB::LLRINT_F128;
2753 else if (VT == MVT::ppcf128)
2754 LC = RTLIB::LLRINT_PPCF128;
2755 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected llrint input type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2755, __PRETTY_FUNCTION__))
;
2756 } else
2757 llvm_unreachable("Unexpected opcode!")::llvm::llvm_unreachable_internal("Unexpected opcode!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2757)
;
2758
2759 SDLoc dl(N);
2760 EVT RetVT = N->getValueType(0);
2761 SDValue Chain = N->isStrictFPOpcode() ? N->getOperand(0) : SDValue();
2762
2763 TargetLowering::MakeLibCallOptions CallOptions;
2764 CallOptions.setSExt(true);
2765 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
2766 Op, CallOptions, dl,
2767 Chain);
2768 SplitInteger(Tmp.first, Lo, Hi);
2769
2770 if (N->isStrictFPOpcode())
2771 ReplaceValueWith(SDValue(N, 1), Tmp.second);
2772}
2773
2774void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
2775 SDValue &Lo, SDValue &Hi) {
2776 if (N->isAtomic()) {
2777 // It's typical to have larger CAS than atomic load instructions.
2778 SDLoc dl(N);
2779 EVT VT = N->getMemoryVT();
2780 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2781 SDValue Zero = DAG.getConstant(0, dl, VT);
2782 SDValue Swap = DAG.getAtomicCmpSwap(
2783 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2784 VT, VTs, N->getOperand(0),
2785 N->getOperand(1), Zero, Zero, N->getMemOperand());
2786 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2787 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2788 return;
2789 }
2790
2791 if (ISD::isNormalLoad(N)) {
2792 ExpandRes_NormalLoad(N, Lo, Hi);
2793 return;
2794 }
2795
2796 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!")((ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDLoad(N) && \"Indexed load during type legalization!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2796, __PRETTY_FUNCTION__))
;
2797
2798 EVT VT = N->getValueType(0);
2799 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2800 SDValue Ch = N->getChain();
2801 SDValue Ptr = N->getBasePtr();
2802 ISD::LoadExtType ExtType = N->getExtensionType();
2803 unsigned Alignment = N->getAlignment();
2804 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
2805 AAMDNodes AAInfo = N->getAAInfo();
2806 SDLoc dl(N);
2807
2808 assert(NVT.isByteSized() && "Expanded type not byte sized!")((NVT.isByteSized() && "Expanded type not byte sized!"
) ? static_cast<void> (0) : __assert_fail ("NVT.isByteSized() && \"Expanded type not byte sized!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2808, __PRETTY_FUNCTION__))
;
2809
2810 if (N->getMemoryVT().bitsLE(NVT)) {
2811 EVT MemVT = N->getMemoryVT();
2812
2813 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
2814 Alignment, MMOFlags, AAInfo);
2815
2816 // Remember the chain.
2817 Ch = Lo.getValue(1);
2818
2819 if (ExtType == ISD::SEXTLOAD) {
2820 // The high part is obtained by SRA'ing all but one of the bits of the
2821 // lo part.
2822 unsigned LoSize = Lo.getValueSizeInBits();
2823 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2824 DAG.getConstant(LoSize - 1, dl,
2825 TLI.getPointerTy(DAG.getDataLayout())));
2826 } else if (ExtType == ISD::ZEXTLOAD) {
2827 // The high part is just a zero.
2828 Hi = DAG.getConstant(0, dl, NVT);
2829 } else {
2830 assert(ExtType == ISD::EXTLOAD && "Unknown extload!")((ExtType == ISD::EXTLOAD && "Unknown extload!") ? static_cast
<void> (0) : __assert_fail ("ExtType == ISD::EXTLOAD && \"Unknown extload!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2830, __PRETTY_FUNCTION__))
;
2831 // The high part is undefined.
2832 Hi = DAG.getUNDEF(NVT);
2833 }
2834 } else if (DAG.getDataLayout().isLittleEndian()) {
2835 // Little-endian - low bits are at low addresses.
2836 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
2837 AAInfo);
2838
2839 unsigned ExcessBits =
2840 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2841 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2842
2843 // Increment the pointer to the other half.
2844 unsigned IncrementSize = NVT.getSizeInBits()/8;
2845 Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
2846 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2847 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2848 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
2849
2850 // Build a factor node to remember that this load is independent of the
2851 // other one.
2852 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2853 Hi.getValue(1));
2854 } else {
2855 // Big-endian - high bits are at low addresses. Favor aligned loads at
2856 // the cost of some bit-fiddling.
2857 EVT MemVT = N->getMemoryVT();
2858 unsigned EBytes = MemVT.getStoreSize();
2859 unsigned IncrementSize = NVT.getSizeInBits()/8;
2860 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2861
2862 // Load both the high bits and maybe some of the low bits.
2863 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2864 EVT::getIntegerVT(*DAG.getContext(),
2865 MemVT.getSizeInBits() - ExcessBits),
2866 Alignment, MMOFlags, AAInfo);
2867
2868 // Increment the pointer to the other half.
2869 Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
2870 // Load the rest of the low bits.
2871 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2872 N->getPointerInfo().getWithOffset(IncrementSize),
2873 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2874 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
2875
2876 // Build a factor node to remember that this load is independent of the
2877 // other one.
2878 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2879 Hi.getValue(1));
2880
2881 if (ExcessBits < NVT.getSizeInBits()) {
2882 // Transfer low bits from the bottom of Hi to the top of Lo.
2883 Lo = DAG.getNode(
2884 ISD::OR, dl, NVT, Lo,
2885 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2886 DAG.getConstant(ExcessBits, dl,
2887 TLI.getPointerTy(DAG.getDataLayout()))));
2888 // Move high bits to the right position in Hi.
2889 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2890 Hi,
2891 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2892 TLI.getPointerTy(DAG.getDataLayout())));
2893 }
2894 }
2895
2896 // Legalize the chain result - switch anything that used the old chain to
2897 // use the new one.
2898 ReplaceValueWith(SDValue(N, 1), Ch);
2899}
2900
2901void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2902 SDValue &Lo, SDValue &Hi) {
2903 SDLoc dl(N);
2904 SDValue LL, LH, RL, RH;
2905 GetExpandedInteger(N->getOperand(0), LL, LH);
2906 GetExpandedInteger(N->getOperand(1), RL, RH);
2907 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2908 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2909}
2910
2911void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2912 SDValue &Lo, SDValue &Hi) {
2913 EVT VT = N->getValueType(0);
2914 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2915 SDLoc dl(N);
2916
2917 SDValue LL, LH, RL, RH;
2918 GetExpandedInteger(N->getOperand(0), LL, LH);
2919 GetExpandedInteger(N->getOperand(1), RL, RH);
2920
2921 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG,
2922 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
2923 LL, LH, RL, RH))
2924 return;
2925
2926 // If nothing else, we can make a libcall.
2927 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2928 if (VT == MVT::i16)
2929 LC = RTLIB::MUL_I16;
2930 else if (VT == MVT::i32)
2931 LC = RTLIB::MUL_I32;
2932 else if (VT == MVT::i64)
2933 LC = RTLIB::MUL_I64;
2934 else if (VT == MVT::i128)
2935 LC = RTLIB::MUL_I128;
2936
2937 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
2938 // We'll expand the multiplication by brute force because we have no other
2939 // options. This is a trivially-generalized version of the code from
2940 // Hacker's Delight (itself derived from Knuth's Algorithm M from section
2941 // 4.3.1).
2942 unsigned Bits = NVT.getSizeInBits();
2943 unsigned HalfBits = Bits >> 1;
2944 SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl,
2945 NVT);
2946 SDValue LLL = DAG.getNode(ISD::AND, dl, NVT, LL, Mask);
2947 SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask);
2948
2949 SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
2950 SDValue TL = DAG.getNode(ISD::AND, dl, NVT, T, Mask);
2951
2952 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
2953 if (APInt::getMaxValue(ShiftAmtTy.getSizeInBits()).ult(HalfBits)) {
2954 // The type from TLI is too small to fit the shift amount we want.
2955 // Override it with i32. The shift will have to be legalized.
2956 ShiftAmtTy = MVT::i32;
2957 }
2958 SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy);
2959 SDValue TH = DAG.getNode(ISD::SRL, dl, NVT, T, Shift);
2960 SDValue LLH = DAG.getNode(ISD::SRL, dl, NVT, LL, Shift);
2961 SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);
2962
2963 SDValue U = DAG.getNode(ISD::ADD, dl, NVT,
2964 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
2965 SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);
2966 SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
2967
2968 SDValue V = DAG.getNode(ISD::ADD, dl, NVT,
2969 DAG.getNode(ISD::MUL, dl, NVT, LLL, RLH), UL);
2970 SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);
2971
2972 SDValue W = DAG.getNode(ISD::ADD, dl, NVT,
2973 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
2974 DAG.getNode(ISD::ADD, dl, NVT, UH, VH));
2975 Lo = DAG.getNode(ISD::ADD, dl, NVT, TL,
2976 DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
2977
2978 Hi = DAG.getNode(ISD::ADD, dl, NVT, W,
2979 DAG.getNode(ISD::ADD, dl, NVT,
2980 DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
2981 DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
2982 return;
2983 }
2984
2985 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2986 TargetLowering::MakeLibCallOptions CallOptions;
2987 CallOptions.setSExt(true);
2988 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first,
2989 Lo, Hi);
2990}
2991
2992void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
2993 SDValue &Hi) {
2994 SDLoc DL(N);
2995 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2996 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
2997 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
2998 Lo = R.getValue(0);
2999 Hi = R.getValue(1);
3000 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
3001}
3002
3003void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
3004 SDValue &Hi) {
3005 SDValue Result = TLI.expandAddSubSat(N, DAG);
3006 SplitInteger(Result, Lo, Hi);
3007}
3008
3009/// This performs an expansion of the integer result for a fixed point
3010/// multiplication. The default expansion performs rounding down towards
3011/// negative infinity, though targets that do care about rounding should specify
3012/// a target hook for rounding and provide their own expansion or lowering of
3013/// fixed point multiplication to be consistent with rounding.
3014void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
3015 SDValue &Hi) {
3016 SDLoc dl(N);
3017 EVT VT = N->getValueType(0);
3018 unsigned VTSize = VT.getScalarSizeInBits();
3019 SDValue LHS = N->getOperand(0);
3020 SDValue RHS = N->getOperand(1);
3021 uint64_t Scale = N->getConstantOperandVal(2);
3022 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
3023 N->getOpcode() == ISD::UMULFIXSAT);
3024 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
3025 N->getOpcode() == ISD::SMULFIXSAT);
3026
3027 // Handle special case when scale is equal to zero.
3028 if (!Scale) {
3029 SDValue Result;
3030 if (!Saturating) {
3031 Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3032 } else {
3033 EVT BoolVT = getSetCCResultType(VT);
3034 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
3035 Result = DAG.getNode(MulOp, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
3036 SDValue Product = Result.getValue(0);
3037 SDValue Overflow = Result.getValue(1);
3038 if (Signed) {
3039 APInt MinVal = APInt::getSignedMinValue(VTSize);
3040 APInt MaxVal = APInt::getSignedMaxValue(VTSize);
3041 SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
3042 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3043 SDValue Zero = DAG.getConstant(0, dl, VT);
3044 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT);
3045 Result = DAG.getSelect(dl, VT, ProdNeg, SatMax, SatMin);
3046 Result = DAG.getSelect(dl, VT, Overflow, Result, Product);
3047 } else {
3048 // For unsigned multiplication, we only need to check the max since we
3049 // can't really overflow towards zero.
3050 APInt MaxVal = APInt::getMaxValue(VTSize);
3051 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3052 Result = DAG.getSelect(dl, VT, Overflow, SatMax, Product);
3053 }
3054 }
3055 SplitInteger(Result, Lo, Hi);
3056 return;
3057 }
3058
3059 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
3060 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
3061 assert(Scale <= VTSize && "Scale can't be larger than the value type size.")((Scale <= VTSize && "Scale can't be larger than the value type size."
) ? static_cast<void> (0) : __assert_fail ("Scale <= VTSize && \"Scale can't be larger than the value type size.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3061, __PRETTY_FUNCTION__))
;
3062
3063 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3064 SDValue LL, LH, RL, RH;
3065 GetExpandedInteger(LHS, LL, LH);
3066 GetExpandedInteger(RHS, RL, RH);
3067 SmallVector<SDValue, 4> Result;
3068
3069 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
3070 if (!TLI.expandMUL_LOHI(LoHiOp, VT, dl, LHS, RHS, Result, NVT, DAG,
3071 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
3072 LL, LH, RL, RH)) {
3073 report_fatal_error("Unable to expand MUL_FIX using MUL_LOHI.");
3074 return;
3075 }
3076
3077 unsigned NVTSize = NVT.getScalarSizeInBits();
3078 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "(((VTSize == NVTSize * 2) && "Expected the new value type to be half "
"the size of the current value type") ? static_cast<void>
(0) : __assert_fail ("(VTSize == NVTSize * 2) && \"Expected the new value type to be half \" \"the size of the current value type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3079, __PRETTY_FUNCTION__))
3079 "the size of the current value type")(((VTSize == NVTSize * 2) && "Expected the new value type to be half "
"the size of the current value type") ? static_cast<void>
(0) : __assert_fail ("(VTSize == NVTSize * 2) && \"Expected the new value type to be half \" \"the size of the current value type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3079, __PRETTY_FUNCTION__))
;
3080 EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3081
3082 // After getting the multiplication result in 4 parts, we need to perform a
3083 // shift right by the amount of the scale to get the result in that scale.
3084 //
3085 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
3086 // 128 bits that are cut into 4 32-bit parts:
3087 //
3088 // HH HL LH LL
3089 // |---32---|---32---|---32---|---32---|
3090 // 128 96 64 32 0
3091 //
3092 // |------VTSize-----|
3093 //
3094 // |NVTSize-|
3095 //
3096 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
3097 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
3098 // amount and get Lo and Hi using two funnel shifts. Or for the special case
3099 // when Scale is a multiple of NVTSize we can just pick the result without
3100 // shifting.
3101 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
3102 if (Scale % NVTSize) {
3103 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy);
3104 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0],
3105 ShiftAmount);
3106 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1],
3107 ShiftAmount);
3108 } else {
3109 Lo = Result[Part0];
3110 Hi = Result[Part0 + 1];
3111 }
3112
3113 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
3114 if (!Saturating)
3115 return;
3116
3117 // Can not overflow when there is no integer part.
3118 if (Scale == VTSize)
3119 return;
3120
3121 // To handle saturation we must check for overflow in the multiplication.
3122 //
3123 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
3124 // aren't all zeroes.
3125 //
3126 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
3127 // aren't all ones or all zeroes.
3128 //
3129 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
3130 // highest bit of HH determines saturation direction in the event of signed
3131 // saturation.
3132
3133 SDValue ResultHL = Result[2];
3134 SDValue ResultHH = Result[3];
3135
3136 SDValue SatMax, SatMin;
3137 SDValue NVTZero = DAG.getConstant(0, dl, NVT);
3138 SDValue NVTNeg1 = DAG.getConstant(-1, dl, NVT);
3139 EVT BoolNVT = getSetCCResultType(NVT);
3140
3141 if (!Signed) {
3142 if (Scale < NVTSize) {
3143 // Overflow happened if ((HH | (HL >> Scale)) != 0).
3144 SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3145 DAG.getConstant(Scale, dl, ShiftTy));
3146 SDValue Tmp = DAG.getNode(ISD::OR, dl, NVT, HLAdjusted, ResultHH);
3147 SatMax = DAG.getSetCC(dl, BoolNVT, Tmp, NVTZero, ISD::SETNE);
3148 } else if (Scale == NVTSize) {
3149 // Overflow happened if (HH != 0).
3150 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETNE);
3151 } else if (Scale < VTSize) {
3152 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
3153 SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3154 DAG.getConstant(Scale - NVTSize, dl,
3155 ShiftTy));
3156 SatMax = DAG.getSetCC(dl, BoolNVT, HLAdjusted, NVTZero, ISD::SETNE);
3157 } else
3158 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"::llvm::llvm_unreachable_internal("Scale must be less or equal to VTSize for UMULFIXSAT"
"(and saturation can't happen with Scale==VTSize).", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3159)
3159 "(and saturation can't happen with Scale==VTSize).")::llvm::llvm_unreachable_internal("Scale must be less or equal to VTSize for UMULFIXSAT"
"(and saturation can't happen with Scale==VTSize).", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3159)
;
3160
3161 Hi = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Hi);
3162 Lo = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Lo);
3163 return;
3164 }
3165
3166 if (Scale < NVTSize) {
3167 // The number of overflow bits we can check are VTSize - Scale + 1 (we
3168 // include the sign bit). If these top bits are > 0, then we overflowed past
3169 // the max value. If these top bits are < -1, then we overflowed past the
3170 // min value. Otherwise, we did not overflow.
3171 unsigned OverflowBits = VTSize - Scale + 1;
3172 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&((OverflowBits <= VTSize && OverflowBits > NVTSize
&& "Extent of overflow bits must start within HL") ?
static_cast<void> (0) : __assert_fail ("OverflowBits <= VTSize && OverflowBits > NVTSize && \"Extent of overflow bits must start within HL\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3173, __PRETTY_FUNCTION__))
3173 "Extent of overflow bits must start within HL")((OverflowBits <= VTSize && OverflowBits > NVTSize
&& "Extent of overflow bits must start within HL") ?
static_cast<void> (0) : __assert_fail ("OverflowBits <= VTSize && OverflowBits > NVTSize && \"Extent of overflow bits must start within HL\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3173, __PRETTY_FUNCTION__))
;
3174 SDValue HLHiMask = DAG.getConstant(
3175 APInt::getHighBitsSet(NVTSize, OverflowBits - NVTSize), dl, NVT);
3176 SDValue HLLoMask = DAG.getConstant(
3177 APInt::getLowBitsSet(NVTSize, VTSize - OverflowBits), dl, NVT);
3178 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
3179 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3180 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3181 SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT);
3182 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3183 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLUGT));
3184 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
3185 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3186 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3187 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT);
3188 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3189 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLULT));
3190 } else if (Scale == NVTSize) {
3191 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
3192 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3193 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3194 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT);
3195 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3196 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLNeg));
3197 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
3198 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3199 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3200 SDValue HLPos = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETGE);
3201 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3202 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLPos));
3203 } else if (Scale < VTSize) {
3204 // This is similar to the case when we saturate if Scale < NVTSize, but we
3205 // only need to check HH.
3206 unsigned OverflowBits = VTSize - Scale + 1;
3207 SDValue HHHiMask = DAG.getConstant(
3208 APInt::getHighBitsSet(NVTSize, OverflowBits), dl, NVT);
3209 SDValue HHLoMask = DAG.getConstant(
3210 APInt::getLowBitsSet(NVTSize, NVTSize - OverflowBits), dl, NVT);
3211 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, HHLoMask, ISD::SETGT);
3212 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT);
3213 } else
3214 llvm_unreachable("Illegal scale for signed fixed point mul.")::llvm::llvm_unreachable_internal("Illegal scale for signed fixed point mul."
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3214)
;
3215
3216 // Saturate to signed maximum.
3217 APInt MaxHi = APInt::getSignedMaxValue(NVTSize);
3218 APInt MaxLo = APInt::getAllOnesValue(NVTSize);
3219 Hi = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxHi, dl, NVT), Hi);
3220 Lo = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxLo, dl, NVT), Lo);
3221 // Saturate to signed minimum.
3222 APInt MinHi = APInt::getSignedMinValue(NVTSize);
3223 Hi = DAG.getSelect(dl, NVT, SatMin, DAG.getConstant(MinHi, dl, NVT), Hi);
3224 Lo = DAG.getSelect(dl, NVT, SatMin, NVTZero, Lo);
3225}
3226
3227void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
3228 SDValue &Hi) {
3229 SDValue Res = earlyExpandDIVFIX(N, N->getOperand(0), N->getOperand(1),
3230 N->getConstantOperandVal(2), TLI, DAG);
3231 SplitInteger(Res, Lo, Hi);
3232}
3233
3234void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
3235 SDValue &Lo, SDValue &Hi) {
3236 SDValue LHS = Node->getOperand(0);
3237 SDValue RHS = Node->getOperand(1);
3238 SDLoc dl(Node);
3239
3240 // Expand the result by simply replacing it with the equivalent
3241 // non-overflow-checking operation.
3242 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3243 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3244 LHS, RHS);
3245 SplitInteger(Sum, Lo, Hi);
3246
3247 // Compute the overflow.
3248 //
3249 // LHSSign -> LHS >= 0
3250 // RHSSign -> RHS >= 0
3251 // SumSign -> Sum >= 0
3252 //
3253 // Add:
3254 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3255 // Sub:
3256 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3257 //
3258 EVT OType = Node->getValueType(1);
3259 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3260
3261 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3262 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3263 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3264 Node->getOpcode() == ISD::SADDO ?
3265 ISD::SETEQ : ISD::SETNE);
3266
3267 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3268 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3269
3270 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3271
3272 // Use the calculated overflow everywhere.
3273 ReplaceValueWith(SDValue(Node, 1), Cmp);
3274}
3275
3276void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
3277 SDValue &Lo, SDValue &Hi) {
3278 EVT VT = N->getValueType(0);
3279 SDLoc dl(N);
3280 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3281
3282 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3283 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3284 SplitInteger(Res.getValue(0), Lo, Hi);
3285 return;
3286 }
3287
3288 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3289 if (VT == MVT::i16)
3290 LC = RTLIB::SDIV_I16;
3291 else if (VT == MVT::i32)
3292 LC = RTLIB::SDIV_I32;
3293 else if (VT == MVT::i64)
3294 LC = RTLIB::SDIV_I64;
3295 else if (VT == MVT::i128)
3296 LC = RTLIB::SDIV_I128;
3297 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported SDIV!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3297, __PRETTY_FUNCTION__))
;
3298
3299 TargetLowering::MakeLibCallOptions CallOptions;
3300 CallOptions.setSExt(true);
3301 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3302}
3303
3304void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
3305 SDValue &Lo, SDValue &Hi) {
3306 EVT VT = N->getValueType(0);
3307 SDLoc dl(N);
3308
3309 // If we can emit an efficient shift operation, do so now. Check to see if
3310 // the RHS is a constant.
3311 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
7
Assuming 'CN' is null
8
Taking false branch
3312 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
3313
3314 // If we can determine that the high bit of the shift is zero or one, even if
3315 // the low bits are variable, emit this shift in an optimized form.
3316 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
9
Calling 'DAGTypeLegalizer::ExpandShiftWithKnownAmountBit'
3317 return;
3318
3319 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
3320 unsigned PartsOpc;
3321 if (N->getOpcode() == ISD::SHL) {
3322 PartsOpc = ISD::SHL_PARTS;
3323 } else if (N->getOpcode() == ISD::SRL) {
3324 PartsOpc = ISD::SRL_PARTS;
3325 } else {
3326 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")((N->getOpcode() == ISD::SRA && "Unknown shift!") ?
static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3326, __PRETTY_FUNCTION__))
;
3327 PartsOpc = ISD::SRA_PARTS;
3328 }
3329
3330 // Next check to see if the target supports this SHL_PARTS operation or if it
3331 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
3332 // size, but create a libcall instead.
3333 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3334 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
3335 const bool LegalOrCustom =
3336 (Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3337 Action == TargetLowering::Custom;
3338
3339 if (LegalOrCustom && TLI.shouldExpandShift(DAG, N)) {
3340 // Expand the subcomponents.
3341 SDValue LHSL, LHSH;
3342 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
3343 EVT VT = LHSL.getValueType();
3344
3345 // If the shift amount operand is coming from a vector legalization it may
3346 // have an illegal type. Fix that first by casting the operand, otherwise
3347 // the new SHL_PARTS operation would need further legalization.
3348 SDValue ShiftOp = N->getOperand(1);
3349 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3350 assert(ShiftTy.getScalarSizeInBits() >=((ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits
()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? static_cast<void> (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3352, __PRETTY_FUNCTION__))
3351 Log2_32_Ceil(VT.getScalarSizeInBits()) &&((ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits
()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? static_cast<void> (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3352, __PRETTY_FUNCTION__))
3352 "ShiftAmountTy is too small to cover the range of this type!")((ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits
()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? static_cast<void> (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3352, __PRETTY_FUNCTION__))
;
3353 if (ShiftOp.getValueType() != ShiftTy)
3354 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
3355
3356 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
3357 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
3358 Hi = Lo.getValue(1);
3359 return;
3360 }
3361
3362 // Otherwise, emit a libcall.
3363 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3364 bool isSigned;
3365 if (N->getOpcode() == ISD::SHL) {
3366 isSigned = false; /*sign irrelevant*/
3367 if (VT == MVT::i16)
3368 LC = RTLIB::SHL_I16;
3369 else if (VT == MVT::i32)
3370 LC = RTLIB::SHL_I32;
3371 else if (VT == MVT::i64)
3372 LC = RTLIB::SHL_I64;
3373 else if (VT == MVT::i128)
3374 LC = RTLIB::SHL_I128;
3375 } else if (N->getOpcode() == ISD::SRL) {
3376 isSigned = false;
3377 if (VT == MVT::i16)
3378 LC = RTLIB::SRL_I16;
3379 else if (VT == MVT::i32)
3380 LC = RTLIB::SRL_I32;
3381 else if (VT == MVT::i64)
3382 LC = RTLIB::SRL_I64;
3383 else if (VT == MVT::i128)
3384 LC = RTLIB::SRL_I128;
3385 } else {
3386 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")((N->getOpcode() == ISD::SRA && "Unknown shift!") ?
static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3386, __PRETTY_FUNCTION__))
;
3387 isSigned = true;
3388 if (VT == MVT::i16)
3389 LC = RTLIB::SRA_I16;
3390 else if (VT == MVT::i32)
3391 LC = RTLIB::SRA_I32;
3392 else if (VT == MVT::i64)
3393 LC = RTLIB::SRA_I64;
3394 else if (VT == MVT::i128)
3395 LC = RTLIB::SRA_I128;
3396 }
3397
3398 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
3399 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3400 TargetLowering::MakeLibCallOptions CallOptions;
3401 CallOptions.setSExt(isSigned);
3402 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3403 return;
3404 }
3405
3406 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
3407 llvm_unreachable("Unsupported shift!")::llvm::llvm_unreachable_internal("Unsupported shift!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3407)
;
3408}
3409
3410void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
3411 SDValue &Lo, SDValue &Hi) {
3412 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3413 SDLoc dl(N);
3414 SDValue Op = N->getOperand(0);
3415 if (Op.getValueType().bitsLE(NVT)) {
3416 // The low part is sign extension of the input (degenerates to a copy).
3417 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
3418 // The high part is obtained by SRA'ing all but one of the bits of low part.
3419 unsigned LoSize = NVT.getSizeInBits();
3420 Hi = DAG.getNode(
3421 ISD::SRA, dl, NVT, Lo,
3422 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
3423 } else {
3424 // For example, extension of an i48 to an i64. The operand type necessarily
3425 // promotes to the result type, so will end up being expanded too.
3426 assert(getTypeAction(Op.getValueType()) ==((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3428, __PRETTY_FUNCTION__))
3427 TargetLowering::TypePromoteInteger &&((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3428, __PRETTY_FUNCTION__))
3428 "Only know how to promote this result!")((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3428, __PRETTY_FUNCTION__))
;
3429 SDValue Res = GetPromotedInteger(Op);
3430 assert(Res.getValueType() == N->getValueType(0) &&((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3431, __PRETTY_FUNCTION__))
3431 "Operand over promoted?")((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3431, __PRETTY_FUNCTION__))
;
3432 // Split the promoted operand. This will simplify when it is expanded.
3433 SplitInteger(Res, Lo, Hi);
3434 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
3435 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
3436 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
3437 ExcessBits)));
3438 }
3439}
3440
3441void DAGTypeLegalizer::
3442ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
3443 SDLoc dl(N);
3444 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3445 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3446
3447 if (EVT.bitsLE(Lo.getValueType())) {
3448 // sext_inreg the low part if needed.
3449 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
3450 N->getOperand(1));
3451
3452 // The high part gets the sign extension from the lo-part. This handles
3453 // things like sextinreg V:i64 from i8.
3454 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
3455 DAG.getConstant(Hi.getValueSizeInBits() - 1, dl,
3456 TLI.getPointerTy(DAG.getDataLayout())));
3457 } else {
3458 // For example, extension of an i48 to an i64. Leave the low part alone,
3459 // sext_inreg the high part.
3460 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
3461 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
3462 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
3463 ExcessBits)));
3464 }
3465}
3466
3467void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
3468 SDValue &Lo, SDValue &Hi) {
3469 EVT VT = N->getValueType(0);
3470 SDLoc dl(N);
3471 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3472
3473 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3474 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3475 SplitInteger(Res.getValue(1), Lo, Hi);
3476 return;
3477 }
3478
3479 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3480 if (VT == MVT::i16)
3481 LC = RTLIB::SREM_I16;
3482 else if (VT == MVT::i32)
3483 LC = RTLIB::SREM_I32;
3484 else if (VT == MVT::i64)
3485 LC = RTLIB::SREM_I64;
3486 else if (VT == MVT::i128)
3487 LC = RTLIB::SREM_I128;
3488 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported SREM!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3488, __PRETTY_FUNCTION__))
;
3489
3490 TargetLowering::MakeLibCallOptions CallOptions;
3491 CallOptions.setSExt(true);
3492 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3493}
3494
3495void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
3496 SDValue &Lo, SDValue &Hi) {
3497 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3498 SDLoc dl(N);
3499 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
3500 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
3501 N->getOperand(0),
3502 DAG.getConstant(NVT.getSizeInBits(), dl,
3503 TLI.getPointerTy(DAG.getDataLayout())));
3504 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
3505}
3506
3507void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
3508 SDValue &Lo, SDValue &Hi) {
3509 EVT VT = N->getValueType(0);
3510 SDLoc dl(N);
3511
3512 if (N->getOpcode() == ISD::UMULO) {
3513 // This section expands the operation into the following sequence of
3514 // instructions. `iNh` here refers to a type which has half the bit width of
3515 // the type the original operation operated on.
3516 //
3517 // %0 = %LHS.HI != 0 && %RHS.HI != 0
3518 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
3519 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
3520 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
3521 // %4 = add iN (%1.0 as iN) << Nh, (%2.0 as iN) << Nh
3522 // %5 = { iN, i1 } @uadd.with.overflow.iN( %4, %3 )
3523 //
3524 // %res = { %5.0, %0 || %1.1 || %2.1 || %5.1 }
3525 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
3526 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
3527 SplitInteger(LHS, LHSLow, LHSHigh);
3528 SplitInteger(RHS, RHSLow, RHSHigh);
3529 EVT HalfVT = LHSLow.getValueType()
3530 , BitVT = N->getValueType(1);
3531 SDVTList VTHalfMulO = DAG.getVTList(HalfVT, BitVT);
3532 SDVTList VTFullAddO = DAG.getVTList(VT, BitVT);
3533
3534 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT);
3535 SDValue Overflow = DAG.getNode(ISD::AND, dl, BitVT,
3536 DAG.getSetCC(dl, BitVT, LHSHigh, HalfZero, ISD::SETNE),
3537 DAG.getSetCC(dl, BitVT, RHSHigh, HalfZero, ISD::SETNE));
3538
3539 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, LHSHigh, RHSLow);
3540 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, One.getValue(1));
3541 SDValue OneInHigh = DAG.getNode(ISD::BUILD_PAIR, dl, VT, HalfZero,
3542 One.getValue(0));
3543
3544 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, RHSHigh, LHSLow);
3545 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Two.getValue(1));
3546 SDValue TwoInHigh = DAG.getNode(ISD::BUILD_PAIR, dl, VT, HalfZero,
3547 Two.getValue(0));
3548
3549 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
3550 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
3551 // operation recursively legalized?).
3552 //
3553 // Many backends understand this pattern and will convert into LOHI
3554 // themselves, if applicable.
3555 SDValue Three = DAG.getNode(ISD::MUL, dl, VT,
3556 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LHSLow),
3557 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RHSLow));
3558 SDValue Four = DAG.getNode(ISD::ADD, dl, VT, OneInHigh, TwoInHigh);
3559 SDValue Five = DAG.getNode(ISD::UADDO, dl, VTFullAddO, Three, Four);
3560 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Five.getValue(1));
3561 SplitInteger(Five, Lo, Hi);
3562 ReplaceValueWith(SDValue(N, 1), Overflow);
3563 return;
3564 }
3565
3566 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
3567 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
3568 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
3569
3570 // Replace this with a libcall that will check overflow.
3571 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3572 if (VT == MVT::i32)
3573 LC = RTLIB::MULO_I32;
3574 else if (VT == MVT::i64)
3575 LC = RTLIB::MULO_I64;
3576 else if (VT == MVT::i128)
3577 LC = RTLIB::MULO_I128;
3578 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported XMULO!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3578, __PRETTY_FUNCTION__))
;
3579
3580 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
3581 // Temporary for the overflow value, default it to zero.
3582 SDValue Chain =
3583 DAG.getStore(DAG.getEntryNode(), dl, DAG.getConstant(0, dl, PtrVT), Temp,
3584 MachinePointerInfo());
3585
3586 TargetLowering::ArgListTy Args;
3587 TargetLowering::ArgListEntry Entry;
3588 for (const SDValue &Op : N->op_values()) {
3589 EVT ArgVT = Op.getValueType();
3590 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
3591 Entry.Node = Op;
3592 Entry.Ty = ArgTy;
3593 Entry.IsSExt = true;
3594 Entry.IsZExt = false;
3595 Args.push_back(Entry);
3596 }
3597
3598 // Also pass the address of the overflow check.
3599 Entry.Node = Temp;
3600 Entry.Ty = PtrTy->getPointerTo();
3601 Entry.IsSExt = true;
3602 Entry.IsZExt = false;
3603 Args.push_back(Entry);
3604
3605 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
3606
3607 TargetLowering::CallLoweringInfo CLI(DAG);
3608 CLI.setDebugLoc(dl)
3609 .setChain(Chain)
3610 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args))
3611 .setSExtResult();
3612
3613 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
3614
3615 SplitInteger(CallInfo.first, Lo, Hi);
3616 SDValue Temp2 =
3617 DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, MachinePointerInfo());
3618 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
3619 DAG.getConstant(0, dl, PtrVT),
3620 ISD::SETNE);
3621 // Use the overflow from the libcall everywhere.
3622 ReplaceValueWith(SDValue(N, 1), Ofl);
3623}
3624
3625void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
3626 SDValue &Lo, SDValue &Hi) {
3627 EVT VT = N->getValueType(0);
3628 SDLoc dl(N);
3629 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3630
3631 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
3632 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3633 SplitInteger(Res.getValue(0), Lo, Hi);
3634 return;
3635 }
3636
3637 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3638 if (VT == MVT::i16)
3639 LC = RTLIB::UDIV_I16;
3640 else if (VT == MVT::i32)
3641 LC = RTLIB::UDIV_I32;
3642 else if (VT == MVT::i64)
3643 LC = RTLIB::UDIV_I64;
3644 else if (VT == MVT::i128)
3645 LC = RTLIB::UDIV_I128;
3646 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported UDIV!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3646, __PRETTY_FUNCTION__))
;
3647
3648 TargetLowering::MakeLibCallOptions CallOptions;
3649 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3650}
3651
3652void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
3653 SDValue &Lo, SDValue &Hi) {
3654 EVT VT = N->getValueType(0);
3655 SDLoc dl(N);
3656 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3657
3658 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
3659 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3660 SplitInteger(Res.getValue(1), Lo, Hi);
3661 return;
3662 }
3663
3664 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3665 if (VT == MVT::i16)
3666 LC = RTLIB::UREM_I16;
3667 else if (VT == MVT::i32)
3668 LC = RTLIB::UREM_I32;
3669 else if (VT == MVT::i64)
3670 LC = RTLIB::UREM_I64;
3671 else if (VT == MVT::i128)
3672 LC = RTLIB::UREM_I128;
3673 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported UREM!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3673, __PRETTY_FUNCTION__))
;
3674
3675 TargetLowering::MakeLibCallOptions CallOptions;
3676 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3677}
3678
3679void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
3680 SDValue &Lo, SDValue &Hi) {
3681 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3682 SDLoc dl(N);
3683 SDValue Op = N->getOperand(0);
3684 if (Op.getValueType().bitsLE(NVT)) {
3685 // The low part is zero extension of the input (degenerates to a copy).
3686 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
3687 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
3688 } else {
3689 // For example, extension of an i48 to an i64. The operand type necessarily
3690 // promotes to the result type, so will end up being expanded too.
3691 assert(getTypeAction(Op.getValueType()) ==((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3693, __PRETTY_FUNCTION__))
3692 TargetLowering::TypePromoteInteger &&((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3693, __PRETTY_FUNCTION__))
3693 "Only know how to promote this result!")((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3693, __PRETTY_FUNCTION__))
;
3694 SDValue Res = GetPromotedInteger(Op);
3695 assert(Res.getValueType() == N->getValueType(0) &&((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3696, __PRETTY_FUNCTION__))
3696 "Operand over promoted?")((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3696, __PRETTY_FUNCTION__))
;
3697 // Split the promoted operand. This will simplify when it is expanded.
3698 SplitInteger(Res, Lo, Hi);
3699 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
3700 Hi = DAG.getZeroExtendInReg(Hi, dl,
3701 EVT::getIntegerVT(*DAG.getContext(),
3702 ExcessBits));
3703 }
3704}
3705
3706void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
3707 SDValue &Lo, SDValue &Hi) {
3708 SDLoc dl(N);
3709 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
3710 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
3711 SDValue Zero = DAG.getConstant(0, dl, VT);
3712 SDValue Swap = DAG.getAtomicCmpSwap(
3713 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
3714 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
3715 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand());
3716
3717 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
3718 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
3719}
3720
3721void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
3722 SDValue &Lo, SDValue &Hi) {
3723 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
3724 // both halves independently.
3725 SDValue Res = TLI.expandVecReduce(N, DAG);
3726 SplitInteger(Res, Lo, Hi);
3727}
3728
3729//===----------------------------------------------------------------------===//
3730// Integer Operand Expansion
3731//===----------------------------------------------------------------------===//
3732
3733/// ExpandIntegerOperand - This method is called when the specified operand of
3734/// the specified node is found to need expansion. At this point, all of the
3735/// result types of the node are known to be legal, but other operands of the
3736/// node may need promotion or expansion as well as the specified one.
3737bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
3738 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
3739 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
3740 SDValue Res = SDValue();
3741
3742 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3743 return false;
3744
3745 switch (N->getOpcode()) {
3746 default:
3747 #ifndef NDEBUG
3748 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
3749 N->dump(&DAG); dbgs() << "\n";
3750 #endif
3751 report_fatal_error("Do not know how to expand this operator's operand!");
3752
3753 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
3754 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
3755 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
3756 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
3757 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
3758 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
3759 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
3760 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
3761 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
3762 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
3763 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
3764 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
3765 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
3766
3767 case ISD::SHL:
3768 case ISD::SRA:
3769 case ISD::SRL:
3770 case ISD::ROTL:
3771 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
3772 case ISD::RETURNADDR:
3773 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
3774
3775 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
3776 }
3777
3778 // If the result is null, the sub-method took care of registering results etc.
3779 if (!Res.getNode()) return false;
3780
3781 // If the result is N, the sub-method updated N in place. Tell the legalizer
3782 // core about this.
3783 if (Res.getNode() == N)
3784 return true;
3785
3786 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3787, __PRETTY_FUNCTION__))
3787 "Invalid operand expansion")((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3787, __PRETTY_FUNCTION__))
;
3788
3789 ReplaceValueWith(SDValue(N, 0), Res);
3790 return false;
3791}
3792
3793/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
3794/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
3795void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
3796 SDValue &NewRHS,
3797 ISD::CondCode &CCCode,
3798 const SDLoc &dl) {
3799 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
3800 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
3801 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
3802
3803 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
3804 if (RHSLo == RHSHi) {
3805 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
3806 if (RHSCST->isAllOnesValue()) {
3807 // Equality comparison to -1.
3808 NewLHS = DAG.getNode(ISD::AND, dl,
3809 LHSLo.getValueType(), LHSLo, LHSHi);
3810 NewRHS = RHSLo;
3811 return;
3812 }
3813 }
3814 }
3815
3816 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
3817 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
3818 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
3819 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
3820 return;
3821 }
3822
3823 // If this is a comparison of the sign bit, just look at the top part.
3824 // X > -1, x < 0
3825 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
3826 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
3827 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
3828 NewLHS = LHSHi;
3829 NewRHS = RHSHi;
3830 return;
3831 }
3832
3833 // FIXME: This generated code sucks.
3834 ISD::CondCode LowCC;
3835 switch (CCCode) {
3836 default: llvm_unreachable("Unknown integer setcc!")::llvm::llvm_unreachable_internal("Unknown integer setcc!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3836)
;
3837 case ISD::SETLT:
3838 case ISD::SETULT: LowCC = ISD::SETULT; break;
3839 case ISD::SETGT:
3840 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3841 case ISD::SETLE:
3842 case ISD::SETULE: LowCC = ISD::SETULE; break;
3843 case ISD::SETGE:
3844 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3845 }
3846
3847 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
3848 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
3849 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
3850
3851 // NOTE: on targets without efficient SELECT of bools, we can always use
3852 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3853 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
3854 nullptr);
3855 SDValue LoCmp, HiCmp;
3856 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
3857 TLI.isTypeLegal(RHSLo.getValueType()))
3858 LoCmp = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()), LHSLo,
3859 RHSLo, LowCC, false, DagCombineInfo, dl);
3860 if (!LoCmp.getNode())
3861 LoCmp = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo,
3862 RHSLo, LowCC);
3863 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
3864 TLI.isTypeLegal(RHSHi.getValueType()))
3865 HiCmp = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()), LHSHi,
3866 RHSHi, CCCode, false, DagCombineInfo, dl);
3867 if (!HiCmp.getNode())
3868 HiCmp =
3869 DAG.getNode(ISD::SETCC, dl, getSetCCResultType(LHSHi.getValueType()),
3870 LHSHi, RHSHi, DAG.getCondCode(CCCode));
3871
3872 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(LoCmp.getNode());
3873 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(HiCmp.getNode());
3874
3875 bool EqAllowed = (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
3876 CCCode == ISD::SETUGE || CCCode == ISD::SETULE);
3877
3878 if ((EqAllowed && (HiCmpC && HiCmpC->isNullValue())) ||
3879 (!EqAllowed && ((HiCmpC && (HiCmpC->getAPIntValue() == 1)) ||
3880 (LoCmpC && LoCmpC->isNullValue())))) {
3881 // For LE / GE, if high part is known false, ignore the low part.
3882 // For LT / GT: if low part is known false, return the high part.
3883 // if high part is known true, ignore the low part.
3884 NewLHS = HiCmp;
3885 NewRHS = SDValue();
3886 return;
3887 }
3888
3889 if (LHSHi == RHSHi) {
3890 // Comparing the low bits is enough.
3891 NewLHS = LoCmp;
3892 NewRHS = SDValue();
3893 return;
3894 }
3895
3896 // Lower with SETCCCARRY if the target supports it.
3897 EVT HiVT = LHSHi.getValueType();
3898 EVT ExpandVT = TLI.getTypeToExpandTo(*DAG.getContext(), HiVT);
3899 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(ISD::SETCCCARRY, ExpandVT);
3900
3901 // FIXME: Make all targets support this, then remove the other lowering.
3902 if (HasSETCCCARRY) {
3903 // SETCCCARRY can detect < and >= directly. For > and <=, flip
3904 // operands and condition code.
3905 bool FlipOperands = false;
3906 switch (CCCode) {
3907 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
3908 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
3909 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
3910 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
3911 default: break;
3912 }
3913 if (FlipOperands) {
3914 std::swap(LHSLo, RHSLo);
3915 std::swap(LHSHi, RHSHi);
3916 }
3917 // Perform a wide subtraction, feeding the carry from the low part into
3918 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
3919 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
3920 // zero or positive iff LHS >= RHS.
3921 EVT LoVT = LHSLo.getValueType();
3922 SDVTList VTList = DAG.getVTList(LoVT, getSetCCResultType(LoVT));
3923 SDValue LowCmp = DAG.getNode(ISD::USUBO, dl, VTList, LHSLo, RHSLo);
3924 SDValue Res = DAG.getNode(ISD::SETCCCARRY, dl, getSetCCResultType(HiVT),
3925 LHSHi, RHSHi, LowCmp.getValue(1),
3926 DAG.getCondCode(CCCode));
3927 NewLHS = Res;
3928 NewRHS = SDValue();
3929 return;
3930 }
3931
3932 NewLHS = TLI.SimplifySetCC(getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ,
3933 false, DagCombineInfo, dl);
3934 if (!NewLHS.getNode())
3935 NewLHS =
3936 DAG.getSetCC(dl, getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ);
3937 NewLHS = DAG.getSelect(dl, LoCmp.getValueType(), NewLHS, LoCmp, HiCmp);
3938 NewRHS = SDValue();
3939}
3940
3941SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
3942 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
3943 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
3944 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
3945
3946 // If ExpandSetCCOperands returned a scalar, we need to compare the result
3947 // against zero to select between true and false values.
3948 if (!NewRHS.getNode()) {
3949 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
3950 CCCode = ISD::SETNE;
3951 }
3952
3953 // Update N to have the operands specified.
3954 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
3955 DAG.getCondCode(CCCode), NewLHS, NewRHS,
3956 N->getOperand(4)), 0);
3957}
3958
3959SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
3960 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
3961 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
3962 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
3963
3964 // If ExpandSetCCOperands returned a scalar, we need to compare the result
3965 // against zero to select between true and false values.
3966 if (!NewRHS.getNode()) {
3967 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
3968 CCCode = ISD::SETNE;
3969 }
3970
3971 // Update N to have the operands specified.
3972 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
3973 N->getOperand(2), N->getOperand(3),
3974 DAG.getCondCode(CCCode)), 0);
3975}
3976
3977SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
3978 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
3979 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
3980 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
3981
3982 // If ExpandSetCCOperands returned a scalar, use it.
3983 if (!NewRHS.getNode()) {
3984 assert(NewLHS.getValueType() == N->getValueType(0) &&((NewLHS.getValueType() == N->getValueType(0) && "Unexpected setcc expansion!"
) ? static_cast<void> (0) : __assert_fail ("NewLHS.getValueType() == N->getValueType(0) && \"Unexpected setcc expansion!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3985, __PRETTY_FUNCTION__))
3985 "Unexpected setcc expansion!")((NewLHS.getValueType() == N->getValueType(0) && "Unexpected setcc expansion!"
) ? static_cast<void> (0) : __assert_fail ("NewLHS.getValueType() == N->getValueType(0) && \"Unexpected setcc expansion!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3985, __PRETTY_FUNCTION__))
;
3986 return NewLHS;
3987 }
3988
3989 // Otherwise, update N to have the operands specified.
3990 return SDValue(
3991 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0);
3992}
3993
3994SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
3995 SDValue LHS = N->getOperand(0);
3996 SDValue RHS = N->getOperand(1);
3997 SDValue Carry = N->getOperand(2);
3998 SDValue Cond = N->getOperand(3);
3999 SDLoc dl = SDLoc(N);
4000
4001 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4002 GetExpandedInteger(LHS, LHSLo, LHSHi);
4003 GetExpandedInteger(RHS, RHSLo, RHSHi);
4004
4005 // Expand to a SUBE for the low part and a smaller SETCCCARRY for the high.
4006 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), Carry.getValueType());
4007 SDValue LowCmp = DAG.getNode(ISD::SUBCARRY, dl, VTList, LHSLo, RHSLo, Carry);
4008 return DAG.getNode(ISD::SETCCCARRY, dl, N->getValueType(0), LHSHi, RHSHi,
4009 LowCmp.getValue(1), Cond);
4010}
4011
4012SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
4013 // The value being shifted is legal, but the shift amount is too big.
4014 // It follows that either the result of the shift is undefined, or the
4015 // upper half of the shift amount is zero. Just use the lower half.
4016 SDValue Lo, Hi;
4017 GetExpandedInteger(N->getOperand(1), Lo, Hi);
4018 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
4019}
4020
4021SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
4022 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
4023 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
4024 // constant to valid type.
4025 SDValue Lo, Hi;
4026 GetExpandedInteger(N->getOperand(0), Lo, Hi);
4027 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
4028}
4029
4030SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
4031 SDValue Op = N->getOperand(0);
4032 EVT DstVT = N->getValueType(0);
4033 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
4034 assert(LC != RTLIB::UNKNOWN_LIBCALL &&((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this SINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this SINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4035, __PRETTY_FUNCTION__))
4035 "Don't know how to expand this SINT_TO_FP!")((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this SINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this SINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4035, __PRETTY_FUNCTION__))
;
4036 TargetLowering::MakeLibCallOptions CallOptions;
4037 CallOptions.setSExt(true);
4038 return TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N)).first;
4039}
4040
4041SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
4042 if (N->isAtomic()) {
4043 // It's typical to have larger CAS than atomic store instructions.
4044 SDLoc dl(N);
4045 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
4046 N->getMemoryVT(),
4047 N->getOperand(0), N->getOperand(2),
4048 N->getOperand(1),
4049 N->getMemOperand());
4050 return Swap.getValue(1);
4051 }
4052 if (ISD::isNormalStore(N))
4053 return ExpandOp_NormalStore(N, OpNo);
4054
4055 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!")((ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDStore(N) && \"Indexed store during type legalization!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4055, __PRETTY_FUNCTION__))
;
4056 assert(OpNo == 1 && "Can only expand the stored value so far")((OpNo == 1 && "Can only expand the stored value so far"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 1 && \"Can only expand the stored value so far\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4056, __PRETTY_FUNCTION__))
;
4057
4058 EVT VT = N->getOperand(1).getValueType();
4059 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4060 SDValue Ch = N->getChain();
4061 SDValue Ptr = N->getBasePtr();
4062 unsigned Alignment = N->getAlignment();
4063 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4064 AAMDNodes AAInfo = N->getAAInfo();
4065 SDLoc dl(N);
4066 SDValue Lo, Hi;
4067
4068 assert(NVT.isByteSized() && "Expanded type not byte sized!")((NVT.isByteSized() && "Expanded type not byte sized!"
) ? static_cast<void> (0) : __assert_fail ("NVT.isByteSized() && \"Expanded type not byte sized!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4068, __PRETTY_FUNCTION__))
;
4069
4070 if (N->getMemoryVT().bitsLE(NVT)) {
4071 GetExpandedInteger(N->getValue(), Lo, Hi);
4072 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
4073 N->getMemoryVT(), Alignment, MMOFlags, AAInfo);
4074 }
4075
4076 if (DAG.getDataLayout().isLittleEndian()) {
4077 // Little-endian - low bits are at low addresses.
4078 GetExpandedInteger(N->getValue(), Lo, Hi);
4079
4080 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
4081 AAInfo);
4082
4083 unsigned ExcessBits =
4084 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4085 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
4086
4087 // Increment the pointer to the other half.
4088 unsigned IncrementSize = NVT.getSizeInBits()/8;
4089 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
4090 Hi = DAG.getTruncStore(
4091 Ch, dl, Hi, Ptr, N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
4092 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
4093 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
4094 }
4095
4096 // Big-endian - high bits are at low addresses. Favor aligned stores at
4097 // the cost of some bit-fiddling.
4098 GetExpandedInteger(N->getValue(), Lo, Hi);
4099
4100 EVT ExtVT = N->getMemoryVT();
4101 unsigned EBytes = ExtVT.getStoreSize();
4102 unsigned IncrementSize = NVT.getSizeInBits()/8;
4103 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4104 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
4105 ExtVT.getSizeInBits() - ExcessBits);
4106
4107 if (ExcessBits < NVT.getSizeInBits()) {
4108 // Transfer high bits from the top of Lo to the bottom of Hi.
4109 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
4110 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
4111 TLI.getPointerTy(DAG.getDataLayout())));
4112 Hi = DAG.getNode(
4113 ISD::OR, dl, NVT, Hi,
4114 DAG.getNode(ISD::SRL, dl, NVT, Lo,
4115 DAG.getConstant(ExcessBits, dl,
4116 TLI.getPointerTy(DAG.getDataLayout()))));
4117 }
4118
4119 // Store both the high bits and maybe some of the low bits.
4120 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), HiVT, Alignment,
4121 MMOFlags, AAInfo);
4122
4123 // Increment the pointer to the other half.
4124 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
4125 // Store the lowest ExcessBits bits in the second half.
4126 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
4127 N->getPointerInfo().getWithOffset(IncrementSize),
4128 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
4129 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
4130 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
4131}
4132
4133SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
4134 SDValue InL, InH;
4135 GetExpandedInteger(N->getOperand(0), InL, InH);
4136 // Just truncate the low part of the source.
4137 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
4138}
4139
4140SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
4141 SDValue Op = N->getOperand(0);
4142 EVT SrcVT = Op.getValueType();
4143 EVT DstVT = N->getValueType(0);
4144 SDLoc dl(N);
4145
4146 // The following optimization is valid only if every value in SrcVT (when
4147 // treated as signed) is representable in DstVT. Check that the mantissa
4148 // size of DstVT is >= than the number of bits in SrcVT -1.
4149 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
4150 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
4151 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
4152 // Do a signed conversion then adjust the result.
4153 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
4154 SignedConv = TLI.LowerOperation(SignedConv, DAG);
4155
4156 // The result of the signed conversion needs adjusting if the 'sign bit' of
4157 // the incoming integer was set. To handle this, we dynamically test to see
4158 // if it is set, and, if so, add a fudge factor.
4159
4160 const uint64_t F32TwoE32 = 0x4F800000ULL;
4161 const uint64_t F32TwoE64 = 0x5F800000ULL;
4162 const uint64_t F32TwoE128 = 0x7F800000ULL;
4163
4164 APInt FF(32, 0);
4165 if (SrcVT == MVT::i32)
4166 FF = APInt(32, F32TwoE32);
4167 else if (SrcVT == MVT::i64)
4168 FF = APInt(32, F32TwoE64);
4169 else if (SrcVT == MVT::i128)
4170 FF = APInt(32, F32TwoE128);
4171 else
4172 llvm_unreachable("Unsupported UINT_TO_FP!")::llvm::llvm_unreachable_internal("Unsupported UINT_TO_FP!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4172)
;
4173
4174 // Check whether the sign bit is set.
4175 SDValue Lo, Hi;
4176 GetExpandedInteger(Op, Lo, Hi);
4177 SDValue SignSet = DAG.getSetCC(dl,
4178 getSetCCResultType(Hi.getValueType()),
4179 Hi,
4180 DAG.getConstant(0, dl, Hi.getValueType()),
4181 ISD::SETLT);
4182
4183 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
4184 SDValue FudgePtr =
4185 DAG.getConstantPool(ConstantInt::get(*DAG.getContext(), FF.zext(64)),
4186 TLI.getPointerTy(DAG.getDataLayout()));
4187
4188 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
4189 SDValue Zero = DAG.getIntPtrConstant(0, dl);
4190 SDValue Four = DAG.getIntPtrConstant(4, dl);
4191 if (DAG.getDataLayout().isBigEndian())
4192 std::swap(Zero, Four);
4193 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
4194 Zero, Four);
4195 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
4196 FudgePtr = DAG.getMemBasePlusOffset(FudgePtr, Offset, dl);
4197 Alignment = std::min(Alignment, 4u);
4198
4199 // Load the value out, extending it from f32 to the destination float type.
4200 // FIXME: Avoid the extend by constructing the right constant pool?
4201 SDValue Fudge = DAG.getExtLoad(
4202 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr,
4203 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
4204 Alignment);
4205 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
4206 }
4207
4208 // Otherwise, use a libcall.
4209 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
4210 assert(LC != RTLIB::UNKNOWN_LIBCALL &&((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this UINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this UINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4211, __PRETTY_FUNCTION__))
4211 "Don't know how to expand this UINT_TO_FP!")((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this UINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this UINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4211, __PRETTY_FUNCTION__))
;
4212 TargetLowering::MakeLibCallOptions CallOptions;
4213 CallOptions.setSExt(true);
4214 return TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, dl).first;
4215}
4216
4217SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
4218 SDLoc dl(N);
4219 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
4220 cast<AtomicSDNode>(N)->getMemoryVT(),
4221 N->getOperand(0),
4222 N->getOperand(1), N->getOperand(2),
4223 cast<AtomicSDNode>(N)->getMemOperand());
4224 return Swap.getValue(1);
4225}
4226
4227
4228SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
4229
4230 EVT OutVT = N->getValueType(0);
4231 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4232 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4232, __PRETTY_FUNCTION__))
;
4233 unsigned OutNumElems = OutVT.getVectorNumElements();
4234 EVT NOutVTElem = NOutVT.getVectorElementType();
4235
4236 SDLoc dl(N);
4237 SDValue BaseIdx = N->getOperand(1);
4238
4239 SDValue InOp0 = N->getOperand(0);
4240 if (getTypeAction(InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
4241 InOp0 = GetPromotedInteger(N->getOperand(0));
4242
4243 EVT InVT = InOp0.getValueType();
4244
4245 SmallVector<SDValue, 8> Ops;
4246 Ops.reserve(OutNumElems);
4247 for (unsigned i = 0; i != OutNumElems; ++i) {
4248
4249 // Extract the element from the original vector.
4250 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
4251 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
4252 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4253 InVT.getVectorElementType(), N->getOperand(0), Index);
4254
4255 SDValue Op = DAG.getAnyExtOrTrunc(Ext, dl, NOutVTElem);
4256 // Insert the converted element to the new vector.
4257 Ops.push_back(Op);
4258 }
4259
4260 return DAG.getBuildVector(NOutVT, dl, Ops);
4261}
4262
4263
4264SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
4265 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
4266 EVT VT = N->getValueType(0);
4267 SDLoc dl(N);
4268
4269 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
4270
4271 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4272 SDValue V1 = GetPromotedInteger(N->getOperand(1));
4273 EVT OutVT = V0.getValueType();
4274
4275 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
4276}
4277
4278
4279SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
4280 EVT OutVT = N->getValueType(0);
4281 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4282 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4282, __PRETTY_FUNCTION__))
;
4283 unsigned NumElems = N->getNumOperands();
4284 EVT NOutVTElem = NOutVT.getVectorElementType();
4285
4286 SDLoc dl(N);
4287
4288 SmallVector<SDValue, 8> Ops;
4289 Ops.reserve(NumElems);
4290 for (unsigned i = 0; i != NumElems; ++i) {
4291 SDValue Op;
4292 // BUILD_VECTOR integer operand types are allowed to be larger than the
4293 // result's element type. This may still be true after the promotion. For
4294 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
4295 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
4296 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
4297 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
4298 else
4299 Op = N->getOperand(i);
4300 Ops.push_back(Op);
4301 }
4302
4303 return DAG.getBuildVector(NOutVT, dl, Ops);
4304}
4305
4306SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
4307
4308 SDLoc dl(N);
4309
4310 assert(!N->getOperand(0).getValueType().isVector() &&((!N->getOperand(0).getValueType().isVector() && "Input must be a scalar"
) ? static_cast<void> (0) : __assert_fail ("!N->getOperand(0).getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4311, __PRETTY_FUNCTION__))
4311 "Input must be a scalar")((!N->getOperand(0).getValueType().isVector() && "Input must be a scalar"
) ? static_cast<void> (0) : __assert_fail ("!N->getOperand(0).getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4311, __PRETTY_FUNCTION__))
;
4312
4313 EVT OutVT = N->getValueType(0);
4314 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4315 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4315, __PRETTY_FUNCTION__))
;
4316 EVT NOutVTElem = NOutVT.getVectorElementType();
4317
4318 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
4319
4320 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
4321}
4322
4323SDValue DAGTypeLegalizer::PromoteIntRes_SPLAT_VECTOR(SDNode *N) {
4324 SDLoc dl(N);
4325
4326 SDValue SplatVal = N->getOperand(0);
4327
4328 assert(!SplatVal.getValueType().isVector() && "Input must be a scalar")((!SplatVal.getValueType().isVector() && "Input must be a scalar"
) ? static_cast<void> (0) : __assert_fail ("!SplatVal.getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4328, __PRETTY_FUNCTION__))
;
4329
4330 EVT OutVT = N->getValueType(0);
4331 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4332 assert(NOutVT.isVector() && "Type must be promoted to a vector type")((NOutVT.isVector() && "Type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"Type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4332, __PRETTY_FUNCTION__))
;
4333 EVT NOutElemVT = NOutVT.getVectorElementType();
4334
4335 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutElemVT, SplatVal);
4336
4337 return DAG.getNode(ISD::SPLAT_VECTOR, dl, NOutVT, Op);
4338}
4339
4340SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
4341 SDLoc dl(N);
4342
4343 EVT OutVT = N->getValueType(0);
4344 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4345 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4345, __PRETTY_FUNCTION__))
;
4346
4347 EVT OutElemTy = NOutVT.getVectorElementType();
4348
4349 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
4350 unsigned NumOutElem = NOutVT.getVectorNumElements();
4351 unsigned NumOperands = N->getNumOperands();
4352 assert(NumElem * NumOperands == NumOutElem &&((NumElem * NumOperands == NumOutElem && "Unexpected number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElem * NumOperands == NumOutElem && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4353, __PRETTY_FUNCTION__))
4353 "Unexpected number of elements")((NumElem * NumOperands == NumOutElem && "Unexpected number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElem * NumOperands == NumOutElem && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4353, __PRETTY_FUNCTION__))
;
4354
4355 // Take the elements from the first vector.
4356 SmallVector<SDValue, 8> Ops(NumOutElem);
4357 for (unsigned i = 0; i < NumOperands; ++i) {
4358 SDValue Op = N->getOperand(i);
4359 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger)
4360 Op = GetPromotedInteger(Op);
4361 EVT SclrTy = Op.getValueType().getVectorElementType();
4362 assert(NumElem == Op.getValueType().getVectorNumElements() &&((NumElem == Op.getValueType().getVectorNumElements() &&
"Unexpected number of elements") ? static_cast<void> (
0) : __assert_fail ("NumElem == Op.getValueType().getVectorNumElements() && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4363, __PRETTY_FUNCTION__))
4363 "Unexpected number of elements")((NumElem == Op.getValueType().getVectorNumElements() &&
"Unexpected number of elements") ? static_cast<void> (
0) : __assert_fail ("NumElem == Op.getValueType().getVectorNumElements() && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4363, __PRETTY_FUNCTION__))
;
4364
4365 for (unsigned j = 0; j < NumElem; ++j) {
4366 SDValue Ext = DAG.getNode(
4367 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op,
4368 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4369 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Ext, dl, OutElemTy);
4370 }
4371 }
4372
4373 return DAG.getBuildVector(NOutVT, dl, Ops);
4374}
4375
4376SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
4377 EVT VT = N->getValueType(0);
4378 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4379 assert(NVT.isVector() && "This type must be promoted to a vector type")((NVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4379, __PRETTY_FUNCTION__))
;
4380
4381 SDLoc dl(N);
4382
4383 // For operands whose TypeAction is to promote, extend the promoted node
4384 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
4385 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
4386 // type..
4387 if (getTypeAction(N->getOperand(0).getValueType())
4388 == TargetLowering::TypePromoteInteger) {
4389 SDValue Promoted;
4390
4391 switch(N->getOpcode()) {
4392 case ISD::SIGN_EXTEND_VECTOR_INREG:
4393 Promoted = SExtPromotedInteger(N->getOperand(0));
4394 break;
4395 case ISD::ZERO_EXTEND_VECTOR_INREG:
4396 Promoted = ZExtPromotedInteger(N->getOperand(0));
4397 break;
4398 case ISD::ANY_EXTEND_VECTOR_INREG:
4399 Promoted = GetPromotedInteger(N->getOperand(0));
4400 break;
4401 default:
4402 llvm_unreachable("Node has unexpected Opcode")::llvm::llvm_unreachable_internal("Node has unexpected Opcode"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4402)
;
4403 }
4404 return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
4405 }
4406
4407 // Directly extend to the appropriate transform-to type.
4408 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
4409}
4410
4411SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
4412 EVT OutVT = N->getValueType(0);
4413 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4414 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4414, __PRETTY_FUNCTION__))
;
4415
4416 EVT NOutVTElem = NOutVT.getVectorElementType();
4417
4418 SDLoc dl(N);
4419 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4420
4421 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
4422 NOutVTElem, N->getOperand(1));
4423 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
4424 V0, ConvElem, N->getOperand(2));
4425}
4426
4427SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
4428 // The VECREDUCE result size may be larger than the element size, so
4429 // we can simply change the result type.
4430 SDLoc dl(N);
4431 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4432 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
4433}
4434
4435SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
4436 SDLoc dl(N);
4437 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4438 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
4439 TLI.getVectorIdxTy(DAG.getDataLayout()));
4440 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4441 V0->getValueType(0).getScalarType(), V0, V1);
4442
4443 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
4444 // element types. If this is the case then we need to expand the outgoing
4445 // value and not truncate it.
4446 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
4447}
4448
4449SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
4450 SDLoc dl(N);
4451 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4452 MVT InVT = V0.getValueType().getSimpleVT();
4453 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
4454 N->getValueType(0).getVectorNumElements());
4455 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
4456 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
4457}
4458
4459SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
4460 SDLoc dl(N);
4461 unsigned NumElems = N->getNumOperands();
4462
4463 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
4464
4465 SmallVector<SDValue, 8> NewOps;
4466 NewOps.reserve(NumElems);
4467
4468 // For each incoming vector
4469 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
4470 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
4471 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
4472 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
4473
4474 for (unsigned i=0; i<NumElem; ++i) {
4475 // Extract element from incoming vector
4476 SDValue Ex = DAG.getNode(
4477 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
4478 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4479 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
4480 NewOps.push_back(Tr);
4481 }
4482 }
4483
4484 return DAG.getBuildVector(N->getValueType(0), dl, NewOps);
4485}

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/Constants.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Instruction.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/Metadata.h"
39#include "llvm/IR/Operator.h"
40#include "llvm/Support/AlignOf.h"
41#include "llvm/Support/AtomicOrdering.h"
42#include "llvm/Support/Casting.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MachineValueType.h"
45#include "llvm/Support/TypeSize.h"
46#include <algorithm>
47#include <cassert>
48#include <climits>
49#include <cstddef>
50#include <cstdint>
51#include <cstring>
52#include <iterator>
53#include <string>
54#include <tuple>
55
56namespace llvm {
57
58class APInt;
59class Constant;
60template <typename T> struct DenseMapInfo;
61class GlobalValue;
62class MachineBasicBlock;
63class MachineConstantPoolValue;
64class MCSymbol;
65class raw_ostream;
66class SDNode;
67class SelectionDAG;
68class Type;
69class Value;
70
71void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
72 bool force = false);
73
74/// This represents a list of ValueType's that has been intern'd by
75/// a SelectionDAG. Instances of this simple value class are returned by
76/// SelectionDAG::getVTList(...).
77///
78struct SDVTList {
79 const EVT *VTs;
80 unsigned int NumVTs;
81};
82
83namespace ISD {
84
85 /// Node predicates
86
87 /// If N is a BUILD_VECTOR node whose elements are all the same constant or
88 /// undefined, return true and return the constant value in \p SplatValue.
89 bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
90
91 /// Return true if the specified node is a BUILD_VECTOR where all of the
92 /// elements are ~0 or undef.
93 bool isBuildVectorAllOnes(const SDNode *N);
94
95 /// Return true if the specified node is a BUILD_VECTOR where all of the
96 /// elements are 0 or undef.
97 bool isBuildVectorAllZeros(const SDNode *N);
98
99 /// Return true if the specified node is a BUILD_VECTOR node of all
100 /// ConstantSDNode or undef.
101 bool isBuildVectorOfConstantSDNodes(const SDNode *N);
102
103 /// Return true if the specified node is a BUILD_VECTOR node of all
104 /// ConstantFPSDNode or undef.
105 bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
106
107 /// Return true if the node has at least one operand and all operands of the
108 /// specified node are ISD::UNDEF.
109 bool allOperandsUndef(const SDNode *N);
110
111} // end namespace ISD
112
113//===----------------------------------------------------------------------===//
114/// Unlike LLVM values, Selection DAG nodes may return multiple
115/// values as the result of a computation. Many nodes return multiple values,
116/// from loads (which define a token and a return value) to ADDC (which returns
117/// a result and a carry value), to calls (which may return an arbitrary number
118/// of values).
119///
120/// As such, each use of a SelectionDAG computation must indicate the node that
121/// computes it as well as which return value to use from that node. This pair
122/// of information is represented with the SDValue value type.
123///
124class SDValue {
125 friend struct DenseMapInfo<SDValue>;
126
127 SDNode *Node = nullptr; // The node defining the value we are using.
128 unsigned ResNo = 0; // Which return value of the node we are using.
129
130public:
131 SDValue() = default;
132 SDValue(SDNode *node, unsigned resno);
133
134 /// get the index which selects a specific result in the SDNode
135 unsigned getResNo() const { return ResNo; }
136
137 /// get the SDNode which holds the desired result
138 SDNode *getNode() const { return Node; }
139
140 /// set the SDNode
141 void setNode(SDNode *N) { Node = N; }
142
143 inline SDNode *operator->() const { return Node; }
144
145 bool operator==(const SDValue &O) const {
146 return Node == O.Node && ResNo == O.ResNo;
147 }
148 bool operator!=(const SDValue &O) const {
149 return !operator==(O);
150 }
151 bool operator<(const SDValue &O) const {
152 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
153 }
154 explicit operator bool() const {
155 return Node != nullptr;
156 }
157
158 SDValue getValue(unsigned R) const {
159 return SDValue(Node, R);
160 }
161
162 /// Return true if this node is an operand of N.
163 bool isOperandOf(const SDNode *N) const;
164
165 /// Return the ValueType of the referenced return value.
166 inline EVT getValueType() const;
167
168 /// Return the simple ValueType of the referenced return value.
169 MVT getSimpleValueType() const {
170 return getValueType().getSimpleVT();
171 }
172
173 /// Returns the size of the value in bits.
174 ///
175 /// If the value type is a scalable vector type, the scalable property will
176 /// be set and the runtime size will be a positive integer multiple of the
177 /// base size.
178 TypeSize getValueSizeInBits() const {
179 return getValueType().getSizeInBits();
180 }
181
182 TypeSize getScalarValueSizeInBits() const {
183 return getValueType().getScalarType().getSizeInBits();
184 }
185
186 // Forwarding methods - These forward to the corresponding methods in SDNode.
187 inline unsigned getOpcode() const;
188 inline unsigned getNumOperands() const;
189 inline const SDValue &getOperand(unsigned i) const;
190 inline uint64_t getConstantOperandVal(unsigned i) const;
191 inline const APInt &getConstantOperandAPInt(unsigned i) const;
192 inline bool isTargetMemoryOpcode() const;
193 inline bool isTargetOpcode() const;
194 inline bool isMachineOpcode() const;
195 inline bool isUndef() const;
196 inline unsigned getMachineOpcode() const;
197 inline const DebugLoc &getDebugLoc() const;
198 inline void dump() const;
199 inline void dump(const SelectionDAG *G) const;
200 inline void dumpr() const;
201 inline void dumpr(const SelectionDAG *G) const;
202
203 /// Return true if this operand (which must be a chain) reaches the
204 /// specified operand without crossing any side-effecting instructions.
205 /// In practice, this looks through token factors and non-volatile loads.
206 /// In order to remain efficient, this only
207 /// looks a couple of nodes in, it does not do an exhaustive search.
208 bool reachesChainWithoutSideEffects(SDValue Dest,
209 unsigned Depth = 2) const;
210
211 /// Return true if there are no nodes using value ResNo of Node.
212 inline bool use_empty() const;
213
214 /// Return true if there is exactly one node using value ResNo of Node.
215 inline bool hasOneUse() const;
216};
217
218template<> struct DenseMapInfo<SDValue> {
219 static inline SDValue getEmptyKey() {
220 SDValue V;
221 V.ResNo = -1U;
222 return V;
223 }
224
225 static inline SDValue getTombstoneKey() {
226 SDValue V;
227 V.ResNo = -2U;
228 return V;
229 }
230
231 static unsigned getHashValue(const SDValue &Val) {
232 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
233 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
234 }
235
236 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
237 return LHS == RHS;
238 }
239};
240
241/// Allow casting operators to work directly on
242/// SDValues as if they were SDNode*'s.
243template<> struct simplify_type<SDValue> {
244 using SimpleType = SDNode *;
245
246 static SimpleType getSimplifiedValue(SDValue &Val) {
247 return Val.getNode();
248 }
249};
250template<> struct simplify_type<const SDValue> {
251 using SimpleType = /*const*/ SDNode *;
252
253 static SimpleType getSimplifiedValue(const SDValue &Val) {
254 return Val.getNode();
255 }
256};
257
258/// Represents a use of a SDNode. This class holds an SDValue,
259/// which records the SDNode being used and the result number, a
260/// pointer to the SDNode using the value, and Next and Prev pointers,
261/// which link together all the uses of an SDNode.
262///
263class SDUse {
264 /// Val - The value being used.
265 SDValue Val;
266 /// User - The user of this value.
267 SDNode *User = nullptr;
268 /// Prev, Next - Pointers to the uses list of the SDNode referred by
269 /// this operand.
270 SDUse **Prev = nullptr;
271 SDUse *Next = nullptr;
272
273public:
274 SDUse() = default;
275 SDUse(const SDUse &U) = delete;
276 SDUse &operator=(const SDUse &) = delete;
277
278 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
279 operator const SDValue&() const { return Val; }
280
281 /// If implicit conversion to SDValue doesn't work, the get() method returns
282 /// the SDValue.
283 const SDValue &get() const { return Val; }
284
285 /// This returns the SDNode that contains this Use.
286 SDNode *getUser() { return User; }
287
288 /// Get the next SDUse in the use list.
289 SDUse *getNext() const { return Next; }
290
291 /// Convenience function for get().getNode().
292 SDNode *getNode() const { return Val.getNode(); }
293 /// Convenience function for get().getResNo().
294 unsigned getResNo() const { return Val.getResNo(); }
295 /// Convenience function for get().getValueType().
296 EVT getValueType() const { return Val.getValueType(); }
297
298 /// Convenience function for get().operator==
299 bool operator==(const SDValue &V) const {
300 return Val == V;
301 }
302
303 /// Convenience function for get().operator!=
304 bool operator!=(const SDValue &V) const {
305 return Val != V;
306 }
307
308 /// Convenience function for get().operator<
309 bool operator<(const SDValue &V) const {
310 return Val < V;
311 }
312
313private:
314 friend class SelectionDAG;
315 friend class SDNode;
316 // TODO: unfriend HandleSDNode once we fix its operand handling.
317 friend class HandleSDNode;
318
319 void setUser(SDNode *p) { User = p; }
320
321 /// Remove this use from its existing use list, assign it the
322 /// given value, and add it to the new value's node's use list.
323 inline void set(const SDValue &V);
324 /// Like set, but only supports initializing a newly-allocated
325 /// SDUse with a non-null value.
326 inline void setInitial(const SDValue &V);
327 /// Like set, but only sets the Node portion of the value,
328 /// leaving the ResNo portion unmodified.
329 inline void setNode(SDNode *N);
330
331 void addToList(SDUse **List) {
332 Next = *List;
333 if (Next) Next->Prev = &Next;
334 Prev = List;
335 *List = this;
336 }
337
338 void removeFromList() {
339 *Prev = Next;
340 if (Next) Next->Prev = Prev;
341 }
342};
343
344/// simplify_type specializations - Allow casting operators to work directly on
345/// SDValues as if they were SDNode*'s.
346template<> struct simplify_type<SDUse> {
347 using SimpleType = SDNode *;
348
349 static SimpleType getSimplifiedValue(SDUse &Val) {
350 return Val.getNode();
351 }
352};
353
354/// These are IR-level optimization flags that may be propagated to SDNodes.
355/// TODO: This data structure should be shared by the IR optimizer and the
356/// the backend.
357struct SDNodeFlags {
358private:
359 // This bit is used to determine if the flags are in a defined state.
360 // Flag bits can only be masked out during intersection if the masking flags
361 // are defined.
362 bool AnyDefined : 1;
363
364 bool NoUnsignedWrap : 1;
365 bool NoSignedWrap : 1;
366 bool Exact : 1;
367 bool NoNaNs : 1;
368 bool NoInfs : 1;
369 bool NoSignedZeros : 1;
370 bool AllowReciprocal : 1;
371 bool VectorReduction : 1;
372 bool AllowContract : 1;
373 bool ApproximateFuncs : 1;
374 bool AllowReassociation : 1;
375
376 // We assume instructions do not raise floating-point exceptions by default,
377 // and only those marked explicitly may do so. We could choose to represent
378 // this via a positive "FPExcept" flags like on the MI level, but having a
379 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
380 // intersection logic more straightforward.
381 bool NoFPExcept : 1;
382
383public:
384 /// Default constructor turns off all optimization flags.
385 SDNodeFlags()
386 : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
387 Exact(false), NoNaNs(false), NoInfs(false),
388 NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
389 AllowContract(false), ApproximateFuncs(false),
390 AllowReassociation(false), NoFPExcept(false) {}
391
392 /// Propagate the fast-math-flags from an IR FPMathOperator.
393 void copyFMF(const FPMathOperator &FPMO) {
394 setNoNaNs(FPMO.hasNoNaNs());
395 setNoInfs(FPMO.hasNoInfs());
396 setNoSignedZeros(FPMO.hasNoSignedZeros());
397 setAllowReciprocal(FPMO.hasAllowReciprocal());
398 setAllowContract(FPMO.hasAllowContract());
399 setApproximateFuncs(FPMO.hasApproxFunc());
400 setAllowReassociation(FPMO.hasAllowReassoc());
401 }
402
403 /// Sets the state of the flags to the defined state.
404 void setDefined() { AnyDefined = true; }
405 /// Returns true if the flags are in a defined state.
406 bool isDefined() const { return AnyDefined; }
407
408 // These are mutators for each flag.
409 void setNoUnsignedWrap(bool b) {
410 setDefined();
411 NoUnsignedWrap = b;
412 }
413 void setNoSignedWrap(bool b) {
414 setDefined();
415 NoSignedWrap = b;
416 }
417 void setExact(bool b) {
418 setDefined();
419 Exact = b;
420 }
421 void setNoNaNs(bool b) {
422 setDefined();
423 NoNaNs = b;
424 }
425 void setNoInfs(bool b) {
426 setDefined();
427 NoInfs = b;
428 }
429 void setNoSignedZeros(bool b) {
430 setDefined();
431 NoSignedZeros = b;
432 }
433 void setAllowReciprocal(bool b) {
434 setDefined();
435 AllowReciprocal = b;
436 }
437 void setVectorReduction(bool b) {
438 setDefined();
439 VectorReduction = b;
440 }
441 void setAllowContract(bool b) {
442 setDefined();
443 AllowContract = b;
444 }
445 void setApproximateFuncs(bool b) {
446 setDefined();
447 ApproximateFuncs = b;
448 }
449 void setAllowReassociation(bool b) {
450 setDefined();
451 AllowReassociation = b;
452 }
453 void setNoFPExcept(bool b) {
454 setDefined();
455 NoFPExcept = b;
456 }
457
458 // These are accessors for each flag.
459 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
460 bool hasNoSignedWrap() const { return NoSignedWrap; }
461 bool hasExact() const { return Exact; }
462 bool hasNoNaNs() const { return NoNaNs; }
463 bool hasNoInfs() const { return NoInfs; }
464 bool hasNoSignedZeros() const { return NoSignedZeros; }
465 bool hasAllowReciprocal() const { return AllowReciprocal; }
466 bool hasVectorReduction() const { return VectorReduction; }
467 bool hasAllowContract() const { return AllowContract; }
468 bool hasApproximateFuncs() const { return ApproximateFuncs; }
469 bool hasAllowReassociation() const { return AllowReassociation; }
470 bool hasNoFPExcept() const { return NoFPExcept; }
471
472 bool isFast() const {
473 return NoSignedZeros && AllowReciprocal && NoNaNs && NoInfs && NoFPExcept &&
474 AllowContract && ApproximateFuncs && AllowReassociation;
475 }
476
477 /// Clear any flags in this flag set that aren't also set in Flags.
478 /// If the given Flags are undefined then don't do anything.
479 void intersectWith(const SDNodeFlags Flags) {
480 if (!Flags.isDefined())
481 return;
482 NoUnsignedWrap &= Flags.NoUnsignedWrap;
483 NoSignedWrap &= Flags.NoSignedWrap;
484 Exact &= Flags.Exact;
485 NoNaNs &= Flags.NoNaNs;
486 NoInfs &= Flags.NoInfs;
487 NoSignedZeros &= Flags.NoSignedZeros;
488 AllowReciprocal &= Flags.AllowReciprocal;
489 VectorReduction &= Flags.VectorReduction;
490 AllowContract &= Flags.AllowContract;
491 ApproximateFuncs &= Flags.ApproximateFuncs;
492 AllowReassociation &= Flags.AllowReassociation;
493 NoFPExcept &= Flags.NoFPExcept;
494 }
495};
496
497/// Represents one node in the SelectionDAG.
498///
499class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
500private:
501 /// The operation that this node performs.
502 int16_t NodeType;
503
504protected:
505 // We define a set of mini-helper classes to help us interpret the bits in our
506 // SubclassData. These are designed to fit within a uint16_t so they pack
507 // with NodeType.
508
509#if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__))
510// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
511// and give the `pack` pragma push semantics.
512#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
513#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
514#else
515#define BEGIN_TWO_BYTE_PACK()
516#define END_TWO_BYTE_PACK()
517#endif
518
519BEGIN_TWO_BYTE_PACK()
520 class SDNodeBitfields {
521 friend class SDNode;
522 friend class MemIntrinsicSDNode;
523 friend class MemSDNode;
524 friend class SelectionDAG;
525
526 uint16_t HasDebugValue : 1;
527 uint16_t IsMemIntrinsic : 1;
528 uint16_t IsDivergent : 1;
529 };
530 enum { NumSDNodeBits = 3 };
531
532 class ConstantSDNodeBitfields {
533 friend class ConstantSDNode;
534
535 uint16_t : NumSDNodeBits;
536
537 uint16_t IsOpaque : 1;
538 };
539
540 class MemSDNodeBitfields {
541 friend class MemSDNode;
542 friend class MemIntrinsicSDNode;
543 friend class AtomicSDNode;
544
545 uint16_t : NumSDNodeBits;
546
547 uint16_t IsVolatile : 1;
548 uint16_t IsNonTemporal : 1;
549 uint16_t IsDereferenceable : 1;
550 uint16_t IsInvariant : 1;
551 };
552 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
553
554 class LSBaseSDNodeBitfields {
555 friend class LSBaseSDNode;
556 friend class MaskedLoadStoreSDNode;
557 friend class MaskedGatherScatterSDNode;
558
559 uint16_t : NumMemSDNodeBits;
560
561 // This storage is shared between disparate class hierarchies to hold an
562 // enumeration specific to the class hierarchy in use.
563 // LSBaseSDNode => enum ISD::MemIndexedMode
564 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
565 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
566 uint16_t AddressingMode : 3;
567 };
568 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
569
570 class LoadSDNodeBitfields {
571 friend class LoadSDNode;
572 friend class MaskedLoadSDNode;
573
574 uint16_t : NumLSBaseSDNodeBits;
575
576 uint16_t ExtTy : 2; // enum ISD::LoadExtType
577 uint16_t IsExpanding : 1;
578 };
579
580 class StoreSDNodeBitfields {
581 friend class StoreSDNode;
582 friend class MaskedStoreSDNode;
583
584 uint16_t : NumLSBaseSDNodeBits;
585
586 uint16_t IsTruncating : 1;
587 uint16_t IsCompressing : 1;
588 };
589
590 union {
591 char RawSDNodeBits[sizeof(uint16_t)];
592 SDNodeBitfields SDNodeBits;
593 ConstantSDNodeBitfields ConstantSDNodeBits;
594 MemSDNodeBitfields MemSDNodeBits;
595 LSBaseSDNodeBitfields LSBaseSDNodeBits;
596 LoadSDNodeBitfields LoadSDNodeBits;
597 StoreSDNodeBitfields StoreSDNodeBits;
598 };
599END_TWO_BYTE_PACK()
600#undef BEGIN_TWO_BYTE_PACK
601#undef END_TWO_BYTE_PACK
602
603 // RawSDNodeBits must cover the entirety of the union. This means that all of
604 // the union's members must have size <= RawSDNodeBits. We write the RHS as
605 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
606 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
607 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
608 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
609 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
610 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
611 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
612
613private:
614 friend class SelectionDAG;
615 // TODO: unfriend HandleSDNode once we fix its operand handling.
616 friend class HandleSDNode;
617
618 /// Unique id per SDNode in the DAG.
619 int NodeId = -1;
620
621 /// The values that are used by this operation.
622 SDUse *OperandList = nullptr;
623
624 /// The types of the values this node defines. SDNode's may
625 /// define multiple values simultaneously.
626 const EVT *ValueList;
627
628 /// List of uses for this SDNode.
629 SDUse *UseList = nullptr;
630
631 /// The number of entries in the Operand/Value list.
632 unsigned short NumOperands = 0;
633 unsigned short NumValues;
634
635 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
636 // original LLVM instructions.
637 // This is used for turning off scheduling, because we'll forgo
638 // the normal scheduling algorithms and output the instructions according to
639 // this ordering.
640 unsigned IROrder;
641
642 /// Source line information.
643 DebugLoc debugLoc;
644
645 /// Return a pointer to the specified value type.
646 static const EVT *getValueTypeList(EVT VT);
647
648 SDNodeFlags Flags;
649
650public:
651 /// Unique and persistent id per SDNode in the DAG.
652 /// Used for debug printing.
653 uint16_t PersistentId;
654
655 //===--------------------------------------------------------------------===//
656 // Accessors
657 //
658
659 /// Return the SelectionDAG opcode value for this node. For
660 /// pre-isel nodes (those for which isMachineOpcode returns false), these
661 /// are the opcode values in the ISD and <target>ISD namespaces. For
662 /// post-isel opcodes, see getMachineOpcode.
663 unsigned getOpcode() const { return (unsigned short)NodeType; }
664
665 /// Test if this node has a target-specific opcode (in the
666 /// \<target\>ISD namespace).
667 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
668
669 /// Test if this node has a target-specific opcode that may raise
670 /// FP exceptions (in the \<target\>ISD namespace and greater than
671 /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
672 /// opcode are currently automatically considered to possibly raise
673 /// FP exceptions as well.
674 bool isTargetStrictFPOpcode() const {
675 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
676 }
677
678 /// Test if this node has a target-specific
679 /// memory-referencing opcode (in the \<target\>ISD namespace and
680 /// greater than FIRST_TARGET_MEMORY_OPCODE).
681 bool isTargetMemoryOpcode() const {
682 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
683 }
684
685 /// Return true if the type of the node type undefined.
686 bool isUndef() const { return NodeType == ISD::UNDEF; }
687
688 /// Test if this node is a memory intrinsic (with valid pointer information).
689 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
690 /// non-memory intrinsics (with chains) that are not really instances of
691 /// MemSDNode. For such nodes, we need some extra state to determine the
692 /// proper classof relationship.
693 bool isMemIntrinsic() const {
694 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
695 NodeType == ISD::INTRINSIC_VOID) &&
696 SDNodeBits.IsMemIntrinsic;
697 }
698
699 /// Test if this node is a strict floating point pseudo-op.
700 bool isStrictFPOpcode() {
701 switch (NodeType) {
702 default:
703 return false;
704#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
705 case ISD::STRICT_##DAGN:
706#include "llvm/IR/ConstrainedOps.def"
707 return true;
708 }
709 }
710
711 /// Test if this node has a post-isel opcode, directly
712 /// corresponding to a MachineInstr opcode.
713 bool isMachineOpcode() const { return NodeType < 0; }
714
715 /// This may only be called if isMachineOpcode returns
716 /// true. It returns the MachineInstr opcode value that the node's opcode
717 /// corresponds to.
718 unsigned getMachineOpcode() const {
719 assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 719, __PRETTY_FUNCTION__))
;
720 return ~NodeType;
721 }
722
723 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
724 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
725
726 bool isDivergent() const { return SDNodeBits.IsDivergent; }
727
728 /// Return true if there are no uses of this node.
729 bool use_empty() const { return UseList == nullptr; }
730
731 /// Return true if there is exactly one use of this node.
732 bool hasOneUse() const {
733 return !use_empty() && std::next(use_begin()) == use_end();
734 }
735
736 /// Return the number of uses of this node. This method takes
737 /// time proportional to the number of uses.
738 size_t use_size() const { return std::distance(use_begin(), use_end()); }
739
740 /// Return the unique node id.
741 int getNodeId() const { return NodeId; }
742
743 /// Set unique node id.
744 void setNodeId(int Id) { NodeId = Id; }
745
746 /// Return the node ordering.
747 unsigned getIROrder() const { return IROrder; }
748
749 /// Set the node ordering.
750 void setIROrder(unsigned Order) { IROrder = Order; }
751
752 /// Return the source location info.
753 const DebugLoc &getDebugLoc() const { return debugLoc; }
754
755 /// Set source location info. Try to avoid this, putting
756 /// it in the constructor is preferable.
757 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
758
759 /// This class provides iterator support for SDUse
760 /// operands that use a specific SDNode.
761 class use_iterator
762 : public std::iterator<std::forward_iterator_tag, SDUse, ptrdiff_t> {
763 friend class SDNode;
764
765 SDUse *Op = nullptr;
766
767 explicit use_iterator(SDUse *op) : Op(op) {}
768
769 public:
770 using reference = std::iterator<std::forward_iterator_tag,
771 SDUse, ptrdiff_t>::reference;
772 using pointer = std::iterator<std::forward_iterator_tag,
773 SDUse, ptrdiff_t>::pointer;
774
775 use_iterator() = default;
776 use_iterator(const use_iterator &I) : Op(I.Op) {}
777
778 bool operator==(const use_iterator &x) const {
779 return Op == x.Op;
780 }
781 bool operator!=(const use_iterator &x) const {
782 return !operator==(x);
783 }
784
785 /// Return true if this iterator is at the end of uses list.
786 bool atEnd() const { return Op == nullptr; }
787
788 // Iterator traversal: forward iteration only.
789 use_iterator &operator++() { // Preincrement
790 assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 790, __PRETTY_FUNCTION__))
;
791 Op = Op->getNext();
792 return *this;
793 }
794
795 use_iterator operator++(int) { // Postincrement
796 use_iterator tmp = *this; ++*this; return tmp;
797 }
798
799 /// Retrieve a pointer to the current user node.
800 SDNode *operator*() const {
801 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 801, __PRETTY_FUNCTION__))
;
802 return Op->getUser();
803 }
804
805 SDNode *operator->() const { return operator*(); }
806
807 SDUse &getUse() const { return *Op; }
808
809 /// Retrieve the operand # of this use in its user.
810 unsigned getOperandNo() const {
811 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 811, __PRETTY_FUNCTION__))
;
812 return (unsigned)(Op - Op->getUser()->OperandList);
813 }
814 };
815
816 /// Provide iteration support to walk over all uses of an SDNode.
817 use_iterator use_begin() const {
818 return use_iterator(UseList);
819 }
820
821 static use_iterator use_end() { return use_iterator(nullptr); }
822
823 inline iterator_range<use_iterator> uses() {
824 return make_range(use_begin(), use_end());
825 }
826 inline iterator_range<use_iterator> uses() const {
827 return make_range(use_begin(), use_end());
828 }
829
830 /// Return true if there are exactly NUSES uses of the indicated value.
831 /// This method ignores uses of other values defined by this operation.
832 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
833
834 /// Return true if there are any use of the indicated value.
835 /// This method ignores uses of other values defined by this operation.
836 bool hasAnyUseOfValue(unsigned Value) const;
837
838 /// Return true if this node is the only use of N.
839 bool isOnlyUserOf(const SDNode *N) const;
840
841 /// Return true if this node is an operand of N.
842 bool isOperandOf(const SDNode *N) const;
843
844 /// Return true if this node is a predecessor of N.
845 /// NOTE: Implemented on top of hasPredecessor and every bit as
846 /// expensive. Use carefully.
847 bool isPredecessorOf(const SDNode *N) const {
848 return N->hasPredecessor(this);
849 }
850
851 /// Return true if N is a predecessor of this node.
852 /// N is either an operand of this node, or can be reached by recursively
853 /// traversing up the operands.
854 /// NOTE: This is an expensive method. Use it carefully.
855 bool hasPredecessor(const SDNode *N) const;
856
857 /// Returns true if N is a predecessor of any node in Worklist. This
858 /// helper keeps Visited and Worklist sets externally to allow unions
859 /// searches to be performed in parallel, caching of results across
860 /// queries and incremental addition to Worklist. Stops early if N is
861 /// found but will resume. Remember to clear Visited and Worklists
862 /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
863 /// giving up. The TopologicalPrune flag signals that positive NodeIds are
864 /// topologically ordered (Operands have strictly smaller node id) and search
865 /// can be pruned leveraging this.
866 static bool hasPredecessorHelper(const SDNode *N,
867 SmallPtrSetImpl<const SDNode *> &Visited,
868 SmallVectorImpl<const SDNode *> &Worklist,
869 unsigned int MaxSteps = 0,
870 bool TopologicalPrune = false) {
871 SmallVector<const SDNode *, 8> DeferredNodes;
872 if (Visited.count(N))
873 return true;
874
875 // Node Id's are assigned in three places: As a topological
876 // ordering (> 0), during legalization (results in values set to
877 // 0), new nodes (set to -1). If N has a topolgical id then we
878 // know that all nodes with ids smaller than it cannot be
879 // successors and we need not check them. Filter out all node
880 // that can't be matches. We add them to the worklist before exit
881 // in case of multiple calls. Note that during selection the topological id
882 // may be violated if a node's predecessor is selected before it. We mark
883 // this at selection negating the id of unselected successors and
884 // restricting topological pruning to positive ids.
885
886 int NId = N->getNodeId();
887 // If we Invalidated the Id, reconstruct original NId.
888 if (NId < -1)
889 NId = -(NId + 1);
890
891 bool Found = false;
892 while (!Worklist.empty()) {
893 const SDNode *M = Worklist.pop_back_val();
894 int MId = M->getNodeId();
895 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
896 (MId > 0) && (MId < NId)) {
897 DeferredNodes.push_back(M);
898 continue;
899 }
900 for (const SDValue &OpV : M->op_values()) {
901 SDNode *Op = OpV.getNode();
902 if (Visited.insert(Op).second)
903 Worklist.push_back(Op);
904 if (Op == N)
905 Found = true;
906 }
907 if (Found)
908 break;
909 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
910 break;
911 }
912 // Push deferred nodes back on worklist.
913 Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
914 // If we bailed early, conservatively return found.
915 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
916 return true;
917 return Found;
918 }
919
920 /// Return true if all the users of N are contained in Nodes.
921 /// NOTE: Requires at least one match, but doesn't require them all.
922 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
923
924 /// Return the number of values used by this operation.
925 unsigned getNumOperands() const { return NumOperands; }
926
927 /// Return the maximum number of operands that a SDNode can hold.
928 static constexpr size_t getMaxNumOperands() {
929 return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
930 }
931
932 /// Helper method returns the integer value of a ConstantSDNode operand.
933 inline uint64_t getConstantOperandVal(unsigned Num) const;
934
935 /// Helper method returns the APInt of a ConstantSDNode operand.
936 inline const APInt &getConstantOperandAPInt(unsigned Num) const;
937
938 const SDValue &getOperand(unsigned Num) const {
939 assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 939, __PRETTY_FUNCTION__))
;
940 return OperandList[Num];
941 }
942
943 using op_iterator = SDUse *;
944
945 op_iterator op_begin() const { return OperandList; }
946 op_iterator op_end() const { return OperandList+NumOperands; }
947 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
948
949 /// Iterator for directly iterating over the operand SDValue's.
950 struct value_op_iterator
951 : iterator_adaptor_base<value_op_iterator, op_iterator,
952 std::random_access_iterator_tag, SDValue,
953 ptrdiff_t, value_op_iterator *,
954 value_op_iterator *> {
955 explicit value_op_iterator(SDUse *U = nullptr)
956 : iterator_adaptor_base(U) {}
957
958 const SDValue &operator*() const { return I->get(); }
959 };
960
961 iterator_range<value_op_iterator> op_values() const {
962 return make_range(value_op_iterator(op_begin()),
963 value_op_iterator(op_end()));
964 }
965
966 SDVTList getVTList() const {
967 SDVTList X = { ValueList, NumValues };
968 return X;
969 }
970
971 /// If this node has a glue operand, return the node
972 /// to which the glue operand points. Otherwise return NULL.
973 SDNode *getGluedNode() const {
974 if (getNumOperands() != 0 &&
975 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
976 return getOperand(getNumOperands()-1).getNode();
977 return nullptr;
978 }
979
980 /// If this node has a glue value with a user, return
981 /// the user (there is at most one). Otherwise return NULL.
982 SDNode *getGluedUser() const {
983 for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
984 if (UI.getUse().get().getValueType() == MVT::Glue)
985 return *UI;
986 return nullptr;
987 }
988
989 const SDNodeFlags getFlags() const { return Flags; }
990 void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
991 bool isFast() { return Flags.isFast(); }
992
993 /// Clear any flags in this node that aren't also set in Flags.
994 /// If Flags is not in a defined state then this has no effect.
995 void intersectFlagsWith(const SDNodeFlags Flags);
996
997 /// Return the number of values defined/returned by this operator.
998 unsigned getNumValues() const { return NumValues; }
999
1000 /// Return the type of a specified result.
1001 EVT getValueType(unsigned ResNo) const {
1002 assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ?
static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1002, __PRETTY_FUNCTION__))
;
1003 return ValueList[ResNo];
1004 }
1005
1006 /// Return the type of a specified result as a simple type.
1007 MVT getSimpleValueType(unsigned ResNo) const {
1008 return getValueType(ResNo).getSimpleVT();
1009 }
1010
1011 /// Returns MVT::getSizeInBits(getValueType(ResNo)).
1012 ///
1013 /// If the value type is a scalable vector type, the scalable property will
1014 /// be set and the runtime size will be a positive integer multiple of the
1015 /// base size.
1016 TypeSize getValueSizeInBits(unsigned ResNo) const {
1017 return getValueType(ResNo).getSizeInBits();
1018 }
1019
1020 using value_iterator = const EVT *;
1021
1022 value_iterator value_begin() const { return ValueList; }
1023 value_iterator value_end() const { return ValueList+NumValues; }
1024
1025 /// Return the opcode of this operation for printing.
1026 std::string getOperationName(const SelectionDAG *G = nullptr) const;
1027 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1028 void print_types(raw_ostream &OS, const SelectionDAG *G) const;
1029 void print_details(raw_ostream &OS, const SelectionDAG *G) const;
1030 void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1031 void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1032
1033 /// Print a SelectionDAG node and all children down to
1034 /// the leaves. The given SelectionDAG allows target-specific nodes
1035 /// to be printed in human-readable form. Unlike printr, this will
1036 /// print the whole DAG, including children that appear multiple
1037 /// times.
1038 ///
1039 void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;
1040
1041 /// Print a SelectionDAG node and children up to
1042 /// depth "depth." The given SelectionDAG allows target-specific
1043 /// nodes to be printed in human-readable form. Unlike printr, this
1044 /// will print children that appear multiple times wherever they are
1045 /// used.
1046 ///
1047 void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
1048 unsigned depth = 100) const;
1049
1050 /// Dump this node, for debugging.
1051 void dump() const;
1052
1053 /// Dump (recursively) this node and its use-def subgraph.
1054 void dumpr() const;
1055
1056 /// Dump this node, for debugging.
1057 /// The given SelectionDAG allows target-specific nodes to be printed
1058 /// in human-readable form.
1059 void dump(const SelectionDAG *G) const;
1060
1061 /// Dump (recursively) this node and its use-def subgraph.
1062 /// The given SelectionDAG allows target-specific nodes to be printed
1063 /// in human-readable form.
1064 void dumpr(const SelectionDAG *G) const;
1065
1066 /// printrFull to dbgs(). The given SelectionDAG allows
1067 /// target-specific nodes to be printed in human-readable form.
1068 /// Unlike dumpr, this will print the whole DAG, including children
1069 /// that appear multiple times.
1070 void dumprFull(const SelectionDAG *G = nullptr) const;
1071
1072 /// printrWithDepth to dbgs(). The given
1073 /// SelectionDAG allows target-specific nodes to be printed in
1074 /// human-readable form. Unlike dumpr, this will print children
1075 /// that appear multiple times wherever they are used.
1076 ///
1077 void dumprWithDepth(const SelectionDAG *G = nullptr,
1078 unsigned depth = 100) const;
1079
1080 /// Gather unique data for the node.
1081 void Profile(FoldingSetNodeID &ID) const;
1082
1083 /// This method should only be used by the SDUse class.
1084 void addUse(SDUse &U) { U.addToList(&UseList); }
1085
1086protected:
1087 static SDVTList getSDVTList(EVT VT) {
1088 SDVTList Ret = { getValueTypeList(VT), 1 };
1089 return Ret;
1090 }
1091
1092 /// Create an SDNode.
1093 ///
1094 /// SDNodes are created without any operands, and never own the operand
1095 /// storage. To add operands, see SelectionDAG::createOperands.
1096 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1097 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1098 IROrder(Order), debugLoc(std::move(dl)) {
1099 memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
1100 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1100, __PRETTY_FUNCTION__))
;
1101 assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1102, __PRETTY_FUNCTION__))
1102 "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1102, __PRETTY_FUNCTION__))
;
1103 }
1104
1105 /// Release the operands and set this node to have zero operands.
1106 void DropOperands();
1107};
1108
1109/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1110/// into SDNode creation functions.
1111/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1112/// from the original Instruction, and IROrder is the ordinal position of
1113/// the instruction.
1114/// When an SDNode is created after the DAG is being built, both DebugLoc and
1115/// the IROrder are propagated from the original SDNode.
1116/// So SDLoc class provides two constructors besides the default one, one to
1117/// be used by the DAGBuilder, the other to be used by others.
1118class SDLoc {
1119private:
1120 DebugLoc DL;
1121 int IROrder = 0;
1122
1123public:
1124 SDLoc() = default;
1125 SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
1126 SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
1127 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1128 assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void
> (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1128, __PRETTY_FUNCTION__))
;
1129 if (I)
1130 DL = I->getDebugLoc();
1131 }
1132
1133 unsigned getIROrder() const { return IROrder; }
1134 const DebugLoc &getDebugLoc() const { return DL; }
1135};
1136
1137// Define inline functions from the SDValue class.
1138
1139inline SDValue::SDValue(SDNode *node, unsigned resno)
1140 : Node(node), ResNo(resno) {
1141 // Explicitly check for !ResNo to avoid use-after-free, because there are
1142 // callers that use SDValue(N, 0) with a deleted N to indicate successful
1143 // combines.
1144 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1145, __PRETTY_FUNCTION__))
1145 "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1145, __PRETTY_FUNCTION__))
;
1146 assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1146, __PRETTY_FUNCTION__))
;
1147}
1148
1149inline unsigned SDValue::getOpcode() const {
1150 return Node->getOpcode();
1151}
1152
1153inline EVT SDValue::getValueType() const {
1154 return Node->getValueType(ResNo);
12
Called C++ object pointer is null
1155}
1156
1157inline unsigned SDValue::getNumOperands() const {
1158 return Node->getNumOperands();
1159}
1160
1161inline const SDValue &SDValue::getOperand(unsigned i) const {
1162 return Node->getOperand(i);
1163}
1164
1165inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
1166 return Node->getConstantOperandVal(i);
1167}
1168
1169inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
1170 return Node->getConstantOperandAPInt(i);
1171}
1172
1173inline bool SDValue::isTargetOpcode() const {
1174 return Node->isTargetOpcode();
1175}
1176
1177inline bool SDValue::isTargetMemoryOpcode() const {
1178 return Node->isTargetMemoryOpcode();
1179}
1180
1181inline bool SDValue::isMachineOpcode() const {
1182 return Node->isMachineOpcode();
1183}
1184
1185inline unsigned SDValue::getMachineOpcode() const {
1186 return Node->getMachineOpcode();
1187}
1188
1189inline bool SDValue::isUndef() const {
1190 return Node->isUndef();
1191}
1192
1193inline bool SDValue::use_empty() const {
1194 return !Node->hasAnyUseOfValue(ResNo);
1195}
1196
1197inline bool SDValue::hasOneUse() const {
1198 return Node->hasNUsesOfValue(1, ResNo);
1199}
1200
1201inline const DebugLoc &SDValue::getDebugLoc() const {
1202 return Node->getDebugLoc();
1203}
1204
1205inline void SDValue::dump() const {
1206 return Node->dump();
1207}
1208
1209inline void SDValue::dump(const SelectionDAG *G) const {
1210 return Node->dump(G);
1211}
1212
1213inline void SDValue::dumpr() const {
1214 return Node->dumpr();
1215}
1216
1217inline void SDValue::dumpr(const SelectionDAG *G) const {
1218 return Node->dumpr(G);
1219}
1220
1221// Define inline functions from the SDUse class.
1222
1223inline void SDUse::set(const SDValue &V) {
1224 if (Val.getNode()) removeFromList();
1225 Val = V;
1226 if (V.getNode()) V.getNode()->addUse(*this);
1227}
1228
1229inline void SDUse::setInitial(const SDValue &V) {
1230 Val = V;
1231 V.getNode()->addUse(*this);
1232}
1233
1234inline void SDUse::setNode(SDNode *N) {
1235 if (Val.getNode()) removeFromList();
1236 Val.setNode(N);
1237 if (N) N->addUse(*this);
1238}
1239
1240/// This class is used to form a handle around another node that
1241/// is persistent and is updated across invocations of replaceAllUsesWith on its
1242/// operand. This node should be directly created by end-users and not added to
1243/// the AllNodes list.
1244class HandleSDNode : public SDNode {
1245 SDUse Op;
1246
1247public:
1248 explicit HandleSDNode(SDValue X)
1249 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
1250 // HandleSDNodes are never inserted into the DAG, so they won't be
1251 // auto-numbered. Use ID 65535 as a sentinel.
1252 PersistentId = 0xffff;
1253
1254 // Manually set up the operand list. This node type is special in that it's
1255 // always stack allocated and SelectionDAG does not manage its operands.
1256 // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
1257 // be so special.
1258 Op.setUser(this);
1259 Op.setInitial(X);
1260 NumOperands = 1;
1261 OperandList = &Op;
1262 }
1263 ~HandleSDNode();
1264
1265 const SDValue &getValue() const { return Op; }
1266};
1267
1268class AddrSpaceCastSDNode : public SDNode {
1269private:
1270 unsigned SrcAddrSpace;
1271 unsigned DestAddrSpace;
1272
1273public:
1274 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1275 unsigned SrcAS, unsigned DestAS);
1276
1277 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
1278 unsigned getDestAddressSpace() const { return DestAddrSpace; }
1279
1280 static bool classof(const SDNode *N) {
1281 return N->getOpcode() == ISD::ADDRSPACECAST;
1282 }
1283};
1284
1285/// This is an abstract virtual class for memory operations.
1286class MemSDNode : public SDNode {
1287private:
1288 // VT of in-memory value.
1289 EVT MemoryVT;
1290
1291protected:
1292 /// Memory reference information.
1293 MachineMemOperand *MMO;
1294
1295public:
1296 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1297 EVT memvt, MachineMemOperand *MMO);
1298
1299 bool readMem() const { return MMO->isLoad(); }
1300 bool writeMem() const { return MMO->isStore(); }
1301
1302 /// Returns alignment and volatility of the memory access
1303 unsigned getOriginalAlignment() const {
1304 return MMO->getBaseAlignment();
1305 }
1306 unsigned getAlignment() const {
1307 return MMO->getAlignment();
1308 }
1309
1310 /// Return the SubclassData value, without HasDebugValue. This contains an
1311 /// encoding of the volatile flag, as well as bits used by subclasses. This
1312 /// function should only be used to compute a FoldingSetNodeID value.
1313 /// The HasDebugValue bit is masked out because CSE map needs to match
1314 /// nodes with debug info with nodes without debug info. Same is about
1315 /// isDivergent bit.
1316 unsigned getRawSubclassData() const {
1317 uint16_t Data;
1318 union {
1319 char RawSDNodeBits[sizeof(uint16_t)];
1320 SDNodeBitfields SDNodeBits;
1321 };
1322 memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
1323 SDNodeBits.HasDebugValue = 0;
1324 SDNodeBits.IsDivergent = false;
1325 memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
1326 return Data;
1327 }
1328
1329 bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
1330 bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
1331 bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
1332 bool isInvariant() const { return MemSDNodeBits.IsInvariant; }
1333
1334 // Returns the offset from the location of the access.
1335 int64_t getSrcValueOffset() const { return MMO->getOffset(); }
1336
1337 /// Returns the AA info that describes the dereference.
1338 AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }
1339
1340 /// Returns the Ranges that describes the dereference.
1341 const MDNode *getRanges() const { return MMO->getRanges(); }
1342
1343 /// Returns the synchronization scope ID for this memory operation.
1344 SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }
1345
1346 /// Return the atomic ordering requirements for this memory operation. For
1347 /// cmpxchg atomic operations, return the atomic ordering requirements when
1348 /// store occurs.
1349 AtomicOrdering getOrdering() const { return MMO->getOrdering(); }
1350
1351 /// Return true if the memory operation ordering is Unordered or higher.
1352 bool isAtomic() const { return MMO->isAtomic(); }
1353
1354 /// Returns true if the memory operation doesn't imply any ordering
1355 /// constraints on surrounding memory operations beyond the normal memory
1356 /// aliasing rules.
1357 bool isUnordered() const { return MMO->isUnordered(); }
1358
1359 /// Returns true if the memory operation is neither atomic or volatile.
1360 bool isSimple() const { return !isAtomic() && !isVolatile(); }
1361
1362 /// Return the type of the in-memory value.
1363 EVT getMemoryVT() const { return MemoryVT; }
1364
1365 /// Return a MachineMemOperand object describing the memory
1366 /// reference performed by operation.
1367 MachineMemOperand *getMemOperand() const { return MMO; }
1368
1369 const MachinePointerInfo &getPointerInfo() const {
1370 return MMO->getPointerInfo();
1371 }
1372
1373 /// Return the address space for the associated pointer
1374 unsigned getAddressSpace() const {
1375 return getPointerInfo().getAddrSpace();
1376 }
1377
1378 /// Update this MemSDNode's MachineMemOperand information
1379 /// to reflect the alignment of NewMMO, if it has a greater alignment.
1380 /// This must only be used when the new alignment applies to all users of
1381 /// this MachineMemOperand.
1382 void refineAlignment(const MachineMemOperand *NewMMO) {
1383 MMO->refineAlignment(NewMMO);
1384 }
1385
1386 const SDValue &getChain() const { return getOperand(0); }
1387 const SDValue &getBasePtr() const {
1388 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1389 }
1390
1391 // Methods to support isa and dyn_cast
1392 static bool classof(const SDNode *N) {
1393 // For some targets, we lower some target intrinsics to a MemIntrinsicNode
1394 // with either an intrinsic or a target opcode.
1395 return N->getOpcode() == ISD::LOAD ||
1396 N->getOpcode() == ISD::STORE ||
1397 N->getOpcode() == ISD::PREFETCH ||
1398 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1399 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1400 N->getOpcode() == ISD::ATOMIC_SWAP ||
1401 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1402 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1403 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1404 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1405 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1406 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1407 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1408 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1409 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1410 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1411 N->getOpcode