Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1153, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name LegalizeIntegerTypes.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-11/lib/clang/11.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/include -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-11/lib/clang/11.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-03-09-184146-41876-1 -x c++ /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/IR/DerivedTypes.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/KnownBits.h"
24#include "llvm/Support/raw_ostream.h"
25using namespace llvm;
26
27#define DEBUG_TYPE"legalize-types" "legalize-types"
28
29//===----------------------------------------------------------------------===//
30// Integer Result Promotion
31//===----------------------------------------------------------------------===//
32
33/// PromoteIntegerResult - This method is called when a result of a node is
34/// found to be in need of promotion to a larger type. At this point, the node
35/// may also have invalid operands or may have other results that need
36/// expansion, we just know that (at least) one result needs promotion.
37void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
39 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
40 SDValue Res = SDValue();
41
42 // See if the target wants to custom expand this node.
43 if (CustomLowerNode(N, N->getValueType(ResNo), true)) {
44 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Node has been custom expanded, done\n"
; } } while (false)
;
45 return;
46 }
47
48 switch (N->getOpcode()) {
49 default:
50#ifndef NDEBUG
51 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); dbgs() << "\n";
53#endif
54 llvm_unreachable("Do not know how to promote this operator!")::llvm::llvm_unreachable_internal("Do not know how to promote this operator!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 54)
;
55 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
56 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
58 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
60 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
61 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
62 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
63 case ISD::CTLZ_ZERO_UNDEF:
64 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
65 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
66 case ISD::CTTZ_ZERO_UNDEF:
67 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
68 case ISD::EXTRACT_VECTOR_ELT:
69 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
70 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
71 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
72 break;
73 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
74 break;
75 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
76 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
77 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
78 case ISD::STRICT_FSETCC:
79 case ISD::STRICT_FSETCCS:
80 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
81 case ISD::SMIN:
82 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
83 case ISD::UMIN:
84 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break;
85
86 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
87 case ISD::SIGN_EXTEND_INREG:
88 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
89 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
90 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
91 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
92 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
93 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
94 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break;
95
96 case ISD::EXTRACT_SUBVECTOR:
97 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
98 case ISD::VECTOR_SHUFFLE:
99 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
100 case ISD::INSERT_VECTOR_ELT:
101 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
102 case ISD::BUILD_VECTOR:
103 Res = PromoteIntRes_BUILD_VECTOR(N); break;
104 case ISD::SCALAR_TO_VECTOR:
105 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
106 case ISD::SPLAT_VECTOR:
107 Res = PromoteIntRes_SPLAT_VECTOR(N); break;
108 case ISD::CONCAT_VECTORS:
109 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
110
111 case ISD::ANY_EXTEND_VECTOR_INREG:
112 case ISD::SIGN_EXTEND_VECTOR_INREG:
113 case ISD::ZERO_EXTEND_VECTOR_INREG:
114 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
115
116 case ISD::SIGN_EXTEND:
117 case ISD::ZERO_EXTEND:
118 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
119
120 case ISD::STRICT_FP_TO_SINT:
121 case ISD::STRICT_FP_TO_UINT:
122 case ISD::FP_TO_SINT:
123 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
124
125 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
126
127 case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break;
128
129 case ISD::AND:
130 case ISD::OR:
131 case ISD::XOR:
132 case ISD::ADD:
133 case ISD::SUB:
134 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
135
136 case ISD::SDIV:
137 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
138
139 case ISD::UDIV:
140 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
141
142 case ISD::SADDO:
143 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
144 case ISD::UADDO:
145 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
146 case ISD::SMULO:
147 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
148
149 case ISD::ADDE:
150 case ISD::SUBE:
151 case ISD::ADDCARRY:
152 case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
153
154 case ISD::SADDSAT:
155 case ISD::UADDSAT:
156 case ISD::SSUBSAT:
157 case ISD::USUBSAT: Res = PromoteIntRes_ADDSUBSAT(N); break;
158
159 case ISD::SMULFIX:
160 case ISD::SMULFIXSAT:
161 case ISD::UMULFIX:
162 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
163
164 case ISD::SDIVFIX:
165 case ISD::SDIVFIXSAT:
166 case ISD::UDIVFIX:
167 case ISD::UDIVFIXSAT: Res = PromoteIntRes_DIVFIX(N); break;
168
169 case ISD::ABS: Res = PromoteIntRes_ABS(N); break;
170
171 case ISD::ATOMIC_LOAD:
172 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
173
174 case ISD::ATOMIC_LOAD_ADD:
175 case ISD::ATOMIC_LOAD_SUB:
176 case ISD::ATOMIC_LOAD_AND:
177 case ISD::ATOMIC_LOAD_CLR:
178 case ISD::ATOMIC_LOAD_OR:
179 case ISD::ATOMIC_LOAD_XOR:
180 case ISD::ATOMIC_LOAD_NAND:
181 case ISD::ATOMIC_LOAD_MIN:
182 case ISD::ATOMIC_LOAD_MAX:
183 case ISD::ATOMIC_LOAD_UMIN:
184 case ISD::ATOMIC_LOAD_UMAX:
185 case ISD::ATOMIC_SWAP:
186 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
187
188 case ISD::ATOMIC_CMP_SWAP:
189 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
190 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
191 break;
192
193 case ISD::VECREDUCE_ADD:
194 case ISD::VECREDUCE_MUL:
195 case ISD::VECREDUCE_AND:
196 case ISD::VECREDUCE_OR:
197 case ISD::VECREDUCE_XOR:
198 case ISD::VECREDUCE_SMAX:
199 case ISD::VECREDUCE_SMIN:
200 case ISD::VECREDUCE_UMAX:
201 case ISD::VECREDUCE_UMIN:
202 Res = PromoteIntRes_VECREDUCE(N);
203 break;
204 }
205
206 // If the result is null then the sub-method took care of registering it.
207 if (Res.getNode())
208 SetPromotedInteger(SDValue(N, ResNo), Res);
209}
210
211SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
212 unsigned ResNo) {
213 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
214 return GetPromotedInteger(Op);
215}
216
217SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
218 // Sign-extend the new bits, and continue the assertion.
219 SDValue Op = SExtPromotedInteger(N->getOperand(0));
220 return DAG.getNode(ISD::AssertSext, SDLoc(N),
221 Op.getValueType(), Op, N->getOperand(1));
222}
223
224SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
225 // Zero the new bits, and continue the assertion.
226 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
227 return DAG.getNode(ISD::AssertZext, SDLoc(N),
228 Op.getValueType(), Op, N->getOperand(1));
229}
230
231SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
232 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
233 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
234 N->getMemoryVT(), ResVT,
235 N->getChain(), N->getBasePtr(),
236 N->getMemOperand());
237 // Legalize the chain result - switch anything that used the old chain to
238 // use the new one.
239 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
240 return Res;
241}
242
243SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
244 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
245 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
246 N->getMemoryVT(),
247 N->getChain(), N->getBasePtr(),
248 Op2, N->getMemOperand());
249 // Legalize the chain result - switch anything that used the old chain to
250 // use the new one.
251 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
252 return Res;
253}
254
255SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
256 unsigned ResNo) {
257 if (ResNo == 1) {
258 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS)((N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS) ? static_cast
<void> (0) : __assert_fail ("N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 258, __PRETTY_FUNCTION__))
;
259 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
260 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
261
262 // Only use the result of getSetCCResultType if it is legal,
263 // otherwise just use the promoted result type (NVT).
264 if (!TLI.isTypeLegal(SVT))
265 SVT = NVT;
266
267 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
268 SDValue Res = DAG.getAtomicCmpSwap(
269 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
270 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
271 N->getMemOperand());
272 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
273 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
274 return Res.getValue(1);
275 }
276
277 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
278 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
279 SDVTList VTs =
280 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
281 SDValue Res = DAG.getAtomicCmpSwap(
282 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
283 N->getBasePtr(), Op2, Op3, N->getMemOperand());
284 // Update the use to N with the newly created Res.
285 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
286 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
287 return Res;
288}
289
290SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
291 SDValue InOp = N->getOperand(0);
292 EVT InVT = InOp.getValueType();
293 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
294 EVT OutVT = N->getValueType(0);
295 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
296 SDLoc dl(N);
297
298 switch (getTypeAction(InVT)) {
299 case TargetLowering::TypeLegal:
300 break;
301 case TargetLowering::TypePromoteInteger:
302 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
303 // The input promotes to the same size. Convert the promoted value.
304 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
305 break;
306 case TargetLowering::TypeSoftenFloat:
307 // Promote the integer operand by hand.
308 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
309 case TargetLowering::TypeSoftPromoteHalf:
310 // Promote the integer operand by hand.
311 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp));
312 case TargetLowering::TypePromoteFloat: {
313 // Convert the promoted float by hand.
314 if (!NOutVT.isVector())
315 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
316 break;
317 }
318 case TargetLowering::TypeExpandInteger:
319 case TargetLowering::TypeExpandFloat:
320 break;
321 case TargetLowering::TypeScalarizeVector:
322 // Convert the element to an integer and promote it by hand.
323 if (!NOutVT.isVector())
324 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
325 BitConvertToInteger(GetScalarizedVector(InOp)));
326 break;
327 case TargetLowering::TypeSplitVector: {
328 if (!NOutVT.isVector()) {
329 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
330 // pieces of the input into integers and reassemble in the final type.
331 SDValue Lo, Hi;
332 GetSplitVector(N->getOperand(0), Lo, Hi);
333 Lo = BitConvertToInteger(Lo);
334 Hi = BitConvertToInteger(Hi);
335
336 if (DAG.getDataLayout().isBigEndian())
337 std::swap(Lo, Hi);
338
339 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
340 EVT::getIntegerVT(*DAG.getContext(),
341 NOutVT.getSizeInBits()),
342 JoinIntegers(Lo, Hi));
343 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
344 }
345 break;
346 }
347 case TargetLowering::TypeWidenVector:
348 // The input is widened to the same size. Convert to the widened value.
349 // Make sure that the outgoing value is not a vector, because this would
350 // make us bitcast between two vectors which are legalized in different ways.
351 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector()) {
352 SDValue Res =
353 DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
354
355 // For big endian targets we need to shift the casted value or the
356 // interesting bits will end up at the wrong place.
357 if (DAG.getDataLayout().isBigEndian()) {
358 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits();
359 EVT ShiftAmtTy = TLI.getShiftAmountTy(NOutVT, DAG.getDataLayout());
360 assert(ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!")((ShiftAmt < NOutVT.getSizeInBits() && "Too large shift amount!"
) ? static_cast<void> (0) : __assert_fail ("ShiftAmt < NOutVT.getSizeInBits() && \"Too large shift amount!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 360, __PRETTY_FUNCTION__))
;
361 Res = DAG.getNode(ISD::SRL, dl, NOutVT, Res,
362 DAG.getConstant(ShiftAmt, dl, ShiftAmtTy));
363 }
364 return Res;
365 }
366 // If the output type is also a vector and widening it to the same size
367 // as the widened input type would be a legal type, we can widen the bitcast
368 // and handle the promotion after.
369 if (NOutVT.isVector()) {
370 unsigned WidenInSize = NInVT.getSizeInBits();
371 unsigned OutSize = OutVT.getSizeInBits();
372 if (WidenInSize % OutSize == 0) {
373 unsigned Scale = WidenInSize / OutSize;
374 EVT WideOutVT = EVT::getVectorVT(*DAG.getContext(),
375 OutVT.getVectorElementType(),
376 OutVT.getVectorNumElements() * Scale);
377 if (isTypeLegal(WideOutVT)) {
378 InOp = DAG.getBitcast(WideOutVT, GetWidenedVector(InOp));
379 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp,
380 DAG.getVectorIdxConstant(0, dl));
381 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp);
382 }
383 }
384 }
385 }
386
387 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
388 CreateStackStoreLoad(InOp, OutVT));
389}
390
391// Helper for BSWAP/BITREVERSE promotion to ensure we can fit any shift amount
392// in the VT returned by getShiftAmountTy and to return a safe VT if we can't.
393static EVT getShiftAmountTyForConstant(EVT VT, const TargetLowering &TLI,
394 SelectionDAG &DAG) {
395 EVT ShiftVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
396 // If any possible shift value won't fit in the prefered type, just use
397 // something safe. It will be legalized when the shift is expanded.
398 if (!ShiftVT.isVector() &&
399 ShiftVT.getSizeInBits() < Log2_32_Ceil(VT.getSizeInBits()))
400 ShiftVT = MVT::i32;
401 return ShiftVT;
402}
403
404SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
405 SDValue Op = GetPromotedInteger(N->getOperand(0));
406 EVT OVT = N->getValueType(0);
407 EVT NVT = Op.getValueType();
408 SDLoc dl(N);
409
410 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
411 EVT ShiftVT = getShiftAmountTyForConstant(NVT, TLI, DAG);
412 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
413 DAG.getConstant(DiffBits, dl, ShiftVT));
414}
415
416SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
417 SDValue Op = GetPromotedInteger(N->getOperand(0));
418 EVT OVT = N->getValueType(0);
419 EVT NVT = Op.getValueType();
420 SDLoc dl(N);
421
422 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
423 EVT ShiftVT = getShiftAmountTyForConstant(NVT, TLI, DAG);
424 return DAG.getNode(ISD::SRL, dl, NVT,
425 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
426 DAG.getConstant(DiffBits, dl, ShiftVT));
427}
428
429SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
430 // The pair element type may be legal, or may not promote to the same type as
431 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
432 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
433 TLI.getTypeToTransformTo(*DAG.getContext(),
434 N->getValueType(0)), JoinIntegers(N->getOperand(0),
435 N->getOperand(1)));
436}
437
438SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
439 EVT VT = N->getValueType(0);
440 // FIXME there is no actual debug info here
441 SDLoc dl(N);
442 // Zero extend things like i1, sign extend everything else. It shouldn't
443 // matter in theory which one we pick, but this tends to give better code?
444 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
445 SDValue Result = DAG.getNode(Opc, dl,
446 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
447 SDValue(N, 0));
448 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?")((isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(Result) && \"Didn't constant fold ext?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 448, __PRETTY_FUNCTION__))
;
449 return Result;
450}
451
452SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
453 // Zero extend to the promoted type and do the count there.
454 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
455 SDLoc dl(N);
456 EVT OVT = N->getValueType(0);
457 EVT NVT = Op.getValueType();
458 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
459 // Subtract off the extra leading bits in the bigger type.
460 return DAG.getNode(
461 ISD::SUB, dl, NVT, Op,
462 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
463 NVT));
464}
465
466SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
467 // Zero extend to the promoted type and do the count there.
468 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
469 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
470}
471
472SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
473 SDValue Op = GetPromotedInteger(N->getOperand(0));
474 EVT OVT = N->getValueType(0);
475 EVT NVT = Op.getValueType();
476 SDLoc dl(N);
477 if (N->getOpcode() == ISD::CTTZ) {
478 // The count is the same in the promoted type except if the original
479 // value was zero. This can be handled by setting the bit just off
480 // the top of the original type.
481 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
482 OVT.getScalarSizeInBits());
483 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
484 }
485 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
486}
487
488SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
489 SDLoc dl(N);
490 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
491
492 SDValue Op0 = N->getOperand(0);
493 SDValue Op1 = N->getOperand(1);
494
495 // If the input also needs to be promoted, do that first so we can get a
496 // get a good idea for the output type.
497 if (TLI.getTypeAction(*DAG.getContext(), Op0.getValueType())
498 == TargetLowering::TypePromoteInteger) {
499 SDValue In = GetPromotedInteger(Op0);
500
501 // If the new type is larger than NVT, use it. We probably won't need to
502 // promote it again.
503 EVT SVT = In.getValueType().getScalarType();
504 if (SVT.bitsGE(NVT)) {
505 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1);
506 return DAG.getAnyExtOrTrunc(Ext, dl, NVT);
507 }
508 }
509
510 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1);
511}
512
513SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
514 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
515 unsigned NewOpc = N->getOpcode();
516 SDLoc dl(N);
517
518 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
519 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
520 // and SINT conversions are Custom, there is no way to tell which is
521 // preferable. We choose SINT because that's the right thing on PPC.)
522 if (N->getOpcode() == ISD::FP_TO_UINT &&
523 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
524 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
525 NewOpc = ISD::FP_TO_SINT;
526
527 if (N->getOpcode() == ISD::STRICT_FP_TO_UINT &&
528 !TLI.isOperationLegal(ISD::STRICT_FP_TO_UINT, NVT) &&
529 TLI.isOperationLegalOrCustom(ISD::STRICT_FP_TO_SINT, NVT))
530 NewOpc = ISD::STRICT_FP_TO_SINT;
531
532 SDValue Res;
533 if (N->isStrictFPOpcode()) {
534 Res = DAG.getNode(NewOpc, dl, { NVT, MVT::Other },
535 { N->getOperand(0), N->getOperand(1) });
536 // Legalize the chain result - switch anything that used the old chain to
537 // use the new one.
538 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
539 } else
540 Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
541
542 // Assert that the converted value fits in the original type. If it doesn't
543 // (eg: because the value being converted is too big), then the result of the
544 // original operation was undefined anyway, so the assert is still correct.
545 //
546 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
547 // before legalization: fp-to-uint16, 65534. -> 0xfffe
548 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
549 return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
550 N->getOpcode() == ISD::STRICT_FP_TO_UINT) ?
551 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
552 DAG.getValueType(N->getValueType(0).getScalarType()));
553}
554
555SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
556 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
557 SDLoc dl(N);
558
559 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
560}
561
562SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) {
563 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
564 SDLoc dl(N);
565
566 SDValue Res =
567 DAG.getNode(N->getOpcode(), dl, {NVT, MVT::Other}, N->getOperand(0));
568
569 // Legalize the chain result - switch anything that used the old chain to
570 // use the new one.
571 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
572 return Res;
573}
574
575SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
576 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
577 SDLoc dl(N);
578
579 if (getTypeAction(N->getOperand(0).getValueType())
580 == TargetLowering::TypePromoteInteger) {
581 SDValue Res = GetPromotedInteger(N->getOperand(0));
582 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!")((Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType().bitsLE(NVT) && \"Extension doesn't make sense!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 582, __PRETTY_FUNCTION__))
;
583
584 // If the result and operand types are the same after promotion, simplify
585 // to an in-register extension.
586 if (NVT == Res.getValueType()) {
587 // The high bits are not guaranteed to be anything. Insert an extend.
588 if (N->getOpcode() == ISD::SIGN_EXTEND)
589 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
590 DAG.getValueType(N->getOperand(0).getValueType()));
591 if (N->getOpcode() == ISD::ZERO_EXTEND)
592 return DAG.getZeroExtendInReg(Res, dl,
593 N->getOperand(0).getValueType().getScalarType());
594 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!")((N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::ANY_EXTEND && \"Unknown integer extension!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 594, __PRETTY_FUNCTION__))
;
595 return Res;
596 }
597 }
598
599 // Otherwise, just extend the original operand all the way to the larger type.
600 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
601}
602
603SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
604 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!")((ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDLoad(N) && \"Indexed load during type legalization!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 604, __PRETTY_FUNCTION__))
;
605 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
606 ISD::LoadExtType ExtType =
607 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
608 SDLoc dl(N);
609 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
610 N->getMemoryVT(), N->getMemOperand());
611
612 // Legalize the chain result - switch anything that used the old chain to
613 // use the new one.
614 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
615 return Res;
616}
617
618SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
619 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
620 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
621
622 SDLoc dl(N);
623 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
624 N->getOffset(), N->getMask(), ExtPassThru,
625 N->getMemoryVT(), N->getMemOperand(),
626 N->getAddressingMode(), ISD::EXTLOAD);
627 // Legalize the chain result - switch anything that used the old chain to
628 // use the new one.
629 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
630 return Res;
631}
632
633SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
634 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
635 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
636 assert(NVT == ExtPassThru.getValueType() &&((NVT == ExtPassThru.getValueType() && "Gather result type and the passThru argument type should be the same"
) ? static_cast<void> (0) : __assert_fail ("NVT == ExtPassThru.getValueType() && \"Gather result type and the passThru argument type should be the same\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 637, __PRETTY_FUNCTION__))
637 "Gather result type and the passThru argument type should be the same")((NVT == ExtPassThru.getValueType() && "Gather result type and the passThru argument type should be the same"
) ? static_cast<void> (0) : __assert_fail ("NVT == ExtPassThru.getValueType() && \"Gather result type and the passThru argument type should be the same\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 637, __PRETTY_FUNCTION__))
;
638
639 SDLoc dl(N);
640 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
641 N->getIndex(), N->getScale() };
642 SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
643 N->getMemoryVT(), dl, Ops,
644 N->getMemOperand(), N->getIndexType());
645 // Legalize the chain result - switch anything that used the old chain to
646 // use the new one.
647 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
648 return Res;
649}
650
651/// Promote the overflow flag of an overflowing arithmetic node.
652SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
653 // Change the return type of the boolean result while obeying
654 // getSetCCResultType.
655 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
656 EVT VT = N->getValueType(0);
657 EVT SVT = getSetCCResultType(VT);
658 SDValue Ops[3] = { N->getOperand(0), N->getOperand(1) };
659 unsigned NumOps = N->getNumOperands();
660 assert(NumOps <= 3 && "Too many operands")((NumOps <= 3 && "Too many operands") ? static_cast
<void> (0) : __assert_fail ("NumOps <= 3 && \"Too many operands\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 660, __PRETTY_FUNCTION__))
;
661 if (NumOps == 3)
662 Ops[2] = N->getOperand(2);
663
664 SDLoc dl(N);
665 SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT),
666 makeArrayRef(Ops, NumOps));
667
668 // Modified the sum result - switch anything that used the old sum to use
669 // the new one.
670 ReplaceValueWith(SDValue(N, 0), Res);
671
672 // Convert to the expected type.
673 return DAG.getBoolExtOrTrunc(Res.getValue(1), dl, NVT, VT);
674}
675
676SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSAT(SDNode *N) {
677 // If the promoted type is legal, we can convert this to:
678 // 1. ANY_EXTEND iN to iM
679 // 2. SHL by M-N
680 // 3. [US][ADD|SUB]SAT
681 // 4. L/ASHR by M-N
682 // Else it is more efficient to convert this to a min and a max
683 // operation in the higher precision arithmetic.
684 SDLoc dl(N);
685 SDValue Op1 = N->getOperand(0);
686 SDValue Op2 = N->getOperand(1);
687 unsigned OldBits = Op1.getScalarValueSizeInBits();
688
689 unsigned Opcode = N->getOpcode();
690
691 SDValue Op1Promoted, Op2Promoted;
692 if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
693 Op1Promoted = ZExtPromotedInteger(Op1);
694 Op2Promoted = ZExtPromotedInteger(Op2);
695 } else {
696 Op1Promoted = SExtPromotedInteger(Op1);
697 Op2Promoted = SExtPromotedInteger(Op2);
698 }
699 EVT PromotedType = Op1Promoted.getValueType();
700 unsigned NewBits = PromotedType.getScalarSizeInBits();
701
702 if (TLI.isOperationLegalOrCustom(Opcode, PromotedType)) {
703 unsigned ShiftOp;
704 switch (Opcode) {
705 case ISD::SADDSAT:
706 case ISD::SSUBSAT:
707 ShiftOp = ISD::SRA;
708 break;
709 case ISD::UADDSAT:
710 case ISD::USUBSAT:
711 ShiftOp = ISD::SRL;
712 break;
713 default:
714 llvm_unreachable("Expected opcode to be signed or unsigned saturation "::llvm::llvm_unreachable_internal("Expected opcode to be signed or unsigned saturation "
"addition or subtraction", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 715)
715 "addition or subtraction")::llvm::llvm_unreachable_internal("Expected opcode to be signed or unsigned saturation "
"addition or subtraction", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 715)
;
716 }
717
718 unsigned SHLAmount = NewBits - OldBits;
719 EVT SHVT = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
720 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT);
721 Op1Promoted =
722 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
723 Op2Promoted =
724 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
725
726 SDValue Result =
727 DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
728 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
729 } else {
730 if (Opcode == ISD::USUBSAT) {
731 SDValue Max =
732 DAG.getNode(ISD::UMAX, dl, PromotedType, Op1Promoted, Op2Promoted);
733 return DAG.getNode(ISD::SUB, dl, PromotedType, Max, Op2Promoted);
734 }
735
736 if (Opcode == ISD::UADDSAT) {
737 APInt MaxVal = APInt::getAllOnesValue(OldBits).zext(NewBits);
738 SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
739 SDValue Add =
740 DAG.getNode(ISD::ADD, dl, PromotedType, Op1Promoted, Op2Promoted);
741 return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
742 }
743
744 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
745 APInt MinVal = APInt::getSignedMinValue(OldBits).sext(NewBits);
746 APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
747 SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
748 SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
749 SDValue Result =
750 DAG.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
751 Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
752 Result = DAG.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
753 return Result;
754 }
755}
756
757SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
758 // Can just promote the operands then continue with operation.
759 SDLoc dl(N);
760 SDValue Op1Promoted, Op2Promoted;
761 bool Signed =
762 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
763 bool Saturating =
764 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
765 if (Signed) {
766 Op1Promoted = SExtPromotedInteger(N->getOperand(0));
767 Op2Promoted = SExtPromotedInteger(N->getOperand(1));
768 } else {
769 Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
770 Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
771 }
772 EVT OldType = N->getOperand(0).getValueType();
773 EVT PromotedType = Op1Promoted.getValueType();
774 unsigned DiffSize =
775 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
776
777 if (Saturating) {
778 // Promoting the operand and result values changes the saturation width,
779 // which is extends the values that we clamp to on saturation. This could be
780 // resolved by shifting one of the operands the same amount, which would
781 // also shift the result we compare against, then shifting back.
782 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
783 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
784 DAG.getConstant(DiffSize, dl, ShiftTy));
785 SDValue Result = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
786 Op2Promoted, N->getOperand(2));
787 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
788 return DAG.getNode(ShiftOp, dl, PromotedType, Result,
789 DAG.getConstant(DiffSize, dl, ShiftTy));
790 }
791 return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted,
792 N->getOperand(2));
793}
794
795static SDValue SaturateWidenedDIVFIX(SDValue V, SDLoc &dl,
796 unsigned SatW, bool Signed,
797 const TargetLowering &TLI,
798 SelectionDAG &DAG) {
799 EVT VT = V.getValueType();
800 unsigned VTW = VT.getScalarSizeInBits();
801
802 if (!Signed) {
803 // Saturate to the unsigned maximum by getting the minimum of V and the
804 // maximum.
805 return DAG.getNode(ISD::UMIN, dl, VT, V,
806 DAG.getConstant(APInt::getLowBitsSet(VTW, SatW),
807 dl, VT));
808 }
809
810 // Saturate to the signed maximum (the low SatW - 1 bits) by taking the
811 // signed minimum of it and V.
812 V = DAG.getNode(ISD::SMIN, dl, VT, V,
813 DAG.getConstant(APInt::getLowBitsSet(VTW, SatW - 1),
814 dl, VT));
815 // Saturate to the signed minimum (the high SatW + 1 bits) by taking the
816 // signed maximum of it and V.
817 V = DAG.getNode(ISD::SMAX, dl, VT, V,
818 DAG.getConstant(APInt::getHighBitsSet(VTW, VTW - SatW + 1),
819 dl, VT));
820 return V;
821}
822
823static SDValue earlyExpandDIVFIX(SDNode *N, SDValue LHS, SDValue RHS,
824 unsigned Scale, const TargetLowering &TLI,
825 SelectionDAG &DAG, unsigned SatW = 0) {
826 EVT VT = LHS.getValueType();
827 unsigned VTSize = VT.getScalarSizeInBits();
828 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
829 N->getOpcode() == ISD::SDIVFIXSAT;
830 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
831 N->getOpcode() == ISD::UDIVFIXSAT;
832
833 SDLoc dl(N);
834 // Widen the types by a factor of two. This is guaranteed to expand, since it
835 // will always have enough high bits in the LHS to shift into.
836 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VTSize * 2);
837 if (VT.isVector())
838 WideVT = EVT::getVectorVT(*DAG.getContext(), WideVT,
839 VT.getVectorElementCount());
840 if (Signed) {
841 LHS = DAG.getSExtOrTrunc(LHS, dl, WideVT);
842 RHS = DAG.getSExtOrTrunc(RHS, dl, WideVT);
843 } else {
844 LHS = DAG.getZExtOrTrunc(LHS, dl, WideVT);
845 RHS = DAG.getZExtOrTrunc(RHS, dl, WideVT);
846 }
847
848 SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, LHS, RHS, Scale,
849 DAG);
850 assert(Res && "Expanding DIVFIX with wide type failed?")((Res && "Expanding DIVFIX with wide type failed?") ?
static_cast<void> (0) : __assert_fail ("Res && \"Expanding DIVFIX with wide type failed?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 850, __PRETTY_FUNCTION__))
;
851 if (Saturating) {
852 // If the caller has told us to saturate at something less, use that width
853 // instead of the type before doubling. However, it cannot be more than
854 // what we just widened!
855 assert(SatW <= VTSize &&((SatW <= VTSize && "Tried to saturate to more than the original type?"
) ? static_cast<void> (0) : __assert_fail ("SatW <= VTSize && \"Tried to saturate to more than the original type?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 856, __PRETTY_FUNCTION__))
856 "Tried to saturate to more than the original type?")((SatW <= VTSize && "Tried to saturate to more than the original type?"
) ? static_cast<void> (0) : __assert_fail ("SatW <= VTSize && \"Tried to saturate to more than the original type?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 856, __PRETTY_FUNCTION__))
;
857 Res = SaturateWidenedDIVFIX(Res, dl, SatW == 0 ? VTSize : SatW, Signed,
858 TLI, DAG);
859 }
860 return DAG.getZExtOrTrunc(Res, dl, VT);
861}
862
863SDValue DAGTypeLegalizer::PromoteIntRes_DIVFIX(SDNode *N) {
864 SDLoc dl(N);
865 SDValue Op1Promoted, Op2Promoted;
866 bool Signed = N->getOpcode() == ISD::SDIVFIX ||
867 N->getOpcode() == ISD::SDIVFIXSAT;
868 bool Saturating = N->getOpcode() == ISD::SDIVFIXSAT ||
869 N->getOpcode() == ISD::UDIVFIXSAT;
870 if (Signed) {
871 Op1Promoted = SExtPromotedInteger(N->getOperand(0));
872 Op2Promoted = SExtPromotedInteger(N->getOperand(1));
873 } else {
874 Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
875 Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
876 }
877 EVT PromotedType = Op1Promoted.getValueType();
878 unsigned Scale = N->getConstantOperandVal(2);
879
880 // If the type is already legal and the operation is legal in that type, we
881 // should not early expand.
882 if (TLI.isTypeLegal(PromotedType)) {
883 TargetLowering::LegalizeAction Action =
884 TLI.getFixedPointOperationAction(N->getOpcode(), PromotedType, Scale);
885 if (Action == TargetLowering::Legal || Action == TargetLowering::Custom) {
886 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
887 unsigned Diff = PromotedType.getScalarSizeInBits() -
888 N->getValueType(0).getScalarSizeInBits();
889 if (Saturating)
890 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
891 DAG.getConstant(Diff, dl, ShiftTy));
892 SDValue Res = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
893 Op2Promoted, N->getOperand(2));
894 if (Saturating)
895 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res,
896 DAG.getConstant(Diff, dl, ShiftTy));
897 return Res;
898 }
899 }
900
901 // See if we can perform the division in this type without expanding.
902 if (SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, Op1Promoted,
903 Op2Promoted, Scale, DAG)) {
904 if (Saturating)
905 Res = SaturateWidenedDIVFIX(Res, dl,
906 N->getValueType(0).getScalarSizeInBits(),
907 Signed, TLI, DAG);
908 return Res;
909 }
910 // If we cannot, expand it to twice the type width. If we are saturating, give
911 // it the original width as a saturating width so we don't need to emit
912 // two saturations.
913 return earlyExpandDIVFIX(N, Op1Promoted, Op2Promoted, Scale, TLI, DAG,
914 N->getValueType(0).getScalarSizeInBits());
915}
916
917SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
918 if (ResNo == 1)
919 return PromoteIntRes_Overflow(N);
920
921 // The operation overflowed iff the result in the larger type is not the
922 // sign extension of its truncation to the original type.
923 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
924 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
925 EVT OVT = N->getOperand(0).getValueType();
926 EVT NVT = LHS.getValueType();
927 SDLoc dl(N);
928
929 // Do the arithmetic in the larger type.
930 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
931 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
932
933 // Calculate the overflow flag: sign extend the arithmetic result from
934 // the original type.
935 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
936 DAG.getValueType(OVT));
937 // Overflowed if and only if this is not equal to Res.
938 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
939
940 // Use the calculated overflow everywhere.
941 ReplaceValueWith(SDValue(N, 1), Ofl);
942
943 return Res;
944}
945
946SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
947 SDValue LHS = GetPromotedInteger(N->getOperand(1));
948 SDValue RHS = GetPromotedInteger(N->getOperand(2));
949 return DAG.getSelect(SDLoc(N),
950 LHS.getValueType(), N->getOperand(0), LHS, RHS);
951}
952
953SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
954 SDValue Mask = N->getOperand(0);
955
956 SDValue LHS = GetPromotedInteger(N->getOperand(1));
957 SDValue RHS = GetPromotedInteger(N->getOperand(2));
958 return DAG.getNode(ISD::VSELECT, SDLoc(N),
959 LHS.getValueType(), Mask, LHS, RHS);
960}
961
962SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
963 SDValue LHS = GetPromotedInteger(N->getOperand(2));
964 SDValue RHS = GetPromotedInteger(N->getOperand(3));
965 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
966 LHS.getValueType(), N->getOperand(0),
967 N->getOperand(1), LHS, RHS, N->getOperand(4));
968}
969
970SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
971 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
972 EVT InVT = N->getOperand(OpNo).getValueType();
973 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
974
975 EVT SVT = getSetCCResultType(InVT);
976
977 // If we got back a type that needs to be promoted, this likely means the
978 // the input type also needs to be promoted. So get the promoted type for
979 // the input and try the query again.
980 if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) {
981 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
982 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
983 SVT = getSetCCResultType(InVT);
984 } else {
985 // Input type isn't promoted, just use the default promoted type.
986 SVT = NVT;
987 }
988 }
989
990 SDLoc dl(N);
991 assert(SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() &&((SVT.isVector() == N->getOperand(OpNo).getValueType().isVector
() && "Vector compare must return a vector result!") ?
static_cast<void> (0) : __assert_fail ("SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() && \"Vector compare must return a vector result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 992, __PRETTY_FUNCTION__))
992 "Vector compare must return a vector result!")((SVT.isVector() == N->getOperand(OpNo).getValueType().isVector
() && "Vector compare must return a vector result!") ?
static_cast<void> (0) : __assert_fail ("SVT.isVector() == N->getOperand(OpNo).getValueType().isVector() && \"Vector compare must return a vector result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 992, __PRETTY_FUNCTION__))
;
993
994 // Get the SETCC result using the canonical SETCC type.
995 SDValue SetCC;
996 if (N->isStrictFPOpcode()) {
997 EVT VTs[] = {SVT, MVT::Other};
998 SDValue Opers[] = {N->getOperand(0), N->getOperand(1),
999 N->getOperand(2), N->getOperand(3)};
1000 SetCC = DAG.getNode(N->getOpcode(), dl, VTs, Opers);
1001 // Legalize the chain result - switch anything that used the old chain to
1002 // use the new one.
1003 ReplaceValueWith(SDValue(N, 1), SetCC.getValue(1));
1004 } else
1005 SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
1006 N->getOperand(1), N->getOperand(2));
1007
1008 // Convert to the expected type.
1009 return DAG.getSExtOrTrunc(SetCC, dl, NVT);
1010}
1011
1012SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
1013 SDValue LHS = GetPromotedInteger(N->getOperand(0));
1014 SDValue RHS = N->getOperand(1);
1015 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1016 RHS = ZExtPromotedInteger(RHS);
1017 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
1018}
1019
1020SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
1021 SDValue Op = GetPromotedInteger(N->getOperand(0));
1022 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
1023 Op.getValueType(), Op, N->getOperand(1));
1024}
1025
1026SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
1027 // The input may have strange things in the top bits of the registers, but
1028 // these operations don't care. They may have weird bits going out, but
1029 // that too is okay if they are integer operations.
1030 SDValue LHS = GetPromotedInteger(N->getOperand(0));
1031 SDValue RHS = GetPromotedInteger(N->getOperand(1));
1032 return DAG.getNode(N->getOpcode(), SDLoc(N),
1033 LHS.getValueType(), LHS, RHS);
1034}
1035
1036SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
1037 // Sign extend the input.
1038 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1039 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1040 return DAG.getNode(N->getOpcode(), SDLoc(N),
1041 LHS.getValueType(), LHS, RHS);
1042}
1043
1044SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
1045 // Zero extend the input.
1046 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1047 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1048 return DAG.getNode(N->getOpcode(), SDLoc(N),
1049 LHS.getValueType(), LHS, RHS);
1050}
1051
1052SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
1053 // The input value must be properly sign extended.
1054 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1055 SDValue RHS = N->getOperand(1);
1056 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1057 RHS = ZExtPromotedInteger(RHS);
1058 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
1059}
1060
1061SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
1062 // The input value must be properly zero extended.
1063 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1064 SDValue RHS = N->getOperand(1);
1065 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
1066 RHS = ZExtPromotedInteger(RHS);
1067 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
1068}
1069
1070SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
1071 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1072 SDValue Res;
1073 SDValue InOp = N->getOperand(0);
1074 SDLoc dl(N);
1075
1076 switch (getTypeAction(InOp.getValueType())) {
1077 default: llvm_unreachable("Unknown type action!")::llvm::llvm_unreachable_internal("Unknown type action!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1077)
;
1078 case TargetLowering::TypeLegal:
1079 case TargetLowering::TypeExpandInteger:
1080 Res = InOp;
1081 break;
1082 case TargetLowering::TypePromoteInteger:
1083 Res = GetPromotedInteger(InOp);
1084 break;
1085 case TargetLowering::TypeSplitVector: {
1086 EVT InVT = InOp.getValueType();
1087 assert(InVT.isVector() && "Cannot split scalar types")((InVT.isVector() && "Cannot split scalar types") ? static_cast
<void> (0) : __assert_fail ("InVT.isVector() && \"Cannot split scalar types\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1087, __PRETTY_FUNCTION__))
;
1088 unsigned NumElts = InVT.getVectorNumElements();
1089 assert(NumElts == NVT.getVectorNumElements() &&((NumElts == NVT.getVectorNumElements() && "Dst and Src must have the same number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElts == NVT.getVectorNumElements() && \"Dst and Src must have the same number of elements\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1090, __PRETTY_FUNCTION__))
1090 "Dst and Src must have the same number of elements")((NumElts == NVT.getVectorNumElements() && "Dst and Src must have the same number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElts == NVT.getVectorNumElements() && \"Dst and Src must have the same number of elements\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1090, __PRETTY_FUNCTION__))
;
1091 assert(isPowerOf2_32(NumElts) &&((isPowerOf2_32(NumElts) && "Promoted vector type must be a power of two"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumElts) && \"Promoted vector type must be a power of two\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1092, __PRETTY_FUNCTION__))
1092 "Promoted vector type must be a power of two")((isPowerOf2_32(NumElts) && "Promoted vector type must be a power of two"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumElts) && \"Promoted vector type must be a power of two\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1092, __PRETTY_FUNCTION__))
;
1093
1094 SDValue EOp1, EOp2;
1095 GetSplitVector(InOp, EOp1, EOp2);
1096
1097 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
1098 NumElts/2);
1099 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
1100 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
1101
1102 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
1103 }
1104 case TargetLowering::TypeWidenVector: {
1105 SDValue WideInOp = GetWidenedVector(InOp);
1106
1107 // Truncate widened InOp.
1108 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
1109 EVT TruncVT = EVT::getVectorVT(*DAG.getContext(),
1110 N->getValueType(0).getScalarType(), NumElem);
1111 SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp);
1112
1113 // Zero extend so that the elements are of same type as those of NVT
1114 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(),
1115 NumElem);
1116 SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
1117
1118 // Extract the low NVT subvector.
1119 SDValue ZeroIdx = DAG.getVectorIdxConstant(0, dl);
1120 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
1121 }
1122 }
1123
1124 // Truncate to NVT instead of VT
1125 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
1126}
1127
1128SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
1129 if (ResNo == 1)
1130 return PromoteIntRes_Overflow(N);
1131
1132 // The operation overflowed iff the result in the larger type is not the
1133 // zero extension of its truncation to the original type.
1134 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
1135 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
1136 EVT OVT = N->getOperand(0).getValueType();
1137 EVT NVT = LHS.getValueType();
1138 SDLoc dl(N);
1139
1140 // Do the arithmetic in the larger type.
1141 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
1142 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
1143
1144 // Calculate the overflow flag: zero extend the arithmetic result from
1145 // the original type.
1146 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT.getScalarType());
1147 // Overflowed if and only if this is not equal to Res.
1148 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
1149
1150 // Use the calculated overflow everywhere.
1151 ReplaceValueWith(SDValue(N, 1), Ofl);
1152
1153 return Res;
1154}
1155
1156// Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
1157// the third operand of ADDE/SUBE nodes is carry flag, which differs from
1158// the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
1159SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
1160 if (ResNo == 1)
1161 return PromoteIntRes_Overflow(N);
1162
1163 // We need to sign-extend the operands so the carry value computed by the
1164 // wide operation will be equivalent to the carry value computed by the
1165 // narrow operation.
1166 // An ADDCARRY can generate carry only if any of the operands has its
1167 // most significant bit set. Sign extension propagates the most significant
1168 // bit into the higher bits which means the extra bit that the narrow
1169 // addition would need (i.e. the carry) will be propagated through the higher
1170 // bits of the wide addition.
1171 // A SUBCARRY can generate borrow only if LHS < RHS and this property will be
1172 // preserved by sign extension.
1173 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1174 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1175
1176 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)};
1177
1178 // Do the arithmetic in the wide type.
1179 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
1180 LHS, RHS, N->getOperand(2));
1181
1182 // Update the users of the original carry/borrow value.
1183 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
1184
1185 return SDValue(Res.getNode(), 0);
1186}
1187
1188SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1189 SDValue Op0 = SExtPromotedInteger(N->getOperand(0));
1190 return DAG.getNode(ISD::ABS, SDLoc(N), Op0.getValueType(), Op0);
1191}
1192
1193SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1194 // Promote the overflow bit trivially.
1195 if (ResNo == 1)
1196 return PromoteIntRes_Overflow(N);
1197
1198 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
1199 SDLoc DL(N);
1200 EVT SmallVT = LHS.getValueType();
1201
1202 // To determine if the result overflowed in a larger type, we extend the
1203 // input to the larger type, do the multiply (checking if it overflows),
1204 // then also check the high bits of the result to see if overflow happened
1205 // there.
1206 if (N->getOpcode() == ISD::SMULO) {
1207 LHS = SExtPromotedInteger(LHS);
1208 RHS = SExtPromotedInteger(RHS);
1209 } else {
1210 LHS = ZExtPromotedInteger(LHS);
1211 RHS = ZExtPromotedInteger(RHS);
1212 }
1213 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
1214 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
1215
1216 // Overflow occurred if it occurred in the larger type, or if the high part
1217 // of the result does not zero/sign-extend the low part. Check this second
1218 // possibility first.
1219 SDValue Overflow;
1220 if (N->getOpcode() == ISD::UMULO) {
1221 // Unsigned overflow occurred if the high part is non-zero.
1222 unsigned Shift = SmallVT.getScalarSizeInBits();
1223 EVT ShiftTy = getShiftAmountTyForConstant(Mul.getValueType(), TLI, DAG);
1224 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
1225 DAG.getConstant(Shift, DL, ShiftTy));
1226 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
1227 DAG.getConstant(0, DL, Hi.getValueType()),
1228 ISD::SETNE);
1229 } else {
1230 // Signed overflow occurred if the high part does not sign extend the low.
1231 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
1232 Mul, DAG.getValueType(SmallVT));
1233 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
1234 }
1235
1236 // The only other way for overflow to occur is if the multiplication in the
1237 // larger type itself overflowed.
1238 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
1239 SDValue(Mul.getNode(), 1));
1240
1241 // Use the calculated overflow everywhere.
1242 ReplaceValueWith(SDValue(N, 1), Overflow);
1243 return Mul;
1244}
1245
1246SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1247 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
1248 N->getValueType(0)));
1249}
1250
1251SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
1252 EVT VT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1253
1254 APInt MulImm = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
1255 return DAG.getVScale(SDLoc(N), VT, MulImm.sextOrSelf(VT.getSizeInBits()));
1256}
1257
1258SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1259 SDValue Chain = N->getOperand(0); // Get the chain.
1260 SDValue Ptr = N->getOperand(1); // Get the pointer.
1261 EVT VT = N->getValueType(0);
1262 SDLoc dl(N);
1263
1264 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
1265 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
1266 // The argument is passed as NumRegs registers of type RegVT.
1267
1268 SmallVector<SDValue, 8> Parts(NumRegs);
1269 for (unsigned i = 0; i < NumRegs; ++i) {
1270 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
1271 N->getConstantOperandVal(3));
1272 Chain = Parts[i].getValue(1);
1273 }
1274
1275 // Handle endianness of the load.
1276 if (DAG.getDataLayout().isBigEndian())
1277 std::reverse(Parts.begin(), Parts.end());
1278
1279 // Assemble the parts in the promoted type.
1280 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1281 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
1282 for (unsigned i = 1; i < NumRegs; ++i) {
1283 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
1284 // Shift it to the right position and "or" it in.
1285 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1286 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
1287 TLI.getPointerTy(DAG.getDataLayout())));
1288 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
1289 }
1290
1291 // Modified the chain result - switch anything that used the old chain to
1292 // use the new one.
1293 ReplaceValueWith(SDValue(N, 1), Chain);
1294
1295 return Res;
1296}
1297
1298//===----------------------------------------------------------------------===//
1299// Integer Operand Promotion
1300//===----------------------------------------------------------------------===//
1301
1302/// PromoteIntegerOperand - This method is called when the specified operand of
1303/// the specified node is found to need promotion. At this point, all of the
1304/// result types of the node are known to be legal, but other operands of the
1305/// node may need promotion or expansion as well as the specified one.
1306bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1307 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1308 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1309 SDValue Res = SDValue();
1310 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
1311 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Node has been custom lowered, done\n"
; } } while (false)
;
1312 return false;
1313 }
1314
1315 switch (N->getOpcode()) {
1316 default:
1317 #ifndef NDEBUG
1318 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
1319 N->dump(&DAG); dbgs() << "\n";
1320 #endif
1321 llvm_unreachable("Do not know how to promote this operator's operand!")::llvm::llvm_unreachable_internal("Do not know how to promote this operator's operand!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1321)
;
1322
1323 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
1324 case ISD::ATOMIC_STORE:
1325 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
1326 break;
1327 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
1328 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1329 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
1330 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
1331 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
1332 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
1333 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
1334 case ISD::INSERT_VECTOR_ELT:
1335 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
1336 case ISD::SCALAR_TO_VECTOR:
1337 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
1338 case ISD::SPLAT_VECTOR:
1339 Res = PromoteIntOp_SPLAT_VECTOR(N); break;
1340 case ISD::VSELECT:
1341 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1342 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
1343 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
1344 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1345 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
1346 case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
1347 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
1348 OpNo); break;
1349 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
1350 OpNo); break;
1351 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
1352 OpNo); break;
1353 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
1354 OpNo); break;
1355 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
1356 OpNo); break;
1357 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
1358 case ISD::FP16_TO_FP:
1359 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
1360 case ISD::STRICT_UINT_TO_FP: Res = PromoteIntOp_STRICT_UINT_TO_FP(N); break;
1361 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
1362 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
1363
1364 case ISD::SHL:
1365 case ISD::SRA:
1366 case ISD::SRL:
1367 case ISD::ROTL:
1368 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
1369
1370 case ISD::ADDCARRY:
1371 case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
1372
1373 case ISD::FRAMEADDR:
1374 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
1375
1376 case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break;
1377
1378 case ISD::SMULFIX:
1379 case ISD::SMULFIXSAT:
1380 case ISD::UMULFIX:
1381 case ISD::UMULFIXSAT:
1382 case ISD::SDIVFIX:
1383 case ISD::SDIVFIXSAT:
1384 case ISD::UDIVFIX:
1385 case ISD::UDIVFIXSAT: Res = PromoteIntOp_FIX(N); break;
1386
1387 case ISD::FPOWI: Res = PromoteIntOp_FPOWI(N); break;
1388
1389 case ISD::VECREDUCE_ADD:
1390 case ISD::VECREDUCE_MUL:
1391 case ISD::VECREDUCE_AND:
1392 case ISD::VECREDUCE_OR:
1393 case ISD::VECREDUCE_XOR:
1394 case ISD::VECREDUCE_SMAX:
1395 case ISD::VECREDUCE_SMIN:
1396 case ISD::VECREDUCE_UMAX:
1397 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
1398 }
1399
1400 // If the result is null, the sub-method took care of registering results etc.
1401 if (!Res.getNode()) return false;
1402
1403 // If the result is N, the sub-method updated N in place. Tell the legalizer
1404 // core about this.
1405 if (Res.getNode() == N)
1406 return true;
1407
1408 const bool IsStrictFp = N->isStrictFPOpcode();
1409 assert(Res.getValueType() == N->getValueType(0) &&((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == (IsStrictFp ? 2 : 1) && "Invalid operand expansion"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1411, __PRETTY_FUNCTION__))
1410 N->getNumValues() == (IsStrictFp ? 2 : 1) &&((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == (IsStrictFp ? 2 : 1) && "Invalid operand expansion"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1411, __PRETTY_FUNCTION__))
1411 "Invalid operand expansion")((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == (IsStrictFp ? 2 : 1) && "Invalid operand expansion"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == (IsStrictFp ? 2 : 1) && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1411, __PRETTY_FUNCTION__))
;
1412 LLVM_DEBUG(dbgs() << "Replacing: "; N->dump(&DAG); dbgs() << " with: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Replacing: "; N->dump
(&DAG); dbgs() << " with: "; Res.dump(); } } while
(false)
1413 Res.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Replacing: "; N->dump
(&DAG); dbgs() << " with: "; Res.dump(); } } while
(false)
;
1414
1415 ReplaceValueWith(SDValue(N, 0), Res);
1416 if (IsStrictFp)
1417 ReplaceValueWith(SDValue(N, 1), SDValue(Res.getNode(), 1));
1418
1419 return false;
1420}
1421
1422/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1423/// shared among BR_CC, SELECT_CC, and SETCC handlers.
1424void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
1425 ISD::CondCode CCCode) {
1426 // We have to insert explicit sign or zero extends. Note that we could
1427 // insert sign extends for ALL conditions. For those operations where either
1428 // zero or sign extension would be valid, use SExtOrZExtPromotedInteger
1429 // which will choose the cheapest for the target.
1430 switch (CCCode) {
1431 default: llvm_unreachable("Unknown integer comparison!")::llvm::llvm_unreachable_internal("Unknown integer comparison!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1431)
;
1432 case ISD::SETEQ:
1433 case ISD::SETNE: {
1434 SDValue OpL = GetPromotedInteger(NewLHS);
1435 SDValue OpR = GetPromotedInteger(NewRHS);
1436
1437 // We would prefer to promote the comparison operand with sign extension.
1438 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
1439 // than the width of NewLHS/NewRH, we can avoid inserting real truncate
1440 // instruction, which is redundant eventually.
1441 unsigned OpLEffectiveBits =
1442 OpL.getScalarValueSizeInBits() - DAG.ComputeNumSignBits(OpL) + 1;
1443 unsigned OpREffectiveBits =
1444 OpR.getScalarValueSizeInBits() - DAG.ComputeNumSignBits(OpR) + 1;
1445 if (OpLEffectiveBits <= NewLHS.getScalarValueSizeInBits() &&
1446 OpREffectiveBits <= NewRHS.getScalarValueSizeInBits()) {
1447 NewLHS = OpL;
1448 NewRHS = OpR;
1449 } else {
1450 NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1451 NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1452 }
1453 break;
1454 }
1455 case ISD::SETUGE:
1456 case ISD::SETUGT:
1457 case ISD::SETULE:
1458 case ISD::SETULT:
1459 NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1460 NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1461 break;
1462 case ISD::SETGE:
1463 case ISD::SETGT:
1464 case ISD::SETLT:
1465 case ISD::SETLE:
1466 NewLHS = SExtPromotedInteger(NewLHS);
1467 NewRHS = SExtPromotedInteger(NewRHS);
1468 break;
1469 }
1470}
1471
1472SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
1473 SDValue Op = GetPromotedInteger(N->getOperand(0));
1474 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
1475}
1476
1477SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
1478 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
1479 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
1480 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand());
1481}
1482
1483SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1484 // This should only occur in unusual situations like bitcasting to an
1485 // x86_fp80, so just turn it into a store+load
1486 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1487}
1488
1489SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1490 assert(OpNo == 2 && "Don't know how to promote this operand!")((OpNo == 2 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 2 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1490, __PRETTY_FUNCTION__))
;
1491
1492 SDValue LHS = N->getOperand(2);
1493 SDValue RHS = N->getOperand(3);
1494 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1495
1496 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1497 // legal types.
1498 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1499 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1500 0);
1501}
1502
1503SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1504 assert(OpNo == 1 && "only know how to promote condition")((OpNo == 1 && "only know how to promote condition") ?
static_cast<void> (0) : __assert_fail ("OpNo == 1 && \"only know how to promote condition\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1504, __PRETTY_FUNCTION__))
;
1505
1506 // Promote all the way up to the canonical SetCC type.
1507 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1508
1509 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1510 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1511 N->getOperand(2)), 0);
1512}
1513
1514SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1515 // Since the result type is legal, the operands must promote to it.
1516 EVT OVT = N->getOperand(0).getValueType();
1517 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1518 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1519 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?")((Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Lo.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1519, __PRETTY_FUNCTION__))
;
1520 SDLoc dl(N);
1521
1522 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1523 DAG.getConstant(OVT.getSizeInBits(), dl,
1524 TLI.getPointerTy(DAG.getDataLayout())));
1525 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1526}
1527
1528SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1529 // The vector type is legal but the element type is not. This implies
1530 // that the vector is a power-of-two in length and that the element
1531 // type does not have a strange size (eg: it is not i1).
1532 EVT VecVT = N->getValueType(0);
1533 unsigned NumElts = VecVT.getVectorNumElements();
1534 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&((!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
"Legal vector of one illegal element?") ? static_cast<void
> (0) : __assert_fail ("!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && \"Legal vector of one illegal element?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1535, __PRETTY_FUNCTION__))
1535 "Legal vector of one illegal element?")((!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
"Legal vector of one illegal element?") ? static_cast<void
> (0) : __assert_fail ("!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && \"Legal vector of one illegal element?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1535, __PRETTY_FUNCTION__))
;
1536
1537 // Promote the inserted value. The type does not need to match the
1538 // vector element type. Check that any extra bits introduced will be
1539 // truncated away.
1540 assert(N->getOperand(0).getValueSizeInBits() >=((N->getOperand(0).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1542, __PRETTY_FUNCTION__))
1541 N->getValueType(0).getScalarSizeInBits() &&((N->getOperand(0).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1542, __PRETTY_FUNCTION__))
1542 "Type of inserted value narrower than vector element type!")((N->getOperand(0).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1542, __PRETTY_FUNCTION__))
;
1543
1544 SmallVector<SDValue, 16> NewOps;
1545 for (unsigned i = 0; i < NumElts; ++i)
1546 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1547
1548 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1549}
1550
1551SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1552 unsigned OpNo) {
1553 if (OpNo == 1) {
1554 // Promote the inserted value. This is valid because the type does not
1555 // have to match the vector element type.
1556
1557 // Check that any extra bits introduced will be truncated away.
1558 assert(N->getOperand(1).getValueSizeInBits() >=((N->getOperand(1).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1560, __PRETTY_FUNCTION__))
1559 N->getValueType(0).getScalarSizeInBits() &&((N->getOperand(1).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1560, __PRETTY_FUNCTION__))
1560 "Type of inserted value narrower than vector element type!")((N->getOperand(1).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1560, __PRETTY_FUNCTION__))
;
1561 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1562 GetPromotedInteger(N->getOperand(1)),
1563 N->getOperand(2)),
1564 0);
1565 }
1566
1567 assert(OpNo == 2 && "Different operand and result vector types?")((OpNo == 2 && "Different operand and result vector types?"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 2 && \"Different operand and result vector types?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1567, __PRETTY_FUNCTION__))
;
1568
1569 // Promote the index.
1570 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1571 TLI.getVectorIdxTy(DAG.getDataLayout()));
1572 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1573 N->getOperand(1), Idx), 0);
1574}
1575
1576SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1577 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1578 // the operand in place.
1579 return SDValue(DAG.UpdateNodeOperands(N,
1580 GetPromotedInteger(N->getOperand(0))), 0);
1581}
1582
1583SDValue DAGTypeLegalizer::PromoteIntOp_SPLAT_VECTOR(SDNode *N) {
1584 // Integer SPLAT_VECTOR operands are implicitly truncated, so just promote the
1585 // operand in place.
1586 return SDValue(
1587 DAG.UpdateNodeOperands(N, GetPromotedInteger(N->getOperand(0))), 0);
1588}
1589
1590SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1591 assert(OpNo == 0 && "Only know how to promote the condition!")((OpNo == 0 && "Only know how to promote the condition!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 0 && \"Only know how to promote the condition!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1591, __PRETTY_FUNCTION__))
;
1592 SDValue Cond = N->getOperand(0);
1593 EVT OpTy = N->getOperand(1).getValueType();
1594
1595 if (N->getOpcode() == ISD::VSELECT)
1596 if (SDValue Res = WidenVSELECTAndMask(N))
1597 return Res;
1598
1599 // Promote all the way up to the canonical SetCC type.
1600 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1601 Cond = PromoteTargetBoolean(Cond, OpVT);
1602
1603 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1604 N->getOperand(2)), 0);
1605}
1606
1607SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1608 assert(OpNo == 0 && "Don't know how to promote this operand!")((OpNo == 0 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 0 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1608, __PRETTY_FUNCTION__))
;
1609
1610 SDValue LHS = N->getOperand(0);
1611 SDValue RHS = N->getOperand(1);
1612 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1613
1614 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1615 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1616 N->getOperand(3), N->getOperand(4)), 0);
1617}
1618
1619SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1620 assert(OpNo == 0 && "Don't know how to promote this operand!")((OpNo == 0 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 0 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1620, __PRETTY_FUNCTION__))
;
1621
1622 SDValue LHS = N->getOperand(0);
1623 SDValue RHS = N->getOperand(1);
1624 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1625
1626 // The CC (#2) is always legal.
1627 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1628}
1629
1630SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1631 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1632 ZExtPromotedInteger(N->getOperand(1))), 0);
1633}
1634
1635SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1636 SDValue Op = GetPromotedInteger(N->getOperand(0));
1637 SDLoc dl(N);
1638 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1639 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1640 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1641}
1642
1643SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1644 return SDValue(DAG.UpdateNodeOperands(N,
1645 SExtPromotedInteger(N->getOperand(0))), 0);
1646}
1647
1648SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_SINT_TO_FP(SDNode *N) {
1649 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1650 SExtPromotedInteger(N->getOperand(1))), 0);
1651}
1652
1653SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1654 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!")((ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDStore(N) && \"Indexed store during type legalization!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1654, __PRETTY_FUNCTION__))
;
1655 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1656 SDLoc dl(N);
1657
1658 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1659
1660 // Truncate the value and store the result.
1661 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1662 N->getMemoryVT(), N->getMemOperand());
1663}
1664
1665SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
1666 unsigned OpNo) {
1667
1668 SDValue DataOp = N->getValue();
1669 EVT DataVT = DataOp.getValueType();
1670 SDValue Mask = N->getMask();
1671 SDLoc dl(N);
1672
1673 bool TruncateStore = false;
1674 if (OpNo == 4) {
1675 Mask = PromoteTargetBoolean(Mask, DataVT);
1676 // Update in place.
1677 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1678 NewOps[4] = Mask;
1679 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1680 } else { // Data operand
1681 assert(OpNo == 1 && "Unexpected operand for promotion")((OpNo == 1 && "Unexpected operand for promotion") ? static_cast
<void> (0) : __assert_fail ("OpNo == 1 && \"Unexpected operand for promotion\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1681, __PRETTY_FUNCTION__))
;
1682 DataOp = GetPromotedInteger(DataOp);
1683 TruncateStore = true;
1684 }
1685
1686 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(),
1687 N->getOffset(), Mask, N->getMemoryVT(),
1688 N->getMemOperand(), N->getAddressingMode(),
1689 TruncateStore, N->isCompressingStore());
1690}
1691
1692SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
1693 unsigned OpNo) {
1694 assert(OpNo == 3 && "Only know how to promote the mask!")((OpNo == 3 && "Only know how to promote the mask!") ?
static_cast<void> (0) : __assert_fail ("OpNo == 3 && \"Only know how to promote the mask!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1694, __PRETTY_FUNCTION__))
;
1695 EVT DataVT = N->getValueType(0);
1696 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1697 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1698 NewOps[OpNo] = Mask;
1699 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1700}
1701
1702SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
1703 unsigned OpNo) {
1704
1705 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1706 if (OpNo == 2) {
1707 // The Mask
1708 EVT DataVT = N->getValueType(0);
1709 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1710 } else if (OpNo == 4) {
1711 // The Index
1712 if (N->isIndexSigned())
1713 // Need to sign extend the index since the bits will likely be used.
1714 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1715 else
1716 NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
1717 } else
1718 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1719
1720 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1721}
1722
1723SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
1724 unsigned OpNo) {
1725 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1726 if (OpNo == 2) {
1727 // The Mask
1728 EVT DataVT = N->getValue().getValueType();
1729 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1730 } else if (OpNo == 4) {
1731 // The Index
1732 if (N->isIndexSigned())
1733 // Need to sign extend the index since the bits will likely be used.
1734 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1735 else
1736 NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
1737 } else
1738 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1739 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1740}
1741
1742SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1743 SDValue Op = GetPromotedInteger(N->getOperand(0));
1744 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1745}
1746
1747SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1748 return SDValue(DAG.UpdateNodeOperands(N,
1749 ZExtPromotedInteger(N->getOperand(0))), 0);
1750}
1751
1752SDValue DAGTypeLegalizer::PromoteIntOp_STRICT_UINT_TO_FP(SDNode *N) {
1753 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1754 ZExtPromotedInteger(N->getOperand(1))), 0);
1755}
1756
1757SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1758 SDLoc dl(N);
1759 SDValue Op = GetPromotedInteger(N->getOperand(0));
1760 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1761 return DAG.getZeroExtendInReg(Op, dl,
1762 N->getOperand(0).getValueType().getScalarType());
1763}
1764
1765SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) {
1766 assert(OpNo == 2 && "Don't know how to promote this operand!")((OpNo == 2 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 2 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1766, __PRETTY_FUNCTION__))
;
1767
1768 SDValue LHS = N->getOperand(0);
1769 SDValue RHS = N->getOperand(1);
1770 SDValue Carry = N->getOperand(2);
1771 SDLoc DL(N);
1772
1773 Carry = PromoteTargetBoolean(Carry, LHS.getValueType());
1774
1775 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, Carry), 0);
1776}
1777
1778SDValue DAGTypeLegalizer::PromoteIntOp_FIX(SDNode *N) {
1779 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
1780 return SDValue(
1781 DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0);
1782}
1783
1784SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
1785 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
1786 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
1787 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
1788}
1789
1790SDValue DAGTypeLegalizer::PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo) {
1791 assert(OpNo > 1 && "Don't know how to promote this operand!")((OpNo > 1 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo > 1 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1791, __PRETTY_FUNCTION__))
;
1792 // Promote the rw, locality, and cache type arguments to a supported integer
1793 // width.
1794 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
1795 SDValue Op3 = ZExtPromotedInteger(N->getOperand(3));
1796 SDValue Op4 = ZExtPromotedInteger(N->getOperand(4));
1797 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
1798 Op2, Op3, Op4),
1799 0);
1800}
1801
1802SDValue DAGTypeLegalizer::PromoteIntOp_FPOWI(SDNode *N) {
1803 SDValue Op = SExtPromotedInteger(N->getOperand(1));
1804 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op), 0);
1805}
1806
1807SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
1808 SDLoc dl(N);
1809 SDValue Op;
1810 switch (N->getOpcode()) {
1811 default: llvm_unreachable("Expected integer vector reduction")::llvm::llvm_unreachable_internal("Expected integer vector reduction"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1811)
;
1812 case ISD::VECREDUCE_ADD:
1813 case ISD::VECREDUCE_MUL:
1814 case ISD::VECREDUCE_AND:
1815 case ISD::VECREDUCE_OR:
1816 case ISD::VECREDUCE_XOR:
1817 Op = GetPromotedInteger(N->getOperand(0));
1818 break;
1819 case ISD::VECREDUCE_SMAX:
1820 case ISD::VECREDUCE_SMIN:
1821 Op = SExtPromotedInteger(N->getOperand(0));
1822 break;
1823 case ISD::VECREDUCE_UMAX:
1824 case ISD::VECREDUCE_UMIN:
1825 Op = ZExtPromotedInteger(N->getOperand(0));
1826 break;
1827 }
1828
1829 EVT EltVT = Op.getValueType().getVectorElementType();
1830 EVT VT = N->getValueType(0);
1831 if (VT.bitsGE(EltVT))
1832 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, Op);
1833
1834 // Result size must be >= element size. If this is not the case after
1835 // promotion, also promote the result type and then truncate.
1836 SDValue Reduce = DAG.getNode(N->getOpcode(), dl, EltVT, Op);
1837 return DAG.getNode(ISD::TRUNCATE, dl, VT, Reduce);
1838}
1839
1840//===----------------------------------------------------------------------===//
1841// Integer Result Expansion
1842//===----------------------------------------------------------------------===//
1843
1844/// ExpandIntegerResult - This method is called when the specified result of the
1845/// specified node is found to need expansion. At this point, the node may also
1846/// have invalid operands or may have other results that need promotion, we just
1847/// know that (at least) one result needs expansion.
1848void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1849 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1
Assuming 'DebugFlag' is false
2
Loop condition is false. Exiting loop
1850 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1851 SDValue Lo, Hi;
1852 Lo = Hi = SDValue();
1853
1854 // See if the target wants to custom expand this node.
1855 if (CustomLowerNode(N, N->getValueType(ResNo), true))
3
Assuming the condition is false
4
Taking false branch
1856 return;
1857
1858 switch (N->getOpcode()) {
5
Control jumps to 'case SHL:' at line 1971
1859 default:
1860#ifndef NDEBUG
1861 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1862 N->dump(&DAG); dbgs() << "\n";
1863#endif
1864 report_fatal_error("Do not know how to expand the result of this "
1865 "operator!");
1866
1867 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1868 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1869 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1870 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1871
1872 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1873 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1874 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1875 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1876 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1877
1878 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1879 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1880 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1881 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
1882 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1883 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1884 case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
1885 case ISD::CTLZ_ZERO_UNDEF:
1886 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1887 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1888 case ISD::CTTZ_ZERO_UNDEF:
1889 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1890 case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
1891 case ISD::STRICT_FP_TO_SINT:
1892 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1893 case ISD::STRICT_FP_TO_UINT:
1894 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1895 case ISD::STRICT_LLROUND:
1896 case ISD::STRICT_LLRINT:
1897 case ISD::LLROUND:
1898 case ISD::LLRINT: ExpandIntRes_LLROUND_LLRINT(N, Lo, Hi); break;
1899 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1900 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1901 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
1902 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1903 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1904 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1905 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1906 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1907 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1908 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1909 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1910 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1911
1912 case ISD::ATOMIC_LOAD_ADD:
1913 case ISD::ATOMIC_LOAD_SUB:
1914 case ISD::ATOMIC_LOAD_AND:
1915 case ISD::ATOMIC_LOAD_CLR:
1916 case ISD::ATOMIC_LOAD_OR:
1917 case ISD::ATOMIC_LOAD_XOR:
1918 case ISD::ATOMIC_LOAD_NAND:
1919 case ISD::ATOMIC_LOAD_MIN:
1920 case ISD::ATOMIC_LOAD_MAX:
1921 case ISD::ATOMIC_LOAD_UMIN:
1922 case ISD::ATOMIC_LOAD_UMAX:
1923 case ISD::ATOMIC_SWAP:
1924 case ISD::ATOMIC_CMP_SWAP: {
1925 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1926 SplitInteger(Tmp.first, Lo, Hi);
1927 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1928 break;
1929 }
1930 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1931 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1932 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1933 SDValue Tmp = DAG.getAtomicCmpSwap(
1934 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1935 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1936 AN->getMemOperand());
1937
1938 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1939 // success simply by comparing the loaded value against the ingoing
1940 // comparison.
1941 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1942 N->getOperand(2), ISD::SETEQ);
1943
1944 SplitInteger(Tmp, Lo, Hi);
1945 ReplaceValueWith(SDValue(N, 1), Success);
1946 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1947 break;
1948 }
1949
1950 case ISD::AND:
1951 case ISD::OR:
1952 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1953
1954 case ISD::UMAX:
1955 case ISD::SMAX:
1956 case ISD::UMIN:
1957 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
1958
1959 case ISD::ADD:
1960 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1961
1962 case ISD::ADDC:
1963 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1964
1965 case ISD::ADDE:
1966 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1967
1968 case ISD::ADDCARRY:
1969 case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
1970
1971 case ISD::SHL:
1972 case ISD::SRA:
1973 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
6
Calling 'DAGTypeLegalizer::ExpandIntRes_Shift'
1974
1975 case ISD::SADDO:
1976 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1977 case ISD::UADDO:
1978 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1979 case ISD::UMULO:
1980 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1981
1982 case ISD::SADDSAT:
1983 case ISD::UADDSAT:
1984 case ISD::SSUBSAT:
1985 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
1986
1987 case ISD::SMULFIX:
1988 case ISD::SMULFIXSAT:
1989 case ISD::UMULFIX:
1990 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
1991
1992 case ISD::SDIVFIX:
1993 case ISD::SDIVFIXSAT:
1994 case ISD::UDIVFIX:
1995 case ISD::UDIVFIXSAT: ExpandIntRes_DIVFIX(N, Lo, Hi); break;
1996
1997 case ISD::VECREDUCE_ADD:
1998 case ISD::VECREDUCE_MUL:
1999 case ISD::VECREDUCE_AND:
2000 case ISD::VECREDUCE_OR:
2001 case ISD::VECREDUCE_XOR:
2002 case ISD::VECREDUCE_SMAX:
2003 case ISD::VECREDUCE_SMIN:
2004 case ISD::VECREDUCE_UMAX:
2005 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
2006 }
2007
2008 // If Lo/Hi is null, the sub-method took care of registering results etc.
2009 if (Lo.getNode())
2010 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
2011}
2012
2013/// Lower an atomic node to the appropriate builtin call.
2014std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
2015 unsigned Opc = Node->getOpcode();
2016 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2017 RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
2018 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected atomic op or value type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2018, __PRETTY_FUNCTION__))
;
2019
2020 EVT RetVT = Node->getValueType(0);
2021 SmallVector<SDValue, 4> Ops(Node->op_begin() + 1, Node->op_end());
2022 TargetLowering::MakeLibCallOptions CallOptions;
2023 return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, SDLoc(Node),
2024 Node->getOperand(0));
2025}
2026
2027/// N is a shift by a value that needs to be expanded,
2028/// and the shift amount is a constant 'Amt'. Expand the operation.
2029void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
2030 SDValue &Lo, SDValue &Hi) {
2031 SDLoc DL(N);
2032 // Expand the incoming operand to be shifted, so that we have its parts
2033 SDValue InL, InH;
2034 GetExpandedInteger(N->getOperand(0), InL, InH);
2035
2036 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
2037 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
2038 if (!Amt) {
2039 Lo = InL;
2040 Hi = InH;
2041 return;
2042 }
2043
2044 EVT NVT = InL.getValueType();
2045 unsigned VTBits = N->getValueType(0).getSizeInBits();
2046 unsigned NVTBits = NVT.getSizeInBits();
2047 EVT ShTy = N->getOperand(1).getValueType();
2048
2049 if (N->getOpcode() == ISD::SHL) {
2050 if (Amt.ugt(VTBits)) {
2051 Lo = Hi = DAG.getConstant(0, DL, NVT);
2052 } else if (Amt.ugt(NVTBits)) {
2053 Lo = DAG.getConstant(0, DL, NVT);
2054 Hi = DAG.getNode(ISD::SHL, DL,
2055 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2056 } else if (Amt == NVTBits) {
2057 Lo = DAG.getConstant(0, DL, NVT);
2058 Hi = InL;
2059 } else {
2060 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
2061 Hi = DAG.getNode(ISD::OR, DL, NVT,
2062 DAG.getNode(ISD::SHL, DL, NVT, InH,
2063 DAG.getConstant(Amt, DL, ShTy)),
2064 DAG.getNode(ISD::SRL, DL, NVT, InL,
2065 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2066 }
2067 return;
2068 }
2069
2070 if (N->getOpcode() == ISD::SRL) {
2071 if (Amt.ugt(VTBits)) {
2072 Lo = Hi = DAG.getConstant(0, DL, NVT);
2073 } else if (Amt.ugt(NVTBits)) {
2074 Lo = DAG.getNode(ISD::SRL, DL,
2075 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
2076 Hi = DAG.getConstant(0, DL, NVT);
2077 } else if (Amt == NVTBits) {
2078 Lo = InH;
2079 Hi = DAG.getConstant(0, DL, NVT);
2080 } else {
2081 Lo = DAG.getNode(ISD::OR, DL, NVT,
2082 DAG.getNode(ISD::SRL, DL, NVT, InL,
2083 DAG.getConstant(Amt, DL, ShTy)),
2084 DAG.getNode(ISD::SHL, DL, NVT, InH,
2085 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2086 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2087 }
2088 return;
2089 }
2090
2091 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")((N->getOpcode() == ISD::SRA && "Unknown shift!") ?
static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2091, __PRETTY_FUNCTION__))
;
2092 if (Amt.ugt(VTBits)) {
2093 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2094 DAG.getConstant(NVTBits - 1, DL, ShTy));
2095 } else if (Amt.ugt(NVTBits)) {
2096 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
2097 DAG.getConstant(Amt - NVTBits, DL, ShTy));
2098 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2099 DAG.getConstant(NVTBits - 1, DL, ShTy));
2100 } else if (Amt == NVTBits) {
2101 Lo = InH;
2102 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
2103 DAG.getConstant(NVTBits - 1, DL, ShTy));
2104 } else {
2105 Lo = DAG.getNode(ISD::OR, DL, NVT,
2106 DAG.getNode(ISD::SRL, DL, NVT, InL,
2107 DAG.getConstant(Amt, DL, ShTy)),
2108 DAG.getNode(ISD::SHL, DL, NVT, InH,
2109 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
2110 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
2111 }
2112}
2113
2114/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
2115/// this shift based on knowledge of the high bit of the shift amount. If we
2116/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
2117/// shift amount.
2118bool DAGTypeLegalizer::
2119ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2120 SDValue Amt = N->getOperand(1);
10
Value assigned to 'Amt.Node'
2121 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2122 EVT ShTy = Amt.getValueType();
11
Calling 'SDValue::getValueType'
2123 unsigned ShBits = ShTy.getScalarSizeInBits();
2124 unsigned NVTBits = NVT.getScalarSizeInBits();
2125 assert(isPowerOf2_32(NVTBits) &&((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2126, __PRETTY_FUNCTION__))
2126 "Expanded integer type size not a power of two!")((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2126, __PRETTY_FUNCTION__))
;
2127 SDLoc dl(N);
2128
2129 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
2130 KnownBits Known = DAG.computeKnownBits(N->getOperand(1));
2131
2132 // If we don't know anything about the high bits, exit.
2133 if (((Known.Zero|Known.One) & HighBitMask) == 0)
2134 return false;
2135
2136 // Get the incoming operand to be shifted.
2137 SDValue InL, InH;
2138 GetExpandedInteger(N->getOperand(0), InL, InH);
2139
2140 // If we know that any of the high bits of the shift amount are one, then we
2141 // can do this as a couple of simple shifts.
2142 if (Known.One.intersects(HighBitMask)) {
2143 // Mask out the high bit, which we know is set.
2144 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
2145 DAG.getConstant(~HighBitMask, dl, ShTy));
2146
2147 switch (N->getOpcode()) {
2148 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2148)
;
2149 case ISD::SHL:
2150 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
2151 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
2152 return true;
2153 case ISD::SRL:
2154 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2155 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
2156 return true;
2157 case ISD::SRA:
2158 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
2159 DAG.getConstant(NVTBits - 1, dl, ShTy));
2160 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
2161 return true;
2162 }
2163 }
2164
2165 // If we know that all of the high bits of the shift amount are zero, then we
2166 // can do this as a couple of simple shifts.
2167 if (HighBitMask.isSubsetOf(Known.Zero)) {
2168 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
2169 // shift if x is zero. We can use XOR here because x is known to be smaller
2170 // than 32.
2171 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
2172 DAG.getConstant(NVTBits - 1, dl, ShTy));
2173
2174 unsigned Op1, Op2;
2175 switch (N->getOpcode()) {
2176 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2176)
;
2177 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
2178 case ISD::SRL:
2179 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
2180 }
2181
2182 // When shifting right the arithmetic for Lo and Hi is swapped.
2183 if (N->getOpcode() != ISD::SHL)
2184 std::swap(InL, InH);
2185
2186 // Use a little trick to get the bits that move from Lo to Hi. First
2187 // shift by one bit.
2188 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
2189 // Then compute the remaining shift with amount-1.
2190 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
2191
2192 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
2193 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
2194
2195 if (N->getOpcode() != ISD::SHL)
2196 std::swap(Hi, Lo);
2197 return true;
2198 }
2199
2200 return false;
2201}
2202
2203/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
2204/// of any size.
2205bool DAGTypeLegalizer::
2206ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2207 SDValue Amt = N->getOperand(1);
2208 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2209 EVT ShTy = Amt.getValueType();
2210 unsigned NVTBits = NVT.getSizeInBits();
2211 assert(isPowerOf2_32(NVTBits) &&((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2212, __PRETTY_FUNCTION__))
2212 "Expanded integer type size not a power of two!")((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2212, __PRETTY_FUNCTION__))
;
2213 SDLoc dl(N);
2214
2215 // Get the incoming operand to be shifted.
2216 SDValue InL, InH;
2217 GetExpandedInteger(N->getOperand(0), InL, InH);
2218
2219 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
2220 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
2221 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
2222 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2223 Amt, NVBitsNode, ISD::SETULT);
2224 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2225 Amt, DAG.getConstant(0, dl, ShTy),
2226 ISD::SETEQ);
2227
2228 SDValue LoS, HiS, LoL, HiL;
2229 switch (N->getOpcode()) {
2230 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2230)
;
2231 case ISD::SHL:
2232 // Short: ShAmt < NVTBits
2233 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
2234 HiS = DAG.getNode(ISD::OR, dl, NVT,
2235 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
2236 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
2237
2238 // Long: ShAmt >= NVTBits
2239 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
2240 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
2241
2242 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
2243 Hi = DAG.getSelect(dl, NVT, isZero, InH,
2244 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
2245 return true;
2246 case ISD::SRL:
2247 // Short: ShAmt < NVTBits
2248 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
2249 LoS = DAG.getNode(ISD::OR, dl, NVT,
2250 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2251 // FIXME: If Amt is zero, the following shift generates an undefined result
2252 // on some architectures.
2253 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2254
2255 // Long: ShAmt >= NVTBits
2256 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2257 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2258
2259 Lo = DAG.getSelect(dl, NVT, isZero, InL,
2260 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2261 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2262 return true;
2263 case ISD::SRA:
2264 // Short: ShAmt < NVTBits
2265 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
2266 LoS = DAG.getNode(ISD::OR, dl, NVT,
2267 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2268 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2269
2270 // Long: ShAmt >= NVTBits
2271 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
2272 DAG.getConstant(NVTBits - 1, dl, ShTy));
2273 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2274
2275 Lo = DAG.getSelect(dl, NVT, isZero, InL,
2276 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2277 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2278 return true;
2279 }
2280}
2281
2282static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
2283
2284 switch (Op) {
2285 default: llvm_unreachable("invalid min/max opcode")::llvm::llvm_unreachable_internal("invalid min/max opcode", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2285)
;
2286 case ISD::SMAX:
2287 return std::make_pair(ISD::SETGT, ISD::UMAX);
2288 case ISD::UMAX:
2289 return std::make_pair(ISD::SETUGT, ISD::UMAX);
2290 case ISD::SMIN:
2291 return std::make_pair(ISD::SETLT, ISD::UMIN);
2292 case ISD::UMIN:
2293 return std::make_pair(ISD::SETULT, ISD::UMIN);
2294 }
2295}
2296
2297void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
2298 SDValue &Lo, SDValue &Hi) {
2299 SDLoc DL(N);
2300 ISD::NodeType LoOpc;
2301 ISD::CondCode CondC;
2302 std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode());
2303
2304 // Expand the subcomponents.
2305 SDValue LHSL, LHSH, RHSL, RHSH;
2306 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2307 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2308
2309 // Value types
2310 EVT NVT = LHSL.getValueType();
2311 EVT CCT = getSetCCResultType(NVT);
2312
2313 // Hi part is always the same op
2314 Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
2315
2316 // We need to know whether to select Lo part that corresponds to 'winning'
2317 // Hi part or if Hi parts are equal.
2318 SDValue IsHiLeft = DAG.getSetCC(DL, CCT, LHSH, RHSH, CondC);
2319 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ);
2320
2321 // Lo part corresponding to the 'winning' Hi part
2322 SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
2323
2324 // Recursed Lo part if Hi parts are equal, this uses unsigned version
2325 SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
2326
2327 Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
2328}
2329
2330void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
2331 SDValue &Lo, SDValue &Hi) {
2332 SDLoc dl(N);
2333 // Expand the subcomponents.
2334 SDValue LHSL, LHSH, RHSL, RHSH;
2335 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2336 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2337
2338 EVT NVT = LHSL.getValueType();
2339 SDValue LoOps[2] = { LHSL, RHSL };
2340 SDValue HiOps[3] = { LHSH, RHSH };
2341
2342 bool HasOpCarry = TLI.isOperationLegalOrCustom(
2343 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
2344 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2345 if (HasOpCarry) {
2346 SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
2347 if (N->getOpcode() == ISD::ADD) {
2348 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2349 HiOps[2] = Lo.getValue(1);
2350 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps);
2351 } else {
2352 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2353 HiOps[2] = Lo.getValue(1);
2354 Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
2355 }
2356 return;
2357 }
2358
2359 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
2360 // them. TODO: Teach operation legalization how to expand unsupported
2361 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
2362 // a carry of type MVT::Glue, but there doesn't seem to be any way to
2363 // generate a value of this type in the expanded code sequence.
2364 bool hasCarry =
2365 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2366 ISD::ADDC : ISD::SUBC,
2367 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2368
2369 if (hasCarry) {
2370 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
2371 if (N->getOpcode() == ISD::ADD) {
2372 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2373 HiOps[2] = Lo.getValue(1);
2374 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2375 } else {
2376 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2377 HiOps[2] = Lo.getValue(1);
2378 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2379 }
2380 return;
2381 }
2382
2383 bool hasOVF =
2384 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2385 ISD::UADDO : ISD::USUBO,
2386 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2387 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
2388
2389 if (hasOVF) {
2390 EVT OvfVT = getSetCCResultType(NVT);
2391 SDVTList VTList = DAG.getVTList(NVT, OvfVT);
2392 int RevOpc;
2393 if (N->getOpcode() == ISD::ADD) {
2394 RevOpc = ISD::SUB;
2395 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2396 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2397 } else {
2398 RevOpc = ISD::ADD;
2399 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2400 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2401 }
2402 SDValue OVF = Lo.getValue(1);
2403
2404 switch (BoolType) {
2405 case TargetLoweringBase::UndefinedBooleanContent:
2406 OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF);
2407 LLVM_FALLTHROUGH[[gnu::fallthrough]];
2408 case TargetLoweringBase::ZeroOrOneBooleanContent:
2409 OVF = DAG.getZExtOrTrunc(OVF, dl, NVT);
2410 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
2411 break;
2412 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2413 OVF = DAG.getSExtOrTrunc(OVF, dl, NVT);
2414 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
2415 }
2416 return;
2417 }
2418
2419 if (N->getOpcode() == ISD::ADD) {
2420 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
2421 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2422 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
2423 ISD::SETULT);
2424
2425 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent) {
2426 SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT);
2427 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
2428 return;
2429 }
2430
2431 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
2432 DAG.getConstant(1, dl, NVT),
2433 DAG.getConstant(0, dl, NVT));
2434 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
2435 ISD::SETULT);
2436 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
2437 DAG.getConstant(1, dl, NVT), Carry1);
2438 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
2439 } else {
2440 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
2441 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2442 SDValue Cmp =
2443 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
2444 LoOps[0], LoOps[1], ISD::SETULT);
2445
2446 SDValue Borrow;
2447 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
2448 Borrow = DAG.getZExtOrTrunc(Cmp, dl, NVT);
2449 else
2450 Borrow = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT),
2451 DAG.getConstant(0, dl, NVT));
2452
2453 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
2454 }
2455}
2456
2457void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
2458 SDValue &Lo, SDValue &Hi) {
2459 // Expand the subcomponents.
2460 SDValue LHSL, LHSH, RHSL, RHSH;
2461 SDLoc dl(N);
2462 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2463 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2464 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2465 SDValue LoOps[2] = { LHSL, RHSL };
2466 SDValue HiOps[3] = { LHSH, RHSH };
2467
2468 if (N->getOpcode() == ISD::ADDC) {
2469 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2470 HiOps[2] = Lo.getValue(1);
2471 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2472 } else {
2473 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2474 HiOps[2] = Lo.getValue(1);
2475 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2476 }
2477
2478 // Legalized the flag result - switch anything that used the old flag to
2479 // use the new one.
2480 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2481}
2482
2483void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
2484 SDValue &Lo, SDValue &Hi) {
2485 // Expand the subcomponents.
2486 SDValue LHSL, LHSH, RHSL, RHSH;
2487 SDLoc dl(N);
2488 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2489 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2490 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2491 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2492 SDValue HiOps[3] = { LHSH, RHSH };
2493
2494 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2495 HiOps[2] = Lo.getValue(1);
2496 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2497
2498 // Legalized the flag result - switch anything that used the old flag to
2499 // use the new one.
2500 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2501}
2502
2503void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2504 SDValue &Lo, SDValue &Hi) {
2505 SDValue LHS = N->getOperand(0);
2506 SDValue RHS = N->getOperand(1);
2507 SDLoc dl(N);
2508
2509 SDValue Ovf;
2510
2511 unsigned CarryOp, NoCarryOp;
2512 ISD::CondCode Cond;
2513 switch(N->getOpcode()) {
2514 case ISD::UADDO:
2515 CarryOp = ISD::ADDCARRY;
2516 NoCarryOp = ISD::ADD;
2517 Cond = ISD::SETULT;
2518 break;
2519 case ISD::USUBO:
2520 CarryOp = ISD::SUBCARRY;
2521 NoCarryOp = ISD::SUB;
2522 Cond = ISD::SETUGT;
2523 break;
2524 default:
2525 llvm_unreachable("Node has unexpected Opcode")::llvm::llvm_unreachable_internal("Node has unexpected Opcode"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2525)
;
2526 }
2527
2528 bool HasCarryOp = TLI.isOperationLegalOrCustom(
2529 CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
2530
2531 if (HasCarryOp) {
2532 // Expand the subcomponents.
2533 SDValue LHSL, LHSH, RHSL, RHSH;
2534 GetExpandedInteger(LHS, LHSL, LHSH);
2535 GetExpandedInteger(RHS, RHSL, RHSH);
2536 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2537 SDValue LoOps[2] = { LHSL, RHSL };
2538 SDValue HiOps[3] = { LHSH, RHSH };
2539
2540 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2541 HiOps[2] = Lo.getValue(1);
2542 Hi = DAG.getNode(CarryOp, dl, VTList, HiOps);
2543
2544 Ovf = Hi.getValue(1);
2545 } else {
2546 // Expand the result by simply replacing it with the equivalent
2547 // non-overflow-checking operation.
2548 SDValue Sum = DAG.getNode(NoCarryOp, dl, LHS.getValueType(), LHS, RHS);
2549 SplitInteger(Sum, Lo, Hi);
2550
2551 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2552 // overflows iff a - b > a.
2553 Ovf = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, Cond);
2554 }
2555
2556 // Legalized the flag result - switch anything that used the old flag to
2557 // use the new one.
2558 ReplaceValueWith(SDValue(N, 1), Ovf);
2559}
2560
2561void DAGTypeLegalizer::ExpandIntRes_ADDSUBCARRY(SDNode *N,
2562 SDValue &Lo, SDValue &Hi) {
2563 // Expand the subcomponents.
2564 SDValue LHSL, LHSH, RHSL, RHSH;
2565 SDLoc dl(N);
2566 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2567 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2568 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2569 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2570 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
2571
2572 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2573 HiOps[2] = Lo.getValue(1);
2574 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2575
2576 // Legalized the flag result - switch anything that used the old flag to
2577 // use the new one.
2578 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2579}
2580
2581void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
2582 SDValue &Lo, SDValue &Hi) {
2583 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2584 SDLoc dl(N);
2585 SDValue Op = N->getOperand(0);
2586 if (Op.getValueType().bitsLE(NVT)) {
2587 // The low part is any extension of the input (which degenerates to a copy).
2588 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
2589 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
2590 } else {
2591 // For example, extension of an i48 to an i64. The operand type necessarily
2592 // promotes to the result type, so will end up being expanded too.
2593 assert(getTypeAction(Op.getValueType()) ==((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2595, __PRETTY_FUNCTION__))
2594 TargetLowering::TypePromoteInteger &&((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2595, __PRETTY_FUNCTION__))
2595 "Only know how to promote this result!")((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2595, __PRETTY_FUNCTION__))
;
2596 SDValue Res = GetPromotedInteger(Op);
2597 assert(Res.getValueType() == N->getValueType(0) &&((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2598, __PRETTY_FUNCTION__))
2598 "Operand over promoted?")((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2598, __PRETTY_FUNCTION__))
;
2599 // Split the promoted operand. This will simplify when it is expanded.
2600 SplitInteger(Res, Lo, Hi);
2601 }
2602}
2603
2604void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
2605 SDValue &Lo, SDValue &Hi) {
2606 SDLoc dl(N);
2607 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2608 EVT NVT = Lo.getValueType();
2609 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2610 unsigned NVTBits = NVT.getSizeInBits();
2611 unsigned EVTBits = EVT.getSizeInBits();
2612
2613 if (NVTBits < EVTBits) {
2614 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
2615 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2616 EVTBits - NVTBits)));
2617 } else {
2618 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
2619 // The high part replicates the sign bit of Lo, make it explicit.
2620 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2621 DAG.getConstant(NVTBits - 1, dl,
2622 TLI.getPointerTy(DAG.getDataLayout())));
2623 }
2624}
2625
2626void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
2627 SDValue &Lo, SDValue &Hi) {
2628 SDLoc dl(N);
2629 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2630 EVT NVT = Lo.getValueType();
2631 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2632 unsigned NVTBits = NVT.getSizeInBits();
2633 unsigned EVTBits = EVT.getSizeInBits();
2634
2635 if (NVTBits < EVTBits) {
2636 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
2637 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2638 EVTBits - NVTBits)));
2639 } else {
2640 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
2641 // The high part must be zero, make it explicit.
2642 Hi = DAG.getConstant(0, dl, NVT);
2643 }
2644}
2645
2646void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
2647 SDValue &Lo, SDValue &Hi) {
2648 SDLoc dl(N);
2649 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
2650 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
2651 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
2652}
2653
2654void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
2655 SDValue &Lo, SDValue &Hi) {
2656 SDLoc dl(N);
2657 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
2658 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
2659 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
2660}
2661
2662void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
2663 SDValue &Lo, SDValue &Hi) {
2664 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2665 unsigned NBitWidth = NVT.getSizeInBits();
2666 auto Constant = cast<ConstantSDNode>(N);
2667 const APInt &Cst = Constant->getAPIntValue();
2668 bool IsTarget = Constant->isTargetOpcode();
2669 bool IsOpaque = Constant->isOpaque();
2670 SDLoc dl(N);
2671 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
2672 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
2673 IsOpaque);
2674}
2675
2676void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
2677 SDLoc dl(N);
2678
2679 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
2680 EVT VT = N->getValueType(0);
2681 SDValue N0 = N->getOperand(0);
2682 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT,
2683 DAG.getConstant(0, dl, VT), N0);
2684 SDValue NegLo, NegHi;
2685 SplitInteger(Neg, NegLo, NegHi);
2686
2687 GetExpandedInteger(N0, Lo, Hi);
2688 EVT NVT = Lo.getValueType();
2689 SDValue HiIsNeg = DAG.getSetCC(dl, getSetCCResultType(NVT),
2690 DAG.getConstant(0, dl, NVT), Hi, ISD::SETGT);
2691 Lo = DAG.getSelect(dl, NVT, HiIsNeg, NegLo, Lo);
2692 Hi = DAG.getSelect(dl, NVT, HiIsNeg, NegHi, Hi);
2693}
2694
2695void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
2696 SDValue &Lo, SDValue &Hi) {
2697 SDLoc dl(N);
2698 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
2699 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2700 EVT NVT = Lo.getValueType();
2701
2702 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
2703 DAG.getConstant(0, dl, NVT), ISD::SETNE);
2704
2705 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
2706 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
2707
2708 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
2709 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
2710 DAG.getConstant(NVT.getSizeInBits(), dl,
2711 NVT)));
2712 Hi = DAG.getConstant(0, dl, NVT);
2713}
2714
2715void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
2716 SDValue &Lo, SDValue &Hi) {
2717 SDLoc dl(N);
2718 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
2719 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2720 EVT NVT = Lo.getValueType();
2721 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
2722 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
2723 Hi = DAG.getConstant(0, dl, NVT);
2724}
2725
2726void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
2727 SDValue &Lo, SDValue &Hi) {
2728 SDLoc dl(N);
2729 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
2730 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2731 EVT NVT = Lo.getValueType();
2732
2733 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
2734 DAG.getConstant(0, dl, NVT), ISD::SETNE);
2735
2736 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
2737 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
2738
2739 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
2740 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
2741 DAG.getConstant(NVT.getSizeInBits(), dl,
2742 NVT)));
2743 Hi = DAG.getConstant(0, dl, NVT);
2744}
2745
2746void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo,
2747 SDValue &Hi) {
2748 SDLoc dl(N);
2749 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2750 unsigned NBitWidth = NVT.getSizeInBits();
2751
2752 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
2753 Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, {NVT, MVT::Other}, N->getOperand(0));
2754 SDValue Chain = Lo.getValue(1);
2755 // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS
2756 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2757 DAG.getConstant(NBitWidth - 1, dl, ShiftAmtTy));
2758
2759 // Legalize the chain result - switch anything that used the old chain to
2760 // use the new one.
2761 ReplaceValueWith(SDValue(N, 1), Chain);
2762}
2763
2764void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
2765 SDValue &Hi) {
2766 SDLoc dl(N);
2767 EVT VT = N->getValueType(0);
2768
2769 bool IsStrict = N->isStrictFPOpcode();
2770 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
2771 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
2772 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
2773 Op = GetPromotedFloat(Op);
2774
2775 if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
2776 EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
2777 Op = GetSoftPromotedHalf(Op);
2778 Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
2779 }
2780
2781 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
2782 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fp-to-sint conversion!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2782, __PRETTY_FUNCTION__))
;
2783 TargetLowering::MakeLibCallOptions CallOptions;
2784 CallOptions.setSExt(true);
2785 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
2786 CallOptions, dl, Chain);
2787 SplitInteger(Tmp.first, Lo, Hi);
2788
2789 if (IsStrict)
2790 ReplaceValueWith(SDValue(N, 1), Tmp.second);
2791}
2792
2793void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
2794 SDValue &Hi) {
2795 SDLoc dl(N);
2796 EVT VT = N->getValueType(0);
2797
2798 bool IsStrict = N->isStrictFPOpcode();
2799 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
2800 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
2801 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
2802 Op = GetPromotedFloat(Op);
2803
2804 if (getTypeAction(Op.getValueType()) == TargetLowering::TypeSoftPromoteHalf) {
2805 EVT NFPVT = TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType());
2806 Op = GetSoftPromotedHalf(Op);
2807 Op = DAG.getNode(ISD::FP16_TO_FP, dl, NFPVT, Op);
2808 }
2809
2810 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
2811 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fp-to-uint conversion!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2811, __PRETTY_FUNCTION__))
;
2812 TargetLowering::MakeLibCallOptions CallOptions;
2813 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, VT, Op,
2814 CallOptions, dl, Chain);
2815 SplitInteger(Tmp.first, Lo, Hi);
2816
2817 if (IsStrict)
2818 ReplaceValueWith(SDValue(N, 1), Tmp.second);
2819}
2820
2821void DAGTypeLegalizer::ExpandIntRes_LLROUND_LLRINT(SDNode *N, SDValue &Lo,
2822 SDValue &Hi) {
2823 SDValue Op = N->getOperand(N->isStrictFPOpcode() ? 1 : 0);
2824
2825 assert(getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat &&((getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat
&& "Input type needs to be promoted!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat && \"Input type needs to be promoted!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2826, __PRETTY_FUNCTION__))
2826 "Input type needs to be promoted!")((getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat
&& "Input type needs to be promoted!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) != TargetLowering::TypePromoteFloat && \"Input type needs to be promoted!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2826, __PRETTY_FUNCTION__))
;
2827
2828 EVT VT = Op.getValueType();
2829
2830 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2831 if (N->getOpcode() == ISD::LLROUND ||
2832 N->getOpcode() == ISD::STRICT_LLROUND) {
2833 if (VT == MVT::f32)
2834 LC = RTLIB::LLROUND_F32;
2835 else if (VT == MVT::f64)
2836 LC = RTLIB::LLROUND_F64;
2837 else if (VT == MVT::f80)
2838 LC = RTLIB::LLROUND_F80;
2839 else if (VT == MVT::f128)
2840 LC = RTLIB::LLROUND_F128;
2841 else if (VT == MVT::ppcf128)
2842 LC = RTLIB::LLROUND_PPCF128;
2843 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected llround input type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2843, __PRETTY_FUNCTION__))
;
2844 } else if (N->getOpcode() == ISD::LLRINT ||
2845 N->getOpcode() == ISD::STRICT_LLRINT) {
2846 if (VT == MVT::f32)
2847 LC = RTLIB::LLRINT_F32;
2848 else if (VT == MVT::f64)
2849 LC = RTLIB::LLRINT_F64;
2850 else if (VT == MVT::f80)
2851 LC = RTLIB::LLRINT_F80;
2852 else if (VT == MVT::f128)
2853 LC = RTLIB::LLRINT_F128;
2854 else if (VT == MVT::ppcf128)
2855 LC = RTLIB::LLRINT_PPCF128;
2856 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected llrint input type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2856, __PRETTY_FUNCTION__))
;
2857 } else
2858 llvm_unreachable("Unexpected opcode!")::llvm::llvm_unreachable_internal("Unexpected opcode!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2858)
;
2859
2860 SDLoc dl(N);
2861 EVT RetVT = N->getValueType(0);
2862 SDValue Chain = N->isStrictFPOpcode() ? N->getOperand(0) : SDValue();
2863
2864 TargetLowering::MakeLibCallOptions CallOptions;
2865 CallOptions.setSExt(true);
2866 std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
2867 Op, CallOptions, dl,
2868 Chain);
2869 SplitInteger(Tmp.first, Lo, Hi);
2870
2871 if (N->isStrictFPOpcode())
2872 ReplaceValueWith(SDValue(N, 1), Tmp.second);
2873}
2874
2875void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
2876 SDValue &Lo, SDValue &Hi) {
2877 if (N->isAtomic()) {
2878 // It's typical to have larger CAS than atomic load instructions.
2879 SDLoc dl(N);
2880 EVT VT = N->getMemoryVT();
2881 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2882 SDValue Zero = DAG.getConstant(0, dl, VT);
2883 SDValue Swap = DAG.getAtomicCmpSwap(
2884 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2885 VT, VTs, N->getOperand(0),
2886 N->getOperand(1), Zero, Zero, N->getMemOperand());
2887 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2888 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2889 return;
2890 }
2891
2892 if (ISD::isNormalLoad(N)) {
2893 ExpandRes_NormalLoad(N, Lo, Hi);
2894 return;
2895 }
2896
2897 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!")((ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDLoad(N) && \"Indexed load during type legalization!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2897, __PRETTY_FUNCTION__))
;
2898
2899 EVT VT = N->getValueType(0);
2900 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2901 SDValue Ch = N->getChain();
2902 SDValue Ptr = N->getBasePtr();
2903 ISD::LoadExtType ExtType = N->getExtensionType();
2904 unsigned Alignment = N->getAlignment();
2905 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
2906 AAMDNodes AAInfo = N->getAAInfo();
2907 SDLoc dl(N);
2908
2909 assert(NVT.isByteSized() && "Expanded type not byte sized!")((NVT.isByteSized() && "Expanded type not byte sized!"
) ? static_cast<void> (0) : __assert_fail ("NVT.isByteSized() && \"Expanded type not byte sized!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2909, __PRETTY_FUNCTION__))
;
2910
2911 if (N->getMemoryVT().bitsLE(NVT)) {
2912 EVT MemVT = N->getMemoryVT();
2913
2914 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
2915 Alignment, MMOFlags, AAInfo);
2916
2917 // Remember the chain.
2918 Ch = Lo.getValue(1);
2919
2920 if (ExtType == ISD::SEXTLOAD) {
2921 // The high part is obtained by SRA'ing all but one of the bits of the
2922 // lo part.
2923 unsigned LoSize = Lo.getValueSizeInBits();
2924 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2925 DAG.getConstant(LoSize - 1, dl,
2926 TLI.getPointerTy(DAG.getDataLayout())));
2927 } else if (ExtType == ISD::ZEXTLOAD) {
2928 // The high part is just a zero.
2929 Hi = DAG.getConstant(0, dl, NVT);
2930 } else {
2931 assert(ExtType == ISD::EXTLOAD && "Unknown extload!")((ExtType == ISD::EXTLOAD && "Unknown extload!") ? static_cast
<void> (0) : __assert_fail ("ExtType == ISD::EXTLOAD && \"Unknown extload!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2931, __PRETTY_FUNCTION__))
;
2932 // The high part is undefined.
2933 Hi = DAG.getUNDEF(NVT);
2934 }
2935 } else if (DAG.getDataLayout().isLittleEndian()) {
2936 // Little-endian - low bits are at low addresses.
2937 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
2938 AAInfo);
2939
2940 unsigned ExcessBits =
2941 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2942 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2943
2944 // Increment the pointer to the other half.
2945 unsigned IncrementSize = NVT.getSizeInBits()/8;
2946 Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
2947 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2948 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2949 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
2950
2951 // Build a factor node to remember that this load is independent of the
2952 // other one.
2953 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2954 Hi.getValue(1));
2955 } else {
2956 // Big-endian - high bits are at low addresses. Favor aligned loads at
2957 // the cost of some bit-fiddling.
2958 EVT MemVT = N->getMemoryVT();
2959 unsigned EBytes = MemVT.getStoreSize();
2960 unsigned IncrementSize = NVT.getSizeInBits()/8;
2961 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2962
2963 // Load both the high bits and maybe some of the low bits.
2964 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2965 EVT::getIntegerVT(*DAG.getContext(),
2966 MemVT.getSizeInBits() - ExcessBits),
2967 Alignment, MMOFlags, AAInfo);
2968
2969 // Increment the pointer to the other half.
2970 Ptr = DAG.getMemBasePlusOffset(Ptr, IncrementSize, dl);
2971 // Load the rest of the low bits.
2972 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2973 N->getPointerInfo().getWithOffset(IncrementSize),
2974 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2975 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
2976
2977 // Build a factor node to remember that this load is independent of the
2978 // other one.
2979 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2980 Hi.getValue(1));
2981
2982 if (ExcessBits < NVT.getSizeInBits()) {
2983 // Transfer low bits from the bottom of Hi to the top of Lo.
2984 Lo = DAG.getNode(
2985 ISD::OR, dl, NVT, Lo,
2986 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2987 DAG.getConstant(ExcessBits, dl,
2988 TLI.getPointerTy(DAG.getDataLayout()))));
2989 // Move high bits to the right position in Hi.
2990 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2991 Hi,
2992 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2993 TLI.getPointerTy(DAG.getDataLayout())));
2994 }
2995 }
2996
2997 // Legalize the chain result - switch anything that used the old chain to
2998 // use the new one.
2999 ReplaceValueWith(SDValue(N, 1), Ch);
3000}
3001
3002void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
3003 SDValue &Lo, SDValue &Hi) {
3004 SDLoc dl(N);
3005 SDValue LL, LH, RL, RH;
3006 GetExpandedInteger(N->getOperand(0), LL, LH);
3007 GetExpandedInteger(N->getOperand(1), RL, RH);
3008 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
3009 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
3010}
3011
3012void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
3013 SDValue &Lo, SDValue &Hi) {
3014 EVT VT = N->getValueType(0);
3015 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3016 SDLoc dl(N);
3017
3018 SDValue LL, LH, RL, RH;
3019 GetExpandedInteger(N->getOperand(0), LL, LH);
3020 GetExpandedInteger(N->getOperand(1), RL, RH);
3021
3022 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG,
3023 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
3024 LL, LH, RL, RH))
3025 return;
3026
3027 // If nothing else, we can make a libcall.
3028 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3029 if (VT == MVT::i16)
3030 LC = RTLIB::MUL_I16;
3031 else if (VT == MVT::i32)
3032 LC = RTLIB::MUL_I32;
3033 else if (VT == MVT::i64)
3034 LC = RTLIB::MUL_I64;
3035 else if (VT == MVT::i128)
3036 LC = RTLIB::MUL_I128;
3037
3038 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
3039 // We'll expand the multiplication by brute force because we have no other
3040 // options. This is a trivially-generalized version of the code from
3041 // Hacker's Delight (itself derived from Knuth's Algorithm M from section
3042 // 4.3.1).
3043 unsigned Bits = NVT.getSizeInBits();
3044 unsigned HalfBits = Bits >> 1;
3045 SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl,
3046 NVT);
3047 SDValue LLL = DAG.getNode(ISD::AND, dl, NVT, LL, Mask);
3048 SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask);
3049
3050 SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
3051 SDValue TL = DAG.getNode(ISD::AND, dl, NVT, T, Mask);
3052
3053 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3054 if (APInt::getMaxValue(ShiftAmtTy.getSizeInBits()).ult(HalfBits)) {
3055 // The type from TLI is too small to fit the shift amount we want.
3056 // Override it with i32. The shift will have to be legalized.
3057 ShiftAmtTy = MVT::i32;
3058 }
3059 SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy);
3060 SDValue TH = DAG.getNode(ISD::SRL, dl, NVT, T, Shift);
3061 SDValue LLH = DAG.getNode(ISD::SRL, dl, NVT, LL, Shift);
3062 SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);
3063
3064 SDValue U = DAG.getNode(ISD::ADD, dl, NVT,
3065 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
3066 SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);
3067 SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
3068
3069 SDValue V = DAG.getNode(ISD::ADD, dl, NVT,
3070 DAG.getNode(ISD::MUL, dl, NVT, LLL, RLH), UL);
3071 SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);
3072
3073 SDValue W = DAG.getNode(ISD::ADD, dl, NVT,
3074 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
3075 DAG.getNode(ISD::ADD, dl, NVT, UH, VH));
3076 Lo = DAG.getNode(ISD::ADD, dl, NVT, TL,
3077 DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
3078
3079 Hi = DAG.getNode(ISD::ADD, dl, NVT, W,
3080 DAG.getNode(ISD::ADD, dl, NVT,
3081 DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
3082 DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
3083 return;
3084 }
3085
3086 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3087 TargetLowering::MakeLibCallOptions CallOptions;
3088 CallOptions.setSExt(true);
3089 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first,
3090 Lo, Hi);
3091}
3092
3093void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
3094 SDValue &Hi) {
3095 SDLoc DL(N);
3096 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3097 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
3098 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
3099 Lo = R.getValue(0);
3100 Hi = R.getValue(1);
3101 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
3102}
3103
3104void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
3105 SDValue &Hi) {
3106 SDValue Result = TLI.expandAddSubSat(N, DAG);
3107 SplitInteger(Result, Lo, Hi);
3108}
3109
3110/// This performs an expansion of the integer result for a fixed point
3111/// multiplication. The default expansion performs rounding down towards
3112/// negative infinity, though targets that do care about rounding should specify
3113/// a target hook for rounding and provide their own expansion or lowering of
3114/// fixed point multiplication to be consistent with rounding.
3115void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
3116 SDValue &Hi) {
3117 SDLoc dl(N);
3118 EVT VT = N->getValueType(0);
3119 unsigned VTSize = VT.getScalarSizeInBits();
3120 SDValue LHS = N->getOperand(0);
3121 SDValue RHS = N->getOperand(1);
3122 uint64_t Scale = N->getConstantOperandVal(2);
3123 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
3124 N->getOpcode() == ISD::UMULFIXSAT);
3125 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
3126 N->getOpcode() == ISD::SMULFIXSAT);
3127
3128 // Handle special case when scale is equal to zero.
3129 if (!Scale) {
3130 SDValue Result;
3131 if (!Saturating) {
3132 Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3133 } else {
3134 EVT BoolVT = getSetCCResultType(VT);
3135 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
3136 Result = DAG.getNode(MulOp, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
3137 SDValue Product = Result.getValue(0);
3138 SDValue Overflow = Result.getValue(1);
3139 if (Signed) {
3140 APInt MinVal = APInt::getSignedMinValue(VTSize);
3141 APInt MaxVal = APInt::getSignedMaxValue(VTSize);
3142 SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
3143 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3144 SDValue Zero = DAG.getConstant(0, dl, VT);
3145 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT);
3146 Result = DAG.getSelect(dl, VT, ProdNeg, SatMax, SatMin);
3147 Result = DAG.getSelect(dl, VT, Overflow, Result, Product);
3148 } else {
3149 // For unsigned multiplication, we only need to check the max since we
3150 // can't really overflow towards zero.
3151 APInt MaxVal = APInt::getMaxValue(VTSize);
3152 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
3153 Result = DAG.getSelect(dl, VT, Overflow, SatMax, Product);
3154 }
3155 }
3156 SplitInteger(Result, Lo, Hi);
3157 return;
3158 }
3159
3160 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
3161 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
3162 assert(Scale <= VTSize && "Scale can't be larger than the value type size.")((Scale <= VTSize && "Scale can't be larger than the value type size."
) ? static_cast<void> (0) : __assert_fail ("Scale <= VTSize && \"Scale can't be larger than the value type size.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3162, __PRETTY_FUNCTION__))
;
3163
3164 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3165 SDValue LL, LH, RL, RH;
3166 GetExpandedInteger(LHS, LL, LH);
3167 GetExpandedInteger(RHS, RL, RH);
3168 SmallVector<SDValue, 4> Result;
3169
3170 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
3171 if (!TLI.expandMUL_LOHI(LoHiOp, VT, dl, LHS, RHS, Result, NVT, DAG,
3172 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
3173 LL, LH, RL, RH)) {
3174 report_fatal_error("Unable to expand MUL_FIX using MUL_LOHI.");
3175 return;
3176 }
3177
3178 unsigned NVTSize = NVT.getScalarSizeInBits();
3179 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "(((VTSize == NVTSize * 2) && "Expected the new value type to be half "
"the size of the current value type") ? static_cast<void>
(0) : __assert_fail ("(VTSize == NVTSize * 2) && \"Expected the new value type to be half \" \"the size of the current value type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3180, __PRETTY_FUNCTION__))
3180 "the size of the current value type")(((VTSize == NVTSize * 2) && "Expected the new value type to be half "
"the size of the current value type") ? static_cast<void>
(0) : __assert_fail ("(VTSize == NVTSize * 2) && \"Expected the new value type to be half \" \"the size of the current value type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3180, __PRETTY_FUNCTION__))
;
3181 EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
3182
3183 // After getting the multiplication result in 4 parts, we need to perform a
3184 // shift right by the amount of the scale to get the result in that scale.
3185 //
3186 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
3187 // 128 bits that are cut into 4 32-bit parts:
3188 //
3189 // HH HL LH LL
3190 // |---32---|---32---|---32---|---32---|
3191 // 128 96 64 32 0
3192 //
3193 // |------VTSize-----|
3194 //
3195 // |NVTSize-|
3196 //
3197 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
3198 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
3199 // amount and get Lo and Hi using two funnel shifts. Or for the special case
3200 // when Scale is a multiple of NVTSize we can just pick the result without
3201 // shifting.
3202 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
3203 if (Scale % NVTSize) {
3204 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy);
3205 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0],
3206 ShiftAmount);
3207 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1],
3208 ShiftAmount);
3209 } else {
3210 Lo = Result[Part0];
3211 Hi = Result[Part0 + 1];
3212 }
3213
3214 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
3215 if (!Saturating)
3216 return;
3217
3218 // Can not overflow when there is no integer part.
3219 if (Scale == VTSize)
3220 return;
3221
3222 // To handle saturation we must check for overflow in the multiplication.
3223 //
3224 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
3225 // aren't all zeroes.
3226 //
3227 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
3228 // aren't all ones or all zeroes.
3229 //
3230 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
3231 // highest bit of HH determines saturation direction in the event of signed
3232 // saturation.
3233
3234 SDValue ResultHL = Result[2];
3235 SDValue ResultHH = Result[3];
3236
3237 SDValue SatMax, SatMin;
3238 SDValue NVTZero = DAG.getConstant(0, dl, NVT);
3239 SDValue NVTNeg1 = DAG.getConstant(-1, dl, NVT);
3240 EVT BoolNVT = getSetCCResultType(NVT);
3241
3242 if (!Signed) {
3243 if (Scale < NVTSize) {
3244 // Overflow happened if ((HH | (HL >> Scale)) != 0).
3245 SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3246 DAG.getConstant(Scale, dl, ShiftTy));
3247 SDValue Tmp = DAG.getNode(ISD::OR, dl, NVT, HLAdjusted, ResultHH);
3248 SatMax = DAG.getSetCC(dl, BoolNVT, Tmp, NVTZero, ISD::SETNE);
3249 } else if (Scale == NVTSize) {
3250 // Overflow happened if (HH != 0).
3251 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETNE);
3252 } else if (Scale < VTSize) {
3253 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
3254 SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3255 DAG.getConstant(Scale - NVTSize, dl,
3256 ShiftTy));
3257 SatMax = DAG.getSetCC(dl, BoolNVT, HLAdjusted, NVTZero, ISD::SETNE);
3258 } else
3259 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"::llvm::llvm_unreachable_internal("Scale must be less or equal to VTSize for UMULFIXSAT"
"(and saturation can't happen with Scale==VTSize).", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3260)
3260 "(and saturation can't happen with Scale==VTSize).")::llvm::llvm_unreachable_internal("Scale must be less or equal to VTSize for UMULFIXSAT"
"(and saturation can't happen with Scale==VTSize).", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3260)
;
3261
3262 Hi = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Hi);
3263 Lo = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Lo);
3264 return;
3265 }
3266
3267 if (Scale < NVTSize) {
3268 // The number of overflow bits we can check are VTSize - Scale + 1 (we
3269 // include the sign bit). If these top bits are > 0, then we overflowed past
3270 // the max value. If these top bits are < -1, then we overflowed past the
3271 // min value. Otherwise, we did not overflow.
3272 unsigned OverflowBits = VTSize - Scale + 1;
3273 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&((OverflowBits <= VTSize && OverflowBits > NVTSize
&& "Extent of overflow bits must start within HL") ?
static_cast<void> (0) : __assert_fail ("OverflowBits <= VTSize && OverflowBits > NVTSize && \"Extent of overflow bits must start within HL\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3274, __PRETTY_FUNCTION__))
3274 "Extent of overflow bits must start within HL")((OverflowBits <= VTSize && OverflowBits > NVTSize
&& "Extent of overflow bits must start within HL") ?
static_cast<void> (0) : __assert_fail ("OverflowBits <= VTSize && OverflowBits > NVTSize && \"Extent of overflow bits must start within HL\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3274, __PRETTY_FUNCTION__))
;
3275 SDValue HLHiMask = DAG.getConstant(
3276 APInt::getHighBitsSet(NVTSize, OverflowBits - NVTSize), dl, NVT);
3277 SDValue HLLoMask = DAG.getConstant(
3278 APInt::getLowBitsSet(NVTSize, VTSize - OverflowBits), dl, NVT);
3279 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
3280 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3281 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3282 SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT);
3283 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3284 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLUGT));
3285 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
3286 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3287 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3288 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT);
3289 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3290 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLULT));
3291 } else if (Scale == NVTSize) {
3292 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
3293 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3294 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3295 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT);
3296 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3297 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLNeg));
3298 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
3299 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3300 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3301 SDValue HLPos = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETGE);
3302 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3303 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLPos));
3304 } else if (Scale < VTSize) {
3305 // This is similar to the case when we saturate if Scale < NVTSize, but we
3306 // only need to check HH.
3307 unsigned OverflowBits = VTSize - Scale + 1;
3308 SDValue HHHiMask = DAG.getConstant(
3309 APInt::getHighBitsSet(NVTSize, OverflowBits), dl, NVT);
3310 SDValue HHLoMask = DAG.getConstant(
3311 APInt::getLowBitsSet(NVTSize, NVTSize - OverflowBits), dl, NVT);
3312 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, HHLoMask, ISD::SETGT);
3313 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT);
3314 } else
3315 llvm_unreachable("Illegal scale for signed fixed point mul.")::llvm::llvm_unreachable_internal("Illegal scale for signed fixed point mul."
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3315)
;
3316
3317 // Saturate to signed maximum.
3318 APInt MaxHi = APInt::getSignedMaxValue(NVTSize);
3319 APInt MaxLo = APInt::getAllOnesValue(NVTSize);
3320 Hi = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxHi, dl, NVT), Hi);
3321 Lo = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxLo, dl, NVT), Lo);
3322 // Saturate to signed minimum.
3323 APInt MinHi = APInt::getSignedMinValue(NVTSize);
3324 Hi = DAG.getSelect(dl, NVT, SatMin, DAG.getConstant(MinHi, dl, NVT), Hi);
3325 Lo = DAG.getSelect(dl, NVT, SatMin, NVTZero, Lo);
3326}
3327
3328void DAGTypeLegalizer::ExpandIntRes_DIVFIX(SDNode *N, SDValue &Lo,
3329 SDValue &Hi) {
3330 SDLoc dl(N);
3331 // Try expanding in the existing type first.
3332 SDValue Res = TLI.expandFixedPointDiv(N->getOpcode(), dl, N->getOperand(0),
3333 N->getOperand(1),
3334 N->getConstantOperandVal(2), DAG);
3335
3336 if (!Res)
3337 Res = earlyExpandDIVFIX(N, N->getOperand(0), N->getOperand(1),
3338 N->getConstantOperandVal(2), TLI, DAG);
3339 SplitInteger(Res, Lo, Hi);
3340}
3341
3342void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
3343 SDValue &Lo, SDValue &Hi) {
3344 SDValue LHS = Node->getOperand(0);
3345 SDValue RHS = Node->getOperand(1);
3346 SDLoc dl(Node);
3347
3348 // Expand the result by simply replacing it with the equivalent
3349 // non-overflow-checking operation.
3350 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3351 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3352 LHS, RHS);
3353 SplitInteger(Sum, Lo, Hi);
3354
3355 // Compute the overflow.
3356 //
3357 // LHSSign -> LHS >= 0
3358 // RHSSign -> RHS >= 0
3359 // SumSign -> Sum >= 0
3360 //
3361 // Add:
3362 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3363 // Sub:
3364 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3365 //
3366 EVT OType = Node->getValueType(1);
3367 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3368
3369 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3370 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3371 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3372 Node->getOpcode() == ISD::SADDO ?
3373 ISD::SETEQ : ISD::SETNE);
3374
3375 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3376 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3377
3378 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3379
3380 // Use the calculated overflow everywhere.
3381 ReplaceValueWith(SDValue(Node, 1), Cmp);
3382}
3383
3384void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
3385 SDValue &Lo, SDValue &Hi) {
3386 EVT VT = N->getValueType(0);
3387 SDLoc dl(N);
3388 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3389
3390 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3391 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3392 SplitInteger(Res.getValue(0), Lo, Hi);
3393 return;
3394 }
3395
3396 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3397 if (VT == MVT::i16)
3398 LC = RTLIB::SDIV_I16;
3399 else if (VT == MVT::i32)
3400 LC = RTLIB::SDIV_I32;
3401 else if (VT == MVT::i64)
3402 LC = RTLIB::SDIV_I64;
3403 else if (VT == MVT::i128)
3404 LC = RTLIB::SDIV_I128;
3405 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported SDIV!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3405, __PRETTY_FUNCTION__))
;
3406
3407 TargetLowering::MakeLibCallOptions CallOptions;
3408 CallOptions.setSExt(true);
3409 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3410}
3411
3412void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
3413 SDValue &Lo, SDValue &Hi) {
3414 EVT VT = N->getValueType(0);
3415 SDLoc dl(N);
3416
3417 // If we can emit an efficient shift operation, do so now. Check to see if
3418 // the RHS is a constant.
3419 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
7
Assuming 'CN' is null
8
Taking false branch
3420 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
3421
3422 // If we can determine that the high bit of the shift is zero or one, even if
3423 // the low bits are variable, emit this shift in an optimized form.
3424 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
9
Calling 'DAGTypeLegalizer::ExpandShiftWithKnownAmountBit'
3425 return;
3426
3427 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
3428 unsigned PartsOpc;
3429 if (N->getOpcode() == ISD::SHL) {
3430 PartsOpc = ISD::SHL_PARTS;
3431 } else if (N->getOpcode() == ISD::SRL) {
3432 PartsOpc = ISD::SRL_PARTS;
3433 } else {
3434 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")((N->getOpcode() == ISD::SRA && "Unknown shift!") ?
static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3434, __PRETTY_FUNCTION__))
;
3435 PartsOpc = ISD::SRA_PARTS;
3436 }
3437
3438 // Next check to see if the target supports this SHL_PARTS operation or if it
3439 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
3440 // size, but create a libcall instead.
3441 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3442 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
3443 const bool LegalOrCustom =
3444 (Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3445 Action == TargetLowering::Custom;
3446
3447 if (LegalOrCustom && TLI.shouldExpandShift(DAG, N)) {
3448 // Expand the subcomponents.
3449 SDValue LHSL, LHSH;
3450 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
3451 EVT VT = LHSL.getValueType();
3452
3453 // If the shift amount operand is coming from a vector legalization it may
3454 // have an illegal type. Fix that first by casting the operand, otherwise
3455 // the new SHL_PARTS operation would need further legalization.
3456 SDValue ShiftOp = N->getOperand(1);
3457 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3458 assert(ShiftTy.getScalarSizeInBits() >=((ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits
()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? static_cast<void> (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3460, __PRETTY_FUNCTION__))
3459 Log2_32_Ceil(VT.getScalarSizeInBits()) &&((ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits
()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? static_cast<void> (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3460, __PRETTY_FUNCTION__))
3460 "ShiftAmountTy is too small to cover the range of this type!")((ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits
()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? static_cast<void> (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3460, __PRETTY_FUNCTION__))
;
3461 if (ShiftOp.getValueType() != ShiftTy)
3462 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
3463
3464 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
3465 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
3466 Hi = Lo.getValue(1);
3467 return;
3468 }
3469
3470 // Otherwise, emit a libcall.
3471 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3472 bool isSigned;
3473 if (N->getOpcode() == ISD::SHL) {
3474 isSigned = false; /*sign irrelevant*/
3475 if (VT == MVT::i16)
3476 LC = RTLIB::SHL_I16;
3477 else if (VT == MVT::i32)
3478 LC = RTLIB::SHL_I32;
3479 else if (VT == MVT::i64)
3480 LC = RTLIB::SHL_I64;
3481 else if (VT == MVT::i128)
3482 LC = RTLIB::SHL_I128;
3483 } else if (N->getOpcode() == ISD::SRL) {
3484 isSigned = false;
3485 if (VT == MVT::i16)
3486 LC = RTLIB::SRL_I16;
3487 else if (VT == MVT::i32)
3488 LC = RTLIB::SRL_I32;
3489 else if (VT == MVT::i64)
3490 LC = RTLIB::SRL_I64;
3491 else if (VT == MVT::i128)
3492 LC = RTLIB::SRL_I128;
3493 } else {
3494 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")((N->getOpcode() == ISD::SRA && "Unknown shift!") ?
static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3494, __PRETTY_FUNCTION__))
;
3495 isSigned = true;
3496 if (VT == MVT::i16)
3497 LC = RTLIB::SRA_I16;
3498 else if (VT == MVT::i32)
3499 LC = RTLIB::SRA_I32;
3500 else if (VT == MVT::i64)
3501 LC = RTLIB::SRA_I64;
3502 else if (VT == MVT::i128)
3503 LC = RTLIB::SRA_I128;
3504 }
3505
3506 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
3507 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3508 TargetLowering::MakeLibCallOptions CallOptions;
3509 CallOptions.setSExt(isSigned);
3510 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3511 return;
3512 }
3513
3514 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
3515 llvm_unreachable("Unsupported shift!")::llvm::llvm_unreachable_internal("Unsupported shift!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3515)
;
3516}
3517
3518void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
3519 SDValue &Lo, SDValue &Hi) {
3520 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3521 SDLoc dl(N);
3522 SDValue Op = N->getOperand(0);
3523 if (Op.getValueType().bitsLE(NVT)) {
3524 // The low part is sign extension of the input (degenerates to a copy).
3525 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
3526 // The high part is obtained by SRA'ing all but one of the bits of low part.
3527 unsigned LoSize = NVT.getSizeInBits();
3528 Hi = DAG.getNode(
3529 ISD::SRA, dl, NVT, Lo,
3530 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
3531 } else {
3532 // For example, extension of an i48 to an i64. The operand type necessarily
3533 // promotes to the result type, so will end up being expanded too.
3534 assert(getTypeAction(Op.getValueType()) ==((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3536, __PRETTY_FUNCTION__))
3535 TargetLowering::TypePromoteInteger &&((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3536, __PRETTY_FUNCTION__))
3536 "Only know how to promote this result!")((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3536, __PRETTY_FUNCTION__))
;
3537 SDValue Res = GetPromotedInteger(Op);
3538 assert(Res.getValueType() == N->getValueType(0) &&((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3539, __PRETTY_FUNCTION__))
3539 "Operand over promoted?")((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3539, __PRETTY_FUNCTION__))
;
3540 // Split the promoted operand. This will simplify when it is expanded.
3541 SplitInteger(Res, Lo, Hi);
3542 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
3543 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
3544 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
3545 ExcessBits)));
3546 }
3547}
3548
3549void DAGTypeLegalizer::
3550ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
3551 SDLoc dl(N);
3552 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3553 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3554
3555 if (EVT.bitsLE(Lo.getValueType())) {
3556 // sext_inreg the low part if needed.
3557 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
3558 N->getOperand(1));
3559
3560 // The high part gets the sign extension from the lo-part. This handles
3561 // things like sextinreg V:i64 from i8.
3562 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
3563 DAG.getConstant(Hi.getValueSizeInBits() - 1, dl,
3564 TLI.getPointerTy(DAG.getDataLayout())));
3565 } else {
3566 // For example, extension of an i48 to an i64. Leave the low part alone,
3567 // sext_inreg the high part.
3568 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
3569 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
3570 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
3571 ExcessBits)));
3572 }
3573}
3574
3575void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
3576 SDValue &Lo, SDValue &Hi) {
3577 EVT VT = N->getValueType(0);
3578 SDLoc dl(N);
3579 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3580
3581 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3582 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3583 SplitInteger(Res.getValue(1), Lo, Hi);
3584 return;
3585 }
3586
3587 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3588 if (VT == MVT::i16)
3589 LC = RTLIB::SREM_I16;
3590 else if (VT == MVT::i32)
3591 LC = RTLIB::SREM_I32;
3592 else if (VT == MVT::i64)
3593 LC = RTLIB::SREM_I64;
3594 else if (VT == MVT::i128)
3595 LC = RTLIB::SREM_I128;
3596 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported SREM!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3596, __PRETTY_FUNCTION__))
;
3597
3598 TargetLowering::MakeLibCallOptions CallOptions;
3599 CallOptions.setSExt(true);
3600 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3601}
3602
3603void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
3604 SDValue &Lo, SDValue &Hi) {
3605 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3606 SDLoc dl(N);
3607 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
3608 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
3609 N->getOperand(0),
3610 DAG.getConstant(NVT.getSizeInBits(), dl,
3611 TLI.getPointerTy(DAG.getDataLayout())));
3612 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
3613}
3614
3615void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
3616 SDValue &Lo, SDValue &Hi) {
3617 EVT VT = N->getValueType(0);
3618 SDLoc dl(N);
3619
3620 if (N->getOpcode() == ISD::UMULO) {
3621 // This section expands the operation into the following sequence of
3622 // instructions. `iNh` here refers to a type which has half the bit width of
3623 // the type the original operation operated on.
3624 //
3625 // %0 = %LHS.HI != 0 && %RHS.HI != 0
3626 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
3627 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
3628 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
3629 // %4 = add iN (%1.0 as iN) << Nh, (%2.0 as iN) << Nh
3630 // %5 = { iN, i1 } @uadd.with.overflow.iN( %4, %3 )
3631 //
3632 // %res = { %5.0, %0 || %1.1 || %2.1 || %5.1 }
3633 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
3634 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
3635 SplitInteger(LHS, LHSLow, LHSHigh);
3636 SplitInteger(RHS, RHSLow, RHSHigh);
3637 EVT HalfVT = LHSLow.getValueType()
3638 , BitVT = N->getValueType(1);
3639 SDVTList VTHalfMulO = DAG.getVTList(HalfVT, BitVT);
3640 SDVTList VTFullAddO = DAG.getVTList(VT, BitVT);
3641
3642 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT);
3643 SDValue Overflow = DAG.getNode(ISD::AND, dl, BitVT,
3644 DAG.getSetCC(dl, BitVT, LHSHigh, HalfZero, ISD::SETNE),
3645 DAG.getSetCC(dl, BitVT, RHSHigh, HalfZero, ISD::SETNE));
3646
3647 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, LHSHigh, RHSLow);
3648 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, One.getValue(1));
3649 SDValue OneInHigh = DAG.getNode(ISD::BUILD_PAIR, dl, VT, HalfZero,
3650 One.getValue(0));
3651
3652 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, RHSHigh, LHSLow);
3653 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Two.getValue(1));
3654 SDValue TwoInHigh = DAG.getNode(ISD::BUILD_PAIR, dl, VT, HalfZero,
3655 Two.getValue(0));
3656
3657 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
3658 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
3659 // operation recursively legalized?).
3660 //
3661 // Many backends understand this pattern and will convert into LOHI
3662 // themselves, if applicable.
3663 SDValue Three = DAG.getNode(ISD::MUL, dl, VT,
3664 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LHSLow),
3665 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RHSLow));
3666 SDValue Four = DAG.getNode(ISD::ADD, dl, VT, OneInHigh, TwoInHigh);
3667 SDValue Five = DAG.getNode(ISD::UADDO, dl, VTFullAddO, Three, Four);
3668 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Five.getValue(1));
3669 SplitInteger(Five, Lo, Hi);
3670 ReplaceValueWith(SDValue(N, 1), Overflow);
3671 return;
3672 }
3673
3674 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
3675 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
3676 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
3677
3678 // Replace this with a libcall that will check overflow.
3679 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3680 if (VT == MVT::i32)
3681 LC = RTLIB::MULO_I32;
3682 else if (VT == MVT::i64)
3683 LC = RTLIB::MULO_I64;
3684 else if (VT == MVT::i128)
3685 LC = RTLIB::MULO_I128;
3686 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported XMULO!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3686, __PRETTY_FUNCTION__))
;
3687
3688 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
3689 // Temporary for the overflow value, default it to zero.
3690 SDValue Chain =
3691 DAG.getStore(DAG.getEntryNode(), dl, DAG.getConstant(0, dl, PtrVT), Temp,
3692 MachinePointerInfo());
3693
3694 TargetLowering::ArgListTy Args;
3695 TargetLowering::ArgListEntry Entry;
3696 for (const SDValue &Op : N->op_values()) {
3697 EVT ArgVT = Op.getValueType();
3698 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
3699 Entry.Node = Op;
3700 Entry.Ty = ArgTy;
3701 Entry.IsSExt = true;
3702 Entry.IsZExt = false;
3703 Args.push_back(Entry);
3704 }
3705
3706 // Also pass the address of the overflow check.
3707 Entry.Node = Temp;
3708 Entry.Ty = PtrTy->getPointerTo();
3709 Entry.IsSExt = true;
3710 Entry.IsZExt = false;
3711 Args.push_back(Entry);
3712
3713 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
3714
3715 TargetLowering::CallLoweringInfo CLI(DAG);
3716 CLI.setDebugLoc(dl)
3717 .setChain(Chain)
3718 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args))
3719 .setSExtResult();
3720
3721 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
3722
3723 SplitInteger(CallInfo.first, Lo, Hi);
3724 SDValue Temp2 =
3725 DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, MachinePointerInfo());
3726 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
3727 DAG.getConstant(0, dl, PtrVT),
3728 ISD::SETNE);
3729 // Use the overflow from the libcall everywhere.
3730 ReplaceValueWith(SDValue(N, 1), Ofl);
3731}
3732
3733void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
3734 SDValue &Lo, SDValue &Hi) {
3735 EVT VT = N->getValueType(0);
3736 SDLoc dl(N);
3737 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3738
3739 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
3740 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3741 SplitInteger(Res.getValue(0), Lo, Hi);
3742 return;
3743 }
3744
3745 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3746 if (VT == MVT::i16)
3747 LC = RTLIB::UDIV_I16;
3748 else if (VT == MVT::i32)
3749 LC = RTLIB::UDIV_I32;
3750 else if (VT == MVT::i64)
3751 LC = RTLIB::UDIV_I64;
3752 else if (VT == MVT::i128)
3753 LC = RTLIB::UDIV_I128;
3754 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported UDIV!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3754, __PRETTY_FUNCTION__))
;
3755
3756 TargetLowering::MakeLibCallOptions CallOptions;
3757 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3758}
3759
3760void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
3761 SDValue &Lo, SDValue &Hi) {
3762 EVT VT = N->getValueType(0);
3763 SDLoc dl(N);
3764 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3765
3766 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
3767 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3768 SplitInteger(Res.getValue(1), Lo, Hi);
3769 return;
3770 }
3771
3772 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3773 if (VT == MVT::i16)
3774 LC = RTLIB::UREM_I16;
3775 else if (VT == MVT::i32)
3776 LC = RTLIB::UREM_I32;
3777 else if (VT == MVT::i64)
3778 LC = RTLIB::UREM_I64;
3779 else if (VT == MVT::i128)
3780 LC = RTLIB::UREM_I128;
3781 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported UREM!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3781, __PRETTY_FUNCTION__))
;
3782
3783 TargetLowering::MakeLibCallOptions CallOptions;
3784 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3785}
3786
3787void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
3788 SDValue &Lo, SDValue &Hi) {
3789 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3790 SDLoc dl(N);
3791 SDValue Op = N->getOperand(0);
3792 if (Op.getValueType().bitsLE(NVT)) {
3793 // The low part is zero extension of the input (degenerates to a copy).
3794 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
3795 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
3796 } else {
3797 // For example, extension of an i48 to an i64. The operand type necessarily
3798 // promotes to the result type, so will end up being expanded too.
3799 assert(getTypeAction(Op.getValueType()) ==((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3801, __PRETTY_FUNCTION__))
3800 TargetLowering::TypePromoteInteger &&((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3801, __PRETTY_FUNCTION__))
3801 "Only know how to promote this result!")((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3801, __PRETTY_FUNCTION__))
;
3802 SDValue Res = GetPromotedInteger(Op);
3803 assert(Res.getValueType() == N->getValueType(0) &&((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3804, __PRETTY_FUNCTION__))
3804 "Operand over promoted?")((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3804, __PRETTY_FUNCTION__))
;
3805 // Split the promoted operand. This will simplify when it is expanded.
3806 SplitInteger(Res, Lo, Hi);
3807 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
3808 Hi = DAG.getZeroExtendInReg(Hi, dl,
3809 EVT::getIntegerVT(*DAG.getContext(),
3810 ExcessBits));
3811 }
3812}
3813
3814void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
3815 SDValue &Lo, SDValue &Hi) {
3816 SDLoc dl(N);
3817 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
3818 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
3819 SDValue Zero = DAG.getConstant(0, dl, VT);
3820 SDValue Swap = DAG.getAtomicCmpSwap(
3821 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
3822 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
3823 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand());
3824
3825 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
3826 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
3827}
3828
3829void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
3830 SDValue &Lo, SDValue &Hi) {
3831 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
3832 // both halves independently.
3833 SDValue Res = TLI.expandVecReduce(N, DAG);
3834 SplitInteger(Res, Lo, Hi);
3835}
3836
3837//===----------------------------------------------------------------------===//
3838// Integer Operand Expansion
3839//===----------------------------------------------------------------------===//
3840
3841/// ExpandIntegerOperand - This method is called when the specified operand of
3842/// the specified node is found to need expansion. At this point, all of the
3843/// result types of the node are known to be legal, but other operands of the
3844/// node may need promotion or expansion as well as the specified one.
3845bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
3846 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
3847 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
3848 SDValue Res = SDValue();
3849
3850 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3851 return false;
3852
3853 switch (N->getOpcode()) {
3854 default:
3855 #ifndef NDEBUG
3856 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
3857 N->dump(&DAG); dbgs() << "\n";
3858 #endif
3859 report_fatal_error("Do not know how to expand this operator's operand!");
3860
3861 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
3862 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
3863 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
3864 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
3865 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
3866 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
3867 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
3868 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
3869 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
3870 case ISD::STRICT_SINT_TO_FP:
3871 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
3872 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
3873 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
3874 case ISD::STRICT_UINT_TO_FP:
3875 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
3876
3877 case ISD::SHL:
3878 case ISD::SRA:
3879 case ISD::SRL:
3880 case ISD::ROTL:
3881 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
3882 case ISD::RETURNADDR:
3883 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
3884
3885 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
3886 }
3887
3888 // If the result is null, the sub-method took care of registering results etc.
3889 if (!Res.getNode()) return false;
3890
3891 // If the result is N, the sub-method updated N in place. Tell the legalizer
3892 // core about this.
3893 if (Res.getNode() == N)
3894 return true;
3895
3896 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3897, __PRETTY_FUNCTION__))
3897 "Invalid operand expansion")((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3897, __PRETTY_FUNCTION__))
;
3898
3899 ReplaceValueWith(SDValue(N, 0), Res);
3900 return false;
3901}
3902
3903/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
3904/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
3905void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
3906 SDValue &NewRHS,
3907 ISD::CondCode &CCCode,
3908 const SDLoc &dl) {
3909 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
3910 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
3911 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
3912
3913 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
3914 if (RHSLo == RHSHi) {
3915 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
3916 if (RHSCST->isAllOnesValue()) {
3917 // Equality comparison to -1.
3918 NewLHS = DAG.getNode(ISD::AND, dl,
3919 LHSLo.getValueType(), LHSLo, LHSHi);
3920 NewRHS = RHSLo;
3921 return;
3922 }
3923 }
3924 }
3925
3926 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
3927 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
3928 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
3929 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
3930 return;
3931 }
3932
3933 // If this is a comparison of the sign bit, just look at the top part.
3934 // X > -1, x < 0
3935 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
3936 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
3937 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
3938 NewLHS = LHSHi;
3939 NewRHS = RHSHi;
3940 return;
3941 }
3942
3943 // FIXME: This generated code sucks.
3944 ISD::CondCode LowCC;
3945 switch (CCCode) {
3946 default: llvm_unreachable("Unknown integer setcc!")::llvm::llvm_unreachable_internal("Unknown integer setcc!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3946)
;
3947 case ISD::SETLT:
3948 case ISD::SETULT: LowCC = ISD::SETULT; break;
3949 case ISD::SETGT:
3950 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3951 case ISD::SETLE:
3952 case ISD::SETULE: LowCC = ISD::SETULE; break;
3953 case ISD::SETGE:
3954 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3955 }
3956
3957 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
3958 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
3959 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
3960
3961 // NOTE: on targets without efficient SELECT of bools, we can always use
3962 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3963 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
3964 nullptr);
3965 SDValue LoCmp, HiCmp;
3966 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
3967 TLI.isTypeLegal(RHSLo.getValueType()))
3968 LoCmp = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()), LHSLo,
3969 RHSLo, LowCC, false, DagCombineInfo, dl);
3970 if (!LoCmp.getNode())
3971 LoCmp = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo,
3972 RHSLo, LowCC);
3973 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
3974 TLI.isTypeLegal(RHSHi.getValueType()))
3975 HiCmp = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()), LHSHi,
3976 RHSHi, CCCode, false, DagCombineInfo, dl);
3977 if (!HiCmp.getNode())
3978 HiCmp =
3979 DAG.getNode(ISD::SETCC, dl, getSetCCResultType(LHSHi.getValueType()),
3980 LHSHi, RHSHi, DAG.getCondCode(CCCode));
3981
3982 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(LoCmp.getNode());
3983 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(HiCmp.getNode());
3984
3985 bool EqAllowed = (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
3986 CCCode == ISD::SETUGE || CCCode == ISD::SETULE);
3987
3988 if ((EqAllowed && (HiCmpC && HiCmpC->isNullValue())) ||
3989 (!EqAllowed && ((HiCmpC && (HiCmpC->getAPIntValue() == 1)) ||
3990 (LoCmpC && LoCmpC->isNullValue())))) {
3991 // For LE / GE, if high part is known false, ignore the low part.
3992 // For LT / GT: if low part is known false, return the high part.
3993 // if high part is known true, ignore the low part.
3994 NewLHS = HiCmp;
3995 NewRHS = SDValue();
3996 return;
3997 }
3998
3999 if (LHSHi == RHSHi) {
4000 // Comparing the low bits is enough.
4001 NewLHS = LoCmp;
4002 NewRHS = SDValue();
4003 return;
4004 }
4005
4006 // Lower with SETCCCARRY if the target supports it.
4007 EVT HiVT = LHSHi.getValueType();
4008 EVT ExpandVT = TLI.getTypeToExpandTo(*DAG.getContext(), HiVT);
4009 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(ISD::SETCCCARRY, ExpandVT);
4010
4011 // FIXME: Make all targets support this, then remove the other lowering.
4012 if (HasSETCCCARRY) {
4013 // SETCCCARRY can detect < and >= directly. For > and <=, flip
4014 // operands and condition code.
4015 bool FlipOperands = false;
4016 switch (CCCode) {
4017 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
4018 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
4019 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
4020 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
4021 default: break;
4022 }
4023 if (FlipOperands) {
4024 std::swap(LHSLo, RHSLo);
4025 std::swap(LHSHi, RHSHi);
4026 }
4027 // Perform a wide subtraction, feeding the carry from the low part into
4028 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
4029 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
4030 // zero or positive iff LHS >= RHS.
4031 EVT LoVT = LHSLo.getValueType();
4032 SDVTList VTList = DAG.getVTList(LoVT, getSetCCResultType(LoVT));
4033 SDValue LowCmp = DAG.getNode(ISD::USUBO, dl, VTList, LHSLo, RHSLo);
4034 SDValue Res = DAG.getNode(ISD::SETCCCARRY, dl, getSetCCResultType(HiVT),
4035 LHSHi, RHSHi, LowCmp.getValue(1),
4036 DAG.getCondCode(CCCode));
4037 NewLHS = Res;
4038 NewRHS = SDValue();
4039 return;
4040 }
4041
4042 NewLHS = TLI.SimplifySetCC(getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ,
4043 false, DagCombineInfo, dl);
4044 if (!NewLHS.getNode())
4045 NewLHS =
4046 DAG.getSetCC(dl, getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ);
4047 NewLHS = DAG.getSelect(dl, LoCmp.getValueType(), NewLHS, LoCmp, HiCmp);
4048 NewRHS = SDValue();
4049}
4050
4051SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
4052 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
4053 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
4054 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
4055
4056 // If ExpandSetCCOperands returned a scalar, we need to compare the result
4057 // against zero to select between true and false values.
4058 if (!NewRHS.getNode()) {
4059 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
4060 CCCode = ISD::SETNE;
4061 }
4062
4063 // Update N to have the operands specified.
4064 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
4065 DAG.getCondCode(CCCode), NewLHS, NewRHS,
4066 N->getOperand(4)), 0);
4067}
4068
4069SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
4070 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
4071 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
4072 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
4073
4074 // If ExpandSetCCOperands returned a scalar, we need to compare the result
4075 // against zero to select between true and false values.
4076 if (!NewRHS.getNode()) {
4077 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
4078 CCCode = ISD::SETNE;
4079 }
4080
4081 // Update N to have the operands specified.
4082 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
4083 N->getOperand(2), N->getOperand(3),
4084 DAG.getCondCode(CCCode)), 0);
4085}
4086
4087SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
4088 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
4089 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
4090 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
4091
4092 // If ExpandSetCCOperands returned a scalar, use it.
4093 if (!NewRHS.getNode()) {
4094 assert(NewLHS.getValueType() == N->getValueType(0) &&((NewLHS.getValueType() == N->getValueType(0) && "Unexpected setcc expansion!"
) ? static_cast<void> (0) : __assert_fail ("NewLHS.getValueType() == N->getValueType(0) && \"Unexpected setcc expansion!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4095, __PRETTY_FUNCTION__))
4095 "Unexpected setcc expansion!")((NewLHS.getValueType() == N->getValueType(0) && "Unexpected setcc expansion!"
) ? static_cast<void> (0) : __assert_fail ("NewLHS.getValueType() == N->getValueType(0) && \"Unexpected setcc expansion!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4095, __PRETTY_FUNCTION__))
;
4096 return NewLHS;
4097 }
4098
4099 // Otherwise, update N to have the operands specified.
4100 return SDValue(
4101 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0);
4102}
4103
4104SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
4105 SDValue LHS = N->getOperand(0);
4106 SDValue RHS = N->getOperand(1);
4107 SDValue Carry = N->getOperand(2);
4108 SDValue Cond = N->getOperand(3);
4109 SDLoc dl = SDLoc(N);
4110
4111 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
4112 GetExpandedInteger(LHS, LHSLo, LHSHi);
4113 GetExpandedInteger(RHS, RHSLo, RHSHi);
4114
4115 // Expand to a SUBE for the low part and a smaller SETCCCARRY for the high.
4116 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), Carry.getValueType());
4117 SDValue LowCmp = DAG.getNode(ISD::SUBCARRY, dl, VTList, LHSLo, RHSLo, Carry);
4118 return DAG.getNode(ISD::SETCCCARRY, dl, N->getValueType(0), LHSHi, RHSHi,
4119 LowCmp.getValue(1), Cond);
4120}
4121
4122SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
4123 // The value being shifted is legal, but the shift amount is too big.
4124 // It follows that either the result of the shift is undefined, or the
4125 // upper half of the shift amount is zero. Just use the lower half.
4126 SDValue Lo, Hi;
4127 GetExpandedInteger(N->getOperand(1), Lo, Hi);
4128 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
4129}
4130
4131SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
4132 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
4133 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
4134 // constant to valid type.
4135 SDValue Lo, Hi;
4136 GetExpandedInteger(N->getOperand(0), Lo, Hi);
4137 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
4138}
4139
4140SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
4141 bool IsStrict = N->isStrictFPOpcode();
4142 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
4143 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
4144 EVT DstVT = N->getValueType(0);
4145 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
4146 assert(LC != RTLIB::UNKNOWN_LIBCALL &&((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this SINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this SINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4147, __PRETTY_FUNCTION__))
4147 "Don't know how to expand this SINT_TO_FP!")((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this SINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this SINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4147, __PRETTY_FUNCTION__))
;
4148 TargetLowering::MakeLibCallOptions CallOptions;
4149 CallOptions.setSExt(true);
4150 std::pair<SDValue, SDValue> Tmp =
4151 TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
4152
4153 if (!IsStrict)
4154 return Tmp.first;
4155
4156 ReplaceValueWith(SDValue(N, 1), Tmp.second);
4157 ReplaceValueWith(SDValue(N, 0), Tmp.first);
4158 return SDValue();
4159}
4160
4161SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
4162 if (N->isAtomic()) {
4163 // It's typical to have larger CAS than atomic store instructions.
4164 SDLoc dl(N);
4165 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
4166 N->getMemoryVT(),
4167 N->getOperand(0), N->getOperand(2),
4168 N->getOperand(1),
4169 N->getMemOperand());
4170 return Swap.getValue(1);
4171 }
4172 if (ISD::isNormalStore(N))
4173 return ExpandOp_NormalStore(N, OpNo);
4174
4175 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!")((ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDStore(N) && \"Indexed store during type legalization!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4175, __PRETTY_FUNCTION__))
;
4176 assert(OpNo == 1 && "Can only expand the stored value so far")((OpNo == 1 && "Can only expand the stored value so far"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 1 && \"Can only expand the stored value so far\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4176, __PRETTY_FUNCTION__))
;
4177
4178 EVT VT = N->getOperand(1).getValueType();
4179 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4180 SDValue Ch = N->getChain();
4181 SDValue Ptr = N->getBasePtr();
4182 unsigned Alignment = N->getAlignment();
4183 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
4184 AAMDNodes AAInfo = N->getAAInfo();
4185 SDLoc dl(N);
4186 SDValue Lo, Hi;
4187
4188 assert(NVT.isByteSized() && "Expanded type not byte sized!")((NVT.isByteSized() && "Expanded type not byte sized!"
) ? static_cast<void> (0) : __assert_fail ("NVT.isByteSized() && \"Expanded type not byte sized!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4188, __PRETTY_FUNCTION__))
;
4189
4190 if (N->getMemoryVT().bitsLE(NVT)) {
4191 GetExpandedInteger(N->getValue(), Lo, Hi);
4192 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
4193 N->getMemoryVT(), Alignment, MMOFlags, AAInfo);
4194 }
4195
4196 if (DAG.getDataLayout().isLittleEndian()) {
4197 // Little-endian - low bits are at low addresses.
4198 GetExpandedInteger(N->getValue(), Lo, Hi);
4199
4200 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
4201 AAInfo);
4202
4203 unsigned ExcessBits =
4204 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
4205 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
4206
4207 // Increment the pointer to the other half.
4208 unsigned IncrementSize = NVT.getSizeInBits()/8;
4209 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
4210 Hi = DAG.getTruncStore(
4211 Ch, dl, Hi, Ptr, N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
4212 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
4213 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
4214 }
4215
4216 // Big-endian - high bits are at low addresses. Favor aligned stores at
4217 // the cost of some bit-fiddling.
4218 GetExpandedInteger(N->getValue(), Lo, Hi);
4219
4220 EVT ExtVT = N->getMemoryVT();
4221 unsigned EBytes = ExtVT.getStoreSize();
4222 unsigned IncrementSize = NVT.getSizeInBits()/8;
4223 unsigned ExcessBits = (EBytes - IncrementSize)*8;
4224 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
4225 ExtVT.getSizeInBits() - ExcessBits);
4226
4227 if (ExcessBits < NVT.getSizeInBits()) {
4228 // Transfer high bits from the top of Lo to the bottom of Hi.
4229 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
4230 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
4231 TLI.getPointerTy(DAG.getDataLayout())));
4232 Hi = DAG.getNode(
4233 ISD::OR, dl, NVT, Hi,
4234 DAG.getNode(ISD::SRL, dl, NVT, Lo,
4235 DAG.getConstant(ExcessBits, dl,
4236 TLI.getPointerTy(DAG.getDataLayout()))));
4237 }
4238
4239 // Store both the high bits and maybe some of the low bits.
4240 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), HiVT, Alignment,
4241 MMOFlags, AAInfo);
4242
4243 // Increment the pointer to the other half.
4244 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
4245 // Store the lowest ExcessBits bits in the second half.
4246 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
4247 N->getPointerInfo().getWithOffset(IncrementSize),
4248 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
4249 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
4250 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
4251}
4252
4253SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
4254 SDValue InL, InH;
4255 GetExpandedInteger(N->getOperand(0), InL, InH);
4256 // Just truncate the low part of the source.
4257 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
4258}
4259
4260SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
4261 bool IsStrict = N->isStrictFPOpcode();
4262 SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
4263 SDValue Op = N->getOperand(IsStrict ? 1 : 0);
4264 EVT DstVT = N->getValueType(0);
4265 RTLIB::Libcall LC = RTLIB::getUINTTOFP(Op.getValueType(), DstVT);
4266 assert(LC != RTLIB::UNKNOWN_LIBCALL &&((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this UINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this UINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4267, __PRETTY_FUNCTION__))
4267 "Don't know how to expand this UINT_TO_FP!")((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this UINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this UINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4267, __PRETTY_FUNCTION__))
;
4268 TargetLowering::MakeLibCallOptions CallOptions;
4269 CallOptions.setSExt(true);
4270 std::pair<SDValue, SDValue> Tmp =
4271 TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N), Chain);
4272
4273 if (!IsStrict)
4274 return Tmp.first;
4275
4276 ReplaceValueWith(SDValue(N, 1), Tmp.second);
4277 ReplaceValueWith(SDValue(N, 0), Tmp.first);
4278 return SDValue();
4279}
4280
4281SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
4282 SDLoc dl(N);
4283 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
4284 cast<AtomicSDNode>(N)->getMemoryVT(),
4285 N->getOperand(0),
4286 N->getOperand(1), N->getOperand(2),
4287 cast<AtomicSDNode>(N)->getMemOperand());
4288 return Swap.getValue(1);
4289}
4290
4291
4292SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
4293
4294 EVT OutVT = N->getValueType(0);
4295 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4296 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4296, __PRETTY_FUNCTION__))
;
4297 unsigned OutNumElems = OutVT.getVectorNumElements();
4298 EVT NOutVTElem = NOutVT.getVectorElementType();
4299
4300 SDLoc dl(N);
4301 SDValue BaseIdx = N->getOperand(1);
4302
4303 SDValue InOp0 = N->getOperand(0);
4304 if (getTypeAction(InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
4305 InOp0 = GetPromotedInteger(N->getOperand(0));
4306
4307 EVT InVT = InOp0.getValueType();
4308
4309 SmallVector<SDValue, 8> Ops;
4310 Ops.reserve(OutNumElems);
4311 for (unsigned i = 0; i != OutNumElems; ++i) {
4312
4313 // Extract the element from the original vector.
4314 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
4315 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
4316 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4317 InVT.getVectorElementType(), N->getOperand(0), Index);
4318
4319 SDValue Op = DAG.getAnyExtOrTrunc(Ext, dl, NOutVTElem);
4320 // Insert the converted element to the new vector.
4321 Ops.push_back(Op);
4322 }
4323
4324 return DAG.getBuildVector(NOutVT, dl, Ops);
4325}
4326
4327
4328SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
4329 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
4330 EVT VT = N->getValueType(0);
4331 SDLoc dl(N);
4332
4333 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
4334
4335 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4336 SDValue V1 = GetPromotedInteger(N->getOperand(1));
4337 EVT OutVT = V0.getValueType();
4338
4339 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
4340}
4341
4342
4343SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
4344 EVT OutVT = N->getValueType(0);
4345 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4346 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4346, __PRETTY_FUNCTION__))
;
4347 unsigned NumElems = N->getNumOperands();
4348 EVT NOutVTElem = NOutVT.getVectorElementType();
4349
4350 SDLoc dl(N);
4351
4352 SmallVector<SDValue, 8> Ops;
4353 Ops.reserve(NumElems);
4354 for (unsigned i = 0; i != NumElems; ++i) {
4355 SDValue Op;
4356 // BUILD_VECTOR integer operand types are allowed to be larger than the
4357 // result's element type. This may still be true after the promotion. For
4358 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
4359 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
4360 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
4361 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
4362 else
4363 Op = N->getOperand(i);
4364 Ops.push_back(Op);
4365 }
4366
4367 return DAG.getBuildVector(NOutVT, dl, Ops);
4368}
4369
4370SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
4371
4372 SDLoc dl(N);
4373
4374 assert(!N->getOperand(0).getValueType().isVector() &&((!N->getOperand(0).getValueType().isVector() && "Input must be a scalar"
) ? static_cast<void> (0) : __assert_fail ("!N->getOperand(0).getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4375, __PRETTY_FUNCTION__))
4375 "Input must be a scalar")((!N->getOperand(0).getValueType().isVector() && "Input must be a scalar"
) ? static_cast<void> (0) : __assert_fail ("!N->getOperand(0).getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4375, __PRETTY_FUNCTION__))
;
4376
4377 EVT OutVT = N->getValueType(0);
4378 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4379 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4379, __PRETTY_FUNCTION__))
;
4380 EVT NOutVTElem = NOutVT.getVectorElementType();
4381
4382 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
4383
4384 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
4385}
4386
4387SDValue DAGTypeLegalizer::PromoteIntRes_SPLAT_VECTOR(SDNode *N) {
4388 SDLoc dl(N);
4389
4390 SDValue SplatVal = N->getOperand(0);
4391
4392 assert(!SplatVal.getValueType().isVector() && "Input must be a scalar")((!SplatVal.getValueType().isVector() && "Input must be a scalar"
) ? static_cast<void> (0) : __assert_fail ("!SplatVal.getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4392, __PRETTY_FUNCTION__))
;
4393
4394 EVT OutVT = N->getValueType(0);
4395 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4396 assert(NOutVT.isVector() && "Type must be promoted to a vector type")((NOutVT.isVector() && "Type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"Type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4396, __PRETTY_FUNCTION__))
;
4397 EVT NOutElemVT = NOutVT.getVectorElementType();
4398
4399 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutElemVT, SplatVal);
4400
4401 return DAG.getNode(ISD::SPLAT_VECTOR, dl, NOutVT, Op);
4402}
4403
4404SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
4405 SDLoc dl(N);
4406
4407 EVT OutVT = N->getValueType(0);
4408 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4409 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4409, __PRETTY_FUNCTION__))
;
4410
4411 EVT OutElemTy = NOutVT.getVectorElementType();
4412
4413 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
4414 unsigned NumOutElem = NOutVT.getVectorNumElements();
4415 unsigned NumOperands = N->getNumOperands();
4416 assert(NumElem * NumOperands == NumOutElem &&((NumElem * NumOperands == NumOutElem && "Unexpected number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElem * NumOperands == NumOutElem && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4417, __PRETTY_FUNCTION__))
4417 "Unexpected number of elements")((NumElem * NumOperands == NumOutElem && "Unexpected number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElem * NumOperands == NumOutElem && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4417, __PRETTY_FUNCTION__))
;
4418
4419 // Take the elements from the first vector.
4420 SmallVector<SDValue, 8> Ops(NumOutElem);
4421 for (unsigned i = 0; i < NumOperands; ++i) {
4422 SDValue Op = N->getOperand(i);
4423 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger)
4424 Op = GetPromotedInteger(Op);
4425 EVT SclrTy = Op.getValueType().getVectorElementType();
4426 assert(NumElem == Op.getValueType().getVectorNumElements() &&((NumElem == Op.getValueType().getVectorNumElements() &&
"Unexpected number of elements") ? static_cast<void> (
0) : __assert_fail ("NumElem == Op.getValueType().getVectorNumElements() && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4427, __PRETTY_FUNCTION__))
4427 "Unexpected number of elements")((NumElem == Op.getValueType().getVectorNumElements() &&
"Unexpected number of elements") ? static_cast<void> (
0) : __assert_fail ("NumElem == Op.getValueType().getVectorNumElements() && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4427, __PRETTY_FUNCTION__))
;
4428
4429 for (unsigned j = 0; j < NumElem; ++j) {
4430 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op,
4431 DAG.getVectorIdxConstant(j, dl));
4432 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Ext, dl, OutElemTy);
4433 }
4434 }
4435
4436 return DAG.getBuildVector(NOutVT, dl, Ops);
4437}
4438
4439SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
4440 EVT VT = N->getValueType(0);
4441 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4442 assert(NVT.isVector() && "This type must be promoted to a vector type")((NVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4442, __PRETTY_FUNCTION__))
;
4443
4444 SDLoc dl(N);
4445
4446 // For operands whose TypeAction is to promote, extend the promoted node
4447 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
4448 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
4449 // type..
4450 if (getTypeAction(N->getOperand(0).getValueType())
4451 == TargetLowering::TypePromoteInteger) {
4452 SDValue Promoted;
4453
4454 switch(N->getOpcode()) {
4455 case ISD::SIGN_EXTEND_VECTOR_INREG:
4456 Promoted = SExtPromotedInteger(N->getOperand(0));
4457 break;
4458 case ISD::ZERO_EXTEND_VECTOR_INREG:
4459 Promoted = ZExtPromotedInteger(N->getOperand(0));
4460 break;
4461 case ISD::ANY_EXTEND_VECTOR_INREG:
4462 Promoted = GetPromotedInteger(N->getOperand(0));
4463 break;
4464 default:
4465 llvm_unreachable("Node has unexpected Opcode")::llvm::llvm_unreachable_internal("Node has unexpected Opcode"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4465)
;
4466 }
4467 return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
4468 }
4469
4470 // Directly extend to the appropriate transform-to type.
4471 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
4472}
4473
4474SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
4475 EVT OutVT = N->getValueType(0);
4476 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4477 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4477, __PRETTY_FUNCTION__))
;
4478
4479 EVT NOutVTElem = NOutVT.getVectorElementType();
4480
4481 SDLoc dl(N);
4482 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4483
4484 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
4485 NOutVTElem, N->getOperand(1));
4486 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
4487 V0, ConvElem, N->getOperand(2));
4488}
4489
4490SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
4491 // The VECREDUCE result size may be larger than the element size, so
4492 // we can simply change the result type.
4493 SDLoc dl(N);
4494 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4495 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
4496}
4497
4498SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
4499 SDLoc dl(N);
4500 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4501 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
4502 TLI.getVectorIdxTy(DAG.getDataLayout()));
4503 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4504 V0->getValueType(0).getScalarType(), V0, V1);
4505
4506 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
4507 // element types. If this is the case then we need to expand the outgoing
4508 // value and not truncate it.
4509 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
4510}
4511
4512SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
4513 SDLoc dl(N);
4514 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4515 MVT InVT = V0.getValueType().getSimpleVT();
4516 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
4517 N->getValueType(0).getVectorNumElements());
4518 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
4519 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
4520}
4521
4522SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
4523 SDLoc dl(N);
4524 unsigned NumElems = N->getNumOperands();
4525
4526 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
4527
4528 SmallVector<SDValue, 8> NewOps;
4529 NewOps.reserve(NumElems);
4530
4531 // For each incoming vector
4532 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
4533 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
4534 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
4535 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
4536
4537 for (unsigned i=0; i<NumElem; ++i) {
4538 // Extract element from incoming vector
4539 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
4540 DAG.getVectorIdxConstant(i, dl));
4541 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
4542 NewOps.push_back(Tr);
4543 }
4544 }
4545
4546 return DAG.getBuildVector(N->getValueType(0), dl, NewOps);
4547}

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/Constants.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Instruction.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/Metadata.h"
39#include "llvm/IR/Operator.h"
40#include "llvm/Support/AlignOf.h"
41#include "llvm/Support/AtomicOrdering.h"
42#include "llvm/Support/Casting.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MachineValueType.h"
45#include "llvm/Support/TypeSize.h"
46#include <algorithm>
47#include <cassert>
48#include <climits>
49#include <cstddef>
50#include <cstdint>
51#include <cstring>
52#include <iterator>
53#include <string>
54#include <tuple>
55
56namespace llvm {
57
58class APInt;
59class Constant;
60template <typename T> struct DenseMapInfo;
61class GlobalValue;
62class MachineBasicBlock;
63class MachineConstantPoolValue;
64class MCSymbol;
65class raw_ostream;
66class SDNode;
67class SelectionDAG;
68class Type;
69class Value;
70
71void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
72 bool force = false);
73
74/// This represents a list of ValueType's that has been intern'd by
75/// a SelectionDAG. Instances of this simple value class are returned by
76/// SelectionDAG::getVTList(...).
77///
78struct SDVTList {
79 const EVT *VTs;
80 unsigned int NumVTs;
81};
82
83namespace ISD {
84
85 /// Node predicates
86
87 /// If N is a BUILD_VECTOR node whose elements are all the same constant or
88 /// undefined, return true and return the constant value in \p SplatValue.
89 bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
90
91 /// Return true if the specified node is a BUILD_VECTOR where all of the
92 /// elements are ~0 or undef.
93 bool isBuildVectorAllOnes(const SDNode *N);
94
95 /// Return true if the specified node is a BUILD_VECTOR where all of the
96 /// elements are 0 or undef.
97 bool isBuildVectorAllZeros(const SDNode *N);
98
99 /// Return true if the specified node is a BUILD_VECTOR node of all
100 /// ConstantSDNode or undef.
101 bool isBuildVectorOfConstantSDNodes(const SDNode *N);
102
103 /// Return true if the specified node is a BUILD_VECTOR node of all
104 /// ConstantFPSDNode or undef.
105 bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
106
107 /// Return true if the node has at least one operand and all operands of the
108 /// specified node are ISD::UNDEF.
109 bool allOperandsUndef(const SDNode *N);
110
111} // end namespace ISD
112
113//===----------------------------------------------------------------------===//
114/// Unlike LLVM values, Selection DAG nodes may return multiple
115/// values as the result of a computation. Many nodes return multiple values,
116/// from loads (which define a token and a return value) to ADDC (which returns
117/// a result and a carry value), to calls (which may return an arbitrary number
118/// of values).
119///
120/// As such, each use of a SelectionDAG computation must indicate the node that
121/// computes it as well as which return value to use from that node. This pair
122/// of information is represented with the SDValue value type.
123///
124class SDValue {
125 friend struct DenseMapInfo<SDValue>;
126
127 SDNode *Node = nullptr; // The node defining the value we are using.
128 unsigned ResNo = 0; // Which return value of the node we are using.
129
130public:
131 SDValue() = default;
132 SDValue(SDNode *node, unsigned resno);
133
134 /// get the index which selects a specific result in the SDNode
135 unsigned getResNo() const { return ResNo; }
136
137 /// get the SDNode which holds the desired result
138 SDNode *getNode() const { return Node; }
139
140 /// set the SDNode
141 void setNode(SDNode *N) { Node = N; }
142
143 inline SDNode *operator->() const { return Node; }
144
145 bool operator==(const SDValue &O) const {
146 return Node == O.Node && ResNo == O.ResNo;
147 }
148 bool operator!=(const SDValue &O) const {
149 return !operator==(O);
150 }
151 bool operator<(const SDValue &O) const {
152 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
153 }
154 explicit operator bool() const {
155 return Node != nullptr;
156 }
157
158 SDValue getValue(unsigned R) const {
159 return SDValue(Node, R);
160 }
161
162 /// Return true if this node is an operand of N.
163 bool isOperandOf(const SDNode *N) const;
164
165 /// Return the ValueType of the referenced return value.
166 inline EVT getValueType() const;
167
168 /// Return the simple ValueType of the referenced return value.
169 MVT getSimpleValueType() const {
170 return getValueType().getSimpleVT();
171 }
172
173 /// Returns the size of the value in bits.
174 ///
175 /// If the value type is a scalable vector type, the scalable property will
176 /// be set and the runtime size will be a positive integer multiple of the
177 /// base size.
178 TypeSize getValueSizeInBits() const {
179 return getValueType().getSizeInBits();
180 }
181
182 TypeSize getScalarValueSizeInBits() const {
183 return getValueType().getScalarType().getSizeInBits();
184 }
185
186 // Forwarding methods - These forward to the corresponding methods in SDNode.
187 inline unsigned getOpcode() const;
188 inline unsigned getNumOperands() const;
189 inline const SDValue &getOperand(unsigned i) const;
190 inline uint64_t getConstantOperandVal(unsigned i) const;
191 inline const APInt &getConstantOperandAPInt(unsigned i) const;
192 inline bool isTargetMemoryOpcode() const;
193 inline bool isTargetOpcode() const;
194 inline bool isMachineOpcode() const;
195 inline bool isUndef() const;
196 inline unsigned getMachineOpcode() const;
197 inline const DebugLoc &getDebugLoc() const;
198 inline void dump() const;
199 inline void dump(const SelectionDAG *G) const;
200 inline void dumpr() const;
201 inline void dumpr(const SelectionDAG *G) const;
202
203 /// Return true if this operand (which must be a chain) reaches the
204 /// specified operand without crossing any side-effecting instructions.
205 /// In practice, this looks through token factors and non-volatile loads.
206 /// In order to remain efficient, this only
207 /// looks a couple of nodes in, it does not do an exhaustive search.
208 bool reachesChainWithoutSideEffects(SDValue Dest,
209 unsigned Depth = 2) const;
210
211 /// Return true if there are no nodes using value ResNo of Node.
212 inline bool use_empty() const;
213
214 /// Return true if there is exactly one node using value ResNo of Node.
215 inline bool hasOneUse() const;
216};
217
218template<> struct DenseMapInfo<SDValue> {
219 static inline SDValue getEmptyKey() {
220 SDValue V;
221 V.ResNo = -1U;
222 return V;
223 }
224
225 static inline SDValue getTombstoneKey() {
226 SDValue V;
227 V.ResNo = -2U;
228 return V;
229 }
230
231 static unsigned getHashValue(const SDValue &Val) {
232 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
233 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
234 }
235
236 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
237 return LHS == RHS;
238 }
239};
240
241/// Allow casting operators to work directly on
242/// SDValues as if they were SDNode*'s.
243template<> struct simplify_type<SDValue> {
244 using SimpleType = SDNode *;
245
246 static SimpleType getSimplifiedValue(SDValue &Val) {
247 return Val.getNode();
248 }
249};
250template<> struct simplify_type<const SDValue> {
251 using SimpleType = /*const*/ SDNode *;
252
253 static SimpleType getSimplifiedValue(const SDValue &Val) {
254 return Val.getNode();
255 }
256};
257
258/// Represents a use of a SDNode. This class holds an SDValue,
259/// which records the SDNode being used and the result number, a
260/// pointer to the SDNode using the value, and Next and Prev pointers,
261/// which link together all the uses of an SDNode.
262///
263class SDUse {
264 /// Val - The value being used.
265 SDValue Val;
266 /// User - The user of this value.
267 SDNode *User = nullptr;
268 /// Prev, Next - Pointers to the uses list of the SDNode referred by
269 /// this operand.
270 SDUse **Prev = nullptr;
271 SDUse *Next = nullptr;
272
273public:
274 SDUse() = default;
275 SDUse(const SDUse &U) = delete;
276 SDUse &operator=(const SDUse &) = delete;
277
278 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
279 operator const SDValue&() const { return Val; }
280
281 /// If implicit conversion to SDValue doesn't work, the get() method returns
282 /// the SDValue.
283 const SDValue &get() const { return Val; }
284
285 /// This returns the SDNode that contains this Use.
286 SDNode *getUser() { return User; }
287
288 /// Get the next SDUse in the use list.
289 SDUse *getNext() const { return Next; }
290
291 /// Convenience function for get().getNode().
292 SDNode *getNode() const { return Val.getNode(); }
293 /// Convenience function for get().getResNo().
294 unsigned getResNo() const { return Val.getResNo(); }
295 /// Convenience function for get().getValueType().
296 EVT getValueType() const { return Val.getValueType(); }
297
298 /// Convenience function for get().operator==
299 bool operator==(const SDValue &V) const {
300 return Val == V;
301 }
302
303 /// Convenience function for get().operator!=
304 bool operator!=(const SDValue &V) const {
305 return Val != V;
306 }
307
308 /// Convenience function for get().operator<
309 bool operator<(const SDValue &V) const {
310 return Val < V;
311 }
312
313private:
314 friend class SelectionDAG;
315 friend class SDNode;
316 // TODO: unfriend HandleSDNode once we fix its operand handling.
317 friend class HandleSDNode;
318
319 void setUser(SDNode *p) { User = p; }
320
321 /// Remove this use from its existing use list, assign it the
322 /// given value, and add it to the new value's node's use list.
323 inline void set(const SDValue &V);
324 /// Like set, but only supports initializing a newly-allocated
325 /// SDUse with a non-null value.
326 inline void setInitial(const SDValue &V);
327 /// Like set, but only sets the Node portion of the value,
328 /// leaving the ResNo portion unmodified.
329 inline void setNode(SDNode *N);
330
331 void addToList(SDUse **List) {
332 Next = *List;
333 if (Next) Next->Prev = &Next;
334 Prev = List;
335 *List = this;
336 }
337
338 void removeFromList() {
339 *Prev = Next;
340 if (Next) Next->Prev = Prev;
341 }
342};
343
344/// simplify_type specializations - Allow casting operators to work directly on
345/// SDValues as if they were SDNode*'s.
346template<> struct simplify_type<SDUse> {
347 using SimpleType = SDNode *;
348
349 static SimpleType getSimplifiedValue(SDUse &Val) {
350 return Val.getNode();
351 }
352};
353
354/// These are IR-level optimization flags that may be propagated to SDNodes.
355/// TODO: This data structure should be shared by the IR optimizer and the
356/// the backend.
357struct SDNodeFlags {
358private:
359 // This bit is used to determine if the flags are in a defined state.
360 // Flag bits can only be masked out during intersection if the masking flags
361 // are defined.
362 bool AnyDefined : 1;
363
364 bool NoUnsignedWrap : 1;
365 bool NoSignedWrap : 1;
366 bool Exact : 1;
367 bool NoNaNs : 1;
368 bool NoInfs : 1;
369 bool NoSignedZeros : 1;
370 bool AllowReciprocal : 1;
371 bool VectorReduction : 1;
372 bool AllowContract : 1;
373 bool ApproximateFuncs : 1;
374 bool AllowReassociation : 1;
375
376 // We assume instructions do not raise floating-point exceptions by default,
377 // and only those marked explicitly may do so. We could choose to represent
378 // this via a positive "FPExcept" flags like on the MI level, but having a
379 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
380 // intersection logic more straightforward.
381 bool NoFPExcept : 1;
382
383public:
384 /// Default constructor turns off all optimization flags.
385 SDNodeFlags()
386 : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
387 Exact(false), NoNaNs(false), NoInfs(false),
388 NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
389 AllowContract(false), ApproximateFuncs(false),
390 AllowReassociation(false), NoFPExcept(false) {}
391
392 /// Propagate the fast-math-flags from an IR FPMathOperator.
393 void copyFMF(const FPMathOperator &FPMO) {
394 setNoNaNs(FPMO.hasNoNaNs());
395 setNoInfs(FPMO.hasNoInfs());
396 setNoSignedZeros(FPMO.hasNoSignedZeros());
397 setAllowReciprocal(FPMO.hasAllowReciprocal());
398 setAllowContract(FPMO.hasAllowContract());
399 setApproximateFuncs(FPMO.hasApproxFunc());
400 setAllowReassociation(FPMO.hasAllowReassoc());
401 }
402
403 /// Sets the state of the flags to the defined state.
404 void setDefined() { AnyDefined = true; }
405 /// Returns true if the flags are in a defined state.
406 bool isDefined() const { return AnyDefined; }
407
408 // These are mutators for each flag.
409 void setNoUnsignedWrap(bool b) {
410 setDefined();
411 NoUnsignedWrap = b;
412 }
413 void setNoSignedWrap(bool b) {
414 setDefined();
415 NoSignedWrap = b;
416 }
417 void setExact(bool b) {
418 setDefined();
419 Exact = b;
420 }
421 void setNoNaNs(bool b) {
422 setDefined();
423 NoNaNs = b;
424 }
425 void setNoInfs(bool b) {
426 setDefined();
427 NoInfs = b;
428 }
429 void setNoSignedZeros(bool b) {
430 setDefined();
431 NoSignedZeros = b;
432 }
433 void setAllowReciprocal(bool b) {
434 setDefined();
435 AllowReciprocal = b;
436 }
437 void setVectorReduction(bool b) {
438 setDefined();
439 VectorReduction = b;
440 }
441 void setAllowContract(bool b) {
442 setDefined();
443 AllowContract = b;
444 }
445 void setApproximateFuncs(bool b) {
446 setDefined();
447 ApproximateFuncs = b;
448 }
449 void setAllowReassociation(bool b) {
450 setDefined();
451 AllowReassociation = b;
452 }
453 void setNoFPExcept(bool b) {
454 setDefined();
455 NoFPExcept = b;
456 }
457
458 // These are accessors for each flag.
459 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
460 bool hasNoSignedWrap() const { return NoSignedWrap; }
461 bool hasExact() const { return Exact; }
462 bool hasNoNaNs() const { return NoNaNs; }
463 bool hasNoInfs() const { return NoInfs; }
464 bool hasNoSignedZeros() const { return NoSignedZeros; }
465 bool hasAllowReciprocal() const { return AllowReciprocal; }
466 bool hasVectorReduction() const { return VectorReduction; }
467 bool hasAllowContract() const { return AllowContract; }
468 bool hasApproximateFuncs() const { return ApproximateFuncs; }
469 bool hasAllowReassociation() const { return AllowReassociation; }
470 bool hasNoFPExcept() const { return NoFPExcept; }
471
472 /// Clear any flags in this flag set that aren't also set in Flags.
473 /// If the given Flags are undefined then don't do anything.
474 void intersectWith(const SDNodeFlags Flags) {
475 if (!Flags.isDefined())
476 return;
477 NoUnsignedWrap &= Flags.NoUnsignedWrap;
478 NoSignedWrap &= Flags.NoSignedWrap;
479 Exact &= Flags.Exact;
480 NoNaNs &= Flags.NoNaNs;
481 NoInfs &= Flags.NoInfs;
482 NoSignedZeros &= Flags.NoSignedZeros;
483 AllowReciprocal &= Flags.AllowReciprocal;
484 VectorReduction &= Flags.VectorReduction;
485 AllowContract &= Flags.AllowContract;
486 ApproximateFuncs &= Flags.ApproximateFuncs;
487 AllowReassociation &= Flags.AllowReassociation;
488 NoFPExcept &= Flags.NoFPExcept;
489 }
490};
491
492/// Represents one node in the SelectionDAG.
493///
494class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
495private:
496 /// The operation that this node performs.
497 int16_t NodeType;
498
499protected:
500 // We define a set of mini-helper classes to help us interpret the bits in our
501 // SubclassData. These are designed to fit within a uint16_t so they pack
502 // with NodeType.
503
504#if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__))
505// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
506// and give the `pack` pragma push semantics.
507#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
508#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
509#else
510#define BEGIN_TWO_BYTE_PACK()
511#define END_TWO_BYTE_PACK()
512#endif
513
514BEGIN_TWO_BYTE_PACK()
515 class SDNodeBitfields {
516 friend class SDNode;
517 friend class MemIntrinsicSDNode;
518 friend class MemSDNode;
519 friend class SelectionDAG;
520
521 uint16_t HasDebugValue : 1;
522 uint16_t IsMemIntrinsic : 1;
523 uint16_t IsDivergent : 1;
524 };
525 enum { NumSDNodeBits = 3 };
526
527 class ConstantSDNodeBitfields {
528 friend class ConstantSDNode;
529
530 uint16_t : NumSDNodeBits;
531
532 uint16_t IsOpaque : 1;
533 };
534
535 class MemSDNodeBitfields {
536 friend class MemSDNode;
537 friend class MemIntrinsicSDNode;
538 friend class AtomicSDNode;
539
540 uint16_t : NumSDNodeBits;
541
542 uint16_t IsVolatile : 1;
543 uint16_t IsNonTemporal : 1;
544 uint16_t IsDereferenceable : 1;
545 uint16_t IsInvariant : 1;
546 };
547 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
548
549 class LSBaseSDNodeBitfields {
550 friend class LSBaseSDNode;
551 friend class MaskedLoadStoreSDNode;
552 friend class MaskedGatherScatterSDNode;
553
554 uint16_t : NumMemSDNodeBits;
555
556 // This storage is shared between disparate class hierarchies to hold an
557 // enumeration specific to the class hierarchy in use.
558 // LSBaseSDNode => enum ISD::MemIndexedMode
559 // MaskedLoadStoreBaseSDNode => enum ISD::MemIndexedMode
560 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
561 uint16_t AddressingMode : 3;
562 };
563 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
564
565 class LoadSDNodeBitfields {
566 friend class LoadSDNode;
567 friend class MaskedLoadSDNode;
568
569 uint16_t : NumLSBaseSDNodeBits;
570
571 uint16_t ExtTy : 2; // enum ISD::LoadExtType
572 uint16_t IsExpanding : 1;
573 };
574
575 class StoreSDNodeBitfields {
576 friend class StoreSDNode;
577 friend class MaskedStoreSDNode;
578
579 uint16_t : NumLSBaseSDNodeBits;
580
581 uint16_t IsTruncating : 1;
582 uint16_t IsCompressing : 1;
583 };
584
585 union {
586 char RawSDNodeBits[sizeof(uint16_t)];
587 SDNodeBitfields SDNodeBits;
588 ConstantSDNodeBitfields ConstantSDNodeBits;
589 MemSDNodeBitfields MemSDNodeBits;
590 LSBaseSDNodeBitfields LSBaseSDNodeBits;
591 LoadSDNodeBitfields LoadSDNodeBits;
592 StoreSDNodeBitfields StoreSDNodeBits;
593 };
594END_TWO_BYTE_PACK()
595#undef BEGIN_TWO_BYTE_PACK
596#undef END_TWO_BYTE_PACK
597
598 // RawSDNodeBits must cover the entirety of the union. This means that all of
599 // the union's members must have size <= RawSDNodeBits. We write the RHS as
600 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
601 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
602 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
603 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
604 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
605 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
606 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
607
608private:
609 friend class SelectionDAG;
610 // TODO: unfriend HandleSDNode once we fix its operand handling.
611 friend class HandleSDNode;
612
613 /// Unique id per SDNode in the DAG.
614 int NodeId = -1;
615
616 /// The values that are used by this operation.
617 SDUse *OperandList = nullptr;
618
619 /// The types of the values this node defines. SDNode's may
620 /// define multiple values simultaneously.
621 const EVT *ValueList;
622
623 /// List of uses for this SDNode.
624 SDUse *UseList = nullptr;
625
626 /// The number of entries in the Operand/Value list.
627 unsigned short NumOperands = 0;
628 unsigned short NumValues;
629
630 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
631 // original LLVM instructions.
632 // This is used for turning off scheduling, because we'll forgo
633 // the normal scheduling algorithms and output the instructions according to
634 // this ordering.
635 unsigned IROrder;
636
637 /// Source line information.
638 DebugLoc debugLoc;
639
640 /// Return a pointer to the specified value type.
641 static const EVT *getValueTypeList(EVT VT);
642
643 SDNodeFlags Flags;
644
645public:
646 /// Unique and persistent id per SDNode in the DAG.
647 /// Used for debug printing.
648 uint16_t PersistentId;
649
650 //===--------------------------------------------------------------------===//
651 // Accessors
652 //
653
654 /// Return the SelectionDAG opcode value for this node. For
655 /// pre-isel nodes (those for which isMachineOpcode returns false), these
656 /// are the opcode values in the ISD and <target>ISD namespaces. For
657 /// post-isel opcodes, see getMachineOpcode.
658 unsigned getOpcode() const { return (unsigned short)NodeType; }
659
660 /// Test if this node has a target-specific opcode (in the
661 /// \<target\>ISD namespace).
662 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
663
664 /// Test if this node has a target-specific opcode that may raise
665 /// FP exceptions (in the \<target\>ISD namespace and greater than
666 /// FIRST_TARGET_STRICTFP_OPCODE). Note that all target memory
667 /// opcode are currently automatically considered to possibly raise
668 /// FP exceptions as well.
669 bool isTargetStrictFPOpcode() const {
670 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
671 }
672
673 /// Test if this node has a target-specific
674 /// memory-referencing opcode (in the \<target\>ISD namespace and
675 /// greater than FIRST_TARGET_MEMORY_OPCODE).
676 bool isTargetMemoryOpcode() const {
677 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
678 }
679
680 /// Return true if the type of the node type undefined.
681 bool isUndef() const { return NodeType == ISD::UNDEF; }
682
683 /// Test if this node is a memory intrinsic (with valid pointer information).
684 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
685 /// non-memory intrinsics (with chains) that are not really instances of
686 /// MemSDNode. For such nodes, we need some extra state to determine the
687 /// proper classof relationship.
688 bool isMemIntrinsic() const {
689 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
690 NodeType == ISD::INTRINSIC_VOID) &&
691 SDNodeBits.IsMemIntrinsic;
692 }
693
694 /// Test if this node is a strict floating point pseudo-op.
695 bool isStrictFPOpcode() {
696 switch (NodeType) {
697 default:
698 return false;
699 case ISD::STRICT_FP16_TO_FP:
700 case ISD::STRICT_FP_TO_FP16:
701#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
702 case ISD::STRICT_##DAGN:
703#include "llvm/IR/ConstrainedOps.def"
704 return true;
705 }
706 }
707
708 /// Test if this node has a post-isel opcode, directly
709 /// corresponding to a MachineInstr opcode.
710 bool isMachineOpcode() const { return NodeType < 0; }
711
712 /// This may only be called if isMachineOpcode returns
713 /// true. It returns the MachineInstr opcode value that the node's opcode
714 /// corresponds to.
715 unsigned getMachineOpcode() const {
716 assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 716, __PRETTY_FUNCTION__))
;
717 return ~NodeType;
718 }
719
720 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
721 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
722
723 bool isDivergent() const { return SDNodeBits.IsDivergent; }
724
725 /// Return true if there are no uses of this node.
726 bool use_empty() const { return UseList == nullptr; }
727
728 /// Return true if there is exactly one use of this node.
729 bool hasOneUse() const {
730 return !use_empty() && std::next(use_begin()) == use_end();
731 }
732
733 /// Return the number of uses of this node. This method takes
734 /// time proportional to the number of uses.
735 size_t use_size() const { return std::distance(use_begin(), use_end()); }
736
737 /// Return the unique node id.
738 int getNodeId() const { return NodeId; }
739
740 /// Set unique node id.
741 void setNodeId(int Id) { NodeId = Id; }
742
743 /// Return the node ordering.
744 unsigned getIROrder() const { return IROrder; }
745
746 /// Set the node ordering.
747 void setIROrder(unsigned Order) { IROrder = Order; }
748
749 /// Return the source location info.
750 const DebugLoc &getDebugLoc() const { return debugLoc; }
751
752 /// Set source location info. Try to avoid this, putting
753 /// it in the constructor is preferable.
754 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
755
756 /// This class provides iterator support for SDUse
757 /// operands that use a specific SDNode.
758 class use_iterator
759 : public std::iterator<std::forward_iterator_tag, SDUse, ptrdiff_t> {
760 friend class SDNode;
761
762 SDUse *Op = nullptr;
763
764 explicit use_iterator(SDUse *op) : Op(op) {}
765
766 public:
767 using reference = std::iterator<std::forward_iterator_tag,
768 SDUse, ptrdiff_t>::reference;
769 using pointer = std::iterator<std::forward_iterator_tag,
770 SDUse, ptrdiff_t>::pointer;
771
772 use_iterator() = default;
773 use_iterator(const use_iterator &I) : Op(I.Op) {}
774
775 bool operator==(const use_iterator &x) const {
776 return Op == x.Op;
777 }
778 bool operator!=(const use_iterator &x) const {
779 return !operator==(x);
780 }
781
782 /// Return true if this iterator is at the end of uses list.
783 bool atEnd() const { return Op == nullptr; }
784
785 // Iterator traversal: forward iteration only.
786 use_iterator &operator++() { // Preincrement
787 assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 787, __PRETTY_FUNCTION__))
;
788 Op = Op->getNext();
789 return *this;
790 }
791
792 use_iterator operator++(int) { // Postincrement
793 use_iterator tmp = *this; ++*this; return tmp;
794 }
795
796 /// Retrieve a pointer to the current user node.
797 SDNode *operator*() const {
798 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 798, __PRETTY_FUNCTION__))
;
799 return Op->getUser();
800 }
801
802 SDNode *operator->() const { return operator*(); }
803
804 SDUse &getUse() const { return *Op; }
805
806 /// Retrieve the operand # of this use in its user.
807 unsigned getOperandNo() const {
808 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 808, __PRETTY_FUNCTION__))
;
809 return (unsigned)(Op - Op->getUser()->OperandList);
810 }
811 };
812
813 /// Provide iteration support to walk over all uses of an SDNode.
814 use_iterator use_begin() const {
815 return use_iterator(UseList);
816 }
817
818 static use_iterator use_end() { return use_iterator(nullptr); }
819
820 inline iterator_range<use_iterator> uses() {
821 return make_range(use_begin(), use_end());
822 }
823 inline iterator_range<use_iterator> uses() const {
824 return make_range(use_begin(), use_end());
825 }
826
827 /// Return true if there are exactly NUSES uses of the indicated value.
828 /// This method ignores uses of other values defined by this operation.
829 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
830
831 /// Return true if there are any use of the indicated value.
832 /// This method ignores uses of other values defined by this operation.
833 bool hasAnyUseOfValue(unsigned Value) const;
834
835 /// Return true if this node is the only use of N.
836 bool isOnlyUserOf(const SDNode *N) const;
837
838 /// Return true if this node is an operand of N.
839 bool isOperandOf(const SDNode *N) const;
840
841 /// Return true if this node is a predecessor of N.
842 /// NOTE: Implemented on top of hasPredecessor and every bit as
843 /// expensive. Use carefully.
844 bool isPredecessorOf(const SDNode *N) const {
845 return N->hasPredecessor(this);
846 }
847
848 /// Return true if N is a predecessor of this node.
849 /// N is either an operand of this node, or can be reached by recursively
850 /// traversing up the operands.
851 /// NOTE: This is an expensive method. Use it carefully.
852 bool hasPredecessor(const SDNode *N) const;
853
854 /// Returns true if N is a predecessor of any node in Worklist. This
855 /// helper keeps Visited and Worklist sets externally to allow unions
856 /// searches to be performed in parallel, caching of results across
857 /// queries and incremental addition to Worklist. Stops early if N is
858 /// found but will resume. Remember to clear Visited and Worklists
859 /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
860 /// giving up. The TopologicalPrune flag signals that positive NodeIds are
861 /// topologically ordered (Operands have strictly smaller node id) and search
862 /// can be pruned leveraging this.
863 static bool hasPredecessorHelper(const SDNode *N,
864 SmallPtrSetImpl<const SDNode *> &Visited,
865 SmallVectorImpl<const SDNode *> &Worklist,
866 unsigned int MaxSteps = 0,
867 bool TopologicalPrune = false) {
868 SmallVector<const SDNode *, 8> DeferredNodes;
869 if (Visited.count(N))
870 return true;
871
872 // Node Id's are assigned in three places: As a topological
873 // ordering (> 0), during legalization (results in values set to
874 // 0), new nodes (set to -1). If N has a topolgical id then we
875 // know that all nodes with ids smaller than it cannot be
876 // successors and we need not check them. Filter out all node
877 // that can't be matches. We add them to the worklist before exit
878 // in case of multiple calls. Note that during selection the topological id
879 // may be violated if a node's predecessor is selected before it. We mark
880 // this at selection negating the id of unselected successors and
881 // restricting topological pruning to positive ids.
882
883 int NId = N->getNodeId();
884 // If we Invalidated the Id, reconstruct original NId.
885 if (NId < -1)
886 NId = -(NId + 1);
887
888 bool Found = false;
889 while (!Worklist.empty()) {
890 const SDNode *M = Worklist.pop_back_val();
891 int MId = M->getNodeId();
892 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
893 (MId > 0) && (MId < NId)) {
894 DeferredNodes.push_back(M);
895 continue;
896 }
897 for (const SDValue &OpV : M->op_values()) {
898 SDNode *Op = OpV.getNode();
899 if (Visited.insert(Op).second)
900 Worklist.push_back(Op);
901 if (Op == N)
902 Found = true;
903 }
904 if (Found)
905 break;
906 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
907 break;
908 }
909 // Push deferred nodes back on worklist.
910 Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
911 // If we bailed early, conservatively return found.
912 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
913 return true;
914 return Found;
915 }
916
917 /// Return true if all the users of N are contained in Nodes.
918 /// NOTE: Requires at least one match, but doesn't require them all.
919 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
920
921 /// Return the number of values used by this operation.
922 unsigned getNumOperands() const { return NumOperands; }
923
924 /// Return the maximum number of operands that a SDNode can hold.
925 static constexpr size_t getMaxNumOperands() {
926 return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
927 }
928
929 /// Helper method returns the integer value of a ConstantSDNode operand.
930 inline uint64_t getConstantOperandVal(unsigned Num) const;
931
932 /// Helper method returns the APInt of a ConstantSDNode operand.
933 inline const APInt &getConstantOperandAPInt(unsigned Num) const;
934
935 const SDValue &getOperand(unsigned Num) const {
936 assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 936, __PRETTY_FUNCTION__))
;
937 return OperandList[Num];
938 }
939
940 using op_iterator = SDUse *;
941
942 op_iterator op_begin() const { return OperandList; }
943 op_iterator op_end() const { return OperandList+NumOperands; }
944 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
945
946 /// Iterator for directly iterating over the operand SDValue's.
947 struct value_op_iterator
948 : iterator_adaptor_base<value_op_iterator, op_iterator,
949 std::random_access_iterator_tag, SDValue,
950 ptrdiff_t, value_op_iterator *,
951 value_op_iterator *> {
952 explicit value_op_iterator(SDUse *U = nullptr)
953 : iterator_adaptor_base(U) {}
954
955 const SDValue &operator*() const { return I->get(); }
956 };
957
958 iterator_range<value_op_iterator> op_values() const {
959 return make_range(value_op_iterator(op_begin()),
960 value_op_iterator(op_end()));
961 }
962
963 SDVTList getVTList() const {
964 SDVTList X = { ValueList, NumValues };
965 return X;
966 }
967
968 /// If this node has a glue operand, return the node
969 /// to which the glue operand points. Otherwise return NULL.
970 SDNode *getGluedNode() const {
971 if (getNumOperands() != 0 &&
972 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
973 return getOperand(getNumOperands()-1).getNode();
974 return nullptr;
975 }
976
977 /// If this node has a glue value with a user, return
978 /// the user (there is at most one). Otherwise return NULL.
979 SDNode *getGluedUser() const {
980 for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
981 if (UI.getUse().get().getValueType() == MVT::Glue)
982 return *UI;
983 return nullptr;
984 }
985
986 const SDNodeFlags getFlags() const { return Flags; }
987 void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
988
989 /// Clear any flags in this node that aren't also set in Flags.
990 /// If Flags is not in a defined state then this has no effect.
991 void intersectFlagsWith(const SDNodeFlags Flags);
992
993 /// Return the number of values defined/returned by this operator.
994 unsigned getNumValues() const { return NumValues; }
995
996 /// Return the type of a specified result.
997 EVT getValueType(unsigned ResNo) const {
998 assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ?
static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 998, __PRETTY_FUNCTION__))
;
999 return ValueList[ResNo];
1000 }
1001
1002 /// Return the type of a specified result as a simple type.
1003 MVT getSimpleValueType(unsigned ResNo) const {
1004 return getValueType(ResNo).getSimpleVT();
1005 }
1006
1007 /// Returns MVT::getSizeInBits(getValueType(ResNo)).
1008 ///
1009 /// If the value type is a scalable vector type, the scalable property will
1010 /// be set and the runtime size will be a positive integer multiple of the
1011 /// base size.
1012 TypeSize getValueSizeInBits(unsigned ResNo) const {
1013 return getValueType(ResNo).getSizeInBits();
1014 }
1015
1016 using value_iterator = const EVT *;
1017
1018 value_iterator value_begin() const { return ValueList; }
1019 value_iterator value_end() const { return ValueList+NumValues; }
1020 iterator_range<value_iterator> values() const {
1021 return llvm::make_range(value_begin(), value_end());
1022 }
1023
1024 /// Return the opcode of this operation for printing.
1025 std::string getOperationName(const SelectionDAG *G = nullptr) const;
1026 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1027 void print_types(raw_ostream &OS, const SelectionDAG *G) const;
1028 void print_details(raw_ostream &OS, const SelectionDAG *G) const;
1029 void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1030 void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1031
1032 /// Print a SelectionDAG node and all children down to
1033 /// the leaves. The given SelectionDAG allows target-specific nodes
1034 /// to be printed in human-readable form. Unlike printr, this will
1035 /// print the whole DAG, including children that appear multiple
1036 /// times.
1037 ///
1038 void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;
1039
1040 /// Print a SelectionDAG node and children up to
1041 /// depth "depth." The given SelectionDAG allows target-specific
1042 /// nodes to be printed in human-readable form. Unlike printr, this
1043 /// will print children that appear multiple times wherever they are
1044 /// used.
1045 ///
1046 void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
1047 unsigned depth = 100) const;
1048
1049 /// Dump this node, for debugging.
1050 void dump() const;
1051
1052 /// Dump (recursively) this node and its use-def subgraph.
1053 void dumpr() const;
1054
1055 /// Dump this node, for debugging.
1056 /// The given SelectionDAG allows target-specific nodes to be printed
1057 /// in human-readable form.
1058 void dump(const SelectionDAG *G) const;
1059
1060 /// Dump (recursively) this node and its use-def subgraph.
1061 /// The given SelectionDAG allows target-specific nodes to be printed
1062 /// in human-readable form.
1063 void dumpr(const SelectionDAG *G) const;
1064
1065 /// printrFull to dbgs(). The given SelectionDAG allows
1066 /// target-specific nodes to be printed in human-readable form.
1067 /// Unlike dumpr, this will print the whole DAG, including children
1068 /// that appear multiple times.
1069 void dumprFull(const SelectionDAG *G = nullptr) const;
1070
1071 /// printrWithDepth to dbgs(). The given
1072 /// SelectionDAG allows target-specific nodes to be printed in
1073 /// human-readable form. Unlike dumpr, this will print children
1074 /// that appear multiple times wherever they are used.
1075 ///
1076 void dumprWithDepth(const SelectionDAG *G = nullptr,
1077 unsigned depth = 100) const;
1078
1079 /// Gather unique data for the node.
1080 void Profile(FoldingSetNodeID &ID) const;
1081
1082 /// This method should only be used by the SDUse class.
1083 void addUse(SDUse &U) { U.addToList(&UseList); }
1084
1085protected:
1086 static SDVTList getSDVTList(EVT VT) {
1087 SDVTList Ret = { getValueTypeList(VT), 1 };
1088 return Ret;
1089 }
1090
1091 /// Create an SDNode.
1092 ///
1093 /// SDNodes are created without any operands, and never own the operand
1094 /// storage. To add operands, see SelectionDAG::createOperands.
1095 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1096 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1097 IROrder(Order), debugLoc(std::move(dl)) {
1098 memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
1099 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1099, __PRETTY_FUNCTION__))
;
1100 assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1101, __PRETTY_FUNCTION__))
1101 "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1101, __PRETTY_FUNCTION__))
;
1102 }
1103
1104 /// Release the operands and set this node to have zero operands.
1105 void DropOperands();
1106};
1107
1108/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1109/// into SDNode creation functions.
1110/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1111/// from the original Instruction, and IROrder is the ordinal position of
1112/// the instruction.
1113/// When an SDNode is created after the DAG is being built, both DebugLoc and
1114/// the IROrder are propagated from the original SDNode.
1115/// So SDLoc class provides two constructors besides the default one, one to
1116/// be used by the DAGBuilder, the other to be used by others.
1117class SDLoc {
1118private:
1119 DebugLoc DL;
1120 int IROrder = 0;
1121
1122public:
1123 SDLoc() = default;
1124 SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
1125 SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
1126 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1127 assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void
> (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1127, __PRETTY_FUNCTION__))
;
1128 if (I)
1129 DL = I->getDebugLoc();
1130 }
1131
1132 unsigned getIROrder() const { return IROrder; }
1133 const DebugLoc &getDebugLoc() const { return DL; }
1134};
1135
1136// Define inline functions from the SDValue class.
1137
1138inline SDValue::SDValue(SDNode *node, unsigned resno)
1139 : Node(node), ResNo(resno) {
1140 // Explicitly check for !ResNo to avoid use-after-free, because there are
1141 // callers that use SDValue(N, 0) with a deleted N to indicate successful
1142 // combines.
1143 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1144, __PRETTY_FUNCTION__))
1144 "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1144, __PRETTY_FUNCTION__))
;
1145 assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1145, __PRETTY_FUNCTION__))
;
1146}
1147
1148inline unsigned SDValue::getOpcode() const {
1149 return Node->getOpcode();
1150}
1151
1152inline EVT SDValue::getValueType() const {
1153 return Node->getValueType(ResNo);
12
Called C++ object pointer is null
1154}
1155
1156inline unsigned SDValue::getNumOperands() const {
1157 return Node->getNumOperands();
1158}
1159
1160inline const SDValue &SDValue::getOperand(unsigned i) const {
1161 return Node->getOperand(i);
1162}
1163
1164inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
1165 return Node->getConstantOperandVal(i);
1166}
1167
1168inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
1169 return Node->getConstantOperandAPInt(i);
1170}
1171
1172inline bool SDValue::isTargetOpcode() const {
1173 return Node->isTargetOpcode();
1174}
1175
1176inline bool SDValue::isTargetMemoryOpcode() const {
1177 return Node->isTargetMemoryOpcode();
1178}
1179
1180inline bool SDValue::isMachineOpcode() const {
1181 return Node->isMachineOpcode();
1182}
1183
1184inline unsigned SDValue::getMachineOpcode() const {
1185 return Node->getMachineOpcode();
1186}
1187
1188inline bool SDValue::isUndef() const {
1189 return Node->isUndef();
1190}
1191
1192inline bool SDValue::use_empty() const {
1193 return !Node->hasAnyUseOfValue(ResNo);
1194}
1195
1196inline bool SDValue::hasOneUse() const {
1197 return Node->hasNUsesOfValue(1, ResNo);
1198}
1199
1200inline const DebugLoc &SDValue::getDebugLoc() const {
1201 return Node->getDebugLoc();
1202}
1203
1204inline void SDValue::dump() const {
1205 return Node->dump();
1206}
1207
1208inline void SDValue::dump(const SelectionDAG *G) const {
1209 return Node->dump(G);
1210}
1211
1212inline void SDValue::dumpr() const {
1213 return Node->dumpr();
1214}
1215
1216inline void SDValue::dumpr(const SelectionDAG *G) const {
1217 return Node->dumpr(G);
1218}
1219
1220// Define inline functions from the SDUse class.
1221
1222inline void SDUse::set(const SDValue &V) {
1223 if (Val.getNode()) removeFromList();
1224 Val = V;
1225 if (V.getNode()) V.getNode()->addUse(*this);
1226}
1227
1228inline void SDUse::setInitial(const SDValue &V) {
1229 Val = V;
1230 V.getNode()->addUse(*this);
1231}
1232
1233inline void SDUse::setNode(SDNode *N) {
1234 if (Val.getNode()) removeFromList();
1235 Val.setNode(N);
1236 if (N) N->addUse(*this);
1237}
1238
1239/// This class is used to form a handle around another node that
1240/// is persistent and is updated across invocations of replaceAllUsesWith on its
1241/// operand. This node should be directly created by end-users and not added to
1242/// the AllNodes list.
1243class HandleSDNode : public SDNode {
1244 SDUse Op;
1245
1246public:
1247 explicit HandleSDNode(SDValue X)
1248 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
1249 // HandleSDNodes are never inserted into the DAG, so they won't be
1250 // auto-numbered. Use ID 65535 as a sentinel.
1251 PersistentId = 0xffff;
1252
1253 // Manually set up the operand list. This node type is special in that it's
1254 // always stack allocated and SelectionDAG does not manage its operands.
1255 // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
1256 // be so special.
1257 Op.setUser(this);
1258 Op.setInitial(X);
1259 NumOperands = 1;
1260 OperandList = &Op;
1261 }
1262 ~HandleSDNode();
1263
1264 const SDValue &getValue() const { return Op; }
1265};
1266
1267class AddrSpaceCastSDNode : public SDNode {
1268private:
1269 unsigned SrcAddrSpace;
1270 unsigned DestAddrSpace;
1271
1272public:
1273 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1274 unsigned SrcAS, unsigned DestAS);
1275
1276 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
1277 unsigned getDestAddressSpace() const { return DestAddrSpace; }
1278
1279 static bool classof(const SDNode *N) {
1280 return N->getOpcode() == ISD::ADDRSPACECAST;
1281 }
1282};
1283
1284/// This is an abstract virtual class for memory operations.
1285class MemSDNode : public SDNode {
1286private:
1287 // VT of in-memory value.
1288 EVT MemoryVT;
1289
1290protected:
1291 /// Memory reference information.
1292 MachineMemOperand *MMO;
1293
1294public:
1295 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1296 EVT memvt, MachineMemOperand *MMO);
1297
1298 bool readMem() const { return MMO->isLoad(); }
1299 bool writeMem() const { return MMO->isStore(); }
1300
1301 /// Returns alignment and volatility of the memory access
1302 unsigned getOriginalAlignment() const {
1303 return MMO->getBaseAlignment();
1304 }
1305 unsigned getAlignment() const {
1306 return MMO->getAlignment();
1307 }
1308
1309 /// Return the SubclassData value, without HasDebugValue. This contains an
1310 /// encoding of the volatile flag, as well as bits used by subclasses. This
1311 /// function should only be used to compute a FoldingSetNodeID value.
1312 /// The HasDebugValue bit is masked out because CSE map needs to match
1313 /// nodes with debug info with nodes without debug info. Same is about
1314 /// isDivergent bit.
1315 unsigned getRawSubclassData() const {
1316 uint16_t Data;
1317 union {
1318 char RawSDNodeBits[sizeof(uint16_t)];
1319 SDNodeBitfields SDNodeBits;
1320 };
1321 memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
1322 SDNodeBits.HasDebugValue = 0;
1323 SDNodeBits.IsDivergent = false;
1324 memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
1325 return Data;
1326 }
1327
1328 bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
1329 bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
1330 bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
1331 bool isInvariant() const { return MemSDNodeBits.IsInvariant; }
1332
1333 // Returns the offset from the location of the access.
1334 int64_t getSrcValueOffset() const { return MMO->getOffset(); }
1335
1336 /// Returns the AA info that describes the dereference.
1337 AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }
1338
1339 /// Returns the Ranges that describes the dereference.
1340 const MDNode *getRanges() const { return MMO->getRanges(); }
1341
1342