Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1163, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name LegalizeIntegerTypes.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/include -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-12-09-002921-48462-1 -x c++ /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

1//===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements integer type expansion and promotion for LegalizeTypes.
10// Promotion is the act of changing a computation in an illegal type into a
11// computation in a larger type. For example, implementing i8 arithmetic in an
12// i32 register (often needed on powerpc).
13// Expansion is the act of changing a computation in an illegal type into a
14// computation in two identical registers of a smaller type. For example,
15// implementing i64 arithmetic in two i32 registers (often needed on 32-bit
16// targets).
17//
18//===----------------------------------------------------------------------===//
19
20#include "LegalizeTypes.h"
21#include "llvm/IR/DerivedTypes.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/KnownBits.h"
24#include "llvm/Support/raw_ostream.h"
25using namespace llvm;
26
27#define DEBUG_TYPE"legalize-types" "legalize-types"
28
29//===----------------------------------------------------------------------===//
30// Integer Result Promotion
31//===----------------------------------------------------------------------===//
32
33/// PromoteIntegerResult - This method is called when a result of a node is
34/// found to be in need of promotion to a larger type. At this point, the node
35/// may also have invalid operands or may have other results that need
36/// expansion, we just know that (at least) one result needs promotion.
37void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
39 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
40 SDValue Res = SDValue();
41
42 // See if the target wants to custom expand this node.
43 if (CustomLowerNode(N, N->getValueType(ResNo), true)) {
44 LLVM_DEBUG(dbgs() << "Node has been custom expanded, done\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Node has been custom expanded, done\n"
; } } while (false)
;
45 return;
46 }
47
48 switch (N->getOpcode()) {
49 default:
50#ifndef NDEBUG
51 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); dbgs() << "\n";
53#endif
54 llvm_unreachable("Do not know how to promote this operator!")::llvm::llvm_unreachable_internal("Do not know how to promote this operator!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 54)
;
55 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
56 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
58 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break;
60 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
61 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
62 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
63 case ISD::CTLZ_ZERO_UNDEF:
64 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
65 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
66 case ISD::CTTZ_ZERO_UNDEF:
67 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
68 case ISD::EXTRACT_VECTOR_ELT:
69 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
70 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
71 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
72 break;
73 case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
74 break;
75 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
76 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
77 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
78 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
79 case ISD::SMIN:
80 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
81 case ISD::UMIN:
82 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break;
83
84 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
85 case ISD::SIGN_EXTEND_INREG:
86 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
87 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
88 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
89 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
90 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
91 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
92
93 case ISD::EXTRACT_SUBVECTOR:
94 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
95 case ISD::VECTOR_SHUFFLE:
96 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
97 case ISD::INSERT_VECTOR_ELT:
98 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
99 case ISD::BUILD_VECTOR:
100 Res = PromoteIntRes_BUILD_VECTOR(N); break;
101 case ISD::SCALAR_TO_VECTOR:
102 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
103 case ISD::SPLAT_VECTOR:
104 Res = PromoteIntRes_SPLAT_VECTOR(N); break;
105 case ISD::CONCAT_VECTORS:
106 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
107
108 case ISD::ANY_EXTEND_VECTOR_INREG:
109 case ISD::SIGN_EXTEND_VECTOR_INREG:
110 case ISD::ZERO_EXTEND_VECTOR_INREG:
111 Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
112
113 case ISD::SIGN_EXTEND:
114 case ISD::ZERO_EXTEND:
115 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
116
117 case ISD::STRICT_FP_TO_SINT:
118 case ISD::STRICT_FP_TO_UINT:
119 case ISD::FP_TO_SINT:
120 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
121
122 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
123
124 case ISD::FLT_ROUNDS_: Res = PromoteIntRes_FLT_ROUNDS(N); break;
125
126 case ISD::AND:
127 case ISD::OR:
128 case ISD::XOR:
129 case ISD::ADD:
130 case ISD::SUB:
131 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
132
133 case ISD::SDIV:
134 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
135
136 case ISD::UDIV:
137 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
138
139 case ISD::SADDO:
140 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
141 case ISD::UADDO:
142 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
143 case ISD::SMULO:
144 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
145
146 case ISD::ADDE:
147 case ISD::SUBE:
148 case ISD::ADDCARRY:
149 case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
150
151 case ISD::SADDSAT:
152 case ISD::UADDSAT:
153 case ISD::SSUBSAT:
154 case ISD::USUBSAT: Res = PromoteIntRes_ADDSUBSAT(N); break;
155
156 case ISD::SMULFIX:
157 case ISD::SMULFIXSAT:
158 case ISD::UMULFIX:
159 case ISD::UMULFIXSAT: Res = PromoteIntRes_MULFIX(N); break;
160
161 case ISD::ABS: Res = PromoteIntRes_ABS(N); break;
162
163 case ISD::ATOMIC_LOAD:
164 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
165
166 case ISD::ATOMIC_LOAD_ADD:
167 case ISD::ATOMIC_LOAD_SUB:
168 case ISD::ATOMIC_LOAD_AND:
169 case ISD::ATOMIC_LOAD_CLR:
170 case ISD::ATOMIC_LOAD_OR:
171 case ISD::ATOMIC_LOAD_XOR:
172 case ISD::ATOMIC_LOAD_NAND:
173 case ISD::ATOMIC_LOAD_MIN:
174 case ISD::ATOMIC_LOAD_MAX:
175 case ISD::ATOMIC_LOAD_UMIN:
176 case ISD::ATOMIC_LOAD_UMAX:
177 case ISD::ATOMIC_SWAP:
178 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
179
180 case ISD::ATOMIC_CMP_SWAP:
181 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
182 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
183 break;
184
185 case ISD::VECREDUCE_ADD:
186 case ISD::VECREDUCE_MUL:
187 case ISD::VECREDUCE_AND:
188 case ISD::VECREDUCE_OR:
189 case ISD::VECREDUCE_XOR:
190 case ISD::VECREDUCE_SMAX:
191 case ISD::VECREDUCE_SMIN:
192 case ISD::VECREDUCE_UMAX:
193 case ISD::VECREDUCE_UMIN:
194 Res = PromoteIntRes_VECREDUCE(N);
195 break;
196 }
197
198 // If the result is null then the sub-method took care of registering it.
199 if (Res.getNode())
200 SetPromotedInteger(SDValue(N, ResNo), Res);
201}
202
203SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
204 unsigned ResNo) {
205 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
206 return GetPromotedInteger(Op);
207}
208
209SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
210 // Sign-extend the new bits, and continue the assertion.
211 SDValue Op = SExtPromotedInteger(N->getOperand(0));
212 return DAG.getNode(ISD::AssertSext, SDLoc(N),
213 Op.getValueType(), Op, N->getOperand(1));
214}
215
216SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
217 // Zero the new bits, and continue the assertion.
218 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
219 return DAG.getNode(ISD::AssertZext, SDLoc(N),
220 Op.getValueType(), Op, N->getOperand(1));
221}
222
223SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
224 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
225 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
226 N->getMemoryVT(), ResVT,
227 N->getChain(), N->getBasePtr(),
228 N->getMemOperand());
229 // Legalize the chain result - switch anything that used the old chain to
230 // use the new one.
231 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
232 return Res;
233}
234
235SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
236 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
237 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
238 N->getMemoryVT(),
239 N->getChain(), N->getBasePtr(),
240 Op2, N->getMemOperand());
241 // Legalize the chain result - switch anything that used the old chain to
242 // use the new one.
243 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
244 return Res;
245}
246
247SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
248 unsigned ResNo) {
249 if (ResNo == 1) {
250 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS)((N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS) ? static_cast
<void> (0) : __assert_fail ("N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 250, __PRETTY_FUNCTION__))
;
251 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
252 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
253
254 // Only use the result of getSetCCResultType if it is legal,
255 // otherwise just use the promoted result type (NVT).
256 if (!TLI.isTypeLegal(SVT))
257 SVT = NVT;
258
259 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
260 SDValue Res = DAG.getAtomicCmpSwap(
261 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
262 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
263 N->getMemOperand());
264 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
265 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
266 return Res.getValue(1);
267 }
268
269 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
270 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
271 SDVTList VTs =
272 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
273 SDValue Res = DAG.getAtomicCmpSwap(
274 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
275 N->getBasePtr(), Op2, Op3, N->getMemOperand());
276 // Update the use to N with the newly created Res.
277 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
278 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
279 return Res;
280}
281
282SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
283 SDValue InOp = N->getOperand(0);
284 EVT InVT = InOp.getValueType();
285 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
286 EVT OutVT = N->getValueType(0);
287 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
288 SDLoc dl(N);
289
290 switch (getTypeAction(InVT)) {
291 case TargetLowering::TypeLegal:
292 break;
293 case TargetLowering::TypePromoteInteger:
294 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
295 // The input promotes to the same size. Convert the promoted value.
296 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
297 break;
298 case TargetLowering::TypeSoftenFloat:
299 // Promote the integer operand by hand.
300 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
301 case TargetLowering::TypePromoteFloat: {
302 // Convert the promoted float by hand.
303 if (!NOutVT.isVector())
304 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
305 break;
306 }
307 case TargetLowering::TypeExpandInteger:
308 case TargetLowering::TypeExpandFloat:
309 break;
310 case TargetLowering::TypeScalarizeVector:
311 // Convert the element to an integer and promote it by hand.
312 if (!NOutVT.isVector())
313 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
314 BitConvertToInteger(GetScalarizedVector(InOp)));
315 break;
316 case TargetLowering::TypeSplitVector: {
317 if (!NOutVT.isVector()) {
318 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
319 // pieces of the input into integers and reassemble in the final type.
320 SDValue Lo, Hi;
321 GetSplitVector(N->getOperand(0), Lo, Hi);
322 Lo = BitConvertToInteger(Lo);
323 Hi = BitConvertToInteger(Hi);
324
325 if (DAG.getDataLayout().isBigEndian())
326 std::swap(Lo, Hi);
327
328 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
329 EVT::getIntegerVT(*DAG.getContext(),
330 NOutVT.getSizeInBits()),
331 JoinIntegers(Lo, Hi));
332 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
333 }
334 break;
335 }
336 case TargetLowering::TypeWidenVector:
337 // The input is widened to the same size. Convert to the widened value.
338 // Make sure that the outgoing value is not a vector, because this would
339 // make us bitcast between two vectors which are legalized in different ways.
340 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
341 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
342 // If the output type is also a vector and widening it to the same size
343 // as the widened input type would be a legal type, we can widen the bitcast
344 // and handle the promotion after.
345 if (NOutVT.isVector()) {
346 unsigned WidenInSize = NInVT.getSizeInBits();
347 unsigned OutSize = OutVT.getSizeInBits();
348 if (WidenInSize % OutSize == 0) {
349 unsigned Scale = WidenInSize / OutSize;
350 EVT WideOutVT = EVT::getVectorVT(*DAG.getContext(),
351 OutVT.getVectorElementType(),
352 OutVT.getVectorNumElements() * Scale);
353 if (isTypeLegal(WideOutVT)) {
354 InOp = DAG.getBitcast(WideOutVT, GetWidenedVector(InOp));
355 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
356 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp,
357 DAG.getConstant(0, dl, IdxTy));
358 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp);
359 }
360 }
361 }
362 }
363
364 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
365 CreateStackStoreLoad(InOp, OutVT));
366}
367
368// Helper for BSWAP/BITREVERSE promotion to ensure we can fit any shift amount
369// in the VT returned by getShiftAmountTy and to return a safe VT if we can't.
370static EVT getShiftAmountTyForConstant(EVT VT, const TargetLowering &TLI,
371 SelectionDAG &DAG) {
372 EVT ShiftVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
373 // If any possible shift value won't fit in the prefered type, just use
374 // something safe. It will be legalized when the shift is expanded.
375 if (!ShiftVT.isVector() &&
376 ShiftVT.getSizeInBits() < Log2_32_Ceil(VT.getSizeInBits()))
377 ShiftVT = MVT::i32;
378 return ShiftVT;
379}
380
381SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
382 SDValue Op = GetPromotedInteger(N->getOperand(0));
383 EVT OVT = N->getValueType(0);
384 EVT NVT = Op.getValueType();
385 SDLoc dl(N);
386
387 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
388 EVT ShiftVT = getShiftAmountTyForConstant(NVT, TLI, DAG);
389 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
390 DAG.getConstant(DiffBits, dl, ShiftVT));
391}
392
393SDValue DAGTypeLegalizer::PromoteIntRes_BITREVERSE(SDNode *N) {
394 SDValue Op = GetPromotedInteger(N->getOperand(0));
395 EVT OVT = N->getValueType(0);
396 EVT NVT = Op.getValueType();
397 SDLoc dl(N);
398
399 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
400 EVT ShiftVT = getShiftAmountTyForConstant(NVT, TLI, DAG);
401 return DAG.getNode(ISD::SRL, dl, NVT,
402 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op),
403 DAG.getConstant(DiffBits, dl, ShiftVT));
404}
405
406SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
407 // The pair element type may be legal, or may not promote to the same type as
408 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
409 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
410 TLI.getTypeToTransformTo(*DAG.getContext(),
411 N->getValueType(0)), JoinIntegers(N->getOperand(0),
412 N->getOperand(1)));
413}
414
415SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
416 EVT VT = N->getValueType(0);
417 // FIXME there is no actual debug info here
418 SDLoc dl(N);
419 // Zero extend things like i1, sign extend everything else. It shouldn't
420 // matter in theory which one we pick, but this tends to give better code?
421 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
422 SDValue Result = DAG.getNode(Opc, dl,
423 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
424 SDValue(N, 0));
425 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?")((isa<ConstantSDNode>(Result) && "Didn't constant fold ext?"
) ? static_cast<void> (0) : __assert_fail ("isa<ConstantSDNode>(Result) && \"Didn't constant fold ext?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 425, __PRETTY_FUNCTION__))
;
426 return Result;
427}
428
429SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
430 // Zero extend to the promoted type and do the count there.
431 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
432 SDLoc dl(N);
433 EVT OVT = N->getValueType(0);
434 EVT NVT = Op.getValueType();
435 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
436 // Subtract off the extra leading bits in the bigger type.
437 return DAG.getNode(
438 ISD::SUB, dl, NVT, Op,
439 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
440 NVT));
441}
442
443SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
444 // Zero extend to the promoted type and do the count there.
445 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
446 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
447}
448
449SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
450 SDValue Op = GetPromotedInteger(N->getOperand(0));
451 EVT OVT = N->getValueType(0);
452 EVT NVT = Op.getValueType();
453 SDLoc dl(N);
454 if (N->getOpcode() == ISD::CTTZ) {
455 // The count is the same in the promoted type except if the original
456 // value was zero. This can be handled by setting the bit just off
457 // the top of the original type.
458 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
459 OVT.getScalarSizeInBits());
460 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
461 }
462 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
463}
464
465SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
466 SDLoc dl(N);
467 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
468
469 SDValue Op0 = N->getOperand(0);
470 SDValue Op1 = N->getOperand(1);
471
472 // If the input also needs to be promoted, do that first so we can get a
473 // get a good idea for the output type.
474 if (TLI.getTypeAction(*DAG.getContext(), Op0.getValueType())
475 == TargetLowering::TypePromoteInteger) {
476 SDValue In = GetPromotedInteger(Op0);
477
478 // If the new type is larger than NVT, use it. We probably won't need to
479 // promote it again.
480 EVT SVT = In.getValueType().getScalarType();
481 if (SVT.bitsGE(NVT)) {
482 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1);
483 return DAG.getAnyExtOrTrunc(Ext, dl, NVT);
484 }
485 }
486
487 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1);
488}
489
490SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
491 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
492 unsigned NewOpc = N->getOpcode();
493 SDLoc dl(N);
494
495 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
496 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
497 // and SINT conversions are Custom, there is no way to tell which is
498 // preferable. We choose SINT because that's the right thing on PPC.)
499 if (N->getOpcode() == ISD::FP_TO_UINT &&
500 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
501 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
502 NewOpc = ISD::FP_TO_SINT;
503
504 if (N->getOpcode() == ISD::STRICT_FP_TO_UINT &&
505 !TLI.isOperationLegal(ISD::STRICT_FP_TO_UINT, NVT) &&
506 TLI.isOperationLegalOrCustom(ISD::STRICT_FP_TO_SINT, NVT))
507 NewOpc = ISD::STRICT_FP_TO_SINT;
508
509 SDValue Res;
510 if (N->isStrictFPOpcode()) {
511 Res = DAG.getNode(NewOpc, dl, { NVT, MVT::Other },
512 { N->getOperand(0), N->getOperand(1) });
513 // Legalize the chain result - switch anything that used the old chain to
514 // use the new one.
515 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
516 } else
517 Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
518
519 // Assert that the converted value fits in the original type. If it doesn't
520 // (eg: because the value being converted is too big), then the result of the
521 // original operation was undefined anyway, so the assert is still correct.
522 //
523 // NOTE: fp-to-uint to fp-to-sint promotion guarantees zero extend. For example:
524 // before legalization: fp-to-uint16, 65534. -> 0xfffe
525 // after legalization: fp-to-sint32, 65534. -> 0x0000fffe
526 return DAG.getNode((N->getOpcode() == ISD::FP_TO_UINT ||
527 N->getOpcode() == ISD::STRICT_FP_TO_UINT) ?
528 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
529 DAG.getValueType(N->getValueType(0).getScalarType()));
530}
531
532SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
533 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
534 SDLoc dl(N);
535
536 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
537}
538
539SDValue DAGTypeLegalizer::PromoteIntRes_FLT_ROUNDS(SDNode *N) {
540 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
541 SDLoc dl(N);
542
543 return DAG.getNode(N->getOpcode(), dl, NVT);
544}
545
546SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
547 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
548 SDLoc dl(N);
549
550 if (getTypeAction(N->getOperand(0).getValueType())
551 == TargetLowering::TypePromoteInteger) {
552 SDValue Res = GetPromotedInteger(N->getOperand(0));
553 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!")((Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType().bitsLE(NVT) && \"Extension doesn't make sense!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 553, __PRETTY_FUNCTION__))
;
554
555 // If the result and operand types are the same after promotion, simplify
556 // to an in-register extension.
557 if (NVT == Res.getValueType()) {
558 // The high bits are not guaranteed to be anything. Insert an extend.
559 if (N->getOpcode() == ISD::SIGN_EXTEND)
560 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
561 DAG.getValueType(N->getOperand(0).getValueType()));
562 if (N->getOpcode() == ISD::ZERO_EXTEND)
563 return DAG.getZeroExtendInReg(Res, dl,
564 N->getOperand(0).getValueType().getScalarType());
565 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!")((N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::ANY_EXTEND && \"Unknown integer extension!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 565, __PRETTY_FUNCTION__))
;
566 return Res;
567 }
568 }
569
570 // Otherwise, just extend the original operand all the way to the larger type.
571 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
572}
573
574SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
575 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!")((ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDLoad(N) && \"Indexed load during type legalization!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 575, __PRETTY_FUNCTION__))
;
576 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
577 ISD::LoadExtType ExtType =
578 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
579 SDLoc dl(N);
580 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
581 N->getMemoryVT(), N->getMemOperand());
582
583 // Legalize the chain result - switch anything that used the old chain to
584 // use the new one.
585 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
586 return Res;
587}
588
589SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
590 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
591 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
592
593 SDLoc dl(N);
594 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
595 N->getMask(), ExtPassThru, N->getMemoryVT(),
596 N->getMemOperand(), ISD::EXTLOAD);
597 // Legalize the chain result - switch anything that used the old chain to
598 // use the new one.
599 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
600 return Res;
601}
602
603SDValue DAGTypeLegalizer::PromoteIntRes_MGATHER(MaskedGatherSDNode *N) {
604 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
605 SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
606 assert(NVT == ExtPassThru.getValueType() &&((NVT == ExtPassThru.getValueType() && "Gather result type and the passThru agrument type should be the same"
) ? static_cast<void> (0) : __assert_fail ("NVT == ExtPassThru.getValueType() && \"Gather result type and the passThru agrument type should be the same\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 607, __PRETTY_FUNCTION__))
607 "Gather result type and the passThru agrument type should be the same")((NVT == ExtPassThru.getValueType() && "Gather result type and the passThru agrument type should be the same"
) ? static_cast<void> (0) : __assert_fail ("NVT == ExtPassThru.getValueType() && \"Gather result type and the passThru agrument type should be the same\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 607, __PRETTY_FUNCTION__))
;
608
609 SDLoc dl(N);
610 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(),
611 N->getIndex(), N->getScale() };
612 SDValue Res = DAG.getMaskedGather(DAG.getVTList(NVT, MVT::Other),
613 N->getMemoryVT(), dl, Ops,
614 N->getMemOperand(), N->getIndexType());
615 // Legalize the chain result - switch anything that used the old chain to
616 // use the new one.
617 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
618 return Res;
619}
620
621/// Promote the overflow flag of an overflowing arithmetic node.
622SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
623 // Change the return type of the boolean result while obeying
624 // getSetCCResultType.
625 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
626 EVT VT = N->getValueType(0);
627 EVT SVT = getSetCCResultType(VT);
628 SDValue Ops[3] = { N->getOperand(0), N->getOperand(1) };
629 unsigned NumOps = N->getNumOperands();
630 assert(NumOps <= 3 && "Too many operands")((NumOps <= 3 && "Too many operands") ? static_cast
<void> (0) : __assert_fail ("NumOps <= 3 && \"Too many operands\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 630, __PRETTY_FUNCTION__))
;
631 if (NumOps == 3)
632 Ops[2] = N->getOperand(2);
633
634 SDLoc dl(N);
635 SDValue Res = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(VT, SVT),
636 makeArrayRef(Ops, NumOps));
637
638 // Modified the sum result - switch anything that used the old sum to use
639 // the new one.
640 ReplaceValueWith(SDValue(N, 0), Res);
641
642 // Convert to the expected type.
643 return DAG.getBoolExtOrTrunc(Res.getValue(1), dl, NVT, VT);
644}
645
646SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBSAT(SDNode *N) {
647 // If the promoted type is legal, we can convert this to:
648 // 1. ANY_EXTEND iN to iM
649 // 2. SHL by M-N
650 // 3. [US][ADD|SUB]SAT
651 // 4. L/ASHR by M-N
652 // Else it is more efficient to convert this to a min and a max
653 // operation in the higher precision arithmetic.
654 SDLoc dl(N);
655 SDValue Op1 = N->getOperand(0);
656 SDValue Op2 = N->getOperand(1);
657 unsigned OldBits = Op1.getScalarValueSizeInBits();
658
659 unsigned Opcode = N->getOpcode();
660
661 SDValue Op1Promoted, Op2Promoted;
662 if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
663 Op1Promoted = ZExtPromotedInteger(Op1);
664 Op2Promoted = ZExtPromotedInteger(Op2);
665 } else {
666 Op1Promoted = SExtPromotedInteger(Op1);
667 Op2Promoted = SExtPromotedInteger(Op2);
668 }
669 EVT PromotedType = Op1Promoted.getValueType();
670 unsigned NewBits = PromotedType.getScalarSizeInBits();
671
672 if (TLI.isOperationLegalOrCustom(Opcode, PromotedType)) {
673 unsigned ShiftOp;
674 switch (Opcode) {
675 case ISD::SADDSAT:
676 case ISD::SSUBSAT:
677 ShiftOp = ISD::SRA;
678 break;
679 case ISD::UADDSAT:
680 case ISD::USUBSAT:
681 ShiftOp = ISD::SRL;
682 break;
683 default:
684 llvm_unreachable("Expected opcode to be signed or unsigned saturation "::llvm::llvm_unreachable_internal("Expected opcode to be signed or unsigned saturation "
"addition or subtraction", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 685)
685 "addition or subtraction")::llvm::llvm_unreachable_internal("Expected opcode to be signed or unsigned saturation "
"addition or subtraction", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 685)
;
686 }
687
688 unsigned SHLAmount = NewBits - OldBits;
689 EVT SHVT = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
690 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT);
691 Op1Promoted =
692 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
693 Op2Promoted =
694 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
695
696 SDValue Result =
697 DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
698 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
699 } else {
700 if (Opcode == ISD::USUBSAT) {
701 SDValue Max =
702 DAG.getNode(ISD::UMAX, dl, PromotedType, Op1Promoted, Op2Promoted);
703 return DAG.getNode(ISD::SUB, dl, PromotedType, Max, Op2Promoted);
704 }
705
706 if (Opcode == ISD::UADDSAT) {
707 APInt MaxVal = APInt::getAllOnesValue(OldBits).zext(NewBits);
708 SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
709 SDValue Add =
710 DAG.getNode(ISD::ADD, dl, PromotedType, Op1Promoted, Op2Promoted);
711 return DAG.getNode(ISD::UMIN, dl, PromotedType, Add, SatMax);
712 }
713
714 unsigned AddOp = Opcode == ISD::SADDSAT ? ISD::ADD : ISD::SUB;
715 APInt MinVal = APInt::getSignedMinValue(OldBits).sext(NewBits);
716 APInt MaxVal = APInt::getSignedMaxValue(OldBits).sext(NewBits);
717 SDValue SatMin = DAG.getConstant(MinVal, dl, PromotedType);
718 SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType);
719 SDValue Result =
720 DAG.getNode(AddOp, dl, PromotedType, Op1Promoted, Op2Promoted);
721 Result = DAG.getNode(ISD::SMIN, dl, PromotedType, Result, SatMax);
722 Result = DAG.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin);
723 return Result;
724 }
725}
726
727SDValue DAGTypeLegalizer::PromoteIntRes_MULFIX(SDNode *N) {
728 // Can just promote the operands then continue with operation.
729 SDLoc dl(N);
730 SDValue Op1Promoted, Op2Promoted;
731 bool Signed =
732 N->getOpcode() == ISD::SMULFIX || N->getOpcode() == ISD::SMULFIXSAT;
733 bool Saturating =
734 N->getOpcode() == ISD::SMULFIXSAT || N->getOpcode() == ISD::UMULFIXSAT;
735 if (Signed) {
736 Op1Promoted = SExtPromotedInteger(N->getOperand(0));
737 Op2Promoted = SExtPromotedInteger(N->getOperand(1));
738 } else {
739 Op1Promoted = ZExtPromotedInteger(N->getOperand(0));
740 Op2Promoted = ZExtPromotedInteger(N->getOperand(1));
741 }
742 EVT OldType = N->getOperand(0).getValueType();
743 EVT PromotedType = Op1Promoted.getValueType();
744 unsigned DiffSize =
745 PromotedType.getScalarSizeInBits() - OldType.getScalarSizeInBits();
746
747 if (Saturating) {
748 // Promoting the operand and result values changes the saturation width,
749 // which is extends the values that we clamp to on saturation. This could be
750 // resolved by shifting one of the operands the same amount, which would
751 // also shift the result we compare against, then shifting back.
752 EVT ShiftTy = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
753 Op1Promoted = DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted,
754 DAG.getConstant(DiffSize, dl, ShiftTy));
755 SDValue Result = DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted,
756 Op2Promoted, N->getOperand(2));
757 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL;
758 return DAG.getNode(ShiftOp, dl, PromotedType, Result,
759 DAG.getConstant(DiffSize, dl, ShiftTy));
760 }
761 return DAG.getNode(N->getOpcode(), dl, PromotedType, Op1Promoted, Op2Promoted,
762 N->getOperand(2));
763}
764
765SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
766 if (ResNo == 1)
767 return PromoteIntRes_Overflow(N);
768
769 // The operation overflowed iff the result in the larger type is not the
770 // sign extension of its truncation to the original type.
771 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
772 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
773 EVT OVT = N->getOperand(0).getValueType();
774 EVT NVT = LHS.getValueType();
775 SDLoc dl(N);
776
777 // Do the arithmetic in the larger type.
778 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
779 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
780
781 // Calculate the overflow flag: sign extend the arithmetic result from
782 // the original type.
783 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
784 DAG.getValueType(OVT));
785 // Overflowed if and only if this is not equal to Res.
786 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
787
788 // Use the calculated overflow everywhere.
789 ReplaceValueWith(SDValue(N, 1), Ofl);
790
791 return Res;
792}
793
794SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
795 SDValue LHS = GetPromotedInteger(N->getOperand(1));
796 SDValue RHS = GetPromotedInteger(N->getOperand(2));
797 return DAG.getSelect(SDLoc(N),
798 LHS.getValueType(), N->getOperand(0), LHS, RHS);
799}
800
801SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
802 SDValue Mask = N->getOperand(0);
803
804 SDValue LHS = GetPromotedInteger(N->getOperand(1));
805 SDValue RHS = GetPromotedInteger(N->getOperand(2));
806 return DAG.getNode(ISD::VSELECT, SDLoc(N),
807 LHS.getValueType(), Mask, LHS, RHS);
808}
809
810SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
811 SDValue LHS = GetPromotedInteger(N->getOperand(2));
812 SDValue RHS = GetPromotedInteger(N->getOperand(3));
813 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
814 LHS.getValueType(), N->getOperand(0),
815 N->getOperand(1), LHS, RHS, N->getOperand(4));
816}
817
818SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
819 EVT InVT = N->getOperand(0).getValueType();
820 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
821
822 EVT SVT = getSetCCResultType(InVT);
823
824 // If we got back a type that needs to be promoted, this likely means the
825 // the input type also needs to be promoted. So get the promoted type for
826 // the input and try the query again.
827 if (getTypeAction(SVT) == TargetLowering::TypePromoteInteger) {
828 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) {
829 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
830 SVT = getSetCCResultType(InVT);
831 } else {
832 // Input type isn't promoted, just use the default promoted type.
833 SVT = NVT;
834 }
835 }
836
837 SDLoc dl(N);
838 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&((SVT.isVector() == N->getOperand(0).getValueType().isVector
() && "Vector compare must return a vector result!") ?
static_cast<void> (0) : __assert_fail ("SVT.isVector() == N->getOperand(0).getValueType().isVector() && \"Vector compare must return a vector result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 839, __PRETTY_FUNCTION__))
839 "Vector compare must return a vector result!")((SVT.isVector() == N->getOperand(0).getValueType().isVector
() && "Vector compare must return a vector result!") ?
static_cast<void> (0) : __assert_fail ("SVT.isVector() == N->getOperand(0).getValueType().isVector() && \"Vector compare must return a vector result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 839, __PRETTY_FUNCTION__))
;
840
841 // Get the SETCC result using the canonical SETCC type.
842 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
843 N->getOperand(1), N->getOperand(2));
844
845 // Convert to the expected type.
846 return DAG.getSExtOrTrunc(SetCC, dl, NVT);
847}
848
849SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
850 SDValue LHS = GetPromotedInteger(N->getOperand(0));
851 SDValue RHS = N->getOperand(1);
852 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
853 RHS = ZExtPromotedInteger(RHS);
854 return DAG.getNode(ISD::SHL, SDLoc(N), LHS.getValueType(), LHS, RHS);
855}
856
857SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
858 SDValue Op = GetPromotedInteger(N->getOperand(0));
859 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
860 Op.getValueType(), Op, N->getOperand(1));
861}
862
863SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
864 // The input may have strange things in the top bits of the registers, but
865 // these operations don't care. They may have weird bits going out, but
866 // that too is okay if they are integer operations.
867 SDValue LHS = GetPromotedInteger(N->getOperand(0));
868 SDValue RHS = GetPromotedInteger(N->getOperand(1));
869 return DAG.getNode(N->getOpcode(), SDLoc(N),
870 LHS.getValueType(), LHS, RHS);
871}
872
873SDValue DAGTypeLegalizer::PromoteIntRes_SExtIntBinOp(SDNode *N) {
874 // Sign extend the input.
875 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
876 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
877 return DAG.getNode(N->getOpcode(), SDLoc(N),
878 LHS.getValueType(), LHS, RHS);
879}
880
881SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
882 // Zero extend the input.
883 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
884 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
885 return DAG.getNode(N->getOpcode(), SDLoc(N),
886 LHS.getValueType(), LHS, RHS);
887}
888
889SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
890 // The input value must be properly sign extended.
891 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
892 SDValue RHS = N->getOperand(1);
893 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
894 RHS = ZExtPromotedInteger(RHS);
895 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
896}
897
898SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
899 // The input value must be properly zero extended.
900 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
901 SDValue RHS = N->getOperand(1);
902 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger)
903 RHS = ZExtPromotedInteger(RHS);
904 return DAG.getNode(ISD::SRL, SDLoc(N), LHS.getValueType(), LHS, RHS);
905}
906
907SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
908 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
909 SDValue Res;
910 SDValue InOp = N->getOperand(0);
911 SDLoc dl(N);
912
913 switch (getTypeAction(InOp.getValueType())) {
914 default: llvm_unreachable("Unknown type action!")::llvm::llvm_unreachable_internal("Unknown type action!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 914)
;
915 case TargetLowering::TypeLegal:
916 case TargetLowering::TypeExpandInteger:
917 Res = InOp;
918 break;
919 case TargetLowering::TypePromoteInteger:
920 Res = GetPromotedInteger(InOp);
921 break;
922 case TargetLowering::TypeSplitVector: {
923 EVT InVT = InOp.getValueType();
924 assert(InVT.isVector() && "Cannot split scalar types")((InVT.isVector() && "Cannot split scalar types") ? static_cast
<void> (0) : __assert_fail ("InVT.isVector() && \"Cannot split scalar types\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 924, __PRETTY_FUNCTION__))
;
925 unsigned NumElts = InVT.getVectorNumElements();
926 assert(NumElts == NVT.getVectorNumElements() &&((NumElts == NVT.getVectorNumElements() && "Dst and Src must have the same number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElts == NVT.getVectorNumElements() && \"Dst and Src must have the same number of elements\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 927, __PRETTY_FUNCTION__))
927 "Dst and Src must have the same number of elements")((NumElts == NVT.getVectorNumElements() && "Dst and Src must have the same number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElts == NVT.getVectorNumElements() && \"Dst and Src must have the same number of elements\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 927, __PRETTY_FUNCTION__))
;
928 assert(isPowerOf2_32(NumElts) &&((isPowerOf2_32(NumElts) && "Promoted vector type must be a power of two"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumElts) && \"Promoted vector type must be a power of two\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 929, __PRETTY_FUNCTION__))
929 "Promoted vector type must be a power of two")((isPowerOf2_32(NumElts) && "Promoted vector type must be a power of two"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumElts) && \"Promoted vector type must be a power of two\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 929, __PRETTY_FUNCTION__))
;
930
931 SDValue EOp1, EOp2;
932 GetSplitVector(InOp, EOp1, EOp2);
933
934 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
935 NumElts/2);
936 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
937 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
938
939 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
940 }
941 case TargetLowering::TypeWidenVector: {
942 SDValue WideInOp = GetWidenedVector(InOp);
943
944 // Truncate widened InOp.
945 unsigned NumElem = WideInOp.getValueType().getVectorNumElements();
946 EVT TruncVT = EVT::getVectorVT(*DAG.getContext(),
947 N->getValueType(0).getScalarType(), NumElem);
948 SDValue WideTrunc = DAG.getNode(ISD::TRUNCATE, dl, TruncVT, WideInOp);
949
950 // Zero extend so that the elements are of same type as those of NVT
951 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(), NVT.getVectorElementType(),
952 NumElem);
953 SDValue WideExt = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, WideTrunc);
954
955 // Extract the low NVT subvector.
956 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
957 SDValue ZeroIdx = DAG.getConstant(0, dl, IdxTy);
958 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx);
959 }
960 }
961
962 // Truncate to NVT instead of VT
963 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
964}
965
966SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
967 if (ResNo == 1)
968 return PromoteIntRes_Overflow(N);
969
970 // The operation overflowed iff the result in the larger type is not the
971 // zero extension of its truncation to the original type.
972 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
973 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
974 EVT OVT = N->getOperand(0).getValueType();
975 EVT NVT = LHS.getValueType();
976 SDLoc dl(N);
977
978 // Do the arithmetic in the larger type.
979 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
980 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
981
982 // Calculate the overflow flag: zero extend the arithmetic result from
983 // the original type.
984 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT.getScalarType());
985 // Overflowed if and only if this is not equal to Res.
986 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
987
988 // Use the calculated overflow everywhere.
989 ReplaceValueWith(SDValue(N, 1), Ofl);
990
991 return Res;
992}
993
994// Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
995// the third operand of ADDE/SUBE nodes is carry flag, which differs from
996// the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
997SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
998 if (ResNo == 1)
999 return PromoteIntRes_Overflow(N);
1000
1001 // We need to sign-extend the operands so the carry value computed by the
1002 // wide operation will be equivalent to the carry value computed by the
1003 // narrow operation.
1004 // An ADDCARRY can generate carry only if any of the operands has its
1005 // most significant bit set. Sign extension propagates the most significant
1006 // bit into the higher bits which means the extra bit that the narrow
1007 // addition would need (i.e. the carry) will be propagated through the higher
1008 // bits of the wide addition.
1009 // A SUBCARRY can generate borrow only if LHS < RHS and this property will be
1010 // preserved by sign extension.
1011 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
1012 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
1013
1014 EVT ValueVTs[] = {LHS.getValueType(), N->getValueType(1)};
1015
1016 // Do the arithmetic in the wide type.
1017 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N), DAG.getVTList(ValueVTs),
1018 LHS, RHS, N->getOperand(2));
1019
1020 // Update the users of the original carry/borrow value.
1021 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
1022
1023 return SDValue(Res.getNode(), 0);
1024}
1025
1026SDValue DAGTypeLegalizer::PromoteIntRes_ABS(SDNode *N) {
1027 SDValue Op0 = SExtPromotedInteger(N->getOperand(0));
1028 return DAG.getNode(ISD::ABS, SDLoc(N), Op0.getValueType(), Op0);
1029}
1030
1031SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
1032 // Promote the overflow bit trivially.
1033 if (ResNo == 1)
1034 return PromoteIntRes_Overflow(N);
1035
1036 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
1037 SDLoc DL(N);
1038 EVT SmallVT = LHS.getValueType();
1039
1040 // To determine if the result overflowed in a larger type, we extend the
1041 // input to the larger type, do the multiply (checking if it overflows),
1042 // then also check the high bits of the result to see if overflow happened
1043 // there.
1044 if (N->getOpcode() == ISD::SMULO) {
1045 LHS = SExtPromotedInteger(LHS);
1046 RHS = SExtPromotedInteger(RHS);
1047 } else {
1048 LHS = ZExtPromotedInteger(LHS);
1049 RHS = ZExtPromotedInteger(RHS);
1050 }
1051 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
1052 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
1053
1054 // Overflow occurred if it occurred in the larger type, or if the high part
1055 // of the result does not zero/sign-extend the low part. Check this second
1056 // possibility first.
1057 SDValue Overflow;
1058 if (N->getOpcode() == ISD::UMULO) {
1059 // Unsigned overflow occurred if the high part is non-zero.
1060 unsigned Shift = SmallVT.getScalarSizeInBits();
1061 EVT ShiftTy = getShiftAmountTyForConstant(Mul.getValueType(), TLI, DAG);
1062 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
1063 DAG.getConstant(Shift, DL, ShiftTy));
1064 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
1065 DAG.getConstant(0, DL, Hi.getValueType()),
1066 ISD::SETNE);
1067 } else {
1068 // Signed overflow occurred if the high part does not sign extend the low.
1069 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
1070 Mul, DAG.getValueType(SmallVT));
1071 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
1072 }
1073
1074 // The only other way for overflow to occur is if the multiplication in the
1075 // larger type itself overflowed.
1076 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
1077 SDValue(Mul.getNode(), 1));
1078
1079 // Use the calculated overflow everywhere.
1080 ReplaceValueWith(SDValue(N, 1), Overflow);
1081 return Mul;
1082}
1083
1084SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
1085 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
1086 N->getValueType(0)));
1087}
1088
1089SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
1090 SDValue Chain = N->getOperand(0); // Get the chain.
1091 SDValue Ptr = N->getOperand(1); // Get the pointer.
1092 EVT VT = N->getValueType(0);
1093 SDLoc dl(N);
1094
1095 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
1096 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
1097 // The argument is passed as NumRegs registers of type RegVT.
1098
1099 SmallVector<SDValue, 8> Parts(NumRegs);
1100 for (unsigned i = 0; i < NumRegs; ++i) {
1101 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
1102 N->getConstantOperandVal(3));
1103 Chain = Parts[i].getValue(1);
1104 }
1105
1106 // Handle endianness of the load.
1107 if (DAG.getDataLayout().isBigEndian())
1108 std::reverse(Parts.begin(), Parts.end());
1109
1110 // Assemble the parts in the promoted type.
1111 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1112 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
1113 for (unsigned i = 1; i < NumRegs; ++i) {
1114 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
1115 // Shift it to the right position and "or" it in.
1116 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
1117 DAG.getConstant(i * RegVT.getSizeInBits(), dl,
1118 TLI.getPointerTy(DAG.getDataLayout())));
1119 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
1120 }
1121
1122 // Modified the chain result - switch anything that used the old chain to
1123 // use the new one.
1124 ReplaceValueWith(SDValue(N, 1), Chain);
1125
1126 return Res;
1127}
1128
1129//===----------------------------------------------------------------------===//
1130// Integer Operand Promotion
1131//===----------------------------------------------------------------------===//
1132
1133/// PromoteIntegerOperand - This method is called when the specified operand of
1134/// the specified node is found to need promotion. At this point, all of the
1135/// result types of the node are known to be legal, but other operands of the
1136/// node may need promotion or expansion as well as the specified one.
1137bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
1138 LLVM_DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1139 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Promote integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1140 SDValue Res = SDValue();
1141
1142 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false)) {
1143 LLVM_DEBUG(dbgs() << "Node has been custom lowered, done\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Node has been custom lowered, done\n"
; } } while (false)
;
1144 return false;
1145 }
1146
1147 switch (N->getOpcode()) {
1148 default:
1149 #ifndef NDEBUG
1150 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
1151 N->dump(&DAG); dbgs() << "\n";
1152 #endif
1153 llvm_unreachable("Do not know how to promote this operator's operand!")::llvm::llvm_unreachable_internal("Do not know how to promote this operator's operand!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1153)
;
1154
1155 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
1156 case ISD::ATOMIC_STORE:
1157 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
1158 break;
1159 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
1160 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
1161 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
1162 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
1163 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
1164 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
1165 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
1166 case ISD::INSERT_VECTOR_ELT:
1167 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
1168 case ISD::SCALAR_TO_VECTOR:
1169 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
1170 case ISD::SPLAT_VECTOR:
1171 Res = PromoteIntOp_SPLAT_VECTOR(N); break;
1172 case ISD::VSELECT:
1173 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1174 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
1175 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
1176 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
1177 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
1178 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
1179 OpNo); break;
1180 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
1181 OpNo); break;
1182 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
1183 OpNo); break;
1184 case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
1185 OpNo); break;
1186 case ISD::MSCATTER: Res = PromoteIntOp_MSCATTER(cast<MaskedScatterSDNode>(N),
1187 OpNo); break;
1188 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
1189 case ISD::FP16_TO_FP:
1190 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
1191 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
1192 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break;
1193
1194 case ISD::SHL:
1195 case ISD::SRA:
1196 case ISD::SRL:
1197 case ISD::ROTL:
1198 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
1199
1200 case ISD::ADDCARRY:
1201 case ISD::SUBCARRY: Res = PromoteIntOp_ADDSUBCARRY(N, OpNo); break;
1202
1203 case ISD::FRAMEADDR:
1204 case ISD::RETURNADDR: Res = PromoteIntOp_FRAMERETURNADDR(N); break;
1205
1206 case ISD::PREFETCH: Res = PromoteIntOp_PREFETCH(N, OpNo); break;
1207
1208 case ISD::SMULFIX:
1209 case ISD::SMULFIXSAT:
1210 case ISD::UMULFIX:
1211 case ISD::UMULFIXSAT: Res = PromoteIntOp_MULFIX(N); break;
1212
1213 case ISD::FPOWI: Res = PromoteIntOp_FPOWI(N); break;
1214
1215 case ISD::VECREDUCE_ADD:
1216 case ISD::VECREDUCE_MUL:
1217 case ISD::VECREDUCE_AND:
1218 case ISD::VECREDUCE_OR:
1219 case ISD::VECREDUCE_XOR:
1220 case ISD::VECREDUCE_SMAX:
1221 case ISD::VECREDUCE_SMIN:
1222 case ISD::VECREDUCE_UMAX:
1223 case ISD::VECREDUCE_UMIN: Res = PromoteIntOp_VECREDUCE(N); break;
1224 }
1225
1226 // If the result is null, the sub-method took care of registering results etc.
1227 if (!Res.getNode()) return false;
1228
1229 // If the result is N, the sub-method updated N in place. Tell the legalizer
1230 // core about this.
1231 if (Res.getNode() == N)
1232 return true;
1233
1234 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1235, __PRETTY_FUNCTION__))
1235 "Invalid operand expansion")((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1235, __PRETTY_FUNCTION__))
;
1236
1237 ReplaceValueWith(SDValue(N, 0), Res);
1238 return false;
1239}
1240
1241/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1242/// shared among BR_CC, SELECT_CC, and SETCC handlers.
1243void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
1244 ISD::CondCode CCCode) {
1245 // We have to insert explicit sign or zero extends. Note that we could
1246 // insert sign extends for ALL conditions. For those operations where either
1247 // zero or sign extension would be valid, use SExtOrZExtPromotedInteger
1248 // which will choose the cheapest for the target.
1249 switch (CCCode) {
1250 default: llvm_unreachable("Unknown integer comparison!")::llvm::llvm_unreachable_internal("Unknown integer comparison!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1250)
;
1251 case ISD::SETEQ:
1252 case ISD::SETNE: {
1253 SDValue OpL = GetPromotedInteger(NewLHS);
1254 SDValue OpR = GetPromotedInteger(NewRHS);
1255
1256 // We would prefer to promote the comparison operand with sign extension.
1257 // If the width of OpL/OpR excluding the duplicated sign bits is no greater
1258 // than the width of NewLHS/NewRH, we can avoid inserting real truncate
1259 // instruction, which is redundant eventually.
1260 unsigned OpLEffectiveBits =
1261 OpL.getScalarValueSizeInBits() - DAG.ComputeNumSignBits(OpL) + 1;
1262 unsigned OpREffectiveBits =
1263 OpR.getScalarValueSizeInBits() - DAG.ComputeNumSignBits(OpR) + 1;
1264 if (OpLEffectiveBits <= NewLHS.getScalarValueSizeInBits() &&
1265 OpREffectiveBits <= NewRHS.getScalarValueSizeInBits()) {
1266 NewLHS = OpL;
1267 NewRHS = OpR;
1268 } else {
1269 NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1270 NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1271 }
1272 break;
1273 }
1274 case ISD::SETUGE:
1275 case ISD::SETUGT:
1276 case ISD::SETULE:
1277 case ISD::SETULT:
1278 NewLHS = SExtOrZExtPromotedInteger(NewLHS);
1279 NewRHS = SExtOrZExtPromotedInteger(NewRHS);
1280 break;
1281 case ISD::SETGE:
1282 case ISD::SETGT:
1283 case ISD::SETLT:
1284 case ISD::SETLE:
1285 NewLHS = SExtPromotedInteger(NewLHS);
1286 NewRHS = SExtPromotedInteger(NewRHS);
1287 break;
1288 }
1289}
1290
1291SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
1292 SDValue Op = GetPromotedInteger(N->getOperand(0));
1293 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
1294}
1295
1296SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
1297 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
1298 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
1299 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand());
1300}
1301
1302SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
1303 // This should only occur in unusual situations like bitcasting to an
1304 // x86_fp80, so just turn it into a store+load
1305 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
1306}
1307
1308SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
1309 assert(OpNo == 2 && "Don't know how to promote this operand!")((OpNo == 2 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 2 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1309, __PRETTY_FUNCTION__))
;
1310
1311 SDValue LHS = N->getOperand(2);
1312 SDValue RHS = N->getOperand(3);
1313 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
1314
1315 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
1316 // legal types.
1317 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1318 N->getOperand(1), LHS, RHS, N->getOperand(4)),
1319 0);
1320}
1321
1322SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
1323 assert(OpNo == 1 && "only know how to promote condition")((OpNo == 1 && "only know how to promote condition") ?
static_cast<void> (0) : __assert_fail ("OpNo == 1 && \"only know how to promote condition\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1323, __PRETTY_FUNCTION__))
;
1324
1325 // Promote all the way up to the canonical SetCC type.
1326 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
1327
1328 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
1329 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
1330 N->getOperand(2)), 0);
1331}
1332
1333SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
1334 // Since the result type is legal, the operands must promote to it.
1335 EVT OVT = N->getOperand(0).getValueType();
1336 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
1337 SDValue Hi = GetPromotedInteger(N->getOperand(1));
1338 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?")((Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Lo.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1338, __PRETTY_FUNCTION__))
;
1339 SDLoc dl(N);
1340
1341 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
1342 DAG.getConstant(OVT.getSizeInBits(), dl,
1343 TLI.getPointerTy(DAG.getDataLayout())));
1344 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1345}
1346
1347SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1348 // The vector type is legal but the element type is not. This implies
1349 // that the vector is a power-of-two in length and that the element
1350 // type does not have a strange size (eg: it is not i1).
1351 EVT VecVT = N->getValueType(0);
1352 unsigned NumElts = VecVT.getVectorNumElements();
1353 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&((!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
"Legal vector of one illegal element?") ? static_cast<void
> (0) : __assert_fail ("!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && \"Legal vector of one illegal element?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1354, __PRETTY_FUNCTION__))
1354 "Legal vector of one illegal element?")((!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
"Legal vector of one illegal element?") ? static_cast<void
> (0) : __assert_fail ("!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) && \"Legal vector of one illegal element?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1354, __PRETTY_FUNCTION__))
;
1355
1356 // Promote the inserted value. The type does not need to match the
1357 // vector element type. Check that any extra bits introduced will be
1358 // truncated away.
1359 assert(N->getOperand(0).getValueSizeInBits() >=((N->getOperand(0).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1361, __PRETTY_FUNCTION__))
1360 N->getValueType(0).getScalarSizeInBits() &&((N->getOperand(0).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1361, __PRETTY_FUNCTION__))
1361 "Type of inserted value narrower than vector element type!")((N->getOperand(0).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(0).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1361, __PRETTY_FUNCTION__))
;
1362
1363 SmallVector<SDValue, 16> NewOps;
1364 for (unsigned i = 0; i < NumElts; ++i)
1365 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1366
1367 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1368}
1369
1370SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1371 unsigned OpNo) {
1372 if (OpNo == 1) {
1373 // Promote the inserted value. This is valid because the type does not
1374 // have to match the vector element type.
1375
1376 // Check that any extra bits introduced will be truncated away.
1377 assert(N->getOperand(1).getValueSizeInBits() >=((N->getOperand(1).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1379, __PRETTY_FUNCTION__))
1378 N->getValueType(0).getScalarSizeInBits() &&((N->getOperand(1).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1379, __PRETTY_FUNCTION__))
1379 "Type of inserted value narrower than vector element type!")((N->getOperand(1).getValueSizeInBits() >= N->getValueType
(0).getScalarSizeInBits() && "Type of inserted value narrower than vector element type!"
) ? static_cast<void> (0) : __assert_fail ("N->getOperand(1).getValueSizeInBits() >= N->getValueType(0).getScalarSizeInBits() && \"Type of inserted value narrower than vector element type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1379, __PRETTY_FUNCTION__))
;
1380 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1381 GetPromotedInteger(N->getOperand(1)),
1382 N->getOperand(2)),
1383 0);
1384 }
1385
1386 assert(OpNo == 2 && "Different operand and result vector types?")((OpNo == 2 && "Different operand and result vector types?"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 2 && \"Different operand and result vector types?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1386, __PRETTY_FUNCTION__))
;
1387
1388 // Promote the index.
1389 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1390 TLI.getVectorIdxTy(DAG.getDataLayout()));
1391 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1392 N->getOperand(1), Idx), 0);
1393}
1394
1395SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1396 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1397 // the operand in place.
1398 return SDValue(DAG.UpdateNodeOperands(N,
1399 GetPromotedInteger(N->getOperand(0))), 0);
1400}
1401
1402SDValue DAGTypeLegalizer::PromoteIntOp_SPLAT_VECTOR(SDNode *N) {
1403 // Integer SPLAT_VECTOR operands are implicitly truncated, so just promote the
1404 // operand in place.
1405 return SDValue(
1406 DAG.UpdateNodeOperands(N, GetPromotedInteger(N->getOperand(0))), 0);
1407}
1408
1409SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1410 assert(OpNo == 0 && "Only know how to promote the condition!")((OpNo == 0 && "Only know how to promote the condition!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 0 && \"Only know how to promote the condition!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1410, __PRETTY_FUNCTION__))
;
1411 SDValue Cond = N->getOperand(0);
1412 EVT OpTy = N->getOperand(1).getValueType();
1413
1414 if (N->getOpcode() == ISD::VSELECT)
1415 if (SDValue Res = WidenVSELECTAndMask(N))
1416 return Res;
1417
1418 // Promote all the way up to the canonical SetCC type.
1419 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1420 Cond = PromoteTargetBoolean(Cond, OpVT);
1421
1422 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1423 N->getOperand(2)), 0);
1424}
1425
1426SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1427 assert(OpNo == 0 && "Don't know how to promote this operand!")((OpNo == 0 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 0 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1427, __PRETTY_FUNCTION__))
;
1428
1429 SDValue LHS = N->getOperand(0);
1430 SDValue RHS = N->getOperand(1);
1431 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1432
1433 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1434 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1435 N->getOperand(3), N->getOperand(4)), 0);
1436}
1437
1438SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1439 assert(OpNo == 0 && "Don't know how to promote this operand!")((OpNo == 0 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 0 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1439, __PRETTY_FUNCTION__))
;
1440
1441 SDValue LHS = N->getOperand(0);
1442 SDValue RHS = N->getOperand(1);
1443 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1444
1445 // The CC (#2) is always legal.
1446 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1447}
1448
1449SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1450 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1451 ZExtPromotedInteger(N->getOperand(1))), 0);
1452}
1453
1454SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1455 SDValue Op = GetPromotedInteger(N->getOperand(0));
1456 SDLoc dl(N);
1457 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1458 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1459 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1460}
1461
1462SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1463 return SDValue(DAG.UpdateNodeOperands(N,
1464 SExtPromotedInteger(N->getOperand(0))), 0);
1465}
1466
1467SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1468 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!")((ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDStore(N) && \"Indexed store during type legalization!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1468, __PRETTY_FUNCTION__))
;
1469 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1470 SDLoc dl(N);
1471
1472 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1473
1474 // Truncate the value and store the result.
1475 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1476 N->getMemoryVT(), N->getMemOperand());
1477}
1478
1479SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
1480 unsigned OpNo) {
1481
1482 SDValue DataOp = N->getValue();
1483 EVT DataVT = DataOp.getValueType();
1484 SDValue Mask = N->getMask();
1485 SDLoc dl(N);
1486
1487 bool TruncateStore = false;
1488 if (OpNo == 3) {
1489 Mask = PromoteTargetBoolean(Mask, DataVT);
1490 // Update in place.
1491 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1492 NewOps[3] = Mask;
1493 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1494 } else { // Data operand
1495 assert(OpNo == 1 && "Unexpected operand for promotion")((OpNo == 1 && "Unexpected operand for promotion") ? static_cast
<void> (0) : __assert_fail ("OpNo == 1 && \"Unexpected operand for promotion\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1495, __PRETTY_FUNCTION__))
;
1496 DataOp = GetPromotedInteger(DataOp);
1497 TruncateStore = true;
1498 }
1499
1500 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1501 N->getMemoryVT(), N->getMemOperand(),
1502 TruncateStore, N->isCompressingStore());
1503}
1504
1505SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N,
1506 unsigned OpNo) {
1507 assert(OpNo == 2 && "Only know how to promote the mask!")((OpNo == 2 && "Only know how to promote the mask!") ?
static_cast<void> (0) : __assert_fail ("OpNo == 2 && \"Only know how to promote the mask!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1507, __PRETTY_FUNCTION__))
;
1508 EVT DataVT = N->getValueType(0);
1509 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1510 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1511 NewOps[OpNo] = Mask;
1512 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1513}
1514
1515SDValue DAGTypeLegalizer::PromoteIntOp_MGATHER(MaskedGatherSDNode *N,
1516 unsigned OpNo) {
1517
1518 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1519 if (OpNo == 2) {
1520 // The Mask
1521 EVT DataVT = N->getValueType(0);
1522 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1523 } else if (OpNo == 4) {
1524 // The Index
1525 if (N->isIndexSigned())
1526 // Need to sign extend the index since the bits will likely be used.
1527 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1528 else
1529 NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
1530 } else
1531 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1532
1533 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1534}
1535
1536SDValue DAGTypeLegalizer::PromoteIntOp_MSCATTER(MaskedScatterSDNode *N,
1537 unsigned OpNo) {
1538 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
1539 if (OpNo == 2) {
1540 // The Mask
1541 EVT DataVT = N->getValue().getValueType();
1542 NewOps[OpNo] = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1543 } else if (OpNo == 4) {
1544 // The Index
1545 if (N->isIndexSigned())
1546 // Need to sign extend the index since the bits will likely be used.
1547 NewOps[OpNo] = SExtPromotedInteger(N->getOperand(OpNo));
1548 else
1549 NewOps[OpNo] = ZExtPromotedInteger(N->getOperand(OpNo));
1550 } else
1551 NewOps[OpNo] = GetPromotedInteger(N->getOperand(OpNo));
1552 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1553}
1554
1555SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1556 SDValue Op = GetPromotedInteger(N->getOperand(0));
1557 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1558}
1559
1560SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1561 return SDValue(DAG.UpdateNodeOperands(N,
1562 ZExtPromotedInteger(N->getOperand(0))), 0);
1563}
1564
1565SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1566 SDLoc dl(N);
1567 SDValue Op = GetPromotedInteger(N->getOperand(0));
1568 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1569 return DAG.getZeroExtendInReg(Op, dl,
1570 N->getOperand(0).getValueType().getScalarType());
1571}
1572
1573SDValue DAGTypeLegalizer::PromoteIntOp_ADDSUBCARRY(SDNode *N, unsigned OpNo) {
1574 assert(OpNo == 2 && "Don't know how to promote this operand!")((OpNo == 2 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 2 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1574, __PRETTY_FUNCTION__))
;
1575
1576 SDValue LHS = N->getOperand(0);
1577 SDValue RHS = N->getOperand(1);
1578 SDValue Carry = N->getOperand(2);
1579 SDLoc DL(N);
1580
1581 Carry = PromoteTargetBoolean(Carry, LHS.getValueType());
1582
1583 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, Carry), 0);
1584}
1585
1586SDValue DAGTypeLegalizer::PromoteIntOp_MULFIX(SDNode *N) {
1587 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
1588 return SDValue(
1589 DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1), Op2), 0);
1590}
1591
1592SDValue DAGTypeLegalizer::PromoteIntOp_FRAMERETURNADDR(SDNode *N) {
1593 // Promote the RETURNADDR/FRAMEADDR argument to a supported integer width.
1594 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
1595 return SDValue(DAG.UpdateNodeOperands(N, Op), 0);
1596}
1597
1598SDValue DAGTypeLegalizer::PromoteIntOp_PREFETCH(SDNode *N, unsigned OpNo) {
1599 assert(OpNo > 1 && "Don't know how to promote this operand!")((OpNo > 1 && "Don't know how to promote this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo > 1 && \"Don't know how to promote this operand!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1599, __PRETTY_FUNCTION__))
;
1600 // Promote the rw, locality, and cache type arguments to a supported integer
1601 // width.
1602 SDValue Op2 = ZExtPromotedInteger(N->getOperand(2));
1603 SDValue Op3 = ZExtPromotedInteger(N->getOperand(3));
1604 SDValue Op4 = ZExtPromotedInteger(N->getOperand(4));
1605 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), N->getOperand(1),
1606 Op2, Op3, Op4),
1607 0);
1608}
1609
1610SDValue DAGTypeLegalizer::PromoteIntOp_FPOWI(SDNode *N) {
1611 SDValue Op = SExtPromotedInteger(N->getOperand(1));
1612 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Op), 0);
1613}
1614
1615SDValue DAGTypeLegalizer::PromoteIntOp_VECREDUCE(SDNode *N) {
1616 SDLoc dl(N);
1617 SDValue Op;
1618 switch (N->getOpcode()) {
1619 default: llvm_unreachable("Expected integer vector reduction")::llvm::llvm_unreachable_internal("Expected integer vector reduction"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1619)
;
1620 case ISD::VECREDUCE_ADD:
1621 case ISD::VECREDUCE_MUL:
1622 case ISD::VECREDUCE_AND:
1623 case ISD::VECREDUCE_OR:
1624 case ISD::VECREDUCE_XOR:
1625 Op = GetPromotedInteger(N->getOperand(0));
1626 break;
1627 case ISD::VECREDUCE_SMAX:
1628 case ISD::VECREDUCE_SMIN:
1629 Op = SExtPromotedInteger(N->getOperand(0));
1630 break;
1631 case ISD::VECREDUCE_UMAX:
1632 case ISD::VECREDUCE_UMIN:
1633 Op = ZExtPromotedInteger(N->getOperand(0));
1634 break;
1635 }
1636
1637 EVT EltVT = Op.getValueType().getVectorElementType();
1638 EVT VT = N->getValueType(0);
1639 if (VT.bitsGE(EltVT))
1640 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, Op);
1641
1642 // Result size must be >= element size. If this is not the case after
1643 // promotion, also promote the result type and then truncate.
1644 SDValue Reduce = DAG.getNode(N->getOpcode(), dl, EltVT, Op);
1645 return DAG.getNode(ISD::TRUNCATE, dl, VT, Reduce);
1646}
1647
1648//===----------------------------------------------------------------------===//
1649// Integer Result Expansion
1650//===----------------------------------------------------------------------===//
1651
1652/// ExpandIntegerResult - This method is called when the specified result of the
1653/// specified node is found to need expansion. At this point, the node may also
1654/// have invalid operands or may have other results that need promotion, we just
1655/// know that (at least) one result needs expansion.
1656void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1657 LLVM_DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1
Assuming 'DebugFlag' is false
2
Loop condition is false. Exiting loop
1658 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer result: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1659 SDValue Lo, Hi;
1660 Lo = Hi = SDValue();
1661
1662 // See if the target wants to custom expand this node.
1663 if (CustomLowerNode(N, N->getValueType(ResNo), true))
3
Assuming the condition is false
4
Taking false branch
1664 return;
1665
1666 switch (N->getOpcode()) {
5
Control jumps to 'case SRL:' at line 1777
1667 default:
1668#ifndef NDEBUG
1669 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1670 N->dump(&DAG); dbgs() << "\n";
1671#endif
1672 report_fatal_error("Do not know how to expand the result of this "
1673 "operator!");
1674
1675 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1676 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1677 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1678 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1679
1680 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1681 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1682 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1683 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1684 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1685
1686 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1687 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1688 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1689 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break;
1690 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1691 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1692 case ISD::ABS: ExpandIntRes_ABS(N, Lo, Hi); break;
1693 case ISD::CTLZ_ZERO_UNDEF:
1694 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1695 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1696 case ISD::CTTZ_ZERO_UNDEF:
1697 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1698 case ISD::FLT_ROUNDS_: ExpandIntRes_FLT_ROUNDS(N, Lo, Hi); break;
1699 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1700 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1701 case ISD::LLROUND: ExpandIntRes_LLROUND(N, Lo, Hi); break;
1702 case ISD::LLRINT: ExpandIntRes_LLRINT(N, Lo, Hi); break;
1703 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1704 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1705 case ISD::READCYCLECOUNTER: ExpandIntRes_READCYCLECOUNTER(N, Lo, Hi); break;
1706 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1707 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1708 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1709 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1710 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1711 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1712 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1713 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1714 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1715
1716 case ISD::ATOMIC_LOAD_ADD:
1717 case ISD::ATOMIC_LOAD_SUB:
1718 case ISD::ATOMIC_LOAD_AND:
1719 case ISD::ATOMIC_LOAD_CLR:
1720 case ISD::ATOMIC_LOAD_OR:
1721 case ISD::ATOMIC_LOAD_XOR:
1722 case ISD::ATOMIC_LOAD_NAND:
1723 case ISD::ATOMIC_LOAD_MIN:
1724 case ISD::ATOMIC_LOAD_MAX:
1725 case ISD::ATOMIC_LOAD_UMIN:
1726 case ISD::ATOMIC_LOAD_UMAX:
1727 case ISD::ATOMIC_SWAP:
1728 case ISD::ATOMIC_CMP_SWAP: {
1729 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1730 SplitInteger(Tmp.first, Lo, Hi);
1731 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1732 break;
1733 }
1734 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1735 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1736 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1737 SDValue Tmp = DAG.getAtomicCmpSwap(
1738 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1739 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1740 AN->getMemOperand());
1741
1742 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1743 // success simply by comparing the loaded value against the ingoing
1744 // comparison.
1745 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1746 N->getOperand(2), ISD::SETEQ);
1747
1748 SplitInteger(Tmp, Lo, Hi);
1749 ReplaceValueWith(SDValue(N, 1), Success);
1750 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1751 break;
1752 }
1753
1754 case ISD::AND:
1755 case ISD::OR:
1756 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1757
1758 case ISD::UMAX:
1759 case ISD::SMAX:
1760 case ISD::UMIN:
1761 case ISD::SMIN: ExpandIntRes_MINMAX(N, Lo, Hi); break;
1762
1763 case ISD::ADD:
1764 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1765
1766 case ISD::ADDC:
1767 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1768
1769 case ISD::ADDE:
1770 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1771
1772 case ISD::ADDCARRY:
1773 case ISD::SUBCARRY: ExpandIntRes_ADDSUBCARRY(N, Lo, Hi); break;
1774
1775 case ISD::SHL:
1776 case ISD::SRA:
1777 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
6
Calling 'DAGTypeLegalizer::ExpandIntRes_Shift'
1778
1779 case ISD::SADDO:
1780 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1781 case ISD::UADDO:
1782 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1783 case ISD::UMULO:
1784 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1785
1786 case ISD::SADDSAT:
1787 case ISD::UADDSAT:
1788 case ISD::SSUBSAT:
1789 case ISD::USUBSAT: ExpandIntRes_ADDSUBSAT(N, Lo, Hi); break;
1790
1791 case ISD::SMULFIX:
1792 case ISD::SMULFIXSAT:
1793 case ISD::UMULFIX:
1794 case ISD::UMULFIXSAT: ExpandIntRes_MULFIX(N, Lo, Hi); break;
1795
1796 case ISD::VECREDUCE_ADD:
1797 case ISD::VECREDUCE_MUL:
1798 case ISD::VECREDUCE_AND:
1799 case ISD::VECREDUCE_OR:
1800 case ISD::VECREDUCE_XOR:
1801 case ISD::VECREDUCE_SMAX:
1802 case ISD::VECREDUCE_SMIN:
1803 case ISD::VECREDUCE_UMAX:
1804 case ISD::VECREDUCE_UMIN: ExpandIntRes_VECREDUCE(N, Lo, Hi); break;
1805 }
1806
1807 // If Lo/Hi is null, the sub-method took care of registering results etc.
1808 if (Lo.getNode())
1809 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1810}
1811
1812/// Lower an atomic node to the appropriate builtin call.
1813std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1814 unsigned Opc = Node->getOpcode();
1815 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1816 RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
1817 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected atomic op or value type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1817, __PRETTY_FUNCTION__))
;
1818
1819 return ExpandChainLibCall(LC, Node, false);
1820}
1821
1822/// N is a shift by a value that needs to be expanded,
1823/// and the shift amount is a constant 'Amt'. Expand the operation.
1824void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
1825 SDValue &Lo, SDValue &Hi) {
1826 SDLoc DL(N);
1827 // Expand the incoming operand to be shifted, so that we have its parts
1828 SDValue InL, InH;
1829 GetExpandedInteger(N->getOperand(0), InL, InH);
1830
1831 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1832 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1833 if (!Amt) {
1834 Lo = InL;
1835 Hi = InH;
1836 return;
1837 }
1838
1839 EVT NVT = InL.getValueType();
1840 unsigned VTBits = N->getValueType(0).getSizeInBits();
1841 unsigned NVTBits = NVT.getSizeInBits();
1842 EVT ShTy = N->getOperand(1).getValueType();
1843
1844 if (N->getOpcode() == ISD::SHL) {
1845 if (Amt.ugt(VTBits)) {
1846 Lo = Hi = DAG.getConstant(0, DL, NVT);
1847 } else if (Amt.ugt(NVTBits)) {
1848 Lo = DAG.getConstant(0, DL, NVT);
1849 Hi = DAG.getNode(ISD::SHL, DL,
1850 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1851 } else if (Amt == NVTBits) {
1852 Lo = DAG.getConstant(0, DL, NVT);
1853 Hi = InL;
1854 } else {
1855 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1856 Hi = DAG.getNode(ISD::OR, DL, NVT,
1857 DAG.getNode(ISD::SHL, DL, NVT, InH,
1858 DAG.getConstant(Amt, DL, ShTy)),
1859 DAG.getNode(ISD::SRL, DL, NVT, InL,
1860 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1861 }
1862 return;
1863 }
1864
1865 if (N->getOpcode() == ISD::SRL) {
1866 if (Amt.ugt(VTBits)) {
1867 Lo = Hi = DAG.getConstant(0, DL, NVT);
1868 } else if (Amt.ugt(NVTBits)) {
1869 Lo = DAG.getNode(ISD::SRL, DL,
1870 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1871 Hi = DAG.getConstant(0, DL, NVT);
1872 } else if (Amt == NVTBits) {
1873 Lo = InH;
1874 Hi = DAG.getConstant(0, DL, NVT);
1875 } else {
1876 Lo = DAG.getNode(ISD::OR, DL, NVT,
1877 DAG.getNode(ISD::SRL, DL, NVT, InL,
1878 DAG.getConstant(Amt, DL, ShTy)),
1879 DAG.getNode(ISD::SHL, DL, NVT, InH,
1880 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1881 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1882 }
1883 return;
1884 }
1885
1886 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")((N->getOpcode() == ISD::SRA && "Unknown shift!") ?
static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1886, __PRETTY_FUNCTION__))
;
1887 if (Amt.ugt(VTBits)) {
1888 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1889 DAG.getConstant(NVTBits - 1, DL, ShTy));
1890 } else if (Amt.ugt(NVTBits)) {
1891 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1892 DAG.getConstant(Amt - NVTBits, DL, ShTy));
1893 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1894 DAG.getConstant(NVTBits - 1, DL, ShTy));
1895 } else if (Amt == NVTBits) {
1896 Lo = InH;
1897 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1898 DAG.getConstant(NVTBits - 1, DL, ShTy));
1899 } else {
1900 Lo = DAG.getNode(ISD::OR, DL, NVT,
1901 DAG.getNode(ISD::SRL, DL, NVT, InL,
1902 DAG.getConstant(Amt, DL, ShTy)),
1903 DAG.getNode(ISD::SHL, DL, NVT, InH,
1904 DAG.getConstant(-Amt + NVTBits, DL, ShTy)));
1905 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1906 }
1907}
1908
1909/// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1910/// this shift based on knowledge of the high bit of the shift amount. If we
1911/// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1912/// shift amount.
1913bool DAGTypeLegalizer::
1914ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1915 SDValue Amt = N->getOperand(1);
10
Value assigned to 'Amt.Node'
1916 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1917 EVT ShTy = Amt.getValueType();
11
Calling 'SDValue::getValueType'
1918 unsigned ShBits = ShTy.getScalarSizeInBits();
1919 unsigned NVTBits = NVT.getScalarSizeInBits();
1920 assert(isPowerOf2_32(NVTBits) &&((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1921, __PRETTY_FUNCTION__))
1921 "Expanded integer type size not a power of two!")((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1921, __PRETTY_FUNCTION__))
;
1922 SDLoc dl(N);
1923
1924 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1925 KnownBits Known = DAG.computeKnownBits(N->getOperand(1));
1926
1927 // If we don't know anything about the high bits, exit.
1928 if (((Known.Zero|Known.One) & HighBitMask) == 0)
1929 return false;
1930
1931 // Get the incoming operand to be shifted.
1932 SDValue InL, InH;
1933 GetExpandedInteger(N->getOperand(0), InL, InH);
1934
1935 // If we know that any of the high bits of the shift amount are one, then we
1936 // can do this as a couple of simple shifts.
1937 if (Known.One.intersects(HighBitMask)) {
1938 // Mask out the high bit, which we know is set.
1939 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1940 DAG.getConstant(~HighBitMask, dl, ShTy));
1941
1942 switch (N->getOpcode()) {
1943 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1943)
;
1944 case ISD::SHL:
1945 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
1946 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1947 return true;
1948 case ISD::SRL:
1949 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1950 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1951 return true;
1952 case ISD::SRA:
1953 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1954 DAG.getConstant(NVTBits - 1, dl, ShTy));
1955 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1956 return true;
1957 }
1958 }
1959
1960 // If we know that all of the high bits of the shift amount are zero, then we
1961 // can do this as a couple of simple shifts.
1962 if (HighBitMask.isSubsetOf(Known.Zero)) {
1963 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1964 // shift if x is zero. We can use XOR here because x is known to be smaller
1965 // than 32.
1966 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1967 DAG.getConstant(NVTBits - 1, dl, ShTy));
1968
1969 unsigned Op1, Op2;
1970 switch (N->getOpcode()) {
1971 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 1971)
;
1972 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1973 case ISD::SRL:
1974 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1975 }
1976
1977 // When shifting right the arithmetic for Lo and Hi is swapped.
1978 if (N->getOpcode() != ISD::SHL)
1979 std::swap(InL, InH);
1980
1981 // Use a little trick to get the bits that move from Lo to Hi. First
1982 // shift by one bit.
1983 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
1984 // Then compute the remaining shift with amount-1.
1985 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1986
1987 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1988 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1989
1990 if (N->getOpcode() != ISD::SHL)
1991 std::swap(Hi, Lo);
1992 return true;
1993 }
1994
1995 return false;
1996}
1997
1998/// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1999/// of any size.
2000bool DAGTypeLegalizer::
2001ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
2002 SDValue Amt = N->getOperand(1);
2003 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2004 EVT ShTy = Amt.getValueType();
2005 unsigned NVTBits = NVT.getSizeInBits();
2006 assert(isPowerOf2_32(NVTBits) &&((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2007, __PRETTY_FUNCTION__))
2007 "Expanded integer type size not a power of two!")((isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NVTBits) && \"Expanded integer type size not a power of two!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2007, __PRETTY_FUNCTION__))
;
2008 SDLoc dl(N);
2009
2010 // Get the incoming operand to be shifted.
2011 SDValue InL, InH;
2012 GetExpandedInteger(N->getOperand(0), InL, InH);
2013
2014 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
2015 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
2016 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
2017 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2018 Amt, NVBitsNode, ISD::SETULT);
2019 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
2020 Amt, DAG.getConstant(0, dl, ShTy),
2021 ISD::SETEQ);
2022
2023 SDValue LoS, HiS, LoL, HiL;
2024 switch (N->getOpcode()) {
2025 default: llvm_unreachable("Unknown shift")::llvm::llvm_unreachable_internal("Unknown shift", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2025)
;
2026 case ISD::SHL:
2027 // Short: ShAmt < NVTBits
2028 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
2029 HiS = DAG.getNode(ISD::OR, dl, NVT,
2030 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
2031 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
2032
2033 // Long: ShAmt >= NVTBits
2034 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
2035 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
2036
2037 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
2038 Hi = DAG.getSelect(dl, NVT, isZero, InH,
2039 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
2040 return true;
2041 case ISD::SRL:
2042 // Short: ShAmt < NVTBits
2043 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
2044 LoS = DAG.getNode(ISD::OR, dl, NVT,
2045 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2046 // FIXME: If Amt is zero, the following shift generates an undefined result
2047 // on some architectures.
2048 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2049
2050 // Long: ShAmt >= NVTBits
2051 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
2052 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2053
2054 Lo = DAG.getSelect(dl, NVT, isZero, InL,
2055 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2056 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2057 return true;
2058 case ISD::SRA:
2059 // Short: ShAmt < NVTBits
2060 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
2061 LoS = DAG.getNode(ISD::OR, dl, NVT,
2062 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
2063 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
2064
2065 // Long: ShAmt >= NVTBits
2066 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
2067 DAG.getConstant(NVTBits - 1, dl, ShTy));
2068 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
2069
2070 Lo = DAG.getSelect(dl, NVT, isZero, InL,
2071 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
2072 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
2073 return true;
2074 }
2075}
2076
2077static std::pair<ISD::CondCode, ISD::NodeType> getExpandedMinMaxOps(int Op) {
2078
2079 switch (Op) {
2080 default: llvm_unreachable("invalid min/max opcode")::llvm::llvm_unreachable_internal("invalid min/max opcode", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2080)
;
2081 case ISD::SMAX:
2082 return std::make_pair(ISD::SETGT, ISD::UMAX);
2083 case ISD::UMAX:
2084 return std::make_pair(ISD::SETUGT, ISD::UMAX);
2085 case ISD::SMIN:
2086 return std::make_pair(ISD::SETLT, ISD::UMIN);
2087 case ISD::UMIN:
2088 return std::make_pair(ISD::SETULT, ISD::UMIN);
2089 }
2090}
2091
2092void DAGTypeLegalizer::ExpandIntRes_MINMAX(SDNode *N,
2093 SDValue &Lo, SDValue &Hi) {
2094 SDLoc DL(N);
2095 ISD::NodeType LoOpc;
2096 ISD::CondCode CondC;
2097 std::tie(CondC, LoOpc) = getExpandedMinMaxOps(N->getOpcode());
2098
2099 // Expand the subcomponents.
2100 SDValue LHSL, LHSH, RHSL, RHSH;
2101 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2102 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2103
2104 // Value types
2105 EVT NVT = LHSL.getValueType();
2106 EVT CCT = getSetCCResultType(NVT);
2107
2108 // Hi part is always the same op
2109 Hi = DAG.getNode(N->getOpcode(), DL, NVT, {LHSH, RHSH});
2110
2111 // We need to know whether to select Lo part that corresponds to 'winning'
2112 // Hi part or if Hi parts are equal.
2113 SDValue IsHiLeft = DAG.getSetCC(DL, CCT, LHSH, RHSH, CondC);
2114 SDValue IsHiEq = DAG.getSetCC(DL, CCT, LHSH, RHSH, ISD::SETEQ);
2115
2116 // Lo part corresponding to the 'winning' Hi part
2117 SDValue LoCmp = DAG.getSelect(DL, NVT, IsHiLeft, LHSL, RHSL);
2118
2119 // Recursed Lo part if Hi parts are equal, this uses unsigned version
2120 SDValue LoMinMax = DAG.getNode(LoOpc, DL, NVT, {LHSL, RHSL});
2121
2122 Lo = DAG.getSelect(DL, NVT, IsHiEq, LoMinMax, LoCmp);
2123}
2124
2125void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
2126 SDValue &Lo, SDValue &Hi) {
2127 SDLoc dl(N);
2128 // Expand the subcomponents.
2129 SDValue LHSL, LHSH, RHSL, RHSH;
2130 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2131 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2132
2133 EVT NVT = LHSL.getValueType();
2134 SDValue LoOps[2] = { LHSL, RHSL };
2135 SDValue HiOps[3] = { LHSH, RHSH };
2136
2137 bool HasOpCarry = TLI.isOperationLegalOrCustom(
2138 N->getOpcode() == ISD::ADD ? ISD::ADDCARRY : ISD::SUBCARRY,
2139 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2140 if (HasOpCarry) {
2141 SDVTList VTList = DAG.getVTList(NVT, getSetCCResultType(NVT));
2142 if (N->getOpcode() == ISD::ADD) {
2143 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2144 HiOps[2] = Lo.getValue(1);
2145 Hi = DAG.getNode(ISD::ADDCARRY, dl, VTList, HiOps);
2146 } else {
2147 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2148 HiOps[2] = Lo.getValue(1);
2149 Hi = DAG.getNode(ISD::SUBCARRY, dl, VTList, HiOps);
2150 }
2151 return;
2152 }
2153
2154 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
2155 // them. TODO: Teach operation legalization how to expand unsupported
2156 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
2157 // a carry of type MVT::Glue, but there doesn't seem to be any way to
2158 // generate a value of this type in the expanded code sequence.
2159 bool hasCarry =
2160 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2161 ISD::ADDC : ISD::SUBC,
2162 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2163
2164 if (hasCarry) {
2165 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
2166 if (N->getOpcode() == ISD::ADD) {
2167 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2168 HiOps[2] = Lo.getValue(1);
2169 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2170 } else {
2171 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2172 HiOps[2] = Lo.getValue(1);
2173 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2174 }
2175 return;
2176 }
2177
2178 bool hasOVF =
2179 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
2180 ISD::UADDO : ISD::USUBO,
2181 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
2182 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
2183
2184 if (hasOVF) {
2185 EVT OvfVT = getSetCCResultType(NVT);
2186 SDVTList VTList = DAG.getVTList(NVT, OvfVT);
2187 int RevOpc;
2188 if (N->getOpcode() == ISD::ADD) {
2189 RevOpc = ISD::SUB;
2190 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
2191 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2192 } else {
2193 RevOpc = ISD::ADD;
2194 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
2195 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2196 }
2197 SDValue OVF = Lo.getValue(1);
2198
2199 switch (BoolType) {
2200 case TargetLoweringBase::UndefinedBooleanContent:
2201 OVF = DAG.getNode(ISD::AND, dl, OvfVT, DAG.getConstant(1, dl, OvfVT), OVF);
2202 LLVM_FALLTHROUGH[[gnu::fallthrough]];
2203 case TargetLoweringBase::ZeroOrOneBooleanContent:
2204 OVF = DAG.getZExtOrTrunc(OVF, dl, NVT);
2205 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
2206 break;
2207 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
2208 OVF = DAG.getSExtOrTrunc(OVF, dl, NVT);
2209 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
2210 }
2211 return;
2212 }
2213
2214 if (N->getOpcode() == ISD::ADD) {
2215 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
2216 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
2217 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
2218 ISD::SETULT);
2219
2220 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent) {
2221 SDValue Carry = DAG.getZExtOrTrunc(Cmp1, dl, NVT);
2222 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry);
2223 return;
2224 }
2225
2226 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
2227 DAG.getConstant(1, dl, NVT),
2228 DAG.getConstant(0, dl, NVT));
2229 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
2230 ISD::SETULT);
2231 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
2232 DAG.getConstant(1, dl, NVT), Carry1);
2233 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
2234 } else {
2235 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
2236 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
2237 SDValue Cmp =
2238 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
2239 LoOps[0], LoOps[1], ISD::SETULT);
2240
2241 SDValue Borrow;
2242 if (BoolType == TargetLoweringBase::ZeroOrOneBooleanContent)
2243 Borrow = DAG.getZExtOrTrunc(Cmp, dl, NVT);
2244 else
2245 Borrow = DAG.getSelect(dl, NVT, Cmp, DAG.getConstant(1, dl, NVT),
2246 DAG.getConstant(0, dl, NVT));
2247
2248 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
2249 }
2250}
2251
2252void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
2253 SDValue &Lo, SDValue &Hi) {
2254 // Expand the subcomponents.
2255 SDValue LHSL, LHSH, RHSL, RHSH;
2256 SDLoc dl(N);
2257 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2258 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2259 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2260 SDValue LoOps[2] = { LHSL, RHSL };
2261 SDValue HiOps[3] = { LHSH, RHSH };
2262
2263 if (N->getOpcode() == ISD::ADDC) {
2264 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
2265 HiOps[2] = Lo.getValue(1);
2266 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
2267 } else {
2268 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
2269 HiOps[2] = Lo.getValue(1);
2270 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
2271 }
2272
2273 // Legalized the flag result - switch anything that used the old flag to
2274 // use the new one.
2275 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2276}
2277
2278void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
2279 SDValue &Lo, SDValue &Hi) {
2280 // Expand the subcomponents.
2281 SDValue LHSL, LHSH, RHSL, RHSH;
2282 SDLoc dl(N);
2283 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2284 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2285 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
2286 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2287 SDValue HiOps[3] = { LHSH, RHSH };
2288
2289 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2290 HiOps[2] = Lo.getValue(1);
2291 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2292
2293 // Legalized the flag result - switch anything that used the old flag to
2294 // use the new one.
2295 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2296}
2297
2298void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2299 SDValue &Lo, SDValue &Hi) {
2300 SDValue LHS = N->getOperand(0);
2301 SDValue RHS = N->getOperand(1);
2302 SDLoc dl(N);
2303
2304 SDValue Ovf;
2305
2306 unsigned CarryOp, NoCarryOp;
2307 ISD::CondCode Cond;
2308 switch(N->getOpcode()) {
2309 case ISD::UADDO:
2310 CarryOp = ISD::ADDCARRY;
2311 NoCarryOp = ISD::ADD;
2312 Cond = ISD::SETULT;
2313 break;
2314 case ISD::USUBO:
2315 CarryOp = ISD::SUBCARRY;
2316 NoCarryOp = ISD::SUB;
2317 Cond = ISD::SETUGT;
2318 break;
2319 default:
2320 llvm_unreachable("Node has unexpected Opcode")::llvm::llvm_unreachable_internal("Node has unexpected Opcode"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2320)
;
2321 }
2322
2323 bool HasCarryOp = TLI.isOperationLegalOrCustom(
2324 CarryOp, TLI.getTypeToExpandTo(*DAG.getContext(), LHS.getValueType()));
2325
2326 if (HasCarryOp) {
2327 // Expand the subcomponents.
2328 SDValue LHSL, LHSH, RHSL, RHSH;
2329 GetExpandedInteger(LHS, LHSL, LHSH);
2330 GetExpandedInteger(RHS, RHSL, RHSH);
2331 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2332 SDValue LoOps[2] = { LHSL, RHSL };
2333 SDValue HiOps[3] = { LHSH, RHSH };
2334
2335 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2336 HiOps[2] = Lo.getValue(1);
2337 Hi = DAG.getNode(CarryOp, dl, VTList, HiOps);
2338
2339 Ovf = Hi.getValue(1);
2340 } else {
2341 // Expand the result by simply replacing it with the equivalent
2342 // non-overflow-checking operation.
2343 SDValue Sum = DAG.getNode(NoCarryOp, dl, LHS.getValueType(), LHS, RHS);
2344 SplitInteger(Sum, Lo, Hi);
2345
2346 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2347 // overflows iff a - b > a.
2348 Ovf = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS, Cond);
2349 }
2350
2351 // Legalized the flag result - switch anything that used the old flag to
2352 // use the new one.
2353 ReplaceValueWith(SDValue(N, 1), Ovf);
2354}
2355
2356void DAGTypeLegalizer::ExpandIntRes_ADDSUBCARRY(SDNode *N,
2357 SDValue &Lo, SDValue &Hi) {
2358 // Expand the subcomponents.
2359 SDValue LHSL, LHSH, RHSL, RHSH;
2360 SDLoc dl(N);
2361 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2362 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
2363 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), N->getValueType(1));
2364 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
2365 SDValue HiOps[3] = { LHSH, RHSH, SDValue() };
2366
2367 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
2368 HiOps[2] = Lo.getValue(1);
2369 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
2370
2371 // Legalized the flag result - switch anything that used the old flag to
2372 // use the new one.
2373 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
2374}
2375
2376void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
2377 SDValue &Lo, SDValue &Hi) {
2378 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2379 SDLoc dl(N);
2380 SDValue Op = N->getOperand(0);
2381 if (Op.getValueType().bitsLE(NVT)) {
2382 // The low part is any extension of the input (which degenerates to a copy).
2383 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
2384 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
2385 } else {
2386 // For example, extension of an i48 to an i64. The operand type necessarily
2387 // promotes to the result type, so will end up being expanded too.
2388 assert(getTypeAction(Op.getValueType()) ==((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2390, __PRETTY_FUNCTION__))
2389 TargetLowering::TypePromoteInteger &&((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2390, __PRETTY_FUNCTION__))
2390 "Only know how to promote this result!")((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2390, __PRETTY_FUNCTION__))
;
2391 SDValue Res = GetPromotedInteger(Op);
2392 assert(Res.getValueType() == N->getValueType(0) &&((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2393, __PRETTY_FUNCTION__))
2393 "Operand over promoted?")((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2393, __PRETTY_FUNCTION__))
;
2394 // Split the promoted operand. This will simplify when it is expanded.
2395 SplitInteger(Res, Lo, Hi);
2396 }
2397}
2398
2399void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
2400 SDValue &Lo, SDValue &Hi) {
2401 SDLoc dl(N);
2402 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2403 EVT NVT = Lo.getValueType();
2404 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2405 unsigned NVTBits = NVT.getSizeInBits();
2406 unsigned EVTBits = EVT.getSizeInBits();
2407
2408 if (NVTBits < EVTBits) {
2409 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
2410 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2411 EVTBits - NVTBits)));
2412 } else {
2413 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
2414 // The high part replicates the sign bit of Lo, make it explicit.
2415 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2416 DAG.getConstant(NVTBits - 1, dl,
2417 TLI.getPointerTy(DAG.getDataLayout())));
2418 }
2419}
2420
2421void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
2422 SDValue &Lo, SDValue &Hi) {
2423 SDLoc dl(N);
2424 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2425 EVT NVT = Lo.getValueType();
2426 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2427 unsigned NVTBits = NVT.getSizeInBits();
2428 unsigned EVTBits = EVT.getSizeInBits();
2429
2430 if (NVTBits < EVTBits) {
2431 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
2432 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2433 EVTBits - NVTBits)));
2434 } else {
2435 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
2436 // The high part must be zero, make it explicit.
2437 Hi = DAG.getConstant(0, dl, NVT);
2438 }
2439}
2440
2441void DAGTypeLegalizer::ExpandIntRes_BITREVERSE(SDNode *N,
2442 SDValue &Lo, SDValue &Hi) {
2443 SDLoc dl(N);
2444 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
2445 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo);
2446 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi);
2447}
2448
2449void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
2450 SDValue &Lo, SDValue &Hi) {
2451 SDLoc dl(N);
2452 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
2453 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
2454 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
2455}
2456
2457void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
2458 SDValue &Lo, SDValue &Hi) {
2459 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2460 unsigned NBitWidth = NVT.getSizeInBits();
2461 auto Constant = cast<ConstantSDNode>(N);
2462 const APInt &Cst = Constant->getAPIntValue();
2463 bool IsTarget = Constant->isTargetOpcode();
2464 bool IsOpaque = Constant->isOpaque();
2465 SDLoc dl(N);
2466 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
2467 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
2468 IsOpaque);
2469}
2470
2471void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
2472 SDLoc dl(N);
2473
2474 // abs(HiLo) -> (Hi < 0 ? -HiLo : HiLo)
2475 EVT VT = N->getValueType(0);
2476 SDValue N0 = N->getOperand(0);
2477 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT,
2478 DAG.getConstant(0, dl, VT), N0);
2479 SDValue NegLo, NegHi;
2480 SplitInteger(Neg, NegLo, NegHi);
2481
2482 GetExpandedInteger(N0, Lo, Hi);
2483 EVT NVT = Lo.getValueType();
2484 SDValue HiIsNeg = DAG.getSetCC(dl, getSetCCResultType(NVT),
2485 DAG.getConstant(0, dl, NVT), Hi, ISD::SETGT);
2486 Lo = DAG.getSelect(dl, NVT, HiIsNeg, NegLo, Lo);
2487 Hi = DAG.getSelect(dl, NVT, HiIsNeg, NegHi, Hi);
2488}
2489
2490void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
2491 SDValue &Lo, SDValue &Hi) {
2492 SDLoc dl(N);
2493 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
2494 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2495 EVT NVT = Lo.getValueType();
2496
2497 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
2498 DAG.getConstant(0, dl, NVT), ISD::SETNE);
2499
2500 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
2501 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
2502
2503 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
2504 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
2505 DAG.getConstant(NVT.getSizeInBits(), dl,
2506 NVT)));
2507 Hi = DAG.getConstant(0, dl, NVT);
2508}
2509
2510void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
2511 SDValue &Lo, SDValue &Hi) {
2512 SDLoc dl(N);
2513 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
2514 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2515 EVT NVT = Lo.getValueType();
2516 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
2517 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
2518 Hi = DAG.getConstant(0, dl, NVT);
2519}
2520
2521void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
2522 SDValue &Lo, SDValue &Hi) {
2523 SDLoc dl(N);
2524 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
2525 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2526 EVT NVT = Lo.getValueType();
2527
2528 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
2529 DAG.getConstant(0, dl, NVT), ISD::SETNE);
2530
2531 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
2532 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
2533
2534 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
2535 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
2536 DAG.getConstant(NVT.getSizeInBits(), dl,
2537 NVT)));
2538 Hi = DAG.getConstant(0, dl, NVT);
2539}
2540
2541void DAGTypeLegalizer::ExpandIntRes_FLT_ROUNDS(SDNode *N, SDValue &Lo,
2542 SDValue &Hi) {
2543 SDLoc dl(N);
2544 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2545 unsigned NBitWidth = NVT.getSizeInBits();
2546
2547 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
2548 Lo = DAG.getNode(ISD::FLT_ROUNDS_, dl, NVT);
2549 // The high part is the sign of Lo, as -1 is a valid value for FLT_ROUNDS
2550 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2551 DAG.getConstant(NBitWidth - 1, dl, ShiftAmtTy));
2552}
2553
2554void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
2555 SDValue &Hi) {
2556 SDLoc dl(N);
2557 EVT VT = N->getValueType(0);
2558
2559 SDValue Op = N->getOperand(0);
2560 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
2561 Op = GetPromotedFloat(Op);
2562
2563 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
2564 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fp-to-sint conversion!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2564, __PRETTY_FUNCTION__))
;
2565 TargetLowering::MakeLibCallOptions CallOptions;
2566 CallOptions.setSExt(true);
2567 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, CallOptions, dl).first,
2568 Lo, Hi);
2569}
2570
2571void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
2572 SDValue &Hi) {
2573 SDLoc dl(N);
2574 EVT VT = N->getValueType(0);
2575
2576 SDValue Op = N->getOperand(0);
2577 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
2578 Op = GetPromotedFloat(Op);
2579
2580 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
2581 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected fp-to-uint conversion!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2581, __PRETTY_FUNCTION__))
;
2582 TargetLowering::MakeLibCallOptions CallOptions;
2583 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Op, CallOptions, dl).first,
2584 Lo, Hi);
2585}
2586
2587void DAGTypeLegalizer::ExpandIntRes_LLROUND(SDNode *N, SDValue &Lo,
2588 SDValue &Hi) {
2589 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2590 EVT VT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
2591 if (VT == MVT::f32)
2592 LC = RTLIB::LLROUND_F32;
2593 else if (VT == MVT::f64)
2594 LC = RTLIB::LLROUND_F64;
2595 else if (VT == MVT::f80)
2596 LC = RTLIB::LLROUND_F80;
2597 else if (VT == MVT::f128)
2598 LC = RTLIB::LLROUND_F128;
2599 else if (VT == MVT::ppcf128)
2600 LC = RTLIB::LLROUND_PPCF128;
2601 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llround input type!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected llround input type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2601, __PRETTY_FUNCTION__))
;
2602
2603 SDValue Op = N->getOperand(0);
2604 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
2605 Op = GetPromotedFloat(Op);
2606
2607 SDLoc dl(N);
2608 EVT RetVT = N->getValueType(0);
2609 TargetLowering::MakeLibCallOptions CallOptions;
2610 CallOptions.setSExt(true);
2611 SplitInteger(TLI.makeLibCall(DAG, LC, RetVT, Op, CallOptions, dl).first,
2612 Lo, Hi);
2613}
2614
2615void DAGTypeLegalizer::ExpandIntRes_LLRINT(SDNode *N, SDValue &Lo,
2616 SDValue &Hi) {
2617 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2618 EVT VT = N->getOperand(0).getValueType().getSimpleVT().SimpleTy;
2619 if (VT == MVT::f32)
2620 LC = RTLIB::LLRINT_F32;
2621 else if (VT == MVT::f64)
2622 LC = RTLIB::LLRINT_F64;
2623 else if (VT == MVT::f80)
2624 LC = RTLIB::LLRINT_F80;
2625 else if (VT == MVT::f128)
2626 LC = RTLIB::LLRINT_F128;
2627 else if (VT == MVT::ppcf128)
2628 LC = RTLIB::LLRINT_PPCF128;
2629 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected llrint input type!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unexpected llrint input type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2629, __PRETTY_FUNCTION__))
;
2630
2631 SDValue Op = N->getOperand(0);
2632 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
2633 Op = GetPromotedFloat(Op);
2634
2635 SDLoc dl(N);
2636 EVT RetVT = N->getValueType(0);
2637 TargetLowering::MakeLibCallOptions CallOptions;
2638 CallOptions.setSExt(true);
2639 SplitInteger(TLI.makeLibCall(DAG, LC, RetVT, Op, CallOptions, dl).first,
2640 Lo, Hi);
2641}
2642
2643void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
2644 SDValue &Lo, SDValue &Hi) {
2645 if (N->isAtomic()) {
2646 // It's typical to have larger CAS than atomic load instructions.
2647 SDLoc dl(N);
2648 EVT VT = N->getMemoryVT();
2649 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2650 SDValue Zero = DAG.getConstant(0, dl, VT);
2651 SDValue Swap = DAG.getAtomicCmpSwap(
2652 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2653 VT, VTs, N->getOperand(0),
2654 N->getOperand(1), Zero, Zero, N->getMemOperand());
2655 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2656 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2657 return;
2658 }
2659
2660 if (ISD::isNormalLoad(N)) {
2661 ExpandRes_NormalLoad(N, Lo, Hi);
2662 return;
2663 }
2664
2665 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!")((ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDLoad(N) && \"Indexed load during type legalization!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2665, __PRETTY_FUNCTION__))
;
2666
2667 EVT VT = N->getValueType(0);
2668 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2669 SDValue Ch = N->getChain();
2670 SDValue Ptr = N->getBasePtr();
2671 ISD::LoadExtType ExtType = N->getExtensionType();
2672 unsigned Alignment = N->getAlignment();
2673 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
2674 AAMDNodes AAInfo = N->getAAInfo();
2675 SDLoc dl(N);
2676
2677 assert(NVT.isByteSized() && "Expanded type not byte sized!")((NVT.isByteSized() && "Expanded type not byte sized!"
) ? static_cast<void> (0) : __assert_fail ("NVT.isByteSized() && \"Expanded type not byte sized!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2677, __PRETTY_FUNCTION__))
;
2678
2679 if (N->getMemoryVT().bitsLE(NVT)) {
2680 EVT MemVT = N->getMemoryVT();
2681
2682 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), MemVT,
2683 Alignment, MMOFlags, AAInfo);
2684
2685 // Remember the chain.
2686 Ch = Lo.getValue(1);
2687
2688 if (ExtType == ISD::SEXTLOAD) {
2689 // The high part is obtained by SRA'ing all but one of the bits of the
2690 // lo part.
2691 unsigned LoSize = Lo.getValueSizeInBits();
2692 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2693 DAG.getConstant(LoSize - 1, dl,
2694 TLI.getPointerTy(DAG.getDataLayout())));
2695 } else if (ExtType == ISD::ZEXTLOAD) {
2696 // The high part is just a zero.
2697 Hi = DAG.getConstant(0, dl, NVT);
2698 } else {
2699 assert(ExtType == ISD::EXTLOAD && "Unknown extload!")((ExtType == ISD::EXTLOAD && "Unknown extload!") ? static_cast
<void> (0) : __assert_fail ("ExtType == ISD::EXTLOAD && \"Unknown extload!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2699, __PRETTY_FUNCTION__))
;
2700 // The high part is undefined.
2701 Hi = DAG.getUNDEF(NVT);
2702 }
2703 } else if (DAG.getDataLayout().isLittleEndian()) {
2704 // Little-endian - low bits are at low addresses.
2705 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
2706 AAInfo);
2707
2708 unsigned ExcessBits =
2709 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2710 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2711
2712 // Increment the pointer to the other half.
2713 unsigned IncrementSize = NVT.getSizeInBits()/8;
2714 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2715 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2716 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
2717 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
2718 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
2719
2720 // Build a factor node to remember that this load is independent of the
2721 // other one.
2722 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2723 Hi.getValue(1));
2724 } else {
2725 // Big-endian - high bits are at low addresses. Favor aligned loads at
2726 // the cost of some bit-fiddling.
2727 EVT MemVT = N->getMemoryVT();
2728 unsigned EBytes = MemVT.getStoreSize();
2729 unsigned IncrementSize = NVT.getSizeInBits()/8;
2730 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2731
2732 // Load both the high bits and maybe some of the low bits.
2733 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2734 EVT::getIntegerVT(*DAG.getContext(),
2735 MemVT.getSizeInBits() - ExcessBits),
2736 Alignment, MMOFlags, AAInfo);
2737
2738 // Increment the pointer to the other half.
2739 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2740 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2741 // Load the rest of the low bits.
2742 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2743 N->getPointerInfo().getWithOffset(IncrementSize),
2744 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2745 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
2746
2747 // Build a factor node to remember that this load is independent of the
2748 // other one.
2749 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2750 Hi.getValue(1));
2751
2752 if (ExcessBits < NVT.getSizeInBits()) {
2753 // Transfer low bits from the bottom of Hi to the top of Lo.
2754 Lo = DAG.getNode(
2755 ISD::OR, dl, NVT, Lo,
2756 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2757 DAG.getConstant(ExcessBits, dl,
2758 TLI.getPointerTy(DAG.getDataLayout()))));
2759 // Move high bits to the right position in Hi.
2760 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2761 Hi,
2762 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2763 TLI.getPointerTy(DAG.getDataLayout())));
2764 }
2765 }
2766
2767 // Legalize the chain result - switch anything that used the old chain to
2768 // use the new one.
2769 ReplaceValueWith(SDValue(N, 1), Ch);
2770}
2771
2772void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2773 SDValue &Lo, SDValue &Hi) {
2774 SDLoc dl(N);
2775 SDValue LL, LH, RL, RH;
2776 GetExpandedInteger(N->getOperand(0), LL, LH);
2777 GetExpandedInteger(N->getOperand(1), RL, RH);
2778 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2779 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2780}
2781
2782void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2783 SDValue &Lo, SDValue &Hi) {
2784 EVT VT = N->getValueType(0);
2785 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2786 SDLoc dl(N);
2787
2788 SDValue LL, LH, RL, RH;
2789 GetExpandedInteger(N->getOperand(0), LL, LH);
2790 GetExpandedInteger(N->getOperand(1), RL, RH);
2791
2792 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG,
2793 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
2794 LL, LH, RL, RH))
2795 return;
2796
2797 // If nothing else, we can make a libcall.
2798 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2799 if (VT == MVT::i16)
2800 LC = RTLIB::MUL_I16;
2801 else if (VT == MVT::i32)
2802 LC = RTLIB::MUL_I32;
2803 else if (VT == MVT::i64)
2804 LC = RTLIB::MUL_I64;
2805 else if (VT == MVT::i128)
2806 LC = RTLIB::MUL_I128;
2807
2808 if (LC == RTLIB::UNKNOWN_LIBCALL || !TLI.getLibcallName(LC)) {
2809 // We'll expand the multiplication by brute force because we have no other
2810 // options. This is a trivially-generalized version of the code from
2811 // Hacker's Delight (itself derived from Knuth's Algorithm M from section
2812 // 4.3.1).
2813 unsigned Bits = NVT.getSizeInBits();
2814 unsigned HalfBits = Bits >> 1;
2815 SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl,
2816 NVT);
2817 SDValue LLL = DAG.getNode(ISD::AND, dl, NVT, LL, Mask);
2818 SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask);
2819
2820 SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
2821 SDValue TL = DAG.getNode(ISD::AND, dl, NVT, T, Mask);
2822
2823 EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
2824 if (APInt::getMaxValue(ShiftAmtTy.getSizeInBits()).ult(HalfBits)) {
2825 // The type from TLI is too small to fit the shift amount we want.
2826 // Override it with i32. The shift will have to be legalized.
2827 ShiftAmtTy = MVT::i32;
2828 }
2829 SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy);
2830 SDValue TH = DAG.getNode(ISD::SRL, dl, NVT, T, Shift);
2831 SDValue LLH = DAG.getNode(ISD::SRL, dl, NVT, LL, Shift);
2832 SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);
2833
2834 SDValue U = DAG.getNode(ISD::ADD, dl, NVT,
2835 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
2836 SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);
2837 SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
2838
2839 SDValue V = DAG.getNode(ISD::ADD, dl, NVT,
2840 DAG.getNode(ISD::MUL, dl, NVT, LLL, RLH), UL);
2841 SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);
2842
2843 SDValue W = DAG.getNode(ISD::ADD, dl, NVT,
2844 DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
2845 DAG.getNode(ISD::ADD, dl, NVT, UH, VH));
2846 Lo = DAG.getNode(ISD::ADD, dl, NVT, TL,
2847 DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
2848
2849 Hi = DAG.getNode(ISD::ADD, dl, NVT, W,
2850 DAG.getNode(ISD::ADD, dl, NVT,
2851 DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
2852 DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
2853 return;
2854 }
2855
2856 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2857 TargetLowering::MakeLibCallOptions CallOptions;
2858 CallOptions.setSExt(true);
2859 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first,
2860 Lo, Hi);
2861}
2862
2863void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
2864 SDValue &Hi) {
2865 SDLoc DL(N);
2866 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2867 SDVTList VTs = DAG.getVTList(NVT, NVT, MVT::Other);
2868 SDValue R = DAG.getNode(N->getOpcode(), DL, VTs, N->getOperand(0));
2869 Lo = R.getValue(0);
2870 Hi = R.getValue(1);
2871 ReplaceValueWith(SDValue(N, 1), R.getValue(2));
2872}
2873
2874void DAGTypeLegalizer::ExpandIntRes_ADDSUBSAT(SDNode *N, SDValue &Lo,
2875 SDValue &Hi) {
2876 SDValue Result = TLI.expandAddSubSat(N, DAG);
2877 SplitInteger(Result, Lo, Hi);
2878}
2879
2880/// This performs an expansion of the integer result for a fixed point
2881/// multiplication. The default expansion performs rounding down towards
2882/// negative infinity, though targets that do care about rounding should specify
2883/// a target hook for rounding and provide their own expansion or lowering of
2884/// fixed point multiplication to be consistent with rounding.
2885void DAGTypeLegalizer::ExpandIntRes_MULFIX(SDNode *N, SDValue &Lo,
2886 SDValue &Hi) {
2887 SDLoc dl(N);
2888 EVT VT = N->getValueType(0);
2889 unsigned VTSize = VT.getScalarSizeInBits();
2890 SDValue LHS = N->getOperand(0);
2891 SDValue RHS = N->getOperand(1);
2892 uint64_t Scale = N->getConstantOperandVal(2);
2893 bool Saturating = (N->getOpcode() == ISD::SMULFIXSAT ||
2894 N->getOpcode() == ISD::UMULFIXSAT);
2895 bool Signed = (N->getOpcode() == ISD::SMULFIX ||
2896 N->getOpcode() == ISD::SMULFIXSAT);
2897
2898 // Handle special case when scale is equal to zero.
2899 if (!Scale) {
2900 SDValue Result;
2901 if (!Saturating) {
2902 Result = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
2903 } else {
2904 EVT BoolVT = getSetCCResultType(VT);
2905 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO;
2906 Result = DAG.getNode(MulOp, dl, DAG.getVTList(VT, BoolVT), LHS, RHS);
2907 SDValue Product = Result.getValue(0);
2908 SDValue Overflow = Result.getValue(1);
2909 if (Signed) {
2910 APInt MinVal = APInt::getSignedMinValue(VTSize);
2911 APInt MaxVal = APInt::getSignedMaxValue(VTSize);
2912 SDValue SatMin = DAG.getConstant(MinVal, dl, VT);
2913 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
2914 SDValue Zero = DAG.getConstant(0, dl, VT);
2915 SDValue ProdNeg = DAG.getSetCC(dl, BoolVT, Product, Zero, ISD::SETLT);
2916 Result = DAG.getSelect(dl, VT, ProdNeg, SatMax, SatMin);
2917 Result = DAG.getSelect(dl, VT, Overflow, Result, Product);
2918 } else {
2919 // For unsigned multiplication, we only need to check the max since we
2920 // can't really overflow towards zero.
2921 APInt MaxVal = APInt::getMaxValue(VTSize);
2922 SDValue SatMax = DAG.getConstant(MaxVal, dl, VT);
2923 Result = DAG.getSelect(dl, VT, Overflow, SatMax, Product);
2924 }
2925 }
2926 SplitInteger(Result, Lo, Hi);
2927 return;
2928 }
2929
2930 // For SMULFIX[SAT] we only expect to find Scale<VTSize, but this assert will
2931 // cover for unhandled cases below, while still being valid for UMULFIX[SAT].
2932 assert(Scale <= VTSize && "Scale can't be larger than the value type size.")((Scale <= VTSize && "Scale can't be larger than the value type size."
) ? static_cast<void> (0) : __assert_fail ("Scale <= VTSize && \"Scale can't be larger than the value type size.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2932, __PRETTY_FUNCTION__))
;
2933
2934 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2935 SDValue LL, LH, RL, RH;
2936 GetExpandedInteger(LHS, LL, LH);
2937 GetExpandedInteger(RHS, RL, RH);
2938 SmallVector<SDValue, 4> Result;
2939
2940 unsigned LoHiOp = Signed ? ISD::SMUL_LOHI : ISD::UMUL_LOHI;
2941 if (!TLI.expandMUL_LOHI(LoHiOp, VT, dl, LHS, RHS, Result, NVT, DAG,
2942 TargetLowering::MulExpansionKind::OnlyLegalOrCustom,
2943 LL, LH, RL, RH)) {
2944 report_fatal_error("Unable to expand MUL_FIX using MUL_LOHI.");
2945 return;
2946 }
2947
2948 unsigned NVTSize = NVT.getScalarSizeInBits();
2949 assert((VTSize == NVTSize * 2) && "Expected the new value type to be half "(((VTSize == NVTSize * 2) && "Expected the new value type to be half "
"the size of the current value type") ? static_cast<void>
(0) : __assert_fail ("(VTSize == NVTSize * 2) && \"Expected the new value type to be half \" \"the size of the current value type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2950, __PRETTY_FUNCTION__))
2950 "the size of the current value type")(((VTSize == NVTSize * 2) && "Expected the new value type to be half "
"the size of the current value type") ? static_cast<void>
(0) : __assert_fail ("(VTSize == NVTSize * 2) && \"Expected the new value type to be half \" \"the size of the current value type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 2950, __PRETTY_FUNCTION__))
;
2951 EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
2952
2953 // After getting the multiplication result in 4 parts, we need to perform a
2954 // shift right by the amount of the scale to get the result in that scale.
2955 //
2956 // Let's say we multiply 2 64 bit numbers. The resulting value can be held in
2957 // 128 bits that are cut into 4 32-bit parts:
2958 //
2959 // HH HL LH LL
2960 // |---32---|---32---|---32---|---32---|
2961 // 128 96 64 32 0
2962 //
2963 // |------VTSize-----|
2964 //
2965 // |NVTSize-|
2966 //
2967 // The resulting Lo and Hi would normally be in LL and LH after the shift. But
2968 // to avoid unneccessary shifting of all 4 parts, we can adjust the shift
2969 // amount and get Lo and Hi using two funnel shifts. Or for the special case
2970 // when Scale is a multiple of NVTSize we can just pick the result without
2971 // shifting.
2972 uint64_t Part0 = Scale / NVTSize; // Part holding lowest bit needed.
2973 if (Scale % NVTSize) {
2974 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy);
2975 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0],
2976 ShiftAmount);
2977 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1],
2978 ShiftAmount);
2979 } else {
2980 Lo = Result[Part0];
2981 Hi = Result[Part0 + 1];
2982 }
2983
2984 // Unless saturation is requested we are done. The result is in <Hi,Lo>.
2985 if (!Saturating)
2986 return;
2987
2988 // Can not overflow when there is no integer part.
2989 if (Scale == VTSize)
2990 return;
2991
2992 // To handle saturation we must check for overflow in the multiplication.
2993 //
2994 // Unsigned overflow happened if the upper (VTSize - Scale) bits (of Result)
2995 // aren't all zeroes.
2996 //
2997 // Signed overflow happened if the upper (VTSize - Scale + 1) bits (of Result)
2998 // aren't all ones or all zeroes.
2999 //
3000 // We cannot overflow past HH when multiplying 2 ints of size VTSize, so the
3001 // highest bit of HH determines saturation direction in the event of signed
3002 // saturation.
3003
3004 SDValue ResultHL = Result[2];
3005 SDValue ResultHH = Result[3];
3006
3007 SDValue SatMax, SatMin;
3008 SDValue NVTZero = DAG.getConstant(0, dl, NVT);
3009 SDValue NVTNeg1 = DAG.getConstant(-1, dl, NVT);
3010 EVT BoolNVT = getSetCCResultType(NVT);
3011
3012 if (!Signed) {
3013 if (Scale < NVTSize) {
3014 // Overflow happened if ((HH | (HL >> Scale)) != 0).
3015 SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3016 DAG.getConstant(Scale, dl, ShiftTy));
3017 SDValue Tmp = DAG.getNode(ISD::OR, dl, NVT, HLAdjusted, ResultHH);
3018 SatMax = DAG.getSetCC(dl, BoolNVT, Tmp, NVTZero, ISD::SETNE);
3019 } else if (Scale == NVTSize) {
3020 // Overflow happened if (HH != 0).
3021 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETNE);
3022 } else if (Scale < VTSize) {
3023 // Overflow happened if ((HH >> (Scale - NVTSize)) != 0).
3024 SDValue HLAdjusted = DAG.getNode(ISD::SRL, dl, NVT, ResultHL,
3025 DAG.getConstant(Scale - NVTSize, dl,
3026 ShiftTy));
3027 SatMax = DAG.getSetCC(dl, BoolNVT, HLAdjusted, NVTZero, ISD::SETNE);
3028 } else
3029 llvm_unreachable("Scale must be less or equal to VTSize for UMULFIXSAT"::llvm::llvm_unreachable_internal("Scale must be less or equal to VTSize for UMULFIXSAT"
"(and saturation can't happen with Scale==VTSize).", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3030)
3030 "(and saturation can't happen with Scale==VTSize).")::llvm::llvm_unreachable_internal("Scale must be less or equal to VTSize for UMULFIXSAT"
"(and saturation can't happen with Scale==VTSize).", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3030)
;
3031
3032 Hi = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Hi);
3033 Lo = DAG.getSelect(dl, NVT, SatMax, NVTNeg1, Lo);
3034 return;
3035 }
3036
3037 if (Scale < NVTSize) {
3038 // The number of overflow bits we can check are VTSize - Scale + 1 (we
3039 // include the sign bit). If these top bits are > 0, then we overflowed past
3040 // the max value. If these top bits are < -1, then we overflowed past the
3041 // min value. Otherwise, we did not overflow.
3042 unsigned OverflowBits = VTSize - Scale + 1;
3043 assert(OverflowBits <= VTSize && OverflowBits > NVTSize &&((OverflowBits <= VTSize && OverflowBits > NVTSize
&& "Extent of overflow bits must start within HL") ?
static_cast<void> (0) : __assert_fail ("OverflowBits <= VTSize && OverflowBits > NVTSize && \"Extent of overflow bits must start within HL\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3044, __PRETTY_FUNCTION__))
3044 "Extent of overflow bits must start within HL")((OverflowBits <= VTSize && OverflowBits > NVTSize
&& "Extent of overflow bits must start within HL") ?
static_cast<void> (0) : __assert_fail ("OverflowBits <= VTSize && OverflowBits > NVTSize && \"Extent of overflow bits must start within HL\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3044, __PRETTY_FUNCTION__))
;
3045 SDValue HLHiMask = DAG.getConstant(
3046 APInt::getHighBitsSet(NVTSize, OverflowBits - NVTSize), dl, NVT);
3047 SDValue HLLoMask = DAG.getConstant(
3048 APInt::getLowBitsSet(NVTSize, VTSize - OverflowBits), dl, NVT);
3049 // We overflow max if HH > 0 or (HH == 0 && HL > HLLoMask).
3050 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3051 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3052 SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT);
3053 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3054 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLUGT));
3055 // We overflow min if HH < -1 or (HH == -1 && HL < HLHiMask).
3056 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3057 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3058 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT);
3059 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3060 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLULT));
3061 } else if (Scale == NVTSize) {
3062 // We overflow max if HH > 0 or (HH == 0 && HL sign bit is 1).
3063 SDValue HHGT0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETGT);
3064 SDValue HHEQ0 = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTZero, ISD::SETEQ);
3065 SDValue HLNeg = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETLT);
3066 SatMax = DAG.getNode(ISD::OR, dl, BoolNVT, HHGT0,
3067 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ0, HLNeg));
3068 // We overflow min if HH < -1 or (HH == -1 && HL sign bit is 0).
3069 SDValue HHLT = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETLT);
3070 SDValue HHEQ = DAG.getSetCC(dl, BoolNVT, ResultHH, NVTNeg1, ISD::SETEQ);
3071 SDValue HLPos = DAG.getSetCC(dl, BoolNVT, ResultHL, NVTZero, ISD::SETGE);
3072 SatMin = DAG.getNode(ISD::OR, dl, BoolNVT, HHLT,
3073 DAG.getNode(ISD::AND, dl, BoolNVT, HHEQ, HLPos));
3074 } else if (Scale < VTSize) {
3075 // This is similar to the case when we saturate if Scale < NVTSize, but we
3076 // only need to check HH.
3077 unsigned OverflowBits = VTSize - Scale + 1;
3078 SDValue HHHiMask = DAG.getConstant(
3079 APInt::getHighBitsSet(NVTSize, OverflowBits), dl, NVT);
3080 SDValue HHLoMask = DAG.getConstant(
3081 APInt::getLowBitsSet(NVTSize, NVTSize - OverflowBits), dl, NVT);
3082 SatMax = DAG.getSetCC(dl, BoolNVT, ResultHH, HHLoMask, ISD::SETGT);
3083 SatMin = DAG.getSetCC(dl, BoolNVT, ResultHH, HHHiMask, ISD::SETLT);
3084 } else
3085 llvm_unreachable("Illegal scale for signed fixed point mul.")::llvm::llvm_unreachable_internal("Illegal scale for signed fixed point mul."
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3085)
;
3086
3087 // Saturate to signed maximum.
3088 APInt MaxHi = APInt::getSignedMaxValue(NVTSize);
3089 APInt MaxLo = APInt::getAllOnesValue(NVTSize);
3090 Hi = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxHi, dl, NVT), Hi);
3091 Lo = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxLo, dl, NVT), Lo);
3092 // Saturate to signed minimum.
3093 APInt MinHi = APInt::getSignedMinValue(NVTSize);
3094 Hi = DAG.getSelect(dl, NVT, SatMin, DAG.getConstant(MinHi, dl, NVT), Hi);
3095 Lo = DAG.getSelect(dl, NVT, SatMin, NVTZero, Lo);
3096}
3097
3098void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
3099 SDValue &Lo, SDValue &Hi) {
3100 SDValue LHS = Node->getOperand(0);
3101 SDValue RHS = Node->getOperand(1);
3102 SDLoc dl(Node);
3103
3104 // Expand the result by simply replacing it with the equivalent
3105 // non-overflow-checking operation.
3106 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3107 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3108 LHS, RHS);
3109 SplitInteger(Sum, Lo, Hi);
3110
3111 // Compute the overflow.
3112 //
3113 // LHSSign -> LHS >= 0
3114 // RHSSign -> RHS >= 0
3115 // SumSign -> Sum >= 0
3116 //
3117 // Add:
3118 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3119 // Sub:
3120 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3121 //
3122 EVT OType = Node->getValueType(1);
3123 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3124
3125 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3126 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3127 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3128 Node->getOpcode() == ISD::SADDO ?
3129 ISD::SETEQ : ISD::SETNE);
3130
3131 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3132 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3133
3134 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3135
3136 // Use the calculated overflow everywhere.
3137 ReplaceValueWith(SDValue(Node, 1), Cmp);
3138}
3139
3140void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
3141 SDValue &Lo, SDValue &Hi) {
3142 EVT VT = N->getValueType(0);
3143 SDLoc dl(N);
3144 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3145
3146 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3147 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3148 SplitInteger(Res.getValue(0), Lo, Hi);
3149 return;
3150 }
3151
3152 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3153 if (VT == MVT::i16)
3154 LC = RTLIB::SDIV_I16;
3155 else if (VT == MVT::i32)
3156 LC = RTLIB::SDIV_I32;
3157 else if (VT == MVT::i64)
3158 LC = RTLIB::SDIV_I64;
3159 else if (VT == MVT::i128)
3160 LC = RTLIB::SDIV_I128;
3161 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported SDIV!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3161, __PRETTY_FUNCTION__))
;
3162
3163 TargetLowering::MakeLibCallOptions CallOptions;
3164 CallOptions.setSExt(true);
3165 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3166}
3167
3168void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
3169 SDValue &Lo, SDValue &Hi) {
3170 EVT VT = N->getValueType(0);
3171 SDLoc dl(N);
3172
3173 // If we can emit an efficient shift operation, do so now. Check to see if
3174 // the RHS is a constant.
3175 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
7
Assuming 'CN' is null
8
Taking false branch
3176 return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
3177
3178 // If we can determine that the high bit of the shift is zero or one, even if
3179 // the low bits are variable, emit this shift in an optimized form.
3180 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
9
Calling 'DAGTypeLegalizer::ExpandShiftWithKnownAmountBit'
3181 return;
3182
3183 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
3184 unsigned PartsOpc;
3185 if (N->getOpcode() == ISD::SHL) {
3186 PartsOpc = ISD::SHL_PARTS;
3187 } else if (N->getOpcode() == ISD::SRL) {
3188 PartsOpc = ISD::SRL_PARTS;
3189 } else {
3190 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")((N->getOpcode() == ISD::SRA && "Unknown shift!") ?
static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3190, __PRETTY_FUNCTION__))
;
3191 PartsOpc = ISD::SRA_PARTS;
3192 }
3193
3194 // Next check to see if the target supports this SHL_PARTS operation or if it
3195 // will custom expand it. Don't lower this to SHL_PARTS when we optimise for
3196 // size, but create a libcall instead.
3197 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3198 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
3199 const bool LegalOrCustom =
3200 (Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3201 Action == TargetLowering::Custom;
3202
3203 if (LegalOrCustom && TLI.shouldExpandShift(DAG, N)) {
3204 // Expand the subcomponents.
3205 SDValue LHSL, LHSH;
3206 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
3207 EVT VT = LHSL.getValueType();
3208
3209 // If the shift amount operand is coming from a vector legalization it may
3210 // have an illegal type. Fix that first by casting the operand, otherwise
3211 // the new SHL_PARTS operation would need further legalization.
3212 SDValue ShiftOp = N->getOperand(1);
3213 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3214 assert(ShiftTy.getScalarSizeInBits() >=((ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits
()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? static_cast<void> (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3216, __PRETTY_FUNCTION__))
3215 Log2_32_Ceil(VT.getScalarSizeInBits()) &&((ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits
()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? static_cast<void> (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3216, __PRETTY_FUNCTION__))
3216 "ShiftAmountTy is too small to cover the range of this type!")((ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits
()) && "ShiftAmountTy is too small to cover the range of this type!"
) ? static_cast<void> (0) : __assert_fail ("ShiftTy.getScalarSizeInBits() >= Log2_32_Ceil(VT.getScalarSizeInBits()) && \"ShiftAmountTy is too small to cover the range of this type!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3216, __PRETTY_FUNCTION__))
;
3217 if (ShiftOp.getValueType() != ShiftTy)
3218 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
3219
3220 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
3221 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
3222 Hi = Lo.getValue(1);
3223 return;
3224 }
3225
3226 // Otherwise, emit a libcall.
3227 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3228 bool isSigned;
3229 if (N->getOpcode() == ISD::SHL) {
3230 isSigned = false; /*sign irrelevant*/
3231 if (VT == MVT::i16)
3232 LC = RTLIB::SHL_I16;
3233 else if (VT == MVT::i32)
3234 LC = RTLIB::SHL_I32;
3235 else if (VT == MVT::i64)
3236 LC = RTLIB::SHL_I64;
3237 else if (VT == MVT::i128)
3238 LC = RTLIB::SHL_I128;
3239 } else if (N->getOpcode() == ISD::SRL) {
3240 isSigned = false;
3241 if (VT == MVT::i16)
3242 LC = RTLIB::SRL_I16;
3243 else if (VT == MVT::i32)
3244 LC = RTLIB::SRL_I32;
3245 else if (VT == MVT::i64)
3246 LC = RTLIB::SRL_I64;
3247 else if (VT == MVT::i128)
3248 LC = RTLIB::SRL_I128;
3249 } else {
3250 assert(N->getOpcode() == ISD::SRA && "Unknown shift!")((N->getOpcode() == ISD::SRA && "Unknown shift!") ?
static_cast<void> (0) : __assert_fail ("N->getOpcode() == ISD::SRA && \"Unknown shift!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3250, __PRETTY_FUNCTION__))
;
3251 isSigned = true;
3252 if (VT == MVT::i16)
3253 LC = RTLIB::SRA_I16;
3254 else if (VT == MVT::i32)
3255 LC = RTLIB::SRA_I32;
3256 else if (VT == MVT::i64)
3257 LC = RTLIB::SRA_I64;
3258 else if (VT == MVT::i128)
3259 LC = RTLIB::SRA_I128;
3260 }
3261
3262 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
3263 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3264 TargetLowering::MakeLibCallOptions CallOptions;
3265 CallOptions.setSExt(isSigned);
3266 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3267 return;
3268 }
3269
3270 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
3271 llvm_unreachable("Unsupported shift!")::llvm::llvm_unreachable_internal("Unsupported shift!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3271)
;
3272}
3273
3274void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
3275 SDValue &Lo, SDValue &Hi) {
3276 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3277 SDLoc dl(N);
3278 SDValue Op = N->getOperand(0);
3279 if (Op.getValueType().bitsLE(NVT)) {
3280 // The low part is sign extension of the input (degenerates to a copy).
3281 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
3282 // The high part is obtained by SRA'ing all but one of the bits of low part.
3283 unsigned LoSize = NVT.getSizeInBits();
3284 Hi = DAG.getNode(
3285 ISD::SRA, dl, NVT, Lo,
3286 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
3287 } else {
3288 // For example, extension of an i48 to an i64. The operand type necessarily
3289 // promotes to the result type, so will end up being expanded too.
3290 assert(getTypeAction(Op.getValueType()) ==((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3292, __PRETTY_FUNCTION__))
3291 TargetLowering::TypePromoteInteger &&((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3292, __PRETTY_FUNCTION__))
3292 "Only know how to promote this result!")((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3292, __PRETTY_FUNCTION__))
;
3293 SDValue Res = GetPromotedInteger(Op);
3294 assert(Res.getValueType() == N->getValueType(0) &&((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3295, __PRETTY_FUNCTION__))
3295 "Operand over promoted?")((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3295, __PRETTY_FUNCTION__))
;
3296 // Split the promoted operand. This will simplify when it is expanded.
3297 SplitInteger(Res, Lo, Hi);
3298 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
3299 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
3300 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
3301 ExcessBits)));
3302 }
3303}
3304
3305void DAGTypeLegalizer::
3306ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
3307 SDLoc dl(N);
3308 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3309 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3310
3311 if (EVT.bitsLE(Lo.getValueType())) {
3312 // sext_inreg the low part if needed.
3313 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
3314 N->getOperand(1));
3315
3316 // The high part gets the sign extension from the lo-part. This handles
3317 // things like sextinreg V:i64 from i8.
3318 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
3319 DAG.getConstant(Hi.getValueSizeInBits() - 1, dl,
3320 TLI.getPointerTy(DAG.getDataLayout())));
3321 } else {
3322 // For example, extension of an i48 to an i64. Leave the low part alone,
3323 // sext_inreg the high part.
3324 unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueSizeInBits();
3325 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
3326 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
3327 ExcessBits)));
3328 }
3329}
3330
3331void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
3332 SDValue &Lo, SDValue &Hi) {
3333 EVT VT = N->getValueType(0);
3334 SDLoc dl(N);
3335 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3336
3337 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) {
3338 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3339 SplitInteger(Res.getValue(1), Lo, Hi);
3340 return;
3341 }
3342
3343 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3344 if (VT == MVT::i16)
3345 LC = RTLIB::SREM_I16;
3346 else if (VT == MVT::i32)
3347 LC = RTLIB::SREM_I32;
3348 else if (VT == MVT::i64)
3349 LC = RTLIB::SREM_I64;
3350 else if (VT == MVT::i128)
3351 LC = RTLIB::SREM_I128;
3352 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported SREM!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3352, __PRETTY_FUNCTION__))
;
3353
3354 TargetLowering::MakeLibCallOptions CallOptions;
3355 CallOptions.setSExt(true);
3356 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3357}
3358
3359void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
3360 SDValue &Lo, SDValue &Hi) {
3361 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3362 SDLoc dl(N);
3363 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
3364 Hi = DAG.getNode(ISD::SRL, dl, N->getOperand(0).getValueType(),
3365 N->getOperand(0),
3366 DAG.getConstant(NVT.getSizeInBits(), dl,
3367 TLI.getPointerTy(DAG.getDataLayout())));
3368 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
3369}
3370
3371void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
3372 SDValue &Lo, SDValue &Hi) {
3373 EVT VT = N->getValueType(0);
3374 SDLoc dl(N);
3375
3376 if (N->getOpcode() == ISD::UMULO) {
3377 // This section expands the operation into the following sequence of
3378 // instructions. `iNh` here refers to a type which has half the bit width of
3379 // the type the original operation operated on.
3380 //
3381 // %0 = %LHS.HI != 0 && %RHS.HI != 0
3382 // %1 = { iNh, i1 } @umul.with.overflow.iNh(iNh %LHS.HI, iNh %RHS.LO)
3383 // %2 = { iNh, i1 } @umul.with.overflow.iNh(iNh %RHS.HI, iNh %LHS.LO)
3384 // %3 = mul nuw iN (%LHS.LOW as iN), (%RHS.LOW as iN)
3385 // %4 = add iN (%1.0 as iN) << Nh, (%2.0 as iN) << Nh
3386 // %5 = { iN, i1 } @uadd.with.overflow.iN( %4, %3 )
3387 //
3388 // %res = { %5.0, %0 || %1.1 || %2.1 || %5.1 }
3389 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
3390 SDValue LHSHigh, LHSLow, RHSHigh, RHSLow;
3391 SplitInteger(LHS, LHSLow, LHSHigh);
3392 SplitInteger(RHS, RHSLow, RHSHigh);
3393 EVT HalfVT = LHSLow.getValueType()
3394 , BitVT = N->getValueType(1);
3395 SDVTList VTHalfMulO = DAG.getVTList(HalfVT, BitVT);
3396 SDVTList VTFullAddO = DAG.getVTList(VT, BitVT);
3397
3398 SDValue HalfZero = DAG.getConstant(0, dl, HalfVT);
3399 SDValue Overflow = DAG.getNode(ISD::AND, dl, BitVT,
3400 DAG.getSetCC(dl, BitVT, LHSHigh, HalfZero, ISD::SETNE),
3401 DAG.getSetCC(dl, BitVT, RHSHigh, HalfZero, ISD::SETNE));
3402
3403 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, LHSHigh, RHSLow);
3404 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, One.getValue(1));
3405 SDValue OneInHigh = DAG.getNode(ISD::BUILD_PAIR, dl, VT, HalfZero,
3406 One.getValue(0));
3407
3408 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, RHSHigh, LHSLow);
3409 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Two.getValue(1));
3410 SDValue TwoInHigh = DAG.getNode(ISD::BUILD_PAIR, dl, VT, HalfZero,
3411 Two.getValue(0));
3412
3413 // Cannot use `UMUL_LOHI` directly, because some 32-bit targets (ARM) do not
3414 // know how to expand `i64,i64 = umul_lohi a, b` and abort (why isn’t this
3415 // operation recursively legalized?).
3416 //
3417 // Many backends understand this pattern and will convert into LOHI
3418 // themselves, if applicable.
3419 SDValue Three = DAG.getNode(ISD::MUL, dl, VT,
3420 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, LHSLow),
3421 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, RHSLow));
3422 SDValue Four = DAG.getNode(ISD::ADD, dl, VT, OneInHigh, TwoInHigh);
3423 SDValue Five = DAG.getNode(ISD::UADDO, dl, VTFullAddO, Three, Four);
3424 Overflow = DAG.getNode(ISD::OR, dl, BitVT, Overflow, Five.getValue(1));
3425 SplitInteger(Five, Lo, Hi);
3426 ReplaceValueWith(SDValue(N, 1), Overflow);
3427 return;
3428 }
3429
3430 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
3431 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
3432 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
3433
3434 // Replace this with a libcall that will check overflow.
3435 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3436 if (VT == MVT::i32)
3437 LC = RTLIB::MULO_I32;
3438 else if (VT == MVT::i64)
3439 LC = RTLIB::MULO_I64;
3440 else if (VT == MVT::i128)
3441 LC = RTLIB::MULO_I128;
3442 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported XMULO!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3442, __PRETTY_FUNCTION__))
;
3443
3444 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
3445 // Temporary for the overflow value, default it to zero.
3446 SDValue Chain =
3447 DAG.getStore(DAG.getEntryNode(), dl, DAG.getConstant(0, dl, PtrVT), Temp,
3448 MachinePointerInfo());
3449
3450 TargetLowering::ArgListTy Args;
3451 TargetLowering::ArgListEntry Entry;
3452 for (const SDValue &Op : N->op_values()) {
3453 EVT ArgVT = Op.getValueType();
3454 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
3455 Entry.Node = Op;
3456 Entry.Ty = ArgTy;
3457 Entry.IsSExt = true;
3458 Entry.IsZExt = false;
3459 Args.push_back(Entry);
3460 }
3461
3462 // Also pass the address of the overflow check.
3463 Entry.Node = Temp;
3464 Entry.Ty = PtrTy->getPointerTo();
3465 Entry.IsSExt = true;
3466 Entry.IsZExt = false;
3467 Args.push_back(Entry);
3468
3469 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
3470
3471 TargetLowering::CallLoweringInfo CLI(DAG);
3472 CLI.setDebugLoc(dl)
3473 .setChain(Chain)
3474 .setLibCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args))
3475 .setSExtResult();
3476
3477 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
3478
3479 SplitInteger(CallInfo.first, Lo, Hi);
3480 SDValue Temp2 =
3481 DAG.getLoad(PtrVT, dl, CallInfo.second, Temp, MachinePointerInfo());
3482 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
3483 DAG.getConstant(0, dl, PtrVT),
3484 ISD::SETNE);
3485 // Use the overflow from the libcall everywhere.
3486 ReplaceValueWith(SDValue(N, 1), Ofl);
3487}
3488
3489void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
3490 SDValue &Lo, SDValue &Hi) {
3491 EVT VT = N->getValueType(0);
3492 SDLoc dl(N);
3493 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3494
3495 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
3496 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3497 SplitInteger(Res.getValue(0), Lo, Hi);
3498 return;
3499 }
3500
3501 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3502 if (VT == MVT::i16)
3503 LC = RTLIB::UDIV_I16;
3504 else if (VT == MVT::i32)
3505 LC = RTLIB::UDIV_I32;
3506 else if (VT == MVT::i64)
3507 LC = RTLIB::UDIV_I64;
3508 else if (VT == MVT::i128)
3509 LC = RTLIB::UDIV_I128;
3510 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported UDIV!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3510, __PRETTY_FUNCTION__))
;
3511
3512 TargetLowering::MakeLibCallOptions CallOptions;
3513 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3514}
3515
3516void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
3517 SDValue &Lo, SDValue &Hi) {
3518 EVT VT = N->getValueType(0);
3519 SDLoc dl(N);
3520 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
3521
3522 if (TLI.getOperationAction(ISD::UDIVREM, VT) == TargetLowering::Custom) {
3523 SDValue Res = DAG.getNode(ISD::UDIVREM, dl, DAG.getVTList(VT, VT), Ops);
3524 SplitInteger(Res.getValue(1), Lo, Hi);
3525 return;
3526 }
3527
3528 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3529 if (VT == MVT::i16)
3530 LC = RTLIB::UREM_I16;
3531 else if (VT == MVT::i32)
3532 LC = RTLIB::UREM_I32;
3533 else if (VT == MVT::i64)
3534 LC = RTLIB::UREM_I64;
3535 else if (VT == MVT::i128)
3536 LC = RTLIB::UREM_I128;
3537 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!")((LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Unsupported UREM!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3537, __PRETTY_FUNCTION__))
;
3538
3539 TargetLowering::MakeLibCallOptions CallOptions;
3540 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, CallOptions, dl).first, Lo, Hi);
3541}
3542
3543void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
3544 SDValue &Lo, SDValue &Hi) {
3545 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3546 SDLoc dl(N);
3547 SDValue Op = N->getOperand(0);
3548 if (Op.getValueType().bitsLE(NVT)) {
3549 // The low part is zero extension of the input (degenerates to a copy).
3550 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
3551 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
3552 } else {
3553 // For example, extension of an i48 to an i64. The operand type necessarily
3554 // promotes to the result type, so will end up being expanded too.
3555 assert(getTypeAction(Op.getValueType()) ==((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3557, __PRETTY_FUNCTION__))
3556 TargetLowering::TypePromoteInteger &&((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3557, __PRETTY_FUNCTION__))
3557 "Only know how to promote this result!")((getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger
&& "Only know how to promote this result!") ? static_cast
<void> (0) : __assert_fail ("getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger && \"Only know how to promote this result!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3557, __PRETTY_FUNCTION__))
;
3558 SDValue Res = GetPromotedInteger(Op);
3559 assert(Res.getValueType() == N->getValueType(0) &&((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3560, __PRETTY_FUNCTION__))
3560 "Operand over promoted?")((Res.getValueType() == N->getValueType(0) && "Operand over promoted?"
) ? static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && \"Operand over promoted?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3560, __PRETTY_FUNCTION__))
;
3561 // Split the promoted operand. This will simplify when it is expanded.
3562 SplitInteger(Res, Lo, Hi);
3563 unsigned ExcessBits = Op.getValueSizeInBits() - NVT.getSizeInBits();
3564 Hi = DAG.getZeroExtendInReg(Hi, dl,
3565 EVT::getIntegerVT(*DAG.getContext(),
3566 ExcessBits));
3567 }
3568}
3569
3570void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
3571 SDValue &Lo, SDValue &Hi) {
3572 SDLoc dl(N);
3573 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
3574 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
3575 SDValue Zero = DAG.getConstant(0, dl, VT);
3576 SDValue Swap = DAG.getAtomicCmpSwap(
3577 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
3578 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
3579 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand());
3580
3581 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
3582 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
3583}
3584
3585void DAGTypeLegalizer::ExpandIntRes_VECREDUCE(SDNode *N,
3586 SDValue &Lo, SDValue &Hi) {
3587 // TODO For VECREDUCE_(AND|OR|XOR) we could split the vector and calculate
3588 // both halves independently.
3589 SDValue Res = TLI.expandVecReduce(N, DAG);
3590 SplitInteger(Res, Lo, Hi);
3591}
3592
3593//===----------------------------------------------------------------------===//
3594// Integer Operand Expansion
3595//===----------------------------------------------------------------------===//
3596
3597/// ExpandIntegerOperand - This method is called when the specified operand of
3598/// the specified node is found to need expansion. At this point, all of the
3599/// result types of the node are known to be legal, but other operands of the
3600/// node may need promotion or expansion as well as the specified one.
3601bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
3602 LLVM_DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
3603 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Expand integer operand: "
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
3604 SDValue Res = SDValue();
3605
3606 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
3607 return false;
3608
3609 switch (N->getOpcode()) {
3610 default:
3611 #ifndef NDEBUG
3612 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
3613 N->dump(&DAG); dbgs() << "\n";
3614 #endif
3615 report_fatal_error("Do not know how to expand this operator's operand!");
3616
3617 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
3618 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
3619 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
3620 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
3621 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
3622 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
3623 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
3624 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
3625 case ISD::SETCCCARRY: Res = ExpandIntOp_SETCCCARRY(N); break;
3626 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
3627 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
3628 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
3629 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
3630
3631 case ISD::SHL:
3632 case ISD::SRA:
3633 case ISD::SRL:
3634 case ISD::ROTL:
3635 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
3636 case ISD::RETURNADDR:
3637 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
3638
3639 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
3640 }
3641
3642 // If the result is null, the sub-method took care of registering results etc.
3643 if (!Res.getNode()) return false;
3644
3645 // If the result is N, the sub-method updated N in place. Tell the legalizer
3646 // core about this.
3647 if (Res.getNode() == N)
3648 return true;
3649
3650 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3651, __PRETTY_FUNCTION__))
3651 "Invalid operand expansion")((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3651, __PRETTY_FUNCTION__))
;
3652
3653 ReplaceValueWith(SDValue(N, 0), Res);
3654 return false;
3655}
3656
3657/// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
3658/// is shared among BR_CC, SELECT_CC, and SETCC handlers.
3659void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
3660 SDValue &NewRHS,
3661 ISD::CondCode &CCCode,
3662 const SDLoc &dl) {
3663 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
3664 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
3665 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
3666
3667 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
3668 if (RHSLo == RHSHi) {
3669 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
3670 if (RHSCST->isAllOnesValue()) {
3671 // Equality comparison to -1.
3672 NewLHS = DAG.getNode(ISD::AND, dl,
3673 LHSLo.getValueType(), LHSLo, LHSHi);
3674 NewRHS = RHSLo;
3675 return;
3676 }
3677 }
3678 }
3679
3680 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
3681 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
3682 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
3683 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
3684 return;
3685 }
3686
3687 // If this is a comparison of the sign bit, just look at the top part.
3688 // X > -1, x < 0
3689 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
3690 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
3691 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
3692 NewLHS = LHSHi;
3693 NewRHS = RHSHi;
3694 return;
3695 }
3696
3697 // FIXME: This generated code sucks.
3698 ISD::CondCode LowCC;
3699 switch (CCCode) {
3700 default: llvm_unreachable("Unknown integer setcc!")::llvm::llvm_unreachable_internal("Unknown integer setcc!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3700)
;
3701 case ISD::SETLT:
3702 case ISD::SETULT: LowCC = ISD::SETULT; break;
3703 case ISD::SETGT:
3704 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3705 case ISD::SETLE:
3706 case ISD::SETULE: LowCC = ISD::SETULE; break;
3707 case ISD::SETGE:
3708 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3709 }
3710
3711 // LoCmp = lo(op1) < lo(op2) // Always unsigned comparison
3712 // HiCmp = hi(op1) < hi(op2) // Signedness depends on operands
3713 // dest = hi(op1) == hi(op2) ? LoCmp : HiCmp;
3714
3715 // NOTE: on targets without efficient SELECT of bools, we can always use
3716 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3717 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
3718 nullptr);
3719 SDValue LoCmp, HiCmp;
3720 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
3721 TLI.isTypeLegal(RHSLo.getValueType()))
3722 LoCmp = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()), LHSLo,
3723 RHSLo, LowCC, false, DagCombineInfo, dl);
3724 if (!LoCmp.getNode())
3725 LoCmp = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()), LHSLo,
3726 RHSLo, LowCC);
3727 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
3728 TLI.isTypeLegal(RHSHi.getValueType()))
3729 HiCmp = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()), LHSHi,
3730 RHSHi, CCCode, false, DagCombineInfo, dl);
3731 if (!HiCmp.getNode())
3732 HiCmp =
3733 DAG.getNode(ISD::SETCC, dl, getSetCCResultType(LHSHi.getValueType()),
3734 LHSHi, RHSHi, DAG.getCondCode(CCCode));
3735
3736 ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(LoCmp.getNode());
3737 ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(HiCmp.getNode());
3738
3739 bool EqAllowed = (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
3740 CCCode == ISD::SETUGE || CCCode == ISD::SETULE);
3741
3742 if ((EqAllowed && (HiCmpC && HiCmpC->isNullValue())) ||
3743 (!EqAllowed && ((HiCmpC && (HiCmpC->getAPIntValue() == 1)) ||
3744 (LoCmpC && LoCmpC->isNullValue())))) {
3745 // For LE / GE, if high part is known false, ignore the low part.
3746 // For LT / GT: if low part is known false, return the high part.
3747 // if high part is known true, ignore the low part.
3748 NewLHS = HiCmp;
3749 NewRHS = SDValue();
3750 return;
3751 }
3752
3753 if (LHSHi == RHSHi) {
3754 // Comparing the low bits is enough.
3755 NewLHS = LoCmp;
3756 NewRHS = SDValue();
3757 return;
3758 }
3759
3760 // Lower with SETCCCARRY if the target supports it.
3761 EVT HiVT = LHSHi.getValueType();
3762 EVT ExpandVT = TLI.getTypeToExpandTo(*DAG.getContext(), HiVT);
3763 bool HasSETCCCARRY = TLI.isOperationLegalOrCustom(ISD::SETCCCARRY, ExpandVT);
3764
3765 // FIXME: Make all targets support this, then remove the other lowering.
3766 if (HasSETCCCARRY) {
3767 // SETCCCARRY can detect < and >= directly. For > and <=, flip
3768 // operands and condition code.
3769 bool FlipOperands = false;
3770 switch (CCCode) {
3771 case ISD::SETGT: CCCode = ISD::SETLT; FlipOperands = true; break;
3772 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break;
3773 case ISD::SETLE: CCCode = ISD::SETGE; FlipOperands = true; break;
3774 case ISD::SETULE: CCCode = ISD::SETUGE; FlipOperands = true; break;
3775 default: break;
3776 }
3777 if (FlipOperands) {
3778 std::swap(LHSLo, RHSLo);
3779 std::swap(LHSHi, RHSHi);
3780 }
3781 // Perform a wide subtraction, feeding the carry from the low part into
3782 // SETCCCARRY. The SETCCCARRY operation is essentially looking at the high
3783 // part of the result of LHS - RHS. It is negative iff LHS < RHS. It is
3784 // zero or positive iff LHS >= RHS.
3785 EVT LoVT = LHSLo.getValueType();
3786 SDVTList VTList = DAG.getVTList(LoVT, getSetCCResultType(LoVT));
3787 SDValue LowCmp = DAG.getNode(ISD::USUBO, dl, VTList, LHSLo, RHSLo);
3788 SDValue Res = DAG.getNode(ISD::SETCCCARRY, dl, getSetCCResultType(HiVT),
3789 LHSHi, RHSHi, LowCmp.getValue(1),
3790 DAG.getCondCode(CCCode));
3791 NewLHS = Res;
3792 NewRHS = SDValue();
3793 return;
3794 }
3795
3796 NewLHS = TLI.SimplifySetCC(getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ,
3797 false, DagCombineInfo, dl);
3798 if (!NewLHS.getNode())
3799 NewLHS =
3800 DAG.getSetCC(dl, getSetCCResultType(HiVT), LHSHi, RHSHi, ISD::SETEQ);
3801 NewLHS = DAG.getSelect(dl, LoCmp.getValueType(), NewLHS, LoCmp, HiCmp);
3802 NewRHS = SDValue();
3803}
3804
3805SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
3806 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
3807 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
3808 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
3809
3810 // If ExpandSetCCOperands returned a scalar, we need to compare the result
3811 // against zero to select between true and false values.
3812 if (!NewRHS.getNode()) {
3813 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
3814 CCCode = ISD::SETNE;
3815 }
3816
3817 // Update N to have the operands specified.
3818 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
3819 DAG.getCondCode(CCCode), NewLHS, NewRHS,
3820 N->getOperand(4)), 0);
3821}
3822
3823SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
3824 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
3825 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
3826 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
3827
3828 // If ExpandSetCCOperands returned a scalar, we need to compare the result
3829 // against zero to select between true and false values.
3830 if (!NewRHS.getNode()) {
3831 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
3832 CCCode = ISD::SETNE;
3833 }
3834
3835 // Update N to have the operands specified.
3836 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
3837 N->getOperand(2), N->getOperand(3),
3838 DAG.getCondCode(CCCode)), 0);
3839}
3840
3841SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
3842 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
3843 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
3844 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
3845
3846 // If ExpandSetCCOperands returned a scalar, use it.
3847 if (!NewRHS.getNode()) {
3848 assert(NewLHS.getValueType() == N->getValueType(0) &&((NewLHS.getValueType() == N->getValueType(0) && "Unexpected setcc expansion!"
) ? static_cast<void> (0) : __assert_fail ("NewLHS.getValueType() == N->getValueType(0) && \"Unexpected setcc expansion!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3849, __PRETTY_FUNCTION__))
3849 "Unexpected setcc expansion!")((NewLHS.getValueType() == N->getValueType(0) && "Unexpected setcc expansion!"
) ? static_cast<void> (0) : __assert_fail ("NewLHS.getValueType() == N->getValueType(0) && \"Unexpected setcc expansion!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3849, __PRETTY_FUNCTION__))
;
3850 return NewLHS;
3851 }
3852
3853 // Otherwise, update N to have the operands specified.
3854 return SDValue(
3855 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0);
3856}
3857
3858SDValue DAGTypeLegalizer::ExpandIntOp_SETCCCARRY(SDNode *N) {
3859 SDValue LHS = N->getOperand(0);
3860 SDValue RHS = N->getOperand(1);
3861 SDValue Carry = N->getOperand(2);
3862 SDValue Cond = N->getOperand(3);
3863 SDLoc dl = SDLoc(N);
3864
3865 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
3866 GetExpandedInteger(LHS, LHSLo, LHSHi);
3867 GetExpandedInteger(RHS, RHSLo, RHSHi);
3868
3869 // Expand to a SUBE for the low part and a smaller SETCCCARRY for the high.
3870 SDVTList VTList = DAG.getVTList(LHSLo.getValueType(), Carry.getValueType());
3871 SDValue LowCmp = DAG.getNode(ISD::SUBCARRY, dl, VTList, LHSLo, RHSLo, Carry);
3872 return DAG.getNode(ISD::SETCCCARRY, dl, N->getValueType(0), LHSHi, RHSHi,
3873 LowCmp.getValue(1), Cond);
3874}
3875
3876SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
3877 // The value being shifted is legal, but the shift amount is too big.
3878 // It follows that either the result of the shift is undefined, or the
3879 // upper half of the shift amount is zero. Just use the lower half.
3880 SDValue Lo, Hi;
3881 GetExpandedInteger(N->getOperand(1), Lo, Hi);
3882 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
3883}
3884
3885SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
3886 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
3887 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
3888 // constant to valid type.
3889 SDValue Lo, Hi;
3890 GetExpandedInteger(N->getOperand(0), Lo, Hi);
3891 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
3892}
3893
3894SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
3895 SDValue Op = N->getOperand(0);
3896 EVT DstVT = N->getValueType(0);
3897 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
3898 assert(LC != RTLIB::UNKNOWN_LIBCALL &&((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this SINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this SINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3899, __PRETTY_FUNCTION__))
3899 "Don't know how to expand this SINT_TO_FP!")((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this SINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this SINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3899, __PRETTY_FUNCTION__))
;
3900 TargetLowering::MakeLibCallOptions CallOptions;
3901 CallOptions.setSExt(true);
3902 return TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, SDLoc(N)).first;
3903}
3904
3905SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
3906 if (N->isAtomic()) {
3907 // It's typical to have larger CAS than atomic store instructions.
3908 SDLoc dl(N);
3909 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3910 N->getMemoryVT(),
3911 N->getOperand(0), N->getOperand(2),
3912 N->getOperand(1),
3913 N->getMemOperand());
3914 return Swap.getValue(1);
3915 }
3916 if (ISD::isNormalStore(N))
3917 return ExpandOp_NormalStore(N, OpNo);
3918
3919 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!")((ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDStore(N) && \"Indexed store during type legalization!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3919, __PRETTY_FUNCTION__))
;
3920 assert(OpNo == 1 && "Can only expand the stored value so far")((OpNo == 1 && "Can only expand the stored value so far"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 1 && \"Can only expand the stored value so far\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3920, __PRETTY_FUNCTION__))
;
3921
3922 EVT VT = N->getOperand(1).getValueType();
3923 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3924 SDValue Ch = N->getChain();
3925 SDValue Ptr = N->getBasePtr();
3926 unsigned Alignment = N->getAlignment();
3927 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
3928 AAMDNodes AAInfo = N->getAAInfo();
3929 SDLoc dl(N);
3930 SDValue Lo, Hi;
3931
3932 assert(NVT.isByteSized() && "Expanded type not byte sized!")((NVT.isByteSized() && "Expanded type not byte sized!"
) ? static_cast<void> (0) : __assert_fail ("NVT.isByteSized() && \"Expanded type not byte sized!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 3932, __PRETTY_FUNCTION__))
;
3933
3934 if (N->getMemoryVT().bitsLE(NVT)) {
3935 GetExpandedInteger(N->getValue(), Lo, Hi);
3936 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
3937 N->getMemoryVT(), Alignment, MMOFlags, AAInfo);
3938 }
3939
3940 if (DAG.getDataLayout().isLittleEndian()) {
3941 // Little-endian - low bits are at low addresses.
3942 GetExpandedInteger(N->getValue(), Lo, Hi);
3943
3944 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
3945 AAInfo);
3946
3947 unsigned ExcessBits =
3948 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
3949 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
3950
3951 // Increment the pointer to the other half.
3952 unsigned IncrementSize = NVT.getSizeInBits()/8;
3953 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
3954 Hi = DAG.getTruncStore(
3955 Ch, dl, Hi, Ptr, N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
3956 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
3957 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
3958 }
3959
3960 // Big-endian - high bits are at low addresses. Favor aligned stores at
3961 // the cost of some bit-fiddling.
3962 GetExpandedInteger(N->getValue(), Lo, Hi);
3963
3964 EVT ExtVT = N->getMemoryVT();
3965 unsigned EBytes = ExtVT.getStoreSize();
3966 unsigned IncrementSize = NVT.getSizeInBits()/8;
3967 unsigned ExcessBits = (EBytes - IncrementSize)*8;
3968 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
3969 ExtVT.getSizeInBits() - ExcessBits);
3970
3971 if (ExcessBits < NVT.getSizeInBits()) {
3972 // Transfer high bits from the top of Lo to the bottom of Hi.
3973 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
3974 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
3975 TLI.getPointerTy(DAG.getDataLayout())));
3976 Hi = DAG.getNode(
3977 ISD::OR, dl, NVT, Hi,
3978 DAG.getNode(ISD::SRL, dl, NVT, Lo,
3979 DAG.getConstant(ExcessBits, dl,
3980 TLI.getPointerTy(DAG.getDataLayout()))));
3981 }
3982
3983 // Store both the high bits and maybe some of the low bits.
3984 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(), HiVT, Alignment,
3985 MMOFlags, AAInfo);
3986
3987 // Increment the pointer to the other half.
3988 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
3989 // Store the lowest ExcessBits bits in the second half.
3990 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
3991 N->getPointerInfo().getWithOffset(IncrementSize),
3992 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
3993 MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo);
3994 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
3995}
3996
3997SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
3998 SDValue InL, InH;
3999 GetExpandedInteger(N->getOperand(0), InL, InH);
4000 // Just truncate the low part of the source.
4001 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
4002}
4003
4004SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
4005 SDValue Op = N->getOperand(0);
4006 EVT SrcVT = Op.getValueType();
4007 EVT DstVT = N->getValueType(0);
4008 SDLoc dl(N);
4009
4010 // The following optimization is valid only if every value in SrcVT (when
4011 // treated as signed) is representable in DstVT. Check that the mantissa
4012 // size of DstVT is >= than the number of bits in SrcVT -1.
4013 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
4014 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
4015 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
4016 // Do a signed conversion then adjust the result.
4017 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
4018 SignedConv = TLI.LowerOperation(SignedConv, DAG);
4019
4020 // The result of the signed conversion needs adjusting if the 'sign bit' of
4021 // the incoming integer was set. To handle this, we dynamically test to see
4022 // if it is set, and, if so, add a fudge factor.
4023
4024 const uint64_t F32TwoE32 = 0x4F800000ULL;
4025 const uint64_t F32TwoE64 = 0x5F800000ULL;
4026 const uint64_t F32TwoE128 = 0x7F800000ULL;
4027
4028 APInt FF(32, 0);
4029 if (SrcVT == MVT::i32)
4030 FF = APInt(32, F32TwoE32);
4031 else if (SrcVT == MVT::i64)
4032 FF = APInt(32, F32TwoE64);
4033 else if (SrcVT == MVT::i128)
4034 FF = APInt(32, F32TwoE128);
4035 else
4036 llvm_unreachable("Unsupported UINT_TO_FP!")::llvm::llvm_unreachable_internal("Unsupported UINT_TO_FP!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4036)
;
4037
4038 // Check whether the sign bit is set.
4039 SDValue Lo, Hi;
4040 GetExpandedInteger(Op, Lo, Hi);
4041 SDValue SignSet = DAG.getSetCC(dl,
4042 getSetCCResultType(Hi.getValueType()),
4043 Hi,
4044 DAG.getConstant(0, dl, Hi.getValueType()),
4045 ISD::SETLT);
4046
4047 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
4048 SDValue FudgePtr =
4049 DAG.getConstantPool(ConstantInt::get(*DAG.getContext(), FF.zext(64)),
4050 TLI.getPointerTy(DAG.getDataLayout()));
4051
4052 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
4053 SDValue Zero = DAG.getIntPtrConstant(0, dl);
4054 SDValue Four = DAG.getIntPtrConstant(4, dl);
4055 if (DAG.getDataLayout().isBigEndian())
4056 std::swap(Zero, Four);
4057 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
4058 Zero, Four);
4059 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
4060 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
4061 FudgePtr, Offset);
4062 Alignment = std::min(Alignment, 4u);
4063
4064 // Load the value out, extending it from f32 to the destination float type.
4065 // FIXME: Avoid the extend by constructing the right constant pool?
4066 SDValue Fudge = DAG.getExtLoad(
4067 ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), FudgePtr,
4068 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
4069 Alignment);
4070 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
4071 }
4072
4073 // Otherwise, use a libcall.
4074 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
4075 assert(LC != RTLIB::UNKNOWN_LIBCALL &&((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this UINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this UINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4076, __PRETTY_FUNCTION__))
4076 "Don't know how to expand this UINT_TO_FP!")((LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this UINT_TO_FP!"
) ? static_cast<void> (0) : __assert_fail ("LC != RTLIB::UNKNOWN_LIBCALL && \"Don't know how to expand this UINT_TO_FP!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4076, __PRETTY_FUNCTION__))
;
4077 TargetLowering::MakeLibCallOptions CallOptions;
4078 CallOptions.setSExt(true);
4079 return TLI.makeLibCall(DAG, LC, DstVT, Op, CallOptions, dl).first;
4080}
4081
4082SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
4083 SDLoc dl(N);
4084 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
4085 cast<AtomicSDNode>(N)->getMemoryVT(),
4086 N->getOperand(0),
4087 N->getOperand(1), N->getOperand(2),
4088 cast<AtomicSDNode>(N)->getMemOperand());
4089 return Swap.getValue(1);
4090}
4091
4092
4093SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
4094
4095 EVT OutVT = N->getValueType(0);
4096 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4097 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4097, __PRETTY_FUNCTION__))
;
4098 unsigned OutNumElems = OutVT.getVectorNumElements();
4099 EVT NOutVTElem = NOutVT.getVectorElementType();
4100
4101 SDLoc dl(N);
4102 SDValue BaseIdx = N->getOperand(1);
4103
4104 SDValue InOp0 = N->getOperand(0);
4105 if (getTypeAction(InOp0.getValueType()) == TargetLowering::TypePromoteInteger)
4106 InOp0 = GetPromotedInteger(N->getOperand(0));
4107
4108 EVT InVT = InOp0.getValueType();
4109
4110 SmallVector<SDValue, 8> Ops;
4111 Ops.reserve(OutNumElems);
4112 for (unsigned i = 0; i != OutNumElems; ++i) {
4113
4114 // Extract the element from the original vector.
4115 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
4116 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
4117 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4118 InVT.getVectorElementType(), N->getOperand(0), Index);
4119
4120 SDValue Op = DAG.getAnyExtOrTrunc(Ext, dl, NOutVTElem);
4121 // Insert the converted element to the new vector.
4122 Ops.push_back(Op);
4123 }
4124
4125 return DAG.getBuildVector(NOutVT, dl, Ops);
4126}
4127
4128
4129SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
4130 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
4131 EVT VT = N->getValueType(0);
4132 SDLoc dl(N);
4133
4134 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
4135
4136 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4137 SDValue V1 = GetPromotedInteger(N->getOperand(1));
4138 EVT OutVT = V0.getValueType();
4139
4140 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
4141}
4142
4143
4144SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
4145 EVT OutVT = N->getValueType(0);
4146 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4147 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4147, __PRETTY_FUNCTION__))
;
4148 unsigned NumElems = N->getNumOperands();
4149 EVT NOutVTElem = NOutVT.getVectorElementType();
4150
4151 SDLoc dl(N);
4152
4153 SmallVector<SDValue, 8> Ops;
4154 Ops.reserve(NumElems);
4155 for (unsigned i = 0; i != NumElems; ++i) {
4156 SDValue Op;
4157 // BUILD_VECTOR integer operand types are allowed to be larger than the
4158 // result's element type. This may still be true after the promotion. For
4159 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
4160 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
4161 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
4162 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
4163 else
4164 Op = N->getOperand(i);
4165 Ops.push_back(Op);
4166 }
4167
4168 return DAG.getBuildVector(NOutVT, dl, Ops);
4169}
4170
4171SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
4172
4173 SDLoc dl(N);
4174
4175 assert(!N->getOperand(0).getValueType().isVector() &&((!N->getOperand(0).getValueType().isVector() && "Input must be a scalar"
) ? static_cast<void> (0) : __assert_fail ("!N->getOperand(0).getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4176, __PRETTY_FUNCTION__))
4176 "Input must be a scalar")((!N->getOperand(0).getValueType().isVector() && "Input must be a scalar"
) ? static_cast<void> (0) : __assert_fail ("!N->getOperand(0).getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4176, __PRETTY_FUNCTION__))
;
4177
4178 EVT OutVT = N->getValueType(0);
4179 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4180 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4180, __PRETTY_FUNCTION__))
;
4181 EVT NOutVTElem = NOutVT.getVectorElementType();
4182
4183 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
4184
4185 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
4186}
4187
4188SDValue DAGTypeLegalizer::PromoteIntRes_SPLAT_VECTOR(SDNode *N) {
4189 SDLoc dl(N);
4190
4191 SDValue SplatVal = N->getOperand(0);
4192
4193 assert(!SplatVal.getValueType().isVector() && "Input must be a scalar")((!SplatVal.getValueType().isVector() && "Input must be a scalar"
) ? static_cast<void> (0) : __assert_fail ("!SplatVal.getValueType().isVector() && \"Input must be a scalar\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4193, __PRETTY_FUNCTION__))
;
4194
4195 EVT OutVT = N->getValueType(0);
4196 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4197 assert(NOutVT.isVector() && "Type must be promoted to a vector type")((NOutVT.isVector() && "Type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"Type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4197, __PRETTY_FUNCTION__))
;
4198 EVT NOutElemVT = NOutVT.getVectorElementType();
4199
4200 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutElemVT, SplatVal);
4201
4202 return DAG.getNode(ISD::SPLAT_VECTOR, dl, NOutVT, Op);
4203}
4204
4205SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
4206 SDLoc dl(N);
4207
4208 EVT OutVT = N->getValueType(0);
4209 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4210 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4210, __PRETTY_FUNCTION__))
;
4211
4212 EVT OutElemTy = NOutVT.getVectorElementType();
4213
4214 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
4215 unsigned NumOutElem = NOutVT.getVectorNumElements();
4216 unsigned NumOperands = N->getNumOperands();
4217 assert(NumElem * NumOperands == NumOutElem &&((NumElem * NumOperands == NumOutElem && "Unexpected number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElem * NumOperands == NumOutElem && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4218, __PRETTY_FUNCTION__))
4218 "Unexpected number of elements")((NumElem * NumOperands == NumOutElem && "Unexpected number of elements"
) ? static_cast<void> (0) : __assert_fail ("NumElem * NumOperands == NumOutElem && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4218, __PRETTY_FUNCTION__))
;
4219
4220 // Take the elements from the first vector.
4221 SmallVector<SDValue, 8> Ops(NumOutElem);
4222 for (unsigned i = 0; i < NumOperands; ++i) {
4223 SDValue Op = N->getOperand(i);
4224 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteInteger)
4225 Op = GetPromotedInteger(Op);
4226 EVT SclrTy = Op.getValueType().getVectorElementType();
4227 assert(NumElem == Op.getValueType().getVectorNumElements() &&((NumElem == Op.getValueType().getVectorNumElements() &&
"Unexpected number of elements") ? static_cast<void> (
0) : __assert_fail ("NumElem == Op.getValueType().getVectorNumElements() && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4228, __PRETTY_FUNCTION__))
4228 "Unexpected number of elements")((NumElem == Op.getValueType().getVectorNumElements() &&
"Unexpected number of elements") ? static_cast<void> (
0) : __assert_fail ("NumElem == Op.getValueType().getVectorNumElements() && \"Unexpected number of elements\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4228, __PRETTY_FUNCTION__))
;
4229
4230 for (unsigned j = 0; j < NumElem; ++j) {
4231 SDValue Ext = DAG.getNode(
4232 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op,
4233 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4234 Ops[i * NumElem + j] = DAG.getAnyExtOrTrunc(Ext, dl, OutElemTy);
4235 }
4236 }
4237
4238 return DAG.getBuildVector(NOutVT, dl, Ops);
4239}
4240
4241SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
4242 EVT VT = N->getValueType(0);
4243 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
4244 assert(NVT.isVector() && "This type must be promoted to a vector type")((NVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4244, __PRETTY_FUNCTION__))
;
4245
4246 SDLoc dl(N);
4247
4248 // For operands whose TypeAction is to promote, extend the promoted node
4249 // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
4250 // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
4251 // type..
4252 if (getTypeAction(N->getOperand(0).getValueType())
4253 == TargetLowering::TypePromoteInteger) {
4254 SDValue Promoted;
4255
4256 switch(N->getOpcode()) {
4257 case ISD::SIGN_EXTEND_VECTOR_INREG:
4258 Promoted = SExtPromotedInteger(N->getOperand(0));
4259 break;
4260 case ISD::ZERO_EXTEND_VECTOR_INREG:
4261 Promoted = ZExtPromotedInteger(N->getOperand(0));
4262 break;
4263 case ISD::ANY_EXTEND_VECTOR_INREG:
4264 Promoted = GetPromotedInteger(N->getOperand(0));
4265 break;
4266 default:
4267 llvm_unreachable("Node has unexpected Opcode")::llvm::llvm_unreachable_internal("Node has unexpected Opcode"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4267)
;
4268 }
4269 return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
4270 }
4271
4272 // Directly extend to the appropriate transform-to type.
4273 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
4274}
4275
4276SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
4277 EVT OutVT = N->getValueType(0);
4278 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
4279 assert(NOutVT.isVector() && "This type must be promoted to a vector type")((NOutVT.isVector() && "This type must be promoted to a vector type"
) ? static_cast<void> (0) : __assert_fail ("NOutVT.isVector() && \"This type must be promoted to a vector type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp"
, 4279, __PRETTY_FUNCTION__))
;
4280
4281 EVT NOutVTElem = NOutVT.getVectorElementType();
4282
4283 SDLoc dl(N);
4284 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4285
4286 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
4287 NOutVTElem, N->getOperand(1));
4288 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
4289 V0, ConvElem, N->getOperand(2));
4290}
4291
4292SDValue DAGTypeLegalizer::PromoteIntRes_VECREDUCE(SDNode *N) {
4293 // The VECREDUCE result size may be larger than the element size, so
4294 // we can simply change the result type.
4295 SDLoc dl(N);
4296 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
4297 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
4298}
4299
4300SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
4301 SDLoc dl(N);
4302 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4303 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl,
4304 TLI.getVectorIdxTy(DAG.getDataLayout()));
4305 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4306 V0->getValueType(0).getScalarType(), V0, V1);
4307
4308 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
4309 // element types. If this is the case then we need to expand the outgoing
4310 // value and not truncate it.
4311 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
4312}
4313
4314SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_SUBVECTOR(SDNode *N) {
4315 SDLoc dl(N);
4316 SDValue V0 = GetPromotedInteger(N->getOperand(0));
4317 MVT InVT = V0.getValueType().getSimpleVT();
4318 MVT OutVT = MVT::getVectorVT(InVT.getVectorElementType(),
4319 N->getValueType(0).getVectorNumElements());
4320 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1));
4321 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
4322}
4323
4324SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
4325 SDLoc dl(N);
4326 unsigned NumElems = N->getNumOperands();
4327
4328 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
4329
4330 SmallVector<SDValue, 8> NewOps;
4331 NewOps.reserve(NumElems);
4332
4333 // For each incoming vector
4334 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
4335 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
4336 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
4337 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
4338
4339 for (unsigned i=0; i<NumElem; ++i) {
4340 // Extract element from incoming vector
4341 SDValue Ex = DAG.getNode(
4342 ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming,
4343 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4344 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
4345 NewOps.push_back(Tr);
4346 }
4347 }
4348
4349 return DAG.getBuildVector(N->getValueType(0), dl, NewOps);
4350}

/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG. These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H
20
21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/Constants.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Instruction.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/Metadata.h"
39#include "llvm/IR/Operator.h"
40#include "llvm/Support/AlignOf.h"
41#include "llvm/Support/AtomicOrdering.h"
42#include "llvm/Support/Casting.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MachineValueType.h"
45#include <algorithm>
46#include <cassert>
47#include <climits>
48#include <cstddef>
49#include <cstdint>
50#include <cstring>
51#include <iterator>
52#include <string>
53#include <tuple>
54
55namespace llvm {
56
57class APInt;
58class Constant;
59template <typename T> struct DenseMapInfo;
60class GlobalValue;
61class MachineBasicBlock;
62class MachineConstantPoolValue;
63class MCSymbol;
64class raw_ostream;
65class SDNode;
66class SelectionDAG;
67class Type;
68class Value;
69
70void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
71 bool force = false);
72
73/// This represents a list of ValueType's that has been intern'd by
74/// a SelectionDAG. Instances of this simple value class are returned by
75/// SelectionDAG::getVTList(...).
76///
77struct SDVTList {
78 const EVT *VTs;
79 unsigned int NumVTs;
80};
81
82namespace ISD {
83
84 /// Node predicates
85
86 /// If N is a BUILD_VECTOR node whose elements are all the same constant or
87 /// undefined, return true and return the constant value in \p SplatValue.
88 bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
89
90 /// Return true if the specified node is a BUILD_VECTOR where all of the
91 /// elements are ~0 or undef.
92 bool isBuildVectorAllOnes(const SDNode *N);
93
94 /// Return true if the specified node is a BUILD_VECTOR where all of the
95 /// elements are 0 or undef.
96 bool isBuildVectorAllZeros(const SDNode *N);
97
98 /// Return true if the specified node is a BUILD_VECTOR node of all
99 /// ConstantSDNode or undef.
100 bool isBuildVectorOfConstantSDNodes(const SDNode *N);
101
102 /// Return true if the specified node is a BUILD_VECTOR node of all
103 /// ConstantFPSDNode or undef.
104 bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
105
106 /// Return true if the node has at least one operand and all operands of the
107 /// specified node are ISD::UNDEF.
108 bool allOperandsUndef(const SDNode *N);
109
110} // end namespace ISD
111
112//===----------------------------------------------------------------------===//
113/// Unlike LLVM values, Selection DAG nodes may return multiple
114/// values as the result of a computation. Many nodes return multiple values,
115/// from loads (which define a token and a return value) to ADDC (which returns
116/// a result and a carry value), to calls (which may return an arbitrary number
117/// of values).
118///
119/// As such, each use of a SelectionDAG computation must indicate the node that
120/// computes it as well as which return value to use from that node. This pair
121/// of information is represented with the SDValue value type.
122///
123class SDValue {
124 friend struct DenseMapInfo<SDValue>;
125
126 SDNode *Node = nullptr; // The node defining the value we are using.
127 unsigned ResNo = 0; // Which return value of the node we are using.
128
129public:
130 SDValue() = default;
131 SDValue(SDNode *node, unsigned resno);
132
133 /// get the index which selects a specific result in the SDNode
134 unsigned getResNo() const { return ResNo; }
135
136 /// get the SDNode which holds the desired result
137 SDNode *getNode() const { return Node; }
138
139 /// set the SDNode
140 void setNode(SDNode *N) { Node = N; }
141
142 inline SDNode *operator->() const { return Node; }
143
144 bool operator==(const SDValue &O) const {
145 return Node == O.Node && ResNo == O.ResNo;
146 }
147 bool operator!=(const SDValue &O) const {
148 return !operator==(O);
149 }
150 bool operator<(const SDValue &O) const {
151 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
152 }
153 explicit operator bool() const {
154 return Node != nullptr;
155 }
156
157 SDValue getValue(unsigned R) const {
158 return SDValue(Node, R);
159 }
160
161 /// Return true if this node is an operand of N.
162 bool isOperandOf(const SDNode *N) const;
163
164 /// Return the ValueType of the referenced return value.
165 inline EVT getValueType() const;
166
167 /// Return the simple ValueType of the referenced return value.
168 MVT getSimpleValueType() const {
169 return getValueType().getSimpleVT();
170 }
171
172 /// Returns the size of the value in bits.
173 unsigned getValueSizeInBits() const {
174 return getValueType().getSizeInBits();
175 }
176
177 unsigned getScalarValueSizeInBits() const {
178 return getValueType().getScalarType().getSizeInBits();
179 }
180
181 // Forwarding methods - These forward to the corresponding methods in SDNode.
182 inline unsigned getOpcode() const;
183 inline unsigned getNumOperands() const;
184 inline const SDValue &getOperand(unsigned i) const;
185 inline uint64_t getConstantOperandVal(unsigned i) const;
186 inline const APInt &getConstantOperandAPInt(unsigned i) const;
187 inline bool isTargetMemoryOpcode() const;
188 inline bool isTargetOpcode() const;
189 inline bool isMachineOpcode() const;
190 inline bool isUndef() const;
191 inline unsigned getMachineOpcode() const;
192 inline const DebugLoc &getDebugLoc() const;
193 inline void dump() const;
194 inline void dump(const SelectionDAG *G) const;
195 inline void dumpr() const;
196 inline void dumpr(const SelectionDAG *G) const;
197
198 /// Return true if this operand (which must be a chain) reaches the
199 /// specified operand without crossing any side-effecting instructions.
200 /// In practice, this looks through token factors and non-volatile loads.
201 /// In order to remain efficient, this only
202 /// looks a couple of nodes in, it does not do an exhaustive search.
203 bool reachesChainWithoutSideEffects(SDValue Dest,
204 unsigned Depth = 2) const;
205
206 /// Return true if there are no nodes using value ResNo of Node.
207 inline bool use_empty() const;
208
209 /// Return true if there is exactly one node using value ResNo of Node.
210 inline bool hasOneUse() const;
211};
212
213template<> struct DenseMapInfo<SDValue> {
214 static inline SDValue getEmptyKey() {
215 SDValue V;
216 V.ResNo = -1U;
217 return V;
218 }
219
220 static inline SDValue getTombstoneKey() {
221 SDValue V;
222 V.ResNo = -2U;
223 return V;
224 }
225
226 static unsigned getHashValue(const SDValue &Val) {
227 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
228 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
229 }
230
231 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
232 return LHS == RHS;
233 }
234};
235
236/// Allow casting operators to work directly on
237/// SDValues as if they were SDNode*'s.
238template<> struct simplify_type<SDValue> {
239 using SimpleType = SDNode *;
240
241 static SimpleType getSimplifiedValue(SDValue &Val) {
242 return Val.getNode();
243 }
244};
245template<> struct simplify_type<const SDValue> {
246 using SimpleType = /*const*/ SDNode *;
247
248 static SimpleType getSimplifiedValue(const SDValue &Val) {
249 return Val.getNode();
250 }
251};
252
253/// Represents a use of a SDNode. This class holds an SDValue,
254/// which records the SDNode being used and the result number, a
255/// pointer to the SDNode using the value, and Next and Prev pointers,
256/// which link together all the uses of an SDNode.
257///
258class SDUse {
259 /// Val - The value being used.
260 SDValue Val;
261 /// User - The user of this value.
262 SDNode *User = nullptr;
263 /// Prev, Next - Pointers to the uses list of the SDNode referred by
264 /// this operand.
265 SDUse **Prev = nullptr;
266 SDUse *Next = nullptr;
267
268public:
269 SDUse() = default;
270 SDUse(const SDUse &U) = delete;
271 SDUse &operator=(const SDUse &) = delete;
272
273 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
274 operator const SDValue&() const { return Val; }
275
276 /// If implicit conversion to SDValue doesn't work, the get() method returns
277 /// the SDValue.
278 const SDValue &get() const { return Val; }
279
280 /// This returns the SDNode that contains this Use.
281 SDNode *getUser() { return User; }
282
283 /// Get the next SDUse in the use list.
284 SDUse *getNext() const { return Next; }
285
286 /// Convenience function for get().getNode().
287 SDNode *getNode() const { return Val.getNode(); }
288 /// Convenience function for get().getResNo().
289 unsigned getResNo() const { return Val.getResNo(); }
290 /// Convenience function for get().getValueType().
291 EVT getValueType() const { return Val.getValueType(); }
292
293 /// Convenience function for get().operator==
294 bool operator==(const SDValue &V) const {
295 return Val == V;
296 }
297
298 /// Convenience function for get().operator!=
299 bool operator!=(const SDValue &V) const {
300 return Val != V;
301 }
302
303 /// Convenience function for get().operator<
304 bool operator<(const SDValue &V) const {
305 return Val < V;
306 }
307
308private:
309 friend class SelectionDAG;
310 friend class SDNode;
311 // TODO: unfriend HandleSDNode once we fix its operand handling.
312 friend class HandleSDNode;
313
314 void setUser(SDNode *p) { User = p; }
315
316 /// Remove this use from its existing use list, assign it the
317 /// given value, and add it to the new value's node's use list.
318 inline void set(const SDValue &V);
319 /// Like set, but only supports initializing a newly-allocated
320 /// SDUse with a non-null value.
321 inline void setInitial(const SDValue &V);
322 /// Like set, but only sets the Node portion of the value,
323 /// leaving the ResNo portion unmodified.
324 inline void setNode(SDNode *N);
325
326 void addToList(SDUse **List) {
327 Next = *List;
328 if (Next) Next->Prev = &Next;
329 Prev = List;
330 *List = this;
331 }
332
333 void removeFromList() {
334 *Prev = Next;
335 if (Next) Next->Prev = Prev;
336 }
337};
338
339/// simplify_type specializations - Allow casting operators to work directly on
340/// SDValues as if they were SDNode*'s.
341template<> struct simplify_type<SDUse> {
342 using SimpleType = SDNode *;
343
344 static SimpleType getSimplifiedValue(SDUse &Val) {
345 return Val.getNode();
346 }
347};
348
349/// These are IR-level optimization flags that may be propagated to SDNodes.
350/// TODO: This data structure should be shared by the IR optimizer and the
351/// the backend.
352struct SDNodeFlags {
353private:
354 // This bit is used to determine if the flags are in a defined state.
355 // Flag bits can only be masked out during intersection if the masking flags
356 // are defined.
357 bool AnyDefined : 1;
358
359 bool NoUnsignedWrap : 1;
360 bool NoSignedWrap : 1;
361 bool Exact : 1;
362 bool NoNaNs : 1;
363 bool NoInfs : 1;
364 bool NoSignedZeros : 1;
365 bool AllowReciprocal : 1;
366 bool VectorReduction : 1;
367 bool AllowContract : 1;
368 bool ApproximateFuncs : 1;
369 bool AllowReassociation : 1;
370
371 // We assume instructions do not raise floating-point exceptions by default,
372 // and only those marked explicitly may do so. We could choose to represent
373 // this via a positive "FPExcept" flags like on the MI level, but having a
374 // negative "NoFPExcept" flag here (that defaults to true) makes the flag
375 // intersection logic more straightforward.
376 bool NoFPExcept : 1;
377
378public:
379 /// Default constructor turns off all optimization flags.
380 SDNodeFlags()
381 : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
382 Exact(false), NoNaNs(false), NoInfs(false),
383 NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
384 AllowContract(false), ApproximateFuncs(false),
385 AllowReassociation(false), NoFPExcept(true) {}
386
387 /// Propagate the fast-math-flags from an IR FPMathOperator.
388 void copyFMF(const FPMathOperator &FPMO) {
389 setNoNaNs(FPMO.hasNoNaNs());
390 setNoInfs(FPMO.hasNoInfs());
391 setNoSignedZeros(FPMO.hasNoSignedZeros());
392 setAllowReciprocal(FPMO.hasAllowReciprocal());
393 setAllowContract(FPMO.hasAllowContract());
394 setApproximateFuncs(FPMO.hasApproxFunc());
395 setAllowReassociation(FPMO.hasAllowReassoc());
396 }
397
398 /// Sets the state of the flags to the defined state.
399 void setDefined() { AnyDefined = true; }
400 /// Returns true if the flags are in a defined state.
401 bool isDefined() const { return AnyDefined; }
402
403 // These are mutators for each flag.
404 void setNoUnsignedWrap(bool b) {
405 setDefined();
406 NoUnsignedWrap = b;
407 }
408 void setNoSignedWrap(bool b) {
409 setDefined();
410 NoSignedWrap = b;
411 }
412 void setExact(bool b) {
413 setDefined();
414 Exact = b;
415 }
416 void setNoNaNs(bool b) {
417 setDefined();
418 NoNaNs = b;
419 }
420 void setNoInfs(bool b) {
421 setDefined();
422 NoInfs = b;
423 }
424 void setNoSignedZeros(bool b) {
425 setDefined();
426 NoSignedZeros = b;
427 }
428 void setAllowReciprocal(bool b) {
429 setDefined();
430 AllowReciprocal = b;
431 }
432 void setVectorReduction(bool b) {
433 setDefined();
434 VectorReduction = b;
435 }
436 void setAllowContract(bool b) {
437 setDefined();
438 AllowContract = b;
439 }
440 void setApproximateFuncs(bool b) {
441 setDefined();
442 ApproximateFuncs = b;
443 }
444 void setAllowReassociation(bool b) {
445 setDefined();
446 AllowReassociation = b;
447 }
448 void setFPExcept(bool b) {
449 setDefined();
450 NoFPExcept = !b;
451 }
452
453 // These are accessors for each flag.
454 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
455 bool hasNoSignedWrap() const { return NoSignedWrap; }
456 bool hasExact() const { return Exact; }
457 bool hasNoNaNs() const { return NoNaNs; }
458 bool hasNoInfs() const { return NoInfs; }
459 bool hasNoSignedZeros() const { return NoSignedZeros; }
460 bool hasAllowReciprocal() const { return AllowReciprocal; }
461 bool hasVectorReduction() const { return VectorReduction; }
462 bool hasAllowContract() const { return AllowContract; }
463 bool hasApproximateFuncs() const { return ApproximateFuncs; }
464 bool hasAllowReassociation() const { return AllowReassociation; }
465 bool hasFPExcept() const { return !NoFPExcept; }
466
467 bool isFast() const {
468 return NoSignedZeros && AllowReciprocal && NoNaNs && NoInfs && NoFPExcept &&
469 AllowContract && ApproximateFuncs && AllowReassociation;
470 }
471
472 /// Clear any flags in this flag set that aren't also set in Flags.
473 /// If the given Flags are undefined then don't do anything.
474 void intersectWith(const SDNodeFlags Flags) {
475 if (!Flags.isDefined())
476 return;
477 NoUnsignedWrap &= Flags.NoUnsignedWrap;
478 NoSignedWrap &= Flags.NoSignedWrap;
479 Exact &= Flags.Exact;
480 NoNaNs &= Flags.NoNaNs;
481 NoInfs &= Flags.NoInfs;
482 NoSignedZeros &= Flags.NoSignedZeros;
483 AllowReciprocal &= Flags.AllowReciprocal;
484 VectorReduction &= Flags.VectorReduction;
485 AllowContract &= Flags.AllowContract;
486 ApproximateFuncs &= Flags.ApproximateFuncs;
487 AllowReassociation &= Flags.AllowReassociation;
488 NoFPExcept &= Flags.NoFPExcept;
489 }
490};
491
492/// Represents one node in the SelectionDAG.
493///
494class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
495private:
496 /// The operation that this node performs.
497 int16_t NodeType;
498
499protected:
500 // We define a set of mini-helper classes to help us interpret the bits in our
501 // SubclassData. These are designed to fit within a uint16_t so they pack
502 // with NodeType.
503
504#if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__))
505// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
506// and give the `pack` pragma push semantics.
507#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
508#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
509#else
510#define BEGIN_TWO_BYTE_PACK()
511#define END_TWO_BYTE_PACK()
512#endif
513
514BEGIN_TWO_BYTE_PACK()
515 class SDNodeBitfields {
516 friend class SDNode;
517 friend class MemIntrinsicSDNode;
518 friend class MemSDNode;
519 friend class SelectionDAG;
520
521 uint16_t HasDebugValue : 1;
522 uint16_t IsMemIntrinsic : 1;
523 uint16_t IsDivergent : 1;
524 };
525 enum { NumSDNodeBits = 3 };
526
527 class ConstantSDNodeBitfields {
528 friend class ConstantSDNode;
529
530 uint16_t : NumSDNodeBits;
531
532 uint16_t IsOpaque : 1;
533 };
534
535 class MemSDNodeBitfields {
536 friend class MemSDNode;
537 friend class MemIntrinsicSDNode;
538 friend class AtomicSDNode;
539
540 uint16_t : NumSDNodeBits;
541
542 uint16_t IsVolatile : 1;
543 uint16_t IsNonTemporal : 1;
544 uint16_t IsDereferenceable : 1;
545 uint16_t IsInvariant : 1;
546 };
547 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
548
549 class LSBaseSDNodeBitfields {
550 friend class LSBaseSDNode;
551 friend class MaskedGatherScatterSDNode;
552
553 uint16_t : NumMemSDNodeBits;
554
555 // This storage is shared between disparate class hierarchies to hold an
556 // enumeration specific to the class hierarchy in use.
557 // LSBaseSDNode => enum ISD::MemIndexedMode
558 // MaskedGatherScatterSDNode => enum ISD::MemIndexType
559 uint16_t AddressingMode : 3;
560 };
561 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
562
563 class LoadSDNodeBitfields {
564 friend class LoadSDNode;
565 friend class MaskedLoadSDNode;
566
567 uint16_t : NumLSBaseSDNodeBits;
568
569 uint16_t ExtTy : 2; // enum ISD::LoadExtType
570 uint16_t IsExpanding : 1;
571 };
572
573 class StoreSDNodeBitfields {
574 friend class StoreSDNode;
575 friend class MaskedStoreSDNode;
576
577 uint16_t : NumLSBaseSDNodeBits;
578
579 uint16_t IsTruncating : 1;
580 uint16_t IsCompressing : 1;
581 };
582
583 union {
584 char RawSDNodeBits[sizeof(uint16_t)];
585 SDNodeBitfields SDNodeBits;
586 ConstantSDNodeBitfields ConstantSDNodeBits;
587 MemSDNodeBitfields MemSDNodeBits;
588 LSBaseSDNodeBitfields LSBaseSDNodeBits;
589 LoadSDNodeBitfields LoadSDNodeBits;
590 StoreSDNodeBitfields StoreSDNodeBits;
591 };
592END_TWO_BYTE_PACK()
593#undef BEGIN_TWO_BYTE_PACK
594#undef END_TWO_BYTE_PACK
595
596 // RawSDNodeBits must cover the entirety of the union. This means that all of
597 // the union's members must have size <= RawSDNodeBits. We write the RHS as
598 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
599 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
600 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
601 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
602 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
603 static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
604 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
605
606private:
607 friend class SelectionDAG;
608 // TODO: unfriend HandleSDNode once we fix its operand handling.
609 friend class HandleSDNode;
610
611 /// Unique id per SDNode in the DAG.
612 int NodeId = -1;
613
614 /// The values that are used by this operation.
615 SDUse *OperandList = nullptr;
616
617 /// The types of the values this node defines. SDNode's may
618 /// define multiple values simultaneously.
619 const EVT *ValueList;
620
621 /// List of uses for this SDNode.
622 SDUse *UseList = nullptr;
623
624 /// The number of entries in the Operand/Value list.
625 unsigned short NumOperands = 0;
626 unsigned short NumValues;
627
628 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
629 // original LLVM instructions.
630 // This is used for turning off scheduling, because we'll forgo
631 // the normal scheduling algorithms and output the instructions according to
632 // this ordering.
633 unsigned IROrder;
634
635 /// Source line information.
636 DebugLoc debugLoc;
637
638 /// Return a pointer to the specified value type.
639 static const EVT *getValueTypeList(EVT VT);
640
641 SDNodeFlags Flags;
642
643public:
644 /// Unique and persistent id per SDNode in the DAG.
645 /// Used for debug printing.
646 uint16_t PersistentId;
647
648 //===--------------------------------------------------------------------===//
649 // Accessors
650 //
651
652 /// Return the SelectionDAG opcode value for this node. For
653 /// pre-isel nodes (those for which isMachineOpcode returns false), these
654 /// are the opcode values in the ISD and <target>ISD namespaces. For
655 /// post-isel opcodes, see getMachineOpcode.
656 unsigned getOpcode() const { return (unsigned short)NodeType; }
657
658 /// Test if this node has a target-specific opcode (in the
659 /// \<target\>ISD namespace).
660 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
661
662 /// Test if this node has a target-specific
663 /// memory-referencing opcode (in the \<target\>ISD namespace and
664 /// greater than FIRST_TARGET_MEMORY_OPCODE).
665 bool isTargetMemoryOpcode() const {
666 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
667 }
668
669 /// Return true if the type of the node type undefined.
670 bool isUndef() const { return NodeType == ISD::UNDEF; }
671
672 /// Test if this node is a memory intrinsic (with valid pointer information).
673 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
674 /// non-memory intrinsics (with chains) that are not really instances of
675 /// MemSDNode. For such nodes, we need some extra state to determine the
676 /// proper classof relationship.
677 bool isMemIntrinsic() const {
678 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
679 NodeType == ISD::INTRINSIC_VOID) &&
680 SDNodeBits.IsMemIntrinsic;
681 }
682
683 /// Test if this node is a strict floating point pseudo-op.
684 bool isStrictFPOpcode() {
685 switch (NodeType) {
686 default:
687 return false;
688 case ISD::STRICT_FADD:
689 case ISD::STRICT_FSUB:
690 case ISD::STRICT_FMUL:
691 case ISD::STRICT_FDIV:
692 case ISD::STRICT_FREM:
693 case ISD::STRICT_FMA:
694 case ISD::STRICT_FSQRT:
695 case ISD::STRICT_FPOW:
696 case ISD::STRICT_FPOWI:
697 case ISD::STRICT_FSIN:
698 case ISD::STRICT_FCOS:
699 case ISD::STRICT_FEXP:
700 case ISD::STRICT_FEXP2:
701 case ISD::STRICT_FLOG:
702 case ISD::STRICT_FLOG10:
703 case ISD::STRICT_FLOG2:
704 case ISD::STRICT_LRINT:
705 case ISD::STRICT_LLRINT:
706 case ISD::STRICT_FRINT:
707 case ISD::STRICT_FNEARBYINT:
708 case ISD::STRICT_FMAXNUM:
709 case ISD::STRICT_FMINNUM:
710 case ISD::STRICT_FCEIL:
711 case ISD::STRICT_FFLOOR:
712 case ISD::STRICT_LROUND:
713 case ISD::STRICT_LLROUND:
714 case ISD::STRICT_FROUND:
715 case ISD::STRICT_FTRUNC:
716 case ISD::STRICT_FP_TO_SINT:
717 case ISD::STRICT_FP_TO_UINT:
718 case ISD::STRICT_FP_ROUND:
719 case ISD::STRICT_FP_EXTEND:
720 return true;
721 }
722 }
723
724 /// Test if this node has a post-isel opcode, directly
725 /// corresponding to a MachineInstr opcode.
726 bool isMachineOpcode() const { return NodeType < 0; }
727
728 /// This may only be called if isMachineOpcode returns
729 /// true. It returns the MachineInstr opcode value that the node's opcode
730 /// corresponds to.
731 unsigned getMachineOpcode() const {
732 assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 732, __PRETTY_FUNCTION__))
;
733 return ~NodeType;
734 }
735
736 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
737 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
738
739 bool isDivergent() const { return SDNodeBits.IsDivergent; }
740
741 /// Return true if there are no uses of this node.
742 bool use_empty() const { return UseList == nullptr; }
743
744 /// Return true if there is exactly one use of this node.
745 bool hasOneUse() const {
746 return !use_empty() && std::next(use_begin()) == use_end();
747 }
748
749 /// Return the number of uses of this node. This method takes
750 /// time proportional to the number of uses.
751 size_t use_size() const { return std::distance(use_begin(), use_end()); }
752
753 /// Return the unique node id.
754 int getNodeId() const { return NodeId; }
755
756 /// Set unique node id.
757 void setNodeId(int Id) { NodeId = Id; }
758
759 /// Return the node ordering.
760 unsigned getIROrder() const { return IROrder; }
761
762 /// Set the node ordering.
763 void setIROrder(unsigned Order) { IROrder = Order; }
764
765 /// Return the source location info.
766 const DebugLoc &getDebugLoc() const { return debugLoc; }
767
768 /// Set source location info. Try to avoid this, putting
769 /// it in the constructor is preferable.
770 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
771
772 /// This class provides iterator support for SDUse
773 /// operands that use a specific SDNode.
774 class use_iterator
775 : public std::iterator<std::forward_iterator_tag, SDUse, ptrdiff_t> {
776 friend class SDNode;
777
778 SDUse *Op = nullptr;
779
780 explicit use_iterator(SDUse *op) : Op(op) {}
781
782 public:
783 using reference = std::iterator<std::forward_iterator_tag,
784 SDUse, ptrdiff_t>::reference;
785 using pointer = std::iterator<std::forward_iterator_tag,
786 SDUse, ptrdiff_t>::pointer;
787
788 use_iterator() = default;
789 use_iterator(const use_iterator &I) : Op(I.Op) {}
790
791 bool operator==(const use_iterator &x) const {
792 return Op == x.Op;
793 }
794 bool operator!=(const use_iterator &x) const {
795 return !operator==(x);
796 }
797
798 /// Return true if this iterator is at the end of uses list.
799 bool atEnd() const { return Op == nullptr; }
800
801 // Iterator traversal: forward iteration only.
802 use_iterator &operator++() { // Preincrement
803 assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 803, __PRETTY_FUNCTION__))
;
804 Op = Op->getNext();
805 return *this;
806 }
807
808 use_iterator operator++(int) { // Postincrement
809 use_iterator tmp = *this; ++*this; return tmp;
810 }
811
812 /// Retrieve a pointer to the current user node.
813 SDNode *operator*() const {
814 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 814, __PRETTY_FUNCTION__))
;
815 return Op->getUser();
816 }
817
818 SDNode *operator->() const { return operator*(); }
819
820 SDUse &getUse() const { return *Op; }
821
822 /// Retrieve the operand # of this use in its user.
823 unsigned getOperandNo() const {
824 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 824, __PRETTY_FUNCTION__))
;
825 return (unsigned)(Op - Op->getUser()->OperandList);
826 }
827 };
828
829 /// Provide iteration support to walk over all uses of an SDNode.
830 use_iterator use_begin() const {
831 return use_iterator(UseList);
832 }
833
834 static use_iterator use_end() { return use_iterator(nullptr); }
835
836 inline iterator_range<use_iterator> uses() {
837 return make_range(use_begin(), use_end());
838 }
839 inline iterator_range<use_iterator> uses() const {
840 return make_range(use_begin(), use_end());
841 }
842
843 /// Return true if there are exactly NUSES uses of the indicated value.
844 /// This method ignores uses of other values defined by this operation.
845 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
846
847 /// Return true if there are any use of the indicated value.
848 /// This method ignores uses of other values defined by this operation.
849 bool hasAnyUseOfValue(unsigned Value) const;
850
851 /// Return true if this node is the only use of N.
852 bool isOnlyUserOf(const SDNode *N) const;
853
854 /// Return true if this node is an operand of N.
855 bool isOperandOf(const SDNode *N) const;
856
857 /// Return true if this node is a predecessor of N.
858 /// NOTE: Implemented on top of hasPredecessor and every bit as
859 /// expensive. Use carefully.
860 bool isPredecessorOf(const SDNode *N) const {
861 return N->hasPredecessor(this);
862 }
863
864 /// Return true if N is a predecessor of this node.
865 /// N is either an operand of this node, or can be reached by recursively
866 /// traversing up the operands.
867 /// NOTE: This is an expensive method. Use it carefully.
868 bool hasPredecessor(const SDNode *N) const;
869
870 /// Returns true if N is a predecessor of any node in Worklist. This
871 /// helper keeps Visited and Worklist sets externally to allow unions
872 /// searches to be performed in parallel, caching of results across
873 /// queries and incremental addition to Worklist. Stops early if N is
874 /// found but will resume. Remember to clear Visited and Worklists
875 /// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
876 /// giving up. The TopologicalPrune flag signals that positive NodeIds are
877 /// topologically ordered (Operands have strictly smaller node id) and search
878 /// can be pruned leveraging this.
879 static bool hasPredecessorHelper(const SDNode *N,
880 SmallPtrSetImpl<const SDNode *> &Visited,
881 SmallVectorImpl<const SDNode *> &Worklist,
882 unsigned int MaxSteps = 0,
883 bool TopologicalPrune = false) {
884 SmallVector<const SDNode *, 8> DeferredNodes;
885 if (Visited.count(N))
886 return true;
887
888 // Node Id's are assigned in three places: As a topological
889 // ordering (> 0), during legalization (results in values set to
890 // 0), new nodes (set to -1). If N has a topolgical id then we
891 // know that all nodes with ids smaller than it cannot be
892 // successors and we need not check them. Filter out all node
893 // that can't be matches. We add them to the worklist before exit
894 // in case of multiple calls. Note that during selection the topological id
895 // may be violated if a node's predecessor is selected before it. We mark
896 // this at selection negating the id of unselected successors and
897 // restricting topological pruning to positive ids.
898
899 int NId = N->getNodeId();
900 // If we Invalidated the Id, reconstruct original NId.
901 if (NId < -1)
902 NId = -(NId + 1);
903
904 bool Found = false;
905 while (!Worklist.empty()) {
906 const SDNode *M = Worklist.pop_back_val();
907 int MId = M->getNodeId();
908 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
909 (MId > 0) && (MId < NId)) {
910 DeferredNodes.push_back(M);
911 continue;
912 }
913 for (const SDValue &OpV : M->op_values()) {
914 SDNode *Op = OpV.getNode();
915 if (Visited.insert(Op).second)
916 Worklist.push_back(Op);
917 if (Op == N)
918 Found = true;
919 }
920 if (Found)
921 break;
922 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
923 break;
924 }
925 // Push deferred nodes back on worklist.
926 Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
927 // If we bailed early, conservatively return found.
928 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
929 return true;
930 return Found;
931 }
932
933 /// Return true if all the users of N are contained in Nodes.
934 /// NOTE: Requires at least one match, but doesn't require them all.
935 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
936
937 /// Return the number of values used by this operation.
938 unsigned getNumOperands() const { return NumOperands; }
939
940 /// Return the maximum number of operands that a SDNode can hold.
941 static constexpr size_t getMaxNumOperands() {
942 return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
943 }
944
945 /// Helper method returns the integer value of a ConstantSDNode operand.
946 inline uint64_t getConstantOperandVal(unsigned Num) const;
947
948 /// Helper method returns the APInt of a ConstantSDNode operand.
949 inline const APInt &getConstantOperandAPInt(unsigned Num) const;
950
951 const SDValue &getOperand(unsigned Num) const {
952 assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 952, __PRETTY_FUNCTION__))
;
953 return OperandList[Num];
954 }
955
956 using op_iterator = SDUse *;
957
958 op_iterator op_begin() const { return OperandList; }
959 op_iterator op_end() const { return OperandList+NumOperands; }
960 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
961
962 /// Iterator for directly iterating over the operand SDValue's.
963 struct value_op_iterator
964 : iterator_adaptor_base<value_op_iterator, op_iterator,
965 std::random_access_iterator_tag, SDValue,
966 ptrdiff_t, value_op_iterator *,
967 value_op_iterator *> {
968 explicit value_op_iterator(SDUse *U = nullptr)
969 : iterator_adaptor_base(U) {}
970
971 const SDValue &operator*() const { return I->get(); }
972 };
973
974 iterator_range<value_op_iterator> op_values() const {
975 return make_range(value_op_iterator(op_begin()),
976 value_op_iterator(op_end()));
977 }
978
979 SDVTList getVTList() const {
980 SDVTList X = { ValueList, NumValues };
981 return X;
982 }
983
984 /// If this node has a glue operand, return the node
985 /// to which the glue operand points. Otherwise return NULL.
986 SDNode *getGluedNode() const {
987 if (getNumOperands() != 0 &&
988 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
989 return getOperand(getNumOperands()-1).getNode();
990 return nullptr;
991 }
992
993 /// If this node has a glue value with a user, return
994 /// the user (there is at most one). Otherwise return NULL.
995 SDNode *getGluedUser() const {
996 for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
997 if (UI.getUse().get().getValueType() == MVT::Glue)
998 return *UI;
999 return nullptr;
1000 }
1001
1002 const SDNodeFlags getFlags() const { return Flags; }
1003 void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
1004 bool isFast() { return Flags.isFast(); }
1005
1006 /// Clear any flags in this node that aren't also set in Flags.
1007 /// If Flags is not in a defined state then this has no effect.
1008 void intersectFlagsWith(const SDNodeFlags Flags);
1009
1010 /// Return the number of values defined/returned by this operator.
1011 unsigned getNumValues() const { return NumValues; }
1012
1013 /// Return the type of a specified result.
1014 EVT getValueType(unsigned ResNo) const {
1015 assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ?
static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1015, __PRETTY_FUNCTION__))
;
1016 return ValueList[ResNo];
1017 }
1018
1019 /// Return the type of a specified result as a simple type.
1020 MVT getSimpleValueType(unsigned ResNo) const {
1021 return getValueType(ResNo).getSimpleVT();
1022 }
1023
1024 /// Returns MVT::getSizeInBits(getValueType(ResNo)).
1025 unsigned getValueSizeInBits(unsigned ResNo) const {
1026 return getValueType(ResNo).getSizeInBits();
1027 }
1028
1029 using value_iterator = const EVT *;
1030
1031 value_iterator value_begin() const { return ValueList; }
1032 value_iterator value_end() const { return ValueList+NumValues; }
1033
1034 /// Return the opcode of this operation for printing.
1035 std::string getOperationName(const SelectionDAG *G = nullptr) const;
1036 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1037 void print_types(raw_ostream &OS, const SelectionDAG *G) const;
1038 void print_details(raw_ostream &OS, const SelectionDAG *G) const;
1039 void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1040 void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
1041
1042 /// Print a SelectionDAG node and all children down to
1043 /// the leaves. The given SelectionDAG allows target-specific nodes
1044 /// to be printed in human-readable form. Unlike printr, this will
1045 /// print the whole DAG, including children that appear multiple
1046 /// times.
1047 ///
1048 void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;
1049
1050 /// Print a SelectionDAG node and children up to
1051 /// depth "depth." The given SelectionDAG allows target-specific
1052 /// nodes to be printed in human-readable form. Unlike printr, this
1053 /// will print children that appear multiple times wherever they are
1054 /// used.
1055 ///
1056 void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
1057 unsigned depth = 100) const;
1058
1059 /// Dump this node, for debugging.
1060 void dump() const;
1061
1062 /// Dump (recursively) this node and its use-def subgraph.
1063 void dumpr() const;
1064
1065 /// Dump this node, for debugging.
1066 /// The given SelectionDAG allows target-specific nodes to be printed
1067 /// in human-readable form.
1068 void dump(const SelectionDAG *G) const;
1069
1070 /// Dump (recursively) this node and its use-def subgraph.
1071 /// The given SelectionDAG allows target-specific nodes to be printed
1072 /// in human-readable form.
1073 void dumpr(const SelectionDAG *G) const;
1074
1075 /// printrFull to dbgs(). The given SelectionDAG allows
1076 /// target-specific nodes to be printed in human-readable form.
1077 /// Unlike dumpr, this will print the whole DAG, including children
1078 /// that appear multiple times.
1079 void dumprFull(const SelectionDAG *G = nullptr) const;
1080
1081 /// printrWithDepth to dbgs(). The given
1082 /// SelectionDAG allows target-specific nodes to be printed in
1083 /// human-readable form. Unlike dumpr, this will print children
1084 /// that appear multiple times wherever they are used.
1085 ///
1086 void dumprWithDepth(const SelectionDAG *G = nullptr,
1087 unsigned depth = 100) const;
1088
1089 /// Gather unique data for the node.
1090 void Profile(FoldingSetNodeID &ID) const;
1091
1092 /// This method should only be used by the SDUse class.
1093 void addUse(SDUse &U) { U.addToList(&UseList); }
1094
1095protected:
1096 static SDVTList getSDVTList(EVT VT) {
1097 SDVTList Ret = { getValueTypeList(VT), 1 };
1098 return Ret;
1099 }
1100
1101 /// Create an SDNode.
1102 ///
1103 /// SDNodes are created without any operands, and never own the operand
1104 /// storage. To add operands, see SelectionDAG::createOperands.
1105 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
1106 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
1107 IROrder(Order), debugLoc(std::move(dl)) {
1108 memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
1109 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1109, __PRETTY_FUNCTION__))
;
1110 assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1111, __PRETTY_FUNCTION__))
1111 "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1111, __PRETTY_FUNCTION__))
;
1112 }
1113
1114 /// Release the operands and set this node to have zero operands.
1115 void DropOperands();
1116};
1117
1118/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1119/// into SDNode creation functions.
1120/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1121/// from the original Instruction, and IROrder is the ordinal position of
1122/// the instruction.
1123/// When an SDNode is created after the DAG is being built, both DebugLoc and
1124/// the IROrder are propagated from the original SDNode.
1125/// So SDLoc class provides two constructors besides the default one, one to
1126/// be used by the DAGBuilder, the other to be used by others.
1127class SDLoc {
1128private:
1129 DebugLoc DL;
1130 int IROrder = 0;
1131
1132public:
1133 SDLoc() = default;
1134 SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
1135 SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
1136 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1137 assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void
> (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1137, __PRETTY_FUNCTION__))
;
1138 if (I)
1139 DL = I->getDebugLoc();
1140 }
1141
1142 unsigned getIROrder() const { return IROrder; }
1143 const DebugLoc &getDebugLoc() const { return DL; }
1144};
1145
1146// Define inline functions from the SDValue class.
1147
1148inline SDValue::SDValue(SDNode *node, unsigned resno)
1149 : Node(node), ResNo(resno) {
1150 // Explicitly check for !ResNo to avoid use-after-free, because there are
1151 // callers that use SDValue(N, 0) with a deleted N to indicate successful
1152 // combines.
1153 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1154, __PRETTY_FUNCTION__))
1154 "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1154, __PRETTY_FUNCTION__))
;
1155 assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1155, __PRETTY_FUNCTION__))
;
1156}
1157
1158inline unsigned SDValue::getOpcode() const {
1159 return Node->getOpcode();
1160}
1161
1162inline EVT SDValue::getValueType() const {
1163 return Node->getValueType(ResNo);
12
Called C++ object pointer is null
1164}
1165
1166inline unsigned SDValue::getNumOperands() const {
1167 return Node->getNumOperands();
1168}
1169
1170inline const SDValue &SDValue::getOperand(unsigned i) const {
1171 return Node->getOperand(i);
1172}
1173
1174inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
1175 return Node->getConstantOperandVal(i);
1176}
1177
1178inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
1179 return Node->getConstantOperandAPInt(i);
1180}
1181
1182inline bool SDValue::isTargetOpcode() const {
1183 return Node->isTargetOpcode();
1184}
1185
1186inline bool SDValue::isTargetMemoryOpcode() const {
1187 return Node->isTargetMemoryOpcode();
1188}
1189
1190inline bool SDValue::isMachineOpcode() const {
1191 return Node->isMachineOpcode();
1192}
1193
1194inline unsigned SDValue::getMachineOpcode() const {
1195 return Node->getMachineOpcode();
1196}
1197
1198inline bool SDValue::isUndef() const {
1199 return Node->isUndef();
1200}
1201
1202inline bool SDValue::use_empty() const {
1203 return !Node->hasAnyUseOfValue(ResNo);
1204}
1205
1206inline bool SDValue::hasOneUse() const {
1207 return Node->hasNUsesOfValue(1, ResNo);
1208}
1209
1210inline const DebugLoc &SDValue::getDebugLoc() const {
1211 return Node->getDebugLoc();
1212}
1213
1214inline void SDValue::dump() const {
1215 return Node->dump();
1216}
1217
1218inline void SDValue::dump(const SelectionDAG *G) const {
1219 return Node->dump(G);
1220}
1221
1222inline void SDValue::dumpr() const {
1223 return Node->dumpr();
1224}
1225
1226inline void SDValue::dumpr(const SelectionDAG *G) const {
1227 return Node->dumpr(G);
1228}
1229
1230// Define inline functions from the SDUse class.
1231
1232inline void SDUse::set(const SDValue &V) {
1233 if (Val.getNode()) removeFromList();
1234 Val = V;
1235 if (V.getNode()) V.getNode()->addUse(*this);
1236}
1237
1238inline void SDUse::setInitial(const SDValue &V) {
1239 Val = V;
1240 V.getNode()->addUse(*this);
1241}
1242
1243inline void SDUse::setNode(SDNode *N) {
1244 if (Val.getNode()) removeFromList();
1245 Val.setNode(N);
1246 if (N) N->addUse(*this);
1247}
1248
1249/// This class is used to form a handle around another node that
1250/// is persistent and is updated across invocations of replaceAllUsesWith on its
1251/// operand. This node should be directly created by end-users and not added to
1252/// the AllNodes list.
1253class HandleSDNode : public SDNode {
1254 SDUse Op;
1255
1256public:
1257 explicit HandleSDNode(SDValue X)
1258 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
1259 // HandleSDNodes are never inserted into the DAG, so they won't be
1260 // auto-numbered. Use ID 65535 as a sentinel.
1261 PersistentId = 0xffff;
1262
1263 // Manually set up the operand list. This node type is special in that it's
1264 // always stack allocated and SelectionDAG does not manage its operands.
1265 // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
1266 // be so special.
1267 Op.setUser(this);
1268 Op.setInitial(X);
1269 NumOperands = 1;
1270 OperandList = &Op;
1271 }
1272 ~HandleSDNode();
1273
1274 const SDValue &getValue() const { return Op; }
1275};
1276
1277class AddrSpaceCastSDNode : public SDNode {
1278private:
1279 unsigned SrcAddrSpace;
1280 unsigned DestAddrSpace;
1281
1282public:
1283 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1284 unsigned SrcAS, unsigned DestAS);
1285
1286 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
1287 unsigned getDestAddressSpace() const { return DestAddrSpace; }
1288
1289 static bool classof(const SDNode *N) {
1290 return N->getOpcode() == ISD::ADDRSPACECAST;
1291 }
1292};
1293
1294/// This is an abstract virtual class for memory operations.
1295class MemSDNode : public SDNode {
1296private:
1297 // VT of in-memory value.
1298 EVT MemoryVT;
1299
1300protected:
1301 /// Memory reference information.
1302 MachineMemOperand *MMO;
1303
1304public:
1305 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1306 EVT memvt, MachineMemOperand *MMO);
1307
1308 bool readMem() const { return MMO->isLoad(); }
1309 bool writeMem() const { return MMO->isStore(); }
1310
1311 /// Returns alignment and volatility of the memory access
1312 unsigned getOriginalAlignment() const {
1313 return MMO->getBaseAlignment();
1314 }
1315 unsigned getAlignment() const {
1316 return MMO->getAlignment();
1317 }
1318
1319 /// Return the SubclassData value, without HasDebugValue. This contains an
1320 /// encoding of the volatile flag, as well as bits used by subclasses. This
1321 /// function should only be used to compute a FoldingSetNodeID value.
1322 /// The HasDebugValue bit is masked out because CSE map needs to match
1323 /// nodes with debug info with nodes without debug info. Same is about
1324 /// isDivergent bit.
1325 unsigned getRawSubclassData() const {
1326 uint16_t Data;
1327 union {
1328 char RawSDNodeBits[sizeof(uint16_t)];
1329 SDNodeBitfields SDNodeBits;
1330 };
1331 memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
1332 SDNodeBits.HasDebugValue = 0;
1333 SDNodeBits.IsDivergent = false;
1334 memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
1335 return Data;
1336 }
1337
1338 bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
1339 bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
1340 bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
1341 bool isInvariant() const { return MemSDNodeBits.IsInvariant; }
1342
1343 // Returns the offset from the location of the access.
1344 int64_t getSrcValueOffset() const { return MMO->getOffset(); }
1345
1346 /// Returns the AA info that describes the dereference.
1347 AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }
1348
1349 /// Returns the Ranges that describes the dereference.
1350 const MDNode *getRanges() const { return MMO->getRanges(); }
1351
1352 /// Returns the synchronization scope ID for this memory operation.
1353 SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }
1354
1355 /// Return the atomic ordering requirements for this memory operation. For
1356 /// cmpxchg atomic operations, return the atomic ordering requirements when
1357 /// store occurs.
1358 AtomicOrdering getOrdering() const { return MMO->getOrdering(); }
1359
1360 /// Return true if the memory operation ordering is Unordered or higher.
1361 bool isAtomic() const { return MMO->isAtomic(); }
1362
1363 /// Returns true if the memory operation doesn't imply any ordering
1364 /// constraints on surrounding memory operations beyond the normal memory
1365 /// aliasing rules.
1366 bool isUnordered() const { return MMO->isUnordered(); }
1367
1368 /// Returns true if the memory operation is neither atomic or volatile.
1369 bool isSimple() const { return !isAtomic() && !isVolatile(); }
1370
1371 /// Return the type of the in-memory value.
1372 EVT getMemoryVT() const { return MemoryVT; }
1373
1374 /// Return a MachineMemOperand object describing the memory
1375 /// reference performed by operation.
1376 MachineMemOperand *getMemOperand() const { return MMO; }
1377
1378 const MachinePointerInfo &getPointerInfo() const {
1379 return MMO->getPointerInfo();
1380 }
1381
1382 /// Return the address space for the associated pointer
1383 unsigned getAddressSpace() const {
1384 return getPointerInfo().getAddrSpace();
1385 }
1386
1387 /// Update this MemSDNode's MachineMemOperand information
1388 /// to reflect the alignment of NewMMO, if it has a greater alignment.
1389 /// This must only be used when the new alignment applies to all users of
1390 /// this MachineMemOperand.
1391 void refineAlignment(const MachineMemOperand *NewMMO) {
1392 MMO->refineAlignment(NewMMO);
1393 }
1394
1395 const SDValue &getChain() const { return getOperand(0); }
1396 const SDValue &getBasePtr() const {
1397 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1398 }
1399
1400 // Methods to support isa and dyn_cast
1401 static bool classof(const SDNode *N) {
1402 // For some targets, we lower some target intrinsics to a MemIntrinsicNode
1403 // with either an intrinsic or a target opcode.
1404 return N->getOpcode() == ISD::LOAD ||
1405 N->getOpcode() == ISD::STORE ||
1406 N->getOpcode() == ISD::PREFETCH ||
1407 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1408 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1409 N->getOpcode() == ISD::ATOMIC_SWAP ||
1410 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1411 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1412 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1413 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1414 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1415 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1416 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1417 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1418 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1419 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1420 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1421 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1422 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1423 N->getOpcode() == ISD::ATOMIC_LOAD ||
1424 N->getOpcode() == ISD::ATOMIC_STORE ||
1425 N->getOpcode() == ISD::MLOAD ||
1426 N->getOpcode() == ISD::MSTORE ||
1427 N->getOpcode() == ISD::MGATHER ||
1428 N->getOpcode() == ISD::MSCATTER ||
1429 N->isMemIntrinsic() ||
1430 N->isTargetMemoryOpcode();
1431 }
1432};
1433
1434/// This is an SDNode representing atomic operations.
1435class AtomicSDNode : public MemSDNode {
1436public:
1437 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
1438 EVT MemVT, MachineMemOperand *MMO)
1439 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
1440 assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1441, __PRETTY_FUNCTION__))
1441 MMO->isAtomic()) && "then why are we using an AtomicSDNode?")((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1441, __PRETTY_FUNCTION__))
;
1442 }
1443
1444 const SDValue &getBasePtr() const { return getOperand(1); }
1445 const SDValue &getVal() const { return getOperand(2); }
1446
1447 /// Returns true if this SDNode represents cmpxchg atomic operation, false
1448 /// otherwise.
1449 bool isCompareAndSwap() const {
1450 unsigned Op = getOpcode();
1451 return Op == ISD::ATOMIC_CMP_SWAP ||
1452 Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
1453 }
1454
1455 /// For cmpxchg atomic operations, return the atomic ordering requirements
1456 /// when store does not occur.
1457 AtomicOrdering getFailureOrdering() const {
1458 assert(isCompareAndSwap() && "Must be cmpxchg operation")((isCompareAndSwap() && "Must be cmpxchg operation") ?
static_cast<void> (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1458, __PRETTY_FUNCTION__))
;
1459 return MMO->getFailureOrdering();
1460 }
1461
1462 // Methods to support isa and dyn_cast
1463 static bool classof(const SDNode *N) {
1464 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1465 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1466 N->getOpcode() == ISD::ATOMIC_SWAP ||
1467 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1468 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1469 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1470 N->getOpcode() == ISD::ATOMIC_LOAD_CLR ||
1471 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1472 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1473 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1474 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1475 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1476 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1477 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1478 N->getOpcode() == ISD::ATOMIC_LOAD_FADD ||
1479 N->getOpcode() == ISD::ATOMIC_LOAD_FSUB ||
1480 N->getOpcode() == ISD::ATOMIC_LOAD ||
1481 N->getOpcode() == ISD::ATOMIC_STORE;
1482 }
1483};
1484
1485/// This SDNode is used for target intrinsics that touch
1486/// memory and need an associated MachineMemOperand. Its opcode may be
1487/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1488/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1489class MemIntrinsicSDNode : public MemSDNode {
1490public:
1491 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1492 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
1493 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
1494 SDNodeBits.IsMemIntrinsic = true;
1495 }
1496
1497 // Methods to support isa and dyn_cast
1498 static bool classof(const SDNode *N) {
1499 // We lower some target intrinsics to their target opcode
1500 // early a node with a target opcode can be of this class
1501 return N->isMemIntrinsic() ||
1502 N->getOpcode() == ISD::PREFETCH ||
1503 N->isTargetMemoryOpcode();
1504 }
1505};
1506
1507/// This SDNode is used to implement the code generator
1508/// support for the llvm IR shufflevector instruction. It combines elements
1509/// from two input vectors into a new input vector, with the selection and
1510/// ordering of elements determined by an array of integers, referred to as
1511/// the shuffle mask. For input vectors of width N, mask indices of 0..N-1
1512/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1513/// An index of -1 is treated as undef, such that the code generator may put
1514/// any value in the corresponding element of the result.
1515class ShuffleVectorSDNode : public SDNode {
1516 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
1517 // is freed when the SelectionDAG object is destroyed.
1518 const int *Mask;
1519
1520protected:
1521 friend class SelectionDAG;
1522
1523 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
1524 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1525
1526public:
1527 ArrayRef<int> getMask() const {
1528 EVT VT = getValueType(0);
1529 return makeArrayRef(Mask, VT.getVectorNumElements());
1530 }
1531
1532 int getMaskElt(unsigned Idx) const {
1533 assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")((Idx < getValueType(0).getVectorNumElements() && "Idx out of range!"
) ? static_cast<void> (0) : __assert_fail ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1533, __PRETTY_FUNCTION__))
;
1534 return Mask[Idx];
1535 }
1536
1537 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
1538
1539 int getSplatIndex() const {