Bug Summary

File:llvm/lib/CodeGen/MachineInstr.cpp
Warning:line 1861, column 7
Value stored to 'HaveSemi' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MachineInstr.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1=. -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2021-01-24-223304-31662-1 -x c++ /build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp
1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/FoldingSet.h"
17#include "llvm/ADT/Hashing.h"
18#include "llvm/ADT/None.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SmallBitVector.h"
21#include "llvm/ADT/SmallString.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/Analysis/Loads.h"
25#include "llvm/Analysis/MemoryLocation.h"
26#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
27#include "llvm/CodeGen/MachineBasicBlock.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineInstrBundle.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/CodeGen/StackMaps.h"
38#include "llvm/CodeGen/TargetInstrInfo.h"
39#include "llvm/CodeGen/TargetRegisterInfo.h"
40#include "llvm/CodeGen/TargetSubtargetInfo.h"
41#include "llvm/Config/llvm-config.h"
42#include "llvm/IR/Constants.h"
43#include "llvm/IR/DebugInfoMetadata.h"
44#include "llvm/IR/DebugLoc.h"
45#include "llvm/IR/DerivedTypes.h"
46#include "llvm/IR/Function.h"
47#include "llvm/IR/InlineAsm.h"
48#include "llvm/IR/InstrTypes.h"
49#include "llvm/IR/Intrinsics.h"
50#include "llvm/IR/LLVMContext.h"
51#include "llvm/IR/Metadata.h"
52#include "llvm/IR/Module.h"
53#include "llvm/IR/ModuleSlotTracker.h"
54#include "llvm/IR/Operator.h"
55#include "llvm/IR/Type.h"
56#include "llvm/IR/Value.h"
57#include "llvm/MC/MCInstrDesc.h"
58#include "llvm/MC/MCRegisterInfo.h"
59#include "llvm/MC/MCSymbol.h"
60#include "llvm/Support/Casting.h"
61#include "llvm/Support/CommandLine.h"
62#include "llvm/Support/Compiler.h"
63#include "llvm/Support/Debug.h"
64#include "llvm/Support/ErrorHandling.h"
65#include "llvm/Support/FormattedStream.h"
66#include "llvm/Support/LowLevelTypeImpl.h"
67#include "llvm/Support/MathExtras.h"
68#include "llvm/Support/raw_ostream.h"
69#include "llvm/Target/TargetIntrinsicInfo.h"
70#include "llvm/Target/TargetMachine.h"
71#include <algorithm>
72#include <cassert>
73#include <cstddef>
74#include <cstdint>
75#include <cstring>
76#include <iterator>
77#include <utility>
78
79using namespace llvm;
80
81static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
82 if (const MachineBasicBlock *MBB = MI.getParent())
83 if (const MachineFunction *MF = MBB->getParent())
84 return MF;
85 return nullptr;
86}
87
88// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
89// it.
90static void tryToGetTargetInfo(const MachineInstr &MI,
91 const TargetRegisterInfo *&TRI,
92 const MachineRegisterInfo *&MRI,
93 const TargetIntrinsicInfo *&IntrinsicInfo,
94 const TargetInstrInfo *&TII) {
95
96 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
97 TRI = MF->getSubtarget().getRegisterInfo();
98 MRI = &MF->getRegInfo();
99 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
100 TII = MF->getSubtarget().getInstrInfo();
101 }
102}
103
104void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
105 if (MCID->ImplicitDefs)
106 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
107 ++ImpDefs)
108 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
109 if (MCID->ImplicitUses)
110 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
111 ++ImpUses)
112 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113}
114
115/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
116/// implicit operands. It reserves space for the number of operands specified by
117/// the MCInstrDesc.
118MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
119 DebugLoc dl, bool NoImp)
120 : MCID(&tid), debugLoc(std::move(dl)), DebugInstrNum(0) {
121 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 121, __PRETTY_FUNCTION__))
;
122
123 // Reserve space for the expected number of operands.
124 if (unsigned NumOps = MCID->getNumOperands() +
125 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
126 CapOperands = OperandCapacity::get(NumOps);
127 Operands = MF.allocateOperandArray(CapOperands);
128 }
129
130 if (!NoImp)
131 addImplicitDefUseOperands(MF);
132}
133
134/// MachineInstr ctor - Copies MachineInstr arg exactly.
135/// Does not copy the number from debug instruction numbering, to preserve
136/// uniqueness.
137MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
138 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()),
139 DebugInstrNum(0) {
140 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 140, __PRETTY_FUNCTION__))
;
141
142 CapOperands = OperandCapacity::get(MI.getNumOperands());
143 Operands = MF.allocateOperandArray(CapOperands);
144
145 // Copy operands.
146 for (const MachineOperand &MO : MI.operands())
147 addOperand(MF, MO);
148
149 // Copy all the sensible flags.
150 setFlags(MI.Flags);
151}
152
153void MachineInstr::moveBefore(MachineInstr *MovePos) {
154 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
155}
156
157/// getRegInfo - If this instruction is embedded into a MachineFunction,
158/// return the MachineRegisterInfo object for the current function, otherwise
159/// return null.
160MachineRegisterInfo *MachineInstr::getRegInfo() {
161 if (MachineBasicBlock *MBB = getParent())
162 return &MBB->getParent()->getRegInfo();
163 return nullptr;
164}
165
166/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
167/// this instruction from their respective use lists. This requires that the
168/// operands already be on their use lists.
169void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170 for (MachineOperand &MO : operands())
171 if (MO.isReg())
172 MRI.removeRegOperandFromUseList(&MO);
173}
174
175/// AddRegOperandsToUseLists - Add all of the register operands in
176/// this instruction from their respective use lists. This requires that the
177/// operands not be on their use lists yet.
178void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
179 for (MachineOperand &MO : operands())
180 if (MO.isReg())
181 MRI.addRegOperandToUseList(&MO);
182}
183
184void MachineInstr::addOperand(const MachineOperand &Op) {
185 MachineBasicBlock *MBB = getParent();
186 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")((MBB && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? static_cast<void> (0) : __assert_fail ("MBB && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 186, __PRETTY_FUNCTION__))
;
187 MachineFunction *MF = MBB->getParent();
188 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")((MF && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? static_cast<void> (0) : __assert_fail ("MF && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 188, __PRETTY_FUNCTION__))
;
189 addOperand(*MF, Op);
190}
191
192/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
193/// ranges. If MRI is non-null also update use-def chains.
194static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
195 unsigned NumOps, MachineRegisterInfo *MRI) {
196 if (MRI)
197 return MRI->moveOperands(Dst, Src, NumOps);
198 // MachineOperand is a trivially copyable type so we can just use memmove.
199 assert(Dst && Src && "Unknown operands")((Dst && Src && "Unknown operands") ? static_cast
<void> (0) : __assert_fail ("Dst && Src && \"Unknown operands\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 199, __PRETTY_FUNCTION__))
;
200 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
201}
202
203/// addOperand - Add the specified operand to the instruction. If it is an
204/// implicit operand, it is added to the end of the operand list. If it is
205/// an explicit operand it is added at the end of the explicit operand list
206/// (before the first implicit operand).
207void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
208 assert(MCID && "Cannot add operands before providing an instr descriptor")((MCID && "Cannot add operands before providing an instr descriptor"
) ? static_cast<void> (0) : __assert_fail ("MCID && \"Cannot add operands before providing an instr descriptor\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 208, __PRETTY_FUNCTION__))
;
209
210 // Check if we're adding one of our existing operands.
211 if (&Op >= Operands && &Op < Operands + NumOperands) {
212 // This is unusual: MI->addOperand(MI->getOperand(i)).
213 // If adding Op requires reallocating or moving existing operands around,
214 // the Op reference could go stale. Support it by copying Op.
215 MachineOperand CopyOp(Op);
216 return addOperand(MF, CopyOp);
217 }
218
219 // Find the insert location for the new operand. Implicit registers go at
220 // the end, everything else goes before the implicit regs.
221 //
222 // FIXME: Allow mixed explicit and implicit operands on inline asm.
223 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
224 // implicit-defs, but they must not be moved around. See the FIXME in
225 // InstrEmitter.cpp.
226 unsigned OpNo = getNumOperands();
227 bool isImpReg = Op.isReg() && Op.isImplicit();
228 if (!isImpReg && !isInlineAsm()) {
229 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
230 --OpNo;
231 assert(!Operands[OpNo].isTied() && "Cannot move tied operands")((!Operands[OpNo].isTied() && "Cannot move tied operands"
) ? static_cast<void> (0) : __assert_fail ("!Operands[OpNo].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 231, __PRETTY_FUNCTION__))
;
232 }
233 }
234
235#ifndef NDEBUG
236 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
237 Op.getType() == MachineOperand::MO_MCSymbol;
238 // OpNo now points as the desired insertion point. Unless this is a variadic
239 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
240 // RegMask operands go between the explicit and implicit operands.
241 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 243, __PRETTY_FUNCTION__))
242 OpNo < MCID->getNumOperands() || isDebugOp) &&(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 243, __PRETTY_FUNCTION__))
243 "Trying to add an operand to a machine instr that is already done!")(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 243, __PRETTY_FUNCTION__))
;
244#endif
245
246 MachineRegisterInfo *MRI = getRegInfo();
247
248 // Determine if the Operands array needs to be reallocated.
249 // Save the old capacity and operand array.
250 OperandCapacity OldCap = CapOperands;
251 MachineOperand *OldOperands = Operands;
252 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
253 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
254 Operands = MF.allocateOperandArray(CapOperands);
255 // Move the operands before the insertion point.
256 if (OpNo)
257 moveOperands(Operands, OldOperands, OpNo, MRI);
258 }
259
260 // Move the operands following the insertion point.
261 if (OpNo != NumOperands)
262 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
263 MRI);
264 ++NumOperands;
265
266 // Deallocate the old operand array.
267 if (OldOperands != Operands && OldOperands)
268 MF.deallocateOperandArray(OldCap, OldOperands);
269
270 // Copy Op into place. It still needs to be inserted into the MRI use lists.
271 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
272 NewMO->ParentMI = this;
273
274 // When adding a register operand, tell MRI about it.
275 if (NewMO->isReg()) {
276 // Ensure isOnRegUseList() returns false, regardless of Op's status.
277 NewMO->Contents.Reg.Prev = nullptr;
278 // Ignore existing ties. This is not a property that can be copied.
279 NewMO->TiedTo = 0;
280 // Add the new operand to MRI, but only for instructions in an MBB.
281 if (MRI)
282 MRI->addRegOperandToUseList(NewMO);
283 // The MCID operand information isn't accurate until we start adding
284 // explicit operands. The implicit operands are added first, then the
285 // explicits are inserted before them.
286 if (!isImpReg) {
287 // Tie uses to defs as indicated in MCInstrDesc.
288 if (NewMO->isUse()) {
289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290 if (DefIdx != -1)
291 tieOperands(DefIdx, OpNo);
292 }
293 // If the register operand is flagged as early, mark the operand as such.
294 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
295 NewMO->setIsEarlyClobber(true);
296 }
297 }
298}
299
300/// RemoveOperand - Erase an operand from an instruction, leaving it with one
301/// fewer operand than it started with.
302///
303void MachineInstr::RemoveOperand(unsigned OpNo) {
304 assert(OpNo < getNumOperands() && "Invalid operand number")((OpNo < getNumOperands() && "Invalid operand number"
) ? static_cast<void> (0) : __assert_fail ("OpNo < getNumOperands() && \"Invalid operand number\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 304, __PRETTY_FUNCTION__))
;
305 untieRegOperand(OpNo);
306
307#ifndef NDEBUG
308 // Moving tied operands would break the ties.
309 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
310 if (Operands[i].isReg())
311 assert(!Operands[i].isTied() && "Cannot move tied operands")((!Operands[i].isTied() && "Cannot move tied operands"
) ? static_cast<void> (0) : __assert_fail ("!Operands[i].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 311, __PRETTY_FUNCTION__))
;
312#endif
313
314 MachineRegisterInfo *MRI = getRegInfo();
315 if (MRI && Operands[OpNo].isReg())
316 MRI->removeRegOperandFromUseList(Operands + OpNo);
317
318 // Don't call the MachineOperand destructor. A lot of this code depends on
319 // MachineOperand having a trivial destructor anyway, and adding a call here
320 // wouldn't make it 'destructor-correct'.
321
322 if (unsigned N = NumOperands - 1 - OpNo)
323 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
324 --NumOperands;
325}
326
327void MachineInstr::setExtraInfo(MachineFunction &MF,
328 ArrayRef<MachineMemOperand *> MMOs,
329 MCSymbol *PreInstrSymbol,
330 MCSymbol *PostInstrSymbol,
331 MDNode *HeapAllocMarker) {
332 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
333 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
334 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
335 int NumPointers =
336 MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
337
338 // Drop all extra info if there is none.
339 if (NumPointers <= 0) {
340 Info.clear();
341 return;
342 }
343
344 // If more than one pointer, then store out of line. Store heap alloc markers
345 // out of line because PointerSumType cannot hold more than 4 tag types with
346 // 32-bit pointers.
347 // FIXME: Maybe we should make the symbols in the extra info mutable?
348 else if (NumPointers > 1 || HasHeapAllocMarker) {
349 Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
350 MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
351 return;
352 }
353
354 // Otherwise store the single pointer inline.
355 if (HasPreInstrSymbol)
356 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
357 else if (HasPostInstrSymbol)
358 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
359 else
360 Info.set<EIIK_MMO>(MMOs[0]);
361}
362
363void MachineInstr::dropMemRefs(MachineFunction &MF) {
364 if (memoperands_empty())
365 return;
366
367 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
368 getHeapAllocMarker());
369}
370
371void MachineInstr::setMemRefs(MachineFunction &MF,
372 ArrayRef<MachineMemOperand *> MMOs) {
373 if (MMOs.empty()) {
374 dropMemRefs(MF);
375 return;
376 }
377
378 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
379 getHeapAllocMarker());
380}
381
382void MachineInstr::addMemOperand(MachineFunction &MF,
383 MachineMemOperand *MO) {
384 SmallVector<MachineMemOperand *, 2> MMOs;
385 MMOs.append(memoperands_begin(), memoperands_end());
386 MMOs.push_back(MO);
387 setMemRefs(MF, MMOs);
388}
389
390void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
391 if (this == &MI)
392 // Nothing to do for a self-clone!
393 return;
394
395 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 396, __PRETTY_FUNCTION__))
396 "Invalid machine functions when cloning memory refrences!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 396, __PRETTY_FUNCTION__))
;
397 // See if we can just steal the extra info already allocated for the
398 // instruction. We can do this whenever the pre- and post-instruction symbols
399 // are the same (including null).
400 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
401 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
402 getHeapAllocMarker() == MI.getHeapAllocMarker()) {
403 Info = MI.Info;
404 return;
405 }
406
407 // Otherwise, fall back on a copy-based clone.
408 setMemRefs(MF, MI.memoperands());
409}
410
411/// Check to see if the MMOs pointed to by the two MemRefs arrays are
412/// identical.
413static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
414 ArrayRef<MachineMemOperand *> RHS) {
415 if (LHS.size() != RHS.size())
416 return false;
417
418 auto LHSPointees = make_pointee_range(LHS);
419 auto RHSPointees = make_pointee_range(RHS);
420 return std::equal(LHSPointees.begin(), LHSPointees.end(),
421 RHSPointees.begin());
422}
423
424void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
425 ArrayRef<const MachineInstr *> MIs) {
426 // Try handling easy numbers of MIs with simpler mechanisms.
427 if (MIs.empty()) {
428 dropMemRefs(MF);
429 return;
430 }
431 if (MIs.size() == 1) {
432 cloneMemRefs(MF, *MIs[0]);
433 return;
434 }
435 // Because an empty memoperands list provides *no* information and must be
436 // handled conservatively (assuming the instruction can do anything), the only
437 // way to merge with it is to drop all other memoperands.
438 if (MIs[0]->memoperands_empty()) {
439 dropMemRefs(MF);
440 return;
441 }
442
443 // Handle the general case.
444 SmallVector<MachineMemOperand *, 2> MergedMMOs;
445 // Start with the first instruction.
446 assert(&MF == MIs[0]->getMF() &&((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 447, __PRETTY_FUNCTION__))
447 "Invalid machine functions when cloning memory references!")((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 447, __PRETTY_FUNCTION__))
;
448 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
449 // Now walk all the other instructions and accumulate any different MMOs.
450 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
451 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 452, __PRETTY_FUNCTION__))
452 "Invalid machine functions when cloning memory references!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 452, __PRETTY_FUNCTION__))
;
453
454 // Skip MIs with identical operands to the first. This is a somewhat
455 // arbitrary hack but will catch common cases without being quadratic.
456 // TODO: We could fully implement merge semantics here if needed.
457 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
458 continue;
459
460 // Because an empty memoperands list provides *no* information and must be
461 // handled conservatively (assuming the instruction can do anything), the
462 // only way to merge with it is to drop all other memoperands.
463 if (MI.memoperands_empty()) {
464 dropMemRefs(MF);
465 return;
466 }
467
468 // Otherwise accumulate these into our temporary buffer of the merged state.
469 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
470 }
471
472 setMemRefs(MF, MergedMMOs);
473}
474
475void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
476 // Do nothing if old and new symbols are the same.
477 if (Symbol == getPreInstrSymbol())
478 return;
479
480 // If there was only one symbol and we're removing it, just clear info.
481 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
482 Info.clear();
483 return;
484 }
485
486 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
487 getHeapAllocMarker());
488}
489
490void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
491 // Do nothing if old and new symbols are the same.
492 if (Symbol == getPostInstrSymbol())
493 return;
494
495 // If there was only one symbol and we're removing it, just clear info.
496 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
497 Info.clear();
498 return;
499 }
500
501 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
502 getHeapAllocMarker());
503}
504
505void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
506 // Do nothing if old and new symbols are the same.
507 if (Marker == getHeapAllocMarker())
508 return;
509
510 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
511 Marker);
512}
513
514void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
515 const MachineInstr &MI) {
516 if (this == &MI)
517 // Nothing to do for a self-clone!
518 return;
519
520 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 521, __PRETTY_FUNCTION__))
521 "Invalid machine functions when cloning instruction symbols!")((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 521, __PRETTY_FUNCTION__))
;
522
523 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
524 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
525 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
526}
527
528uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
529 // For now, the just return the union of the flags. If the flags get more
530 // complicated over time, we might need more logic here.
531 return getFlags() | Other.getFlags();
532}
533
534uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
535 uint16_t MIFlags = 0;
536 // Copy the wrapping flags.
537 if (const OverflowingBinaryOperator *OB =
538 dyn_cast<OverflowingBinaryOperator>(&I)) {
539 if (OB->hasNoSignedWrap())
540 MIFlags |= MachineInstr::MIFlag::NoSWrap;
541 if (OB->hasNoUnsignedWrap())
542 MIFlags |= MachineInstr::MIFlag::NoUWrap;
543 }
544
545 // Copy the exact flag.
546 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
547 if (PE->isExact())
548 MIFlags |= MachineInstr::MIFlag::IsExact;
549
550 // Copy the fast-math flags.
551 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
552 const FastMathFlags Flags = FP->getFastMathFlags();
553 if (Flags.noNaNs())
554 MIFlags |= MachineInstr::MIFlag::FmNoNans;
555 if (Flags.noInfs())
556 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
557 if (Flags.noSignedZeros())
558 MIFlags |= MachineInstr::MIFlag::FmNsz;
559 if (Flags.allowReciprocal())
560 MIFlags |= MachineInstr::MIFlag::FmArcp;
561 if (Flags.allowContract())
562 MIFlags |= MachineInstr::MIFlag::FmContract;
563 if (Flags.approxFunc())
564 MIFlags |= MachineInstr::MIFlag::FmAfn;
565 if (Flags.allowReassoc())
566 MIFlags |= MachineInstr::MIFlag::FmReassoc;
567 }
568
569 return MIFlags;
570}
571
572void MachineInstr::copyIRFlags(const Instruction &I) {
573 Flags = copyFlagsFromInstruction(I);
574}
575
576bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
577 assert(!isBundledWithPred() && "Must be called on bundle header")((!isBundledWithPred() && "Must be called on bundle header"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"Must be called on bundle header\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 577, __PRETTY_FUNCTION__))
;
578 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
579 if (MII->getDesc().getFlags() & Mask) {
580 if (Type == AnyInBundle)
581 return true;
582 } else {
583 if (Type == AllInBundle && !MII->isBundle())
584 return false;
585 }
586 // This was the last instruction in the bundle.
587 if (!MII->isBundledWithSucc())
588 return Type == AllInBundle;
589 }
590}
591
592bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
593 MICheckType Check) const {
594 // If opcodes or number of operands are not the same then the two
595 // instructions are obviously not identical.
596 if (Other.getOpcode() != getOpcode() ||
597 Other.getNumOperands() != getNumOperands())
598 return false;
599
600 if (isBundle()) {
601 // We have passed the test above that both instructions have the same
602 // opcode, so we know that both instructions are bundles here. Let's compare
603 // MIs inside the bundle.
604 assert(Other.isBundle() && "Expected that both instructions are bundles.")((Other.isBundle() && "Expected that both instructions are bundles."
) ? static_cast<void> (0) : __assert_fail ("Other.isBundle() && \"Expected that both instructions are bundles.\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 604, __PRETTY_FUNCTION__))
;
605 MachineBasicBlock::const_instr_iterator I1 = getIterator();
606 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
607 // Loop until we analysed the last intruction inside at least one of the
608 // bundles.
609 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
610 ++I1;
611 ++I2;
612 if (!I1->isIdenticalTo(*I2, Check))
613 return false;
614 }
615 // If we've reached the end of just one of the two bundles, but not both,
616 // the instructions are not identical.
617 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
618 return false;
619 }
620
621 // Check operands to make sure they match.
622 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
623 const MachineOperand &MO = getOperand(i);
624 const MachineOperand &OMO = Other.getOperand(i);
625 if (!MO.isReg()) {
626 if (!MO.isIdenticalTo(OMO))
627 return false;
628 continue;
629 }
630
631 // Clients may or may not want to ignore defs when testing for equality.
632 // For example, machine CSE pass only cares about finding common
633 // subexpressions, so it's safe to ignore virtual register defs.
634 if (MO.isDef()) {
635 if (Check == IgnoreDefs)
636 continue;
637 else if (Check == IgnoreVRegDefs) {
638 if (!Register::isVirtualRegister(MO.getReg()) ||
639 !Register::isVirtualRegister(OMO.getReg()))
640 if (!MO.isIdenticalTo(OMO))
641 return false;
642 } else {
643 if (!MO.isIdenticalTo(OMO))
644 return false;
645 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
646 return false;
647 }
648 } else {
649 if (!MO.isIdenticalTo(OMO))
650 return false;
651 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
652 return false;
653 }
654 }
655 // If DebugLoc does not match then two debug instructions are not identical.
656 if (isDebugInstr())
657 if (getDebugLoc() && Other.getDebugLoc() &&
658 getDebugLoc() != Other.getDebugLoc())
659 return false;
660 return true;
661}
662
663const MachineFunction *MachineInstr::getMF() const {
664 return getParent()->getParent();
665}
666
667MachineInstr *MachineInstr::removeFromParent() {
668 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 668, __PRETTY_FUNCTION__))
;
669 return getParent()->remove(this);
670}
671
672MachineInstr *MachineInstr::removeFromBundle() {
673 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 673, __PRETTY_FUNCTION__))
;
674 return getParent()->remove_instr(this);
675}
676
677void MachineInstr::eraseFromParent() {
678 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 678, __PRETTY_FUNCTION__))
;
679 getParent()->erase(this);
680}
681
682void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
683 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 683, __PRETTY_FUNCTION__))
;
684 MachineBasicBlock *MBB = getParent();
685 MachineFunction *MF = MBB->getParent();
686 assert(MF && "Not embedded in a function!")((MF && "Not embedded in a function!") ? static_cast<
void> (0) : __assert_fail ("MF && \"Not embedded in a function!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 686, __PRETTY_FUNCTION__))
;
687
688 MachineInstr *MI = (MachineInstr *)this;
689 MachineRegisterInfo &MRI = MF->getRegInfo();
690
691 for (const MachineOperand &MO : MI->operands()) {
692 if (!MO.isReg() || !MO.isDef())
693 continue;
694 Register Reg = MO.getReg();
695 if (!Reg.isVirtual())
696 continue;
697 MRI.markUsesInDebugValueAsUndef(Reg);
698 }
699 MI->eraseFromParent();
700}
701
702void MachineInstr::eraseFromBundle() {
703 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 703, __PRETTY_FUNCTION__))
;
704 getParent()->erase_instr(this);
705}
706
707bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const {
708 if (!isCall(Type))
709 return false;
710 switch (getOpcode()) {
711 case TargetOpcode::PATCHABLE_EVENT_CALL:
712 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
713 case TargetOpcode::PATCHPOINT:
714 case TargetOpcode::STACKMAP:
715 case TargetOpcode::STATEPOINT:
716 case TargetOpcode::FENTRY_CALL:
717 return false;
718 }
719 return true;
720}
721
722bool MachineInstr::shouldUpdateCallSiteInfo() const {
723 if (isBundle())
724 return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle);
725 return isCandidateForCallSiteEntry();
726}
727
728unsigned MachineInstr::getNumExplicitOperands() const {
729 unsigned NumOperands = MCID->getNumOperands();
730 if (!MCID->isVariadic())
731 return NumOperands;
732
733 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
734 const MachineOperand &MO = getOperand(I);
735 // The operands must always be in the following order:
736 // - explicit reg defs,
737 // - other explicit operands (reg uses, immediates, etc.),
738 // - implicit reg defs
739 // - implicit reg uses
740 if (MO.isReg() && MO.isImplicit())
741 break;
742 ++NumOperands;
743 }
744 return NumOperands;
745}
746
747unsigned MachineInstr::getNumExplicitDefs() const {
748 unsigned NumDefs = MCID->getNumDefs();
749 if (!MCID->isVariadic())
750 return NumDefs;
751
752 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
753 const MachineOperand &MO = getOperand(I);
754 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
755 break;
756 ++NumDefs;
757 }
758 return NumDefs;
759}
760
761void MachineInstr::bundleWithPred() {
762 assert(!isBundledWithPred() && "MI is already bundled with its predecessor")((!isBundledWithPred() && "MI is already bundled with its predecessor"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"MI is already bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 762, __PRETTY_FUNCTION__))
;
763 setFlag(BundledPred);
764 MachineBasicBlock::instr_iterator Pred = getIterator();
765 --Pred;
766 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")((!Pred->isBundledWithSucc() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("!Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 766, __PRETTY_FUNCTION__))
;
767 Pred->setFlag(BundledSucc);
768}
769
770void MachineInstr::bundleWithSucc() {
771 assert(!isBundledWithSucc() && "MI is already bundled with its successor")((!isBundledWithSucc() && "MI is already bundled with its successor"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithSucc() && \"MI is already bundled with its successor\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 771, __PRETTY_FUNCTION__))
;
772 setFlag(BundledSucc);
773 MachineBasicBlock::instr_iterator Succ = getIterator();
774 ++Succ;
775 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")((!Succ->isBundledWithPred() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("!Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 775, __PRETTY_FUNCTION__))
;
776 Succ->setFlag(BundledPred);
777}
778
779void MachineInstr::unbundleFromPred() {
780 assert(isBundledWithPred() && "MI isn't bundled with its predecessor")((isBundledWithPred() && "MI isn't bundled with its predecessor"
) ? static_cast<void> (0) : __assert_fail ("isBundledWithPred() && \"MI isn't bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 780, __PRETTY_FUNCTION__))
;
781 clearFlag(BundledPred);
782 MachineBasicBlock::instr_iterator Pred = getIterator();
783 --Pred;
784 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")((Pred->isBundledWithSucc() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 784, __PRETTY_FUNCTION__))
;
785 Pred->clearFlag(BundledSucc);
786}
787
788void MachineInstr::unbundleFromSucc() {
789 assert(isBundledWithSucc() && "MI isn't bundled with its successor")((isBundledWithSucc() && "MI isn't bundled with its successor"
) ? static_cast<void> (0) : __assert_fail ("isBundledWithSucc() && \"MI isn't bundled with its successor\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 789, __PRETTY_FUNCTION__))
;
790 clearFlag(BundledSucc);
791 MachineBasicBlock::instr_iterator Succ = getIterator();
792 ++Succ;
793 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")((Succ->isBundledWithPred() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 793, __PRETTY_FUNCTION__))
;
794 Succ->clearFlag(BundledPred);
795}
796
797bool MachineInstr::isStackAligningInlineAsm() const {
798 if (isInlineAsm()) {
799 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
800 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
801 return true;
802 }
803 return false;
804}
805
806InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
807 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")((isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"
) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"getInlineAsmDialect() only works for inline asms!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 807, __PRETTY_FUNCTION__))
;
808 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
809 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
810}
811
812int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
813 unsigned *GroupNo) const {
814 assert(isInlineAsm() && "Expected an inline asm instruction")((isInlineAsm() && "Expected an inline asm instruction"
) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"Expected an inline asm instruction\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 814, __PRETTY_FUNCTION__))
;
815 assert(OpIdx < getNumOperands() && "OpIdx out of range")((OpIdx < getNumOperands() && "OpIdx out of range"
) ? static_cast<void> (0) : __assert_fail ("OpIdx < getNumOperands() && \"OpIdx out of range\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 815, __PRETTY_FUNCTION__))
;
816
817 // Ignore queries about the initial operands.
818 if (OpIdx < InlineAsm::MIOp_FirstOperand)
819 return -1;
820
821 unsigned Group = 0;
822 unsigned NumOps;
823 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
824 i += NumOps) {
825 const MachineOperand &FlagMO = getOperand(i);
826 // If we reach the implicit register operands, stop looking.
827 if (!FlagMO.isImm())
828 return -1;
829 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
830 if (i + NumOps > OpIdx) {
831 if (GroupNo)
832 *GroupNo = Group;
833 return i;
834 }
835 ++Group;
836 }
837 return -1;
838}
839
840const DILabel *MachineInstr::getDebugLabel() const {
841 assert(isDebugLabel() && "not a DBG_LABEL")((isDebugLabel() && "not a DBG_LABEL") ? static_cast<
void> (0) : __assert_fail ("isDebugLabel() && \"not a DBG_LABEL\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 841, __PRETTY_FUNCTION__))
;
842 return cast<DILabel>(getOperand(0).getMetadata());
843}
844
845const MachineOperand &MachineInstr::getDebugVariableOp() const {
846 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 846, __PRETTY_FUNCTION__))
;
847 return getOperand(2);
848}
849
850MachineOperand &MachineInstr::getDebugVariableOp() {
851 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 851, __PRETTY_FUNCTION__))
;
852 return getOperand(2);
853}
854
855const DILocalVariable *MachineInstr::getDebugVariable() const {
856 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 856, __PRETTY_FUNCTION__))
;
857 return cast<DILocalVariable>(getOperand(2).getMetadata());
858}
859
860MachineOperand &MachineInstr::getDebugExpressionOp() {
861 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 861, __PRETTY_FUNCTION__))
;
862 return getOperand(3);
863}
864
865const DIExpression *MachineInstr::getDebugExpression() const {
866 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE")(((isDebugValue() || isDebugRef()) && "not a DBG_VALUE"
) ? static_cast<void> (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 866, __PRETTY_FUNCTION__))
;
867 return cast<DIExpression>(getOperand(3).getMetadata());
868}
869
870bool MachineInstr::isDebugEntryValue() const {
871 return isDebugValue() && getDebugExpression()->isEntryValue();
872}
873
874const TargetRegisterClass*
875MachineInstr::getRegClassConstraint(unsigned OpIdx,
876 const TargetInstrInfo *TII,
877 const TargetRegisterInfo *TRI) const {
878 assert(getParent() && "Can't have an MBB reference here!")((getParent() && "Can't have an MBB reference here!")
? static_cast<void> (0) : __assert_fail ("getParent() && \"Can't have an MBB reference here!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 878, __PRETTY_FUNCTION__))
;
879 assert(getMF() && "Can't have an MF reference here!")((getMF() && "Can't have an MF reference here!") ? static_cast
<void> (0) : __assert_fail ("getMF() && \"Can't have an MF reference here!\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 879, __PRETTY_FUNCTION__))
;
880 const MachineFunction &MF = *getMF();
881
882 // Most opcodes have fixed constraints in their MCInstrDesc.
883 if (!isInlineAsm())
884 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
885
886 if (!getOperand(OpIdx).isReg())
887 return nullptr;
888
889 // For tied uses on inline asm, get the constraint from the def.
890 unsigned DefIdx;
891 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
892 OpIdx = DefIdx;
893
894 // Inline asm stores register class constraints in the flag word.
895 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
896 if (FlagIdx < 0)
897 return nullptr;
898
899 unsigned Flag = getOperand(FlagIdx).getImm();
900 unsigned RCID;
901 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
902 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
903 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
904 InlineAsm::hasRegClassConstraint(Flag, RCID))
905 return TRI->getRegClass(RCID);
906
907 // Assume that all registers in a memory operand are pointers.
908 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
909 return TRI->getPointerRegClass(MF);
910
911 return nullptr;
912}
913
914const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
915 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
916 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
917 // Check every operands inside the bundle if we have
918 // been asked to.
919 if (ExploreBundle)
920 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
921 ++OpndIt)
922 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
923 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
924 else
925 // Otherwise, just check the current operands.
926 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
927 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
928 return CurRC;
929}
930
931const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
932 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
933 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
934 assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast
<void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 934, __PRETTY_FUNCTION__))
;
935 // Check if Reg is constrained by some of its use/def from MI.
936 const MachineOperand &MO = getOperand(OpIdx);
937 if (!MO.isReg() || MO.getReg() != Reg)
938 return CurRC;
939 // If yes, accumulate the constraints through the operand.
940 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
941}
942
943const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
944 unsigned OpIdx, const TargetRegisterClass *CurRC,
945 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
946 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
947 const MachineOperand &MO = getOperand(OpIdx);
948 assert(MO.isReg() &&((MO.isReg() && "Cannot get register constraints for non-register operand"
) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 949, __PRETTY_FUNCTION__))
949 "Cannot get register constraints for non-register operand")((MO.isReg() && "Cannot get register constraints for non-register operand"
) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 949, __PRETTY_FUNCTION__))
;
950 assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast
<void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 950, __PRETTY_FUNCTION__))
;
951 if (unsigned SubIdx = MO.getSubReg()) {
952 if (OpRC)
953 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
954 else
955 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
956 } else if (OpRC)
957 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
958 return CurRC;
959}
960
961/// Return the number of instructions inside the MI bundle, not counting the
962/// header instruction.
963unsigned MachineInstr::getBundleSize() const {
964 MachineBasicBlock::const_instr_iterator I = getIterator();
965 unsigned Size = 0;
966 while (I->isBundledWithSucc()) {
967 ++Size;
968 ++I;
969 }
970 return Size;
971}
972
973/// Returns true if the MachineInstr has an implicit-use operand of exactly
974/// the given register (not considering sub/super-registers).
975bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
976 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
977 const MachineOperand &MO = getOperand(i);
978 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
979 return true;
980 }
981 return false;
982}
983
984/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
985/// the specific register or -1 if it is not found. It further tightens
986/// the search criteria to a use that kills the register if isKill is true.
987int MachineInstr::findRegisterUseOperandIdx(
988 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
989 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
990 const MachineOperand &MO = getOperand(i);
991 if (!MO.isReg() || !MO.isUse())
992 continue;
993 Register MOReg = MO.getReg();
994 if (!MOReg)
995 continue;
996 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
997 if (!isKill || MO.isKill())
998 return i;
999 }
1000 return -1;
1001}
1002
1003/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1004/// indicating if this instruction reads or writes Reg. This also considers
1005/// partial defines.
1006std::pair<bool,bool>
1007MachineInstr::readsWritesVirtualRegister(Register Reg,
1008 SmallVectorImpl<unsigned> *Ops) const {
1009 bool PartDef = false; // Partial redefine.
1010 bool FullDef = false; // Full define.
1011 bool Use = false;
1012
1013 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1014 const MachineOperand &MO = getOperand(i);
1015 if (!MO.isReg() || MO.getReg() != Reg)
1016 continue;
1017 if (Ops)
1018 Ops->push_back(i);
1019 if (MO.isUse())
1020 Use |= !MO.isUndef();
1021 else if (MO.getSubReg() && !MO.isUndef())
1022 // A partial def undef doesn't count as reading the register.
1023 PartDef = true;
1024 else
1025 FullDef = true;
1026 }
1027 // A partial redefine uses Reg unless there is also a full define.
1028 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1029}
1030
1031/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1032/// the specified register or -1 if it is not found. If isDead is true, defs
1033/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1034/// also checks if there is a def of a super-register.
1035int
1036MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
1037 const TargetRegisterInfo *TRI) const {
1038 bool isPhys = Register::isPhysicalRegister(Reg);
1039 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1040 const MachineOperand &MO = getOperand(i);
1041 // Accept regmask operands when Overlap is set.
1042 // Ignore them when looking for a specific def operand (Overlap == false).
1043 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1044 return i;
1045 if (!MO.isReg() || !MO.isDef())
1046 continue;
1047 Register MOReg = MO.getReg();
1048 bool Found = (MOReg == Reg);
1049 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1050 if (Overlap)
1051 Found = TRI->regsOverlap(MOReg, Reg);
1052 else
1053 Found = TRI->isSubRegister(MOReg, Reg);
1054 }
1055 if (Found && (!isDead || MO.isDead()))
1056 return i;
1057 }
1058 return -1;
1059}
1060
1061/// findFirstPredOperandIdx() - Find the index of the first operand in the
1062/// operand list that is used to represent the predicate. It returns -1 if
1063/// none is found.
1064int MachineInstr::findFirstPredOperandIdx() const {
1065 // Don't call MCID.findFirstPredOperandIdx() because this variant
1066 // is sometimes called on an instruction that's not yet complete, and
1067 // so the number of operands is less than the MCID indicates. In
1068 // particular, the PTX target does this.
1069 const MCInstrDesc &MCID = getDesc();
1070 if (MCID.isPredicable()) {
1071 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1072 if (MCID.OpInfo[i].isPredicate())
1073 return i;
1074 }
1075
1076 return -1;
1077}
1078
1079// MachineOperand::TiedTo is 4 bits wide.
1080const unsigned TiedMax = 15;
1081
1082/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1083///
1084/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1085/// field. TiedTo can have these values:
1086///
1087/// 0: Operand is not tied to anything.
1088/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1089/// TiedMax: Tied to an operand >= TiedMax-1.
1090///
1091/// The tied def must be one of the first TiedMax operands on a normal
1092/// instruction. INLINEASM instructions allow more tied defs.
1093///
1094void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1095 MachineOperand &DefMO = getOperand(DefIdx);
1096 MachineOperand &UseMO = getOperand(UseIdx);
1097 assert(DefMO.isDef() && "DefIdx must be a def operand")((DefMO.isDef() && "DefIdx must be a def operand") ? static_cast
<void> (0) : __assert_fail ("DefMO.isDef() && \"DefIdx must be a def operand\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1097, __PRETTY_FUNCTION__))
;
1098 assert(UseMO.isUse() && "UseIdx must be a use operand")((UseMO.isUse() && "UseIdx must be a use operand") ? static_cast
<void> (0) : __assert_fail ("UseMO.isUse() && \"UseIdx must be a use operand\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1098, __PRETTY_FUNCTION__))
;
1099 assert(!DefMO.isTied() && "Def is already tied to another use")((!DefMO.isTied() && "Def is already tied to another use"
) ? static_cast<void> (0) : __assert_fail ("!DefMO.isTied() && \"Def is already tied to another use\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1099, __PRETTY_FUNCTION__))
;
1100 assert(!UseMO.isTied() && "Use is already tied to another def")((!UseMO.isTied() && "Use is already tied to another def"
) ? static_cast<void> (0) : __assert_fail ("!UseMO.isTied() && \"Use is already tied to another def\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1100, __PRETTY_FUNCTION__))
;
1101
1102 if (DefIdx < TiedMax)
1103 UseMO.TiedTo = DefIdx + 1;
1104 else {
1105 // Inline asm can use the group descriptors to find tied operands,
1106 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1107 // but on normal instruction, the tied def must be within the first TiedMax
1108 // operands.
1109 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&(((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
"DefIdx out of range") ? static_cast<void> (0) : __assert_fail
("(isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) && \"DefIdx out of range\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1110, __PRETTY_FUNCTION__))
1110 "DefIdx out of range")(((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&
"DefIdx out of range") ? static_cast<void> (0) : __assert_fail
("(isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) && \"DefIdx out of range\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1110, __PRETTY_FUNCTION__))
;
1111 UseMO.TiedTo = TiedMax;
1112 }
1113
1114 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1115 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1116}
1117
1118/// Given the index of a tied register operand, find the operand it is tied to.
1119/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1120/// which must exist.
1121unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1122 const MachineOperand &MO = getOperand(OpIdx);
1123 assert(MO.isTied() && "Operand isn't tied")((MO.isTied() && "Operand isn't tied") ? static_cast<
void> (0) : __assert_fail ("MO.isTied() && \"Operand isn't tied\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1123, __PRETTY_FUNCTION__))
;
1124
1125 // Normally TiedTo is in range.
1126 if (MO.TiedTo < TiedMax)
1127 return MO.TiedTo - 1;
1128
1129 // Uses on normal instructions can be out of range.
1130 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1131 // Normal tied defs must be in the 0..TiedMax-1 range.
1132 if (MO.isUse())
1133 return TiedMax - 1;
1134 // MO is a def. Search for the tied use.
1135 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1136 const MachineOperand &UseMO = getOperand(i);
1137 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1138 return i;
1139 }
1140 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1140)
;
1141 }
1142
1143 if (getOpcode() == TargetOpcode::STATEPOINT) {
1144 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1145 // on registers.
1146 StatepointOpers SO(this);
1147 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1148 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied")((CurUseIdx != -1U && "only gc pointer statepoint operands can be tied"
) ? static_cast<void> (0) : __assert_fail ("CurUseIdx != -1U && \"only gc pointer statepoint operands can be tied\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1148, __PRETTY_FUNCTION__))
;
1149 unsigned NumDefs = getNumDefs();
1150 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1151 while (!getOperand(CurUseIdx).isReg())
1152 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1153 if (OpIdx == CurDefIdx)
1154 return CurUseIdx;
1155 if (OpIdx == CurUseIdx)
1156 return CurDefIdx;
1157 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1158 }
1159 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1159)
;
1160 }
1161
1162 // Now deal with inline asm by parsing the operand group descriptor flags.
1163 // Find the beginning of each operand group.
1164 SmallVector<unsigned, 8> GroupIdx;
1165 unsigned OpIdxGroup = ~0u;
1166 unsigned NumOps;
1167 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1168 i += NumOps) {
1169 const MachineOperand &FlagMO = getOperand(i);
1170 assert(FlagMO.isImm() && "Invalid tied operand on inline asm")((FlagMO.isImm() && "Invalid tied operand on inline asm"
) ? static_cast<void> (0) : __assert_fail ("FlagMO.isImm() && \"Invalid tied operand on inline asm\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1170, __PRETTY_FUNCTION__))
;
1171 unsigned CurGroup = GroupIdx.size();
1172 GroupIdx.push_back(i);
1173 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1174 // OpIdx belongs to this operand group.
1175 if (OpIdx > i && OpIdx < i + NumOps)
1176 OpIdxGroup = CurGroup;
1177 unsigned TiedGroup;
1178 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1179 continue;
1180 // Operands in this group are tied to operands in TiedGroup which must be
1181 // earlier. Find the number of operands between the two groups.
1182 unsigned Delta = i - GroupIdx[TiedGroup];
1183
1184 // OpIdx is a use tied to TiedGroup.
1185 if (OpIdxGroup == CurGroup)
1186 return OpIdx - Delta;
1187
1188 // OpIdx is a def tied to this use group.
1189 if (OpIdxGroup == TiedGroup)
1190 return OpIdx + Delta;
1191 }
1192 llvm_unreachable("Invalid tied operand on inline asm")::llvm::llvm_unreachable_internal("Invalid tied operand on inline asm"
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1192)
;
1193}
1194
1195/// clearKillInfo - Clears kill flags on all operands.
1196///
1197void MachineInstr::clearKillInfo() {
1198 for (MachineOperand &MO : operands()) {
1199 if (MO.isReg() && MO.isUse())
1200 MO.setIsKill(false);
1201 }
1202}
1203
1204void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1205 unsigned SubIdx,
1206 const TargetRegisterInfo &RegInfo) {
1207 if (Register::isPhysicalRegister(ToReg)) {
1208 if (SubIdx)
1209 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1210 for (MachineOperand &MO : operands()) {
1211 if (!MO.isReg() || MO.getReg() != FromReg)
1212 continue;
1213 MO.substPhysReg(ToReg, RegInfo);
1214 }
1215 } else {
1216 for (MachineOperand &MO : operands()) {
1217 if (!MO.isReg() || MO.getReg() != FromReg)
1218 continue;
1219 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1220 }
1221 }
1222}
1223
1224/// isSafeToMove - Return true if it is safe to move this instruction. If
1225/// SawStore is set to true, it means that there is a store (or call) between
1226/// the instruction's location and its intended destination.
1227bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1228 // Ignore stuff that we obviously can't move.
1229 //
1230 // Treat volatile loads as stores. This is not strictly necessary for
1231 // volatiles, but it is required for atomic loads. It is not allowed to move
1232 // a load across an atomic load with Ordering > Monotonic.
1233 if (mayStore() || isCall() || isPHI() ||
1234 (mayLoad() && hasOrderedMemoryRef())) {
1235 SawStore = true;
1236 return false;
1237 }
1238
1239 if (isPosition() || isDebugInstr() || isTerminator() ||
1240 mayRaiseFPException() || hasUnmodeledSideEffects())
1241 return false;
1242
1243 // See if this instruction does a load. If so, we have to guarantee that the
1244 // loaded value doesn't change between the load and the its intended
1245 // destination. The check for isInvariantLoad gives the target the chance to
1246 // classify the load as always returning a constant, e.g. a constant pool
1247 // load.
1248 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1249 // Otherwise, this is a real load. If there is a store between the load and
1250 // end of block, we can't move it.
1251 return !SawStore;
1252
1253 return true;
1254}
1255
1256static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
1257 bool UseTBAA, const MachineMemOperand *MMOa,
1258 const MachineMemOperand *MMOb) {
1259 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1260 // operates with MachineMemOperand offset with some important assumptions:
1261 // - LLVM fundamentally assumes flat address spaces.
1262 // - MachineOperand offset can *only* result from legalization and cannot
1263 // affect queries other than the trivial case of overlap checking.
1264 // - These offsets never wrap and never step outside of allocated objects.
1265 // - There should never be any negative offsets here.
1266 //
1267 // FIXME: Modify API to hide this math from "user"
1268 // Even before we go to AA we can reason locally about some memory objects. It
1269 // can save compile time, and possibly catch some corner cases not currently
1270 // covered.
1271
1272 int64_t OffsetA = MMOa->getOffset();
1273 int64_t OffsetB = MMOb->getOffset();
1274 int64_t MinOffset = std::min(OffsetA, OffsetB);
1275
1276 uint64_t WidthA = MMOa->getSize();
1277 uint64_t WidthB = MMOb->getSize();
1278 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1279 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1280
1281 const Value *ValA = MMOa->getValue();
1282 const Value *ValB = MMOb->getValue();
1283 bool SameVal = (ValA && ValB && (ValA == ValB));
1284 if (!SameVal) {
1285 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1286 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1287 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1288 return false;
1289 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1290 return false;
1291 if (PSVa && PSVb && (PSVa == PSVb))
1292 SameVal = true;
1293 }
1294
1295 if (SameVal) {
1296 if (!KnownWidthA || !KnownWidthB)
1297 return true;
1298 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1299 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1300 return (MinOffset + LowWidth > MaxOffset);
1301 }
1302
1303 if (!AA)
1304 return true;
1305
1306 if (!ValA || !ValB)
1307 return true;
1308
1309 assert((OffsetA >= 0) && "Negative MachineMemOperand offset")(((OffsetA >= 0) && "Negative MachineMemOperand offset"
) ? static_cast<void> (0) : __assert_fail ("(OffsetA >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1309, __PRETTY_FUNCTION__))
;
1310 assert((OffsetB >= 0) && "Negative MachineMemOperand offset")(((OffsetB >= 0) && "Negative MachineMemOperand offset"
) ? static_cast<void> (0) : __assert_fail ("(OffsetB >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1310, __PRETTY_FUNCTION__))
;
1311
1312 int64_t OverlapA =
1313 KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1314 int64_t OverlapB =
1315 KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1316
1317 AliasResult AAResult = AA->alias(
1318 MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1319 MemoryLocation(ValB, OverlapB,
1320 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1321
1322 return (AAResult != NoAlias);
1323}
1324
1325bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1326 bool UseTBAA) const {
1327 const MachineFunction *MF = getMF();
1328 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1329 const MachineFrameInfo &MFI = MF->getFrameInfo();
1330
1331 // Exclude call instruction which may alter the memory but can not be handled
1332 // by this function.
1333 if (isCall() || Other.isCall())
1334 return true;
1335
1336 // If neither instruction stores to memory, they can't alias in any
1337 // meaningful way, even if they read from the same address.
1338 if (!mayStore() && !Other.mayStore())
1339 return false;
1340
1341 // Both instructions must be memory operations to be able to alias.
1342 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1343 return false;
1344
1345 // Let the target decide if memory accesses cannot possibly overlap.
1346 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1347 return false;
1348
1349 // Memory operations without memory operands may access anything. Be
1350 // conservative and assume `MayAlias`.
1351 if (memoperands_empty() || Other.memoperands_empty())
1352 return true;
1353
1354 // Skip if there are too many memory operands.
1355 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1356 if (NumChecks > TII->getMemOperandAACheckLimit())
1357 return true;
1358
1359 // Check each pair of memory operands from both instructions, which can't
1360 // alias only if all pairs won't alias.
1361 for (auto *MMOa : memoperands())
1362 for (auto *MMOb : Other.memoperands())
1363 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1364 return true;
1365
1366 return false;
1367}
1368
1369/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1370/// or volatile memory reference, or if the information describing the memory
1371/// reference is not available. Return false if it is known to have no ordered
1372/// memory references.
1373bool MachineInstr::hasOrderedMemoryRef() const {
1374 // An instruction known never to access memory won't have a volatile access.
1375 if (!mayStore() &&
1376 !mayLoad() &&
1377 !isCall() &&
1378 !hasUnmodeledSideEffects())
1379 return false;
1380
1381 // Otherwise, if the instruction has no memory reference information,
1382 // conservatively assume it wasn't preserved.
1383 if (memoperands_empty())
1384 return true;
1385
1386 // Check if any of our memory operands are ordered.
1387 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1388 return !MMO->isUnordered();
1389 });
1390}
1391
1392/// isDereferenceableInvariantLoad - Return true if this instruction will never
1393/// trap and is loading from a location whose value is invariant across a run of
1394/// this function.
1395bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
1396 // If the instruction doesn't load at all, it isn't an invariant load.
1397 if (!mayLoad())
1398 return false;
1399
1400 // If the instruction has lost its memoperands, conservatively assume that
1401 // it may not be an invariant load.
1402 if (memoperands_empty())
1403 return false;
1404
1405 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1406
1407 for (MachineMemOperand *MMO : memoperands()) {
1408 if (!MMO->isUnordered())
1409 // If the memory operand has ordering side effects, we can't move the
1410 // instruction. Such an instruction is technically an invariant load,
1411 // but the caller code would need updated to expect that.
1412 return false;
1413 if (MMO->isStore()) return false;
1414 if (MMO->isInvariant() && MMO->isDereferenceable())
1415 continue;
1416
1417 // A load from a constant PseudoSourceValue is invariant.
1418 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1419 if (PSV->isConstant(&MFI))
1420 continue;
1421
1422 if (const Value *V = MMO->getValue()) {
1423 // If we have an AliasAnalysis, ask it whether the memory is constant.
1424 if (AA &&
1425 AA->pointsToConstantMemory(
1426 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1427 continue;
1428 }
1429
1430 // Otherwise assume conservatively.
1431 return false;
1432 }
1433
1434 // Everything checks out.
1435 return true;
1436}
1437
1438/// isConstantValuePHI - If the specified instruction is a PHI that always
1439/// merges together the same virtual register, return the register, otherwise
1440/// return 0.
1441unsigned MachineInstr::isConstantValuePHI() const {
1442 if (!isPHI())
1443 return 0;
1444 assert(getNumOperands() >= 3 &&((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1445, __PRETTY_FUNCTION__))
1445 "It's illegal to have a PHI without source operands")((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1445, __PRETTY_FUNCTION__))
;
1446
1447 Register Reg = getOperand(1).getReg();
1448 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1449 if (getOperand(i).getReg() != Reg)
1450 return 0;
1451 return Reg;
1452}
1453
1454bool MachineInstr::hasUnmodeledSideEffects() const {
1455 if (hasProperty(MCID::UnmodeledSideEffects))
1456 return true;
1457 if (isInlineAsm()) {
1458 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1459 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1460 return true;
1461 }
1462
1463 return false;
1464}
1465
1466bool MachineInstr::isLoadFoldBarrier() const {
1467 return mayStore() || isCall() || hasUnmodeledSideEffects();
1468}
1469
1470/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1471///
1472bool MachineInstr::allDefsAreDead() const {
1473 for (const MachineOperand &MO : operands()) {
1474 if (!MO.isReg() || MO.isUse())
1475 continue;
1476 if (!MO.isDead())
1477 return false;
1478 }
1479 return true;
1480}
1481
1482/// copyImplicitOps - Copy implicit register operands from specified
1483/// instruction to this instruction.
1484void MachineInstr::copyImplicitOps(MachineFunction &MF,
1485 const MachineInstr &MI) {
1486 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1487 i != e; ++i) {
1488 const MachineOperand &MO = MI.getOperand(i);
1489 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1490 addOperand(MF, MO);
1491 }
1492}
1493
1494bool MachineInstr::hasComplexRegisterTies() const {
1495 const MCInstrDesc &MCID = getDesc();
1496 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1497 return true;
1498 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1499 const auto &Operand = getOperand(I);
1500 if (!Operand.isReg() || Operand.isDef())
1501 // Ignore the defined registers as MCID marks only the uses as tied.
1502 continue;
1503 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1504 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1505 if (ExpectedTiedIdx != TiedIdx)
1506 return true;
1507 }
1508 return false;
1509}
1510
1511LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1512 const MachineRegisterInfo &MRI) const {
1513 const MachineOperand &Op = getOperand(OpIdx);
1514 if (!Op.isReg())
1515 return LLT{};
1516
1517 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1518 return MRI.getType(Op.getReg());
1519
1520 auto &OpInfo = getDesc().OpInfo[OpIdx];
1521 if (!OpInfo.isGenericType())
1522 return MRI.getType(Op.getReg());
1523
1524 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1525 return LLT{};
1526
1527 LLT TypeToPrint = MRI.getType(Op.getReg());
1528 // Don't mark the type index printed if it wasn't actually printed: maybe
1529 // another operand with the same type index has an actual type attached:
1530 if (TypeToPrint.isValid())
1531 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1532 return TypeToPrint;
1533}
1534
1535#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1536LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dump() const {
1537 dbgs() << " ";
1538 print(dbgs());
1539}
1540
1541LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dumprImpl(
1542 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1543 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1544 if (Depth >= MaxDepth)
1545 return;
1546 if (!AlreadySeenInstrs.insert(this).second)
1547 return;
1548 // PadToColumn always inserts at least one space.
1549 // Don't mess up the alignment if we don't want any space.
1550 if (Depth)
1551 fdbgs().PadToColumn(Depth * 2);
1552 print(fdbgs());
1553 for (const MachineOperand &MO : operands()) {
1554 if (!MO.isReg() || MO.isDef())
1555 continue;
1556 Register Reg = MO.getReg();
1557 if (Reg.isPhysical())
1558 continue;
1559 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1560 if (NewMI == nullptr)
1561 continue;
1562 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1563 }
1564}
1565
1566LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1567 unsigned MaxDepth) const {
1568 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1569 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1570}
1571#endif
1572
1573void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1574 bool SkipDebugLoc, bool AddNewLine,
1575 const TargetInstrInfo *TII) const {
1576 const Module *M = nullptr;
1577 const Function *F = nullptr;
1578 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1579 F = &MF->getFunction();
1580 M = F->getParent();
1581 if (!TII)
1582 TII = MF->getSubtarget().getInstrInfo();
1583 }
1584
1585 ModuleSlotTracker MST(M);
1586 if (F)
1587 MST.incorporateFunction(*F);
1588 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1589}
1590
1591void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1592 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1593 bool AddNewLine, const TargetInstrInfo *TII) const {
1594 // We can be a bit tidier if we know the MachineFunction.
1595 const TargetRegisterInfo *TRI = nullptr;
1596 const MachineRegisterInfo *MRI = nullptr;
1597 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1598 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1599
1600 if (isCFIInstruction())
1601 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")((getNumOperands() == 1 && "Expected 1 operand in CFI instruction"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() == 1 && \"Expected 1 operand in CFI instruction\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 1601, __PRETTY_FUNCTION__))
;
1602
1603 SmallBitVector PrintedTypes(8);
1604 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1605 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1606 if (!ShouldPrintRegisterTies)
1607 return 0U;
1608 const MachineOperand &MO = getOperand(OpIdx);
1609 if (MO.isReg() && MO.isTied() && !MO.isDef())
1610 return findTiedOperandIdx(OpIdx);
1611 return 0U;
1612 };
1613 unsigned StartOp = 0;
1614 unsigned e = getNumOperands();
1615
1616 // Print explicitly defined operands on the left of an assignment syntax.
1617 while (StartOp < e) {
1618 const MachineOperand &MO = getOperand(StartOp);
1619 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1620 break;
1621
1622 if (StartOp != 0)
1623 OS << ", ";
1624
1625 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1626 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1627 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1628 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1629 ++StartOp;
1630 }
1631
1632 if (StartOp != 0)
1633 OS << " = ";
1634
1635 if (getFlag(MachineInstr::FrameSetup))
1636 OS << "frame-setup ";
1637 if (getFlag(MachineInstr::FrameDestroy))
1638 OS << "frame-destroy ";
1639 if (getFlag(MachineInstr::FmNoNans))
1640 OS << "nnan ";
1641 if (getFlag(MachineInstr::FmNoInfs))
1642 OS << "ninf ";
1643 if (getFlag(MachineInstr::FmNsz))
1644 OS << "nsz ";
1645 if (getFlag(MachineInstr::FmArcp))
1646 OS << "arcp ";
1647 if (getFlag(MachineInstr::FmContract))
1648 OS << "contract ";
1649 if (getFlag(MachineInstr::FmAfn))
1650 OS << "afn ";
1651 if (getFlag(MachineInstr::FmReassoc))
1652 OS << "reassoc ";
1653 if (getFlag(MachineInstr::NoUWrap))
1654 OS << "nuw ";
1655 if (getFlag(MachineInstr::NoSWrap))
1656 OS << "nsw ";
1657 if (getFlag(MachineInstr::IsExact))
1658 OS << "exact ";
1659 if (getFlag(MachineInstr::NoFPExcept))
1660 OS << "nofpexcept ";
1661 if (getFlag(MachineInstr::NoMerge))
1662 OS << "nomerge ";
1663
1664 // Print the opcode name.
1665 if (TII)
1666 OS << TII->getName(getOpcode());
1667 else
1668 OS << "UNKNOWN";
1669
1670 if (SkipOpers)
1671 return;
1672
1673 // Print the rest of the operands.
1674 bool FirstOp = true;
1675 unsigned AsmDescOp = ~0u;
1676 unsigned AsmOpCount = 0;
1677
1678 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1679 // Print asm string.
1680 OS << " ";
1681 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1682 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1683 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1684 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1685 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1686 IntrinsicInfo);
1687
1688 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1689 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1690 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1691 OS << " [sideeffect]";
1692 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1693 OS << " [mayload]";
1694 if (ExtraInfo & InlineAsm::Extra_MayStore)
1695 OS << " [maystore]";
1696 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1697 OS << " [isconvergent]";
1698 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1699 OS << " [alignstack]";
1700 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1701 OS << " [attdialect]";
1702 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1703 OS << " [inteldialect]";
1704
1705 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1706 FirstOp = false;
1707 }
1708
1709 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1710 const MachineOperand &MO = getOperand(i);
1711
1712 if (FirstOp) FirstOp = false; else OS << ",";
1713 OS << " ";
1714
1715 if (isDebugValue() && MO.isMetadata()) {
1716 // Pretty print DBG_VALUE instructions.
1717 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1718 if (DIV && !DIV->getName().empty())
1719 OS << "!\"" << DIV->getName() << '\"';
1720 else {
1721 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1722 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1723 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1724 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1725 }
1726 } else if (isDebugLabel() && MO.isMetadata()) {
1727 // Pretty print DBG_LABEL instructions.
1728 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1729 if (DIL && !DIL->getName().empty())
1730 OS << "\"" << DIL->getName() << '\"';
1731 else {
1732 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1733 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1734 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1735 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1736 }
1737 } else if (i == AsmDescOp && MO.isImm()) {
1738 // Pretty print the inline asm operand descriptor.
1739 OS << '$' << AsmOpCount++;
1740 unsigned Flag = MO.getImm();
1741 OS << ":[";
1742 OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
1743
1744 unsigned RCID = 0;
1745 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1746 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1747 if (TRI) {
1748 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1749 } else
1750 OS << ":RC" << RCID;
1751 }
1752
1753 if (InlineAsm::isMemKind(Flag)) {
1754 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1755 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1756 }
1757
1758 unsigned TiedTo = 0;
1759 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1760 OS << " tiedto:$" << TiedTo;
1761
1762 OS << ']';
1763
1764 // Compute the index of the next operand descriptor.
1765 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1766 } else {
1767 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1768 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1769 if (MO.isImm() && isOperandSubregIdx(i))
1770 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1771 else
1772 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1773 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1774 }
1775 }
1776
1777 // Print any optional symbols attached to this instruction as-if they were
1778 // operands.
1779 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1780 if (!FirstOp) {
1781 FirstOp = false;
1782 OS << ',';
1783 }
1784 OS << " pre-instr-symbol ";
1785 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1786 }
1787 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1788 if (!FirstOp) {
1789 FirstOp = false;
1790 OS << ',';
1791 }
1792 OS << " post-instr-symbol ";
1793 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1794 }
1795 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1796 if (!FirstOp) {
1797 FirstOp = false;
1798 OS << ',';
1799 }
1800 OS << " heap-alloc-marker ";
1801 HeapAllocMarker->printAsOperand(OS, MST);
1802 }
1803
1804 if (DebugInstrNum) {
1805 if (!FirstOp)
1806 OS << ",";
1807 OS << " debug-instr-number " << DebugInstrNum;
1808 }
1809
1810 if (!SkipDebugLoc) {
1811 if (const DebugLoc &DL = getDebugLoc()) {
1812 if (!FirstOp)
1813 OS << ',';
1814 OS << " debug-location ";
1815 DL->printAsOperand(OS, MST);
1816 }
1817 }
1818
1819 if (!memoperands_empty()) {
1820 SmallVector<StringRef, 0> SSNs;
1821 const LLVMContext *Context = nullptr;
1822 std::unique_ptr<LLVMContext> CtxPtr;
1823 const MachineFrameInfo *MFI = nullptr;
1824 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1825 MFI = &MF->getFrameInfo();
1826 Context = &MF->getFunction().getContext();
1827 } else {
1828 CtxPtr = std::make_unique<LLVMContext>();
1829 Context = CtxPtr.get();
1830 }
1831
1832 OS << " :: ";
1833 bool NeedComma = false;
1834 for (const MachineMemOperand *Op : memoperands()) {
1835 if (NeedComma)
1836 OS << ", ";
1837 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1838 NeedComma = true;
1839 }
1840 }
1841
1842 if (SkipDebugLoc)
1843 return;
1844
1845 bool HaveSemi = false;
1846
1847 // Print debug location information.
1848 if (const DebugLoc &DL = getDebugLoc()) {
1849 if (!HaveSemi) {
1850 OS << ';';
1851 HaveSemi = true;
1852 }
1853 OS << ' ';
1854 DL.print(OS);
1855 }
1856
1857 // Print extra comments for DEBUG_VALUE.
1858 if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1859 if (!HaveSemi) {
1860 OS << ";";
1861 HaveSemi = true;
Value stored to 'HaveSemi' is never read
1862 }
1863 auto *DV = getDebugVariable();
1864 OS << " line no:" << DV->getLine();
1865 if (isIndirectDebugValue())
1866 OS << " indirect";
1867 }
1868 // TODO: DBG_LABEL
1869
1870 if (AddNewLine)
1871 OS << '\n';
1872}
1873
1874bool MachineInstr::addRegisterKilled(Register IncomingReg,
1875 const TargetRegisterInfo *RegInfo,
1876 bool AddIfNotFound) {
1877 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1878 bool hasAliases = isPhysReg &&
1879 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1880 bool Found = false;
1881 SmallVector<unsigned,4> DeadOps;
1882 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1883 MachineOperand &MO = getOperand(i);
1884 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1885 continue;
1886
1887 // DEBUG_VALUE nodes do not contribute to code generation and should
1888 // always be ignored. Failure to do so may result in trying to modify
1889 // KILL flags on DEBUG_VALUE nodes.
1890 if (MO.isDebug())
1891 continue;
1892
1893 Register Reg = MO.getReg();
1894 if (!Reg)
1895 continue;
1896
1897 if (Reg == IncomingReg) {
1898 if (!Found) {
1899 if (MO.isKill())
1900 // The register is already marked kill.
1901 return true;
1902 if (isPhysReg && isRegTiedToDefOperand(i))
1903 // Two-address uses of physregs must not be marked kill.
1904 return true;
1905 MO.setIsKill();
1906 Found = true;
1907 }
1908 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1909 // A super-register kill already exists.
1910 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1911 return true;
1912 if (RegInfo->isSubRegister(IncomingReg, Reg))
1913 DeadOps.push_back(i);
1914 }
1915 }
1916
1917 // Trim unneeded kill operands.
1918 while (!DeadOps.empty()) {
1919 unsigned OpIdx = DeadOps.back();
1920 if (getOperand(OpIdx).isImplicit() &&
1921 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1922 RemoveOperand(OpIdx);
1923 else
1924 getOperand(OpIdx).setIsKill(false);
1925 DeadOps.pop_back();
1926 }
1927
1928 // If not found, this means an alias of one of the operands is killed. Add a
1929 // new implicit operand if required.
1930 if (!Found && AddIfNotFound) {
1931 addOperand(MachineOperand::CreateReg(IncomingReg,
1932 false /*IsDef*/,
1933 true /*IsImp*/,
1934 true /*IsKill*/));
1935 return true;
1936 }
1937 return Found;
1938}
1939
1940void MachineInstr::clearRegisterKills(Register Reg,
1941 const TargetRegisterInfo *RegInfo) {
1942 if (!Register::isPhysicalRegister(Reg))
1943 RegInfo = nullptr;
1944 for (MachineOperand &MO : operands()) {
1945 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1946 continue;
1947 Register OpReg = MO.getReg();
1948 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1949 MO.setIsKill(false);
1950 }
1951}
1952
1953bool MachineInstr::addRegisterDead(Register Reg,
1954 const TargetRegisterInfo *RegInfo,
1955 bool AddIfNotFound) {
1956 bool isPhysReg = Register::isPhysicalRegister(Reg);
1957 bool hasAliases = isPhysReg &&
1958 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1959 bool Found = false;
1960 SmallVector<unsigned,4> DeadOps;
1961 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1962 MachineOperand &MO = getOperand(i);
1963 if (!MO.isReg() || !MO.isDef())
1964 continue;
1965 Register MOReg = MO.getReg();
1966 if (!MOReg)
1967 continue;
1968
1969 if (MOReg == Reg) {
1970 MO.setIsDead();
1971 Found = true;
1972 } else if (hasAliases && MO.isDead() &&
1973 Register::isPhysicalRegister(MOReg)) {
1974 // There exists a super-register that's marked dead.
1975 if (RegInfo->isSuperRegister(Reg, MOReg))
1976 return true;
1977 if (RegInfo->isSubRegister(Reg, MOReg))
1978 DeadOps.push_back(i);
1979 }
1980 }
1981
1982 // Trim unneeded dead operands.
1983 while (!DeadOps.empty()) {
1984 unsigned OpIdx = DeadOps.back();
1985 if (getOperand(OpIdx).isImplicit() &&
1986 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1987 RemoveOperand(OpIdx);
1988 else
1989 getOperand(OpIdx).setIsDead(false);
1990 DeadOps.pop_back();
1991 }
1992
1993 // If not found, this means an alias of one of the operands is dead. Add a
1994 // new implicit operand if required.
1995 if (Found || !AddIfNotFound)
1996 return Found;
1997
1998 addOperand(MachineOperand::CreateReg(Reg,
1999 true /*IsDef*/,
2000 true /*IsImp*/,
2001 false /*IsKill*/,
2002 true /*IsDead*/));
2003 return true;
2004}
2005
2006void MachineInstr::clearRegisterDeads(Register Reg) {
2007 for (MachineOperand &MO : operands()) {
2008 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2009 continue;
2010 MO.setIsDead(false);
2011 }
2012}
2013
2014void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2015 for (MachineOperand &MO : operands()) {
2016 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2017 continue;
2018 MO.setIsUndef(IsUndef);
2019 }
2020}
2021
2022void MachineInstr::addRegisterDefined(Register Reg,
2023 const TargetRegisterInfo *RegInfo) {
2024 if (Register::isPhysicalRegister(Reg)) {
2025 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2026 if (MO)
2027 return;
2028 } else {
2029 for (const MachineOperand &MO : operands()) {
2030 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2031 MO.getSubReg() == 0)
2032 return;
2033 }
2034 }
2035 addOperand(MachineOperand::CreateReg(Reg,
2036 true /*IsDef*/,
2037 true /*IsImp*/));
2038}
2039
2040void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
2041 const TargetRegisterInfo &TRI) {
2042 bool HasRegMask = false;
2043 for (MachineOperand &MO : operands()) {
2044 if (MO.isRegMask()) {
2045 HasRegMask = true;
2046 continue;
2047 }
2048 if (!MO.isReg() || !MO.isDef()) continue;
2049 Register Reg = MO.getReg();
2050 if (!Reg.isPhysical())
2051 continue;
2052 // If there are no uses, including partial uses, the def is dead.
2053 if (llvm::none_of(UsedRegs,
2054 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2055 MO.setIsDead();
2056 }
2057
2058 // This is a call with a register mask operand.
2059 // Mask clobbers are always dead, so add defs for the non-dead defines.
2060 if (HasRegMask)
2061 for (ArrayRef<Register>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
2062 I != E; ++I)
2063 addRegisterDefined(*I, &TRI);
2064}
2065
2066unsigned
2067MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2068 // Build up a buffer of hash code components.
2069 SmallVector<size_t, 16> HashComponents;
2070 HashComponents.reserve(MI->getNumOperands() + 1);
2071 HashComponents.push_back(MI->getOpcode());
2072 for (const MachineOperand &MO : MI->operands()) {
2073 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2074 continue; // Skip virtual register defs.
2075
2076 HashComponents.push_back(hash_value(MO));
2077 }
2078 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2079}
2080
2081void MachineInstr::emitError(StringRef Msg) const {
2082 // Find the source location cookie.
2083 unsigned LocCookie = 0;
2084 const MDNode *LocMD = nullptr;
2085 for (unsigned i = getNumOperands(); i != 0; --i) {
2086 if (getOperand(i-1).isMetadata() &&
2087 (LocMD = getOperand(i-1).getMetadata()) &&
2088 LocMD->getNumOperands() != 0) {
2089 if (const ConstantInt *CI =
2090 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2091 LocCookie = CI->getZExtValue();
2092 break;
2093 }
2094 }
2095 }
2096
2097 if (const MachineBasicBlock *MBB = getParent())
2098 if (const MachineFunction *MF = MBB->getParent())
2099 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2100 report_fatal_error(Msg);
2101}
2102
2103MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2104 const MCInstrDesc &MCID, bool IsIndirect,
2105 Register Reg, const MDNode *Variable,
2106 const MDNode *Expr) {
2107 assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable"
) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2107, __PRETTY_FUNCTION__))
;
2108 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression"
) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2108, __PRETTY_FUNCTION__))
;
2109 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2110, __PRETTY_FUNCTION__))
2110 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2110, __PRETTY_FUNCTION__))
;
2111 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2112 if (IsIndirect)
2113 MIB.addImm(0U);
2114 else
2115 MIB.addReg(0U, RegState::Debug);
2116 return MIB.addMetadata(Variable).addMetadata(Expr);
2117}
2118
2119MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2120 const MCInstrDesc &MCID, bool IsIndirect,
2121 MachineOperand &MO, const MDNode *Variable,
2122 const MDNode *Expr) {
2123 assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable"
) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2123, __PRETTY_FUNCTION__))
;
2124 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression"
) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2124, __PRETTY_FUNCTION__))
;
2125 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2126, __PRETTY_FUNCTION__))
2126 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2126, __PRETTY_FUNCTION__))
;
2127 if (MO.isReg())
2128 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2129
2130 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2131 if (IsIndirect)
2132 MIB.addImm(0U);
2133 else
2134 MIB.addReg(0U, RegState::Debug);
2135 return MIB.addMetadata(Variable).addMetadata(Expr);
2136 }
2137
2138MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2139 MachineBasicBlock::iterator I,
2140 const DebugLoc &DL, const MCInstrDesc &MCID,
2141 bool IsIndirect, Register Reg,
2142 const MDNode *Variable, const MDNode *Expr) {
2143 MachineFunction &MF = *BB.getParent();
2144 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2145 BB.insert(I, MI);
2146 return MachineInstrBuilder(MF, MI);
2147}
2148
2149MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2150 MachineBasicBlock::iterator I,
2151 const DebugLoc &DL, const MCInstrDesc &MCID,
2152 bool IsIndirect, MachineOperand &MO,
2153 const MDNode *Variable, const MDNode *Expr) {
2154 MachineFunction &MF = *BB.getParent();
2155 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2156 BB.insert(I, MI);
2157 return MachineInstrBuilder(MF, *MI);
2158}
2159
2160/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2161/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2162static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
2163 assert(MI.getOperand(0).isReg() && "can't spill non-register")((MI.getOperand(0).isReg() && "can't spill non-register"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && \"can't spill non-register\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2163, __PRETTY_FUNCTION__))
;
2164 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc
()) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2165, __PRETTY_FUNCTION__))
2165 "Expected inlined-at fields to agree")((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc
()) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2165, __PRETTY_FUNCTION__))
;
2166
2167 const DIExpression *Expr = MI.getDebugExpression();
2168 if (MI.isIndirectDebugValue()) {
2169 assert(MI.getDebugOffset().getImm() == 0 &&((MI.getDebugOffset().getImm() == 0 && "DBG_VALUE with nonzero offset"
) ? static_cast<void> (0) : __assert_fail ("MI.getDebugOffset().getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2170, __PRETTY_FUNCTION__))
2170 "DBG_VALUE with nonzero offset")((MI.getDebugOffset().getImm() == 0 && "DBG_VALUE with nonzero offset"
) ? static_cast<void> (0) : __assert_fail ("MI.getDebugOffset().getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "/build/llvm-toolchain-snapshot-12~++20210124100612+2afaf072f5c1/llvm/lib/CodeGen/MachineInstr.cpp"
, 2170, __PRETTY_FUNCTION__))
;
2171 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2172 }
2173 return Expr;
2174}
2175
2176MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2177 MachineBasicBlock::iterator I,
2178 const MachineInstr &Orig,
2179 int FrameIndex) {
2180 const DIExpression *Expr = computeExprForSpill(Orig);
2181 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
2182 .addFrameIndex(FrameIndex)
2183 .addImm(0U)
2184 .addMetadata(Orig.getDebugVariable())
2185 .addMetadata(Expr);
2186}
2187
2188void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
2189 const DIExpression *Expr = computeExprForSpill(Orig);
2190 Orig.getDebugOperand(0).ChangeToFrameIndex(FrameIndex);
2191 Orig.getDebugOffset().ChangeToImmediate(0U);
2192 Orig.getDebugExpressionOp().setMetadata(Expr);
2193}
2194
2195void MachineInstr::collectDebugValues(
2196 SmallVectorImpl<MachineInstr *> &DbgValues) {
2197 MachineInstr &MI = *this;
2198 if (!MI.getOperand(0).isReg())
2199 return;
2200
2201 MachineBasicBlock::iterator DI = MI; ++DI;
2202 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2203 DI != DE; ++DI) {
2204 if (!DI->isDebugValue())
2205 return;
2206 if (DI->getDebugOperandForReg(MI.getOperand(0).getReg()))
2207 DbgValues.push_back(&*DI);
2208 }
2209}
2210
2211void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2212 // Collect matching debug values.
2213 SmallVector<MachineInstr *, 2> DbgValues;
2214
2215 if (!getOperand(0).isReg())
2216 return;
2217
2218 Register DefReg = getOperand(0).getReg();
2219 auto *MRI = getRegInfo();
2220 for (auto &MO : MRI->use_operands(DefReg)) {
2221 auto *DI = MO.getParent();
2222 if (!DI->isDebugValue())
2223 continue;
2224 if (DI->getDebugOperandForReg(DefReg)) {
2225 DbgValues.push_back(DI);
2226 }
2227 }
2228
2229 // Propagate Reg to debug value instructions.
2230 for (auto *DBI : DbgValues)
2231 DBI->getDebugOperandForReg(DefReg)->setReg(Reg);
2232}
2233
2234using MMOList = SmallVector<const MachineMemOperand *, 2>;
2235
2236static unsigned getSpillSlotSize(const MMOList &Accesses,
2237 const MachineFrameInfo &MFI) {
2238 unsigned Size = 0;
2239 for (auto A : Accesses)
2240 if (MFI.isSpillSlotObjectIndex(
2241 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2242 ->getFrameIndex()))
2243 Size += A->getSize();
2244 return Size;
2245}
2246
2247Optional<unsigned>
2248MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2249 int FI;
2250 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2251 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2252 if (MFI.isSpillSlotObjectIndex(FI))
2253 return (*memoperands_begin())->getSize();
2254 }
2255 return None;
2256}
2257
2258Optional<unsigned>
2259MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2260 MMOList Accesses;
2261 if (TII->hasStoreToStackSlot(*this, Accesses))
2262 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2263 return None;
2264}
2265
2266Optional<unsigned>
2267MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2268 int FI;
2269 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2270 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2271 if (MFI.isSpillSlotObjectIndex(FI))
2272 return (*memoperands_begin())->getSize();
2273 }
2274 return None;
2275}
2276
2277Optional<unsigned>
2278MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2279 MMOList Accesses;
2280 if (TII->hasLoadFromStackSlot(*this, Accesses))
2281 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2282 return None;
2283}
2284
2285unsigned MachineInstr::getDebugInstrNum() {
2286 if (DebugInstrNum == 0)
2287 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2288 return DebugInstrNum;
2289}