Bug Summary

File:llvm/lib/CodeGen/MachineInstr.cpp
Warning:line 1846, column 7
Value stored to 'HaveSemi' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name MachineInstr.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/CodeGen -I /build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/lib/CodeGen -I include -I /build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm=build-llvm -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm=build-llvm -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm=build-llvm -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/= -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-01-19-134126-35450-1 -x c++ /build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/lib/CodeGen/MachineInstr.cpp
1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/ADT/APFloat.h"
15#include "llvm/ADT/ArrayRef.h"
16#include "llvm/ADT/FoldingSet.h"
17#include "llvm/ADT/Hashing.h"
18#include "llvm/ADT/None.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SmallBitVector.h"
21#include "llvm/ADT/SmallString.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/Analysis/Loads.h"
25#include "llvm/Analysis/MemoryLocation.h"
26#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
27#include "llvm/CodeGen/MachineBasicBlock.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineInstrBundle.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/CodeGen/StackMaps.h"
38#include "llvm/CodeGen/TargetInstrInfo.h"
39#include "llvm/CodeGen/TargetRegisterInfo.h"
40#include "llvm/CodeGen/TargetSubtargetInfo.h"
41#include "llvm/Config/llvm-config.h"
42#include "llvm/IR/Constants.h"
43#include "llvm/IR/DebugInfoMetadata.h"
44#include "llvm/IR/DebugLoc.h"
45#include "llvm/IR/DerivedTypes.h"
46#include "llvm/IR/Function.h"
47#include "llvm/IR/InlineAsm.h"
48#include "llvm/IR/InstrTypes.h"
49#include "llvm/IR/Intrinsics.h"
50#include "llvm/IR/LLVMContext.h"
51#include "llvm/IR/Metadata.h"
52#include "llvm/IR/Module.h"
53#include "llvm/IR/ModuleSlotTracker.h"
54#include "llvm/IR/Operator.h"
55#include "llvm/IR/Type.h"
56#include "llvm/IR/Value.h"
57#include "llvm/MC/MCInstrDesc.h"
58#include "llvm/MC/MCRegisterInfo.h"
59#include "llvm/MC/MCSymbol.h"
60#include "llvm/Support/Casting.h"
61#include "llvm/Support/CommandLine.h"
62#include "llvm/Support/Compiler.h"
63#include "llvm/Support/Debug.h"
64#include "llvm/Support/ErrorHandling.h"
65#include "llvm/Support/FormattedStream.h"
66#include "llvm/Support/LowLevelTypeImpl.h"
67#include "llvm/Support/MathExtras.h"
68#include "llvm/Support/raw_ostream.h"
69#include "llvm/Target/TargetIntrinsicInfo.h"
70#include "llvm/Target/TargetMachine.h"
71#include <algorithm>
72#include <cassert>
73#include <cstddef>
74#include <cstdint>
75#include <cstring>
76#include <iterator>
77#include <utility>
78
79using namespace llvm;
80
81static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
82 if (const MachineBasicBlock *MBB = MI.getParent())
83 if (const MachineFunction *MF = MBB->getParent())
84 return MF;
85 return nullptr;
86}
87
88// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
89// it.
90static void tryToGetTargetInfo(const MachineInstr &MI,
91 const TargetRegisterInfo *&TRI,
92 const MachineRegisterInfo *&MRI,
93 const TargetIntrinsicInfo *&IntrinsicInfo,
94 const TargetInstrInfo *&TII) {
95
96 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
97 TRI = MF->getSubtarget().getRegisterInfo();
98 MRI = &MF->getRegInfo();
99 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
100 TII = MF->getSubtarget().getInstrInfo();
101 }
102}
103
104void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
105 if (MCID->ImplicitDefs)
106 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
107 ++ImpDefs)
108 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
109 if (MCID->ImplicitUses)
110 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
111 ++ImpUses)
112 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
113}
114
115/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
116/// implicit operands. It reserves space for the number of operands specified by
117/// the MCInstrDesc.
118MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
119 DebugLoc DL, bool NoImp)
120 : MCID(&TID), DbgLoc(std::move(DL)), DebugInstrNum(0) {
121 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (DbgLoc.hasTrivialDestructor() &&
"Expected trivial destructor") ? void (0) : __assert_fail ("DbgLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 121, __extension__ __PRETTY_FUNCTION__
))
;
122
123 // Reserve space for the expected number of operands.
124 if (unsigned NumOps = MCID->getNumOperands() +
125 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
126 CapOperands = OperandCapacity::get(NumOps);
127 Operands = MF.allocateOperandArray(CapOperands);
128 }
129
130 if (!NoImp)
131 addImplicitDefUseOperands(MF);
132}
133
134/// MachineInstr ctor - Copies MachineInstr arg exactly.
135/// Does not copy the number from debug instruction numbering, to preserve
136/// uniqueness.
137MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
138 : MCID(&MI.getDesc()), Info(MI.Info), DbgLoc(MI.getDebugLoc()),
139 DebugInstrNum(0) {
140 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (DbgLoc.hasTrivialDestructor() &&
"Expected trivial destructor") ? void (0) : __assert_fail ("DbgLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 140, __extension__ __PRETTY_FUNCTION__
))
;
141
142 CapOperands = OperandCapacity::get(MI.getNumOperands());
143 Operands = MF.allocateOperandArray(CapOperands);
144
145 // Copy operands.
146 for (const MachineOperand &MO : MI.operands())
147 addOperand(MF, MO);
148
149 // Copy all the sensible flags.
150 setFlags(MI.Flags);
151}
152
153void MachineInstr::moveBefore(MachineInstr *MovePos) {
154 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
155}
156
157/// getRegInfo - If this instruction is embedded into a MachineFunction,
158/// return the MachineRegisterInfo object for the current function, otherwise
159/// return null.
160MachineRegisterInfo *MachineInstr::getRegInfo() {
161 if (MachineBasicBlock *MBB = getParent())
162 return &MBB->getParent()->getRegInfo();
163 return nullptr;
164}
165
166/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
167/// this instruction from their respective use lists. This requires that the
168/// operands already be on their use lists.
169void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
170 for (MachineOperand &MO : operands())
171 if (MO.isReg())
172 MRI.removeRegOperandFromUseList(&MO);
173}
174
175/// AddRegOperandsToUseLists - Add all of the register operands in
176/// this instruction from their respective use lists. This requires that the
177/// operands not be on their use lists yet.
178void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
179 for (MachineOperand &MO : operands())
180 if (MO.isReg())
181 MRI.addRegOperandToUseList(&MO);
182}
183
184void MachineInstr::addOperand(const MachineOperand &Op) {
185 MachineBasicBlock *MBB = getParent();
186 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")(static_cast <bool> (MBB && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? void (0) : __assert_fail ("MBB && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 186, __extension__ __PRETTY_FUNCTION__
))
;
187 MachineFunction *MF = MBB->getParent();
188 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")(static_cast <bool> (MF && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? void (0) : __assert_fail ("MF && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 188, __extension__ __PRETTY_FUNCTION__
))
;
189 addOperand(*MF, Op);
190}
191
192/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
193/// ranges. If MRI is non-null also update use-def chains.
194static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
195 unsigned NumOps, MachineRegisterInfo *MRI) {
196 if (MRI)
197 return MRI->moveOperands(Dst, Src, NumOps);
198 // MachineOperand is a trivially copyable type so we can just use memmove.
199 assert(Dst && Src && "Unknown operands")(static_cast <bool> (Dst && Src && "Unknown operands"
) ? void (0) : __assert_fail ("Dst && Src && \"Unknown operands\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 199, __extension__ __PRETTY_FUNCTION__
))
;
200 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
201}
202
203/// addOperand - Add the specified operand to the instruction. If it is an
204/// implicit operand, it is added to the end of the operand list. If it is
205/// an explicit operand it is added at the end of the explicit operand list
206/// (before the first implicit operand).
207void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
208 assert(MCID && "Cannot add operands before providing an instr descriptor")(static_cast <bool> (MCID && "Cannot add operands before providing an instr descriptor"
) ? void (0) : __assert_fail ("MCID && \"Cannot add operands before providing an instr descriptor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 208, __extension__ __PRETTY_FUNCTION__
))
;
209
210 // Check if we're adding one of our existing operands.
211 if (&Op >= Operands && &Op < Operands + NumOperands) {
212 // This is unusual: MI->addOperand(MI->getOperand(i)).
213 // If adding Op requires reallocating or moving existing operands around,
214 // the Op reference could go stale. Support it by copying Op.
215 MachineOperand CopyOp(Op);
216 return addOperand(MF, CopyOp);
217 }
218
219 // Find the insert location for the new operand. Implicit registers go at
220 // the end, everything else goes before the implicit regs.
221 //
222 // FIXME: Allow mixed explicit and implicit operands on inline asm.
223 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
224 // implicit-defs, but they must not be moved around. See the FIXME in
225 // InstrEmitter.cpp.
226 unsigned OpNo = getNumOperands();
227 bool isImpReg = Op.isReg() && Op.isImplicit();
228 if (!isImpReg && !isInlineAsm()) {
229 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
230 --OpNo;
231 assert(!Operands[OpNo].isTied() && "Cannot move tied operands")(static_cast <bool> (!Operands[OpNo].isTied() &&
"Cannot move tied operands") ? void (0) : __assert_fail ("!Operands[OpNo].isTied() && \"Cannot move tied operands\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 231, __extension__ __PRETTY_FUNCTION__
))
;
232 }
233 }
234
235#ifndef NDEBUG
236 bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata ||
237 Op.getType() == MachineOperand::MO_MCSymbol;
238 // OpNo now points as the desired insertion point. Unless this is a variadic
239 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
240 // RegMask operands go between the explicit and implicit operands.
241 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||(static_cast <bool> ((isImpReg || Op.isRegMask() || MCID
->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp
) && "Trying to add an operand to a machine instr that is already done!"
) ? void (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 243, __extension__ __PRETTY_FUNCTION__
))
242 OpNo < MCID->getNumOperands() || isDebugOp) &&(static_cast <bool> ((isImpReg || Op.isRegMask() || MCID
->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp
) && "Trying to add an operand to a machine instr that is already done!"
) ? void (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 243, __extension__ __PRETTY_FUNCTION__
))
243 "Trying to add an operand to a machine instr that is already done!")(static_cast <bool> ((isImpReg || Op.isRegMask() || MCID
->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp
) && "Trying to add an operand to a machine instr that is already done!"
) ? void (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 243, __extension__ __PRETTY_FUNCTION__
))
;
244#endif
245
246 MachineRegisterInfo *MRI = getRegInfo();
247
248 // Determine if the Operands array needs to be reallocated.
249 // Save the old capacity and operand array.
250 OperandCapacity OldCap = CapOperands;
251 MachineOperand *OldOperands = Operands;
252 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
253 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
254 Operands = MF.allocateOperandArray(CapOperands);
255 // Move the operands before the insertion point.
256 if (OpNo)
257 moveOperands(Operands, OldOperands, OpNo, MRI);
258 }
259
260 // Move the operands following the insertion point.
261 if (OpNo != NumOperands)
262 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
263 MRI);
264 ++NumOperands;
265
266 // Deallocate the old operand array.
267 if (OldOperands != Operands && OldOperands)
268 MF.deallocateOperandArray(OldCap, OldOperands);
269
270 // Copy Op into place. It still needs to be inserted into the MRI use lists.
271 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
272 NewMO->ParentMI = this;
273
274 // When adding a register operand, tell MRI about it.
275 if (NewMO->isReg()) {
276 // Ensure isOnRegUseList() returns false, regardless of Op's status.
277 NewMO->Contents.Reg.Prev = nullptr;
278 // Ignore existing ties. This is not a property that can be copied.
279 NewMO->TiedTo = 0;
280 // Add the new operand to MRI, but only for instructions in an MBB.
281 if (MRI)
282 MRI->addRegOperandToUseList(NewMO);
283 // The MCID operand information isn't accurate until we start adding
284 // explicit operands. The implicit operands are added first, then the
285 // explicits are inserted before them.
286 if (!isImpReg) {
287 // Tie uses to defs as indicated in MCInstrDesc.
288 if (NewMO->isUse()) {
289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
290 if (DefIdx != -1)
291 tieOperands(DefIdx, OpNo);
292 }
293 // If the register operand is flagged as early, mark the operand as such.
294 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
295 NewMO->setIsEarlyClobber(true);
296 }
297 // Ensure debug instructions set debug flag on register uses.
298 if (NewMO->isUse() && isDebugInstr())
299 NewMO->setIsDebug();
300 }
301}
302
303/// RemoveOperand - Erase an operand from an instruction, leaving it with one
304/// fewer operand than it started with.
305///
306void MachineInstr::RemoveOperand(unsigned OpNo) {
307 assert(OpNo < getNumOperands() && "Invalid operand number")(static_cast <bool> (OpNo < getNumOperands() &&
"Invalid operand number") ? void (0) : __assert_fail ("OpNo < getNumOperands() && \"Invalid operand number\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 307, __extension__ __PRETTY_FUNCTION__
))
;
308 untieRegOperand(OpNo);
309
310#ifndef NDEBUG
311 // Moving tied operands would break the ties.
312 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
313 if (Operands[i].isReg())
314 assert(!Operands[i].isTied() && "Cannot move tied operands")(static_cast <bool> (!Operands[i].isTied() && "Cannot move tied operands"
) ? void (0) : __assert_fail ("!Operands[i].isTied() && \"Cannot move tied operands\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 314, __extension__ __PRETTY_FUNCTION__
))
;
315#endif
316
317 MachineRegisterInfo *MRI = getRegInfo();
318 if (MRI && Operands[OpNo].isReg())
319 MRI->removeRegOperandFromUseList(Operands + OpNo);
320
321 // Don't call the MachineOperand destructor. A lot of this code depends on
322 // MachineOperand having a trivial destructor anyway, and adding a call here
323 // wouldn't make it 'destructor-correct'.
324
325 if (unsigned N = NumOperands - 1 - OpNo)
326 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
327 --NumOperands;
328}
329
330void MachineInstr::setExtraInfo(MachineFunction &MF,
331 ArrayRef<MachineMemOperand *> MMOs,
332 MCSymbol *PreInstrSymbol,
333 MCSymbol *PostInstrSymbol,
334 MDNode *HeapAllocMarker) {
335 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
336 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
337 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
338 int NumPointers =
339 MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + HasHeapAllocMarker;
340
341 // Drop all extra info if there is none.
342 if (NumPointers <= 0) {
343 Info.clear();
344 return;
345 }
346
347 // If more than one pointer, then store out of line. Store heap alloc markers
348 // out of line because PointerSumType cannot hold more than 4 tag types with
349 // 32-bit pointers.
350 // FIXME: Maybe we should make the symbols in the extra info mutable?
351 else if (NumPointers > 1 || HasHeapAllocMarker) {
352 Info.set<EIIK_OutOfLine>(MF.createMIExtraInfo(
353 MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker));
354 return;
355 }
356
357 // Otherwise store the single pointer inline.
358 if (HasPreInstrSymbol)
359 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
360 else if (HasPostInstrSymbol)
361 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
362 else
363 Info.set<EIIK_MMO>(MMOs[0]);
364}
365
366void MachineInstr::dropMemRefs(MachineFunction &MF) {
367 if (memoperands_empty())
368 return;
369
370 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
371 getHeapAllocMarker());
372}
373
374void MachineInstr::setMemRefs(MachineFunction &MF,
375 ArrayRef<MachineMemOperand *> MMOs) {
376 if (MMOs.empty()) {
377 dropMemRefs(MF);
378 return;
379 }
380
381 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
382 getHeapAllocMarker());
383}
384
385void MachineInstr::addMemOperand(MachineFunction &MF,
386 MachineMemOperand *MO) {
387 SmallVector<MachineMemOperand *, 2> MMOs;
388 MMOs.append(memoperands_begin(), memoperands_end());
389 MMOs.push_back(MO);
390 setMemRefs(MF, MMOs);
391}
392
393void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
394 if (this == &MI)
395 // Nothing to do for a self-clone!
396 return;
397
398 assert(&MF == MI.getMF() &&(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 399, __extension__ __PRETTY_FUNCTION__
))
399 "Invalid machine functions when cloning memory refrences!")(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 399, __extension__ __PRETTY_FUNCTION__
))
;
400 // See if we can just steal the extra info already allocated for the
401 // instruction. We can do this whenever the pre- and post-instruction symbols
402 // are the same (including null).
403 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
404 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
405 getHeapAllocMarker() == MI.getHeapAllocMarker()) {
406 Info = MI.Info;
407 return;
408 }
409
410 // Otherwise, fall back on a copy-based clone.
411 setMemRefs(MF, MI.memoperands());
412}
413
414/// Check to see if the MMOs pointed to by the two MemRefs arrays are
415/// identical.
416static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
417 ArrayRef<MachineMemOperand *> RHS) {
418 if (LHS.size() != RHS.size())
419 return false;
420
421 auto LHSPointees = make_pointee_range(LHS);
422 auto RHSPointees = make_pointee_range(RHS);
423 return std::equal(LHSPointees.begin(), LHSPointees.end(),
424 RHSPointees.begin());
425}
426
427void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
428 ArrayRef<const MachineInstr *> MIs) {
429 // Try handling easy numbers of MIs with simpler mechanisms.
430 if (MIs.empty()) {
431 dropMemRefs(MF);
432 return;
433 }
434 if (MIs.size() == 1) {
435 cloneMemRefs(MF, *MIs[0]);
436 return;
437 }
438 // Because an empty memoperands list provides *no* information and must be
439 // handled conservatively (assuming the instruction can do anything), the only
440 // way to merge with it is to drop all other memoperands.
441 if (MIs[0]->memoperands_empty()) {
442 dropMemRefs(MF);
443 return;
444 }
445
446 // Handle the general case.
447 SmallVector<MachineMemOperand *, 2> MergedMMOs;
448 // Start with the first instruction.
449 assert(&MF == MIs[0]->getMF() &&(static_cast <bool> (&MF == MIs[0]->getMF() &&
"Invalid machine functions when cloning memory references!")
? void (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 450, __extension__ __PRETTY_FUNCTION__
))
450 "Invalid machine functions when cloning memory references!")(static_cast <bool> (&MF == MIs[0]->getMF() &&
"Invalid machine functions when cloning memory references!")
? void (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 450, __extension__ __PRETTY_FUNCTION__
))
;
451 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
452 // Now walk all the other instructions and accumulate any different MMOs.
453 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
454 assert(&MF == MI.getMF() &&(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 455, __extension__ __PRETTY_FUNCTION__
))
455 "Invalid machine functions when cloning memory references!")(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 455, __extension__ __PRETTY_FUNCTION__
))
;
456
457 // Skip MIs with identical operands to the first. This is a somewhat
458 // arbitrary hack but will catch common cases without being quadratic.
459 // TODO: We could fully implement merge semantics here if needed.
460 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
461 continue;
462
463 // Because an empty memoperands list provides *no* information and must be
464 // handled conservatively (assuming the instruction can do anything), the
465 // only way to merge with it is to drop all other memoperands.
466 if (MI.memoperands_empty()) {
467 dropMemRefs(MF);
468 return;
469 }
470
471 // Otherwise accumulate these into our temporary buffer of the merged state.
472 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
473 }
474
475 setMemRefs(MF, MergedMMOs);
476}
477
478void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
479 // Do nothing if old and new symbols are the same.
480 if (Symbol == getPreInstrSymbol())
481 return;
482
483 // If there was only one symbol and we're removing it, just clear info.
484 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
485 Info.clear();
486 return;
487 }
488
489 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
490 getHeapAllocMarker());
491}
492
493void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
494 // Do nothing if old and new symbols are the same.
495 if (Symbol == getPostInstrSymbol())
496 return;
497
498 // If there was only one symbol and we're removing it, just clear info.
499 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
500 Info.clear();
501 return;
502 }
503
504 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
505 getHeapAllocMarker());
506}
507
508void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
509 // Do nothing if old and new symbols are the same.
510 if (Marker == getHeapAllocMarker())
511 return;
512
513 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
514 Marker);
515}
516
517void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
518 const MachineInstr &MI) {
519 if (this == &MI)
520 // Nothing to do for a self-clone!
521 return;
522
523 assert(&MF == MI.getMF() &&(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 524, __extension__ __PRETTY_FUNCTION__
))
524 "Invalid machine functions when cloning instruction symbols!")(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 524, __extension__ __PRETTY_FUNCTION__
))
;
525
526 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
527 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
528 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
529}
530
531uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
532 // For now, the just return the union of the flags. If the flags get more
533 // complicated over time, we might need more logic here.
534 return getFlags() | Other.getFlags();
535}
536
537uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
538 uint16_t MIFlags = 0;
539 // Copy the wrapping flags.
540 if (const OverflowingBinaryOperator *OB =
541 dyn_cast<OverflowingBinaryOperator>(&I)) {
542 if (OB->hasNoSignedWrap())
543 MIFlags |= MachineInstr::MIFlag::NoSWrap;
544 if (OB->hasNoUnsignedWrap())
545 MIFlags |= MachineInstr::MIFlag::NoUWrap;
546 }
547
548 // Copy the exact flag.
549 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
550 if (PE->isExact())
551 MIFlags |= MachineInstr::MIFlag::IsExact;
552
553 // Copy the fast-math flags.
554 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
555 const FastMathFlags Flags = FP->getFastMathFlags();
556 if (Flags.noNaNs())
557 MIFlags |= MachineInstr::MIFlag::FmNoNans;
558 if (Flags.noInfs())
559 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
560 if (Flags.noSignedZeros())
561 MIFlags |= MachineInstr::MIFlag::FmNsz;
562 if (Flags.allowReciprocal())
563 MIFlags |= MachineInstr::MIFlag::FmArcp;
564 if (Flags.allowContract())
565 MIFlags |= MachineInstr::MIFlag::FmContract;
566 if (Flags.approxFunc())
567 MIFlags |= MachineInstr::MIFlag::FmAfn;
568 if (Flags.allowReassoc())
569 MIFlags |= MachineInstr::MIFlag::FmReassoc;
570 }
571
572 return MIFlags;
573}
574
575void MachineInstr::copyIRFlags(const Instruction &I) {
576 Flags = copyFlagsFromInstruction(I);
577}
578
579bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
580 assert(!isBundledWithPred() && "Must be called on bundle header")(static_cast <bool> (!isBundledWithPred() && "Must be called on bundle header"
) ? void (0) : __assert_fail ("!isBundledWithPred() && \"Must be called on bundle header\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 580, __extension__ __PRETTY_FUNCTION__
))
;
581 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
582 if (MII->getDesc().getFlags() & Mask) {
583 if (Type == AnyInBundle)
584 return true;
585 } else {
586 if (Type == AllInBundle && !MII->isBundle())
587 return false;
588 }
589 // This was the last instruction in the bundle.
590 if (!MII->isBundledWithSucc())
591 return Type == AllInBundle;
592 }
593}
594
595bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
596 MICheckType Check) const {
597 // If opcodes or number of operands are not the same then the two
598 // instructions are obviously not identical.
599 if (Other.getOpcode() != getOpcode() ||
600 Other.getNumOperands() != getNumOperands())
601 return false;
602
603 if (isBundle()) {
604 // We have passed the test above that both instructions have the same
605 // opcode, so we know that both instructions are bundles here. Let's compare
606 // MIs inside the bundle.
607 assert(Other.isBundle() && "Expected that both instructions are bundles.")(static_cast <bool> (Other.isBundle() && "Expected that both instructions are bundles."
) ? void (0) : __assert_fail ("Other.isBundle() && \"Expected that both instructions are bundles.\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 607, __extension__ __PRETTY_FUNCTION__
))
;
608 MachineBasicBlock::const_instr_iterator I1 = getIterator();
609 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
610 // Loop until we analysed the last intruction inside at least one of the
611 // bundles.
612 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
613 ++I1;
614 ++I2;
615 if (!I1->isIdenticalTo(*I2, Check))
616 return false;
617 }
618 // If we've reached the end of just one of the two bundles, but not both,
619 // the instructions are not identical.
620 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
621 return false;
622 }
623
624 // Check operands to make sure they match.
625 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
626 const MachineOperand &MO = getOperand(i);
627 const MachineOperand &OMO = Other.getOperand(i);
628 if (!MO.isReg()) {
629 if (!MO.isIdenticalTo(OMO))
630 return false;
631 continue;
632 }
633
634 // Clients may or may not want to ignore defs when testing for equality.
635 // For example, machine CSE pass only cares about finding common
636 // subexpressions, so it's safe to ignore virtual register defs.
637 if (MO.isDef()) {
638 if (Check == IgnoreDefs)
639 continue;
640 else if (Check == IgnoreVRegDefs) {
641 if (!Register::isVirtualRegister(MO.getReg()) ||
642 !Register::isVirtualRegister(OMO.getReg()))
643 if (!MO.isIdenticalTo(OMO))
644 return false;
645 } else {
646 if (!MO.isIdenticalTo(OMO))
647 return false;
648 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
649 return false;
650 }
651 } else {
652 if (!MO.isIdenticalTo(OMO))
653 return false;
654 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
655 return false;
656 }
657 }
658 // If DebugLoc does not match then two debug instructions are not identical.
659 if (isDebugInstr())
660 if (getDebugLoc() && Other.getDebugLoc() &&
661 getDebugLoc() != Other.getDebugLoc())
662 return false;
663 return true;
664}
665
666const MachineFunction *MachineInstr::getMF() const {
667 return getParent()->getParent();
668}
669
670MachineInstr *MachineInstr::removeFromParent() {
671 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 671, __extension__ __PRETTY_FUNCTION__
))
;
672 return getParent()->remove(this);
673}
674
675MachineInstr *MachineInstr::removeFromBundle() {
676 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 676, __extension__ __PRETTY_FUNCTION__
))
;
677 return getParent()->remove_instr(this);
678}
679
680void MachineInstr::eraseFromParent() {
681 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 681, __extension__ __PRETTY_FUNCTION__
))
;
682 getParent()->erase(this);
683}
684
685void MachineInstr::eraseFromBundle() {
686 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 686, __extension__ __PRETTY_FUNCTION__
))
;
687 getParent()->erase_instr(this);
688}
689
690bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const {
691 if (!isCall(Type))
692 return false;
693 switch (getOpcode()) {
694 case TargetOpcode::PATCHPOINT:
695 case TargetOpcode::STACKMAP:
696 case TargetOpcode::STATEPOINT:
697 case TargetOpcode::FENTRY_CALL:
698 return false;
699 }
700 return true;
701}
702
703bool MachineInstr::shouldUpdateCallSiteInfo() const {
704 if (isBundle())
705 return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle);
706 return isCandidateForCallSiteEntry();
707}
708
709unsigned MachineInstr::getNumExplicitOperands() const {
710 unsigned NumOperands = MCID->getNumOperands();
711 if (!MCID->isVariadic())
712 return NumOperands;
713
714 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
715 const MachineOperand &MO = getOperand(I);
716 // The operands must always be in the following order:
717 // - explicit reg defs,
718 // - other explicit operands (reg uses, immediates, etc.),
719 // - implicit reg defs
720 // - implicit reg uses
721 if (MO.isReg() && MO.isImplicit())
722 break;
723 ++NumOperands;
724 }
725 return NumOperands;
726}
727
728unsigned MachineInstr::getNumExplicitDefs() const {
729 unsigned NumDefs = MCID->getNumDefs();
730 if (!MCID->isVariadic())
731 return NumDefs;
732
733 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
734 const MachineOperand &MO = getOperand(I);
735 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
736 break;
737 ++NumDefs;
738 }
739 return NumDefs;
740}
741
742void MachineInstr::bundleWithPred() {
743 assert(!isBundledWithPred() && "MI is already bundled with its predecessor")(static_cast <bool> (!isBundledWithPred() && "MI is already bundled with its predecessor"
) ? void (0) : __assert_fail ("!isBundledWithPred() && \"MI is already bundled with its predecessor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 743, __extension__ __PRETTY_FUNCTION__
))
;
744 setFlag(BundledPred);
745 MachineBasicBlock::instr_iterator Pred = getIterator();
746 --Pred;
747 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")(static_cast <bool> (!Pred->isBundledWithSucc() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("!Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 747, __extension__ __PRETTY_FUNCTION__
))
;
748 Pred->setFlag(BundledSucc);
749}
750
751void MachineInstr::bundleWithSucc() {
752 assert(!isBundledWithSucc() && "MI is already bundled with its successor")(static_cast <bool> (!isBundledWithSucc() && "MI is already bundled with its successor"
) ? void (0) : __assert_fail ("!isBundledWithSucc() && \"MI is already bundled with its successor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 752, __extension__ __PRETTY_FUNCTION__
))
;
753 setFlag(BundledSucc);
754 MachineBasicBlock::instr_iterator Succ = getIterator();
755 ++Succ;
756 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")(static_cast <bool> (!Succ->isBundledWithPred() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("!Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 756, __extension__ __PRETTY_FUNCTION__
))
;
757 Succ->setFlag(BundledPred);
758}
759
760void MachineInstr::unbundleFromPred() {
761 assert(isBundledWithPred() && "MI isn't bundled with its predecessor")(static_cast <bool> (isBundledWithPred() && "MI isn't bundled with its predecessor"
) ? void (0) : __assert_fail ("isBundledWithPred() && \"MI isn't bundled with its predecessor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 761, __extension__ __PRETTY_FUNCTION__
))
;
762 clearFlag(BundledPred);
763 MachineBasicBlock::instr_iterator Pred = getIterator();
764 --Pred;
765 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")(static_cast <bool> (Pred->isBundledWithSucc() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 765, __extension__ __PRETTY_FUNCTION__
))
;
766 Pred->clearFlag(BundledSucc);
767}
768
769void MachineInstr::unbundleFromSucc() {
770 assert(isBundledWithSucc() && "MI isn't bundled with its successor")(static_cast <bool> (isBundledWithSucc() && "MI isn't bundled with its successor"
) ? void (0) : __assert_fail ("isBundledWithSucc() && \"MI isn't bundled with its successor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 770, __extension__ __PRETTY_FUNCTION__
))
;
771 clearFlag(BundledSucc);
772 MachineBasicBlock::instr_iterator Succ = getIterator();
773 ++Succ;
774 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")(static_cast <bool> (Succ->isBundledWithPred() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 774, __extension__ __PRETTY_FUNCTION__
))
;
775 Succ->clearFlag(BundledPred);
776}
777
778bool MachineInstr::isStackAligningInlineAsm() const {
779 if (isInlineAsm()) {
780 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
781 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
782 return true;
783 }
784 return false;
785}
786
787InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
788 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")(static_cast <bool> (isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"
) ? void (0) : __assert_fail ("isInlineAsm() && \"getInlineAsmDialect() only works for inline asms!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 788, __extension__ __PRETTY_FUNCTION__
))
;
789 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
790 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
791}
792
793int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
794 unsigned *GroupNo) const {
795 assert(isInlineAsm() && "Expected an inline asm instruction")(static_cast <bool> (isInlineAsm() && "Expected an inline asm instruction"
) ? void (0) : __assert_fail ("isInlineAsm() && \"Expected an inline asm instruction\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 795, __extension__ __PRETTY_FUNCTION__
))
;
796 assert(OpIdx < getNumOperands() && "OpIdx out of range")(static_cast <bool> (OpIdx < getNumOperands() &&
"OpIdx out of range") ? void (0) : __assert_fail ("OpIdx < getNumOperands() && \"OpIdx out of range\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 796, __extension__ __PRETTY_FUNCTION__
))
;
797
798 // Ignore queries about the initial operands.
799 if (OpIdx < InlineAsm::MIOp_FirstOperand)
800 return -1;
801
802 unsigned Group = 0;
803 unsigned NumOps;
804 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
805 i += NumOps) {
806 const MachineOperand &FlagMO = getOperand(i);
807 // If we reach the implicit register operands, stop looking.
808 if (!FlagMO.isImm())
809 return -1;
810 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
811 if (i + NumOps > OpIdx) {
812 if (GroupNo)
813 *GroupNo = Group;
814 return i;
815 }
816 ++Group;
817 }
818 return -1;
819}
820
821const DILabel *MachineInstr::getDebugLabel() const {
822 assert(isDebugLabel() && "not a DBG_LABEL")(static_cast <bool> (isDebugLabel() && "not a DBG_LABEL"
) ? void (0) : __assert_fail ("isDebugLabel() && \"not a DBG_LABEL\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 822, __extension__ __PRETTY_FUNCTION__
))
;
823 return cast<DILabel>(getOperand(0).getMetadata());
824}
825
826const MachineOperand &MachineInstr::getDebugVariableOp() const {
827 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")(static_cast <bool> ((isDebugValue() || isDebugRef()) &&
"not a DBG_VALUE*") ? void (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE*\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 827, __extension__ __PRETTY_FUNCTION__
))
;
828 unsigned VariableOp = isDebugValueList() ? 0 : 2;
829 return getOperand(VariableOp);
830}
831
832MachineOperand &MachineInstr::getDebugVariableOp() {
833 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")(static_cast <bool> ((isDebugValue() || isDebugRef()) &&
"not a DBG_VALUE*") ? void (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE*\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 833, __extension__ __PRETTY_FUNCTION__
))
;
834 unsigned VariableOp = isDebugValueList() ? 0 : 2;
835 return getOperand(VariableOp);
836}
837
838const DILocalVariable *MachineInstr::getDebugVariable() const {
839 return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
840}
841
842const MachineOperand &MachineInstr::getDebugExpressionOp() const {
843 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")(static_cast <bool> ((isDebugValue() || isDebugRef()) &&
"not a DBG_VALUE*") ? void (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE*\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 843, __extension__ __PRETTY_FUNCTION__
))
;
844 unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
845 return getOperand(ExpressionOp);
846}
847
848MachineOperand &MachineInstr::getDebugExpressionOp() {
849 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")(static_cast <bool> ((isDebugValue() || isDebugRef()) &&
"not a DBG_VALUE*") ? void (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE*\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 849, __extension__ __PRETTY_FUNCTION__
))
;
850 unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
851 return getOperand(ExpressionOp);
852}
853
854const DIExpression *MachineInstr::getDebugExpression() const {
855 return cast<DIExpression>(getDebugExpressionOp().getMetadata());
856}
857
858bool MachineInstr::isDebugEntryValue() const {
859 return isDebugValue() && getDebugExpression()->isEntryValue();
860}
861
862const TargetRegisterClass*
863MachineInstr::getRegClassConstraint(unsigned OpIdx,
864 const TargetInstrInfo *TII,
865 const TargetRegisterInfo *TRI) const {
866 assert(getParent() && "Can't have an MBB reference here!")(static_cast <bool> (getParent() && "Can't have an MBB reference here!"
) ? void (0) : __assert_fail ("getParent() && \"Can't have an MBB reference here!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 866, __extension__ __PRETTY_FUNCTION__
))
;
867 assert(getMF() && "Can't have an MF reference here!")(static_cast <bool> (getMF() && "Can't have an MF reference here!"
) ? void (0) : __assert_fail ("getMF() && \"Can't have an MF reference here!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 867, __extension__ __PRETTY_FUNCTION__
))
;
868 const MachineFunction &MF = *getMF();
869
870 // Most opcodes have fixed constraints in their MCInstrDesc.
871 if (!isInlineAsm())
872 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
873
874 if (!getOperand(OpIdx).isReg())
875 return nullptr;
876
877 // For tied uses on inline asm, get the constraint from the def.
878 unsigned DefIdx;
879 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
880 OpIdx = DefIdx;
881
882 // Inline asm stores register class constraints in the flag word.
883 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
884 if (FlagIdx < 0)
885 return nullptr;
886
887 unsigned Flag = getOperand(FlagIdx).getImm();
888 unsigned RCID;
889 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
890 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
891 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
892 InlineAsm::hasRegClassConstraint(Flag, RCID))
893 return TRI->getRegClass(RCID);
894
895 // Assume that all registers in a memory operand are pointers.
896 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
897 return TRI->getPointerRegClass(MF);
898
899 return nullptr;
900}
901
902const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
903 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
904 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
905 // Check every operands inside the bundle if we have
906 // been asked to.
907 if (ExploreBundle)
908 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
909 ++OpndIt)
910 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
911 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
912 else
913 // Otherwise, just check the current operands.
914 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
915 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
916 return CurRC;
917}
918
919const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
920 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
921 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
922 assert(CurRC && "Invalid initial register class")(static_cast <bool> (CurRC && "Invalid initial register class"
) ? void (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 922, __extension__ __PRETTY_FUNCTION__
))
;
923 // Check if Reg is constrained by some of its use/def from MI.
924 const MachineOperand &MO = getOperand(OpIdx);
925 if (!MO.isReg() || MO.getReg() != Reg)
926 return CurRC;
927 // If yes, accumulate the constraints through the operand.
928 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
929}
930
931const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
932 unsigned OpIdx, const TargetRegisterClass *CurRC,
933 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
934 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
935 const MachineOperand &MO = getOperand(OpIdx);
936 assert(MO.isReg() &&(static_cast <bool> (MO.isReg() && "Cannot get register constraints for non-register operand"
) ? void (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 937, __extension__ __PRETTY_FUNCTION__
))
937 "Cannot get register constraints for non-register operand")(static_cast <bool> (MO.isReg() && "Cannot get register constraints for non-register operand"
) ? void (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 937, __extension__ __PRETTY_FUNCTION__
))
;
938 assert(CurRC && "Invalid initial register class")(static_cast <bool> (CurRC && "Invalid initial register class"
) ? void (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 938, __extension__ __PRETTY_FUNCTION__
))
;
939 if (unsigned SubIdx = MO.getSubReg()) {
940 if (OpRC)
941 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
942 else
943 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
944 } else if (OpRC)
945 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
946 return CurRC;
947}
948
949/// Return the number of instructions inside the MI bundle, not counting the
950/// header instruction.
951unsigned MachineInstr::getBundleSize() const {
952 MachineBasicBlock::const_instr_iterator I = getIterator();
953 unsigned Size = 0;
954 while (I->isBundledWithSucc()) {
955 ++Size;
956 ++I;
957 }
958 return Size;
959}
960
961/// Returns true if the MachineInstr has an implicit-use operand of exactly
962/// the given register (not considering sub/super-registers).
963bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
964 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
965 const MachineOperand &MO = getOperand(i);
966 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
967 return true;
968 }
969 return false;
970}
971
972/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
973/// the specific register or -1 if it is not found. It further tightens
974/// the search criteria to a use that kills the register if isKill is true.
975int MachineInstr::findRegisterUseOperandIdx(
976 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
977 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
978 const MachineOperand &MO = getOperand(i);
979 if (!MO.isReg() || !MO.isUse())
980 continue;
981 Register MOReg = MO.getReg();
982 if (!MOReg)
983 continue;
984 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
985 if (!isKill || MO.isKill())
986 return i;
987 }
988 return -1;
989}
990
991/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
992/// indicating if this instruction reads or writes Reg. This also considers
993/// partial defines.
994std::pair<bool,bool>
995MachineInstr::readsWritesVirtualRegister(Register Reg,
996 SmallVectorImpl<unsigned> *Ops) const {
997 bool PartDef = false; // Partial redefine.
998 bool FullDef = false; // Full define.
999 bool Use = false;
1000
1001 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1002 const MachineOperand &MO = getOperand(i);
1003 if (!MO.isReg() || MO.getReg() != Reg)
1004 continue;
1005 if (Ops)
1006 Ops->push_back(i);
1007 if (MO.isUse())
1008 Use |= !MO.isUndef();
1009 else if (MO.getSubReg() && !MO.isUndef())
1010 // A partial def undef doesn't count as reading the register.
1011 PartDef = true;
1012 else
1013 FullDef = true;
1014 }
1015 // A partial redefine uses Reg unless there is also a full define.
1016 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1017}
1018
1019/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1020/// the specified register or -1 if it is not found. If isDead is true, defs
1021/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1022/// also checks if there is a def of a super-register.
1023int
1024MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
1025 const TargetRegisterInfo *TRI) const {
1026 bool isPhys = Register::isPhysicalRegister(Reg);
1027 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1028 const MachineOperand &MO = getOperand(i);
1029 // Accept regmask operands when Overlap is set.
1030 // Ignore them when looking for a specific def operand (Overlap == false).
1031 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1032 return i;
1033 if (!MO.isReg() || !MO.isDef())
1034 continue;
1035 Register MOReg = MO.getReg();
1036 bool Found = (MOReg == Reg);
1037 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1038 if (Overlap)
1039 Found = TRI->regsOverlap(MOReg, Reg);
1040 else
1041 Found = TRI->isSubRegister(MOReg, Reg);
1042 }
1043 if (Found && (!isDead || MO.isDead()))
1044 return i;
1045 }
1046 return -1;
1047}
1048
1049/// findFirstPredOperandIdx() - Find the index of the first operand in the
1050/// operand list that is used to represent the predicate. It returns -1 if
1051/// none is found.
1052int MachineInstr::findFirstPredOperandIdx() const {
1053 // Don't call MCID.findFirstPredOperandIdx() because this variant
1054 // is sometimes called on an instruction that's not yet complete, and
1055 // so the number of operands is less than the MCID indicates. In
1056 // particular, the PTX target does this.
1057 const MCInstrDesc &MCID = getDesc();
1058 if (MCID.isPredicable()) {
1059 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1060 if (MCID.OpInfo[i].isPredicate())
1061 return i;
1062 }
1063
1064 return -1;
1065}
1066
1067// MachineOperand::TiedTo is 4 bits wide.
1068const unsigned TiedMax = 15;
1069
1070/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1071///
1072/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1073/// field. TiedTo can have these values:
1074///
1075/// 0: Operand is not tied to anything.
1076/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1077/// TiedMax: Tied to an operand >= TiedMax-1.
1078///
1079/// The tied def must be one of the first TiedMax operands on a normal
1080/// instruction. INLINEASM instructions allow more tied defs.
1081///
1082void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1083 MachineOperand &DefMO = getOperand(DefIdx);
1084 MachineOperand &UseMO = getOperand(UseIdx);
1085 assert(DefMO.isDef() && "DefIdx must be a def operand")(static_cast <bool> (DefMO.isDef() && "DefIdx must be a def operand"
) ? void (0) : __assert_fail ("DefMO.isDef() && \"DefIdx must be a def operand\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1085, __extension__ __PRETTY_FUNCTION__
))
;
1086 assert(UseMO.isUse() && "UseIdx must be a use operand")(static_cast <bool> (UseMO.isUse() && "UseIdx must be a use operand"
) ? void (0) : __assert_fail ("UseMO.isUse() && \"UseIdx must be a use operand\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1086, __extension__ __PRETTY_FUNCTION__
))
;
1087 assert(!DefMO.isTied() && "Def is already tied to another use")(static_cast <bool> (!DefMO.isTied() && "Def is already tied to another use"
) ? void (0) : __assert_fail ("!DefMO.isTied() && \"Def is already tied to another use\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1087, __extension__ __PRETTY_FUNCTION__
))
;
1088 assert(!UseMO.isTied() && "Use is already tied to another def")(static_cast <bool> (!UseMO.isTied() && "Use is already tied to another def"
) ? void (0) : __assert_fail ("!UseMO.isTied() && \"Use is already tied to another def\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1088, __extension__ __PRETTY_FUNCTION__
))
;
1089
1090 if (DefIdx < TiedMax)
1091 UseMO.TiedTo = DefIdx + 1;
1092 else {
1093 // Inline asm can use the group descriptors to find tied operands,
1094 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1095 // but on normal instruction, the tied def must be within the first TiedMax
1096 // operands.
1097 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&(static_cast <bool> ((isInlineAsm() || getOpcode() == TargetOpcode
::STATEPOINT) && "DefIdx out of range") ? void (0) : __assert_fail
("(isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) && \"DefIdx out of range\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1098, __extension__ __PRETTY_FUNCTION__
))
1098 "DefIdx out of range")(static_cast <bool> ((isInlineAsm() || getOpcode() == TargetOpcode
::STATEPOINT) && "DefIdx out of range") ? void (0) : __assert_fail
("(isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) && \"DefIdx out of range\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1098, __extension__ __PRETTY_FUNCTION__
))
;
1099 UseMO.TiedTo = TiedMax;
1100 }
1101
1102 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1103 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1104}
1105
1106/// Given the index of a tied register operand, find the operand it is tied to.
1107/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1108/// which must exist.
1109unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1110 const MachineOperand &MO = getOperand(OpIdx);
1111 assert(MO.isTied() && "Operand isn't tied")(static_cast <bool> (MO.isTied() && "Operand isn't tied"
) ? void (0) : __assert_fail ("MO.isTied() && \"Operand isn't tied\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1111, __extension__ __PRETTY_FUNCTION__
))
;
1112
1113 // Normally TiedTo is in range.
1114 if (MO.TiedTo < TiedMax)
1115 return MO.TiedTo - 1;
1116
1117 // Uses on normal instructions can be out of range.
1118 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1119 // Normal tied defs must be in the 0..TiedMax-1 range.
1120 if (MO.isUse())
1121 return TiedMax - 1;
1122 // MO is a def. Search for the tied use.
1123 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1124 const MachineOperand &UseMO = getOperand(i);
1125 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1126 return i;
1127 }
1128 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "llvm/lib/CodeGen/MachineInstr.cpp"
, 1128)
;
1129 }
1130
1131 if (getOpcode() == TargetOpcode::STATEPOINT) {
1132 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1133 // on registers.
1134 StatepointOpers SO(this);
1135 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1136 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied")(static_cast <bool> (CurUseIdx != -1U && "only gc pointer statepoint operands can be tied"
) ? void (0) : __assert_fail ("CurUseIdx != -1U && \"only gc pointer statepoint operands can be tied\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1136, __extension__ __PRETTY_FUNCTION__
))
;
1137 unsigned NumDefs = getNumDefs();
1138 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1139 while (!getOperand(CurUseIdx).isReg())
1140 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1141 if (OpIdx == CurDefIdx)
1142 return CurUseIdx;
1143 if (OpIdx == CurUseIdx)
1144 return CurDefIdx;
1145 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1146 }
1147 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "llvm/lib/CodeGen/MachineInstr.cpp"
, 1147)
;
1148 }
1149
1150 // Now deal with inline asm by parsing the operand group descriptor flags.
1151 // Find the beginning of each operand group.
1152 SmallVector<unsigned, 8> GroupIdx;
1153 unsigned OpIdxGroup = ~0u;
1154 unsigned NumOps;
1155 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1156 i += NumOps) {
1157 const MachineOperand &FlagMO = getOperand(i);
1158 assert(FlagMO.isImm() && "Invalid tied operand on inline asm")(static_cast <bool> (FlagMO.isImm() && "Invalid tied operand on inline asm"
) ? void (0) : __assert_fail ("FlagMO.isImm() && \"Invalid tied operand on inline asm\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1158, __extension__ __PRETTY_FUNCTION__
))
;
1159 unsigned CurGroup = GroupIdx.size();
1160 GroupIdx.push_back(i);
1161 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1162 // OpIdx belongs to this operand group.
1163 if (OpIdx > i && OpIdx < i + NumOps)
1164 OpIdxGroup = CurGroup;
1165 unsigned TiedGroup;
1166 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1167 continue;
1168 // Operands in this group are tied to operands in TiedGroup which must be
1169 // earlier. Find the number of operands between the two groups.
1170 unsigned Delta = i - GroupIdx[TiedGroup];
1171
1172 // OpIdx is a use tied to TiedGroup.
1173 if (OpIdxGroup == CurGroup)
1174 return OpIdx - Delta;
1175
1176 // OpIdx is a def tied to this use group.
1177 if (OpIdxGroup == TiedGroup)
1178 return OpIdx + Delta;
1179 }
1180 llvm_unreachable("Invalid tied operand on inline asm")::llvm::llvm_unreachable_internal("Invalid tied operand on inline asm"
, "llvm/lib/CodeGen/MachineInstr.cpp", 1180)
;
1181}
1182
1183/// clearKillInfo - Clears kill flags on all operands.
1184///
1185void MachineInstr::clearKillInfo() {
1186 for (MachineOperand &MO : operands()) {
1187 if (MO.isReg() && MO.isUse())
1188 MO.setIsKill(false);
1189 }
1190}
1191
1192void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1193 unsigned SubIdx,
1194 const TargetRegisterInfo &RegInfo) {
1195 if (Register::isPhysicalRegister(ToReg)) {
1196 if (SubIdx)
1197 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1198 for (MachineOperand &MO : operands()) {
1199 if (!MO.isReg() || MO.getReg() != FromReg)
1200 continue;
1201 MO.substPhysReg(ToReg, RegInfo);
1202 }
1203 } else {
1204 for (MachineOperand &MO : operands()) {
1205 if (!MO.isReg() || MO.getReg() != FromReg)
1206 continue;
1207 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1208 }
1209 }
1210}
1211
1212/// isSafeToMove - Return true if it is safe to move this instruction. If
1213/// SawStore is set to true, it means that there is a store (or call) between
1214/// the instruction's location and its intended destination.
1215bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1216 // Ignore stuff that we obviously can't move.
1217 //
1218 // Treat volatile loads as stores. This is not strictly necessary for
1219 // volatiles, but it is required for atomic loads. It is not allowed to move
1220 // a load across an atomic load with Ordering > Monotonic.
1221 if (mayStore() || isCall() || isPHI() ||
1222 (mayLoad() && hasOrderedMemoryRef())) {
1223 SawStore = true;
1224 return false;
1225 }
1226
1227 if (isPosition() || isDebugInstr() || isTerminator() ||
1228 mayRaiseFPException() || hasUnmodeledSideEffects())
1229 return false;
1230
1231 // See if this instruction does a load. If so, we have to guarantee that the
1232 // loaded value doesn't change between the load and the its intended
1233 // destination. The check for isInvariantLoad gives the target the chance to
1234 // classify the load as always returning a constant, e.g. a constant pool
1235 // load.
1236 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1237 // Otherwise, this is a real load. If there is a store between the load and
1238 // end of block, we can't move it.
1239 return !SawStore;
1240
1241 return true;
1242}
1243
1244static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
1245 bool UseTBAA, const MachineMemOperand *MMOa,
1246 const MachineMemOperand *MMOb) {
1247 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1248 // operates with MachineMemOperand offset with some important assumptions:
1249 // - LLVM fundamentally assumes flat address spaces.
1250 // - MachineOperand offset can *only* result from legalization and cannot
1251 // affect queries other than the trivial case of overlap checking.
1252 // - These offsets never wrap and never step outside of allocated objects.
1253 // - There should never be any negative offsets here.
1254 //
1255 // FIXME: Modify API to hide this math from "user"
1256 // Even before we go to AA we can reason locally about some memory objects. It
1257 // can save compile time, and possibly catch some corner cases not currently
1258 // covered.
1259
1260 int64_t OffsetA = MMOa->getOffset();
1261 int64_t OffsetB = MMOb->getOffset();
1262 int64_t MinOffset = std::min(OffsetA, OffsetB);
1263
1264 uint64_t WidthA = MMOa->getSize();
1265 uint64_t WidthB = MMOb->getSize();
1266 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1267 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1268
1269 const Value *ValA = MMOa->getValue();
1270 const Value *ValB = MMOb->getValue();
1271 bool SameVal = (ValA && ValB && (ValA == ValB));
1272 if (!SameVal) {
1273 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1274 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1275 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1276 return false;
1277 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1278 return false;
1279 if (PSVa && PSVb && (PSVa == PSVb))
1280 SameVal = true;
1281 }
1282
1283 if (SameVal) {
1284 if (!KnownWidthA || !KnownWidthB)
1285 return true;
1286 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1287 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1288 return (MinOffset + LowWidth > MaxOffset);
1289 }
1290
1291 if (!AA)
1292 return true;
1293
1294 if (!ValA || !ValB)
1295 return true;
1296
1297 assert((OffsetA >= 0) && "Negative MachineMemOperand offset")(static_cast <bool> ((OffsetA >= 0) && "Negative MachineMemOperand offset"
) ? void (0) : __assert_fail ("(OffsetA >= 0) && \"Negative MachineMemOperand offset\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1297, __extension__ __PRETTY_FUNCTION__
))
;
1298 assert((OffsetB >= 0) && "Negative MachineMemOperand offset")(static_cast <bool> ((OffsetB >= 0) && "Negative MachineMemOperand offset"
) ? void (0) : __assert_fail ("(OffsetB >= 0) && \"Negative MachineMemOperand offset\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1298, __extension__ __PRETTY_FUNCTION__
))
;
1299
1300 int64_t OverlapA =
1301 KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1302 int64_t OverlapB =
1303 KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1304
1305 return !AA->isNoAlias(
1306 MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1307 MemoryLocation(ValB, OverlapB,
1308 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1309}
1310
1311bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1312 bool UseTBAA) const {
1313 const MachineFunction *MF = getMF();
1314 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1315 const MachineFrameInfo &MFI = MF->getFrameInfo();
1316
1317 // Exclude call instruction which may alter the memory but can not be handled
1318 // by this function.
1319 if (isCall() || Other.isCall())
1320 return true;
1321
1322 // If neither instruction stores to memory, they can't alias in any
1323 // meaningful way, even if they read from the same address.
1324 if (!mayStore() && !Other.mayStore())
1325 return false;
1326
1327 // Both instructions must be memory operations to be able to alias.
1328 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1329 return false;
1330
1331 // Let the target decide if memory accesses cannot possibly overlap.
1332 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1333 return false;
1334
1335 // Memory operations without memory operands may access anything. Be
1336 // conservative and assume `MayAlias`.
1337 if (memoperands_empty() || Other.memoperands_empty())
1338 return true;
1339
1340 // Skip if there are too many memory operands.
1341 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1342 if (NumChecks > TII->getMemOperandAACheckLimit())
1343 return true;
1344
1345 // Check each pair of memory operands from both instructions, which can't
1346 // alias only if all pairs won't alias.
1347 for (auto *MMOa : memoperands())
1348 for (auto *MMOb : Other.memoperands())
1349 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1350 return true;
1351
1352 return false;
1353}
1354
1355/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1356/// or volatile memory reference, or if the information describing the memory
1357/// reference is not available. Return false if it is known to have no ordered
1358/// memory references.
1359bool MachineInstr::hasOrderedMemoryRef() const {
1360 // An instruction known never to access memory won't have a volatile access.
1361 if (!mayStore() &&
1362 !mayLoad() &&
1363 !isCall() &&
1364 !hasUnmodeledSideEffects())
1365 return false;
1366
1367 // Otherwise, if the instruction has no memory reference information,
1368 // conservatively assume it wasn't preserved.
1369 if (memoperands_empty())
1370 return true;
1371
1372 // Check if any of our memory operands are ordered.
1373 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1374 return !MMO->isUnordered();
1375 });
1376}
1377
1378/// isDereferenceableInvariantLoad - Return true if this instruction will never
1379/// trap and is loading from a location whose value is invariant across a run of
1380/// this function.
1381bool MachineInstr::isDereferenceableInvariantLoad(AAResults *AA) const {
1382 // If the instruction doesn't load at all, it isn't an invariant load.
1383 if (!mayLoad())
1384 return false;
1385
1386 // If the instruction has lost its memoperands, conservatively assume that
1387 // it may not be an invariant load.
1388 if (memoperands_empty())
1389 return false;
1390
1391 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1392
1393 for (MachineMemOperand *MMO : memoperands()) {
1394 if (!MMO->isUnordered())
1395 // If the memory operand has ordering side effects, we can't move the
1396 // instruction. Such an instruction is technically an invariant load,
1397 // but the caller code would need updated to expect that.
1398 return false;
1399 if (MMO->isStore()) return false;
1400 if (MMO->isInvariant() && MMO->isDereferenceable())
1401 continue;
1402
1403 // A load from a constant PseudoSourceValue is invariant.
1404 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1405 if (PSV->isConstant(&MFI))
1406 continue;
1407
1408 if (const Value *V = MMO->getValue()) {
1409 // If we have an AliasAnalysis, ask it whether the memory is constant.
1410 if (AA &&
1411 AA->pointsToConstantMemory(
1412 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1413 continue;
1414 }
1415
1416 // Otherwise assume conservatively.
1417 return false;
1418 }
1419
1420 // Everything checks out.
1421 return true;
1422}
1423
1424/// isConstantValuePHI - If the specified instruction is a PHI that always
1425/// merges together the same virtual register, return the register, otherwise
1426/// return 0.
1427unsigned MachineInstr::isConstantValuePHI() const {
1428 if (!isPHI())
1429 return 0;
1430 assert(getNumOperands() >= 3 &&(static_cast <bool> (getNumOperands() >= 3 &&
"It's illegal to have a PHI without source operands") ? void
(0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1431, __extension__ __PRETTY_FUNCTION__
))
1431 "It's illegal to have a PHI without source operands")(static_cast <bool> (getNumOperands() >= 3 &&
"It's illegal to have a PHI without source operands") ? void
(0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1431, __extension__ __PRETTY_FUNCTION__
))
;
1432
1433 Register Reg = getOperand(1).getReg();
1434 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1435 if (getOperand(i).getReg() != Reg)
1436 return 0;
1437 return Reg;
1438}
1439
1440bool MachineInstr::hasUnmodeledSideEffects() const {
1441 if (hasProperty(MCID::UnmodeledSideEffects))
1442 return true;
1443 if (isInlineAsm()) {
1444 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1445 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1446 return true;
1447 }
1448
1449 return false;
1450}
1451
1452bool MachineInstr::isLoadFoldBarrier() const {
1453 return mayStore() || isCall() ||
1454 (hasUnmodeledSideEffects() && !isPseudoProbe());
1455}
1456
1457/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1458///
1459bool MachineInstr::allDefsAreDead() const {
1460 for (const MachineOperand &MO : operands()) {
1461 if (!MO.isReg() || MO.isUse())
1462 continue;
1463 if (!MO.isDead())
1464 return false;
1465 }
1466 return true;
1467}
1468
1469/// copyImplicitOps - Copy implicit register operands from specified
1470/// instruction to this instruction.
1471void MachineInstr::copyImplicitOps(MachineFunction &MF,
1472 const MachineInstr &MI) {
1473 for (const MachineOperand &MO :
1474 llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands()))
1475 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1476 addOperand(MF, MO);
1477}
1478
1479bool MachineInstr::hasComplexRegisterTies() const {
1480 const MCInstrDesc &MCID = getDesc();
1481 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1482 return true;
1483 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1484 const auto &Operand = getOperand(I);
1485 if (!Operand.isReg() || Operand.isDef())
1486 // Ignore the defined registers as MCID marks only the uses as tied.
1487 continue;
1488 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1489 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1490 if (ExpectedTiedIdx != TiedIdx)
1491 return true;
1492 }
1493 return false;
1494}
1495
1496LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1497 const MachineRegisterInfo &MRI) const {
1498 const MachineOperand &Op = getOperand(OpIdx);
1499 if (!Op.isReg())
1500 return LLT{};
1501
1502 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1503 return MRI.getType(Op.getReg());
1504
1505 auto &OpInfo = getDesc().OpInfo[OpIdx];
1506 if (!OpInfo.isGenericType())
1507 return MRI.getType(Op.getReg());
1508
1509 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1510 return LLT{};
1511
1512 LLT TypeToPrint = MRI.getType(Op.getReg());
1513 // Don't mark the type index printed if it wasn't actually printed: maybe
1514 // another operand with the same type index has an actual type attached:
1515 if (TypeToPrint.isValid())
1516 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1517 return TypeToPrint;
1518}
1519
1520#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1521LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dump() const {
1522 dbgs() << " ";
1523 print(dbgs());
1524}
1525
1526LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dumprImpl(
1527 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1528 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1529 if (Depth >= MaxDepth)
1530 return;
1531 if (!AlreadySeenInstrs.insert(this).second)
1532 return;
1533 // PadToColumn always inserts at least one space.
1534 // Don't mess up the alignment if we don't want any space.
1535 if (Depth)
1536 fdbgs().PadToColumn(Depth * 2);
1537 print(fdbgs());
1538 for (const MachineOperand &MO : operands()) {
1539 if (!MO.isReg() || MO.isDef())
1540 continue;
1541 Register Reg = MO.getReg();
1542 if (Reg.isPhysical())
1543 continue;
1544 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1545 if (NewMI == nullptr)
1546 continue;
1547 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1548 }
1549}
1550
1551LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1552 unsigned MaxDepth) const {
1553 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1554 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1555}
1556#endif
1557
1558void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1559 bool SkipDebugLoc, bool AddNewLine,
1560 const TargetInstrInfo *TII) const {
1561 const Module *M = nullptr;
1562 const Function *F = nullptr;
1563 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1564 F = &MF->getFunction();
1565 M = F->getParent();
1566 if (!TII)
1567 TII = MF->getSubtarget().getInstrInfo();
1568 }
1569
1570 ModuleSlotTracker MST(M);
1571 if (F)
1572 MST.incorporateFunction(*F);
1573 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1574}
1575
1576void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1577 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1578 bool AddNewLine, const TargetInstrInfo *TII) const {
1579 // We can be a bit tidier if we know the MachineFunction.
1580 const TargetRegisterInfo *TRI = nullptr;
1581 const MachineRegisterInfo *MRI = nullptr;
1582 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1583 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1584
1585 if (isCFIInstruction())
1586 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")(static_cast <bool> (getNumOperands() == 1 && "Expected 1 operand in CFI instruction"
) ? void (0) : __assert_fail ("getNumOperands() == 1 && \"Expected 1 operand in CFI instruction\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1586, __extension__ __PRETTY_FUNCTION__
))
;
1587
1588 SmallBitVector PrintedTypes(8);
1589 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1590 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1591 if (!ShouldPrintRegisterTies)
1592 return 0U;
1593 const MachineOperand &MO = getOperand(OpIdx);
1594 if (MO.isReg() && MO.isTied() && !MO.isDef())
1595 return findTiedOperandIdx(OpIdx);
1596 return 0U;
1597 };
1598 unsigned StartOp = 0;
1599 unsigned e = getNumOperands();
1600
1601 // Print explicitly defined operands on the left of an assignment syntax.
1602 while (StartOp < e) {
1603 const MachineOperand &MO = getOperand(StartOp);
1604 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1605 break;
1606
1607 if (StartOp != 0)
1608 OS << ", ";
1609
1610 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1611 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1612 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1613 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1614 ++StartOp;
1615 }
1616
1617 if (StartOp != 0)
1618 OS << " = ";
1619
1620 if (getFlag(MachineInstr::FrameSetup))
1621 OS << "frame-setup ";
1622 if (getFlag(MachineInstr::FrameDestroy))
1623 OS << "frame-destroy ";
1624 if (getFlag(MachineInstr::FmNoNans))
1625 OS << "nnan ";
1626 if (getFlag(MachineInstr::FmNoInfs))
1627 OS << "ninf ";
1628 if (getFlag(MachineInstr::FmNsz))
1629 OS << "nsz ";
1630 if (getFlag(MachineInstr::FmArcp))
1631 OS << "arcp ";
1632 if (getFlag(MachineInstr::FmContract))
1633 OS << "contract ";
1634 if (getFlag(MachineInstr::FmAfn))
1635 OS << "afn ";
1636 if (getFlag(MachineInstr::FmReassoc))
1637 OS << "reassoc ";
1638 if (getFlag(MachineInstr::NoUWrap))
1639 OS << "nuw ";
1640 if (getFlag(MachineInstr::NoSWrap))
1641 OS << "nsw ";
1642 if (getFlag(MachineInstr::IsExact))
1643 OS << "exact ";
1644 if (getFlag(MachineInstr::NoFPExcept))
1645 OS << "nofpexcept ";
1646 if (getFlag(MachineInstr::NoMerge))
1647 OS << "nomerge ";
1648
1649 // Print the opcode name.
1650 if (TII)
1651 OS << TII->getName(getOpcode());
1652 else
1653 OS << "UNKNOWN";
1654
1655 if (SkipOpers)
1656 return;
1657
1658 // Print the rest of the operands.
1659 bool FirstOp = true;
1660 unsigned AsmDescOp = ~0u;
1661 unsigned AsmOpCount = 0;
1662
1663 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1664 // Print asm string.
1665 OS << " ";
1666 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1667 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1668 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1669 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1670 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1671 IntrinsicInfo);
1672
1673 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1674 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1675 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1676 OS << " [sideeffect]";
1677 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1678 OS << " [mayload]";
1679 if (ExtraInfo & InlineAsm::Extra_MayStore)
1680 OS << " [maystore]";
1681 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1682 OS << " [isconvergent]";
1683 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1684 OS << " [alignstack]";
1685 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1686 OS << " [attdialect]";
1687 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1688 OS << " [inteldialect]";
1689
1690 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1691 FirstOp = false;
1692 }
1693
1694 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1695 const MachineOperand &MO = getOperand(i);
1696
1697 if (FirstOp) FirstOp = false; else OS << ",";
1698 OS << " ";
1699
1700 if (isDebugValue() && MO.isMetadata()) {
1701 // Pretty print DBG_VALUE* instructions.
1702 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1703 if (DIV && !DIV->getName().empty())
1704 OS << "!\"" << DIV->getName() << '\"';
1705 else {
1706 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1707 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1708 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1709 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1710 }
1711 } else if (isDebugLabel() && MO.isMetadata()) {
1712 // Pretty print DBG_LABEL instructions.
1713 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1714 if (DIL && !DIL->getName().empty())
1715 OS << "\"" << DIL->getName() << '\"';
1716 else {
1717 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1718 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1719 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1720 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1721 }
1722 } else if (i == AsmDescOp && MO.isImm()) {
1723 // Pretty print the inline asm operand descriptor.
1724 OS << '$' << AsmOpCount++;
1725 unsigned Flag = MO.getImm();
1726 OS << ":[";
1727 OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
1728
1729 unsigned RCID = 0;
1730 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1731 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1732 if (TRI) {
1733 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1734 } else
1735 OS << ":RC" << RCID;
1736 }
1737
1738 if (InlineAsm::isMemKind(Flag)) {
1739 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1740 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1741 }
1742
1743 unsigned TiedTo = 0;
1744 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1745 OS << " tiedto:$" << TiedTo;
1746
1747 OS << ']';
1748
1749 // Compute the index of the next operand descriptor.
1750 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1751 } else {
1752 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1753 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1754 if (MO.isImm() && isOperandSubregIdx(i))
1755 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1756 else
1757 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1758 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1759 }
1760 }
1761
1762 // Print any optional symbols attached to this instruction as-if they were
1763 // operands.
1764 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1765 if (!FirstOp) {
1766 FirstOp = false;
1767 OS << ',';
1768 }
1769 OS << " pre-instr-symbol ";
1770 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1771 }
1772 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1773 if (!FirstOp) {
1774 FirstOp = false;
1775 OS << ',';
1776 }
1777 OS << " post-instr-symbol ";
1778 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1779 }
1780 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1781 if (!FirstOp) {
1782 FirstOp = false;
1783 OS << ',';
1784 }
1785 OS << " heap-alloc-marker ";
1786 HeapAllocMarker->printAsOperand(OS, MST);
1787 }
1788
1789 if (DebugInstrNum) {
1790 if (!FirstOp)
1791 OS << ",";
1792 OS << " debug-instr-number " << DebugInstrNum;
1793 }
1794
1795 if (!SkipDebugLoc) {
1796 if (const DebugLoc &DL = getDebugLoc()) {
1797 if (!FirstOp)
1798 OS << ',';
1799 OS << " debug-location ";
1800 DL->printAsOperand(OS, MST);
1801 }
1802 }
1803
1804 if (!memoperands_empty()) {
1805 SmallVector<StringRef, 0> SSNs;
1806 const LLVMContext *Context = nullptr;
1807 std::unique_ptr<LLVMContext> CtxPtr;
1808 const MachineFrameInfo *MFI = nullptr;
1809 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1810 MFI = &MF->getFrameInfo();
1811 Context = &MF->getFunction().getContext();
1812 } else {
1813 CtxPtr = std::make_unique<LLVMContext>();
1814 Context = CtxPtr.get();
1815 }
1816
1817 OS << " :: ";
1818 bool NeedComma = false;
1819 for (const MachineMemOperand *Op : memoperands()) {
1820 if (NeedComma)
1821 OS << ", ";
1822 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1823 NeedComma = true;
1824 }
1825 }
1826
1827 if (SkipDebugLoc)
1828 return;
1829
1830 bool HaveSemi = false;
1831
1832 // Print debug location information.
1833 if (const DebugLoc &DL = getDebugLoc()) {
1834 if (!HaveSemi) {
1835 OS << ';';
1836 HaveSemi = true;
1837 }
1838 OS << ' ';
1839 DL.print(OS);
1840 }
1841
1842 // Print extra comments for DEBUG_VALUE.
1843 if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1844 if (!HaveSemi) {
1845 OS << ";";
1846 HaveSemi = true;
Value stored to 'HaveSemi' is never read
1847 }
1848 auto *DV = getDebugVariable();
1849 OS << " line no:" << DV->getLine();
1850 if (isIndirectDebugValue())
1851 OS << " indirect";
1852 }
1853 // TODO: DBG_LABEL
1854
1855 if (AddNewLine)
1856 OS << '\n';
1857}
1858
1859bool MachineInstr::addRegisterKilled(Register IncomingReg,
1860 const TargetRegisterInfo *RegInfo,
1861 bool AddIfNotFound) {
1862 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1863 bool hasAliases = isPhysReg &&
1864 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1865 bool Found = false;
1866 SmallVector<unsigned,4> DeadOps;
1867 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1868 MachineOperand &MO = getOperand(i);
1869 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1870 continue;
1871
1872 // DEBUG_VALUE nodes do not contribute to code generation and should
1873 // always be ignored. Failure to do so may result in trying to modify
1874 // KILL flags on DEBUG_VALUE nodes.
1875 if (MO.isDebug())
1876 continue;
1877
1878 Register Reg = MO.getReg();
1879 if (!Reg)
1880 continue;
1881
1882 if (Reg == IncomingReg) {
1883 if (!Found) {
1884 if (MO.isKill())
1885 // The register is already marked kill.
1886 return true;
1887 if (isPhysReg && isRegTiedToDefOperand(i))
1888 // Two-address uses of physregs must not be marked kill.
1889 return true;
1890 MO.setIsKill();
1891 Found = true;
1892 }
1893 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1894 // A super-register kill already exists.
1895 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1896 return true;
1897 if (RegInfo->isSubRegister(IncomingReg, Reg))
1898 DeadOps.push_back(i);
1899 }
1900 }
1901
1902 // Trim unneeded kill operands.
1903 while (!DeadOps.empty()) {
1904 unsigned OpIdx = DeadOps.back();
1905 if (getOperand(OpIdx).isImplicit() &&
1906 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1907 RemoveOperand(OpIdx);
1908 else
1909 getOperand(OpIdx).setIsKill(false);
1910 DeadOps.pop_back();
1911 }
1912
1913 // If not found, this means an alias of one of the operands is killed. Add a
1914 // new implicit operand if required.
1915 if (!Found && AddIfNotFound) {
1916 addOperand(MachineOperand::CreateReg(IncomingReg,
1917 false /*IsDef*/,
1918 true /*IsImp*/,
1919 true /*IsKill*/));
1920 return true;
1921 }
1922 return Found;
1923}
1924
1925void MachineInstr::clearRegisterKills(Register Reg,
1926 const TargetRegisterInfo *RegInfo) {
1927 if (!Register::isPhysicalRegister(Reg))
1928 RegInfo = nullptr;
1929 for (MachineOperand &MO : operands()) {
1930 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1931 continue;
1932 Register OpReg = MO.getReg();
1933 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1934 MO.setIsKill(false);
1935 }
1936}
1937
1938bool MachineInstr::addRegisterDead(Register Reg,
1939 const TargetRegisterInfo *RegInfo,
1940 bool AddIfNotFound) {
1941 bool isPhysReg = Register::isPhysicalRegister(Reg);
1942 bool hasAliases = isPhysReg &&
1943 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1944 bool Found = false;
1945 SmallVector<unsigned,4> DeadOps;
1946 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1947 MachineOperand &MO = getOperand(i);
1948 if (!MO.isReg() || !MO.isDef())
1949 continue;
1950 Register MOReg = MO.getReg();
1951 if (!MOReg)
1952 continue;
1953
1954 if (MOReg == Reg) {
1955 MO.setIsDead();
1956 Found = true;
1957 } else if (hasAliases && MO.isDead() &&
1958 Register::isPhysicalRegister(MOReg)) {
1959 // There exists a super-register that's marked dead.
1960 if (RegInfo->isSuperRegister(Reg, MOReg))
1961 return true;
1962 if (RegInfo->isSubRegister(Reg, MOReg))
1963 DeadOps.push_back(i);
1964 }
1965 }
1966
1967 // Trim unneeded dead operands.
1968 while (!DeadOps.empty()) {
1969 unsigned OpIdx = DeadOps.back();
1970 if (getOperand(OpIdx).isImplicit() &&
1971 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1972 RemoveOperand(OpIdx);
1973 else
1974 getOperand(OpIdx).setIsDead(false);
1975 DeadOps.pop_back();
1976 }
1977
1978 // If not found, this means an alias of one of the operands is dead. Add a
1979 // new implicit operand if required.
1980 if (Found || !AddIfNotFound)
1981 return Found;
1982
1983 addOperand(MachineOperand::CreateReg(Reg,
1984 true /*IsDef*/,
1985 true /*IsImp*/,
1986 false /*IsKill*/,
1987 true /*IsDead*/));
1988 return true;
1989}
1990
1991void MachineInstr::clearRegisterDeads(Register Reg) {
1992 for (MachineOperand &MO : operands()) {
1993 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1994 continue;
1995 MO.setIsDead(false);
1996 }
1997}
1998
1999void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2000 for (MachineOperand &MO : operands()) {
2001 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2002 continue;
2003 MO.setIsUndef(IsUndef);
2004 }
2005}
2006
2007void MachineInstr::addRegisterDefined(Register Reg,
2008 const TargetRegisterInfo *RegInfo) {
2009 if (Register::isPhysicalRegister(Reg)) {
2010 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2011 if (MO)
2012 return;
2013 } else {
2014 for (const MachineOperand &MO : operands()) {
2015 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2016 MO.getSubReg() == 0)
2017 return;
2018 }
2019 }
2020 addOperand(MachineOperand::CreateReg(Reg,
2021 true /*IsDef*/,
2022 true /*IsImp*/));
2023}
2024
2025void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
2026 const TargetRegisterInfo &TRI) {
2027 bool HasRegMask = false;
2028 for (MachineOperand &MO : operands()) {
2029 if (MO.isRegMask()) {
2030 HasRegMask = true;
2031 continue;
2032 }
2033 if (!MO.isReg() || !MO.isDef()) continue;
2034 Register Reg = MO.getReg();
2035 if (!Reg.isPhysical())
2036 continue;
2037 // If there are no uses, including partial uses, the def is dead.
2038 if (llvm::none_of(UsedRegs,
2039 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2040 MO.setIsDead();
2041 }
2042
2043 // This is a call with a register mask operand.
2044 // Mask clobbers are always dead, so add defs for the non-dead defines.
2045 if (HasRegMask)
2046 for (const Register &UsedReg : UsedRegs)
2047 addRegisterDefined(UsedReg, &TRI);
2048}
2049
2050unsigned
2051MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2052 // Build up a buffer of hash code components.
2053 SmallVector<size_t, 16> HashComponents;
2054 HashComponents.reserve(MI->getNumOperands() + 1);
2055 HashComponents.push_back(MI->getOpcode());
2056 for (const MachineOperand &MO : MI->operands()) {
2057 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2058 continue; // Skip virtual register defs.
2059
2060 HashComponents.push_back(hash_value(MO));
2061 }
2062 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2063}
2064
2065void MachineInstr::emitError(StringRef Msg) const {
2066 // Find the source location cookie.
2067 uint64_t LocCookie = 0;
2068 const MDNode *LocMD = nullptr;
2069 for (unsigned i = getNumOperands(); i != 0; --i) {
2070 if (getOperand(i-1).isMetadata() &&
2071 (LocMD = getOperand(i-1).getMetadata()) &&
2072 LocMD->getNumOperands() != 0) {
2073 if (const ConstantInt *CI =
2074 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2075 LocCookie = CI->getZExtValue();
2076 break;
2077 }
2078 }
2079 }
2080
2081 if (const MachineBasicBlock *MBB = getParent())
2082 if (const MachineFunction *MF = MBB->getParent())
2083 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2084 report_fatal_error(Msg);
2085}
2086
2087MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2088 const MCInstrDesc &MCID, bool IsIndirect,
2089 Register Reg, const MDNode *Variable,
2090 const MDNode *Expr) {
2091 assert(isa<DILocalVariable>(Variable) && "not a variable")(static_cast <bool> (isa<DILocalVariable>(Variable
) && "not a variable") ? void (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2091, __extension__ __PRETTY_FUNCTION__
))
;
2092 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")(static_cast <bool> (cast<DIExpression>(Expr)->
isValid() && "not an expression") ? void (0) : __assert_fail
("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2092, __extension__ __PRETTY_FUNCTION__
))
;
2093 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2094, __extension__ __PRETTY_FUNCTION__
))
2094 "Expected inlined-at fields to agree")(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2094, __extension__ __PRETTY_FUNCTION__
))
;
2095 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);
2096 if (IsIndirect)
2097 MIB.addImm(0U);
2098 else
2099 MIB.addReg(0U);
2100 return MIB.addMetadata(Variable).addMetadata(Expr);
2101}
2102
2103MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2104 const MCInstrDesc &MCID, bool IsIndirect,
2105 const MachineOperand &MO,
2106 const MDNode *Variable, const MDNode *Expr) {
2107 assert(isa<DILocalVariable>(Variable) && "not a variable")(static_cast <bool> (isa<DILocalVariable>(Variable
) && "not a variable") ? void (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2107, __extension__ __PRETTY_FUNCTION__
))
;
2108 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")(static_cast <bool> (cast<DIExpression>(Expr)->
isValid() && "not an expression") ? void (0) : __assert_fail
("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2108, __extension__ __PRETTY_FUNCTION__
))
;
2109 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2110, __extension__ __PRETTY_FUNCTION__
))
2110 "Expected inlined-at fields to agree")(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2110, __extension__ __PRETTY_FUNCTION__
))
;
2111 if (MO.isReg())
2112 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2113
2114 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2115 if (IsIndirect)
2116 MIB.addImm(0U);
2117 else
2118 MIB.addReg(0U);
2119 return MIB.addMetadata(Variable).addMetadata(Expr);
2120}
2121
2122MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2123 const MCInstrDesc &MCID, bool IsIndirect,
2124 ArrayRef<MachineOperand> MOs,
2125 const MDNode *Variable, const MDNode *Expr) {
2126 assert(isa<DILocalVariable>(Variable) && "not a variable")(static_cast <bool> (isa<DILocalVariable>(Variable
) && "not a variable") ? void (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2126, __extension__ __PRETTY_FUNCTION__
))
;
2127 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")(static_cast <bool> (cast<DIExpression>(Expr)->
isValid() && "not an expression") ? void (0) : __assert_fail
("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2127, __extension__ __PRETTY_FUNCTION__
))
;
2128 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2129, __extension__ __PRETTY_FUNCTION__
))
2129 "Expected inlined-at fields to agree")(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2129, __extension__ __PRETTY_FUNCTION__
))
;
2130 if (MCID.Opcode == TargetOpcode::DBG_VALUE)
2131 return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
2132
2133 auto MIB = BuildMI(MF, DL, MCID);
2134 MIB.addMetadata(Variable).addMetadata(Expr);
2135 for (const MachineOperand &MO : MOs)
2136 if (MO.isReg())
2137 MIB.addReg(MO.getReg());
2138 else
2139 MIB.add(MO);
2140 return MIB;
2141}
2142
2143MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2144 MachineBasicBlock::iterator I,
2145 const DebugLoc &DL, const MCInstrDesc &MCID,
2146 bool IsIndirect, Register Reg,
2147 const MDNode *Variable, const MDNode *Expr) {
2148 MachineFunction &MF = *BB.getParent();
2149 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2150 BB.insert(I, MI);
2151 return MachineInstrBuilder(MF, MI);
2152}
2153
2154MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2155 MachineBasicBlock::iterator I,
2156 const DebugLoc &DL, const MCInstrDesc &MCID,
2157 bool IsIndirect, MachineOperand &MO,
2158 const MDNode *Variable, const MDNode *Expr) {
2159 MachineFunction &MF = *BB.getParent();
2160 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2161 BB.insert(I, MI);
2162 return MachineInstrBuilder(MF, *MI);
2163}
2164
2165MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2166 MachineBasicBlock::iterator I,
2167 const DebugLoc &DL, const MCInstrDesc &MCID,
2168 bool IsIndirect, ArrayRef<MachineOperand> MOs,
2169 const MDNode *Variable, const MDNode *Expr) {
2170 MachineFunction &MF = *BB.getParent();
2171 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
2172 BB.insert(I, MI);
2173 return MachineInstrBuilder(MF, *MI);
2174}
2175
2176/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2177/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2178static const DIExpression *
2179computeExprForSpill(const MachineInstr &MI,
2180 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2181 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&(static_cast <bool> (MI.getDebugVariable()->isValidLocationForIntrinsic
(MI.getDebugLoc()) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2182, __extension__ __PRETTY_FUNCTION__
))
2182 "Expected inlined-at fields to agree")(static_cast <bool> (MI.getDebugVariable()->isValidLocationForIntrinsic
(MI.getDebugLoc()) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2182, __extension__ __PRETTY_FUNCTION__
))
;
2183
2184 const DIExpression *Expr = MI.getDebugExpression();
2185 if (MI.isIndirectDebugValue()) {
2186 assert(MI.getDebugOffset().getImm() == 0 &&(static_cast <bool> (MI.getDebugOffset().getImm() == 0 &&
"DBG_VALUE with nonzero offset") ? void (0) : __assert_fail (
"MI.getDebugOffset().getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2187, __extension__ __PRETTY_FUNCTION__
))
2187 "DBG_VALUE with nonzero offset")(static_cast <bool> (MI.getDebugOffset().getImm() == 0 &&
"DBG_VALUE with nonzero offset") ? void (0) : __assert_fail (
"MI.getDebugOffset().getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2187, __extension__ __PRETTY_FUNCTION__
))
;
2188 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2189 } else if (MI.isDebugValueList()) {
2190 // We will replace the spilled register with a frame index, so
2191 // immediately deref all references to the spilled register.
2192 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2193 for (const MachineOperand *Op : SpilledOperands) {
2194 unsigned OpIdx = MI.getDebugOperandIndex(Op);
2195 Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2196 }
2197 }
2198 return Expr;
2199}
2200static const DIExpression *computeExprForSpill(const MachineInstr &MI,
2201 Register SpillReg) {
2202 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.")(static_cast <bool> (MI.hasDebugOperandForReg(SpillReg)
&& "Spill Reg is not used in MI.") ? void (0) : __assert_fail
("MI.hasDebugOperandForReg(SpillReg) && \"Spill Reg is not used in MI.\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2202, __extension__ __PRETTY_FUNCTION__
))
;
2203 SmallVector<const MachineOperand *> SpillOperands;
2204 for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2205 SpillOperands.push_back(&Op);
2206 return computeExprForSpill(MI, SpillOperands);
2207}
2208
2209MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2210 MachineBasicBlock::iterator I,
2211 const MachineInstr &Orig,
2212 int FrameIndex, Register SpillReg) {
2213 const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2214 MachineInstrBuilder NewMI =
2215 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2216 // Non-Variadic Operands: Location, Offset, Variable, Expression
2217 // Variadic Operands: Variable, Expression, Locations...
2218 if (Orig.isNonListDebugValue())
2219 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2220 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2221 if (Orig.isDebugValueList()) {
2222 for (const MachineOperand &Op : Orig.debug_operands())
2223 if (Op.isReg() && Op.getReg() == SpillReg)
2224 NewMI.addFrameIndex(FrameIndex);
2225 else
2226 NewMI.add(MachineOperand(Op));
2227 }
2228 return NewMI;
2229}
2230MachineInstr *llvm::buildDbgValueForSpill(
2231 MachineBasicBlock &BB, MachineBasicBlock::iterator I,
2232 const MachineInstr &Orig, int FrameIndex,
2233 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2234 const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2235 MachineInstrBuilder NewMI =
2236 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2237 // Non-Variadic Operands: Location, Offset, Variable, Expression
2238 // Variadic Operands: Variable, Expression, Locations...
2239 if (Orig.isNonListDebugValue())
2240 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2241 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2242 if (Orig.isDebugValueList()) {
2243 for (const MachineOperand &Op : Orig.debug_operands())
2244 if (is_contained(SpilledOperands, &Op))
2245 NewMI.addFrameIndex(FrameIndex);
2246 else
2247 NewMI.add(MachineOperand(Op));
2248 }
2249 return NewMI;
2250}
2251
2252void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex,
2253 Register Reg) {
2254 const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2255 if (Orig.isNonListDebugValue())
2256 Orig.getDebugOffset().ChangeToImmediate(0U);
2257 for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))
2258 Op.ChangeToFrameIndex(FrameIndex);
2259 Orig.getDebugExpressionOp().setMetadata(Expr);
2260}
2261
2262void MachineInstr::collectDebugValues(
2263 SmallVectorImpl<MachineInstr *> &DbgValues) {
2264 MachineInstr &MI = *this;
2265 if (!MI.getOperand(0).isReg())
2266 return;
2267
2268 MachineBasicBlock::iterator DI = MI; ++DI;
2269 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2270 DI != DE; ++DI) {
2271 if (!DI->isDebugValue())
2272 return;
2273 if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2274 DbgValues.push_back(&*DI);
2275 }
2276}
2277
2278void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2279 // Collect matching debug values.
2280 SmallVector<MachineInstr *, 2> DbgValues;
2281
2282 if (!getOperand(0).isReg())
2283 return;
2284
2285 Register DefReg = getOperand(0).getReg();
2286 auto *MRI = getRegInfo();
2287 for (auto &MO : MRI->use_operands(DefReg)) {
2288 auto *DI = MO.getParent();
2289 if (!DI->isDebugValue())
2290 continue;
2291 if (DI->hasDebugOperandForReg(DefReg)) {
2292 DbgValues.push_back(DI);
2293 }
2294 }
2295
2296 // Propagate Reg to debug value instructions.
2297 for (auto *DBI : DbgValues)
2298 for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2299 Op.setReg(Reg);
2300}
2301
2302using MMOList = SmallVector<const MachineMemOperand *, 2>;
2303
2304static unsigned getSpillSlotSize(const MMOList &Accesses,
2305 const MachineFrameInfo &MFI) {
2306 unsigned Size = 0;
2307 for (auto A : Accesses)
2308 if (MFI.isSpillSlotObjectIndex(
2309 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2310 ->getFrameIndex()))
2311 Size += A->getSize();
2312 return Size;
2313}
2314
2315Optional<unsigned>
2316MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2317 int FI;
2318 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2319 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2320 if (MFI.isSpillSlotObjectIndex(FI))
2321 return (*memoperands_begin())->getSize();
2322 }
2323 return None;
2324}
2325
2326Optional<unsigned>
2327MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2328 MMOList Accesses;
2329 if (TII->hasStoreToStackSlot(*this, Accesses))
2330 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2331 return None;
2332}
2333
2334Optional<unsigned>
2335MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2336 int FI;
2337 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2338 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2339 if (MFI.isSpillSlotObjectIndex(FI))
2340 return (*memoperands_begin())->getSize();
2341 }
2342 return None;
2343}
2344
2345Optional<unsigned>
2346MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2347 MMOList Accesses;
2348 if (TII->hasLoadFromStackSlot(*this, Accesses))
2349 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2350 return None;
2351}
2352
2353unsigned MachineInstr::getDebugInstrNum() {
2354 if (DebugInstrNum == 0)
2355 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2356 return DebugInstrNum;
2357}
2358
2359unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) {
2360 if (DebugInstrNum == 0)
2361 DebugInstrNum = MF.getNewDebugInstrNum();
2362 return DebugInstrNum;
2363}