Bug Summary

File:build/source/llvm/lib/CodeGen/MachineInstr.cpp
Warning:line 1864, column 7
Value stored to 'HaveSemi' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name MachineInstr.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/source/build-llvm -resource-dir /usr/lib/llvm-16/lib/clang/16.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/CodeGen -I /build/source/llvm/lib/CodeGen -I include -I /build/source/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-16/lib/clang/16.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/source/build-llvm=build-llvm -fmacro-prefix-map=/build/source/= -fcoverage-prefix-map=/build/source/build-llvm=build-llvm -fcoverage-prefix-map=/build/source/= -source-date-epoch 1668078801 -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/source/build-llvm -fdebug-prefix-map=/build/source/build-llvm=build-llvm -fdebug-prefix-map=/build/source/= -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-11-10-135928-647445-1 -x c++ /build/source/llvm/lib/CodeGen/MachineInstr.cpp
1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Methods common to all machine instructions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineInstr.h"
14#include "llvm/ADT/ArrayRef.h"
15#include "llvm/ADT/Hashing.h"
16#include "llvm/ADT/None.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/ADT/SmallBitVector.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/Analysis/AliasAnalysis.h"
21#include "llvm/Analysis/MemoryLocation.h"
22#include "llvm/CodeGen/MachineBasicBlock.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineInstrBundle.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineModuleInfo.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/PseudoSourceValue.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/CodeGen/TargetInstrInfo.h"
34#include "llvm/CodeGen/TargetRegisterInfo.h"
35#include "llvm/CodeGen/TargetSubtargetInfo.h"
36#include "llvm/IR/Constants.h"
37#include "llvm/IR/DebugInfoMetadata.h"
38#include "llvm/IR/DebugLoc.h"
39#include "llvm/IR/Function.h"
40#include "llvm/IR/InlineAsm.h"
41#include "llvm/IR/LLVMContext.h"
42#include "llvm/IR/Metadata.h"
43#include "llvm/IR/Module.h"
44#include "llvm/IR/ModuleSlotTracker.h"
45#include "llvm/IR/Operator.h"
46#include "llvm/MC/MCInstrDesc.h"
47#include "llvm/MC/MCRegisterInfo.h"
48#include "llvm/Support/Casting.h"
49#include "llvm/Support/Compiler.h"
50#include "llvm/Support/Debug.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/FormattedStream.h"
53#include "llvm/Support/LowLevelTypeImpl.h"
54#include "llvm/Support/raw_ostream.h"
55#include "llvm/Target/TargetMachine.h"
56#include <algorithm>
57#include <cassert>
58#include <cstdint>
59#include <cstring>
60#include <utility>
61
62using namespace llvm;
63
64static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
65 if (const MachineBasicBlock *MBB = MI.getParent())
66 if (const MachineFunction *MF = MBB->getParent())
67 return MF;
68 return nullptr;
69}
70
71// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
72// it.
73static void tryToGetTargetInfo(const MachineInstr &MI,
74 const TargetRegisterInfo *&TRI,
75 const MachineRegisterInfo *&MRI,
76 const TargetIntrinsicInfo *&IntrinsicInfo,
77 const TargetInstrInfo *&TII) {
78
79 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
80 TRI = MF->getSubtarget().getRegisterInfo();
81 MRI = &MF->getRegInfo();
82 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
83 TII = MF->getSubtarget().getInstrInfo();
84 }
85}
86
87void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
88 if (MCID->ImplicitDefs)
89 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
90 ++ImpDefs)
91 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
92 if (MCID->ImplicitUses)
93 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
94 ++ImpUses)
95 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
96}
97
98/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
99/// implicit operands. It reserves space for the number of operands specified by
100/// the MCInstrDesc.
101MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID,
102 DebugLoc DL, bool NoImp)
103 : MCID(&TID), DbgLoc(std::move(DL)), DebugInstrNum(0) {
104 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (DbgLoc.hasTrivialDestructor() &&
"Expected trivial destructor") ? void (0) : __assert_fail ("DbgLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 104, __extension__ __PRETTY_FUNCTION__
))
;
105
106 // Reserve space for the expected number of operands.
107 if (unsigned NumOps = MCID->getNumOperands() +
108 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
109 CapOperands = OperandCapacity::get(NumOps);
110 Operands = MF.allocateOperandArray(CapOperands);
111 }
112
113 if (!NoImp)
114 addImplicitDefUseOperands(MF);
115}
116
117/// MachineInstr ctor - Copies MachineInstr arg exactly.
118/// Does not copy the number from debug instruction numbering, to preserve
119/// uniqueness.
120MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
121 : MCID(&MI.getDesc()), Info(MI.Info), DbgLoc(MI.getDebugLoc()),
122 DebugInstrNum(0) {
123 assert(DbgLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (DbgLoc.hasTrivialDestructor() &&
"Expected trivial destructor") ? void (0) : __assert_fail ("DbgLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 123, __extension__ __PRETTY_FUNCTION__
))
;
124
125 CapOperands = OperandCapacity::get(MI.getNumOperands());
126 Operands = MF.allocateOperandArray(CapOperands);
127
128 // Copy operands.
129 for (const MachineOperand &MO : MI.operands())
130 addOperand(MF, MO);
131
132 // Replicate ties between the operands, which addOperand was not
133 // able to do reliably.
134 for (unsigned i = 0, e = getNumOperands(); i < e; ++i) {
135 MachineOperand &NewMO = getOperand(i);
136 const MachineOperand &OrigMO = MI.getOperand(i);
137 NewMO.TiedTo = OrigMO.TiedTo;
138 }
139
140 // Copy all the sensible flags.
141 setFlags(MI.Flags);
142}
143
144void MachineInstr::moveBefore(MachineInstr *MovePos) {
145 MovePos->getParent()->splice(MovePos, getParent(), getIterator());
146}
147
148/// getRegInfo - If this instruction is embedded into a MachineFunction,
149/// return the MachineRegisterInfo object for the current function, otherwise
150/// return null.
151MachineRegisterInfo *MachineInstr::getRegInfo() {
152 if (MachineBasicBlock *MBB = getParent())
153 return &MBB->getParent()->getRegInfo();
154 return nullptr;
155}
156
157void MachineInstr::removeRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
158 for (MachineOperand &MO : operands())
159 if (MO.isReg())
160 MRI.removeRegOperandFromUseList(&MO);
161}
162
163void MachineInstr::addRegOperandsToUseLists(MachineRegisterInfo &MRI) {
164 for (MachineOperand &MO : operands())
165 if (MO.isReg())
166 MRI.addRegOperandToUseList(&MO);
167}
168
169void MachineInstr::addOperand(const MachineOperand &Op) {
170 MachineBasicBlock *MBB = getParent();
171 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")(static_cast <bool> (MBB && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? void (0) : __assert_fail ("MBB && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 171, __extension__ __PRETTY_FUNCTION__
))
;
172 MachineFunction *MF = MBB->getParent();
173 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")(static_cast <bool> (MF && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? void (0) : __assert_fail ("MF && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 173, __extension__ __PRETTY_FUNCTION__
))
;
174 addOperand(*MF, Op);
175}
176
177/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
178/// ranges. If MRI is non-null also update use-def chains.
179static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
180 unsigned NumOps, MachineRegisterInfo *MRI) {
181 if (MRI)
182 return MRI->moveOperands(Dst, Src, NumOps);
183 // MachineOperand is a trivially copyable type so we can just use memmove.
184 assert(Dst && Src && "Unknown operands")(static_cast <bool> (Dst && Src && "Unknown operands"
) ? void (0) : __assert_fail ("Dst && Src && \"Unknown operands\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 184, __extension__ __PRETTY_FUNCTION__
))
;
185 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
186}
187
188/// addOperand - Add the specified operand to the instruction. If it is an
189/// implicit operand, it is added to the end of the operand list. If it is
190/// an explicit operand it is added at the end of the explicit operand list
191/// (before the first implicit operand).
192void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
193 assert(MCID && "Cannot add operands before providing an instr descriptor")(static_cast <bool> (MCID && "Cannot add operands before providing an instr descriptor"
) ? void (0) : __assert_fail ("MCID && \"Cannot add operands before providing an instr descriptor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 193, __extension__ __PRETTY_FUNCTION__
))
;
194
195 // Check if we're adding one of our existing operands.
196 if (&Op >= Operands && &Op < Operands + NumOperands) {
197 // This is unusual: MI->addOperand(MI->getOperand(i)).
198 // If adding Op requires reallocating or moving existing operands around,
199 // the Op reference could go stale. Support it by copying Op.
200 MachineOperand CopyOp(Op);
201 return addOperand(MF, CopyOp);
202 }
203
204 // Find the insert location for the new operand. Implicit registers go at
205 // the end, everything else goes before the implicit regs.
206 //
207 // FIXME: Allow mixed explicit and implicit operands on inline asm.
208 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
209 // implicit-defs, but they must not be moved around. See the FIXME in
210 // InstrEmitter.cpp.
211 unsigned OpNo = getNumOperands();
212 bool isImpReg = Op.isReg() && Op.isImplicit();
213 if (!isImpReg && !isInlineAsm()) {
214 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
215 --OpNo;
216 assert(!Operands[OpNo].isTied() && "Cannot move tied operands")(static_cast <bool> (!Operands[OpNo].isTied() &&
"Cannot move tied operands") ? void (0) : __assert_fail ("!Operands[OpNo].isTied() && \"Cannot move tied operands\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 216, __extension__ __PRETTY_FUNCTION__
))
;
217 }
218 }
219
220 // OpNo now points as the desired insertion point. Unless this is a variadic
221 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
222 // RegMask operands go between the explicit and implicit operands.
223 assert((MCID->isVariadic() || OpNo < MCID->getNumOperands() ||(static_cast <bool> ((MCID->isVariadic() || OpNo <
MCID->getNumOperands() || Op.isValidExcessOperand()) &&
"Trying to add an operand to a machine instr that is already done!"
) ? void (0) : __assert_fail ("(MCID->isVariadic() || OpNo < MCID->getNumOperands() || Op.isValidExcessOperand()) && \"Trying to add an operand to a machine instr that is already done!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 225, __extension__ __PRETTY_FUNCTION__
))
224 Op.isValidExcessOperand()) &&(static_cast <bool> ((MCID->isVariadic() || OpNo <
MCID->getNumOperands() || Op.isValidExcessOperand()) &&
"Trying to add an operand to a machine instr that is already done!"
) ? void (0) : __assert_fail ("(MCID->isVariadic() || OpNo < MCID->getNumOperands() || Op.isValidExcessOperand()) && \"Trying to add an operand to a machine instr that is already done!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 225, __extension__ __PRETTY_FUNCTION__
))
225 "Trying to add an operand to a machine instr that is already done!")(static_cast <bool> ((MCID->isVariadic() || OpNo <
MCID->getNumOperands() || Op.isValidExcessOperand()) &&
"Trying to add an operand to a machine instr that is already done!"
) ? void (0) : __assert_fail ("(MCID->isVariadic() || OpNo < MCID->getNumOperands() || Op.isValidExcessOperand()) && \"Trying to add an operand to a machine instr that is already done!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 225, __extension__ __PRETTY_FUNCTION__
))
;
226
227 MachineRegisterInfo *MRI = getRegInfo();
228
229 // Determine if the Operands array needs to be reallocated.
230 // Save the old capacity and operand array.
231 OperandCapacity OldCap = CapOperands;
232 MachineOperand *OldOperands = Operands;
233 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
234 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
235 Operands = MF.allocateOperandArray(CapOperands);
236 // Move the operands before the insertion point.
237 if (OpNo)
238 moveOperands(Operands, OldOperands, OpNo, MRI);
239 }
240
241 // Move the operands following the insertion point.
242 if (OpNo != NumOperands)
243 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
244 MRI);
245 ++NumOperands;
246
247 // Deallocate the old operand array.
248 if (OldOperands != Operands && OldOperands)
249 MF.deallocateOperandArray(OldCap, OldOperands);
250
251 // Copy Op into place. It still needs to be inserted into the MRI use lists.
252 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
253 NewMO->ParentMI = this;
254
255 // When adding a register operand, tell MRI about it.
256 if (NewMO->isReg()) {
257 // Ensure isOnRegUseList() returns false, regardless of Op's status.
258 NewMO->Contents.Reg.Prev = nullptr;
259 // Ignore existing ties. This is not a property that can be copied.
260 NewMO->TiedTo = 0;
261 // Add the new operand to MRI, but only for instructions in an MBB.
262 if (MRI)
263 MRI->addRegOperandToUseList(NewMO);
264 // The MCID operand information isn't accurate until we start adding
265 // explicit operands. The implicit operands are added first, then the
266 // explicits are inserted before them.
267 if (!isImpReg) {
268 // Tie uses to defs as indicated in MCInstrDesc.
269 if (NewMO->isUse()) {
270 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
271 if (DefIdx != -1)
272 tieOperands(DefIdx, OpNo);
273 }
274 // If the register operand is flagged as early, mark the operand as such.
275 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
276 NewMO->setIsEarlyClobber(true);
277 }
278 // Ensure debug instructions set debug flag on register uses.
279 if (NewMO->isUse() && isDebugInstr())
280 NewMO->setIsDebug();
281 }
282}
283
284void MachineInstr::removeOperand(unsigned OpNo) {
285 assert(OpNo < getNumOperands() && "Invalid operand number")(static_cast <bool> (OpNo < getNumOperands() &&
"Invalid operand number") ? void (0) : __assert_fail ("OpNo < getNumOperands() && \"Invalid operand number\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 285, __extension__ __PRETTY_FUNCTION__
))
;
286 untieRegOperand(OpNo);
287
288#ifndef NDEBUG
289 // Moving tied operands would break the ties.
290 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
291 if (Operands[i].isReg())
292 assert(!Operands[i].isTied() && "Cannot move tied operands")(static_cast <bool> (!Operands[i].isTied() && "Cannot move tied operands"
) ? void (0) : __assert_fail ("!Operands[i].isTied() && \"Cannot move tied operands\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 292, __extension__ __PRETTY_FUNCTION__
))
;
293#endif
294
295 MachineRegisterInfo *MRI = getRegInfo();
296 if (MRI && Operands[OpNo].isReg())
297 MRI->removeRegOperandFromUseList(Operands + OpNo);
298
299 // Don't call the MachineOperand destructor. A lot of this code depends on
300 // MachineOperand having a trivial destructor anyway, and adding a call here
301 // wouldn't make it 'destructor-correct'.
302
303 if (unsigned N = NumOperands - 1 - OpNo)
304 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
305 --NumOperands;
306}
307
308void MachineInstr::setExtraInfo(MachineFunction &MF,
309 ArrayRef<MachineMemOperand *> MMOs,
310 MCSymbol *PreInstrSymbol,
311 MCSymbol *PostInstrSymbol,
312 MDNode *HeapAllocMarker, MDNode *PCSections,
313 uint32_t CFIType) {
314 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
315 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
316 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
317 bool HasPCSections = PCSections != nullptr;
318 bool HasCFIType = CFIType != 0;
319 int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol +
320 HasHeapAllocMarker + HasPCSections + HasCFIType;
321
322 // Drop all extra info if there is none.
323 if (NumPointers <= 0) {
324 Info.clear();
325 return;
326 }
327
328 // If more than one pointer, then store out of line. Store heap alloc markers
329 // out of line because PointerSumType cannot hold more than 4 tag types with
330 // 32-bit pointers.
331 // FIXME: Maybe we should make the symbols in the extra info mutable?
332 else if (NumPointers > 1 || HasHeapAllocMarker || HasPCSections ||
333 HasCFIType) {
334 Info.set<EIIK_OutOfLine>(
335 MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol,
336 HeapAllocMarker, PCSections, CFIType));
337 return;
338 }
339
340 // Otherwise store the single pointer inline.
341 if (HasPreInstrSymbol)
342 Info.set<EIIK_PreInstrSymbol>(PreInstrSymbol);
343 else if (HasPostInstrSymbol)
344 Info.set<EIIK_PostInstrSymbol>(PostInstrSymbol);
345 else
346 Info.set<EIIK_MMO>(MMOs[0]);
347}
348
349void MachineInstr::dropMemRefs(MachineFunction &MF) {
350 if (memoperands_empty())
351 return;
352
353 setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(),
354 getHeapAllocMarker(), getPCSections(), getCFIType());
355}
356
357void MachineInstr::setMemRefs(MachineFunction &MF,
358 ArrayRef<MachineMemOperand *> MMOs) {
359 if (MMOs.empty()) {
360 dropMemRefs(MF);
361 return;
362 }
363
364 setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(),
365 getHeapAllocMarker(), getPCSections(), getCFIType());
366}
367
368void MachineInstr::addMemOperand(MachineFunction &MF,
369 MachineMemOperand *MO) {
370 SmallVector<MachineMemOperand *, 2> MMOs;
371 MMOs.append(memoperands_begin(), memoperands_end());
372 MMOs.push_back(MO);
373 setMemRefs(MF, MMOs);
374}
375
376void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
377 if (this == &MI)
378 // Nothing to do for a self-clone!
379 return;
380
381 assert(&MF == MI.getMF() &&(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 382, __extension__ __PRETTY_FUNCTION__
))
382 "Invalid machine functions when cloning memory refrences!")(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 382, __extension__ __PRETTY_FUNCTION__
))
;
383 // See if we can just steal the extra info already allocated for the
384 // instruction. We can do this whenever the pre- and post-instruction symbols
385 // are the same (including null).
386 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
387 getPostInstrSymbol() == MI.getPostInstrSymbol() &&
388 getHeapAllocMarker() == MI.getHeapAllocMarker() &&
389 getPCSections() == MI.getPCSections()) {
390 Info = MI.Info;
391 return;
392 }
393
394 // Otherwise, fall back on a copy-based clone.
395 setMemRefs(MF, MI.memoperands());
396}
397
398/// Check to see if the MMOs pointed to by the two MemRefs arrays are
399/// identical.
400static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
401 ArrayRef<MachineMemOperand *> RHS) {
402 if (LHS.size() != RHS.size())
403 return false;
404
405 auto LHSPointees = make_pointee_range(LHS);
406 auto RHSPointees = make_pointee_range(RHS);
407 return std::equal(LHSPointees.begin(), LHSPointees.end(),
408 RHSPointees.begin());
409}
410
411void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
412 ArrayRef<const MachineInstr *> MIs) {
413 // Try handling easy numbers of MIs with simpler mechanisms.
414 if (MIs.empty()) {
415 dropMemRefs(MF);
416 return;
417 }
418 if (MIs.size() == 1) {
419 cloneMemRefs(MF, *MIs[0]);
420 return;
421 }
422 // Because an empty memoperands list provides *no* information and must be
423 // handled conservatively (assuming the instruction can do anything), the only
424 // way to merge with it is to drop all other memoperands.
425 if (MIs[0]->memoperands_empty()) {
426 dropMemRefs(MF);
427 return;
428 }
429
430 // Handle the general case.
431 SmallVector<MachineMemOperand *, 2> MergedMMOs;
432 // Start with the first instruction.
433 assert(&MF == MIs[0]->getMF() &&(static_cast <bool> (&MF == MIs[0]->getMF() &&
"Invalid machine functions when cloning memory references!")
? void (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 434, __extension__ __PRETTY_FUNCTION__
))
434 "Invalid machine functions when cloning memory references!")(static_cast <bool> (&MF == MIs[0]->getMF() &&
"Invalid machine functions when cloning memory references!")
? void (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 434, __extension__ __PRETTY_FUNCTION__
))
;
435 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
436 // Now walk all the other instructions and accumulate any different MMOs.
437 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
438 assert(&MF == MI.getMF() &&(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 439, __extension__ __PRETTY_FUNCTION__
))
439 "Invalid machine functions when cloning memory references!")(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 439, __extension__ __PRETTY_FUNCTION__
))
;
440
441 // Skip MIs with identical operands to the first. This is a somewhat
442 // arbitrary hack but will catch common cases without being quadratic.
443 // TODO: We could fully implement merge semantics here if needed.
444 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
445 continue;
446
447 // Because an empty memoperands list provides *no* information and must be
448 // handled conservatively (assuming the instruction can do anything), the
449 // only way to merge with it is to drop all other memoperands.
450 if (MI.memoperands_empty()) {
451 dropMemRefs(MF);
452 return;
453 }
454
455 // Otherwise accumulate these into our temporary buffer of the merged state.
456 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
457 }
458
459 setMemRefs(MF, MergedMMOs);
460}
461
462void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
463 // Do nothing if old and new symbols are the same.
464 if (Symbol == getPreInstrSymbol())
465 return;
466
467 // If there was only one symbol and we're removing it, just clear info.
468 if (!Symbol && Info.is<EIIK_PreInstrSymbol>()) {
469 Info.clear();
470 return;
471 }
472
473 setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(),
474 getHeapAllocMarker(), getPCSections(), getCFIType());
475}
476
477void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
478 // Do nothing if old and new symbols are the same.
479 if (Symbol == getPostInstrSymbol())
480 return;
481
482 // If there was only one symbol and we're removing it, just clear info.
483 if (!Symbol && Info.is<EIIK_PostInstrSymbol>()) {
484 Info.clear();
485 return;
486 }
487
488 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol,
489 getHeapAllocMarker(), getPCSections(), getCFIType());
490}
491
492void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) {
493 // Do nothing if old and new symbols are the same.
494 if (Marker == getHeapAllocMarker())
495 return;
496
497 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
498 Marker, getPCSections(), getCFIType());
499}
500
501void MachineInstr::setPCSections(MachineFunction &MF, MDNode *PCSections) {
502 // Do nothing if old and new symbols are the same.
503 if (PCSections == getPCSections())
504 return;
505
506 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
507 getHeapAllocMarker(), PCSections, getCFIType());
508}
509
510void MachineInstr::setCFIType(MachineFunction &MF, uint32_t Type) {
511 // Do nothing if old and new types are the same.
512 if (Type == getCFIType())
513 return;
514
515 setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(),
516 getHeapAllocMarker(), getPCSections(), Type);
517}
518
519void MachineInstr::cloneInstrSymbols(MachineFunction &MF,
520 const MachineInstr &MI) {
521 if (this == &MI)
522 // Nothing to do for a self-clone!
523 return;
524
525 assert(&MF == MI.getMF() &&(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 526, __extension__ __PRETTY_FUNCTION__
))
526 "Invalid machine functions when cloning instruction symbols!")(static_cast <bool> (&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!"
) ? void (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 526, __extension__ __PRETTY_FUNCTION__
))
;
527
528 setPreInstrSymbol(MF, MI.getPreInstrSymbol());
529 setPostInstrSymbol(MF, MI.getPostInstrSymbol());
530 setHeapAllocMarker(MF, MI.getHeapAllocMarker());
531 setPCSections(MF, MI.getPCSections());
532}
533
534uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
535 // For now, the just return the union of the flags. If the flags get more
536 // complicated over time, we might need more logic here.
537 return getFlags() | Other.getFlags();
538}
539
540uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) {
541 uint16_t MIFlags = 0;
542 // Copy the wrapping flags.
543 if (const OverflowingBinaryOperator *OB =
544 dyn_cast<OverflowingBinaryOperator>(&I)) {
545 if (OB->hasNoSignedWrap())
546 MIFlags |= MachineInstr::MIFlag::NoSWrap;
547 if (OB->hasNoUnsignedWrap())
548 MIFlags |= MachineInstr::MIFlag::NoUWrap;
549 }
550
551 // Copy the exact flag.
552 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
553 if (PE->isExact())
554 MIFlags |= MachineInstr::MIFlag::IsExact;
555
556 // Copy the fast-math flags.
557 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
558 const FastMathFlags Flags = FP->getFastMathFlags();
559 if (Flags.noNaNs())
560 MIFlags |= MachineInstr::MIFlag::FmNoNans;
561 if (Flags.noInfs())
562 MIFlags |= MachineInstr::MIFlag::FmNoInfs;
563 if (Flags.noSignedZeros())
564 MIFlags |= MachineInstr::MIFlag::FmNsz;
565 if (Flags.allowReciprocal())
566 MIFlags |= MachineInstr::MIFlag::FmArcp;
567 if (Flags.allowContract())
568 MIFlags |= MachineInstr::MIFlag::FmContract;
569 if (Flags.approxFunc())
570 MIFlags |= MachineInstr::MIFlag::FmAfn;
571 if (Flags.allowReassoc())
572 MIFlags |= MachineInstr::MIFlag::FmReassoc;
573 }
574
575 return MIFlags;
576}
577
578void MachineInstr::copyIRFlags(const Instruction &I) {
579 Flags = copyFlagsFromInstruction(I);
580}
581
582bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
583 assert(!isBundledWithPred() && "Must be called on bundle header")(static_cast <bool> (!isBundledWithPred() && "Must be called on bundle header"
) ? void (0) : __assert_fail ("!isBundledWithPred() && \"Must be called on bundle header\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 583, __extension__ __PRETTY_FUNCTION__
))
;
584 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
585 if (MII->getDesc().getFlags() & Mask) {
586 if (Type == AnyInBundle)
587 return true;
588 } else {
589 if (Type == AllInBundle && !MII->isBundle())
590 return false;
591 }
592 // This was the last instruction in the bundle.
593 if (!MII->isBundledWithSucc())
594 return Type == AllInBundle;
595 }
596}
597
598bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
599 MICheckType Check) const {
600 // If opcodes or number of operands are not the same then the two
601 // instructions are obviously not identical.
602 if (Other.getOpcode() != getOpcode() ||
603 Other.getNumOperands() != getNumOperands())
604 return false;
605
606 if (isBundle()) {
607 // We have passed the test above that both instructions have the same
608 // opcode, so we know that both instructions are bundles here. Let's compare
609 // MIs inside the bundle.
610 assert(Other.isBundle() && "Expected that both instructions are bundles.")(static_cast <bool> (Other.isBundle() && "Expected that both instructions are bundles."
) ? void (0) : __assert_fail ("Other.isBundle() && \"Expected that both instructions are bundles.\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 610, __extension__ __PRETTY_FUNCTION__
))
;
611 MachineBasicBlock::const_instr_iterator I1 = getIterator();
612 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
613 // Loop until we analysed the last intruction inside at least one of the
614 // bundles.
615 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
616 ++I1;
617 ++I2;
618 if (!I1->isIdenticalTo(*I2, Check))
619 return false;
620 }
621 // If we've reached the end of just one of the two bundles, but not both,
622 // the instructions are not identical.
623 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
624 return false;
625 }
626
627 // Check operands to make sure they match.
628 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
629 const MachineOperand &MO = getOperand(i);
630 const MachineOperand &OMO = Other.getOperand(i);
631 if (!MO.isReg()) {
632 if (!MO.isIdenticalTo(OMO))
633 return false;
634 continue;
635 }
636
637 // Clients may or may not want to ignore defs when testing for equality.
638 // For example, machine CSE pass only cares about finding common
639 // subexpressions, so it's safe to ignore virtual register defs.
640 if (MO.isDef()) {
641 if (Check == IgnoreDefs)
642 continue;
643 else if (Check == IgnoreVRegDefs) {
644 if (!Register::isVirtualRegister(MO.getReg()) ||
645 !Register::isVirtualRegister(OMO.getReg()))
646 if (!MO.isIdenticalTo(OMO))
647 return false;
648 } else {
649 if (!MO.isIdenticalTo(OMO))
650 return false;
651 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
652 return false;
653 }
654 } else {
655 if (!MO.isIdenticalTo(OMO))
656 return false;
657 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
658 return false;
659 }
660 }
661 // If DebugLoc does not match then two debug instructions are not identical.
662 if (isDebugInstr())
663 if (getDebugLoc() && Other.getDebugLoc() &&
664 getDebugLoc() != Other.getDebugLoc())
665 return false;
666 // If pre- or post-instruction symbols do not match then the two instructions
667 // are not identical.
668 if (getPreInstrSymbol() != Other.getPreInstrSymbol() ||
669 getPostInstrSymbol() != Other.getPostInstrSymbol())
670 return false;
671 // Call instructions with different CFI types are not identical.
672 if (isCall() && getCFIType() != Other.getCFIType())
673 return false;
674
675 return true;
676}
677
678const MachineFunction *MachineInstr::getMF() const {
679 return getParent()->getParent();
680}
681
682MachineInstr *MachineInstr::removeFromParent() {
683 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 683, __extension__ __PRETTY_FUNCTION__
))
;
684 return getParent()->remove(this);
685}
686
687MachineInstr *MachineInstr::removeFromBundle() {
688 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 688, __extension__ __PRETTY_FUNCTION__
))
;
689 return getParent()->remove_instr(this);
690}
691
692void MachineInstr::eraseFromParent() {
693 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 693, __extension__ __PRETTY_FUNCTION__
))
;
694 getParent()->erase(this);
695}
696
697void MachineInstr::eraseFromBundle() {
698 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 698, __extension__ __PRETTY_FUNCTION__
))
;
699 getParent()->erase_instr(this);
700}
701
702bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const {
703 if (!isCall(Type))
704 return false;
705 switch (getOpcode()) {
706 case TargetOpcode::PATCHPOINT:
707 case TargetOpcode::STACKMAP:
708 case TargetOpcode::STATEPOINT:
709 case TargetOpcode::FENTRY_CALL:
710 return false;
711 }
712 return true;
713}
714
715bool MachineInstr::shouldUpdateCallSiteInfo() const {
716 if (isBundle())
717 return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle);
718 return isCandidateForCallSiteEntry();
719}
720
721unsigned MachineInstr::getNumExplicitOperands() const {
722 unsigned NumOperands = MCID->getNumOperands();
723 if (!MCID->isVariadic())
724 return NumOperands;
725
726 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
727 const MachineOperand &MO = getOperand(I);
728 // The operands must always be in the following order:
729 // - explicit reg defs,
730 // - other explicit operands (reg uses, immediates, etc.),
731 // - implicit reg defs
732 // - implicit reg uses
733 if (MO.isReg() && MO.isImplicit())
734 break;
735 ++NumOperands;
736 }
737 return NumOperands;
738}
739
740unsigned MachineInstr::getNumExplicitDefs() const {
741 unsigned NumDefs = MCID->getNumDefs();
742 if (!MCID->isVariadic())
743 return NumDefs;
744
745 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
746 const MachineOperand &MO = getOperand(I);
747 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
748 break;
749 ++NumDefs;
750 }
751 return NumDefs;
752}
753
754void MachineInstr::bundleWithPred() {
755 assert(!isBundledWithPred() && "MI is already bundled with its predecessor")(static_cast <bool> (!isBundledWithPred() && "MI is already bundled with its predecessor"
) ? void (0) : __assert_fail ("!isBundledWithPred() && \"MI is already bundled with its predecessor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 755, __extension__ __PRETTY_FUNCTION__
))
;
756 setFlag(BundledPred);
757 MachineBasicBlock::instr_iterator Pred = getIterator();
758 --Pred;
759 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")(static_cast <bool> (!Pred->isBundledWithSucc() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("!Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 759, __extension__ __PRETTY_FUNCTION__
))
;
760 Pred->setFlag(BundledSucc);
761}
762
763void MachineInstr::bundleWithSucc() {
764 assert(!isBundledWithSucc() && "MI is already bundled with its successor")(static_cast <bool> (!isBundledWithSucc() && "MI is already bundled with its successor"
) ? void (0) : __assert_fail ("!isBundledWithSucc() && \"MI is already bundled with its successor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 764, __extension__ __PRETTY_FUNCTION__
))
;
765 setFlag(BundledSucc);
766 MachineBasicBlock::instr_iterator Succ = getIterator();
767 ++Succ;
768 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")(static_cast <bool> (!Succ->isBundledWithPred() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("!Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 768, __extension__ __PRETTY_FUNCTION__
))
;
769 Succ->setFlag(BundledPred);
770}
771
772void MachineInstr::unbundleFromPred() {
773 assert(isBundledWithPred() && "MI isn't bundled with its predecessor")(static_cast <bool> (isBundledWithPred() && "MI isn't bundled with its predecessor"
) ? void (0) : __assert_fail ("isBundledWithPred() && \"MI isn't bundled with its predecessor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 773, __extension__ __PRETTY_FUNCTION__
))
;
774 clearFlag(BundledPred);
775 MachineBasicBlock::instr_iterator Pred = getIterator();
776 --Pred;
777 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")(static_cast <bool> (Pred->isBundledWithSucc() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 777, __extension__ __PRETTY_FUNCTION__
))
;
778 Pred->clearFlag(BundledSucc);
779}
780
781void MachineInstr::unbundleFromSucc() {
782 assert(isBundledWithSucc() && "MI isn't bundled with its successor")(static_cast <bool> (isBundledWithSucc() && "MI isn't bundled with its successor"
) ? void (0) : __assert_fail ("isBundledWithSucc() && \"MI isn't bundled with its successor\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 782, __extension__ __PRETTY_FUNCTION__
))
;
783 clearFlag(BundledSucc);
784 MachineBasicBlock::instr_iterator Succ = getIterator();
785 ++Succ;
786 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")(static_cast <bool> (Succ->isBundledWithPred() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 786, __extension__ __PRETTY_FUNCTION__
))
;
787 Succ->clearFlag(BundledPred);
788}
789
790bool MachineInstr::isStackAligningInlineAsm() const {
791 if (isInlineAsm()) {
792 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
793 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
794 return true;
795 }
796 return false;
797}
798
799InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
800 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")(static_cast <bool> (isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"
) ? void (0) : __assert_fail ("isInlineAsm() && \"getInlineAsmDialect() only works for inline asms!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 800, __extension__ __PRETTY_FUNCTION__
))
;
801 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
802 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
803}
804
805int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
806 unsigned *GroupNo) const {
807 assert(isInlineAsm() && "Expected an inline asm instruction")(static_cast <bool> (isInlineAsm() && "Expected an inline asm instruction"
) ? void (0) : __assert_fail ("isInlineAsm() && \"Expected an inline asm instruction\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 807, __extension__ __PRETTY_FUNCTION__
))
;
808 assert(OpIdx < getNumOperands() && "OpIdx out of range")(static_cast <bool> (OpIdx < getNumOperands() &&
"OpIdx out of range") ? void (0) : __assert_fail ("OpIdx < getNumOperands() && \"OpIdx out of range\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 808, __extension__ __PRETTY_FUNCTION__
))
;
809
810 // Ignore queries about the initial operands.
811 if (OpIdx < InlineAsm::MIOp_FirstOperand)
812 return -1;
813
814 unsigned Group = 0;
815 unsigned NumOps;
816 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
817 i += NumOps) {
818 const MachineOperand &FlagMO = getOperand(i);
819 // If we reach the implicit register operands, stop looking.
820 if (!FlagMO.isImm())
821 return -1;
822 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
823 if (i + NumOps > OpIdx) {
824 if (GroupNo)
825 *GroupNo = Group;
826 return i;
827 }
828 ++Group;
829 }
830 return -1;
831}
832
833const DILabel *MachineInstr::getDebugLabel() const {
834 assert(isDebugLabel() && "not a DBG_LABEL")(static_cast <bool> (isDebugLabel() && "not a DBG_LABEL"
) ? void (0) : __assert_fail ("isDebugLabel() && \"not a DBG_LABEL\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 834, __extension__ __PRETTY_FUNCTION__
))
;
835 return cast<DILabel>(getOperand(0).getMetadata());
836}
837
838const MachineOperand &MachineInstr::getDebugVariableOp() const {
839 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")(static_cast <bool> ((isDebugValue() || isDebugRef()) &&
"not a DBG_VALUE*") ? void (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE*\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 839, __extension__ __PRETTY_FUNCTION__
))
;
840 unsigned VariableOp = isDebugValueList() ? 0 : 2;
841 return getOperand(VariableOp);
842}
843
844MachineOperand &MachineInstr::getDebugVariableOp() {
845 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")(static_cast <bool> ((isDebugValue() || isDebugRef()) &&
"not a DBG_VALUE*") ? void (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE*\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 845, __extension__ __PRETTY_FUNCTION__
))
;
846 unsigned VariableOp = isDebugValueList() ? 0 : 2;
847 return getOperand(VariableOp);
848}
849
850const DILocalVariable *MachineInstr::getDebugVariable() const {
851 return cast<DILocalVariable>(getDebugVariableOp().getMetadata());
852}
853
854const MachineOperand &MachineInstr::getDebugExpressionOp() const {
855 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")(static_cast <bool> ((isDebugValue() || isDebugRef()) &&
"not a DBG_VALUE*") ? void (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE*\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 855, __extension__ __PRETTY_FUNCTION__
))
;
856 unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
857 return getOperand(ExpressionOp);
858}
859
860MachineOperand &MachineInstr::getDebugExpressionOp() {
861 assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*")(static_cast <bool> ((isDebugValue() || isDebugRef()) &&
"not a DBG_VALUE*") ? void (0) : __assert_fail ("(isDebugValue() || isDebugRef()) && \"not a DBG_VALUE*\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 861, __extension__ __PRETTY_FUNCTION__
))
;
862 unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
863 return getOperand(ExpressionOp);
864}
865
866const DIExpression *MachineInstr::getDebugExpression() const {
867 return cast<DIExpression>(getDebugExpressionOp().getMetadata());
868}
869
870bool MachineInstr::isDebugEntryValue() const {
871 return isDebugValue() && getDebugExpression()->isEntryValue();
872}
873
874const TargetRegisterClass*
875MachineInstr::getRegClassConstraint(unsigned OpIdx,
876 const TargetInstrInfo *TII,
877 const TargetRegisterInfo *TRI) const {
878 assert(getParent() && "Can't have an MBB reference here!")(static_cast <bool> (getParent() && "Can't have an MBB reference here!"
) ? void (0) : __assert_fail ("getParent() && \"Can't have an MBB reference here!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 878, __extension__ __PRETTY_FUNCTION__
))
;
879 assert(getMF() && "Can't have an MF reference here!")(static_cast <bool> (getMF() && "Can't have an MF reference here!"
) ? void (0) : __assert_fail ("getMF() && \"Can't have an MF reference here!\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 879, __extension__ __PRETTY_FUNCTION__
))
;
880 const MachineFunction &MF = *getMF();
881
882 // Most opcodes have fixed constraints in their MCInstrDesc.
883 if (!isInlineAsm())
884 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
885
886 if (!getOperand(OpIdx).isReg())
887 return nullptr;
888
889 // For tied uses on inline asm, get the constraint from the def.
890 unsigned DefIdx;
891 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
892 OpIdx = DefIdx;
893
894 // Inline asm stores register class constraints in the flag word.
895 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
896 if (FlagIdx < 0)
897 return nullptr;
898
899 unsigned Flag = getOperand(FlagIdx).getImm();
900 unsigned RCID;
901 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
902 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
903 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
904 InlineAsm::hasRegClassConstraint(Flag, RCID))
905 return TRI->getRegClass(RCID);
906
907 // Assume that all registers in a memory operand are pointers.
908 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
909 return TRI->getPointerRegClass(MF);
910
911 return nullptr;
912}
913
914const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
915 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
916 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
917 // Check every operands inside the bundle if we have
918 // been asked to.
919 if (ExploreBundle)
920 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
921 ++OpndIt)
922 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
923 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
924 else
925 // Otherwise, just check the current operands.
926 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
927 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
928 return CurRC;
929}
930
931const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
932 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
933 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
934 assert(CurRC && "Invalid initial register class")(static_cast <bool> (CurRC && "Invalid initial register class"
) ? void (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 934, __extension__ __PRETTY_FUNCTION__
))
;
935 // Check if Reg is constrained by some of its use/def from MI.
936 const MachineOperand &MO = getOperand(OpIdx);
937 if (!MO.isReg() || MO.getReg() != Reg)
938 return CurRC;
939 // If yes, accumulate the constraints through the operand.
940 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
941}
942
943const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
944 unsigned OpIdx, const TargetRegisterClass *CurRC,
945 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
946 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
947 const MachineOperand &MO = getOperand(OpIdx);
948 assert(MO.isReg() &&(static_cast <bool> (MO.isReg() && "Cannot get register constraints for non-register operand"
) ? void (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 949, __extension__ __PRETTY_FUNCTION__
))
949 "Cannot get register constraints for non-register operand")(static_cast <bool> (MO.isReg() && "Cannot get register constraints for non-register operand"
) ? void (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 949, __extension__ __PRETTY_FUNCTION__
))
;
950 assert(CurRC && "Invalid initial register class")(static_cast <bool> (CurRC && "Invalid initial register class"
) ? void (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 950, __extension__ __PRETTY_FUNCTION__
))
;
951 if (unsigned SubIdx = MO.getSubReg()) {
952 if (OpRC)
953 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
954 else
955 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
956 } else if (OpRC)
957 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
958 return CurRC;
959}
960
961/// Return the number of instructions inside the MI bundle, not counting the
962/// header instruction.
963unsigned MachineInstr::getBundleSize() const {
964 MachineBasicBlock::const_instr_iterator I = getIterator();
965 unsigned Size = 0;
966 while (I->isBundledWithSucc()) {
967 ++Size;
968 ++I;
969 }
970 return Size;
971}
972
973/// Returns true if the MachineInstr has an implicit-use operand of exactly
974/// the given register (not considering sub/super-registers).
975bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
976 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
977 const MachineOperand &MO = getOperand(i);
978 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
979 return true;
980 }
981 return false;
982}
983
984/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
985/// the specific register or -1 if it is not found. It further tightens
986/// the search criteria to a use that kills the register if isKill is true.
987int MachineInstr::findRegisterUseOperandIdx(
988 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
989 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
990 const MachineOperand &MO = getOperand(i);
991 if (!MO.isReg() || !MO.isUse())
992 continue;
993 Register MOReg = MO.getReg();
994 if (!MOReg)
995 continue;
996 if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg)))
997 if (!isKill || MO.isKill())
998 return i;
999 }
1000 return -1;
1001}
1002
1003/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1004/// indicating if this instruction reads or writes Reg. This also considers
1005/// partial defines.
1006std::pair<bool,bool>
1007MachineInstr::readsWritesVirtualRegister(Register Reg,
1008 SmallVectorImpl<unsigned> *Ops) const {
1009 bool PartDef = false; // Partial redefine.
1010 bool FullDef = false; // Full define.
1011 bool Use = false;
1012
1013 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1014 const MachineOperand &MO = getOperand(i);
1015 if (!MO.isReg() || MO.getReg() != Reg)
1016 continue;
1017 if (Ops)
1018 Ops->push_back(i);
1019 if (MO.isUse())
1020 Use |= !MO.isUndef();
1021 else if (MO.getSubReg() && !MO.isUndef())
1022 // A partial def undef doesn't count as reading the register.
1023 PartDef = true;
1024 else
1025 FullDef = true;
1026 }
1027 // A partial redefine uses Reg unless there is also a full define.
1028 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1029}
1030
1031/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1032/// the specified register or -1 if it is not found. If isDead is true, defs
1033/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1034/// also checks if there is a def of a super-register.
1035int
1036MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap,
1037 const TargetRegisterInfo *TRI) const {
1038 bool isPhys = Register::isPhysicalRegister(Reg);
1039 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1040 const MachineOperand &MO = getOperand(i);
1041 // Accept regmask operands when Overlap is set.
1042 // Ignore them when looking for a specific def operand (Overlap == false).
1043 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1044 return i;
1045 if (!MO.isReg() || !MO.isDef())
1046 continue;
1047 Register MOReg = MO.getReg();
1048 bool Found = (MOReg == Reg);
1049 if (!Found && TRI && isPhys && Register::isPhysicalRegister(MOReg)) {
1050 if (Overlap)
1051 Found = TRI->regsOverlap(MOReg, Reg);
1052 else
1053 Found = TRI->isSubRegister(MOReg, Reg);
1054 }
1055 if (Found && (!isDead || MO.isDead()))
1056 return i;
1057 }
1058 return -1;
1059}
1060
1061/// findFirstPredOperandIdx() - Find the index of the first operand in the
1062/// operand list that is used to represent the predicate. It returns -1 if
1063/// none is found.
1064int MachineInstr::findFirstPredOperandIdx() const {
1065 // Don't call MCID.findFirstPredOperandIdx() because this variant
1066 // is sometimes called on an instruction that's not yet complete, and
1067 // so the number of operands is less than the MCID indicates. In
1068 // particular, the PTX target does this.
1069 const MCInstrDesc &MCID = getDesc();
1070 if (MCID.isPredicable()) {
1071 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1072 if (MCID.OpInfo[i].isPredicate())
1073 return i;
1074 }
1075
1076 return -1;
1077}
1078
1079// MachineOperand::TiedTo is 4 bits wide.
1080const unsigned TiedMax = 15;
1081
1082/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1083///
1084/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1085/// field. TiedTo can have these values:
1086///
1087/// 0: Operand is not tied to anything.
1088/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1089/// TiedMax: Tied to an operand >= TiedMax-1.
1090///
1091/// The tied def must be one of the first TiedMax operands on a normal
1092/// instruction. INLINEASM instructions allow more tied defs.
1093///
1094void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1095 MachineOperand &DefMO = getOperand(DefIdx);
1096 MachineOperand &UseMO = getOperand(UseIdx);
1097 assert(DefMO.isDef() && "DefIdx must be a def operand")(static_cast <bool> (DefMO.isDef() && "DefIdx must be a def operand"
) ? void (0) : __assert_fail ("DefMO.isDef() && \"DefIdx must be a def operand\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1097, __extension__ __PRETTY_FUNCTION__
))
;
1098 assert(UseMO.isUse() && "UseIdx must be a use operand")(static_cast <bool> (UseMO.isUse() && "UseIdx must be a use operand"
) ? void (0) : __assert_fail ("UseMO.isUse() && \"UseIdx must be a use operand\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1098, __extension__ __PRETTY_FUNCTION__
))
;
1099 assert(!DefMO.isTied() && "Def is already tied to another use")(static_cast <bool> (!DefMO.isTied() && "Def is already tied to another use"
) ? void (0) : __assert_fail ("!DefMO.isTied() && \"Def is already tied to another use\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1099, __extension__ __PRETTY_FUNCTION__
))
;
1100 assert(!UseMO.isTied() && "Use is already tied to another def")(static_cast <bool> (!UseMO.isTied() && "Use is already tied to another def"
) ? void (0) : __assert_fail ("!UseMO.isTied() && \"Use is already tied to another def\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1100, __extension__ __PRETTY_FUNCTION__
))
;
1101
1102 if (DefIdx < TiedMax)
1103 UseMO.TiedTo = DefIdx + 1;
1104 else {
1105 // Inline asm can use the group descriptors to find tied operands,
1106 // statepoint tied operands are trivial to match (1-1 reg def with reg use),
1107 // but on normal instruction, the tied def must be within the first TiedMax
1108 // operands.
1109 assert((isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) &&(static_cast <bool> ((isInlineAsm() || getOpcode() == TargetOpcode
::STATEPOINT) && "DefIdx out of range") ? void (0) : __assert_fail
("(isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) && \"DefIdx out of range\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1110, __extension__ __PRETTY_FUNCTION__
))
1110 "DefIdx out of range")(static_cast <bool> ((isInlineAsm() || getOpcode() == TargetOpcode
::STATEPOINT) && "DefIdx out of range") ? void (0) : __assert_fail
("(isInlineAsm() || getOpcode() == TargetOpcode::STATEPOINT) && \"DefIdx out of range\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1110, __extension__ __PRETTY_FUNCTION__
))
;
1111 UseMO.TiedTo = TiedMax;
1112 }
1113
1114 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1115 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1116}
1117
1118/// Given the index of a tied register operand, find the operand it is tied to.
1119/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1120/// which must exist.
1121unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1122 const MachineOperand &MO = getOperand(OpIdx);
1123 assert(MO.isTied() && "Operand isn't tied")(static_cast <bool> (MO.isTied() && "Operand isn't tied"
) ? void (0) : __assert_fail ("MO.isTied() && \"Operand isn't tied\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1123, __extension__ __PRETTY_FUNCTION__
))
;
1124
1125 // Normally TiedTo is in range.
1126 if (MO.TiedTo < TiedMax)
1127 return MO.TiedTo - 1;
1128
1129 // Uses on normal instructions can be out of range.
1130 if (!isInlineAsm() && getOpcode() != TargetOpcode::STATEPOINT) {
1131 // Normal tied defs must be in the 0..TiedMax-1 range.
1132 if (MO.isUse())
1133 return TiedMax - 1;
1134 // MO is a def. Search for the tied use.
1135 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1136 const MachineOperand &UseMO = getOperand(i);
1137 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1138 return i;
1139 }
1140 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "llvm/lib/CodeGen/MachineInstr.cpp"
, 1140)
;
1141 }
1142
1143 if (getOpcode() == TargetOpcode::STATEPOINT) {
1144 // In STATEPOINT defs correspond 1-1 to GC pointer operands passed
1145 // on registers.
1146 StatepointOpers SO(this);
1147 unsigned CurUseIdx = SO.getFirstGCPtrIdx();
1148 assert(CurUseIdx != -1U && "only gc pointer statepoint operands can be tied")(static_cast <bool> (CurUseIdx != -1U && "only gc pointer statepoint operands can be tied"
) ? void (0) : __assert_fail ("CurUseIdx != -1U && \"only gc pointer statepoint operands can be tied\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1148, __extension__ __PRETTY_FUNCTION__
))
;
1149 unsigned NumDefs = getNumDefs();
1150 for (unsigned CurDefIdx = 0; CurDefIdx < NumDefs; ++CurDefIdx) {
1151 while (!getOperand(CurUseIdx).isReg())
1152 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1153 if (OpIdx == CurDefIdx)
1154 return CurUseIdx;
1155 if (OpIdx == CurUseIdx)
1156 return CurDefIdx;
1157 CurUseIdx = StackMaps::getNextMetaArgIdx(this, CurUseIdx);
1158 }
1159 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "llvm/lib/CodeGen/MachineInstr.cpp"
, 1159)
;
1160 }
1161
1162 // Now deal with inline asm by parsing the operand group descriptor flags.
1163 // Find the beginning of each operand group.
1164 SmallVector<unsigned, 8> GroupIdx;
1165 unsigned OpIdxGroup = ~0u;
1166 unsigned NumOps;
1167 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1168 i += NumOps) {
1169 const MachineOperand &FlagMO = getOperand(i);
1170 assert(FlagMO.isImm() && "Invalid tied operand on inline asm")(static_cast <bool> (FlagMO.isImm() && "Invalid tied operand on inline asm"
) ? void (0) : __assert_fail ("FlagMO.isImm() && \"Invalid tied operand on inline asm\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1170, __extension__ __PRETTY_FUNCTION__
))
;
1171 unsigned CurGroup = GroupIdx.size();
1172 GroupIdx.push_back(i);
1173 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1174 // OpIdx belongs to this operand group.
1175 if (OpIdx > i && OpIdx < i + NumOps)
1176 OpIdxGroup = CurGroup;
1177 unsigned TiedGroup;
1178 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1179 continue;
1180 // Operands in this group are tied to operands in TiedGroup which must be
1181 // earlier. Find the number of operands between the two groups.
1182 unsigned Delta = i - GroupIdx[TiedGroup];
1183
1184 // OpIdx is a use tied to TiedGroup.
1185 if (OpIdxGroup == CurGroup)
1186 return OpIdx - Delta;
1187
1188 // OpIdx is a def tied to this use group.
1189 if (OpIdxGroup == TiedGroup)
1190 return OpIdx + Delta;
1191 }
1192 llvm_unreachable("Invalid tied operand on inline asm")::llvm::llvm_unreachable_internal("Invalid tied operand on inline asm"
, "llvm/lib/CodeGen/MachineInstr.cpp", 1192)
;
1193}
1194
1195/// clearKillInfo - Clears kill flags on all operands.
1196///
1197void MachineInstr::clearKillInfo() {
1198 for (MachineOperand &MO : operands()) {
1199 if (MO.isReg() && MO.isUse())
1200 MO.setIsKill(false);
1201 }
1202}
1203
1204void MachineInstr::substituteRegister(Register FromReg, Register ToReg,
1205 unsigned SubIdx,
1206 const TargetRegisterInfo &RegInfo) {
1207 if (Register::isPhysicalRegister(ToReg)) {
1208 if (SubIdx)
1209 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1210 for (MachineOperand &MO : operands()) {
1211 if (!MO.isReg() || MO.getReg() != FromReg)
1212 continue;
1213 MO.substPhysReg(ToReg, RegInfo);
1214 }
1215 } else {
1216 for (MachineOperand &MO : operands()) {
1217 if (!MO.isReg() || MO.getReg() != FromReg)
1218 continue;
1219 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1220 }
1221 }
1222}
1223
1224/// isSafeToMove - Return true if it is safe to move this instruction. If
1225/// SawStore is set to true, it means that there is a store (or call) between
1226/// the instruction's location and its intended destination.
1227bool MachineInstr::isSafeToMove(AAResults *AA, bool &SawStore) const {
1228 // Ignore stuff that we obviously can't move.
1229 //
1230 // Treat volatile loads as stores. This is not strictly necessary for
1231 // volatiles, but it is required for atomic loads. It is not allowed to move
1232 // a load across an atomic load with Ordering > Monotonic.
1233 if (mayStore() || isCall() || isPHI() ||
1234 (mayLoad() && hasOrderedMemoryRef())) {
1235 SawStore = true;
1236 return false;
1237 }
1238
1239 if (isPosition() || isDebugInstr() || isTerminator() ||
1240 mayRaiseFPException() || hasUnmodeledSideEffects())
1241 return false;
1242
1243 // See if this instruction does a load. If so, we have to guarantee that the
1244 // loaded value doesn't change between the load and the its intended
1245 // destination. The check for isInvariantLoad gives the target the chance to
1246 // classify the load as always returning a constant, e.g. a constant pool
1247 // load.
1248 if (mayLoad() && !isDereferenceableInvariantLoad())
1249 // Otherwise, this is a real load. If there is a store between the load and
1250 // end of block, we can't move it.
1251 return !SawStore;
1252
1253 return true;
1254}
1255
1256static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
1257 bool UseTBAA, const MachineMemOperand *MMOa,
1258 const MachineMemOperand *MMOb) {
1259 // The following interface to AA is fashioned after DAGCombiner::isAlias and
1260 // operates with MachineMemOperand offset with some important assumptions:
1261 // - LLVM fundamentally assumes flat address spaces.
1262 // - MachineOperand offset can *only* result from legalization and cannot
1263 // affect queries other than the trivial case of overlap checking.
1264 // - These offsets never wrap and never step outside of allocated objects.
1265 // - There should never be any negative offsets here.
1266 //
1267 // FIXME: Modify API to hide this math from "user"
1268 // Even before we go to AA we can reason locally about some memory objects. It
1269 // can save compile time, and possibly catch some corner cases not currently
1270 // covered.
1271
1272 int64_t OffsetA = MMOa->getOffset();
1273 int64_t OffsetB = MMOb->getOffset();
1274 int64_t MinOffset = std::min(OffsetA, OffsetB);
1275
1276 uint64_t WidthA = MMOa->getSize();
1277 uint64_t WidthB = MMOb->getSize();
1278 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1279 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1280
1281 const Value *ValA = MMOa->getValue();
1282 const Value *ValB = MMOb->getValue();
1283 bool SameVal = (ValA && ValB && (ValA == ValB));
1284 if (!SameVal) {
1285 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1286 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1287 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1288 return false;
1289 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1290 return false;
1291 if (PSVa && PSVb && (PSVa == PSVb))
1292 SameVal = true;
1293 }
1294
1295 if (SameVal) {
1296 if (!KnownWidthA || !KnownWidthB)
1297 return true;
1298 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1299 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1300 return (MinOffset + LowWidth > MaxOffset);
1301 }
1302
1303 if (!AA)
1304 return true;
1305
1306 if (!ValA || !ValB)
1307 return true;
1308
1309 assert((OffsetA >= 0) && "Negative MachineMemOperand offset")(static_cast <bool> ((OffsetA >= 0) && "Negative MachineMemOperand offset"
) ? void (0) : __assert_fail ("(OffsetA >= 0) && \"Negative MachineMemOperand offset\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1309, __extension__ __PRETTY_FUNCTION__
))
;
1310 assert((OffsetB >= 0) && "Negative MachineMemOperand offset")(static_cast <bool> ((OffsetB >= 0) && "Negative MachineMemOperand offset"
) ? void (0) : __assert_fail ("(OffsetB >= 0) && \"Negative MachineMemOperand offset\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1310, __extension__ __PRETTY_FUNCTION__
))
;
1311
1312 int64_t OverlapA =
1313 KnownWidthA ? WidthA + OffsetA - MinOffset : MemoryLocation::UnknownSize;
1314 int64_t OverlapB =
1315 KnownWidthB ? WidthB + OffsetB - MinOffset : MemoryLocation::UnknownSize;
1316
1317 return !AA->isNoAlias(
1318 MemoryLocation(ValA, OverlapA, UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1319 MemoryLocation(ValB, OverlapB,
1320 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1321}
1322
1323bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1324 bool UseTBAA) const {
1325 const MachineFunction *MF = getMF();
1326 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1327 const MachineFrameInfo &MFI = MF->getFrameInfo();
1328
1329 // Exclude call instruction which may alter the memory but can not be handled
1330 // by this function.
1331 if (isCall() || Other.isCall())
1332 return true;
1333
1334 // If neither instruction stores to memory, they can't alias in any
1335 // meaningful way, even if they read from the same address.
1336 if (!mayStore() && !Other.mayStore())
1337 return false;
1338
1339 // Both instructions must be memory operations to be able to alias.
1340 if (!mayLoadOrStore() || !Other.mayLoadOrStore())
1341 return false;
1342
1343 // Let the target decide if memory accesses cannot possibly overlap.
1344 if (TII->areMemAccessesTriviallyDisjoint(*this, Other))
1345 return false;
1346
1347 // Memory operations without memory operands may access anything. Be
1348 // conservative and assume `MayAlias`.
1349 if (memoperands_empty() || Other.memoperands_empty())
1350 return true;
1351
1352 // Skip if there are too many memory operands.
1353 auto NumChecks = getNumMemOperands() * Other.getNumMemOperands();
1354 if (NumChecks > TII->getMemOperandAACheckLimit())
1355 return true;
1356
1357 // Check each pair of memory operands from both instructions, which can't
1358 // alias only if all pairs won't alias.
1359 for (auto *MMOa : memoperands())
1360 for (auto *MMOb : Other.memoperands())
1361 if (MemOperandsHaveAlias(MFI, AA, UseTBAA, MMOa, MMOb))
1362 return true;
1363
1364 return false;
1365}
1366
1367/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1368/// or volatile memory reference, or if the information describing the memory
1369/// reference is not available. Return false if it is known to have no ordered
1370/// memory references.
1371bool MachineInstr::hasOrderedMemoryRef() const {
1372 // An instruction known never to access memory won't have a volatile access.
1373 if (!mayStore() &&
1374 !mayLoad() &&
1375 !isCall() &&
1376 !hasUnmodeledSideEffects())
1377 return false;
1378
1379 // Otherwise, if the instruction has no memory reference information,
1380 // conservatively assume it wasn't preserved.
1381 if (memoperands_empty())
1382 return true;
1383
1384 // Check if any of our memory operands are ordered.
1385 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1386 return !MMO->isUnordered();
1387 });
1388}
1389
1390/// isDereferenceableInvariantLoad - Return true if this instruction will never
1391/// trap and is loading from a location whose value is invariant across a run of
1392/// this function.
1393bool MachineInstr::isDereferenceableInvariantLoad() const {
1394 // If the instruction doesn't load at all, it isn't an invariant load.
1395 if (!mayLoad())
1396 return false;
1397
1398 // If the instruction has lost its memoperands, conservatively assume that
1399 // it may not be an invariant load.
1400 if (memoperands_empty())
1401 return false;
1402
1403 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1404
1405 for (MachineMemOperand *MMO : memoperands()) {
1406 if (!MMO->isUnordered())
1407 // If the memory operand has ordering side effects, we can't move the
1408 // instruction. Such an instruction is technically an invariant load,
1409 // but the caller code would need updated to expect that.
1410 return false;
1411 if (MMO->isStore()) return false;
1412 if (MMO->isInvariant() && MMO->isDereferenceable())
1413 continue;
1414
1415 // A load from a constant PseudoSourceValue is invariant.
1416 if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) {
1417 if (PSV->isConstant(&MFI))
1418 continue;
1419 }
1420
1421 // Otherwise assume conservatively.
1422 return false;
1423 }
1424
1425 // Everything checks out.
1426 return true;
1427}
1428
1429/// isConstantValuePHI - If the specified instruction is a PHI that always
1430/// merges together the same virtual register, return the register, otherwise
1431/// return 0.
1432unsigned MachineInstr::isConstantValuePHI() const {
1433 if (!isPHI())
1434 return 0;
1435 assert(getNumOperands() >= 3 &&(static_cast <bool> (getNumOperands() >= 3 &&
"It's illegal to have a PHI without source operands") ? void
(0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1436, __extension__ __PRETTY_FUNCTION__
))
1436 "It's illegal to have a PHI without source operands")(static_cast <bool> (getNumOperands() >= 3 &&
"It's illegal to have a PHI without source operands") ? void
(0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1436, __extension__ __PRETTY_FUNCTION__
))
;
1437
1438 Register Reg = getOperand(1).getReg();
1439 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1440 if (getOperand(i).getReg() != Reg)
1441 return 0;
1442 return Reg;
1443}
1444
1445bool MachineInstr::hasUnmodeledSideEffects() const {
1446 if (hasProperty(MCID::UnmodeledSideEffects))
1447 return true;
1448 if (isInlineAsm()) {
1449 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1450 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1451 return true;
1452 }
1453
1454 return false;
1455}
1456
1457bool MachineInstr::isLoadFoldBarrier() const {
1458 return mayStore() || isCall() ||
1459 (hasUnmodeledSideEffects() && !isPseudoProbe());
1460}
1461
1462/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1463///
1464bool MachineInstr::allDefsAreDead() const {
1465 for (const MachineOperand &MO : operands()) {
1466 if (!MO.isReg() || MO.isUse())
1467 continue;
1468 if (!MO.isDead())
1469 return false;
1470 }
1471 return true;
1472}
1473
1474/// copyImplicitOps - Copy implicit register operands from specified
1475/// instruction to this instruction.
1476void MachineInstr::copyImplicitOps(MachineFunction &MF,
1477 const MachineInstr &MI) {
1478 for (const MachineOperand &MO :
1479 llvm::drop_begin(MI.operands(), MI.getDesc().getNumOperands()))
1480 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1481 addOperand(MF, MO);
1482}
1483
1484bool MachineInstr::hasComplexRegisterTies() const {
1485 const MCInstrDesc &MCID = getDesc();
1486 if (MCID.Opcode == TargetOpcode::STATEPOINT)
1487 return true;
1488 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1489 const auto &Operand = getOperand(I);
1490 if (!Operand.isReg() || Operand.isDef())
1491 // Ignore the defined registers as MCID marks only the uses as tied.
1492 continue;
1493 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1494 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1495 if (ExpectedTiedIdx != TiedIdx)
1496 return true;
1497 }
1498 return false;
1499}
1500
1501LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1502 const MachineRegisterInfo &MRI) const {
1503 const MachineOperand &Op = getOperand(OpIdx);
1504 if (!Op.isReg())
1505 return LLT{};
1506
1507 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1508 return MRI.getType(Op.getReg());
1509
1510 auto &OpInfo = getDesc().OpInfo[OpIdx];
1511 if (!OpInfo.isGenericType())
1512 return MRI.getType(Op.getReg());
1513
1514 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1515 return LLT{};
1516
1517 LLT TypeToPrint = MRI.getType(Op.getReg());
1518 // Don't mark the type index printed if it wasn't actually printed: maybe
1519 // another operand with the same type index has an actual type attached:
1520 if (TypeToPrint.isValid())
1521 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1522 return TypeToPrint;
1523}
1524
1525#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1526LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dump() const {
1527 dbgs() << " ";
1528 print(dbgs());
1529}
1530
1531LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dumprImpl(
1532 const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
1533 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const {
1534 if (Depth >= MaxDepth)
1535 return;
1536 if (!AlreadySeenInstrs.insert(this).second)
1537 return;
1538 // PadToColumn always inserts at least one space.
1539 // Don't mess up the alignment if we don't want any space.
1540 if (Depth)
1541 fdbgs().PadToColumn(Depth * 2);
1542 print(fdbgs());
1543 for (const MachineOperand &MO : operands()) {
1544 if (!MO.isReg() || MO.isDef())
1545 continue;
1546 Register Reg = MO.getReg();
1547 if (Reg.isPhysical())
1548 continue;
1549 const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg);
1550 if (NewMI == nullptr)
1551 continue;
1552 NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs);
1553 }
1554}
1555
1556LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dumpr(const MachineRegisterInfo &MRI,
1557 unsigned MaxDepth) const {
1558 SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs;
1559 dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs);
1560}
1561#endif
1562
1563void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1564 bool SkipDebugLoc, bool AddNewLine,
1565 const TargetInstrInfo *TII) const {
1566 const Module *M = nullptr;
1567 const Function *F = nullptr;
1568 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1569 F = &MF->getFunction();
1570 M = F->getParent();
1571 if (!TII)
1572 TII = MF->getSubtarget().getInstrInfo();
1573 }
1574
1575 ModuleSlotTracker MST(M);
1576 if (F)
1577 MST.incorporateFunction(*F);
1578 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII);
1579}
1580
1581void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1582 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1583 bool AddNewLine, const TargetInstrInfo *TII) const {
1584 // We can be a bit tidier if we know the MachineFunction.
1585 const TargetRegisterInfo *TRI = nullptr;
1586 const MachineRegisterInfo *MRI = nullptr;
1587 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1588 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1589
1590 if (isCFIInstruction())
1591 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")(static_cast <bool> (getNumOperands() == 1 && "Expected 1 operand in CFI instruction"
) ? void (0) : __assert_fail ("getNumOperands() == 1 && \"Expected 1 operand in CFI instruction\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 1591, __extension__ __PRETTY_FUNCTION__
))
;
1592
1593 SmallBitVector PrintedTypes(8);
1594 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1595 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1596 if (!ShouldPrintRegisterTies)
1597 return 0U;
1598 const MachineOperand &MO = getOperand(OpIdx);
1599 if (MO.isReg() && MO.isTied() && !MO.isDef())
1600 return findTiedOperandIdx(OpIdx);
1601 return 0U;
1602 };
1603 unsigned StartOp = 0;
1604 unsigned e = getNumOperands();
1605
1606 // Print explicitly defined operands on the left of an assignment syntax.
1607 while (StartOp < e) {
1608 const MachineOperand &MO = getOperand(StartOp);
1609 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1610 break;
1611
1612 if (StartOp != 0)
1613 OS << ", ";
1614
1615 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1616 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1617 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone,
1618 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1619 ++StartOp;
1620 }
1621
1622 if (StartOp != 0)
1623 OS << " = ";
1624
1625 if (getFlag(MachineInstr::FrameSetup))
1626 OS << "frame-setup ";
1627 if (getFlag(MachineInstr::FrameDestroy))
1628 OS << "frame-destroy ";
1629 if (getFlag(MachineInstr::FmNoNans))
1630 OS << "nnan ";
1631 if (getFlag(MachineInstr::FmNoInfs))
1632 OS << "ninf ";
1633 if (getFlag(MachineInstr::FmNsz))
1634 OS << "nsz ";
1635 if (getFlag(MachineInstr::FmArcp))
1636 OS << "arcp ";
1637 if (getFlag(MachineInstr::FmContract))
1638 OS << "contract ";
1639 if (getFlag(MachineInstr::FmAfn))
1640 OS << "afn ";
1641 if (getFlag(MachineInstr::FmReassoc))
1642 OS << "reassoc ";
1643 if (getFlag(MachineInstr::NoUWrap))
1644 OS << "nuw ";
1645 if (getFlag(MachineInstr::NoSWrap))
1646 OS << "nsw ";
1647 if (getFlag(MachineInstr::IsExact))
1648 OS << "exact ";
1649 if (getFlag(MachineInstr::NoFPExcept))
1650 OS << "nofpexcept ";
1651 if (getFlag(MachineInstr::NoMerge))
1652 OS << "nomerge ";
1653
1654 // Print the opcode name.
1655 if (TII)
1656 OS << TII->getName(getOpcode());
1657 else
1658 OS << "UNKNOWN";
1659
1660 if (SkipOpers)
1661 return;
1662
1663 // Print the rest of the operands.
1664 bool FirstOp = true;
1665 unsigned AsmDescOp = ~0u;
1666 unsigned AsmOpCount = 0;
1667
1668 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1669 // Print asm string.
1670 OS << " ";
1671 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1672 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1673 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1674 getOperand(OpIdx).print(OS, MST, TypeToPrint, OpIdx, /*PrintDef=*/true, IsStandalone,
1675 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1676 IntrinsicInfo);
1677
1678 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1679 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1680 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1681 OS << " [sideeffect]";
1682 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1683 OS << " [mayload]";
1684 if (ExtraInfo & InlineAsm::Extra_MayStore)
1685 OS << " [maystore]";
1686 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1687 OS << " [isconvergent]";
1688 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1689 OS << " [alignstack]";
1690 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1691 OS << " [attdialect]";
1692 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1693 OS << " [inteldialect]";
1694
1695 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1696 FirstOp = false;
1697 }
1698
1699 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1700 const MachineOperand &MO = getOperand(i);
1701
1702 if (FirstOp) FirstOp = false; else OS << ",";
1703 OS << " ";
1704
1705 if (isDebugValue() && MO.isMetadata()) {
1706 // Pretty print DBG_VALUE* instructions.
1707 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1708 if (DIV && !DIV->getName().empty())
1709 OS << "!\"" << DIV->getName() << '\"';
1710 else {
1711 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1712 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1713 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1714 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1715 }
1716 } else if (isDebugLabel() && MO.isMetadata()) {
1717 // Pretty print DBG_LABEL instructions.
1718 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1719 if (DIL && !DIL->getName().empty())
1720 OS << "\"" << DIL->getName() << '\"';
1721 else {
1722 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1723 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1724 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1725 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1726 }
1727 } else if (i == AsmDescOp && MO.isImm()) {
1728 // Pretty print the inline asm operand descriptor.
1729 OS << '$' << AsmOpCount++;
1730 unsigned Flag = MO.getImm();
1731 OS << ":[";
1732 OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
1733
1734 unsigned RCID = 0;
1735 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1736 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1737 if (TRI) {
1738 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1739 } else
1740 OS << ":RC" << RCID;
1741 }
1742
1743 if (InlineAsm::isMemKind(Flag)) {
1744 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1745 OS << ":" << InlineAsm::getMemConstraintName(MCID);
1746 }
1747
1748 unsigned TiedTo = 0;
1749 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1750 OS << " tiedto:$" << TiedTo;
1751
1752 OS << ']';
1753
1754 // Compute the index of the next operand descriptor.
1755 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1756 } else {
1757 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1758 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1759 if (MO.isImm() && isOperandSubregIdx(i))
1760 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1761 else
1762 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone,
1763 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1764 }
1765 }
1766
1767 // Print any optional symbols attached to this instruction as-if they were
1768 // operands.
1769 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1770 if (!FirstOp) {
1771 FirstOp = false;
1772 OS << ',';
1773 }
1774 OS << " pre-instr-symbol ";
1775 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1776 }
1777 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1778 if (!FirstOp) {
1779 FirstOp = false;
1780 OS << ',';
1781 }
1782 OS << " post-instr-symbol ";
1783 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1784 }
1785 if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
1786 if (!FirstOp) {
1787 FirstOp = false;
1788 OS << ',';
1789 }
1790 OS << " heap-alloc-marker ";
1791 HeapAllocMarker->printAsOperand(OS, MST);
1792 }
1793 if (MDNode *PCSections = getPCSections()) {
1794 if (!FirstOp) {
1795 FirstOp = false;
1796 OS << ',';
1797 }
1798 OS << " pcsections ";
1799 PCSections->printAsOperand(OS, MST);
1800 }
1801 if (uint32_t CFIType = getCFIType()) {
1802 if (!FirstOp)
1803 OS << ',';
1804 OS << " cfi-type " << CFIType;
1805 }
1806
1807 if (DebugInstrNum) {
1808 if (!FirstOp)
1809 OS << ",";
1810 OS << " debug-instr-number " << DebugInstrNum;
1811 }
1812
1813 if (!SkipDebugLoc) {
1814 if (const DebugLoc &DL = getDebugLoc()) {
1815 if (!FirstOp)
1816 OS << ',';
1817 OS << " debug-location ";
1818 DL->printAsOperand(OS, MST);
1819 }
1820 }
1821
1822 if (!memoperands_empty()) {
1823 SmallVector<StringRef, 0> SSNs;
1824 const LLVMContext *Context = nullptr;
1825 std::unique_ptr<LLVMContext> CtxPtr;
1826 const MachineFrameInfo *MFI = nullptr;
1827 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1828 MFI = &MF->getFrameInfo();
1829 Context = &MF->getFunction().getContext();
1830 } else {
1831 CtxPtr = std::make_unique<LLVMContext>();
1832 Context = CtxPtr.get();
1833 }
1834
1835 OS << " :: ";
1836 bool NeedComma = false;
1837 for (const MachineMemOperand *Op : memoperands()) {
1838 if (NeedComma)
1839 OS << ", ";
1840 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1841 NeedComma = true;
1842 }
1843 }
1844
1845 if (SkipDebugLoc)
1846 return;
1847
1848 bool HaveSemi = false;
1849
1850 // Print debug location information.
1851 if (const DebugLoc &DL = getDebugLoc()) {
1852 if (!HaveSemi) {
1853 OS << ';';
1854 HaveSemi = true;
1855 }
1856 OS << ' ';
1857 DL.print(OS);
1858 }
1859
1860 // Print extra comments for DEBUG_VALUE.
1861 if (isDebugValue() && getDebugVariableOp().isMetadata()) {
1862 if (!HaveSemi) {
1863 OS << ";";
1864 HaveSemi = true;
Value stored to 'HaveSemi' is never read
1865 }
1866 auto *DV = getDebugVariable();
1867 OS << " line no:" << DV->getLine();
1868 if (isIndirectDebugValue())
1869 OS << " indirect";
1870 }
1871 // TODO: DBG_LABEL
1872
1873 if (AddNewLine)
1874 OS << '\n';
1875}
1876
1877bool MachineInstr::addRegisterKilled(Register IncomingReg,
1878 const TargetRegisterInfo *RegInfo,
1879 bool AddIfNotFound) {
1880 bool isPhysReg = Register::isPhysicalRegister(IncomingReg);
1881 bool hasAliases = isPhysReg &&
1882 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1883 bool Found = false;
1884 SmallVector<unsigned,4> DeadOps;
1885 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1886 MachineOperand &MO = getOperand(i);
1887 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1888 continue;
1889
1890 // DEBUG_VALUE nodes do not contribute to code generation and should
1891 // always be ignored. Failure to do so may result in trying to modify
1892 // KILL flags on DEBUG_VALUE nodes.
1893 if (MO.isDebug())
1894 continue;
1895
1896 Register Reg = MO.getReg();
1897 if (!Reg)
1898 continue;
1899
1900 if (Reg == IncomingReg) {
1901 if (!Found) {
1902 if (MO.isKill())
1903 // The register is already marked kill.
1904 return true;
1905 if (isPhysReg && isRegTiedToDefOperand(i))
1906 // Two-address uses of physregs must not be marked kill.
1907 return true;
1908 MO.setIsKill();
1909 Found = true;
1910 }
1911 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) {
1912 // A super-register kill already exists.
1913 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1914 return true;
1915 if (RegInfo->isSubRegister(IncomingReg, Reg))
1916 DeadOps.push_back(i);
1917 }
1918 }
1919
1920 // Trim unneeded kill operands.
1921 while (!DeadOps.empty()) {
1922 unsigned OpIdx = DeadOps.back();
1923 if (getOperand(OpIdx).isImplicit() &&
1924 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1925 removeOperand(OpIdx);
1926 else
1927 getOperand(OpIdx).setIsKill(false);
1928 DeadOps.pop_back();
1929 }
1930
1931 // If not found, this means an alias of one of the operands is killed. Add a
1932 // new implicit operand if required.
1933 if (!Found && AddIfNotFound) {
1934 addOperand(MachineOperand::CreateReg(IncomingReg,
1935 false /*IsDef*/,
1936 true /*IsImp*/,
1937 true /*IsKill*/));
1938 return true;
1939 }
1940 return Found;
1941}
1942
1943void MachineInstr::clearRegisterKills(Register Reg,
1944 const TargetRegisterInfo *RegInfo) {
1945 if (!Register::isPhysicalRegister(Reg))
1946 RegInfo = nullptr;
1947 for (MachineOperand &MO : operands()) {
1948 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1949 continue;
1950 Register OpReg = MO.getReg();
1951 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1952 MO.setIsKill(false);
1953 }
1954}
1955
1956bool MachineInstr::addRegisterDead(Register Reg,
1957 const TargetRegisterInfo *RegInfo,
1958 bool AddIfNotFound) {
1959 bool isPhysReg = Register::isPhysicalRegister(Reg);
1960 bool hasAliases = isPhysReg &&
1961 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1962 bool Found = false;
1963 SmallVector<unsigned,4> DeadOps;
1964 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1965 MachineOperand &MO = getOperand(i);
1966 if (!MO.isReg() || !MO.isDef())
1967 continue;
1968 Register MOReg = MO.getReg();
1969 if (!MOReg)
1970 continue;
1971
1972 if (MOReg == Reg) {
1973 MO.setIsDead();
1974 Found = true;
1975 } else if (hasAliases && MO.isDead() &&
1976 Register::isPhysicalRegister(MOReg)) {
1977 // There exists a super-register that's marked dead.
1978 if (RegInfo->isSuperRegister(Reg, MOReg))
1979 return true;
1980 if (RegInfo->isSubRegister(Reg, MOReg))
1981 DeadOps.push_back(i);
1982 }
1983 }
1984
1985 // Trim unneeded dead operands.
1986 while (!DeadOps.empty()) {
1987 unsigned OpIdx = DeadOps.back();
1988 if (getOperand(OpIdx).isImplicit() &&
1989 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1990 removeOperand(OpIdx);
1991 else
1992 getOperand(OpIdx).setIsDead(false);
1993 DeadOps.pop_back();
1994 }
1995
1996 // If not found, this means an alias of one of the operands is dead. Add a
1997 // new implicit operand if required.
1998 if (Found || !AddIfNotFound)
1999 return Found;
2000
2001 addOperand(MachineOperand::CreateReg(Reg,
2002 true /*IsDef*/,
2003 true /*IsImp*/,
2004 false /*IsKill*/,
2005 true /*IsDead*/));
2006 return true;
2007}
2008
2009void MachineInstr::clearRegisterDeads(Register Reg) {
2010 for (MachineOperand &MO : operands()) {
2011 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
2012 continue;
2013 MO.setIsDead(false);
2014 }
2015}
2016
2017void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) {
2018 for (MachineOperand &MO : operands()) {
2019 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
2020 continue;
2021 MO.setIsUndef(IsUndef);
2022 }
2023}
2024
2025void MachineInstr::addRegisterDefined(Register Reg,
2026 const TargetRegisterInfo *RegInfo) {
2027 if (Register::isPhysicalRegister(Reg)) {
2028 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo);
2029 if (MO)
2030 return;
2031 } else {
2032 for (const MachineOperand &MO : operands()) {
2033 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
2034 MO.getSubReg() == 0)
2035 return;
2036 }
2037 }
2038 addOperand(MachineOperand::CreateReg(Reg,
2039 true /*IsDef*/,
2040 true /*IsImp*/));
2041}
2042
2043void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
2044 const TargetRegisterInfo &TRI) {
2045 bool HasRegMask = false;
2046 for (MachineOperand &MO : operands()) {
2047 if (MO.isRegMask()) {
2048 HasRegMask = true;
2049 continue;
2050 }
2051 if (!MO.isReg() || !MO.isDef()) continue;
2052 Register Reg = MO.getReg();
2053 if (!Reg.isPhysical())
2054 continue;
2055 // If there are no uses, including partial uses, the def is dead.
2056 if (llvm::none_of(UsedRegs,
2057 [&](MCRegister Use) { return TRI.regsOverlap(Use, Reg); }))
2058 MO.setIsDead();
2059 }
2060
2061 // This is a call with a register mask operand.
2062 // Mask clobbers are always dead, so add defs for the non-dead defines.
2063 if (HasRegMask)
2064 for (const Register &UsedReg : UsedRegs)
2065 addRegisterDefined(UsedReg, &TRI);
2066}
2067
2068unsigned
2069MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
2070 // Build up a buffer of hash code components.
2071 SmallVector<size_t, 16> HashComponents;
2072 HashComponents.reserve(MI->getNumOperands() + 1);
2073 HashComponents.push_back(MI->getOpcode());
2074 for (const MachineOperand &MO : MI->operands()) {
2075 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2076 continue; // Skip virtual register defs.
2077
2078 HashComponents.push_back(hash_value(MO));
2079 }
2080 return hash_combine_range(HashComponents.begin(), HashComponents.end());
2081}
2082
2083void MachineInstr::emitError(StringRef Msg) const {
2084 // Find the source location cookie.
2085 uint64_t LocCookie = 0;
2086 const MDNode *LocMD = nullptr;
2087 for (unsigned i = getNumOperands(); i != 0; --i) {
2088 if (getOperand(i-1).isMetadata() &&
2089 (LocMD = getOperand(i-1).getMetadata()) &&
2090 LocMD->getNumOperands() != 0) {
2091 if (const ConstantInt *CI =
2092 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
2093 LocCookie = CI->getZExtValue();
2094 break;
2095 }
2096 }
2097 }
2098
2099 if (const MachineBasicBlock *MBB = getParent())
2100 if (const MachineFunction *MF = MBB->getParent())
2101 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
2102 report_fatal_error(Msg);
2103}
2104
2105MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2106 const MCInstrDesc &MCID, bool IsIndirect,
2107 Register Reg, const MDNode *Variable,
2108 const MDNode *Expr) {
2109 assert(isa<DILocalVariable>(Variable) && "not a variable")(static_cast <bool> (isa<DILocalVariable>(Variable
) && "not a variable") ? void (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2109, __extension__ __PRETTY_FUNCTION__
))
;
2110 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")(static_cast <bool> (cast<DIExpression>(Expr)->
isValid() && "not an expression") ? void (0) : __assert_fail
("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2110, __extension__ __PRETTY_FUNCTION__
))
;
2111 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2112, __extension__ __PRETTY_FUNCTION__
))
2112 "Expected inlined-at fields to agree")(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2112, __extension__ __PRETTY_FUNCTION__
))
;
2113 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg);
2114 if (IsIndirect)
2115 MIB.addImm(0U);
2116 else
2117 MIB.addReg(0U);
2118 return MIB.addMetadata(Variable).addMetadata(Expr);
2119}
2120
2121MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2122 const MCInstrDesc &MCID, bool IsIndirect,
2123 const MachineOperand &MO,
2124 const MDNode *Variable, const MDNode *Expr) {
2125 assert(isa<DILocalVariable>(Variable) && "not a variable")(static_cast <bool> (isa<DILocalVariable>(Variable
) && "not a variable") ? void (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2125, __extension__ __PRETTY_FUNCTION__
))
;
2126 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")(static_cast <bool> (cast<DIExpression>(Expr)->
isValid() && "not an expression") ? void (0) : __assert_fail
("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2126, __extension__ __PRETTY_FUNCTION__
))
;
2127 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2128, __extension__ __PRETTY_FUNCTION__
))
2128 "Expected inlined-at fields to agree")(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2128, __extension__ __PRETTY_FUNCTION__
))
;
2129 if (MO.isReg())
2130 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2131
2132 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2133 if (IsIndirect)
2134 MIB.addImm(0U);
2135 else
2136 MIB.addReg(0U);
2137 return MIB.addMetadata(Variable).addMetadata(Expr);
2138}
2139
2140MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2141 const MCInstrDesc &MCID, bool IsIndirect,
2142 ArrayRef<MachineOperand> MOs,
2143 const MDNode *Variable, const MDNode *Expr) {
2144 assert(isa<DILocalVariable>(Variable) && "not a variable")(static_cast <bool> (isa<DILocalVariable>(Variable
) && "not a variable") ? void (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2144, __extension__ __PRETTY_FUNCTION__
))
;
2145 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")(static_cast <bool> (cast<DIExpression>(Expr)->
isValid() && "not an expression") ? void (0) : __assert_fail
("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2145, __extension__ __PRETTY_FUNCTION__
))
;
2146 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2147, __extension__ __PRETTY_FUNCTION__
))
2147 "Expected inlined-at fields to agree")(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2147, __extension__ __PRETTY_FUNCTION__
))
;
2148 if (MCID.Opcode == TargetOpcode::DBG_VALUE)
2149 return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
2150
2151 auto MIB = BuildMI(MF, DL, MCID);
2152 MIB.addMetadata(Variable).addMetadata(Expr);
2153 for (const MachineOperand &MO : MOs)
2154 if (MO.isReg())
2155 MIB.addReg(MO.getReg());
2156 else
2157 MIB.add(MO);
2158 return MIB;
2159}
2160
2161MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2162 MachineBasicBlock::iterator I,
2163 const DebugLoc &DL, const MCInstrDesc &MCID,
2164 bool IsIndirect, Register Reg,
2165 const MDNode *Variable, const MDNode *Expr) {
2166 MachineFunction &MF = *BB.getParent();
2167 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2168 BB.insert(I, MI);
2169 return MachineInstrBuilder(MF, MI);
2170}
2171
2172MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2173 MachineBasicBlock::iterator I,
2174 const DebugLoc &DL, const MCInstrDesc &MCID,
2175 bool IsIndirect, MachineOperand &MO,
2176 const MDNode *Variable, const MDNode *Expr) {
2177 MachineFunction &MF = *BB.getParent();
2178 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2179 BB.insert(I, MI);
2180 return MachineInstrBuilder(MF, *MI);
2181}
2182
2183MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2184 MachineBasicBlock::iterator I,
2185 const DebugLoc &DL, const MCInstrDesc &MCID,
2186 bool IsIndirect, ArrayRef<MachineOperand> MOs,
2187 const MDNode *Variable, const MDNode *Expr) {
2188 MachineFunction &MF = *BB.getParent();
2189 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
2190 BB.insert(I, MI);
2191 return MachineInstrBuilder(MF, *MI);
2192}
2193
2194/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2195/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2196static const DIExpression *
2197computeExprForSpill(const MachineInstr &MI,
2198 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2199 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&(static_cast <bool> (MI.getDebugVariable()->isValidLocationForIntrinsic
(MI.getDebugLoc()) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2200, __extension__ __PRETTY_FUNCTION__
))
2200 "Expected inlined-at fields to agree")(static_cast <bool> (MI.getDebugVariable()->isValidLocationForIntrinsic
(MI.getDebugLoc()) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2200, __extension__ __PRETTY_FUNCTION__
))
;
2201
2202 const DIExpression *Expr = MI.getDebugExpression();
2203 if (MI.isIndirectDebugValue()) {
2204 assert(MI.getDebugOffset().getImm() == 0 &&(static_cast <bool> (MI.getDebugOffset().getImm() == 0 &&
"DBG_VALUE with nonzero offset") ? void (0) : __assert_fail (
"MI.getDebugOffset().getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2205, __extension__ __PRETTY_FUNCTION__
))
2205 "DBG_VALUE with nonzero offset")(static_cast <bool> (MI.getDebugOffset().getImm() == 0 &&
"DBG_VALUE with nonzero offset") ? void (0) : __assert_fail (
"MI.getDebugOffset().getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2205, __extension__ __PRETTY_FUNCTION__
))
;
2206 Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore);
2207 } else if (MI.isDebugValueList()) {
2208 // We will replace the spilled register with a frame index, so
2209 // immediately deref all references to the spilled register.
2210 std::array<uint64_t, 1> Ops{{dwarf::DW_OP_deref}};
2211 for (const MachineOperand *Op : SpilledOperands) {
2212 unsigned OpIdx = MI.getDebugOperandIndex(Op);
2213 Expr = DIExpression::appendOpsToArg(Expr, Ops, OpIdx);
2214 }
2215 }
2216 return Expr;
2217}
2218static const DIExpression *computeExprForSpill(const MachineInstr &MI,
2219 Register SpillReg) {
2220 assert(MI.hasDebugOperandForReg(SpillReg) && "Spill Reg is not used in MI.")(static_cast <bool> (MI.hasDebugOperandForReg(SpillReg)
&& "Spill Reg is not used in MI.") ? void (0) : __assert_fail
("MI.hasDebugOperandForReg(SpillReg) && \"Spill Reg is not used in MI.\""
, "llvm/lib/CodeGen/MachineInstr.cpp", 2220, __extension__ __PRETTY_FUNCTION__
))
;
2221 SmallVector<const MachineOperand *> SpillOperands;
2222 for (const MachineOperand &Op : MI.getDebugOperandsForReg(SpillReg))
2223 SpillOperands.push_back(&Op);
2224 return computeExprForSpill(MI, SpillOperands);
2225}
2226
2227MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2228 MachineBasicBlock::iterator I,
2229 const MachineInstr &Orig,
2230 int FrameIndex, Register SpillReg) {
2231 const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
2232 MachineInstrBuilder NewMI =
2233 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2234 // Non-Variadic Operands: Location, Offset, Variable, Expression
2235 // Variadic Operands: Variable, Expression, Locations...
2236 if (Orig.isNonListDebugValue())
2237 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2238 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2239 if (Orig.isDebugValueList()) {
2240 for (const MachineOperand &Op : Orig.debug_operands())
2241 if (Op.isReg() && Op.getReg() == SpillReg)
2242 NewMI.addFrameIndex(FrameIndex);
2243 else
2244 NewMI.add(MachineOperand(Op));
2245 }
2246 return NewMI;
2247}
2248MachineInstr *llvm::buildDbgValueForSpill(
2249 MachineBasicBlock &BB, MachineBasicBlock::iterator I,
2250 const MachineInstr &Orig, int FrameIndex,
2251 SmallVectorImpl<const MachineOperand *> &SpilledOperands) {
2252 const DIExpression *Expr = computeExprForSpill(Orig, SpilledOperands);
2253 MachineInstrBuilder NewMI =
2254 BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
2255 // Non-Variadic Operands: Location, Offset, Variable, Expression
2256 // Variadic Operands: Variable, Expression, Locations...
2257 if (Orig.isNonListDebugValue())
2258 NewMI.addFrameIndex(FrameIndex).addImm(0U);
2259 NewMI.addMetadata(Orig.getDebugVariable()).addMetadata(Expr);
2260 if (Orig.isDebugValueList()) {
2261 for (const MachineOperand &Op : Orig.debug_operands())
2262 if (is_contained(SpilledOperands, &Op))
2263 NewMI.addFrameIndex(FrameIndex);
2264 else
2265 NewMI.add(MachineOperand(Op));
2266 }
2267 return NewMI;
2268}
2269
2270void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex,
2271 Register Reg) {
2272 const DIExpression *Expr = computeExprForSpill(Orig, Reg);
2273 if (Orig.isNonListDebugValue())
2274 Orig.getDebugOffset().ChangeToImmediate(0U);
2275 for (MachineOperand &Op : Orig.getDebugOperandsForReg(Reg))
2276 Op.ChangeToFrameIndex(FrameIndex);
2277 Orig.getDebugExpressionOp().setMetadata(Expr);
2278}
2279
2280void MachineInstr::collectDebugValues(
2281 SmallVectorImpl<MachineInstr *> &DbgValues) {
2282 MachineInstr &MI = *this;
2283 if (!MI.getOperand(0).isReg())
2284 return;
2285
2286 MachineBasicBlock::iterator DI = MI; ++DI;
2287 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2288 DI != DE; ++DI) {
2289 if (!DI->isDebugValue())
2290 return;
2291 if (DI->hasDebugOperandForReg(MI.getOperand(0).getReg()))
2292 DbgValues.push_back(&*DI);
2293 }
2294}
2295
2296void MachineInstr::changeDebugValuesDefReg(Register Reg) {
2297 // Collect matching debug values.
2298 SmallVector<MachineInstr *, 2> DbgValues;
2299
2300 if (!getOperand(0).isReg())
2301 return;
2302
2303 Register DefReg = getOperand(0).getReg();
2304 auto *MRI = getRegInfo();
2305 for (auto &MO : MRI->use_operands(DefReg)) {
2306 auto *DI = MO.getParent();
2307 if (!DI->isDebugValue())
2308 continue;
2309 if (DI->hasDebugOperandForReg(DefReg)) {
2310 DbgValues.push_back(DI);
2311 }
2312 }
2313
2314 // Propagate Reg to debug value instructions.
2315 for (auto *DBI : DbgValues)
2316 for (MachineOperand &Op : DBI->getDebugOperandsForReg(DefReg))
2317 Op.setReg(Reg);
2318}
2319
2320using MMOList = SmallVector<const MachineMemOperand *, 2>;
2321
2322static unsigned getSpillSlotSize(const MMOList &Accesses,
2323 const MachineFrameInfo &MFI) {
2324 unsigned Size = 0;
2325 for (const auto *A : Accesses)
2326 if (MFI.isSpillSlotObjectIndex(
2327 cast<FixedStackPseudoSourceValue>(A->getPseudoValue())
2328 ->getFrameIndex()))
2329 Size += A->getSize();
2330 return Size;
2331}
2332
2333Optional<unsigned>
2334MachineInstr::getSpillSize(const TargetInstrInfo *TII) const {
2335 int FI;
2336 if (TII->isStoreToStackSlotPostFE(*this, FI)) {
2337 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2338 if (MFI.isSpillSlotObjectIndex(FI))
2339 return (*memoperands_begin())->getSize();
2340 }
2341 return None;
2342}
2343
2344Optional<unsigned>
2345MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const {
2346 MMOList Accesses;
2347 if (TII->hasStoreToStackSlot(*this, Accesses))
2348 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2349 return None;
2350}
2351
2352Optional<unsigned>
2353MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const {
2354 int FI;
2355 if (TII->isLoadFromStackSlotPostFE(*this, FI)) {
2356 const MachineFrameInfo &MFI = getMF()->getFrameInfo();
2357 if (MFI.isSpillSlotObjectIndex(FI))
2358 return (*memoperands_begin())->getSize();
2359 }
2360 return None;
2361}
2362
2363Optional<unsigned>
2364MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
2365 MMOList Accesses;
2366 if (TII->hasLoadFromStackSlot(*this, Accesses))
2367 return getSpillSlotSize(Accesses, getMF()->getFrameInfo());
2368 return None;
2369}
2370
2371unsigned MachineInstr::getDebugInstrNum() {
2372 if (DebugInstrNum == 0)
2373 DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
2374 return DebugInstrNum;
2375}
2376
2377unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) {
2378 if (DebugInstrNum == 0)
2379 DebugInstrNum = MF.getNewDebugInstrNum();
2380 return DebugInstrNum;
2381}