/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include/llvm/CodeGen/MachineInstrBuilder.h

Bug Summary

File:	llvm/include/llvm/CodeGen/MachineInstrBuilder.h
Warning:	line 422, column 10 Forming reference to null pointer

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86SpeculativeExecutionSideEffectSuppression.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/X86 -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/X86 -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/include -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include -D NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/X86 -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-04-040900-46481-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp

→

1//===-- X86SpeculativeExecutionSideEffectSuppression.cpp ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file contains the X86 implementation of the speculative execution side
11/// effect suppression mitigation.
12///
13/// This must be used with the -mlvi-cfi flag in order to mitigate indirect
14/// branches and returns.
15//===----------------------------------------------------------------------===//
16 
17#include "X86.h"
18#include "X86InstrInfo.h"
19#include "X86Subtarget.h"
20#include "llvm/ADT/Statistic.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/Pass.h"
25#include "llvm/Target/TargetMachine.h"
26using namespace llvm;
27 
28#define DEBUG_TYPE"x86-seses" "x86-seses"
29 
30STATISTIC(NumLFENCEsInserted, "Number of lfence instructions inserted")static llvm::Statistic NumLFENCEsInserted = {"x86-seses", "NumLFENCEsInserted"
, "Number of lfence instructions inserted"};
31 
32static cl::opt<bool> EnableSpeculativeExecutionSideEffectSuppression(
33    "x86-seses-enable-without-lvi-cfi",
34    cl::desc("Force enable speculative execution side effect suppression. "
35             "(Note: User must pass -mlvi-cfi in order to mitigate indirect "
36             "branches and returns.)"),
37    cl::init(false), cl::Hidden);
38 
39static cl::opt<bool> OneLFENCEPerBasicBlock(
40    "x86-seses-one-lfence-per-bb",
41    cl::desc(
42        "Omit all lfences other than the first to be placed in a basic block."),
43    cl::init(false), cl::Hidden);
44 
45static cl::opt<bool> OnlyLFENCENonConst(
46    "x86-seses-only-lfence-non-const",
47    cl::desc("Only lfence before groups of terminators where at least one "
48             "branch instruction has an input to the addressing mode that is a "
49             "register other than %rip."),
50    cl::init(false), cl::Hidden);
51 
52static cl::opt<bool>
53    OmitBranchLFENCEs("x86-seses-omit-branch-lfences",
54                      cl::desc("Omit all lfences before branch instructions."),
55                      cl::init(false), cl::Hidden);
56 
57namespace {
58 
59class X86SpeculativeExecutionSideEffectSuppression
60    : public MachineFunctionPass {
61public:
62  X86SpeculativeExecutionSideEffectSuppression() : MachineFunctionPass(ID) {}
63 
64  static char ID;
65  StringRef getPassName() const override {
66    return "X86 Speculative Execution Side Effect Suppression";
67  }
68 
69  bool runOnMachineFunction(MachineFunction &MF) override;
70};
71} // namespace
72 
73char X86SpeculativeExecutionSideEffectSuppression::ID = 0;
74 
75// This function returns whether the passed instruction uses a memory addressing
76// mode that is constant. We treat all memory addressing modes that read
77// from a register that is not %rip as non-constant. Note that the use
78// of the EFLAGS register results in an addressing mode being considered
79// non-constant, therefore all JCC instructions will return false from this
80// function since one of their operands will always be the EFLAGS register.
81static bool hasConstantAddressingMode(const MachineInstr &MI) {
82  for (const MachineOperand &MO : MI.uses())
83    if (MO.isReg() && X86::RIP != MO.getReg())
84      return false;
85  return true;
86}
87 
88bool X86SpeculativeExecutionSideEffectSuppression::runOnMachineFunction(
89    MachineFunction &MF) {
90 
91  const auto &OptLevel = MF.getTarget().getOptLevel();
92  const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
93 
94  // Check whether SESES needs to run as the fallback for LVI at O0, whether the
95  // user explicitly passed an SESES flag, or whether the SESES target feature
96  // was set.
97  if (!EnableSpeculativeExecutionSideEffectSuppression &&
1
Assuming the condition is false→
98      !(Subtarget.useLVILoadHardening() && OptLevel == CodeGenOpt::None) &&
99      !Subtarget.useSpeculativeExecutionSideEffectSuppression())
100    return false;
101 
102  LLVM_DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName()do { } while (false)
2
←
Loop condition is false.  Exiting loop→
103                    << " **********\n")do { } while (false);
104  bool Modified = false;
105  const X86InstrInfo *TII = Subtarget.getInstrInfo();
106  for (MachineBasicBlock &MBB : MF) {
107    MachineInstr *FirstTerminator = nullptr;
3
←
'FirstTerminator' initialized to a null pointer value→
108    // Keep track of whether the previous instruction was an LFENCE to avoid
109    // adding redundant LFENCEs.
110    bool PrevInstIsLFENCE = false;
111    for (auto &MI : MBB) {
112 
113      if (MI.getOpcode() == X86::LFENCE) {
4
←
Assuming the condition is false→
114        PrevInstIsLFENCE = true;
115        continue;
116      }
117      // We want to put an LFENCE before any instruction that
118      // may load or store. This LFENCE is intended to avoid leaking any secret
119      // data due to a given load or store. This results in closing the cache
120      // and memory timing side channels. We will treat terminators that load
121      // or store separately.
122      if (MI.mayLoadOrStore() && !MI.isTerminator()) {
5
←
Calling 'MachineInstr::mayLoadOrStore'→
8
←
Returning from 'MachineInstr::mayLoadOrStore'→
9
←
Calling 'MachineInstr::isTerminator'→
18
←
Returning from 'MachineInstr::isTerminator'→
19
←
Assuming the condition is false→
123        if (!PrevInstIsLFENCE) {
124          BuildMI(MBB, MI, DebugLoc(), TII->get(X86::LFENCE));
125          NumLFENCEsInserted++;
126          Modified = true;
127        }
128        if (OneLFENCEPerBasicBlock)
129          break;
130      }
131      // The following section will be LFENCEing before groups of terminators
132      // that include branches. This will close the branch prediction side
133      // channels since we will prevent code executing after misspeculation as
134      // a result of the LFENCEs placed with this logic.
135 
136      // Keep track of the first terminator in a basic block since if we need
137      // to LFENCE the terminators in this basic block we must add the
138      // instruction before the first terminator in the basic block (as
139      // opposed to before the terminator that indicates an LFENCE is
140      // required). An example of why this is necessary is that the
141      // X86InstrInfo::analyzeBranch method assumes all terminators are grouped
142      // together and terminates it's analysis once the first non-termintor
143      // instruction is found.
144      if (MI.isTerminator() && FirstTerminator == nullptr)
20
←
Assuming the condition is false→
145        FirstTerminator = &MI;
146 
147      // Look for branch instructions that will require an LFENCE to be put
148      // before this basic block's terminators.
149      if (!MI.isBranch() || OmitBranchLFENCEs) {
21
←
Calling 'MachineInstr::isBranch'→
30
←
Returning from 'MachineInstr::isBranch'→
31
←
Assuming the condition is false→
32
←
Assuming the condition is false→
150        // This isn't a branch or we're not putting LFENCEs before branches.
151        PrevInstIsLFENCE = false;
152        continue;
153      }
154 
155      if (OnlyLFENCENonConst && hasConstantAddressingMode(MI)) {
33
←
Assuming the condition is false→
156        // This is a branch, but it only has constant addressing mode and we're
157        // not adding LFENCEs before such branches.
158        PrevInstIsLFENCE = false;
159        continue;
160      }
161 
162      // This branch requires adding an LFENCE.
163      if (!PrevInstIsLFENCE33.1
'PrevInstIsLFENCE' is false
33.1
'PrevInstIsLFENCE' is false
33.1
'PrevInstIsLFENCE' is false
) {
34
←
Taking true branch→
164        assert(FirstTerminator && "Unknown terminator instruction")(static_cast<void> (0));
165        BuildMI(MBB, FirstTerminator, DebugLoc(), TII->get(X86::LFENCE));
35
←
Passing null pointer value via 2nd parameter 'I'→
36
←
Calling 'BuildMI'→
166        NumLFENCEsInserted++;
167        Modified = true;
168      }
169      break;
170    }
171  }
172 
173  return Modified;
174}
175 
176FunctionPass *llvm::createX86SpeculativeExecutionSideEffectSuppression() {
177  return new X86SpeculativeExecutionSideEffectSuppression();
178}
179 
180INITIALIZE_PASS(X86SpeculativeExecutionSideEffectSuppression, "x86-seses",static void *initializeX86SpeculativeExecutionSideEffectSuppressionPassOnce
(PassRegistry &Registry) { PassInfo *PI = new PassInfo( "X86 Speculative Execution Side Effect Suppression"
, "x86-seses", &X86SpeculativeExecutionSideEffectSuppression
::ID, PassInfo::NormalCtor_t(callDefaultCtor<X86SpeculativeExecutionSideEffectSuppression
>), false, false); Registry.registerPass(*PI, true); return
 PI; } static llvm::once_flag InitializeX86SpeculativeExecutionSideEffectSuppressionPassFlag
; void llvm::initializeX86SpeculativeExecutionSideEffectSuppressionPass
(PassRegistry &Registry) { llvm::call_once(InitializeX86SpeculativeExecutionSideEffectSuppressionPassFlag
, initializeX86SpeculativeExecutionSideEffectSuppressionPassOnce
, std::ref(Registry)); }
181                "X86 Speculative Execution Side Effect Suppression", false,static void *initializeX86SpeculativeExecutionSideEffectSuppressionPassOnce
(PassRegistry &Registry) { PassInfo *PI = new PassInfo( "X86 Speculative Execution Side Effect Suppression"
, "x86-seses", &X86SpeculativeExecutionSideEffectSuppression
::ID, PassInfo::NormalCtor_t(callDefaultCtor<X86SpeculativeExecutionSideEffectSuppression
>), false, false); Registry.registerPass(*PI, true); return
 PI; } static llvm::once_flag InitializeX86SpeculativeExecutionSideEffectSuppressionPassFlag
; void llvm::initializeX86SpeculativeExecutionSideEffectSuppressionPass
(PassRegistry &Registry) { llvm::call_once(InitializeX86SpeculativeExecutionSideEffectSuppressionPassFlag
, initializeX86SpeculativeExecutionSideEffectSuppressionPassOnce
, std::ref(Registry)); }
182                false)static void *initializeX86SpeculativeExecutionSideEffectSuppressionPassOnce
(PassRegistry &Registry) { PassInfo *PI = new PassInfo( "X86 Speculative Execution Side Effect Suppression"
, "x86-seses", &X86SpeculativeExecutionSideEffectSuppression
::ID, PassInfo::NormalCtor_t(callDefaultCtor<X86SpeculativeExecutionSideEffectSuppression
>), false, false); Registry.registerPass(*PI, true); return
 PI; } static llvm::once_flag InitializeX86SpeculativeExecutionSideEffectSuppressionPassFlag
; void llvm::initializeX86SpeculativeExecutionSideEffectSuppressionPass
(PassRegistry &Registry) { llvm::call_once(InitializeX86SpeculativeExecutionSideEffectSuppressionPassFlag
, initializeX86SpeculativeExecutionSideEffectSuppressionPassOnce
, std::ref(Registry)); }

←

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include/llvm/CodeGen/MachineInstr.h

→

1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//

15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H

18#include "llvm/ADT/DenseMapInfo.h"
19#include "llvm/ADT/PointerSumType.h"
20#include "llvm/ADT/SmallSet.h"
21#include "llvm/ADT/ilist.h"
22#include "llvm/ADT/ilist_node.h"
23#include "llvm/ADT/iterator_range.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineOperand.h"
26#include "llvm/CodeGen/TargetOpcodes.h"
27#include "llvm/IR/DebugLoc.h"
28#include "llvm/IR/InlineAsm.h"
29#include "llvm/IR/PseudoProbe.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Support/ArrayRecycler.h"
33#include "llvm/Support/TrailingObjects.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <utility>

39namespace llvm {

41class AAResults;
42template <typename T> class ArrayRef;
43class DIExpression;
44class DILocalVariable;
45class MachineBasicBlock;
46class MachineFunction;
47class MachineRegisterInfo;
48class ModuleSlotTracker;
49class raw_ostream;
50template <typename T> class SmallVectorImpl;
51class SmallBitVector;
52class StringRef;
53class TargetInstrInfo;
54class TargetRegisterClass;
55class TargetRegisterInfo;

57//===----------------------------------------------------------------------===//
58/// Representation of each machine instruction.
59///
60/// This class isn't a POD type, but it must have a trivial destructor. When a
61/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
62/// without having their destructor called.
63///
64class MachineInstr
  : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
                                  ilist_sentinel_tracking<true>> {
67public:
using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;

/// Flags to specify different kinds of comments to output in
/// assembly code.  These flags carry semantic information not
/// otherwise easily derivable from the IR text.
///
enum CommentFlag {
  ReloadReuse = 0x1,    // higher bits are reserved for target dep comments.
  NoSchedComment = 0x2,
  TAsmComments = 0x4    // Target Asm comments should start from this value.
};

enum MIFlag {
  NoFlags      = 0,
  FrameSetup   = 1 << 0,              // Instruction is used as a part of
                                      // function frame setup code.
  FrameDestroy = 1 << 1,              // Instruction is used as a part of
                                      // function frame destruction code.
  BundledPred  = 1 << 2,              // Instruction has bundled predecessors.
  BundledSucc  = 1 << 3,              // Instruction has bundled successors.
  FmNoNans     = 1 << 4,              // Instruction does not support Fast
                                      // math nan values.
  FmNoInfs     = 1 << 5,              // Instruction does not support Fast
                                      // math infinity values.
  FmNsz        = 1 << 6,              // Instruction is not required to retain
                                      // signed zero values.
  FmArcp       = 1 << 7,              // Instruction supports Fast math
                                      // reciprocal approximations.
  FmContract   = 1 << 8,              // Instruction supports Fast math
                                      // contraction operations like fma.
  FmAfn        = 1 << 9,              // Instruction may map to Fast math
                                      // instrinsic approximation.
  FmReassoc    = 1 << 10,             // Instruction supports Fast math
                                      // reassociation of operand order.
  NoUWrap      = 1 << 11,             // Instruction supports binary operator
                                      // no unsigned wrap.
  NoSWrap      = 1 << 12,             // Instruction supports binary operator
                                      // no signed wrap.
  IsExact      = 1 << 13,             // Instruction supports division is
                                      // known to be exact.
  NoFPExcept   = 1 << 14,             // Instruction does not raise
                                      // floatint-point exceptions.
  NoMerge      = 1 << 15,             // Passes that drop source location info
                                      // (e.g. branch folding) should skip
                                      // this instruction.
};

115private:
const MCInstrDesc *MCID;              // Instruction descriptor.
MachineBasicBlock *Parent = nullptr;  // Pointer to the owning basic block.

// Operands are allocated by an ArrayRecycler.
MachineOperand *Operands = nullptr;   // Pointer to the first operand.
unsigned NumOperands = 0;             // Number of operands on instruction.

uint16_t Flags = 0;                   // Various bits of additional
                                      // information about machine
                                      // instruction.

uint8_t AsmPrinterFlags = 0;          // Various bits of information used by
                                      // the AsmPrinter to emit helpful
                                      // comments.  This is *not* semantic
                                      // information.  Do not use this for
                                      // anything other than to convey comment
                                      // information to AsmPrinter.

// OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
// to properly pack.
using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
OperandCapacity CapOperands;          // Capacity of the Operands array.

/// Internal implementation detail class that provides out-of-line storage for
/// extra info used by the machine instruction when this info cannot be stored
/// in-line within the instruction itself.
///
/// This has to be defined eagerly due to the implementation constraints of
/// `PointerSumType` where it is used.
class ExtraInfo final
    : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> {
public:
  static ExtraInfo *create(BumpPtrAllocator &Allocator,
                           ArrayRef<MachineMemOperand *> MMOs,
                           MCSymbol *PreInstrSymbol = nullptr,
                           MCSymbol *PostInstrSymbol = nullptr,
                           MDNode *HeapAllocMarker = nullptr) {
    bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
    bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
    bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
    auto *Result = new (Allocator.Allocate(
        totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>(
            MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
            HasHeapAllocMarker),
        alignof(ExtraInfo)))
        ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
                  HasHeapAllocMarker);

    // Copy the actual data into the trailing objects.
    std::copy(MMOs.begin(), MMOs.end(),
              Result->getTrailingObjects<MachineMemOperand *>());

    if (HasPreInstrSymbol)
      Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
    if (HasPostInstrSymbol)
      Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
          PostInstrSymbol;
    if (HasHeapAllocMarker)
      Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;

    return Result;
  }

  ArrayRef<MachineMemOperand *> getMMOs() const {
    return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
  }

  MCSymbol *getPreInstrSymbol() const {
    return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
  }

  MCSymbol *getPostInstrSymbol() const {
    return HasPostInstrSymbol
               ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
               : nullptr;
  }

  MDNode *getHeapAllocMarker() const {
    return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
  }

private:
  friend TrailingObjects;

  // Description of the extra info, used to interpret the actual optional
  // data appended.
  //
  // Note that this is not terribly space optimized. This leaves a great deal
  // of flexibility to fit more in here later.
  const int NumMMOs;
  const bool HasPreInstrSymbol;
  const bool HasPostInstrSymbol;
  const bool HasHeapAllocMarker;

  // Implement the `TrailingObjects` internal API.
  size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
    return NumMMOs;
  }
  size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
    return HasPreInstrSymbol + HasPostInstrSymbol;
  }
  size_t numTrailingObjects(OverloadToken<MDNode *>) const {
    return HasHeapAllocMarker;
  }

  // Just a boring constructor to allow us to initialize the sizes. Always use
  // the `create` routine above.
  ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
            bool HasHeapAllocMarker)
      : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
        HasPostInstrSymbol(HasPostInstrSymbol),
        HasHeapAllocMarker(HasHeapAllocMarker) {}
};

/// Enumeration of the kinds of inline extra info available. It is important
/// that the `MachineMemOperand` inline kind has a tag value of zero to make
/// it accessible as an `ArrayRef`.
enum ExtraInfoInlineKinds {
  EIIK_MMO = 0,
  EIIK_PreInstrSymbol,
  EIIK_PostInstrSymbol,
  EIIK_OutOfLine
};

// We store extra information about the instruction here. The common case is
// expected to be nothing or a single pointer (typically a MMO or a symbol).
// We work to optimize this common case by storing it inline here rather than
// requiring a separate allocation, but we fall back to an allocation when
// multiple pointers are needed.
PointerSumType<ExtraInfoInlineKinds,
               PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
               PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
               PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
               PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
    Info;

DebugLoc debugLoc;                    // Source line information.

/// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
/// defined by this instruction.
unsigned DebugInstrNum;

// Intrusive list support
friend struct ilist_traits<MachineInstr>;
friend struct ilist_callback_traits<MachineBasicBlock>;
void setParent(MachineBasicBlock *P) { Parent = P; }

/// This constructor creates a copy of the given
/// MachineInstr in the given MachineFunction.
MachineInstr(MachineFunction &, const MachineInstr &);

/// This constructor create a MachineInstr and add the implicit operands.
/// It reserves space for number of operands specified by
/// MCInstrDesc.  An explicit DebugLoc is supplied.
MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
             bool NoImp = false);

// MachineInstrs are pool-allocated and owned by MachineFunction.
friend class MachineFunction;

void
dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
          SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;

280public:
MachineInstr(const MachineInstr &) = delete;
MachineInstr &operator=(const MachineInstr &) = delete;
// Use MachineFunction::DeleteMachineInstr() instead.
~MachineInstr() = delete;

const MachineBasicBlock* getParent() const { return Parent; }
MachineBasicBlock* getParent() { return Parent; }

/// Move the instruction before \p MovePos.
void moveBefore(MachineInstr *MovePos);

/// Return the function that contains the basic block that this instruction
/// belongs to.
///
/// Note: this is undefined behaviour if the instruction does not have a
/// parent.
const MachineFunction *getMF() const;
MachineFunction *getMF() {
  return const_cast<MachineFunction *>(
      static_cast<const MachineInstr *>(this)->getMF());
}

/// Return the asm printer flags bitvector.
uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }

/// Clear the AsmPrinter bitvector.
void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }

/// Return whether an AsmPrinter flag is set.
bool getAsmPrinterFlag(CommentFlag Flag) const {
  return AsmPrinterFlags & Flag;
}

/// Set a flag for the AsmPrinter.
void setAsmPrinterFlag(uint8_t Flag) {
  AsmPrinterFlags |= Flag;
}

/// Clear specific AsmPrinter flags.
void clearAsmPrinterFlag(CommentFlag Flag) {
  AsmPrinterFlags &= ~Flag;
}

/// Return the MI flags bitvector.
uint16_t getFlags() const {
  return Flags;
}

/// Return whether an MI flag is set.
bool getFlag(MIFlag Flag) const {
  return Flags & Flag;
}

/// Set a MI flag.
void setFlag(MIFlag Flag) {
  Flags |= (uint16_t)Flag;
}

void setFlags(unsigned flags) {
  // Filter out the automatically maintained flags.
  unsigned Mask = BundledPred | BundledSucc;
  Flags = (Flags & Mask) | (flags & ~Mask);
}

/// clearFlag - Clear a MI flag.
void clearFlag(MIFlag Flag) {
  Flags &= ~((uint16_t)Flag);
}

/// Return true if MI is in a bundle (but not the first MI in a bundle).
///
/// A bundle looks like this before it's finalized:
///   ----------------
///   |      MI      |
///   ----------------
///          |
///   ----------------
///   |      MI    * |
///   ----------------
///          |
///   ----------------
///   |      MI    * |
///   ----------------
/// In this case, the first MI starts a bundle but is not inside a bundle, the
/// next 2 MIs are considered "inside" the bundle.
///
/// After a bundle is finalized, it looks like this:
///   ----------------
///   |    Bundle    |
///   ----------------
///          |
///   ----------------
///   |      MI    * |
///   ----------------
///          |
///   ----------------
///   |      MI    * |
///   ----------------
///          |
///   ----------------
///   |      MI    * |
///   ----------------
/// The first instruction has the special opcode "BUNDLE". It's not "inside"
/// a bundle, but the next three MIs are.
bool isInsideBundle() const {
  return getFlag(BundledPred);
}

/// Return true if this instruction part of a bundle. This is true
/// if either itself or its following instruction is marked "InsideBundle".
bool isBundled() const {
  return isBundledWithPred() || isBundledWithSucc();
12
←
Returning value, which participates in a condition later→
24
←
Returning value, which participates in a condition later→
}

/// Return true if this instruction is part of a bundle, and it is not the
/// first instruction in the bundle.
bool isBundledWithPred() const { return getFlag(BundledPred); }

/// Return true if this instruction is part of a bundle, and it is not the
/// last instruction in the bundle.
bool isBundledWithSucc() const { return getFlag(BundledSucc); }

/// Bundle this instruction with its predecessor. This can be an unbundled
/// instruction, or it can be the first instruction in a bundle.
void bundleWithPred();

/// Bundle this instruction with its successor. This can be an unbundled
/// instruction, or it can be the last instruction in a bundle.
void bundleWithSucc();

/// Break bundle above this instruction.
void unbundleFromPred();

/// Break bundle below this instruction.
void unbundleFromSucc();

/// Returns the debug location id of this MachineInstr.
const DebugLoc &getDebugLoc() const { return debugLoc; }

/// Return the operand containing the offset to be used if this DBG_VALUE
/// instruction is indirect; will be an invalid register if this value is
/// not indirect, and an immediate with value 0 otherwise.
const MachineOperand &getDebugOffset() const {
  assert(isNonListDebugValue() && "not a DBG_VALUE")(static_cast<void> (0));
  return getOperand(1);
}
MachineOperand &getDebugOffset() {
  assert(isNonListDebugValue() && "not a DBG_VALUE")(static_cast<void> (0));
  return getOperand(1);
}

/// Return the operand for the debug variable referenced by
/// this DBG_VALUE instruction.
const MachineOperand &getDebugVariableOp() const;
MachineOperand &getDebugVariableOp();

/// Return the debug variable referenced by
/// this DBG_VALUE instruction.
const DILocalVariable *getDebugVariable() const;

/// Return the operand for the complex address expression referenced by
/// this DBG_VALUE instruction.
const MachineOperand &getDebugExpressionOp() const;
MachineOperand &getDebugExpressionOp();

/// Return the complex address expression referenced by
/// this DBG_VALUE instruction.
const DIExpression *getDebugExpression() const;

/// Return the debug label referenced by
/// this DBG_LABEL instruction.
const DILabel *getDebugLabel() const;

/// Fetch the instruction number of this MachineInstr. If it does not have
/// one already, a new and unique number will be assigned.
unsigned getDebugInstrNum();

/// Fetch instruction number of this MachineInstr -- but before it's inserted
/// into \p MF. Needed for transformations that create an instruction but
/// don't immediately insert them.
unsigned getDebugInstrNum(MachineFunction &MF);

/// Examine the instruction number of this MachineInstr. May be zero if
/// it hasn't been assigned a number yet.
unsigned peekDebugInstrNum() const { return DebugInstrNum; }

/// Set instruction number of this MachineInstr. Avoid using unless you're
/// deserializing this information.
void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }

/// Drop any variable location debugging information associated with this
/// instruction. Use when an instruction is modified in such a way that it no
/// longer defines the value it used to. Variable locations using that value
/// will be dropped.
void dropDebugNumber() { DebugInstrNum = 0; }

/// Emit an error referring to the source location of this instruction.
/// This should only be used for inline assembly that is somehow
/// impossible to compile. Other errors should have been handled much
/// earlier.
///
/// If this method returns, the caller should try to recover from the error.
void emitError(StringRef Msg) const;

/// Returns the target instruction descriptor of this MachineInstr.
const MCInstrDesc &getDesc() const { return *MCID; }

/// Returns the opcode of this MachineInstr.
unsigned getOpcode() const { return MCID->Opcode; }

/// Retuns the total number of operands.
unsigned getNumOperands() const { return NumOperands; }

/// Returns the total number of operands which are debug locations.
unsigned getNumDebugOperands() const {
  return std::distance(debug_operands().begin(), debug_operands().end());
}

const MachineOperand& getOperand(unsigned i) const {
  assert(i < getNumOperands() && "getOperand() out of range!")(static_cast<void> (0));
  return Operands[i];
}
MachineOperand& getOperand(unsigned i) {
  assert(i < getNumOperands() && "getOperand() out of range!")(static_cast<void> (0));
  return Operands[i];
}

MachineOperand &getDebugOperand(unsigned Index) {
  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!")(static_cast<void> (0));
  return *(debug_operands().begin() + Index);
}
const MachineOperand &getDebugOperand(unsigned Index) const {
  assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!")(static_cast<void> (0));
  return *(debug_operands().begin() + Index);
}

SmallSet<Register, 4> getUsedDebugRegs() const {
  assert(isDebugValue() && "not a DBG_VALUE*")(static_cast<void> (0));
  SmallSet<Register, 4> UsedRegs;
  for (auto MO : debug_operands())
    if (MO.isReg() && MO.getReg())
      UsedRegs.insert(MO.getReg());
  return UsedRegs;
}

/// Returns whether this debug value has at least one debug operand with the
/// register \p Reg.
bool hasDebugOperandForReg(Register Reg) const {
  return any_of(debug_operands(), [Reg](const MachineOperand &Op) {
    return Op.isReg() && Op.getReg() == Reg;
  });
}

/// Returns a range of all of the operands that correspond to a debug use of
/// \p Reg.
template <typename Operand, typename Instruction>
static iterator_range<
    filter_iterator<Operand *, std::function<bool(Operand &Op)>>>
getDebugOperandsForReg(Instruction *MI, Register Reg) {
  std::function<bool(Operand & Op)> OpUsesReg(
      [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; });
  return make_filter_range(MI->debug_operands(), OpUsesReg);
}
iterator_range<filter_iterator<const MachineOperand *,
                               std::function<bool(const MachineOperand &Op)>>>
getDebugOperandsForReg(Register Reg) const {
  return MachineInstr::getDebugOperandsForReg<const MachineOperand,
                                              const MachineInstr>(this, Reg);
}
iterator_range<filter_iterator<MachineOperand *,
                               std::function<bool(MachineOperand &Op)>>>
getDebugOperandsForReg(Register Reg) {
  return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>(
      this, Reg);
}

bool isDebugOperand(const MachineOperand *Op) const {
  return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands());
}

unsigned getDebugOperandIndex(const MachineOperand *Op) const {
  assert(isDebugOperand(Op) && "Expected a debug operand.")(static_cast<void> (0));
  return std::distance(adl_begin(debug_operands()), Op);
}

/// Returns the total number of definitions.
unsigned getNumDefs() const {
  return getNumExplicitDefs() + MCID->getNumImplicitDefs();
}

/// Returns true if the instruction has implicit definition.
bool hasImplicitDef() const {
  for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
    I != E; ++I) {
    const MachineOperand &MO = getOperand(I);
    if (MO.isDef() && MO.isImplicit())
      return true;
  }
  return false;
}

/// Returns the implicit operands number.
unsigned getNumImplicitOperands() const {
  return getNumOperands() - getNumExplicitOperands();
}

/// Return true if operand \p OpIdx is a subregister index.
bool isOperandSubregIdx(unsigned OpIdx) const {
  assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&(static_cast<void> (0))
         "Expected MO_Immediate operand type.")(static_cast<void> (0));
  if (isExtractSubreg() && OpIdx == 2)
    return true;
  if (isInsertSubreg() && OpIdx == 3)
    return true;
  if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
    return true;
  if (isSubregToReg() && OpIdx == 3)
    return true;
  return false;
}

/// Returns the number of non-implicit operands.
unsigned getNumExplicitOperands() const;

/// Returns the number of non-implicit definitions.
unsigned getNumExplicitDefs() const;

/// iterator/begin/end - Iterate over all operands of a machine instruction.
using mop_iterator = MachineOperand *;
using const_mop_iterator = const MachineOperand *;

mop_iterator operands_begin() { return Operands; }
mop_iterator operands_end() { return Operands + NumOperands; }

const_mop_iterator operands_begin() const { return Operands; }
const_mop_iterator operands_end() const { return Operands + NumOperands; }

iterator_range<mop_iterator> operands() {
  return make_range(operands_begin(), operands_end());
}
iterator_range<const_mop_iterator> operands() const {
  return make_range(operands_begin(), operands_end());
}
iterator_range<mop_iterator> explicit_operands() {
  return make_range(operands_begin(),
                    operands_begin() + getNumExplicitOperands());
}
iterator_range<const_mop_iterator> explicit_operands() const {
  return make_range(operands_begin(),
                    operands_begin() + getNumExplicitOperands());
}
iterator_range<mop_iterator> implicit_operands() {
  return make_range(explicit_operands().end(), operands_end());
}
iterator_range<const_mop_iterator> implicit_operands() const {
  return make_range(explicit_operands().end(), operands_end());
}
/// Returns a range over all operands that are used to determine the variable
/// location for this DBG_VALUE instruction.
iterator_range<mop_iterator> debug_operands() {
  assert(isDebugValue() && "Must be a debug value instruction.")(static_cast<void> (0));
  return isDebugValueList()
             ? make_range(operands_begin() + 2, operands_end())
             : make_range(operands_begin(), operands_begin() + 1);
}
/// \copydoc debug_operands()
iterator_range<const_mop_iterator> debug_operands() const {
  assert(isDebugValue() && "Must be a debug value instruction.")(static_cast<void> (0));
  return isDebugValueList()
             ? make_range(operands_begin() + 2, operands_end())
             : make_range(operands_begin(), operands_begin() + 1);
}
/// Returns a range over all explicit operands that are register definitions.
/// Implicit definition are not included!
iterator_range<mop_iterator> defs() {
  return make_range(operands_begin(),
                    operands_begin() + getNumExplicitDefs());
}
/// \copydoc defs()
iterator_range<const_mop_iterator> defs() const {
  return make_range(operands_begin(),
                    operands_begin() + getNumExplicitDefs());
}
/// Returns a range that includes all operands that are register uses.
/// This may include unrelated operands which are not register uses.
iterator_range<mop_iterator> uses() {
  return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
}
/// \copydoc uses()
iterator_range<const_mop_iterator> uses() const {
  return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
}
iterator_range<mop_iterator> explicit_uses() {
  return make_range(operands_begin() + getNumExplicitDefs(),
                    operands_begin() + getNumExplicitOperands());
}
iterator_range<const_mop_iterator> explicit_uses() const {
  return make_range(operands_begin() + getNumExplicitDefs(),
                    operands_begin() + getNumExplicitOperands());
}

/// Returns the number of the operand iterator \p I points to.
unsigned getOperandNo(const_mop_iterator I) const {
  return I - operands_begin();
}

/// Access to memory operands of the instruction. If there are none, that does
/// not imply anything about whether the function accesses memory. Instead,
/// the caller must behave conservatively.
ArrayRef<MachineMemOperand *> memoperands() const {
  if (!Info)
    return {};

  if (Info.is<EIIK_MMO>())
    return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);

  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
    return EI->getMMOs();

  return {};
}

/// Access to memory operands of the instruction.
///
/// If `memoperands_begin() == memoperands_end()`, that does not imply
/// anything about whether the function accesses memory. Instead, the caller
/// must behave conservatively.
mmo_iterator memoperands_begin() const { return memoperands().begin(); }

/// Access to memory operands of the instruction.
///
/// If `memoperands_begin() == memoperands_end()`, that does not imply
/// anything about whether the function accesses memory. Instead, the caller
/// must behave conservatively.
mmo_iterator memoperands_end() const { return memoperands().end(); }

/// Return true if we don't have any memory operands which described the
/// memory access done by this instruction.  If this is true, calling code
/// must be conservative.
bool memoperands_empty() const { return memoperands().empty(); }

/// Return true if this instruction has exactly one MachineMemOperand.
bool hasOneMemOperand() const { return memoperands().size() == 1; }

/// Return the number of memory operands.
unsigned getNumMemOperands() const { return memoperands().size(); }

/// Helper to extract a pre-instruction symbol if one has been added.
MCSymbol *getPreInstrSymbol() const {
  if (!Info)
    return nullptr;
  if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
    return S;
  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
    return EI->getPreInstrSymbol();

  return nullptr;
}

/// Helper to extract a post-instruction symbol if one has been added.
MCSymbol *getPostInstrSymbol() const {
  if (!Info)
    return nullptr;
  if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
    return S;
  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
    return EI->getPostInstrSymbol();

  return nullptr;
}

/// Helper to extract a heap alloc marker if one has been added.
MDNode *getHeapAllocMarker() const {
  if (!Info)
    return nullptr;
  if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
    return EI->getHeapAllocMarker();

  return nullptr;
}

/// API for querying MachineInstr properties. They are the same as MCInstrDesc
/// queries but they are bundle aware.

enum QueryType {
  IgnoreBundle,    // Ignore bundles
  AnyInBundle,     // Return true if any instruction in bundle has property
  AllInBundle      // Return true if all instructions in bundle have property
};

/// Return true if the instruction (or in the case of a bundle,
/// the instructions inside the bundle) has the specified property.
/// The first argument is the property being queried.
/// The second argument indicates whether the query should look inside
/// instruction bundles.
bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
  assert(MCFlag < 64 &&(static_cast<void> (0))
         "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.")(static_cast<void> (0));
  // Inline the fast path for unbundled or bundle-internal instructions.
  if (Type10.1
'Type' is not equal to IgnoreBundle
1
'Type' is not equal to IgnoreBundle
1
'Type' is not equal to IgnoreBundle
1
'Type' is not equal to IgnoreBundle
1
'Type' is not equal to IgnoreBundle
1
'Type' is not equal to IgnoreBundle
 == IgnoreBundle || !isBundled() || isBundledWithPred())
11
←
Calling 'MachineInstr::isBundled'→
13
←
Returning from 'MachineInstr::isBundled'→
14
←
Taking false branch→
23
←
Calling 'MachineInstr::isBundled'→
25
←
Returning from 'MachineInstr::isBundled'→
26
←
Taking false branch→
    return getDesc().getFlags() & (1ULL << MCFlag);

  // If this is the first instruction in a bundle, take the slow path.
  return hasPropertyInBundle(1ULL << MCFlag, Type);
15
←
Returning value, which participates in a condition later→
27
←
Returning value, which participates in a condition later→
}

/// Return true if this is an instruction that should go through the usual
/// legalization steps.
bool isPreISelOpcode(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::PreISelOpcode, Type);
}

/// Return true if this instruction can have a variable number of operands.
/// In this case, the variable operands will be after the normal
/// operands but before the implicit definitions and uses (if any are
/// present).
bool isVariadic(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Variadic, Type);
}

/// Set if this instruction has an optional definition, e.g.
/// ARM instructions which can set condition code if 's' bit is set.
bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::HasOptionalDef, Type);
}

/// Return true if this is a pseudo instruction that doesn't
/// correspond to a real machine instruction.
bool isPseudo(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Pseudo, Type);
}

bool isReturn(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::Return, Type);
}

/// Return true if this is an instruction that marks the end of an EH scope,
/// i.e., a catchpad or a cleanuppad instruction.
bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::EHScopeReturn, Type);
}

bool isCall(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::Call, Type);
}

/// Return true if this is a call instruction that may have an associated
/// call site entry in the debug info.
bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const;
/// Return true if copying, moving, or erasing this instruction requires
/// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
/// \ref eraseCallSiteInfo).
bool shouldUpdateCallSiteInfo() const;

/// Returns true if the specified instruction stops control flow
/// from executing the instruction immediately following it.  Examples include
/// unconditional branches and return instructions.
bool isBarrier(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::Barrier, Type);
}

/// Returns true if this instruction part of the terminator for a basic block.
/// Typically this is things like return and branch instructions.
///
/// Various passes use this to insert code into the bottom of a basic block,
/// but before control flow occurs.
bool isTerminator(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::Terminator, Type);
10
←
Calling 'MachineInstr::hasProperty'→
16
←
Returning from 'MachineInstr::hasProperty'→
17
←
Returning value, which participates in a condition later→
}

/// Returns true if this is a conditional, unconditional, or indirect branch.
/// Predicates below can be used to discriminate between
/// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
/// get more information.
bool isBranch(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::Branch, Type);
22
←
Calling 'MachineInstr::hasProperty'→
28
←
Returning from 'MachineInstr::hasProperty'→
29
←
Returning value, which participates in a condition later→
}

/// Return true if this is an indirect branch, such as a
/// branch through a register.
bool isIndirectBranch(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::IndirectBranch, Type);
}

/// Return true if this is a branch which may fall
/// through to the next instruction or may transfer control flow to some other
/// block.  The TargetInstrInfo::analyzeBranch method can be used to get more
/// information about this branch.
bool isConditionalBranch(QueryType Type = AnyInBundle) const {
  return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
}

/// Return true if this is a branch which always
/// transfers control flow to some other block.  The
/// TargetInstrInfo::analyzeBranch method can be used to get more information
/// about this branch.
bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
  return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
}

/// Return true if this instruction has a predicate operand that
/// controls execution.  It may be set to 'always', or may be set to other
/// values.   There are various methods in TargetInstrInfo that can be used to
/// control and modify the predicate in this instruction.
bool isPredicable(QueryType Type = AllInBundle) const {
  // If it's a bundle than all bundled instructions must be predicable for this
  // to return true.
  return hasProperty(MCID::Predicable, Type);
}

/// Return true if this instruction is a comparison.
bool isCompare(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Compare, Type);
}

/// Return true if this instruction is a move immediate
/// (including conditional moves) instruction.
bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::MoveImm, Type);
}

/// Return true if this instruction is a register move.
/// (including moving values from subreg to reg)
bool isMoveReg(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::MoveReg, Type);
}

/// Return true if this instruction is a bitcast instruction.
bool isBitcast(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Bitcast, Type);
}

/// Return true if this instruction is a select instruction.
bool isSelect(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Select, Type);
}

/// Return true if this instruction cannot be safely duplicated.
/// For example, if the instruction has a unique labels attached
/// to it, duplicating it would cause multiple definition errors.
bool isNotDuplicable(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::NotDuplicable, Type);
}

/// Return true if this instruction is convergent.
/// Convergent instructions can not be made control-dependent on any
/// additional values.
bool isConvergent(QueryType Type = AnyInBundle) const {
  if (isInlineAsm()) {
    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    if (ExtraInfo & InlineAsm::Extra_IsConvergent)
      return true;
  }
  return hasProperty(MCID::Convergent, Type);
}

/// Returns true if the specified instruction has a delay slot
/// which must be filled by the code generator.
bool hasDelaySlot(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::DelaySlot, Type);
}

/// Return true for instructions that can be folded as
/// memory operands in other instructions. The most common use for this
/// is instructions that are simple loads from memory that don't modify
/// the loaded value in any way, but it can also be used for instructions
/// that can be expressed as constant-pool loads, such as V_SETALLONES
/// on x86, to allow them to be folded when it is beneficial.
/// This should only be set on instructions that return a value in their
/// only virtual register definition.
bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::FoldableAsLoad, Type);
}

/// Return true if this instruction behaves
/// the same way as the generic REG_SEQUENCE instructions.
/// E.g., on ARM,
/// dX VMOVDRR rY, rZ
/// is equivalent to
/// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
///
/// Note that for the optimizers to be able to take advantage of
/// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
/// override accordingly.
bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::RegSequence, Type);
}

/// Return true if this instruction behaves
/// the same way as the generic EXTRACT_SUBREG instructions.
/// E.g., on ARM,
/// rX, rY VMOVRRD dZ
/// is equivalent to two EXTRACT_SUBREG:
/// rX = EXTRACT_SUBREG dZ, ssub_0
/// rY = EXTRACT_SUBREG dZ, ssub_1
///
/// Note that for the optimizers to be able to take advantage of
/// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
/// override accordingly.
bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::ExtractSubreg, Type);
}

/// Return true if this instruction behaves
/// the same way as the generic INSERT_SUBREG instructions.
/// E.g., on ARM,
/// dX = VSETLNi32 dY, rZ, Imm
/// is equivalent to a INSERT_SUBREG:
/// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
///
/// Note that for the optimizers to be able to take advantage of
/// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
/// override accordingly.
bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::InsertSubreg, Type);
}

//===--------------------------------------------------------------------===//
// Side Effect Analysis
//===--------------------------------------------------------------------===//

/// Return true if this instruction could possibly read memory.
/// Instructions with this flag set are not necessarily simple load
/// instructions, they may load a value and modify it, for example.
bool mayLoad(QueryType Type = AnyInBundle) const {
  if (isInlineAsm()) {
    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    if (ExtraInfo & InlineAsm::Extra_MayLoad)
      return true;
  }
  return hasProperty(MCID::MayLoad, Type);
}

/// Return true if this instruction could possibly modify memory.
/// Instructions with this flag set are not necessarily simple store
/// instructions, they may store a modified value based on their operands, or
/// may not actually modify anything, for example.
bool mayStore(QueryType Type = AnyInBundle) const {
  if (isInlineAsm()) {
    unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
    if (ExtraInfo & InlineAsm::Extra_MayStore)
      return true;
  }
  return hasProperty(MCID::MayStore, Type);
}

/// Return true if this instruction could possibly read or modify memory.
bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
  return mayLoad(Type) || mayStore(Type);
6
←
Assuming the condition is true→
7
←
Returning the value 1, which participates in a condition later→
}

/// Return true if this instruction could possibly raise a floating-point
/// exception.  This is the case if the instruction is a floating-point
/// instruction that can in principle raise an exception, as indicated
/// by the MCID::MayRaiseFPException property, *and* at the same time,
/// the instruction is used in a context where we expect floating-point
/// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
bool mayRaiseFPException() const {
  return hasProperty(MCID::MayRaiseFPException) &&
         !getFlag(MachineInstr::MIFlag::NoFPExcept);
}

//===--------------------------------------------------------------------===//
// Flags that indicate whether an instruction can be modified by a method.
//===--------------------------------------------------------------------===//

/// Return true if this may be a 2- or 3-address
/// instruction (of the form "X = op Y, Z, ..."), which produces the same
/// result if Y and Z are exchanged.  If this flag is set, then the
/// TargetInstrInfo::commuteInstruction method may be used to hack on the
/// instruction.
///
/// Note that this flag may be set on instructions that are only commutable
/// sometimes.  In these cases, the call to commuteInstruction will fail.
/// Also note that some instructions require non-trivial modification to
/// commute them.
bool isCommutable(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::Commutable, Type);
}

/// Return true if this is a 2-address instruction
/// which can be changed into a 3-address instruction if needed.  Doing this
/// transformation can be profitable in the register allocator, because it
/// means that the instruction can use a 2-address form if possible, but
/// degrade into a less efficient form if the source and dest register cannot
/// be assigned to the same register.  For example, this allows the x86
/// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
/// is the same speed as the shift but has bigger code size.
///
/// If this returns true, then the target must implement the
/// TargetInstrInfo::convertToThreeAddress method for this instruction, which
/// is allowed to fail if the transformation isn't valid for this specific
/// instruction (e.g. shl reg, 4 on x86).
///
bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::ConvertibleTo3Addr, Type);
}

/// Return true if this instruction requires
/// custom insertion support when the DAG scheduler is inserting it into a
/// machine basic block.  If this is true for the instruction, it basically
/// means that it is a pseudo instruction used at SelectionDAG time that is
/// expanded out into magic code by the target when MachineInstrs are formed.
///
/// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
/// is used to insert this into the MachineBasicBlock.
bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::UsesCustomInserter, Type);
}

/// Return true if this instruction requires *adjustment*
/// after instruction selection by calling a target hook. For example, this
/// can be used to fill in ARM 's' optional operand depending on whether
/// the conditional flag register is used.
bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
  return hasProperty(MCID::HasPostISelHook, Type);
}

/// Returns true if this instruction is a candidate for remat.
/// This flag is deprecated, please don't use it anymore.  If this
/// flag is set, the isReallyTriviallyReMaterializable() method is called to
/// verify the instruction is really rematable.
bool isRematerializable(QueryType Type = AllInBundle) const {
  // It's only possible to re-mat a bundle if all bundled instructions are
  // re-materializable.
  return hasProperty(MCID::Rematerializable, Type);
}

/// Returns true if this instruction has the same cost (or less) than a move
/// instruction. This is useful during certain types of optimizations
/// (e.g., remat during two-address conversion or machine licm)
/// where we would like to remat or hoist the instruction, but not if it costs
/// more than moving the instruction into the appropriate register. Note, we
/// are not marking copies from and to the same register class with this flag.
bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
  // Only returns true for a bundle if all bundled instructions are cheap.
  return hasProperty(MCID::CheapAsAMove, Type);
}

/// Returns true if this instruction source operands
/// have special register allocation requirements that are not captured by the
/// operand register classes. e.g. ARM::STRD's two source registers must be an
/// even / odd pair, ARM::STM registers have to be in ascending order.
/// Post-register allocation passes should not attempt to change allocations
/// for sources of instructions with this flag.
bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
}

/// Returns true if this instruction def operands
/// have special register allocation requirements that are not captured by the
/// operand register classes. e.g. ARM::LDRD's two def registers must be an
/// even / odd pair, ARM::LDM registers have to be in ascending order.
/// Post-register allocation passes should not attempt to change allocations
/// for definitions of instructions with this flag.
bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
  return hasProperty(MCID::ExtraDefRegAllocReq, Type);
}

enum MICheckType {
  CheckDefs,      // Check all operands for equality
  CheckKillDead,  // Check all operands including kill / dead markers
  IgnoreDefs,     // Ignore all definitions
  IgnoreVRegDefs  // Ignore virtual register definitions
};

/// Return true if this instruction is identical to \p Other.
/// Two instructions are identical if they have the same opcode and all their
/// operands are identical (with respect to MachineOperand::isIdenticalTo()).
/// Note that this means liveness related flags (dead, undef, kill) do not
/// affect the notion of identical.
bool isIdenticalTo(const MachineInstr &Other,
                   MICheckType Check = CheckDefs) const;

/// Unlink 'this' from the containing basic block, and return it without
/// deleting it.
///
/// This function can not be used on bundled instructions, use
/// removeFromBundle() to remove individual instructions from a bundle.
MachineInstr *removeFromParent();

/// Unlink this instruction from its basic block and return it without
/// deleting it.
///
/// If the instruction is part of a bundle, the other instructions in the
/// bundle remain bundled.
MachineInstr *removeFromBundle();

/// Unlink 'this' from the containing basic block and delete it.
///
/// If this instruction is the header of a bundle, the whole bundle is erased.
/// This function can not be used for instructions inside a bundle, use
/// eraseFromBundle() to erase individual bundled instructions.
void eraseFromParent();

/// Unlink 'this' from the containing basic block and delete it.
///
/// For all definitions mark their uses in DBG_VALUE nodes
/// as undefined. Otherwise like eraseFromParent().
void eraseFromParentAndMarkDBGValuesForRemoval();

/// Unlink 'this' form its basic block and delete it.
///
/// If the instruction is part of a bundle, the other instructions in the
/// bundle remain bundled.
void eraseFromBundle();

bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
bool isAnnotationLabel() const {
  return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
}

/// Returns true if the MachineInstr represents a label.
bool isLabel() const {
  return isEHLabel() || isGCLabel() || isAnnotationLabel();
}

bool isCFIInstruction() const {
  return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
}

bool isPseudoProbe() const {
  return getOpcode() == TargetOpcode::PSEUDO_PROBE;
}

// True if the instruction represents a position in the function.
bool isPosition() const { return isLabel() || isCFIInstruction(); }

bool isNonListDebugValue() const {
  return getOpcode() == TargetOpcode::DBG_VALUE;
}
bool isDebugValueList() const {
  return getOpcode() == TargetOpcode::DBG_VALUE_LIST;
}
bool isDebugValue() const {
  return isNonListDebugValue() || isDebugValueList();
}
bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
bool isDebugInstr() const {
  return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
}
bool isDebugOrPseudoInstr() const {
  return isDebugInstr() || isPseudoProbe();
}

bool isDebugOffsetImm() const {
  return isNonListDebugValue() && getDebugOffset().isImm();
}

/// A DBG_VALUE is indirect iff the location operand is a register and
/// the offset operand is an immediate.
bool isIndirectDebugValue() const {
  return isDebugOffsetImm() && getDebugOperand(0).isReg();
}

/// A DBG_VALUE is an entry value iff its debug expression contains the
/// DW_OP_LLVM_entry_value operation.
bool isDebugEntryValue() const;

/// Return true if the instruction is a debug value which describes a part of
/// a variable as unavailable.
bool isUndefDebugValue() const {
  if (!isDebugValue())
    return false;
  // If any $noreg locations are given, this DV is undef.
  for (const MachineOperand &Op : debug_operands())
    if (Op.isReg() && !Op.getReg().isValid())
      return true;
  return false;
}

bool isPHI() const {
  return getOpcode() == TargetOpcode::PHI ||
         getOpcode() == TargetOpcode::G_PHI;
}
bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
bool isInlineAsm() const {
  return getOpcode() == TargetOpcode::INLINEASM ||
         getOpcode() == TargetOpcode::INLINEASM_BR;
}

/// FIXME: Seems like a layering violation that the AsmDialect, which is X86
/// specific, be attached to a generic MachineInstr.
bool isMSInlineAsm() const {
  return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
}

bool isStackAligningInlineAsm() const;
InlineAsm::AsmDialect getInlineAsmDialect() const;

bool isInsertSubreg() const {
  return getOpcode() == TargetOpcode::INSERT_SUBREG;
}

bool isSubregToReg() const {
  return getOpcode() == TargetOpcode::SUBREG_TO_REG;
}

bool isRegSequence() const {
  return getOpcode() == TargetOpcode::REG_SEQUENCE;
}

bool isBundle() const {
  return getOpcode() == TargetOpcode::BUNDLE;
}

bool isCopy() const {
  return getOpcode() == TargetOpcode::COPY;
}

bool isFullCopy() const {
  return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
}

bool isExtractSubreg() const {
  return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
}

/// Return true if the instruction behaves like a copy.
/// This does not include native copy instructions.
bool isCopyLike() const {
  return isCopy() || isSubregToReg();
}

/// Return true is the instruction is an identity copy.
bool isIdentityCopy() const {
  return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
    getOperand(0).getSubReg() == getOperand(1).getSubReg();
}

/// Return true if this instruction doesn't produce any output in the form of
/// executable instructions.
bool isMetaInstruction() const {
  switch (getOpcode()) {
  default:
    return false;
  case TargetOpcode::IMPLICIT_DEF:
  case TargetOpcode::KILL:
  case TargetOpcode::CFI_INSTRUCTION:
  case TargetOpcode::EH_LABEL:
  case TargetOpcode::GC_LABEL:
  case TargetOpcode::DBG_VALUE:
  case TargetOpcode::DBG_VALUE_LIST:
  case TargetOpcode::DBG_INSTR_REF:
  case TargetOpcode::DBG_PHI:
  case TargetOpcode::DBG_LABEL:
  case TargetOpcode::LIFETIME_START:
  case TargetOpcode::LIFETIME_END:
  case TargetOpcode::PSEUDO_PROBE:
    return true;
  }
}

/// Return true if this is a transient instruction that is either very likely
/// to be eliminated during register allocation (such as copy-like
/// instructions), or if this instruction doesn't have an execution-time cost.
bool isTransient() const {
  switch (getOpcode()) {
  default:
    return isMetaInstruction();
  // Copy-like instructions are usually eliminated during register allocation.
  case TargetOpcode::PHI:
  case TargetOpcode::G_PHI:
  case TargetOpcode::COPY:
  case TargetOpcode::INSERT_SUBREG:
  case TargetOpcode::SUBREG_TO_REG:
  case TargetOpcode::REG_SEQUENCE:
    return true;
  }
}

/// Return the number of instructions inside the MI bundle, excluding the
/// bundle header.
///
/// This is the number of instructions that MachineBasicBlock::iterator
/// skips, 0 for unbundled instructions.
unsigned getBundleSize() const;

/// Return true if the MachineInstr reads the specified register.
/// If TargetRegisterInfo is passed, then it also checks if there
/// is a read of a super-register.
/// This does not count partial redefines of virtual registers as reads:
///   %reg1024:6 = OP.
bool readsRegister(Register Reg,
                   const TargetRegisterInfo *TRI = nullptr) const {
  return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
}

/// Return true if the MachineInstr reads the specified virtual register.
/// Take into account that a partial define is a
/// read-modify-write operation.
bool readsVirtualRegister(Register Reg) const {
  return readsWritesVirtualRegister(Reg).first;
}

/// Return a pair of bools (reads, writes) indicating if this instruction
/// reads or writes Reg. This also considers partial defines.
/// If Ops is not null, all operand indices for Reg are added.
std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
                              SmallVectorImpl<unsigned> *Ops = nullptr) const;

/// Return true if the MachineInstr kills the specified register.
/// If TargetRegisterInfo is passed, then it also checks if there is
/// a kill of a super-register.
bool killsRegister(Register Reg,
                   const TargetRegisterInfo *TRI = nullptr) const {
  return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
}

/// Return true if the MachineInstr fully defines the specified register.
/// If TargetRegisterInfo is passed, then it also checks
/// if there is a def of a super-register.
/// NOTE: It's ignoring subreg indices on virtual registers.
bool definesRegister(Register Reg,
                     const TargetRegisterInfo *TRI = nullptr) const {
  return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
}

/// Return true if the MachineInstr modifies (fully define or partially
/// define) the specified register.
/// NOTE: It's ignoring subreg indices on virtual registers.
bool modifiesRegister(Register Reg,
                      const TargetRegisterInfo *TRI = nullptr) const {
  return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
}

/// Returns true if the register is dead in this machine instruction.
/// If TargetRegisterInfo is passed, then it also checks
/// if there is a dead def of a super-register.
bool registerDefIsDead(Register Reg,
                       const TargetRegisterInfo *TRI = nullptr) const {
  return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
}

/// Returns true if the MachineInstr has an implicit-use operand of exactly
/// the given register (not considering sub/super-registers).
bool hasRegisterImplicitUseOperand(Register Reg) const;

/// Returns the operand index that is a use of the specific register or -1
/// if it is not found. It further tightens the search criteria to a use
/// that kills the register if isKill is true.
int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
                              const TargetRegisterInfo *TRI = nullptr) const;

/// Wrapper for findRegisterUseOperandIdx, it returns
/// a pointer to the MachineOperand rather than an index.
MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
                                    const TargetRegisterInfo *TRI = nullptr) {
  int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
  return (Idx == -1) ? nullptr : &getOperand(Idx);
}

const MachineOperand *findRegisterUseOperand(
  Register Reg, bool isKill = false,
  const TargetRegisterInfo *TRI = nullptr) const {
  return const_cast<MachineInstr *>(this)->
    findRegisterUseOperand(Reg, isKill, TRI);
}

/// Returns the operand index that is a def of the specified register or
/// -1 if it is not found. If isDead is true, defs that are not dead are
/// skipped. If Overlap is true, then it also looks for defs that merely
/// overlap the specified register. If TargetRegisterInfo is non-null,
/// then it also checks if there is a def of a super-register.
/// This may also return a register mask operand when Overlap is true.
int findRegisterDefOperandIdx(Register Reg,
                              bool isDead = false, bool Overlap = false,
                              const TargetRegisterInfo *TRI = nullptr) const;

/// Wrapper for findRegisterDefOperandIdx, it returns
/// a pointer to the MachineOperand rather than an index.
MachineOperand *
findRegisterDefOperand(Register Reg, bool isDead = false,
                       bool Overlap = false,
                       const TargetRegisterInfo *TRI = nullptr) {
  int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
  return (Idx == -1) ? nullptr : &getOperand(Idx);
}

const MachineOperand *
findRegisterDefOperand(Register Reg, bool isDead = false,
                       bool Overlap = false,
                       const TargetRegisterInfo *TRI = nullptr) const {
  return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
      Reg, isDead, Overlap, TRI);
}

/// Find the index of the first operand in the
/// operand list that is used to represent the predicate. It returns -1 if
/// none is found.
int findFirstPredOperandIdx() const;

/// Find the index of the flag word operand that
/// corresponds to operand OpIdx on an inline asm instruction.  Returns -1 if
/// getOperand(OpIdx) does not belong to an inline asm operand group.
///
/// If GroupNo is not NULL, it will receive the number of the operand group
/// containing OpIdx.
int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;

/// Compute the static register class constraint for operand OpIdx.
/// For normal instructions, this is derived from the MCInstrDesc.
/// For inline assembly it is derived from the flag words.
///
/// Returns NULL if the static register class constraint cannot be
/// determined.
const TargetRegisterClass*
getRegClassConstraint(unsigned OpIdx,
                      const TargetInstrInfo *TII,
                      const TargetRegisterInfo *TRI) const;

/// Applies the constraints (def/use) implied by this MI on \p Reg to
/// the given \p CurRC.
/// If \p ExploreBundle is set and MI is part of a bundle, all the
/// instructions inside the bundle will be taken into account. In other words,
/// this method accumulates all the constraints of the operand of this MI and
/// the related bundle if MI is a bundle or inside a bundle.
///
/// Returns the register class that satisfies both \p CurRC and the
/// constraints set by MI. Returns NULL if such a register class does not
/// exist.
///
/// \pre CurRC must not be NULL.
const TargetRegisterClass *getRegClassConstraintEffectForVReg(
    Register Reg, const TargetRegisterClass *CurRC,
    const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
    bool ExploreBundle = false) const;

/// Applies the constraints (def/use) implied by the \p OpIdx operand
/// to the given \p CurRC.
///
/// Returns the register class that satisfies both \p CurRC and the
/// constraints set by \p OpIdx MI. Returns NULL if such a register class
/// does not exist.
///
/// \pre CurRC must not be NULL.
/// \pre The operand at \p OpIdx must be a register.
const TargetRegisterClass *
getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
                            const TargetInstrInfo *TII,
                            const TargetRegisterInfo *TRI) const;

/// Add a tie between the register operands at DefIdx and UseIdx.
/// The tie will cause the register allocator to ensure that the two
/// operands are assigned the same physical register.
///
/// Tied operands are managed automatically for explicit operands in the
/// MCInstrDesc. This method is for exceptional cases like inline asm.
void tieOperands(unsigned DefIdx, unsigned UseIdx);

/// Given the index of a tied register operand, find the
/// operand it is tied to. Defs are tied to uses and vice versa. Returns the
/// index of the tied operand which must exist.
unsigned findTiedOperandIdx(unsigned OpIdx) const;

/// Given the index of a register def operand,
/// check if the register def is tied to a source operand, due to either
/// two-address elimination or inline assembly constraints. Returns the
/// first tied use operand index by reference if UseOpIdx is not null.
bool isRegTiedToUseOperand(unsigned DefOpIdx,
                           unsigned *UseOpIdx = nullptr) const {
  const MachineOperand &MO = getOperand(DefOpIdx);
  if (!MO.isReg() || !MO.isDef() || !MO.isTied())
    return false;
  if (UseOpIdx)
    *UseOpIdx = findTiedOperandIdx(DefOpIdx);
  return true;
}

/// Return true if the use operand of the specified index is tied to a def
/// operand. It also returns the def operand index by reference if DefOpIdx
/// is not null.
bool isRegTiedToDefOperand(unsigned UseOpIdx,
                           unsigned *DefOpIdx = nullptr) const {
  const MachineOperand &MO = getOperand(UseOpIdx);
  if (!MO.isReg() || !MO.isUse() || !MO.isTied())
    return false;
  if (DefOpIdx)
    *DefOpIdx = findTiedOperandIdx(UseOpIdx);
  return true;
}

/// Clears kill flags on all operands.
void clearKillInfo();

/// Replace all occurrences of FromReg with ToReg:SubIdx,
/// properly composing subreg indices where necessary.
void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
                        const TargetRegisterInfo &RegInfo);

/// We have determined MI kills a register. Look for the
/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
/// add a implicit operand if it's not found. Returns true if the operand
/// exists / is added.
bool addRegisterKilled(Register IncomingReg,
                       const TargetRegisterInfo *RegInfo,
                       bool AddIfNotFound = false);

/// Clear all kill flags affecting Reg.  If RegInfo is provided, this includes
/// all aliasing registers.
void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);

/// We have determined MI defined a register without a use.
/// Look for the operand that defines it and mark it as IsDead. If
/// AddIfNotFound is true, add a implicit operand if it's not found. Returns
/// true if the operand exists / is added.
bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
                     bool AddIfNotFound = false);

/// Clear all dead flags on operands defining register @p Reg.
void clearRegisterDeads(Register Reg);

/// Mark all subregister defs of register @p Reg with the undef flag.
/// This function is used when we determined to have a subregister def in an
/// otherwise undefined super register.
void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);

/// We have determined MI defines a register. Make sure there is an operand
/// defining Reg.
void addRegisterDefined(Register Reg,
                        const TargetRegisterInfo *RegInfo = nullptr);

/// Mark every physreg used by this instruction as
/// dead except those in the UsedRegs list.
///
/// On instructions with register mask operands, also add implicit-def
/// operands for all registers in UsedRegs.
void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
                           const TargetRegisterInfo &TRI);

/// Return true if it is safe to move this instruction. If
/// SawStore is set to true, it means that there is a store (or call) between
/// the instruction's location and its intended destination.
bool isSafeToMove(AAResults *AA, bool &SawStore) const;

/// Returns true if this instruction's memory access aliases the memory
/// access of Other.
//
/// Assumes any physical registers used to compute addresses
/// have the same value for both instructions.  Returns false if neither
/// instruction writes to memory.
///
/// @param AA Optional alias analysis, used to compare memory operands.
/// @param Other MachineInstr to check aliasing against.
/// @param UseTBAA Whether to pass TBAA information to alias analysis.
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;

/// Return true if this instruction may have an ordered
/// or volatile memory reference, or if the information describing the memory
/// reference is not available. Return false if it is known to have no
/// ordered or volatile memory references.
bool hasOrderedMemoryRef() const;

/// Return true if this load instruction never traps and points to a memory
/// location whose value doesn't change during the execution of this function.
///
/// Examples include loading a value from the constant pool or from the
/// argument area of a function (if it does not change).  If the instruction
/// does multiple loads, this returns true only if all of the loads are
/// dereferenceable and invariant.
bool isDereferenceableInvariantLoad(AAResults *AA) const;

/// If the specified instruction is a PHI that always merges together the
/// same virtual register, return the register, otherwise return 0.
unsigned isConstantValuePHI() const;

/// Return true if this instruction has side effects that are not modeled
/// by mayLoad / mayStore, etc.
/// For all instructions, the property is encoded in MCInstrDesc::Flags
/// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
/// INLINEASM instruction, in which case the side effect property is encoded
/// in one of its operands (see InlineAsm::Extra_HasSideEffect).
///
bool hasUnmodeledSideEffects() const;

/// Returns true if it is illegal to fold a load across this instruction.
bool isLoadFoldBarrier() const;

/// Return true if all the defs of this instruction are dead.
bool allDefsAreDead() const;

/// Return a valid size if the instruction is a spill instruction.
Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;

/// Return a valid size if the instruction is a folded spill instruction.
Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;

/// Return a valid size if the instruction is a restore instruction.
Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;

/// Return a valid size if the instruction is a folded restore instruction.
Optional<unsigned>
getFoldedRestoreSize(const TargetInstrInfo *TII) const;

/// Copy implicit register operands from specified
/// instruction to this instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);

/// Debugging support
/// @{
/// Determine the generic type to be printed (if needed) on uses and defs.
LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
                   const MachineRegisterInfo &MRI) const;

/// Return true when an instruction has tied register that can't be determined
/// by the instruction's descriptor. This is useful for MIR printing, to
/// determine whether we need to print the ties or not.
bool hasComplexRegisterTies() const;

/// Print this MI to \p OS.
/// Don't print information that can be inferred from other instructions if
/// \p IsStandalone is false. It is usually true when only a fragment of the
/// function is printed.
/// Only print the defs and the opcode if \p SkipOpers is true.
/// Otherwise, also print operands if \p SkipDebugLoc is true.
/// Otherwise, also print the debug loc, with a terminating newline.
/// \p TII is used to print the opcode name.  If it's not present, but the
/// MI is in a function, the opcode will be printed using the function's TII.
void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
           bool SkipDebugLoc = false, bool AddNewLine = true,
           const TargetInstrInfo *TII = nullptr) const;
void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
           bool SkipOpers = false, bool SkipDebugLoc = false,
           bool AddNewLine = true,
           const TargetInstrInfo *TII = nullptr) const;
void dump() const;
/// Print on dbgs() the current instruction and the instructions defining its
/// operands and so on until we reach \p MaxDepth.
void dumpr(const MachineRegisterInfo &MRI,
           unsigned MaxDepth = UINT_MAX(2147483647 *2U +1U)) const;
/// @}

//===--------------------------------------------------------------------===//
// Accessors used to build up machine instructions.

/// Add the specified operand to the instruction.  If it is an implicit
/// operand, it is added to the end of the operand list.  If it is an
/// explicit operand it is added at the end of the explicit operand list
/// (before the first implicit operand).
///
/// MF must be the machine function that was used to allocate this
/// instruction.
///
/// MachineInstrBuilder provides a more convenient interface for creating
/// instructions and adding operands.
void addOperand(MachineFunction &MF, const MachineOperand &Op);

/// Add an operand without providing an MF reference. This only works for
/// instructions that are inserted in a basic block.
///
/// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
/// preferred.
void addOperand(const MachineOperand &Op);

/// Replace the instruction descriptor (thus opcode) of
/// the current instruction with a new one.
void setDesc(const MCInstrDesc &tid) { MCID = &tid; }

/// Replace current source information with new such.
/// Avoid using this, the constructor argument is preferable.
void setDebugLoc(DebugLoc dl) {
  debugLoc = std::move(dl);
  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast<void> (0));
}

/// Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with.
void RemoveOperand(unsigned OpNo);

/// Clear this MachineInstr's memory reference descriptor list.  This resets
/// the memrefs to their most conservative state.  This should be used only
/// as a last resort since it greatly pessimizes our knowledge of the memory
/// access performed by the instruction.
void dropMemRefs(MachineFunction &MF);

/// Assign this MachineInstr's memory reference descriptor list.
///
/// Unlike other methods, this *will* allocate them into a new array
/// associated with the provided `MachineFunction`.
void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);

/// Add a MachineMemOperand to the machine instruction.
/// This function should be used only occasionally. The setMemRefs function
/// is the primary method for setting up a MachineInstr's MemRefs list.
void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);

/// Clone another MachineInstr's memory reference descriptor list and replace
/// ours with it.
///
/// Note that `*this` may be the incoming MI!
///
/// Prefer this API whenever possible as it can avoid allocations in common
/// cases.
void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);

/// Clone the merge of multiple MachineInstrs' memory reference descriptors
/// list and replace ours with it.
///
/// Note that `*this` may be one of the incoming MIs!
///
/// Prefer this API whenever possible as it can avoid allocations in common
/// cases.
void cloneMergedMemRefs(MachineFunction &MF,
                        ArrayRef<const MachineInstr *> MIs);

/// Set a symbol that will be emitted just prior to the instruction itself.
///
/// Setting this to a null pointer will remove any such symbol.
///
/// FIXME: This is not fully implemented yet.
void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);

/// Set a symbol that will be emitted just after the instruction itself.
///
/// Setting this to a null pointer will remove any such symbol.
///
/// FIXME: This is not fully implemented yet.
void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);

/// Clone another MachineInstr's pre- and post- instruction symbols and
/// replace ours with it.
void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);

/// Set a marker on instructions that denotes where we should create and emit
/// heap alloc site labels. This waits until after instruction selection and
/// optimizations to create the label, so it should still work if the
/// instruction is removed or duplicated.
void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);

/// Return the MIFlags which represent both MachineInstrs. This
/// should be used when merging two MachineInstrs into one. This routine does
/// not modify the MIFlags of this MachineInstr.
uint16_t mergeFlagsWith(const MachineInstr& Other) const;

static uint16_t copyFlagsFromInstruction(const Instruction &I);

/// Copy all flags to MachineInst MIFlags
void copyIRFlags(const Instruction &I);

/// Break any tie involving OpIdx.
void untieRegOperand(unsigned OpIdx) {
  MachineOperand &MO = getOperand(OpIdx);
  if (MO.isReg() && MO.isTied()) {
    getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
    MO.TiedTo = 0;
  }
}

/// Add all implicit def and use operands to this instruction.
void addImplicitDefUseOperands(MachineFunction &MF);

/// Scan instructions immediately following MI and collect any matching
/// DBG_VALUEs.
void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);

/// Find all DBG_VALUEs that point to the register def in this instruction
/// and point them to \p Reg instead.
void changeDebugValuesDefReg(Register Reg);

/// Returns the Intrinsic::ID for this instruction.
/// \pre Must have an intrinsic ID operand.
unsigned getIntrinsicID() const {
  return getOperand(getNumExplicitDefs()).getIntrinsicID();
}

/// Sets all register debug operands in this debug value instruction to be
/// undef.
void setDebugValueUndef() {
  assert(isDebugValue() && "Must be a debug value instruction.")(static_cast<void> (0));
  for (MachineOperand &MO : debug_operands()) {
    if (MO.isReg()) {
      MO.setReg(0);
      MO.setSubReg(0);
    }
  }
}

1862private:
/// If this instruction is embedded into a MachineFunction, return the
/// MachineRegisterInfo object for the current function, otherwise
/// return null.
MachineRegisterInfo *getRegInfo();

/// Unlink all of the register operands in this instruction from their
/// respective use lists.  This requires that the operands already be on their
/// use lists.
void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);

/// Add all of the register operands in this instruction from their
/// respective use lists.  This requires that the operands not be on their
/// use lists yet.
void AddRegOperandsToUseLists(MachineRegisterInfo&);

/// Slow path for hasProperty when we're dealing with a bundle.
bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;

/// Implements the logic of getRegClassConstraintEffectForVReg for the
/// this MI and the given operand index \p OpIdx.
/// If the related operand does not constrained Reg, this returns CurRC.
const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
    unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
    const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;

/// Stores extra instruction information inline or allocates as ExtraInfo
/// based on the number of pointers.
void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
                  MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
                  MDNode *HeapAllocMarker);
1893};

1895/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1896/// instruction rather than by pointer value.
1897/// The hashing and equality testing functions ignore definitions so this is
1898/// useful for CSE, etc.
1899struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
static inline MachineInstr *getEmptyKey() {
  return nullptr;
}

static inline MachineInstr *getTombstoneKey() {
  return reinterpret_cast<MachineInstr*>(-1);
}

static unsigned getHashValue(const MachineInstr* const &MI);

static bool isEqual(const MachineInstr* const &LHS,
                    const MachineInstr* const &RHS) {
  if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
      LHS == getEmptyKey() || LHS == getTombstoneKey())
    return LHS == RHS;
  return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
}
1917};

1919//===----------------------------------------------------------------------===//
1920// Debugging Support

1922inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
MI.print(OS);
return OS;
1925}

1927} // end namespace llvm

1929#endif // LLVM_CODEGEN_MACHINEINSTR_H

←

/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include/llvm/CodeGen/MachineInstrBuilder.h

1//===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file exposes a function named BuildMI, which is useful for dramatically
10// simplifying how MachineInstr's are created.  It allows use of code like this:
11//
12//   M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
13//           .addReg(argVal1)
14//           .addReg(argVal2);
15//
16//===----------------------------------------------------------------------===//

18#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
19#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H

21#include "llvm/ADT/ArrayRef.h"
22#include "llvm/CodeGen/GlobalISel/Utils.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstr.h"
26#include "llvm/CodeGen/MachineInstrBundle.h"
27#include "llvm/CodeGen/MachineOperand.h"
28#include "llvm/CodeGen/TargetRegisterInfo.h"
29#include "llvm/IR/InstrTypes.h"
30#include "llvm/IR/Intrinsics.h"
31#include "llvm/Support/ErrorHandling.h"
32#include <cassert>
33#include <cstdint>

35namespace llvm {

37class MCInstrDesc;
38class MDNode;

40namespace RegState {

42enum {
/// Register definition.
Define = 0x2,
/// Not emitted register (e.g. carry, or temporary result).
Implicit = 0x4,
/// The last use of a register.
Kill = 0x8,
/// Unused definition.
Dead = 0x10,
/// Value of the register doesn't matter.
Undef = 0x20,
/// Register definition happens before uses.
EarlyClobber = 0x40,
/// Register 'use' is for debugging purpose.
Debug = 0x80,
/// Register reads a value that is defined inside the same instruction or
/// bundle.
InternalRead = 0x100,
/// Register that may be renamed.
Renamable = 0x200,
DefineNoRead = Define | Undef,
ImplicitDefine = Implicit | Define,
ImplicitKill = Implicit | Kill
65};

67} // end namespace RegState

69class MachineInstrBuilder {
MachineFunction *MF = nullptr;
MachineInstr *MI = nullptr;

73public:
MachineInstrBuilder() = default;

/// Create a MachineInstrBuilder for manipulating an existing instruction.
/// F must be the machine function that was used to allocate I.
MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
    : MF(&F), MI(&*I) {}

/// Allow automatic conversion to the machine instruction we are working on.
operator MachineInstr*() const { return MI; }
MachineInstr *operator->() const { return MI; }
operator MachineBasicBlock::iterator() const { return MI; }

/// If conversion operators fail, use this method to get the MachineInstr
/// explicitly.
MachineInstr *getInstr() const { return MI; }

/// Get the register for the operand index.
/// The operand at the index should be a register (asserted by
/// MachineOperand).
Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }

/// Add a new virtual register operand.
const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0,
                                  unsigned SubReg = 0) const {
  assert((flags & 0x1) == 0 &&(static_cast<void> (0))
         "Passing in 'true' to addReg is forbidden! Use enums instead.")(static_cast<void> (0));
  MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
                                             flags & RegState::Define,
                                             flags & RegState::Implicit,
                                             flags & RegState::Kill,
                                             flags & RegState::Dead,
                                             flags & RegState::Undef,
                                             flags & RegState::EarlyClobber,
                                             SubReg,
                                             flags & RegState::Debug,
                                             flags & RegState::InternalRead,
                                             flags & RegState::Renamable));
  return *this;
}

/// Add a virtual register definition operand.
const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
                                  unsigned SubReg = 0) const {
  return addReg(RegNo, Flags | RegState::Define, SubReg);
}

/// Add a virtual register use operand. It is an error for Flags to contain
/// `RegState::Define` when calling this function.
const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
                                  unsigned SubReg = 0) const {
  assert(!(Flags & RegState::Define) &&(static_cast<void> (0))
         "Misleading addUse defines register, use addReg instead.")(static_cast<void> (0));
  return addReg(RegNo, Flags, SubReg);
}

/// Add a new immediate operand.
const MachineInstrBuilder &addImm(int64_t Val) const {
  MI->addOperand(*MF, MachineOperand::CreateImm(Val));
  return *this;
}

const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
  MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
  return *this;
}

const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
  MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
  return *this;
}

const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
                                  unsigned TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addFrameIndex(int Idx) const {
  MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
  return *this;
}

const MachineInstrBuilder &
addConstantPoolIndex(unsigned Idx, int Offset = 0,
                     unsigned TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
                                        unsigned TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
                                                        TargetFlags));
  return *this;
}

const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
                                             unsigned TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
                                            int64_t Offset = 0,
                                            unsigned TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addExternalSymbol(const char *FnName,
                                             unsigned TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA,
                                           int64_t Offset = 0,
                                           unsigned TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
  return *this;
}

const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
  MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
  return *this;
}

const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
  MI->addMemOperand(*MF, MMO);
  return *this;
}

const MachineInstrBuilder &
setMemRefs(ArrayRef<MachineMemOperand *> MMOs) const {
  MI->setMemRefs(*MF, MMOs);
  return *this;
}

const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
  MI->cloneMemRefs(*MF, OtherMI);
  return *this;
}

const MachineInstrBuilder &
cloneMergedMemRefs(ArrayRef<const MachineInstr *> OtherMIs) const {
  MI->cloneMergedMemRefs(*MF, OtherMIs);
  return *this;
}

const MachineInstrBuilder &add(const MachineOperand &MO) const {
  MI->addOperand(*MF, MO);
  return *this;
}

const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
  for (const MachineOperand &MO : MOs) {
    MI->addOperand(*MF, MO);
  }
  return *this;
}

const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
  MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
  assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())(static_cast<void> (0))
                             : true) &&(static_cast<void> (0))
         "first MDNode argument of a DBG_VALUE not a variable")(static_cast<void> (0));
  assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())(static_cast<void> (0))
                             : true) &&(static_cast<void> (0))
         "first MDNode argument of a DBG_LABEL not a label")(static_cast<void> (0));
  return *this;
}

const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
  MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
  return *this;
}

const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const {
  MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
  return *this;
}

const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const {
  MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
  return *this;
}

const MachineInstrBuilder &addShuffleMask(ArrayRef<int> Val) const {
  MI->addOperand(*MF, MachineOperand::CreateShuffleMask(Val));
  return *this;
}

const MachineInstrBuilder &addSym(MCSymbol *Sym,
                                  unsigned char TargetFlags = 0) const {
  MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
  return *this;
}

const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
  MI->setFlags(Flags);
  return *this;
}

const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
  MI->setFlag(Flag);
  return *this;
}

// Add a displacement from an existing MachineOperand with an added offset.
const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
                                   unsigned char TargetFlags = 0) const {
  // If caller specifies new TargetFlags then use it, otherwise the
  // default behavior is to copy the target flags from the existing
  // MachineOperand. This means if the caller wants to clear the
  // target flags it needs to do so explicitly.
  if (0 == TargetFlags)
    TargetFlags = Disp.getTargetFlags();

  switch (Disp.getType()) {
    default:
      llvm_unreachable("Unhandled operand type in addDisp()")__builtin_unreachable();
    case MachineOperand::MO_Immediate:
      return addImm(Disp.getImm() + off);
    case MachineOperand::MO_ConstantPoolIndex:
      return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
                                  TargetFlags);
    case MachineOperand::MO_GlobalAddress:
      return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
                              TargetFlags);
    case MachineOperand::MO_BlockAddress:
      return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off,
                             TargetFlags);
    case MachineOperand::MO_JumpTableIndex:
      assert(off == 0 && "cannot create offset into jump tables")(static_cast<void> (0));
      return addJumpTableIndex(Disp.getIndex(), TargetFlags);
  }
}

/// Copy all the implicit operands from OtherMI onto this one.
const MachineInstrBuilder &
copyImplicitOps(const MachineInstr &OtherMI) const {
  MI->copyImplicitOps(*MF, OtherMI);
  return *this;
}

bool constrainAllUses(const TargetInstrInfo &TII,
                      const TargetRegisterInfo &TRI,
                      const RegisterBankInfo &RBI) const {
  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
}
325};

327/// Builder interface. Specify how to create the initial instruction itself.
328inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
331}

333/// This version of the builder sets up the first operand as a
334/// destination virtual register.
335inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                                 const MCInstrDesc &MCID, Register DestReg) {
return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
         .addReg(DestReg, RegState::Define);
339}

341/// This version of the builder inserts the newly-built instruction before
342/// the given position in the given MachineBasicBlock, and sets up the first
343/// operand as a destination virtual register.
344inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                 MachineBasicBlock::iterator I,
                                 const DebugLoc &DL, const MCInstrDesc &MCID,
                                 Register DestReg) {
MachineFunction &MF = *BB.getParent();
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
BB.insert(I, MI);
return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
352}

354/// This version of the builder inserts the newly-built instruction before
355/// the given position in the given MachineBasicBlock, and sets up the first
356/// operand as a destination virtual register.
357///
358/// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
359/// added to the same bundle.
360inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                 MachineBasicBlock::instr_iterator I,
                                 const DebugLoc &DL, const MCInstrDesc &MCID,
                                 Register DestReg) {
MachineFunction &MF = *BB.getParent();
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
BB.insert(I, MI);
return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
368}

370inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
                                 const DebugLoc &DL, const MCInstrDesc &MCID,
                                 Register DestReg) {
// Calling the overload for instr_iterator is always correct.  However, the
// definition is not available in headers, so inline the check.
if (I.isInsideBundle())
  return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg);
return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
378}

380inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
                                 const DebugLoc &DL, const MCInstrDesc &MCID,
                                 Register DestReg) {
return BuildMI(BB, *I, DL, MCID, DestReg);
384}

386/// This version of the builder inserts the newly-built instruction before the
387/// given position in the given MachineBasicBlock, and does NOT take a
388/// destination register.
389inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                 MachineBasicBlock::iterator I,
                                 const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
MachineFunction &MF = *BB.getParent();
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
BB.insert(I, MI);
return MachineInstrBuilder(MF, MI);
397}

399inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                 MachineBasicBlock::instr_iterator I,
                                 const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
MachineFunction &MF = *BB.getParent();
MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
BB.insert(I, MI);
return MachineInstrBuilder(MF, MI);
407}

409inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
                                 const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
// Calling the overload for instr_iterator is always correct.  However, the
// definition is not available in headers, so inline the check.
if (I.isInsideBundle())
  return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID);
return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID);
417}

419inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
                                 const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
return BuildMI(BB, *I, DL, MCID);
37
←
Forming reference to null pointer
423}

425/// This version of the builder inserts the newly-built instruction at the end
426/// of the given MachineBasicBlock, and does NOT take a destination register.
427inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
                                 const MCInstrDesc &MCID) {
return BuildMI(*BB, BB->end(), DL, MCID);
430}

432/// This version of the builder inserts the newly-built instruction at the
433/// end of the given MachineBasicBlock, and sets up the first operand as a
434/// destination virtual register.
435inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
                                 const MCInstrDesc &MCID, Register DestReg) {
return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
438}

440/// This version of the builder builds a DBG_VALUE intrinsic
441/// for either a value in a register or a register-indirect
442/// address.  The convention is that a DBG_VALUE is indirect iff the
443/// second operand is an immediate.
444MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                          const MCInstrDesc &MCID, bool IsIndirect,
                          Register Reg, const MDNode *Variable,
                          const MDNode *Expr);

449/// This version of the builder builds a DBG_VALUE intrinsic
450/// for a MachineOperand.
451MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                          const MCInstrDesc &MCID, bool IsIndirect,
                          const MachineOperand &MO, const MDNode *Variable,
                          const MDNode *Expr);

456/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
457/// for a MachineOperand.
458MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
                          const MCInstrDesc &MCID, bool IsIndirect,
                          ArrayRef<MachineOperand> MOs,
                          const MDNode *Variable, const MDNode *Expr);

463/// This version of the builder builds a DBG_VALUE intrinsic
464/// for either a value in a register or a register-indirect
465/// address and inserts it at position I.
466MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                          MachineBasicBlock::iterator I, const DebugLoc &DL,
                          const MCInstrDesc &MCID, bool IsIndirect,
                          Register Reg, const MDNode *Variable,
                          const MDNode *Expr);

472/// This version of the builder builds a DBG_VALUE intrinsic
473/// for a machine operand and inserts it at position I.
474MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                          MachineBasicBlock::iterator I, const DebugLoc &DL,
                          const MCInstrDesc &MCID, bool IsIndirect,
                          MachineOperand &MO, const MDNode *Variable,
                          const MDNode *Expr);

480/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
481/// for a machine operand and inserts it at position I.
482MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                          MachineBasicBlock::iterator I, const DebugLoc &DL,
                          const MCInstrDesc &MCID, bool IsIndirect,
                          ArrayRef<MachineOperand> MOs,
                          const MDNode *Variable, const MDNode *Expr);

488/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
489MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
                                  MachineBasicBlock::iterator I,
                                  const MachineInstr &Orig, int FrameIndex,
                                  Register SpillReg);
493MachineInstr *
494buildDbgValueForSpill(MachineBasicBlock &BB, MachineBasicBlock::iterator I,
                    const MachineInstr &Orig, int FrameIndex,
                    SmallVectorImpl<const MachineOperand *> &SpilledOperands);

498/// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
499/// modifying an instruction in place while iterating over a basic block.
500void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex, Register Reg);

502inline unsigned getDefRegState(bool B) {
return B ? RegState::Define : 0;
504}
505inline unsigned getImplRegState(bool B) {
return B ? RegState::Implicit : 0;
507}
508inline unsigned getKillRegState(bool B) {
return B ? RegState::Kill : 0;
510}
511inline unsigned getDeadRegState(bool B) {
return B ? RegState::Dead : 0;
513}
514inline unsigned getUndefRegState(bool B) {
return B ? RegState::Undef : 0;
516}
517inline unsigned getInternalReadRegState(bool B) {
return B ? RegState::InternalRead : 0;
519}
520inline unsigned getDebugRegState(bool B) {
return B ? RegState::Debug : 0;
522}
523inline unsigned getRenamableRegState(bool B) {
return B ? RegState::Renamable : 0;
525}

527/// Get all register state flags from machine operand \p RegOp.
528inline unsigned getRegState(const MachineOperand &RegOp) {
assert(RegOp.isReg() && "Not a register operand")(static_cast<void> (0));
return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) |
       getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
       getUndefRegState(RegOp.isUndef()) |
       getInternalReadRegState(RegOp.isInternalRead()) |
       getDebugRegState(RegOp.isDebug()) |
       getRenamableRegState(Register::isPhysicalRegister(RegOp.getReg()) &&
                            RegOp.isRenamable());
537}

539/// Helper class for constructing bundles of MachineInstrs.
540///
541/// MIBundleBuilder can create a bundle from scratch by inserting new
542/// MachineInstrs one at a time, or it can create a bundle from a sequence of
543/// existing MachineInstrs in a basic block.
544class MIBundleBuilder {
MachineBasicBlock &MBB;
MachineBasicBlock::instr_iterator Begin;
MachineBasicBlock::instr_iterator End;

549public:
/// Create an MIBundleBuilder that inserts instructions into a new bundle in
/// BB above the bundle or instruction at Pos.
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
    : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}

/// Create a bundle from the sequence of instructions between B and E.
MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B,
                MachineBasicBlock::iterator E)
    : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
  assert(B != E && "No instructions to bundle")(static_cast<void> (0));
  ++B;
  while (B != E) {
    MachineInstr &MI = *B;
    ++B;
    MI.bundleWithPred();
  }
}

/// Create an MIBundleBuilder representing an existing instruction or bundle
/// that has MI as its head.
explicit MIBundleBuilder(MachineInstr *MI)
    : MBB(*MI->getParent()), Begin(MI),
      End(getBundleEnd(MI->getIterator())) {}

/// Return a reference to the basic block containing this bundle.
MachineBasicBlock &getMBB() const { return MBB; }

/// Return true if no instructions have been inserted in this bundle yet.
/// Empty bundles aren't representable in a MachineBasicBlock.
bool empty() const { return Begin == End; }

/// Return an iterator to the first bundled instruction.
MachineBasicBlock::instr_iterator begin() const { return Begin; }

/// Return an iterator beyond the last bundled instruction.
MachineBasicBlock::instr_iterator end() const { return End; }

/// Insert MI into this bundle before I which must point to an instruction in
/// the bundle, or end().
MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I,
                        MachineInstr *MI) {
  MBB.insert(I, MI);
  if (I == Begin) {
    if (!empty())
      MI->bundleWithSucc();
    Begin = MI->getIterator();
    return *this;
  }
  if (I == End) {
    MI->bundleWithPred();
    return *this;
  }
  // MI was inserted in the middle of the bundle, so its neighbors' flags are
  // already fine. Update MI's bundle flags manually.
  MI->setFlag(MachineInstr::BundledPred);
  MI->setFlag(MachineInstr::BundledSucc);
  return *this;
}

/// Insert MI into MBB by prepending it to the instructions in the bundle.
/// MI will become the first instruction in the bundle.
MIBundleBuilder &prepend(MachineInstr *MI) {
  return insert(begin(), MI);
}

/// Insert MI into MBB by appending it to the instructions in the bundle.
/// MI will become the last instruction in the bundle.
MIBundleBuilder &append(MachineInstr *MI) {
  return insert(end(), MI);
}
620};

622} // end namespace llvm

624#endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H