Bug Summary

File:lib/CodeGen/MachineOperand.cpp
Warning:line 1097, column 18
Forming reference to null pointer

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MachineOperand.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~svn373386/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~svn373386/build-llvm/include -I /build/llvm-toolchain-snapshot-10~svn373386/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~svn373386/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~svn373386=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-10-02-042503-23017-1 -x c++ /build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp
1//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file Methods common to all machine operands.
10//
11//===----------------------------------------------------------------------===//
12
13#include "llvm/CodeGen/MachineOperand.h"
14#include "llvm/ADT/StringExtras.h"
15#include "llvm/Analysis/Loads.h"
16#include "llvm/Analysis/MemoryLocation.h"
17#include "llvm/CodeGen/MIRPrinter.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineJumpTableInfo.h"
20#include "llvm/CodeGen/MachineRegisterInfo.h"
21#include "llvm/CodeGen/TargetInstrInfo.h"
22#include "llvm/CodeGen/TargetRegisterInfo.h"
23#include "llvm/Config/llvm-config.h"
24#include "llvm/IR/Constants.h"
25#include "llvm/IR/IRPrintingPasses.h"
26#include "llvm/IR/ModuleSlotTracker.h"
27#include "llvm/MC/MCDwarf.h"
28#include "llvm/Target/TargetIntrinsicInfo.h"
29#include "llvm/Target/TargetMachine.h"
30
31using namespace llvm;
32
33static cl::opt<int>
34 PrintRegMaskNumRegs("print-regmask-num-regs",
35 cl::desc("Number of registers to limit to when "
36 "printing regmask operands in IR dumps. "
37 "unlimited = -1"),
38 cl::init(32), cl::Hidden);
39
40static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
41 if (const MachineInstr *MI = MO.getParent())
42 if (const MachineBasicBlock *MBB = MI->getParent())
43 if (const MachineFunction *MF = MBB->getParent())
44 return MF;
45 return nullptr;
46}
47static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
48 return const_cast<MachineFunction *>(
49 getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
50}
51
52void MachineOperand::setReg(Register Reg) {
53 if (getReg() == Reg)
54 return; // No change.
55
56 // Clear the IsRenamable bit to keep it conservatively correct.
57 IsRenamable = false;
58
59 // Otherwise, we have to change the register. If this operand is embedded
60 // into a machine function, we need to update the old and new register's
61 // use/def lists.
62 if (MachineFunction *MF = getMFIfAvailable(*this)) {
63 MachineRegisterInfo &MRI = MF->getRegInfo();
64 MRI.removeRegOperandFromUseList(this);
65 SmallContents.RegNo = Reg;
66 MRI.addRegOperandToUseList(this);
67 return;
68 }
69
70 // Otherwise, just change the register, no problem. :)
71 SmallContents.RegNo = Reg;
72}
73
74void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
75 const TargetRegisterInfo &TRI) {
76 assert(Reg.isVirtual())((Reg.isVirtual()) ? static_cast<void> (0) : __assert_fail
("Reg.isVirtual()", "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 76, __PRETTY_FUNCTION__));
77 if (SubIdx && getSubReg())
78 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
79 setReg(Reg);
80 if (SubIdx)
81 setSubReg(SubIdx);
82}
83
84void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
85 assert(Reg.isPhysical())((Reg.isPhysical()) ? static_cast<void> (0) : __assert_fail
("Reg.isPhysical()", "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 85, __PRETTY_FUNCTION__));
86 if (getSubReg()) {
87 Reg = TRI.getSubReg(Reg, getSubReg());
88 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
89 // That won't happen in legal code.
90 setSubReg(0);
91 if (isDef())
92 setIsUndef(false);
93 }
94 setReg(Reg);
95}
96
97/// Change a def to a use, or a use to a def.
98void MachineOperand::setIsDef(bool Val) {
99 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 99, __PRETTY_FUNCTION__));
100 assert((!Val || !isDebug()) && "Marking a debug operation as def")(((!Val || !isDebug()) && "Marking a debug operation as def"
) ? static_cast<void> (0) : __assert_fail ("(!Val || !isDebug()) && \"Marking a debug operation as def\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 100, __PRETTY_FUNCTION__));
101 if (IsDef == Val)
102 return;
103 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported")((!IsDeadOrKill && "Changing def/use with dead/kill set not supported"
) ? static_cast<void> (0) : __assert_fail ("!IsDeadOrKill && \"Changing def/use with dead/kill set not supported\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 103, __PRETTY_FUNCTION__));
104 // MRI may keep uses and defs in different list positions.
105 if (MachineFunction *MF = getMFIfAvailable(*this)) {
106 MachineRegisterInfo &MRI = MF->getRegInfo();
107 MRI.removeRegOperandFromUseList(this);
108 IsDef = Val;
109 MRI.addRegOperandToUseList(this);
110 return;
111 }
112 IsDef = Val;
113}
114
115bool MachineOperand::isRenamable() const {
116 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 116, __PRETTY_FUNCTION__));
117 assert(Register::isPhysicalRegister(getReg()) &&((Register::isPhysicalRegister(getReg()) && "isRenamable should only be checked on physical registers"
) ? static_cast<void> (0) : __assert_fail ("Register::isPhysicalRegister(getReg()) && \"isRenamable should only be checked on physical registers\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 118, __PRETTY_FUNCTION__))
118 "isRenamable should only be checked on physical registers")((Register::isPhysicalRegister(getReg()) && "isRenamable should only be checked on physical registers"
) ? static_cast<void> (0) : __assert_fail ("Register::isPhysicalRegister(getReg()) && \"isRenamable should only be checked on physical registers\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 118, __PRETTY_FUNCTION__));
119 if (!IsRenamable)
120 return false;
121
122 const MachineInstr *MI = getParent();
123 if (!MI)
124 return true;
125
126 if (isDef())
127 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
128
129 assert(isUse() && "Reg is not def or use")((isUse() && "Reg is not def or use") ? static_cast<
void> (0) : __assert_fail ("isUse() && \"Reg is not def or use\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 129, __PRETTY_FUNCTION__));
130 return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
131}
132
133void MachineOperand::setIsRenamable(bool Val) {
134 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 134, __PRETTY_FUNCTION__));
135 assert(Register::isPhysicalRegister(getReg()) &&((Register::isPhysicalRegister(getReg()) && "setIsRenamable should only be called on physical registers"
) ? static_cast<void> (0) : __assert_fail ("Register::isPhysicalRegister(getReg()) && \"setIsRenamable should only be called on physical registers\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 136, __PRETTY_FUNCTION__))
136 "setIsRenamable should only be called on physical registers")((Register::isPhysicalRegister(getReg()) && "setIsRenamable should only be called on physical registers"
) ? static_cast<void> (0) : __assert_fail ("Register::isPhysicalRegister(getReg()) && \"setIsRenamable should only be called on physical registers\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 136, __PRETTY_FUNCTION__));
137 IsRenamable = Val;
138}
139
140// If this operand is currently a register operand, and if this is in a
141// function, deregister the operand from the register's use/def list.
142void MachineOperand::removeRegFromUses() {
143 if (!isReg() || !isOnRegUseList())
144 return;
145
146 if (MachineFunction *MF = getMFIfAvailable(*this))
147 MF->getRegInfo().removeRegOperandFromUseList(this);
148}
149
150/// ChangeToImmediate - Replace this operand with a new immediate operand of
151/// the specified value. If an operand is known to be an immediate already,
152/// the setImm method should be used.
153void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
154 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm")(((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an imm\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 154, __PRETTY_FUNCTION__));
155
156 removeRegFromUses();
157
158 OpKind = MO_Immediate;
159 Contents.ImmVal = ImmVal;
160}
161
162void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
163 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm")(((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an imm\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 163, __PRETTY_FUNCTION__));
164
165 removeRegFromUses();
166
167 OpKind = MO_FPImmediate;
168 Contents.CFP = FPImm;
169}
170
171void MachineOperand::ChangeToES(const char *SymName,
172 unsigned TargetFlags) {
173 assert((!isReg() || !isTied()) &&(((!isReg() || !isTied()) && "Cannot change a tied operand into an external symbol"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an external symbol\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 174, __PRETTY_FUNCTION__))
174 "Cannot change a tied operand into an external symbol")(((!isReg() || !isTied()) && "Cannot change a tied operand into an external symbol"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an external symbol\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 174, __PRETTY_FUNCTION__));
175
176 removeRegFromUses();
177
178 OpKind = MO_ExternalSymbol;
179 Contents.OffsetedInfo.Val.SymbolName = SymName;
180 setOffset(0); // Offset is always 0.
181 setTargetFlags(TargetFlags);
182}
183
184void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
185 unsigned TargetFlags) {
186 assert((!isReg() || !isTied()) &&(((!isReg() || !isTied()) && "Cannot change a tied operand into a global address"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into a global address\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 187, __PRETTY_FUNCTION__))
187 "Cannot change a tied operand into a global address")(((!isReg() || !isTied()) && "Cannot change a tied operand into a global address"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into a global address\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 187, __PRETTY_FUNCTION__));
188
189 removeRegFromUses();
190
191 OpKind = MO_GlobalAddress;
192 Contents.OffsetedInfo.Val.GV = GV;
193 setOffset(Offset);
194 setTargetFlags(TargetFlags);
195}
196
197void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
198 assert((!isReg() || !isTied()) &&(((!isReg() || !isTied()) && "Cannot change a tied operand into an MCSymbol"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an MCSymbol\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 199, __PRETTY_FUNCTION__))
199 "Cannot change a tied operand into an MCSymbol")(((!isReg() || !isTied()) && "Cannot change a tied operand into an MCSymbol"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an MCSymbol\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 199, __PRETTY_FUNCTION__));
200
201 removeRegFromUses();
202
203 OpKind = MO_MCSymbol;
204 Contents.Sym = Sym;
205}
206
207void MachineOperand::ChangeToFrameIndex(int Idx) {
208 assert((!isReg() || !isTied()) &&(((!isReg() || !isTied()) && "Cannot change a tied operand into a FrameIndex"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into a FrameIndex\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 209, __PRETTY_FUNCTION__))
209 "Cannot change a tied operand into a FrameIndex")(((!isReg() || !isTied()) && "Cannot change a tied operand into a FrameIndex"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into a FrameIndex\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 209, __PRETTY_FUNCTION__));
210
211 removeRegFromUses();
212
213 OpKind = MO_FrameIndex;
214 setIndex(Idx);
215}
216
217void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
218 unsigned TargetFlags) {
219 assert((!isReg() || !isTied()) &&(((!isReg() || !isTied()) && "Cannot change a tied operand into a FrameIndex"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into a FrameIndex\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 220, __PRETTY_FUNCTION__))
220 "Cannot change a tied operand into a FrameIndex")(((!isReg() || !isTied()) && "Cannot change a tied operand into a FrameIndex"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into a FrameIndex\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 220, __PRETTY_FUNCTION__));
221
222 removeRegFromUses();
223
224 OpKind = MO_TargetIndex;
225 setIndex(Idx);
226 setOffset(Offset);
227 setTargetFlags(TargetFlags);
228}
229
230/// ChangeToRegister - Replace this operand with a new register operand of
231/// the specified value. If an operand is known to be an register already,
232/// the setReg method should be used.
233void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
234 bool isKill, bool isDead, bool isUndef,
235 bool isDebug) {
236 MachineRegisterInfo *RegInfo = nullptr;
237 if (MachineFunction *MF = getMFIfAvailable(*this))
238 RegInfo = &MF->getRegInfo();
239 // If this operand is already a register operand, remove it from the
240 // register's use/def lists.
241 bool WasReg = isReg();
242 if (RegInfo && WasReg)
243 RegInfo->removeRegOperandFromUseList(this);
244
245 // Change this to a register and set the reg#.
246 assert(!(isDead && !isDef) && "Dead flag on non-def")((!(isDead && !isDef) && "Dead flag on non-def"
) ? static_cast<void> (0) : __assert_fail ("!(isDead && !isDef) && \"Dead flag on non-def\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 246, __PRETTY_FUNCTION__));
247 assert(!(isKill && isDef) && "Kill flag on def")((!(isKill && isDef) && "Kill flag on def") ?
static_cast<void> (0) : __assert_fail ("!(isKill && isDef) && \"Kill flag on def\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 247, __PRETTY_FUNCTION__));
248 OpKind = MO_Register;
249 SmallContents.RegNo = Reg;
250 SubReg_TargetFlags = 0;
251 IsDef = isDef;
252 IsImp = isImp;
253 IsDeadOrKill = isKill | isDead;
254 IsRenamable = false;
255 IsUndef = isUndef;
256 IsInternalRead = false;
257 IsEarlyClobber = false;
258 IsDebug = isDebug;
259 // Ensure isOnRegUseList() returns false.
260 Contents.Reg.Prev = nullptr;
261 // Preserve the tie when the operand was already a register.
262 if (!WasReg)
263 TiedTo = 0;
264
265 // If this operand is embedded in a function, add the operand to the
266 // register's use/def list.
267 if (RegInfo)
268 RegInfo->addRegOperandToUseList(this);
269}
270
271/// isIdenticalTo - Return true if this operand is identical to the specified
272/// operand. Note that this should stay in sync with the hash_value overload
273/// below.
274bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
275 if (getType() != Other.getType() ||
276 getTargetFlags() != Other.getTargetFlags())
277 return false;
278
279 switch (getType()) {
280 case MachineOperand::MO_Register:
281 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
282 getSubReg() == Other.getSubReg();
283 case MachineOperand::MO_Immediate:
284 return getImm() == Other.getImm();
285 case MachineOperand::MO_CImmediate:
286 return getCImm() == Other.getCImm();
287 case MachineOperand::MO_FPImmediate:
288 return getFPImm() == Other.getFPImm();
289 case MachineOperand::MO_MachineBasicBlock:
290 return getMBB() == Other.getMBB();
291 case MachineOperand::MO_FrameIndex:
292 return getIndex() == Other.getIndex();
293 case MachineOperand::MO_ConstantPoolIndex:
294 case MachineOperand::MO_TargetIndex:
295 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
296 case MachineOperand::MO_JumpTableIndex:
297 return getIndex() == Other.getIndex();
298 case MachineOperand::MO_GlobalAddress:
299 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
300 case MachineOperand::MO_ExternalSymbol:
301 return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
302 getOffset() == Other.getOffset();
303 case MachineOperand::MO_BlockAddress:
304 return getBlockAddress() == Other.getBlockAddress() &&
305 getOffset() == Other.getOffset();
306 case MachineOperand::MO_RegisterMask:
307 case MachineOperand::MO_RegisterLiveOut: {
308 // Shallow compare of the two RegMasks
309 const uint32_t *RegMask = getRegMask();
310 const uint32_t *OtherRegMask = Other.getRegMask();
311 if (RegMask == OtherRegMask)
312 return true;
313
314 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
315 // Calculate the size of the RegMask
316 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
317 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
318
319 // Deep compare of the two RegMasks
320 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
321 }
322 // We don't know the size of the RegMask, so we can't deep compare the two
323 // reg masks.
324 return false;
325 }
326 case MachineOperand::MO_MCSymbol:
327 return getMCSymbol() == Other.getMCSymbol();
328 case MachineOperand::MO_CFIIndex:
329 return getCFIIndex() == Other.getCFIIndex();
330 case MachineOperand::MO_Metadata:
331 return getMetadata() == Other.getMetadata();
332 case MachineOperand::MO_IntrinsicID:
333 return getIntrinsicID() == Other.getIntrinsicID();
334 case MachineOperand::MO_Predicate:
335 return getPredicate() == Other.getPredicate();
336 case MachineOperand::MO_ShuffleMask:
337 return getShuffleMask() == Other.getShuffleMask();
338 }
339 llvm_unreachable("Invalid machine operand type")::llvm::llvm_unreachable_internal("Invalid machine operand type"
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 339);
340}
341
342// Note: this must stay exactly in sync with isIdenticalTo above.
343hash_code llvm::hash_value(const MachineOperand &MO) {
344 switch (MO.getType()) {
345 case MachineOperand::MO_Register:
346 // Register operands don't have target flags.
347 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
348 case MachineOperand::MO_Immediate:
349 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
350 case MachineOperand::MO_CImmediate:
351 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
352 case MachineOperand::MO_FPImmediate:
353 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
354 case MachineOperand::MO_MachineBasicBlock:
355 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
356 case MachineOperand::MO_FrameIndex:
357 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
358 case MachineOperand::MO_ConstantPoolIndex:
359 case MachineOperand::MO_TargetIndex:
360 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
361 MO.getOffset());
362 case MachineOperand::MO_JumpTableIndex:
363 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
364 case MachineOperand::MO_ExternalSymbol:
365 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
366 StringRef(MO.getSymbolName()));
367 case MachineOperand::MO_GlobalAddress:
368 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
369 MO.getOffset());
370 case MachineOperand::MO_BlockAddress:
371 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
372 MO.getOffset());
373 case MachineOperand::MO_RegisterMask:
374 case MachineOperand::MO_RegisterLiveOut:
375 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
376 case MachineOperand::MO_Metadata:
377 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
378 case MachineOperand::MO_MCSymbol:
379 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
380 case MachineOperand::MO_CFIIndex:
381 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
382 case MachineOperand::MO_IntrinsicID:
383 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
384 case MachineOperand::MO_Predicate:
385 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
386 case MachineOperand::MO_ShuffleMask:
387 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
388 }
389 llvm_unreachable("Invalid machine operand type")::llvm::llvm_unreachable_internal("Invalid machine operand type"
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 389);
390}
391
392// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
393// it.
394static void tryToGetTargetInfo(const MachineOperand &MO,
395 const TargetRegisterInfo *&TRI,
396 const TargetIntrinsicInfo *&IntrinsicInfo) {
397 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
398 TRI = MF->getSubtarget().getRegisterInfo();
399 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
400 }
401}
402
403static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
404 const auto *TII = MF.getSubtarget().getInstrInfo();
405 assert(TII && "expected instruction info")((TII && "expected instruction info") ? static_cast<
void> (0) : __assert_fail ("TII && \"expected instruction info\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 405, __PRETTY_FUNCTION__));
406 auto Indices = TII->getSerializableTargetIndices();
407 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
408 return I.first == Index;
409 });
410 if (Found != Indices.end())
411 return Found->second;
412 return nullptr;
413}
414
415static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
416 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
417 for (const auto &I : Flags) {
418 if (I.first == TF) {
419 return I.second;
420 }
421 }
422 return nullptr;
423}
424
425static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
426 const TargetRegisterInfo *TRI) {
427 if (!TRI) {
428 OS << "%dwarfreg." << DwarfReg;
429 return;
430 }
431
432 if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
433 OS << printReg(*Reg, TRI);
434 else
435 OS << "<badreg>";
436}
437
438static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
439 ModuleSlotTracker &MST) {
440 OS << "%ir-block.";
441 if (BB.hasName()) {
442 printLLVMNameWithoutPrefix(OS, BB.getName());
443 return;
444 }
445 Optional<int> Slot;
446 if (const Function *F = BB.getParent()) {
447 if (F == MST.getCurrentFunction()) {
448 Slot = MST.getLocalSlot(&BB);
449 } else if (const Module *M = F->getParent()) {
450 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
451 CustomMST.incorporateFunction(*F);
452 Slot = CustomMST.getLocalSlot(&BB);
453 }
454 }
455 if (Slot)
456 MachineOperand::printIRSlotNumber(OS, *Slot);
457 else
458 OS << "<unknown>";
459}
460
461static void printIRValueReference(raw_ostream &OS, const Value &V,
462 ModuleSlotTracker &MST) {
463 if (isa<GlobalValue>(V)) {
464 V.printAsOperand(OS, /*PrintType=*/false, MST);
465 return;
466 }
467 if (isa<Constant>(V)) {
468 // Machine memory operands can load/store to/from constant value pointers.
469 OS << '`';
470 V.printAsOperand(OS, /*PrintType=*/true, MST);
471 OS << '`';
472 return;
473 }
474 OS << "%ir.";
475 if (V.hasName()) {
476 printLLVMNameWithoutPrefix(OS, V.getName());
477 return;
478 }
479 int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
480 MachineOperand::printIRSlotNumber(OS, Slot);
481}
482
483static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
484 SyncScope::ID SSID,
485 SmallVectorImpl<StringRef> &SSNs) {
486 switch (SSID) {
487 case SyncScope::System:
488 break;
489 default:
490 if (SSNs.empty())
491 Context.getSyncScopeNames(SSNs);
492
493 OS << "syncscope(\"";
494 printEscapedString(SSNs[SSID], OS);
495 OS << "\") ";
496 break;
497 }
498}
499
500static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
501 unsigned TMMOFlag) {
502 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
503 for (const auto &I : Flags) {
504 if (I.first == TMMOFlag) {
505 return I.second;
506 }
507 }
508 return nullptr;
509}
510
511static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
512 const MachineFrameInfo *MFI) {
513 StringRef Name;
514 if (MFI) {
515 IsFixed = MFI->isFixedObjectIndex(FrameIndex);
516 if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
517 if (Alloca->hasName())
518 Name = Alloca->getName();
519 if (IsFixed)
520 FrameIndex -= MFI->getObjectIndexBegin();
521 }
522 MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
523}
524
525void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
526 const TargetRegisterInfo *TRI) {
527 OS << "%subreg.";
528 if (TRI)
529 OS << TRI->getSubRegIndexName(Index);
530 else
531 OS << Index;
532}
533
534void MachineOperand::printTargetFlags(raw_ostream &OS,
535 const MachineOperand &Op) {
536 if (!Op.getTargetFlags())
537 return;
538 const MachineFunction *MF = getMFIfAvailable(Op);
539 if (!MF)
540 return;
541
542 const auto *TII = MF->getSubtarget().getInstrInfo();
543 assert(TII && "expected instruction info")((TII && "expected instruction info") ? static_cast<
void> (0) : __assert_fail ("TII && \"expected instruction info\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 543, __PRETTY_FUNCTION__));
544 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
545 OS << "target-flags(";
546 const bool HasDirectFlags = Flags.first;
547 const bool HasBitmaskFlags = Flags.second;
548 if (!HasDirectFlags && !HasBitmaskFlags) {
549 OS << "<unknown>) ";
550 return;
551 }
552 if (HasDirectFlags) {
553 if (const auto *Name = getTargetFlagName(TII, Flags.first))
554 OS << Name;
555 else
556 OS << "<unknown target flag>";
557 }
558 if (!HasBitmaskFlags) {
559 OS << ") ";
560 return;
561 }
562 bool IsCommaNeeded = HasDirectFlags;
563 unsigned BitMask = Flags.second;
564 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
565 for (const auto &Mask : BitMasks) {
566 // Check if the flag's bitmask has the bits of the current mask set.
567 if ((BitMask & Mask.first) == Mask.first) {
568 if (IsCommaNeeded)
569 OS << ", ";
570 IsCommaNeeded = true;
571 OS << Mask.second;
572 // Clear the bits which were serialized from the flag's bitmask.
573 BitMask &= ~(Mask.first);
574 }
575 }
576 if (BitMask) {
577 // When the resulting flag's bitmask isn't zero, we know that we didn't
578 // serialize all of the bit flags.
579 if (IsCommaNeeded)
580 OS << ", ";
581 OS << "<unknown bitmask target flag>";
582 }
583 OS << ") ";
584}
585
586void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
587 OS << "<mcsymbol " << Sym << ">";
588}
589
590void MachineOperand::printStackObjectReference(raw_ostream &OS,
591 unsigned FrameIndex,
592 bool IsFixed, StringRef Name) {
593 if (IsFixed) {
594 OS << "%fixed-stack." << FrameIndex;
595 return;
596 }
597
598 OS << "%stack." << FrameIndex;
599 if (!Name.empty())
600 OS << '.' << Name;
601}
602
603void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
604 if (Offset == 0)
605 return;
606 if (Offset < 0) {
607 OS << " - " << -Offset;
608 return;
609 }
610 OS << " + " << Offset;
611}
612
613void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
614 if (Slot == -1)
615 OS << "<badref>";
616 else
617 OS << Slot;
618}
619
620static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
621 const TargetRegisterInfo *TRI) {
622 switch (CFI.getOperation()) {
623 case MCCFIInstruction::OpSameValue:
624 OS << "same_value ";
625 if (MCSymbol *Label = CFI.getLabel())
626 MachineOperand::printSymbol(OS, *Label);
627 printCFIRegister(CFI.getRegister(), OS, TRI);
628 break;
629 case MCCFIInstruction::OpRememberState:
630 OS << "remember_state ";
631 if (MCSymbol *Label = CFI.getLabel())
632 MachineOperand::printSymbol(OS, *Label);
633 break;
634 case MCCFIInstruction::OpRestoreState:
635 OS << "restore_state ";
636 if (MCSymbol *Label = CFI.getLabel())
637 MachineOperand::printSymbol(OS, *Label);
638 break;
639 case MCCFIInstruction::OpOffset:
640 OS << "offset ";
641 if (MCSymbol *Label = CFI.getLabel())
642 MachineOperand::printSymbol(OS, *Label);
643 printCFIRegister(CFI.getRegister(), OS, TRI);
644 OS << ", " << CFI.getOffset();
645 break;
646 case MCCFIInstruction::OpDefCfaRegister:
647 OS << "def_cfa_register ";
648 if (MCSymbol *Label = CFI.getLabel())
649 MachineOperand::printSymbol(OS, *Label);
650 printCFIRegister(CFI.getRegister(), OS, TRI);
651 break;
652 case MCCFIInstruction::OpDefCfaOffset:
653 OS << "def_cfa_offset ";
654 if (MCSymbol *Label = CFI.getLabel())
655 MachineOperand::printSymbol(OS, *Label);
656 OS << CFI.getOffset();
657 break;
658 case MCCFIInstruction::OpDefCfa:
659 OS << "def_cfa ";
660 if (MCSymbol *Label = CFI.getLabel())
661 MachineOperand::printSymbol(OS, *Label);
662 printCFIRegister(CFI.getRegister(), OS, TRI);
663 OS << ", " << CFI.getOffset();
664 break;
665 case MCCFIInstruction::OpRelOffset:
666 OS << "rel_offset ";
667 if (MCSymbol *Label = CFI.getLabel())
668 MachineOperand::printSymbol(OS, *Label);
669 printCFIRegister(CFI.getRegister(), OS, TRI);
670 OS << ", " << CFI.getOffset();
671 break;
672 case MCCFIInstruction::OpAdjustCfaOffset:
673 OS << "adjust_cfa_offset ";
674 if (MCSymbol *Label = CFI.getLabel())
675 MachineOperand::printSymbol(OS, *Label);
676 OS << CFI.getOffset();
677 break;
678 case MCCFIInstruction::OpRestore:
679 OS << "restore ";
680 if (MCSymbol *Label = CFI.getLabel())
681 MachineOperand::printSymbol(OS, *Label);
682 printCFIRegister(CFI.getRegister(), OS, TRI);
683 break;
684 case MCCFIInstruction::OpEscape: {
685 OS << "escape ";
686 if (MCSymbol *Label = CFI.getLabel())
687 MachineOperand::printSymbol(OS, *Label);
688 if (!CFI.getValues().empty()) {
689 size_t e = CFI.getValues().size() - 1;
690 for (size_t i = 0; i < e; ++i)
691 OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
692 OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
693 }
694 break;
695 }
696 case MCCFIInstruction::OpUndefined:
697 OS << "undefined ";
698 if (MCSymbol *Label = CFI.getLabel())
699 MachineOperand::printSymbol(OS, *Label);
700 printCFIRegister(CFI.getRegister(), OS, TRI);
701 break;
702 case MCCFIInstruction::OpRegister:
703 OS << "register ";
704 if (MCSymbol *Label = CFI.getLabel())
705 MachineOperand::printSymbol(OS, *Label);
706 printCFIRegister(CFI.getRegister(), OS, TRI);
707 OS << ", ";
708 printCFIRegister(CFI.getRegister2(), OS, TRI);
709 break;
710 case MCCFIInstruction::OpWindowSave:
711 OS << "window_save ";
712 if (MCSymbol *Label = CFI.getLabel())
713 MachineOperand::printSymbol(OS, *Label);
714 break;
715 case MCCFIInstruction::OpNegateRAState:
716 OS << "negate_ra_sign_state ";
717 if (MCSymbol *Label = CFI.getLabel())
718 MachineOperand::printSymbol(OS, *Label);
719 break;
720 default:
721 // TODO: Print the other CFI Operations.
722 OS << "<unserializable cfi directive>";
723 break;
724 }
725}
726
727void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
728 const TargetIntrinsicInfo *IntrinsicInfo) const {
729 print(OS, LLT{}, TRI, IntrinsicInfo);
730}
731
732void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
733 const TargetRegisterInfo *TRI,
734 const TargetIntrinsicInfo *IntrinsicInfo) const {
735 tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
736 ModuleSlotTracker DummyMST(nullptr);
737 print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
738 /*ShouldPrintRegisterTies=*/true,
739 /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
740}
741
742void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
743 LLT TypeToPrint, bool PrintDef, bool IsStandalone,
744 bool ShouldPrintRegisterTies,
745 unsigned TiedOperandIdx,
746 const TargetRegisterInfo *TRI,
747 const TargetIntrinsicInfo *IntrinsicInfo) const {
748 printTargetFlags(OS, *this);
749 switch (getType()) {
750 case MachineOperand::MO_Register: {
751 Register Reg = getReg();
752 if (isImplicit())
753 OS << (isDef() ? "implicit-def " : "implicit ");
754 else if (PrintDef && isDef())
755 // Print the 'def' flag only when the operand is defined after '='.
756 OS << "def ";
757 if (isInternalRead())
758 OS << "internal ";
759 if (isDead())
760 OS << "dead ";
761 if (isKill())
762 OS << "killed ";
763 if (isUndef())
764 OS << "undef ";
765 if (isEarlyClobber())
766 OS << "early-clobber ";
767 if (Register::isPhysicalRegister(getReg()) && isRenamable())
768 OS << "renamable ";
769 // isDebug() is exactly true for register operands of a DBG_VALUE. So we
770 // simply infer it when parsing and do not need to print it.
771
772 const MachineRegisterInfo *MRI = nullptr;
773 if (Register::isVirtualRegister(Reg)) {
774 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
775 MRI = &MF->getRegInfo();
776 }
777 }
778
779 OS << printReg(Reg, TRI, 0, MRI);
780 // Print the sub register.
781 if (unsigned SubReg = getSubReg()) {
782 if (TRI)
783 OS << '.' << TRI->getSubRegIndexName(SubReg);
784 else
785 OS << ".subreg" << SubReg;
786 }
787 // Print the register class / bank.
788 if (Register::isVirtualRegister(Reg)) {
789 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
790 const MachineRegisterInfo &MRI = MF->getRegInfo();
791 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
792 OS << ':';
793 OS << printRegClassOrBank(Reg, MRI, TRI);
794 }
795 }
796 }
797 // Print ties.
798 if (ShouldPrintRegisterTies && isTied() && !isDef())
799 OS << "(tied-def " << TiedOperandIdx << ")";
800 // Print types.
801 if (TypeToPrint.isValid())
802 OS << '(' << TypeToPrint << ')';
803 break;
804 }
805 case MachineOperand::MO_Immediate:
806 OS << getImm();
807 break;
808 case MachineOperand::MO_CImmediate:
809 getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
810 break;
811 case MachineOperand::MO_FPImmediate:
812 getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
813 break;
814 case MachineOperand::MO_MachineBasicBlock:
815 OS << printMBBReference(*getMBB());
816 break;
817 case MachineOperand::MO_FrameIndex: {
818 int FrameIndex = getIndex();
819 bool IsFixed = false;
820 const MachineFrameInfo *MFI = nullptr;
821 if (const MachineFunction *MF = getMFIfAvailable(*this))
822 MFI = &MF->getFrameInfo();
823 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
824 break;
825 }
826 case MachineOperand::MO_ConstantPoolIndex:
827 OS << "%const." << getIndex();
828 printOperandOffset(OS, getOffset());
829 break;
830 case MachineOperand::MO_TargetIndex: {
831 OS << "target-index(";
832 const char *Name = "<unknown>";
833 if (const MachineFunction *MF = getMFIfAvailable(*this))
834 if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
835 Name = TargetIndexName;
836 OS << Name << ')';
837 printOperandOffset(OS, getOffset());
838 break;
839 }
840 case MachineOperand::MO_JumpTableIndex:
841 OS << printJumpTableEntryReference(getIndex());
842 break;
843 case MachineOperand::MO_GlobalAddress:
844 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
845 printOperandOffset(OS, getOffset());
846 break;
847 case MachineOperand::MO_ExternalSymbol: {
848 StringRef Name = getSymbolName();
849 OS << '&';
850 if (Name.empty()) {
851 OS << "\"\"";
852 } else {
853 printLLVMNameWithoutPrefix(OS, Name);
854 }
855 printOperandOffset(OS, getOffset());
856 break;
857 }
858 case MachineOperand::MO_BlockAddress: {
859 OS << "blockaddress(";
860 getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
861 MST);
862 OS << ", ";
863 printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
864 OS << ')';
865 MachineOperand::printOperandOffset(OS, getOffset());
866 break;
867 }
868 case MachineOperand::MO_RegisterMask: {
869 OS << "<regmask";
870 if (TRI) {
871 unsigned NumRegsInMask = 0;
872 unsigned NumRegsEmitted = 0;
873 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
874 unsigned MaskWord = i / 32;
875 unsigned MaskBit = i % 32;
876 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
877 if (PrintRegMaskNumRegs < 0 ||
878 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
879 OS << " " << printReg(i, TRI);
880 NumRegsEmitted++;
881 }
882 NumRegsInMask++;
883 }
884 }
885 if (NumRegsEmitted != NumRegsInMask)
886 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
887 } else {
888 OS << " ...";
889 }
890 OS << ">";
891 break;
892 }
893 case MachineOperand::MO_RegisterLiveOut: {
894 const uint32_t *RegMask = getRegLiveOut();
895 OS << "liveout(";
896 if (!TRI) {
897 OS << "<unknown>";
898 } else {
899 bool IsCommaNeeded = false;
900 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
901 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
902 if (IsCommaNeeded)
903 OS << ", ";
904 OS << printReg(Reg, TRI);
905 IsCommaNeeded = true;
906 }
907 }
908 }
909 OS << ")";
910 break;
911 }
912 case MachineOperand::MO_Metadata:
913 getMetadata()->printAsOperand(OS, MST);
914 break;
915 case MachineOperand::MO_MCSymbol:
916 printSymbol(OS, *getMCSymbol());
917 break;
918 case MachineOperand::MO_CFIIndex: {
919 if (const MachineFunction *MF = getMFIfAvailable(*this))
920 printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
921 else
922 OS << "<cfi directive>";
923 break;
924 }
925 case MachineOperand::MO_IntrinsicID: {
926 Intrinsic::ID ID = getIntrinsicID();
927 if (ID < Intrinsic::num_intrinsics)
928 OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
929 else if (IntrinsicInfo)
930 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
931 else
932 OS << "intrinsic(" << ID << ')';
933 break;
934 }
935 case MachineOperand::MO_Predicate: {
936 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
937 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
938 << CmpInst::getPredicateName(Pred) << ')';
939 break;
940 }
941 case MachineOperand::MO_ShuffleMask:
942 OS << "shufflemask(";
943 const Constant* C = getShuffleMask();
944 const int NumElts = C->getType()->getVectorNumElements();
945
946 StringRef Separator;
947 for (int I = 0; I != NumElts; ++I) {
948 OS << Separator;
949 C->getAggregateElement(I)->printAsOperand(OS, false, MST);
950 Separator = ", ";
951 }
952
953 OS << ')';
954 break;
955 }
956}
957
958#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
959LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineOperand::dump() const { dbgs() << *this << '\n'; }
960#endif
961
962//===----------------------------------------------------------------------===//
963// MachineMemOperand Implementation
964//===----------------------------------------------------------------------===//
965
966/// getAddrSpace - Return the LLVM IR address space number that this pointer
967/// points into.
968unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
969
970/// isDereferenceable - Return true if V is always dereferenceable for
971/// Offset + Size byte.
972bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
973 const DataLayout &DL) const {
974 if (!V.is<const Value *>())
975 return false;
976
977 const Value *BasePtr = V.get<const Value *>();
978 if (BasePtr == nullptr)
979 return false;
980
981 return isDereferenceableAndAlignedPointer(
982 BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
983}
984
985/// getConstantPool - Return a MachinePointerInfo record that refers to the
986/// constant pool.
987MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
988 return MachinePointerInfo(MF.getPSVManager().getConstantPool());
989}
990
991/// getFixedStack - Return a MachinePointerInfo record that refers to the
992/// the specified FrameIndex.
993MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
994 int FI, int64_t Offset) {
995 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
996}
997
998MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
999 return MachinePointerInfo(MF.getPSVManager().getJumpTable());
1000}
1001
1002MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1003 return MachinePointerInfo(MF.getPSVManager().getGOT());
1004}
1005
1006MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1007 int64_t Offset, uint8_t ID) {
1008 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1009}
1010
1011MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1012 return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1013}
1014
1015MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1016 uint64_t s, uint64_t a,
1017 const AAMDNodes &AAInfo,
1018 const MDNode *Ranges, SyncScope::ID SSID,
1019 AtomicOrdering Ordering,
1020 AtomicOrdering FailureOrdering)
1021 : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
1022 AAInfo(AAInfo), Ranges(Ranges) {
1023 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||(((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue
*>() || isa<PointerType>(PtrInfo.V.get<const Value
*>()->getType())) && "invalid pointer value") ?
static_cast<void> (0) : __assert_fail ("(PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() || isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) && \"invalid pointer value\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1025, __PRETTY_FUNCTION__))
1024 isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&(((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue
*>() || isa<PointerType>(PtrInfo.V.get<const Value
*>()->getType())) && "invalid pointer value") ?
static_cast<void> (0) : __assert_fail ("(PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() || isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) && \"invalid pointer value\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1025, __PRETTY_FUNCTION__))
1025 "invalid pointer value")(((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue
*>() || isa<PointerType>(PtrInfo.V.get<const Value
*>()->getType())) && "invalid pointer value") ?
static_cast<void> (0) : __assert_fail ("(PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() || isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) && \"invalid pointer value\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1025, __PRETTY_FUNCTION__));
1026 assert(getBaseAlignment() == a && a != 0 && "Alignment is not a power of 2!")((getBaseAlignment() == a && a != 0 && "Alignment is not a power of 2!"
) ? static_cast<void> (0) : __assert_fail ("getBaseAlignment() == a && a != 0 && \"Alignment is not a power of 2!\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1026, __PRETTY_FUNCTION__));
1027 assert((isLoad() || isStore()) && "Not a load/store!")(((isLoad() || isStore()) && "Not a load/store!") ? static_cast
<void> (0) : __assert_fail ("(isLoad() || isStore()) && \"Not a load/store!\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1027, __PRETTY_FUNCTION__));
1028
1029 AtomicInfo.SSID = static_cast<unsigned>(SSID);
1030 assert(getSyncScopeID() == SSID && "Value truncated")((getSyncScopeID() == SSID && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getSyncScopeID() == SSID && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1030, __PRETTY_FUNCTION__));
1031 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1032 assert(getOrdering() == Ordering && "Value truncated")((getOrdering() == Ordering && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getOrdering() == Ordering && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1032, __PRETTY_FUNCTION__));
1033 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1034 assert(getFailureOrdering() == FailureOrdering && "Value truncated")((getFailureOrdering() == FailureOrdering && "Value truncated"
) ? static_cast<void> (0) : __assert_fail ("getFailureOrdering() == FailureOrdering && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1034, __PRETTY_FUNCTION__));
1035}
1036
1037/// Profile - Gather unique data for the object.
1038///
1039void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1040 ID.AddInteger(getOffset());
1041 ID.AddInteger(Size);
1042 ID.AddPointer(getOpaqueValue());
1043 ID.AddInteger(getFlags());
1044 ID.AddInteger(getBaseAlignment());
1045}
1046
1047void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1048 // The Value and Offset may differ due to CSE. But the flags and size
1049 // should be the same.
1050 assert(MMO->getFlags() == getFlags() && "Flags mismatch!")((MMO->getFlags() == getFlags() && "Flags mismatch!"
) ? static_cast<void> (0) : __assert_fail ("MMO->getFlags() == getFlags() && \"Flags mismatch!\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1050, __PRETTY_FUNCTION__));
1051 assert(MMO->getSize() == getSize() && "Size mismatch!")((MMO->getSize() == getSize() && "Size mismatch!")
? static_cast<void> (0) : __assert_fail ("MMO->getSize() == getSize() && \"Size mismatch!\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1051, __PRETTY_FUNCTION__));
1052
1053 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1054 // Update the alignment value.
1055 BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1056 // Also update the base and offset, because the new alignment may
1057 // not be applicable with the old ones.
1058 PtrInfo = MMO->PtrInfo;
1059 }
1060}
1061
1062/// getAlignment - Return the minimum known alignment in bytes of the
1063/// actual memory reference.
1064uint64_t MachineMemOperand::getAlignment() const {
1065 return MinAlign(getBaseAlignment(), getOffset());
1066}
1067
1068void MachineMemOperand::print(raw_ostream &OS) const {
1069 ModuleSlotTracker DummyMST(nullptr);
1070 print(OS, DummyMST);
1
Calling 'MachineMemOperand::print'
→
1071}
1072
1073void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
1074 SmallVector<StringRef, 0> SSNs;
1075 LLVMContext Ctx;
1076 print(OS, MST, SSNs, Ctx, nullptr, nullptr);
2
←
Passing null pointer value via 6th parameter 'TII'
→
3
←
Calling 'MachineMemOperand::print'
→
1077}
1078
1079void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1080 SmallVectorImpl<StringRef> &SSNs,
1081 const LLVMContext &Context,
1082 const MachineFrameInfo *MFI,
1083 const TargetInstrInfo *TII) const {
1084 OS << '(';
1085 if (isVolatile())
4
←
Assuming the condition is false
→
5
←
Taking false branch
→
1086 OS << "volatile ";
1087 if (isNonTemporal())
6
←
Assuming the condition is false
→
7
←
Taking false branch
→
1088 OS << "non-temporal ";
1089 if (isDereferenceable())
8
←
Assuming the condition is false
→
9
←
Taking false branch
→
1090 OS << "dereferenceable ";
1091 if (isInvariant())
10
←
Assuming the condition is false
→
11
←
Taking false branch
→
1092 OS << "invariant ";
1093 if (getFlags() & MachineMemOperand::MOTargetFlag1)
12
←
Assuming the condition is false
→
13
←
Taking false branch
→
1094 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1095 << "\" ";
1096 if (getFlags() & MachineMemOperand::MOTargetFlag2)
14
←
Assuming the condition is true
→
15
←
Taking true branch
→
1097 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
16
←
Forming reference to null pointer
1098 << "\" ";
1099 if (getFlags() & MachineMemOperand::MOTargetFlag3)
1100 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1101 << "\" ";
1102
1103 assert((isLoad() || isStore()) &&(((isLoad() || isStore()) && "machine memory operand must be a load or store (or both)"
) ? static_cast<void> (0) : __assert_fail ("(isLoad() || isStore()) && \"machine memory operand must be a load or store (or both)\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1104, __PRETTY_FUNCTION__))
1104 "machine memory operand must be a load or store (or both)")(((isLoad() || isStore()) && "machine memory operand must be a load or store (or both)"
) ? static_cast<void> (0) : __assert_fail ("(isLoad() || isStore()) && \"machine memory operand must be a load or store (or both)\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1104, __PRETTY_FUNCTION__));
1105 if (isLoad())
1106 OS << "load ";
1107 if (isStore())
1108 OS << "store ";
1109
1110 printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1111
1112 if (getOrdering() != AtomicOrdering::NotAtomic)
1113 OS << toIRString(getOrdering()) << ' ';
1114 if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1115 OS << toIRString(getFailureOrdering()) << ' ';
1116
1117 if (getSize() == MemoryLocation::UnknownSize)
1118 OS << "unknown-size";
1119 else
1120 OS << getSize();
1121
1122 if (const Value *Val = getValue()) {
1123 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1124 printIRValueReference(OS, *Val, MST);
1125 } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1126 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1127 assert(PVal && "Expected a pseudo source value")((PVal && "Expected a pseudo source value") ? static_cast
<void> (0) : __assert_fail ("PVal && \"Expected a pseudo source value\""
, "/build/llvm-toolchain-snapshot-10~svn373386/lib/CodeGen/MachineOperand.cpp"
, 1127, __PRETTY_FUNCTION__));
1128 switch (PVal->kind()) {
1129 case PseudoSourceValue::Stack:
1130 OS << "stack";
1131 break;
1132 case PseudoSourceValue::GOT:
1133 OS << "got";
1134 break;
1135 case PseudoSourceValue::JumpTable:
1136 OS << "jump-table";
1137 break;
1138 case PseudoSourceValue::ConstantPool:
1139 OS << "constant-pool";
1140 break;
1141 case PseudoSourceValue::FixedStack: {
1142 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1143 bool IsFixed = true;
1144 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1145 break;
1146 }
1147 case PseudoSourceValue::GlobalValueCallEntry:
1148 OS << "call-entry ";
1149 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1150 OS, /*PrintType=*/false, MST);
1151 break;
1152 case PseudoSourceValue::ExternalSymbolCallEntry:
1153 OS << "call-entry &";
1154 printLLVMNameWithoutPrefix(
1155 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1156 break;
1157 default:
1158 // FIXME: This is not necessarily the correct MIR serialization format for
1159 // a custom pseudo source value, but at least it allows
1160 // -print-machineinstrs to work on a target with custom pseudo source
1161 // values.
1162 OS << "custom ";
1163 PVal->printCustom(OS);
1164 break;
1165 }
1166 }
1167 MachineOperand::printOperandOffset(OS, getOffset());
1168 if (getBaseAlignment() != getSize())
1169 OS << ", align " << getBaseAlignment();
1170 auto AAInfo = getAAInfo();
1171 if (AAInfo.TBAA) {
1172 OS << ", !tbaa ";
1173 AAInfo.TBAA->printAsOperand(OS, MST);
1174 }
1175 if (AAInfo.Scope) {
1176 OS << ", !alias.scope ";
1177 AAInfo.Scope->printAsOperand(OS, MST);
1178 }
1179 if (AAInfo.NoAlias) {
1180 OS << ", !noalias ";
1181 AAInfo.NoAlias->printAsOperand(OS, MST);
1182 }
1183 if (getRanges()) {
1184 OS << ", !range ";
1185 getRanges()->printAsOperand(OS, MST);
1186 }
1187 // FIXME: Implement addrspace printing/parsing in MIR.
1188 // For now, print this even though parsing it is not available in MIR.
1189 if (unsigned AS = getAddrSpace())
1190 OS << ", addrspace " << AS;
1191
1192 OS << ')';
1193}