Bug Summary

File:lib/CodeGen/MachineOperand.cpp
Warning:line 1071, column 18
Forming reference to null pointer

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MachineOperand.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen -I /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn350071/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn350071/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-8~svn350071=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-12-27-042839-1215-1 -x c++ /build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp -faddrsig
1//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file Methods common to all machine operands.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineOperand.h"
15#include "llvm/ADT/StringExtras.h"
16#include "llvm/Analysis/Loads.h"
17#include "llvm/Analysis/MemoryLocation.h"
18#include "llvm/CodeGen/MIRPrinter.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineJumpTableInfo.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/TargetInstrInfo.h"
23#include "llvm/CodeGen/TargetRegisterInfo.h"
24#include "llvm/Config/llvm-config.h"
25#include "llvm/IR/Constants.h"
26#include "llvm/IR/IRPrintingPasses.h"
27#include "llvm/IR/ModuleSlotTracker.h"
28#include "llvm/Target/TargetIntrinsicInfo.h"
29#include "llvm/Target/TargetMachine.h"
30
31using namespace llvm;
32
33static cl::opt<int>
34 PrintRegMaskNumRegs("print-regmask-num-regs",
35 cl::desc("Number of registers to limit to when "
36 "printing regmask operands in IR dumps. "
37 "unlimited = -1"),
38 cl::init(32), cl::Hidden);
39
40static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
41 if (const MachineInstr *MI = MO.getParent())
42 if (const MachineBasicBlock *MBB = MI->getParent())
43 if (const MachineFunction *MF = MBB->getParent())
44 return MF;
45 return nullptr;
46}
47static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
48 return const_cast<MachineFunction *>(
49 getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
50}
51
52void MachineOperand::setReg(unsigned Reg) {
53 if (getReg() == Reg)
54 return; // No change.
55
56 // Clear the IsRenamable bit to keep it conservatively correct.
57 IsRenamable = false;
58
59 // Otherwise, we have to change the register. If this operand is embedded
60 // into a machine function, we need to update the old and new register's
61 // use/def lists.
62 if (MachineFunction *MF = getMFIfAvailable(*this)) {
63 MachineRegisterInfo &MRI = MF->getRegInfo();
64 MRI.removeRegOperandFromUseList(this);
65 SmallContents.RegNo = Reg;
66 MRI.addRegOperandToUseList(this);
67 return;
68 }
69
70 // Otherwise, just change the register, no problem. :)
71 SmallContents.RegNo = Reg;
72}
73
74void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
75 const TargetRegisterInfo &TRI) {
76 assert(TargetRegisterInfo::isVirtualRegister(Reg))((TargetRegisterInfo::isVirtualRegister(Reg)) ? static_cast<
void> (0) : __assert_fail ("TargetRegisterInfo::isVirtualRegister(Reg)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 76, __PRETTY_FUNCTION__))
;
77 if (SubIdx && getSubReg())
78 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
79 setReg(Reg);
80 if (SubIdx)
81 setSubReg(SubIdx);
82}
83
84void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
85 assert(TargetRegisterInfo::isPhysicalRegister(Reg))((TargetRegisterInfo::isPhysicalRegister(Reg)) ? static_cast<
void> (0) : __assert_fail ("TargetRegisterInfo::isPhysicalRegister(Reg)"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 85, __PRETTY_FUNCTION__))
;
86 if (getSubReg()) {
87 Reg = TRI.getSubReg(Reg, getSubReg());
88 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
89 // That won't happen in legal code.
90 setSubReg(0);
91 if (isDef())
92 setIsUndef(false);
93 }
94 setReg(Reg);
95}
96
97/// Change a def to a use, or a use to a def.
98void MachineOperand::setIsDef(bool Val) {
99 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 99, __PRETTY_FUNCTION__))
;
100 assert((!Val || !isDebug()) && "Marking a debug operation as def")(((!Val || !isDebug()) && "Marking a debug operation as def"
) ? static_cast<void> (0) : __assert_fail ("(!Val || !isDebug()) && \"Marking a debug operation as def\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 100, __PRETTY_FUNCTION__))
;
101 if (IsDef == Val)
102 return;
103 assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported")((!IsDeadOrKill && "Changing def/use with dead/kill set not supported"
) ? static_cast<void> (0) : __assert_fail ("!IsDeadOrKill && \"Changing def/use with dead/kill set not supported\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 103, __PRETTY_FUNCTION__))
;
104 // MRI may keep uses and defs in different list positions.
105 if (MachineFunction *MF = getMFIfAvailable(*this)) {
106 MachineRegisterInfo &MRI = MF->getRegInfo();
107 MRI.removeRegOperandFromUseList(this);
108 IsDef = Val;
109 MRI.addRegOperandToUseList(this);
110 return;
111 }
112 IsDef = Val;
113}
114
115bool MachineOperand::isRenamable() const {
116 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 116, __PRETTY_FUNCTION__))
;
117 assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&((TargetRegisterInfo::isPhysicalRegister(getReg()) &&
"isRenamable should only be checked on physical registers") ?
static_cast<void> (0) : __assert_fail ("TargetRegisterInfo::isPhysicalRegister(getReg()) && \"isRenamable should only be checked on physical registers\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 118, __PRETTY_FUNCTION__))
118 "isRenamable should only be checked on physical registers")((TargetRegisterInfo::isPhysicalRegister(getReg()) &&
"isRenamable should only be checked on physical registers") ?
static_cast<void> (0) : __assert_fail ("TargetRegisterInfo::isPhysicalRegister(getReg()) && \"isRenamable should only be checked on physical registers\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 118, __PRETTY_FUNCTION__))
;
119 if (!IsRenamable)
120 return false;
121
122 const MachineInstr *MI = getParent();
123 if (!MI)
124 return true;
125
126 if (isDef())
127 return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
128
129 assert(isUse() && "Reg is not def or use")((isUse() && "Reg is not def or use") ? static_cast<
void> (0) : __assert_fail ("isUse() && \"Reg is not def or use\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 129, __PRETTY_FUNCTION__))
;
130 return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
131}
132
133void MachineOperand::setIsRenamable(bool Val) {
134 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 134, __PRETTY_FUNCTION__))
;
135 assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&((TargetRegisterInfo::isPhysicalRegister(getReg()) &&
"setIsRenamable should only be called on physical registers"
) ? static_cast<void> (0) : __assert_fail ("TargetRegisterInfo::isPhysicalRegister(getReg()) && \"setIsRenamable should only be called on physical registers\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 136, __PRETTY_FUNCTION__))
136 "setIsRenamable should only be called on physical registers")((TargetRegisterInfo::isPhysicalRegister(getReg()) &&
"setIsRenamable should only be called on physical registers"
) ? static_cast<void> (0) : __assert_fail ("TargetRegisterInfo::isPhysicalRegister(getReg()) && \"setIsRenamable should only be called on physical registers\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 136, __PRETTY_FUNCTION__))
;
137 IsRenamable = Val;
138}
139
140// If this operand is currently a register operand, and if this is in a
141// function, deregister the operand from the register's use/def list.
142void MachineOperand::removeRegFromUses() {
143 if (!isReg() || !isOnRegUseList())
144 return;
145
146 if (MachineFunction *MF = getMFIfAvailable(*this))
147 MF->getRegInfo().removeRegOperandFromUseList(this);
148}
149
150/// ChangeToImmediate - Replace this operand with a new immediate operand of
151/// the specified value. If an operand is known to be an immediate already,
152/// the setImm method should be used.
153void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
154 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm")(((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an imm\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 154, __PRETTY_FUNCTION__))
;
155
156 removeRegFromUses();
157
158 OpKind = MO_Immediate;
159 Contents.ImmVal = ImmVal;
160}
161
162void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
163 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm")(((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an imm\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 163, __PRETTY_FUNCTION__))
;
164
165 removeRegFromUses();
166
167 OpKind = MO_FPImmediate;
168 Contents.CFP = FPImm;
169}
170
171void MachineOperand::ChangeToES(const char *SymName,
172 unsigned char TargetFlags) {
173 assert((!isReg() || !isTied()) &&(((!isReg() || !isTied()) && "Cannot change a tied operand into an external symbol"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an external symbol\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 174, __PRETTY_FUNCTION__))
174 "Cannot change a tied operand into an external symbol")(((!isReg() || !isTied()) && "Cannot change a tied operand into an external symbol"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an external symbol\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 174, __PRETTY_FUNCTION__))
;
175
176 removeRegFromUses();
177
178 OpKind = MO_ExternalSymbol;
179 Contents.OffsetedInfo.Val.SymbolName = SymName;
180 setOffset(0); // Offset is always 0.
181 setTargetFlags(TargetFlags);
182}
183
184void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
185 assert((!isReg() || !isTied()) &&(((!isReg() || !isTied()) && "Cannot change a tied operand into an MCSymbol"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an MCSymbol\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 186, __PRETTY_FUNCTION__))
186 "Cannot change a tied operand into an MCSymbol")(((!isReg() || !isTied()) && "Cannot change a tied operand into an MCSymbol"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into an MCSymbol\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 186, __PRETTY_FUNCTION__))
;
187
188 removeRegFromUses();
189
190 OpKind = MO_MCSymbol;
191 Contents.Sym = Sym;
192}
193
194void MachineOperand::ChangeToFrameIndex(int Idx) {
195 assert((!isReg() || !isTied()) &&(((!isReg() || !isTied()) && "Cannot change a tied operand into a FrameIndex"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into a FrameIndex\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 196, __PRETTY_FUNCTION__))
196 "Cannot change a tied operand into a FrameIndex")(((!isReg() || !isTied()) && "Cannot change a tied operand into a FrameIndex"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into a FrameIndex\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 196, __PRETTY_FUNCTION__))
;
197
198 removeRegFromUses();
199
200 OpKind = MO_FrameIndex;
201 setIndex(Idx);
202}
203
204void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
205 unsigned char TargetFlags) {
206 assert((!isReg() || !isTied()) &&(((!isReg() || !isTied()) && "Cannot change a tied operand into a FrameIndex"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into a FrameIndex\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 207, __PRETTY_FUNCTION__))
207 "Cannot change a tied operand into a FrameIndex")(((!isReg() || !isTied()) && "Cannot change a tied operand into a FrameIndex"
) ? static_cast<void> (0) : __assert_fail ("(!isReg() || !isTied()) && \"Cannot change a tied operand into a FrameIndex\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 207, __PRETTY_FUNCTION__))
;
208
209 removeRegFromUses();
210
211 OpKind = MO_TargetIndex;
212 setIndex(Idx);
213 setOffset(Offset);
214 setTargetFlags(TargetFlags);
215}
216
217/// ChangeToRegister - Replace this operand with a new register operand of
218/// the specified value. If an operand is known to be an register already,
219/// the setReg method should be used.
220void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
221 bool isKill, bool isDead, bool isUndef,
222 bool isDebug) {
223 MachineRegisterInfo *RegInfo = nullptr;
224 if (MachineFunction *MF = getMFIfAvailable(*this))
225 RegInfo = &MF->getRegInfo();
226 // If this operand is already a register operand, remove it from the
227 // register's use/def lists.
228 bool WasReg = isReg();
229 if (RegInfo && WasReg)
230 RegInfo->removeRegOperandFromUseList(this);
231
232 // Change this to a register and set the reg#.
233 assert(!(isDead && !isDef) && "Dead flag on non-def")((!(isDead && !isDef) && "Dead flag on non-def"
) ? static_cast<void> (0) : __assert_fail ("!(isDead && !isDef) && \"Dead flag on non-def\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 233, __PRETTY_FUNCTION__))
;
234 assert(!(isKill && isDef) && "Kill flag on def")((!(isKill && isDef) && "Kill flag on def") ?
static_cast<void> (0) : __assert_fail ("!(isKill && isDef) && \"Kill flag on def\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 234, __PRETTY_FUNCTION__))
;
235 OpKind = MO_Register;
236 SmallContents.RegNo = Reg;
237 SubReg_TargetFlags = 0;
238 IsDef = isDef;
239 IsImp = isImp;
240 IsDeadOrKill = isKill | isDead;
241 IsRenamable = false;
242 IsUndef = isUndef;
243 IsInternalRead = false;
244 IsEarlyClobber = false;
245 IsDebug = isDebug;
246 // Ensure isOnRegUseList() returns false.
247 Contents.Reg.Prev = nullptr;
248 // Preserve the tie when the operand was already a register.
249 if (!WasReg)
250 TiedTo = 0;
251
252 // If this operand is embedded in a function, add the operand to the
253 // register's use/def list.
254 if (RegInfo)
255 RegInfo->addRegOperandToUseList(this);
256}
257
258/// isIdenticalTo - Return true if this operand is identical to the specified
259/// operand. Note that this should stay in sync with the hash_value overload
260/// below.
261bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
262 if (getType() != Other.getType() ||
263 getTargetFlags() != Other.getTargetFlags())
264 return false;
265
266 switch (getType()) {
267 case MachineOperand::MO_Register:
268 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
269 getSubReg() == Other.getSubReg();
270 case MachineOperand::MO_Immediate:
271 return getImm() == Other.getImm();
272 case MachineOperand::MO_CImmediate:
273 return getCImm() == Other.getCImm();
274 case MachineOperand::MO_FPImmediate:
275 return getFPImm() == Other.getFPImm();
276 case MachineOperand::MO_MachineBasicBlock:
277 return getMBB() == Other.getMBB();
278 case MachineOperand::MO_FrameIndex:
279 return getIndex() == Other.getIndex();
280 case MachineOperand::MO_ConstantPoolIndex:
281 case MachineOperand::MO_TargetIndex:
282 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
283 case MachineOperand::MO_JumpTableIndex:
284 return getIndex() == Other.getIndex();
285 case MachineOperand::MO_GlobalAddress:
286 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
287 case MachineOperand::MO_ExternalSymbol:
288 return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
289 getOffset() == Other.getOffset();
290 case MachineOperand::MO_BlockAddress:
291 return getBlockAddress() == Other.getBlockAddress() &&
292 getOffset() == Other.getOffset();
293 case MachineOperand::MO_RegisterMask:
294 case MachineOperand::MO_RegisterLiveOut: {
295 // Shallow compare of the two RegMasks
296 const uint32_t *RegMask = getRegMask();
297 const uint32_t *OtherRegMask = Other.getRegMask();
298 if (RegMask == OtherRegMask)
299 return true;
300
301 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
302 // Calculate the size of the RegMask
303 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
304 unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
305
306 // Deep compare of the two RegMasks
307 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
308 }
309 // We don't know the size of the RegMask, so we can't deep compare the two
310 // reg masks.
311 return false;
312 }
313 case MachineOperand::MO_MCSymbol:
314 return getMCSymbol() == Other.getMCSymbol();
315 case MachineOperand::MO_CFIIndex:
316 return getCFIIndex() == Other.getCFIIndex();
317 case MachineOperand::MO_Metadata:
318 return getMetadata() == Other.getMetadata();
319 case MachineOperand::MO_IntrinsicID:
320 return getIntrinsicID() == Other.getIntrinsicID();
321 case MachineOperand::MO_Predicate:
322 return getPredicate() == Other.getPredicate();
323 }
324 llvm_unreachable("Invalid machine operand type")::llvm::llvm_unreachable_internal("Invalid machine operand type"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 324)
;
325}
326
327// Note: this must stay exactly in sync with isIdenticalTo above.
328hash_code llvm::hash_value(const MachineOperand &MO) {
329 switch (MO.getType()) {
330 case MachineOperand::MO_Register:
331 // Register operands don't have target flags.
332 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
333 case MachineOperand::MO_Immediate:
334 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
335 case MachineOperand::MO_CImmediate:
336 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
337 case MachineOperand::MO_FPImmediate:
338 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
339 case MachineOperand::MO_MachineBasicBlock:
340 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
341 case MachineOperand::MO_FrameIndex:
342 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
343 case MachineOperand::MO_ConstantPoolIndex:
344 case MachineOperand::MO_TargetIndex:
345 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
346 MO.getOffset());
347 case MachineOperand::MO_JumpTableIndex:
348 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
349 case MachineOperand::MO_ExternalSymbol:
350 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
351 MO.getSymbolName());
352 case MachineOperand::MO_GlobalAddress:
353 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
354 MO.getOffset());
355 case MachineOperand::MO_BlockAddress:
356 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
357 MO.getOffset());
358 case MachineOperand::MO_RegisterMask:
359 case MachineOperand::MO_RegisterLiveOut:
360 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
361 case MachineOperand::MO_Metadata:
362 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
363 case MachineOperand::MO_MCSymbol:
364 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
365 case MachineOperand::MO_CFIIndex:
366 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
367 case MachineOperand::MO_IntrinsicID:
368 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
369 case MachineOperand::MO_Predicate:
370 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
371 }
372 llvm_unreachable("Invalid machine operand type")::llvm::llvm_unreachable_internal("Invalid machine operand type"
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 372)
;
373}
374
375// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
376// it.
377static void tryToGetTargetInfo(const MachineOperand &MO,
378 const TargetRegisterInfo *&TRI,
379 const TargetIntrinsicInfo *&IntrinsicInfo) {
380 if (const MachineFunction *MF = getMFIfAvailable(MO)) {
381 TRI = MF->getSubtarget().getRegisterInfo();
382 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
383 }
384}
385
386static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
387 const auto *TII = MF.getSubtarget().getInstrInfo();
388 assert(TII && "expected instruction info")((TII && "expected instruction info") ? static_cast<
void> (0) : __assert_fail ("TII && \"expected instruction info\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 388, __PRETTY_FUNCTION__))
;
389 auto Indices = TII->getSerializableTargetIndices();
390 auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
391 return I.first == Index;
392 });
393 if (Found != Indices.end())
394 return Found->second;
395 return nullptr;
396}
397
398static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
399 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
400 for (const auto &I : Flags) {
401 if (I.first == TF) {
402 return I.second;
403 }
404 }
405 return nullptr;
406}
407
408static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
409 const TargetRegisterInfo *TRI) {
410 if (!TRI) {
411 OS << "%dwarfreg." << DwarfReg;
412 return;
413 }
414
415 int Reg = TRI->getLLVMRegNum(DwarfReg, true);
416 if (Reg == -1) {
417 OS << "<badreg>";
418 return;
419 }
420 OS << printReg(Reg, TRI);
421}
422
423static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
424 ModuleSlotTracker &MST) {
425 OS << "%ir-block.";
426 if (BB.hasName()) {
427 printLLVMNameWithoutPrefix(OS, BB.getName());
428 return;
429 }
430 Optional<int> Slot;
431 if (const Function *F = BB.getParent()) {
432 if (F == MST.getCurrentFunction()) {
433 Slot = MST.getLocalSlot(&BB);
434 } else if (const Module *M = F->getParent()) {
435 ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
436 CustomMST.incorporateFunction(*F);
437 Slot = CustomMST.getLocalSlot(&BB);
438 }
439 }
440 if (Slot)
441 MachineOperand::printIRSlotNumber(OS, *Slot);
442 else
443 OS << "<unknown>";
444}
445
446static void printIRValueReference(raw_ostream &OS, const Value &V,
447 ModuleSlotTracker &MST) {
448 if (isa<GlobalValue>(V)) {
449 V.printAsOperand(OS, /*PrintType=*/false, MST);
450 return;
451 }
452 if (isa<Constant>(V)) {
453 // Machine memory operands can load/store to/from constant value pointers.
454 OS << '`';
455 V.printAsOperand(OS, /*PrintType=*/true, MST);
456 OS << '`';
457 return;
458 }
459 OS << "%ir.";
460 if (V.hasName()) {
461 printLLVMNameWithoutPrefix(OS, V.getName());
462 return;
463 }
464 int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
465 MachineOperand::printIRSlotNumber(OS, Slot);
466}
467
468static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
469 SyncScope::ID SSID,
470 SmallVectorImpl<StringRef> &SSNs) {
471 switch (SSID) {
472 case SyncScope::System:
473 break;
474 default:
475 if (SSNs.empty())
476 Context.getSyncScopeNames(SSNs);
477
478 OS << "syncscope(\"";
479 printEscapedString(SSNs[SSID], OS);
480 OS << "\") ";
481 break;
482 }
483}
484
485static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
486 unsigned TMMOFlag) {
487 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
488 for (const auto &I : Flags) {
489 if (I.first == TMMOFlag) {
490 return I.second;
491 }
492 }
493 return nullptr;
494}
495
496static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
497 const MachineFrameInfo *MFI) {
498 StringRef Name;
499 if (MFI) {
500 IsFixed = MFI->isFixedObjectIndex(FrameIndex);
501 if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
502 if (Alloca->hasName())
503 Name = Alloca->getName();
504 if (IsFixed)
505 FrameIndex -= MFI->getObjectIndexBegin();
506 }
507 MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
508}
509
510void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
511 const TargetRegisterInfo *TRI) {
512 OS << "%subreg.";
513 if (TRI)
514 OS << TRI->getSubRegIndexName(Index);
515 else
516 OS << Index;
517}
518
519void MachineOperand::printTargetFlags(raw_ostream &OS,
520 const MachineOperand &Op) {
521 if (!Op.getTargetFlags())
522 return;
523 const MachineFunction *MF = getMFIfAvailable(Op);
524 if (!MF)
525 return;
526
527 const auto *TII = MF->getSubtarget().getInstrInfo();
528 assert(TII && "expected instruction info")((TII && "expected instruction info") ? static_cast<
void> (0) : __assert_fail ("TII && \"expected instruction info\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 528, __PRETTY_FUNCTION__))
;
529 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
530 OS << "target-flags(";
531 const bool HasDirectFlags = Flags.first;
532 const bool HasBitmaskFlags = Flags.second;
533 if (!HasDirectFlags && !HasBitmaskFlags) {
534 OS << "<unknown>) ";
535 return;
536 }
537 if (HasDirectFlags) {
538 if (const auto *Name = getTargetFlagName(TII, Flags.first))
539 OS << Name;
540 else
541 OS << "<unknown target flag>";
542 }
543 if (!HasBitmaskFlags) {
544 OS << ") ";
545 return;
546 }
547 bool IsCommaNeeded = HasDirectFlags;
548 unsigned BitMask = Flags.second;
549 auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
550 for (const auto &Mask : BitMasks) {
551 // Check if the flag's bitmask has the bits of the current mask set.
552 if ((BitMask & Mask.first) == Mask.first) {
553 if (IsCommaNeeded)
554 OS << ", ";
555 IsCommaNeeded = true;
556 OS << Mask.second;
557 // Clear the bits which were serialized from the flag's bitmask.
558 BitMask &= ~(Mask.first);
559 }
560 }
561 if (BitMask) {
562 // When the resulting flag's bitmask isn't zero, we know that we didn't
563 // serialize all of the bit flags.
564 if (IsCommaNeeded)
565 OS << ", ";
566 OS << "<unknown bitmask target flag>";
567 }
568 OS << ") ";
569}
570
571void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
572 OS << "<mcsymbol " << Sym << ">";
573}
574
575void MachineOperand::printStackObjectReference(raw_ostream &OS,
576 unsigned FrameIndex,
577 bool IsFixed, StringRef Name) {
578 if (IsFixed) {
579 OS << "%fixed-stack." << FrameIndex;
580 return;
581 }
582
583 OS << "%stack." << FrameIndex;
584 if (!Name.empty())
585 OS << '.' << Name;
586}
587
588void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
589 if (Offset == 0)
590 return;
591 if (Offset < 0) {
592 OS << " - " << -Offset;
593 return;
594 }
595 OS << " + " << Offset;
596}
597
598void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
599 if (Slot == -1)
600 OS << "<badref>";
601 else
602 OS << Slot;
603}
604
605static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
606 const TargetRegisterInfo *TRI) {
607 switch (CFI.getOperation()) {
608 case MCCFIInstruction::OpSameValue:
609 OS << "same_value ";
610 if (MCSymbol *Label = CFI.getLabel())
611 MachineOperand::printSymbol(OS, *Label);
612 printCFIRegister(CFI.getRegister(), OS, TRI);
613 break;
614 case MCCFIInstruction::OpRememberState:
615 OS << "remember_state ";
616 if (MCSymbol *Label = CFI.getLabel())
617 MachineOperand::printSymbol(OS, *Label);
618 break;
619 case MCCFIInstruction::OpRestoreState:
620 OS << "restore_state ";
621 if (MCSymbol *Label = CFI.getLabel())
622 MachineOperand::printSymbol(OS, *Label);
623 break;
624 case MCCFIInstruction::OpOffset:
625 OS << "offset ";
626 if (MCSymbol *Label = CFI.getLabel())
627 MachineOperand::printSymbol(OS, *Label);
628 printCFIRegister(CFI.getRegister(), OS, TRI);
629 OS << ", " << CFI.getOffset();
630 break;
631 case MCCFIInstruction::OpDefCfaRegister:
632 OS << "def_cfa_register ";
633 if (MCSymbol *Label = CFI.getLabel())
634 MachineOperand::printSymbol(OS, *Label);
635 printCFIRegister(CFI.getRegister(), OS, TRI);
636 break;
637 case MCCFIInstruction::OpDefCfaOffset:
638 OS << "def_cfa_offset ";
639 if (MCSymbol *Label = CFI.getLabel())
640 MachineOperand::printSymbol(OS, *Label);
641 OS << CFI.getOffset();
642 break;
643 case MCCFIInstruction::OpDefCfa:
644 OS << "def_cfa ";
645 if (MCSymbol *Label = CFI.getLabel())
646 MachineOperand::printSymbol(OS, *Label);
647 printCFIRegister(CFI.getRegister(), OS, TRI);
648 OS << ", " << CFI.getOffset();
649 break;
650 case MCCFIInstruction::OpRelOffset:
651 OS << "rel_offset ";
652 if (MCSymbol *Label = CFI.getLabel())
653 MachineOperand::printSymbol(OS, *Label);
654 printCFIRegister(CFI.getRegister(), OS, TRI);
655 OS << ", " << CFI.getOffset();
656 break;
657 case MCCFIInstruction::OpAdjustCfaOffset:
658 OS << "adjust_cfa_offset ";
659 if (MCSymbol *Label = CFI.getLabel())
660 MachineOperand::printSymbol(OS, *Label);
661 OS << CFI.getOffset();
662 break;
663 case MCCFIInstruction::OpRestore:
664 OS << "restore ";
665 if (MCSymbol *Label = CFI.getLabel())
666 MachineOperand::printSymbol(OS, *Label);
667 printCFIRegister(CFI.getRegister(), OS, TRI);
668 break;
669 case MCCFIInstruction::OpEscape: {
670 OS << "escape ";
671 if (MCSymbol *Label = CFI.getLabel())
672 MachineOperand::printSymbol(OS, *Label);
673 if (!CFI.getValues().empty()) {
674 size_t e = CFI.getValues().size() - 1;
675 for (size_t i = 0; i < e; ++i)
676 OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
677 OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
678 }
679 break;
680 }
681 case MCCFIInstruction::OpUndefined:
682 OS << "undefined ";
683 if (MCSymbol *Label = CFI.getLabel())
684 MachineOperand::printSymbol(OS, *Label);
685 printCFIRegister(CFI.getRegister(), OS, TRI);
686 break;
687 case MCCFIInstruction::OpRegister:
688 OS << "register ";
689 if (MCSymbol *Label = CFI.getLabel())
690 MachineOperand::printSymbol(OS, *Label);
691 printCFIRegister(CFI.getRegister(), OS, TRI);
692 OS << ", ";
693 printCFIRegister(CFI.getRegister2(), OS, TRI);
694 break;
695 case MCCFIInstruction::OpWindowSave:
696 OS << "window_save ";
697 if (MCSymbol *Label = CFI.getLabel())
698 MachineOperand::printSymbol(OS, *Label);
699 break;
700 case MCCFIInstruction::OpNegateRAState:
701 OS << "negate_ra_sign_state ";
702 if (MCSymbol *Label = CFI.getLabel())
703 MachineOperand::printSymbol(OS, *Label);
704 break;
705 default:
706 // TODO: Print the other CFI Operations.
707 OS << "<unserializable cfi directive>";
708 break;
709 }
710}
711
712void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
713 const TargetIntrinsicInfo *IntrinsicInfo) const {
714 print(OS, LLT{}, TRI, IntrinsicInfo);
715}
716
717void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
718 const TargetRegisterInfo *TRI,
719 const TargetIntrinsicInfo *IntrinsicInfo) const {
720 tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
721 ModuleSlotTracker DummyMST(nullptr);
722 print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
723 /*ShouldPrintRegisterTies=*/true,
724 /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
725}
726
727void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
728 LLT TypeToPrint, bool PrintDef, bool IsStandalone,
729 bool ShouldPrintRegisterTies,
730 unsigned TiedOperandIdx,
731 const TargetRegisterInfo *TRI,
732 const TargetIntrinsicInfo *IntrinsicInfo) const {
733 printTargetFlags(OS, *this);
734 switch (getType()) {
735 case MachineOperand::MO_Register: {
736 unsigned Reg = getReg();
737 if (isImplicit())
738 OS << (isDef() ? "implicit-def " : "implicit ");
739 else if (PrintDef && isDef())
740 // Print the 'def' flag only when the operand is defined after '='.
741 OS << "def ";
742 if (isInternalRead())
743 OS << "internal ";
744 if (isDead())
745 OS << "dead ";
746 if (isKill())
747 OS << "killed ";
748 if (isUndef())
749 OS << "undef ";
750 if (isEarlyClobber())
751 OS << "early-clobber ";
752 if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable())
753 OS << "renamable ";
754 // isDebug() is exactly true for register operands of a DBG_VALUE. So we
755 // simply infer it when parsing and do not need to print it.
756
757 const MachineRegisterInfo *MRI = nullptr;
758 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
759 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
760 MRI = &MF->getRegInfo();
761 }
762 }
763
764 OS << printReg(Reg, TRI, 0, MRI);
765 // Print the sub register.
766 if (unsigned SubReg = getSubReg()) {
767 if (TRI)
768 OS << '.' << TRI->getSubRegIndexName(SubReg);
769 else
770 OS << ".subreg" << SubReg;
771 }
772 // Print the register class / bank.
773 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
774 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
775 const MachineRegisterInfo &MRI = MF->getRegInfo();
776 if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
777 OS << ':';
778 OS << printRegClassOrBank(Reg, MRI, TRI);
779 }
780 }
781 }
782 // Print ties.
783 if (ShouldPrintRegisterTies && isTied() && !isDef())
784 OS << "(tied-def " << TiedOperandIdx << ")";
785 // Print types.
786 if (TypeToPrint.isValid())
787 OS << '(' << TypeToPrint << ')';
788 break;
789 }
790 case MachineOperand::MO_Immediate:
791 OS << getImm();
792 break;
793 case MachineOperand::MO_CImmediate:
794 getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
795 break;
796 case MachineOperand::MO_FPImmediate:
797 getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
798 break;
799 case MachineOperand::MO_MachineBasicBlock:
800 OS << printMBBReference(*getMBB());
801 break;
802 case MachineOperand::MO_FrameIndex: {
803 int FrameIndex = getIndex();
804 bool IsFixed = false;
805 const MachineFrameInfo *MFI = nullptr;
806 if (const MachineFunction *MF = getMFIfAvailable(*this))
807 MFI = &MF->getFrameInfo();
808 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
809 break;
810 }
811 case MachineOperand::MO_ConstantPoolIndex:
812 OS << "%const." << getIndex();
813 printOperandOffset(OS, getOffset());
814 break;
815 case MachineOperand::MO_TargetIndex: {
816 OS << "target-index(";
817 const char *Name = "<unknown>";
818 if (const MachineFunction *MF = getMFIfAvailable(*this))
819 if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
820 Name = TargetIndexName;
821 OS << Name << ')';
822 printOperandOffset(OS, getOffset());
823 break;
824 }
825 case MachineOperand::MO_JumpTableIndex:
826 OS << printJumpTableEntryReference(getIndex());
827 break;
828 case MachineOperand::MO_GlobalAddress:
829 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
830 printOperandOffset(OS, getOffset());
831 break;
832 case MachineOperand::MO_ExternalSymbol: {
833 StringRef Name = getSymbolName();
834 OS << '&';
835 if (Name.empty()) {
836 OS << "\"\"";
837 } else {
838 printLLVMNameWithoutPrefix(OS, Name);
839 }
840 printOperandOffset(OS, getOffset());
841 break;
842 }
843 case MachineOperand::MO_BlockAddress: {
844 OS << "blockaddress(";
845 getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
846 MST);
847 OS << ", ";
848 printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
849 OS << ')';
850 MachineOperand::printOperandOffset(OS, getOffset());
851 break;
852 }
853 case MachineOperand::MO_RegisterMask: {
854 OS << "<regmask";
855 if (TRI) {
856 unsigned NumRegsInMask = 0;
857 unsigned NumRegsEmitted = 0;
858 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
859 unsigned MaskWord = i / 32;
860 unsigned MaskBit = i % 32;
861 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
862 if (PrintRegMaskNumRegs < 0 ||
863 NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
864 OS << " " << printReg(i, TRI);
865 NumRegsEmitted++;
866 }
867 NumRegsInMask++;
868 }
869 }
870 if (NumRegsEmitted != NumRegsInMask)
871 OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
872 } else {
873 OS << " ...";
874 }
875 OS << ">";
876 break;
877 }
878 case MachineOperand::MO_RegisterLiveOut: {
879 const uint32_t *RegMask = getRegLiveOut();
880 OS << "liveout(";
881 if (!TRI) {
882 OS << "<unknown>";
883 } else {
884 bool IsCommaNeeded = false;
885 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
886 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
887 if (IsCommaNeeded)
888 OS << ", ";
889 OS << printReg(Reg, TRI);
890 IsCommaNeeded = true;
891 }
892 }
893 }
894 OS << ")";
895 break;
896 }
897 case MachineOperand::MO_Metadata:
898 getMetadata()->printAsOperand(OS, MST);
899 break;
900 case MachineOperand::MO_MCSymbol:
901 printSymbol(OS, *getMCSymbol());
902 break;
903 case MachineOperand::MO_CFIIndex: {
904 if (const MachineFunction *MF = getMFIfAvailable(*this))
905 printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
906 else
907 OS << "<cfi directive>";
908 break;
909 }
910 case MachineOperand::MO_IntrinsicID: {
911 Intrinsic::ID ID = getIntrinsicID();
912 if (ID < Intrinsic::num_intrinsics)
913 OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
914 else if (IntrinsicInfo)
915 OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
916 else
917 OS << "intrinsic(" << ID << ')';
918 break;
919 }
920 case MachineOperand::MO_Predicate: {
921 auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
922 OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
923 << CmpInst::getPredicateName(Pred) << ')';
924 break;
925 }
926 }
927}
928
929#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
930LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineOperand::dump() const { dbgs() << *this << '\n'; }
931#endif
932
933//===----------------------------------------------------------------------===//
934// MachineMemOperand Implementation
935//===----------------------------------------------------------------------===//
936
937/// getAddrSpace - Return the LLVM IR address space number that this pointer
938/// points into.
939unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
940
941/// isDereferenceable - Return true if V is always dereferenceable for
942/// Offset + Size byte.
943bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
944 const DataLayout &DL) const {
945 if (!V.is<const Value *>())
946 return false;
947
948 const Value *BasePtr = V.get<const Value *>();
949 if (BasePtr == nullptr)
950 return false;
951
952 return isDereferenceableAndAlignedPointer(
953 BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
954}
955
956/// getConstantPool - Return a MachinePointerInfo record that refers to the
957/// constant pool.
958MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
959 return MachinePointerInfo(MF.getPSVManager().getConstantPool());
960}
961
962/// getFixedStack - Return a MachinePointerInfo record that refers to the
963/// the specified FrameIndex.
964MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
965 int FI, int64_t Offset) {
966 return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
967}
968
969MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
970 return MachinePointerInfo(MF.getPSVManager().getJumpTable());
971}
972
973MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
974 return MachinePointerInfo(MF.getPSVManager().getGOT());
975}
976
977MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
978 int64_t Offset, uint8_t ID) {
979 return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
980}
981
982MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
983 return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
984}
985
986MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
987 uint64_t s, uint64_t a,
988 const AAMDNodes &AAInfo,
989 const MDNode *Ranges, SyncScope::ID SSID,
990 AtomicOrdering Ordering,
991 AtomicOrdering FailureOrdering)
992 : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
993 AAInfo(AAInfo), Ranges(Ranges) {
994 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||(((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue
*>() || isa<PointerType>(PtrInfo.V.get<const Value
*>()->getType())) && "invalid pointer value") ?
static_cast<void> (0) : __assert_fail ("(PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() || isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) && \"invalid pointer value\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 996, __PRETTY_FUNCTION__))
995 isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&(((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue
*>() || isa<PointerType>(PtrInfo.V.get<const Value
*>()->getType())) && "invalid pointer value") ?
static_cast<void> (0) : __assert_fail ("(PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() || isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) && \"invalid pointer value\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 996, __PRETTY_FUNCTION__))
996 "invalid pointer value")(((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue
*>() || isa<PointerType>(PtrInfo.V.get<const Value
*>()->getType())) && "invalid pointer value") ?
static_cast<void> (0) : __assert_fail ("(PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() || isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) && \"invalid pointer value\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 996, __PRETTY_FUNCTION__))
;
997 assert(getBaseAlignment() == a && "Alignment is not a power of 2!")((getBaseAlignment() == a && "Alignment is not a power of 2!"
) ? static_cast<void> (0) : __assert_fail ("getBaseAlignment() == a && \"Alignment is not a power of 2!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 997, __PRETTY_FUNCTION__))
;
998 assert((isLoad() || isStore()) && "Not a load/store!")(((isLoad() || isStore()) && "Not a load/store!") ? static_cast
<void> (0) : __assert_fail ("(isLoad() || isStore()) && \"Not a load/store!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 998, __PRETTY_FUNCTION__))
;
999
1000 AtomicInfo.SSID = static_cast<unsigned>(SSID);
1001 assert(getSyncScopeID() == SSID && "Value truncated")((getSyncScopeID() == SSID && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getSyncScopeID() == SSID && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 1001, __PRETTY_FUNCTION__))
;
1002 AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1003 assert(getOrdering() == Ordering && "Value truncated")((getOrdering() == Ordering && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getOrdering() == Ordering && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 1003, __PRETTY_FUNCTION__))
;
1004 AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1005 assert(getFailureOrdering() == FailureOrdering && "Value truncated")((getFailureOrdering() == FailureOrdering && "Value truncated"
) ? static_cast<void> (0) : __assert_fail ("getFailureOrdering() == FailureOrdering && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 1005, __PRETTY_FUNCTION__))
;
1006}
1007
1008/// Profile - Gather unique data for the object.
1009///
1010void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1011 ID.AddInteger(getOffset());
1012 ID.AddInteger(Size);
1013 ID.AddPointer(getOpaqueValue());
1014 ID.AddInteger(getFlags());
1015 ID.AddInteger(getBaseAlignment());
1016}
1017
1018void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1019 // The Value and Offset may differ due to CSE. But the flags and size
1020 // should be the same.
1021 assert(MMO->getFlags() == getFlags() && "Flags mismatch!")((MMO->getFlags() == getFlags() && "Flags mismatch!"
) ? static_cast<void> (0) : __assert_fail ("MMO->getFlags() == getFlags() && \"Flags mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 1021, __PRETTY_FUNCTION__))
;
1022 assert(MMO->getSize() == getSize() && "Size mismatch!")((MMO->getSize() == getSize() && "Size mismatch!")
? static_cast<void> (0) : __assert_fail ("MMO->getSize() == getSize() && \"Size mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 1022, __PRETTY_FUNCTION__))
;
1023
1024 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1025 // Update the alignment value.
1026 BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1027 // Also update the base and offset, because the new alignment may
1028 // not be applicable with the old ones.
1029 PtrInfo = MMO->PtrInfo;
1030 }
1031}
1032
1033/// getAlignment - Return the minimum known alignment in bytes of the
1034/// actual memory reference.
1035uint64_t MachineMemOperand::getAlignment() const {
1036 return MinAlign(getBaseAlignment(), getOffset());
1037}
1038
1039void MachineMemOperand::print(raw_ostream &OS) const {
1040 ModuleSlotTracker DummyMST(nullptr);
1041 print(OS, DummyMST);
1
Calling 'MachineMemOperand::print'
1042}
1043
1044void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
1045 SmallVector<StringRef, 0> SSNs;
1046 LLVMContext Ctx;
1047 print(OS, MST, SSNs, Ctx, nullptr, nullptr);
2
Passing null pointer value via 6th parameter 'TII'
3
Calling 'MachineMemOperand::print'
1048}
1049
1050void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1051 SmallVectorImpl<StringRef> &SSNs,
1052 const LLVMContext &Context,
1053 const MachineFrameInfo *MFI,
1054 const TargetInstrInfo *TII) const {
1055 OS << '(';
1056 if (isVolatile())
4
Assuming the condition is false
5
Taking false branch
1057 OS << "volatile ";
1058 if (isNonTemporal())
6
Assuming the condition is false
7
Taking false branch
1059 OS << "non-temporal ";
1060 if (isDereferenceable())
8
Assuming the condition is false
9
Taking false branch
1061 OS << "dereferenceable ";
1062 if (isInvariant())
10
Assuming the condition is false
11
Taking false branch
1063 OS << "invariant ";
1064 if (getFlags() & MachineMemOperand::MOTargetFlag1)
12
Assuming the condition is false
13
Taking false branch
1065 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1066 << "\" ";
1067 if (getFlags() & MachineMemOperand::MOTargetFlag2)
14
Assuming the condition is false
15
Taking false branch
1068 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1069 << "\" ";
1070 if (getFlags() & MachineMemOperand::MOTargetFlag3)
16
Assuming the condition is true
17
Taking true branch
1071 OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
18
Forming reference to null pointer
1072 << "\" ";
1073
1074 assert((isLoad() || isStore()) &&(((isLoad() || isStore()) && "machine memory operand must be a load or store (or both)"
) ? static_cast<void> (0) : __assert_fail ("(isLoad() || isStore()) && \"machine memory operand must be a load or store (or both)\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 1075, __PRETTY_FUNCTION__))
1075 "machine memory operand must be a load or store (or both)")(((isLoad() || isStore()) && "machine memory operand must be a load or store (or both)"
) ? static_cast<void> (0) : __assert_fail ("(isLoad() || isStore()) && \"machine memory operand must be a load or store (or both)\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 1075, __PRETTY_FUNCTION__))
;
1076 if (isLoad())
1077 OS << "load ";
1078 if (isStore())
1079 OS << "store ";
1080
1081 printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1082
1083 if (getOrdering() != AtomicOrdering::NotAtomic)
1084 OS << toIRString(getOrdering()) << ' ';
1085 if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1086 OS << toIRString(getFailureOrdering()) << ' ';
1087
1088 if (getSize() == MemoryLocation::UnknownSize)
1089 OS << "unknown-size";
1090 else
1091 OS << getSize();
1092
1093 if (const Value *Val = getValue()) {
1094 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1095 printIRValueReference(OS, *Val, MST);
1096 } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1097 OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1098 assert(PVal && "Expected a pseudo source value")((PVal && "Expected a pseudo source value") ? static_cast
<void> (0) : __assert_fail ("PVal && \"Expected a pseudo source value\""
, "/build/llvm-toolchain-snapshot-8~svn350071/lib/CodeGen/MachineOperand.cpp"
, 1098, __PRETTY_FUNCTION__))
;
1099 switch (PVal->kind()) {
1100 case PseudoSourceValue::Stack:
1101 OS << "stack";
1102 break;
1103 case PseudoSourceValue::GOT:
1104 OS << "got";
1105 break;
1106 case PseudoSourceValue::JumpTable:
1107 OS << "jump-table";
1108 break;
1109 case PseudoSourceValue::ConstantPool:
1110 OS << "constant-pool";
1111 break;
1112 case PseudoSourceValue::FixedStack: {
1113 int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1114 bool IsFixed = true;
1115 printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1116 break;
1117 }
1118 case PseudoSourceValue::GlobalValueCallEntry:
1119 OS << "call-entry ";
1120 cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1121 OS, /*PrintType=*/false, MST);
1122 break;
1123 case PseudoSourceValue::ExternalSymbolCallEntry:
1124 OS << "call-entry &";
1125 printLLVMNameWithoutPrefix(
1126 OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1127 break;
1128 case PseudoSourceValue::TargetCustom:
1129 // FIXME: This is not necessarily the correct MIR serialization format for
1130 // a custom pseudo source value, but at least it allows
1131 // -print-machineinstrs to work on a target with custom pseudo source
1132 // values.
1133 OS << "custom ";
1134 PVal->printCustom(OS);
1135 break;
1136 }
1137 }
1138 MachineOperand::printOperandOffset(OS, getOffset());
1139 if (getBaseAlignment() != getSize())
1140 OS << ", align " << getBaseAlignment();
1141 auto AAInfo = getAAInfo();
1142 if (AAInfo.TBAA) {
1143 OS << ", !tbaa ";
1144 AAInfo.TBAA->printAsOperand(OS, MST);
1145 }
1146 if (AAInfo.Scope) {
1147 OS << ", !alias.scope ";
1148 AAInfo.Scope->printAsOperand(OS, MST);
1149 }
1150 if (AAInfo.NoAlias) {
1151 OS << ", !noalias ";
1152 AAInfo.NoAlias->printAsOperand(OS, MST);
1153 }
1154 if (getRanges()) {
1155 OS << ", !range ";
1156 getRanges()->printAsOperand(OS, MST);
1157 }
1158 // FIXME: Implement addrspace printing/parsing in MIR.
1159 // For now, print this even though parsing it is not available in MIR.
1160 if (unsigned AS = getAddrSpace())
1161 OS << ", addrspace " << AS;
1162
1163 OS << ')';
1164}