Bug Summary

File:build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/lib/CodeGen/MachineVerifier.cpp
Warning:line 2518, column 9
Forming reference to null pointer

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name MachineVerifier.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm -resource-dir /usr/lib/llvm-16/lib/clang/16.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/CodeGen -I /build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/lib/CodeGen -I include -I /build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-16/lib/clang/16.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm=build-llvm -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm=build-llvm -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/build-llvm=build-llvm -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/= -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-10-03-140002-15933-1 -x c++ /build/llvm-toolchain-snapshot-16~++20221003111214+1fa2019828ca/llvm/lib/CodeGen/MachineVerifier.cpp
1//===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Pass to verify generated machine code. The following is checked:
10//
11// Operand counts: All explicit operands must be present.
12//
13// Register classes: All physical and virtual register operands must be
14// compatible with the register class required by the instruction descriptor.
15//
16// Register live intervals: Registers must be defined only once, and must be
17// defined before use.
18//
19// The machine code verifier is enabled with the command-line option
20// -verify-machineinstrs.
21//===----------------------------------------------------------------------===//
22
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/DenseMap.h"
25#include "llvm/ADT/DenseSet.h"
26#include "llvm/ADT/DepthFirstIterator.h"
27#include "llvm/ADT/PostOrderIterator.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/ADT/SetOperations.h"
30#include "llvm/ADT/SmallPtrSet.h"
31#include "llvm/ADT/SmallVector.h"
32#include "llvm/ADT/StringRef.h"
33#include "llvm/ADT/Twine.h"
34#include "llvm/Analysis/EHPersonalities.h"
35#include "llvm/CodeGen/CodeGenCommonISel.h"
36#include "llvm/CodeGen/LiveInterval.h"
37#include "llvm/CodeGen/LiveIntervals.h"
38#include "llvm/CodeGen/LiveRangeCalc.h"
39#include "llvm/CodeGen/LiveStacks.h"
40#include "llvm/CodeGen/LiveVariables.h"
41#include "llvm/CodeGen/MachineBasicBlock.h"
42#include "llvm/CodeGen/MachineFrameInfo.h"
43#include "llvm/CodeGen/MachineFunction.h"
44#include "llvm/CodeGen/MachineFunctionPass.h"
45#include "llvm/CodeGen/MachineInstr.h"
46#include "llvm/CodeGen/MachineInstrBundle.h"
47#include "llvm/CodeGen/MachineMemOperand.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/PseudoSourceValue.h"
51#include "llvm/CodeGen/RegisterBank.h"
52#include "llvm/CodeGen/RegisterBankInfo.h"
53#include "llvm/CodeGen/SlotIndexes.h"
54#include "llvm/CodeGen/StackMaps.h"
55#include "llvm/CodeGen/TargetInstrInfo.h"
56#include "llvm/CodeGen/TargetOpcodes.h"
57#include "llvm/CodeGen/TargetRegisterInfo.h"
58#include "llvm/CodeGen/TargetSubtargetInfo.h"
59#include "llvm/IR/BasicBlock.h"
60#include "llvm/IR/Constants.h"
61#include "llvm/IR/Function.h"
62#include "llvm/IR/InlineAsm.h"
63#include "llvm/IR/Instructions.h"
64#include "llvm/InitializePasses.h"
65#include "llvm/MC/LaneBitmask.h"
66#include "llvm/MC/MCAsmInfo.h"
67#include "llvm/MC/MCDwarf.h"
68#include "llvm/MC/MCInstrDesc.h"
69#include "llvm/MC/MCRegisterInfo.h"
70#include "llvm/MC/MCTargetOptions.h"
71#include "llvm/Pass.h"
72#include "llvm/Support/Casting.h"
73#include "llvm/Support/ErrorHandling.h"
74#include "llvm/Support/LowLevelTypeImpl.h"
75#include "llvm/Support/MathExtras.h"
76#include "llvm/Support/raw_ostream.h"
77#include "llvm/Target/TargetMachine.h"
78#include <algorithm>
79#include <cassert>
80#include <cstddef>
81#include <cstdint>
82#include <iterator>
83#include <string>
84#include <utility>
85
86using namespace llvm;
87
88namespace {
89
90 struct MachineVerifier {
91 MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
92
93 unsigned verify(const MachineFunction &MF);
94
95 Pass *const PASS;
96 const char *Banner;
97 const MachineFunction *MF;
98 const TargetMachine *TM;
99 const TargetInstrInfo *TII;
100 const TargetRegisterInfo *TRI;
101 const MachineRegisterInfo *MRI;
102 const RegisterBankInfo *RBI;
103
104 unsigned foundErrors;
105
106 // Avoid querying the MachineFunctionProperties for each operand.
107 bool isFunctionRegBankSelected;
108 bool isFunctionSelected;
109 bool isFunctionTracksDebugUserValues;
110
111 using RegVector = SmallVector<Register, 16>;
112 using RegMaskVector = SmallVector<const uint32_t *, 4>;
113 using RegSet = DenseSet<Register>;
114 using RegMap = DenseMap<Register, const MachineInstr *>;
115 using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
116
117 const MachineInstr *FirstNonPHI;
118 const MachineInstr *FirstTerminator;
119 BlockSet FunctionBlocks;
120
121 BitVector regsReserved;
122 RegSet regsLive;
123 RegVector regsDefined, regsDead, regsKilled;
124 RegMaskVector regMasks;
125
126 SlotIndex lastIndex;
127
128 // Add Reg and any sub-registers to RV
129 void addRegWithSubRegs(RegVector &RV, Register Reg) {
130 RV.push_back(Reg);
21
Value assigned to field 'LiveInts', which participates in a condition later
131 if (Reg.isPhysical())
22
Taking false branch
23
Taking false branch
132 append_range(RV, TRI->subregs(Reg.asMCReg()));
133 }
134
135 struct BBInfo {
136 // Is this MBB reachable from the MF entry point?
137 bool reachable = false;
138
139 // Vregs that must be live in because they are used without being
140 // defined. Map value is the user. vregsLiveIn doesn't include regs
141 // that only are used by PHI nodes.
142 RegMap vregsLiveIn;
143
144 // Regs killed in MBB. They may be defined again, and will then be in both
145 // regsKilled and regsLiveOut.
146 RegSet regsKilled;
147
148 // Regs defined in MBB and live out. Note that vregs passing through may
149 // be live out without being mentioned here.
150 RegSet regsLiveOut;
151
152 // Vregs that pass through MBB untouched. This set is disjoint from
153 // regsKilled and regsLiveOut.
154 RegSet vregsPassed;
155
156 // Vregs that must pass through MBB because they are needed by a successor
157 // block. This set is disjoint from regsLiveOut.
158 RegSet vregsRequired;
159
160 // Set versions of block's predecessor and successor lists.
161 BlockSet Preds, Succs;
162
163 BBInfo() = default;
164
165 // Add register to vregsRequired if it belongs there. Return true if
166 // anything changed.
167 bool addRequired(Register Reg) {
168 if (!Reg.isVirtual())
169 return false;
170 if (regsLiveOut.count(Reg))
171 return false;
172 return vregsRequired.insert(Reg).second;
173 }
174
175 // Same for a full set.
176 bool addRequired(const RegSet &RS) {
177 bool Changed = false;
178 for (Register Reg : RS)
179 Changed |= addRequired(Reg);
180 return Changed;
181 }
182
183 // Same for a full map.
184 bool addRequired(const RegMap &RM) {
185 bool Changed = false;
186 for (const auto &I : RM)
187 Changed |= addRequired(I.first);
188 return Changed;
189 }
190
191 // Live-out registers are either in regsLiveOut or vregsPassed.
192 bool isLiveOut(Register Reg) const {
193 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
194 }
195 };
196
197 // Extra register info per MBB.
198 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
199
200 bool isReserved(Register Reg) {
201 return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
202 }
203
204 bool isAllocatable(Register Reg) const {
205 return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
206 !regsReserved.test(Reg.id());
207 }
208
209 // Analysis information if available
210 LiveVariables *LiveVars;
211 LiveIntervals *LiveInts;
212 LiveStacks *LiveStks;
213 SlotIndexes *Indexes;
214
215 void visitMachineFunctionBefore();
216 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
217 void visitMachineBundleBefore(const MachineInstr *MI);
218
219 /// Verify that all of \p MI's virtual register operands are scalars.
220 /// \returns True if all virtual register operands are scalar. False
221 /// otherwise.
222 bool verifyAllRegOpsScalar(const MachineInstr &MI,
223 const MachineRegisterInfo &MRI);
224 bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
225 void verifyPreISelGenericInstruction(const MachineInstr *MI);
226 void visitMachineInstrBefore(const MachineInstr *MI);
227 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
228 void visitMachineBundleAfter(const MachineInstr *MI);
229 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
230 void visitMachineFunctionAfter();
231
232 void report(const char *msg, const MachineFunction *MF);
233 void report(const char *msg, const MachineBasicBlock *MBB);
234 void report(const char *msg, const MachineInstr *MI);
235 void report(const char *msg, const MachineOperand *MO, unsigned MONum,
236 LLT MOVRegType = LLT{});
237 void report(const Twine &Msg, const MachineInstr *MI);
238
239 void report_context(const LiveInterval &LI) const;
240 void report_context(const LiveRange &LR, Register VRegUnit,
241 LaneBitmask LaneMask) const;
242 void report_context(const LiveRange::Segment &S) const;
243 void report_context(const VNInfo &VNI) const;
244 void report_context(SlotIndex Pos) const;
245 void report_context(MCPhysReg PhysReg) const;
246 void report_context_liverange(const LiveRange &LR) const;
247 void report_context_lanemask(LaneBitmask LaneMask) const;
248 void report_context_vreg(Register VReg) const;
249 void report_context_vreg_regunit(Register VRegOrUnit) const;
250
251 void verifyInlineAsm(const MachineInstr *MI);
252
253 void checkLiveness(const MachineOperand *MO, unsigned MONum);
254 void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
255 SlotIndex UseIdx, const LiveRange &LR,
256 Register VRegOrUnit,
257 LaneBitmask LaneMask = LaneBitmask::getNone());
258 void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
259 SlotIndex DefIdx, const LiveRange &LR,
260 Register VRegOrUnit, bool SubRangeCheck = false,
261 LaneBitmask LaneMask = LaneBitmask::getNone());
262
263 void markReachable(const MachineBasicBlock *MBB);
264 void calcRegsPassed();
265 void checkPHIOps(const MachineBasicBlock &MBB);
266
267 void calcRegsRequired();
268 void verifyLiveVariables();
269 void verifyLiveIntervals();
270 void verifyLiveInterval(const LiveInterval&);
271 void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
272 LaneBitmask);
273 void verifyLiveRangeSegment(const LiveRange &,
274 const LiveRange::const_iterator I, Register,
275 LaneBitmask);
276 void verifyLiveRange(const LiveRange &, Register,
277 LaneBitmask LaneMask = LaneBitmask::getNone());
278
279 void verifyStackFrame();
280
281 void verifySlotIndexes() const;
282 void verifyProperties(const MachineFunction &MF);
283 };
284
285 struct MachineVerifierPass : public MachineFunctionPass {
286 static char ID; // Pass ID, replacement for typeid
287
288 const std::string Banner;
289
290 MachineVerifierPass(std::string banner = std::string())
291 : MachineFunctionPass(ID), Banner(std::move(banner)) {
292 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
293 }
294
295 void getAnalysisUsage(AnalysisUsage &AU) const override {
296 AU.addUsedIfAvailable<LiveStacks>();
297 AU.setPreservesAll();
298 MachineFunctionPass::getAnalysisUsage(AU);
299 }
300
301 bool runOnMachineFunction(MachineFunction &MF) override {
302 // Skip functions that have known verification problems.
303 // FIXME: Remove this mechanism when all problematic passes have been
304 // fixed.
305 if (MF.getProperties().hasProperty(
306 MachineFunctionProperties::Property::FailsVerification))
307 return false;
308
309 unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
310 if (FoundErrors)
311 report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
312 return false;
313 }
314 };
315
316} // end anonymous namespace
317
318char MachineVerifierPass::ID = 0;
319
320INITIALIZE_PASS(MachineVerifierPass, "machineverifier",static void *initializeMachineVerifierPassPassOnce(PassRegistry
&Registry) { PassInfo *PI = new PassInfo( "Verify generated machine code"
, "machineverifier", &MachineVerifierPass::ID, PassInfo::
NormalCtor_t(callDefaultCtor<MachineVerifierPass>), false
, false); Registry.registerPass(*PI, true); return PI; } static
llvm::once_flag InitializeMachineVerifierPassPassFlag; void llvm
::initializeMachineVerifierPassPass(PassRegistry &Registry
) { llvm::call_once(InitializeMachineVerifierPassPassFlag, initializeMachineVerifierPassPassOnce
, std::ref(Registry)); }
321 "Verify generated machine code", false, false)static void *initializeMachineVerifierPassPassOnce(PassRegistry
&Registry) { PassInfo *PI = new PassInfo( "Verify generated machine code"
, "machineverifier", &MachineVerifierPass::ID, PassInfo::
NormalCtor_t(callDefaultCtor<MachineVerifierPass>), false
, false); Registry.registerPass(*PI, true); return PI; } static
llvm::once_flag InitializeMachineVerifierPassPassFlag; void llvm
::initializeMachineVerifierPassPass(PassRegistry &Registry
) { llvm::call_once(InitializeMachineVerifierPassPassFlag, initializeMachineVerifierPassPassOnce
, std::ref(Registry)); }
322
323FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
324 return new MachineVerifierPass(Banner);
325}
326
327void llvm::verifyMachineFunction(MachineFunctionAnalysisManager *,
328 const std::string &Banner,
329 const MachineFunction &MF) {
330 // TODO: Use MFAM after porting below analyses.
331 // LiveVariables *LiveVars;
332 // LiveIntervals *LiveInts;
333 // LiveStacks *LiveStks;
334 // SlotIndexes *Indexes;
335 unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
336 if (FoundErrors)
337 report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
338}
339
340bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
341 const {
342 MachineFunction &MF = const_cast<MachineFunction&>(*this);
343 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
344 if (AbortOnErrors && FoundErrors)
345 report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
346 return FoundErrors == 0;
347}
348
349void MachineVerifier::verifySlotIndexes() const {
350 if (Indexes == nullptr)
351 return;
352
353 // Ensure the IdxMBB list is sorted by slot indexes.
354 SlotIndex Last;
355 for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
356 E = Indexes->MBBIndexEnd(); I != E; ++I) {
357 assert(!Last.isValid() || I->first > Last)(static_cast <bool> (!Last.isValid() || I->first >
Last) ? void (0) : __assert_fail ("!Last.isValid() || I->first > Last"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 357, __extension__ __PRETTY_FUNCTION__
))
;
358 Last = I->first;
359 }
360}
361
362void MachineVerifier::verifyProperties(const MachineFunction &MF) {
363 // If a pass has introduced virtual registers without clearing the
364 // NoVRegs property (or set it without allocating the vregs)
365 // then report an error.
366 if (MF.getProperties().hasProperty(
367 MachineFunctionProperties::Property::NoVRegs) &&
368 MRI->getNumVirtRegs())
369 report("Function has NoVRegs property but there are VReg operands", &MF);
370}
371
372unsigned MachineVerifier::verify(const MachineFunction &MF) {
373 foundErrors = 0;
374
375 this->MF = &MF;
376 TM = &MF.getTarget();
377 TII = MF.getSubtarget().getInstrInfo();
378 TRI = MF.getSubtarget().getRegisterInfo();
379 RBI = MF.getSubtarget().getRegBankInfo();
380 MRI = &MF.getRegInfo();
381
382 const bool isFunctionFailedISel = MF.getProperties().hasProperty(
383 MachineFunctionProperties::Property::FailedISel);
384
385 // If we're mid-GlobalISel and we already triggered the fallback path then
386 // it's expected that the MIR is somewhat broken but that's ok since we'll
387 // reset it and clear the FailedISel attribute in ResetMachineFunctions.
388 if (isFunctionFailedISel)
389 return foundErrors;
390
391 isFunctionRegBankSelected = MF.getProperties().hasProperty(
392 MachineFunctionProperties::Property::RegBankSelected);
393 isFunctionSelected = MF.getProperties().hasProperty(
394 MachineFunctionProperties::Property::Selected);
395 isFunctionTracksDebugUserValues = MF.getProperties().hasProperty(
396 MachineFunctionProperties::Property::TracksDebugUserValues);
397
398 LiveVars = nullptr;
399 LiveInts = nullptr;
400 LiveStks = nullptr;
401 Indexes = nullptr;
402 if (PASS) {
403 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
404 // We don't want to verify LiveVariables if LiveIntervals is available.
405 if (!LiveInts)
406 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
407 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
408 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
409 }
410
411 verifySlotIndexes();
412
413 verifyProperties(MF);
414
415 visitMachineFunctionBefore();
416 for (const MachineBasicBlock &MBB : MF) {
417 visitMachineBasicBlockBefore(&MBB);
418 // Keep track of the current bundle header.
419 const MachineInstr *CurBundle = nullptr;
420 // Do we expect the next instruction to be part of the same bundle?
421 bool InBundle = false;
422
423 for (const MachineInstr &MI : MBB.instrs()) {
424 if (MI.getParent() != &MBB) {
425 report("Bad instruction parent pointer", &MBB);
426 errs() << "Instruction: " << MI;
427 continue;
428 }
429
430 // Check for consistent bundle flags.
431 if (InBundle && !MI.isBundledWithPred())
432 report("Missing BundledPred flag, "
433 "BundledSucc was set on predecessor",
434 &MI);
435 if (!InBundle && MI.isBundledWithPred())
436 report("BundledPred flag is set, "
437 "but BundledSucc not set on predecessor",
438 &MI);
439
440 // Is this a bundle header?
441 if (!MI.isInsideBundle()) {
442 if (CurBundle)
443 visitMachineBundleAfter(CurBundle);
444 CurBundle = &MI;
445 visitMachineBundleBefore(CurBundle);
446 } else if (!CurBundle)
447 report("No bundle header", &MI);
448 visitMachineInstrBefore(&MI);
449 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
450 const MachineOperand &Op = MI.getOperand(I);
451 if (Op.getParent() != &MI) {
452 // Make sure to use correct addOperand / removeOperand / ChangeTo
453 // functions when replacing operands of a MachineInstr.
454 report("Instruction has operand with wrong parent set", &MI);
455 }
456
457 visitMachineOperand(&Op, I);
458 }
459
460 // Was this the last bundled instruction?
461 InBundle = MI.isBundledWithSucc();
462 }
463 if (CurBundle)
464 visitMachineBundleAfter(CurBundle);
465 if (InBundle)
466 report("BundledSucc flag set on last instruction in block", &MBB.back());
467 visitMachineBasicBlockAfter(&MBB);
468 }
469 visitMachineFunctionAfter();
470
471 // Clean up.
472 regsLive.clear();
473 regsDefined.clear();
474 regsDead.clear();
475 regsKilled.clear();
476 regMasks.clear();
477 MBBInfoMap.clear();
478
479 return foundErrors;
480}
481
482void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
483 assert(MF)(static_cast <bool> (MF) ? void (0) : __assert_fail ("MF"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 483, __extension__ __PRETTY_FUNCTION__
))
;
484 errs() << '\n';
485 if (!foundErrors++) {
486 if (Banner)
487 errs() << "# " << Banner << '\n';
488 if (LiveInts != nullptr)
489 LiveInts->print(errs());
490 else
491 MF->print(errs(), Indexes);
492 }
493 errs() << "*** Bad machine code: " << msg << " ***\n"
494 << "- function: " << MF->getName() << "\n";
495}
496
497void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
498 assert(MBB)(static_cast <bool> (MBB) ? void (0) : __assert_fail ("MBB"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 498, __extension__ __PRETTY_FUNCTION__
))
;
499 report(msg, MBB->getParent());
500 errs() << "- basic block: " << printMBBReference(*MBB) << ' '
501 << MBB->getName() << " (" << (const void *)MBB << ')';
502 if (Indexes)
503 errs() << " [" << Indexes->getMBBStartIdx(MBB)
504 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
505 errs() << '\n';
506}
507
508void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
509 assert(MI)(static_cast <bool> (MI) ? void (0) : __assert_fail ("MI"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 509, __extension__ __PRETTY_FUNCTION__
))
;
510 report(msg, MI->getParent());
511 errs() << "- instruction: ";
512 if (Indexes && Indexes->hasIndex(*MI))
513 errs() << Indexes->getInstructionIndex(*MI) << '\t';
514 MI->print(errs(), /*IsStandalone=*/true);
515}
516
517void MachineVerifier::report(const char *msg, const MachineOperand *MO,
518 unsigned MONum, LLT MOVRegType) {
519 assert(MO)(static_cast <bool> (MO) ? void (0) : __assert_fail ("MO"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 519, __extension__ __PRETTY_FUNCTION__
))
;
520 report(msg, MO->getParent());
521 errs() << "- operand " << MONum << ": ";
522 MO->print(errs(), MOVRegType, TRI);
523 errs() << "\n";
524}
525
526void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
527 report(Msg.str().c_str(), MI);
528}
529
530void MachineVerifier::report_context(SlotIndex Pos) const {
531 errs() << "- at: " << Pos << '\n';
532}
533
534void MachineVerifier::report_context(const LiveInterval &LI) const {
535 errs() << "- interval: " << LI << '\n';
536}
537
538void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
539 LaneBitmask LaneMask) const {
540 report_context_liverange(LR);
541 report_context_vreg_regunit(VRegUnit);
542 if (LaneMask.any())
543 report_context_lanemask(LaneMask);
544}
545
546void MachineVerifier::report_context(const LiveRange::Segment &S) const {
547 errs() << "- segment: " << S << '\n';
548}
549
550void MachineVerifier::report_context(const VNInfo &VNI) const {
551 errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
552}
553
554void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
555 errs() << "- liverange: " << LR << '\n';
556}
557
558void MachineVerifier::report_context(MCPhysReg PReg) const {
559 errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
560}
561
562void MachineVerifier::report_context_vreg(Register VReg) const {
563 errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
564}
565
566void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
567 if (Register::isVirtualRegister(VRegOrUnit)) {
568 report_context_vreg(VRegOrUnit);
569 } else {
570 errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
571 }
572}
573
574void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
575 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
576}
577
578void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
579 BBInfo &MInfo = MBBInfoMap[MBB];
580 if (!MInfo.reachable) {
581 MInfo.reachable = true;
582 for (const MachineBasicBlock *Succ : MBB->successors())
583 markReachable(Succ);
584 }
585}
586
587void MachineVerifier::visitMachineFunctionBefore() {
588 lastIndex = SlotIndex();
589 regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
590 : TRI->getReservedRegs(*MF);
591
592 if (!MF->empty())
593 markReachable(&MF->front());
594
595 // Build a set of the basic blocks in the function.
596 FunctionBlocks.clear();
597 for (const auto &MBB : *MF) {
598 FunctionBlocks.insert(&MBB);
599 BBInfo &MInfo = MBBInfoMap[&MBB];
600
601 MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
602 if (MInfo.Preds.size() != MBB.pred_size())
603 report("MBB has duplicate entries in its predecessor list.", &MBB);
604
605 MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
606 if (MInfo.Succs.size() != MBB.succ_size())
607 report("MBB has duplicate entries in its successor list.", &MBB);
608 }
609
610 // Check that the register use lists are sane.
611 MRI->verifyUseLists();
612
613 if (!MF->empty())
614 verifyStackFrame();
615}
616
617void
618MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
619 FirstTerminator = nullptr;
620 FirstNonPHI = nullptr;
621
622 if (!MF->getProperties().hasProperty(
623 MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
624 // If this block has allocatable physical registers live-in, check that
625 // it is an entry block or landing pad.
626 for (const auto &LI : MBB->liveins()) {
627 if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
628 MBB->getIterator() != MBB->getParent()->begin()) {
629 report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
630 report_context(LI.PhysReg);
631 }
632 }
633 }
634
635 if (MBB->isIRBlockAddressTaken()) {
636 if (!MBB->getAddressTakenIRBlock()->hasAddressTaken())
637 report("ir-block-address-taken is associated with basic block not used by "
638 "a blockaddress.",
639 MBB);
640 }
641
642 // Count the number of landing pad successors.
643 SmallPtrSet<const MachineBasicBlock*, 4> LandingPadSuccs;
644 for (const auto *succ : MBB->successors()) {
645 if (succ->isEHPad())
646 LandingPadSuccs.insert(succ);
647 if (!FunctionBlocks.count(succ))
648 report("MBB has successor that isn't part of the function.", MBB);
649 if (!MBBInfoMap[succ].Preds.count(MBB)) {
650 report("Inconsistent CFG", MBB);
651 errs() << "MBB is not in the predecessor list of the successor "
652 << printMBBReference(*succ) << ".\n";
653 }
654 }
655
656 // Check the predecessor list.
657 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
658 if (!FunctionBlocks.count(Pred))
659 report("MBB has predecessor that isn't part of the function.", MBB);
660 if (!MBBInfoMap[Pred].Succs.count(MBB)) {
661 report("Inconsistent CFG", MBB);
662 errs() << "MBB is not in the successor list of the predecessor "
663 << printMBBReference(*Pred) << ".\n";
664 }
665 }
666
667 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
668 const BasicBlock *BB = MBB->getBasicBlock();
669 const Function &F = MF->getFunction();
670 if (LandingPadSuccs.size() > 1 &&
671 !(AsmInfo &&
672 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
673 BB && isa<SwitchInst>(BB->getTerminator())) &&
674 !isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
675 report("MBB has more than one landing pad successor", MBB);
676
677 // Call analyzeBranch. If it succeeds, there several more conditions to check.
678 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
679 SmallVector<MachineOperand, 4> Cond;
680 if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
681 Cond)) {
682 // Ok, analyzeBranch thinks it knows what's going on with this block. Let's
683 // check whether its answers match up with reality.
684 if (!TBB && !FBB) {
685 // Block falls through to its successor.
686 if (!MBB->empty() && MBB->back().isBarrier() &&
687 !TII->isPredicated(MBB->back())) {
688 report("MBB exits via unconditional fall-through but ends with a "
689 "barrier instruction!", MBB);
690 }
691 if (!Cond.empty()) {
692 report("MBB exits via unconditional fall-through but has a condition!",
693 MBB);
694 }
695 } else if (TBB && !FBB && Cond.empty()) {
696 // Block unconditionally branches somewhere.
697 if (MBB->empty()) {
698 report("MBB exits via unconditional branch but doesn't contain "
699 "any instructions!", MBB);
700 } else if (!MBB->back().isBarrier()) {
701 report("MBB exits via unconditional branch but doesn't end with a "
702 "barrier instruction!", MBB);
703 } else if (!MBB->back().isTerminator()) {
704 report("MBB exits via unconditional branch but the branch isn't a "
705 "terminator instruction!", MBB);
706 }
707 } else if (TBB && !FBB && !Cond.empty()) {
708 // Block conditionally branches somewhere, otherwise falls through.
709 if (MBB->empty()) {
710 report("MBB exits via conditional branch/fall-through but doesn't "
711 "contain any instructions!", MBB);
712 } else if (MBB->back().isBarrier()) {
713 report("MBB exits via conditional branch/fall-through but ends with a "
714 "barrier instruction!", MBB);
715 } else if (!MBB->back().isTerminator()) {
716 report("MBB exits via conditional branch/fall-through but the branch "
717 "isn't a terminator instruction!", MBB);
718 }
719 } else if (TBB && FBB) {
720 // Block conditionally branches somewhere, otherwise branches
721 // somewhere else.
722 if (MBB->empty()) {
723 report("MBB exits via conditional branch/branch but doesn't "
724 "contain any instructions!", MBB);
725 } else if (!MBB->back().isBarrier()) {
726 report("MBB exits via conditional branch/branch but doesn't end with a "
727 "barrier instruction!", MBB);
728 } else if (!MBB->back().isTerminator()) {
729 report("MBB exits via conditional branch/branch but the branch "
730 "isn't a terminator instruction!", MBB);
731 }
732 if (Cond.empty()) {
733 report("MBB exits via conditional branch/branch but there's no "
734 "condition!", MBB);
735 }
736 } else {
737 report("analyzeBranch returned invalid data!", MBB);
738 }
739
740 // Now check that the successors match up with the answers reported by
741 // analyzeBranch.
742 if (TBB && !MBB->isSuccessor(TBB))
743 report("MBB exits via jump or conditional branch, but its target isn't a "
744 "CFG successor!",
745 MBB);
746 if (FBB && !MBB->isSuccessor(FBB))
747 report("MBB exits via conditional branch, but its target isn't a CFG "
748 "successor!",
749 MBB);
750
751 // There might be a fallthrough to the next block if there's either no
752 // unconditional true branch, or if there's a condition, and one of the
753 // branches is missing.
754 bool Fallthrough = !TBB || (!Cond.empty() && !FBB);
755
756 // A conditional fallthrough must be an actual CFG successor, not
757 // unreachable. (Conversely, an unconditional fallthrough might not really
758 // be a successor, because the block might end in unreachable.)
759 if (!Cond.empty() && !FBB) {
760 MachineFunction::const_iterator MBBI = std::next(MBB->getIterator());
761 if (MBBI == MF->end()) {
762 report("MBB conditionally falls through out of function!", MBB);
763 } else if (!MBB->isSuccessor(&*MBBI))
764 report("MBB exits via conditional branch/fall-through but the CFG "
765 "successors don't match the actual successors!",
766 MBB);
767 }
768
769 // Verify that there aren't any extra un-accounted-for successors.
770 for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
771 // If this successor is one of the branch targets, it's okay.
772 if (SuccMBB == TBB || SuccMBB == FBB)
773 continue;
774 // If we might have a fallthrough, and the successor is the fallthrough
775 // block, that's also ok.
776 if (Fallthrough && SuccMBB == MBB->getNextNode())
777 continue;
778 // Also accept successors which are for exception-handling or might be
779 // inlineasm_br targets.
780 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
781 continue;
782 report("MBB has unexpected successors which are not branch targets, "
783 "fallthrough, EHPads, or inlineasm_br targets.",
784 MBB);
785 }
786 }
787
788 regsLive.clear();
789 if (MRI->tracksLiveness()) {
790 for (const auto &LI : MBB->liveins()) {
791 if (!Register::isPhysicalRegister(LI.PhysReg)) {
792 report("MBB live-in list contains non-physical register", MBB);
793 continue;
794 }
795 for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
796 regsLive.insert(SubReg);
797 }
798 }
799
800 const MachineFrameInfo &MFI = MF->getFrameInfo();
801 BitVector PR = MFI.getPristineRegs(*MF);
802 for (unsigned I : PR.set_bits()) {
803 for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
804 regsLive.insert(SubReg);
805 }
806
807 regsKilled.clear();
808 regsDefined.clear();
809
810 if (Indexes)
811 lastIndex = Indexes->getMBBStartIdx(MBB);
812}
813
814// This function gets called for all bundle headers, including normal
815// stand-alone unbundled instructions.
816void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
817 if (Indexes && Indexes->hasIndex(*MI)) {
818 SlotIndex idx = Indexes->getInstructionIndex(*MI);
819 if (!(idx > lastIndex)) {
820 report("Instruction index out of order", MI);
821 errs() << "Last instruction was at " << lastIndex << '\n';
822 }
823 lastIndex = idx;
824 }
825
826 // Ensure non-terminators don't follow terminators.
827 if (MI->isTerminator()) {
828 if (!FirstTerminator)
829 FirstTerminator = MI;
830 } else if (FirstTerminator) {
831 report("Non-terminator instruction after the first terminator", MI);
832 errs() << "First terminator was:\t" << *FirstTerminator;
833 }
834}
835
836// The operands on an INLINEASM instruction must follow a template.
837// Verify that the flag operands make sense.
838void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
839 // The first two operands on INLINEASM are the asm string and global flags.
840 if (MI->getNumOperands() < 2) {
841 report("Too few operands on inline asm", MI);
842 return;
843 }
844 if (!MI->getOperand(0).isSymbol())
845 report("Asm string must be an external symbol", MI);
846 if (!MI->getOperand(1).isImm())
847 report("Asm flags must be an immediate", MI);
848 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
849 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
850 // and Extra_IsConvergent = 32.
851 if (!isUInt<6>(MI->getOperand(1).getImm()))
852 report("Unknown asm flags", &MI->getOperand(1), 1);
853
854 static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
855
856 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
857 unsigned NumOps;
858 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
859 const MachineOperand &MO = MI->getOperand(OpNo);
860 // There may be implicit ops after the fixed operands.
861 if (!MO.isImm())
862 break;
863 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
864 }
865
866 if (OpNo > MI->getNumOperands())
867 report("Missing operands in last group", MI);
868
869 // An optional MDNode follows the groups.
870 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
871 ++OpNo;
872
873 // All trailing operands must be implicit registers.
874 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
875 const MachineOperand &MO = MI->getOperand(OpNo);
876 if (!MO.isReg() || !MO.isImplicit())
877 report("Expected implicit register after groups", &MO, OpNo);
878 }
879
880 if (MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
881 const MachineBasicBlock *MBB = MI->getParent();
882
883 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
884 i != e; ++i) {
885 const MachineOperand &MO = MI->getOperand(i);
886
887 if (!MO.isMBB())
888 continue;
889
890 // Check the successor & predecessor lists look ok, assume they are
891 // not. Find the indirect target without going through the successors.
892 const MachineBasicBlock *IndirectTargetMBB = MO.getMBB();
893 if (!IndirectTargetMBB) {
894 report("INLINEASM_BR indirect target does not exist", &MO, i);
895 break;
896 }
897
898 if (!MBB->isSuccessor(IndirectTargetMBB))
899 report("INLINEASM_BR indirect target missing from successor list", &MO,
900 i);
901
902 if (!IndirectTargetMBB->isPredecessor(MBB))
903 report("INLINEASM_BR indirect target predecessor list missing parent",
904 &MO, i);
905 }
906 }
907}
908
909bool MachineVerifier::verifyAllRegOpsScalar(const MachineInstr &MI,
910 const MachineRegisterInfo &MRI) {
911 if (none_of(MI.explicit_operands(), [&MRI](const MachineOperand &Op) {
912 if (!Op.isReg())
913 return false;
914 const auto Reg = Op.getReg();
915 if (Reg.isPhysical())
916 return false;
917 return !MRI.getType(Reg).isScalar();
918 }))
919 return true;
920 report("All register operands must have scalar types", &MI);
921 return false;
922}
923
924/// Check that types are consistent when two operands need to have the same
925/// number of vector elements.
926/// \return true if the types are valid.
927bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
928 const MachineInstr *MI) {
929 if (Ty0.isVector() != Ty1.isVector()) {
930 report("operand types must be all-vector or all-scalar", MI);
931 // Generally we try to report as many issues as possible at once, but in
932 // this case it's not clear what should we be comparing the size of the
933 // scalar with: the size of the whole vector or its lane. Instead of
934 // making an arbitrary choice and emitting not so helpful message, let's
935 // avoid the extra noise and stop here.
936 return false;
937 }
938
939 if (Ty0.isVector() && Ty0.getNumElements() != Ty1.getNumElements()) {
940 report("operand types must preserve number of vector elements", MI);
941 return false;
942 }
943
944 return true;
945}
946
947void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
948 if (isFunctionSelected)
949 report("Unexpected generic instruction in a Selected function", MI);
950
951 const MCInstrDesc &MCID = MI->getDesc();
952 unsigned NumOps = MI->getNumOperands();
953
954 // Branches must reference a basic block if they are not indirect
955 if (MI->isBranch() && !MI->isIndirectBranch()) {
956 bool HasMBB = false;
957 for (const MachineOperand &Op : MI->operands()) {
958 if (Op.isMBB()) {
959 HasMBB = true;
960 break;
961 }
962 }
963
964 if (!HasMBB) {
965 report("Branch instruction is missing a basic block operand or "
966 "isIndirectBranch property",
967 MI);
968 }
969 }
970
971 // Check types.
972 SmallVector<LLT, 4> Types;
973 for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
974 I != E; ++I) {
975 if (!MCID.OpInfo[I].isGenericType())
976 continue;
977 // Generic instructions specify type equality constraints between some of
978 // their operands. Make sure these are consistent.
979 size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
980 Types.resize(std::max(TypeIdx + 1, Types.size()));
981
982 const MachineOperand *MO = &MI->getOperand(I);
983 if (!MO->isReg()) {
984 report("generic instruction must use register operands", MI);
985 continue;
986 }
987
988 LLT OpTy = MRI->getType(MO->getReg());
989 // Don't report a type mismatch if there is no actual mismatch, only a
990 // type missing, to reduce noise:
991 if (OpTy.isValid()) {
992 // Only the first valid type for a type index will be printed: don't
993 // overwrite it later so it's always clear which type was expected:
994 if (!Types[TypeIdx].isValid())
995 Types[TypeIdx] = OpTy;
996 else if (Types[TypeIdx] != OpTy)
997 report("Type mismatch in generic instruction", MO, I, OpTy);
998 } else {
999 // Generic instructions must have types attached to their operands.
1000 report("Generic instruction is missing a virtual register type", MO, I);
1001 }
1002 }
1003
1004 // Generic opcodes must not have physical register operands.
1005 for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
1006 const MachineOperand *MO = &MI->getOperand(I);
1007 if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
1008 report("Generic instruction cannot have physical register", MO, I);
1009 }
1010
1011 // Avoid out of bounds in checks below. This was already reported earlier.
1012 if (MI->getNumOperands() < MCID.getNumOperands())
1013 return;
1014
1015 StringRef ErrorInfo;
1016 if (!TII->verifyInstruction(*MI, ErrorInfo))
1017 report(ErrorInfo.data(), MI);
1018
1019 // Verify properties of various specific instruction types
1020 unsigned Opc = MI->getOpcode();
1021 switch (Opc) {
1022 case TargetOpcode::G_ASSERT_SEXT:
1023 case TargetOpcode::G_ASSERT_ZEXT: {
1024 std::string OpcName =
1025 Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
1026 if (!MI->getOperand(2).isImm()) {
1027 report(Twine(OpcName, " expects an immediate operand #2"), MI);
1028 break;
1029 }
1030
1031 Register Dst = MI->getOperand(0).getReg();
1032 Register Src = MI->getOperand(1).getReg();
1033 LLT SrcTy = MRI->getType(Src);
1034 int64_t Imm = MI->getOperand(2).getImm();
1035 if (Imm <= 0) {
1036 report(Twine(OpcName, " size must be >= 1"), MI);
1037 break;
1038 }
1039
1040 if (Imm >= SrcTy.getScalarSizeInBits()) {
1041 report(Twine(OpcName, " size must be less than source bit width"), MI);
1042 break;
1043 }
1044
1045 const RegisterBank *SrcRB = RBI->getRegBank(Src, *MRI, *TRI);
1046 const RegisterBank *DstRB = RBI->getRegBank(Dst, *MRI, *TRI);
1047
1048 // Allow only the source bank to be set.
1049 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1050 report(Twine(OpcName, " cannot change register bank"), MI);
1051 break;
1052 }
1053
1054 // Don't allow a class change. Do allow member class->regbank.
1055 const TargetRegisterClass *DstRC = MRI->getRegClassOrNull(Dst);
1056 if (DstRC && DstRC != MRI->getRegClassOrNull(Src)) {
1057 report(
1058 Twine(OpcName, " source and destination register classes must match"),
1059 MI);
1060 break;
1061 }
1062
1063 break;
1064 }
1065
1066 case TargetOpcode::G_CONSTANT:
1067 case TargetOpcode::G_FCONSTANT: {
1068 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1069 if (DstTy.isVector())
1070 report("Instruction cannot use a vector result type", MI);
1071
1072 if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1073 if (!MI->getOperand(1).isCImm()) {
1074 report("G_CONSTANT operand must be cimm", MI);
1075 break;
1076 }
1077
1078 const ConstantInt *CI = MI->getOperand(1).getCImm();
1079 if (CI->getBitWidth() != DstTy.getSizeInBits())
1080 report("inconsistent constant size", MI);
1081 } else {
1082 if (!MI->getOperand(1).isFPImm()) {
1083 report("G_FCONSTANT operand must be fpimm", MI);
1084 break;
1085 }
1086 const ConstantFP *CF = MI->getOperand(1).getFPImm();
1087
1088 if (APFloat::getSizeInBits(CF->getValueAPF().getSemantics()) !=
1089 DstTy.getSizeInBits()) {
1090 report("inconsistent constant size", MI);
1091 }
1092 }
1093
1094 break;
1095 }
1096 case TargetOpcode::G_LOAD:
1097 case TargetOpcode::G_STORE:
1098 case TargetOpcode::G_ZEXTLOAD:
1099 case TargetOpcode::G_SEXTLOAD: {
1100 LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1101 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1102 if (!PtrTy.isPointer())
1103 report("Generic memory instruction must access a pointer", MI);
1104
1105 // Generic loads and stores must have a single MachineMemOperand
1106 // describing that access.
1107 if (!MI->hasOneMemOperand()) {
1108 report("Generic instruction accessing memory must have one mem operand",
1109 MI);
1110 } else {
1111 const MachineMemOperand &MMO = **MI->memoperands_begin();
1112 if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1113 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1114 if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
1115 report("Generic extload must have a narrower memory type", MI);
1116 } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1117 if (MMO.getSize() > ValTy.getSizeInBytes())
1118 report("load memory size cannot exceed result size", MI);
1119 } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1120 if (ValTy.getSizeInBytes() < MMO.getSize())
1121 report("store memory size cannot exceed value size", MI);
1122 }
1123
1124 const AtomicOrdering Order = MMO.getSuccessOrdering();
1125 if (Opc == TargetOpcode::G_STORE) {
1126 if (Order == AtomicOrdering::Acquire ||
1127 Order == AtomicOrdering::AcquireRelease)
1128 report("atomic store cannot use acquire ordering", MI);
1129
1130 } else {
1131 if (Order == AtomicOrdering::Release ||
1132 Order == AtomicOrdering::AcquireRelease)
1133 report("atomic load cannot use release ordering", MI);
1134 }
1135 }
1136
1137 break;
1138 }
1139 case TargetOpcode::G_PHI: {
1140 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1141 if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()),
1142 [this, &DstTy](const MachineOperand &MO) {
1143 if (!MO.isReg())
1144 return true;
1145 LLT Ty = MRI->getType(MO.getReg());
1146 if (!Ty.isValid() || (Ty != DstTy))
1147 return false;
1148 return true;
1149 }))
1150 report("Generic Instruction G_PHI has operands with incompatible/missing "
1151 "types",
1152 MI);
1153 break;
1154 }
1155 case TargetOpcode::G_BITCAST: {
1156 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1157 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1158 if (!DstTy.isValid() || !SrcTy.isValid())
1159 break;
1160
1161 if (SrcTy.isPointer() != DstTy.isPointer())
1162 report("bitcast cannot convert between pointers and other types", MI);
1163
1164 if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1165 report("bitcast sizes must match", MI);
1166
1167 if (SrcTy == DstTy)
1168 report("bitcast must change the type", MI);
1169
1170 break;
1171 }
1172 case TargetOpcode::G_INTTOPTR:
1173 case TargetOpcode::G_PTRTOINT:
1174 case TargetOpcode::G_ADDRSPACE_CAST: {
1175 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1176 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1177 if (!DstTy.isValid() || !SrcTy.isValid())
1178 break;
1179
1180 verifyVectorElementMatch(DstTy, SrcTy, MI);
1181
1182 DstTy = DstTy.getScalarType();
1183 SrcTy = SrcTy.getScalarType();
1184
1185 if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1186 if (!DstTy.isPointer())
1187 report("inttoptr result type must be a pointer", MI);
1188 if (SrcTy.isPointer())
1189 report("inttoptr source type must not be a pointer", MI);
1190 } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1191 if (!SrcTy.isPointer())
1192 report("ptrtoint source type must be a pointer", MI);
1193 if (DstTy.isPointer())
1194 report("ptrtoint result type must not be a pointer", MI);
1195 } else {
1196 assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)(static_cast <bool> (MI->getOpcode() == TargetOpcode
::G_ADDRSPACE_CAST) ? void (0) : __assert_fail ("MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 1196, __extension__
__PRETTY_FUNCTION__))
;
1197 if (!SrcTy.isPointer() || !DstTy.isPointer())
1198 report("addrspacecast types must be pointers", MI);
1199 else {
1200 if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1201 report("addrspacecast must convert different address spaces", MI);
1202 }
1203 }
1204
1205 break;
1206 }
1207 case TargetOpcode::G_PTR_ADD: {
1208 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1209 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1210 LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1211 if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1212 break;
1213
1214 if (!PtrTy.getScalarType().isPointer())
1215 report("gep first operand must be a pointer", MI);
1216
1217 if (OffsetTy.getScalarType().isPointer())
1218 report("gep offset operand must not be a pointer", MI);
1219
1220 // TODO: Is the offset allowed to be a scalar with a vector?
1221 break;
1222 }
1223 case TargetOpcode::G_PTRMASK: {
1224 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1225 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1226 LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
1227 if (!DstTy.isValid() || !SrcTy.isValid() || !MaskTy.isValid())
1228 break;
1229
1230 if (!DstTy.getScalarType().isPointer())
1231 report("ptrmask result type must be a pointer", MI);
1232
1233 if (!MaskTy.getScalarType().isScalar())
1234 report("ptrmask mask type must be an integer", MI);
1235
1236 verifyVectorElementMatch(DstTy, MaskTy, MI);
1237 break;
1238 }
1239 case TargetOpcode::G_SEXT:
1240 case TargetOpcode::G_ZEXT:
1241 case TargetOpcode::G_ANYEXT:
1242 case TargetOpcode::G_TRUNC:
1243 case TargetOpcode::G_FPEXT:
1244 case TargetOpcode::G_FPTRUNC: {
1245 // Number of operands and presense of types is already checked (and
1246 // reported in case of any issues), so no need to report them again. As
1247 // we're trying to report as many issues as possible at once, however, the
1248 // instructions aren't guaranteed to have the right number of operands or
1249 // types attached to them at this point
1250 assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}")(static_cast <bool> (MCID.getNumOperands() == 2 &&
"Expected 2 operands G_*{EXT,TRUNC}") ? void (0) : __assert_fail
("MCID.getNumOperands() == 2 && \"Expected 2 operands G_*{EXT,TRUNC}\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 1250, __extension__
__PRETTY_FUNCTION__))
;
1251 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1252 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1253 if (!DstTy.isValid() || !SrcTy.isValid())
1254 break;
1255
1256 LLT DstElTy = DstTy.getScalarType();
1257 LLT SrcElTy = SrcTy.getScalarType();
1258 if (DstElTy.isPointer() || SrcElTy.isPointer())
1259 report("Generic extend/truncate can not operate on pointers", MI);
1260
1261 verifyVectorElementMatch(DstTy, SrcTy, MI);
1262
1263 unsigned DstSize = DstElTy.getSizeInBits();
1264 unsigned SrcSize = SrcElTy.getSizeInBits();
1265 switch (MI->getOpcode()) {
1266 default:
1267 if (DstSize <= SrcSize)
1268 report("Generic extend has destination type no larger than source", MI);
1269 break;
1270 case TargetOpcode::G_TRUNC:
1271 case TargetOpcode::G_FPTRUNC:
1272 if (DstSize >= SrcSize)
1273 report("Generic truncate has destination type no smaller than source",
1274 MI);
1275 break;
1276 }
1277 break;
1278 }
1279 case TargetOpcode::G_SELECT: {
1280 LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1281 LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1282 if (!SelTy.isValid() || !CondTy.isValid())
1283 break;
1284
1285 // Scalar condition select on a vector is valid.
1286 if (CondTy.isVector())
1287 verifyVectorElementMatch(SelTy, CondTy, MI);
1288 break;
1289 }
1290 case TargetOpcode::G_MERGE_VALUES: {
1291 // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1292 // e.g. s2N = MERGE sN, sN
1293 // Merging multiple scalars into a vector is not allowed, should use
1294 // G_BUILD_VECTOR for that.
1295 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1296 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1297 if (DstTy.isVector() || SrcTy.isVector())
1298 report("G_MERGE_VALUES cannot operate on vectors", MI);
1299
1300 const unsigned NumOps = MI->getNumOperands();
1301 if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1302 report("G_MERGE_VALUES result size is inconsistent", MI);
1303
1304 for (unsigned I = 2; I != NumOps; ++I) {
1305 if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1306 report("G_MERGE_VALUES source types do not match", MI);
1307 }
1308
1309 break;
1310 }
1311 case TargetOpcode::G_UNMERGE_VALUES: {
1312 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1313 LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1314 // For now G_UNMERGE can split vectors.
1315 for (unsigned i = 0; i < MI->getNumOperands()-1; ++i) {
1316 if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1317 report("G_UNMERGE_VALUES destination types do not match", MI);
1318 }
1319 if (SrcTy.getSizeInBits() !=
1320 (DstTy.getSizeInBits() * (MI->getNumOperands() - 1))) {
1321 report("G_UNMERGE_VALUES source operand does not cover dest operands",
1322 MI);
1323 }
1324 break;
1325 }
1326 case TargetOpcode::G_BUILD_VECTOR: {
1327 // Source types must be scalars, dest type a vector. Total size of scalars
1328 // must match the dest vector size.
1329 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1330 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1331 if (!DstTy.isVector() || SrcEltTy.isVector()) {
1332 report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1333 break;
1334 }
1335
1336 if (DstTy.getElementType() != SrcEltTy)
1337 report("G_BUILD_VECTOR result element type must match source type", MI);
1338
1339 if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1340 report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1341
1342 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1343 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1344 report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1345
1346 break;
1347 }
1348 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1349 // Source types must be scalars, dest type a vector. Scalar types must be
1350 // larger than the dest vector elt type, as this is a truncating operation.
1351 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1352 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1353 if (!DstTy.isVector() || SrcEltTy.isVector())
1354 report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1355 MI);
1356 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1357 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1358 report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1359 MI);
1360 if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1361 report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1362 "dest elt type",
1363 MI);
1364 break;
1365 }
1366 case TargetOpcode::G_CONCAT_VECTORS: {
1367 // Source types should be vectors, and total size should match the dest
1368 // vector size.
1369 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1370 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1371 if (!DstTy.isVector() || !SrcTy.isVector())
1372 report("G_CONCAT_VECTOR requires vector source and destination operands",
1373 MI);
1374
1375 if (MI->getNumOperands() < 3)
1376 report("G_CONCAT_VECTOR requires at least 2 source operands", MI);
1377
1378 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1379 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1380 report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1381 if (DstTy.getNumElements() !=
1382 SrcTy.getNumElements() * (MI->getNumOperands() - 1))
1383 report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1384 break;
1385 }
1386 case TargetOpcode::G_ICMP:
1387 case TargetOpcode::G_FCMP: {
1388 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1389 LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1390
1391 if ((DstTy.isVector() != SrcTy.isVector()) ||
1392 (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1393 report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1394
1395 break;
1396 }
1397 case TargetOpcode::G_EXTRACT: {
1398 const MachineOperand &SrcOp = MI->getOperand(1);
1399 if (!SrcOp.isReg()) {
1400 report("extract source must be a register", MI);
1401 break;
1402 }
1403
1404 const MachineOperand &OffsetOp = MI->getOperand(2);
1405 if (!OffsetOp.isImm()) {
1406 report("extract offset must be a constant", MI);
1407 break;
1408 }
1409
1410 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1411 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1412 if (SrcSize == DstSize)
1413 report("extract source must be larger than result", MI);
1414
1415 if (DstSize + OffsetOp.getImm() > SrcSize)
1416 report("extract reads past end of register", MI);
1417 break;
1418 }
1419 case TargetOpcode::G_INSERT: {
1420 const MachineOperand &SrcOp = MI->getOperand(2);
1421 if (!SrcOp.isReg()) {
1422 report("insert source must be a register", MI);
1423 break;
1424 }
1425
1426 const MachineOperand &OffsetOp = MI->getOperand(3);
1427 if (!OffsetOp.isImm()) {
1428 report("insert offset must be a constant", MI);
1429 break;
1430 }
1431
1432 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1433 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1434
1435 if (DstSize <= SrcSize)
1436 report("inserted size must be smaller than total register", MI);
1437
1438 if (SrcSize + OffsetOp.getImm() > DstSize)
1439 report("insert writes past end of register", MI);
1440
1441 break;
1442 }
1443 case TargetOpcode::G_JUMP_TABLE: {
1444 if (!MI->getOperand(1).isJTI())
1445 report("G_JUMP_TABLE source operand must be a jump table index", MI);
1446 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1447 if (!DstTy.isPointer())
1448 report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1449 break;
1450 }
1451 case TargetOpcode::G_BRJT: {
1452 if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1453 report("G_BRJT src operand 0 must be a pointer type", MI);
1454
1455 if (!MI->getOperand(1).isJTI())
1456 report("G_BRJT src operand 1 must be a jump table index", MI);
1457
1458 const auto &IdxOp = MI->getOperand(2);
1459 if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1460 report("G_BRJT src operand 2 must be a scalar reg type", MI);
1461 break;
1462 }
1463 case TargetOpcode::G_INTRINSIC:
1464 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1465 // TODO: Should verify number of def and use operands, but the current
1466 // interface requires passing in IR types for mangling.
1467 const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1468 if (!IntrIDOp.isIntrinsicID()) {
1469 report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1470 break;
1471 }
1472
1473 bool NoSideEffects = MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1474 unsigned IntrID = IntrIDOp.getIntrinsicID();
1475 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1476 AttributeList Attrs
1477 = Intrinsic::getAttributes(MF->getFunction().getContext(),
1478 static_cast<Intrinsic::ID>(IntrID));
1479 bool DeclHasSideEffects = !Attrs.hasFnAttr(Attribute::ReadNone);
1480 if (NoSideEffects && DeclHasSideEffects) {
1481 report("G_INTRINSIC used with intrinsic that accesses memory", MI);
1482 break;
1483 }
1484 if (!NoSideEffects && !DeclHasSideEffects) {
1485 report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI);
1486 break;
1487 }
1488 }
1489
1490 break;
1491 }
1492 case TargetOpcode::G_SEXT_INREG: {
1493 if (!MI->getOperand(2).isImm()) {
1494 report("G_SEXT_INREG expects an immediate operand #2", MI);
1495 break;
1496 }
1497
1498 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1499 int64_t Imm = MI->getOperand(2).getImm();
1500 if (Imm <= 0)
1501 report("G_SEXT_INREG size must be >= 1", MI);
1502 if (Imm >= SrcTy.getScalarSizeInBits())
1503 report("G_SEXT_INREG size must be less than source bit width", MI);
1504 break;
1505 }
1506 case TargetOpcode::G_SHUFFLE_VECTOR: {
1507 const MachineOperand &MaskOp = MI->getOperand(3);
1508 if (!MaskOp.isShuffleMask()) {
1509 report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
1510 break;
1511 }
1512
1513 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1514 LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1515 LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1516
1517 if (Src0Ty != Src1Ty)
1518 report("Source operands must be the same type", MI);
1519
1520 if (Src0Ty.getScalarType() != DstTy.getScalarType())
1521 report("G_SHUFFLE_VECTOR cannot change element type", MI);
1522
1523 // Don't check that all operands are vector because scalars are used in
1524 // place of 1 element vectors.
1525 int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
1526 int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
1527
1528 ArrayRef<int> MaskIdxes = MaskOp.getShuffleMask();
1529
1530 if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
1531 report("Wrong result type for shufflemask", MI);
1532
1533 for (int Idx : MaskIdxes) {
1534 if (Idx < 0)
1535 continue;
1536
1537 if (Idx >= 2 * SrcNumElts)
1538 report("Out of bounds shuffle index", MI);
1539 }
1540
1541 break;
1542 }
1543 case TargetOpcode::G_DYN_STACKALLOC: {
1544 const MachineOperand &DstOp = MI->getOperand(0);
1545 const MachineOperand &AllocOp = MI->getOperand(1);
1546 const MachineOperand &AlignOp = MI->getOperand(2);
1547
1548 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1549 report("dst operand 0 must be a pointer type", MI);
1550 break;
1551 }
1552
1553 if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1554 report("src operand 1 must be a scalar reg type", MI);
1555 break;
1556 }
1557
1558 if (!AlignOp.isImm()) {
1559 report("src operand 2 must be an immediate type", MI);
1560 break;
1561 }
1562 break;
1563 }
1564 case TargetOpcode::G_MEMCPY_INLINE:
1565 case TargetOpcode::G_MEMCPY:
1566 case TargetOpcode::G_MEMMOVE: {
1567 ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1568 if (MMOs.size() != 2) {
1569 report("memcpy/memmove must have 2 memory operands", MI);
1570 break;
1571 }
1572
1573 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
1574 (MMOs[1]->isStore() || !MMOs[1]->isLoad())) {
1575 report("wrong memory operand types", MI);
1576 break;
1577 }
1578
1579 if (MMOs[0]->getSize() != MMOs[1]->getSize())
1580 report("inconsistent memory operand sizes", MI);
1581
1582 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1583 LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
1584
1585 if (!DstPtrTy.isPointer() || !SrcPtrTy.isPointer()) {
1586 report("memory instruction operand must be a pointer", MI);
1587 break;
1588 }
1589
1590 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1591 report("inconsistent store address space", MI);
1592 if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
1593 report("inconsistent load address space", MI);
1594
1595 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1596 if (!MI->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL))
1597 report("'tail' flag (operand 3) must be an immediate 0 or 1", MI);
1598
1599 break;
1600 }
1601 case TargetOpcode::G_BZERO:
1602 case TargetOpcode::G_MEMSET: {
1603 ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1604 std::string Name = Opc == TargetOpcode::G_MEMSET ? "memset" : "bzero";
1605 if (MMOs.size() != 1) {
1606 report(Twine(Name, " must have 1 memory operand"), MI);
1607 break;
1608 }
1609
1610 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
1611 report(Twine(Name, " memory operand must be a store"), MI);
1612 break;
1613 }
1614
1615 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1616 if (!DstPtrTy.isPointer()) {
1617 report(Twine(Name, " operand must be a pointer"), MI);
1618 break;
1619 }
1620
1621 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1622 report("inconsistent " + Twine(Name, " address space"), MI);
1623
1624 if (!MI->getOperand(MI->getNumOperands() - 1).isImm() ||
1625 (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL))
1626 report("'tail' flag (last operand) must be an immediate 0 or 1", MI);
1627
1628 break;
1629 }
1630 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1631 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1632 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1633 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1634 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1635 if (!DstTy.isScalar())
1636 report("Vector reduction requires a scalar destination type", MI);
1637 if (!Src1Ty.isScalar())
1638 report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
1639 if (!Src2Ty.isVector())
1640 report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
1641 break;
1642 }
1643 case TargetOpcode::G_VECREDUCE_FADD:
1644 case TargetOpcode::G_VECREDUCE_FMUL:
1645 case TargetOpcode::G_VECREDUCE_FMAX:
1646 case TargetOpcode::G_VECREDUCE_FMIN:
1647 case TargetOpcode::G_VECREDUCE_ADD:
1648 case TargetOpcode::G_VECREDUCE_MUL:
1649 case TargetOpcode::G_VECREDUCE_AND:
1650 case TargetOpcode::G_VECREDUCE_OR:
1651 case TargetOpcode::G_VECREDUCE_XOR:
1652 case TargetOpcode::G_VECREDUCE_SMAX:
1653 case TargetOpcode::G_VECREDUCE_SMIN:
1654 case TargetOpcode::G_VECREDUCE_UMAX:
1655 case TargetOpcode::G_VECREDUCE_UMIN: {
1656 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1657 if (!DstTy.isScalar())
1658 report("Vector reduction requires a scalar destination type", MI);
1659 break;
1660 }
1661
1662 case TargetOpcode::G_SBFX:
1663 case TargetOpcode::G_UBFX: {
1664 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1665 if (DstTy.isVector()) {
1666 report("Bitfield extraction is not supported on vectors", MI);
1667 break;
1668 }
1669 break;
1670 }
1671 case TargetOpcode::G_SHL:
1672 case TargetOpcode::G_LSHR:
1673 case TargetOpcode::G_ASHR:
1674 case TargetOpcode::G_ROTR:
1675 case TargetOpcode::G_ROTL: {
1676 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1677 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1678 if (Src1Ty.isVector() != Src2Ty.isVector()) {
1679 report("Shifts and rotates require operands to be either all scalars or "
1680 "all vectors",
1681 MI);
1682 break;
1683 }
1684 break;
1685 }
1686 case TargetOpcode::G_LLROUND:
1687 case TargetOpcode::G_LROUND: {
1688 verifyAllRegOpsScalar(*MI, *MRI);
1689 break;
1690 }
1691 case TargetOpcode::G_IS_FPCLASS: {
1692 LLT DestTy = MRI->getType(MI->getOperand(0).getReg());
1693 LLT DestEltTy = DestTy.getScalarType();
1694 if (!DestEltTy.isScalar()) {
1695 report("Destination must be a scalar or vector of scalars", MI);
1696 break;
1697 }
1698 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1699 LLT SrcEltTy = SrcTy.getScalarType();
1700 if (!SrcEltTy.isScalar()) {
1701 report("Source must be a scalar or vector of scalars", MI);
1702 break;
1703 }
1704 if (!verifyVectorElementMatch(DestTy, SrcTy, MI))
1705 break;
1706 const MachineOperand &TestMO = MI->getOperand(2);
1707 if (!TestMO.isImm()) {
1708 report("floating-point class set (operand 2) must be an immediate", MI);
1709 break;
1710 }
1711 int64_t Test = TestMO.getImm();
1712 if (Test < 0 || Test > fcAllFlags) {
1713 report("Incorrect floating-point class set (operand 2)", MI);
1714 break;
1715 }
1716 const MachineOperand &SemanticsMO = MI->getOperand(3);
1717 if (!SemanticsMO.isImm()) {
1718 report("floating-point semantics (operand 3) must be an immediate", MI);
1719 break;
1720 }
1721 int64_t Semantics = SemanticsMO.getImm();
1722 if (Semantics < 0 || Semantics > APFloat::S_MaxSemantics) {
1723 report("Incorrect floating-point semantics (operand 3)", MI);
1724 break;
1725 }
1726 break;
1727 }
1728 case TargetOpcode::G_ASSERT_ALIGN: {
1729 if (MI->getOperand(2).getImm() < 1)
1730 report("alignment immediate must be >= 1", MI);
1731 break;
1732 }
1733 default:
1734 break;
1735 }
1736}
1737
1738void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
1739 const MCInstrDesc &MCID = MI->getDesc();
1740 if (MI->getNumOperands() < MCID.getNumOperands()) {
1741 report("Too few operands", MI);
1742 errs() << MCID.getNumOperands() << " operands expected, but "
1743 << MI->getNumOperands() << " given.\n";
1744 }
1745
1746 if (MI->isPHI()) {
1747 if (MF->getProperties().hasProperty(
1748 MachineFunctionProperties::Property::NoPHIs))
1749 report("Found PHI instruction with NoPHIs property set", MI);
1750
1751 if (FirstNonPHI)
1752 report("Found PHI instruction after non-PHI", MI);
1753 } else if (FirstNonPHI == nullptr)
1754 FirstNonPHI = MI;
1755
1756 // Check the tied operands.
1757 if (MI->isInlineAsm())
1758 verifyInlineAsm(MI);
1759
1760 // Check that unspillable terminators define a reg and have at most one use.
1761 if (TII->isUnspillableTerminator(MI)) {
1762 if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
1763 report("Unspillable Terminator does not define a reg", MI);
1764 Register Def = MI->getOperand(0).getReg();
1765 if (Def.isVirtual() &&
1766 !MF->getProperties().hasProperty(
1767 MachineFunctionProperties::Property::NoPHIs) &&
1768 std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
1769 report("Unspillable Terminator expected to have at most one use!", MI);
1770 }
1771
1772 // A fully-formed DBG_VALUE must have a location. Ignore partially formed
1773 // DBG_VALUEs: these are convenient to use in tests, but should never get
1774 // generated.
1775 if (MI->isDebugValue() && MI->getNumOperands() == 4)
1776 if (!MI->getDebugLoc())
1777 report("Missing DebugLoc for debug instruction", MI);
1778
1779 // Meta instructions should never be the subject of debug value tracking,
1780 // they don't create a value in the output program at all.
1781 if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
1782 report("Metadata instruction should not have a value tracking number", MI);
1783
1784 // Check the MachineMemOperands for basic consistency.
1785 for (MachineMemOperand *Op : MI->memoperands()) {
1786 if (Op->isLoad() && !MI->mayLoad())
1787 report("Missing mayLoad flag", MI);
1788 if (Op->isStore() && !MI->mayStore())
1789 report("Missing mayStore flag", MI);
1790 }
1791
1792 // Debug values must not have a slot index.
1793 // Other instructions must have one, unless they are inside a bundle.
1794 if (LiveInts) {
1795 bool mapped = !LiveInts->isNotInMIMap(*MI);
1796 if (MI->isDebugOrPseudoInstr()) {
1797 if (mapped)
1798 report("Debug instruction has a slot index", MI);
1799 } else if (MI->isInsideBundle()) {
1800 if (mapped)
1801 report("Instruction inside bundle has a slot index", MI);
1802 } else {
1803 if (!mapped)
1804 report("Missing slot index", MI);
1805 }
1806 }
1807
1808 unsigned Opc = MCID.getOpcode();
1809 if (isPreISelGenericOpcode(Opc) || isPreISelGenericOptimizationHint(Opc)) {
1810 verifyPreISelGenericInstruction(MI);
1811 return;
1812 }
1813
1814 StringRef ErrorInfo;
1815 if (!TII->verifyInstruction(*MI, ErrorInfo))
1816 report(ErrorInfo.data(), MI);
1817
1818 // Verify properties of various specific instruction types
1819 switch (MI->getOpcode()) {
1820 case TargetOpcode::COPY: {
1821 const MachineOperand &DstOp = MI->getOperand(0);
1822 const MachineOperand &SrcOp = MI->getOperand(1);
1823 const Register SrcReg = SrcOp.getReg();
1824 const Register DstReg = DstOp.getReg();
1825
1826 LLT DstTy = MRI->getType(DstReg);
1827 LLT SrcTy = MRI->getType(SrcReg);
1828 if (SrcTy.isValid() && DstTy.isValid()) {
1829 // If both types are valid, check that the types are the same.
1830 if (SrcTy != DstTy) {
1831 report("Copy Instruction is illegal with mismatching types", MI);
1832 errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
1833 }
1834
1835 break;
1836 }
1837
1838 if (!SrcTy.isValid() && !DstTy.isValid())
1839 break;
1840
1841 // If we have only one valid type, this is likely a copy between a virtual
1842 // and physical register.
1843 unsigned SrcSize = 0;
1844 unsigned DstSize = 0;
1845 if (SrcReg.isPhysical() && DstTy.isValid()) {
1846 const TargetRegisterClass *SrcRC =
1847 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
1848 if (SrcRC)
1849 SrcSize = TRI->getRegSizeInBits(*SrcRC);
1850 }
1851
1852 if (SrcSize == 0)
1853 SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
1854
1855 if (DstReg.isPhysical() && SrcTy.isValid()) {
1856 const TargetRegisterClass *DstRC =
1857 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1858 if (DstRC)
1859 DstSize = TRI->getRegSizeInBits(*DstRC);
1860 }
1861
1862 if (DstSize == 0)
1863 DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
1864
1865 if (SrcSize != 0 && DstSize != 0 && SrcSize != DstSize) {
1866 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1867 report("Copy Instruction is illegal with mismatching sizes", MI);
1868 errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
1869 << "\n";
1870 }
1871 }
1872 break;
1873 }
1874 case TargetOpcode::STATEPOINT: {
1875 StatepointOpers SO(MI);
1876 if (!MI->getOperand(SO.getIDPos()).isImm() ||
1877 !MI->getOperand(SO.getNBytesPos()).isImm() ||
1878 !MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1879 report("meta operands to STATEPOINT not constant!", MI);
1880 break;
1881 }
1882
1883 auto VerifyStackMapConstant = [&](unsigned Offset) {
1884 if (Offset >= MI->getNumOperands()) {
1885 report("stack map constant to STATEPOINT is out of range!", MI);
1886 return;
1887 }
1888 if (!MI->getOperand(Offset - 1).isImm() ||
1889 MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
1890 !MI->getOperand(Offset).isImm())
1891 report("stack map constant to STATEPOINT not well formed!", MI);
1892 };
1893 VerifyStackMapConstant(SO.getCCIdx());
1894 VerifyStackMapConstant(SO.getFlagsIdx());
1895 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
1896 VerifyStackMapConstant(SO.getNumGCPtrIdx());
1897 VerifyStackMapConstant(SO.getNumAllocaIdx());
1898 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
1899
1900 // Verify that all explicit statepoint defs are tied to gc operands as
1901 // they are expected to be a relocation of gc operands.
1902 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
1903 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
1904 for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
1905 unsigned UseOpIdx;
1906 if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
1907 report("STATEPOINT defs expected to be tied", MI);
1908 break;
1909 }
1910 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
1911 report("STATEPOINT def tied to non-gc operand", MI);
1912 break;
1913 }
1914 }
1915
1916 // TODO: verify we have properly encoded deopt arguments
1917 } break;
1918 case TargetOpcode::INSERT_SUBREG: {
1919 unsigned InsertedSize;
1920 if (unsigned SubIdx = MI->getOperand(2).getSubReg())
1921 InsertedSize = TRI->getSubRegIdxSize(SubIdx);
1922 else
1923 InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
1924 unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
1925 if (SubRegSize < InsertedSize) {
1926 report("INSERT_SUBREG expected inserted value to have equal or lesser "
1927 "size than the subreg it was inserted into", MI);
1928 break;
1929 }
1930 } break;
1931 case TargetOpcode::REG_SEQUENCE: {
1932 unsigned NumOps = MI->getNumOperands();
1933 if (!(NumOps & 1)) {
1934 report("Invalid number of operands for REG_SEQUENCE", MI);
1935 break;
1936 }
1937
1938 for (unsigned I = 1; I != NumOps; I += 2) {
1939 const MachineOperand &RegOp = MI->getOperand(I);
1940 const MachineOperand &SubRegOp = MI->getOperand(I + 1);
1941
1942 if (!RegOp.isReg())
1943 report("Invalid register operand for REG_SEQUENCE", &RegOp, I);
1944
1945 if (!SubRegOp.isImm() || SubRegOp.getImm() == 0 ||
1946 SubRegOp.getImm() >= TRI->getNumSubRegIndices()) {
1947 report("Invalid subregister index operand for REG_SEQUENCE",
1948 &SubRegOp, I + 1);
1949 }
1950 }
1951
1952 Register DstReg = MI->getOperand(0).getReg();
1953 if (DstReg.isPhysical())
1954 report("REG_SEQUENCE does not support physical register results", MI);
1955
1956 if (MI->getOperand(0).getSubReg())
1957 report("Invalid subreg result for REG_SEQUENCE", MI);
1958
1959 break;
1960 }
1961 }
1962}
1963
1964void
1965MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1966 const MachineInstr *MI = MO->getParent();
1967 const MCInstrDesc &MCID = MI->getDesc();
1968 unsigned NumDefs = MCID.getNumDefs();
1969 if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
1
Assuming the condition is false
2
Taking false branch
1970 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
1971
1972 // The first MCID.NumDefs operands must be explicit register defines
1973 if (MONum < NumDefs) {
3
Assuming 'MONum' is < 'NumDefs'
4
Taking true branch
1974 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1975 if (!MO->isReg())
1976 report("Explicit definition must be a register", MO, MONum);
1977 else if (!MO->isDef() && !MCOI.isOptionalDef())
5
Assuming the condition is false
1978 report("Explicit definition marked as use", MO, MONum);
1979 else if (MO->isImplicit())
6
Assuming the condition is false
7
Taking false branch
1980 report("Explicit definition marked as implicit", MO, MONum);
1981 } else if (MONum < MCID.getNumOperands()) {
1982 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1983 // Don't check if it's the last operand in a variadic instruction. See,
1984 // e.g., LDM_RET in the arm back end. Check non-variadic operands only.
1985 bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
1986 if (!IsOptional) {
1987 if (MO->isReg()) {
1988 if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs())
1989 report("Explicit operand marked as def", MO, MONum);
1990 if (MO->isImplicit())
1991 report("Explicit operand marked as implicit", MO, MONum);
1992 }
1993
1994 // Check that an instruction has register operands only as expected.
1995 if (MCOI.OperandType == MCOI::OPERAND_REGISTER &&
1996 !MO->isReg() && !MO->isFI())
1997 report("Expected a register operand.", MO, MONum);
1998 if (MO->isReg()) {
1999 if (MCOI.OperandType == MCOI::OPERAND_IMMEDIATE ||
2000 (MCOI.OperandType == MCOI::OPERAND_PCREL &&
2001 !TII->isPCRelRegisterOperandLegal(*MO)))
2002 report("Expected a non-register operand.", MO, MONum);
2003 }
2004 }
2005
2006 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
2007 if (TiedTo != -1) {
2008 if (!MO->isReg())
2009 report("Tied use must be a register", MO, MONum);
2010 else if (!MO->isTied())
2011 report("Operand should be tied", MO, MONum);
2012 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
2013 report("Tied def doesn't match MCInstrDesc", MO, MONum);
2014 else if (Register::isPhysicalRegister(MO->getReg())) {
2015 const MachineOperand &MOTied = MI->getOperand(TiedTo);
2016 if (!MOTied.isReg())
2017 report("Tied counterpart must be a register", &MOTied, TiedTo);
2018 else if (Register::isPhysicalRegister(MOTied.getReg()) &&
2019 MO->getReg() != MOTied.getReg())
2020 report("Tied physical registers must match.", &MOTied, TiedTo);
2021 }
2022 } else if (MO->isReg() && MO->isTied())
2023 report("Explicit operand should not be tied", MO, MONum);
2024 } else {
2025 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
2026 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
2027 report("Extra explicit operand on non-variadic instruction", MO, MONum);
2028 }
2029
2030 switch (MO->getType()) {
8
Control jumps to 'case MO_Register:' at line 2031
2031 case MachineOperand::MO_Register: {
2032 // Verify debug flag on debug instructions. Check this first because reg0
2033 // indicates an undefined debug value.
2034 if (MI->isDebugInstr() && MO->isUse()) {
2035 if (!MO->isDebug())
2036 report("Register operand must be marked debug", MO, MONum);
2037 } else if (MO->isDebug()) {
9
Assuming the condition is false
10
Taking false branch
2038 report("Register operand must not be marked debug", MO, MONum);
2039 }
2040
2041 const Register Reg = MO->getReg();
2042 if (!Reg)
11
Assuming the condition is false
2043 return;
2044 if (MRI->tracksLiveness() && !MI->isDebugInstr())
12
Taking true branch
2045 checkLiveness(MO, MONum);
13
Calling 'MachineVerifier::checkLiveness'
2046
2047 if (MO->isDef() && MO->isUndef() && !MO->getSubReg() &&
2048 MO->getReg().isVirtual()) // TODO: Apply to physregs too
2049 report("Undef virtual register def operands require a subregister", MO, MONum);
2050
2051 // Verify the consistency of tied operands.
2052 if (MO->isTied()) {
2053 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
2054 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
2055 if (!OtherMO.isReg())
2056 report("Must be tied to a register", MO, MONum);
2057 if (!OtherMO.isTied())
2058 report("Missing tie flags on tied operand", MO, MONum);
2059 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
2060 report("Inconsistent tie links", MO, MONum);
2061 if (MONum < MCID.getNumDefs()) {
2062 if (OtherIdx < MCID.getNumOperands()) {
2063 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
2064 report("Explicit def tied to explicit use without tie constraint",
2065 MO, MONum);
2066 } else {
2067 if (!OtherMO.isImplicit())
2068 report("Explicit def should be tied to implicit use", MO, MONum);
2069 }
2070 }
2071 }
2072
2073 // Verify two-address constraints after the twoaddressinstruction pass.
2074 // Both twoaddressinstruction pass and phi-node-elimination pass call
2075 // MRI->leaveSSA() to set MF as NoSSA, we should do the verification after
2076 // twoaddressinstruction pass not after phi-node-elimination pass. So we
2077 // shouldn't use the NoSSA as the condition, we should based on
2078 // TiedOpsRewritten property to verify two-address constraints, this
2079 // property will be set in twoaddressinstruction pass.
2080 unsigned DefIdx;
2081 if (MF->getProperties().hasProperty(
2082 MachineFunctionProperties::Property::TiedOpsRewritten) &&
2083 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2084 Reg != MI->getOperand(DefIdx).getReg())
2085 report("Two-address instruction operands must be identical", MO, MONum);
2086
2087 // Check register classes.
2088 unsigned SubIdx = MO->getSubReg();
2089
2090 if (Register::isPhysicalRegister(Reg)) {
2091 if (SubIdx) {
2092 report("Illegal subregister index for physical register", MO, MONum);
2093 return;
2094 }
2095 if (MONum < MCID.getNumOperands()) {
2096 if (const TargetRegisterClass *DRC =
2097 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2098 if (!DRC->contains(Reg)) {
2099 report("Illegal physical register for instruction", MO, MONum);
2100 errs() << printReg(Reg, TRI) << " is not a "
2101 << TRI->getRegClassName(DRC) << " register.\n";
2102 }
2103 }
2104 }
2105 if (MO->isRenamable()) {
2106 if (MRI->isReserved(Reg)) {
2107 report("isRenamable set on reserved register", MO, MONum);
2108 return;
2109 }
2110 }
2111 } else {
2112 // Virtual register.
2113 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
2114 if (!RC) {
2115 // This is a generic virtual register.
2116
2117 // Do not allow undef uses for generic virtual registers. This ensures
2118 // getVRegDef can never fail and return null on a generic register.
2119 //
2120 // FIXME: This restriction should probably be broadened to all SSA
2121 // MIR. However, DetectDeadLanes/ProcessImplicitDefs technically still
2122 // run on the SSA function just before phi elimination.
2123 if (MO->isUndef())
2124 report("Generic virtual register use cannot be undef", MO, MONum);
2125
2126 // Debug value instruction is permitted to use undefined vregs.
2127 // This is a performance measure to skip the overhead of immediately
2128 // pruning unused debug operands. The final undef substitution occurs
2129 // when debug values are allocated in LDVImpl::handleDebugValue, so
2130 // these verifications always apply after this pass.
2131 if (isFunctionTracksDebugUserValues || !MO->isUse() ||
2132 !MI->isDebugValue() || !MRI->def_empty(Reg)) {
2133 // If we're post-Select, we can't have gvregs anymore.
2134 if (isFunctionSelected) {
2135 report("Generic virtual register invalid in a Selected function",
2136 MO, MONum);
2137 return;
2138 }
2139
2140 // The gvreg must have a type and it must not have a SubIdx.
2141 LLT Ty = MRI->getType(Reg);
2142 if (!Ty.isValid()) {
2143 report("Generic virtual register must have a valid type", MO,
2144 MONum);
2145 return;
2146 }
2147
2148 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
2149
2150 // If we're post-RegBankSelect, the gvreg must have a bank.
2151 if (!RegBank && isFunctionRegBankSelected) {
2152 report("Generic virtual register must have a bank in a "
2153 "RegBankSelected function",
2154 MO, MONum);
2155 return;
2156 }
2157
2158 // Make sure the register fits into its register bank if any.
2159 if (RegBank && Ty.isValid() &&
2160 RegBank->getSize() < Ty.getSizeInBits()) {
2161 report("Register bank is too small for virtual register", MO,
2162 MONum);
2163 errs() << "Register bank " << RegBank->getName() << " too small("
2164 << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
2165 << "-bits\n";
2166 return;
2167 }
2168 }
2169
2170 if (SubIdx) {
2171 report("Generic virtual register does not allow subregister index", MO,
2172 MONum);
2173 return;
2174 }
2175
2176 // If this is a target specific instruction and this operand
2177 // has register class constraint, the virtual register must
2178 // comply to it.
2179 if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
2180 MONum < MCID.getNumOperands() &&
2181 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2182 report("Virtual register does not match instruction constraint", MO,
2183 MONum);
2184 errs() << "Expect register class "
2185 << TRI->getRegClassName(
2186 TII->getRegClass(MCID, MONum, TRI, *MF))
2187 << " but got nothing\n";
2188 return;
2189 }
2190
2191 break;
2192 }
2193 if (SubIdx) {
2194 const TargetRegisterClass *SRC =
2195 TRI->getSubClassWithSubReg(RC, SubIdx);
2196 if (!SRC) {
2197 report("Invalid subregister index for virtual register", MO, MONum);
2198 errs() << "Register class " << TRI->getRegClassName(RC)
2199 << " does not support subreg index " << SubIdx << "\n";
2200 return;
2201 }
2202 if (RC != SRC) {
2203 report("Invalid register class for subregister index", MO, MONum);
2204 errs() << "Register class " << TRI->getRegClassName(RC)
2205 << " does not fully support subreg index " << SubIdx << "\n";
2206 return;
2207 }
2208 }
2209 if (MONum < MCID.getNumOperands()) {
2210 if (const TargetRegisterClass *DRC =
2211 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2212 if (SubIdx) {
2213 const TargetRegisterClass *SuperRC =
2214 TRI->getLargestLegalSuperClass(RC, *MF);
2215 if (!SuperRC) {
2216 report("No largest legal super class exists.", MO, MONum);
2217 return;
2218 }
2219 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2220 if (!DRC) {
2221 report("No matching super-reg register class.", MO, MONum);
2222 return;
2223 }
2224 }
2225 if (!RC->hasSuperClassEq(DRC)) {
2226 report("Illegal virtual register for instruction", MO, MONum);
2227 errs() << "Expected a " << TRI->getRegClassName(DRC)
2228 << " register, but got a " << TRI->getRegClassName(RC)
2229 << " register\n";
2230 }
2231 }
2232 }
2233 }
2234 break;
2235 }
2236
2237 case MachineOperand::MO_RegisterMask:
2238 regMasks.push_back(MO->getRegMask());
2239 break;
2240
2241 case MachineOperand::MO_MachineBasicBlock:
2242 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
2243 report("PHI operand is not in the CFG", MO, MONum);
2244 break;
2245
2246 case MachineOperand::MO_FrameIndex:
2247 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
2248 LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2249 int FI = MO->getIndex();
2250 LiveInterval &LI = LiveStks->getInterval(FI);
2251 SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
2252
2253 bool stores = MI->mayStore();
2254 bool loads = MI->mayLoad();
2255 // For a memory-to-memory move, we need to check if the frame
2256 // index is used for storing or loading, by inspecting the
2257 // memory operands.
2258 if (stores && loads) {
2259 for (auto *MMO : MI->memoperands()) {
2260 const PseudoSourceValue *PSV = MMO->getPseudoValue();
2261 if (PSV == nullptr) continue;
2262 const FixedStackPseudoSourceValue *Value =
2263 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2264 if (Value == nullptr) continue;
2265 if (Value->getFrameIndex() != FI) continue;
2266
2267 if (MMO->isStore())
2268 loads = false;
2269 else
2270 stores = false;
2271 break;
2272 }
2273 if (loads == stores)
2274 report("Missing fixed stack memoperand.", MI);
2275 }
2276 if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
2277 report("Instruction loads from dead spill slot", MO, MONum);
2278 errs() << "Live stack: " << LI << '\n';
2279 }
2280 if (stores && !LI.liveAt(Idx.getRegSlot())) {
2281 report("Instruction stores to dead spill slot", MO, MONum);
2282 errs() << "Live stack: " << LI << '\n';
2283 }
2284 }
2285 break;
2286
2287 case MachineOperand::MO_CFIIndex:
2288 if (MO->getCFIIndex() >= MF->getFrameInstructions().size())
2289 report("CFI instruction has invalid index", MO, MONum);
2290 break;
2291
2292 default:
2293 break;
2294 }
2295}
2296
2297void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
2298 unsigned MONum, SlotIndex UseIdx,
2299 const LiveRange &LR,
2300 Register VRegOrUnit,
2301 LaneBitmask LaneMask) {
2302 LiveQueryResult LRQ = LR.Query(UseIdx);
2303 // Check if we have a segment at the use, note however that we only need one
2304 // live subregister range, the others may be dead.
2305 if (!LRQ.valueIn() && LaneMask.none()) {
2306 report("No live segment at use", MO, MONum);
2307 report_context_liverange(LR);
2308 report_context_vreg_regunit(VRegOrUnit);
2309 report_context(UseIdx);
2310 }
2311 if (MO->isKill() && !LRQ.isKill()) {
2312 report("Live range continues after kill flag", MO, MONum);
2313 report_context_liverange(LR);
2314 report_context_vreg_regunit(VRegOrUnit);
2315 if (LaneMask.any())
2316 report_context_lanemask(LaneMask);
2317 report_context(UseIdx);
2318 }
2319}
2320
2321void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
2322 unsigned MONum, SlotIndex DefIdx,
2323 const LiveRange &LR,
2324 Register VRegOrUnit,
2325 bool SubRangeCheck,
2326 LaneBitmask LaneMask) {
2327 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
2328 // The LR can correspond to the whole reg and its def slot is not obliged
2329 // to be the same as the MO' def slot. E.g. when we check here "normal"
2330 // subreg MO but there is other EC subreg MO in the same instruction so the
2331 // whole reg has EC def slot and differs from the currently checked MO' def
2332 // slot. For example:
2333 // %0 [16e,32r:0) 0@16e L..3 [16e,32r:0) 0@16e L..C [16r,32r:0) 0@16r
2334 // Check that there is an early-clobber def of the same superregister
2335 // somewhere is performed in visitMachineFunctionAfter()
2336 if (((SubRangeCheck || MO->getSubReg() == 0) && VNI->def != DefIdx) ||
2337 !SlotIndex::isSameInstr(VNI->def, DefIdx) ||
2338 (VNI->def != DefIdx &&
2339 (!VNI->def.isEarlyClobber() || !DefIdx.isRegister()))) {
2340 report("Inconsistent valno->def", MO, MONum);
2341 report_context_liverange(LR);
2342 report_context_vreg_regunit(VRegOrUnit);
2343 if (LaneMask.any())
2344 report_context_lanemask(LaneMask);
2345 report_context(*VNI);
2346 report_context(DefIdx);
2347 }
2348 } else {
2349 report("No live segment at def", MO, MONum);
2350 report_context_liverange(LR);
2351 report_context_vreg_regunit(VRegOrUnit);
2352 if (LaneMask.any())
2353 report_context_lanemask(LaneMask);
2354 report_context(DefIdx);
2355 }
2356 // Check that, if the dead def flag is present, LiveInts agree.
2357 if (MO->isDead()) {
2358 LiveQueryResult LRQ = LR.Query(DefIdx);
2359 if (!LRQ.isDeadDef()) {
2360 assert(Register::isVirtualRegister(VRegOrUnit) &&(static_cast <bool> (Register::isVirtualRegister(VRegOrUnit
) && "Expecting a virtual register.") ? void (0) : __assert_fail
("Register::isVirtualRegister(VRegOrUnit) && \"Expecting a virtual register.\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2361, __extension__
__PRETTY_FUNCTION__))
2361 "Expecting a virtual register.")(static_cast <bool> (Register::isVirtualRegister(VRegOrUnit
) && "Expecting a virtual register.") ? void (0) : __assert_fail
("Register::isVirtualRegister(VRegOrUnit) && \"Expecting a virtual register.\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2361, __extension__
__PRETTY_FUNCTION__))
;
2362 // A dead subreg def only tells us that the specific subreg is dead. There
2363 // could be other non-dead defs of other subregs, or we could have other
2364 // parts of the register being live through the instruction. So unless we
2365 // are checking liveness for a subrange it is ok for the live range to
2366 // continue, given that we have a dead def of a subregister.
2367 if (SubRangeCheck || MO->getSubReg() == 0) {
2368 report("Live range continues after dead def flag", MO, MONum);
2369 report_context_liverange(LR);
2370 report_context_vreg_regunit(VRegOrUnit);
2371 if (LaneMask.any())
2372 report_context_lanemask(LaneMask);
2373 }
2374 }
2375 }
2376}
2377
2378void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
2379 const MachineInstr *MI = MO->getParent();
2380 const Register Reg = MO->getReg();
2381 const unsigned SubRegIdx = MO->getSubReg();
2382
2383 const LiveInterval *LI = nullptr;
14
'LI' initialized to a null pointer value
2384 if (LiveInts && Reg.isVirtual()) {
15
Assuming field 'LiveInts' is null
2385 if (LiveInts->hasInterval(Reg)) {
2386 LI = &LiveInts->getInterval(Reg);
2387 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() &&
2388 !LI->hasSubRanges() && MRI->shouldTrackSubRegLiveness(Reg))
2389 report("Live interval for subreg operand has no subranges", MO, MONum);
2390 } else {
2391 report("Virtual register has no live interval", MO, MONum);
2392 }
2393 }
2394
2395 // Both use and def operands can read a register.
2396 if (MO->readsReg()) {
16
Taking false branch
2397 if (MO->isKill())
2398 addRegWithSubRegs(regsKilled, Reg);
2399
2400 // Check that LiveVars knows this kill (unless we are inside a bundle, in
2401 // which case we have already checked that LiveVars knows any kills on the
2402 // bundle header instead).
2403 if (LiveVars && Reg.isVirtual() && MO->isKill() &&
2404 !MI->isBundledWithPred()) {
2405 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2406 if (!is_contained(VI.Kills, MI))
2407 report("Kill missing from LiveVariables", MO, MONum);
2408 }
2409
2410 // Check LiveInts liveness and kill.
2411 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2412 SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
2413 // Check the cached regunit intervals.
2414 if (Reg.isPhysical() && !isReserved(Reg)) {
2415 for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
2416 ++Units) {
2417 if (MRI->isReservedRegUnit(*Units))
2418 continue;
2419 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
2420 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2421 }
2422 }
2423
2424 if (Reg.isVirtual()) {
2425 // This is a virtual register interval.
2426 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2427
2428 if (LI->hasSubRanges() && !MO->isDef()) {
2429 LaneBitmask MOMask = SubRegIdx != 0
2430 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2431 : MRI->getMaxLaneMaskForVReg(Reg);
2432 LaneBitmask LiveInMask;
2433 for (const LiveInterval::SubRange &SR : LI->subranges()) {
2434 if ((MOMask & SR.LaneMask).none())
2435 continue;
2436 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2437 LiveQueryResult LRQ = SR.Query(UseIdx);
2438 if (LRQ.valueIn())
2439 LiveInMask |= SR.LaneMask;
2440 }
2441 // At least parts of the register has to be live at the use.
2442 if ((LiveInMask & MOMask).none()) {
2443 report("No live subrange at use", MO, MONum);
2444 report_context(*LI);
2445 report_context(UseIdx);
2446 }
2447 }
2448 }
2449 }
2450
2451 // Use of a dead register.
2452 if (!regsLive.count(Reg)) {
2453 if (Reg.isPhysical()) {
2454 // Reserved registers may be used even when 'dead'.
2455 bool Bad = !isReserved(Reg);
2456 // We are fine if just any subregister has a defined value.
2457 if (Bad) {
2458
2459 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
2460 if (regsLive.count(SubReg)) {
2461 Bad = false;
2462 break;
2463 }
2464 }
2465 }
2466 // If there is an additional implicit-use of a super register we stop
2467 // here. By definition we are fine if the super register is not
2468 // (completely) dead, if the complete super register is dead we will
2469 // get a report for its operand.
2470 if (Bad) {
2471 for (const MachineOperand &MOP : MI->uses()) {
2472 if (!MOP.isReg() || !MOP.isImplicit())
2473 continue;
2474
2475 if (!MOP.getReg().isPhysical())
2476 continue;
2477
2478 if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
2479 Bad = false;
2480 }
2481 }
2482 if (Bad)
2483 report("Using an undefined physical register", MO, MONum);
2484 } else if (MRI->def_empty(Reg)) {
2485 report("Reading virtual register without a def", MO, MONum);
2486 } else {
2487 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2488 // We don't know which virtual registers are live in, so only complain
2489 // if vreg was killed in this MBB. Otherwise keep track of vregs that
2490 // must be live in. PHI instructions are handled separately.
2491 if (MInfo.regsKilled.count(Reg))
2492 report("Using a killed virtual register", MO, MONum);
2493 else if (!MI->isPHI())
2494 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
2495 }
2496 }
2497 }
2498
2499 if (MO->isDef()) {
17
Taking true branch
2500 // Register defined.
2501 // TODO: verify that earlyclobber ops are not used.
2502 if (MO->isDead())
18
Assuming the condition is false
19
Taking false branch
2503 addRegWithSubRegs(regsDead, Reg);
2504 else
2505 addRegWithSubRegs(regsDefined, Reg);
20
Calling 'MachineVerifier::addRegWithSubRegs'
24
Returning from 'MachineVerifier::addRegWithSubRegs'
2506
2507 // Verify SSA form.
2508 if (MRI->isSSA() && Reg.isVirtual() &&
2509 std::next(MRI->def_begin(Reg)) != MRI->def_end())
2510 report("Multiple virtual register defs in SSA form", MO, MONum);
2511
2512 // Check LiveInts for a live segment, but only for virtual registers.
2513 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
25
Assuming field 'LiveInts' is non-null
26
Taking true branch
2514 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
2515 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
2516
2517 if (Reg.isVirtual()) {
27
Assuming the condition is true
28
Taking true branch
2518 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
29
Forming reference to null pointer
2519
2520 if (LI->hasSubRanges()) {
2521 LaneBitmask MOMask = SubRegIdx != 0
2522 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2523 : MRI->getMaxLaneMaskForVReg(Reg);
2524 for (const LiveInterval::SubRange &SR : LI->subranges()) {
2525 if ((SR.LaneMask & MOMask).none())
2526 continue;
2527 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
2528 }
2529 }
2530 }
2531 }
2532 }
2533}
2534
2535// This function gets called after visiting all instructions in a bundle. The
2536// argument points to the bundle header.
2537// Normal stand-alone instructions are also considered 'bundles', and this
2538// function is called for all of them.
2539void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
2540 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2541 set_union(MInfo.regsKilled, regsKilled);
2542 set_subtract(regsLive, regsKilled); regsKilled.clear();
2543 // Kill any masked registers.
2544 while (!regMasks.empty()) {
2545 const uint32_t *Mask = regMasks.pop_back_val();
2546 for (Register Reg : regsLive)
2547 if (Reg.isPhysical() &&
2548 MachineOperand::clobbersPhysReg(Mask, Reg.asMCReg()))
2549 regsDead.push_back(Reg);
2550 }
2551 set_subtract(regsLive, regsDead); regsDead.clear();
2552 set_union(regsLive, regsDefined); regsDefined.clear();
2553}
2554
2555void
2556MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
2557 MBBInfoMap[MBB].regsLiveOut = regsLive;
2558 regsLive.clear();
2559
2560 if (Indexes) {
2561 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
2562 if (!(stop > lastIndex)) {
2563 report("Block ends before last instruction index", MBB);
2564 errs() << "Block ends at " << stop
2565 << " last instruction was at " << lastIndex << '\n';
2566 }
2567 lastIndex = stop;
2568 }
2569}
2570
2571namespace {
2572// This implements a set of registers that serves as a filter: can filter other
2573// sets by passing through elements not in the filter and blocking those that
2574// are. Any filter implicitly includes the full set of physical registers upon
2575// creation, thus filtering them all out. The filter itself as a set only grows,
2576// and needs to be as efficient as possible.
2577struct VRegFilter {
2578 // Add elements to the filter itself. \pre Input set \p FromRegSet must have
2579 // no duplicates. Both virtual and physical registers are fine.
2580 template <typename RegSetT> void add(const RegSetT &FromRegSet) {
2581 SmallVector<Register, 0> VRegsBuffer;
2582 filterAndAdd(FromRegSet, VRegsBuffer);
2583 }
2584 // Filter \p FromRegSet through the filter and append passed elements into \p
2585 // ToVRegs. All elements appended are then added to the filter itself.
2586 // \returns true if anything changed.
2587 template <typename RegSetT>
2588 bool filterAndAdd(const RegSetT &FromRegSet,
2589 SmallVectorImpl<Register> &ToVRegs) {
2590 unsigned SparseUniverse = Sparse.size();
2591 unsigned NewSparseUniverse = SparseUniverse;
2592 unsigned NewDenseSize = Dense.size();
2593 size_t Begin = ToVRegs.size();
2594 for (Register Reg : FromRegSet) {
2595 if (!Reg.isVirtual())
2596 continue;
2597 unsigned Index = Register::virtReg2Index(Reg);
2598 if (Index < SparseUniverseMax) {
2599 if (Index < SparseUniverse && Sparse.test(Index))
2600 continue;
2601 NewSparseUniverse = std::max(NewSparseUniverse, Index + 1);
2602 } else {
2603 if (Dense.count(Reg))
2604 continue;
2605 ++NewDenseSize;
2606 }
2607 ToVRegs.push_back(Reg);
2608 }
2609 size_t End = ToVRegs.size();
2610 if (Begin == End)
2611 return false;
2612 // Reserving space in sets once performs better than doing so continuously
2613 // and pays easily for double look-ups (even in Dense with SparseUniverseMax
2614 // tuned all the way down) and double iteration (the second one is over a
2615 // SmallVector, which is a lot cheaper compared to DenseSet or BitVector).
2616 Sparse.resize(NewSparseUniverse);
2617 Dense.reserve(NewDenseSize);
2618 for (unsigned I = Begin; I < End; ++I) {
2619 Register Reg = ToVRegs[I];
2620 unsigned Index = Register::virtReg2Index(Reg);
2621 if (Index < SparseUniverseMax)
2622 Sparse.set(Index);
2623 else
2624 Dense.insert(Reg);
2625 }
2626 return true;
2627 }
2628
2629private:
2630 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2631 // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound
2632 // are tracked by Dense. The only purpose of the threashold and the Dense set
2633 // is to have a reasonably growing memory usage in pathological cases (large
2634 // number of very sparse VRegFilter instances live at the same time). In
2635 // practice even in the worst-by-execution time cases having all elements
2636 // tracked by Sparse (very large SparseUniverseMax scenario) tends to be more
2637 // space efficient than if tracked by Dense. The threashold is set to keep the
2638 // worst-case memory usage within 2x of figures determined empirically for
2639 // "all Dense" scenario in such worst-by-execution-time cases.
2640 BitVector Sparse;
2641 DenseSet<unsigned> Dense;
2642};
2643
2644// Implements both a transfer function and a (binary, in-place) join operator
2645// for a dataflow over register sets with set union join and filtering transfer
2646// (out_b = in_b \ filter_b). filter_b is expected to be set-up ahead of time.
2647// Maintains out_b as its state, allowing for O(n) iteration over it at any
2648// time, where n is the size of the set (as opposed to O(U) where U is the
2649// universe). filter_b implicitly contains all physical registers at all times.
2650class FilteringVRegSet {
2651 VRegFilter Filter;
2652 SmallVector<Register, 0> VRegs;
2653
2654public:
2655 // Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
2656 // Both virtual and physical registers are fine.
2657 template <typename RegSetT> void addToFilter(const RegSetT &RS) {
2658 Filter.add(RS);
2659 }
2660 // Passes \p RS through the filter_b (transfer function) and adds what's left
2661 // to itself (out_b).
2662 template <typename RegSetT> bool add(const RegSetT &RS) {
2663 // Double-duty the Filter: to maintain VRegs a set (and the join operation
2664 // a set union) just add everything being added here to the Filter as well.
2665 return Filter.filterAndAdd(RS, VRegs);
2666 }
2667 using const_iterator = decltype(VRegs)::const_iterator;
2668 const_iterator begin() const { return VRegs.begin(); }
2669 const_iterator end() const { return VRegs.end(); }
2670 size_t size() const { return VRegs.size(); }
2671};
2672} // namespace
2673
2674// Calculate the largest possible vregsPassed sets. These are the registers that
2675// can pass through an MBB live, but may not be live every time. It is assumed
2676// that all vregsPassed sets are empty before the call.
2677void MachineVerifier::calcRegsPassed() {
2678 if (MF->empty())
2679 // ReversePostOrderTraversal doesn't handle empty functions.
2680 return;
2681
2682 for (const MachineBasicBlock *MB :
2683 ReversePostOrderTraversal<const MachineFunction *>(MF)) {
2684 FilteringVRegSet VRegs;
2685 BBInfo &Info = MBBInfoMap[MB];
2686 assert(Info.reachable)(static_cast <bool> (Info.reachable) ? void (0) : __assert_fail
("Info.reachable", "llvm/lib/CodeGen/MachineVerifier.cpp", 2686
, __extension__ __PRETTY_FUNCTION__))
;
2687
2688 VRegs.addToFilter(Info.regsKilled);
2689 VRegs.addToFilter(Info.regsLiveOut);
2690 for (const MachineBasicBlock *Pred : MB->predecessors()) {
2691 const BBInfo &PredInfo = MBBInfoMap[Pred];
2692 if (!PredInfo.reachable)
2693 continue;
2694
2695 VRegs.add(PredInfo.regsLiveOut);
2696 VRegs.add(PredInfo.vregsPassed);
2697 }
2698 Info.vregsPassed.reserve(VRegs.size());
2699 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2700 }
2701}
2702
2703// Calculate the set of virtual registers that must be passed through each basic
2704// block in order to satisfy the requirements of successor blocks. This is very
2705// similar to calcRegsPassed, only backwards.
2706void MachineVerifier::calcRegsRequired() {
2707 // First push live-in regs to predecessors' vregsRequired.
2708 SmallPtrSet<const MachineBasicBlock*, 8> todo;
2709 for (const auto &MBB : *MF) {
2710 BBInfo &MInfo = MBBInfoMap[&MBB];
2711 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2712 BBInfo &PInfo = MBBInfoMap[Pred];
2713 if (PInfo.addRequired(MInfo.vregsLiveIn))
2714 todo.insert(Pred);
2715 }
2716
2717 // Handle the PHI node.
2718 for (const MachineInstr &MI : MBB.phis()) {
2719 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
2720 // Skip those Operands which are undef regs or not regs.
2721 if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg())
2722 continue;
2723
2724 // Get register and predecessor for one PHI edge.
2725 Register Reg = MI.getOperand(i).getReg();
2726 const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB();
2727
2728 BBInfo &PInfo = MBBInfoMap[Pred];
2729 if (PInfo.addRequired(Reg))
2730 todo.insert(Pred);
2731 }
2732 }
2733 }
2734
2735 // Iteratively push vregsRequired to predecessors. This will converge to the
2736 // same final state regardless of DenseSet iteration order.
2737 while (!todo.empty()) {
2738 const MachineBasicBlock *MBB = *todo.begin();
2739 todo.erase(MBB);
2740 BBInfo &MInfo = MBBInfoMap[MBB];
2741 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
2742 if (Pred == MBB)
2743 continue;
2744 BBInfo &SInfo = MBBInfoMap[Pred];
2745 if (SInfo.addRequired(MInfo.vregsRequired))
2746 todo.insert(Pred);
2747 }
2748 }
2749}
2750
2751// Check PHI instructions at the beginning of MBB. It is assumed that
2752// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2753void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
2754 BBInfo &MInfo = MBBInfoMap[&MBB];
2755
2756 SmallPtrSet<const MachineBasicBlock*, 8> seen;
2757 for (const MachineInstr &Phi : MBB) {
2758 if (!Phi.isPHI())
2759 break;
2760 seen.clear();
2761
2762 const MachineOperand &MODef = Phi.getOperand(0);
2763 if (!MODef.isReg() || !MODef.isDef()) {
2764 report("Expected first PHI operand to be a register def", &MODef, 0);
2765 continue;
2766 }
2767 if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
2768 MODef.isEarlyClobber() || MODef.isDebug())
2769 report("Unexpected flag on PHI operand", &MODef, 0);
2770 Register DefReg = MODef.getReg();
2771 if (!Register::isVirtualRegister(DefReg))
2772 report("Expected first PHI operand to be a virtual register", &MODef, 0);
2773
2774 for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
2775 const MachineOperand &MO0 = Phi.getOperand(I);
2776 if (!MO0.isReg()) {
2777 report("Expected PHI operand to be a register", &MO0, I);
2778 continue;
2779 }
2780 if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
2781 MO0.isDebug() || MO0.isTied())
2782 report("Unexpected flag on PHI operand", &MO0, I);
2783
2784 const MachineOperand &MO1 = Phi.getOperand(I + 1);
2785 if (!MO1.isMBB()) {
2786 report("Expected PHI operand to be a basic block", &MO1, I + 1);
2787 continue;
2788 }
2789
2790 const MachineBasicBlock &Pre = *MO1.getMBB();
2791 if (!Pre.isSuccessor(&MBB)) {
2792 report("PHI input is not a predecessor block", &MO1, I + 1);
2793 continue;
2794 }
2795
2796 if (MInfo.reachable) {
2797 seen.insert(&Pre);
2798 BBInfo &PrInfo = MBBInfoMap[&Pre];
2799 if (!MO0.isUndef() && PrInfo.reachable &&
2800 !PrInfo.isLiveOut(MO0.getReg()))
2801 report("PHI operand is not live-out from predecessor", &MO0, I);
2802 }
2803 }
2804
2805 // Did we see all predecessors?
2806 if (MInfo.reachable) {
2807 for (MachineBasicBlock *Pred : MBB.predecessors()) {
2808 if (!seen.count(Pred)) {
2809 report("Missing PHI operand", &Phi);
2810 errs() << printMBBReference(*Pred)
2811 << " is a predecessor according to the CFG.\n";
2812 }
2813 }
2814 }
2815 }
2816}
2817
2818void MachineVerifier::visitMachineFunctionAfter() {
2819 calcRegsPassed();
2820
2821 for (const MachineBasicBlock &MBB : *MF)
2822 checkPHIOps(MBB);
2823
2824 // Now check liveness info if available
2825 calcRegsRequired();
2826
2827 // Check for killed virtual registers that should be live out.
2828 for (const auto &MBB : *MF) {
2829 BBInfo &MInfo = MBBInfoMap[&MBB];
2830 for (Register VReg : MInfo.vregsRequired)
2831 if (MInfo.regsKilled.count(VReg)) {
2832 report("Virtual register killed in block, but needed live out.", &MBB);
2833 errs() << "Virtual register " << printReg(VReg)
2834 << " is used after the block.\n";
2835 }
2836 }
2837
2838 if (!MF->empty()) {
2839 BBInfo &MInfo = MBBInfoMap[&MF->front()];
2840 for (Register VReg : MInfo.vregsRequired) {
2841 report("Virtual register defs don't dominate all uses.", MF);
2842 report_context_vreg(VReg);
2843 }
2844 }
2845
2846 if (LiveVars)
2847 verifyLiveVariables();
2848 if (LiveInts)
2849 verifyLiveIntervals();
2850
2851 // Check live-in list of each MBB. If a register is live into MBB, check
2852 // that the register is in regsLiveOut of each predecessor block. Since
2853 // this must come from a definition in the predecesssor or its live-in
2854 // list, this will catch a live-through case where the predecessor does not
2855 // have the register in its live-in list. This currently only checks
2856 // registers that have no aliases, are not allocatable and are not
2857 // reserved, which could mean a condition code register for instance.
2858 if (MRI->tracksLiveness())
2859 for (const auto &MBB : *MF)
2860 for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
2861 MCPhysReg LiveInReg = P.PhysReg;
2862 bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
2863 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2864 continue;
2865 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2866 BBInfo &PInfo = MBBInfoMap[Pred];
2867 if (!PInfo.regsLiveOut.count(LiveInReg)) {
2868 report("Live in register not found to be live out from predecessor.",
2869 &MBB);
2870 errs() << TRI->getName(LiveInReg)
2871 << " not found to be live out from "
2872 << printMBBReference(*Pred) << "\n";
2873 }
2874 }
2875 }
2876
2877 for (auto CSInfo : MF->getCallSitesInfo())
2878 if (!CSInfo.first->isCall())
2879 report("Call site info referencing instruction that is not call", MF);
2880
2881 // If there's debug-info, check that we don't have any duplicate value
2882 // tracking numbers.
2883 if (MF->getFunction().getSubprogram()) {
2884 DenseSet<unsigned> SeenNumbers;
2885 for (const auto &MBB : *MF) {
2886 for (const auto &MI : MBB) {
2887 if (auto Num = MI.peekDebugInstrNum()) {
2888 auto Result = SeenNumbers.insert((unsigned)Num);
2889 if (!Result.second)
2890 report("Instruction has a duplicated value tracking number", &MI);
2891 }
2892 }
2893 }
2894 }
2895}
2896
2897void MachineVerifier::verifyLiveVariables() {
2898 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars")(static_cast <bool> (LiveVars && "Don't call verifyLiveVariables without LiveVars"
) ? void (0) : __assert_fail ("LiveVars && \"Don't call verifyLiveVariables without LiveVars\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2898, __extension__
__PRETTY_FUNCTION__))
;
2899 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2900 Register Reg = Register::index2VirtReg(I);
2901 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2902 for (const auto &MBB : *MF) {
2903 BBInfo &MInfo = MBBInfoMap[&MBB];
2904
2905 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2906 if (MInfo.vregsRequired.count(Reg)) {
2907 if (!VI.AliveBlocks.test(MBB.getNumber())) {
2908 report("LiveVariables: Block missing from AliveBlocks", &MBB);
2909 errs() << "Virtual register " << printReg(Reg)
2910 << " must be live through the block.\n";
2911 }
2912 } else {
2913 if (VI.AliveBlocks.test(MBB.getNumber())) {
2914 report("LiveVariables: Block should not be in AliveBlocks", &MBB);
2915 errs() << "Virtual register " << printReg(Reg)
2916 << " is not needed live through the block.\n";
2917 }
2918 }
2919 }
2920 }
2921}
2922
2923void MachineVerifier::verifyLiveIntervals() {
2924 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts")(static_cast <bool> (LiveInts && "Don't call verifyLiveIntervals without LiveInts"
) ? void (0) : __assert_fail ("LiveInts && \"Don't call verifyLiveIntervals without LiveInts\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2924, __extension__
__PRETTY_FUNCTION__))
;
2925 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2926 Register Reg = Register::index2VirtReg(I);
2927
2928 // Spilling and splitting may leave unused registers around. Skip them.
2929 if (MRI->reg_nodbg_empty(Reg))
2930 continue;
2931
2932 if (!LiveInts->hasInterval(Reg)) {
2933 report("Missing live interval for virtual register", MF);
2934 errs() << printReg(Reg, TRI) << " still has defs or uses\n";
2935 continue;
2936 }
2937
2938 const LiveInterval &LI = LiveInts->getInterval(Reg);
2939 assert(Reg == LI.reg() && "Invalid reg to interval mapping")(static_cast <bool> (Reg == LI.reg() && "Invalid reg to interval mapping"
) ? void (0) : __assert_fail ("Reg == LI.reg() && \"Invalid reg to interval mapping\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2939, __extension__
__PRETTY_FUNCTION__))
;
2940 verifyLiveInterval(LI);
2941 }
2942
2943 // Verify all the cached regunit intervals.
2944 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
2945 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
2946 verifyLiveRange(*LR, i);
2947}
2948
2949void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
2950 const VNInfo *VNI, Register Reg,
2951 LaneBitmask LaneMask) {
2952 if (VNI->isUnused())
2953 return;
2954
2955 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
2956
2957 if (!DefVNI) {
2958 report("Value not live at VNInfo def and not marked unused", MF);
2959 report_context(LR, Reg, LaneMask);
2960 report_context(*VNI);
2961 return;
2962 }
2963
2964 if (DefVNI != VNI) {
2965 report("Live segment at def has different VNInfo", MF);
2966 report_context(LR, Reg, LaneMask);
2967 report_context(*VNI);
2968 return;
2969 }
2970
2971 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
2972 if (!MBB) {
2973 report("Invalid VNInfo definition index", MF);
2974 report_context(LR, Reg, LaneMask);
2975 report_context(*VNI);
2976 return;
2977 }
2978
2979 if (VNI->isPHIDef()) {
2980 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
2981 report("PHIDef VNInfo is not defined at MBB start", MBB);
2982 report_context(LR, Reg, LaneMask);
2983 report_context(*VNI);
2984 }
2985 return;
2986 }
2987
2988 // Non-PHI def.
2989 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
2990 if (!MI) {
2991 report("No instruction at VNInfo def index", MBB);
2992 report_context(LR, Reg, LaneMask);
2993 report_context(*VNI);
2994 return;
2995 }
2996
2997 if (Reg != 0) {
2998 bool hasDef = false;
2999 bool isEarlyClobber = false;
3000 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
3001 if (!MOI->isReg() || !MOI->isDef())
3002 continue;
3003 if (Register::isVirtualRegister(Reg)) {
3004 if (MOI->getReg() != Reg)
3005 continue;
3006 } else {
3007 if (!Register::isPhysicalRegister(MOI->getReg()) ||
3008 !TRI->hasRegUnit(MOI->getReg(), Reg))
3009 continue;
3010 }
3011 if (LaneMask.any() &&
3012 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3013 continue;
3014 hasDef = true;
3015 if (MOI->isEarlyClobber())
3016 isEarlyClobber = true;
3017 }
3018
3019 if (!hasDef) {
3020 report("Defining instruction does not modify register", MI);
3021 report_context(LR, Reg, LaneMask);
3022 report_context(*VNI);
3023 }
3024
3025 // Early clobber defs begin at USE slots, but other defs must begin at
3026 // DEF slots.
3027 if (isEarlyClobber) {
3028 if (!VNI->def.isEarlyClobber()) {
3029 report("Early clobber def must be at an early-clobber slot", MBB);
3030 report_context(LR, Reg, LaneMask);
3031 report_context(*VNI);
3032 }
3033 } else if (!VNI->def.isRegister()) {
3034 report("Non-PHI, non-early clobber def must be at a register slot", MBB);
3035 report_context(LR, Reg, LaneMask);
3036 report_context(*VNI);
3037 }
3038 }
3039}
3040
3041void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
3042 const LiveRange::const_iterator I,
3043 Register Reg,
3044 LaneBitmask LaneMask) {
3045 const LiveRange::Segment &S = *I;
3046 const VNInfo *VNI = S.valno;
3047 assert(VNI && "Live segment has no valno")(static_cast <bool> (VNI && "Live segment has no valno"
) ? void (0) : __assert_fail ("VNI && \"Live segment has no valno\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 3047, __extension__
__PRETTY_FUNCTION__))
;
3048
3049 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
3050 report("Foreign valno in live segment", MF);
3051 report_context(LR, Reg, LaneMask);
3052 report_context(S);
3053 report_context(*VNI);
3054 }
3055
3056 if (VNI->isUnused()) {
3057 report("Live segment valno is marked unused", MF);
3058 report_context(LR, Reg, LaneMask);
3059 report_context(S);
3060 }
3061
3062 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
3063 if (!MBB) {
3064 report("Bad start of live segment, no basic block", MF);
3065 report_context(LR, Reg, LaneMask);
3066 report_context(S);
3067 return;
3068 }
3069 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
3070 if (S.start != MBBStartIdx && S.start != VNI->def) {
3071 report("Live segment must begin at MBB entry or valno def", MBB);
3072 report_context(LR, Reg, LaneMask);
3073 report_context(S);
3074 }
3075
3076 const MachineBasicBlock *EndMBB =
3077 LiveInts->getMBBFromIndex(S.end.getPrevSlot());
3078 if (!EndMBB) {
3079 report("Bad end of live segment, no basic block", MF);
3080 report_context(LR, Reg, LaneMask);
3081 report_context(S);
3082 return;
3083 }
3084
3085 // No more checks for live-out segments.
3086 if (S.end == LiveInts->getMBBEndIdx(EndMBB))
3087 return;
3088
3089 // RegUnit intervals are allowed dead phis.
3090 if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
3091 S.start == VNI->def && S.end == VNI->def.getDeadSlot())
3092 return;
3093
3094 // The live segment is ending inside EndMBB
3095 const MachineInstr *MI =
3096 LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
3097 if (!MI) {
3098 report("Live segment doesn't end at a valid instruction", EndMBB);
3099 report_context(LR, Reg, LaneMask);
3100 report_context(S);
3101 return;
3102 }
3103
3104 // The block slot must refer to a basic block boundary.
3105 if (S.end.isBlock()) {
3106 report("Live segment ends at B slot of an instruction", EndMBB);
3107 report_context(LR, Reg, LaneMask);
3108 report_context(S);
3109 }
3110
3111 if (S.end.isDead()) {
3112 // Segment ends on the dead slot.
3113 // That means there must be a dead def.
3114 if (!SlotIndex::isSameInstr(S.start, S.end)) {
3115 report("Live segment ending at dead slot spans instructions", EndMBB);
3116 report_context(LR, Reg, LaneMask);
3117 report_context(S);
3118 }
3119 }
3120
3121 // After tied operands are rewritten, a live segment can only end at an
3122 // early-clobber slot if it is being redefined by an early-clobber def.
3123 // TODO: Before tied operands are rewritten, a live segment can only end at an
3124 // early-clobber slot if the last use is tied to an early-clobber def.
3125 if (MF->getProperties().hasProperty(
3126 MachineFunctionProperties::Property::TiedOpsRewritten) &&
3127 S.end.isEarlyClobber()) {
3128 if (I+1 == LR.end() || (I+1)->start != S.end) {
3129 report("Live segment ending at early clobber slot must be "
3130 "redefined by an EC def in the same instruction", EndMBB);
3131 report_context(LR, Reg, LaneMask);
3132 report_context(S);
3133 }
3134 }
3135
3136 // The following checks only apply to virtual registers. Physreg liveness
3137 // is too weird to check.
3138 if (Register::isVirtualRegister(Reg)) {
3139 // A live segment can end with either a redefinition, a kill flag on a
3140 // use, or a dead flag on a def.
3141 bool hasRead = false;
3142 bool hasSubRegDef = false;
3143 bool hasDeadDef = false;
3144 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
3145 if (!MOI->isReg() || MOI->getReg() != Reg)
3146 continue;
3147 unsigned Sub = MOI->getSubReg();
3148 LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
3149 : LaneBitmask::getAll();
3150 if (MOI->isDef()) {
3151 if (Sub != 0) {
3152 hasSubRegDef = true;
3153 // An operand %0:sub0 reads %0:sub1..n. Invert the lane
3154 // mask for subregister defs. Read-undef defs will be handled by
3155 // readsReg below.
3156 SLM = ~SLM;
3157 }
3158 if (MOI->isDead())
3159 hasDeadDef = true;
3160 }
3161 if (LaneMask.any() && (LaneMask & SLM).none())
3162 continue;
3163 if (MOI->readsReg())
3164 hasRead = true;
3165 }
3166 if (S.end.isDead()) {
3167 // Make sure that the corresponding machine operand for a "dead" live
3168 // range has the dead flag. We cannot perform this check for subregister
3169 // liveranges as partially dead values are allowed.
3170 if (LaneMask.none() && !hasDeadDef) {
3171 report("Instruction ending live segment on dead slot has no dead flag",
3172 MI);
3173 report_context(LR, Reg, LaneMask);
3174 report_context(S);
3175 }
3176 } else {
3177 if (!hasRead) {
3178 // When tracking subregister liveness, the main range must start new
3179 // values on partial register writes, even if there is no read.
3180 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
3181 !hasSubRegDef) {
3182 report("Instruction ending live segment doesn't read the register",
3183 MI);
3184 report_context(LR, Reg, LaneMask);
3185 report_context(S);
3186 }
3187 }
3188 }
3189 }
3190
3191 // Now check all the basic blocks in this live segment.
3192 MachineFunction::const_iterator MFI = MBB->getIterator();
3193 // Is this live segment the beginning of a non-PHIDef VN?
3194 if (S.start == VNI->def && !VNI->isPHIDef()) {
3195 // Not live-in to any blocks.
3196 if (MBB == EndMBB)
3197 return;
3198 // Skip this block.
3199 ++MFI;
3200 }
3201
3202 SmallVector<SlotIndex, 4> Undefs;
3203 if (LaneMask.any()) {
3204 LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
3205 OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
3206 }
3207
3208 while (true) {
3209 assert(LiveInts->isLiveInToMBB(LR, &*MFI))(static_cast <bool> (LiveInts->isLiveInToMBB(LR, &
*MFI)) ? void (0) : __assert_fail ("LiveInts->isLiveInToMBB(LR, &*MFI)"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 3209, __extension__
__PRETTY_FUNCTION__))
;
3210 // We don't know how to track physregs into a landing pad.
3211 if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
3212 if (&*MFI == EndMBB)
3213 break;
3214 ++MFI;
3215 continue;
3216 }
3217
3218 // Is VNI a PHI-def in the current block?
3219 bool IsPHI = VNI->isPHIDef() &&
3220 VNI->def == LiveInts->getMBBStartIdx(&*MFI);
3221
3222 // Check that VNI is live-out of all predecessors.
3223 for (const MachineBasicBlock *Pred : MFI->predecessors()) {
3224 SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3225 // Predecessor of landing pad live-out on last call.
3226 if (MFI->isEHPad()) {
3227 for (const MachineInstr &MI : llvm::reverse(*Pred)) {
3228 if (MI.isCall()) {
3229 PEnd = Indexes->getInstructionIndex(MI).getBoundaryIndex();
3230 break;
3231 }
3232 }
3233 }
3234 const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
3235
3236 // All predecessors must have a live-out value. However for a phi
3237 // instruction with subregister intervals
3238 // only one of the subregisters (not necessarily the current one) needs to
3239 // be defined.
3240 if (!PVNI && (LaneMask.none() || !IsPHI)) {
3241 if (LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes))
3242 continue;
3243 report("Register not marked live out of predecessor", Pred);
3244 report_context(LR, Reg, LaneMask);
3245 report_context(*VNI);
3246 errs() << " live into " << printMBBReference(*MFI) << '@'
3247 << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
3248 << PEnd << '\n';
3249 continue;
3250 }
3251
3252 // Only PHI-defs can take different predecessor values.
3253 if (!IsPHI && PVNI != VNI) {
3254 report("Different value live out of predecessor", Pred);
3255 report_context(LR, Reg, LaneMask);
3256 errs() << "Valno #" << PVNI->id << " live out of "
3257 << printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
3258 << VNI->id << " live into " << printMBBReference(*MFI) << '@'
3259 << LiveInts->getMBBStartIdx(&*MFI) << '\n';
3260 }
3261 }
3262 if (&*MFI == EndMBB)
3263 break;
3264 ++MFI;
3265 }
3266}
3267
3268void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
3269 LaneBitmask LaneMask) {
3270 for (const VNInfo *VNI : LR.valnos)
3271 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3272
3273 for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
3274 verifyLiveRangeSegment(LR, I, Reg, LaneMask);
3275}
3276
3277void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
3278 Register Reg = LI.reg();
3279 assert(Register::isVirtualRegister(Reg))(static_cast <bool> (Register::isVirtualRegister(Reg)) ?
void (0) : __assert_fail ("Register::isVirtualRegister(Reg)"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 3279, __extension__
__PRETTY_FUNCTION__))
;
3280 verifyLiveRange(LI, Reg);
3281
3282 LaneBitmask Mask;
3283 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
3284 for (const LiveInterval::SubRange &SR : LI.subranges()) {
3285 if ((Mask & SR.LaneMask).any()) {
3286 report("Lane masks of sub ranges overlap in live interval", MF);
3287 report_context(LI);
3288 }
3289 if ((SR.LaneMask & ~MaxMask).any()) {
3290 report("Subrange lanemask is invalid", MF);
3291 report_context(LI);
3292 }
3293 if (SR.empty()) {
3294 report("Subrange must not be empty", MF);
3295 report_context(SR, LI.reg(), SR.LaneMask);
3296 }
3297 Mask |= SR.LaneMask;
3298 verifyLiveRange(SR, LI.reg(), SR.LaneMask);
3299 if (!LI.covers(SR)) {
3300 report("A Subrange is not covered by the main range", MF);
3301 report_context(LI);
3302 }
3303 }
3304
3305 // Check the LI only has one connected component.
3306 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
3307 unsigned NumComp = ConEQ.Classify(LI);
3308 if (NumComp > 1) {
3309 report("Multiple connected components in live interval", MF);
3310 report_context(LI);
3311 for (unsigned comp = 0; comp != NumComp; ++comp) {
3312 errs() << comp << ": valnos";
3313 for (const VNInfo *I : LI.valnos)
3314 if (comp == ConEQ.getEqClass(I))
3315 errs() << ' ' << I->id;
3316 errs() << '\n';
3317 }
3318 }
3319}
3320
3321namespace {
3322
3323 // FrameSetup and FrameDestroy can have zero adjustment, so using a single
3324 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
3325 // value is zero.
3326 // We use a bool plus an integer to capture the stack state.
3327 struct StackStateOfBB {
3328 StackStateOfBB() = default;
3329 StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
3330 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3331 ExitIsSetup(ExitSetup) {}
3332
3333 // Can be negative, which means we are setting up a frame.
3334 int EntryValue = 0;
3335 int ExitValue = 0;
3336 bool EntryIsSetup = false;
3337 bool ExitIsSetup = false;
3338 };
3339
3340} // end anonymous namespace
3341
3342/// Make sure on every path through the CFG, a FrameSetup <n> is always followed
3343/// by a FrameDestroy <n>, stack adjustments are identical on all
3344/// CFG edges to a merge point, and frame is destroyed at end of a return block.
3345void MachineVerifier::verifyStackFrame() {
3346 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
3347 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
3348 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3349 return;
3350
3351 SmallVector<StackStateOfBB, 8> SPState;
3352 SPState.resize(MF->getNumBlockIDs());
3353 df_iterator_default_set<const MachineBasicBlock*> Reachable;
3354
3355 // Visit the MBBs in DFS order.
3356 for (df_ext_iterator<const MachineFunction *,
3357 df_iterator_default_set<const MachineBasicBlock *>>
3358 DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
3359 DFI != DFE; ++DFI) {
3360 const MachineBasicBlock *MBB = *DFI;
3361
3362 StackStateOfBB BBState;
3363 // Check the exit state of the DFS stack predecessor.
3364 if (DFI.getPathLength() >= 2) {
3365 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
3366 assert(Reachable.count(StackPred) &&(static_cast <bool> (Reachable.count(StackPred) &&
"DFS stack predecessor is already visited.\n") ? void (0) : __assert_fail
("Reachable.count(StackPred) && \"DFS stack predecessor is already visited.\\n\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 3367, __extension__
__PRETTY_FUNCTION__))
3367 "DFS stack predecessor is already visited.\n")(static_cast <bool> (Reachable.count(StackPred) &&
"DFS stack predecessor is already visited.\n") ? void (0) : __assert_fail
("Reachable.count(StackPred) && \"DFS stack predecessor is already visited.\\n\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 3367, __extension__
__PRETTY_FUNCTION__))
;
3368 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
3369 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
3370 BBState.ExitValue = BBState.EntryValue;
3371 BBState.ExitIsSetup = BBState.EntryIsSetup;
3372 }
3373
3374 // Update stack state by checking contents of MBB.
3375 for (const auto &I : *MBB) {
3376 if (I.getOpcode() == FrameSetupOpcode) {
3377 if (BBState.ExitIsSetup)
3378 report("FrameSetup is after another FrameSetup", &I);
3379 BBState.ExitValue -= TII->getFrameTotalSize(I);
3380 BBState.ExitIsSetup = true;
3381 }
3382
3383 if (I.getOpcode() == FrameDestroyOpcode) {
3384 int Size = TII->getFrameTotalSize(I);
3385 if (!BBState.ExitIsSetup)
3386 report("FrameDestroy is not after a FrameSetup", &I);
3387 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3388 BBState.ExitValue;
3389 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
3390 report("FrameDestroy <n> is after FrameSetup <m>", &I);
3391 errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
3392 << AbsSPAdj << ">.\n";
3393 }
3394 BBState.ExitValue += Size;
3395 BBState.ExitIsSetup = false;
3396 }
3397 }
3398 SPState[MBB->getNumber()] = BBState;
3399
3400 // Make sure the exit state of any predecessor is consistent with the entry
3401 // state.
3402 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3403 if (Reachable.count(Pred) &&
3404 (SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
3405 SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3406 report("The exit stack state of a predecessor is inconsistent.", MBB);
3407 errs() << "Predecessor " << printMBBReference(*Pred)
3408 << " has exit state (" << SPState[Pred->getNumber()].ExitValue
3409 << ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
3410 << printMBBReference(*MBB) << " has entry state ("
3411 << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
3412 }
3413 }
3414
3415 // Make sure the entry state of any successor is consistent with the exit
3416 // state.
3417 for (const MachineBasicBlock *Succ : MBB->successors()) {
3418 if (Reachable.count(Succ) &&
3419 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3420 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3421 report("The entry stack state of a successor is inconsistent.", MBB);
3422 errs() << "Successor " << printMBBReference(*Succ)
3423 << " has entry state (" << SPState[Succ->getNumber()].EntryValue
3424 << ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
3425 << printMBBReference(*MBB) << " has exit state ("
3426 << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
3427 }
3428 }
3429
3430 // Make sure a basic block with return ends with zero stack adjustment.
3431 if (!MBB->empty() && MBB->back().isReturn()) {
3432 if (BBState.ExitIsSetup)
3433 report("A return block ends with a FrameSetup.", MBB);
3434 if (BBState.ExitValue)
3435 report("A return block ends with a nonzero stack adjustment.", MBB);
3436 }
3437 }
3438}