Bug Summary

File:llvm/lib/CodeGen/MachineVerifier.cpp
Warning:line 2367, column 9
Forming reference to null pointer

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name MachineVerifier.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/CodeGen -I /build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/lib/CodeGen -I include -I /build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm=build-llvm -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm=build-llvm -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm=build-llvm -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/= -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-01-19-134126-35450-1 -x c++ /build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/lib/CodeGen/MachineVerifier.cpp

/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/lib/CodeGen/MachineVerifier.cpp

1//===- MachineVerifier.cpp - Machine Code Verifier ------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Pass to verify generated machine code. The following is checked:
10//
11// Operand counts: All explicit operands must be present.
12//
13// Register classes: All physical and virtual register operands must be
14// compatible with the register class required by the instruction descriptor.
15//
16// Register live intervals: Registers must be defined only once, and must be
17// defined before use.
18//
19// The machine code verifier is enabled with the command-line option
20// -verify-machineinstrs.
21//===----------------------------------------------------------------------===//
22
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/DenseMap.h"
25#include "llvm/ADT/DenseSet.h"
26#include "llvm/ADT/DepthFirstIterator.h"
27#include "llvm/ADT/PostOrderIterator.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/ADT/SetOperations.h"
30#include "llvm/ADT/SmallPtrSet.h"
31#include "llvm/ADT/SmallVector.h"
32#include "llvm/ADT/StringRef.h"
33#include "llvm/ADT/Twine.h"
34#include "llvm/Analysis/EHPersonalities.h"
35#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
36#include "llvm/CodeGen/LiveInterval.h"
37#include "llvm/CodeGen/LiveIntervalCalc.h"
38#include "llvm/CodeGen/LiveIntervals.h"
39#include "llvm/CodeGen/LiveStacks.h"
40#include "llvm/CodeGen/LiveVariables.h"
41#include "llvm/CodeGen/MachineBasicBlock.h"
42#include "llvm/CodeGen/MachineFrameInfo.h"
43#include "llvm/CodeGen/MachineFunction.h"
44#include "llvm/CodeGen/MachineFunctionPass.h"
45#include "llvm/CodeGen/MachineInstr.h"
46#include "llvm/CodeGen/MachineInstrBundle.h"
47#include "llvm/CodeGen/MachineMemOperand.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/PseudoSourceValue.h"
51#include "llvm/CodeGen/SlotIndexes.h"
52#include "llvm/CodeGen/StackMaps.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetOpcodes.h"
55#include "llvm/CodeGen/TargetRegisterInfo.h"
56#include "llvm/CodeGen/TargetSubtargetInfo.h"
57#include "llvm/IR/BasicBlock.h"
58#include "llvm/IR/Function.h"
59#include "llvm/IR/InlineAsm.h"
60#include "llvm/IR/Instructions.h"
61#include "llvm/InitializePasses.h"
62#include "llvm/MC/LaneBitmask.h"
63#include "llvm/MC/MCAsmInfo.h"
64#include "llvm/MC/MCInstrDesc.h"
65#include "llvm/MC/MCRegisterInfo.h"
66#include "llvm/MC/MCTargetOptions.h"
67#include "llvm/Pass.h"
68#include "llvm/Support/Casting.h"
69#include "llvm/Support/ErrorHandling.h"
70#include "llvm/Support/LowLevelTypeImpl.h"
71#include "llvm/Support/MathExtras.h"
72#include "llvm/Support/raw_ostream.h"
73#include "llvm/Target/TargetMachine.h"
74#include <algorithm>
75#include <cassert>
76#include <cstddef>
77#include <cstdint>
78#include <iterator>
79#include <string>
80#include <utility>
81
82using namespace llvm;
83
84namespace {
85
86 struct MachineVerifier {
87 MachineVerifier(Pass *pass, const char *b) : PASS(pass), Banner(b) {}
88
89 unsigned verify(const MachineFunction &MF);
90
91 Pass *const PASS;
92 const char *Banner;
93 const MachineFunction *MF;
94 const TargetMachine *TM;
95 const TargetInstrInfo *TII;
96 const TargetRegisterInfo *TRI;
97 const MachineRegisterInfo *MRI;
98
99 unsigned foundErrors;
100
101 // Avoid querying the MachineFunctionProperties for each operand.
102 bool isFunctionRegBankSelected;
103 bool isFunctionSelected;
104 bool isFunctionTracksDebugUserValues;
105
106 using RegVector = SmallVector<Register, 16>;
107 using RegMaskVector = SmallVector<const uint32_t *, 4>;
108 using RegSet = DenseSet<Register>;
109 using RegMap = DenseMap<Register, const MachineInstr *>;
110 using BlockSet = SmallPtrSet<const MachineBasicBlock *, 8>;
111
112 const MachineInstr *FirstNonPHI;
113 const MachineInstr *FirstTerminator;
114 BlockSet FunctionBlocks;
115
116 BitVector regsReserved;
117 RegSet regsLive;
118 RegVector regsDefined, regsDead, regsKilled;
119 RegMaskVector regMasks;
120
121 SlotIndex lastIndex;
122
123 // Add Reg and any sub-registers to RV
124 void addRegWithSubRegs(RegVector &RV, Register Reg) {
125 RV.push_back(Reg);
25
Value assigned to field 'LiveInts', which participates in a condition later
126 if (Reg.isPhysical())
26
Taking false branch
27
Taking false branch
127 append_range(RV, TRI->subregs(Reg.asMCReg()));
128 }
129
130 struct BBInfo {
131 // Is this MBB reachable from the MF entry point?
132 bool reachable = false;
133
134 // Vregs that must be live in because they are used without being
135 // defined. Map value is the user. vregsLiveIn doesn't include regs
136 // that only are used by PHI nodes.
137 RegMap vregsLiveIn;
138
139 // Regs killed in MBB. They may be defined again, and will then be in both
140 // regsKilled and regsLiveOut.
141 RegSet regsKilled;
142
143 // Regs defined in MBB and live out. Note that vregs passing through may
144 // be live out without being mentioned here.
145 RegSet regsLiveOut;
146
147 // Vregs that pass through MBB untouched. This set is disjoint from
148 // regsKilled and regsLiveOut.
149 RegSet vregsPassed;
150
151 // Vregs that must pass through MBB because they are needed by a successor
152 // block. This set is disjoint from regsLiveOut.
153 RegSet vregsRequired;
154
155 // Set versions of block's predecessor and successor lists.
156 BlockSet Preds, Succs;
157
158 BBInfo() = default;
159
160 // Add register to vregsRequired if it belongs there. Return true if
161 // anything changed.
162 bool addRequired(Register Reg) {
163 if (!Reg.isVirtual())
164 return false;
165 if (regsLiveOut.count(Reg))
166 return false;
167 return vregsRequired.insert(Reg).second;
168 }
169
170 // Same for a full set.
171 bool addRequired(const RegSet &RS) {
172 bool Changed = false;
173 for (Register Reg : RS)
174 Changed |= addRequired(Reg);
175 return Changed;
176 }
177
178 // Same for a full map.
179 bool addRequired(const RegMap &RM) {
180 bool Changed = false;
181 for (const auto &I : RM)
182 Changed |= addRequired(I.first);
183 return Changed;
184 }
185
186 // Live-out registers are either in regsLiveOut or vregsPassed.
187 bool isLiveOut(Register Reg) const {
188 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
189 }
190 };
191
192 // Extra register info per MBB.
193 DenseMap<const MachineBasicBlock*, BBInfo> MBBInfoMap;
194
195 bool isReserved(Register Reg) {
196 return Reg.id() < regsReserved.size() && regsReserved.test(Reg.id());
197 }
198
199 bool isAllocatable(Register Reg) const {
200 return Reg.id() < TRI->getNumRegs() && TRI->isInAllocatableClass(Reg) &&
201 !regsReserved.test(Reg.id());
202 }
203
204 // Analysis information if available
205 LiveVariables *LiveVars;
206 LiveIntervals *LiveInts;
207 LiveStacks *LiveStks;
208 SlotIndexes *Indexes;
209
210 void visitMachineFunctionBefore();
211 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
212 void visitMachineBundleBefore(const MachineInstr *MI);
213
214 /// Verify that all of \p MI's virtual register operands are scalars.
215 /// \returns True if all virtual register operands are scalar. False
216 /// otherwise.
217 bool verifyAllRegOpsScalar(const MachineInstr &MI,
218 const MachineRegisterInfo &MRI);
219 bool verifyVectorElementMatch(LLT Ty0, LLT Ty1, const MachineInstr *MI);
220 void verifyPreISelGenericInstruction(const MachineInstr *MI);
221 void visitMachineInstrBefore(const MachineInstr *MI);
222 void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
223 void visitMachineBundleAfter(const MachineInstr *MI);
224 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
225 void visitMachineFunctionAfter();
226
227 void report(const char *msg, const MachineFunction *MF);
228 void report(const char *msg, const MachineBasicBlock *MBB);
229 void report(const char *msg, const MachineInstr *MI);
230 void report(const char *msg, const MachineOperand *MO, unsigned MONum,
231 LLT MOVRegType = LLT{});
232 void report(const Twine &Msg, const MachineInstr *MI);
233
234 void report_context(const LiveInterval &LI) const;
235 void report_context(const LiveRange &LR, Register VRegUnit,
236 LaneBitmask LaneMask) const;
237 void report_context(const LiveRange::Segment &S) const;
238 void report_context(const VNInfo &VNI) const;
239 void report_context(SlotIndex Pos) const;
240 void report_context(MCPhysReg PhysReg) const;
241 void report_context_liverange(const LiveRange &LR) const;
242 void report_context_lanemask(LaneBitmask LaneMask) const;
243 void report_context_vreg(Register VReg) const;
244 void report_context_vreg_regunit(Register VRegOrUnit) const;
245
246 void verifyInlineAsm(const MachineInstr *MI);
247
248 void checkLiveness(const MachineOperand *MO, unsigned MONum);
249 void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
250 SlotIndex UseIdx, const LiveRange &LR,
251 Register VRegOrUnit,
252 LaneBitmask LaneMask = LaneBitmask::getNone());
253 void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
254 SlotIndex DefIdx, const LiveRange &LR,
255 Register VRegOrUnit, bool SubRangeCheck = false,
256 LaneBitmask LaneMask = LaneBitmask::getNone());
257
258 void markReachable(const MachineBasicBlock *MBB);
259 void calcRegsPassed();
260 void checkPHIOps(const MachineBasicBlock &MBB);
261
262 void calcRegsRequired();
263 void verifyLiveVariables();
264 void verifyLiveIntervals();
265 void verifyLiveInterval(const LiveInterval&);
266 void verifyLiveRangeValue(const LiveRange &, const VNInfo *, Register,
267 LaneBitmask);
268 void verifyLiveRangeSegment(const LiveRange &,
269 const LiveRange::const_iterator I, Register,
270 LaneBitmask);
271 void verifyLiveRange(const LiveRange &, Register,
272 LaneBitmask LaneMask = LaneBitmask::getNone());
273
274 void verifyStackFrame();
275
276 void verifySlotIndexes() const;
277 void verifyProperties(const MachineFunction &MF);
278 };
279
280 struct MachineVerifierPass : public MachineFunctionPass {
281 static char ID; // Pass ID, replacement for typeid
282
283 const std::string Banner;
284
285 MachineVerifierPass(std::string banner = std::string())
286 : MachineFunctionPass(ID), Banner(std::move(banner)) {
287 initializeMachineVerifierPassPass(*PassRegistry::getPassRegistry());
288 }
289
290 void getAnalysisUsage(AnalysisUsage &AU) const override {
291 AU.setPreservesAll();
292 MachineFunctionPass::getAnalysisUsage(AU);
293 }
294
295 bool runOnMachineFunction(MachineFunction &MF) override {
296 // Skip functions that have known verification problems.
297 // FIXME: Remove this mechanism when all problematic passes have been
298 // fixed.
299 if (MF.getProperties().hasProperty(
300 MachineFunctionProperties::Property::FailsVerification))
301 return false;
302
303 unsigned FoundErrors = MachineVerifier(this, Banner.c_str()).verify(MF);
304 if (FoundErrors)
305 report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
306 return false;
307 }
308 };
309
310} // end anonymous namespace
311
312char MachineVerifierPass::ID = 0;
313
314INITIALIZE_PASS(MachineVerifierPass, "machineverifier",static void *initializeMachineVerifierPassPassOnce(PassRegistry
&Registry) { PassInfo *PI = new PassInfo( "Verify generated machine code"
, "machineverifier", &MachineVerifierPass::ID, PassInfo::
NormalCtor_t(callDefaultCtor<MachineVerifierPass>), false
, false); Registry.registerPass(*PI, true); return PI; } static
llvm::once_flag InitializeMachineVerifierPassPassFlag; void llvm
::initializeMachineVerifierPassPass(PassRegistry &Registry
) { llvm::call_once(InitializeMachineVerifierPassPassFlag, initializeMachineVerifierPassPassOnce
, std::ref(Registry)); }
315 "Verify generated machine code", false, false)static void *initializeMachineVerifierPassPassOnce(PassRegistry
&Registry) { PassInfo *PI = new PassInfo( "Verify generated machine code"
, "machineverifier", &MachineVerifierPass::ID, PassInfo::
NormalCtor_t(callDefaultCtor<MachineVerifierPass>), false
, false); Registry.registerPass(*PI, true); return PI; } static
llvm::once_flag InitializeMachineVerifierPassPassFlag; void llvm
::initializeMachineVerifierPassPass(PassRegistry &Registry
) { llvm::call_once(InitializeMachineVerifierPassPassFlag, initializeMachineVerifierPassPassOnce
, std::ref(Registry)); }
316
317FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) {
318 return new MachineVerifierPass(Banner);
319}
320
321void llvm::verifyMachineFunction(MachineFunctionAnalysisManager *,
322 const std::string &Banner,
323 const MachineFunction &MF) {
324 // TODO: Use MFAM after porting below analyses.
325 // LiveVariables *LiveVars;
326 // LiveIntervals *LiveInts;
327 // LiveStacks *LiveStks;
328 // SlotIndexes *Indexes;
329 unsigned FoundErrors = MachineVerifier(nullptr, Banner.c_str()).verify(MF);
330 if (FoundErrors)
331 report_fatal_error("Found " + Twine(FoundErrors) + " machine code errors.");
332}
333
334bool MachineFunction::verify(Pass *p, const char *Banner, bool AbortOnErrors)
335 const {
336 MachineFunction &MF = const_cast<MachineFunction&>(*this);
337 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
338 if (AbortOnErrors && FoundErrors)
339 report_fatal_error("Found "+Twine(FoundErrors)+" machine code errors.");
340 return FoundErrors == 0;
341}
342
343void MachineVerifier::verifySlotIndexes() const {
344 if (Indexes == nullptr)
345 return;
346
347 // Ensure the IdxMBB list is sorted by slot indexes.
348 SlotIndex Last;
349 for (SlotIndexes::MBBIndexIterator I = Indexes->MBBIndexBegin(),
350 E = Indexes->MBBIndexEnd(); I != E; ++I) {
351 assert(!Last.isValid() || I->first > Last)(static_cast <bool> (!Last.isValid() || I->first >
Last) ? void (0) : __assert_fail ("!Last.isValid() || I->first > Last"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 351, __extension__ __PRETTY_FUNCTION__
))
;
352 Last = I->first;
353 }
354}
355
356void MachineVerifier::verifyProperties(const MachineFunction &MF) {
357 // If a pass has introduced virtual registers without clearing the
358 // NoVRegs property (or set it without allocating the vregs)
359 // then report an error.
360 if (MF.getProperties().hasProperty(
361 MachineFunctionProperties::Property::NoVRegs) &&
362 MRI->getNumVirtRegs())
363 report("Function has NoVRegs property but there are VReg operands", &MF);
364}
365
366unsigned MachineVerifier::verify(const MachineFunction &MF) {
367 foundErrors = 0;
368
369 this->MF = &MF;
370 TM = &MF.getTarget();
371 TII = MF.getSubtarget().getInstrInfo();
372 TRI = MF.getSubtarget().getRegisterInfo();
373 MRI = &MF.getRegInfo();
374
375 const bool isFunctionFailedISel = MF.getProperties().hasProperty(
376 MachineFunctionProperties::Property::FailedISel);
377
378 // If we're mid-GlobalISel and we already triggered the fallback path then
379 // it's expected that the MIR is somewhat broken but that's ok since we'll
380 // reset it and clear the FailedISel attribute in ResetMachineFunctions.
381 if (isFunctionFailedISel)
382 return foundErrors;
383
384 isFunctionRegBankSelected = MF.getProperties().hasProperty(
385 MachineFunctionProperties::Property::RegBankSelected);
386 isFunctionSelected = MF.getProperties().hasProperty(
387 MachineFunctionProperties::Property::Selected);
388 isFunctionTracksDebugUserValues = MF.getProperties().hasProperty(
389 MachineFunctionProperties::Property::TracksDebugUserValues);
390
391 LiveVars = nullptr;
392 LiveInts = nullptr;
393 LiveStks = nullptr;
394 Indexes = nullptr;
395 if (PASS) {
396 LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
397 // We don't want to verify LiveVariables if LiveIntervals is available.
398 if (!LiveInts)
399 LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
400 LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
401 Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
402 }
403
404 verifySlotIndexes();
405
406 verifyProperties(MF);
407
408 visitMachineFunctionBefore();
409 for (const MachineBasicBlock &MBB : MF) {
410 visitMachineBasicBlockBefore(&MBB);
411 // Keep track of the current bundle header.
412 const MachineInstr *CurBundle = nullptr;
413 // Do we expect the next instruction to be part of the same bundle?
414 bool InBundle = false;
415
416 for (const MachineInstr &MI : MBB.instrs()) {
417 if (MI.getParent() != &MBB) {
418 report("Bad instruction parent pointer", &MBB);
419 errs() << "Instruction: " << MI;
420 continue;
421 }
422
423 // Check for consistent bundle flags.
424 if (InBundle && !MI.isBundledWithPred())
425 report("Missing BundledPred flag, "
426 "BundledSucc was set on predecessor",
427 &MI);
428 if (!InBundle && MI.isBundledWithPred())
429 report("BundledPred flag is set, "
430 "but BundledSucc not set on predecessor",
431 &MI);
432
433 // Is this a bundle header?
434 if (!MI.isInsideBundle()) {
435 if (CurBundle)
436 visitMachineBundleAfter(CurBundle);
437 CurBundle = &MI;
438 visitMachineBundleBefore(CurBundle);
439 } else if (!CurBundle)
440 report("No bundle header", &MI);
441 visitMachineInstrBefore(&MI);
442 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
443 const MachineOperand &Op = MI.getOperand(I);
444 if (Op.getParent() != &MI) {
445 // Make sure to use correct addOperand / RemoveOperand / ChangeTo
446 // functions when replacing operands of a MachineInstr.
447 report("Instruction has operand with wrong parent set", &MI);
448 }
449
450 visitMachineOperand(&Op, I);
451 }
452
453 // Was this the last bundled instruction?
454 InBundle = MI.isBundledWithSucc();
455 }
456 if (CurBundle)
457 visitMachineBundleAfter(CurBundle);
458 if (InBundle)
459 report("BundledSucc flag set on last instruction in block", &MBB.back());
460 visitMachineBasicBlockAfter(&MBB);
461 }
462 visitMachineFunctionAfter();
463
464 // Clean up.
465 regsLive.clear();
466 regsDefined.clear();
467 regsDead.clear();
468 regsKilled.clear();
469 regMasks.clear();
470 MBBInfoMap.clear();
471
472 return foundErrors;
473}
474
475void MachineVerifier::report(const char *msg, const MachineFunction *MF) {
476 assert(MF)(static_cast <bool> (MF) ? void (0) : __assert_fail ("MF"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 476, __extension__ __PRETTY_FUNCTION__
))
;
477 errs() << '\n';
478 if (!foundErrors++) {
479 if (Banner)
480 errs() << "# " << Banner << '\n';
481 if (LiveInts != nullptr)
482 LiveInts->print(errs());
483 else
484 MF->print(errs(), Indexes);
485 }
486 errs() << "*** Bad machine code: " << msg << " ***\n"
487 << "- function: " << MF->getName() << "\n";
488}
489
490void MachineVerifier::report(const char *msg, const MachineBasicBlock *MBB) {
491 assert(MBB)(static_cast <bool> (MBB) ? void (0) : __assert_fail ("MBB"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 491, __extension__ __PRETTY_FUNCTION__
))
;
492 report(msg, MBB->getParent());
493 errs() << "- basic block: " << printMBBReference(*MBB) << ' '
494 << MBB->getName() << " (" << (const void *)MBB << ')';
495 if (Indexes)
496 errs() << " [" << Indexes->getMBBStartIdx(MBB)
497 << ';' << Indexes->getMBBEndIdx(MBB) << ')';
498 errs() << '\n';
499}
500
501void MachineVerifier::report(const char *msg, const MachineInstr *MI) {
502 assert(MI)(static_cast <bool> (MI) ? void (0) : __assert_fail ("MI"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 502, __extension__ __PRETTY_FUNCTION__
))
;
503 report(msg, MI->getParent());
504 errs() << "- instruction: ";
505 if (Indexes && Indexes->hasIndex(*MI))
506 errs() << Indexes->getInstructionIndex(*MI) << '\t';
507 MI->print(errs(), /*IsStandalone=*/true);
508}
509
510void MachineVerifier::report(const char *msg, const MachineOperand *MO,
511 unsigned MONum, LLT MOVRegType) {
512 assert(MO)(static_cast <bool> (MO) ? void (0) : __assert_fail ("MO"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 512, __extension__ __PRETTY_FUNCTION__
))
;
513 report(msg, MO->getParent());
514 errs() << "- operand " << MONum << ": ";
515 MO->print(errs(), MOVRegType, TRI);
516 errs() << "\n";
517}
518
519void MachineVerifier::report(const Twine &Msg, const MachineInstr *MI) {
520 report(Msg.str().c_str(), MI);
521}
522
523void MachineVerifier::report_context(SlotIndex Pos) const {
524 errs() << "- at: " << Pos << '\n';
525}
526
527void MachineVerifier::report_context(const LiveInterval &LI) const {
528 errs() << "- interval: " << LI << '\n';
529}
530
531void MachineVerifier::report_context(const LiveRange &LR, Register VRegUnit,
532 LaneBitmask LaneMask) const {
533 report_context_liverange(LR);
534 report_context_vreg_regunit(VRegUnit);
535 if (LaneMask.any())
536 report_context_lanemask(LaneMask);
537}
538
539void MachineVerifier::report_context(const LiveRange::Segment &S) const {
540 errs() << "- segment: " << S << '\n';
541}
542
543void MachineVerifier::report_context(const VNInfo &VNI) const {
544 errs() << "- ValNo: " << VNI.id << " (def " << VNI.def << ")\n";
545}
546
547void MachineVerifier::report_context_liverange(const LiveRange &LR) const {
548 errs() << "- liverange: " << LR << '\n';
549}
550
551void MachineVerifier::report_context(MCPhysReg PReg) const {
552 errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
553}
554
555void MachineVerifier::report_context_vreg(Register VReg) const {
556 errs() << "- v. register: " << printReg(VReg, TRI) << '\n';
557}
558
559void MachineVerifier::report_context_vreg_regunit(Register VRegOrUnit) const {
560 if (Register::isVirtualRegister(VRegOrUnit)) {
561 report_context_vreg(VRegOrUnit);
562 } else {
563 errs() << "- regunit: " << printRegUnit(VRegOrUnit, TRI) << '\n';
564 }
565}
566
567void MachineVerifier::report_context_lanemask(LaneBitmask LaneMask) const {
568 errs() << "- lanemask: " << PrintLaneMask(LaneMask) << '\n';
569}
570
571void MachineVerifier::markReachable(const MachineBasicBlock *MBB) {
572 BBInfo &MInfo = MBBInfoMap[MBB];
573 if (!MInfo.reachable) {
574 MInfo.reachable = true;
575 for (const MachineBasicBlock *Succ : MBB->successors())
576 markReachable(Succ);
577 }
578}
579
580void MachineVerifier::visitMachineFunctionBefore() {
581 lastIndex = SlotIndex();
582 regsReserved = MRI->reservedRegsFrozen() ? MRI->getReservedRegs()
583 : TRI->getReservedRegs(*MF);
584
585 if (!MF->empty())
586 markReachable(&MF->front());
587
588 // Build a set of the basic blocks in the function.
589 FunctionBlocks.clear();
590 for (const auto &MBB : *MF) {
591 FunctionBlocks.insert(&MBB);
592 BBInfo &MInfo = MBBInfoMap[&MBB];
593
594 MInfo.Preds.insert(MBB.pred_begin(), MBB.pred_end());
595 if (MInfo.Preds.size() != MBB.pred_size())
596 report("MBB has duplicate entries in its predecessor list.", &MBB);
597
598 MInfo.Succs.insert(MBB.succ_begin(), MBB.succ_end());
599 if (MInfo.Succs.size() != MBB.succ_size())
600 report("MBB has duplicate entries in its successor list.", &MBB);
601 }
602
603 // Check that the register use lists are sane.
604 MRI->verifyUseLists();
605
606 if (!MF->empty())
607 verifyStackFrame();
608}
609
610void
611MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
612 FirstTerminator = nullptr;
613 FirstNonPHI = nullptr;
614
615 if (!MF->getProperties().hasProperty(
616 MachineFunctionProperties::Property::NoPHIs) && MRI->tracksLiveness()) {
617 // If this block has allocatable physical registers live-in, check that
618 // it is an entry block or landing pad.
619 for (const auto &LI : MBB->liveins()) {
620 if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
621 MBB->getIterator() != MBB->getParent()->begin()) {
622 report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
623 report_context(LI.PhysReg);
624 }
625 }
626 }
627
628 // Count the number of landing pad successors.
629 SmallPtrSet<const MachineBasicBlock*, 4> LandingPadSuccs;
630 for (const auto *succ : MBB->successors()) {
631 if (succ->isEHPad())
632 LandingPadSuccs.insert(succ);
633 if (!FunctionBlocks.count(succ))
634 report("MBB has successor that isn't part of the function.", MBB);
635 if (!MBBInfoMap[succ].Preds.count(MBB)) {
636 report("Inconsistent CFG", MBB);
637 errs() << "MBB is not in the predecessor list of the successor "
638 << printMBBReference(*succ) << ".\n";
639 }
640 }
641
642 // Check the predecessor list.
643 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
644 if (!FunctionBlocks.count(Pred))
645 report("MBB has predecessor that isn't part of the function.", MBB);
646 if (!MBBInfoMap[Pred].Succs.count(MBB)) {
647 report("Inconsistent CFG", MBB);
648 errs() << "MBB is not in the successor list of the predecessor "
649 << printMBBReference(*Pred) << ".\n";
650 }
651 }
652
653 const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
654 const BasicBlock *BB = MBB->getBasicBlock();
655 const Function &F = MF->getFunction();
656 if (LandingPadSuccs.size() > 1 &&
657 !(AsmInfo &&
658 AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
659 BB && isa<SwitchInst>(BB->getTerminator())) &&
660 !isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
661 report("MBB has more than one landing pad successor", MBB);
662
663 // Call analyzeBranch. If it succeeds, there several more conditions to check.
664 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
665 SmallVector<MachineOperand, 4> Cond;
666 if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
667 Cond)) {
668 // Ok, analyzeBranch thinks it knows what's going on with this block. Let's
669 // check whether its answers match up with reality.
670 if (!TBB && !FBB) {
671 // Block falls through to its successor.
672 if (!MBB->empty() && MBB->back().isBarrier() &&
673 !TII->isPredicated(MBB->back())) {
674 report("MBB exits via unconditional fall-through but ends with a "
675 "barrier instruction!", MBB);
676 }
677 if (!Cond.empty()) {
678 report("MBB exits via unconditional fall-through but has a condition!",
679 MBB);
680 }
681 } else if (TBB && !FBB && Cond.empty()) {
682 // Block unconditionally branches somewhere.
683 if (MBB->empty()) {
684 report("MBB exits via unconditional branch but doesn't contain "
685 "any instructions!", MBB);
686 } else if (!MBB->back().isBarrier()) {
687 report("MBB exits via unconditional branch but doesn't end with a "
688 "barrier instruction!", MBB);
689 } else if (!MBB->back().isTerminator()) {
690 report("MBB exits via unconditional branch but the branch isn't a "
691 "terminator instruction!", MBB);
692 }
693 } else if (TBB && !FBB && !Cond.empty()) {
694 // Block conditionally branches somewhere, otherwise falls through.
695 if (MBB->empty()) {
696 report("MBB exits via conditional branch/fall-through but doesn't "
697 "contain any instructions!", MBB);
698 } else if (MBB->back().isBarrier()) {
699 report("MBB exits via conditional branch/fall-through but ends with a "
700 "barrier instruction!", MBB);
701 } else if (!MBB->back().isTerminator()) {
702 report("MBB exits via conditional branch/fall-through but the branch "
703 "isn't a terminator instruction!", MBB);
704 }
705 } else if (TBB && FBB) {
706 // Block conditionally branches somewhere, otherwise branches
707 // somewhere else.
708 if (MBB->empty()) {
709 report("MBB exits via conditional branch/branch but doesn't "
710 "contain any instructions!", MBB);
711 } else if (!MBB->back().isBarrier()) {
712 report("MBB exits via conditional branch/branch but doesn't end with a "
713 "barrier instruction!", MBB);
714 } else if (!MBB->back().isTerminator()) {
715 report("MBB exits via conditional branch/branch but the branch "
716 "isn't a terminator instruction!", MBB);
717 }
718 if (Cond.empty()) {
719 report("MBB exits via conditional branch/branch but there's no "
720 "condition!", MBB);
721 }
722 } else {
723 report("analyzeBranch returned invalid data!", MBB);
724 }
725
726 // Now check that the successors match up with the answers reported by
727 // analyzeBranch.
728 if (TBB && !MBB->isSuccessor(TBB))
729 report("MBB exits via jump or conditional branch, but its target isn't a "
730 "CFG successor!",
731 MBB);
732 if (FBB && !MBB->isSuccessor(FBB))
733 report("MBB exits via conditional branch, but its target isn't a CFG "
734 "successor!",
735 MBB);
736
737 // There might be a fallthrough to the next block if there's either no
738 // unconditional true branch, or if there's a condition, and one of the
739 // branches is missing.
740 bool Fallthrough = !TBB || (!Cond.empty() && !FBB);
741
742 // A conditional fallthrough must be an actual CFG successor, not
743 // unreachable. (Conversely, an unconditional fallthrough might not really
744 // be a successor, because the block might end in unreachable.)
745 if (!Cond.empty() && !FBB) {
746 MachineFunction::const_iterator MBBI = std::next(MBB->getIterator());
747 if (MBBI == MF->end()) {
748 report("MBB conditionally falls through out of function!", MBB);
749 } else if (!MBB->isSuccessor(&*MBBI))
750 report("MBB exits via conditional branch/fall-through but the CFG "
751 "successors don't match the actual successors!",
752 MBB);
753 }
754
755 // Verify that there aren't any extra un-accounted-for successors.
756 for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
757 // If this successor is one of the branch targets, it's okay.
758 if (SuccMBB == TBB || SuccMBB == FBB)
759 continue;
760 // If we might have a fallthrough, and the successor is the fallthrough
761 // block, that's also ok.
762 if (Fallthrough && SuccMBB == MBB->getNextNode())
763 continue;
764 // Also accept successors which are for exception-handling or might be
765 // inlineasm_br targets.
766 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
767 continue;
768 report("MBB has unexpected successors which are not branch targets, "
769 "fallthrough, EHPads, or inlineasm_br targets.",
770 MBB);
771 }
772 }
773
774 regsLive.clear();
775 if (MRI->tracksLiveness()) {
776 for (const auto &LI : MBB->liveins()) {
777 if (!Register::isPhysicalRegister(LI.PhysReg)) {
778 report("MBB live-in list contains non-physical register", MBB);
779 continue;
780 }
781 for (const MCPhysReg &SubReg : TRI->subregs_inclusive(LI.PhysReg))
782 regsLive.insert(SubReg);
783 }
784 }
785
786 const MachineFrameInfo &MFI = MF->getFrameInfo();
787 BitVector PR = MFI.getPristineRegs(*MF);
788 for (unsigned I : PR.set_bits()) {
789 for (const MCPhysReg &SubReg : TRI->subregs_inclusive(I))
790 regsLive.insert(SubReg);
791 }
792
793 regsKilled.clear();
794 regsDefined.clear();
795
796 if (Indexes)
797 lastIndex = Indexes->getMBBStartIdx(MBB);
798}
799
800// This function gets called for all bundle headers, including normal
801// stand-alone unbundled instructions.
802void MachineVerifier::visitMachineBundleBefore(const MachineInstr *MI) {
803 if (Indexes && Indexes->hasIndex(*MI)) {
804 SlotIndex idx = Indexes->getInstructionIndex(*MI);
805 if (!(idx > lastIndex)) {
806 report("Instruction index out of order", MI);
807 errs() << "Last instruction was at " << lastIndex << '\n';
808 }
809 lastIndex = idx;
810 }
811
812 // Ensure non-terminators don't follow terminators.
813 if (MI->isTerminator()) {
814 if (!FirstTerminator)
815 FirstTerminator = MI;
816 } else if (FirstTerminator) {
817 report("Non-terminator instruction after the first terminator", MI);
818 errs() << "First terminator was:\t" << *FirstTerminator;
819 }
820}
821
822// The operands on an INLINEASM instruction must follow a template.
823// Verify that the flag operands make sense.
824void MachineVerifier::verifyInlineAsm(const MachineInstr *MI) {
825 // The first two operands on INLINEASM are the asm string and global flags.
826 if (MI->getNumOperands() < 2) {
827 report("Too few operands on inline asm", MI);
828 return;
829 }
830 if (!MI->getOperand(0).isSymbol())
831 report("Asm string must be an external symbol", MI);
832 if (!MI->getOperand(1).isImm())
833 report("Asm flags must be an immediate", MI);
834 // Allowed flags are Extra_HasSideEffects = 1, Extra_IsAlignStack = 2,
835 // Extra_AsmDialect = 4, Extra_MayLoad = 8, and Extra_MayStore = 16,
836 // and Extra_IsConvergent = 32.
837 if (!isUInt<6>(MI->getOperand(1).getImm()))
838 report("Unknown asm flags", &MI->getOperand(1), 1);
839
840 static_assert(InlineAsm::MIOp_FirstOperand == 2, "Asm format changed");
841
842 unsigned OpNo = InlineAsm::MIOp_FirstOperand;
843 unsigned NumOps;
844 for (unsigned e = MI->getNumOperands(); OpNo < e; OpNo += NumOps) {
845 const MachineOperand &MO = MI->getOperand(OpNo);
846 // There may be implicit ops after the fixed operands.
847 if (!MO.isImm())
848 break;
849 NumOps = 1 + InlineAsm::getNumOperandRegisters(MO.getImm());
850 }
851
852 if (OpNo > MI->getNumOperands())
853 report("Missing operands in last group", MI);
854
855 // An optional MDNode follows the groups.
856 if (OpNo < MI->getNumOperands() && MI->getOperand(OpNo).isMetadata())
857 ++OpNo;
858
859 // All trailing operands must be implicit registers.
860 for (unsigned e = MI->getNumOperands(); OpNo < e; ++OpNo) {
861 const MachineOperand &MO = MI->getOperand(OpNo);
862 if (!MO.isReg() || !MO.isImplicit())
863 report("Expected implicit register after groups", &MO, OpNo);
864 }
865}
866
867bool MachineVerifier::verifyAllRegOpsScalar(const MachineInstr &MI,
868 const MachineRegisterInfo &MRI) {
869 if (none_of(MI.explicit_operands(), [&MRI](const MachineOperand &Op) {
870 if (!Op.isReg())
871 return false;
872 const auto Reg = Op.getReg();
873 if (Reg.isPhysical())
874 return false;
875 return !MRI.getType(Reg).isScalar();
876 }))
877 return true;
878 report("All register operands must have scalar types", &MI);
879 return false;
880}
881
882/// Check that types are consistent when two operands need to have the same
883/// number of vector elements.
884/// \return true if the types are valid.
885bool MachineVerifier::verifyVectorElementMatch(LLT Ty0, LLT Ty1,
886 const MachineInstr *MI) {
887 if (Ty0.isVector() != Ty1.isVector()) {
888 report("operand types must be all-vector or all-scalar", MI);
889 // Generally we try to report as many issues as possible at once, but in
890 // this case it's not clear what should we be comparing the size of the
891 // scalar with: the size of the whole vector or its lane. Instead of
892 // making an arbitrary choice and emitting not so helpful message, let's
893 // avoid the extra noise and stop here.
894 return false;
895 }
896
897 if (Ty0.isVector() && Ty0.getNumElements() != Ty1.getNumElements()) {
898 report("operand types must preserve number of vector elements", MI);
899 return false;
900 }
901
902 return true;
903}
904
905void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
906 if (isFunctionSelected)
907 report("Unexpected generic instruction in a Selected function", MI);
908
909 const MCInstrDesc &MCID = MI->getDesc();
910 unsigned NumOps = MI->getNumOperands();
911
912 // Branches must reference a basic block if they are not indirect
913 if (MI->isBranch() && !MI->isIndirectBranch()) {
914 bool HasMBB = false;
915 for (const MachineOperand &Op : MI->operands()) {
916 if (Op.isMBB()) {
917 HasMBB = true;
918 break;
919 }
920 }
921
922 if (!HasMBB) {
923 report("Branch instruction is missing a basic block operand or "
924 "isIndirectBranch property",
925 MI);
926 }
927 }
928
929 // Check types.
930 SmallVector<LLT, 4> Types;
931 for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps);
932 I != E; ++I) {
933 if (!MCID.OpInfo[I].isGenericType())
934 continue;
935 // Generic instructions specify type equality constraints between some of
936 // their operands. Make sure these are consistent.
937 size_t TypeIdx = MCID.OpInfo[I].getGenericTypeIndex();
938 Types.resize(std::max(TypeIdx + 1, Types.size()));
939
940 const MachineOperand *MO = &MI->getOperand(I);
941 if (!MO->isReg()) {
942 report("generic instruction must use register operands", MI);
943 continue;
944 }
945
946 LLT OpTy = MRI->getType(MO->getReg());
947 // Don't report a type mismatch if there is no actual mismatch, only a
948 // type missing, to reduce noise:
949 if (OpTy.isValid()) {
950 // Only the first valid type for a type index will be printed: don't
951 // overwrite it later so it's always clear which type was expected:
952 if (!Types[TypeIdx].isValid())
953 Types[TypeIdx] = OpTy;
954 else if (Types[TypeIdx] != OpTy)
955 report("Type mismatch in generic instruction", MO, I, OpTy);
956 } else {
957 // Generic instructions must have types attached to their operands.
958 report("Generic instruction is missing a virtual register type", MO, I);
959 }
960 }
961
962 // Generic opcodes must not have physical register operands.
963 for (unsigned I = 0; I < MI->getNumOperands(); ++I) {
964 const MachineOperand *MO = &MI->getOperand(I);
965 if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
966 report("Generic instruction cannot have physical register", MO, I);
967 }
968
969 // Avoid out of bounds in checks below. This was already reported earlier.
970 if (MI->getNumOperands() < MCID.getNumOperands())
971 return;
972
973 StringRef ErrorInfo;
974 if (!TII->verifyInstruction(*MI, ErrorInfo))
975 report(ErrorInfo.data(), MI);
976
977 // Verify properties of various specific instruction types
978 unsigned Opc = MI->getOpcode();
979 switch (Opc) {
980 case TargetOpcode::G_ASSERT_SEXT:
981 case TargetOpcode::G_ASSERT_ZEXT: {
982 std::string OpcName =
983 Opc == TargetOpcode::G_ASSERT_ZEXT ? "G_ASSERT_ZEXT" : "G_ASSERT_SEXT";
984 if (!MI->getOperand(2).isImm()) {
985 report(Twine(OpcName, " expects an immediate operand #2"), MI);
986 break;
987 }
988
989 Register Dst = MI->getOperand(0).getReg();
990 Register Src = MI->getOperand(1).getReg();
991 LLT SrcTy = MRI->getType(Src);
992 int64_t Imm = MI->getOperand(2).getImm();
993 if (Imm <= 0) {
994 report(Twine(OpcName, " size must be >= 1"), MI);
995 break;
996 }
997
998 if (Imm >= SrcTy.getScalarSizeInBits()) {
999 report(Twine(OpcName, " size must be less than source bit width"), MI);
1000 break;
1001 }
1002
1003 if (MRI->getRegBankOrNull(Src) != MRI->getRegBankOrNull(Dst)) {
1004 report(
1005 Twine(OpcName, " source and destination register banks must match"),
1006 MI);
1007 break;
1008 }
1009
1010 if (MRI->getRegClassOrNull(Src) != MRI->getRegClassOrNull(Dst))
1011 report(
1012 Twine(OpcName, " source and destination register classes must match"),
1013 MI);
1014
1015 break;
1016 }
1017
1018 case TargetOpcode::G_CONSTANT:
1019 case TargetOpcode::G_FCONSTANT: {
1020 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1021 if (DstTy.isVector())
1022 report("Instruction cannot use a vector result type", MI);
1023
1024 if (MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1025 if (!MI->getOperand(1).isCImm()) {
1026 report("G_CONSTANT operand must be cimm", MI);
1027 break;
1028 }
1029
1030 const ConstantInt *CI = MI->getOperand(1).getCImm();
1031 if (CI->getBitWidth() != DstTy.getSizeInBits())
1032 report("inconsistent constant size", MI);
1033 } else {
1034 if (!MI->getOperand(1).isFPImm()) {
1035 report("G_FCONSTANT operand must be fpimm", MI);
1036 break;
1037 }
1038 const ConstantFP *CF = MI->getOperand(1).getFPImm();
1039
1040 if (APFloat::getSizeInBits(CF->getValueAPF().getSemantics()) !=
1041 DstTy.getSizeInBits()) {
1042 report("inconsistent constant size", MI);
1043 }
1044 }
1045
1046 break;
1047 }
1048 case TargetOpcode::G_LOAD:
1049 case TargetOpcode::G_STORE:
1050 case TargetOpcode::G_ZEXTLOAD:
1051 case TargetOpcode::G_SEXTLOAD: {
1052 LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1053 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1054 if (!PtrTy.isPointer())
1055 report("Generic memory instruction must access a pointer", MI);
1056
1057 // Generic loads and stores must have a single MachineMemOperand
1058 // describing that access.
1059 if (!MI->hasOneMemOperand()) {
1060 report("Generic instruction accessing memory must have one mem operand",
1061 MI);
1062 } else {
1063 const MachineMemOperand &MMO = **MI->memoperands_begin();
1064 if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1065 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1066 if (MMO.getSizeInBits() >= ValTy.getSizeInBits())
1067 report("Generic extload must have a narrower memory type", MI);
1068 } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
1069 if (MMO.getSize() > ValTy.getSizeInBytes())
1070 report("load memory size cannot exceed result size", MI);
1071 } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
1072 if (ValTy.getSizeInBytes() < MMO.getSize())
1073 report("store memory size cannot exceed value size", MI);
1074 }
1075 }
1076
1077 break;
1078 }
1079 case TargetOpcode::G_PHI: {
1080 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1081 if (!DstTy.isValid() || !all_of(drop_begin(MI->operands()),
1082 [this, &DstTy](const MachineOperand &MO) {
1083 if (!MO.isReg())
1084 return true;
1085 LLT Ty = MRI->getType(MO.getReg());
1086 if (!Ty.isValid() || (Ty != DstTy))
1087 return false;
1088 return true;
1089 }))
1090 report("Generic Instruction G_PHI has operands with incompatible/missing "
1091 "types",
1092 MI);
1093 break;
1094 }
1095 case TargetOpcode::G_BITCAST: {
1096 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1097 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1098 if (!DstTy.isValid() || !SrcTy.isValid())
1099 break;
1100
1101 if (SrcTy.isPointer() != DstTy.isPointer())
1102 report("bitcast cannot convert between pointers and other types", MI);
1103
1104 if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
1105 report("bitcast sizes must match", MI);
1106
1107 if (SrcTy == DstTy)
1108 report("bitcast must change the type", MI);
1109
1110 break;
1111 }
1112 case TargetOpcode::G_INTTOPTR:
1113 case TargetOpcode::G_PTRTOINT:
1114 case TargetOpcode::G_ADDRSPACE_CAST: {
1115 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1116 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1117 if (!DstTy.isValid() || !SrcTy.isValid())
1118 break;
1119
1120 verifyVectorElementMatch(DstTy, SrcTy, MI);
1121
1122 DstTy = DstTy.getScalarType();
1123 SrcTy = SrcTy.getScalarType();
1124
1125 if (MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1126 if (!DstTy.isPointer())
1127 report("inttoptr result type must be a pointer", MI);
1128 if (SrcTy.isPointer())
1129 report("inttoptr source type must not be a pointer", MI);
1130 } else if (MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1131 if (!SrcTy.isPointer())
1132 report("ptrtoint source type must be a pointer", MI);
1133 if (DstTy.isPointer())
1134 report("ptrtoint result type must not be a pointer", MI);
1135 } else {
1136 assert(MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)(static_cast <bool> (MI->getOpcode() == TargetOpcode
::G_ADDRSPACE_CAST) ? void (0) : __assert_fail ("MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 1136, __extension__
__PRETTY_FUNCTION__))
;
1137 if (!SrcTy.isPointer() || !DstTy.isPointer())
1138 report("addrspacecast types must be pointers", MI);
1139 else {
1140 if (SrcTy.getAddressSpace() == DstTy.getAddressSpace())
1141 report("addrspacecast must convert different address spaces", MI);
1142 }
1143 }
1144
1145 break;
1146 }
1147 case TargetOpcode::G_PTR_ADD: {
1148 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1149 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1150 LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1151 if (!DstTy.isValid() || !PtrTy.isValid() || !OffsetTy.isValid())
1152 break;
1153
1154 if (!PtrTy.getScalarType().isPointer())
1155 report("gep first operand must be a pointer", MI);
1156
1157 if (OffsetTy.getScalarType().isPointer())
1158 report("gep offset operand must not be a pointer", MI);
1159
1160 // TODO: Is the offset allowed to be a scalar with a vector?
1161 break;
1162 }
1163 case TargetOpcode::G_PTRMASK: {
1164 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1165 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1166 LLT MaskTy = MRI->getType(MI->getOperand(2).getReg());
1167 if (!DstTy.isValid() || !SrcTy.isValid() || !MaskTy.isValid())
1168 break;
1169
1170 if (!DstTy.getScalarType().isPointer())
1171 report("ptrmask result type must be a pointer", MI);
1172
1173 if (!MaskTy.getScalarType().isScalar())
1174 report("ptrmask mask type must be an integer", MI);
1175
1176 verifyVectorElementMatch(DstTy, MaskTy, MI);
1177 break;
1178 }
1179 case TargetOpcode::G_SEXT:
1180 case TargetOpcode::G_ZEXT:
1181 case TargetOpcode::G_ANYEXT:
1182 case TargetOpcode::G_TRUNC:
1183 case TargetOpcode::G_FPEXT:
1184 case TargetOpcode::G_FPTRUNC: {
1185 // Number of operands and presense of types is already checked (and
1186 // reported in case of any issues), so no need to report them again. As
1187 // we're trying to report as many issues as possible at once, however, the
1188 // instructions aren't guaranteed to have the right number of operands or
1189 // types attached to them at this point
1190 assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}")(static_cast <bool> (MCID.getNumOperands() == 2 &&
"Expected 2 operands G_*{EXT,TRUNC}") ? void (0) : __assert_fail
("MCID.getNumOperands() == 2 && \"Expected 2 operands G_*{EXT,TRUNC}\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 1190, __extension__
__PRETTY_FUNCTION__))
;
1191 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1192 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1193 if (!DstTy.isValid() || !SrcTy.isValid())
1194 break;
1195
1196 LLT DstElTy = DstTy.getScalarType();
1197 LLT SrcElTy = SrcTy.getScalarType();
1198 if (DstElTy.isPointer() || SrcElTy.isPointer())
1199 report("Generic extend/truncate can not operate on pointers", MI);
1200
1201 verifyVectorElementMatch(DstTy, SrcTy, MI);
1202
1203 unsigned DstSize = DstElTy.getSizeInBits();
1204 unsigned SrcSize = SrcElTy.getSizeInBits();
1205 switch (MI->getOpcode()) {
1206 default:
1207 if (DstSize <= SrcSize)
1208 report("Generic extend has destination type no larger than source", MI);
1209 break;
1210 case TargetOpcode::G_TRUNC:
1211 case TargetOpcode::G_FPTRUNC:
1212 if (DstSize >= SrcSize)
1213 report("Generic truncate has destination type no smaller than source",
1214 MI);
1215 break;
1216 }
1217 break;
1218 }
1219 case TargetOpcode::G_SELECT: {
1220 LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1221 LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1222 if (!SelTy.isValid() || !CondTy.isValid())
1223 break;
1224
1225 // Scalar condition select on a vector is valid.
1226 if (CondTy.isVector())
1227 verifyVectorElementMatch(SelTy, CondTy, MI);
1228 break;
1229 }
1230 case TargetOpcode::G_MERGE_VALUES: {
1231 // G_MERGE_VALUES should only be used to merge scalars into a larger scalar,
1232 // e.g. s2N = MERGE sN, sN
1233 // Merging multiple scalars into a vector is not allowed, should use
1234 // G_BUILD_VECTOR for that.
1235 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1236 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1237 if (DstTy.isVector() || SrcTy.isVector())
1238 report("G_MERGE_VALUES cannot operate on vectors", MI);
1239
1240 const unsigned NumOps = MI->getNumOperands();
1241 if (DstTy.getSizeInBits() != SrcTy.getSizeInBits() * (NumOps - 1))
1242 report("G_MERGE_VALUES result size is inconsistent", MI);
1243
1244 for (unsigned I = 2; I != NumOps; ++I) {
1245 if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1246 report("G_MERGE_VALUES source types do not match", MI);
1247 }
1248
1249 break;
1250 }
1251 case TargetOpcode::G_UNMERGE_VALUES: {
1252 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1253 LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1254 // For now G_UNMERGE can split vectors.
1255 for (unsigned i = 0; i < MI->getNumOperands()-1; ++i) {
1256 if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1257 report("G_UNMERGE_VALUES destination types do not match", MI);
1258 }
1259 if (SrcTy.getSizeInBits() !=
1260 (DstTy.getSizeInBits() * (MI->getNumOperands() - 1))) {
1261 report("G_UNMERGE_VALUES source operand does not cover dest operands",
1262 MI);
1263 }
1264 break;
1265 }
1266 case TargetOpcode::G_BUILD_VECTOR: {
1267 // Source types must be scalars, dest type a vector. Total size of scalars
1268 // must match the dest vector size.
1269 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1270 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1271 if (!DstTy.isVector() || SrcEltTy.isVector()) {
1272 report("G_BUILD_VECTOR must produce a vector from scalar operands", MI);
1273 break;
1274 }
1275
1276 if (DstTy.getElementType() != SrcEltTy)
1277 report("G_BUILD_VECTOR result element type must match source type", MI);
1278
1279 if (DstTy.getNumElements() != MI->getNumOperands() - 1)
1280 report("G_BUILD_VECTOR must have an operand for each elemement", MI);
1281
1282 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1283 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1284 report("G_BUILD_VECTOR source operand types are not homogeneous", MI);
1285
1286 break;
1287 }
1288 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1289 // Source types must be scalars, dest type a vector. Scalar types must be
1290 // larger than the dest vector elt type, as this is a truncating operation.
1291 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1292 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1293 if (!DstTy.isVector() || SrcEltTy.isVector())
1294 report("G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1295 MI);
1296 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1297 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1298 report("G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1299 MI);
1300 if (SrcEltTy.getSizeInBits() <= DstTy.getElementType().getSizeInBits())
1301 report("G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1302 "dest elt type",
1303 MI);
1304 break;
1305 }
1306 case TargetOpcode::G_CONCAT_VECTORS: {
1307 // Source types should be vectors, and total size should match the dest
1308 // vector size.
1309 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1310 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1311 if (!DstTy.isVector() || !SrcTy.isVector())
1312 report("G_CONCAT_VECTOR requires vector source and destination operands",
1313 MI);
1314
1315 if (MI->getNumOperands() < 3)
1316 report("G_CONCAT_VECTOR requires at least 2 source operands", MI);
1317
1318 for (const MachineOperand &MO : llvm::drop_begin(MI->operands(), 2))
1319 if (MRI->getType(MI->getOperand(1).getReg()) != MRI->getType(MO.getReg()))
1320 report("G_CONCAT_VECTOR source operand types are not homogeneous", MI);
1321 if (DstTy.getNumElements() !=
1322 SrcTy.getNumElements() * (MI->getNumOperands() - 1))
1323 report("G_CONCAT_VECTOR num dest and source elements should match", MI);
1324 break;
1325 }
1326 case TargetOpcode::G_ICMP:
1327 case TargetOpcode::G_FCMP: {
1328 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1329 LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1330
1331 if ((DstTy.isVector() != SrcTy.isVector()) ||
1332 (DstTy.isVector() && DstTy.getNumElements() != SrcTy.getNumElements()))
1333 report("Generic vector icmp/fcmp must preserve number of lanes", MI);
1334
1335 break;
1336 }
1337 case TargetOpcode::G_EXTRACT: {
1338 const MachineOperand &SrcOp = MI->getOperand(1);
1339 if (!SrcOp.isReg()) {
1340 report("extract source must be a register", MI);
1341 break;
1342 }
1343
1344 const MachineOperand &OffsetOp = MI->getOperand(2);
1345 if (!OffsetOp.isImm()) {
1346 report("extract offset must be a constant", MI);
1347 break;
1348 }
1349
1350 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1351 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1352 if (SrcSize == DstSize)
1353 report("extract source must be larger than result", MI);
1354
1355 if (DstSize + OffsetOp.getImm() > SrcSize)
1356 report("extract reads past end of register", MI);
1357 break;
1358 }
1359 case TargetOpcode::G_INSERT: {
1360 const MachineOperand &SrcOp = MI->getOperand(2);
1361 if (!SrcOp.isReg()) {
1362 report("insert source must be a register", MI);
1363 break;
1364 }
1365
1366 const MachineOperand &OffsetOp = MI->getOperand(3);
1367 if (!OffsetOp.isImm()) {
1368 report("insert offset must be a constant", MI);
1369 break;
1370 }
1371
1372 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1373 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1374
1375 if (DstSize <= SrcSize)
1376 report("inserted size must be smaller than total register", MI);
1377
1378 if (SrcSize + OffsetOp.getImm() > DstSize)
1379 report("insert writes past end of register", MI);
1380
1381 break;
1382 }
1383 case TargetOpcode::G_JUMP_TABLE: {
1384 if (!MI->getOperand(1).isJTI())
1385 report("G_JUMP_TABLE source operand must be a jump table index", MI);
1386 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1387 if (!DstTy.isPointer())
1388 report("G_JUMP_TABLE dest operand must have a pointer type", MI);
1389 break;
1390 }
1391 case TargetOpcode::G_BRJT: {
1392 if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1393 report("G_BRJT src operand 0 must be a pointer type", MI);
1394
1395 if (!MI->getOperand(1).isJTI())
1396 report("G_BRJT src operand 1 must be a jump table index", MI);
1397
1398 const auto &IdxOp = MI->getOperand(2);
1399 if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1400 report("G_BRJT src operand 2 must be a scalar reg type", MI);
1401 break;
1402 }
1403 case TargetOpcode::G_INTRINSIC:
1404 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: {
1405 // TODO: Should verify number of def and use operands, but the current
1406 // interface requires passing in IR types for mangling.
1407 const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs());
1408 if (!IntrIDOp.isIntrinsicID()) {
1409 report("G_INTRINSIC first src operand must be an intrinsic ID", MI);
1410 break;
1411 }
1412
1413 bool NoSideEffects = MI->getOpcode() == TargetOpcode::G_INTRINSIC;
1414 unsigned IntrID = IntrIDOp.getIntrinsicID();
1415 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1416 AttributeList Attrs
1417 = Intrinsic::getAttributes(MF->getFunction().getContext(),
1418 static_cast<Intrinsic::ID>(IntrID));
1419 bool DeclHasSideEffects = !Attrs.hasFnAttr(Attribute::ReadNone);
1420 if (NoSideEffects && DeclHasSideEffects) {
1421 report("G_INTRINSIC used with intrinsic that accesses memory", MI);
1422 break;
1423 }
1424 if (!NoSideEffects && !DeclHasSideEffects) {
1425 report("G_INTRINSIC_W_SIDE_EFFECTS used with readnone intrinsic", MI);
1426 break;
1427 }
1428 }
1429
1430 break;
1431 }
1432 case TargetOpcode::G_SEXT_INREG: {
1433 if (!MI->getOperand(2).isImm()) {
1434 report("G_SEXT_INREG expects an immediate operand #2", MI);
1435 break;
1436 }
1437
1438 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1439 int64_t Imm = MI->getOperand(2).getImm();
1440 if (Imm <= 0)
1441 report("G_SEXT_INREG size must be >= 1", MI);
1442 if (Imm >= SrcTy.getScalarSizeInBits())
1443 report("G_SEXT_INREG size must be less than source bit width", MI);
1444 break;
1445 }
1446 case TargetOpcode::G_SHUFFLE_VECTOR: {
1447 const MachineOperand &MaskOp = MI->getOperand(3);
1448 if (!MaskOp.isShuffleMask()) {
1449 report("Incorrect mask operand type for G_SHUFFLE_VECTOR", MI);
1450 break;
1451 }
1452
1453 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1454 LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1455 LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1456
1457 if (Src0Ty != Src1Ty)
1458 report("Source operands must be the same type", MI);
1459
1460 if (Src0Ty.getScalarType() != DstTy.getScalarType())
1461 report("G_SHUFFLE_VECTOR cannot change element type", MI);
1462
1463 // Don't check that all operands are vector because scalars are used in
1464 // place of 1 element vectors.
1465 int SrcNumElts = Src0Ty.isVector() ? Src0Ty.getNumElements() : 1;
1466 int DstNumElts = DstTy.isVector() ? DstTy.getNumElements() : 1;
1467
1468 ArrayRef<int> MaskIdxes = MaskOp.getShuffleMask();
1469
1470 if (static_cast<int>(MaskIdxes.size()) != DstNumElts)
1471 report("Wrong result type for shufflemask", MI);
1472
1473 for (int Idx : MaskIdxes) {
1474 if (Idx < 0)
1475 continue;
1476
1477 if (Idx >= 2 * SrcNumElts)
1478 report("Out of bounds shuffle index", MI);
1479 }
1480
1481 break;
1482 }
1483 case TargetOpcode::G_DYN_STACKALLOC: {
1484 const MachineOperand &DstOp = MI->getOperand(0);
1485 const MachineOperand &AllocOp = MI->getOperand(1);
1486 const MachineOperand &AlignOp = MI->getOperand(2);
1487
1488 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1489 report("dst operand 0 must be a pointer type", MI);
1490 break;
1491 }
1492
1493 if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1494 report("src operand 1 must be a scalar reg type", MI);
1495 break;
1496 }
1497
1498 if (!AlignOp.isImm()) {
1499 report("src operand 2 must be an immediate type", MI);
1500 break;
1501 }
1502 break;
1503 }
1504 case TargetOpcode::G_MEMCPY_INLINE:
1505 case TargetOpcode::G_MEMCPY:
1506 case TargetOpcode::G_MEMMOVE: {
1507 ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1508 if (MMOs.size() != 2) {
1509 report("memcpy/memmove must have 2 memory operands", MI);
1510 break;
1511 }
1512
1513 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad()) ||
1514 (MMOs[1]->isStore() || !MMOs[1]->isLoad())) {
1515 report("wrong memory operand types", MI);
1516 break;
1517 }
1518
1519 if (MMOs[0]->getSize() != MMOs[1]->getSize())
1520 report("inconsistent memory operand sizes", MI);
1521
1522 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1523 LLT SrcPtrTy = MRI->getType(MI->getOperand(1).getReg());
1524
1525 if (!DstPtrTy.isPointer() || !SrcPtrTy.isPointer()) {
1526 report("memory instruction operand must be a pointer", MI);
1527 break;
1528 }
1529
1530 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1531 report("inconsistent store address space", MI);
1532 if (SrcPtrTy.getAddressSpace() != MMOs[1]->getAddrSpace())
1533 report("inconsistent load address space", MI);
1534
1535 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1536 if (!MI->getOperand(3).isImm() || (MI->getOperand(3).getImm() & ~1LL))
1537 report("'tail' flag (operand 3) must be an immediate 0 or 1", MI);
1538
1539 break;
1540 }
1541 case TargetOpcode::G_BZERO:
1542 case TargetOpcode::G_MEMSET: {
1543 ArrayRef<MachineMemOperand *> MMOs = MI->memoperands();
1544 std::string Name = Opc == TargetOpcode::G_MEMSET ? "memset" : "bzero";
1545 if (MMOs.size() != 1) {
1546 report(Twine(Name, " must have 1 memory operand"), MI);
1547 break;
1548 }
1549
1550 if ((!MMOs[0]->isStore() || MMOs[0]->isLoad())) {
1551 report(Twine(Name, " memory operand must be a store"), MI);
1552 break;
1553 }
1554
1555 LLT DstPtrTy = MRI->getType(MI->getOperand(0).getReg());
1556 if (!DstPtrTy.isPointer()) {
1557 report(Twine(Name, " operand must be a pointer"), MI);
1558 break;
1559 }
1560
1561 if (DstPtrTy.getAddressSpace() != MMOs[0]->getAddrSpace())
1562 report("inconsistent " + Twine(Name, " address space"), MI);
1563
1564 if (!MI->getOperand(MI->getNumOperands() - 1).isImm() ||
1565 (MI->getOperand(MI->getNumOperands() - 1).getImm() & ~1LL))
1566 report("'tail' flag (last operand) must be an immediate 0 or 1", MI);
1567
1568 break;
1569 }
1570 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1571 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1572 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1573 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1574 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1575 if (!DstTy.isScalar())
1576 report("Vector reduction requires a scalar destination type", MI);
1577 if (!Src1Ty.isScalar())
1578 report("Sequential FADD/FMUL vector reduction requires a scalar 1st operand", MI);
1579 if (!Src2Ty.isVector())
1580 report("Sequential FADD/FMUL vector reduction must have a vector 2nd operand", MI);
1581 break;
1582 }
1583 case TargetOpcode::G_VECREDUCE_FADD:
1584 case TargetOpcode::G_VECREDUCE_FMUL:
1585 case TargetOpcode::G_VECREDUCE_FMAX:
1586 case TargetOpcode::G_VECREDUCE_FMIN:
1587 case TargetOpcode::G_VECREDUCE_ADD:
1588 case TargetOpcode::G_VECREDUCE_MUL:
1589 case TargetOpcode::G_VECREDUCE_AND:
1590 case TargetOpcode::G_VECREDUCE_OR:
1591 case TargetOpcode::G_VECREDUCE_XOR:
1592 case TargetOpcode::G_VECREDUCE_SMAX:
1593 case TargetOpcode::G_VECREDUCE_SMIN:
1594 case TargetOpcode::G_VECREDUCE_UMAX:
1595 case TargetOpcode::G_VECREDUCE_UMIN: {
1596 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1597 if (!DstTy.isScalar())
1598 report("Vector reduction requires a scalar destination type", MI);
1599 break;
1600 }
1601
1602 case TargetOpcode::G_SBFX:
1603 case TargetOpcode::G_UBFX: {
1604 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1605 if (DstTy.isVector()) {
1606 report("Bitfield extraction is not supported on vectors", MI);
1607 break;
1608 }
1609 break;
1610 }
1611 case TargetOpcode::G_SHL:
1612 case TargetOpcode::G_LSHR:
1613 case TargetOpcode::G_ASHR:
1614 case TargetOpcode::G_ROTR:
1615 case TargetOpcode::G_ROTL: {
1616 LLT Src1Ty = MRI->getType(MI->getOperand(1).getReg());
1617 LLT Src2Ty = MRI->getType(MI->getOperand(2).getReg());
1618 if (Src1Ty.isVector() != Src2Ty.isVector()) {
1619 report("Shifts and rotates require operands to be either all scalars or "
1620 "all vectors",
1621 MI);
1622 break;
1623 }
1624 break;
1625 }
1626 case TargetOpcode::G_LLROUND:
1627 case TargetOpcode::G_LROUND: {
1628 verifyAllRegOpsScalar(*MI, *MRI);
1629 break;
1630 }
1631 default:
1632 break;
1633 }
1634}
1635
1636void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
1637 const MCInstrDesc &MCID = MI->getDesc();
1638 if (MI->getNumOperands() < MCID.getNumOperands()) {
1639 report("Too few operands", MI);
1640 errs() << MCID.getNumOperands() << " operands expected, but "
1641 << MI->getNumOperands() << " given.\n";
1642 }
1643
1644 if (MI->isPHI()) {
1645 if (MF->getProperties().hasProperty(
1646 MachineFunctionProperties::Property::NoPHIs))
1647 report("Found PHI instruction with NoPHIs property set", MI);
1648
1649 if (FirstNonPHI)
1650 report("Found PHI instruction after non-PHI", MI);
1651 } else if (FirstNonPHI == nullptr)
1652 FirstNonPHI = MI;
1653
1654 // Check the tied operands.
1655 if (MI->isInlineAsm())
1656 verifyInlineAsm(MI);
1657
1658 // Check that unspillable terminators define a reg and have at most one use.
1659 if (TII->isUnspillableTerminator(MI)) {
1660 if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
1661 report("Unspillable Terminator does not define a reg", MI);
1662 Register Def = MI->getOperand(0).getReg();
1663 if (Def.isVirtual() &&
1664 !MF->getProperties().hasProperty(
1665 MachineFunctionProperties::Property::NoPHIs) &&
1666 std::distance(MRI->use_nodbg_begin(Def), MRI->use_nodbg_end()) > 1)
1667 report("Unspillable Terminator expected to have at most one use!", MI);
1668 }
1669
1670 // A fully-formed DBG_VALUE must have a location. Ignore partially formed
1671 // DBG_VALUEs: these are convenient to use in tests, but should never get
1672 // generated.
1673 if (MI->isDebugValue() && MI->getNumOperands() == 4)
1674 if (!MI->getDebugLoc())
1675 report("Missing DebugLoc for debug instruction", MI);
1676
1677 // Meta instructions should never be the subject of debug value tracking,
1678 // they don't create a value in the output program at all.
1679 if (MI->isMetaInstruction() && MI->peekDebugInstrNum())
1680 report("Metadata instruction should not have a value tracking number", MI);
1681
1682 // Check the MachineMemOperands for basic consistency.
1683 for (MachineMemOperand *Op : MI->memoperands()) {
1684 if (Op->isLoad() && !MI->mayLoad())
1685 report("Missing mayLoad flag", MI);
1686 if (Op->isStore() && !MI->mayStore())
1687 report("Missing mayStore flag", MI);
1688 }
1689
1690 // Debug values must not have a slot index.
1691 // Other instructions must have one, unless they are inside a bundle.
1692 if (LiveInts) {
1693 bool mapped = !LiveInts->isNotInMIMap(*MI);
1694 if (MI->isDebugOrPseudoInstr()) {
1695 if (mapped)
1696 report("Debug instruction has a slot index", MI);
1697 } else if (MI->isInsideBundle()) {
1698 if (mapped)
1699 report("Instruction inside bundle has a slot index", MI);
1700 } else {
1701 if (!mapped)
1702 report("Missing slot index", MI);
1703 }
1704 }
1705
1706 unsigned Opc = MCID.getOpcode();
1707 if (isPreISelGenericOpcode(Opc) || isPreISelGenericOptimizationHint(Opc)) {
1708 verifyPreISelGenericInstruction(MI);
1709 return;
1710 }
1711
1712 StringRef ErrorInfo;
1713 if (!TII->verifyInstruction(*MI, ErrorInfo))
1714 report(ErrorInfo.data(), MI);
1715
1716 // Verify properties of various specific instruction types
1717 switch (MI->getOpcode()) {
1718 case TargetOpcode::COPY: {
1719 const MachineOperand &DstOp = MI->getOperand(0);
1720 const MachineOperand &SrcOp = MI->getOperand(1);
1721 const Register SrcReg = SrcOp.getReg();
1722 const Register DstReg = DstOp.getReg();
1723
1724 LLT DstTy = MRI->getType(DstReg);
1725 LLT SrcTy = MRI->getType(SrcReg);
1726 if (SrcTy.isValid() && DstTy.isValid()) {
1727 // If both types are valid, check that the types are the same.
1728 if (SrcTy != DstTy) {
1729 report("Copy Instruction is illegal with mismatching types", MI);
1730 errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
1731 }
1732
1733 break;
1734 }
1735
1736 if (!SrcTy.isValid() && !DstTy.isValid())
1737 break;
1738
1739 // If we have only one valid type, this is likely a copy between a virtual
1740 // and physical register.
1741 unsigned SrcSize = 0;
1742 unsigned DstSize = 0;
1743 if (SrcReg.isPhysical() && DstTy.isValid()) {
1744 const TargetRegisterClass *SrcRC =
1745 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
1746 if (SrcRC)
1747 SrcSize = TRI->getRegSizeInBits(*SrcRC);
1748 }
1749
1750 if (SrcSize == 0)
1751 SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
1752
1753 if (DstReg.isPhysical() && SrcTy.isValid()) {
1754 const TargetRegisterClass *DstRC =
1755 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
1756 if (DstRC)
1757 DstSize = TRI->getRegSizeInBits(*DstRC);
1758 }
1759
1760 if (DstSize == 0)
1761 DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
1762
1763 if (SrcSize != 0 && DstSize != 0 && SrcSize != DstSize) {
1764 if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
1765 report("Copy Instruction is illegal with mismatching sizes", MI);
1766 errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
1767 << "\n";
1768 }
1769 }
1770 break;
1771 }
1772 case TargetOpcode::STATEPOINT: {
1773 StatepointOpers SO(MI);
1774 if (!MI->getOperand(SO.getIDPos()).isImm() ||
1775 !MI->getOperand(SO.getNBytesPos()).isImm() ||
1776 !MI->getOperand(SO.getNCallArgsPos()).isImm()) {
1777 report("meta operands to STATEPOINT not constant!", MI);
1778 break;
1779 }
1780
1781 auto VerifyStackMapConstant = [&](unsigned Offset) {
1782 if (Offset >= MI->getNumOperands()) {
1783 report("stack map constant to STATEPOINT is out of range!", MI);
1784 return;
1785 }
1786 if (!MI->getOperand(Offset - 1).isImm() ||
1787 MI->getOperand(Offset - 1).getImm() != StackMaps::ConstantOp ||
1788 !MI->getOperand(Offset).isImm())
1789 report("stack map constant to STATEPOINT not well formed!", MI);
1790 };
1791 VerifyStackMapConstant(SO.getCCIdx());
1792 VerifyStackMapConstant(SO.getFlagsIdx());
1793 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
1794 VerifyStackMapConstant(SO.getNumGCPtrIdx());
1795 VerifyStackMapConstant(SO.getNumAllocaIdx());
1796 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
1797
1798 // Verify that all explicit statepoint defs are tied to gc operands as
1799 // they are expected to be a relocation of gc operands.
1800 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
1801 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
1802 for (unsigned Idx = 0; Idx < MI->getNumDefs(); Idx++) {
1803 unsigned UseOpIdx;
1804 if (!MI->isRegTiedToUseOperand(Idx, &UseOpIdx)) {
1805 report("STATEPOINT defs expected to be tied", MI);
1806 break;
1807 }
1808 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
1809 report("STATEPOINT def tied to non-gc operand", MI);
1810 break;
1811 }
1812 }
1813
1814 // TODO: verify we have properly encoded deopt arguments
1815 } break;
1816 case TargetOpcode::INSERT_SUBREG: {
1817 unsigned InsertedSize;
1818 if (unsigned SubIdx = MI->getOperand(2).getSubReg())
1819 InsertedSize = TRI->getSubRegIdxSize(SubIdx);
1820 else
1821 InsertedSize = TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
1822 unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
1823 if (SubRegSize < InsertedSize) {
1824 report("INSERT_SUBREG expected inserted value to have equal or lesser "
1825 "size than the subreg it was inserted into", MI);
1826 break;
1827 }
1828 } break;
1829 }
1830}
1831
1832void
1833MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
1834 const MachineInstr *MI = MO->getParent();
1835 const MCInstrDesc &MCID = MI->getDesc();
1836 unsigned NumDefs = MCID.getNumDefs();
1837 if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
1
Assuming the condition is false
2
Taking false branch
1838 NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
1839
1840 // The first MCID.NumDefs operands must be explicit register defines
1841 if (MONum < NumDefs) {
3
Assuming 'MONum' is < 'NumDefs'
4
Taking true branch
1842 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1843 if (!MO->isReg())
1844 report("Explicit definition must be a register", MO, MONum);
1845 else if (!MO->isDef() && !MCOI.isOptionalDef())
5
Assuming the condition is false
1846 report("Explicit definition marked as use", MO, MONum);
1847 else if (MO->isImplicit())
6
Assuming the condition is false
7
Taking false branch
1848 report("Explicit definition marked as implicit", MO, MONum);
1849 } else if (MONum < MCID.getNumOperands()) {
1850 const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
1851 // Don't check if it's the last operand in a variadic instruction. See,
1852 // e.g., LDM_RET in the arm back end. Check non-variadic operands only.
1853 bool IsOptional = MI->isVariadic() && MONum == MCID.getNumOperands() - 1;
1854 if (!IsOptional) {
1855 if (MO->isReg()) {
1856 if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs())
1857 report("Explicit operand marked as def", MO, MONum);
1858 if (MO->isImplicit())
1859 report("Explicit operand marked as implicit", MO, MONum);
1860 }
1861
1862 // Check that an instruction has register operands only as expected.
1863 if (MCOI.OperandType == MCOI::OPERAND_REGISTER &&
1864 !MO->isReg() && !MO->isFI())
1865 report("Expected a register operand.", MO, MONum);
1866 if (MO->isReg()) {
1867 if (MCOI.OperandType == MCOI::OPERAND_IMMEDIATE ||
1868 (MCOI.OperandType == MCOI::OPERAND_PCREL &&
1869 !TII->isPCRelRegisterOperandLegal(*MO)))
1870 report("Expected a non-register operand.", MO, MONum);
1871 }
1872 }
1873
1874 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);
1875 if (TiedTo != -1) {
1876 if (!MO->isReg())
1877 report("Tied use must be a register", MO, MONum);
1878 else if (!MO->isTied())
1879 report("Operand should be tied", MO, MONum);
1880 else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
1881 report("Tied def doesn't match MCInstrDesc", MO, MONum);
1882 else if (Register::isPhysicalRegister(MO->getReg())) {
1883 const MachineOperand &MOTied = MI->getOperand(TiedTo);
1884 if (!MOTied.isReg())
1885 report("Tied counterpart must be a register", &MOTied, TiedTo);
1886 else if (Register::isPhysicalRegister(MOTied.getReg()) &&
1887 MO->getReg() != MOTied.getReg())
1888 report("Tied physical registers must match.", &MOTied, TiedTo);
1889 }
1890 } else if (MO->isReg() && MO->isTied())
1891 report("Explicit operand should not be tied", MO, MONum);
1892 } else {
1893 // ARM adds %reg0 operands to indicate predicates. We'll allow that.
1894 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
1895 report("Extra explicit operand on non-variadic instruction", MO, MONum);
1896 }
1897
1898 switch (MO->getType()) {
8
Control jumps to 'case MO_Register:' at line 1899
1899 case MachineOperand::MO_Register: {
1900 // Verify debug flag on debug instructions. Check this first because reg0
1901 // indicates an undefined debug value.
1902 if (MI->isDebugInstr() && MO->isUse()) {
1903 if (!MO->isDebug())
1904 report("Register operand must be marked debug", MO, MONum);
1905 } else if (MO->isDebug()) {
9
Assuming the condition is false
10
Taking false branch
1906 report("Register operand must not be marked debug", MO, MONum);
1907 }
1908
1909 const Register Reg = MO->getReg();
1910 if (!Reg)
11
Assuming the condition is false
1911 return;
1912 if (MRI->tracksLiveness() && !MI->isDebugValue())
12
Taking true branch
1913 checkLiveness(MO, MONum);
13
Calling 'MachineVerifier::checkLiveness'
1914
1915 // Verify the consistency of tied operands.
1916 if (MO->isTied()) {
1917 unsigned OtherIdx = MI->findTiedOperandIdx(MONum);
1918 const MachineOperand &OtherMO = MI->getOperand(OtherIdx);
1919 if (!OtherMO.isReg())
1920 report("Must be tied to a register", MO, MONum);
1921 if (!OtherMO.isTied())
1922 report("Missing tie flags on tied operand", MO, MONum);
1923 if (MI->findTiedOperandIdx(OtherIdx) != MONum)
1924 report("Inconsistent tie links", MO, MONum);
1925 if (MONum < MCID.getNumDefs()) {
1926 if (OtherIdx < MCID.getNumOperands()) {
1927 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO))
1928 report("Explicit def tied to explicit use without tie constraint",
1929 MO, MONum);
1930 } else {
1931 if (!OtherMO.isImplicit())
1932 report("Explicit def should be tied to implicit use", MO, MONum);
1933 }
1934 }
1935 }
1936
1937 // Verify two-address constraints after the twoaddressinstruction pass.
1938 // Both twoaddressinstruction pass and phi-node-elimination pass call
1939 // MRI->leaveSSA() to set MF as NoSSA, we should do the verification after
1940 // twoaddressinstruction pass not after phi-node-elimination pass. So we
1941 // shouldn't use the NoSSA as the condition, we should based on
1942 // TiedOpsRewritten property to verify two-address constraints, this
1943 // property will be set in twoaddressinstruction pass.
1944 unsigned DefIdx;
1945 if (MF->getProperties().hasProperty(
1946 MachineFunctionProperties::Property::TiedOpsRewritten) &&
1947 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
1948 Reg != MI->getOperand(DefIdx).getReg())
1949 report("Two-address instruction operands must be identical", MO, MONum);
1950
1951 // Check register classes.
1952 unsigned SubIdx = MO->getSubReg();
1953
1954 if (Register::isPhysicalRegister(Reg)) {
1955 if (SubIdx) {
1956 report("Illegal subregister index for physical register", MO, MONum);
1957 return;
1958 }
1959 if (MONum < MCID.getNumOperands()) {
1960 if (const TargetRegisterClass *DRC =
1961 TII->getRegClass(MCID, MONum, TRI, *MF)) {
1962 if (!DRC->contains(Reg)) {
1963 report("Illegal physical register for instruction", MO, MONum);
1964 errs() << printReg(Reg, TRI) << " is not a "
1965 << TRI->getRegClassName(DRC) << " register.\n";
1966 }
1967 }
1968 }
1969 if (MO->isRenamable()) {
1970 if (MRI->isReserved(Reg)) {
1971 report("isRenamable set on reserved register", MO, MONum);
1972 return;
1973 }
1974 }
1975 } else {
1976 // Virtual register.
1977 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
1978 if (!RC) {
1979 // This is a generic virtual register.
1980
1981 // Do not allow undef uses for generic virtual registers. This ensures
1982 // getVRegDef can never fail and return null on a generic register.
1983 //
1984 // FIXME: This restriction should probably be broadened to all SSA
1985 // MIR. However, DetectDeadLanes/ProcessImplicitDefs technically still
1986 // run on the SSA function just before phi elimination.
1987 if (MO->isUndef())
1988 report("Generic virtual register use cannot be undef", MO, MONum);
1989
1990 // Debug value instruction is permitted to use undefined vregs.
1991 // This is a performance measure to skip the overhead of immediately
1992 // pruning unused debug operands. The final undef substitution occurs
1993 // when debug values are allocated in LDVImpl::handleDebugValue, so
1994 // these verifications always apply after this pass.
1995 if (isFunctionTracksDebugUserValues || !MO->isUse() ||
1996 !MI->isDebugValue() || !MRI->def_empty(Reg)) {
1997 // If we're post-Select, we can't have gvregs anymore.
1998 if (isFunctionSelected) {
1999 report("Generic virtual register invalid in a Selected function",
2000 MO, MONum);
2001 return;
2002 }
2003
2004 // The gvreg must have a type and it must not have a SubIdx.
2005 LLT Ty = MRI->getType(Reg);
2006 if (!Ty.isValid()) {
2007 report("Generic virtual register must have a valid type", MO,
2008 MONum);
2009 return;
2010 }
2011
2012 const RegisterBank *RegBank = MRI->getRegBankOrNull(Reg);
2013
2014 // If we're post-RegBankSelect, the gvreg must have a bank.
2015 if (!RegBank && isFunctionRegBankSelected) {
2016 report("Generic virtual register must have a bank in a "
2017 "RegBankSelected function",
2018 MO, MONum);
2019 return;
2020 }
2021
2022 // Make sure the register fits into its register bank if any.
2023 if (RegBank && Ty.isValid() &&
2024 RegBank->getSize() < Ty.getSizeInBits()) {
2025 report("Register bank is too small for virtual register", MO,
2026 MONum);
2027 errs() << "Register bank " << RegBank->getName() << " too small("
2028 << RegBank->getSize() << ") to fit " << Ty.getSizeInBits()
2029 << "-bits\n";
2030 return;
2031 }
2032 }
2033
2034 if (SubIdx) {
2035 report("Generic virtual register does not allow subregister index", MO,
2036 MONum);
2037 return;
2038 }
2039
2040 // If this is a target specific instruction and this operand
2041 // has register class constraint, the virtual register must
2042 // comply to it.
2043 if (!isPreISelGenericOpcode(MCID.getOpcode()) &&
2044 MONum < MCID.getNumOperands() &&
2045 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2046 report("Virtual register does not match instruction constraint", MO,
2047 MONum);
2048 errs() << "Expect register class "
2049 << TRI->getRegClassName(
2050 TII->getRegClass(MCID, MONum, TRI, *MF))
2051 << " but got nothing\n";
2052 return;
2053 }
2054
2055 break;
2056 }
2057 if (SubIdx) {
2058 const TargetRegisterClass *SRC =
2059 TRI->getSubClassWithSubReg(RC, SubIdx);
2060 if (!SRC) {
2061 report("Invalid subregister index for virtual register", MO, MONum);
2062 errs() << "Register class " << TRI->getRegClassName(RC)
2063 << " does not support subreg index " << SubIdx << "\n";
2064 return;
2065 }
2066 if (RC != SRC) {
2067 report("Invalid register class for subregister index", MO, MONum);
2068 errs() << "Register class " << TRI->getRegClassName(RC)
2069 << " does not fully support subreg index " << SubIdx << "\n";
2070 return;
2071 }
2072 }
2073 if (MONum < MCID.getNumOperands()) {
2074 if (const TargetRegisterClass *DRC =
2075 TII->getRegClass(MCID, MONum, TRI, *MF)) {
2076 if (SubIdx) {
2077 const TargetRegisterClass *SuperRC =
2078 TRI->getLargestLegalSuperClass(RC, *MF);
2079 if (!SuperRC) {
2080 report("No largest legal super class exists.", MO, MONum);
2081 return;
2082 }
2083 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2084 if (!DRC) {
2085 report("No matching super-reg register class.", MO, MONum);
2086 return;
2087 }
2088 }
2089 if (!RC->hasSuperClassEq(DRC)) {
2090 report("Illegal virtual register for instruction", MO, MONum);
2091 errs() << "Expected a " << TRI->getRegClassName(DRC)
2092 << " register, but got a " << TRI->getRegClassName(RC)
2093 << " register\n";
2094 }
2095 }
2096 }
2097 }
2098 break;
2099 }
2100
2101 case MachineOperand::MO_RegisterMask:
2102 regMasks.push_back(MO->getRegMask());
2103 break;
2104
2105 case MachineOperand::MO_MachineBasicBlock:
2106 if (MI->isPHI() && !MO->getMBB()->isSuccessor(MI->getParent()))
2107 report("PHI operand is not in the CFG", MO, MONum);
2108 break;
2109
2110 case MachineOperand::MO_FrameIndex:
2111 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) &&
2112 LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2113 int FI = MO->getIndex();
2114 LiveInterval &LI = LiveStks->getInterval(FI);
2115 SlotIndex Idx = LiveInts->getInstructionIndex(*MI);
2116
2117 bool stores = MI->mayStore();
2118 bool loads = MI->mayLoad();
2119 // For a memory-to-memory move, we need to check if the frame
2120 // index is used for storing or loading, by inspecting the
2121 // memory operands.
2122 if (stores && loads) {
2123 for (auto *MMO : MI->memoperands()) {
2124 const PseudoSourceValue *PSV = MMO->getPseudoValue();
2125 if (PSV == nullptr) continue;
2126 const FixedStackPseudoSourceValue *Value =
2127 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2128 if (Value == nullptr) continue;
2129 if (Value->getFrameIndex() != FI) continue;
2130
2131 if (MMO->isStore())
2132 loads = false;
2133 else
2134 stores = false;
2135 break;
2136 }
2137 if (loads == stores)
2138 report("Missing fixed stack memoperand.", MI);
2139 }
2140 if (loads && !LI.liveAt(Idx.getRegSlot(true))) {
2141 report("Instruction loads from dead spill slot", MO, MONum);
2142 errs() << "Live stack: " << LI << '\n';
2143 }
2144 if (stores && !LI.liveAt(Idx.getRegSlot())) {
2145 report("Instruction stores to dead spill slot", MO, MONum);
2146 errs() << "Live stack: " << LI << '\n';
2147 }
2148 }
2149 break;
2150
2151 default:
2152 break;
2153 }
2154}
2155
2156void MachineVerifier::checkLivenessAtUse(const MachineOperand *MO,
2157 unsigned MONum, SlotIndex UseIdx,
2158 const LiveRange &LR,
2159 Register VRegOrUnit,
2160 LaneBitmask LaneMask) {
2161 LiveQueryResult LRQ = LR.Query(UseIdx);
2162 // Check if we have a segment at the use, note however that we only need one
2163 // live subregister range, the others may be dead.
2164 if (!LRQ.valueIn() && LaneMask.none()) {
2165 report("No live segment at use", MO, MONum);
2166 report_context_liverange(LR);
2167 report_context_vreg_regunit(VRegOrUnit);
2168 report_context(UseIdx);
2169 }
2170 if (MO->isKill() && !LRQ.isKill()) {
2171 report("Live range continues after kill flag", MO, MONum);
2172 report_context_liverange(LR);
2173 report_context_vreg_regunit(VRegOrUnit);
2174 if (LaneMask.any())
2175 report_context_lanemask(LaneMask);
2176 report_context(UseIdx);
2177 }
2178}
2179
2180void MachineVerifier::checkLivenessAtDef(const MachineOperand *MO,
2181 unsigned MONum, SlotIndex DefIdx,
2182 const LiveRange &LR,
2183 Register VRegOrUnit,
2184 bool SubRangeCheck,
2185 LaneBitmask LaneMask) {
2186 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) {
2187 assert(VNI && "NULL valno is not allowed")(static_cast <bool> (VNI && "NULL valno is not allowed"
) ? void (0) : __assert_fail ("VNI && \"NULL valno is not allowed\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2187, __extension__
__PRETTY_FUNCTION__))
;
2188 if (VNI->def != DefIdx) {
2189 report("Inconsistent valno->def", MO, MONum);
2190 report_context_liverange(LR);
2191 report_context_vreg_regunit(VRegOrUnit);
2192 if (LaneMask.any())
2193 report_context_lanemask(LaneMask);
2194 report_context(*VNI);
2195 report_context(DefIdx);
2196 }
2197 } else {
2198 report("No live segment at def", MO, MONum);
2199 report_context_liverange(LR);
2200 report_context_vreg_regunit(VRegOrUnit);
2201 if (LaneMask.any())
2202 report_context_lanemask(LaneMask);
2203 report_context(DefIdx);
2204 }
2205 // Check that, if the dead def flag is present, LiveInts agree.
2206 if (MO->isDead()) {
2207 LiveQueryResult LRQ = LR.Query(DefIdx);
2208 if (!LRQ.isDeadDef()) {
2209 assert(Register::isVirtualRegister(VRegOrUnit) &&(static_cast <bool> (Register::isVirtualRegister(VRegOrUnit
) && "Expecting a virtual register.") ? void (0) : __assert_fail
("Register::isVirtualRegister(VRegOrUnit) && \"Expecting a virtual register.\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2210, __extension__
__PRETTY_FUNCTION__))
2210 "Expecting a virtual register.")(static_cast <bool> (Register::isVirtualRegister(VRegOrUnit
) && "Expecting a virtual register.") ? void (0) : __assert_fail
("Register::isVirtualRegister(VRegOrUnit) && \"Expecting a virtual register.\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2210, __extension__
__PRETTY_FUNCTION__))
;
2211 // A dead subreg def only tells us that the specific subreg is dead. There
2212 // could be other non-dead defs of other subregs, or we could have other
2213 // parts of the register being live through the instruction. So unless we
2214 // are checking liveness for a subrange it is ok for the live range to
2215 // continue, given that we have a dead def of a subregister.
2216 if (SubRangeCheck || MO->getSubReg() == 0) {
2217 report("Live range continues after dead def flag", MO, MONum);
2218 report_context_liverange(LR);
2219 report_context_vreg_regunit(VRegOrUnit);
2220 if (LaneMask.any())
2221 report_context_lanemask(LaneMask);
2222 }
2223 }
2224 }
2225}
2226
2227void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
2228 const MachineInstr *MI = MO->getParent();
2229 const Register Reg = MO->getReg();
2230 const unsigned SubRegIdx = MO->getSubReg();
2231
2232 const LiveInterval *LI = nullptr;
14
'LI' initialized to a null pointer value
2233 if (LiveInts && Reg.isVirtual()) {
15
Assuming field 'LiveInts' is null
2234 if (LiveInts->hasInterval(Reg)) {
2235 LI = &LiveInts->getInterval(Reg);
2236 if (SubRegIdx != 0 && (MO->isDef() || !MO->isUndef()) && !LI->empty() &&
2237 !LI->hasSubRanges() && MRI->shouldTrackSubRegLiveness(Reg))
2238 report("Live interval for subreg operand has no subranges", MO, MONum);
2239 } else {
2240 report("Virtual register has no live interval", MO, MONum);
2241 }
2242 }
2243
2244 // Both use and def operands can read a register.
2245 if (MO->readsReg()) {
16
Taking false branch
2246 if (MO->isKill())
2247 addRegWithSubRegs(regsKilled, Reg);
2248
2249 // Check that LiveVars knows this kill (unless we are inside a bundle, in
2250 // which case we have already checked that LiveVars knows any kills on the
2251 // bundle header instead).
2252 if (LiveVars && Reg.isVirtual() && MO->isKill() &&
2253 !MI->isBundledWithPred()) {
2254 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2255 if (!is_contained(VI.Kills, MI))
2256 report("Kill missing from LiveVariables", MO, MONum);
2257 }
2258
2259 // Check LiveInts liveness and kill.
2260 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
2261 SlotIndex UseIdx = LiveInts->getInstructionIndex(*MI);
2262 // Check the cached regunit intervals.
2263 if (Reg.isPhysical() && !isReserved(Reg)) {
2264 for (MCRegUnitIterator Units(Reg.asMCReg(), TRI); Units.isValid();
2265 ++Units) {
2266 if (MRI->isReservedRegUnit(*Units))
2267 continue;
2268 if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
2269 checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
2270 }
2271 }
2272
2273 if (Reg.isVirtual()) {
2274 // This is a virtual register interval.
2275 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2276
2277 if (LI->hasSubRanges() && !MO->isDef()) {
2278 LaneBitmask MOMask = SubRegIdx != 0
2279 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2280 : MRI->getMaxLaneMaskForVReg(Reg);
2281 LaneBitmask LiveInMask;
2282 for (const LiveInterval::SubRange &SR : LI->subranges()) {
2283 if ((MOMask & SR.LaneMask).none())
2284 continue;
2285 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2286 LiveQueryResult LRQ = SR.Query(UseIdx);
2287 if (LRQ.valueIn())
2288 LiveInMask |= SR.LaneMask;
2289 }
2290 // At least parts of the register has to be live at the use.
2291 if ((LiveInMask & MOMask).none()) {
2292 report("No live subrange at use", MO, MONum);
2293 report_context(*LI);
2294 report_context(UseIdx);
2295 }
2296 }
2297 }
2298 }
2299
2300 // Use of a dead register.
2301 if (!regsLive.count(Reg)) {
2302 if (Reg.isPhysical()) {
2303 // Reserved registers may be used even when 'dead'.
2304 bool Bad = !isReserved(Reg);
2305 // We are fine if just any subregister has a defined value.
2306 if (Bad) {
2307
2308 for (const MCPhysReg &SubReg : TRI->subregs(Reg)) {
2309 if (regsLive.count(SubReg)) {
2310 Bad = false;
2311 break;
2312 }
2313 }
2314 }
2315 // If there is an additional implicit-use of a super register we stop
2316 // here. By definition we are fine if the super register is not
2317 // (completely) dead, if the complete super register is dead we will
2318 // get a report for its operand.
2319 if (Bad) {
2320 for (const MachineOperand &MOP : MI->uses()) {
2321 if (!MOP.isReg() || !MOP.isImplicit())
2322 continue;
2323
2324 if (!MOP.getReg().isPhysical())
2325 continue;
2326
2327 if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
2328 Bad = false;
2329 }
2330 }
2331 if (Bad)
2332 report("Using an undefined physical register", MO, MONum);
2333 } else if (MRI->def_empty(Reg)) {
2334 report("Reading virtual register without a def", MO, MONum);
2335 } else {
2336 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2337 // We don't know which virtual registers are live in, so only complain
2338 // if vreg was killed in this MBB. Otherwise keep track of vregs that
2339 // must be live in. PHI instructions are handled separately.
2340 if (MInfo.regsKilled.count(Reg))
2341 report("Using a killed virtual register", MO, MONum);
2342 else if (!MI->isPHI())
2343 MInfo.vregsLiveIn.insert(std::make_pair(Reg, MI));
2344 }
2345 }
2346 }
2347
2348 if (MO->isDef()) {
17
Calling 'MachineOperand::isDef'
20
Returning from 'MachineOperand::isDef'
21
Taking true branch
2349 // Register defined.
2350 // TODO: verify that earlyclobber ops are not used.
2351 if (MO->isDead())
22
Assuming the condition is false
23
Taking false branch
2352 addRegWithSubRegs(regsDead, Reg);
2353 else
2354 addRegWithSubRegs(regsDefined, Reg);
24
Calling 'MachineVerifier::addRegWithSubRegs'
28
Returning from 'MachineVerifier::addRegWithSubRegs'
2355
2356 // Verify SSA form.
2357 if (MRI->isSSA() && Reg.isVirtual() &&
2358 std::next(MRI->def_begin(Reg)) != MRI->def_end())
2359 report("Multiple virtual register defs in SSA form", MO, MONum);
2360
2361 // Check LiveInts for a live segment, but only for virtual registers.
2362 if (LiveInts && !LiveInts->isNotInMIMap(*MI)) {
29
Assuming field 'LiveInts' is non-null
30
Calling 'LiveIntervals::isNotInMIMap'
33
Returning from 'LiveIntervals::isNotInMIMap'
34
Taking true branch
2363 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI);
2364 DefIdx = DefIdx.getRegSlot(MO->isEarlyClobber());
2365
2366 if (Reg.isVirtual()) {
35
Calling 'Register::isVirtual'
41
Returning from 'Register::isVirtual'
42
Taking true branch
2367 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
43
Forming reference to null pointer
2368
2369 if (LI->hasSubRanges()) {
2370 LaneBitmask MOMask = SubRegIdx != 0
2371 ? TRI->getSubRegIndexLaneMask(SubRegIdx)
2372 : MRI->getMaxLaneMaskForVReg(Reg);
2373 for (const LiveInterval::SubRange &SR : LI->subranges()) {
2374 if ((SR.LaneMask & MOMask).none())
2375 continue;
2376 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg, true, SR.LaneMask);
2377 }
2378 }
2379 }
2380 }
2381 }
2382}
2383
2384// This function gets called after visiting all instructions in a bundle. The
2385// argument points to the bundle header.
2386// Normal stand-alone instructions are also considered 'bundles', and this
2387// function is called for all of them.
2388void MachineVerifier::visitMachineBundleAfter(const MachineInstr *MI) {
2389 BBInfo &MInfo = MBBInfoMap[MI->getParent()];
2390 set_union(MInfo.regsKilled, regsKilled);
2391 set_subtract(regsLive, regsKilled); regsKilled.clear();
2392 // Kill any masked registers.
2393 while (!regMasks.empty()) {
2394 const uint32_t *Mask = regMasks.pop_back_val();
2395 for (Register Reg : regsLive)
2396 if (Reg.isPhysical() &&
2397 MachineOperand::clobbersPhysReg(Mask, Reg.asMCReg()))
2398 regsDead.push_back(Reg);
2399 }
2400 set_subtract(regsLive, regsDead); regsDead.clear();
2401 set_union(regsLive, regsDefined); regsDefined.clear();
2402}
2403
2404void
2405MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) {
2406 MBBInfoMap[MBB].regsLiveOut = regsLive;
2407 regsLive.clear();
2408
2409 if (Indexes) {
2410 SlotIndex stop = Indexes->getMBBEndIdx(MBB);
2411 if (!(stop > lastIndex)) {
2412 report("Block ends before last instruction index", MBB);
2413 errs() << "Block ends at " << stop
2414 << " last instruction was at " << lastIndex << '\n';
2415 }
2416 lastIndex = stop;
2417 }
2418}
2419
2420namespace {
2421// This implements a set of registers that serves as a filter: can filter other
2422// sets by passing through elements not in the filter and blocking those that
2423// are. Any filter implicitly includes the full set of physical registers upon
2424// creation, thus filtering them all out. The filter itself as a set only grows,
2425// and needs to be as efficient as possible.
2426struct VRegFilter {
2427 // Add elements to the filter itself. \pre Input set \p FromRegSet must have
2428 // no duplicates. Both virtual and physical registers are fine.
2429 template <typename RegSetT> void add(const RegSetT &FromRegSet) {
2430 SmallVector<Register, 0> VRegsBuffer;
2431 filterAndAdd(FromRegSet, VRegsBuffer);
2432 }
2433 // Filter \p FromRegSet through the filter and append passed elements into \p
2434 // ToVRegs. All elements appended are then added to the filter itself.
2435 // \returns true if anything changed.
2436 template <typename RegSetT>
2437 bool filterAndAdd(const RegSetT &FromRegSet,
2438 SmallVectorImpl<Register> &ToVRegs) {
2439 unsigned SparseUniverse = Sparse.size();
2440 unsigned NewSparseUniverse = SparseUniverse;
2441 unsigned NewDenseSize = Dense.size();
2442 size_t Begin = ToVRegs.size();
2443 for (Register Reg : FromRegSet) {
2444 if (!Reg.isVirtual())
2445 continue;
2446 unsigned Index = Register::virtReg2Index(Reg);
2447 if (Index < SparseUniverseMax) {
2448 if (Index < SparseUniverse && Sparse.test(Index))
2449 continue;
2450 NewSparseUniverse = std::max(NewSparseUniverse, Index + 1);
2451 } else {
2452 if (Dense.count(Reg))
2453 continue;
2454 ++NewDenseSize;
2455 }
2456 ToVRegs.push_back(Reg);
2457 }
2458 size_t End = ToVRegs.size();
2459 if (Begin == End)
2460 return false;
2461 // Reserving space in sets once performs better than doing so continuously
2462 // and pays easily for double look-ups (even in Dense with SparseUniverseMax
2463 // tuned all the way down) and double iteration (the second one is over a
2464 // SmallVector, which is a lot cheaper compared to DenseSet or BitVector).
2465 Sparse.resize(NewSparseUniverse);
2466 Dense.reserve(NewDenseSize);
2467 for (unsigned I = Begin; I < End; ++I) {
2468 Register Reg = ToVRegs[I];
2469 unsigned Index = Register::virtReg2Index(Reg);
2470 if (Index < SparseUniverseMax)
2471 Sparse.set(Index);
2472 else
2473 Dense.insert(Reg);
2474 }
2475 return true;
2476 }
2477
2478private:
2479 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2480 // VRegs indexed within SparseUniverseMax are tracked by Sparse, those beyound
2481 // are tracked by Dense. The only purpose of the threashold and the Dense set
2482 // is to have a reasonably growing memory usage in pathological cases (large
2483 // number of very sparse VRegFilter instances live at the same time). In
2484 // practice even in the worst-by-execution time cases having all elements
2485 // tracked by Sparse (very large SparseUniverseMax scenario) tends to be more
2486 // space efficient than if tracked by Dense. The threashold is set to keep the
2487 // worst-case memory usage within 2x of figures determined empirically for
2488 // "all Dense" scenario in such worst-by-execution-time cases.
2489 BitVector Sparse;
2490 DenseSet<unsigned> Dense;
2491};
2492
2493// Implements both a transfer function and a (binary, in-place) join operator
2494// for a dataflow over register sets with set union join and filtering transfer
2495// (out_b = in_b \ filter_b). filter_b is expected to be set-up ahead of time.
2496// Maintains out_b as its state, allowing for O(n) iteration over it at any
2497// time, where n is the size of the set (as opposed to O(U) where U is the
2498// universe). filter_b implicitly contains all physical registers at all times.
2499class FilteringVRegSet {
2500 VRegFilter Filter;
2501 SmallVector<Register, 0> VRegs;
2502
2503public:
2504 // Set-up the filter_b. \pre Input register set \p RS must have no duplicates.
2505 // Both virtual and physical registers are fine.
2506 template <typename RegSetT> void addToFilter(const RegSetT &RS) {
2507 Filter.add(RS);
2508 }
2509 // Passes \p RS through the filter_b (transfer function) and adds what's left
2510 // to itself (out_b).
2511 template <typename RegSetT> bool add(const RegSetT &RS) {
2512 // Double-duty the Filter: to maintain VRegs a set (and the join operation
2513 // a set union) just add everything being added here to the Filter as well.
2514 return Filter.filterAndAdd(RS, VRegs);
2515 }
2516 using const_iterator = decltype(VRegs)::const_iterator;
2517 const_iterator begin() const { return VRegs.begin(); }
2518 const_iterator end() const { return VRegs.end(); }
2519 size_t size() const { return VRegs.size(); }
2520};
2521} // namespace
2522
2523// Calculate the largest possible vregsPassed sets. These are the registers that
2524// can pass through an MBB live, but may not be live every time. It is assumed
2525// that all vregsPassed sets are empty before the call.
2526void MachineVerifier::calcRegsPassed() {
2527 if (MF->empty())
2528 // ReversePostOrderTraversal doesn't handle empty functions.
2529 return;
2530
2531 for (const MachineBasicBlock *MB :
2532 ReversePostOrderTraversal<const MachineFunction *>(MF)) {
2533 FilteringVRegSet VRegs;
2534 BBInfo &Info = MBBInfoMap[MB];
2535 assert(Info.reachable)(static_cast <bool> (Info.reachable) ? void (0) : __assert_fail
("Info.reachable", "llvm/lib/CodeGen/MachineVerifier.cpp", 2535
, __extension__ __PRETTY_FUNCTION__))
;
2536
2537 VRegs.addToFilter(Info.regsKilled);
2538 VRegs.addToFilter(Info.regsLiveOut);
2539 for (const MachineBasicBlock *Pred : MB->predecessors()) {
2540 const BBInfo &PredInfo = MBBInfoMap[Pred];
2541 if (!PredInfo.reachable)
2542 continue;
2543
2544 VRegs.add(PredInfo.regsLiveOut);
2545 VRegs.add(PredInfo.vregsPassed);
2546 }
2547 Info.vregsPassed.reserve(VRegs.size());
2548 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
2549 }
2550}
2551
2552// Calculate the set of virtual registers that must be passed through each basic
2553// block in order to satisfy the requirements of successor blocks. This is very
2554// similar to calcRegsPassed, only backwards.
2555void MachineVerifier::calcRegsRequired() {
2556 // First push live-in regs to predecessors' vregsRequired.
2557 SmallPtrSet<const MachineBasicBlock*, 8> todo;
2558 for (const auto &MBB : *MF) {
2559 BBInfo &MInfo = MBBInfoMap[&MBB];
2560 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2561 BBInfo &PInfo = MBBInfoMap[Pred];
2562 if (PInfo.addRequired(MInfo.vregsLiveIn))
2563 todo.insert(Pred);
2564 }
2565
2566 // Handle the PHI node.
2567 for (const MachineInstr &MI : MBB.phis()) {
2568 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
2569 // Skip those Operands which are undef regs or not regs.
2570 if (!MI.getOperand(i).isReg() || !MI.getOperand(i).readsReg())
2571 continue;
2572
2573 // Get register and predecessor for one PHI edge.
2574 Register Reg = MI.getOperand(i).getReg();
2575 const MachineBasicBlock *Pred = MI.getOperand(i + 1).getMBB();
2576
2577 BBInfo &PInfo = MBBInfoMap[Pred];
2578 if (PInfo.addRequired(Reg))
2579 todo.insert(Pred);
2580 }
2581 }
2582 }
2583
2584 // Iteratively push vregsRequired to predecessors. This will converge to the
2585 // same final state regardless of DenseSet iteration order.
2586 while (!todo.empty()) {
2587 const MachineBasicBlock *MBB = *todo.begin();
2588 todo.erase(MBB);
2589 BBInfo &MInfo = MBBInfoMap[MBB];
2590 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
2591 if (Pred == MBB)
2592 continue;
2593 BBInfo &SInfo = MBBInfoMap[Pred];
2594 if (SInfo.addRequired(MInfo.vregsRequired))
2595 todo.insert(Pred);
2596 }
2597 }
2598}
2599
2600// Check PHI instructions at the beginning of MBB. It is assumed that
2601// calcRegsPassed has been run so BBInfo::isLiveOut is valid.
2602void MachineVerifier::checkPHIOps(const MachineBasicBlock &MBB) {
2603 BBInfo &MInfo = MBBInfoMap[&MBB];
2604
2605 SmallPtrSet<const MachineBasicBlock*, 8> seen;
2606 for (const MachineInstr &Phi : MBB) {
2607 if (!Phi.isPHI())
2608 break;
2609 seen.clear();
2610
2611 const MachineOperand &MODef = Phi.getOperand(0);
2612 if (!MODef.isReg() || !MODef.isDef()) {
2613 report("Expected first PHI operand to be a register def", &MODef, 0);
2614 continue;
2615 }
2616 if (MODef.isTied() || MODef.isImplicit() || MODef.isInternalRead() ||
2617 MODef.isEarlyClobber() || MODef.isDebug())
2618 report("Unexpected flag on PHI operand", &MODef, 0);
2619 Register DefReg = MODef.getReg();
2620 if (!Register::isVirtualRegister(DefReg))
2621 report("Expected first PHI operand to be a virtual register", &MODef, 0);
2622
2623 for (unsigned I = 1, E = Phi.getNumOperands(); I != E; I += 2) {
2624 const MachineOperand &MO0 = Phi.getOperand(I);
2625 if (!MO0.isReg()) {
2626 report("Expected PHI operand to be a register", &MO0, I);
2627 continue;
2628 }
2629 if (MO0.isImplicit() || MO0.isInternalRead() || MO0.isEarlyClobber() ||
2630 MO0.isDebug() || MO0.isTied())
2631 report("Unexpected flag on PHI operand", &MO0, I);
2632
2633 const MachineOperand &MO1 = Phi.getOperand(I + 1);
2634 if (!MO1.isMBB()) {
2635 report("Expected PHI operand to be a basic block", &MO1, I + 1);
2636 continue;
2637 }
2638
2639 const MachineBasicBlock &Pre = *MO1.getMBB();
2640 if (!Pre.isSuccessor(&MBB)) {
2641 report("PHI input is not a predecessor block", &MO1, I + 1);
2642 continue;
2643 }
2644
2645 if (MInfo.reachable) {
2646 seen.insert(&Pre);
2647 BBInfo &PrInfo = MBBInfoMap[&Pre];
2648 if (!MO0.isUndef() && PrInfo.reachable &&
2649 !PrInfo.isLiveOut(MO0.getReg()))
2650 report("PHI operand is not live-out from predecessor", &MO0, I);
2651 }
2652 }
2653
2654 // Did we see all predecessors?
2655 if (MInfo.reachable) {
2656 for (MachineBasicBlock *Pred : MBB.predecessors()) {
2657 if (!seen.count(Pred)) {
2658 report("Missing PHI operand", &Phi);
2659 errs() << printMBBReference(*Pred)
2660 << " is a predecessor according to the CFG.\n";
2661 }
2662 }
2663 }
2664 }
2665}
2666
2667void MachineVerifier::visitMachineFunctionAfter() {
2668 calcRegsPassed();
2669
2670 for (const MachineBasicBlock &MBB : *MF)
2671 checkPHIOps(MBB);
2672
2673 // Now check liveness info if available
2674 calcRegsRequired();
2675
2676 // Check for killed virtual registers that should be live out.
2677 for (const auto &MBB : *MF) {
2678 BBInfo &MInfo = MBBInfoMap[&MBB];
2679 for (Register VReg : MInfo.vregsRequired)
2680 if (MInfo.regsKilled.count(VReg)) {
2681 report("Virtual register killed in block, but needed live out.", &MBB);
2682 errs() << "Virtual register " << printReg(VReg)
2683 << " is used after the block.\n";
2684 }
2685 }
2686
2687 if (!MF->empty()) {
2688 BBInfo &MInfo = MBBInfoMap[&MF->front()];
2689 for (Register VReg : MInfo.vregsRequired) {
2690 report("Virtual register defs don't dominate all uses.", MF);
2691 report_context_vreg(VReg);
2692 }
2693 }
2694
2695 if (LiveVars)
2696 verifyLiveVariables();
2697 if (LiveInts)
2698 verifyLiveIntervals();
2699
2700 // Check live-in list of each MBB. If a register is live into MBB, check
2701 // that the register is in regsLiveOut of each predecessor block. Since
2702 // this must come from a definition in the predecesssor or its live-in
2703 // list, this will catch a live-through case where the predecessor does not
2704 // have the register in its live-in list. This currently only checks
2705 // registers that have no aliases, are not allocatable and are not
2706 // reserved, which could mean a condition code register for instance.
2707 if (MRI->tracksLiveness())
2708 for (const auto &MBB : *MF)
2709 for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
2710 MCPhysReg LiveInReg = P.PhysReg;
2711 bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
2712 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
2713 continue;
2714 for (const MachineBasicBlock *Pred : MBB.predecessors()) {
2715 BBInfo &PInfo = MBBInfoMap[Pred];
2716 if (!PInfo.regsLiveOut.count(LiveInReg)) {
2717 report("Live in register not found to be live out from predecessor.",
2718 &MBB);
2719 errs() << TRI->getName(LiveInReg)
2720 << " not found to be live out from "
2721 << printMBBReference(*Pred) << "\n";
2722 }
2723 }
2724 }
2725
2726 for (auto CSInfo : MF->getCallSitesInfo())
2727 if (!CSInfo.first->isCall())
2728 report("Call site info referencing instruction that is not call", MF);
2729
2730 // If there's debug-info, check that we don't have any duplicate value
2731 // tracking numbers.
2732 if (MF->getFunction().getSubprogram()) {
2733 DenseSet<unsigned> SeenNumbers;
2734 for (auto &MBB : *MF) {
2735 for (auto &MI : MBB) {
2736 if (auto Num = MI.peekDebugInstrNum()) {
2737 auto Result = SeenNumbers.insert((unsigned)Num);
2738 if (!Result.second)
2739 report("Instruction has a duplicated value tracking number", &MI);
2740 }
2741 }
2742 }
2743 }
2744}
2745
2746void MachineVerifier::verifyLiveVariables() {
2747 assert(LiveVars && "Don't call verifyLiveVariables without LiveVars")(static_cast <bool> (LiveVars && "Don't call verifyLiveVariables without LiveVars"
) ? void (0) : __assert_fail ("LiveVars && \"Don't call verifyLiveVariables without LiveVars\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2747, __extension__
__PRETTY_FUNCTION__))
;
2748 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2749 Register Reg = Register::index2VirtReg(I);
2750 LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
2751 for (const auto &MBB : *MF) {
2752 BBInfo &MInfo = MBBInfoMap[&MBB];
2753
2754 // Our vregsRequired should be identical to LiveVariables' AliveBlocks
2755 if (MInfo.vregsRequired.count(Reg)) {
2756 if (!VI.AliveBlocks.test(MBB.getNumber())) {
2757 report("LiveVariables: Block missing from AliveBlocks", &MBB);
2758 errs() << "Virtual register " << printReg(Reg)
2759 << " must be live through the block.\n";
2760 }
2761 } else {
2762 if (VI.AliveBlocks.test(MBB.getNumber())) {
2763 report("LiveVariables: Block should not be in AliveBlocks", &MBB);
2764 errs() << "Virtual register " << printReg(Reg)
2765 << " is not needed live through the block.\n";
2766 }
2767 }
2768 }
2769 }
2770}
2771
2772void MachineVerifier::verifyLiveIntervals() {
2773 assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts")(static_cast <bool> (LiveInts && "Don't call verifyLiveIntervals without LiveInts"
) ? void (0) : __assert_fail ("LiveInts && \"Don't call verifyLiveIntervals without LiveInts\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2773, __extension__
__PRETTY_FUNCTION__))
;
2774 for (unsigned I = 0, E = MRI->getNumVirtRegs(); I != E; ++I) {
2775 Register Reg = Register::index2VirtReg(I);
2776
2777 // Spilling and splitting may leave unused registers around. Skip them.
2778 if (MRI->reg_nodbg_empty(Reg))
2779 continue;
2780
2781 if (!LiveInts->hasInterval(Reg)) {
2782 report("Missing live interval for virtual register", MF);
2783 errs() << printReg(Reg, TRI) << " still has defs or uses\n";
2784 continue;
2785 }
2786
2787 const LiveInterval &LI = LiveInts->getInterval(Reg);
2788 assert(Reg == LI.reg() && "Invalid reg to interval mapping")(static_cast <bool> (Reg == LI.reg() && "Invalid reg to interval mapping"
) ? void (0) : __assert_fail ("Reg == LI.reg() && \"Invalid reg to interval mapping\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2788, __extension__
__PRETTY_FUNCTION__))
;
2789 verifyLiveInterval(LI);
2790 }
2791
2792 // Verify all the cached regunit intervals.
2793 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
2794 if (const LiveRange *LR = LiveInts->getCachedRegUnit(i))
2795 verifyLiveRange(*LR, i);
2796}
2797
2798void MachineVerifier::verifyLiveRangeValue(const LiveRange &LR,
2799 const VNInfo *VNI, Register Reg,
2800 LaneBitmask LaneMask) {
2801 if (VNI->isUnused())
2802 return;
2803
2804 const VNInfo *DefVNI = LR.getVNInfoAt(VNI->def);
2805
2806 if (!DefVNI) {
2807 report("Value not live at VNInfo def and not marked unused", MF);
2808 report_context(LR, Reg, LaneMask);
2809 report_context(*VNI);
2810 return;
2811 }
2812
2813 if (DefVNI != VNI) {
2814 report("Live segment at def has different VNInfo", MF);
2815 report_context(LR, Reg, LaneMask);
2816 report_context(*VNI);
2817 return;
2818 }
2819
2820 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
2821 if (!MBB) {
2822 report("Invalid VNInfo definition index", MF);
2823 report_context(LR, Reg, LaneMask);
2824 report_context(*VNI);
2825 return;
2826 }
2827
2828 if (VNI->isPHIDef()) {
2829 if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
2830 report("PHIDef VNInfo is not defined at MBB start", MBB);
2831 report_context(LR, Reg, LaneMask);
2832 report_context(*VNI);
2833 }
2834 return;
2835 }
2836
2837 // Non-PHI def.
2838 const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
2839 if (!MI) {
2840 report("No instruction at VNInfo def index", MBB);
2841 report_context(LR, Reg, LaneMask);
2842 report_context(*VNI);
2843 return;
2844 }
2845
2846 if (Reg != 0) {
2847 bool hasDef = false;
2848 bool isEarlyClobber = false;
2849 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2850 if (!MOI->isReg() || !MOI->isDef())
2851 continue;
2852 if (Register::isVirtualRegister(Reg)) {
2853 if (MOI->getReg() != Reg)
2854 continue;
2855 } else {
2856 if (!Register::isPhysicalRegister(MOI->getReg()) ||
2857 !TRI->hasRegUnit(MOI->getReg(), Reg))
2858 continue;
2859 }
2860 if (LaneMask.any() &&
2861 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
2862 continue;
2863 hasDef = true;
2864 if (MOI->isEarlyClobber())
2865 isEarlyClobber = true;
2866 }
2867
2868 if (!hasDef) {
2869 report("Defining instruction does not modify register", MI);
2870 report_context(LR, Reg, LaneMask);
2871 report_context(*VNI);
2872 }
2873
2874 // Early clobber defs begin at USE slots, but other defs must begin at
2875 // DEF slots.
2876 if (isEarlyClobber) {
2877 if (!VNI->def.isEarlyClobber()) {
2878 report("Early clobber def must be at an early-clobber slot", MBB);
2879 report_context(LR, Reg, LaneMask);
2880 report_context(*VNI);
2881 }
2882 } else if (!VNI->def.isRegister()) {
2883 report("Non-PHI, non-early clobber def must be at a register slot", MBB);
2884 report_context(LR, Reg, LaneMask);
2885 report_context(*VNI);
2886 }
2887 }
2888}
2889
2890void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
2891 const LiveRange::const_iterator I,
2892 Register Reg,
2893 LaneBitmask LaneMask) {
2894 const LiveRange::Segment &S = *I;
2895 const VNInfo *VNI = S.valno;
2896 assert(VNI && "Live segment has no valno")(static_cast <bool> (VNI && "Live segment has no valno"
) ? void (0) : __assert_fail ("VNI && \"Live segment has no valno\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 2896, __extension__
__PRETTY_FUNCTION__))
;
2897
2898 if (VNI->id >= LR.getNumValNums() || VNI != LR.getValNumInfo(VNI->id)) {
2899 report("Foreign valno in live segment", MF);
2900 report_context(LR, Reg, LaneMask);
2901 report_context(S);
2902 report_context(*VNI);
2903 }
2904
2905 if (VNI->isUnused()) {
2906 report("Live segment valno is marked unused", MF);
2907 report_context(LR, Reg, LaneMask);
2908 report_context(S);
2909 }
2910
2911 const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(S.start);
2912 if (!MBB) {
2913 report("Bad start of live segment, no basic block", MF);
2914 report_context(LR, Reg, LaneMask);
2915 report_context(S);
2916 return;
2917 }
2918 SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
2919 if (S.start != MBBStartIdx && S.start != VNI->def) {
2920 report("Live segment must begin at MBB entry or valno def", MBB);
2921 report_context(LR, Reg, LaneMask);
2922 report_context(S);
2923 }
2924
2925 const MachineBasicBlock *EndMBB =
2926 LiveInts->getMBBFromIndex(S.end.getPrevSlot());
2927 if (!EndMBB) {
2928 report("Bad end of live segment, no basic block", MF);
2929 report_context(LR, Reg, LaneMask);
2930 report_context(S);
2931 return;
2932 }
2933
2934 // No more checks for live-out segments.
2935 if (S.end == LiveInts->getMBBEndIdx(EndMBB))
2936 return;
2937
2938 // RegUnit intervals are allowed dead phis.
2939 if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
2940 S.start == VNI->def && S.end == VNI->def.getDeadSlot())
2941 return;
2942
2943 // The live segment is ending inside EndMBB
2944 const MachineInstr *MI =
2945 LiveInts->getInstructionFromIndex(S.end.getPrevSlot());
2946 if (!MI) {
2947 report("Live segment doesn't end at a valid instruction", EndMBB);
2948 report_context(LR, Reg, LaneMask);
2949 report_context(S);
2950 return;
2951 }
2952
2953 // The block slot must refer to a basic block boundary.
2954 if (S.end.isBlock()) {
2955 report("Live segment ends at B slot of an instruction", EndMBB);
2956 report_context(LR, Reg, LaneMask);
2957 report_context(S);
2958 }
2959
2960 if (S.end.isDead()) {
2961 // Segment ends on the dead slot.
2962 // That means there must be a dead def.
2963 if (!SlotIndex::isSameInstr(S.start, S.end)) {
2964 report("Live segment ending at dead slot spans instructions", EndMBB);
2965 report_context(LR, Reg, LaneMask);
2966 report_context(S);
2967 }
2968 }
2969
2970 // After tied operands are rewritten, a live segment can only end at an
2971 // early-clobber slot if it is being redefined by an early-clobber def.
2972 // TODO: Before tied operands are rewritten, a live segment can only end at an
2973 // early-clobber slot if the last use is tied to an early-clobber def.
2974 if (MF->getProperties().hasProperty(
2975 MachineFunctionProperties::Property::TiedOpsRewritten) &&
2976 S.end.isEarlyClobber()) {
2977 if (I+1 == LR.end() || (I+1)->start != S.end) {
2978 report("Live segment ending at early clobber slot must be "
2979 "redefined by an EC def in the same instruction", EndMBB);
2980 report_context(LR, Reg, LaneMask);
2981 report_context(S);
2982 }
2983 }
2984
2985 // The following checks only apply to virtual registers. Physreg liveness
2986 // is too weird to check.
2987 if (Register::isVirtualRegister(Reg)) {
2988 // A live segment can end with either a redefinition, a kill flag on a
2989 // use, or a dead flag on a def.
2990 bool hasRead = false;
2991 bool hasSubRegDef = false;
2992 bool hasDeadDef = false;
2993 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) {
2994 if (!MOI->isReg() || MOI->getReg() != Reg)
2995 continue;
2996 unsigned Sub = MOI->getSubReg();
2997 LaneBitmask SLM = Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
2998 : LaneBitmask::getAll();
2999 if (MOI->isDef()) {
3000 if (Sub != 0) {
3001 hasSubRegDef = true;
3002 // An operand %0:sub0 reads %0:sub1..n. Invert the lane
3003 // mask for subregister defs. Read-undef defs will be handled by
3004 // readsReg below.
3005 SLM = ~SLM;
3006 }
3007 if (MOI->isDead())
3008 hasDeadDef = true;
3009 }
3010 if (LaneMask.any() && (LaneMask & SLM).none())
3011 continue;
3012 if (MOI->readsReg())
3013 hasRead = true;
3014 }
3015 if (S.end.isDead()) {
3016 // Make sure that the corresponding machine operand for a "dead" live
3017 // range has the dead flag. We cannot perform this check for subregister
3018 // liveranges as partially dead values are allowed.
3019 if (LaneMask.none() && !hasDeadDef) {
3020 report("Instruction ending live segment on dead slot has no dead flag",
3021 MI);
3022 report_context(LR, Reg, LaneMask);
3023 report_context(S);
3024 }
3025 } else {
3026 if (!hasRead) {
3027 // When tracking subregister liveness, the main range must start new
3028 // values on partial register writes, even if there is no read.
3029 if (!MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.any() ||
3030 !hasSubRegDef) {
3031 report("Instruction ending live segment doesn't read the register",
3032 MI);
3033 report_context(LR, Reg, LaneMask);
3034 report_context(S);
3035 }
3036 }
3037 }
3038 }
3039
3040 // Now check all the basic blocks in this live segment.
3041 MachineFunction::const_iterator MFI = MBB->getIterator();
3042 // Is this live segment the beginning of a non-PHIDef VN?
3043 if (S.start == VNI->def && !VNI->isPHIDef()) {
3044 // Not live-in to any blocks.
3045 if (MBB == EndMBB)
3046 return;
3047 // Skip this block.
3048 ++MFI;
3049 }
3050
3051 SmallVector<SlotIndex, 4> Undefs;
3052 if (LaneMask.any()) {
3053 LiveInterval &OwnerLI = LiveInts->getInterval(Reg);
3054 OwnerLI.computeSubRangeUndefs(Undefs, LaneMask, *MRI, *Indexes);
3055 }
3056
3057 while (true) {
3058 assert(LiveInts->isLiveInToMBB(LR, &*MFI))(static_cast <bool> (LiveInts->isLiveInToMBB(LR, &
*MFI)) ? void (0) : __assert_fail ("LiveInts->isLiveInToMBB(LR, &*MFI)"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 3058, __extension__
__PRETTY_FUNCTION__))
;
3059 // We don't know how to track physregs into a landing pad.
3060 if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
3061 if (&*MFI == EndMBB)
3062 break;
3063 ++MFI;
3064 continue;
3065 }
3066
3067 // Is VNI a PHI-def in the current block?
3068 bool IsPHI = VNI->isPHIDef() &&
3069 VNI->def == LiveInts->getMBBStartIdx(&*MFI);
3070
3071 // Check that VNI is live-out of all predecessors.
3072 for (const MachineBasicBlock *Pred : MFI->predecessors()) {
3073 SlotIndex PEnd = LiveInts->getMBBEndIdx(Pred);
3074 // Predecessor of landing pad live-out on last call.
3075 if (MFI->isEHPad()) {
3076 for (const MachineInstr &MI : llvm::reverse(*Pred)) {
3077 if (MI.isCall()) {
3078 PEnd = Indexes->getInstructionIndex(MI).getBoundaryIndex();
3079 break;
3080 }
3081 }
3082 }
3083 const VNInfo *PVNI = LR.getVNInfoBefore(PEnd);
3084
3085 // All predecessors must have a live-out value. However for a phi
3086 // instruction with subregister intervals
3087 // only one of the subregisters (not necessarily the current one) needs to
3088 // be defined.
3089 if (!PVNI && (LaneMask.none() || !IsPHI)) {
3090 if (LiveRangeCalc::isJointlyDominated(Pred, Undefs, *Indexes))
3091 continue;
3092 report("Register not marked live out of predecessor", Pred);
3093 report_context(LR, Reg, LaneMask);
3094 report_context(*VNI);
3095 errs() << " live into " << printMBBReference(*MFI) << '@'
3096 << LiveInts->getMBBStartIdx(&*MFI) << ", not live before "
3097 << PEnd << '\n';
3098 continue;
3099 }
3100
3101 // Only PHI-defs can take different predecessor values.
3102 if (!IsPHI && PVNI != VNI) {
3103 report("Different value live out of predecessor", Pred);
3104 report_context(LR, Reg, LaneMask);
3105 errs() << "Valno #" << PVNI->id << " live out of "
3106 << printMBBReference(*Pred) << '@' << PEnd << "\nValno #"
3107 << VNI->id << " live into " << printMBBReference(*MFI) << '@'
3108 << LiveInts->getMBBStartIdx(&*MFI) << '\n';
3109 }
3110 }
3111 if (&*MFI == EndMBB)
3112 break;
3113 ++MFI;
3114 }
3115}
3116
3117void MachineVerifier::verifyLiveRange(const LiveRange &LR, Register Reg,
3118 LaneBitmask LaneMask) {
3119 for (const VNInfo *VNI : LR.valnos)
3120 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3121
3122 for (LiveRange::const_iterator I = LR.begin(), E = LR.end(); I != E; ++I)
3123 verifyLiveRangeSegment(LR, I, Reg, LaneMask);
3124}
3125
3126void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
3127 Register Reg = LI.reg();
3128 assert(Register::isVirtualRegister(Reg))(static_cast <bool> (Register::isVirtualRegister(Reg)) ?
void (0) : __assert_fail ("Register::isVirtualRegister(Reg)"
, "llvm/lib/CodeGen/MachineVerifier.cpp", 3128, __extension__
__PRETTY_FUNCTION__))
;
3129 verifyLiveRange(LI, Reg);
3130
3131 LaneBitmask Mask;
3132 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
3133 for (const LiveInterval::SubRange &SR : LI.subranges()) {
3134 if ((Mask & SR.LaneMask).any()) {
3135 report("Lane masks of sub ranges overlap in live interval", MF);
3136 report_context(LI);
3137 }
3138 if ((SR.LaneMask & ~MaxMask).any()) {
3139 report("Subrange lanemask is invalid", MF);
3140 report_context(LI);
3141 }
3142 if (SR.empty()) {
3143 report("Subrange must not be empty", MF);
3144 report_context(SR, LI.reg(), SR.LaneMask);
3145 }
3146 Mask |= SR.LaneMask;
3147 verifyLiveRange(SR, LI.reg(), SR.LaneMask);
3148 if (!LI.covers(SR)) {
3149 report("A Subrange is not covered by the main range", MF);
3150 report_context(LI);
3151 }
3152 }
3153
3154 // Check the LI only has one connected component.
3155 ConnectedVNInfoEqClasses ConEQ(*LiveInts);
3156 unsigned NumComp = ConEQ.Classify(LI);
3157 if (NumComp > 1) {
3158 report("Multiple connected components in live interval", MF);
3159 report_context(LI);
3160 for (unsigned comp = 0; comp != NumComp; ++comp) {
3161 errs() << comp << ": valnos";
3162 for (const VNInfo *I : LI.valnos)
3163 if (comp == ConEQ.getEqClass(I))
3164 errs() << ' ' << I->id;
3165 errs() << '\n';
3166 }
3167 }
3168}
3169
3170namespace {
3171
3172 // FrameSetup and FrameDestroy can have zero adjustment, so using a single
3173 // integer, we can't tell whether it is a FrameSetup or FrameDestroy if the
3174 // value is zero.
3175 // We use a bool plus an integer to capture the stack state.
3176 struct StackStateOfBB {
3177 StackStateOfBB() = default;
3178 StackStateOfBB(int EntryVal, int ExitVal, bool EntrySetup, bool ExitSetup) :
3179 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3180 ExitIsSetup(ExitSetup) {}
3181
3182 // Can be negative, which means we are setting up a frame.
3183 int EntryValue = 0;
3184 int ExitValue = 0;
3185 bool EntryIsSetup = false;
3186 bool ExitIsSetup = false;
3187 };
3188
3189} // end anonymous namespace
3190
3191/// Make sure on every path through the CFG, a FrameSetup <n> is always followed
3192/// by a FrameDestroy <n>, stack adjustments are identical on all
3193/// CFG edges to a merge point, and frame is destroyed at end of a return block.
3194void MachineVerifier::verifyStackFrame() {
3195 unsigned FrameSetupOpcode = TII->getCallFrameSetupOpcode();
3196 unsigned FrameDestroyOpcode = TII->getCallFrameDestroyOpcode();
3197 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3198 return;
3199
3200 SmallVector<StackStateOfBB, 8> SPState;
3201 SPState.resize(MF->getNumBlockIDs());
3202 df_iterator_default_set<const MachineBasicBlock*> Reachable;
3203
3204 // Visit the MBBs in DFS order.
3205 for (df_ext_iterator<const MachineFunction *,
3206 df_iterator_default_set<const MachineBasicBlock *>>
3207 DFI = df_ext_begin(MF, Reachable), DFE = df_ext_end(MF, Reachable);
3208 DFI != DFE; ++DFI) {
3209 const MachineBasicBlock *MBB = *DFI;
3210
3211 StackStateOfBB BBState;
3212 // Check the exit state of the DFS stack predecessor.
3213 if (DFI.getPathLength() >= 2) {
3214 const MachineBasicBlock *StackPred = DFI.getPath(DFI.getPathLength() - 2);
3215 assert(Reachable.count(StackPred) &&(static_cast <bool> (Reachable.count(StackPred) &&
"DFS stack predecessor is already visited.\n") ? void (0) : __assert_fail
("Reachable.count(StackPred) && \"DFS stack predecessor is already visited.\\n\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 3216, __extension__
__PRETTY_FUNCTION__))
3216 "DFS stack predecessor is already visited.\n")(static_cast <bool> (Reachable.count(StackPred) &&
"DFS stack predecessor is already visited.\n") ? void (0) : __assert_fail
("Reachable.count(StackPred) && \"DFS stack predecessor is already visited.\\n\""
, "llvm/lib/CodeGen/MachineVerifier.cpp", 3216, __extension__
__PRETTY_FUNCTION__))
;
3217 BBState.EntryValue = SPState[StackPred->getNumber()].ExitValue;
3218 BBState.EntryIsSetup = SPState[StackPred->getNumber()].ExitIsSetup;
3219 BBState.ExitValue = BBState.EntryValue;
3220 BBState.ExitIsSetup = BBState.EntryIsSetup;
3221 }
3222
3223 // Update stack state by checking contents of MBB.
3224 for (const auto &I : *MBB) {
3225 if (I.getOpcode() == FrameSetupOpcode) {
3226 if (BBState.ExitIsSetup)
3227 report("FrameSetup is after another FrameSetup", &I);
3228 BBState.ExitValue -= TII->getFrameTotalSize(I);
3229 BBState.ExitIsSetup = true;
3230 }
3231
3232 if (I.getOpcode() == FrameDestroyOpcode) {
3233 int Size = TII->getFrameTotalSize(I);
3234 if (!BBState.ExitIsSetup)
3235 report("FrameDestroy is not after a FrameSetup", &I);
3236 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3237 BBState.ExitValue;
3238 if (BBState.ExitIsSetup && AbsSPAdj != Size) {
3239 report("FrameDestroy <n> is after FrameSetup <m>", &I);
3240 errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
3241 << AbsSPAdj << ">.\n";
3242 }
3243 BBState.ExitValue += Size;
3244 BBState.ExitIsSetup = false;
3245 }
3246 }
3247 SPState[MBB->getNumber()] = BBState;
3248
3249 // Make sure the exit state of any predecessor is consistent with the entry
3250 // state.
3251 for (const MachineBasicBlock *Pred : MBB->predecessors()) {
3252 if (Reachable.count(Pred) &&
3253 (SPState[Pred->getNumber()].ExitValue != BBState.EntryValue ||
3254 SPState[Pred->getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3255 report("The exit stack state of a predecessor is inconsistent.", MBB);
3256 errs() << "Predecessor " << printMBBReference(*Pred)
3257 << " has exit state (" << SPState[Pred->getNumber()].ExitValue
3258 << ", " << SPState[Pred->getNumber()].ExitIsSetup << "), while "
3259 << printMBBReference(*MBB) << " has entry state ("
3260 << BBState.EntryValue << ", " << BBState.EntryIsSetup << ").\n";
3261 }
3262 }
3263
3264 // Make sure the entry state of any successor is consistent with the exit
3265 // state.
3266 for (const MachineBasicBlock *Succ : MBB->successors()) {
3267 if (Reachable.count(Succ) &&
3268 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3269 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3270 report("The entry stack state of a successor is inconsistent.", MBB);
3271 errs() << "Successor " << printMBBReference(*Succ)
3272 << " has entry state (" << SPState[Succ->getNumber()].EntryValue
3273 << ", " << SPState[Succ->getNumber()].EntryIsSetup << "), while "
3274 << printMBBReference(*MBB) << " has exit state ("
3275 << BBState.ExitValue << ", " << BBState.ExitIsSetup << ").\n";
3276 }
3277 }
3278
3279 // Make sure a basic block with return ends with zero stack adjustment.
3280 if (!MBB->empty() && MBB->back().isReturn()) {
3281 if (BBState.ExitIsSetup)
3282 report("A return block ends with a FrameSetup.", MBB);
3283 if (BBState.ExitValue)
3284 report("A return block ends with a nonzero stack adjustment.", MBB);
3285 }
3286 }
3287}

/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/include/llvm/CodeGen/MachineOperand.h

1//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineOperand class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEOPERAND_H
14#define LLVM_CODEGEN_MACHINEOPERAND_H
15
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/CodeGen/Register.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/DataTypes.h"
20#include "llvm/Support/LowLevelTypeImpl.h"
21#include <cassert>
22
23namespace llvm {
24
25class BlockAddress;
26class Constant;
27class ConstantFP;
28class ConstantInt;
29class GlobalValue;
30class MachineBasicBlock;
31class MachineInstr;
32class MachineRegisterInfo;
33class MCCFIInstruction;
34class MDNode;
35class ModuleSlotTracker;
36class TargetIntrinsicInfo;
37class TargetRegisterInfo;
38class hash_code;
39class raw_ostream;
40class MCSymbol;
41
42/// MachineOperand class - Representation of each machine instruction operand.
43///
44/// This class isn't a POD type because it has a private constructor, but its
45/// destructor must be trivial. Functions like MachineInstr::addOperand(),
46/// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
47/// not having to call the MachineOperand destructor.
48///
49class MachineOperand {
50public:
51 enum MachineOperandType : unsigned char {
52 MO_Register, ///< Register operand.
53 MO_Immediate, ///< Immediate operand
54 MO_CImmediate, ///< Immediate >64bit operand
55 MO_FPImmediate, ///< Floating-point immediate operand
56 MO_MachineBasicBlock, ///< MachineBasicBlock reference
57 MO_FrameIndex, ///< Abstract Stack Frame Index
58 MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
59 MO_TargetIndex, ///< Target-dependent index+offset operand.
60 MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
61 MO_ExternalSymbol, ///< Name of external global symbol
62 MO_GlobalAddress, ///< Address of a global value
63 MO_BlockAddress, ///< Address of a basic block
64 MO_RegisterMask, ///< Mask of preserved registers.
65 MO_RegisterLiveOut, ///< Mask of live-out registers.
66 MO_Metadata, ///< Metadata reference (for debug info)
67 MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
68 MO_CFIIndex, ///< MCCFIInstruction index.
69 MO_IntrinsicID, ///< Intrinsic ID for ISel
70 MO_Predicate, ///< Generic predicate for ISel
71 MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
72 MO_Last = MO_ShuffleMask
73 };
74
75private:
76 /// OpKind - Specify what kind of operand this is. This discriminates the
77 /// union.
78 unsigned OpKind : 8;
79
80 /// Subregister number for MO_Register. A value of 0 indicates the
81 /// MO_Register has no subReg.
82 ///
83 /// For all other kinds of operands, this field holds target-specific flags.
84 unsigned SubReg_TargetFlags : 12;
85
86 /// TiedTo - Non-zero when this register operand is tied to another register
87 /// operand. The encoding of this field is described in the block comment
88 /// before MachineInstr::tieOperands().
89 unsigned TiedTo : 4;
90
91 /// IsDef - True if this is a def, false if this is a use of the register.
92 /// This is only valid on register operands.
93 ///
94 unsigned IsDef : 1;
95
96 /// IsImp - True if this is an implicit def or use, false if it is explicit.
97 /// This is only valid on register opderands.
98 ///
99 unsigned IsImp : 1;
100
101 /// IsDeadOrKill
102 /// For uses: IsKill - Conservatively indicates the last use of a register
103 /// on this path through the function. A register operand with true value of
104 /// this flag must be the last use of the register, a register operand with
105 /// false value may or may not be the last use of the register. After regalloc
106 /// we can use recomputeLivenessFlags to get precise kill flags.
107 /// For defs: IsDead - True if this register is never used by a subsequent
108 /// instruction.
109 /// This is only valid on register operands.
110 unsigned IsDeadOrKill : 1;
111
112 /// See isRenamable().
113 unsigned IsRenamable : 1;
114
115 /// IsUndef - True if this register operand reads an "undef" value, i.e. the
116 /// read value doesn't matter. This flag can be set on both use and def
117 /// operands. On a sub-register def operand, it refers to the part of the
118 /// register that isn't written. On a full-register def operand, it is a
119 /// noop. See readsReg().
120 ///
121 /// This is only valid on registers.
122 ///
123 /// Note that an instruction may have multiple <undef> operands referring to
124 /// the same register. In that case, the instruction may depend on those
125 /// operands reading the same dont-care value. For example:
126 ///
127 /// %1 = XOR undef %2, undef %2
128 ///
129 /// Any register can be used for %2, and its value doesn't matter, but
130 /// the two operands must be the same register.
131 ///
132 unsigned IsUndef : 1;
133
134 /// IsInternalRead - True if this operand reads a value that was defined
135 /// inside the same instruction or bundle. This flag can be set on both use
136 /// and def operands. On a sub-register def operand, it refers to the part
137 /// of the register that isn't written. On a full-register def operand, it
138 /// is a noop.
139 ///
140 /// When this flag is set, the instruction bundle must contain at least one
141 /// other def of the register. If multiple instructions in the bundle define
142 /// the register, the meaning is target-defined.
143 unsigned IsInternalRead : 1;
144
145 /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
146 /// by the MachineInstr before all input registers are read. This is used to
147 /// model the GCC inline asm '&' constraint modifier.
148 unsigned IsEarlyClobber : 1;
149
150 /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
151 /// not a real instruction. Such uses should be ignored during codegen.
152 unsigned IsDebug : 1;
153
154 /// SmallContents - This really should be part of the Contents union, but
155 /// lives out here so we can get a better packed struct.
156 /// MO_Register: Register number.
157 /// OffsetedInfo: Low bits of offset.
158 union {
159 unsigned RegNo; // For MO_Register.
160 unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
161 } SmallContents;
162
163 /// ParentMI - This is the instruction that this operand is embedded into.
164 /// This is valid for all operand types, when the operand is in an instr.
165 MachineInstr *ParentMI;
166
167 /// Contents union - This contains the payload for the various operand types.
168 union ContentsUnion {
169 ContentsUnion() {}
170 MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
171 const ConstantFP *CFP; // For MO_FPImmediate.
172 const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
173 int64_t ImmVal; // For MO_Immediate.
174 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
175 const MDNode *MD; // For MO_Metadata.
176 MCSymbol *Sym; // For MO_MCSymbol.
177 unsigned CFIIndex; // For MO_CFI.
178 Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
179 unsigned Pred; // For MO_Predicate
180 ArrayRef<int> ShuffleMask; // For MO_ShuffleMask
181
182 struct { // For MO_Register.
183 // Register number is in SmallContents.RegNo.
184 MachineOperand *Prev; // Access list for register. See MRI.
185 MachineOperand *Next;
186 } Reg;
187
188 /// OffsetedInfo - This struct contains the offset and an object identifier.
189 /// this represent the object as with an optional offset from it.
190 struct {
191 union {
192 int Index; // For MO_*Index - The index itself.
193 const char *SymbolName; // For MO_ExternalSymbol.
194 const GlobalValue *GV; // For MO_GlobalAddress.
195 const BlockAddress *BA; // For MO_BlockAddress.
196 } Val;
197 // Low bits of offset are in SmallContents.OffsetLo.
198 int OffsetHi; // An offset from the object, high 32 bits.
199 } OffsetedInfo;
200 } Contents;
201
202 explicit MachineOperand(MachineOperandType K)
203 : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
204 // Assert that the layout is what we expect. It's easy to grow this object.
205 static_assert(alignof(MachineOperand) <= alignof(int64_t),
206 "MachineOperand shouldn't be more than 8 byte aligned");
207 static_assert(sizeof(Contents) <= 2 * sizeof(void *),
208 "Contents should be at most two pointers");
209 static_assert(sizeof(MachineOperand) <=
210 alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
211 3 * sizeof(void *)),
212 "MachineOperand too big. Should be Kind, SmallContents, "
213 "ParentMI, and Contents");
214 }
215
216public:
217 /// getType - Returns the MachineOperandType for this operand.
218 ///
219 MachineOperandType getType() const { return (MachineOperandType)OpKind; }
220
221 unsigned getTargetFlags() const {
222 return isReg() ? 0 : SubReg_TargetFlags;
223 }
224 void setTargetFlags(unsigned F) {
225 assert(!isReg() && "Register operands can't have target flags")(static_cast <bool> (!isReg() && "Register operands can't have target flags"
) ? void (0) : __assert_fail ("!isReg() && \"Register operands can't have target flags\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 225, __extension__
__PRETTY_FUNCTION__))
;
226 SubReg_TargetFlags = F;
227 assert(SubReg_TargetFlags == F && "Target flags out of range")(static_cast <bool> (SubReg_TargetFlags == F &&
"Target flags out of range") ? void (0) : __assert_fail ("SubReg_TargetFlags == F && \"Target flags out of range\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 227, __extension__
__PRETTY_FUNCTION__))
;
228 }
229 void addTargetFlag(unsigned F) {
230 assert(!isReg() && "Register operands can't have target flags")(static_cast <bool> (!isReg() && "Register operands can't have target flags"
) ? void (0) : __assert_fail ("!isReg() && \"Register operands can't have target flags\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 230, __extension__
__PRETTY_FUNCTION__))
;
231 SubReg_TargetFlags |= F;
232 assert((SubReg_TargetFlags & F) && "Target flags out of range")(static_cast <bool> ((SubReg_TargetFlags & F) &&
"Target flags out of range") ? void (0) : __assert_fail ("(SubReg_TargetFlags & F) && \"Target flags out of range\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 232, __extension__
__PRETTY_FUNCTION__))
;
233 }
234
235
236 /// getParent - Return the instruction that this operand belongs to.
237 ///
238 MachineInstr *getParent() { return ParentMI; }
239 const MachineInstr *getParent() const { return ParentMI; }
240
241 /// clearParent - Reset the parent pointer.
242 ///
243 /// The MachineOperand copy constructor also copies ParentMI, expecting the
244 /// original to be deleted. If a MachineOperand is ever stored outside a
245 /// MachineInstr, the parent pointer must be cleared.
246 ///
247 /// Never call clearParent() on an operand in a MachineInstr.
248 ///
249 void clearParent() { ParentMI = nullptr; }
250
251 /// Print a subreg index operand.
252 /// MO_Immediate operands can also be subreg idices. If it's the case, the
253 /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
254 /// called to check this.
255 static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
256 const TargetRegisterInfo *TRI);
257
258 /// Print operand target flags.
259 static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
260
261 /// Print a MCSymbol as an operand.
262 static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
263
264 /// Print a stack object reference.
265 static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
266 bool IsFixed, StringRef Name);
267
268 /// Print the offset with explicit +/- signs.
269 static void printOperandOffset(raw_ostream &OS, int64_t Offset);
270
271 /// Print an IRSlotNumber.
272 static void printIRSlotNumber(raw_ostream &OS, int Slot);
273
274 /// Print the MachineOperand to \p os.
275 /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
276 /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
277 /// function will try to pick it up from the parent.
278 void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
279 const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
280
281 /// More complex way of printing a MachineOperand.
282 /// \param TypeToPrint specifies the generic type to be printed on uses and
283 /// defs. It can be determined using MachineInstr::getTypeToPrint.
284 /// \param OpIdx - specifies the index of the operand in machine instruction.
285 /// This will be used by target dependent MIR formatter. Could be None if the
286 /// index is unknown, e.g. called by dump().
287 /// \param PrintDef - whether we want to print `def` on an operand which
288 /// isDef. Sometimes, if the operand is printed before '=', we don't print
289 /// `def`.
290 /// \param IsStandalone - whether we want a verbose output of the MO. This
291 /// prints extra information that can be easily inferred when printing the
292 /// whole function, but not when printing only a fragment of it.
293 /// \param ShouldPrintRegisterTies - whether we want to print register ties.
294 /// Sometimes they are easily determined by the instruction's descriptor
295 /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
296 /// \param TiedOperandIdx - if we need to print register ties this needs to
297 /// provide the index of the tied register. If not, it will be ignored.
298 /// \param TRI - provide more target-specific information to the printer.
299 /// Unlike the previous function, this one will not try and get the
300 /// information from it's parent.
301 /// \param IntrinsicInfo - same as \p TRI.
302 void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
303 Optional<unsigned> OpIdx, bool PrintDef, bool IsStandalone,
304 bool ShouldPrintRegisterTies, unsigned TiedOperandIdx,
305 const TargetRegisterInfo *TRI,
306 const TargetIntrinsicInfo *IntrinsicInfo) const;
307
308 /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
309 /// type to be printed the same way the full version of print(...) does it.
310 void print(raw_ostream &os, LLT TypeToPrint,
311 const TargetRegisterInfo *TRI = nullptr,
312 const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
313
314 void dump() const;
315
316 //===--------------------------------------------------------------------===//
317 // Accessors that tell you what kind of MachineOperand you're looking at.
318 //===--------------------------------------------------------------------===//
319
320 /// isReg - Tests if this is a MO_Register operand.
321 bool isReg() const { return OpKind == MO_Register; }
322 /// isImm - Tests if this is a MO_Immediate operand.
323 bool isImm() const { return OpKind == MO_Immediate; }
324 /// isCImm - Test if this is a MO_CImmediate operand.
325 bool isCImm() const { return OpKind == MO_CImmediate; }
326 /// isFPImm - Tests if this is a MO_FPImmediate operand.
327 bool isFPImm() const { return OpKind == MO_FPImmediate; }
328 /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
329 bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
330 /// isFI - Tests if this is a MO_FrameIndex operand.
331 bool isFI() const { return OpKind == MO_FrameIndex; }
332 /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
333 bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
334 /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
335 bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
336 /// isJTI - Tests if this is a MO_JumpTableIndex operand.
337 bool isJTI() const { return OpKind == MO_JumpTableIndex; }
338 /// isGlobal - Tests if this is a MO_GlobalAddress operand.
339 bool isGlobal() const { return OpKind == MO_GlobalAddress; }
340 /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
341 bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
342 /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
343 bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
344 /// isRegMask - Tests if this is a MO_RegisterMask operand.
345 bool isRegMask() const { return OpKind == MO_RegisterMask; }
346 /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
347 bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
348 /// isMetadata - Tests if this is a MO_Metadata operand.
349 bool isMetadata() const { return OpKind == MO_Metadata; }
350 bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
351 bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
352 bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
353 bool isPredicate() const { return OpKind == MO_Predicate; }
354 bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
355 //===--------------------------------------------------------------------===//
356 // Accessors for Register Operands
357 //===--------------------------------------------------------------------===//
358
359 /// getReg - Returns the register number.
360 Register getReg() const {
361 assert(isReg() && "This is not a register operand!")(static_cast <bool> (isReg() && "This is not a register operand!"
) ? void (0) : __assert_fail ("isReg() && \"This is not a register operand!\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 361, __extension__
__PRETTY_FUNCTION__))
;
362 return Register(SmallContents.RegNo);
363 }
364
365 unsigned getSubReg() const {
366 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 366, __extension__
__PRETTY_FUNCTION__))
;
367 return SubReg_TargetFlags;
368 }
369
370 bool isUse() const {
371 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 371, __extension__
__PRETTY_FUNCTION__))
;
372 return !IsDef;
373 }
374
375 bool isDef() const {
376 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 376, __extension__
__PRETTY_FUNCTION__))
;
18
'?' condition is true
377 return IsDef;
19
Returning value, which participates in a condition later
378 }
379
380 bool isImplicit() const {
381 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 381, __extension__
__PRETTY_FUNCTION__))
;
382 return IsImp;
383 }
384
385 bool isDead() const {
386 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 386, __extension__
__PRETTY_FUNCTION__))
;
387 return IsDeadOrKill & IsDef;
388 }
389
390 bool isKill() const {
391 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 391, __extension__
__PRETTY_FUNCTION__))
;
392 return IsDeadOrKill & !IsDef;
393 }
394
395 bool isUndef() const {
396 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 396, __extension__
__PRETTY_FUNCTION__))
;
397 return IsUndef;
398 }
399
400 /// isRenamable - Returns true if this register may be renamed, i.e. it does
401 /// not generate a value that is somehow read in a way that is not represented
402 /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
403 /// valid on physical register operands. Virtual registers are assumed to
404 /// always be renamable regardless of the value of this field.
405 ///
406 /// Operands that are renamable can freely be changed to any other register
407 /// that is a member of the register class returned by
408 /// MI->getRegClassConstraint().
409 ///
410 /// isRenamable can return false for several different reasons:
411 ///
412 /// - ABI constraints (since liveness is not always precisely modeled). We
413 /// conservatively handle these cases by setting all physical register
414 /// operands that didn’t start out as virtual regs to not be renamable.
415 /// Also any physical register operands created after register allocation or
416 /// whose register is changed after register allocation will not be
417 /// renamable. This state is tracked in the MachineOperand::IsRenamable
418 /// bit.
419 ///
420 /// - Opcode/target constraints: for opcodes that have complex register class
421 /// requirements (e.g. that depend on other operands/instructions), we set
422 /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
423 /// description. Operands belonging to instructions with opcodes that are
424 /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
425 /// isRenamable(). Additionally, the AllowRegisterRenaming target property
426 /// prevents any operands from being marked renamable for targets that don't
427 /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
428 /// values.
429 bool isRenamable() const;
430
431 bool isInternalRead() const {
432 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 432, __extension__
__PRETTY_FUNCTION__))
;
433 return IsInternalRead;
434 }
435
436 bool isEarlyClobber() const {
437 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 437, __extension__
__PRETTY_FUNCTION__))
;
438 return IsEarlyClobber;
439 }
440
441 bool isTied() const {
442 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 442, __extension__
__PRETTY_FUNCTION__))
;
443 return TiedTo;
444 }
445
446 bool isDebug() const {
447 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 447, __extension__
__PRETTY_FUNCTION__))
;
448 return IsDebug;
449 }
450
451 /// readsReg - Returns true if this operand reads the previous value of its
452 /// register. A use operand with the <undef> flag set doesn't read its
453 /// register. A sub-register def implicitly reads the other parts of the
454 /// register being redefined unless the <undef> flag is set.
455 ///
456 /// This refers to reading the register value from before the current
457 /// instruction or bundle. Internal bundle reads are not included.
458 bool readsReg() const {
459 assert(isReg() && "Wrong MachineOperand accessor")(static_cast <bool> (isReg() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 459, __extension__
__PRETTY_FUNCTION__))
;
460 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
461 }
462
463 //===--------------------------------------------------------------------===//
464 // Mutators for Register Operands
465 //===--------------------------------------------------------------------===//
466
467 /// Change the register this operand corresponds to.
468 ///
469 void setReg(Register Reg);
470
471 void setSubReg(unsigned subReg) {
472 assert(isReg() && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 472, __extension__
__PRETTY_FUNCTION__))
;
473 SubReg_TargetFlags = subReg;
474 assert(SubReg_TargetFlags == subReg && "SubReg out of range")(static_cast <bool> (SubReg_TargetFlags == subReg &&
"SubReg out of range") ? void (0) : __assert_fail ("SubReg_TargetFlags == subReg && \"SubReg out of range\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 474, __extension__
__PRETTY_FUNCTION__))
;
475 }
476
477 /// substVirtReg - Substitute the current register with the virtual
478 /// subregister Reg:SubReg. Take any existing SubReg index into account,
479 /// using TargetRegisterInfo to compose the subreg indices if necessary.
480 /// Reg must be a virtual register, SubIdx can be 0.
481 ///
482 void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
483
484 /// substPhysReg - Substitute the current register with the physical register
485 /// Reg, taking any existing SubReg into account. For instance,
486 /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
487 ///
488 void substPhysReg(MCRegister Reg, const TargetRegisterInfo&);
489
490 void setIsUse(bool Val = true) { setIsDef(!Val); }
491
492 /// Change a def to a use, or a use to a def.
493 void setIsDef(bool Val = true);
494
495 void setImplicit(bool Val = true) {
496 assert(isReg() && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 496, __extension__
__PRETTY_FUNCTION__))
;
497 IsImp = Val;
498 }
499
500 void setIsKill(bool Val = true) {
501 assert(isReg() && !IsDef && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && !IsDef &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"isReg() && !IsDef && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 501, __extension__
__PRETTY_FUNCTION__))
;
502 assert((!Val || !isDebug()) && "Marking a debug operation as kill")(static_cast <bool> ((!Val || !isDebug()) && "Marking a debug operation as kill"
) ? void (0) : __assert_fail ("(!Val || !isDebug()) && \"Marking a debug operation as kill\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 502, __extension__
__PRETTY_FUNCTION__))
;
503 IsDeadOrKill = Val;
504 }
505
506 void setIsDead(bool Val = true) {
507 assert(isReg() && IsDef && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && IsDef &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"isReg() && IsDef && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 507, __extension__
__PRETTY_FUNCTION__))
;
508 IsDeadOrKill = Val;
509 }
510
511 void setIsUndef(bool Val = true) {
512 assert(isReg() && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 512, __extension__
__PRETTY_FUNCTION__))
;
513 IsUndef = Val;
514 }
515
516 void setIsRenamable(bool Val = true);
517
518 void setIsInternalRead(bool Val = true) {
519 assert(isReg() && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 519, __extension__
__PRETTY_FUNCTION__))
;
520 IsInternalRead = Val;
521 }
522
523 void setIsEarlyClobber(bool Val = true) {
524 assert(isReg() && IsDef && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && IsDef &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"isReg() && IsDef && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 524, __extension__
__PRETTY_FUNCTION__))
;
525 IsEarlyClobber = Val;
526 }
527
528 void setIsDebug(bool Val = true) {
529 assert(isReg() && !IsDef && "Wrong MachineOperand mutator")(static_cast <bool> (isReg() && !IsDef &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"isReg() && !IsDef && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 529, __extension__
__PRETTY_FUNCTION__))
;
530 IsDebug = Val;
531 }
532
533 //===--------------------------------------------------------------------===//
534 // Accessors for various operand types.
535 //===--------------------------------------------------------------------===//
536
537 int64_t getImm() const {
538 assert(isImm() && "Wrong MachineOperand accessor")(static_cast <bool> (isImm() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isImm() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 538, __extension__
__PRETTY_FUNCTION__))
;
539 return Contents.ImmVal;
540 }
541
542 const ConstantInt *getCImm() const {
543 assert(isCImm() && "Wrong MachineOperand accessor")(static_cast <bool> (isCImm() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isCImm() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 543, __extension__
__PRETTY_FUNCTION__))
;
544 return Contents.CI;
545 }
546
547 const ConstantFP *getFPImm() const {
548 assert(isFPImm() && "Wrong MachineOperand accessor")(static_cast <bool> (isFPImm() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isFPImm() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 548, __extension__
__PRETTY_FUNCTION__))
;
549 return Contents.CFP;
550 }
551
552 MachineBasicBlock *getMBB() const {
553 assert(isMBB() && "Wrong MachineOperand accessor")(static_cast <bool> (isMBB() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isMBB() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 553, __extension__
__PRETTY_FUNCTION__))
;
554 return Contents.MBB;
555 }
556
557 int getIndex() const {
558 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&(static_cast <bool> ((isFI() || isCPI() || isTargetIndex
() || isJTI()) && "Wrong MachineOperand accessor") ? void
(0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 559, __extension__
__PRETTY_FUNCTION__))
559 "Wrong MachineOperand accessor")(static_cast <bool> ((isFI() || isCPI() || isTargetIndex
() || isJTI()) && "Wrong MachineOperand accessor") ? void
(0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 559, __extension__
__PRETTY_FUNCTION__))
;
560 return Contents.OffsetedInfo.Val.Index;
561 }
562
563 const GlobalValue *getGlobal() const {
564 assert(isGlobal() && "Wrong MachineOperand accessor")(static_cast <bool> (isGlobal() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isGlobal() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 564, __extension__
__PRETTY_FUNCTION__))
;
565 return Contents.OffsetedInfo.Val.GV;
566 }
567
568 const BlockAddress *getBlockAddress() const {
569 assert(isBlockAddress() && "Wrong MachineOperand accessor")(static_cast <bool> (isBlockAddress() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isBlockAddress() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 569, __extension__
__PRETTY_FUNCTION__))
;
570 return Contents.OffsetedInfo.Val.BA;
571 }
572
573 MCSymbol *getMCSymbol() const {
574 assert(isMCSymbol() && "Wrong MachineOperand accessor")(static_cast <bool> (isMCSymbol() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isMCSymbol() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 574, __extension__
__PRETTY_FUNCTION__))
;
575 return Contents.Sym;
576 }
577
578 unsigned getCFIIndex() const {
579 assert(isCFIIndex() && "Wrong MachineOperand accessor")(static_cast <bool> (isCFIIndex() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isCFIIndex() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 579, __extension__
__PRETTY_FUNCTION__))
;
580 return Contents.CFIIndex;
581 }
582
583 Intrinsic::ID getIntrinsicID() const {
584 assert(isIntrinsicID() && "Wrong MachineOperand accessor")(static_cast <bool> (isIntrinsicID() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isIntrinsicID() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 584, __extension__
__PRETTY_FUNCTION__))
;
585 return Contents.IntrinsicID;
586 }
587
588 unsigned getPredicate() const {
589 assert(isPredicate() && "Wrong MachineOperand accessor")(static_cast <bool> (isPredicate() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isPredicate() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 589, __extension__
__PRETTY_FUNCTION__))
;
590 return Contents.Pred;
591 }
592
593 ArrayRef<int> getShuffleMask() const {
594 assert(isShuffleMask() && "Wrong MachineOperand accessor")(static_cast <bool> (isShuffleMask() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isShuffleMask() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 594, __extension__
__PRETTY_FUNCTION__))
;
595 return Contents.ShuffleMask;
596 }
597
598 /// Return the offset from the symbol in this operand. This always returns 0
599 /// for ExternalSymbol operands.
600 int64_t getOffset() const {
601 assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand accessor") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 603, __extension__
__PRETTY_FUNCTION__))
602 isTargetIndex() || isBlockAddress()) &&(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand accessor") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 603, __extension__
__PRETTY_FUNCTION__))
603 "Wrong MachineOperand accessor")(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand accessor") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 603, __extension__
__PRETTY_FUNCTION__))
;
604 return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
605 SmallContents.OffsetLo;
606 }
607
608 const char *getSymbolName() const {
609 assert(isSymbol() && "Wrong MachineOperand accessor")(static_cast <bool> (isSymbol() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isSymbol() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 609, __extension__
__PRETTY_FUNCTION__))
;
610 return Contents.OffsetedInfo.Val.SymbolName;
611 }
612
613 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
614 /// It is sometimes necessary to detach the register mask pointer from its
615 /// machine operand. This static method can be used for such detached bit
616 /// mask pointers.
617 static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) {
618 // See TargetRegisterInfo.h.
619 assert(PhysReg < (1u << 30) && "Not a physical register")(static_cast <bool> (PhysReg < (1u << 30) &&
"Not a physical register") ? void (0) : __assert_fail ("PhysReg < (1u << 30) && \"Not a physical register\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 619, __extension__
__PRETTY_FUNCTION__))
;
620 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
621 }
622
623 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
624 bool clobbersPhysReg(MCRegister PhysReg) const {
625 return clobbersPhysReg(getRegMask(), PhysReg);
626 }
627
628 /// getRegMask - Returns a bit mask of registers preserved by this RegMask
629 /// operand.
630 const uint32_t *getRegMask() const {
631 assert(isRegMask() && "Wrong MachineOperand accessor")(static_cast <bool> (isRegMask() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isRegMask() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 631, __extension__
__PRETTY_FUNCTION__))
;
632 return Contents.RegMask;
633 }
634
635 /// Returns number of elements needed for a regmask array.
636 static unsigned getRegMaskSize(unsigned NumRegs) {
637 return (NumRegs + 31) / 32;
638 }
639
640 /// getRegLiveOut - Returns a bit mask of live-out registers.
641 const uint32_t *getRegLiveOut() const {
642 assert(isRegLiveOut() && "Wrong MachineOperand accessor")(static_cast <bool> (isRegLiveOut() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isRegLiveOut() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 642, __extension__
__PRETTY_FUNCTION__))
;
643 return Contents.RegMask;
644 }
645
646 const MDNode *getMetadata() const {
647 assert(isMetadata() && "Wrong MachineOperand accessor")(static_cast <bool> (isMetadata() && "Wrong MachineOperand accessor"
) ? void (0) : __assert_fail ("isMetadata() && \"Wrong MachineOperand accessor\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 647, __extension__
__PRETTY_FUNCTION__))
;
648 return Contents.MD;
649 }
650
651 //===--------------------------------------------------------------------===//
652 // Mutators for various operand types.
653 //===--------------------------------------------------------------------===//
654
655 void setImm(int64_t immVal) {
656 assert(isImm() && "Wrong MachineOperand mutator")(static_cast <bool> (isImm() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isImm() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 656, __extension__
__PRETTY_FUNCTION__))
;
657 Contents.ImmVal = immVal;
658 }
659
660 void setCImm(const ConstantInt *CI) {
661 assert(isCImm() && "Wrong MachineOperand mutator")(static_cast <bool> (isCImm() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isCImm() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 661, __extension__
__PRETTY_FUNCTION__))
;
662 Contents.CI = CI;
663 }
664
665 void setFPImm(const ConstantFP *CFP) {
666 assert(isFPImm() && "Wrong MachineOperand mutator")(static_cast <bool> (isFPImm() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isFPImm() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 666, __extension__
__PRETTY_FUNCTION__))
;
667 Contents.CFP = CFP;
668 }
669
670 void setOffset(int64_t Offset) {
671 assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 673, __extension__
__PRETTY_FUNCTION__))
672 isTargetIndex() || isBlockAddress()) &&(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 673, __extension__
__PRETTY_FUNCTION__))
673 "Wrong MachineOperand mutator")(static_cast <bool> ((isGlobal() || isSymbol() || isMCSymbol
() || isCPI() || isTargetIndex() || isBlockAddress()) &&
"Wrong MachineOperand mutator") ? void (0) : __assert_fail (
"(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 673, __extension__
__PRETTY_FUNCTION__))
;
674 SmallContents.OffsetLo = unsigned(Offset);
675 Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
676 }
677
678 void setIndex(int Idx) {
679 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&(static_cast <bool> ((isFI() || isCPI() || isTargetIndex
() || isJTI()) && "Wrong MachineOperand mutator") ? void
(0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 680, __extension__
__PRETTY_FUNCTION__))
680 "Wrong MachineOperand mutator")(static_cast <bool> ((isFI() || isCPI() || isTargetIndex
() || isJTI()) && "Wrong MachineOperand mutator") ? void
(0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 680, __extension__
__PRETTY_FUNCTION__))
;
681 Contents.OffsetedInfo.Val.Index = Idx;
682 }
683
684 void setMetadata(const MDNode *MD) {
685 assert(isMetadata() && "Wrong MachineOperand mutator")(static_cast <bool> (isMetadata() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isMetadata() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 685, __extension__
__PRETTY_FUNCTION__))
;
686 Contents.MD = MD;
687 }
688
689 void setMBB(MachineBasicBlock *MBB) {
690 assert(isMBB() && "Wrong MachineOperand mutator")(static_cast <bool> (isMBB() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isMBB() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 690, __extension__
__PRETTY_FUNCTION__))
;
691 Contents.MBB = MBB;
692 }
693
694 /// Sets value of register mask operand referencing Mask. The
695 /// operand does not take ownership of the memory referenced by Mask, it must
696 /// remain valid for the lifetime of the operand. See CreateRegMask().
697 /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
698 void setRegMask(const uint32_t *RegMaskPtr) {
699 assert(isRegMask() && "Wrong MachineOperand mutator")(static_cast <bool> (isRegMask() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isRegMask() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 699, __extension__
__PRETTY_FUNCTION__))
;
700 Contents.RegMask = RegMaskPtr;
701 }
702
703 void setIntrinsicID(Intrinsic::ID IID) {
704 assert(isIntrinsicID() && "Wrong MachineOperand mutator")(static_cast <bool> (isIntrinsicID() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isIntrinsicID() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 704, __extension__
__PRETTY_FUNCTION__))
;
705 Contents.IntrinsicID = IID;
706 }
707
708 void setPredicate(unsigned Predicate) {
709 assert(isPredicate() && "Wrong MachineOperand mutator")(static_cast <bool> (isPredicate() && "Wrong MachineOperand mutator"
) ? void (0) : __assert_fail ("isPredicate() && \"Wrong MachineOperand mutator\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 709, __extension__
__PRETTY_FUNCTION__))
;
710 Contents.Pred = Predicate;
711 }
712
713 //===--------------------------------------------------------------------===//
714 // Other methods.
715 //===--------------------------------------------------------------------===//
716
717 /// Returns true if this operand is identical to the specified operand except
718 /// for liveness related flags (isKill, isUndef and isDead). Note that this
719 /// should stay in sync with the hash_value overload below.
720 bool isIdenticalTo(const MachineOperand &Other) const;
721
722 /// MachineOperand hash_value overload.
723 ///
724 /// Note that this includes the same information in the hash that
725 /// isIdenticalTo uses for comparison. It is thus suited for use in hash
726 /// tables which use that function for equality comparisons only. This must
727 /// stay exactly in sync with isIdenticalTo above.
728 friend hash_code hash_value(const MachineOperand &MO);
729
730 /// ChangeToImmediate - Replace this operand with a new immediate operand of
731 /// the specified value. If an operand is known to be an immediate already,
732 /// the setImm method should be used.
733 void ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags = 0);
734
735 /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
736 /// of the specified value. If an operand is known to be an FP immediate
737 /// already, the setFPImm method should be used.
738 void ChangeToFPImmediate(const ConstantFP *FPImm, unsigned TargetFlags = 0);
739
740 /// ChangeToES - Replace this operand with a new external symbol operand.
741 void ChangeToES(const char *SymName, unsigned TargetFlags = 0);
742
743 /// ChangeToGA - Replace this operand with a new global address operand.
744 void ChangeToGA(const GlobalValue *GV, int64_t Offset,
745 unsigned TargetFlags = 0);
746
747 /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
748 void ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags = 0);
749
750 /// Replace this operand with a frame index.
751 void ChangeToFrameIndex(int Idx, unsigned TargetFlags = 0);
752
753 /// Replace this operand with a target index.
754 void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
755 unsigned TargetFlags = 0);
756
757 /// ChangeToRegister - Replace this operand with a new register operand of
758 /// the specified value. If an operand is known to be an register already,
759 /// the setReg method should be used.
760 void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
761 bool isKill = false, bool isDead = false,
762 bool isUndef = false, bool isDebug = false);
763
764 /// getTargetIndexName - If this MachineOperand is a TargetIndex that has a
765 /// name, attempt to get the name. Returns nullptr if the TargetIndex does not
766 /// have a name. Asserts if MO is not a TargetIndex.
767 const char *getTargetIndexName() const;
768
769 //===--------------------------------------------------------------------===//
770 // Construction methods.
771 //===--------------------------------------------------------------------===//
772
773 static MachineOperand CreateImm(int64_t Val) {
774 MachineOperand Op(MachineOperand::MO_Immediate);
775 Op.setImm(Val);
776 return Op;
777 }
778
779 static MachineOperand CreateCImm(const ConstantInt *CI) {
780 MachineOperand Op(MachineOperand::MO_CImmediate);
781 Op.Contents.CI = CI;
782 return Op;
783 }
784
785 static MachineOperand CreateFPImm(const ConstantFP *CFP) {
786 MachineOperand Op(MachineOperand::MO_FPImmediate);
787 Op.Contents.CFP = CFP;
788 return Op;
789 }
790
791 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
792 bool isKill = false, bool isDead = false,
793 bool isUndef = false,
794 bool isEarlyClobber = false,
795 unsigned SubReg = 0, bool isDebug = false,
796 bool isInternalRead = false,
797 bool isRenamable = false) {
798 assert(!(isDead && !isDef) && "Dead flag on non-def")(static_cast <bool> (!(isDead && !isDef) &&
"Dead flag on non-def") ? void (0) : __assert_fail ("!(isDead && !isDef) && \"Dead flag on non-def\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 798, __extension__
__PRETTY_FUNCTION__))
;
799 assert(!(isKill && isDef) && "Kill flag on def")(static_cast <bool> (!(isKill && isDef) &&
"Kill flag on def") ? void (0) : __assert_fail ("!(isKill && isDef) && \"Kill flag on def\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 799, __extension__
__PRETTY_FUNCTION__))
;
800 MachineOperand Op(MachineOperand::MO_Register);
801 Op.IsDef = isDef;
802 Op.IsImp = isImp;
803 Op.IsDeadOrKill = isKill | isDead;
804 Op.IsRenamable = isRenamable;
805 Op.IsUndef = isUndef;
806 Op.IsInternalRead = isInternalRead;
807 Op.IsEarlyClobber = isEarlyClobber;
808 Op.TiedTo = 0;
809 Op.IsDebug = isDebug;
810 Op.SmallContents.RegNo = Reg;
811 Op.Contents.Reg.Prev = nullptr;
812 Op.Contents.Reg.Next = nullptr;
813 Op.setSubReg(SubReg);
814 return Op;
815 }
816 static MachineOperand CreateMBB(MachineBasicBlock *MBB,
817 unsigned TargetFlags = 0) {
818 MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
819 Op.setMBB(MBB);
820 Op.setTargetFlags(TargetFlags);
821 return Op;
822 }
823 static MachineOperand CreateFI(int Idx) {
824 MachineOperand Op(MachineOperand::MO_FrameIndex);
825 Op.setIndex(Idx);
826 return Op;
827 }
828 static MachineOperand CreateCPI(unsigned Idx, int Offset,
829 unsigned TargetFlags = 0) {
830 MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
831 Op.setIndex(Idx);
832 Op.setOffset(Offset);
833 Op.setTargetFlags(TargetFlags);
834 return Op;
835 }
836 static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
837 unsigned TargetFlags = 0) {
838 MachineOperand Op(MachineOperand::MO_TargetIndex);
839 Op.setIndex(Idx);
840 Op.setOffset(Offset);
841 Op.setTargetFlags(TargetFlags);
842 return Op;
843 }
844 static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags = 0) {
845 MachineOperand Op(MachineOperand::MO_JumpTableIndex);
846 Op.setIndex(Idx);
847 Op.setTargetFlags(TargetFlags);
848 return Op;
849 }
850 static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
851 unsigned TargetFlags = 0) {
852 MachineOperand Op(MachineOperand::MO_GlobalAddress);
853 Op.Contents.OffsetedInfo.Val.GV = GV;
854 Op.setOffset(Offset);
855 Op.setTargetFlags(TargetFlags);
856 return Op;
857 }
858 static MachineOperand CreateES(const char *SymName,
859 unsigned TargetFlags = 0) {
860 MachineOperand Op(MachineOperand::MO_ExternalSymbol);
861 Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
862 Op.setOffset(0); // Offset is always 0.
863 Op.setTargetFlags(TargetFlags);
864 return Op;
865 }
866 static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
867 unsigned TargetFlags = 0) {
868 MachineOperand Op(MachineOperand::MO_BlockAddress);
869 Op.Contents.OffsetedInfo.Val.BA = BA;
870 Op.setOffset(Offset);
871 Op.setTargetFlags(TargetFlags);
872 return Op;
873 }
874 /// CreateRegMask - Creates a register mask operand referencing Mask. The
875 /// operand does not take ownership of the memory referenced by Mask, it
876 /// must remain valid for the lifetime of the operand.
877 ///
878 /// A RegMask operand represents a set of non-clobbered physical registers
879 /// on an instruction that clobbers many registers, typically a call. The
880 /// bit mask has a bit set for each physreg that is preserved by this
881 /// instruction, as described in the documentation for
882 /// TargetRegisterInfo::getCallPreservedMask().
883 ///
884 /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
885 ///
886 static MachineOperand CreateRegMask(const uint32_t *Mask) {
887 assert(Mask && "Missing register mask")(static_cast <bool> (Mask && "Missing register mask"
) ? void (0) : __assert_fail ("Mask && \"Missing register mask\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 887, __extension__
__PRETTY_FUNCTION__))
;
888 MachineOperand Op(MachineOperand::MO_RegisterMask);
889 Op.Contents.RegMask = Mask;
890 return Op;
891 }
892 static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
893 assert(Mask && "Missing live-out register mask")(static_cast <bool> (Mask && "Missing live-out register mask"
) ? void (0) : __assert_fail ("Mask && \"Missing live-out register mask\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 893, __extension__
__PRETTY_FUNCTION__))
;
894 MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
895 Op.Contents.RegMask = Mask;
896 return Op;
897 }
898 static MachineOperand CreateMetadata(const MDNode *Meta) {
899 MachineOperand Op(MachineOperand::MO_Metadata);
900 Op.Contents.MD = Meta;
901 return Op;
902 }
903
904 static MachineOperand CreateMCSymbol(MCSymbol *Sym,
905 unsigned TargetFlags = 0) {
906 MachineOperand Op(MachineOperand::MO_MCSymbol);
907 Op.Contents.Sym = Sym;
908 Op.setOffset(0);
909 Op.setTargetFlags(TargetFlags);
910 return Op;
911 }
912
913 static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
914 MachineOperand Op(MachineOperand::MO_CFIIndex);
915 Op.Contents.CFIIndex = CFIIndex;
916 return Op;
917 }
918
919 static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
920 MachineOperand Op(MachineOperand::MO_IntrinsicID);
921 Op.Contents.IntrinsicID = ID;
922 return Op;
923 }
924
925 static MachineOperand CreatePredicate(unsigned Pred) {
926 MachineOperand Op(MachineOperand::MO_Predicate);
927 Op.Contents.Pred = Pred;
928 return Op;
929 }
930
931 static MachineOperand CreateShuffleMask(ArrayRef<int> Mask) {
932 MachineOperand Op(MachineOperand::MO_ShuffleMask);
933 Op.Contents.ShuffleMask = Mask;
934 return Op;
935 }
936
937 friend class MachineInstr;
938 friend class MachineRegisterInfo;
939
940private:
941 // If this operand is currently a register operand, and if this is in a
942 // function, deregister the operand from the register's use/def list.
943 void removeRegFromUses();
944
945 /// Artificial kinds for DenseMap usage.
946 enum : unsigned char {
947 MO_Empty = MO_Last + 1,
948 MO_Tombstone,
949 };
950
951 friend struct DenseMapInfo<MachineOperand>;
952
953 //===--------------------------------------------------------------------===//
954 // Methods for handling register use/def lists.
955 //===--------------------------------------------------------------------===//
956
957 /// isOnRegUseList - Return true if this operand is on a register use/def
958 /// list or false if not. This can only be called for register operands
959 /// that are part of a machine instruction.
960 bool isOnRegUseList() const {
961 assert(isReg() && "Can only add reg operand to use lists")(static_cast <bool> (isReg() && "Can only add reg operand to use lists"
) ? void (0) : __assert_fail ("isReg() && \"Can only add reg operand to use lists\""
, "llvm/include/llvm/CodeGen/MachineOperand.h", 961, __extension__
__PRETTY_FUNCTION__))
;
962 return Contents.Reg.Prev != nullptr;
963 }
964};
965
966template <> struct DenseMapInfo<MachineOperand> {
967 static MachineOperand getEmptyKey() {
968 return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
969 MachineOperand::MO_Empty));
970 }
971 static MachineOperand getTombstoneKey() {
972 return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
973 MachineOperand::MO_Tombstone));
974 }
975 static unsigned getHashValue(const MachineOperand &MO) {
976 return hash_value(MO);
977 }
978 static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
979 if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
980 MachineOperand::MO_Empty) ||
981 LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
982 MachineOperand::MO_Tombstone))
983 return LHS.getType() == RHS.getType();
984 return LHS.isIdenticalTo(RHS);
985 }
986};
987
988inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
989 MO.print(OS);
990 return OS;
991}
992
993// See friend declaration above. This additional declaration is required in
994// order to compile LLVM with IBM xlC compiler.
995hash_code hash_value(const MachineOperand &MO);
996} // namespace llvm
997
998#endif

/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/include/llvm/CodeGen/LiveIntervals.h

1//===- LiveIntervals.h - Live Interval Analysis -----------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file This file implements the LiveInterval analysis pass. Given some
10/// numbering of each the machine instructions (in this implemention depth-first
11/// order) an interval [i, j) is said to be a live interval for register v if
12/// there is no instruction with number j' > j such that v is live at j' and
13/// there is no instruction with number i' < i such that v is live at i'. In
14/// this implementation intervals can have holes, i.e. an interval might look
15/// like [1,20), [50,65), [1000,1001).
16//
17//===----------------------------------------------------------------------===//
18
19#ifndef LLVM_CODEGEN_LIVEINTERVALS_H
20#define LLVM_CODEGEN_LIVEINTERVALS_H
21
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/IndexedMap.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/CodeGen/LiveInterval.h"
26#include "llvm/CodeGen/MachineBasicBlock.h"
27#include "llvm/CodeGen/MachineFunctionPass.h"
28#include "llvm/CodeGen/SlotIndexes.h"
29#include "llvm/CodeGen/TargetRegisterInfo.h"
30#include "llvm/MC/LaneBitmask.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/Compiler.h"
33#include "llvm/Support/ErrorHandling.h"
34#include <cassert>
35#include <cstdint>
36#include <utility>
37
38namespace llvm {
39
40extern cl::opt<bool> UseSegmentSetForPhysRegs;
41
42class AAResults;
43class BitVector;
44class LiveIntervalCalc;
45class MachineBlockFrequencyInfo;
46class MachineDominatorTree;
47class MachineFunction;
48class MachineInstr;
49class MachineRegisterInfo;
50class raw_ostream;
51class TargetInstrInfo;
52class VirtRegMap;
53
54 class LiveIntervals : public MachineFunctionPass {
55 MachineFunction* MF;
56 MachineRegisterInfo* MRI;
57 const TargetRegisterInfo* TRI;
58 const TargetInstrInfo* TII;
59 AAResults *AA;
60 SlotIndexes* Indexes;
61 MachineDominatorTree *DomTree = nullptr;
62 LiveIntervalCalc *LICalc = nullptr;
63
64 /// Special pool allocator for VNInfo's (LiveInterval val#).
65 VNInfo::Allocator VNInfoAllocator;
66
67 /// Live interval pointers for all the virtual registers.
68 IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
69
70 /// Sorted list of instructions with register mask operands. Always use the
71 /// 'r' slot, RegMasks are normal clobbers, not early clobbers.
72 SmallVector<SlotIndex, 8> RegMaskSlots;
73
74 /// This vector is parallel to RegMaskSlots, it holds a pointer to the
75 /// corresponding register mask. This pointer can be recomputed as:
76 ///
77 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
78 /// unsigned OpNum = findRegMaskOperand(MI);
79 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
80 ///
81 /// This is kept in a separate vector partly because some standard
82 /// libraries don't support lower_bound() with mixed objects, partly to
83 /// improve locality when searching in RegMaskSlots.
84 /// Also see the comment in LiveInterval::find().
85 SmallVector<const uint32_t*, 8> RegMaskBits;
86
87 /// For each basic block number, keep (begin, size) pairs indexing into the
88 /// RegMaskSlots and RegMaskBits arrays.
89 /// Note that basic block numbers may not be layout contiguous, that's why
90 /// we can't just keep track of the first register mask in each basic
91 /// block.
92 SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
93
94 /// Keeps a live range set for each register unit to track fixed physreg
95 /// interference.
96 SmallVector<LiveRange*, 0> RegUnitRanges;
97
98 public:
99 static char ID;
100
101 LiveIntervals();
102 ~LiveIntervals() override;
103
104 /// Calculate the spill weight to assign to a single instruction.
105 static float getSpillWeight(bool isDef, bool isUse,
106 const MachineBlockFrequencyInfo *MBFI,
107 const MachineInstr &MI);
108
109 /// Calculate the spill weight to assign to a single instruction.
110 static float getSpillWeight(bool isDef, bool isUse,
111 const MachineBlockFrequencyInfo *MBFI,
112 const MachineBasicBlock *MBB);
113
114 LiveInterval &getInterval(Register Reg) {
115 if (hasInterval(Reg))
116 return *VirtRegIntervals[Reg.id()];
117
118 return createAndComputeVirtRegInterval(Reg);
119 }
120
121 const LiveInterval &getInterval(Register Reg) const {
122 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
123 }
124
125 bool hasInterval(Register Reg) const {
126 return VirtRegIntervals.inBounds(Reg.id()) &&
127 VirtRegIntervals[Reg.id()];
128 }
129
130 /// Interval creation.
131 LiveInterval &createEmptyInterval(Register Reg) {
132 assert(!hasInterval(Reg) && "Interval already exists!")(static_cast <bool> (!hasInterval(Reg) && "Interval already exists!"
) ? void (0) : __assert_fail ("!hasInterval(Reg) && \"Interval already exists!\""
, "llvm/include/llvm/CodeGen/LiveIntervals.h", 132, __extension__
__PRETTY_FUNCTION__))
;
133 VirtRegIntervals.grow(Reg.id());
134 VirtRegIntervals[Reg.id()] = createInterval(Reg);
135 return *VirtRegIntervals[Reg.id()];
136 }
137
138 LiveInterval &createAndComputeVirtRegInterval(Register Reg) {
139 LiveInterval &LI = createEmptyInterval(Reg);
140 computeVirtRegInterval(LI);
141 return LI;
142 }
143
144 /// Interval removal.
145 void removeInterval(Register Reg) {
146 delete VirtRegIntervals[Reg];
147 VirtRegIntervals[Reg] = nullptr;
148 }
149
150 /// Given a register and an instruction, adds a live segment from that
151 /// instruction to the end of its MBB.
152 LiveInterval::Segment addSegmentToEndOfBlock(Register Reg,
153 MachineInstr &startInst);
154
155 /// After removing some uses of a register, shrink its live range to just
156 /// the remaining uses. This method does not compute reaching defs for new
157 /// uses, and it doesn't remove dead defs.
158 /// Dead PHIDef values are marked as unused. New dead machine instructions
159 /// are added to the dead vector. Returns true if the interval may have been
160 /// separated into multiple connected components.
161 bool shrinkToUses(LiveInterval *li,
162 SmallVectorImpl<MachineInstr*> *dead = nullptr);
163
164 /// Specialized version of
165 /// shrinkToUses(LiveInterval *li, SmallVectorImpl<MachineInstr*> *dead)
166 /// that works on a subregister live range and only looks at uses matching
167 /// the lane mask of the subregister range.
168 /// This may leave the subrange empty which needs to be cleaned up with
169 /// LiveInterval::removeEmptySubranges() afterwards.
170 void shrinkToUses(LiveInterval::SubRange &SR, Register Reg);
171
172 /// Extend the live range \p LR to reach all points in \p Indices. The
173 /// points in the \p Indices array must be jointly dominated by the union
174 /// of the existing defs in \p LR and points in \p Undefs.
175 ///
176 /// PHI-defs are added as needed to maintain SSA form.
177 ///
178 /// If a SlotIndex in \p Indices is the end index of a basic block, \p LR
179 /// will be extended to be live out of the basic block.
180 /// If a SlotIndex in \p Indices is jointy dominated only by points in
181 /// \p Undefs, the live range will not be extended to that point.
182 ///
183 /// See also LiveRangeCalc::extend().
184 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices,
185 ArrayRef<SlotIndex> Undefs);
186
187 void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices) {
188 extendToIndices(LR, Indices, /*Undefs=*/{});
189 }
190
191 /// If \p LR has a live value at \p Kill, prune its live range by removing
192 /// any liveness reachable from Kill. Add live range end points to
193 /// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
194 /// value's live range.
195 ///
196 /// Calling pruneValue() and extendToIndices() can be used to reconstruct
197 /// SSA form after adding defs to a virtual register.
198 void pruneValue(LiveRange &LR, SlotIndex Kill,
199 SmallVectorImpl<SlotIndex> *EndPoints);
200
201 /// This function should not be used. Its intent is to tell you that you are
202 /// doing something wrong if you call pruneValue directly on a
203 /// LiveInterval. Indeed, you are supposed to call pruneValue on the main
204 /// LiveRange and all the LiveRanges of the subranges if any.
205 LLVM_ATTRIBUTE_UNUSED__attribute__((__unused__)) void pruneValue(LiveInterval &, SlotIndex,
206 SmallVectorImpl<SlotIndex> *) {
207 llvm_unreachable(::llvm::llvm_unreachable_internal("Use pruneValue on the main LiveRange and on each subrange"
, "llvm/include/llvm/CodeGen/LiveIntervals.h", 208)
208 "Use pruneValue on the main LiveRange and on each subrange")::llvm::llvm_unreachable_internal("Use pruneValue on the main LiveRange and on each subrange"
, "llvm/include/llvm/CodeGen/LiveIntervals.h", 208)
;
209 }
210
211 SlotIndexes *getSlotIndexes() const {
212 return Indexes;
213 }
214
215 AAResults *getAliasAnalysis() const {
216 return AA;
217 }
218
219 /// Returns true if the specified machine instr has been removed or was
220 /// never entered in the map.
221 bool isNotInMIMap(const MachineInstr &Instr) const {
222 return !Indexes->hasIndex(Instr);
31
Assuming the condition is false
32
Returning zero, which participates in a condition later
223 }
224
225 /// Returns the base index of the given instruction.
226 SlotIndex getInstructionIndex(const MachineInstr &Instr) const {
227 return Indexes->getInstructionIndex(Instr);
228 }
229
230 /// Returns the instruction associated with the given index.
231 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
232 return Indexes->getInstructionFromIndex(index);
233 }
234
235 /// Return the first index in the given basic block.
236 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
237 return Indexes->getMBBStartIdx(mbb);
238 }
239
240 /// Return the last index in the given basic block.
241 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
242 return Indexes->getMBBEndIdx(mbb);
243 }
244
245 bool isLiveInToMBB(const LiveRange &LR,
246 const MachineBasicBlock *mbb) const {
247 return LR.liveAt(getMBBStartIdx(mbb));
248 }
249
250 bool isLiveOutOfMBB(const LiveRange &LR,
251 const MachineBasicBlock *mbb) const {
252 return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
253 }
254
255 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
256 return Indexes->getMBBFromIndex(index);
257 }
258
259 void insertMBBInMaps(MachineBasicBlock *MBB) {
260 Indexes->insertMBBInMaps(MBB);
261 assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&(static_cast <bool> (unsigned(MBB->getNumber()) == RegMaskBlocks
.size() && "Blocks must be added in order.") ? void (
0) : __assert_fail ("unsigned(MBB->getNumber()) == RegMaskBlocks.size() && \"Blocks must be added in order.\""
, "llvm/include/llvm/CodeGen/LiveIntervals.h", 262, __extension__
__PRETTY_FUNCTION__))
262 "Blocks must be added in order.")(static_cast <bool> (unsigned(MBB->getNumber()) == RegMaskBlocks
.size() && "Blocks must be added in order.") ? void (
0) : __assert_fail ("unsigned(MBB->getNumber()) == RegMaskBlocks.size() && \"Blocks must be added in order.\""
, "llvm/include/llvm/CodeGen/LiveIntervals.h", 262, __extension__
__PRETTY_FUNCTION__))
;
263 RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
264 }
265
266 SlotIndex InsertMachineInstrInMaps(MachineInstr &MI) {
267 return Indexes->insertMachineInstrInMaps(MI);
268 }
269
270 void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B,
271 MachineBasicBlock::iterator E) {
272 for (MachineBasicBlock::iterator I = B; I != E; ++I)
273 Indexes->insertMachineInstrInMaps(*I);
274 }
275
276 void RemoveMachineInstrFromMaps(MachineInstr &MI) {
277 Indexes->removeMachineInstrFromMaps(MI);
278 }
279
280 SlotIndex ReplaceMachineInstrInMaps(MachineInstr &MI, MachineInstr &NewMI) {
281 return Indexes->replaceMachineInstrInMaps(MI, NewMI);
282 }
283
284 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
285
286 void getAnalysisUsage(AnalysisUsage &AU) const override;
287 void releaseMemory() override;
288
289 /// Pass entry point; Calculates LiveIntervals.
290 bool runOnMachineFunction(MachineFunction&) override;
291
292 /// Implement the dump method.
293 void print(raw_ostream &O, const Module* = nullptr) const override;
294
295 /// If LI is confined to a single basic block, return a pointer to that
296 /// block. If LI is live in to or out of any block, return NULL.
297 MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
298
299 /// Returns true if VNI is killed by any PHI-def values in LI.
300 /// This may conservatively return true to avoid expensive computations.
301 bool hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const;
302
303 /// Add kill flags to any instruction that kills a virtual register.
304 void addKillFlags(const VirtRegMap*);
305
306 /// Call this method to notify LiveIntervals that instruction \p MI has been
307 /// moved within a basic block. This will update the live intervals for all
308 /// operands of \p MI. Moves between basic blocks are not supported.
309 ///
310 /// \param UpdateFlags Update live intervals for nonallocatable physregs.
311 void handleMove(MachineInstr &MI, bool UpdateFlags = false);
312
313 /// Update intervals of operands of all instructions in the newly
314 /// created bundle specified by \p BundleStart.
315 ///
316 /// \param UpdateFlags Update live intervals for nonallocatable physregs.
317 ///
318 /// Assumes existing liveness is accurate.
319 /// \pre BundleStart should be the first instruction in the Bundle.
320 /// \pre BundleStart should not have a have SlotIndex as one will be assigned.
321 void handleMoveIntoNewBundle(MachineInstr &BundleStart,
322 bool UpdateFlags = false);
323
324 /// Update live intervals for instructions in a range of iterators. It is
325 /// intended for use after target hooks that may insert or remove
326 /// instructions, and is only efficient for a small number of instructions.
327 ///
328 /// OrigRegs is a vector of registers that were originally used by the
329 /// instructions in the range between the two iterators.
330 ///
331 /// Currently, the only only changes that are supported are simple removal
332 /// and addition of uses.
333 void repairIntervalsInRange(MachineBasicBlock *MBB,
334 MachineBasicBlock::iterator Begin,
335 MachineBasicBlock::iterator End,
336 ArrayRef<Register> OrigRegs);
337
338 // Register mask functions.
339 //
340 // Machine instructions may use a register mask operand to indicate that a
341 // large number of registers are clobbered by the instruction. This is
342 // typically used for calls.
343 //
344 // For compile time performance reasons, these clobbers are not recorded in
345 // the live intervals for individual physical registers. Instead,
346 // LiveIntervalAnalysis maintains a sorted list of instructions with
347 // register mask operands.
348
349 /// Returns a sorted array of slot indices of all instructions with
350 /// register mask operands.
351 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
352
353 /// Returns a sorted array of slot indices of all instructions with register
354 /// mask operands in the basic block numbered \p MBBNum.
355 ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
356 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
357 return getRegMaskSlots().slice(P.first, P.second);
358 }
359
360 /// Returns an array of register mask pointers corresponding to
361 /// getRegMaskSlots().
362 ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
363
364 /// Returns an array of mask pointers corresponding to
365 /// getRegMaskSlotsInBlock(MBBNum).
366 ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
367 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
368 return getRegMaskBits().slice(P.first, P.second);
369 }
370
371 /// Test if \p LI is live across any register mask instructions, and
372 /// compute a bit mask of physical registers that are not clobbered by any
373 /// of them.
374 ///
375 /// Returns false if \p LI doesn't cross any register mask instructions. In
376 /// that case, the bit vector is not filled in.
377 bool checkRegMaskInterference(LiveInterval &LI,
378 BitVector &UsableRegs);
379
380 // Register unit functions.
381 //
382 // Fixed interference occurs when MachineInstrs use physregs directly
383 // instead of virtual registers. This typically happens when passing
384 // arguments to a function call, or when instructions require operands in
385 // fixed registers.
386 //
387 // Each physreg has one or more register units, see MCRegisterInfo. We
388 // track liveness per register unit to handle aliasing registers more
389 // efficiently.
390
391 /// Return the live range for register unit \p Unit. It will be computed if
392 /// it doesn't exist.
393 LiveRange &getRegUnit(unsigned Unit) {
394 LiveRange *LR = RegUnitRanges[Unit];
395 if (!LR) {
396 // Compute missing ranges on demand.
397 // Use segment set to speed-up initial computation of the live range.
398 RegUnitRanges[Unit] = LR = new LiveRange(UseSegmentSetForPhysRegs);
399 computeRegUnitRange(*LR, Unit);
400 }
401 return *LR;
402 }
403
404 /// Return the live range for register unit \p Unit if it has already been
405 /// computed, or nullptr if it hasn't been computed yet.
406 LiveRange *getCachedRegUnit(unsigned Unit) {
407 return RegUnitRanges[Unit];
408 }
409
410 const LiveRange *getCachedRegUnit(unsigned Unit) const {
411 return RegUnitRanges[Unit];
412 }
413
414 /// Remove computed live range for register unit \p Unit. Subsequent uses
415 /// should rely on on-demand recomputation.
416 void removeRegUnit(unsigned Unit) {
417 delete RegUnitRanges[Unit];
418 RegUnitRanges[Unit] = nullptr;
419 }
420
421 /// Remove associated live ranges for the register units associated with \p
422 /// Reg. Subsequent uses should rely on on-demand recomputation. \note This
423 /// method can result in inconsistent liveness tracking if multiple phyical
424 /// registers share a regunit, and should be used cautiously.
425 void removeAllRegUnitsForPhysReg(MCRegister Reg) {
426 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
427 removeRegUnit(*Units);
428 }
429
430 /// Remove value numbers and related live segments starting at position
431 /// \p Pos that are part of any liverange of physical register \p Reg or one
432 /// of its subregisters.
433 void removePhysRegDefAt(MCRegister Reg, SlotIndex Pos);
434
435 /// Remove value number and related live segments of \p LI and its subranges
436 /// that start at position \p Pos.
437 void removeVRegDefAt(LiveInterval &LI, SlotIndex Pos);
438
439 /// Split separate components in LiveInterval \p LI into separate intervals.
440 void splitSeparateComponents(LiveInterval &LI,
441 SmallVectorImpl<LiveInterval*> &SplitLIs);
442
443 /// For live interval \p LI with correct SubRanges construct matching
444 /// information for the main live range. Expects the main live range to not
445 /// have any segments or value numbers.
446 void constructMainRangeFromSubranges(LiveInterval &LI);
447
448 private:
449 /// Compute live intervals for all virtual registers.
450 void computeVirtRegs();
451
452 /// Compute RegMaskSlots and RegMaskBits.
453 void computeRegMasks();
454
455 /// Walk the values in \p LI and check for dead values:
456 /// - Dead PHIDef values are marked as unused.
457 /// - Dead operands are marked as such.
458 /// - Completely dead machine instructions are added to the \p dead vector
459 /// if it is not nullptr.
460 /// Returns true if any PHI value numbers have been removed which may
461 /// have separated the interval into multiple connected components.
462 bool computeDeadValues(LiveInterval &LI,
463 SmallVectorImpl<MachineInstr*> *dead);
464
465 static LiveInterval *createInterval(Register Reg);
466
467 void printInstrs(raw_ostream &O) const;
468 void dumpInstrs() const;
469
470 void computeLiveInRegUnits();
471 void computeRegUnitRange(LiveRange&, unsigned Unit);
472 bool computeVirtRegInterval(LiveInterval&);
473
474 using ShrinkToUsesWorkList = SmallVector<std::pair<SlotIndex, VNInfo*>, 16>;
475 void extendSegmentsToUses(LiveRange &Segments,
476 ShrinkToUsesWorkList &WorkList, Register Reg,
477 LaneBitmask LaneMask);
478
479 /// Helper function for repairIntervalsInRange(), walks backwards and
480 /// creates/modifies live segments in \p LR to match the operands found.
481 /// Only full operands or operands with subregisters matching \p LaneMask
482 /// are considered.
483 void repairOldRegInRange(MachineBasicBlock::iterator Begin,
484 MachineBasicBlock::iterator End,
485 const SlotIndex endIdx, LiveRange &LR,
486 Register Reg,
487 LaneBitmask LaneMask = LaneBitmask::getAll());
488
489 class HMEditor;
490 };
491
492} // end namespace llvm
493
494#endif

/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/include/llvm/CodeGen/Register.h

1//===-- llvm/CodeGen/Register.h ---------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_CODEGEN_REGISTER_H
10#define LLVM_CODEGEN_REGISTER_H
11
12#include "llvm/MC/MCRegister.h"
13#include <cassert>
14
15namespace llvm {
16
17/// Wrapper class representing virtual and physical registers. Should be passed
18/// by value.
19class Register {
20 unsigned Reg;
21
22public:
23 constexpr Register(unsigned Val = 0): Reg(Val) {}
24 constexpr Register(MCRegister Val): Reg(Val) {}
25
26 // Register numbers can represent physical registers, virtual registers, and
27 // sometimes stack slots. The unsigned values are divided into these ranges:
28 //
29 // 0 Not a register, can be used as a sentinel.
30 // [1;2^30) Physical registers assigned by TableGen.
31 // [2^30;2^31) Stack slots. (Rarely used.)
32 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
33 //
34 // Further sentinels can be allocated from the small negative integers.
35 // DenseMapInfo<unsigned> uses -1u and -2u.
36 static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF,
37 "Reg isn't large enough to hold full range.");
38
39 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
40 /// frame index in a variable that normally holds a register. isStackSlot()
41 /// returns true if Reg is in the range used for stack slots.
42 ///
43 /// FIXME: remove in favor of member.
44 static bool isStackSlot(unsigned Reg) {
45 return MCRegister::isStackSlot(Reg);
46 }
47
48 /// Return true if this is a stack slot.
49 bool isStack() const { return MCRegister::isStackSlot(Reg); }
50
51 /// Compute the frame index from a register value representing a stack slot.
52 static int stackSlot2Index(Register Reg) {
53 assert(Reg.isStack() && "Not a stack slot")(static_cast <bool> (Reg.isStack() && "Not a stack slot"
) ? void (0) : __assert_fail ("Reg.isStack() && \"Not a stack slot\""
, "llvm/include/llvm/CodeGen/Register.h", 53, __extension__ __PRETTY_FUNCTION__
))
;
54 return int(Reg - MCRegister::FirstStackSlot);
55 }
56
57 /// Convert a non-negative frame index to a stack slot register value.
58 static Register index2StackSlot(int FI) {
59 assert(FI >= 0 && "Cannot hold a negative frame index.")(static_cast <bool> (FI >= 0 && "Cannot hold a negative frame index."
) ? void (0) : __assert_fail ("FI >= 0 && \"Cannot hold a negative frame index.\""
, "llvm/include/llvm/CodeGen/Register.h", 59, __extension__ __PRETTY_FUNCTION__
))
;
60 return Register(FI + MCRegister::FirstStackSlot);
61 }
62
63 /// Return true if the specified register number is in
64 /// the physical register namespace.
65 static bool isPhysicalRegister(unsigned Reg) {
66 return MCRegister::isPhysicalRegister(Reg);
67 }
68
69 /// Return true if the specified register number is in
70 /// the virtual register namespace.
71 static bool isVirtualRegister(unsigned Reg) {
72 return Reg & MCRegister::VirtualRegFlag && !isStackSlot(Reg);
37
Assuming the condition is true
38
Returning the value 1, which participates in a condition later
73 }
74
75 /// Convert a virtual register number to a 0-based index.
76 /// The first virtual register in a function will get the index 0.
77 static unsigned virtReg2Index(Register Reg) {
78 assert(isVirtualRegister(Reg) && "Not a virtual register")(static_cast <bool> (isVirtualRegister(Reg) && "Not a virtual register"
) ? void (0) : __assert_fail ("isVirtualRegister(Reg) && \"Not a virtual register\""
, "llvm/include/llvm/CodeGen/Register.h", 78, __extension__ __PRETTY_FUNCTION__
))
;
79 return Reg & ~MCRegister::VirtualRegFlag;
80 }
81
82 /// Convert a 0-based index to a virtual register number.
83 /// This is the inverse operation of VirtReg2IndexFunctor below.
84 static Register index2VirtReg(unsigned Index) {
85 assert(Index < (1u << 31) && "Index too large for virtual register range.")(static_cast <bool> (Index < (1u << 31) &&
"Index too large for virtual register range.") ? void (0) : __assert_fail
("Index < (1u << 31) && \"Index too large for virtual register range.\""
, "llvm/include/llvm/CodeGen/Register.h", 85, __extension__ __PRETTY_FUNCTION__
))
;
86 return Index | MCRegister::VirtualRegFlag;
87 }
88
89 /// Return true if the specified register number is in the virtual register
90 /// namespace.
91 bool isVirtual() const {
92 return isVirtualRegister(Reg);
36
Calling 'Register::isVirtualRegister'
39
Returning from 'Register::isVirtualRegister'
40
Returning the value 1, which participates in a condition later
93 }
94
95 /// Return true if the specified register number is in the physical register
96 /// namespace.
97 bool isPhysical() const {
98 return isPhysicalRegister(Reg);
99 }
100
101 /// Convert a virtual register number to a 0-based index. The first virtual
102 /// register in a function will get the index 0.
103 unsigned virtRegIndex() const {
104 return virtReg2Index(Reg);
105 }
106
107 constexpr operator unsigned() const {
108 return Reg;
109 }
110
111 unsigned id() const { return Reg; }
112
113 operator MCRegister() const {
114 return MCRegister(Reg);
115 }
116
117 /// Utility to check-convert this value to a MCRegister. The caller is
118 /// expected to have already validated that this Register is, indeed,
119 /// physical.
120 MCRegister asMCReg() const {
121 assert(Reg == MCRegister::NoRegister ||(static_cast <bool> (Reg == MCRegister::NoRegister || MCRegister
::isPhysicalRegister(Reg)) ? void (0) : __assert_fail ("Reg == MCRegister::NoRegister || MCRegister::isPhysicalRegister(Reg)"
, "llvm/include/llvm/CodeGen/Register.h", 122, __extension__ __PRETTY_FUNCTION__
))
122 MCRegister::isPhysicalRegister(Reg))(static_cast <bool> (Reg == MCRegister::NoRegister || MCRegister
::isPhysicalRegister(Reg)) ? void (0) : __assert_fail ("Reg == MCRegister::NoRegister || MCRegister::isPhysicalRegister(Reg)"
, "llvm/include/llvm/CodeGen/Register.h", 122, __extension__ __PRETTY_FUNCTION__
))
;
123 return MCRegister(Reg);
124 }
125
126 bool isValid() const { return Reg != MCRegister::NoRegister; }
127
128 /// Comparisons between register objects
129 bool operator==(const Register &Other) const { return Reg == Other.Reg; }
130 bool operator!=(const Register &Other) const { return Reg != Other.Reg; }
131 bool operator==(const MCRegister &Other) const { return Reg == Other.id(); }
132 bool operator!=(const MCRegister &Other) const { return Reg != Other.id(); }
133
134 /// Comparisons against register constants. E.g.
135 /// * R == AArch64::WZR
136 /// * R == 0
137 /// * R == VirtRegMap::NO_PHYS_REG
138 bool operator==(unsigned Other) const { return Reg == Other; }
139 bool operator!=(unsigned Other) const { return Reg != Other; }
140 bool operator==(int Other) const { return Reg == unsigned(Other); }
141 bool operator!=(int Other) const { return Reg != unsigned(Other); }
142 // MSVC requires that we explicitly declare these two as well.
143 bool operator==(MCPhysReg Other) const { return Reg == unsigned(Other); }
144 bool operator!=(MCPhysReg Other) const { return Reg != unsigned(Other); }
145};
146
147// Provide DenseMapInfo for Register
148template<> struct DenseMapInfo<Register> {
149 static inline unsigned getEmptyKey() {
150 return DenseMapInfo<unsigned>::getEmptyKey();
151 }
152 static inline unsigned getTombstoneKey() {
153 return DenseMapInfo<unsigned>::getTombstoneKey();
154 }
155 static unsigned getHashValue(const Register &Val) {
156 return DenseMapInfo<unsigned>::getHashValue(Val.id());
157 }
158 static bool isEqual(const Register &LHS, const Register &RHS) {
159 return DenseMapInfo<unsigned>::isEqual(LHS.id(), RHS.id());
160 }
161};
162
163}
164
165#endif // LLVM_CODEGEN_REGISTER_H