/build/source/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Bug Summary

File:	build/source/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
Warning:	line 4018, column 31 The left operand of '==' is a garbage value
Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name MipsAsmParser.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-17/lib/clang/17 -D _DEBUG -D _GLIBCXX_ASSERTIONS -D _GNU_SOURCE -D _LIBCPP_ENABLE_ASSERTIONS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/Mips/AsmParser -I /build/source/llvm/lib/Target/Mips/AsmParser -I /build/source/llvm/lib/Target/Mips -I lib/Target/Mips -I include -I /build/source/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-17/lib/clang/17/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/source/= -fcoverage-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/source/= -source-date-epoch 1683717183 -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/source/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/source/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2023-05-10-133810-16478-1 -x c++ /build/source/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
1//===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//

9#include "MCTargetDesc/MipsABIFlagsSection.h"
10#include "MCTargetDesc/MipsABIInfo.h"
11#include "MCTargetDesc/MipsBaseInfo.h"
12#include "MCTargetDesc/MipsMCExpr.h"
13#include "MCTargetDesc/MipsMCTargetDesc.h"
14#include "MipsTargetStreamer.h"
15#include "TargetInfo/MipsTargetInfo.h"
16#include "llvm/ADT/APFloat.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/ADT/StringSwitch.h"
21#include "llvm/ADT/Twine.h"
22#include "llvm/BinaryFormat/ELF.h"
23#include "llvm/MC/MCContext.h"
24#include "llvm/MC/MCExpr.h"
25#include "llvm/MC/MCInst.h"
26#include "llvm/MC/MCInstrDesc.h"
27#include "llvm/MC/MCInstrInfo.h"
28#include "llvm/MC/MCObjectFileInfo.h"
29#include "llvm/MC/MCParser/MCAsmLexer.h"
30#include "llvm/MC/MCParser/MCAsmParser.h"
31#include "llvm/MC/MCParser/MCAsmParserExtension.h"
32#include "llvm/MC/MCParser/MCAsmParserUtils.h"
33#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34#include "llvm/MC/MCParser/MCTargetAsmParser.h"
35#include "llvm/MC/MCSectionELF.h"
36#include "llvm/MC/MCStreamer.h"
37#include "llvm/MC/MCSubtargetInfo.h"
38#include "llvm/MC/MCSymbol.h"
39#include "llvm/MC/MCSymbolELF.h"
40#include "llvm/MC/MCValue.h"
41#include "llvm/MC/SubtargetFeature.h"
42#include "llvm/MC/TargetRegistry.h"
43#include "llvm/Support/Alignment.h"
44#include "llvm/Support/Casting.h"
45#include "llvm/Support/CommandLine.h"
46#include "llvm/Support/Compiler.h"
47#include "llvm/Support/Debug.h"
48#include "llvm/Support/ErrorHandling.h"
49#include "llvm/Support/MathExtras.h"
50#include "llvm/Support/SMLoc.h"
51#include "llvm/Support/SourceMgr.h"
52#include "llvm/Support/raw_ostream.h"
53#include "llvm/TargetParser/Triple.h"
54#include <algorithm>
55#include <cassert>
56#include <cstdint>
57#include <memory>
58#include <string>
59#include <utility>

61using namespace llvm;

63#define DEBUG_TYPE"mips-asm-parser" "mips-asm-parser"

65namespace llvm {

67class MCInstrInfo;

69} // end namespace llvm

71extern cl::opt<bool> EmitJalrReloc;

73namespace {

75class MipsAssemblerOptions {
76public:
MipsAssemblerOptions(const FeatureBitset &Features_) : Features(Features_) {}

MipsAssemblerOptions(const MipsAssemblerOptions *Opts) {
  ATReg = Opts->getATRegIndex();
  Reorder = Opts->isReorder();
  Macro = Opts->isMacro();
  Features = Opts->getFeatures();
}

unsigned getATRegIndex() const { return ATReg; }
bool setATRegIndex(unsigned Reg) {
  if (Reg > 31)
    return false;

  ATReg = Reg;
  return true;
}

bool isReorder() const { return Reorder; }
void setReorder() { Reorder = true; }
void setNoReorder() { Reorder = false; }

bool isMacro() const { return Macro; }
void setMacro() { Macro = true; }
void setNoMacro() { Macro = false; }

const FeatureBitset &getFeatures() const { return Features; }
void setFeatures(const FeatureBitset &Features_) { Features = Features_; }

// Set of features that are either architecture features or referenced
// by them (e.g.: FeatureNaN2008 implied by FeatureMips32r6).
// The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]).
// The reason we need this mask is explained in the selectArch function.
// FIXME: Ideally we would like TableGen to generate this information.
static const FeatureBitset AllArchRelatedMask;

113private:
unsigned ATReg = 1;
bool Reorder = true;
bool Macro = true;
FeatureBitset Features;
118};

120} // end anonymous namespace

122const FeatureBitset MipsAssemblerOptions::AllArchRelatedMask = {
  Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
  Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
  Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
  Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
  Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
  Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
  Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
  Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
  Mips::FeatureNaN2008
132};

134namespace {

136class MipsAsmParser : public MCTargetAsmParser {
MipsTargetStreamer &getTargetStreamer() {
  assert(getParser().getStreamer().getTargetStreamer() &&(static_cast <bool> (getParser().getStreamer().getTargetStreamer
() && "do not have a target streamer") ? void (0) : __assert_fail
 ("getParser().getStreamer().getTargetStreamer() && \"do not have a target streamer\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 139, __extension__
 __PRETTY_FUNCTION__))
         "do not have a target streamer")(static_cast <bool> (getParser().getStreamer().getTargetStreamer
() && "do not have a target streamer") ? void (0) : __assert_fail
 ("getParser().getStreamer().getTargetStreamer() && \"do not have a target streamer\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 139, __extension__
 __PRETTY_FUNCTION__));
  MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
  return static_cast<MipsTargetStreamer &>(TS);
}

MipsABIInfo ABI;
SmallVector<std::unique_ptr<MipsAssemblerOptions>, 2> AssemblerOptions;
MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a
                     // nullptr, which indicates that no function is currently
                     // selected. This usually happens after an '.end func'
                     // directive.
bool IsLittleEndian;
bool IsPicEnabled;
bool IsCpRestoreSet;
int CpRestoreOffset;
unsigned GPReg;
unsigned CpSaveLocation;
/// If true, then CpSaveLocation is a register, otherwise it's an offset.
bool     CpSaveLocationIsRegister;

// Map of register aliases created via the .set directive.
StringMap<AsmToken> RegisterSets;

// Print a warning along with its fix-it message at the given range.
void printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg,
                           SMRange Range, bool ShowColors = true);

void ConvertXWPOperands(MCInst &Inst, const OperandVector &Operands);

168#define GET_ASSEMBLER_HEADER
169#include "MipsGenAsmMatcher.inc"

unsigned
checkEarlyTargetMatchPredicate(MCInst &Inst,
                               const OperandVector &Operands) override;
unsigned checkTargetMatchPredicate(MCInst &Inst) override;

bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                             OperandVector &Operands, MCStreamer &Out,
                             uint64_t &ErrorInfo,
                             bool MatchingInlineAsm) override;

/// Parse a register as used in CFI directives
bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
                   SMLoc &EndLoc) override;
OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
                                      SMLoc &EndLoc) override;

bool parseParenSuffix(StringRef Name, OperandVector &Operands);

bool parseBracketSuffix(StringRef Name, OperandVector &Operands);

bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);

bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                      SMLoc NameLoc, OperandVector &Operands) override;

bool ParseDirective(AsmToken DirectiveID) override;

OperandMatchResultTy parseMemOperand(OperandVector &Operands);
OperandMatchResultTy
matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
                                  StringRef Identifier, SMLoc S);
OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
                                                   const AsmToken &Token,
                                                   SMLoc S);
OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
                                                   SMLoc S);
OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
OperandMatchResultTy parseImm(OperandVector &Operands);
OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
OperandMatchResultTy parseInvNum(OperandVector &Operands);
OperandMatchResultTy parseRegisterList(OperandVector &Operands);

bool searchSymbolAlias(OperandVector &Operands);

bool parseOperand(OperandVector &, StringRef Mnemonic);

enum MacroExpanderResultTy {
  MER_NotAMacro,
  MER_Success,
  MER_Fail,
};

// Expands assembly pseudo instructions.
MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
                                           MCStreamer &Out,
                                           const MCSubtargetInfo *STI);

bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                       const MCSubtargetInfo *STI);

bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
                   bool Is32BitImm, bool IsAddress, SMLoc IDLoc,
                   MCStreamer &Out, const MCSubtargetInfo *STI);

bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
                             unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
                             MCStreamer &Out, const MCSubtargetInfo *STI);

bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym);

bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
                   MCStreamer &Out, const MCSubtargetInfo *STI);

bool expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                              const MCSubtargetInfo *STI);
bool expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                              const MCSubtargetInfo *STI);
bool expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                              const MCSubtargetInfo *STI);
bool expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc,
                              MCStreamer &Out, const MCSubtargetInfo *STI);

bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
                       const MCOperand &Offset, bool Is32BitAddress,
                       SMLoc IDLoc, MCStreamer &Out,
                       const MCSubtargetInfo *STI);

bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                const MCSubtargetInfo *STI);

void expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                     const MCSubtargetInfo *STI, bool IsLoad);
void expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                    const MCSubtargetInfo *STI, bool IsLoad);

bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                             const MCSubtargetInfo *STI);

bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                          const MCSubtargetInfo *STI);

bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                     const MCSubtargetInfo *STI);

bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                        const MCSubtargetInfo *STI);

bool expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                  const MCSubtargetInfo *STI, const bool IsMips64,
                  const bool Signed);

bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
                 MCStreamer &Out, const MCSubtargetInfo *STI);

bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out,
               const MCSubtargetInfo *STI);

bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
               const MCSubtargetInfo *STI);

bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
               const MCSubtargetInfo *STI);

bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
               const MCSubtargetInfo *STI);

bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                  const MCSubtargetInfo *STI);

bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                  const MCSubtargetInfo *STI);

bool expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
               const MCSubtargetInfo *STI);

bool expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                  const MCSubtargetInfo *STI);

bool expandRotation(MCInst &Inst, SMLoc IDLoc,
                    MCStreamer &Out, const MCSubtargetInfo *STI);
bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                       const MCSubtargetInfo *STI);
bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                     const MCSubtargetInfo *STI);
bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                        const MCSubtargetInfo *STI);

bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
               const MCSubtargetInfo *STI);

bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                  const MCSubtargetInfo *STI);

bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                const MCSubtargetInfo *STI);

bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                 const MCSubtargetInfo *STI);

bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                     const MCSubtargetInfo *STI);

bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                           const MCSubtargetInfo *STI, bool IsLoad);

bool expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                         const MCSubtargetInfo *STI);

bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
               const MCSubtargetInfo *STI);

bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                const MCSubtargetInfo *STI);

bool expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
               const MCSubtargetInfo *STI);

bool expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                const MCSubtargetInfo *STI);

bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                     const MCSubtargetInfo *STI);

bool expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                   const MCSubtargetInfo *STI);

bool reportParseError(const Twine &ErrorMsg);
bool reportParseError(SMLoc Loc, const Twine &ErrorMsg);

bool parseMemOffset(const MCExpr *&Res, bool isParenExpr);

bool parseSetMips0Directive();
bool parseSetArchDirective();
bool parseSetFeature(uint64_t Feature);
bool isPicAndNotNxxAbi(); // Used by .cpload, .cprestore, and .cpsetup.
bool parseDirectiveCpAdd(SMLoc Loc);
bool parseDirectiveCpLoad(SMLoc Loc);
bool parseDirectiveCpLocal(SMLoc Loc);
bool parseDirectiveCpRestore(SMLoc Loc);
bool parseDirectiveCPSetup();
bool parseDirectiveCPReturn();
bool parseDirectiveNaN();
bool parseDirectiveSet();
bool parseDirectiveOption();
bool parseInsnDirective();
bool parseRSectionDirective(StringRef Section);
bool parseSSectionDirective(StringRef Section, unsigned Type);

bool parseSetAtDirective();
bool parseSetNoAtDirective();
bool parseSetMacroDirective();
bool parseSetNoMacroDirective();
bool parseSetMsaDirective();
bool parseSetNoMsaDirective();
bool parseSetNoDspDirective();
bool parseSetNoMips3DDirective();
bool parseSetReorderDirective();
bool parseSetNoReorderDirective();
bool parseSetMips16Directive();
bool parseSetNoMips16Directive();
bool parseSetFpDirective();
bool parseSetOddSPRegDirective();
bool parseSetNoOddSPRegDirective();
bool parseSetPopDirective();
bool parseSetPushDirective();
bool parseSetSoftFloatDirective();
bool parseSetHardFloatDirective();
bool parseSetMtDirective();
bool parseSetNoMtDirective();
bool parseSetNoCRCDirective();
bool parseSetNoVirtDirective();
bool parseSetNoGINVDirective();

bool parseSetAssignment();

bool parseDirectiveGpWord();
bool parseDirectiveGpDWord();
bool parseDirectiveDtpRelWord();
bool parseDirectiveDtpRelDWord();
bool parseDirectiveTpRelWord();
bool parseDirectiveTpRelDWord();
bool parseDirectiveModule();
bool parseDirectiveModuleFP();
bool parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI,
                     StringRef Directive);

bool parseInternalDirectiveReallowModule();

bool eatComma(StringRef ErrorStr);

int matchCPURegisterName(StringRef Symbol);

int matchHWRegsRegisterName(StringRef Symbol);

int matchFPURegisterName(StringRef Name);

int matchFCCRegisterName(StringRef Name);

int matchACRegisterName(StringRef Name);

int matchMSA128RegisterName(StringRef Name);

int matchMSA128CtrlRegisterName(StringRef Name);

unsigned getReg(int RC, int RegNo);

/// Returns the internal register number for the current AT. Also checks if
/// the current AT is unavailable (set to $0) and gives an error if it is.
/// This should be used in pseudo-instruction expansions which need AT.
unsigned getATReg(SMLoc Loc);

bool canUseATReg();

bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                        const MCSubtargetInfo *STI);

// Helper function that checks if the value of a vector index is within the
// boundaries of accepted values for each RegisterKind
// Example: INSERT.B $w0[n], $1 => 16 > n >= 0
bool validateMSAIndex(int Val, int RegKind);

// Selects a new architecture by updating the FeatureBits with the necessary
// info including implied dependencies.
// Internally, it clears all the feature bits related to *any* architecture
// and selects the new one using the ToggleFeature functionality of the
// MCSubtargetInfo object that handles implied dependencies. The reason we
// clear all the arch related bits manually is because ToggleFeature only
// clears the features that imply the feature being cleared and not the
// features implied by the feature being cleared. This is easier to see
// with an example:
//  --------------------------------------------------
// | Feature         | Implies                        |
// | -------------------------------------------------|
// | FeatureMips1    | None                           |
// | FeatureMips2    | FeatureMips1                   |
// | FeatureMips3    | FeatureMips2 | FeatureMipsGP64 |
// | FeatureMips4    | FeatureMips3                   |
// | ...             |                                |
//  --------------------------------------------------
//
// Setting Mips3 is equivalent to set: (FeatureMips3 | FeatureMips2 |
// FeatureMipsGP64 | FeatureMips1)
// Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4).
void selectArch(StringRef ArchFeature) {
  MCSubtargetInfo &STI = copySTI();
  FeatureBitset FeatureBits = STI.getFeatureBits();
  FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask;
  STI.setFeatureBits(FeatureBits);
  setAvailableFeatures(
      ComputeAvailableFeatures(STI.ToggleFeature(ArchFeature)));
  AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
}

void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
  if (!(getSTI().hasFeature(Feature))) {
    MCSubtargetInfo &STI = copySTI();
    setAvailableFeatures(
        ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
    AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
  }
}

void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
  if (getSTI().hasFeature(Feature)) {
    MCSubtargetInfo &STI = copySTI();
    setAvailableFeatures(
        ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
    AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
  }
}

void setModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
  setFeatureBits(Feature, FeatureString);
  AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
}

void clearModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
  clearFeatureBits(Feature, FeatureString);
  AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
}

512public:
enum MipsMatchResultTy {
  Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY,
  Match_RequiresDifferentOperands,
  Match_RequiresNoZeroRegister,
  Match_RequiresSameSrcAndDst,
  Match_NoFCCRegisterForCurrentISA,
  Match_NonZeroOperandForSync,
  Match_NonZeroOperandForMTCX,
  Match_RequiresPosSizeRange0_32,
  Match_RequiresPosSizeRange33_64,
  Match_RequiresPosSizeUImm6,
524#define GET_OPERAND_DIAGNOSTIC_TYPES
525#include "MipsGenAsmMatcher.inc"
526#undef GET_OPERAND_DIAGNOSTIC_TYPES
};

MipsAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
              const MCInstrInfo &MII, const MCTargetOptions &Options)
  : MCTargetAsmParser(Options, sti, MII),
      ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
                                        sti.getCPU(), Options)) {
  MCAsmParserExtension::Initialize(parser);

  parser.addAliasForDirective(".asciiz", ".asciz");
  parser.addAliasForDirective(".hword", ".2byte");
  parser.addAliasForDirective(".word", ".4byte");
  parser.addAliasForDirective(".dword", ".8byte");

  // Initialize the set of available features.
  setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));

  // Remember the initial assembler options. The user can not modify these.
  AssemblerOptions.push_back(
      std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));

  // Create an assembler options environment for the user to modify.
  AssemblerOptions.push_back(
      std::make_unique<MipsAssemblerOptions>(getSTI().getFeatureBits()));

  getTargetStreamer().updateABIInfo(*this);

  if (!isABI_O32() && !useOddSPReg() != 0)
    report_fatal_error("-mno-odd-spreg requires the O32 ABI");

  CurrentFn = nullptr;

  IsPicEnabled = getContext().getObjectFileInfo()->isPositionIndependent();

  IsCpRestoreSet = false;
  CpRestoreOffset = -1;
  GPReg = ABI.GetGlobalPtr();

  const Triple &TheTriple = sti.getTargetTriple();
  IsLittleEndian = TheTriple.isLittleEndian();

  if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode())
    report_fatal_error("microMIPS64R6 is not supported", false);

  if (!isABI_O32() && inMicroMipsMode())
    report_fatal_error("microMIPS64 is not supported", false);
}

/// True if all of $fcc0 - $fcc7 exist for the current ISA.
bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }

bool isGP64bit() const {
  return getSTI().hasFeature(Mips::FeatureGP64Bit);
}

bool isFP64bit() const {
  return getSTI().hasFeature(Mips::FeatureFP64Bit);
}

bool isJalrRelocAvailable(const MCExpr *JalExpr) {
  if (!EmitJalrReloc)
    return false;
  MCValue Res;
  if (!JalExpr->evaluateAsRelocatable(Res, nullptr, nullptr))
    return false;
  if (Res.getSymB() != nullptr)
    return false;
  if (Res.getConstant() != 0)
    return ABI.IsN32() || ABI.IsN64();
  return true;
}

const MipsABIInfo &getABI() const { return ABI; }
bool isABI_N32() const { return ABI.IsN32(); }
bool isABI_N64() const { return ABI.IsN64(); }
bool isABI_O32() const { return ABI.IsO32(); }
bool isABI_FPXX() const {
  return getSTI().hasFeature(Mips::FeatureFPXX);
}

bool useOddSPReg() const {
  return !(getSTI().hasFeature(Mips::FeatureNoOddSPReg));
}

bool inMicroMipsMode() const {
  return getSTI().hasFeature(Mips::FeatureMicroMips);
}

bool hasMips1() const {
  return getSTI().hasFeature(Mips::FeatureMips1);
}

bool hasMips2() const {
  return getSTI().hasFeature(Mips::FeatureMips2);
}

bool hasMips3() const {
  return getSTI().hasFeature(Mips::FeatureMips3);
}

bool hasMips4() const {
  return getSTI().hasFeature(Mips::FeatureMips4);
}

bool hasMips5() const {
  return getSTI().hasFeature(Mips::FeatureMips5);
}

bool hasMips32() const {
  return getSTI().hasFeature(Mips::FeatureMips32);
}

bool hasMips64() const {
  return getSTI().hasFeature(Mips::FeatureMips64);
}

bool hasMips32r2() const {
  return getSTI().hasFeature(Mips::FeatureMips32r2);
}

bool hasMips64r2() const {
  return getSTI().hasFeature(Mips::FeatureMips64r2);
}

bool hasMips32r3() const {
  return (getSTI().hasFeature(Mips::FeatureMips32r3));
}

bool hasMips64r3() const {
  return (getSTI().hasFeature(Mips::FeatureMips64r3));
}

bool hasMips32r5() const {
  return (getSTI().hasFeature(Mips::FeatureMips32r5));
}

bool hasMips64r5() const {
  return (getSTI().hasFeature(Mips::FeatureMips64r5));
}

bool hasMips32r6() const {
  return getSTI().hasFeature(Mips::FeatureMips32r6);
}

bool hasMips64r6() const {
  return getSTI().hasFeature(Mips::FeatureMips64r6);
}

bool hasDSP() const {
  return getSTI().hasFeature(Mips::FeatureDSP);
}

bool hasDSPR2() const {
  return getSTI().hasFeature(Mips::FeatureDSPR2);
}

bool hasDSPR3() const {
  return getSTI().hasFeature(Mips::FeatureDSPR3);
}

bool hasMSA() const {
  return getSTI().hasFeature(Mips::FeatureMSA);
}

bool hasCnMips() const {
  return (getSTI().hasFeature(Mips::FeatureCnMips));
}

bool hasCnMipsP() const {
  return (getSTI().hasFeature(Mips::FeatureCnMipsP));
}

bool inPicMode() {
  return IsPicEnabled;
}

bool inMips16Mode() const {
  return getSTI().hasFeature(Mips::FeatureMips16);
}

bool useTraps() const {
  return getSTI().hasFeature(Mips::FeatureUseTCCInDIV);
}

bool useSoftFloat() const {
  return getSTI().hasFeature(Mips::FeatureSoftFloat);
}
bool hasMT() const {
  return getSTI().hasFeature(Mips::FeatureMT);
}

bool hasCRC() const {
  return getSTI().hasFeature(Mips::FeatureCRC);
}

bool hasVirt() const {
  return getSTI().hasFeature(Mips::FeatureVirt);
}

bool hasGINV() const {
  return getSTI().hasFeature(Mips::FeatureGINV);
}

/// Warn if RegIndex is the same as the current AT.
void warnIfRegIndexIsAT(unsigned RegIndex, SMLoc Loc);

void warnIfNoMacro(SMLoc Loc);

bool isLittle() const { return IsLittleEndian; }

const MCExpr *createTargetUnaryExpr(const MCExpr *E,
                                    AsmToken::TokenKind OperatorToken,
                                    MCContext &Ctx) override {
  switch(OperatorToken) {
  default:
    llvm_unreachable("Unknown token")::llvm::llvm_unreachable_internal("Unknown token", "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp"
, 742);
    return nullptr;
  case AsmToken::PercentCall16:
    return MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, E, Ctx);
  case AsmToken::PercentCall_Hi:
    return MipsMCExpr::create(MipsMCExpr::MEK_CALL_HI16, E, Ctx);
  case AsmToken::PercentCall_Lo:
    return MipsMCExpr::create(MipsMCExpr::MEK_CALL_LO16, E, Ctx);
  case AsmToken::PercentDtprel_Hi:
    return MipsMCExpr::create(MipsMCExpr::MEK_DTPREL_HI, E, Ctx);
  case AsmToken::PercentDtprel_Lo:
    return MipsMCExpr::create(MipsMCExpr::MEK_DTPREL_LO, E, Ctx);
  case AsmToken::PercentGot:
    return MipsMCExpr::create(MipsMCExpr::MEK_GOT, E, Ctx);
  case AsmToken::PercentGot_Disp:
    return MipsMCExpr::create(MipsMCExpr::MEK_GOT_DISP, E, Ctx);
  case AsmToken::PercentGot_Hi:
    return MipsMCExpr::create(MipsMCExpr::MEK_GOT_HI16, E, Ctx);
  case AsmToken::PercentGot_Lo:
    return MipsMCExpr::create(MipsMCExpr::MEK_GOT_LO16, E, Ctx);
  case AsmToken::PercentGot_Ofst:
    return MipsMCExpr::create(MipsMCExpr::MEK_GOT_OFST, E, Ctx);
  case AsmToken::PercentGot_Page:
    return MipsMCExpr::create(MipsMCExpr::MEK_GOT_PAGE, E, Ctx);
  case AsmToken::PercentGottprel:
    return MipsMCExpr::create(MipsMCExpr::MEK_GOTTPREL, E, Ctx);
  case AsmToken::PercentGp_Rel:
    return MipsMCExpr::create(MipsMCExpr::MEK_GPREL, E, Ctx);
  case AsmToken::PercentHi:
    return MipsMCExpr::create(MipsMCExpr::MEK_HI, E, Ctx);
  case AsmToken::PercentHigher:
    return MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, E, Ctx);
  case AsmToken::PercentHighest:
    return MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, E, Ctx);
  case AsmToken::PercentLo:
    return MipsMCExpr::create(MipsMCExpr::MEK_LO, E, Ctx);
  case AsmToken::PercentNeg:
    return MipsMCExpr::create(MipsMCExpr::MEK_NEG, E, Ctx);
  case AsmToken::PercentPcrel_Hi:
    return MipsMCExpr::create(MipsMCExpr::MEK_PCREL_HI16, E, Ctx);
  case AsmToken::PercentPcrel_Lo:
    return MipsMCExpr::create(MipsMCExpr::MEK_PCREL_LO16, E, Ctx);
  case AsmToken::PercentTlsgd:
    return MipsMCExpr::create(MipsMCExpr::MEK_TLSGD, E, Ctx);
  case AsmToken::PercentTlsldm:
    return MipsMCExpr::create(MipsMCExpr::MEK_TLSLDM, E, Ctx);
  case AsmToken::PercentTprel_Hi:
    return MipsMCExpr::create(MipsMCExpr::MEK_TPREL_HI, E, Ctx);
  case AsmToken::PercentTprel_Lo:
    return MipsMCExpr::create(MipsMCExpr::MEK_TPREL_LO, E, Ctx);
  }
}

bool areEqualRegs(const MCParsedAsmOperand &Op1,
                  const MCParsedAsmOperand &Op2) const override;
797};

799/// MipsOperand - Instances of this class represent a parsed Mips machine
800/// instruction.
801class MipsOperand : public MCParsedAsmOperand {
802public:
/// Broad categories of register classes
/// The exact class is finalized by the render method.
enum RegKind {
  RegKind_GPR = 1,      /// GPR32 and GPR64 (depending on isGP64bit())
  RegKind_FGR = 2,      /// FGR32, FGR64, AFGR64 (depending on context and
                        /// isFP64bit())
  RegKind_FCC = 4,      /// FCC
  RegKind_MSA128 = 8,   /// MSA128[BHWD] (makes no difference which)
  RegKind_MSACtrl = 16, /// MSA control registers
  RegKind_COP2 = 32,    /// COP2
  RegKind_ACC = 64,     /// HI32DSP, LO32DSP, and ACC64DSP (depending on
                        /// context).
  RegKind_CCR = 128,    /// CCR
  RegKind_HWRegs = 256, /// HWRegs
  RegKind_COP3 = 512,   /// COP3
  RegKind_COP0 = 1024,  /// COP0
  /// Potentially any (e.g. $1)
  RegKind_Numeric = RegKind_GPR | RegKind_FGR | RegKind_FCC | RegKind_MSA128 |
                    RegKind_MSACtrl | RegKind_COP2 | RegKind_ACC |
                    RegKind_CCR | RegKind_HWRegs | RegKind_COP3 | RegKind_COP0
};

825private:
enum KindTy {
  k_Immediate,     /// An immediate (possibly involving symbol references)
  k_Memory,        /// Base + Offset Memory Address
  k_RegisterIndex, /// A register index in one or more RegKind.
  k_Token,         /// A simple token
  k_RegList,       /// A physical register list
} Kind;

834public:
MipsOperand(KindTy K, MipsAsmParser &Parser) : Kind(K), AsmParser(Parser) {}

~MipsOperand() override {
  switch (Kind) {
  case k_Memory:
    delete Mem.Base;
    break;
  case k_RegList:
    delete RegList.List;
    break;
  case k_Immediate:
  case k_RegisterIndex:
  case k_Token:
    break;
  }
}

852private:
/// For diagnostics, and checking the assembler temporary
MipsAsmParser &AsmParser;

struct Token {
  const char *Data;
  unsigned Length;
};

struct RegIdxOp {
  unsigned Index; /// Index into the register class
  RegKind Kind;   /// Bitfield of the kinds it could possibly be
  struct Token Tok; /// The input token this operand originated from.
  const MCRegisterInfo *RegInfo;
};

struct ImmOp {
  const MCExpr *Val;
};

struct MemOp {
  MipsOperand *Base;
  const MCExpr *Off;
};

struct RegListOp {
  SmallVector<unsigned, 10> *List;
};

union {
  struct Token Tok;
  struct RegIdxOp RegIdx;
  struct ImmOp Imm;
  struct MemOp Mem;
  struct RegListOp RegList;
};

SMLoc StartLoc, EndLoc;

/// Internal constructor for register kinds
static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, StringRef Str,
                                              RegKind RegKind,
                                              const MCRegisterInfo *RegInfo,
                                              SMLoc S, SMLoc E,
                                              MipsAsmParser &Parser) {
  auto Op = std::make_unique<MipsOperand>(k_RegisterIndex, Parser);
  Op->RegIdx.Index = Index;
  Op->RegIdx.RegInfo = RegInfo;
  Op->RegIdx.Kind = RegKind;
  Op->RegIdx.Tok.Data = Str.data();
  Op->RegIdx.Tok.Length = Str.size();
  Op->StartLoc = S;
  Op->EndLoc = E;
  return Op;
}

908public:
/// Coerce the register to GPR32 and return the real register for the current
/// target.
unsigned getGPR32Reg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_GPR) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_GPR) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 912, __extension__
 __PRETTY_FUNCTION__));
  AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
  unsigned ClassID = Mips::GPR32RegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to GPR32 and return the real register for the current
/// target.
unsigned getGPRMM16Reg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_GPR) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_GPR) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 921, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::GPR32RegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to GPR64 and return the real register for the current
/// target.
unsigned getGPR64Reg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_GPR) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_GPR) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 929, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::GPR64RegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

934private:
/// Coerce the register to AFGR64 and return the real register for the current
/// target.
unsigned getAFGR64Reg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_FGR) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_FGR) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 938, __extension__
 __PRETTY_FUNCTION__));
  if (RegIdx.Index % 2 != 0)
    AsmParser.Warning(StartLoc, "Float register should be even.");
  return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
      .getRegister(RegIdx.Index / 2);
}

/// Coerce the register to FGR64 and return the real register for the current
/// target.
unsigned getFGR64Reg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_FGR) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_FGR) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 948, __extension__
 __PRETTY_FUNCTION__));
  return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
      .getRegister(RegIdx.Index);
}

/// Coerce the register to FGR32 and return the real register for the current
/// target.
unsigned getFGR32Reg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_FGR) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_FGR) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 956, __extension__
 __PRETTY_FUNCTION__));
  return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
      .getRegister(RegIdx.Index);
}

/// Coerce the register to FCC and return the real register for the current
/// target.
unsigned getFCCReg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_FCC) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_FCC) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 964, __extension__
 __PRETTY_FUNCTION__));
  return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
      .getRegister(RegIdx.Index);
}

/// Coerce the register to MSA128 and return the real register for the current
/// target.
unsigned getMSA128Reg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_MSA128) && "Invalid access!") ? void (
0) : __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 972, __extension__
 __PRETTY_FUNCTION__));
  // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
  // identical
  unsigned ClassID = Mips::MSA128BRegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to MSACtrl and return the real register for the
/// current target.
unsigned getMSACtrlReg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_MSACtrl) && "Invalid access!") ? void (
0) : __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 982, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::MSACtrlRegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to COP0 and return the real register for the
/// current target.
unsigned getCOP0Reg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_COP0) && "Invalid access!") ? void (0)
 : __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_COP0) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 990, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::COP0RegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to COP2 and return the real register for the
/// current target.
unsigned getCOP2Reg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_COP2) && "Invalid access!") ? void (0)
 : __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_COP2) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 998, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::COP2RegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to COP3 and return the real register for the
/// current target.
unsigned getCOP3Reg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_COP3) && "Invalid access!") ? void (0)
 : __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_COP3) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1006, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::COP3RegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to ACC64DSP and return the real register for the
/// current target.
unsigned getACC64DSPReg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_ACC) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_ACC) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1014, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::ACC64DSPRegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to HI32DSP and return the real register for the
/// current target.
unsigned getHI32DSPReg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_ACC) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_ACC) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1022, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::HI32DSPRegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to LO32DSP and return the real register for the
/// current target.
unsigned getLO32DSPReg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_ACC) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_ACC) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1030, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::LO32DSPRegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to CCR and return the real register for the
/// current target.
unsigned getCCRReg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_CCR) && "Invalid access!") ? void (0) :
 __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_CCR) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1038, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::CCRRegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

/// Coerce the register to HWRegs and return the real register for the
/// current target.
unsigned getHWRegsReg() const {
  assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!")(static_cast <bool> (isRegIdx() && (RegIdx.Kind
 & RegKind_HWRegs) && "Invalid access!") ? void (
0) : __assert_fail ("isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1046, __extension__
 __PRETTY_FUNCTION__));
  unsigned ClassID = Mips::HWRegsRegClassID;
  return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
}

1051public:
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
  // Add as immediate when possible.  Null MCExpr = 0.
  if (!Expr)
    Inst.addOperand(MCOperand::createImm(0));
  else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
    Inst.addOperand(MCOperand::createImm(CE->getValue()));
  else
    Inst.addOperand(MCOperand::createExpr(Expr));
}

void addRegOperands(MCInst &Inst, unsigned N) const {
  llvm_unreachable("Use a custom parser instead")::llvm::llvm_unreachable_internal("Use a custom parser instead"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1063);
}

/// Render the operand to an MCInst as a GPR32
/// Asserts if the wrong number of operands are requested, or the operand
/// is not a k_RegisterIndex compatible with RegKind_GPR
void addGPR32ZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1070, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
}

void addGPR32NonZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1075, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
}

void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1080, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
}

void addGPRMM16AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1085, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
}

void addGPRMM16AsmRegZeroOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1090, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
}

void addGPRMM16AsmRegMovePOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1095, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
}

void addGPRMM16AsmRegMovePPairFirstOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1100, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
}

void addGPRMM16AsmRegMovePPairSecondOperands(MCInst &Inst,
                                             unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1106, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getGPRMM16Reg()));
}

/// Render the operand to an MCInst as a GPR64
/// Asserts if the wrong number of operands are requested, or the operand
/// is not a k_RegisterIndex compatible with RegKind_GPR
void addGPR64AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1114, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getGPR64Reg()));
}

void addAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1119, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getAFGR64Reg()));
}

void addStrictlyAFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1124, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getAFGR64Reg()));
}

void addStrictlyFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1129, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getFGR64Reg()));
}

void addFGR64AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1134, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getFGR64Reg()));
}

void addFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1139, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
  // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
  // FIXME: This should propagate failure up to parseStatement.
  if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
    AsmParser.getParser().printError(
        StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
                  "registers");
}

void addStrictlyFGR32AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1150, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getFGR32Reg()));
  // FIXME: We ought to do this for -integrated-as without -via-file-asm too.
  if (!AsmParser.useOddSPReg() && RegIdx.Index & 1)
    AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU "
                              "registers");
}

void addFCCAsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1159, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getFCCReg()));
}

void addMSA128AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1164, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getMSA128Reg()));
}

void addMSACtrlAsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1169, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getMSACtrlReg()));
}

void addCOP0AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1174, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getCOP0Reg()));
}

void addCOP2AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1179, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getCOP2Reg()));
}

void addCOP3AsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1184, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getCOP3Reg()));
}

void addACC64DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1189, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getACC64DSPReg()));
}

void addHI32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1194, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getHI32DSPReg()));
}

void addLO32DSPAsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1199, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getLO32DSPReg()));
}

void addCCRAsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1204, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getCCRReg()));
}

void addHWRegsAsmRegOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1209, __extension__
 __PRETTY_FUNCTION__));
  Inst.addOperand(MCOperand::createReg(getHWRegsReg()));
}

template <unsigned Bits, int Offset = 0, int AdjustOffset = 0>
void addConstantUImmOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1215, __extension__
 __PRETTY_FUNCTION__));
  uint64_t Imm = getConstantImm() - Offset;
  Imm &= (1ULL << Bits) - 1;
  Imm += Offset;
  Imm += AdjustOffset;
  Inst.addOperand(MCOperand::createImm(Imm));
}

template <unsigned Bits>
void addSImmOperands(MCInst &Inst, unsigned N) const {
  if (isImm() && !isConstantImm()) {
    addExpr(Inst, getImm());
    return;
  }
  addConstantSImmOperands<Bits, 0, 0>(Inst, N);
}

template <unsigned Bits>
void addUImmOperands(MCInst &Inst, unsigned N) const {
  if (isImm() && !isConstantImm()) {
    addExpr(Inst, getImm());
    return;
  }
  addConstantUImmOperands<Bits, 0, 0>(Inst, N);
}

template <unsigned Bits, int Offset = 0, int AdjustOffset = 0>
void addConstantSImmOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1243, __extension__
 __PRETTY_FUNCTION__));
  int64_t Imm = getConstantImm() - Offset;
  Imm = SignExtend64<Bits>(Imm);
  Imm += Offset;
  Imm += AdjustOffset;
  Inst.addOperand(MCOperand::createImm(Imm));
}

void addImmOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1252, __extension__
 __PRETTY_FUNCTION__));
  const MCExpr *Expr = getImm();
  addExpr(Inst, Expr);
}

void addMemOperands(MCInst &Inst, unsigned N) const {
  assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1258, __extension__
 __PRETTY_FUNCTION__));

  Inst.addOperand(MCOperand::createReg(AsmParser.getABI().ArePtrs64bit()
                                           ? getMemBase()->getGPR64Reg()
                                           : getMemBase()->getGPR32Reg()));

  const MCExpr *Expr = getMemOff();
  addExpr(Inst, Expr);
}

void addMicroMipsMemOperands(MCInst &Inst, unsigned N) const {
  assert(N == 2 && "Invalid number of operands!")(static_cast <bool> (N == 2 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 2 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1269, __extension__
 __PRETTY_FUNCTION__));

  Inst.addOperand(MCOperand::createReg(getMemBase()->getGPRMM16Reg()));

  const MCExpr *Expr = getMemOff();
  addExpr(Inst, Expr);
}

void addRegListOperands(MCInst &Inst, unsigned N) const {
  assert(N == 1 && "Invalid number of operands!")(static_cast <bool> (N == 1 && "Invalid number of operands!"
) ? void (0) : __assert_fail ("N == 1 && \"Invalid number of operands!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1278, __extension__
 __PRETTY_FUNCTION__));

  for (auto RegNo : getRegList())
    Inst.addOperand(MCOperand::createReg(RegNo));
}

bool isReg() const override {
  // As a special case until we sort out the definition of div/divu, accept
  // $0/$zero here so that MCK_ZERO works correctly.
  return isGPRAsmReg() && RegIdx.Index == 0;
}

bool isRegIdx() const { return Kind == k_RegisterIndex; }
bool isImm() const override { return Kind == k_Immediate; }

bool isConstantImm() const {
  int64_t Res;
  return isImm() && getImm()->evaluateAsAbsolute(Res);
}

bool isConstantImmz() const {
  return isConstantImm() && getConstantImm() == 0;
}

template <unsigned Bits, int Offset = 0> bool isConstantUImm() const {
  return isConstantImm() && isUInt<Bits>(getConstantImm() - Offset);
}

template <unsigned Bits> bool isSImm() const {
  return isConstantImm() ? isInt<Bits>(getConstantImm()) : isImm();
}

template <unsigned Bits> bool isUImm() const {
  return isConstantImm() ? isUInt<Bits>(getConstantImm()) : isImm();
}

template <unsigned Bits> bool isAnyImm() const {
  return isConstantImm() ? (isInt<Bits>(getConstantImm()) ||
                            isUInt<Bits>(getConstantImm()))
                         : isImm();
}

template <unsigned Bits, int Offset = 0> bool isConstantSImm() const {
  return isConstantImm() && isInt<Bits>(getConstantImm() - Offset);
}

template <unsigned Bottom, unsigned Top> bool isConstantUImmRange() const {
  return isConstantImm() && getConstantImm() >= Bottom &&
         getConstantImm() <= Top;
}

bool isToken() const override {
  // Note: It's not possible to pretend that other operand kinds are tokens.
  // The matcher emitter checks tokens first.
  return Kind == k_Token;
}

bool isMem() const override { return Kind == k_Memory; }

bool isConstantMemOff() const {
  return isMem() && isa<MCConstantExpr>(getMemOff());
}

// Allow relocation operators.
template <unsigned Bits, unsigned ShiftAmount = 0>
bool isMemWithSimmOffset() const {
  if (!isMem())
    return false;
  if (!getMemBase()->isGPRAsmReg())
    return false;
  if (isa<MCTargetExpr>(getMemOff()) ||
      (isConstantMemOff() &&
       isShiftedInt<Bits, ShiftAmount>(getConstantMemOff())))
    return true;
  MCValue Res;
  bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
  return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant());
}

bool isMemWithPtrSizeOffset() const {
  if (!isMem())
    return false;
  if (!getMemBase()->isGPRAsmReg())
    return false;
  const unsigned PtrBits = AsmParser.getABI().ArePtrs64bit() ? 64 : 32;
  if (isa<MCTargetExpr>(getMemOff()) ||
      (isConstantMemOff() && isIntN(PtrBits, getConstantMemOff())))
    return true;
  MCValue Res;
  bool IsReloc = getMemOff()->evaluateAsRelocatable(Res, nullptr, nullptr);
  return IsReloc && isIntN(PtrBits, Res.getConstant());
}

bool isMemWithGRPMM16Base() const {
  return isMem() && getMemBase()->isMM16AsmReg();
}

template <unsigned Bits> bool isMemWithUimmOffsetSP() const {
  return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
    && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);
}

template <unsigned Bits> bool isMemWithUimmWordAlignedOffsetSP() const {
  return isMem() && isConstantMemOff() && isUInt<Bits>(getConstantMemOff())
    && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
    && (getMemBase()->getGPR32Reg() == Mips::SP);
}

template <unsigned Bits> bool isMemWithSimmWordAlignedOffsetGP() const {
  return isMem() && isConstantMemOff() && isInt<Bits>(getConstantMemOff())
    && (getConstantMemOff() % 4 == 0) && getMemBase()->isRegIdx()
    && (getMemBase()->getGPR32Reg() == Mips::GP);
}

template <unsigned Bits, unsigned ShiftLeftAmount>
bool isScaledUImm() const {
  return isConstantImm() &&
         isShiftedUInt<Bits, ShiftLeftAmount>(getConstantImm());
}

template <unsigned Bits, unsigned ShiftLeftAmount>
bool isScaledSImm() const {
  if (isConstantImm() &&
      isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm()))
    return true;
  // Operand can also be a symbol or symbol plus
  // offset in case of relocations.
  if (Kind != k_Immediate)
    return false;
  MCValue Res;
  bool Success = getImm()->evaluateAsRelocatable(Res, nullptr, nullptr);
  return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant());
}

bool isRegList16() const {
  if (!isRegList())
    return false;

  int Size = RegList.List->size();
  if (Size < 2 || Size > 5)
    return false;

  unsigned R0 = RegList.List->front();
  unsigned R1 = RegList.List->back();
  if (!((R0 == Mips::S0 && R1 == Mips::RA) ||
        (R0 == Mips::S0_64 && R1 == Mips::RA_64)))
    return false;

  int PrevReg = *RegList.List->begin();
  for (int i = 1; i < Size - 1; i++) {
    int Reg = (*(RegList.List))[i];
    if ( Reg != PrevReg + 1)
      return false;
    PrevReg = Reg;
  }

  return true;
}

bool isInvNum() const { return Kind == k_Immediate; }

bool isLSAImm() const {
  if (!isConstantImm())
    return false;
  int64_t Val = getConstantImm();
  return 1 <= Val && Val <= 4;
}

bool isRegList() const { return Kind == k_RegList; }

StringRef getToken() const {
  assert(Kind == k_Token && "Invalid access!")(static_cast <bool> (Kind == k_Token && "Invalid access!"
) ? void (0) : __assert_fail ("Kind == k_Token && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1449, __extension__
 __PRETTY_FUNCTION__));
  return StringRef(Tok.Data, Tok.Length);
}

unsigned getReg() const override {
  // As a special case until we sort out the definition of div/divu, accept
  // $0/$zero here so that MCK_ZERO works correctly.
  if (Kind == k_RegisterIndex && RegIdx.Index == 0 &&
      RegIdx.Kind & RegKind_GPR)
    return getGPR32Reg(); // FIXME: GPR64 too

  llvm_unreachable("Invalid access!")::llvm::llvm_unreachable_internal("Invalid access!", "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp"
, 1460);
  return 0;
}

const MCExpr *getImm() const {
  assert((Kind == k_Immediate) && "Invalid access!")(static_cast <bool> ((Kind == k_Immediate) && "Invalid access!"
) ? void (0) : __assert_fail ("(Kind == k_Immediate) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1465, __extension__
 __PRETTY_FUNCTION__));
  return Imm.Val;
}

int64_t getConstantImm() const {
  const MCExpr *Val = getImm();
  int64_t Value = 0;
  (void)Val->evaluateAsAbsolute(Value);
  return Value;
}

MipsOperand *getMemBase() const {
  assert((Kind == k_Memory) && "Invalid access!")(static_cast <bool> ((Kind == k_Memory) && "Invalid access!"
) ? void (0) : __assert_fail ("(Kind == k_Memory) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1477, __extension__
 __PRETTY_FUNCTION__));
  return Mem.Base;
}

const MCExpr *getMemOff() const {
  assert((Kind == k_Memory) && "Invalid access!")(static_cast <bool> ((Kind == k_Memory) && "Invalid access!"
) ? void (0) : __assert_fail ("(Kind == k_Memory) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1482, __extension__
 __PRETTY_FUNCTION__));
  return Mem.Off;
}

int64_t getConstantMemOff() const {
  return static_cast<const MCConstantExpr *>(getMemOff())->getValue();
}

const SmallVectorImpl<unsigned> &getRegList() const {
  assert((Kind == k_RegList) && "Invalid access!")(static_cast <bool> ((Kind == k_RegList) && "Invalid access!"
) ? void (0) : __assert_fail ("(Kind == k_RegList) && \"Invalid access!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1491, __extension__
 __PRETTY_FUNCTION__));
  return *(RegList.List);
}

static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S,
                                                MipsAsmParser &Parser) {
  auto Op = std::make_unique<MipsOperand>(k_Token, Parser);
  Op->Tok.Data = Str.data();
  Op->Tok.Length = Str.size();
  Op->StartLoc = S;
  Op->EndLoc = S;
  return Op;
}

/// Create a numeric register (e.g. $1). The exact register remains
/// unresolved until an instruction successfully matches
static std::unique_ptr<MipsOperand>
createNumericReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
                 SMLoc S, SMLoc E, MipsAsmParser &Parser) {
  LLVM_DEBUG(dbgs() << "createNumericReg(" << Index << ", ...)\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("mips-asm-parser")) { dbgs() << "createNumericReg(" <<
 Index << ", ...)\n"; } } while (false);
  return CreateReg(Index, Str, RegKind_Numeric, RegInfo, S, E, Parser);
}

/// Create a register that is definitely a GPR.
/// This is typically only used for named registers such as $gp.
static std::unique_ptr<MipsOperand>
createGPRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
             SMLoc S, SMLoc E, MipsAsmParser &Parser) {
  return CreateReg(Index, Str, RegKind_GPR, RegInfo, S, E, Parser);
}

/// Create a register that is definitely a FGR.
/// This is typically only used for named registers such as $f0.
static std::unique_ptr<MipsOperand>
createFGRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
             SMLoc S, SMLoc E, MipsAsmParser &Parser) {
  return CreateReg(Index, Str, RegKind_FGR, RegInfo, S, E, Parser);
}

/// Create a register that is definitely a HWReg.
/// This is typically only used for named registers such as $hwr_cpunum.
static std::unique_ptr<MipsOperand>
createHWRegsReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
                SMLoc S, SMLoc E, MipsAsmParser &Parser) {
  return CreateReg(Index, Str, RegKind_HWRegs, RegInfo, S, E, Parser);
}

/// Create a register that is definitely an FCC.
/// This is typically only used for named registers such as $fcc0.
static std::unique_ptr<MipsOperand>
createFCCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
             SMLoc S, SMLoc E, MipsAsmParser &Parser) {
  return CreateReg(Index, Str, RegKind_FCC, RegInfo, S, E, Parser);
}

/// Create a register that is definitely an ACC.
/// This is typically only used for named registers such as $ac0.
static std::unique_ptr<MipsOperand>
createACCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
             SMLoc S, SMLoc E, MipsAsmParser &Parser) {
  return CreateReg(Index, Str, RegKind_ACC, RegInfo, S, E, Parser);
}

/// Create a register that is definitely an MSA128.
/// This is typically only used for named registers such as $w0.
static std::unique_ptr<MipsOperand>
createMSA128Reg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
                SMLoc S, SMLoc E, MipsAsmParser &Parser) {
  return CreateReg(Index, Str, RegKind_MSA128, RegInfo, S, E, Parser);
}

/// Create a register that is definitely an MSACtrl.
/// This is typically only used for named registers such as $msaaccess.
static std::unique_ptr<MipsOperand>
createMSACtrlReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo,
                 SMLoc S, SMLoc E, MipsAsmParser &Parser) {
  return CreateReg(Index, Str, RegKind_MSACtrl, RegInfo, S, E, Parser);
}

static std::unique_ptr<MipsOperand>
CreateImm(const MCExpr *Val, SMLoc S, SMLoc E, MipsAsmParser &Parser) {
  auto Op = std::make_unique<MipsOperand>(k_Immediate, Parser);
  Op->Imm.Val = Val;
  Op->StartLoc = S;
  Op->EndLoc = E;
  return Op;
}

static std::unique_ptr<MipsOperand>
CreateMem(std::unique_ptr<MipsOperand> Base, const MCExpr *Off, SMLoc S,
          SMLoc E, MipsAsmParser &Parser) {
  auto Op = std::make_unique<MipsOperand>(k_Memory, Parser);
  Op->Mem.Base = Base.release();
  Op->Mem.Off = Off;
  Op->StartLoc = S;
  Op->EndLoc = E;
  return Op;
}

static std::unique_ptr<MipsOperand>
CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc,
              MipsAsmParser &Parser) {
  assert(Regs.size() > 0 && "Empty list not allowed")(static_cast <bool> (Regs.size() > 0 && "Empty list not allowed"
) ? void (0) : __assert_fail ("Regs.size() > 0 && \"Empty list not allowed\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1593, __extension__
 __PRETTY_FUNCTION__));

  auto Op = std::make_unique<MipsOperand>(k_RegList, Parser);
  Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end());
  Op->StartLoc = StartLoc;
  Op->EndLoc = EndLoc;
  return Op;
}

bool isGPRZeroAsmReg() const {
  return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index == 0;
}

bool isGPRNonZeroAsmReg() const {
 return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index > 0 &&
        RegIdx.Index <= 31;
}

bool isGPRAsmReg() const {
  return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
}

bool isMM16AsmReg() const {
  if (!(isRegIdx() && RegIdx.Kind))
    return false;
  return ((RegIdx.Index >= 2 && RegIdx.Index <= 7)
          || RegIdx.Index == 16 || RegIdx.Index == 17);

}
bool isMM16AsmRegZero() const {
  if (!(isRegIdx() && RegIdx.Kind))
    return false;
  return (RegIdx.Index == 0 ||
          (RegIdx.Index >= 2 && RegIdx.Index <= 7) ||
          RegIdx.Index == 17);
}

bool isMM16AsmRegMoveP() const {
  if (!(isRegIdx() && RegIdx.Kind))
    return false;
  return (RegIdx.Index == 0 || (RegIdx.Index >= 2 && RegIdx.Index <= 3) ||
    (RegIdx.Index >= 16 && RegIdx.Index <= 20));
}

bool isMM16AsmRegMovePPairFirst() const {
  if (!(isRegIdx() && RegIdx.Kind))
    return false;
  return RegIdx.Index >= 4 && RegIdx.Index <= 6;
}

bool isMM16AsmRegMovePPairSecond() const {
  if (!(isRegIdx() && RegIdx.Kind))
    return false;
  return (RegIdx.Index == 21 || RegIdx.Index == 22 ||
    (RegIdx.Index >= 5 && RegIdx.Index <= 7));
}

bool isFGRAsmReg() const {
  // AFGR64 is $0-$15 but we handle this in getAFGR64()
  return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31;
}

bool isStrictlyFGRAsmReg() const {
  // AFGR64 is $0-$15 but we handle this in getAFGR64()
  return isRegIdx() && RegIdx.Kind == RegKind_FGR && RegIdx.Index <= 31;
}

bool isHWRegsAsmReg() const {
  return isRegIdx() && RegIdx.Kind & RegKind_HWRegs && RegIdx.Index <= 31;
}

bool isCCRAsmReg() const {
  return isRegIdx() && RegIdx.Kind & RegKind_CCR && RegIdx.Index <= 31;
}

bool isFCCAsmReg() const {
  if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC))
    return false;
  return RegIdx.Index <= 7;
}

bool isACCAsmReg() const {
  return isRegIdx() && RegIdx.Kind & RegKind_ACC && RegIdx.Index <= 3;
}

bool isCOP0AsmReg() const {
  return isRegIdx() && RegIdx.Kind & RegKind_COP0 && RegIdx.Index <= 31;
}

bool isCOP2AsmReg() const {
  return isRegIdx() && RegIdx.Kind & RegKind_COP2 && RegIdx.Index <= 31;
}

bool isCOP3AsmReg() const {
  return isRegIdx() && RegIdx.Kind & RegKind_COP3 && RegIdx.Index <= 31;
}

bool isMSA128AsmReg() const {
  return isRegIdx() && RegIdx.Kind & RegKind_MSA128 && RegIdx.Index <= 31;
}

bool isMSACtrlAsmReg() const {
  return isRegIdx() && RegIdx.Kind & RegKind_MSACtrl && RegIdx.Index <= 7;
}

/// getStartLoc - Get the location of the first token of this operand.
SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Get the location of the last token of this operand.
SMLoc getEndLoc() const override { return EndLoc; }

void print(raw_ostream &OS) const override {
  switch (Kind) {
  case k_Immediate:
    OS << "Imm<";
    OS << *Imm.Val;
    OS << ">";
    break;
  case k_Memory:
    OS << "Mem<";
    Mem.Base->print(OS);
    OS << ", ";
    OS << *Mem.Off;
    OS << ">";
    break;
  case k_RegisterIndex:
    OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ", "
       << StringRef(RegIdx.Tok.Data, RegIdx.Tok.Length) << ">";
    break;
  case k_Token:
    OS << getToken();
    break;
  case k_RegList:
    OS << "RegList< ";
    for (auto Reg : (*RegList.List))
      OS << Reg << " ";
    OS <<  ">";
    break;
  }
}

bool isValidForTie(const MipsOperand &Other) const {
  if (Kind != Other.Kind)
    return false;

  switch (Kind) {
  default:
    llvm_unreachable("Unexpected kind")::llvm::llvm_unreachable_internal("Unexpected kind", "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp"
, 1739);
    return false;
  case k_RegisterIndex: {
    StringRef Token(RegIdx.Tok.Data, RegIdx.Tok.Length);
    StringRef OtherToken(Other.RegIdx.Tok.Data, Other.RegIdx.Tok.Length);
    return Token == OtherToken;
  }
  }
}
1748}; // class MipsOperand

1750} // end anonymous namespace

1752static bool hasShortDelaySlot(MCInst &Inst) {
switch (Inst.getOpcode()) {
  case Mips::BEQ_MM:
  case Mips::BNE_MM:
  case Mips::BLTZ_MM:
  case Mips::BGEZ_MM:
  case Mips::BLEZ_MM:
  case Mips::BGTZ_MM:
  case Mips::JRC16_MM:
  case Mips::JALS_MM:
  case Mips::JALRS_MM:
  case Mips::JALRS16_MM:
  case Mips::BGEZALS_MM:
  case Mips::BLTZALS_MM:
    return true;
  case Mips::J_MM:
    return !Inst.getOperand(0).isReg();
  default:
    return false;
}
1772}

1774static const MCSymbol *getSingleMCSymbol(const MCExpr *Expr) {
if (const MCSymbolRefExpr *SRExpr = dyn_cast<MCSymbolRefExpr>(Expr)) {
  return &SRExpr->getSymbol();
}

if (const MCBinaryExpr *BExpr = dyn_cast<MCBinaryExpr>(Expr)) {
  const MCSymbol *LHSSym = getSingleMCSymbol(BExpr->getLHS());
  const MCSymbol *RHSSym = getSingleMCSymbol(BExpr->getRHS());

  if (LHSSym)
    return LHSSym;

  if (RHSSym)
    return RHSSym;

  return nullptr;
}

if (const MCUnaryExpr *UExpr = dyn_cast<MCUnaryExpr>(Expr))
  return getSingleMCSymbol(UExpr->getSubExpr());

return nullptr;
1796}

1798static unsigned countMCSymbolRefExpr(const MCExpr *Expr) {
if (isa<MCSymbolRefExpr>(Expr))
  return 1;

if (const MCBinaryExpr *BExpr = dyn_cast<MCBinaryExpr>(Expr))
  return countMCSymbolRefExpr(BExpr->getLHS()) +
         countMCSymbolRefExpr(BExpr->getRHS());

if (const MCUnaryExpr *UExpr = dyn_cast<MCUnaryExpr>(Expr))
  return countMCSymbolRefExpr(UExpr->getSubExpr());

return 0;
1810}

1812static bool isEvaluated(const MCExpr *Expr) {
switch (Expr->getKind()) {
case MCExpr::Constant:
  return true;
case MCExpr::SymbolRef:
  return (cast<MCSymbolRefExpr>(Expr)->getKind() != MCSymbolRefExpr::VK_None);
case MCExpr::Binary: {
  const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
  if (!isEvaluated(BE->getLHS()))
    return false;
  return isEvaluated(BE->getRHS());
}
case MCExpr::Unary:
  return isEvaluated(cast<MCUnaryExpr>(Expr)->getSubExpr());
case MCExpr::Target:
  return true;
}
return false;
1830}

1832static bool needsExpandMemInst(MCInst &Inst, const MCInstrDesc &MCID) {
unsigned NumOp = MCID.getNumOperands();
if (NumOp != 3 && NumOp != 4)
  return false;

const MCOperandInfo &OpInfo = MCID.operands()[NumOp - 1];
if (OpInfo.OperandType != MCOI::OPERAND_MEMORY &&
    OpInfo.OperandType != MCOI::OPERAND_UNKNOWN &&
    OpInfo.OperandType != MipsII::OPERAND_MEM_SIMM9)
  return false;

MCOperand &Op = Inst.getOperand(NumOp - 1);
if (Op.isImm()) {
  if (OpInfo.OperandType == MipsII::OPERAND_MEM_SIMM9)
    return !isInt<9>(Op.getImm());
  // Offset can't exceed 16bit value.
  return !isInt<16>(Op.getImm());
}

if (Op.isExpr()) {
  const MCExpr *Expr = Op.getExpr();
  if (Expr->getKind() != MCExpr::SymbolRef)
    return !isEvaluated(Expr);

  // Expand symbol.
  const MCSymbolRefExpr *SR = static_cast<const MCSymbolRefExpr *>(Expr);
  return SR->getKind() == MCSymbolRefExpr::VK_None;
}

return false;
1862}

1864bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
                                     MCStreamer &Out,
                                     const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
const unsigned Opcode = Inst.getOpcode();
const MCInstrDesc &MCID = MII.get(Opcode);
bool ExpandedJalSym = false;

Inst.setLoc(IDLoc);

if (MCID.isBranch() || MCID.isCall()) {
  MCOperand Offset;

  switch (Opcode) {
  default:
    break;
  case Mips::BBIT0:
  case Mips::BBIT032:
  case Mips::BBIT1:
  case Mips::BBIT132:
    assert(hasCnMips() && "instruction only valid for octeon cpus")(static_cast <bool> (hasCnMips() && "instruction only valid for octeon cpus"
) ? void (0) : __assert_fail ("hasCnMips() && \"instruction only valid for octeon cpus\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1884, __extension__
 __PRETTY_FUNCTION__));
    [[fallthrough]];

  case Mips::BEQ:
  case Mips::BNE:
  case Mips::BEQ_MM:
  case Mips::BNE_MM:
    assert(MCID.getNumOperands() == 3 && "unexpected number of operands")(static_cast <bool> (MCID.getNumOperands() == 3 &&
 "unexpected number of operands") ? void (0) : __assert_fail (
"MCID.getNumOperands() == 3 && \"unexpected number of operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1891, __extension__
 __PRETTY_FUNCTION__));
    Offset = Inst.getOperand(2);
    if (!Offset.isImm())
      break; // We'll deal with this situation later on when applying fixups.
    if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
      return Error(IDLoc, "branch target out of range");
    if (offsetToAlignment(Offset.getImm(),
                          (inMicroMipsMode() ? Align(2) : Align(4))))
      return Error(IDLoc, "branch to misaligned address");
    break;
  case Mips::BGEZ:
  case Mips::BGTZ:
  case Mips::BLEZ:
  case Mips::BLTZ:
  case Mips::BGEZAL:
  case Mips::BLTZAL:
  case Mips::BC1F:
  case Mips::BC1T:
  case Mips::BGEZ_MM:
  case Mips::BGTZ_MM:
  case Mips::BLEZ_MM:
  case Mips::BLTZ_MM:
  case Mips::BGEZAL_MM:
  case Mips::BLTZAL_MM:
  case Mips::BC1F_MM:
  case Mips::BC1T_MM:
  case Mips::BC1EQZC_MMR6:
  case Mips::BC1NEZC_MMR6:
  case Mips::BC2EQZC_MMR6:
  case Mips::BC2NEZC_MMR6:
    assert(MCID.getNumOperands() == 2 && "unexpected number of operands")(static_cast <bool> (MCID.getNumOperands() == 2 &&
 "unexpected number of operands") ? void (0) : __assert_fail (
"MCID.getNumOperands() == 2 && \"unexpected number of operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1921, __extension__
 __PRETTY_FUNCTION__));
    Offset = Inst.getOperand(1);
    if (!Offset.isImm())
      break; // We'll deal with this situation later on when applying fixups.
    if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
      return Error(IDLoc, "branch target out of range");
    if (offsetToAlignment(Offset.getImm(),
                          (inMicroMipsMode() ? Align(2) : Align(4))))
      return Error(IDLoc, "branch to misaligned address");
    break;
  case Mips::BGEC:    case Mips::BGEC_MMR6:
  case Mips::BLTC:    case Mips::BLTC_MMR6:
  case Mips::BGEUC:   case Mips::BGEUC_MMR6:
  case Mips::BLTUC:   case Mips::BLTUC_MMR6:
  case Mips::BEQC:    case Mips::BEQC_MMR6:
  case Mips::BNEC:    case Mips::BNEC_MMR6:
    assert(MCID.getNumOperands() == 3 && "unexpected number of operands")(static_cast <bool> (MCID.getNumOperands() == 3 &&
 "unexpected number of operands") ? void (0) : __assert_fail (
"MCID.getNumOperands() == 3 && \"unexpected number of operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1937, __extension__
 __PRETTY_FUNCTION__));
    Offset = Inst.getOperand(2);
    if (!Offset.isImm())
      break; // We'll deal with this situation later on when applying fixups.
    if (!isIntN(18, Offset.getImm()))
      return Error(IDLoc, "branch target out of range");
    if (offsetToAlignment(Offset.getImm(), Align(4)))
      return Error(IDLoc, "branch to misaligned address");
    break;
  case Mips::BLEZC:   case Mips::BLEZC_MMR6:
  case Mips::BGEZC:   case Mips::BGEZC_MMR6:
  case Mips::BGTZC:   case Mips::BGTZC_MMR6:
  case Mips::BLTZC:   case Mips::BLTZC_MMR6:
    assert(MCID.getNumOperands() == 2 && "unexpected number of operands")(static_cast <bool> (MCID.getNumOperands() == 2 &&
 "unexpected number of operands") ? void (0) : __assert_fail (
"MCID.getNumOperands() == 2 && \"unexpected number of operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1950, __extension__
 __PRETTY_FUNCTION__));
    Offset = Inst.getOperand(1);
    if (!Offset.isImm())
      break; // We'll deal with this situation later on when applying fixups.
    if (!isIntN(18, Offset.getImm()))
      return Error(IDLoc, "branch target out of range");
    if (offsetToAlignment(Offset.getImm(), Align(4)))
      return Error(IDLoc, "branch to misaligned address");
    break;
  case Mips::BEQZC:   case Mips::BEQZC_MMR6:
  case Mips::BNEZC:   case Mips::BNEZC_MMR6:
    assert(MCID.getNumOperands() == 2 && "unexpected number of operands")(static_cast <bool> (MCID.getNumOperands() == 2 &&
 "unexpected number of operands") ? void (0) : __assert_fail (
"MCID.getNumOperands() == 2 && \"unexpected number of operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1961, __extension__
 __PRETTY_FUNCTION__));
    Offset = Inst.getOperand(1);
    if (!Offset.isImm())
      break; // We'll deal with this situation later on when applying fixups.
    if (!isIntN(23, Offset.getImm()))
      return Error(IDLoc, "branch target out of range");
    if (offsetToAlignment(Offset.getImm(), Align(4)))
      return Error(IDLoc, "branch to misaligned address");
    break;
  case Mips::BEQZ16_MM:
  case Mips::BEQZC16_MMR6:
  case Mips::BNEZ16_MM:
  case Mips::BNEZC16_MMR6:
    assert(MCID.getNumOperands() == 2 && "unexpected number of operands")(static_cast <bool> (MCID.getNumOperands() == 2 &&
 "unexpected number of operands") ? void (0) : __assert_fail (
"MCID.getNumOperands() == 2 && \"unexpected number of operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 1974, __extension__
 __PRETTY_FUNCTION__));
    Offset = Inst.getOperand(1);
    if (!Offset.isImm())
      break; // We'll deal with this situation later on when applying fixups.
    if (!isInt<8>(Offset.getImm()))
      return Error(IDLoc, "branch target out of range");
    if (offsetToAlignment(Offset.getImm(), Align(2)))
      return Error(IDLoc, "branch to misaligned address");
    break;
  }
}

// SSNOP is deprecated on MIPS32r6/MIPS64r6
// We still accept it but it is a normal nop.
if (hasMips32r6() && Opcode == Mips::SSNOP) {
  std::string ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
  Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a "
                                                    "nop instruction");
}

if (hasCnMips()) {
  MCOperand Opnd;
  int Imm;

  switch (Opcode) {
    default:
      break;

    case Mips::BBIT0:
    case Mips::BBIT032:
    case Mips::BBIT1:
    case Mips::BBIT132:
      assert(MCID.getNumOperands() == 3 && "unexpected number of operands")(static_cast <bool> (MCID.getNumOperands() == 3 &&
 "unexpected number of operands") ? void (0) : __assert_fail (
"MCID.getNumOperands() == 3 && \"unexpected number of operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2006, __extension__
 __PRETTY_FUNCTION__));
      // The offset is handled above
      Opnd = Inst.getOperand(1);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 ||
                            Opcode == Mips::BBIT1 ? 63 : 31))
        return Error(IDLoc, "immediate operand value out of range");
      if (Imm > 31) {
        Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032
                                             : Mips::BBIT132);
        Inst.getOperand(1).setImm(Imm - 32);
      }
      break;

    case Mips::SEQi:
    case Mips::SNEi:
      assert(MCID.getNumOperands() == 3 && "unexpected number of operands")(static_cast <bool> (MCID.getNumOperands() == 3 &&
 "unexpected number of operands") ? void (0) : __assert_fail (
"MCID.getNumOperands() == 3 && \"unexpected number of operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2024, __extension__
 __PRETTY_FUNCTION__));
      Opnd = Inst.getOperand(2);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (!isInt<10>(Imm))
        return Error(IDLoc, "immediate operand value out of range");
      break;
  }
}

// Warn on division by zero. We're checking here as all instructions get
// processed here, not just the macros that need expansion.
//
// The MIPS backend models most of the divison instructions and macros as
// three operand instructions. The pre-R6 divide instructions however have
// two operands and explicitly define HI/LO as part of the instruction,
// not in the operands.
unsigned FirstOp = 1;
unsigned SecondOp = 2;
switch (Opcode) {
default:
  break;
case Mips::SDivIMacro:
case Mips::UDivIMacro:
case Mips::DSDivIMacro:
case Mips::DUDivIMacro:
  if (Inst.getOperand(2).getImm() == 0) {
    if (Inst.getOperand(1).getReg() == Mips::ZERO ||
        Inst.getOperand(1).getReg() == Mips::ZERO_64)
      Warning(IDLoc, "dividing zero by zero");
    else
      Warning(IDLoc, "division by zero");
  }
  break;
case Mips::DSDIV:
case Mips::SDIV:
case Mips::UDIV:
case Mips::DUDIV:
case Mips::UDIV_MM:
case Mips::SDIV_MM:
  FirstOp = 0;
  SecondOp = 1;
  [[fallthrough]];
case Mips::SDivMacro:
case Mips::DSDivMacro:
case Mips::UDivMacro:
case Mips::DUDivMacro:
case Mips::DIV:
case Mips::DIVU:
case Mips::DDIV:
case Mips::DDIVU:
case Mips::DIVU_MMR6:
case Mips::DIV_MMR6:
  if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
      Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) {
    if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
        Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64)
      Warning(IDLoc, "dividing zero by zero");
    else
      Warning(IDLoc, "division by zero");
  }
  break;
}

// For PIC code convert unconditional jump to unconditional branch.
if ((Opcode == Mips::J || Opcode == Mips::J_MM) && inPicMode()) {
  MCInst BInst;
  BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ);
  BInst.addOperand(MCOperand::createReg(Mips::ZERO));
  BInst.addOperand(MCOperand::createReg(Mips::ZERO));
  BInst.addOperand(Inst.getOperand(0));
  Inst = BInst;
}

// This expansion is not in a function called by tryExpandInstruction()
// because the pseudo-instruction doesn't have a distinct opcode.
if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) {
  warnIfNoMacro(IDLoc);

  const MCExpr *JalExpr = Inst.getOperand(0).getExpr();

  // We can do this expansion if there's only 1 symbol in the argument
  // expression.
  if (countMCSymbolRefExpr(JalExpr) > 1)
    return Error(IDLoc, "jal doesn't support multiple symbols in PIC mode");

  // FIXME: This is checking the expression can be handled by the later stages
  //        of the assembler. We ought to leave it to those later stages.
  const MCSymbol *JalSym = getSingleMCSymbol(JalExpr);

  if (expandLoadAddress(Mips::T9, Mips::NoRegister, Inst.getOperand(0),
                        !isGP64bit(), IDLoc, Out, STI))
    return true;

  MCInst JalrInst;
  if (inMicroMipsMode())
    JalrInst.setOpcode(IsCpRestoreSet ? Mips::JALRS_MM : Mips::JALR_MM);
  else
    JalrInst.setOpcode(Mips::JALR);
  JalrInst.addOperand(MCOperand::createReg(Mips::RA));
  JalrInst.addOperand(MCOperand::createReg(Mips::T9));

  if (isJalrRelocAvailable(JalExpr)) {
    // As an optimization hint for the linker, before the JALR we add:
    // .reloc tmplabel, R_{MICRO}MIPS_JALR, symbol
    // tmplabel:
    MCSymbol *TmpLabel = getContext().createTempSymbol();
    const MCExpr *TmpExpr = MCSymbolRefExpr::create(TmpLabel, getContext());
    const MCExpr *RelocJalrExpr =
        MCSymbolRefExpr::create(JalSym, MCSymbolRefExpr::VK_None,
                                getContext(), IDLoc);

    TOut.getStreamer().emitRelocDirective(
        *TmpExpr, inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
        RelocJalrExpr, IDLoc, *STI);
    TOut.getStreamer().emitLabel(TmpLabel);
  }

  Inst = JalrInst;
  ExpandedJalSym = true;
}

if (MCID.mayLoad() || MCID.mayStore()) {
  // Check the offset of memory operand, if it is a symbol
  // reference or immediate we may have to expand instructions.
  if (needsExpandMemInst(Inst, MCID)) {
    switch (MCID.operands()[MCID.getNumOperands() - 1].OperandType) {
    case MipsII::OPERAND_MEM_SIMM9:
      expandMem9Inst(Inst, IDLoc, Out, STI, MCID.mayLoad());
      break;
    default:
      expandMem16Inst(Inst, IDLoc, Out, STI, MCID.mayLoad());
      break;
    }
    return getParser().hasPendingError();
  }
}

if (inMicroMipsMode()) {
  if (MCID.mayLoad() && Opcode != Mips::LWP_MM) {
    // Try to create 16-bit GP relative load instruction.
    for (unsigned i = 0; i < MCID.getNumOperands(); i++) {
      const MCOperandInfo &OpInfo = MCID.operands()[i];
      if ((OpInfo.OperandType == MCOI::OPERAND_MEMORY) ||
          (OpInfo.OperandType == MCOI::OPERAND_UNKNOWN)) {
        MCOperand &Op = Inst.getOperand(i);
        if (Op.isImm()) {
          int MemOffset = Op.getImm();
          MCOperand &DstReg = Inst.getOperand(0);
          MCOperand &BaseReg = Inst.getOperand(1);
          if (isInt<9>(MemOffset) && (MemOffset % 4 == 0) &&
              getContext().getRegisterInfo()->getRegClass(
                Mips::GPRMM16RegClassID).contains(DstReg.getReg()) &&
              (BaseReg.getReg() == Mips::GP ||
              BaseReg.getReg() == Mips::GP_64)) {

            TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset,
                         IDLoc, STI);
            return false;
          }
        }
      }
    } // for
  }   // if load

  // TODO: Handle this with the AsmOperandClass.PredicateMethod.

  MCOperand Opnd;
  int Imm;

  switch (Opcode) {
    default:
      break;
    case Mips::ADDIUSP_MM:
      Opnd = Inst.getOperand(0);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (Imm < -1032 || Imm > 1028 || (Imm < 8 && Imm > -12) ||
          Imm % 4 != 0)
        return Error(IDLoc, "immediate operand value out of range");
      break;
    case Mips::SLL16_MM:
    case Mips::SRL16_MM:
      Opnd = Inst.getOperand(2);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (Imm < 1 || Imm > 8)
        return Error(IDLoc, "immediate operand value out of range");
      break;
    case Mips::LI16_MM:
      Opnd = Inst.getOperand(1);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (Imm < -1 || Imm > 126)
        return Error(IDLoc, "immediate operand value out of range");
      break;
    case Mips::ADDIUR2_MM:
      Opnd = Inst.getOperand(2);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (!(Imm == 1 || Imm == -1 ||
            ((Imm % 4 == 0) && Imm < 28 && Imm > 0)))
        return Error(IDLoc, "immediate operand value out of range");
      break;
    case Mips::ANDI16_MM:
      Opnd = Inst.getOperand(2);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (!(Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
            Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
            Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535))
        return Error(IDLoc, "immediate operand value out of range");
      break;
    case Mips::LBU16_MM:
      Opnd = Inst.getOperand(2);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (Imm < -1 || Imm > 14)
        return Error(IDLoc, "immediate operand value out of range");
      break;
    case Mips::SB16_MM:
    case Mips::SB16_MMR6:
      Opnd = Inst.getOperand(2);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (Imm < 0 || Imm > 15)
        return Error(IDLoc, "immediate operand value out of range");
      break;
    case Mips::LHU16_MM:
    case Mips::SH16_MM:
    case Mips::SH16_MMR6:
      Opnd = Inst.getOperand(2);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (Imm < 0 || Imm > 30 || (Imm % 2 != 0))
        return Error(IDLoc, "immediate operand value out of range");
      break;
    case Mips::LW16_MM:
    case Mips::SW16_MM:
    case Mips::SW16_MMR6:
      Opnd = Inst.getOperand(2);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if (Imm < 0 || Imm > 60 || (Imm % 4 != 0))
        return Error(IDLoc, "immediate operand value out of range");
      break;
    case Mips::ADDIUPC_MM:
      Opnd = Inst.getOperand(1);
      if (!Opnd.isImm())
        return Error(IDLoc, "expected immediate operand kind");
      Imm = Opnd.getImm();
      if ((Imm % 4 != 0) || !isInt<25>(Imm))
        return Error(IDLoc, "immediate operand value out of range");
      break;
    case Mips::LWP_MM:
    case Mips::SWP_MM:
      if (Inst.getOperand(0).getReg() == Mips::RA)
        return Error(IDLoc, "invalid operand for instruction");
      break;
    case Mips::MOVEP_MM:
    case Mips::MOVEP_MMR6: {
      unsigned R0 = Inst.getOperand(0).getReg();
      unsigned R1 = Inst.getOperand(1).getReg();
      bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) ||
                      (R0 == Mips::A1 && R1 == Mips::A3) ||
                      (R0 == Mips::A2 && R1 == Mips::A3) ||
                      (R0 == Mips::A0 && R1 == Mips::S5) ||
                      (R0 == Mips::A0 && R1 == Mips::S6) ||
                      (R0 == Mips::A0 && R1 == Mips::A1) ||
                      (R0 == Mips::A0 && R1 == Mips::A2) ||
                      (R0 == Mips::A0 && R1 == Mips::A3));
      if (!RegPair)
        return Error(IDLoc, "invalid operand for instruction");
      break;
    }
  }
}

bool FillDelaySlot =
    MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder();
if (FillDelaySlot)
  TOut.emitDirectiveSetNoReorder();

MacroExpanderResultTy ExpandResult =
    tryExpandInstruction(Inst, IDLoc, Out, STI);
switch (ExpandResult) {
case MER_NotAMacro:
  Out.emitInstruction(Inst, *STI);
  break;
case MER_Success:
  break;
case MER_Fail:
  return true;
}

// We know we emitted an instruction on the MER_NotAMacro or MER_Success path.
// If we're in microMIPS mode then we must also set EF_MIPS_MICROMIPS.
if (inMicroMipsMode()) {
  TOut.setUsesMicroMips();
  TOut.updateABIInfo(*this);
}

// If this instruction has a delay slot and .set reorder is active,
// emit a NOP after it.
if (FillDelaySlot) {
  TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI);
  TOut.emitDirectiveSetReorder();
}

if ((Opcode == Mips::JalOneReg || Opcode == Mips::JalTwoReg ||
     ExpandedJalSym) &&
    isPicAndNotNxxAbi()) {
  if (IsCpRestoreSet) {
    // We need a NOP between the JALR and the LW:
    // If .set reorder has been used, we've already emitted a NOP.
    // If .set noreorder has been used, we need to emit a NOP at this point.
    if (!AssemblerOptions.back()->isReorder())
      TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc,
                              STI);

    // Load the $gp from the stack.
    TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI);
  } else
    Warning(IDLoc, "no .cprestore used in PIC mode");
}

return false;
2361}

2363MipsAsmParser::MacroExpanderResultTy
2364MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                  const MCSubtargetInfo *STI) {
switch (Inst.getOpcode()) {
default:
  return MER_NotAMacro;
case Mips::LoadImm32:
  return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::LoadImm64:
  return expandLoadImm(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::LoadAddrImm32:
case Mips::LoadAddrImm64:
  assert(Inst.getOperand(0).isReg() && "expected register operand kind")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 "expected register operand kind") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2375, __extension__
 __PRETTY_FUNCTION__));
  assert((Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) &&(static_cast <bool> ((Inst.getOperand(1).isImm() || Inst
.getOperand(1).isExpr()) && "expected immediate operand kind"
) ? void (0) : __assert_fail ("(Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) && \"expected immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2377, __extension__
 __PRETTY_FUNCTION__))
         "expected immediate operand kind")(static_cast <bool> ((Inst.getOperand(1).isImm() || Inst
.getOperand(1).isExpr()) && "expected immediate operand kind"
) ? void (0) : __assert_fail ("(Inst.getOperand(1).isImm() || Inst.getOperand(1).isExpr()) && \"expected immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2377, __extension__
 __PRETTY_FUNCTION__));

  return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister,
                           Inst.getOperand(1),
                           Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc,
                           Out, STI)
             ? MER_Fail
             : MER_Success;
case Mips::LoadAddrReg32:
case Mips::LoadAddrReg64:
  assert(Inst.getOperand(0).isReg() && "expected register operand kind")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 "expected register operand kind") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2387, __extension__
 __PRETTY_FUNCTION__));
  assert(Inst.getOperand(1).isReg() && "expected register operand kind")(static_cast <bool> (Inst.getOperand(1).isReg() &&
 "expected register operand kind") ? void (0) : __assert_fail
 ("Inst.getOperand(1).isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2388, __extension__
 __PRETTY_FUNCTION__));
  assert((Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) &&(static_cast <bool> ((Inst.getOperand(2).isImm() || Inst
.getOperand(2).isExpr()) && "expected immediate operand kind"
) ? void (0) : __assert_fail ("(Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) && \"expected immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2390, __extension__
 __PRETTY_FUNCTION__))
         "expected immediate operand kind")(static_cast <bool> ((Inst.getOperand(2).isImm() || Inst
.getOperand(2).isExpr()) && "expected immediate operand kind"
) ? void (0) : __assert_fail ("(Inst.getOperand(2).isImm() || Inst.getOperand(2).isExpr()) && \"expected immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2390, __extension__
 __PRETTY_FUNCTION__));

  return expandLoadAddress(Inst.getOperand(0).getReg(),
                           Inst.getOperand(1).getReg(), Inst.getOperand(2),
                           Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc,
                           Out, STI)
             ? MER_Fail
             : MER_Success;
case Mips::B_MM_Pseudo:
case Mips::B_MMR6_Pseudo:
  return expandUncondBranchMMPseudo(Inst, IDLoc, Out, STI) ? MER_Fail
                                                           : MER_Success;
case Mips::SWM_MM:
case Mips::LWM_MM:
  return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail
                                                        : MER_Success;
case Mips::JalOneReg:
case Mips::JalTwoReg:
  return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::BneImm:
case Mips::BeqImm:
case Mips::BEQLImmMacro:
case Mips::BNELImmMacro:
  return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::BLT:
case Mips::BLE:
case Mips::BGE:
case Mips::BGT:
case Mips::BLTU:
case Mips::BLEU:
case Mips::BGEU:
case Mips::BGTU:
case Mips::BLTL:
case Mips::BLEL:
case Mips::BGEL:
case Mips::BGTL:
case Mips::BLTUL:
case Mips::BLEUL:
case Mips::BGEUL:
case Mips::BGTUL:
case Mips::BLTImmMacro:
case Mips::BLEImmMacro:
case Mips::BGEImmMacro:
case Mips::BGTImmMacro:
case Mips::BLTUImmMacro:
case Mips::BLEUImmMacro:
case Mips::BGEUImmMacro:
case Mips::BGTUImmMacro:
case Mips::BLTLImmMacro:
case Mips::BLELImmMacro:
case Mips::BGELImmMacro:
case Mips::BGTLImmMacro:
case Mips::BLTULImmMacro:
case Mips::BLEULImmMacro:
case Mips::BGEULImmMacro:
case Mips::BGTULImmMacro:
  return expandCondBranches(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SDivMacro:
case Mips::SDivIMacro:
case Mips::SRemMacro:
case Mips::SRemIMacro:
  return expandDivRem(Inst, IDLoc, Out, STI, false, true) ? MER_Fail
                                                          : MER_Success;
case Mips::DSDivMacro:
case Mips::DSDivIMacro:
case Mips::DSRemMacro:
case Mips::DSRemIMacro:
  return expandDivRem(Inst, IDLoc, Out, STI, true, true) ? MER_Fail
                                                         : MER_Success;
case Mips::UDivMacro:
case Mips::UDivIMacro:
case Mips::URemMacro:
case Mips::URemIMacro:
  return expandDivRem(Inst, IDLoc, Out, STI, false, false) ? MER_Fail
                                                           : MER_Success;
case Mips::DUDivMacro:
case Mips::DUDivIMacro:
case Mips::DURemMacro:
case Mips::DURemIMacro:
  return expandDivRem(Inst, IDLoc, Out, STI, true, false) ? MER_Fail
                                                          : MER_Success;
case Mips::PseudoTRUNC_W_S:
  return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail
                                                          : MER_Success;
case Mips::PseudoTRUNC_W_D32:
  return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail
                                                         : MER_Success;
case Mips::PseudoTRUNC_W_D:
  return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail
                                                        : MER_Success;

case Mips::LoadImmSingleGPR:
  return expandLoadSingleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail
                                                         : MER_Success;
case Mips::LoadImmSingleFGR:
  return expandLoadSingleImmToFPR(Inst, IDLoc, Out, STI) ? MER_Fail
                                                         : MER_Success;
case Mips::LoadImmDoubleGPR:
  return expandLoadDoubleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail
                                                         : MER_Success;
case Mips::LoadImmDoubleFGR:
  return expandLoadDoubleImmToFPR(Inst, true, IDLoc, Out, STI) ? MER_Fail
                                                               : MER_Success;
case Mips::LoadImmDoubleFGR_32:
  return expandLoadDoubleImmToFPR(Inst, false, IDLoc, Out, STI) ? MER_Fail
                                                                : MER_Success;

case Mips::Ulh:
  return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::Ulhu:
  return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::Ush:
  return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::Ulw:
case Mips::Usw:
  return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::NORImm:
case Mips::NORImm64:
  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SGE:
case Mips::SGEU:
  return expandSge(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SGEImm:
case Mips::SGEUImm:
case Mips::SGEImm64:
case Mips::SGEUImm64:
  return expandSgeImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SGTImm:
case Mips::SGTUImm:
case Mips::SGTImm64:
case Mips::SGTUImm64:
  return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SLE:
case Mips::SLEU:
  return expandSle(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SLEImm:
case Mips::SLEUImm:
case Mips::SLEImm64:
case Mips::SLEUImm64:
  return expandSleImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SLTImm64:
  if (isInt<16>(Inst.getOperand(2).getImm())) {
    Inst.setOpcode(Mips::SLTi64);
    return MER_NotAMacro;
  }
  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SLTUImm64:
  if (isInt<16>(Inst.getOperand(2).getImm())) {
    Inst.setOpcode(Mips::SLTiu64);
    return MER_NotAMacro;
  }
  return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::ADDi:   case Mips::ADDi_MM:
case Mips::ADDiu:  case Mips::ADDiu_MM:
case Mips::SLTi:   case Mips::SLTi_MM:
case Mips::SLTiu:  case Mips::SLTiu_MM:
  if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
      Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
    int64_t ImmValue = Inst.getOperand(2).getImm();
    if (isInt<16>(ImmValue))
      return MER_NotAMacro;
    return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail
                                                       : MER_Success;
  }
  return MER_NotAMacro;
case Mips::ANDi:  case Mips::ANDi_MM:  case Mips::ANDi64:
case Mips::ORi:   case Mips::ORi_MM:   case Mips::ORi64:
case Mips::XORi:  case Mips::XORi_MM:  case Mips::XORi64:
  if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
      Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
    int64_t ImmValue = Inst.getOperand(2).getImm();
    if (isUInt<16>(ImmValue))
      return MER_NotAMacro;
    return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail
                                                       : MER_Success;
  }
  return MER_NotAMacro;
case Mips::ROL:
case Mips::ROR:
  return expandRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::ROLImm:
case Mips::RORImm:
  return expandRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::DROL:
case Mips::DROR:
  return expandDRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::DROLImm:
case Mips::DRORImm:
  return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::ABSMacro:
  return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::MULImmMacro:
case Mips::DMULImmMacro:
  return expandMulImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::MULOMacro:
case Mips::DMULOMacro:
  return expandMulO(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::MULOUMacro:
case Mips::DMULOUMacro:
  return expandMulOU(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::DMULMacro:
  return expandDMULMacro(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::LDMacro:
case Mips::SDMacro:
  return expandLoadStoreDMacro(Inst, IDLoc, Out, STI,
                               Inst.getOpcode() == Mips::LDMacro)
             ? MER_Fail
             : MER_Success;
case Mips::SDC1_M1:
  return expandStoreDM1Macro(Inst, IDLoc, Out, STI)
             ? MER_Fail
             : MER_Success;
case Mips::SEQMacro:
  return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SEQIMacro:
  return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SNEMacro:
  return expandSne(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SNEIMacro:
  return expandSneI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::MFTC0:   case Mips::MTTC0:
case Mips::MFTGPR:  case Mips::MTTGPR:
case Mips::MFTLO:   case Mips::MTTLO:
case Mips::MFTHI:   case Mips::MTTHI:
case Mips::MFTACX:  case Mips::MTTACX:
case Mips::MFTDSP:  case Mips::MTTDSP:
case Mips::MFTC1:   case Mips::MTTC1:
case Mips::MFTHC1:  case Mips::MTTHC1:
case Mips::CFTC1:   case Mips::CTTC1:
  return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
case Mips::SaaAddr:
case Mips::SaadAddr:
  return expandSaaAddr(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
}
2624}

2626bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc,
                                    MCStreamer &Out,
                                    const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

// Create a JALR instruction which is going to replace the pseudo-JAL.
MCInst JalrInst;
JalrInst.setLoc(IDLoc);
const MCOperand FirstRegOp = Inst.getOperand(0);
const unsigned Opcode = Inst.getOpcode();

if (Opcode == Mips::JalOneReg) {
  // jal $rs => jalr $rs
  if (IsCpRestoreSet && inMicroMipsMode()) {
    JalrInst.setOpcode(Mips::JALRS16_MM);
    JalrInst.addOperand(FirstRegOp);
  } else if (inMicroMipsMode()) {
    JalrInst.setOpcode(hasMips32r6() ? Mips::JALRC16_MMR6 : Mips::JALR16_MM);
    JalrInst.addOperand(FirstRegOp);
  } else {
    JalrInst.setOpcode(Mips::JALR);
    JalrInst.addOperand(MCOperand::createReg(Mips::RA));
    JalrInst.addOperand(FirstRegOp);
  }
} else if (Opcode == Mips::JalTwoReg) {
  // jal $rd, $rs => jalr $rd, $rs
  if (IsCpRestoreSet && inMicroMipsMode())
    JalrInst.setOpcode(Mips::JALRS_MM);
  else
    JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
  JalrInst.addOperand(FirstRegOp);
  const MCOperand SecondRegOp = Inst.getOperand(1);
  JalrInst.addOperand(SecondRegOp);
}
Out.emitInstruction(JalrInst, *STI);

// If .set reorder is active and branch instruction has a delay slot,
// emit a NOP after it.
const MCInstrDesc &MCID = MII.get(JalrInst.getOpcode());
if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
  TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst), IDLoc,
                          STI);

return false;
2670}

2672/// Can the value be represented by a unsigned N-bit value and a shift left?
2673template <unsigned N> static bool isShiftedUIntAtAnyPosition(uint64_t x) {
return x && isUInt<N>(x >> llvm::countr_zero(x));
2675}

2677/// Load (or add) an immediate into a register.
2678///
2679/// @param ImmValue     The immediate to load.
2680/// @param DstReg       The register that will hold the immediate.
2681/// @param SrcReg       A register to add to the immediate or Mips::NoRegister
2682///                     for a simple initialization.
2683/// @param Is32BitImm   Is ImmValue 32-bit or 64-bit?
2684/// @param IsAddress    True if the immediate represents an address. False if it
2685///                     is an integer.
2686/// @param IDLoc        Location of the immediate in the source file.
2687bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
                                unsigned SrcReg, bool Is32BitImm,
                                bool IsAddress, SMLoc IDLoc, MCStreamer &Out,
                                const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

if (!Is32BitImm && !isGP64bit()) {
  Error(IDLoc, "instruction requires a 64-bit architecture");
  return true;
}

if (Is32BitImm) {
  if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) {
    // Sign extend up to 64-bit so that the predicates match the hardware
    // behaviour. In particular, isInt<16>(0xffff8000) and similar should be
    // true.
    ImmValue = SignExtend64<32>(ImmValue);
  } else {
    Error(IDLoc, "instruction requires a 32-bit immediate");
    return true;
  }
}

unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg();
unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu;

bool UseSrcReg = false;
if (SrcReg != Mips::NoRegister)
  UseSrcReg = true;

unsigned TmpReg = DstReg;
if (UseSrcReg &&
    getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
  // At this point we need AT to perform the expansions and we exit if it is
  // not available.
  unsigned ATReg = getATReg(IDLoc);
  if (!ATReg)
    return true;
  TmpReg = ATReg;
}

if (isInt<16>(ImmValue)) {
  if (!UseSrcReg)
    SrcReg = ZeroReg;

  // This doesn't quite follow the usual ABI expectations for N32 but matches
  // traditional assembler behaviour. N32 would normally use addiu for both
  // integers and addresses.
  if (IsAddress && !Is32BitImm) {
    TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
    return false;
  }

  TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
  return false;
}

if (isUInt<16>(ImmValue)) {
  unsigned TmpReg = DstReg;
  if (SrcReg == DstReg) {
    TmpReg = getATReg(IDLoc);
    if (!TmpReg)
      return true;
  }

  TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
  if (UseSrcReg)
    TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI);
  return false;
}

if (isInt<32>(ImmValue) || isUInt<32>(ImmValue)) {
  warnIfNoMacro(IDLoc);

  uint16_t Bits31To16 = (ImmValue >> 16) & 0xffff;
  uint16_t Bits15To0 = ImmValue & 0xffff;
  if (!Is32BitImm && !isInt<32>(ImmValue)) {
    // Traditional behaviour seems to special case this particular value. It's
    // not clear why other masks are handled differently.
    if (ImmValue == 0xffffffff) {
      TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI);
      TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI);
      if (UseSrcReg)
        TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
      return false;
    }

    // Expand to an ORi instead of a LUi to avoid sign-extending into the
    // upper 32 bits.
    TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
    TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
    if (Bits15To0)
      TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
    if (UseSrcReg)
      TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
    return false;
  }

  TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI);
  if (Bits15To0)
    TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
  if (UseSrcReg)
    TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
  return false;
}

if (isShiftedUIntAtAnyPosition<16>(ImmValue)) {
  if (Is32BitImm) {
    Error(IDLoc, "instruction requires a 32-bit immediate");
    return true;
  }

  // We've processed ImmValue satisfying isUInt<16> above, so ImmValue must be
  // at least 17-bit wide here.
  unsigned BitWidth = llvm::bit_width((uint64_t)ImmValue);
  assert(BitWidth >= 17 && "ImmValue must be at least 17-bit wide")(static_cast <bool> (BitWidth >= 17 && "ImmValue must be at least 17-bit wide"
) ? void (0) : __assert_fail ("BitWidth >= 17 && \"ImmValue must be at least 17-bit wide\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2802, __extension__
 __PRETTY_FUNCTION__));

  // Traditionally, these immediates are shifted as little as possible and as
  // such we align the most significant bit to bit 15 of our temporary.
  unsigned ShiftAmount = BitWidth - 16;
  uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff;
  TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
  TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);

  if (UseSrcReg)
    TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);

  return false;
}

warnIfNoMacro(IDLoc);

// The remaining case is packed with a sequence of dsll and ori with zeros
// being omitted and any neighbouring dsll's being coalesced.
// The highest 32-bit's are equivalent to a 32-bit immediate load.

// Load bits 32-63 of ImmValue into bits 0-31 of the temporary register.
if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false,
                  IDLoc, Out, STI))
  return false;

// Shift and accumulate into the register. If a 16-bit chunk is zero, then
// skip it and defer the shift to the next chunk.
unsigned ShiftCarriedForwards = 16;
for (int BitNum = 16; BitNum >= 0; BitNum -= 16) {
  uint16_t ImmChunk = (ImmValue >> BitNum) & 0xffff;

  if (ImmChunk != 0) {
    TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
    TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI);
    ShiftCarriedForwards = 0;
  }

  ShiftCarriedForwards += 16;
}
ShiftCarriedForwards -= 16;

// Finish any remaining shifts left by trailing zeros.
if (ShiftCarriedForwards)
  TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);

if (UseSrcReg)
  TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);

return false;
2852}

2854bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
                                MCStreamer &Out, const MCSubtargetInfo *STI) {
const MCOperand &ImmOp = Inst.getOperand(1);
assert(ImmOp.isImm() && "expected immediate operand kind")(static_cast <bool> (ImmOp.isImm() && "expected immediate operand kind"
) ? void (0) : __assert_fail ("ImmOp.isImm() && \"expected immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2857, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind")(static_cast <bool> (DstRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("DstRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 2859, __extension__
 __PRETTY_FUNCTION__));

if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
                  Is32BitImm, false, IDLoc, Out, STI))
  return true;

return false;
2866}

2868bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg,
                                    const MCOperand &Offset,
                                    bool Is32BitAddress, SMLoc IDLoc,
                                    MCStreamer &Out,
                                    const MCSubtargetInfo *STI) {
// la can't produce a usable address when addresses are 64-bit.
if (Is32BitAddress && ABI.ArePtrs64bit()) {
  Warning(IDLoc, "la used to load 64-bit address");
  // Continue as if we had 'dla' instead.
  Is32BitAddress = false;
}

// dla requires 64-bit addresses.
if (!Is32BitAddress && !hasMips3()) {
  Error(IDLoc, "instruction requires a 64-bit architecture");
  return true;
}

if (!Offset.isImm())
  return loadAndAddSymbolAddress(Offset.getExpr(), DstReg, BaseReg,
                                 Is32BitAddress, IDLoc, Out, STI);

if (!ABI.ArePtrs64bit()) {
  // Continue as if we had 'la' whether we had 'la' or 'dla'.
  Is32BitAddress = true;
}

return loadImmediate(Offset.getImm(), DstReg, BaseReg, Is32BitAddress, true,
                     IDLoc, Out, STI);
2897}

2899bool MipsAsmParser::loadAndAddSymbolAddress(const MCExpr *SymExpr,
                                          unsigned DstReg, unsigned SrcReg,
                                          bool Is32BitSym, SMLoc IDLoc,
                                          MCStreamer &Out,
                                          const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO &&
                 SrcReg != Mips::ZERO_64;
warnIfNoMacro(IDLoc);

if (inPicMode()) {
  MCValue Res;
  if (!SymExpr->evaluateAsRelocatable(Res, nullptr, nullptr)) {
    Error(IDLoc, "expected relocatable expression");
    return true;
  }
  if (Res.getSymB() != nullptr) {
    Error(IDLoc, "expected relocatable expression with only one symbol");
    return true;
  }

  bool IsPtr64 = ABI.ArePtrs64bit();
  bool IsLocalSym =
      Res.getSymA()->getSymbol().isInSection() ||
      Res.getSymA()->getSymbol().isTemporary() ||
      (Res.getSymA()->getSymbol().isELF() &&
       cast<MCSymbolELF>(Res.getSymA()->getSymbol()).getBinding() ==
           ELF::STB_LOCAL);
  bool UseXGOT = STI->hasFeature(Mips::FeatureXGOT) && !IsLocalSym;

  // The case where the result register is $25 is somewhat special. If the
  // symbol in the final relocation is external and not modified with a
  // constant then we must use R_MIPS_CALL16 instead of R_MIPS_GOT16
  // or R_MIPS_CALL16 instead of R_MIPS_GOT_DISP in 64-bit case.
  if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg &&
      Res.getConstant() == 0 && !IsLocalSym) {
    if (UseXGOT) {
      const MCExpr *CallHiExpr = MipsMCExpr::create(MipsMCExpr::MEK_CALL_HI16,
                                                    SymExpr, getContext());
      const MCExpr *CallLoExpr = MipsMCExpr::create(MipsMCExpr::MEK_CALL_LO16,
                                                    SymExpr, getContext());
      TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc,
                  STI);
      TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg,
                   IDLoc, STI);
      TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, DstReg,
                   MCOperand::createExpr(CallLoExpr), IDLoc, STI);
    } else {
      const MCExpr *CallExpr =
          MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, SymExpr, getContext());
      TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg,
                   MCOperand::createExpr(CallExpr), IDLoc, STI);
    }
    return false;
  }

  unsigned TmpReg = DstReg;
  if (UseSrcReg &&
      getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg,
                                                             SrcReg)) {
    // If $rs is the same as $rd, we need to use AT.
    // If it is not available we exit.
    unsigned ATReg = getATReg(IDLoc);
    if (!ATReg)
      return true;
    TmpReg = ATReg;
  }

  // FIXME: In case of N32 / N64 ABI and emabled XGOT, local addresses
  // loaded using R_MIPS_GOT_PAGE / R_MIPS_GOT_OFST pair of relocations.
  // FIXME: Implement XGOT for microMIPS.
  if (UseXGOT) {
    // Loading address from XGOT
    //   External GOT: lui $tmp, %got_hi(symbol)($gp)
    //                 addu $tmp, $tmp, $gp
    //                 lw $tmp, %got_lo(symbol)($tmp)
    //                >addiu $tmp, $tmp, offset
    //                >addiu $rd, $tmp, $rs
    // The addiu's marked with a '>' may be omitted if they are redundant. If
    // this happens then the last instruction must use $rd as the result
    // register.
    const MCExpr *CallHiExpr =
        MipsMCExpr::create(MipsMCExpr::MEK_GOT_HI16, SymExpr, getContext());
    const MCExpr *CallLoExpr = MipsMCExpr::create(
        MipsMCExpr::MEK_GOT_LO16, Res.getSymA(), getContext());

    TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(CallHiExpr), IDLoc,
                STI);
    TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, GPReg,
                 IDLoc, STI);
    TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg,
                 MCOperand::createExpr(CallLoExpr), IDLoc, STI);

    if (Res.getConstant() != 0)
      TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
                   MCOperand::createExpr(MCConstantExpr::create(
                       Res.getConstant(), getContext())),
                   IDLoc, STI);

    if (UseSrcReg)
      TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg,
                   IDLoc, STI);
    return false;
  }

  const MipsMCExpr *GotExpr = nullptr;
  const MCExpr *LoExpr = nullptr;
  if (ABI.IsN32() || ABI.IsN64()) {
    // The remaining cases are:
    //   Small offset: ld $tmp, %got_disp(symbol)($gp)
    //                >daddiu $tmp, $tmp, offset
    //                >daddu $rd, $tmp, $rs
    // The daddiu's marked with a '>' may be omitted if they are redundant. If
    // this happens then the last instruction must use $rd as the result
    // register.
    GotExpr = MipsMCExpr::create(MipsMCExpr::MEK_GOT_DISP, Res.getSymA(),
                                 getContext());
    if (Res.getConstant() != 0) {
      // Symbols fully resolve with just the %got_disp(symbol) but we
      // must still account for any offset to the symbol for
      // expressions like symbol+8.
      LoExpr = MCConstantExpr::create(Res.getConstant(), getContext());

      // FIXME: Offsets greater than 16 bits are not yet implemented.
      // FIXME: The correct range is a 32-bit sign-extended number.
      if (Res.getConstant() < -0x8000 || Res.getConstant() > 0x7fff) {
        Error(IDLoc, "macro instruction uses large offset, which is not "
                     "currently supported");
        return true;
      }
    }
  } else {
    // The remaining cases are:
    //   External GOT: lw $tmp, %got(symbol)($gp)
    //                >addiu $tmp, $tmp, offset
    //                >addiu $rd, $tmp, $rs
    //   Local GOT:    lw $tmp, %got(symbol+offset)($gp)
    //                 addiu $tmp, $tmp, %lo(symbol+offset)($gp)
    //                >addiu $rd, $tmp, $rs
    // The addiu's marked with a '>' may be omitted if they are redundant. If
    // this happens then the last instruction must use $rd as the result
    // register.
    if (IsLocalSym) {
      GotExpr =
          MipsMCExpr::create(MipsMCExpr::MEK_GOT, SymExpr, getContext());
      LoExpr = MipsMCExpr::create(MipsMCExpr::MEK_LO, SymExpr, getContext());
    } else {
      // External symbols fully resolve the symbol with just the %got(symbol)
      // but we must still account for any offset to the symbol for
      // expressions like symbol+8.
      GotExpr = MipsMCExpr::create(MipsMCExpr::MEK_GOT, Res.getSymA(),
                                   getContext());
      if (Res.getConstant() != 0)
        LoExpr = MCConstantExpr::create(Res.getConstant(), getContext());
    }
  }

  TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, GPReg,
               MCOperand::createExpr(GotExpr), IDLoc, STI);

  if (LoExpr)
    TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
                 MCOperand::createExpr(LoExpr), IDLoc, STI);

  if (UseSrcReg)
    TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg,
                 IDLoc, STI);

  return false;
}

const MipsMCExpr *HiExpr =
    MipsMCExpr::create(MipsMCExpr::MEK_HI, SymExpr, getContext());
const MipsMCExpr *LoExpr =
    MipsMCExpr::create(MipsMCExpr::MEK_LO, SymExpr, getContext());

// This is the 64-bit symbol address expansion.
if (ABI.ArePtrs64bit() && isGP64bit()) {
  // We need AT for the 64-bit expansion in the cases where the optional
  // source register is the destination register and for the superscalar
  // scheduled form.
  //
  // If it is not available we exit if the destination is the same as the
  // source register.

  const MipsMCExpr *HighestExpr =
      MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, SymExpr, getContext());
  const MipsMCExpr *HigherExpr =
      MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, SymExpr, getContext());

  bool RdRegIsRsReg =
      getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg);

  if (canUseATReg() && UseSrcReg && RdRegIsRsReg) {
    unsigned ATReg = getATReg(IDLoc);

    // If $rs is the same as $rd:
    // (d)la $rd, sym($rd) => lui    $at, %highest(sym)
    //                        daddiu $at, $at, %higher(sym)
    //                        dsll   $at, $at, 16
    //                        daddiu $at, $at, %hi(sym)
    //                        dsll   $at, $at, 16
    //                        daddiu $at, $at, %lo(sym)
    //                        daddu  $rd, $at, $rd
    TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
                STI);
    TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
                 MCOperand::createExpr(HigherExpr), IDLoc, STI);
    TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
    TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),
                 IDLoc, STI);
    TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
    TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
                 IDLoc, STI);
    TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI);

    return false;
  } else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) {
    unsigned ATReg = getATReg(IDLoc);

    // If the $rs is different from $rd or if $rs isn't specified and we
    // have $at available:
    // (d)la $rd, sym/sym($rs) => lui    $rd, %highest(sym)
    //                            lui    $at, %hi(sym)
    //                            daddiu $rd, $rd, %higher(sym)
    //                            daddiu $at, $at, %lo(sym)
    //                            dsll32 $rd, $rd, 0
    //                            daddu  $rd, $rd, $at
    //                            (daddu  $rd, $rd, $rs)
    //
    // Which is preferred for superscalar issue.
    TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
                STI);
    TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
    TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
                 MCOperand::createExpr(HigherExpr), IDLoc, STI);
    TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
                 IDLoc, STI);
    TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI);
    TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI);
    if (UseSrcReg)
      TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);

    return false;
  } else if ((!canUseATReg() && !RdRegIsRsReg) ||
             (canUseATReg() && DstReg == getATReg(IDLoc))) {
    // Otherwise, synthesize the address in the destination register
    // serially:
    // (d)la $rd, sym/sym($rs) => lui    $rd, %highest(sym)
    //                            daddiu $rd, $rd, %higher(sym)
    //                            dsll   $rd, $rd, 16
    //                            daddiu $rd, $rd, %hi(sym)
    //                            dsll   $rd, $rd, 16
    //                            daddiu $rd, $rd, %lo(sym)
    TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
                STI);
    TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
                 MCOperand::createExpr(HigherExpr), IDLoc, STI);
    TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI);
    TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
                 MCOperand::createExpr(HiExpr), IDLoc, STI);
    TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI);
    TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
                 MCOperand::createExpr(LoExpr), IDLoc, STI);
    if (UseSrcReg)
      TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);

    return false;
  } else {
    // We have a case where SrcReg == DstReg and we don't have $at
    // available. We can't expand this case, so error out appropriately.
    assert(SrcReg == DstReg && !canUseATReg() &&(static_cast <bool> (SrcReg == DstReg && !canUseATReg
() && "Could have expanded dla but didn't?") ? void (
0) : __assert_fail ("SrcReg == DstReg && !canUseATReg() && \"Could have expanded dla but didn't?\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3171, __extension__
 __PRETTY_FUNCTION__))
           "Could have expanded dla but didn't?")(static_cast <bool> (SrcReg == DstReg && !canUseATReg
() && "Could have expanded dla but didn't?") ? void (
0) : __assert_fail ("SrcReg == DstReg && !canUseATReg() && \"Could have expanded dla but didn't?\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3171, __extension__
 __PRETTY_FUNCTION__));
    reportParseError(IDLoc,
                   "pseudo-instruction requires $at, which is not available");
    return true;
  }
}

// And now, the 32-bit symbol address expansion:
// If $rs is the same as $rd:
// (d)la $rd, sym($rd)     => lui   $at, %hi(sym)
//                            ori   $at, $at, %lo(sym)
//                            addu  $rd, $at, $rd
// Otherwise, if the $rs is different from $rd or if $rs isn't specified:
// (d)la $rd, sym/sym($rs) => lui   $rd, %hi(sym)
//                            ori   $rd, $rd, %lo(sym)
//                            (addu $rd, $rd, $rs)
unsigned TmpReg = DstReg;
if (UseSrcReg &&
    getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) {
  // If $rs is the same as $rd, we need to use AT.
  // If it is not available we exit.
  unsigned ATReg = getATReg(IDLoc);
  if (!ATReg)
    return true;
  TmpReg = ATReg;
}

TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
             IDLoc, STI);

if (UseSrcReg)
  TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
else
  assert((static_cast <bool> (getContext().getRegisterInfo()->
isSuperOrSubRegisterEq(DstReg, TmpReg)) ? void (0) : __assert_fail
 ("getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg)"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3206, __extension__
 __PRETTY_FUNCTION__))
      getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg))(static_cast <bool> (getContext().getRegisterInfo()->
isSuperOrSubRegisterEq(DstReg, TmpReg)) ? void (0) : __assert_fail
 ("getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, TmpReg)"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3206, __extension__
 __PRETTY_FUNCTION__));

return false;
3209}

3211// Each double-precision register DO-D15 overlaps with two of the single
3212// precision registers F0-F31. As an example, all of the following hold true:
3213// D0 + 1 == F1, F1 + 1 == D1, F1 + 1 == F2, depending on the context.
3214static unsigned nextReg(unsigned Reg) {
if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg))
  return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1;
switch (Reg) {
default: llvm_unreachable("Unknown register in assembly macro expansion!")::llvm::llvm_unreachable_internal("Unknown register in assembly macro expansion!"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3218);
case Mips::ZERO: return Mips::AT;
case Mips::AT:   return Mips::V0;
case Mips::V0:   return Mips::V1;
case Mips::V1:   return Mips::A0;
case Mips::A0:   return Mips::A1;
case Mips::A1:   return Mips::A2;
case Mips::A2:   return Mips::A3;
case Mips::A3:   return Mips::T0;
case Mips::T0:   return Mips::T1;
case Mips::T1:   return Mips::T2;
case Mips::T2:   return Mips::T3;
case Mips::T3:   return Mips::T4;
case Mips::T4:   return Mips::T5;
case Mips::T5:   return Mips::T6;
case Mips::T6:   return Mips::T7;
case Mips::T7:   return Mips::S0;
case Mips::S0:   return Mips::S1;
case Mips::S1:   return Mips::S2;
case Mips::S2:   return Mips::S3;
case Mips::S3:   return Mips::S4;
case Mips::S4:   return Mips::S5;
case Mips::S5:   return Mips::S6;
case Mips::S6:   return Mips::S7;
case Mips::S7:   return Mips::T8;
case Mips::T8:   return Mips::T9;
case Mips::T9:   return Mips::K0;
case Mips::K0:   return Mips::K1;
case Mips::K1:   return Mips::GP;
case Mips::GP:   return Mips::SP;
case Mips::SP:   return Mips::FP;
case Mips::FP:   return Mips::RA;
case Mips::RA:   return Mips::ZERO;
case Mips::D0:   return Mips::F1;
case Mips::D1:   return Mips::F3;
case Mips::D2:   return Mips::F5;
case Mips::D3:   return Mips::F7;
case Mips::D4:   return Mips::F9;
case Mips::D5:   return Mips::F11;
case Mips::D6:   return Mips::F13;
case Mips::D7:   return Mips::F15;
case Mips::D8:   return Mips::F17;
case Mips::D9:   return Mips::F19;
case Mips::D10:   return Mips::F21;
case Mips::D11:   return Mips::F23;
case Mips::D12:   return Mips::F25;
case Mips::D13:   return Mips::F27;
case Mips::D14:   return Mips::F29;
case Mips::D15:   return Mips::F31;
}
3268}

3270// FIXME: This method is too general. In principle we should compute the number
3271// of instructions required to synthesize the immediate inline compared to
3272// synthesizing the address inline and relying on non .text sections.
3273// For static O32 and N32 this may yield a small benefit, for static N64 this is
3274// likely to yield a much larger benefit as we have to synthesize a 64bit
3275// address to load a 64 bit value.
3276bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc,
                                     MCSymbol *Sym) {
unsigned ATReg = getATReg(IDLoc);
if (!ATReg)
  return true;

if(IsPicEnabled) {
  const MCExpr *GotSym =
      MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
  const MipsMCExpr *GotExpr =
      MipsMCExpr::create(MipsMCExpr::MEK_GOT, GotSym, getContext());

  if(isABI_O32() || isABI_N32()) {
    TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr),
                 IDLoc, STI);
  } else { //isABI_N64()
    TOut.emitRRX(Mips::LD, ATReg, GPReg, MCOperand::createExpr(GotExpr),
                 IDLoc, STI);
  }
} else { //!IsPicEnabled
  const MCExpr *HiSym =
      MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
  const MipsMCExpr *HiExpr =
      MipsMCExpr::create(MipsMCExpr::MEK_HI, HiSym, getContext());

  // FIXME: This is technically correct but gives a different result to gas,
  // but gas is incomplete there (it has a fixme noting it doesn't work with
  // 64-bit addresses).
  // FIXME: With -msym32 option, the address expansion for N64 should probably
  // use the O32 / N32 case. It's safe to use the 64 address expansion as the
  // symbol's value is considered sign extended.
  if(isABI_O32() || isABI_N32()) {
    TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
  } else { //isABI_N64()
    const MCExpr *HighestSym =
        MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
    const MipsMCExpr *HighestExpr =
        MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, HighestSym, getContext());
    const MCExpr *HigherSym =
        MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
    const MipsMCExpr *HigherExpr =
        MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, HigherSym, getContext());

    TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
                STI);
    TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
                 MCOperand::createExpr(HigherExpr), IDLoc, STI);
    TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
    TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),
                 IDLoc, STI);
    TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
  }
}
return false;
3330}

3332static uint64_t convertIntToDoubleImm(uint64_t ImmOp64) {
// If ImmOp64 is AsmToken::Integer type (all bits set to zero in the
// exponent field), convert it to double (e.g. 1 to 1.0)
if ((Hi_32(ImmOp64) & 0x7ff00000) == 0) {
  APFloat RealVal(APFloat::IEEEdouble(), ImmOp64);
  ImmOp64 = RealVal.bitcastToAPInt().getZExtValue();
}
return ImmOp64;
3340}

3342static uint32_t covertDoubleImmToSingleImm(uint64_t ImmOp64) {
// Conversion of a double in an uint64_t to a float in a uint32_t,
// retaining the bit pattern of a float.
double DoubleImm = llvm::bit_cast<double>(ImmOp64);
float TmpFloat = static_cast<float>(DoubleImm);
return llvm::bit_cast<uint32_t>(TmpFloat);
3348}

3350bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc,
                                           MCStreamer &Out,
                                           const MCSubtargetInfo *STI) {
assert(Inst.getNumOperands() == 2 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 2 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 2 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3353, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isImm() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3355, __extension__
 __PRETTY_FUNCTION__))
       "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isImm() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3355, __extension__
 __PRETTY_FUNCTION__));

unsigned FirstReg = Inst.getOperand(0).getReg();
uint64_t ImmOp64 = Inst.getOperand(1).getImm();

uint32_t ImmOp32 = covertDoubleImmToSingleImm(convertIntToDoubleImm(ImmOp64));

return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc,
                     Out, STI);
3364}

3366bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc,
                                           MCStreamer &Out,
                                           const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
assert(Inst.getNumOperands() == 2 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 2 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 2 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3370, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isImm() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3372, __extension__
 __PRETTY_FUNCTION__))
       "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isImm() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3372, __extension__
 __PRETTY_FUNCTION__));

unsigned FirstReg = Inst.getOperand(0).getReg();
uint64_t ImmOp64 = Inst.getOperand(1).getImm();

ImmOp64 = convertIntToDoubleImm(ImmOp64);

uint32_t ImmOp32 = covertDoubleImmToSingleImm(ImmOp64);

unsigned TmpReg = Mips::ZERO;
if (ImmOp32 != 0) {
  TmpReg = getATReg(IDLoc);
  if (!TmpReg)
    return true;
}

if (Lo_32(ImmOp64) == 0) {
  if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister,
                                            true, false, IDLoc, Out, STI))
    return true;
  TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
  return false;
}

MCSection *CS = getStreamer().getCurrentSectionOnly();
// FIXME: Enhance this expansion to use the .lit4 & .lit8 sections
// where appropriate.
MCSection *ReadOnlySection =
    getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);

MCSymbol *Sym = getContext().createTempSymbol();
const MCExpr *LoSym =
    MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
const MipsMCExpr *LoExpr =
    MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());

getStreamer().switchSection(ReadOnlySection);
getStreamer().emitLabel(Sym, IDLoc);
getStreamer().emitInt32(ImmOp32);
getStreamer().switchSection(CS);

if (emitPartialAddress(TOut, IDLoc, Sym))
  return true;
TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr),
             IDLoc, STI);
return false;
3418}

3420bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc,
                                           MCStreamer &Out,
                                           const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
assert(Inst.getNumOperands() == 2 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 2 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 2 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3424, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isImm() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3426, __extension__
 __PRETTY_FUNCTION__))
       "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isImm() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3426, __extension__
 __PRETTY_FUNCTION__));

unsigned FirstReg = Inst.getOperand(0).getReg();
uint64_t ImmOp64 = Inst.getOperand(1).getImm();

ImmOp64 = convertIntToDoubleImm(ImmOp64);

if (Lo_32(ImmOp64) == 0) {
  if (isGP64bit()) {
    if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false,
                      IDLoc, Out, STI))
      return true;
  } else {
    if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false,
                      IDLoc, Out, STI))
      return true;

    if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false,
                      IDLoc, Out, STI))
      return true;
  }
  return false;
}

MCSection *CS = getStreamer().getCurrentSectionOnly();
MCSection *ReadOnlySection =
    getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);

MCSymbol *Sym = getContext().createTempSymbol();
const MCExpr *LoSym =
    MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
const MipsMCExpr *LoExpr =
    MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());

getStreamer().switchSection(ReadOnlySection);
getStreamer().emitLabel(Sym, IDLoc);
getStreamer().emitValueToAlignment(Align(8));
getStreamer().emitIntValue(ImmOp64, 8);
getStreamer().switchSection(CS);

unsigned TmpReg = getATReg(IDLoc);
if (!TmpReg)
  return true;

if (emitPartialAddress(TOut, IDLoc, Sym))
  return true;

TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
             MCOperand::createExpr(LoExpr), IDLoc, STI);

if (isGP64bit())
  TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI);
else {
  TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI);
  TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI);
}
return false;
3483}

3485bool MipsAsmParser::expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU,
                                           SMLoc IDLoc, MCStreamer &Out,
                                           const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
assert(Inst.getNumOperands() == 2 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 2 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 2 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3489, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isImm() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3491, __extension__
 __PRETTY_FUNCTION__))
       "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isImm() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3491, __extension__
 __PRETTY_FUNCTION__));

unsigned FirstReg = Inst.getOperand(0).getReg();
uint64_t ImmOp64 = Inst.getOperand(1).getImm();

ImmOp64 = convertIntToDoubleImm(ImmOp64);

unsigned TmpReg = Mips::ZERO;
if (ImmOp64 != 0) {
  TmpReg = getATReg(IDLoc);
  if (!TmpReg)
    return true;
}

if ((Lo_32(ImmOp64) == 0) &&
    !((Hi_32(ImmOp64) & 0xffff0000) && (Hi_32(ImmOp64) & 0x0000ffff))) {
  if (isGP64bit()) {
    if (TmpReg != Mips::ZERO &&
        loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc,
                      Out, STI))
      return true;
    TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
    return false;
  }

  if (TmpReg != Mips::ZERO &&
      loadImmediate(Hi_32(ImmOp64), TmpReg, Mips::NoRegister, true, false,
                    IDLoc, Out, STI))
    return true;

  if (hasMips32r2()) {
    TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
    TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI);
  } else {
    TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);
    TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
  }
  return false;
}

MCSection *CS = getStreamer().getCurrentSectionOnly();
// FIXME: Enhance this expansion to use the .lit4 & .lit8 sections
// where appropriate.
MCSection *ReadOnlySection =
    getContext().getELFSection(".rodata", ELF::SHT_PROGBITS, ELF::SHF_ALLOC);

MCSymbol *Sym = getContext().createTempSymbol();
const MCExpr *LoSym =
    MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
const MipsMCExpr *LoExpr =
    MipsMCExpr::create(MipsMCExpr::MEK_LO, LoSym, getContext());

getStreamer().switchSection(ReadOnlySection);
getStreamer().emitLabel(Sym, IDLoc);
getStreamer().emitValueToAlignment(Align(8));
getStreamer().emitIntValue(ImmOp64, 8);
getStreamer().switchSection(CS);

if (emitPartialAddress(TOut, IDLoc, Sym))
  return true;

TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg,
             MCOperand::createExpr(LoExpr), IDLoc, STI);

return false;
3556}

3558bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc,
                                             MCStreamer &Out,
                                             const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(MII.get(Inst.getOpcode()).getNumOperands() == 1 &&(static_cast <bool> (MII.get(Inst.getOpcode()).getNumOperands
() == 1 && "unexpected number of operands") ? void (0
) : __assert_fail ("MII.get(Inst.getOpcode()).getNumOperands() == 1 && \"unexpected number of operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3564, __extension__
 __PRETTY_FUNCTION__))
       "unexpected number of operands")(static_cast <bool> (MII.get(Inst.getOpcode()).getNumOperands
() == 1 && "unexpected number of operands") ? void (0
) : __assert_fail ("MII.get(Inst.getOpcode()).getNumOperands() == 1 && \"unexpected number of operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3564, __extension__
 __PRETTY_FUNCTION__));

MCOperand Offset = Inst.getOperand(0);
if (Offset.isExpr()) {
  Inst.clear();
  Inst.setOpcode(Mips::BEQ_MM);
  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
  Inst.addOperand(MCOperand::createReg(Mips::ZERO));
  Inst.addOperand(MCOperand::createExpr(Offset.getExpr()));
} else {
  assert(Offset.isImm() && "expected immediate operand kind")(static_cast <bool> (Offset.isImm() && "expected immediate operand kind"
) ? void (0) : __assert_fail ("Offset.isImm() && \"expected immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3574, __extension__
 __PRETTY_FUNCTION__));
  if (isInt<11>(Offset.getImm())) {
    // If offset fits into 11 bits then this instruction becomes microMIPS
    // 16-bit unconditional branch instruction.
    if (inMicroMipsMode())
      Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM);
  } else {
    if (!isInt<17>(Offset.getImm()))
      return Error(IDLoc, "branch target out of range");
    if (offsetToAlignment(Offset.getImm(), Align(2)))
      return Error(IDLoc, "branch to misaligned address");
    Inst.clear();
    Inst.setOpcode(Mips::BEQ_MM);
    Inst.addOperand(MCOperand::createReg(Mips::ZERO));
    Inst.addOperand(MCOperand::createReg(Mips::ZERO));
    Inst.addOperand(MCOperand::createImm(Offset.getImm()));
  }
}
Out.emitInstruction(Inst, *STI);

// If .set reorder is active and branch instruction has a delay slot,
// emit a NOP after it.
const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder())
  TOut.emitEmptyDelaySlot(true, IDLoc, STI);

return false;
3601}

3603bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                  const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind")(static_cast <bool> (DstRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("DstRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3607, __extension__
 __PRETTY_FUNCTION__));

const MCOperand &ImmOp = Inst.getOperand(1);
assert(ImmOp.isImm() && "expected immediate operand kind")(static_cast <bool> (ImmOp.isImm() && "expected immediate operand kind"
) ? void (0) : __assert_fail ("ImmOp.isImm() && \"expected immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3610, __extension__
 __PRETTY_FUNCTION__));

const MCOperand &MemOffsetOp = Inst.getOperand(2);
assert((MemOffsetOp.isImm() || MemOffsetOp.isExpr()) &&(static_cast <bool> ((MemOffsetOp.isImm() || MemOffsetOp
.isExpr()) && "expected immediate or expression operand"
) ? void (0) : __assert_fail ("(MemOffsetOp.isImm() || MemOffsetOp.isExpr()) && \"expected immediate or expression operand\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3614, __extension__
 __PRETTY_FUNCTION__))
       "expected immediate or expression operand")(static_cast <bool> ((MemOffsetOp.isImm() || MemOffsetOp
.isExpr()) && "expected immediate or expression operand"
) ? void (0) : __assert_fail ("(MemOffsetOp.isImm() || MemOffsetOp.isExpr()) && \"expected immediate or expression operand\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3614, __extension__
 __PRETTY_FUNCTION__));

bool IsLikely = false;

unsigned OpCode = 0;
switch(Inst.getOpcode()) {
  case Mips::BneImm:
    OpCode = Mips::BNE;
    break;
  case Mips::BeqImm:
    OpCode = Mips::BEQ;
    break;
  case Mips::BEQLImmMacro:
    OpCode = Mips::BEQL;
    IsLikely = true;
    break;
  case Mips::BNELImmMacro:
    OpCode = Mips::BNEL;
    IsLikely = true;
    break;
  default:
    llvm_unreachable("Unknown immediate branch pseudo-instruction.")::llvm::llvm_unreachable_internal("Unknown immediate branch pseudo-instruction."
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3635);
    break;
}

int64_t ImmValue = ImmOp.getImm();
if (ImmValue == 0) {
  if (IsLikely) {
    TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,
                 MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI);
    TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
  } else
    TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
            STI);
} else {
  warnIfNoMacro(IDLoc);

  unsigned ATReg = getATReg(IDLoc);
  if (!ATReg)
    return true;

  if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true,
                    IDLoc, Out, STI))
    return true;

  if (IsLikely) {
    TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg,
            MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI);
    TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
  } else
    TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
}
return false;
3667}

3669void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                  const MCSubtargetInfo *STI, bool IsLoad) {
unsigned NumOp = Inst.getNumOperands();
assert((NumOp == 3 || NumOp == 4) && "unexpected operands number")(static_cast <bool> ((NumOp == 3 || NumOp == 4) &&
 "unexpected operands number") ? void (0) : __assert_fail ("(NumOp == 3 || NumOp == 4) && \"unexpected operands number\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3672, __extension__
 __PRETTY_FUNCTION__));
unsigned StartOp = NumOp == 3 ? 0 : 1;

const MCOperand &DstRegOp = Inst.getOperand(StartOp);
assert(DstRegOp.isReg() && "expected register operand kind")(static_cast <bool> (DstRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("DstRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3676, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &BaseRegOp = Inst.getOperand(StartOp + 1);
assert(BaseRegOp.isReg() && "expected register operand kind")(static_cast <bool> (BaseRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("BaseRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3678, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &OffsetOp = Inst.getOperand(StartOp + 2);

MipsTargetStreamer &TOut = getTargetStreamer();
unsigned OpCode = Inst.getOpcode();
unsigned DstReg = DstRegOp.getReg();
unsigned BaseReg = BaseRegOp.getReg();
unsigned TmpReg = DstReg;

const MCInstrDesc &Desc = MII.get(OpCode);
int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
unsigned DstRegClassID =
    getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
             (DstRegClassID == Mips::GPR64RegClassID);

if (!IsLoad || !IsGPR || (BaseReg == DstReg)) {
  // At this point we need AT to perform the expansions
  // and we exit if it is not available.
  TmpReg = getATReg(IDLoc);
  if (!TmpReg)
    return;
}

auto emitInstWithOffset = [&](const MCOperand &Off) {
  if (NumOp == 3)
    TOut.emitRRX(OpCode, DstReg, TmpReg, Off, IDLoc, STI);
  else
    TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, Off, IDLoc, STI);
};

if (OffsetOp.isImm()) {
  int64_t LoOffset = OffsetOp.getImm() & 0xffff;
  int64_t HiOffset = OffsetOp.getImm() & ~0xffff;

  // If msb of LoOffset is 1(negative number) we must increment
  // HiOffset to account for the sign-extension of the low part.
  if (LoOffset & 0x8000)
    HiOffset += 0x10000;

  bool IsLargeOffset = HiOffset != 0;

  if (IsLargeOffset) {
    bool Is32BitImm = isInt<32>(OffsetOp.getImm());
    if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true,
                      IDLoc, Out, STI))
      return;
  }

  if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
    TOut.emitRRR(ABI.ArePtrs64bit() ? Mips::DADDu : Mips::ADDu, TmpReg,
                 TmpReg, BaseReg, IDLoc, STI);
  emitInstWithOffset(MCOperand::createImm(int16_t(LoOffset)));
  return;
}

if (OffsetOp.isExpr()) {
  if (inPicMode()) {
    // FIXME:
    // c) Check that immediates of R_MIPS_GOT16/R_MIPS_LO16 relocations
    //    do not exceed 16-bit.
    // d) Use R_MIPS_GOT_PAGE/R_MIPS_GOT_OFST relocations instead
    //    of R_MIPS_GOT_DISP in appropriate cases to reduce number
    //    of GOT entries.
    MCValue Res;
    if (!OffsetOp.getExpr()->evaluateAsRelocatable(Res, nullptr, nullptr)) {
      Error(IDLoc, "expected relocatable expression");
      return;
    }
    if (Res.getSymB() != nullptr) {
      Error(IDLoc, "expected relocatable expression with only one symbol");
      return;
    }

    loadAndAddSymbolAddress(Res.getSymA(), TmpReg, BaseReg,
                            !ABI.ArePtrs64bit(), IDLoc, Out, STI);
    emitInstWithOffset(MCOperand::createImm(int16_t(Res.getConstant())));
  } else {
    // FIXME: Implement 64-bit case.
    // 1) lw $8, sym => lui $8,  %hi(sym)
    //                  lw  $8,  %lo(sym)($8)
    // 2) sw $8, sym => lui $at, %hi(sym)
    //                  sw  $8,  %lo(sym)($at)
    const MCExpr *OffExpr = OffsetOp.getExpr();
    MCOperand LoOperand = MCOperand::createExpr(
        MipsMCExpr::create(MipsMCExpr::MEK_LO, OffExpr, getContext()));
    MCOperand HiOperand = MCOperand::createExpr(
        MipsMCExpr::create(MipsMCExpr::MEK_HI, OffExpr, getContext()));

    if (ABI.IsN64()) {
      MCOperand HighestOperand = MCOperand::createExpr(
          MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, OffExpr, getContext()));
      MCOperand HigherOperand = MCOperand::createExpr(
          MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, OffExpr, getContext()));

      TOut.emitRX(Mips::LUi, TmpReg, HighestOperand, IDLoc, STI);
      TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HigherOperand, IDLoc, STI);
      TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
      TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HiOperand, IDLoc, STI);
      TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
      if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
        TOut.emitRRR(Mips::DADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
      emitInstWithOffset(LoOperand);
    } else {
      // Generate the base address in TmpReg.
      TOut.emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
      if (BaseReg != Mips::ZERO)
        TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
      // Emit the load or store with the adjusted base and offset.
      emitInstWithOffset(LoOperand);
    }
  }
  return;
}

llvm_unreachable("unexpected operand type")::llvm::llvm_unreachable_internal("unexpected operand type", "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp"
, 3793);
3794}

3796void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                 const MCSubtargetInfo *STI, bool IsLoad) {
unsigned NumOp = Inst.getNumOperands();
assert((NumOp == 3 || NumOp == 4) && "unexpected operands number")(static_cast <bool> ((NumOp == 3 || NumOp == 4) &&
 "unexpected operands number") ? void (0) : __assert_fail ("(NumOp == 3 || NumOp == 4) && \"unexpected operands number\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3799, __extension__
 __PRETTY_FUNCTION__));
unsigned StartOp = NumOp == 3 ? 0 : 1;

const MCOperand &DstRegOp = Inst.getOperand(StartOp);
assert(DstRegOp.isReg() && "expected register operand kind")(static_cast <bool> (DstRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("DstRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3803, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &BaseRegOp = Inst.getOperand(StartOp + 1);
assert(BaseRegOp.isReg() && "expected register operand kind")(static_cast <bool> (BaseRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("BaseRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3805, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &OffsetOp = Inst.getOperand(StartOp + 2);

MipsTargetStreamer &TOut = getTargetStreamer();
unsigned OpCode = Inst.getOpcode();
unsigned DstReg = DstRegOp.getReg();
unsigned BaseReg = BaseRegOp.getReg();
unsigned TmpReg = DstReg;

const MCInstrDesc &Desc = MII.get(OpCode);
int16_t DstRegClass = Desc.operands()[StartOp].RegClass;
unsigned DstRegClassID =
    getContext().getRegisterInfo()->getRegClass(DstRegClass).getID();
bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
             (DstRegClassID == Mips::GPR64RegClassID);

if (!IsLoad || !IsGPR || (BaseReg == DstReg)) {
  // At this point we need AT to perform the expansions
  // and we exit if it is not available.
  TmpReg = getATReg(IDLoc);
  if (!TmpReg)
    return;
}

auto emitInst = [&]() {
  if (NumOp == 3)
    TOut.emitRRX(OpCode, DstReg, TmpReg, MCOperand::createImm(0), IDLoc, STI);
  else
    TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, MCOperand::createImm(0),
                  IDLoc, STI);
};

if (OffsetOp.isImm()) {
  loadImmediate(OffsetOp.getImm(), TmpReg, BaseReg, !ABI.ArePtrs64bit(), true,
                IDLoc, Out, STI);
  emitInst();
  return;
}

if (OffsetOp.isExpr()) {
  loadAndAddSymbolAddress(OffsetOp.getExpr(), TmpReg, BaseReg,
                          !ABI.ArePtrs64bit(), IDLoc, Out, STI);
  emitInst();
  return;
}

llvm_unreachable("unexpected operand type")::llvm::llvm_unreachable_internal("unexpected operand type", "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp"
, 3851);
3852}

3854bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
                                          MCStreamer &Out,
                                          const MCSubtargetInfo *STI) {
unsigned OpNum = Inst.getNumOperands();
unsigned Opcode = Inst.getOpcode();
unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM;

assert(Inst.getOperand(OpNum - 1).isImm() &&(static_cast <bool> (Inst.getOperand(OpNum - 1).isImm()
 && Inst.getOperand(OpNum - 2).isReg() && Inst
.getOperand(OpNum - 3).isReg() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(OpNum - 1).isImm() && Inst.getOperand(OpNum - 2).isReg() && Inst.getOperand(OpNum - 3).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3863, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(OpNum - 2).isReg() &&(static_cast <bool> (Inst.getOperand(OpNum - 1).isImm()
 && Inst.getOperand(OpNum - 2).isReg() && Inst
.getOperand(OpNum - 3).isReg() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(OpNum - 1).isImm() && Inst.getOperand(OpNum - 2).isReg() && Inst.getOperand(OpNum - 3).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3863, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(OpNum - 3).isReg() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(OpNum - 1).isImm()
 && Inst.getOperand(OpNum - 2).isReg() && Inst
.getOperand(OpNum - 3).isReg() && "Invalid instruction operand."
) ? void (0) : __assert_fail ("Inst.getOperand(OpNum - 1).isImm() && Inst.getOperand(OpNum - 2).isReg() && Inst.getOperand(OpNum - 3).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3863, __extension__
 __PRETTY_FUNCTION__));

if (OpNum < 8 && Inst.getOperand(OpNum - 1).getImm() <= 60 &&
    Inst.getOperand(OpNum - 1).getImm() >= 0 &&
    (Inst.getOperand(OpNum - 2).getReg() == Mips::SP ||
     Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) &&
    (Inst.getOperand(OpNum - 3).getReg() == Mips::RA ||
     Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) {
  // It can be implemented as SWM16 or LWM16 instruction.
  if (inMicroMipsMode() && hasMips32r6())
    NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6;
  else
    NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
}

Inst.setOpcode(NewOpcode);
Out.emitInstruction(Inst, *STI);
return false;
3881}

3883bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
                                     MCStreamer &Out,
                                     const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
bool EmittedNoMacroWarning = false;
unsigned PseudoOpcode = Inst.getOpcode();
unsigned SrcReg = Inst.getOperand(0).getReg();
const MCOperand &TrgOp = Inst.getOperand(1);
const MCExpr *OffsetExpr = Inst.getOperand(2).getExpr();

unsigned ZeroSrcOpcode, ZeroTrgOpcode;
bool ReverseOrderSLT, IsUnsigned, IsLikely, AcceptsEquality;

unsigned TrgReg;
1
'TrgReg' declared without an initial value→
if (TrgOp.isReg())
2
←
Taking false branch→
  TrgReg = TrgOp.getReg();
else if (TrgOp.isImm()) {
3
←
Taking false branch→
  warnIfNoMacro(IDLoc);
  EmittedNoMacroWarning = true;

  TrgReg = getATReg(IDLoc);
  if (!TrgReg)
    return true;

  switch(PseudoOpcode) {
  default:
    llvm_unreachable("unknown opcode for branch pseudo-instruction")::llvm::llvm_unreachable_internal("unknown opcode for branch pseudo-instruction"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 3909);
  case Mips::BLTImmMacro:
    PseudoOpcode = Mips::BLT;
    break;
  case Mips::BLEImmMacro:
    PseudoOpcode = Mips::BLE;
    break;
  case Mips::BGEImmMacro:
    PseudoOpcode = Mips::BGE;
    break;
  case Mips::BGTImmMacro:
    PseudoOpcode = Mips::BGT;
    break;
  case Mips::BLTUImmMacro:
    PseudoOpcode = Mips::BLTU;
    break;
  case Mips::BLEUImmMacro:
    PseudoOpcode = Mips::BLEU;
    break;
  case Mips::BGEUImmMacro:
    PseudoOpcode = Mips::BGEU;
    break;
  case Mips::BGTUImmMacro:
    PseudoOpcode = Mips::BGTU;
    break;
  case Mips::BLTLImmMacro:
    PseudoOpcode = Mips::BLTL;
    break;
  case Mips::BLELImmMacro:
    PseudoOpcode = Mips::BLEL;
    break;
  case Mips::BGELImmMacro:
    PseudoOpcode = Mips::BGEL;
    break;
  case Mips::BGTLImmMacro:
    PseudoOpcode = Mips::BGTL;
    break;
  case Mips::BLTULImmMacro:
    PseudoOpcode = Mips::BLTUL;
    break;
  case Mips::BLEULImmMacro:
    PseudoOpcode = Mips::BLEUL;
    break;
  case Mips::BGEULImmMacro:
    PseudoOpcode = Mips::BGEUL;
    break;
  case Mips::BGTULImmMacro:
    PseudoOpcode = Mips::BGTUL;
    break;
  }

  if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(),
                    false, IDLoc, Out, STI))
    return true;
}

switch (PseudoOpcode) {
4
←
Control jumps to 'case BGTL:'  at line 4004→
case Mips::BLT:
case Mips::BLTU:
case Mips::BLTL:
case Mips::BLTUL:
  AcceptsEquality = false;
  ReverseOrderSLT = false;
  IsUnsigned =
      ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL));
  IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL));
  ZeroSrcOpcode = Mips::BGTZ;
  ZeroTrgOpcode = Mips::BLTZ;
  break;
case Mips::BLE:
case Mips::BLEU:
case Mips::BLEL:
case Mips::BLEUL:
  AcceptsEquality = true;
  ReverseOrderSLT = true;
  IsUnsigned =
      ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL));
  IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL));
  ZeroSrcOpcode = Mips::BGEZ;
  ZeroTrgOpcode = Mips::BLEZ;
  break;
case Mips::BGE:
case Mips::BGEU:
case Mips::BGEL:
case Mips::BGEUL:
  AcceptsEquality = true;
  ReverseOrderSLT = false;
  IsUnsigned =
      ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL));
  IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL));
  ZeroSrcOpcode = Mips::BLEZ;
  ZeroTrgOpcode = Mips::BGEZ;
  break;
case Mips::BGT:
case Mips::BGTU:
case Mips::BGTL:
case Mips::BGTUL:
  AcceptsEquality = false;
  ReverseOrderSLT = true;
  IsUnsigned =
      ((PseudoOpcode4.1
'PseudoOpcode' is not equal to BGTU
 == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL));
  IsLikely = ((PseudoOpcode4.2
'PseudoOpcode' is equal to BGTL
 == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL));
  ZeroSrcOpcode = Mips::BLTZ;
  ZeroTrgOpcode = Mips::BGTZ;
  break;
5
←
 Execution continues on line 4018→
default:
  llvm_unreachable("unknown opcode for branch pseudo-instruction")::llvm::llvm_unreachable_internal("unknown opcode for branch pseudo-instruction"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4015);
}

bool IsTrgRegZero = (TrgReg == Mips::ZERO);
6
←
The left operand of '==' is a garbage value
bool IsSrcRegZero = (SrcReg == Mips::ZERO);
if (IsSrcRegZero && IsTrgRegZero) {
  // FIXME: All of these Opcode-specific if's are needed for compatibility
  // with GAS' behaviour. However, they may not generate the most efficient
  // code in some circumstances.
  if (PseudoOpcode == Mips::BLT) {
    TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
                IDLoc, STI);
    return false;
  }
  if (PseudoOpcode == Mips::BLE) {
    TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
                IDLoc, STI);
    Warning(IDLoc, "branch is always taken");
    return false;
  }
  if (PseudoOpcode == Mips::BGE) {
    TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
                IDLoc, STI);
    Warning(IDLoc, "branch is always taken");
    return false;
  }
  if (PseudoOpcode == Mips::BGT) {
    TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
                IDLoc, STI);
    return false;
  }
  if (PseudoOpcode == Mips::BGTU) {
    TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
                 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
    return false;
  }
  if (AcceptsEquality) {
    // If both registers are $0 and the pseudo-branch accepts equality, it
    // will always be taken, so we emit an unconditional branch.
    TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
                 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
    Warning(IDLoc, "branch is always taken");
    return false;
  }
  // If both registers are $0 and the pseudo-branch does not accept
  // equality, it will never be taken, so we don't have to emit anything.
  return false;
}
if (IsSrcRegZero || IsTrgRegZero) {
  if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) ||
      (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) {
    // If the $rs is $0 and the pseudo-branch is BGTU (0 > x) or
    // if the $rt is $0 and the pseudo-branch is BLTU (x < 0),
    // the pseudo-branch will never be taken, so we don't emit anything.
    // This only applies to unsigned pseudo-branches.
    return false;
  }
  if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) ||
      (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) {
    // If the $rs is $0 and the pseudo-branch is BLEU (0 <= x) or
    // if the $rt is $0 and the pseudo-branch is BGEU (x >= 0),
    // the pseudo-branch will always be taken, so we emit an unconditional
    // branch.
    // This only applies to unsigned pseudo-branches.
    TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
                 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
    Warning(IDLoc, "branch is always taken");
    return false;
  }
  if (IsUnsigned) {
    // If the $rs is $0 and the pseudo-branch is BLTU (0 < x) or
    // if the $rt is $0 and the pseudo-branch is BGTU (x > 0),
    // the pseudo-branch will be taken only when the non-zero register is
    // different from 0, so we emit a BNEZ.
    //
    // If the $rs is $0 and the pseudo-branch is BGEU (0 >= x) or
    // if the $rt is $0 and the pseudo-branch is BLEU (x <= 0),
    // the pseudo-branch will be taken only when the non-zero register is
    // equal to 0, so we emit a BEQZ.
    //
    // Because only BLEU and BGEU branch on equality, we can use the
    // AcceptsEquality variable to decide when to emit the BEQZ.
    TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE,
                 IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO,
                 MCOperand::createExpr(OffsetExpr), IDLoc, STI);
    return false;
  }
  // If we have a signed pseudo-branch and one of the registers is $0,
  // we can use an appropriate compare-to-zero branch. We select which one
  // to use in the switch statement above.
  TOut.emitRX(IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode,
              IsSrcRegZero ? TrgReg : SrcReg,
              MCOperand::createExpr(OffsetExpr), IDLoc, STI);
  return false;
}

// If neither the SrcReg nor the TrgReg are $0, we need AT to perform the
// expansions. If it is not available, we return.
unsigned ATRegNum = getATReg(IDLoc);
if (!ATRegNum)
  return true;

if (!EmittedNoMacroWarning)
  warnIfNoMacro(IDLoc);

// SLT fits well with 2 of our 4 pseudo-branches:
//   BLT, where $rs < $rt, translates into "slt $at, $rs, $rt" and
//   BGT, where $rs > $rt, translates into "slt $at, $rt, $rs".
// If the result of the SLT is 1, we branch, and if it's 0, we don't.
// This is accomplished by using a BNEZ with the result of the SLT.
//
// The other 2 pseudo-branches are opposites of the above 2 (BGE with BLT
// and BLE with BGT), so we change the BNEZ into a BEQZ.
// Because only BGE and BLE branch on equality, we can use the
// AcceptsEquality variable to decide when to emit the BEQZ.
// Note that the order of the SLT arguments doesn't change between
// opposites.
//
// The same applies to the unsigned variants, except that SLTu is used
// instead of SLT.
TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum,
             ReverseOrderSLT ? TrgReg : SrcReg,
             ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI);

TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL)
                      : (AcceptsEquality ? Mips::BEQ : Mips::BNE),
             ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
             STI);
return false;
4144}

4146// Expand a integer division macro.
4147//
4148// Notably we don't have to emit a warning when encountering $rt as the $zero
4149// register, or 0 as an immediate. processInstruction() has already done that.
4150//
4151// The destination register can only be $zero when expanding (S)DivIMacro or
4152// D(S)DivMacro.

4154bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                               const MCSubtargetInfo *STI,
                               const bool IsMips64, const bool Signed) {
MipsTargetStreamer &TOut = getTargetStreamer();

warnIfNoMacro(IDLoc);

const MCOperand &RdRegOp = Inst.getOperand(0);
assert(RdRegOp.isReg() && "expected register operand kind")(static_cast <bool> (RdRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("RdRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4162, __extension__
 __PRETTY_FUNCTION__));
unsigned RdReg = RdRegOp.getReg();

const MCOperand &RsRegOp = Inst.getOperand(1);
assert(RsRegOp.isReg() && "expected register operand kind")(static_cast <bool> (RsRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("RsRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4166, __extension__
 __PRETTY_FUNCTION__));
unsigned RsReg = RsRegOp.getReg();

unsigned RtReg;
int64_t ImmValue;

const MCOperand &RtOp = Inst.getOperand(2);
assert((RtOp.isReg() || RtOp.isImm()) &&(static_cast <bool> ((RtOp.isReg() || RtOp.isImm()) &&
 "expected register or immediate operand kind") ? void (0) : __assert_fail
 ("(RtOp.isReg() || RtOp.isImm()) && \"expected register or immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4174, __extension__
 __PRETTY_FUNCTION__))
       "expected register or immediate operand kind")(static_cast <bool> ((RtOp.isReg() || RtOp.isImm()) &&
 "expected register or immediate operand kind") ? void (0) : __assert_fail
 ("(RtOp.isReg() || RtOp.isImm()) && \"expected register or immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4174, __extension__
 __PRETTY_FUNCTION__));
if (RtOp.isReg())
  RtReg = RtOp.getReg();
else
  ImmValue = RtOp.getImm();

unsigned DivOp;
unsigned ZeroReg;
unsigned SubOp;

if (IsMips64) {
  DivOp = Signed ? Mips::DSDIV : Mips::DUDIV;
  ZeroReg = Mips::ZERO_64;
  SubOp = Mips::DSUB;
} else {
  DivOp = Signed ? Mips::SDIV : Mips::UDIV;
  ZeroReg = Mips::ZERO;
  SubOp = Mips::SUB;
}

bool UseTraps = useTraps();

unsigned Opcode = Inst.getOpcode();
bool isDiv = Opcode == Mips::SDivMacro || Opcode == Mips::SDivIMacro ||
             Opcode == Mips::UDivMacro || Opcode == Mips::UDivIMacro ||
             Opcode == Mips::DSDivMacro || Opcode == Mips::DSDivIMacro ||
             Opcode == Mips::DUDivMacro || Opcode == Mips::DUDivIMacro;

bool isRem = Opcode == Mips::SRemMacro || Opcode == Mips::SRemIMacro ||
             Opcode == Mips::URemMacro || Opcode == Mips::URemIMacro ||
             Opcode == Mips::DSRemMacro || Opcode == Mips::DSRemIMacro ||
             Opcode == Mips::DURemMacro || Opcode == Mips::DURemIMacro;

if (RtOp.isImm()) {
  unsigned ATReg = getATReg(IDLoc);
  if (!ATReg)
    return true;

  if (ImmValue == 0) {
    if (UseTraps)
      TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
    else
      TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
    return false;
  }

  if (isRem && (ImmValue == 1 || (Signed && (ImmValue == -1)))) {
    TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI);
    return false;
  } else if (isDiv && ImmValue == 1) {
    TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
    return false;
  } else if (isDiv && Signed && ImmValue == -1) {
    TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI);
    return false;
  } else {
    if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
                      false, Inst.getLoc(), Out, STI))
      return true;
    TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI);
    TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
    return false;
  }
  return true;
}

// If the macro expansion of (d)div(u) or (d)rem(u) would always trap or
// break, insert the trap/break and exit. This gives a different result to
// GAS. GAS has an inconsistency/missed optimization in that not all cases
// are handled equivalently. As the observed behaviour is the same, we're ok.
if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {
  if (UseTraps) {
    TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
    return false;
  }
  TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
  return false;
}

// (d)rem(u) $0, $X, $Y is a special case. Like div $zero, $X, $Y, it does
// not expand to macro sequence.
if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) {
  TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
  return false;
}

// Temporary label for first branch traget
MCContext &Context = TOut.getStreamer().getContext();
MCSymbol *BrTarget;
MCOperand LabelOp;

if (UseTraps) {
  TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
} else {
  // Branch to the li instruction.
  BrTarget = Context.createTempSymbol();
  LabelOp = MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
  TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
}

TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);

if (!UseTraps)
  TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);

if (!Signed) {
  if (!UseTraps)
    TOut.getStreamer().emitLabel(BrTarget);

  TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
  return false;
}

unsigned ATReg = getATReg(IDLoc);
if (!ATReg)
  return true;

if (!UseTraps)
  TOut.getStreamer().emitLabel(BrTarget);

TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);

// Temporary label for the second branch target.
MCSymbol *BrTargetEnd = Context.createTempSymbol();
MCOperand LabelOpEnd =
    MCOperand::createExpr(MCSymbolRefExpr::create(BrTargetEnd, Context));

// Branch to the mflo instruction.
TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI);

if (IsMips64) {
  TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
  TOut.emitDSLL(ATReg, ATReg, 63, IDLoc, STI);
} else {
  TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
}

if (UseTraps)
  TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
else {
  // Branch to the mflo instruction.
  TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI);
  TOut.emitNop(IDLoc, STI);
  TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
}

TOut.getStreamer().emitLabel(BrTargetEnd);
TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
return false;
4323}

4325bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU,
                              SMLoc IDLoc, MCStreamer &Out,
                              const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4330, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4332, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isReg() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4332, __extension__
 __PRETTY_FUNCTION__));

unsigned FirstReg = Inst.getOperand(0).getReg();
unsigned SecondReg = Inst.getOperand(1).getReg();
unsigned ThirdReg = Inst.getOperand(2).getReg();

if (hasMips1() && !hasMips2()) {
  unsigned ATReg = getATReg(IDLoc);
  if (!ATReg)
    return true;
  TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
  TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
  TOut.emitNop(IDLoc, STI);
  TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI);
  TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI);
  TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI);
  TOut.emitNop(IDLoc, STI);
  TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)
                       : Mips::CVT_W_S,
              FirstReg, SecondReg, IDLoc, STI);
  TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI);
  TOut.emitNop(IDLoc, STI);
  return false;
}

TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)
                     : Mips::TRUNC_W_S,
            FirstReg, SecondReg, IDLoc, STI);

return false;
4362}

4364bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
                            MCStreamer &Out, const MCSubtargetInfo *STI) {
if (hasMips32r6() || hasMips64r6()) {
  return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
}

const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind")(static_cast <bool> (DstRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("DstRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4371, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &SrcRegOp = Inst.getOperand(1);
assert(SrcRegOp.isReg() && "expected register operand kind")(static_cast <bool> (SrcRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("SrcRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4373, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &OffsetImmOp = Inst.getOperand(2);
assert(OffsetImmOp.isImm() && "expected immediate operand kind")(static_cast <bool> (OffsetImmOp.isImm() && "expected immediate operand kind"
) ? void (0) : __assert_fail ("OffsetImmOp.isImm() && \"expected immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4375, __extension__
 __PRETTY_FUNCTION__));

MipsTargetStreamer &TOut = getTargetStreamer();
unsigned DstReg = DstRegOp.getReg();
unsigned SrcReg = SrcRegOp.getReg();
int64_t OffsetValue = OffsetImmOp.getImm();

// NOTE: We always need AT for ULHU, as it is always used as the source
// register for one of the LBu's.
warnIfNoMacro(IDLoc);
unsigned ATReg = getATReg(IDLoc);
if (!ATReg)
  return true;

bool IsLargeOffset = !(isInt<16>(OffsetValue + 1) && isInt<16>(OffsetValue));
if (IsLargeOffset) {
  if (loadImmediate(OffsetValue, ATReg, SrcReg, !ABI.ArePtrs64bit(), true,
                    IDLoc, Out, STI))
    return true;
}

int64_t FirstOffset = IsLargeOffset ? 0 : OffsetValue;
int64_t SecondOffset = IsLargeOffset ? 1 : (OffsetValue + 1);
if (isLittle())
  std::swap(FirstOffset, SecondOffset);

unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg;
unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg;

unsigned LbuSrcReg = IsLargeOffset ? ATReg : SrcReg;
unsigned SllReg = IsLargeOffset ? DstReg : ATReg;

TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg,
             FirstOffset, IDLoc, STI);
TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI);
TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI);
TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);

return false;
4414}

4416bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                            const MCSubtargetInfo *STI) {
if (hasMips32r6() || hasMips64r6()) {
  return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
}

const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind")(static_cast <bool> (DstRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("DstRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4423, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &SrcRegOp = Inst.getOperand(1);
assert(SrcRegOp.isReg() && "expected register operand kind")(static_cast <bool> (SrcRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("SrcRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4425, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &OffsetImmOp = Inst.getOperand(2);
assert(OffsetImmOp.isImm() && "expected immediate operand kind")(static_cast <bool> (OffsetImmOp.isImm() && "expected immediate operand kind"
) ? void (0) : __assert_fail ("OffsetImmOp.isImm() && \"expected immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4427, __extension__
 __PRETTY_FUNCTION__));

MipsTargetStreamer &TOut = getTargetStreamer();
unsigned DstReg = DstRegOp.getReg();
unsigned SrcReg = SrcRegOp.getReg();
int64_t OffsetValue = OffsetImmOp.getImm();

warnIfNoMacro(IDLoc);
unsigned ATReg = getATReg(IDLoc);
if (!ATReg)
  return true;

bool IsLargeOffset = !(isInt<16>(OffsetValue + 1) && isInt<16>(OffsetValue));
if (IsLargeOffset) {
  if (loadImmediate(OffsetValue, ATReg, SrcReg, !ABI.ArePtrs64bit(), true,
                    IDLoc, Out, STI))
    return true;
}

int64_t FirstOffset = IsLargeOffset ? 1 : (OffsetValue + 1);
int64_t SecondOffset = IsLargeOffset ? 0 : OffsetValue;
if (isLittle())
  std::swap(FirstOffset, SecondOffset);

if (IsLargeOffset) {
  TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI);
  TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI);
  TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI);
  TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI);
  TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI);
  TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
} else {
  TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI);
  TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI);
  TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI);
}

return false;
4465}

4467bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                            const MCSubtargetInfo *STI) {
if (hasMips32r6() || hasMips64r6()) {
  return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
}

const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind")(static_cast <bool> (DstRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("DstRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4474, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &SrcRegOp = Inst.getOperand(1);
assert(SrcRegOp.isReg() && "expected register operand kind")(static_cast <bool> (SrcRegOp.isReg() && "expected register operand kind"
) ? void (0) : __assert_fail ("SrcRegOp.isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4476, __extension__
 __PRETTY_FUNCTION__));
const MCOperand &OffsetImmOp = Inst.getOperand(2);
assert(OffsetImmOp.isImm() && "expected immediate operand kind")(static_cast <bool> (OffsetImmOp.isImm() && "expected immediate operand kind"
) ? void (0) : __assert_fail ("OffsetImmOp.isImm() && \"expected immediate operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4478, __extension__
 __PRETTY_FUNCTION__));

MipsTargetStreamer &TOut = getTargetStreamer();
unsigned DstReg = DstRegOp.getReg();
unsigned SrcReg = SrcRegOp.getReg();
int64_t OffsetValue = OffsetImmOp.getImm();

// Compute left/right load/store offsets.
bool IsLargeOffset = !(isInt<16>(OffsetValue + 3) && isInt<16>(OffsetValue));
int64_t LxlOffset = IsLargeOffset ? 0 : OffsetValue;
int64_t LxrOffset = IsLargeOffset ? 3 : (OffsetValue + 3);
if (isLittle())
  std::swap(LxlOffset, LxrOffset);

bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw);
bool DoMove = IsLoadInst && (SrcReg == DstReg) && !IsLargeOffset;
unsigned TmpReg = SrcReg;
if (IsLargeOffset || DoMove) {
  warnIfNoMacro(IDLoc);
  TmpReg = getATReg(IDLoc);
  if (!TmpReg)
    return true;
}

if (IsLargeOffset) {
  if (loadImmediate(OffsetValue, TmpReg, SrcReg, !ABI.ArePtrs64bit(), true,
                    IDLoc, Out, STI))
    return true;
}

if (DoMove)
  std::swap(DstReg, TmpReg);

unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL;
unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR;
TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI);
TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI);

if (DoMove)
  TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);

return false;
4520}

4522bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                            const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4526, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4529, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4529, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isReg() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4529, __extension__
 __PRETTY_FUNCTION__));

unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
unsigned OpReg = Inst.getOperand(2).getReg();
unsigned OpCode;

warnIfNoMacro(IDLoc);

switch (Inst.getOpcode()) {
case Mips::SGE:
  OpCode = Mips::SLT;
  break;
case Mips::SGEU:
  OpCode = Mips::SLTu;
  break;
default:
  llvm_unreachable("unexpected 'sge' opcode")::llvm::llvm_unreachable_internal("unexpected 'sge' opcode", "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp"
, 4546);
}

// $SrcReg >= $OpReg is equal to (not ($SrcReg < $OpReg))
TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI);
TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);

return false;
4554}

4556bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                               const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4560, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4563, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4563, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isImm() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4563, __extension__
 __PRETTY_FUNCTION__));

unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm();
unsigned OpRegCode, OpImmCode;

warnIfNoMacro(IDLoc);

switch (Inst.getOpcode()) {
case Mips::SGEImm:
case Mips::SGEImm64:
  OpRegCode = Mips::SLT;
  OpImmCode = Mips::SLTi;
  break;
case Mips::SGEUImm:
case Mips::SGEUImm64:
  OpRegCode = Mips::SLTu;
  OpImmCode = Mips::SLTiu;
  break;
default:
  llvm_unreachable("unexpected 'sge' opcode with immediate")::llvm::llvm_unreachable_internal("unexpected 'sge' opcode with immediate"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4584);
}

// $SrcReg >= Imm is equal to (not ($SrcReg < Imm))
if (isInt<16>(ImmValue)) {
  // Use immediate version of STL.
  TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI);
  TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
} else {
  unsigned ImmReg = DstReg;
  if (DstReg == SrcReg) {
    unsigned ATReg = getATReg(Inst.getLoc());
    if (!ATReg)
      return true;
    ImmReg = ATReg;
  }

  if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
                    false, IDLoc, Out, STI))
    return true;

  TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI);
  TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
}

return false;
4610}

4612bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                               const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4616, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4619, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4619, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isImm() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4619, __extension__
 __PRETTY_FUNCTION__));

unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
unsigned ImmReg = DstReg;
int64_t ImmValue = Inst.getOperand(2).getImm();
unsigned OpCode;

warnIfNoMacro(IDLoc);

switch (Inst.getOpcode()) {
case Mips::SGTImm:
case Mips::SGTImm64:
  OpCode = Mips::SLT;
  break;
case Mips::SGTUImm:
case Mips::SGTUImm64:
  OpCode = Mips::SLTu;
  break;
default:
  llvm_unreachable("unexpected 'sgt' opcode with immediate")::llvm::llvm_unreachable_internal("unexpected 'sgt' opcode with immediate"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4639);
}

if (DstReg == SrcReg) {
  unsigned ATReg = getATReg(Inst.getLoc());
  if (!ATReg)
    return true;
  ImmReg = ATReg;
}

if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
                  false, IDLoc, Out, STI))
  return true;

// $SrcReg > $ImmReg is equal to $ImmReg < $SrcReg
TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI);

return false;
4657}

4659bool MipsAsmParser::expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                            const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4663, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4666, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4666, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isReg() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4666, __extension__
 __PRETTY_FUNCTION__));

unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
unsigned OpReg = Inst.getOperand(2).getReg();
unsigned OpCode;

warnIfNoMacro(IDLoc);

switch (Inst.getOpcode()) {
case Mips::SLE:
  OpCode = Mips::SLT;
  break;
case Mips::SLEU:
  OpCode = Mips::SLTu;
  break;
default:
  llvm_unreachable("unexpected 'sge' opcode")::llvm::llvm_unreachable_internal("unexpected 'sge' opcode", "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp"
, 4683);
}

// $SrcReg <= $OpReg is equal to (not ($OpReg < $SrcReg))
TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI);
TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);

return false;
4691}

4693bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                               const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4697, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4700, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4700, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isImm() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4700, __extension__
 __PRETTY_FUNCTION__));

unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm();
unsigned OpRegCode;

warnIfNoMacro(IDLoc);

switch (Inst.getOpcode()) {
case Mips::SLEImm:
case Mips::SLEImm64:
  OpRegCode = Mips::SLT;
  break;
case Mips::SLEUImm:
case Mips::SLEUImm64:
  OpRegCode = Mips::SLTu;
  break;
default:
  llvm_unreachable("unexpected 'sge' opcode with immediate")::llvm::llvm_unreachable_internal("unexpected 'sge' opcode with immediate"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4719);
}

// $SrcReg <= Imm is equal to (not (Imm < $SrcReg))
unsigned ImmReg = DstReg;
if (DstReg == SrcReg) {
  unsigned ATReg = getATReg(Inst.getLoc());
  if (!ATReg)
    return true;
  ImmReg = ATReg;
}

if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
                  false, IDLoc, Out, STI))
  return true;

TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI);
TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);

return false;
4739}

4741bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
                                       MCStreamer &Out,
                                       const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4746, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4749, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4749, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isImm() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4749, __extension__
 __PRETTY_FUNCTION__));

unsigned ATReg = Mips::NoRegister;
unsigned FinalDstReg = Mips::NoRegister;
unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm();

bool Is32Bit = isInt<32>(ImmValue) || (!isGP64bit() && isUInt<32>(ImmValue));

unsigned FinalOpcode = Inst.getOpcode();

if (DstReg == SrcReg) {
  ATReg = getATReg(Inst.getLoc());
  if (!ATReg)
    return true;
  FinalDstReg = DstReg;
  DstReg = ATReg;
}

if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false,
                   Inst.getLoc(), Out, STI)) {
  switch (FinalOpcode) {
  default:
    llvm_unreachable("unimplemented expansion")::llvm::llvm_unreachable_internal("unimplemented expansion", "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp"
, 4773);
  case Mips::ADDi:
    FinalOpcode = Mips::ADD;
    break;
  case Mips::ADDiu:
    FinalOpcode = Mips::ADDu;
    break;
  case Mips::ANDi:
    FinalOpcode = Mips::AND;
    break;
  case Mips::NORImm:
    FinalOpcode = Mips::NOR;
    break;
  case Mips::ORi:
    FinalOpcode = Mips::OR;
    break;
  case Mips::SLTi:
    FinalOpcode = Mips::SLT;
    break;
  case Mips::SLTiu:
    FinalOpcode = Mips::SLTu;
    break;
  case Mips::XORi:
    FinalOpcode = Mips::XOR;
    break;
  case Mips::ADDi_MM:
    FinalOpcode = Mips::ADD_MM;
    break;
  case Mips::ADDiu_MM:
    FinalOpcode = Mips::ADDu_MM;
    break;
  case Mips::ANDi_MM:
    FinalOpcode = Mips::AND_MM;
    break;
  case Mips::ORi_MM:
    FinalOpcode = Mips::OR_MM;
    break;
  case Mips::SLTi_MM:
    FinalOpcode = Mips::SLT_MM;
    break;
  case Mips::SLTiu_MM:
    FinalOpcode = Mips::SLTu_MM;
    break;
  case Mips::XORi_MM:
    FinalOpcode = Mips::XOR_MM;
    break;
  case Mips::ANDi64:
    FinalOpcode = Mips::AND64;
    break;
  case Mips::NORImm64:
    FinalOpcode = Mips::NOR64;
    break;
  case Mips::ORi64:
    FinalOpcode = Mips::OR64;
    break;
  case Mips::SLTImm64:
    FinalOpcode = Mips::SLT64;
    break;
  case Mips::SLTUImm64:
    FinalOpcode = Mips::SLTu64;
    break;
  case Mips::XORi64:
    FinalOpcode = Mips::XOR64;
    break;
  }

  if (FinalDstReg == Mips::NoRegister)
    TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI);
  else
    TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI);
  return false;
}
return true;
4846}

4848bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                 const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned ATReg = Mips::NoRegister;
unsigned DReg = Inst.getOperand(0).getReg();
unsigned SReg = Inst.getOperand(1).getReg();
unsigned TReg = Inst.getOperand(2).getReg();
unsigned TmpReg = DReg;

unsigned FirstShift = Mips::NOP;
unsigned SecondShift = Mips::NOP;

if (hasMips32r2()) {
  if (DReg == SReg) {
    TmpReg = getATReg(Inst.getLoc());
    if (!TmpReg)
      return true;
  }

  if (Inst.getOpcode() == Mips::ROL) {
    TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
    TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
    return false;
  }

  if (Inst.getOpcode() == Mips::ROR) {
    TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
    return false;
  }

  return true;
}

if (hasMips32()) {
  switch (Inst.getOpcode()) {
  default:
    llvm_unreachable("unexpected instruction opcode")::llvm::llvm_unreachable_internal("unexpected instruction opcode"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4884);
  case Mips::ROL:
    FirstShift = Mips::SRLV;
    SecondShift = Mips::SLLV;
    break;
  case Mips::ROR:
    FirstShift = Mips::SLLV;
    SecondShift = Mips::SRLV;
    break;
  }

  ATReg = getATReg(Inst.getLoc());
  if (!ATReg)
    return true;

  TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
  TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
  TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);

  return false;
}

return true;
4908}

4910bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc,
                                    MCStreamer &Out,
                                    const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned ATReg = Mips::NoRegister;
unsigned DReg = Inst.getOperand(0).getReg();
unsigned SReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm();

unsigned FirstShift = Mips::NOP;
unsigned SecondShift = Mips::NOP;

if (hasMips32r2()) {
  if (Inst.getOpcode() == Mips::ROLImm) {
    uint64_t MaxShift = 32;
    uint64_t ShiftValue = ImmValue;
    if (ImmValue != 0)
      ShiftValue = MaxShift - ImmValue;
    TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
    return false;
  }

  if (Inst.getOpcode() == Mips::RORImm) {
    TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI);
    return false;
  }

  return true;
}

if (hasMips32()) {
  if (ImmValue == 0) {
    TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI);
    return false;
  }

  switch (Inst.getOpcode()) {
  default:
    llvm_unreachable("unexpected instruction opcode")::llvm::llvm_unreachable_internal("unexpected instruction opcode"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 4948);
  case Mips::ROLImm:
    FirstShift = Mips::SLL;
    SecondShift = Mips::SRL;
    break;
  case Mips::RORImm:
    FirstShift = Mips::SRL;
    SecondShift = Mips::SLL;
    break;
  }

  ATReg = getATReg(Inst.getLoc());
  if (!ATReg)
    return true;

  TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue, Inst.getLoc(), STI);
  TOut.emitRRI(SecondShift, DReg, SReg, 32 - ImmValue, Inst.getLoc(), STI);
  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);

  return false;
}

return true;
4971}

4973bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                  const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned ATReg = Mips::NoRegister;
unsigned DReg = Inst.getOperand(0).getReg();
unsigned SReg = Inst.getOperand(1).getReg();
unsigned TReg = Inst.getOperand(2).getReg();
unsigned TmpReg = DReg;

unsigned FirstShift = Mips::NOP;
unsigned SecondShift = Mips::NOP;

if (hasMips64r2()) {
  if (TmpReg == SReg) {
    TmpReg = getATReg(Inst.getLoc());
    if (!TmpReg)
      return true;
  }

  if (Inst.getOpcode() == Mips::DROL) {
    TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
    TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
    return false;
  }

  if (Inst.getOpcode() == Mips::DROR) {
    TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
    return false;
  }

  return true;
}

if (hasMips64()) {
  switch (Inst.getOpcode()) {
  default:
    llvm_unreachable("unexpected instruction opcode")::llvm::llvm_unreachable_internal("unexpected instruction opcode"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5009);
  case Mips::DROL:
    FirstShift = Mips::DSRLV;
    SecondShift = Mips::DSLLV;
    break;
  case Mips::DROR:
    FirstShift = Mips::DSLLV;
    SecondShift = Mips::DSRLV;
    break;
  }

  ATReg = getATReg(Inst.getLoc());
  if (!ATReg)
    return true;

  TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
  TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
  TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);

  return false;
}

return true;
5033}

5035bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc,
                                     MCStreamer &Out,
                                     const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned ATReg = Mips::NoRegister;
unsigned DReg = Inst.getOperand(0).getReg();
unsigned SReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm() % 64;

unsigned FirstShift = Mips::NOP;
unsigned SecondShift = Mips::NOP;

MCInst TmpInst;

if (hasMips64r2()) {
  unsigned FinalOpcode = Mips::NOP;
  if (ImmValue == 0)
    FinalOpcode = Mips::DROTR;
  else if (ImmValue % 32 == 0)
    FinalOpcode = Mips::DROTR32;
  else if ((ImmValue >= 1) && (ImmValue <= 32)) {
    if (Inst.getOpcode() == Mips::DROLImm)
      FinalOpcode = Mips::DROTR32;
    else
      FinalOpcode = Mips::DROTR;
  } else if (ImmValue >= 33) {
    if (Inst.getOpcode() == Mips::DROLImm)
      FinalOpcode = Mips::DROTR;
    else
      FinalOpcode = Mips::DROTR32;
  }

  uint64_t ShiftValue = ImmValue % 32;
  if (Inst.getOpcode() == Mips::DROLImm)
    ShiftValue = (32 - ImmValue % 32) % 32;

  TOut.emitRRI(FinalOpcode, DReg, SReg, ShiftValue, Inst.getLoc(), STI);

  return false;
}

if (hasMips64()) {
  if (ImmValue == 0) {
    TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI);
    return false;
  }

  switch (Inst.getOpcode()) {
  default:
    llvm_unreachable("unexpected instruction opcode")::llvm::llvm_unreachable_internal("unexpected instruction opcode"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5084);
  case Mips::DROLImm:
    if ((ImmValue >= 1) && (ImmValue <= 31)) {
      FirstShift = Mips::DSLL;
      SecondShift = Mips::DSRL32;
    }
    if (ImmValue == 32) {
      FirstShift = Mips::DSLL32;
      SecondShift = Mips::DSRL32;
    }
    if ((ImmValue >= 33) && (ImmValue <= 63)) {
      FirstShift = Mips::DSLL32;
      SecondShift = Mips::DSRL;
    }
    break;
  case Mips::DRORImm:
    if ((ImmValue >= 1) && (ImmValue <= 31)) {
      FirstShift = Mips::DSRL;
      SecondShift = Mips::DSLL32;
    }
    if (ImmValue == 32) {
      FirstShift = Mips::DSRL32;
      SecondShift = Mips::DSLL32;
    }
    if ((ImmValue >= 33) && (ImmValue <= 63)) {
      FirstShift = Mips::DSRL32;
      SecondShift = Mips::DSLL;
    }
    break;
  }

  ATReg = getATReg(Inst.getLoc());
  if (!ATReg)
    return true;

  TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue % 32, Inst.getLoc(), STI);
  TOut.emitRRI(SecondShift, DReg, SReg, (32 - ImmValue % 32) % 32,
               Inst.getLoc(), STI);
  TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);

  return false;
}

return true;
5128}

5130bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                            const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned FirstRegOp = Inst.getOperand(0).getReg();
unsigned SecondRegOp = Inst.getOperand(1).getReg();

TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI);
if (FirstRegOp != SecondRegOp)
  TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);
else
  TOut.emitEmptyDelaySlot(false, IDLoc, STI);
TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);

return false;
5144}

5146bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                               const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned ATReg = Mips::NoRegister;
unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
int32_t ImmValue = Inst.getOperand(2).getImm();

ATReg = getATReg(IDLoc);
if (!ATReg)
  return true;

loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out,
              STI);

TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT,
            SrcReg, ATReg, IDLoc, STI);

TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);

return false;
5167}

5169bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                             const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned ATReg = Mips::NoRegister;
unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
unsigned TmpReg = Inst.getOperand(2).getReg();

ATReg = getATReg(Inst.getLoc());
if (!ATReg)
  return true;

TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT,
            SrcReg, TmpReg, IDLoc, STI);

TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);

TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32,
             DstReg, DstReg, 0x1F, IDLoc, STI);

TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);

if (useTraps()) {
  TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI);
} else {
  MCContext & Context = TOut.getStreamer().getContext();
  MCSymbol * BrTarget = Context.createTempSymbol();
  MCOperand LabelOp =
      MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));

  TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI);
  if (AssemblerOptions.back()->isReorder())
    TOut.emitNop(IDLoc, STI);
  TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);

  TOut.getStreamer().emitLabel(BrTarget);
}
TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);

return false;
5209}

5211bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                              const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned ATReg = Mips::NoRegister;
unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
unsigned TmpReg = Inst.getOperand(2).getReg();

ATReg = getATReg(IDLoc);
if (!ATReg)
  return true;

TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu,
            SrcReg, TmpReg, IDLoc, STI);

TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
if (useTraps()) {
  TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI);
} else {
  MCContext & Context = TOut.getStreamer().getContext();
  MCSymbol * BrTarget = Context.createTempSymbol();
  MCOperand LabelOp =
      MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));

  TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI);
  if (AssemblerOptions.back()->isReorder())
    TOut.emitNop(IDLoc, STI);
  TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);

  TOut.getStreamer().emitLabel(BrTarget);
}

return false;
5245}

5247bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                  const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
unsigned TmpReg = Inst.getOperand(2).getReg();

TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI);
TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);

return false;
5258}

5260// Expand 'ld $<reg> offset($reg2)' to 'lw $<reg>, offset($reg2);
5261//                                      lw $<reg+1>>, offset+4($reg2)'
5262// or expand 'sd $<reg> offset($reg2)' to 'sw $<reg>, offset($reg2);
5263//                                         sw $<reg+1>>, offset+4($reg2)'
5264// for O32.
5265bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc,
                                        MCStreamer &Out,
                                        const MCSubtargetInfo *STI,
                                        bool IsLoad) {
if (!isABI_O32())
  return true;

warnIfNoMacro(IDLoc);

MipsTargetStreamer &TOut = getTargetStreamer();
unsigned Opcode = IsLoad ? Mips::LW : Mips::SW;
unsigned FirstReg = Inst.getOperand(0).getReg();
unsigned SecondReg = nextReg(FirstReg);
unsigned BaseReg = Inst.getOperand(1).getReg();
if (!SecondReg)
  return true;

warnIfRegIndexIsAT(FirstReg, IDLoc);

assert(Inst.getOperand(2).isImm() &&(static_cast <bool> (Inst.getOperand(2).isImm() &&
 "Offset for load macro is not immediate!") ? void (0) : __assert_fail
 ("Inst.getOperand(2).isImm() && \"Offset for load macro is not immediate!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5285, __extension__
 __PRETTY_FUNCTION__))
       "Offset for load macro is not immediate!")(static_cast <bool> (Inst.getOperand(2).isImm() &&
 "Offset for load macro is not immediate!") ? void (0) : __assert_fail
 ("Inst.getOperand(2).isImm() && \"Offset for load macro is not immediate!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5285, __extension__
 __PRETTY_FUNCTION__));

MCOperand &FirstOffset = Inst.getOperand(2);
signed NextOffset = FirstOffset.getImm() + 4;
MCOperand SecondOffset = MCOperand::createImm(NextOffset);

if (!isInt<16>(FirstOffset.getImm()) || !isInt<16>(NextOffset))
  return true;

// For loads, clobber the base register with the second load instead of the
// first if the BaseReg == FirstReg.
if (FirstReg != BaseReg || !IsLoad) {
  TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
  TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
} else {
  TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);
  TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
}

return false;
5305}


5308// Expand 's.d $<reg> offset($reg2)' to 'swc1 $<reg+1>, offset($reg2);
5309//                                       swc1 $<reg>, offset+4($reg2)'
5310// or if little endian to 'swc1 $<reg>, offset($reg2);
5311//                         swc1 $<reg+1>, offset+4($reg2)'
5312// for Mips1.
5313bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc,
                                      MCStreamer &Out,
                                      const MCSubtargetInfo *STI) {
if (!isABI_O32())
  return true;

warnIfNoMacro(IDLoc);

MipsTargetStreamer &TOut = getTargetStreamer();
unsigned Opcode = Mips::SWC1;
unsigned FirstReg = Inst.getOperand(0).getReg();
unsigned SecondReg = nextReg(FirstReg);
unsigned BaseReg = Inst.getOperand(1).getReg();
if (!SecondReg)
  return true;

warnIfRegIndexIsAT(FirstReg, IDLoc);

assert(Inst.getOperand(2).isImm() &&(static_cast <bool> (Inst.getOperand(2).isImm() &&
 "Offset for macro is not immediate!") ? void (0) : __assert_fail
 ("Inst.getOperand(2).isImm() && \"Offset for macro is not immediate!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5332, __extension__
 __PRETTY_FUNCTION__))
       "Offset for macro is not immediate!")(static_cast <bool> (Inst.getOperand(2).isImm() &&
 "Offset for macro is not immediate!") ? void (0) : __assert_fail
 ("Inst.getOperand(2).isImm() && \"Offset for macro is not immediate!\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5332, __extension__
 __PRETTY_FUNCTION__));

MCOperand &FirstOffset = Inst.getOperand(2);
signed NextOffset = FirstOffset.getImm() + 4;
MCOperand SecondOffset = MCOperand::createImm(NextOffset);

if (!isInt<16>(FirstOffset.getImm()) || !isInt<16>(NextOffset))
  return true;

if (!IsLittleEndian)
  std::swap(FirstReg, SecondReg);

TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);
TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI);

return false;
5348}

5350bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                            const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5354, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5357, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5357, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isReg() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5357, __extension__
 __PRETTY_FUNCTION__));

unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
unsigned OpReg = Inst.getOperand(2).getReg();

warnIfNoMacro(IDLoc);

if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
  TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
  TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
  return false;
}

unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI);
return false;
5374}

5376bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                             const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5380, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5383, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5383, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isImm() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5383, __extension__
 __PRETTY_FUNCTION__));

unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
int64_t Imm = Inst.getOperand(2).getImm();

warnIfNoMacro(IDLoc);

if (Imm == 0) {
  TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI);
  return false;
}

if (SrcReg == Mips::ZERO) {
  Warning(IDLoc, "comparison is always false");
  TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu,
               DstReg, SrcReg, SrcReg, IDLoc, STI);
  return false;
}

unsigned Opc;
if (Imm > -0x8000 && Imm < 0) {
  Imm = -Imm;
  Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
} else {
  Opc = Mips::XORi;
}

if (!isUInt<16>(Imm)) {
  unsigned ATReg = getATReg(IDLoc);
  if (!ATReg)
    return true;

  if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc,
                    Out, STI))
    return true;

  TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
  TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
  return false;
}

TOut.emitRRI(Opc, DstReg, SrcReg, Imm, IDLoc, STI);
TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
return false;
5428}

5430bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                            const MCSubtargetInfo *STI) {

MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5435, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5438, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5438, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isReg() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isReg() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5438, __extension__
 __PRETTY_FUNCTION__));

unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
unsigned OpReg = Inst.getOperand(2).getReg();

warnIfNoMacro(IDLoc);

if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
  TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
  TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
  return false;
}

unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI);
return false;
5455}

5457bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                             const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();

assert(Inst.getNumOperands() == 3 && "Invalid operand count")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "Invalid operand count") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"Invalid operand count\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5461, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5464, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(1).isReg() &&(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5464, __extension__
 __PRETTY_FUNCTION__))
       Inst.getOperand(2).isImm() && "Invalid instruction operand.")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm
() && "Invalid instruction operand.") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm() && \"Invalid instruction operand.\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5464, __extension__
 __PRETTY_FUNCTION__));

unsigned DstReg = Inst.getOperand(0).getReg();
unsigned SrcReg = Inst.getOperand(1).getReg();
int64_t ImmValue = Inst.getOperand(2).getImm();

warnIfNoMacro(IDLoc);

if (ImmValue == 0) {
  TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI);
  return false;
}

if (SrcReg == Mips::ZERO) {
  Warning(IDLoc, "comparison is always true");
  if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out,
                    STI))
    return true;
  return false;
}

unsigned Opc;
if (ImmValue > -0x8000 && ImmValue < 0) {
  ImmValue = -ImmValue;
  Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
} else {
  Opc = Mips::XORi;
}

if (isUInt<16>(ImmValue)) {
  TOut.emitRRI(Opc, DstReg, SrcReg, ImmValue, IDLoc, STI);
  TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
  return false;
}

unsigned ATReg = getATReg(IDLoc);
if (!ATReg)
  return true;

if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
                  false, IDLoc, Out, STI))
  return true;

TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
return false;
5510}

5512// Map the DSP accumulator and control register to the corresponding gpr
5513// operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions
5514// do not map the DSP registers contigously to gpr registers.
5515static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
switch (Inst.getOpcode()) {
  case Mips::MFTLO:
  case Mips::MTTLO:
    switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
      case Mips::AC0:
        return Mips::ZERO;
      case Mips::AC1:
        return Mips::A0;
      case Mips::AC2:
        return Mips::T0;
      case Mips::AC3:
        return Mips::T4;
      default:
        llvm_unreachable("Unknown register for 'mttr' alias!")::llvm::llvm_unreachable_internal("Unknown register for 'mttr' alias!"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5529);
  }
  case Mips::MFTHI:
  case Mips::MTTHI:
    switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
      case Mips::AC0:
        return Mips::AT;
      case Mips::AC1:
        return Mips::A1;
      case Mips::AC2:
        return Mips::T1;
      case Mips::AC3:
        return Mips::T5;
      default:
        llvm_unreachable("Unknown register for 'mttr' alias!")::llvm::llvm_unreachable_internal("Unknown register for 'mttr' alias!"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5543);
  }
  case Mips::MFTACX:
  case Mips::MTTACX:
    switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
      case Mips::AC0:
        return Mips::V0;
      case Mips::AC1:
        return Mips::A2;
      case Mips::AC2:
        return Mips::T2;
      case Mips::AC3:
        return Mips::T6;
      default:
        llvm_unreachable("Unknown register for 'mttr' alias!")::llvm::llvm_unreachable_internal("Unknown register for 'mttr' alias!"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5557);
  }
  case Mips::MFTDSP:
  case Mips::MTTDSP:
    return Mips::S0;
  default:
    llvm_unreachable("Unknown instruction for 'mttr' dsp alias!")::llvm::llvm_unreachable_internal("Unknown instruction for 'mttr' dsp alias!"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5563);
}
5565}

5567// Map the floating point register operand to the corresponding register
5568// operand.
5569static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) {
  case Mips::F0:  return Mips::ZERO;
  case Mips::F1:  return Mips::AT;
  case Mips::F2:  return Mips::V0;
  case Mips::F3:  return Mips::V1;
  case Mips::F4:  return Mips::A0;
  case Mips::F5:  return Mips::A1;
  case Mips::F6:  return Mips::A2;
  case Mips::F7:  return Mips::A3;
  case Mips::F8:  return Mips::T0;
  case Mips::F9:  return Mips::T1;
  case Mips::F10: return Mips::T2;
  case Mips::F11: return Mips::T3;
  case Mips::F12: return Mips::T4;
  case Mips::F13: return Mips::T5;
  case Mips::F14: return Mips::T6;
  case Mips::F15: return Mips::T7;
  case Mips::F16: return Mips::S0;
  case Mips::F17: return Mips::S1;
  case Mips::F18: return Mips::S2;
  case Mips::F19: return Mips::S3;
  case Mips::F20: return Mips::S4;
  case Mips::F21: return Mips::S5;
  case Mips::F22: return Mips::S6;
  case Mips::F23: return Mips::S7;
  case Mips::F24: return Mips::T8;
  case Mips::F25: return Mips::T9;
  case Mips::F26: return Mips::K0;
  case Mips::F27: return Mips::K1;
  case Mips::F28: return Mips::GP;
  case Mips::F29: return Mips::SP;
  case Mips::F30: return Mips::FP;
  case Mips::F31: return Mips::RA;
  default: llvm_unreachable("Unknown register for mttc1 alias!")::llvm::llvm_unreachable_internal("Unknown register for mttc1 alias!"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5603);
}
5605}

5607// Map the coprocessor operand the corresponding gpr register operand.
5608static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) {
  case Mips::COP00:  return Mips::ZERO;
  case Mips::COP01:  return Mips::AT;
  case Mips::COP02:  return Mips::V0;
  case Mips::COP03:  return Mips::V1;
  case Mips::COP04:  return Mips::A0;
  case Mips::COP05:  return Mips::A1;
  case Mips::COP06:  return Mips::A2;
  case Mips::COP07:  return Mips::A3;
  case Mips::COP08:  return Mips::T0;
  case Mips::COP09:  return Mips::T1;
  case Mips::COP010: return Mips::T2;
  case Mips::COP011: return Mips::T3;
  case Mips::COP012: return Mips::T4;
  case Mips::COP013: return Mips::T5;
  case Mips::COP014: return Mips::T6;
  case Mips::COP015: return Mips::T7;
  case Mips::COP016: return Mips::S0;
  case Mips::COP017: return Mips::S1;
  case Mips::COP018: return Mips::S2;
  case Mips::COP019: return Mips::S3;
  case Mips::COP020: return Mips::S4;
  case Mips::COP021: return Mips::S5;
  case Mips::COP022: return Mips::S6;
  case Mips::COP023: return Mips::S7;
  case Mips::COP024: return Mips::T8;
  case Mips::COP025: return Mips::T9;
  case Mips::COP026: return Mips::K0;
  case Mips::COP027: return Mips::K1;
  case Mips::COP028: return Mips::GP;
  case Mips::COP029: return Mips::SP;
  case Mips::COP030: return Mips::FP;
  case Mips::COP031: return Mips::RA;
  default: llvm_unreachable("Unknown register for mttc0 alias!")::llvm::llvm_unreachable_internal("Unknown register for mttc0 alias!"
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5642);
}
5644}

5646/// Expand an alias of 'mftr' or 'mttr' into the full instruction, by producing
5647/// an mftr or mttr with the correctly mapped gpr register, u, sel and h bits.
5648bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                  const MCSubtargetInfo *STI) {
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned rd = 0;
unsigned u = 1;
unsigned sel = 0;
unsigned h = 0;
bool IsMFTR = false;
switch (Inst.getOpcode()) {
  case Mips::MFTC0:
    IsMFTR = true;
    [[fallthrough]];
  case Mips::MTTC0:
    u = 0;
    rd = getRegisterForMxtrC0(Inst, IsMFTR);
    sel = Inst.getOperand(2).getImm();
    break;
  case Mips::MFTGPR:
    IsMFTR = true;
    [[fallthrough]];
  case Mips::MTTGPR:
    rd = Inst.getOperand(IsMFTR ? 1 : 0).getReg();
    break;
  case Mips::MFTLO:
  case Mips::MFTHI:
  case Mips::MFTACX:
  case Mips::MFTDSP:
    IsMFTR = true;
    [[fallthrough]];
  case Mips::MTTLO:
  case Mips::MTTHI:
  case Mips::MTTACX:
  case Mips::MTTDSP:
    rd = getRegisterForMxtrDSP(Inst, IsMFTR);
    sel = 1;
    break;
  case Mips::MFTHC1:
    h = 1;
    [[fallthrough]];
  case Mips::MFTC1:
    IsMFTR = true;
    rd = getRegisterForMxtrFP(Inst, IsMFTR);
    sel = 2;
    break;
  case Mips::MTTHC1:
    h = 1;
    [[fallthrough]];
  case Mips::MTTC1:
    rd = getRegisterForMxtrFP(Inst, IsMFTR);
    sel = 2;
    break;
  case Mips::CFTC1:
    IsMFTR = true;
    [[fallthrough]];
  case Mips::CTTC1:
    rd = getRegisterForMxtrFP(Inst, IsMFTR);
    sel = 3;
    break;
}
unsigned Op0 = IsMFTR ? Inst.getOperand(0).getReg() : rd;
unsigned Op1 =
    IsMFTR ? rd
           : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg()
                                               : Inst.getOperand(0).getReg());

TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc,
               STI);
return false;
5716}

5718bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                                const MCSubtargetInfo *STI) {
assert(Inst.getNumOperands() == 3 && "expected three operands")(static_cast <bool> (Inst.getNumOperands() == 3 &&
 "expected three operands") ? void (0) : __assert_fail ("Inst.getNumOperands() == 3 && \"expected three operands\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5720, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(0).isReg() && "expected register operand kind")(static_cast <bool> (Inst.getOperand(0).isReg() &&
 "expected register operand kind") ? void (0) : __assert_fail
 ("Inst.getOperand(0).isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5721, __extension__
 __PRETTY_FUNCTION__));
assert(Inst.getOperand(1).isReg() && "expected register operand kind")(static_cast <bool> (Inst.getOperand(1).isReg() &&
 "expected register operand kind") ? void (0) : __assert_fail
 ("Inst.getOperand(1).isReg() && \"expected register operand kind\""
, "llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp", 5722, __extension__
 __PRETTY_FUNCTION__));

warnIfNoMacro(IDLoc);

MipsTargetStreamer &TOut = getTargetStreamer();
5727