Bug Summary

File:lib/Target/Mips/MipsISelLowering.cpp
Warning:line 1701, column 3
Value stored to 'BB' is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MipsISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/Mips -I /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/Mips -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp
1//===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "MipsISelLowering.h"
16#include "InstPrinter/MipsInstPrinter.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "MCTargetDesc/MipsMCTargetDesc.h"
19#include "MipsCCState.h"
20#include "MipsInstrInfo.h"
21#include "MipsMachineFunction.h"
22#include "MipsRegisterInfo.h"
23#include "MipsSubtarget.h"
24#include "MipsTargetMachine.h"
25#include "MipsTargetObjectFile.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/SmallVector.h"
29#include "llvm/ADT/Statistic.h"
30#include "llvm/ADT/StringRef.h"
31#include "llvm/ADT/StringSwitch.h"
32#include "llvm/CodeGen/CallingConvLower.h"
33#include "llvm/CodeGen/FunctionLoweringInfo.h"
34#include "llvm/CodeGen/ISDOpcodes.h"
35#include "llvm/CodeGen/MachineBasicBlock.h"
36#include "llvm/CodeGen/MachineFrameInfo.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineInstr.h"
39#include "llvm/CodeGen/MachineInstrBuilder.h"
40#include "llvm/CodeGen/MachineJumpTableInfo.h"
41#include "llvm/CodeGen/MachineMemOperand.h"
42#include "llvm/CodeGen/MachineOperand.h"
43#include "llvm/CodeGen/MachineRegisterInfo.h"
44#include "llvm/CodeGen/RuntimeLibcalls.h"
45#include "llvm/CodeGen/SelectionDAG.h"
46#include "llvm/CodeGen/SelectionDAGNodes.h"
47#include "llvm/CodeGen/TargetFrameLowering.h"
48#include "llvm/CodeGen/TargetInstrInfo.h"
49#include "llvm/CodeGen/TargetRegisterInfo.h"
50#include "llvm/CodeGen/ValueTypes.h"
51#include "llvm/IR/CallingConv.h"
52#include "llvm/IR/Constants.h"
53#include "llvm/IR/DataLayout.h"
54#include "llvm/IR/DebugLoc.h"
55#include "llvm/IR/DerivedTypes.h"
56#include "llvm/IR/Function.h"
57#include "llvm/IR/GlobalValue.h"
58#include "llvm/IR/Type.h"
59#include "llvm/IR/Value.h"
60#include "llvm/MC/MCRegisterInfo.h"
61#include "llvm/Support/Casting.h"
62#include "llvm/Support/CodeGen.h"
63#include "llvm/Support/CommandLine.h"
64#include "llvm/Support/Compiler.h"
65#include "llvm/Support/ErrorHandling.h"
66#include "llvm/Support/MachineValueType.h"
67#include "llvm/Support/MathExtras.h"
68#include "llvm/Target/TargetMachine.h"
69#include "llvm/Target/TargetOptions.h"
70#include <algorithm>
71#include <cassert>
72#include <cctype>
73#include <cstdint>
74#include <deque>
75#include <iterator>
76#include <utility>
77#include <vector>
78
79using namespace llvm;
80
81#define DEBUG_TYPE"mips-lower" "mips-lower"
82
83STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"mips-lower", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
84
85static cl::opt<bool>
86LargeGOT("mxgot", cl::Hidden,
87 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
88
89static cl::opt<bool>
90NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
91 cl::desc("MIPS: Don't trap on integer division by zero."),
92 cl::init(false));
93
94static const MCPhysReg Mips64DPRegs[8] = {
95 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
96 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
97};
98
99// If I is a shifted mask, set the size (Size) and the first bit of the
100// mask (Pos), and return true.
101// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
102static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
103 if (!isShiftedMask_64(I))
104 return false;
105
106 Size = countPopulation(I);
107 Pos = countTrailingZeros(I);
108 return true;
109}
110
111// The MIPS MSA ABI passes vector arguments in the integer register set.
112// The number of integer registers used is dependant on the ABI used.
113MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const {
114 if (VT.isVector() && Subtarget.hasMSA())
115 return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64;
116 return MipsTargetLowering::getRegisterType(VT);
117}
118
119MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
120 EVT VT) const {
121 if (VT.isVector()) {
122 if (Subtarget.isABI_O32()) {
123 return MVT::i32;
124 } else {
125 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
126 }
127 }
128 return MipsTargetLowering::getRegisterType(Context, VT);
129}
130
131unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
132 EVT VT) const {
133 if (VT.isVector())
134 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)),
135 1U);
136 return MipsTargetLowering::getNumRegisters(Context, VT);
137}
138
139unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
140 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
141 unsigned &NumIntermediates, MVT &RegisterVT) const {
142 // Break down vector types to either 2 i64s or 4 i32s.
143 RegisterVT = getRegisterTypeForCallingConv(Context, VT) ;
144 IntermediateVT = RegisterVT;
145 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
146 ? VT.getVectorNumElements()
147 : VT.getSizeInBits() / RegisterVT.getSizeInBits();
148
149 return NumIntermediates;
150}
151
152SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
153 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
154 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
155}
156
157SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
158 SelectionDAG &DAG,
159 unsigned Flag) const {
160 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
161}
162
163SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
164 SelectionDAG &DAG,
165 unsigned Flag) const {
166 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
167}
168
169SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
170 SelectionDAG &DAG,
171 unsigned Flag) const {
172 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
173}
174
175SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
176 SelectionDAG &DAG,
177 unsigned Flag) const {
178 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
179}
180
181SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
182 SelectionDAG &DAG,
183 unsigned Flag) const {
184 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
185 N->getOffset(), Flag);
186}
187
188const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
189 switch ((MipsISD::NodeType)Opcode) {
190 case MipsISD::FIRST_NUMBER: break;
191 case MipsISD::JmpLink: return "MipsISD::JmpLink";
192 case MipsISD::TailCall: return "MipsISD::TailCall";
193 case MipsISD::Highest: return "MipsISD::Highest";
194 case MipsISD::Higher: return "MipsISD::Higher";
195 case MipsISD::Hi: return "MipsISD::Hi";
196 case MipsISD::Lo: return "MipsISD::Lo";
197 case MipsISD::GotHi: return "MipsISD::GotHi";
198 case MipsISD::GPRel: return "MipsISD::GPRel";
199 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
200 case MipsISD::Ret: return "MipsISD::Ret";
201 case MipsISD::ERet: return "MipsISD::ERet";
202 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
203 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
204 case MipsISD::FPCmp: return "MipsISD::FPCmp";
205 case MipsISD::FSELECT: return "MipsISD::FSELECT";
206 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
207 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
208 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
209 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
210 case MipsISD::MFHI: return "MipsISD::MFHI";
211 case MipsISD::MFLO: return "MipsISD::MFLO";
212 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
213 case MipsISD::Mult: return "MipsISD::Mult";
214 case MipsISD::Multu: return "MipsISD::Multu";
215 case MipsISD::MAdd: return "MipsISD::MAdd";
216 case MipsISD::MAddu: return "MipsISD::MAddu";
217 case MipsISD::MSub: return "MipsISD::MSub";
218 case MipsISD::MSubu: return "MipsISD::MSubu";
219 case MipsISD::DivRem: return "MipsISD::DivRem";
220 case MipsISD::DivRemU: return "MipsISD::DivRemU";
221 case MipsISD::DivRem16: return "MipsISD::DivRem16";
222 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
223 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
224 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
225 case MipsISD::Wrapper: return "MipsISD::Wrapper";
226 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
227 case MipsISD::Sync: return "MipsISD::Sync";
228 case MipsISD::Ext: return "MipsISD::Ext";
229 case MipsISD::Ins: return "MipsISD::Ins";
230 case MipsISD::CIns: return "MipsISD::CIns";
231 case MipsISD::LWL: return "MipsISD::LWL";
232 case MipsISD::LWR: return "MipsISD::LWR";
233 case MipsISD::SWL: return "MipsISD::SWL";
234 case MipsISD::SWR: return "MipsISD::SWR";
235 case MipsISD::LDL: return "MipsISD::LDL";
236 case MipsISD::LDR: return "MipsISD::LDR";
237 case MipsISD::SDL: return "MipsISD::SDL";
238 case MipsISD::SDR: return "MipsISD::SDR";
239 case MipsISD::EXTP: return "MipsISD::EXTP";
240 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
241 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
242 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
243 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
244 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
245 case MipsISD::SHILO: return "MipsISD::SHILO";
246 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
247 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
248 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
249 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
250 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
251 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
252 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
253 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
254 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
255 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
256 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
257 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
258 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
259 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
260 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
261 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
262 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
263 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
264 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
265 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
266 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
267 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
268 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
269 case MipsISD::MULT: return "MipsISD::MULT";
270 case MipsISD::MULTU: return "MipsISD::MULTU";
271 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
272 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
273 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
274 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
275 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
276 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
277 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
278 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
279 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
280 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
281 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
282 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
283 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
284 case MipsISD::VCEQ: return "MipsISD::VCEQ";
285 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
286 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
287 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
288 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
289 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
290 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
291 case MipsISD::VNOR: return "MipsISD::VNOR";
292 case MipsISD::VSHF: return "MipsISD::VSHF";
293 case MipsISD::SHF: return "MipsISD::SHF";
294 case MipsISD::ILVEV: return "MipsISD::ILVEV";
295 case MipsISD::ILVOD: return "MipsISD::ILVOD";
296 case MipsISD::ILVL: return "MipsISD::ILVL";
297 case MipsISD::ILVR: return "MipsISD::ILVR";
298 case MipsISD::PCKEV: return "MipsISD::PCKEV";
299 case MipsISD::PCKOD: return "MipsISD::PCKOD";
300 case MipsISD::INSVE: return "MipsISD::INSVE";
301 }
302 return nullptr;
303}
304
305MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
306 const MipsSubtarget &STI)
307 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
308 // Mips does not have i1 type, so use i32 for
309 // setcc operations results (slt, sgt, ...).
310 setBooleanContents(ZeroOrOneBooleanContent);
311 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
312 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
313 // does. Integer booleans still use 0 and 1.
314 if (Subtarget.hasMips32r6())
315 setBooleanContents(ZeroOrOneBooleanContent,
316 ZeroOrNegativeOneBooleanContent);
317
318 // Load extented operations for i1 types must be promoted
319 for (MVT VT : MVT::integer_valuetypes()) {
320 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
321 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
322 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
323 }
324
325 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
326 // for f32, f16
327 for (MVT VT : MVT::fp_valuetypes()) {
328 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
329 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
330 }
331
332 // Set LoadExtAction for f16 vectors to Expand
333 for (MVT VT : MVT::fp_vector_valuetypes()) {
334 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
335 if (F16VT.isValid())
336 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
337 }
338
339 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
340 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
341
342 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
343
344 // Used by legalize types to correctly generate the setcc result.
345 // Without this, every float setcc comes with a AND/OR with the result,
346 // we don't want this, since the fpcmp result goes to a flag register,
347 // which is used implicitly by brcond and select operations.
348 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
349
350 // Mips Custom Operations
351 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
352 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
353 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
354 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
355 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
356 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
357 setOperationAction(ISD::SELECT, MVT::f32, Custom);
358 setOperationAction(ISD::SELECT, MVT::f64, Custom);
359 setOperationAction(ISD::SELECT, MVT::i32, Custom);
360 setOperationAction(ISD::SETCC, MVT::f32, Custom);
361 setOperationAction(ISD::SETCC, MVT::f64, Custom);
362 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
363 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
364 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
365 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
366
367 if (Subtarget.isGP64bit()) {
368 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
369 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
370 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
371 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
372 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
373 setOperationAction(ISD::SELECT, MVT::i64, Custom);
374 setOperationAction(ISD::LOAD, MVT::i64, Custom);
375 setOperationAction(ISD::STORE, MVT::i64, Custom);
376 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
377 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
378 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
379 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
380 }
381
382 if (!Subtarget.isGP64bit()) {
383 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
384 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
385 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
386 }
387
388 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
389 if (Subtarget.isGP64bit())
390 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
391
392 setOperationAction(ISD::SDIV, MVT::i32, Expand);
393 setOperationAction(ISD::SREM, MVT::i32, Expand);
394 setOperationAction(ISD::UDIV, MVT::i32, Expand);
395 setOperationAction(ISD::UREM, MVT::i32, Expand);
396 setOperationAction(ISD::SDIV, MVT::i64, Expand);
397 setOperationAction(ISD::SREM, MVT::i64, Expand);
398 setOperationAction(ISD::UDIV, MVT::i64, Expand);
399 setOperationAction(ISD::UREM, MVT::i64, Expand);
400
401 if (!(Subtarget.hasDSP() && Subtarget.hasMips32r2())) {
402 setOperationAction(ISD::ADDC, MVT::i32, Expand);
403 setOperationAction(ISD::ADDE, MVT::i32, Expand);
404 }
405
406 setOperationAction(ISD::ADDC, MVT::i64, Expand);
407 setOperationAction(ISD::ADDE, MVT::i64, Expand);
408 setOperationAction(ISD::SUBC, MVT::i32, Expand);
409 setOperationAction(ISD::SUBE, MVT::i32, Expand);
410 setOperationAction(ISD::SUBC, MVT::i64, Expand);
411 setOperationAction(ISD::SUBE, MVT::i64, Expand);
412
413 // Operations not directly supported by Mips.
414 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
415 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
416 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
417 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
418 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
419 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
420 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
421 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
422 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
423 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
424 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
425 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
426 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
427 if (Subtarget.hasCnMips()) {
428 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
429 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
430 } else {
431 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
432 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
433 }
434 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
435 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
436 setOperationAction(ISD::ROTL, MVT::i32, Expand);
437 setOperationAction(ISD::ROTL, MVT::i64, Expand);
438 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
439 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
440
441 if (!Subtarget.hasMips32r2())
442 setOperationAction(ISD::ROTR, MVT::i32, Expand);
443
444 if (!Subtarget.hasMips64r2())
445 setOperationAction(ISD::ROTR, MVT::i64, Expand);
446
447 setOperationAction(ISD::FSIN, MVT::f32, Expand);
448 setOperationAction(ISD::FSIN, MVT::f64, Expand);
449 setOperationAction(ISD::FCOS, MVT::f32, Expand);
450 setOperationAction(ISD::FCOS, MVT::f64, Expand);
451 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
452 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
453 setOperationAction(ISD::FPOW, MVT::f32, Expand);
454 setOperationAction(ISD::FPOW, MVT::f64, Expand);
455 setOperationAction(ISD::FLOG, MVT::f32, Expand);
456 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
457 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
458 setOperationAction(ISD::FEXP, MVT::f32, Expand);
459 setOperationAction(ISD::FMA, MVT::f32, Expand);
460 setOperationAction(ISD::FMA, MVT::f64, Expand);
461 setOperationAction(ISD::FREM, MVT::f32, Expand);
462 setOperationAction(ISD::FREM, MVT::f64, Expand);
463
464 // Lower f16 conversion operations into library calls
465 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
466 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
467 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
468 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
469
470 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
471
472 setOperationAction(ISD::VASTART, MVT::Other, Custom);
473 setOperationAction(ISD::VAARG, MVT::Other, Custom);
474 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
475 setOperationAction(ISD::VAEND, MVT::Other, Expand);
476
477 // Use the default for now
478 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
479 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
480
481 if (!Subtarget.isGP64bit()) {
482 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
483 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
484 }
485
486 if (!Subtarget.hasMips32r2()) {
487 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
488 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
489 }
490
491 // MIPS16 lacks MIPS32's clz and clo instructions.
492 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
493 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
494 if (!Subtarget.hasMips64())
495 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
496
497 if (!Subtarget.hasMips32r2())
498 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
499 if (!Subtarget.hasMips64r2())
500 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
501
502 if (Subtarget.isGP64bit()) {
503 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
504 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
505 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
506 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
507 }
508
509 setOperationAction(ISD::TRAP, MVT::Other, Legal);
510
511 setTargetDAGCombine(ISD::SDIVREM);
512 setTargetDAGCombine(ISD::UDIVREM);
513 setTargetDAGCombine(ISD::SELECT);
514 setTargetDAGCombine(ISD::AND);
515 setTargetDAGCombine(ISD::OR);
516 setTargetDAGCombine(ISD::ADD);
517 setTargetDAGCombine(ISD::SUB);
518 setTargetDAGCombine(ISD::AssertZext);
519 setTargetDAGCombine(ISD::SHL);
520
521 if (ABI.IsO32()) {
522 // These libcalls are not available in 32-bit.
523 setLibcallName(RTLIB::SHL_I128, nullptr);
524 setLibcallName(RTLIB::SRL_I128, nullptr);
525 setLibcallName(RTLIB::SRA_I128, nullptr);
526 }
527
528 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
529
530 // The arguments on the stack are defined in terms of 4-byte slots on O32
531 // and 8-byte slots on N32/N64.
532 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
533
534 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
535
536 MaxStoresPerMemcpy = 16;
537
538 isMicroMips = Subtarget.inMicroMipsMode();
539}
540
541const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
542 const MipsSubtarget &STI) {
543 if (STI.inMips16Mode())
544 return createMips16TargetLowering(TM, STI);
545
546 return createMipsSETargetLowering(TM, STI);
547}
548
549// Create a fast isel object.
550FastISel *
551MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
552 const TargetLibraryInfo *libInfo) const {
553 const MipsTargetMachine &TM =
554 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
555
556 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
557 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
558 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() &&
559 !Subtarget.inMicroMipsMode();
560
561 // Disable if either of the following is true:
562 // We do not generate PIC, the ABI is not O32, LargeGOT is being used.
563 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || LargeGOT)
564 UseFastISel = false;
565
566 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
567}
568
569EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
570 EVT VT) const {
571 if (!VT.isVector())
572 return MVT::i32;
573 return VT.changeVectorElementTypeToInteger();
574}
575
576static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
577 TargetLowering::DAGCombinerInfo &DCI,
578 const MipsSubtarget &Subtarget) {
579 if (DCI.isBeforeLegalizeOps())
580 return SDValue();
581
582 EVT Ty = N->getValueType(0);
583 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
584 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
585 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
586 MipsISD::DivRemU16;
587 SDLoc DL(N);
588
589 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
590 N->getOperand(0), N->getOperand(1));
591 SDValue InChain = DAG.getEntryNode();
592 SDValue InGlue = DivRem;
593
594 // insert MFLO
595 if (N->hasAnyUseOfValue(0)) {
596 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
597 InGlue);
598 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
599 InChain = CopyFromLo.getValue(1);
600 InGlue = CopyFromLo.getValue(2);
601 }
602
603 // insert MFHI
604 if (N->hasAnyUseOfValue(1)) {
605 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
606 HI, Ty, InGlue);
607 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
608 }
609
610 return SDValue();
611}
612
613static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
614 switch (CC) {
615 default: llvm_unreachable("Unknown fp condition code!")::llvm::llvm_unreachable_internal("Unknown fp condition code!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 615)
;
616 case ISD::SETEQ:
617 case ISD::SETOEQ: return Mips::FCOND_OEQ;
618 case ISD::SETUNE: return Mips::FCOND_UNE;
619 case ISD::SETLT:
620 case ISD::SETOLT: return Mips::FCOND_OLT;
621 case ISD::SETGT:
622 case ISD::SETOGT: return Mips::FCOND_OGT;
623 case ISD::SETLE:
624 case ISD::SETOLE: return Mips::FCOND_OLE;
625 case ISD::SETGE:
626 case ISD::SETOGE: return Mips::FCOND_OGE;
627 case ISD::SETULT: return Mips::FCOND_ULT;
628 case ISD::SETULE: return Mips::FCOND_ULE;
629 case ISD::SETUGT: return Mips::FCOND_UGT;
630 case ISD::SETUGE: return Mips::FCOND_UGE;
631 case ISD::SETUO: return Mips::FCOND_UN;
632 case ISD::SETO: return Mips::FCOND_OR;
633 case ISD::SETNE:
634 case ISD::SETONE: return Mips::FCOND_ONE;
635 case ISD::SETUEQ: return Mips::FCOND_UEQ;
636 }
637}
638
639/// This function returns true if the floating point conditional branches and
640/// conditional moves which use condition code CC should be inverted.
641static bool invertFPCondCodeUser(Mips::CondCode CC) {
642 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
643 return false;
644
645 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&(static_cast <bool> ((CC >= Mips::FCOND_T &&
CC <= Mips::FCOND_GT) && "Illegal Condition Code"
) ? void (0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 646, __extension__ __PRETTY_FUNCTION__))
646 "Illegal Condition Code")(static_cast <bool> ((CC >= Mips::FCOND_T &&
CC <= Mips::FCOND_GT) && "Illegal Condition Code"
) ? void (0) : __assert_fail ("(CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && \"Illegal Condition Code\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 646, __extension__ __PRETTY_FUNCTION__))
;
647
648 return true;
649}
650
651// Creates and returns an FPCmp node from a setcc node.
652// Returns Op if setcc is not a floating point comparison.
653static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
654 // must be a SETCC node
655 if (Op.getOpcode() != ISD::SETCC)
656 return Op;
657
658 SDValue LHS = Op.getOperand(0);
659
660 if (!LHS.getValueType().isFloatingPoint())
661 return Op;
662
663 SDValue RHS = Op.getOperand(1);
664 SDLoc DL(Op);
665
666 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
667 // node if necessary.
668 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
669
670 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
671 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
672}
673
674// Creates and returns a CMovFPT/F node.
675static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
676 SDValue False, const SDLoc &DL) {
677 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
678 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
679 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
680
681 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
682 True.getValueType(), True, FCC0, False, Cond);
683}
684
685static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
686 TargetLowering::DAGCombinerInfo &DCI,
687 const MipsSubtarget &Subtarget) {
688 if (DCI.isBeforeLegalizeOps())
689 return SDValue();
690
691 SDValue SetCC = N->getOperand(0);
692
693 if ((SetCC.getOpcode() != ISD::SETCC) ||
694 !SetCC.getOperand(0).getValueType().isInteger())
695 return SDValue();
696
697 SDValue False = N->getOperand(2);
698 EVT FalseTy = False.getValueType();
699
700 if (!FalseTy.isInteger())
701 return SDValue();
702
703 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
704
705 // If the RHS (False) is 0, we swap the order of the operands
706 // of ISD::SELECT (obviously also inverting the condition) so that we can
707 // take advantage of conditional moves using the $0 register.
708 // Example:
709 // return (a != 0) ? x : 0;
710 // load $reg, x
711 // movz $reg, $0, a
712 if (!FalseC)
713 return SDValue();
714
715 const SDLoc DL(N);
716
717 if (!FalseC->getZExtValue()) {
718 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
719 SDValue True = N->getOperand(1);
720
721 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
722 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
723
724 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
725 }
726
727 // If both operands are integer constants there's a possibility that we
728 // can do some interesting optimizations.
729 SDValue True = N->getOperand(1);
730 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
731
732 if (!TrueC || !True.getValueType().isInteger())
733 return SDValue();
734
735 // We'll also ignore MVT::i64 operands as this optimizations proves
736 // to be ineffective because of the required sign extensions as the result
737 // of a SETCC operator is always MVT::i32 for non-vector types.
738 if (True.getValueType() == MVT::i64)
739 return SDValue();
740
741 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
742
743 // 1) (a < x) ? y : y-1
744 // slti $reg1, a, x
745 // addiu $reg2, $reg1, y-1
746 if (Diff == 1)
747 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
748
749 // 2) (a < x) ? y-1 : y
750 // slti $reg1, a, x
751 // xor $reg1, $reg1, 1
752 // addiu $reg2, $reg1, y-1
753 if (Diff == -1) {
754 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
755 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
756 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
757 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
758 }
759
760 // Couldn't optimize.
761 return SDValue();
762}
763
764static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
765 TargetLowering::DAGCombinerInfo &DCI,
766 const MipsSubtarget &Subtarget) {
767 if (DCI.isBeforeLegalizeOps())
768 return SDValue();
769
770 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
771
772 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
773 if (!FalseC || FalseC->getZExtValue())
774 return SDValue();
775
776 // Since RHS (False) is 0, we swap the order of the True/False operands
777 // (obviously also inverting the condition) so that we can
778 // take advantage of conditional moves using the $0 register.
779 // Example:
780 // return (a != 0) ? x : 0;
781 // load $reg, x
782 // movz $reg, $0, a
783 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
784 MipsISD::CMovFP_T;
785
786 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
787 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
788 ValueIfFalse, FCC, ValueIfTrue, Glue);
789}
790
791static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
792 TargetLowering::DAGCombinerInfo &DCI,
793 const MipsSubtarget &Subtarget) {
794 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
795 return SDValue();
796
797 SDValue FirstOperand = N->getOperand(0);
798 unsigned FirstOperandOpc = FirstOperand.getOpcode();
799 SDValue Mask = N->getOperand(1);
800 EVT ValTy = N->getValueType(0);
801 SDLoc DL(N);
802
803 uint64_t Pos = 0, SMPos, SMSize;
804 ConstantSDNode *CN;
805 SDValue NewOperand;
806 unsigned Opc;
807
808 // Op's second operand must be a shifted mask.
809 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
810 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
811 return SDValue();
812
813 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
814 // Pattern match EXT.
815 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
816 // => ext $dst, $src, pos, size
817
818 // The second operand of the shift must be an immediate.
819 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
820 return SDValue();
821
822 Pos = CN->getZExtValue();
823
824 // Return if the shifted mask does not start at bit 0 or the sum of its size
825 // and Pos exceeds the word's size.
826 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
827 return SDValue();
828
829 Opc = MipsISD::Ext;
830 NewOperand = FirstOperand.getOperand(0);
831 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
832 // Pattern match CINS.
833 // $dst = and (shl $src , pos), mask
834 // => cins $dst, $src, pos, size
835 // mask is a shifted mask with consecutive 1's, pos = shift amount,
836 // size = population count.
837
838 // The second operand of the shift must be an immediate.
839 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
840 return SDValue();
841
842 Pos = CN->getZExtValue();
843
844 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
845 Pos + SMSize > ValTy.getSizeInBits())
846 return SDValue();
847
848 NewOperand = FirstOperand.getOperand(0);
849 // SMSize is 'location' (position) in this case, not size.
850 SMSize--;
851 Opc = MipsISD::CIns;
852 } else {
853 // Pattern match EXT.
854 // $dst = and $src, (2**size - 1) , if size > 16
855 // => ext $dst, $src, pos, size , pos = 0
856
857 // If the mask is <= 0xffff, andi can be used instead.
858 if (CN->getZExtValue() <= 0xffff)
859 return SDValue();
860
861 // Return if the mask doesn't start at position 0.
862 if (SMPos)
863 return SDValue();
864
865 Opc = MipsISD::Ext;
866 NewOperand = FirstOperand;
867 }
868 return DAG.getNode(Opc, DL, ValTy, NewOperand,
869 DAG.getConstant(Pos, DL, MVT::i32),
870 DAG.getConstant(SMSize, DL, MVT::i32));
871}
872
873static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
874 TargetLowering::DAGCombinerInfo &DCI,
875 const MipsSubtarget &Subtarget) {
876 // Pattern match INS.
877 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
878 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
879 // => ins $dst, $src, size, pos, $src1
880 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
881 return SDValue();
882
883 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
884 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
885 ConstantSDNode *CN, *CN1;
886
887 // See if Op's first operand matches (and $src1 , mask0).
888 if (And0.getOpcode() != ISD::AND)
889 return SDValue();
890
891 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
892 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
893 return SDValue();
894
895 // See if Op's second operand matches (and (shl $src, pos), mask1).
896 if (And1.getOpcode() == ISD::AND &&
897 And1.getOperand(0).getOpcode() == ISD::SHL) {
898
899 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
900 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
901 return SDValue();
902
903 // The shift masks must have the same position and size.
904 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
905 return SDValue();
906
907 SDValue Shl = And1.getOperand(0);
908
909 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
910 return SDValue();
911
912 unsigned Shamt = CN->getZExtValue();
913
914 // Return if the shift amount and the first bit position of mask are not the
915 // same.
916 EVT ValTy = N->getValueType(0);
917 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
918 return SDValue();
919
920 SDLoc DL(N);
921 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
922 DAG.getConstant(SMPos0, DL, MVT::i32),
923 DAG.getConstant(SMSize0, DL, MVT::i32),
924 And0.getOperand(0));
925 } else {
926 // Pattern match DINS.
927 // $dst = or (and $src, mask0), mask1
928 // where mask0 = ((1 << SMSize0) -1) << SMPos0
929 // => dins $dst, $src, pos, size
930 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
931 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
932 (SMSize0 + SMPos0 <= 32))) {
933 // Check if AND instruction has constant as argument
934 bool isConstCase = And1.getOpcode() != ISD::AND;
935 if (And1.getOpcode() == ISD::AND) {
936 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
937 return SDValue();
938 } else {
939 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
940 return SDValue();
941 }
942 // Don't generate INS if constant OR operand doesn't fit into bits
943 // cleared by constant AND operand.
944 if (CN->getSExtValue() & CN1->getSExtValue())
945 return SDValue();
946
947 SDLoc DL(N);
948 EVT ValTy = N->getOperand(0)->getValueType(0);
949 SDValue Const1;
950 SDValue SrlX;
951 if (!isConstCase) {
952 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
953 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
954 }
955 return DAG.getNode(
956 MipsISD::Ins, DL, N->getValueType(0),
957 isConstCase
958 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
959 : SrlX,
960 DAG.getConstant(SMPos0, DL, MVT::i32),
961 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
962 : SMSize0,
963 DL, MVT::i32),
964 And0->getOperand(0));
965
966 }
967 return SDValue();
968 }
969}
970
971static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG,
972 const MipsSubtarget &Subtarget) {
973 // ROOTNode must have a multiplication as an operand for the match to be
974 // successful.
975 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
976 ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
977 return SDValue();
978
979 // We don't handle vector types here.
980 if (ROOTNode->getValueType(0).isVector())
981 return SDValue();
982
983 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
984 // arithmetic. E.g.
985 // (add (mul a b) c) =>
986 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
987 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
988 // or
989 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
990 //
991 // The overhead of setting up the Hi/Lo registers and reassembling the
992 // result makes this a dubious optimzation for MIPS64. The core of the
993 // problem is that Hi/Lo contain the upper and lower 32 bits of the
994 // operand and result.
995 //
996 // It requires a chain of 4 add/mul for MIPS64R2 to get better code
997 // density than doing it naively, 5 for MIPS64. Additionally, using
998 // madd/msub on MIPS64 requires the operands actually be 32 bit sign
999 // extended operands, not true 64 bit values.
1000 //
1001 // FIXME: For the moment, disable this completely for MIPS64.
1002 if (Subtarget.hasMips64())
1003 return SDValue();
1004
1005 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1006 ? ROOTNode->getOperand(0)
1007 : ROOTNode->getOperand(1);
1008
1009 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1010 ? ROOTNode->getOperand(1)
1011 : ROOTNode->getOperand(0);
1012
1013 // Transform this to a MADD only if the user of this node is the add.
1014 // If there are other users of the mul, this function returns here.
1015 if (!Mult.hasOneUse())
1016 return SDValue();
1017
1018 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1019 // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1020 // of the multiply must have 32 or more sign bits, otherwise we cannot
1021 // perform this optimization. We have to check this here as we're performing
1022 // this optimization pre-legalization.
1023 SDValue MultLHS = Mult->getOperand(0);
1024 SDValue MultRHS = Mult->getOperand(1);
1025
1026 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1027 MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1028 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1029 MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1030
1031 if (!IsSigned && !IsUnsigned)
1032 return SDValue();
1033
1034 // Initialize accumulator.
1035 SDLoc DL(ROOTNode);
1036 SDValue TopHalf;
1037 SDValue BottomHalf;
1038 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1039 CurDAG.getIntPtrConstant(0, DL));
1040
1041 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1042 CurDAG.getIntPtrConstant(1, DL));
1043 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1044 BottomHalf,
1045 TopHalf);
1046
1047 // Create MipsMAdd(u) / MipsMSub(u) node.
1048 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1049 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1050 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1051 SDValue MAddOps[3] = {
1052 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1053 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1054 EVT VTs[2] = {MVT::i32, MVT::i32};
1055 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1056
1057 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1058 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1059 SDValue Combined =
1060 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1061 return Combined;
1062}
1063
1064static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
1065 TargetLowering::DAGCombinerInfo &DCI,
1066 const MipsSubtarget &Subtarget) {
1067 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1068 if (DCI.isBeforeLegalizeOps()) {
1069 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1070 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1071 return performMADD_MSUBCombine(N, DAG, Subtarget);
1072
1073 return SDValue();
1074 }
1075
1076 return SDValue();
1077}
1078
1079static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
1080 TargetLowering::DAGCombinerInfo &DCI,
1081 const MipsSubtarget &Subtarget) {
1082 // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1083 if (DCI.isBeforeLegalizeOps()) {
1084 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1085 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1086 return performMADD_MSUBCombine(N, DAG, Subtarget);
1087
1088 return SDValue();
1089 }
1090
1091 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1092 SDValue Add = N->getOperand(1);
1093
1094 if (Add.getOpcode() != ISD::ADD)
1095 return SDValue();
1096
1097 SDValue Lo = Add.getOperand(1);
1098
1099 if ((Lo.getOpcode() != MipsISD::Lo) ||
1100 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1101 return SDValue();
1102
1103 EVT ValTy = N->getValueType(0);
1104 SDLoc DL(N);
1105
1106 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1107 Add.getOperand(0));
1108 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1109}
1110
1111static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
1112 TargetLowering::DAGCombinerInfo &DCI,
1113 const MipsSubtarget &Subtarget) {
1114 // Pattern match CINS.
1115 // $dst = shl (and $src , imm), pos
1116 // => cins $dst, $src, pos, size
1117
1118 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1119 return SDValue();
1120
1121 SDValue FirstOperand = N->getOperand(0);
1122 unsigned FirstOperandOpc = FirstOperand.getOpcode();
1123 SDValue SecondOperand = N->getOperand(1);
1124 EVT ValTy = N->getValueType(0);
1125 SDLoc DL(N);
1126
1127 uint64_t Pos = 0, SMPos, SMSize;
1128 ConstantSDNode *CN;
1129 SDValue NewOperand;
1130
1131 // The second operand of the shift must be an immediate.
1132 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1133 return SDValue();
1134
1135 Pos = CN->getZExtValue();
1136
1137 if (Pos >= ValTy.getSizeInBits())
1138 return SDValue();
1139
1140 if (FirstOperandOpc != ISD::AND)
1141 return SDValue();
1142
1143 // AND's second operand must be a shifted mask.
1144 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1145 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
1146 return SDValue();
1147
1148 // Return if the shifted mask does not start at bit 0 or the sum of its size
1149 // and Pos exceeds the word's size.
1150 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1151 return SDValue();
1152
1153 NewOperand = FirstOperand.getOperand(0);
1154 // SMSize is 'location' (position) in this case, not size.
1155 SMSize--;
1156
1157 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1158 DAG.getConstant(Pos, DL, MVT::i32),
1159 DAG.getConstant(SMSize, DL, MVT::i32));
1160}
1161
1162SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
1163 const {
1164 SelectionDAG &DAG = DCI.DAG;
1165 unsigned Opc = N->getOpcode();
1166
1167 switch (Opc) {
1168 default: break;
1169 case ISD::SDIVREM:
1170 case ISD::UDIVREM:
1171 return performDivRemCombine(N, DAG, DCI, Subtarget);
1172 case ISD::SELECT:
1173 return performSELECTCombine(N, DAG, DCI, Subtarget);
1174 case MipsISD::CMovFP_F:
1175 case MipsISD::CMovFP_T:
1176 return performCMovFPCombine(N, DAG, DCI, Subtarget);
1177 case ISD::AND:
1178 return performANDCombine(N, DAG, DCI, Subtarget);
1179 case ISD::OR:
1180 return performORCombine(N, DAG, DCI, Subtarget);
1181 case ISD::ADD:
1182 return performADDCombine(N, DAG, DCI, Subtarget);
1183 case ISD::SHL:
1184 return performSHLCombine(N, DAG, DCI, Subtarget);
1185 case ISD::SUB:
1186 return performSUBCombine(N, DAG, DCI, Subtarget);
1187 }
1188
1189 return SDValue();
1190}
1191
1192bool MipsTargetLowering::isCheapToSpeculateCttz() const {
1193 return Subtarget.hasMips32();
1194}
1195
1196bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
1197 return Subtarget.hasMips32();
1198}
1199
1200void
1201MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1202 SmallVectorImpl<SDValue> &Results,
1203 SelectionDAG &DAG) const {
1204 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1205
1206 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1207 Results.push_back(Res.getValue(I));
1208}
1209
1210void
1211MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1212 SmallVectorImpl<SDValue> &Results,
1213 SelectionDAG &DAG) const {
1214 return LowerOperationWrapper(N, Results, DAG);
1215}
1216
1217SDValue MipsTargetLowering::
1218LowerOperation(SDValue Op, SelectionDAG &DAG) const
1219{
1220 switch (Op.getOpcode())
1221 {
1222 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1223 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1224 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1225 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1226 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1227 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1228 case ISD::SELECT: return lowerSELECT(Op, DAG);
1229 case ISD::SETCC: return lowerSETCC(Op, DAG);
1230 case ISD::VASTART: return lowerVASTART(Op, DAG);
1231 case ISD::VAARG: return lowerVAARG(Op, DAG);
1232 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1233 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1234 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1235 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1236 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1237 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1238 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
1239 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
1240 case ISD::LOAD: return lowerLOAD(Op, DAG);
1241 case ISD::STORE: return lowerSTORE(Op, DAG);
1242 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1243 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1244 }
1245 return SDValue();
1246}
1247
1248//===----------------------------------------------------------------------===//
1249// Lower helper functions
1250//===----------------------------------------------------------------------===//
1251
1252// addLiveIn - This helper function adds the specified physical register to the
1253// MachineFunction as a live in value. It also creates a corresponding
1254// virtual register for it.
1255static unsigned
1256addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1257{
1258 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1259 MF.getRegInfo().addLiveIn(PReg, VReg);
1260 return VReg;
1261}
1262
1263static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
1264 MachineBasicBlock &MBB,
1265 const TargetInstrInfo &TII,
1266 bool Is64Bit, bool IsMicroMips) {
1267 if (NoZeroDivCheck)
1268 return &MBB;
1269
1270 // Insert instruction "teq $divisor_reg, $zero, 7".
1271 MachineBasicBlock::iterator I(MI);
1272 MachineInstrBuilder MIB;
1273 MachineOperand &Divisor = MI.getOperand(2);
1274 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1275 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1276 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1277 .addReg(Mips::ZERO)
1278 .addImm(7);
1279
1280 // Use the 32-bit sub-register if this is a 64-bit division.
1281 if (Is64Bit)
1282 MIB->getOperand(0).setSubReg(Mips::sub_32);
1283
1284 // Clear Divisor's kill flag.
1285 Divisor.setIsKill(false);
1286
1287 // We would normally delete the original instruction here but in this case
1288 // we only needed to inject an additional instruction rather than replace it.
1289
1290 return &MBB;
1291}
1292
1293MachineBasicBlock *
1294MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1295 MachineBasicBlock *BB) const {
1296 switch (MI.getOpcode()) {
1297 default:
1298 llvm_unreachable("Unexpected instr type to insert")::llvm::llvm_unreachable_internal("Unexpected instr type to insert"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1298)
;
1299 case Mips::ATOMIC_LOAD_ADD_I8:
1300 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
1301 case Mips::ATOMIC_LOAD_ADD_I16:
1302 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
1303 case Mips::ATOMIC_LOAD_ADD_I32:
1304 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
1305 case Mips::ATOMIC_LOAD_ADD_I64:
1306 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
1307
1308 case Mips::ATOMIC_LOAD_AND_I8:
1309 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
1310 case Mips::ATOMIC_LOAD_AND_I16:
1311 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
1312 case Mips::ATOMIC_LOAD_AND_I32:
1313 return emitAtomicBinary(MI, BB, 4, Mips::AND);
1314 case Mips::ATOMIC_LOAD_AND_I64:
1315 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
1316
1317 case Mips::ATOMIC_LOAD_OR_I8:
1318 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
1319 case Mips::ATOMIC_LOAD_OR_I16:
1320 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
1321 case Mips::ATOMIC_LOAD_OR_I32:
1322 return emitAtomicBinary(MI, BB, 4, Mips::OR);
1323 case Mips::ATOMIC_LOAD_OR_I64:
1324 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
1325
1326 case Mips::ATOMIC_LOAD_XOR_I8:
1327 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
1328 case Mips::ATOMIC_LOAD_XOR_I16:
1329 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
1330 case Mips::ATOMIC_LOAD_XOR_I32:
1331 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
1332 case Mips::ATOMIC_LOAD_XOR_I64:
1333 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
1334
1335 case Mips::ATOMIC_LOAD_NAND_I8:
1336 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
1337 case Mips::ATOMIC_LOAD_NAND_I16:
1338 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
1339 case Mips::ATOMIC_LOAD_NAND_I32:
1340 return emitAtomicBinary(MI, BB, 4, 0, true);
1341 case Mips::ATOMIC_LOAD_NAND_I64:
1342 return emitAtomicBinary(MI, BB, 8, 0, true);
1343
1344 case Mips::ATOMIC_LOAD_SUB_I8:
1345 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
1346 case Mips::ATOMIC_LOAD_SUB_I16:
1347 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
1348 case Mips::ATOMIC_LOAD_SUB_I32:
1349 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
1350 case Mips::ATOMIC_LOAD_SUB_I64:
1351 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
1352
1353 case Mips::ATOMIC_SWAP_I8:
1354 return emitAtomicBinaryPartword(MI, BB, 1, 0);
1355 case Mips::ATOMIC_SWAP_I16:
1356 return emitAtomicBinaryPartword(MI, BB, 2, 0);
1357 case Mips::ATOMIC_SWAP_I32:
1358 return emitAtomicBinary(MI, BB, 4, 0);
1359 case Mips::ATOMIC_SWAP_I64:
1360 return emitAtomicBinary(MI, BB, 8, 0);
1361
1362 case Mips::ATOMIC_CMP_SWAP_I8:
1363 return emitAtomicCmpSwapPartword(MI, BB, 1);
1364 case Mips::ATOMIC_CMP_SWAP_I16:
1365 return emitAtomicCmpSwapPartword(MI, BB, 2);
1366 case Mips::ATOMIC_CMP_SWAP_I32:
1367 return emitAtomicCmpSwap(MI, BB, 4);
1368 case Mips::ATOMIC_CMP_SWAP_I64:
1369 return emitAtomicCmpSwap(MI, BB, 8);
1370 case Mips::PseudoSDIV:
1371 case Mips::PseudoUDIV:
1372 case Mips::DIV:
1373 case Mips::DIVU:
1374 case Mips::MOD:
1375 case Mips::MODU:
1376 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1377 false);
1378 case Mips::SDIV_MM_Pseudo:
1379 case Mips::UDIV_MM_Pseudo:
1380 case Mips::SDIV_MM:
1381 case Mips::UDIV_MM:
1382 case Mips::DIV_MMR6:
1383 case Mips::DIVU_MMR6:
1384 case Mips::MOD_MMR6:
1385 case Mips::MODU_MMR6:
1386 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1387 case Mips::PseudoDSDIV:
1388 case Mips::PseudoDUDIV:
1389 case Mips::DDIV:
1390 case Mips::DDIVU:
1391 case Mips::DMOD:
1392 case Mips::DMODU:
1393 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1394
1395 case Mips::PseudoSELECT_I:
1396 case Mips::PseudoSELECT_I64:
1397 case Mips::PseudoSELECT_S:
1398 case Mips::PseudoSELECT_D32:
1399 case Mips::PseudoSELECT_D64:
1400 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1401 case Mips::PseudoSELECTFP_F_I:
1402 case Mips::PseudoSELECTFP_F_I64:
1403 case Mips::PseudoSELECTFP_F_S:
1404 case Mips::PseudoSELECTFP_F_D32:
1405 case Mips::PseudoSELECTFP_F_D64:
1406 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1407 case Mips::PseudoSELECTFP_T_I:
1408 case Mips::PseudoSELECTFP_T_I64:
1409 case Mips::PseudoSELECTFP_T_S:
1410 case Mips::PseudoSELECTFP_T_D32:
1411 case Mips::PseudoSELECTFP_T_D64:
1412 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1413 }
1414}
1415
1416// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1417// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1418MachineBasicBlock *MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1419 MachineBasicBlock *BB,
1420 unsigned Size,
1421 unsigned BinOpcode,
1422 bool Nand) const {
1423 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.")(static_cast <bool> ((Size == 4 || Size == 8) &&
"Unsupported size for EmitAtomicBinary.") ? void (0) : __assert_fail
("(Size == 4 || Size == 8) && \"Unsupported size for EmitAtomicBinary.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1423, __extension__ __PRETTY_FUNCTION__))
;
1424
1425 MachineFunction *MF = BB->getParent();
1426 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1427 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1428 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1429 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1430 DebugLoc DL = MI.getDebugLoc();
1431 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1432
1433 if (Size == 4) {
1434 if (isMicroMips) {
1435 LL = Mips::LL_MM;
1436 SC = Mips::SC_MM;
1437 } else {
1438 LL = Subtarget.hasMips32r6()
1439 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1440 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1441 SC = Subtarget.hasMips32r6()
1442 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1443 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1444 }
1445
1446 AND = Mips::AND;
1447 NOR = Mips::NOR;
1448 ZERO = Mips::ZERO;
1449 BEQ = Mips::BEQ;
1450 } else {
1451 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1452 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1453 AND = Mips::AND64;
1454 NOR = Mips::NOR64;
1455 ZERO = Mips::ZERO_64;
1456 BEQ = Mips::BEQ64;
1457 }
1458
1459 unsigned OldVal = MI.getOperand(0).getReg();
1460 unsigned Ptr = MI.getOperand(1).getReg();
1461 unsigned Incr = MI.getOperand(2).getReg();
1462
1463 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1464 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1465 unsigned Success = RegInfo.createVirtualRegister(RC);
1466
1467 // insert new blocks after the current block
1468 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1469 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1470 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1471 MachineFunction::iterator It = ++BB->getIterator();
1472 MF->insert(It, loopMBB);
1473 MF->insert(It, exitMBB);
1474
1475 // Transfer the remainder of BB and its successor edges to exitMBB.
1476 exitMBB->splice(exitMBB->begin(), BB,
1477 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1478 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1479
1480 // thisMBB:
1481 // ...
1482 // fallthrough --> loopMBB
1483 BB->addSuccessor(loopMBB);
1484 loopMBB->addSuccessor(loopMBB);
1485 loopMBB->addSuccessor(exitMBB);
1486
1487 // loopMBB:
1488 // ll oldval, 0(ptr)
1489 // <binop> storeval, oldval, incr
1490 // sc success, storeval, 0(ptr)
1491 // beq success, $0, loopMBB
1492 BB = loopMBB;
1493 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1494 if (Nand) {
1495 // and andres, oldval, incr
1496 // nor storeval, $0, andres
1497 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1498 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1499 } else if (BinOpcode) {
1500 // <binop> storeval, oldval, incr
1501 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1502 } else {
1503 StoreVal = Incr;
1504 }
1505 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1506 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1507
1508 MI.eraseFromParent(); // The instruction is gone now.
1509
1510 return exitMBB;
1511}
1512
1513MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1514 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1515 unsigned SrcReg) const {
1516 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1517 const DebugLoc &DL = MI.getDebugLoc();
1518
1519 if (Subtarget.hasMips32r2() && Size == 1) {
1520 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1521 return BB;
1522 }
1523
1524 if (Subtarget.hasMips32r2() && Size == 2) {
1525 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1526 return BB;
1527 }
1528
1529 MachineFunction *MF = BB->getParent();
1530 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1531 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1532 unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1533
1534 assert(Size < 32)(static_cast <bool> (Size < 32) ? void (0) : __assert_fail
("Size < 32", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1534, __extension__ __PRETTY_FUNCTION__))
;
1535 int64_t ShiftImm = 32 - (Size * 8);
1536
1537 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1538 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1539
1540 return BB;
1541}
1542
1543MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1544 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1545 bool Nand) const {
1546 assert((Size == 1 || Size == 2) &&(static_cast <bool> ((Size == 1 || Size == 2) &&
"Unsupported size for EmitAtomicBinaryPartial.") ? void (0) :
__assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1547, __extension__ __PRETTY_FUNCTION__))
1547 "Unsupported size for EmitAtomicBinaryPartial.")(static_cast <bool> ((Size == 1 || Size == 2) &&
"Unsupported size for EmitAtomicBinaryPartial.") ? void (0) :
__assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicBinaryPartial.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1547, __extension__ __PRETTY_FUNCTION__))
;
1548
1549 MachineFunction *MF = BB->getParent();
1550 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1551 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1552 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1553 const TargetRegisterClass *RCp =
1554 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1555 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1556 DebugLoc DL = MI.getDebugLoc();
1557
1558 unsigned Dest = MI.getOperand(0).getReg();
1559 unsigned Ptr = MI.getOperand(1).getReg();
1560 unsigned Incr = MI.getOperand(2).getReg();
1561
1562 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1563 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1564 unsigned Mask = RegInfo.createVirtualRegister(RC);
1565 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1566 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1567 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1568 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1569 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1570 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1571 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1572 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1573 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1574 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1575 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1576 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1577 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1578 unsigned Success = RegInfo.createVirtualRegister(RC);
1579
1580 unsigned LL, SC;
1581 if (isMicroMips) {
1582 LL = Mips::LL_MM;
1583 SC = Mips::SC_MM;
1584 } else {
1585 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1586 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1587 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1588 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1589 }
1590
1591 // insert new blocks after the current block
1592 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1593 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1594 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1595 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1596 MachineFunction::iterator It = ++BB->getIterator();
1597 MF->insert(It, loopMBB);
1598 MF->insert(It, sinkMBB);
1599 MF->insert(It, exitMBB);
1600
1601 // Transfer the remainder of BB and its successor edges to exitMBB.
1602 exitMBB->splice(exitMBB->begin(), BB,
1603 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1604 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1605
1606 BB->addSuccessor(loopMBB);
1607 loopMBB->addSuccessor(loopMBB);
1608 loopMBB->addSuccessor(sinkMBB);
1609 sinkMBB->addSuccessor(exitMBB);
1610
1611 // thisMBB:
1612 // addiu masklsb2,$0,-4 # 0xfffffffc
1613 // and alignedaddr,ptr,masklsb2
1614 // andi ptrlsb2,ptr,3
1615 // sll shiftamt,ptrlsb2,3
1616 // ori maskupper,$0,255 # 0xff
1617 // sll mask,maskupper,shiftamt
1618 // nor mask2,$0,mask
1619 // sll incr2,incr,shiftamt
1620
1621 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1622 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1623 .addReg(ABI.GetNullPtr()).addImm(-4);
1624 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1625 .addReg(Ptr).addReg(MaskLSB2);
1626 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1627 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1628 if (Subtarget.isLittle()) {
1629 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1630 } else {
1631 unsigned Off = RegInfo.createVirtualRegister(RC);
1632 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1633 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1634 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1635 }
1636 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1637 .addReg(Mips::ZERO).addImm(MaskImm);
1638 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1639 .addReg(MaskUpper).addReg(ShiftAmt);
1640 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1641 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1642
1643 // atomic.load.binop
1644 // loopMBB:
1645 // ll oldval,0(alignedaddr)
1646 // binop binopres,oldval,incr2
1647 // and newval,binopres,mask
1648 // and maskedoldval0,oldval,mask2
1649 // or storeval,maskedoldval0,newval
1650 // sc success,storeval,0(alignedaddr)
1651 // beq success,$0,loopMBB
1652
1653 // atomic.swap
1654 // loopMBB:
1655 // ll oldval,0(alignedaddr)
1656 // and newval,incr2,mask
1657 // and maskedoldval0,oldval,mask2
1658 // or storeval,maskedoldval0,newval
1659 // sc success,storeval,0(alignedaddr)
1660 // beq success,$0,loopMBB
1661
1662 BB = loopMBB;
1663 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1664 if (Nand) {
1665 // and andres, oldval, incr2
1666 // nor binopres, $0, andres
1667 // and newval, binopres, mask
1668 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1669 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1670 .addReg(Mips::ZERO).addReg(AndRes);
1671 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1672 } else if (BinOpcode) {
1673 // <binop> binopres, oldval, incr2
1674 // and newval, binopres, mask
1675 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1676 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1677 } else { // atomic.swap
1678 // and newval, incr2, mask
1679 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1680 }
1681
1682 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1683 .addReg(OldVal).addReg(Mask2);
1684 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1685 .addReg(MaskedOldVal0).addReg(NewVal);
1686 BuildMI(BB, DL, TII->get(SC), Success)
1687 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1688 BuildMI(BB, DL, TII->get(Mips::BEQ))
1689 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1690
1691 // sinkMBB:
1692 // and maskedoldval1,oldval,mask
1693 // srl srlres,maskedoldval1,shiftamt
1694 // sign_extend dest,srlres
1695 BB = sinkMBB;
1696
1697 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1698 .addReg(OldVal).addReg(Mask);
1699 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1700 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1701 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
Value stored to 'BB' is never read
1702
1703 MI.eraseFromParent(); // The instruction is gone now.
1704
1705 return exitMBB;
1706}
1707
1708MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1709 MachineBasicBlock *BB,
1710 unsigned Size) const {
1711 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.")(static_cast <bool> ((Size == 4 || Size == 8) &&
"Unsupported size for EmitAtomicCmpSwap.") ? void (0) : __assert_fail
("(Size == 4 || Size == 8) && \"Unsupported size for EmitAtomicCmpSwap.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1711, __extension__ __PRETTY_FUNCTION__))
;
1712
1713 MachineFunction *MF = BB->getParent();
1714 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1715 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1716 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1717 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1718 DebugLoc DL = MI.getDebugLoc();
1719 unsigned LL, SC, ZERO, BNE, BEQ;
1720
1721 if (Size == 4) {
1722 if (isMicroMips) {
1723 LL = Mips::LL_MM;
1724 SC = Mips::SC_MM;
1725 } else {
1726 LL = Subtarget.hasMips32r6()
1727 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1728 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1729 SC = Subtarget.hasMips32r6()
1730 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1731 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1732 }
1733
1734 ZERO = Mips::ZERO;
1735 BNE = Mips::BNE;
1736 BEQ = Mips::BEQ;
1737 } else {
1738 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1739 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1740 ZERO = Mips::ZERO_64;
1741 BNE = Mips::BNE64;
1742 BEQ = Mips::BEQ64;
1743 }
1744
1745 unsigned Dest = MI.getOperand(0).getReg();
1746 unsigned Ptr = MI.getOperand(1).getReg();
1747 unsigned OldVal = MI.getOperand(2).getReg();
1748 unsigned NewVal = MI.getOperand(3).getReg();
1749
1750 unsigned Success = RegInfo.createVirtualRegister(RC);
1751
1752 // insert new blocks after the current block
1753 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1754 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1755 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1756 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1757 MachineFunction::iterator It = ++BB->getIterator();
1758 MF->insert(It, loop1MBB);
1759 MF->insert(It, loop2MBB);
1760 MF->insert(It, exitMBB);
1761
1762 // Transfer the remainder of BB and its successor edges to exitMBB.
1763 exitMBB->splice(exitMBB->begin(), BB,
1764 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1765 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1766
1767 // thisMBB:
1768 // ...
1769 // fallthrough --> loop1MBB
1770 BB->addSuccessor(loop1MBB);
1771 loop1MBB->addSuccessor(exitMBB);
1772 loop1MBB->addSuccessor(loop2MBB);
1773 loop2MBB->addSuccessor(loop1MBB);
1774 loop2MBB->addSuccessor(exitMBB);
1775
1776 // loop1MBB:
1777 // ll dest, 0(ptr)
1778 // bne dest, oldval, exitMBB
1779 BB = loop1MBB;
1780 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1781 BuildMI(BB, DL, TII->get(BNE))
1782 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1783
1784 // loop2MBB:
1785 // sc success, newval, 0(ptr)
1786 // beq success, $0, loop1MBB
1787 BB = loop2MBB;
1788 BuildMI(BB, DL, TII->get(SC), Success)
1789 .addReg(NewVal).addReg(Ptr).addImm(0);
1790 BuildMI(BB, DL, TII->get(BEQ))
1791 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1792
1793 MI.eraseFromParent(); // The instruction is gone now.
1794
1795 return exitMBB;
1796}
1797
1798MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1799 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1800 assert((Size == 1 || Size == 2) &&(static_cast <bool> ((Size == 1 || Size == 2) &&
"Unsupported size for EmitAtomicCmpSwapPartial.") ? void (0)
: __assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1801, __extension__ __PRETTY_FUNCTION__))
1801 "Unsupported size for EmitAtomicCmpSwapPartial.")(static_cast <bool> ((Size == 1 || Size == 2) &&
"Unsupported size for EmitAtomicCmpSwapPartial.") ? void (0)
: __assert_fail ("(Size == 1 || Size == 2) && \"Unsupported size for EmitAtomicCmpSwapPartial.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1801, __extension__ __PRETTY_FUNCTION__))
;
1802
1803 MachineFunction *MF = BB->getParent();
1804 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1805 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1806 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1807 const TargetRegisterClass *RCp =
1808 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1809 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1810 DebugLoc DL = MI.getDebugLoc();
1811
1812 unsigned Dest = MI.getOperand(0).getReg();
1813 unsigned Ptr = MI.getOperand(1).getReg();
1814 unsigned CmpVal = MI.getOperand(2).getReg();
1815 unsigned NewVal = MI.getOperand(3).getReg();
1816
1817 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp);
1818 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1819 unsigned Mask = RegInfo.createVirtualRegister(RC);
1820 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1821 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1822 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1823 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1824 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1825 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1826 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1827 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1828 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1829 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1830 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1831 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1832 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1833 unsigned Success = RegInfo.createVirtualRegister(RC);
1834 unsigned LL, SC;
1835
1836 if (isMicroMips) {
1837 LL = Mips::LL_MM;
1838 SC = Mips::SC_MM;
1839 } else {
1840 LL = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
1841 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
1842 SC = Subtarget.hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
1843 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
1844 }
1845
1846 // insert new blocks after the current block
1847 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1848 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1849 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1850 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1851 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1852 MachineFunction::iterator It = ++BB->getIterator();
1853 MF->insert(It, loop1MBB);
1854 MF->insert(It, loop2MBB);
1855 MF->insert(It, sinkMBB);
1856 MF->insert(It, exitMBB);
1857
1858 // Transfer the remainder of BB and its successor edges to exitMBB.
1859 exitMBB->splice(exitMBB->begin(), BB,
1860 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1861 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1862
1863 BB->addSuccessor(loop1MBB);
1864 loop1MBB->addSuccessor(sinkMBB);
1865 loop1MBB->addSuccessor(loop2MBB);
1866 loop2MBB->addSuccessor(loop1MBB);
1867 loop2MBB->addSuccessor(sinkMBB);
1868 sinkMBB->addSuccessor(exitMBB);
1869
1870 // FIXME: computation of newval2 can be moved to loop2MBB.
1871 // thisMBB:
1872 // addiu masklsb2,$0,-4 # 0xfffffffc
1873 // and alignedaddr,ptr,masklsb2
1874 // andi ptrlsb2,ptr,3
1875 // xori ptrlsb2,ptrlsb2,3 # Only for BE
1876 // sll shiftamt,ptrlsb2,3
1877 // ori maskupper,$0,255 # 0xff
1878 // sll mask,maskupper,shiftamt
1879 // nor mask2,$0,mask
1880 // andi maskedcmpval,cmpval,255
1881 // sll shiftedcmpval,maskedcmpval,shiftamt
1882 // andi maskednewval,newval,255
1883 // sll shiftednewval,maskednewval,shiftamt
1884 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1885 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1886 .addReg(ABI.GetNullPtr()).addImm(-4);
1887 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1888 .addReg(Ptr).addReg(MaskLSB2);
1889 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1890 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1891 if (Subtarget.isLittle()) {
1892 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1893 } else {
1894 unsigned Off = RegInfo.createVirtualRegister(RC);
1895 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1896 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1897 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1898 }
1899 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1900 .addReg(Mips::ZERO).addImm(MaskImm);
1901 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1902 .addReg(MaskUpper).addReg(ShiftAmt);
1903 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1904 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1905 .addReg(CmpVal).addImm(MaskImm);
1906 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1907 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1908 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1909 .addReg(NewVal).addImm(MaskImm);
1910 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1911 .addReg(MaskedNewVal).addReg(ShiftAmt);
1912
1913 // loop1MBB:
1914 // ll oldval,0(alginedaddr)
1915 // and maskedoldval0,oldval,mask
1916 // bne maskedoldval0,shiftedcmpval,sinkMBB
1917 BB = loop1MBB;
1918 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1919 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1920 .addReg(OldVal).addReg(Mask);
1921 BuildMI(BB, DL, TII->get(Mips::BNE))
1922 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1923
1924 // loop2MBB:
1925 // and maskedoldval1,oldval,mask2
1926 // or storeval,maskedoldval1,shiftednewval
1927 // sc success,storeval,0(alignedaddr)
1928 // beq success,$0,loop1MBB
1929 BB = loop2MBB;
1930 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1931 .addReg(OldVal).addReg(Mask2);
1932 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1933 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1934 BuildMI(BB, DL, TII->get(SC), Success)
1935 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1936 BuildMI(BB, DL, TII->get(Mips::BEQ))
1937 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1938
1939 // sinkMBB:
1940 // srl srlres,maskedoldval0,shiftamt
1941 // sign_extend dest,srlres
1942 BB = sinkMBB;
1943
1944 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1945 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1946 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1947
1948 MI.eraseFromParent(); // The instruction is gone now.
1949
1950 return exitMBB;
1951}
1952
1953SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1954 // The first operand is the chain, the second is the condition, the third is
1955 // the block to branch to if the condition is true.
1956 SDValue Chain = Op.getOperand(0);
1957 SDValue Dest = Op.getOperand(2);
1958 SDLoc DL(Op);
1959
1960 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())(static_cast <bool> (!Subtarget.hasMips32r6() &&
!Subtarget.hasMips64r6()) ? void (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1960, __extension__ __PRETTY_FUNCTION__))
;
1961 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1962
1963 // Return if flag is not set by a floating point comparison.
1964 if (CondRes.getOpcode() != MipsISD::FPCmp)
1965 return Op;
1966
1967 SDValue CCNode = CondRes.getOperand(2);
1968 Mips::CondCode CC =
1969 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1970 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1971 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1972 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1973 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1974 FCC0, Dest, CondRes);
1975}
1976
1977SDValue MipsTargetLowering::
1978lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1979{
1980 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())(static_cast <bool> (!Subtarget.hasMips32r6() &&
!Subtarget.hasMips64r6()) ? void (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1980, __extension__ __PRETTY_FUNCTION__))
;
1981 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1982
1983 // Return if flag is not set by a floating point comparison.
1984 if (Cond.getOpcode() != MipsISD::FPCmp)
1985 return Op;
1986
1987 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1988 SDLoc(Op));
1989}
1990
1991SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1992 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6())(static_cast <bool> (!Subtarget.hasMips32r6() &&
!Subtarget.hasMips64r6()) ? void (0) : __assert_fail ("!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1992, __extension__ __PRETTY_FUNCTION__))
;
1993 SDValue Cond = createFPCmp(DAG, Op);
1994
1995 assert(Cond.getOpcode() == MipsISD::FPCmp &&(static_cast <bool> (Cond.getOpcode() == MipsISD::FPCmp
&& "Floating point operand expected.") ? void (0) : __assert_fail
("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1996, __extension__ __PRETTY_FUNCTION__))
1996 "Floating point operand expected.")(static_cast <bool> (Cond.getOpcode() == MipsISD::FPCmp
&& "Floating point operand expected.") ? void (0) : __assert_fail
("Cond.getOpcode() == MipsISD::FPCmp && \"Floating point operand expected.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 1996, __extension__ __PRETTY_FUNCTION__))
;
1997
1998 SDLoc DL(Op);
1999 SDValue True = DAG.getConstant(1, DL, MVT::i32);
2000 SDValue False = DAG.getConstant(0, DL, MVT::i32);
2001
2002 return createCMovFP(DAG, Cond, True, False, DL);
2003}
2004
2005SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
2006 SelectionDAG &DAG) const {
2007 EVT Ty = Op.getValueType();
2008 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
2009 const GlobalValue *GV = N->getGlobal();
2010
2011 if (!isPositionIndependent()) {
2012 const MipsTargetObjectFile *TLOF =
2013 static_cast<const MipsTargetObjectFile *>(
2014 getTargetMachine().getObjFileLowering());
2015 const GlobalObject *GO = GV->getBaseObject();
2016 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
2017 // %gp_rel relocation
2018 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2019
2020 // %hi/%lo relocation
2021 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2022 // %highest/%higher/%hi/%lo relocation
2023 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2024 }
2025
2026 // Every other architecture would use shouldAssumeDSOLocal in here, but
2027 // mips is special.
2028 // * In PIC code mips requires got loads even for local statics!
2029 // * To save on got entries, for local statics the got entry contains the
2030 // page and an additional add instruction takes care of the low bits.
2031 // * It is legal to access a hidden symbol with a non hidden undefined,
2032 // so one cannot guarantee that all access to a hidden symbol will know
2033 // it is hidden.
2034 // * Mips linkers don't support creating a page and a full got entry for
2035 // the same symbol.
2036 // * Given all that, we have to use a full got entry for hidden symbols :-(
2037 if (GV->hasLocalLinkage())
2038 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2039
2040 if (LargeGOT)
2041 return getAddrGlobalLargeGOT(
2042 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
2043 DAG.getEntryNode(),
2044 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2045
2046 return getAddrGlobal(
2047 N, SDLoc(N), Ty, DAG,
2048 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
2049 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2050}
2051
2052SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2053 SelectionDAG &DAG) const {
2054 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2055 EVT Ty = Op.getValueType();
2056
2057 if (!isPositionIndependent())
2058 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2059 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2060
2061 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2062}
2063
2064SDValue MipsTargetLowering::
2065lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2066{
2067 // If the relocation model is PIC, use the General Dynamic TLS Model or
2068 // Local Dynamic TLS model, otherwise use the Initial Exec or
2069 // Local Exec TLS Model.
2070
2071 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2072 if (DAG.getTarget().useEmulatedTLS())
2073 return LowerToTLSEmulatedModel(GA, DAG);
2074
2075 SDLoc DL(GA);
2076 const GlobalValue *GV = GA->getGlobal();
2077 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2078
2079 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2080
2081 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2082 // General Dynamic and Local Dynamic TLS Model.
2083 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2084 : MipsII::MO_TLSGD;
2085
2086 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2087 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2088 getGlobalReg(DAG, PtrVT), TGA);
2089 unsigned PtrSize = PtrVT.getSizeInBits();
2090 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2091
2092 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2093
2094 ArgListTy Args;
2095 ArgListEntry Entry;
2096 Entry.Node = Argument;
2097 Entry.Ty = PtrTy;
2098 Args.push_back(Entry);
2099
2100 TargetLowering::CallLoweringInfo CLI(DAG);
2101 CLI.setDebugLoc(DL)
2102 .setChain(DAG.getEntryNode())
2103 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2104 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2105
2106 SDValue Ret = CallResult.first;
2107
2108 if (model != TLSModel::LocalDynamic)
2109 return Ret;
2110
2111 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2112 MipsII::MO_DTPREL_HI);
2113 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2114 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2115 MipsII::MO_DTPREL_LO);
2116 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2117 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2118 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2119 }
2120
2121 SDValue Offset;
2122 if (model == TLSModel::InitialExec) {
2123 // Initial Exec TLS Model
2124 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2125 MipsII::MO_GOTTPREL);
2126 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2127 TGA);
2128 Offset =
2129 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2130 } else {
2131 // Local Exec TLS Model
2132 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2132, __extension__ __PRETTY_FUNCTION__))
;
2133 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2134 MipsII::MO_TPREL_HI);
2135 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2136 MipsII::MO_TPREL_LO);
2137 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
2138 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2139 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2140 }
2141
2142 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2143 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2144}
2145
2146SDValue MipsTargetLowering::
2147lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2148{
2149 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2150 EVT Ty = Op.getValueType();
2151
2152 if (!isPositionIndependent())
2153 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2154 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2155
2156 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2157}
2158
2159SDValue MipsTargetLowering::
2160lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2161{
2162 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2163 EVT Ty = Op.getValueType();
2164
2165 if (!isPositionIndependent()) {
2166 const MipsTargetObjectFile *TLOF =
2167 static_cast<const MipsTargetObjectFile *>(
2168 getTargetMachine().getObjFileLowering());
2169
2170 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2171 getTargetMachine()))
2172 // %gp_rel relocation
2173 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2174
2175 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2176 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2177 }
2178
2179 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2180}
2181
2182SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2183 MachineFunction &MF = DAG.getMachineFunction();
2184 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2185
2186 SDLoc DL(Op);
2187 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2188 getPointerTy(MF.getDataLayout()));
2189
2190 // vastart just stores the address of the VarArgsFrameIndex slot into the
2191 // memory location argument.
2192 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2193 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2194 MachinePointerInfo(SV));
2195}
2196
2197SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2198 SDNode *Node = Op.getNode();
2199 EVT VT = Node->getValueType(0);
2200 SDValue Chain = Node->getOperand(0);
2201 SDValue VAListPtr = Node->getOperand(1);
2202 unsigned Align = Node->getConstantOperandVal(3);
2203 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2204 SDLoc DL(Node);
2205 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2206
2207 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2208 VAListPtr, MachinePointerInfo(SV));
2209 SDValue VAList = VAListLoad;
2210
2211 // Re-align the pointer if necessary.
2212 // It should only ever be necessary for 64-bit types on O32 since the minimum
2213 // argument alignment is the same as the maximum type alignment for N32/N64.
2214 //
2215 // FIXME: We currently align too often. The code generator doesn't notice
2216 // when the pointer is still aligned from the last va_arg (or pair of
2217 // va_args for the i64 on O32 case).
2218 if (Align > getMinStackArgumentAlignment()) {
2219 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2")(static_cast <bool> (((Align & (Align-1)) == 0) &&
"Expected Align to be a power of 2") ? void (0) : __assert_fail
("((Align & (Align-1)) == 0) && \"Expected Align to be a power of 2\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2219, __extension__ __PRETTY_FUNCTION__))
;
2220
2221 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2222 DAG.getConstant(Align - 1, DL, VAList.getValueType()));
2223
2224 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
2225 DAG.getConstant(-(int64_t)Align, DL,
2226 VAList.getValueType()));
2227 }
2228
2229 // Increment the pointer, VAList, to the next vaarg.
2230 auto &TD = DAG.getDataLayout();
2231 unsigned ArgSizeInBytes =
2232 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2233 SDValue Tmp3 =
2234 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2235 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2236 DL, VAList.getValueType()));
2237 // Store the incremented VAList to the legalized pointer
2238 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2239 MachinePointerInfo(SV));
2240
2241 // In big-endian mode we must adjust the pointer when the load size is smaller
2242 // than the argument slot size. We must also reduce the known alignment to
2243 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2244 // the correct half of the slot, and reduce the alignment from 8 (slot
2245 // alignment) down to 4 (type alignment).
2246 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2247 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2248 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2249 DAG.getIntPtrConstant(Adjustment, DL));
2250 }
2251 // Load the actual argument out of the pointer VAList
2252 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2253}
2254
2255static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
2256 bool HasExtractInsert) {
2257 EVT TyX = Op.getOperand(0).getValueType();
2258 EVT TyY = Op.getOperand(1).getValueType();
2259 SDLoc DL(Op);
2260 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2261 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2262 SDValue Res;
2263
2264 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2265 // to i32.
2266 SDValue X = (TyX == MVT::f32) ?
2267 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2268 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2269 Const1);
2270 SDValue Y = (TyY == MVT::f32) ?
2271 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2272 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2273 Const1);
2274
2275 if (HasExtractInsert) {
2276 // ext E, Y, 31, 1 ; extract bit31 of Y
2277 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2278 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2279 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2280 } else {
2281 // sll SllX, X, 1
2282 // srl SrlX, SllX, 1
2283 // srl SrlY, Y, 31
2284 // sll SllY, SrlX, 31
2285 // or Or, SrlX, SllY
2286 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2287 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2288 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2289 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2290 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2291 }
2292
2293 if (TyX == MVT::f32)
2294 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2295
2296 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2297 Op.getOperand(0),
2298 DAG.getConstant(0, DL, MVT::i32));
2299 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2300}
2301
2302static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2303 bool HasExtractInsert) {
2304 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2305 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2306 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2307 SDLoc DL(Op);
2308 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2309
2310 // Bitcast to integer nodes.
2311 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2312 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2313
2314 if (HasExtractInsert) {
2315 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2316 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2317 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2318 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2319
2320 if (WidthX > WidthY)
2321 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2322 else if (WidthY > WidthX)
2323 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2324
2325 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2326 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2327 X);
2328 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2329 }
2330
2331 // (d)sll SllX, X, 1
2332 // (d)srl SrlX, SllX, 1
2333 // (d)srl SrlY, Y, width(Y)-1
2334 // (d)sll SllY, SrlX, width(Y)-1
2335 // or Or, SrlX, SllY
2336 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2337 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2338 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2339 DAG.getConstant(WidthY - 1, DL, MVT::i32));
2340
2341 if (WidthX > WidthY)
2342 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2343 else if (WidthY > WidthX)
2344 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2345
2346 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2347 DAG.getConstant(WidthX - 1, DL, MVT::i32));
2348 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2349 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2350}
2351
2352SDValue
2353MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2354 if (Subtarget.isGP64bit())
2355 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2356
2357 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2358}
2359
2360SDValue MipsTargetLowering::
2361lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2362 // check the depth
2363 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(static_cast <bool> ((cast<ConstantSDNode>(Op.getOperand
(0))->getZExtValue() == 0) && "Frame address can only be determined for current frame."
) ? void (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2364, __extension__ __PRETTY_FUNCTION__))
2364 "Frame address can only be determined for current frame.")(static_cast <bool> ((cast<ConstantSDNode>(Op.getOperand
(0))->getZExtValue() == 0) && "Frame address can only be determined for current frame."
) ? void (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Frame address can only be determined for current frame.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2364, __extension__ __PRETTY_FUNCTION__))
;
2365
2366 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2367 MFI.setFrameAddressIsTaken(true);
2368 EVT VT = Op.getValueType();
2369 SDLoc DL(Op);
2370 SDValue FrameAddr = DAG.getCopyFromReg(
2371 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2372 return FrameAddr;
2373}
2374
2375SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2376 SelectionDAG &DAG) const {
2377 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2378 return SDValue();
2379
2380 // check the depth
2381 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&(static_cast <bool> ((cast<ConstantSDNode>(Op.getOperand
(0))->getZExtValue() == 0) && "Return address can be determined only for current frame."
) ? void (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2382, __extension__ __PRETTY_FUNCTION__))
2382 "Return address can be determined only for current frame.")(static_cast <bool> ((cast<ConstantSDNode>(Op.getOperand
(0))->getZExtValue() == 0) && "Return address can be determined only for current frame."
) ? void (0) : __assert_fail ("(cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && \"Return address can be determined only for current frame.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2382, __extension__ __PRETTY_FUNCTION__))
;
2383
2384 MachineFunction &MF = DAG.getMachineFunction();
2385 MachineFrameInfo &MFI = MF.getFrameInfo();
2386 MVT VT = Op.getSimpleValueType();
2387 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2388 MFI.setReturnAddressIsTaken(true);
2389
2390 // Return RA, which contains the return address. Mark it an implicit live-in.
2391 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2392 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2393}
2394
2395// An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2396// generated from __builtin_eh_return (offset, handler)
2397// The effect of this is to adjust the stack pointer by "offset"
2398// and then branch to "handler".
2399SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2400 const {
2401 MachineFunction &MF = DAG.getMachineFunction();
2402 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2403
2404 MipsFI->setCallsEhReturn();
2405 SDValue Chain = Op.getOperand(0);
2406 SDValue Offset = Op.getOperand(1);
2407 SDValue Handler = Op.getOperand(2);
2408 SDLoc DL(Op);
2409 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2410
2411 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2412 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2413 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2414 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2415 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2416 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2417 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2418 DAG.getRegister(OffsetReg, Ty),
2419 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2420 Chain.getValue(1));
2421}
2422
2423SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2424 SelectionDAG &DAG) const {
2425 // FIXME: Need pseudo-fence for 'singlethread' fences
2426 // FIXME: Set SType for weaker fences where supported/appropriate.
2427 unsigned SType = 0;
2428 SDLoc DL(Op);
2429 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2430 DAG.getConstant(SType, DL, MVT::i32));
2431}
2432
2433SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2434 SelectionDAG &DAG) const {
2435 SDLoc DL(Op);
2436 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2437
2438 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2439 SDValue Shamt = Op.getOperand(2);
2440 // if shamt < (VT.bits):
2441 // lo = (shl lo, shamt)
2442 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2443 // else:
2444 // lo = 0
2445 // hi = (shl lo, shamt[4:0])
2446 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2447 DAG.getConstant(-1, DL, MVT::i32));
2448 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2449 DAG.getConstant(1, DL, VT));
2450 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2451 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2452 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2453 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2454 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2455 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2456 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2457 DAG.getConstant(0, DL, VT), ShiftLeftLo);
2458 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2459
2460 SDValue Ops[2] = {Lo, Hi};
2461 return DAG.getMergeValues(Ops, DL);
2462}
2463
2464SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2465 bool IsSRA) const {
2466 SDLoc DL(Op);
2467 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2468 SDValue Shamt = Op.getOperand(2);
2469 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2470
2471 // if shamt < (VT.bits):
2472 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2473 // if isSRA:
2474 // hi = (sra hi, shamt)
2475 // else:
2476 // hi = (srl hi, shamt)
2477 // else:
2478 // if isSRA:
2479 // lo = (sra hi, shamt[4:0])
2480 // hi = (sra hi, 31)
2481 // else:
2482 // lo = (srl hi, shamt[4:0])
2483 // hi = 0
2484 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2485 DAG.getConstant(-1, DL, MVT::i32));
2486 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2487 DAG.getConstant(1, DL, VT));
2488 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2489 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2490 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2491 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2492 DL, VT, Hi, Shamt);
2493 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2494 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2495 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2496 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2497 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2498 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2499 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2500
2501 SDValue Ops[2] = {Lo, Hi};
2502 return DAG.getMergeValues(Ops, DL);
2503}
2504
2505static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2506 SDValue Chain, SDValue Src, unsigned Offset) {
2507 SDValue Ptr = LD->getBasePtr();
2508 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2509 EVT BasePtrVT = Ptr.getValueType();
2510 SDLoc DL(LD);
2511 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2512
2513 if (Offset)
2514 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2515 DAG.getConstant(Offset, DL, BasePtrVT));
2516
2517 SDValue Ops[] = { Chain, Ptr, Src };
2518 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2519 LD->getMemOperand());
2520}
2521
2522// Expand an unaligned 32 or 64-bit integer load node.
2523SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2524 LoadSDNode *LD = cast<LoadSDNode>(Op);
2525 EVT MemVT = LD->getMemoryVT();
2526
2527 if (Subtarget.systemSupportsUnalignedAccess())
2528 return Op;
2529
2530 // Return if load is aligned or if MemVT is neither i32 nor i64.
2531 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2532 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2533 return SDValue();
2534
2535 bool IsLittle = Subtarget.isLittle();
2536 EVT VT = Op.getValueType();
2537 ISD::LoadExtType ExtType = LD->getExtensionType();
2538 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2539
2540 assert((VT == MVT::i32) || (VT == MVT::i64))(static_cast <bool> ((VT == MVT::i32) || (VT == MVT::i64
)) ? void (0) : __assert_fail ("(VT == MVT::i32) || (VT == MVT::i64)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2540, __extension__ __PRETTY_FUNCTION__))
;
2541
2542 // Expand
2543 // (set dst, (i64 (load baseptr)))
2544 // to
2545 // (set tmp, (ldl (add baseptr, 7), undef))
2546 // (set dst, (ldr baseptr, tmp))
2547 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2548 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2549 IsLittle ? 7 : 0);
2550 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2551 IsLittle ? 0 : 7);
2552 }
2553
2554 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2555 IsLittle ? 3 : 0);
2556 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2557 IsLittle ? 0 : 3);
2558
2559 // Expand
2560 // (set dst, (i32 (load baseptr))) or
2561 // (set dst, (i64 (sextload baseptr))) or
2562 // (set dst, (i64 (extload baseptr)))
2563 // to
2564 // (set tmp, (lwl (add baseptr, 3), undef))
2565 // (set dst, (lwr baseptr, tmp))
2566 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2567 (ExtType == ISD::EXTLOAD))
2568 return LWR;
2569
2570 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD))(static_cast <bool> ((VT == MVT::i64) && (ExtType
== ISD::ZEXTLOAD)) ? void (0) : __assert_fail ("(VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2570, __extension__ __PRETTY_FUNCTION__))
;
2571
2572 // Expand
2573 // (set dst, (i64 (zextload baseptr)))
2574 // to
2575 // (set tmp0, (lwl (add baseptr, 3), undef))
2576 // (set tmp1, (lwr baseptr, tmp0))
2577 // (set tmp2, (shl tmp1, 32))
2578 // (set dst, (srl tmp2, 32))
2579 SDLoc DL(LD);
2580 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2581 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2582 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2583 SDValue Ops[] = { SRL, LWR.getValue(1) };
2584 return DAG.getMergeValues(Ops, DL);
2585}
2586
2587static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2588 SDValue Chain, unsigned Offset) {
2589 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2590 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2591 SDLoc DL(SD);
2592 SDVTList VTList = DAG.getVTList(MVT::Other);
2593
2594 if (Offset)
2595 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2596 DAG.getConstant(Offset, DL, BasePtrVT));
2597
2598 SDValue Ops[] = { Chain, Value, Ptr };
2599 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2600 SD->getMemOperand());
2601}
2602
2603// Expand an unaligned 32 or 64-bit integer store node.
2604static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2605 bool IsLittle) {
2606 SDValue Value = SD->getValue(), Chain = SD->getChain();
2607 EVT VT = Value.getValueType();
2608
2609 // Expand
2610 // (store val, baseptr) or
2611 // (truncstore val, baseptr)
2612 // to
2613 // (swl val, (add baseptr, 3))
2614 // (swr val, baseptr)
2615 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2616 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2617 IsLittle ? 3 : 0);
2618 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2619 }
2620
2621 assert(VT == MVT::i64)(static_cast <bool> (VT == MVT::i64) ? void (0) : __assert_fail
("VT == MVT::i64", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2621, __extension__ __PRETTY_FUNCTION__))
;
2622
2623 // Expand
2624 // (store val, baseptr)
2625 // to
2626 // (sdl val, (add baseptr, 7))
2627 // (sdr val, baseptr)
2628 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2629 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2630}
2631
2632// Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2633static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2634 SDValue Val = SD->getValue();
2635
2636 if (Val.getOpcode() != ISD::FP_TO_SINT)
2637 return SDValue();
2638
2639 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2640 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2641 Val.getOperand(0));
2642 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2643 SD->getPointerInfo(), SD->getAlignment(),
2644 SD->getMemOperand()->getFlags());
2645}
2646
2647SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2648 StoreSDNode *SD = cast<StoreSDNode>(Op);
2649 EVT MemVT = SD->getMemoryVT();
2650
2651 // Lower unaligned integer stores.
2652 if (!Subtarget.systemSupportsUnalignedAccess() &&
2653 (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2654 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2655 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2656
2657 return lowerFP_TO_SINT_STORE(SD, DAG);
2658}
2659
2660SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2661 SelectionDAG &DAG) const {
2662
2663 // Return a fixed StackObject with offset 0 which points to the old stack
2664 // pointer.
2665 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2666 EVT ValTy = Op->getValueType(0);
2667 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2668 return DAG.getFrameIndex(FI, ValTy);
2669}
2670
2671SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2672 SelectionDAG &DAG) const {
2673 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2674 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2675 Op.getOperand(0));
2676 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2677}
2678
2679//===----------------------------------------------------------------------===//
2680// Calling Convention Implementation
2681//===----------------------------------------------------------------------===//
2682
2683//===----------------------------------------------------------------------===//
2684// TODO: Implement a generic logic using tblgen that can support this.
2685// Mips O32 ABI rules:
2686// ---
2687// i32 - Passed in A0, A1, A2, A3 and stack
2688// f32 - Only passed in f32 registers if no int reg has been used yet to hold
2689// an argument. Otherwise, passed in A1, A2, A3 and stack.
2690// f64 - Only passed in two aliased f32 registers if no int reg has been used
2691// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2692// not used, it must be shadowed. If only A3 is available, shadow it and
2693// go to stack.
2694// vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2695// vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2696// with the remainder spilled to the stack.
2697// vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2698// spilling the remainder to the stack.
2699//
2700// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2701//===----------------------------------------------------------------------===//
2702
2703static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2704 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2705 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2706 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2707 State.getMachineFunction().getSubtarget());
2708
2709 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2710
2711 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2712
2713 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2714
2715 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2716
2717 // Do not process byval args here.
2718 if (ArgFlags.isByVal())
2719 return true;
2720
2721 // Promote i8 and i16
2722 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2723 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2724 LocVT = MVT::i32;
2725 if (ArgFlags.isSExt())
2726 LocInfo = CCValAssign::SExtUpper;
2727 else if (ArgFlags.isZExt())
2728 LocInfo = CCValAssign::ZExtUpper;
2729 else
2730 LocInfo = CCValAssign::AExtUpper;
2731 }
2732 }
2733
2734 // Promote i8 and i16
2735 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2736 LocVT = MVT::i32;
2737 if (ArgFlags.isSExt())
2738 LocInfo = CCValAssign::SExt;
2739 else if (ArgFlags.isZExt())
2740 LocInfo = CCValAssign::ZExt;
2741 else
2742 LocInfo = CCValAssign::AExt;
2743 }
2744
2745 unsigned Reg;
2746
2747 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2748 // is true: function is vararg, argument is 3rd or higher, there is previous
2749 // argument which is not f32 or f64.
2750 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2751 State.getFirstUnallocated(F32Regs) != ValNo;
2752 unsigned OrigAlign = ArgFlags.getOrigAlign();
2753 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2754 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2755
2756 // The MIPS vector ABI for floats passes them in a pair of registers
2757 if (ValVT == MVT::i32 && isVectorFloat) {
2758 // This is the start of an vector that was scalarized into an unknown number
2759 // of components. It doesn't matter how many there are. Allocate one of the
2760 // notional 8 byte aligned registers which map onto the argument stack, and
2761 // shadow the register lost to alignment requirements.
2762 if (ArgFlags.isSplit()) {
2763 Reg = State.AllocateReg(FloatVectorIntRegs);
2764 if (Reg == Mips::A2)
2765 State.AllocateReg(Mips::A1);
2766 else if (Reg == 0)
2767 State.AllocateReg(Mips::A3);
2768 } else {
2769 // If we're an intermediate component of the split, we can just attempt to
2770 // allocate a register directly.
2771 Reg = State.AllocateReg(IntRegs);
2772 }
2773 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2774 Reg = State.AllocateReg(IntRegs);
2775 // If this is the first part of an i64 arg,
2776 // the allocated register must be either A0 or A2.
2777 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2778 Reg = State.AllocateReg(IntRegs);
2779 LocVT = MVT::i32;
2780 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2781 // Allocate int register and shadow next int register. If first
2782 // available register is Mips::A1 or Mips::A3, shadow it too.
2783 Reg = State.AllocateReg(IntRegs);
2784 if (Reg == Mips::A1 || Reg == Mips::A3)
2785 Reg = State.AllocateReg(IntRegs);
2786 State.AllocateReg(IntRegs);
2787 LocVT = MVT::i32;
2788 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2789 // we are guaranteed to find an available float register
2790 if (ValVT == MVT::f32) {
2791 Reg = State.AllocateReg(F32Regs);
2792 // Shadow int register
2793 State.AllocateReg(IntRegs);
2794 } else {
2795 Reg = State.AllocateReg(F64Regs);
2796 // Shadow int registers
2797 unsigned Reg2 = State.AllocateReg(IntRegs);
2798 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2799 State.AllocateReg(IntRegs);
2800 State.AllocateReg(IntRegs);
2801 }
2802 } else
2803 llvm_unreachable("Cannot handle this ValVT.")::llvm::llvm_unreachable_internal("Cannot handle this ValVT."
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2803)
;
2804
2805 if (!Reg) {
2806 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
2807 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2808 } else
2809 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2810
2811 return false;
2812}
2813
2814static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2815 MVT LocVT, CCValAssign::LocInfo LocInfo,
2816 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2817 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2818
2819 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2820}
2821
2822static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2823 MVT LocVT, CCValAssign::LocInfo LocInfo,
2824 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2825 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2826
2827 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2828}
2829
2830static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2831 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2832 CCState &State) LLVM_ATTRIBUTE_UNUSED__attribute__((__unused__));
2833
2834#include "MipsGenCallingConv.inc"
2835
2836//===----------------------------------------------------------------------===//
2837// Call Calling Convention Implementation
2838//===----------------------------------------------------------------------===//
2839
2840// Return next O32 integer argument register.
2841static unsigned getNextIntArgReg(unsigned Reg) {
2842 assert((Reg == Mips::A0) || (Reg == Mips::A2))(static_cast <bool> ((Reg == Mips::A0) || (Reg == Mips::
A2)) ? void (0) : __assert_fail ("(Reg == Mips::A0) || (Reg == Mips::A2)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2842, __extension__ __PRETTY_FUNCTION__))
;
2843 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2844}
2845
2846SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2847 SDValue Chain, SDValue Arg,
2848 const SDLoc &DL, bool IsTailCall,
2849 SelectionDAG &DAG) const {
2850 if (!IsTailCall) {
2851 SDValue PtrOff =
2852 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2853 DAG.getIntPtrConstant(Offset, DL));
2854 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
2855 }
2856
2857 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2858 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2859 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2860 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2861 /* Alignment = */ 0, MachineMemOperand::MOVolatile);
2862}
2863
2864void MipsTargetLowering::
2865getOpndList(SmallVectorImpl<SDValue> &Ops,
2866 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
2867 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2868 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2869 SDValue Chain) const {
2870 // Insert node "GP copy globalreg" before call to function.
2871 //
2872 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2873 // in PIC mode) allow symbols to be resolved via lazy binding.
2874 // The lazy binding stub requires GP to point to the GOT.
2875 // Note that we don't need GP to point to the GOT for indirect calls
2876 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2877 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2878 // used for the function (that is, Mips linker doesn't generate lazy binding
2879 // stub for a function whose address is taken in the program).
2880 if (IsPICCall && !InternalLinkage && IsCallReloc) {
2881 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2882 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2883 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2884 }
2885
2886 // Build a sequence of copy-to-reg nodes chained together with token
2887 // chain and flag operands which copy the outgoing args into registers.
2888 // The InFlag in necessary since all emitted instructions must be
2889 // stuck together.
2890 SDValue InFlag;
2891
2892 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2893 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2894 RegsToPass[i].second, InFlag);
2895 InFlag = Chain.getValue(1);
2896 }
2897
2898 // Add argument registers to the end of the list so that they are
2899 // known live into the call.
2900 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2901 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2902 RegsToPass[i].second.getValueType()));
2903
2904 // Add a register mask operand representing the call-preserved registers.
2905 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2906 const uint32_t *Mask =
2907 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2908 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 2908, __extension__ __PRETTY_FUNCTION__))
;
2909 if (Subtarget.inMips16HardFloat()) {
2910 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2911 StringRef Sym = G->getGlobal()->getName();
2912 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2913 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2914 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2915 }
2916 }
2917 }
2918 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2919
2920 if (InFlag.getNode())
2921 Ops.push_back(InFlag);
2922}
2923
2924/// LowerCall - functions arguments are copied from virtual regs to
2925/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2926SDValue
2927MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2928 SmallVectorImpl<SDValue> &InVals) const {
2929 SelectionDAG &DAG = CLI.DAG;
2930 SDLoc DL = CLI.DL;
2931 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2932 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2933 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2934 SDValue Chain = CLI.Chain;
2935 SDValue Callee = CLI.Callee;
2936 bool &IsTailCall = CLI.IsTailCall;
2937 CallingConv::ID CallConv = CLI.CallConv;
2938 bool IsVarArg = CLI.IsVarArg;
2939
2940 MachineFunction &MF = DAG.getMachineFunction();
2941 MachineFrameInfo &MFI = MF.getFrameInfo();
2942 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
2943 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2944 bool IsPIC = isPositionIndependent();
2945
2946 // Analyze operands of the call, assigning locations to each operand.
2947 SmallVector<CCValAssign, 16> ArgLocs;
2948 MipsCCState CCInfo(
2949 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2950 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2951
2952 const ExternalSymbolSDNode *ES =
2953 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
2954
2955 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
2956 // is during the lowering of a call with a byval argument which produces
2957 // a call to memcpy. For the O32 case, this causes the caller to allocate
2958 // stack space for the reserved argument area for the callee, then recursively
2959 // again for the memcpy call. In the NEWABI case, this doesn't occur as those
2960 // ABIs mandate that the callee allocates the reserved argument area. We do
2961 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
2962 //
2963 // If the callee has a byval argument and memcpy is used, we are mandated
2964 // to already have produced a reserved argument area for the callee for O32.
2965 // Therefore, the reserved argument area can be reused for both calls.
2966 //
2967 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
2968 // present, as we have yet to hook that node onto the chain.
2969 //
2970 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
2971 // case. GCC does a similar trick, in that wherever possible, it calculates
2972 // the maximum out going argument area (including the reserved area), and
2973 // preallocates the stack space on entrance to the caller.
2974 //
2975 // FIXME: We should do the same for efficency and space.
2976
2977 // Note: The check on the calling convention below must match
2978 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
2979 bool MemcpyInByVal = ES &&
2980 StringRef(ES->getSymbol()) == StringRef("memcpy") &&
2981 CallConv != CallingConv::Fast &&
2982 Chain.getOpcode() == ISD::CALLSEQ_START;
2983
2984 // Allocate the reserved argument area. It seems strange to do this from the
2985 // caller side but removing it breaks the frame size calculation.
2986 unsigned ReservedArgArea =
2987 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv);
2988 CCInfo.AllocateStack(ReservedArgArea, 1);
2989
2990 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
2991 ES ? ES->getSymbol() : nullptr);
2992
2993 // Get a count of how many bytes are to be pushed on the stack.
2994 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2995
2996 // Check if it's really possible to do a tail call. Restrict it to functions
2997 // that are part of this compilation unit.
2998 bool InternalLinkage = false;
2999 if (IsTailCall) {
3000 IsTailCall = isEligibleForTailCallOptimization(
3001 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
3002 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3003 InternalLinkage = G->getGlobal()->hasInternalLinkage();
3004 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
3005 G->getGlobal()->hasPrivateLinkage() ||
3006 G->getGlobal()->hasHiddenVisibility() ||
3007 G->getGlobal()->hasProtectedVisibility());
3008 }
3009 }
3010 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall())
3011 report_fatal_error("failed to perform tail call elimination on a call "
3012 "site marked musttail");
3013
3014 if (IsTailCall)
3015 ++NumTailCalls;
3016
3017 // Chain is the output chain of the last Load/Store or CopyToReg node.
3018 // ByValChain is the output chain of the last Memcpy node created for copying
3019 // byval arguments to the stack.
3020 unsigned StackAlignment = TFL->getStackAlignment();
3021 NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3022 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3023
3024 if (!(IsTailCall || MemcpyInByVal))
3025 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3026
3027 SDValue StackPtr =
3028 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3029 getPointerTy(DAG.getDataLayout()));
3030
3031 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3032 SmallVector<SDValue, 8> MemOpChains;
3033
3034 CCInfo.rewindByValRegsInfo();
3035
3036 // Walk the register/memloc assignments, inserting copies/loads.
3037 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3038 SDValue Arg = OutVals[i];
3039 CCValAssign &VA = ArgLocs[i];
3040 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3041 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3042 bool UseUpperBits = false;
3043
3044 // ByVal Arg.
3045 if (Flags.isByVal()) {
3046 unsigned FirstByValReg, LastByValReg;
3047 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3048 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3049
3050 assert(Flags.getByValSize() &&(static_cast <bool> (Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? void (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3051, __extension__ __PRETTY_FUNCTION__))
3051 "ByVal args of size 0 should have been ignored by front-end.")(static_cast <bool> (Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? void (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3051, __extension__ __PRETTY_FUNCTION__))
;
3052 assert(ByValIdx < CCInfo.getInRegsParamsCount())(static_cast <bool> (ByValIdx < CCInfo.getInRegsParamsCount
()) ? void (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3052, __extension__ __PRETTY_FUNCTION__))
;
3053 assert(!IsTailCall &&(static_cast <bool> (!IsTailCall && "Do not tail-call optimize if there is a byval argument."
) ? void (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3054, __extension__ __PRETTY_FUNCTION__))
3054 "Do not tail-call optimize if there is a byval argument.")(static_cast <bool> (!IsTailCall && "Do not tail-call optimize if there is a byval argument."
) ? void (0) : __assert_fail ("!IsTailCall && \"Do not tail-call optimize if there is a byval argument.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3054, __extension__ __PRETTY_FUNCTION__))
;
3055 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3056 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3057 VA);
3058 CCInfo.nextInRegsParam();
3059 continue;
3060 }
3061
3062 // Promote the value if needed.
3063 switch (VA.getLocInfo()) {
3064 default:
3065 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3065)
;
3066 case CCValAssign::Full:
3067 if (VA.isRegLoc()) {
3068 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3069 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3070 (ValVT == MVT::i64 && LocVT == MVT::f64))
3071 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3072 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3073 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3074 Arg, DAG.getConstant(0, DL, MVT::i32));
3075 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3076 Arg, DAG.getConstant(1, DL, MVT::i32));
3077 if (!Subtarget.isLittle())
3078 std::swap(Lo, Hi);
3079 unsigned LocRegLo = VA.getLocReg();
3080 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3081 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3082 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3083 continue;
3084 }
3085 }
3086 break;
3087 case CCValAssign::BCvt:
3088 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3089 break;
3090 case CCValAssign::SExtUpper:
3091 UseUpperBits = true;
3092 LLVM_FALLTHROUGH[[clang::fallthrough]];
3093 case CCValAssign::SExt:
3094 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3095 break;
3096 case CCValAssign::ZExtUpper:
3097 UseUpperBits = true;
3098 LLVM_FALLTHROUGH[[clang::fallthrough]];
3099 case CCValAssign::ZExt:
3100 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3101 break;
3102 case CCValAssign::AExtUpper:
3103 UseUpperBits = true;
3104 LLVM_FALLTHROUGH[[clang::fallthrough]];
3105 case CCValAssign::AExt:
3106 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3107 break;
3108 }
3109
3110 if (UseUpperBits) {
3111 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3112 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3113 Arg = DAG.getNode(
3114 ISD::SHL, DL, VA.getLocVT(), Arg,
3115 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3116 }
3117
3118 // Arguments that can be passed on register must be kept at
3119 // RegsToPass vector
3120 if (VA.isRegLoc()) {
3121 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3122 continue;
3123 }
3124
3125 // Register can't get to this point...
3126 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3126, __extension__ __PRETTY_FUNCTION__))
;
3127
3128 // emit ISD::STORE whichs stores the
3129 // parameter value to a stack Location
3130 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3131 Chain, Arg, DL, IsTailCall, DAG));
3132 }
3133
3134 // Transform all store nodes into one single node because all store
3135 // nodes are independent of each other.
3136 if (!MemOpChains.empty())
3137 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3138
3139 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3140 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3141 // node so that legalize doesn't hack it.
3142
3143 EVT Ty = Callee.getValueType();
3144 bool GlobalOrExternal = false, IsCallReloc = false;
3145
3146 // The long-calls feature is ignored in case of PIC.
3147 // While we do not support -mshared / -mno-shared properly,
3148 // ignore long-calls in case of -mabicalls too.
3149 if (!Subtarget.isABICalls() && !IsPIC) {
3150 // If the function should be called using "long call",
3151 // get its address into a register to prevent using
3152 // of the `jal` instruction for the direct call.
3153 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3154 if (Subtarget.useLongCalls())
3155 Callee = Subtarget.hasSym32()
3156 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3157 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3158 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3159 bool UseLongCalls = Subtarget.useLongCalls();
3160 // If the function has long-call/far/near attribute
3161 // it overrides command line switch pased to the backend.
3162 if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3163 if (F->hasFnAttribute("long-call"))
3164 UseLongCalls = true;
3165 else if (F->hasFnAttribute("short-call"))
3166 UseLongCalls = false;
3167 }
3168 if (UseLongCalls)
3169 Callee = Subtarget.hasSym32()
3170 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3171 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3172 }
3173 }
3174
3175 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3176 if (IsPIC) {
3177 const GlobalValue *Val = G->getGlobal();
3178 InternalLinkage = Val->hasInternalLinkage();
3179
3180 if (InternalLinkage)
3181 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3182 else if (LargeGOT) {
3183 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3184 MipsII::MO_CALL_LO16, Chain,
3185 FuncInfo->callPtrInfo(Val));
3186 IsCallReloc = true;
3187 } else {
3188 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3189 FuncInfo->callPtrInfo(Val));
3190 IsCallReloc = true;
3191 }
3192 } else
3193 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3194 getPointerTy(DAG.getDataLayout()), 0,
3195 MipsII::MO_NO_FLAG);
3196 GlobalOrExternal = true;
3197 }
3198 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3199 const char *Sym = S->getSymbol();
3200
3201 if (!IsPIC) // static
3202 Callee = DAG.getTargetExternalSymbol(
3203 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
3204 else if (LargeGOT) {
3205 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3206 MipsII::MO_CALL_LO16, Chain,
3207 FuncInfo->callPtrInfo(Sym));
3208 IsCallReloc = true;
3209 } else { // PIC
3210 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3211 FuncInfo->callPtrInfo(Sym));
3212 IsCallReloc = true;
3213 }
3214
3215 GlobalOrExternal = true;
3216 }
3217
3218 SmallVector<SDValue, 8> Ops(1, Chain);
3219 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3220
3221 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3222 IsCallReloc, CLI, Callee, Chain);
3223
3224 if (IsTailCall) {
3225 MF.getFrameInfo().setHasTailCall();
3226 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3227 }
3228
3229 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3230 SDValue InFlag = Chain.getValue(1);
3231
3232 // Create the CALLSEQ_END node in the case of where it is not a call to
3233 // memcpy.
3234 if (!(MemcpyInByVal)) {
3235 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3236 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3237 InFlag = Chain.getValue(1);
3238 }
3239
3240 // Handle result values, copying them out of physregs into vregs that we
3241 // return.
3242 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3243 InVals, CLI);
3244}
3245
3246/// LowerCallResult - Lower the result values of a call into the
3247/// appropriate copies out of appropriate physical registers.
3248SDValue MipsTargetLowering::LowerCallResult(
3249 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3250 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3251 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3252 TargetLowering::CallLoweringInfo &CLI) const {
3253 // Assign locations to each value returned by this call.
3254 SmallVector<CCValAssign, 16> RVLocs;
3255 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3256 *DAG.getContext());
3257
3258 const ExternalSymbolSDNode *ES =
3259 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3260 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3261 ES ? ES->getSymbol() : nullptr);
3262
3263 // Copy all of the result registers out of their specified physreg.
3264 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3265 CCValAssign &VA = RVLocs[i];
3266 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3266, __extension__ __PRETTY_FUNCTION__))
;
3267
3268 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3269 RVLocs[i].getLocVT(), InFlag);
3270 Chain = Val.getValue(1);
3271 InFlag = Val.getValue(2);
3272
3273 if (VA.isUpperBitsInLoc()) {
3274 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3275 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3276 unsigned Shift =
3277 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3278 Val = DAG.getNode(
3279 Shift, DL, VA.getLocVT(), Val,
3280 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3281 }
3282
3283 switch (VA.getLocInfo()) {
3284 default:
3285 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3285)
;
3286 case CCValAssign::Full:
3287 break;
3288 case CCValAssign::BCvt:
3289 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3290 break;
3291 case CCValAssign::AExt:
3292 case CCValAssign::AExtUpper:
3293 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3294 break;
3295 case CCValAssign::ZExt:
3296 case CCValAssign::ZExtUpper:
3297 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3298 DAG.getValueType(VA.getValVT()));
3299 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3300 break;
3301 case CCValAssign::SExt:
3302 case CCValAssign::SExtUpper:
3303 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3304 DAG.getValueType(VA.getValVT()));
3305 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3306 break;
3307 }
3308
3309 InVals.push_back(Val);
3310 }
3311
3312 return Chain;
3313}
3314
3315static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
3316 EVT ArgVT, const SDLoc &DL,
3317 SelectionDAG &DAG) {
3318 MVT LocVT = VA.getLocVT();
3319 EVT ValVT = VA.getValVT();
3320
3321 // Shift into the upper bits if necessary.
3322 switch (VA.getLocInfo()) {
3323 default:
3324 break;
3325 case CCValAssign::AExtUpper:
3326 case CCValAssign::SExtUpper:
3327 case CCValAssign::ZExtUpper: {
3328 unsigned ValSizeInBits = ArgVT.getSizeInBits();
3329 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3330 unsigned Opcode =
3331 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3332 Val = DAG.getNode(
3333 Opcode, DL, VA.getLocVT(), Val,
3334 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3335 break;
3336 }
3337 }
3338
3339 // If this is an value smaller than the argument slot size (32-bit for O32,
3340 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3341 // size. Extract the value and insert any appropriate assertions regarding
3342 // sign/zero extension.
3343 switch (VA.getLocInfo()) {
3344 default:
3345 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3345)
;
3346 case CCValAssign::Full:
3347 break;
3348 case CCValAssign::AExtUpper:
3349 case CCValAssign::AExt:
3350 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3351 break;
3352 case CCValAssign::SExtUpper:
3353 case CCValAssign::SExt:
3354 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3355 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3356 break;
3357 case CCValAssign::ZExtUpper:
3358 case CCValAssign::ZExt:
3359 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3360 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3361 break;
3362 case CCValAssign::BCvt:
3363 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3364 break;
3365 }
3366
3367 return Val;
3368}
3369
3370//===----------------------------------------------------------------------===//
3371// Formal Arguments Calling Convention Implementation
3372//===----------------------------------------------------------------------===//
3373/// LowerFormalArguments - transform physical registers into virtual registers
3374/// and generate load operations for arguments places on the stack.
3375SDValue MipsTargetLowering::LowerFormalArguments(
3376 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3377 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3378 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3379 MachineFunction &MF = DAG.getMachineFunction();
3380 MachineFrameInfo &MFI = MF.getFrameInfo();
3381 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3382
3383 MipsFI->setVarArgsFrameIndex(0);
3384
3385 // Used with vargs to acumulate store chains.
3386 std::vector<SDValue> OutChains;
3387
3388 // Assign locations to all of the incoming arguments.
3389 SmallVector<CCValAssign, 16> ArgLocs;
3390 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3391 *DAG.getContext());
3392 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3393 const Function &Func = DAG.getMachineFunction().getFunction();
3394 Function::const_arg_iterator FuncArg = Func.arg_begin();
3395
3396 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty())
3397 report_fatal_error(
3398 "Functions with the interrupt attribute cannot have arguments!");
3399
3400 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3401 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3402 CCInfo.getInRegsParamsCount() > 0);
3403
3404 unsigned CurArgIdx = 0;
3405 CCInfo.rewindByValRegsInfo();
3406
3407 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3408 CCValAssign &VA = ArgLocs[i];
3409 if (Ins[i].isOrigArg()) {
3410 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3411 CurArgIdx = Ins[i].getOrigArgIndex();
3412 }
3413 EVT ValVT = VA.getValVT();
3414 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3415 bool IsRegLoc = VA.isRegLoc();
3416
3417 if (Flags.isByVal()) {
3418 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit")(static_cast <bool> (Ins[i].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[i].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3418, __extension__ __PRETTY_FUNCTION__))
;
3419 unsigned FirstByValReg, LastByValReg;
3420 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3421 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3422
3423 assert(Flags.getByValSize() &&(static_cast <bool> (Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? void (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3424, __extension__ __PRETTY_FUNCTION__))
3424 "ByVal args of size 0 should have been ignored by front-end.")(static_cast <bool> (Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."
) ? void (0) : __assert_fail ("Flags.getByValSize() && \"ByVal args of size 0 should have been ignored by front-end.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3424, __extension__ __PRETTY_FUNCTION__))
;
3425 assert(ByValIdx < CCInfo.getInRegsParamsCount())(static_cast <bool> (ByValIdx < CCInfo.getInRegsParamsCount
()) ? void (0) : __assert_fail ("ByValIdx < CCInfo.getInRegsParamsCount()"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3425, __extension__ __PRETTY_FUNCTION__))
;
3426 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3427 FirstByValReg, LastByValReg, VA, CCInfo);
3428 CCInfo.nextInRegsParam();
3429 continue;
3430 }
3431
3432 // Arguments stored on registers
3433 if (IsRegLoc) {
3434 MVT RegVT = VA.getLocVT();
3435 unsigned ArgReg = VA.getLocReg();
3436 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3437
3438 // Transform the arguments stored on
3439 // physical registers into virtual ones
3440 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3441 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3442
3443 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3444
3445 // Handle floating point arguments passed in integer registers and
3446 // long double arguments passed in floating point registers.
3447 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3448 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3449 (RegVT == MVT::f64 && ValVT == MVT::i64))
3450 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3451 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3452 ValVT == MVT::f64) {
3453 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3454 getNextIntArgReg(ArgReg), RC);
3455 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3456 if (!Subtarget.isLittle())
3457 std::swap(ArgValue, ArgValue2);
3458 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3459 ArgValue, ArgValue2);
3460 }
3461
3462 InVals.push_back(ArgValue);
3463 } else { // VA.isRegLoc()
3464 MVT LocVT = VA.getLocVT();
3465
3466 if (ABI.IsO32()) {
3467 // We ought to be able to use LocVT directly but O32 sets it to i32
3468 // when allocating floating point values to integer registers.
3469 // This shouldn't influence how we load the value into registers unless
3470 // we are targeting softfloat.
3471 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3472 LocVT = VA.getValVT();
3473 }
3474
3475 // sanity check
3476 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3476, __extension__ __PRETTY_FUNCTION__))
;
3477
3478 // The stack pointer offset is relative to the caller stack frame.
3479 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3480 VA.getLocMemOffset(), true);
3481
3482 // Create load nodes to retrieve arguments from the stack
3483 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3484 SDValue ArgValue = DAG.getLoad(
3485 LocVT, DL, Chain, FIN,
3486 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3487 OutChains.push_back(ArgValue.getValue(1));
3488
3489 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3490
3491 InVals.push_back(ArgValue);
3492 }
3493 }
3494
3495 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3496 // The mips ABIs for returning structs by value requires that we copy
3497 // the sret argument into $v0 for the return. Save the argument into
3498 // a virtual register so that we can access it from the return points.
3499 if (Ins[i].Flags.isSRet()) {
3500 unsigned Reg = MipsFI->getSRetReturnReg();
3501 if (!Reg) {
3502 Reg = MF.getRegInfo().createVirtualRegister(
3503 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3504 MipsFI->setSRetReturnReg(Reg);
3505 }
3506 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3507 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3508 break;
3509 }
3510 }
3511
3512 if (IsVarArg)
3513 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3514
3515 // All stores are grouped in one node to allow the matching between
3516 // the size of Ins and InVals. This only happens when on varg functions
3517 if (!OutChains.empty()) {
3518 OutChains.push_back(Chain);
3519 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3520 }
3521
3522 return Chain;
3523}
3524
3525//===----------------------------------------------------------------------===//
3526// Return Value Calling Convention Implementation
3527//===----------------------------------------------------------------------===//
3528
3529bool
3530MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3531 MachineFunction &MF, bool IsVarArg,
3532 const SmallVectorImpl<ISD::OutputArg> &Outs,
3533 LLVMContext &Context) const {
3534 SmallVector<CCValAssign, 16> RVLocs;
3535 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3536 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3537}
3538
3539bool
3540MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3541 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
3542 return true;
3543
3544 return IsSigned;
3545}
3546
3547SDValue
3548MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3549 const SDLoc &DL,
3550 SelectionDAG &DAG) const {
3551 MachineFunction &MF = DAG.getMachineFunction();
3552 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3553
3554 MipsFI->setISR();
3555
3556 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3557}
3558
3559SDValue
3560MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3561 bool IsVarArg,
3562 const SmallVectorImpl<ISD::OutputArg> &Outs,
3563 const SmallVectorImpl<SDValue> &OutVals,
3564 const SDLoc &DL, SelectionDAG &DAG) const {
3565 // CCValAssign - represent the assignment of
3566 // the return value to a location
3567 SmallVector<CCValAssign, 16> RVLocs;
3568 MachineFunction &MF = DAG.getMachineFunction();
3569
3570 // CCState - Info about the registers and stack slot.
3571 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3572
3573 // Analyze return values.
3574 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3575
3576 SDValue Flag;
3577 SmallVector<SDValue, 4> RetOps(1, Chain);
3578
3579 // Copy the result values into the output registers.
3580 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3581 SDValue Val = OutVals[i];
3582 CCValAssign &VA = RVLocs[i];
3583 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3583, __extension__ __PRETTY_FUNCTION__))
;
3584 bool UseUpperBits = false;
3585
3586 switch (VA.getLocInfo()) {
3587 default:
3588 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3588)
;
3589 case CCValAssign::Full:
3590 break;
3591 case CCValAssign::BCvt:
3592 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3593 break;
3594 case CCValAssign::AExtUpper:
3595 UseUpperBits = true;
3596 LLVM_FALLTHROUGH[[clang::fallthrough]];
3597 case CCValAssign::AExt:
3598 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3599 break;
3600 case CCValAssign::ZExtUpper:
3601 UseUpperBits = true;
3602 LLVM_FALLTHROUGH[[clang::fallthrough]];
3603 case CCValAssign::ZExt:
3604 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3605 break;
3606 case CCValAssign::SExtUpper:
3607 UseUpperBits = true;
3608 LLVM_FALLTHROUGH[[clang::fallthrough]];
3609 case CCValAssign::SExt:
3610 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3611 break;
3612 }
3613
3614 if (UseUpperBits) {
3615 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3616 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3617 Val = DAG.getNode(
3618 ISD::SHL, DL, VA.getLocVT(), Val,
3619 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3620 }
3621
3622 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3623
3624 // Guarantee that all emitted copies are stuck together with flags.
3625 Flag = Chain.getValue(1);
3626 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3627 }
3628
3629 // The mips ABIs for returning structs by value requires that we copy
3630 // the sret argument into $v0 for the return. We saved the argument into
3631 // a virtual register in the entry block, so now we copy the value out
3632 // and into $v0.
3633 if (MF.getFunction().hasStructRetAttr()) {
3634 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3635 unsigned Reg = MipsFI->getSRetReturnReg();
3636
3637 if (!Reg)
3638 llvm_unreachable("sret virtual register not created in the entry block")::llvm::llvm_unreachable_internal("sret virtual register not created in the entry block"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3638)
;
3639 SDValue Val =
3640 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3641 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3642
3643 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3644 Flag = Chain.getValue(1);
3645 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3646 }
3647
3648 RetOps[0] = Chain; // Update chain.
3649
3650 // Add the flag if we have it.
3651 if (Flag.getNode())
3652 RetOps.push_back(Flag);
3653
3654 // ISRs must use "eret".
3655 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
3656 return LowerInterruptReturn(RetOps, DL, DAG);
3657
3658 // Standard return on Mips is a "jr $ra"
3659 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3660}
3661
3662//===----------------------------------------------------------------------===//
3663// Mips Inline Assembly Support
3664//===----------------------------------------------------------------------===//
3665
3666/// getConstraintType - Given a constraint letter, return the type of
3667/// constraint it is for this target.
3668MipsTargetLowering::ConstraintType
3669MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3670 // Mips specific constraints
3671 // GCC config/mips/constraints.md
3672 //
3673 // 'd' : An address register. Equivalent to r
3674 // unless generating MIPS16 code.
3675 // 'y' : Equivalent to r; retained for
3676 // backwards compatibility.
3677 // 'c' : A register suitable for use in an indirect
3678 // jump. This will always be $25 for -mabicalls.
3679 // 'l' : The lo register. 1 word storage.
3680 // 'x' : The hilo register pair. Double word storage.
3681 if (Constraint.size() == 1) {
3682 switch (Constraint[0]) {
3683 default : break;
3684 case 'd':
3685 case 'y':
3686 case 'f':
3687 case 'c':
3688 case 'l':
3689 case 'x':
3690 return C_RegisterClass;
3691 case 'R':
3692 return C_Memory;
3693 }
3694 }
3695
3696 if (Constraint == "ZC")
3697 return C_Memory;
3698
3699 return TargetLowering::getConstraintType(Constraint);
3700}
3701
3702/// Examine constraint type and operand type and determine a weight value.
3703/// This object must already have been set up with the operand type
3704/// and the current alternative constraint selected.
3705TargetLowering::ConstraintWeight
3706MipsTargetLowering::getSingleConstraintMatchWeight(
3707 AsmOperandInfo &info, const char *constraint) const {
3708 ConstraintWeight weight = CW_Invalid;
3709 Value *CallOperandVal = info.CallOperandVal;
3710 // If we don't have a value, we can't do a match,
3711 // but allow it at the lowest weight.
3712 if (!CallOperandVal)
3713 return CW_Default;
3714 Type *type = CallOperandVal->getType();
3715 // Look at the constraint type.
3716 switch (*constraint) {
3717 default:
3718 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3719 break;
3720 case 'd':
3721 case 'y':
3722 if (type->isIntegerTy())
3723 weight = CW_Register;
3724 break;
3725 case 'f': // FPU or MSA register
3726 if (Subtarget.hasMSA() && type->isVectorTy() &&
3727 cast<VectorType>(type)->getBitWidth() == 128)
3728 weight = CW_Register;
3729 else if (type->isFloatTy())
3730 weight = CW_Register;
3731 break;
3732 case 'c': // $25 for indirect jumps
3733 case 'l': // lo register
3734 case 'x': // hilo register pair
3735 if (type->isIntegerTy())
3736 weight = CW_SpecificReg;
3737 break;
3738 case 'I': // signed 16 bit immediate
3739 case 'J': // integer zero
3740 case 'K': // unsigned 16 bit immediate
3741 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3742 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3743 case 'O': // signed 15 bit immediate (+- 16383)
3744 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3745 if (isa<ConstantInt>(CallOperandVal))
3746 weight = CW_Constant;
3747 break;
3748 case 'R':
3749 weight = CW_Memory;
3750 break;
3751 }
3752 return weight;
3753}
3754
3755/// This is a helper function to parse a physical register string and split it
3756/// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3757/// that is returned indicates whether parsing was successful. The second flag
3758/// is true if the numeric part exists.
3759static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3760 unsigned long long &Reg) {
3761 if (C.front() != '{' || C.back() != '}')
3762 return std::make_pair(false, false);
3763
3764 // Search for the first numeric character.
3765 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3766 I = std::find_if(B, E, isdigit);
3767
3768 Prefix = StringRef(B, I - B);
3769
3770 // The second flag is set to false if no numeric characters were found.
3771 if (I == E)
3772 return std::make_pair(true, false);
3773
3774 // Parse the numeric characters.
3775 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3776 true);
3777}
3778
3779std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3780parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3781 const TargetRegisterInfo *TRI =
3782 Subtarget.getRegisterInfo();
3783 const TargetRegisterClass *RC;
3784 StringRef Prefix;
3785 unsigned long long Reg;
3786
3787 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3788
3789 if (!R.first)
3790 return std::make_pair(0U, nullptr);
3791
3792 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3793 // No numeric characters follow "hi" or "lo".
3794 if (R.second)
3795 return std::make_pair(0U, nullptr);
3796
3797 RC = TRI->getRegClass(Prefix == "hi" ?
3798 Mips::HI32RegClassID : Mips::LO32RegClassID);
3799 return std::make_pair(*(RC->begin()), RC);
3800 } else if (Prefix.startswith("$msa")) {
3801 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3802
3803 // No numeric characters follow the name.
3804 if (R.second)
3805 return std::make_pair(0U, nullptr);
3806
3807 Reg = StringSwitch<unsigned long long>(Prefix)
3808 .Case("$msair", Mips::MSAIR)
3809 .Case("$msacsr", Mips::MSACSR)
3810 .Case("$msaaccess", Mips::MSAAccess)
3811 .Case("$msasave", Mips::MSASave)
3812 .Case("$msamodify", Mips::MSAModify)
3813 .Case("$msarequest", Mips::MSARequest)
3814 .Case("$msamap", Mips::MSAMap)
3815 .Case("$msaunmap", Mips::MSAUnmap)
3816 .Default(0);
3817
3818 if (!Reg)
3819 return std::make_pair(0U, nullptr);
3820
3821 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3822 return std::make_pair(Reg, RC);
3823 }
3824
3825 if (!R.second)
3826 return std::make_pair(0U, nullptr);
3827
3828 if (Prefix == "$f") { // Parse $f0-$f31.
3829 // If the size of FP registers is 64-bit or Reg is an even number, select
3830 // the 64-bit register class. Otherwise, select the 32-bit register class.
3831 if (VT == MVT::Other)
3832 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3833
3834 RC = getRegClassFor(VT);
3835
3836 if (RC == &Mips::AFGR64RegClass) {
3837 assert(Reg % 2 == 0)(static_cast <bool> (Reg % 2 == 0) ? void (0) : __assert_fail
("Reg % 2 == 0", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3837, __extension__ __PRETTY_FUNCTION__))
;
3838 Reg >>= 1;
3839 }
3840 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3841 RC = TRI->getRegClass(Mips::FCCRegClassID);
3842 else if (Prefix == "$w") { // Parse $w0-$w31.
3843 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3844 } else { // Parse $0-$31.
3845 assert(Prefix == "$")(static_cast <bool> (Prefix == "$") ? void (0) : __assert_fail
("Prefix == \"$\"", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3845, __extension__ __PRETTY_FUNCTION__))
;
3846 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3847 }
3848
3849 assert(Reg < RC->getNumRegs())(static_cast <bool> (Reg < RC->getNumRegs()) ? void
(0) : __assert_fail ("Reg < RC->getNumRegs()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 3849, __extension__ __PRETTY_FUNCTION__))
;
3850 return std::make_pair(*(RC->begin() + Reg), RC);
3851}
3852
3853/// Given a register class constraint, like 'r', if this corresponds directly
3854/// to an LLVM register class, return a register of 0 and the register class
3855/// pointer.
3856std::pair<unsigned, const TargetRegisterClass *>
3857MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3858 StringRef Constraint,
3859 MVT VT) const {
3860 if (Constraint.size() == 1) {
3861 switch (Constraint[0]) {
3862 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3863 case 'y': // Same as 'r'. Exists for compatibility.
3864 case 'r':
3865 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3866 if (Subtarget.inMips16Mode())
3867 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3868 return std::make_pair(0U, &Mips::GPR32RegClass);
3869 }
3870 if (VT == MVT::i64 && !Subtarget.isGP64bit())
3871 return std::make_pair(0U, &Mips::GPR32RegClass);
3872 if (VT == MVT::i64 && Subtarget.isGP64bit())
3873 return std::make_pair(0U, &Mips::GPR64RegClass);
3874 // This will generate an error message
3875 return std::make_pair(0U, nullptr);
3876 case 'f': // FPU or MSA register
3877 if (VT == MVT::v16i8)
3878 return std::make_pair(0U, &Mips::MSA128BRegClass);
3879 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3880 return std::make_pair(0U, &Mips::MSA128HRegClass);
3881 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3882 return std::make_pair(0U, &Mips::MSA128WRegClass);
3883 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3884 return std::make_pair(0U, &Mips::MSA128DRegClass);
3885 else if (VT == MVT::f32)
3886 return std::make_pair(0U, &Mips::FGR32RegClass);
3887 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3888 if (Subtarget.isFP64bit())
3889 return std::make_pair(0U, &Mips::FGR64RegClass);
3890 return std::make_pair(0U, &Mips::AFGR64RegClass);
3891 }
3892 break;
3893 case 'c': // register suitable for indirect jump
3894 if (VT == MVT::i32)
3895 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3896 if (VT == MVT::i64)
3897 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3898 // This will generate an error message
3899 return std::make_pair(0U, nullptr);
3900 case 'l': // use the `lo` register to store values
3901 // that are no bigger than a word
3902 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
3903 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3904 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3905 case 'x': // use the concatenated `hi` and `lo` registers
3906 // to store doubleword values
3907 // Fixme: Not triggering the use of both hi and low
3908 // This will generate an error message
3909 return std::make_pair(0U, nullptr);
3910 }
3911 }
3912
3913 std::pair<unsigned, const TargetRegisterClass *> R;
3914 R = parseRegForInlineAsmConstraint(Constraint, VT);
3915
3916 if (R.second)
3917 return R;
3918
3919 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3920}
3921
3922/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3923/// vector. If it is invalid, don't add anything to Ops.
3924void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3925 std::string &Constraint,
3926 std::vector<SDValue>&Ops,
3927 SelectionDAG &DAG) const {
3928 SDLoc DL(Op);
3929 SDValue Result;
3930
3931 // Only support length 1 constraints for now.
3932 if (Constraint.length() > 1) return;
3933
3934 char ConstraintLetter = Constraint[0];
3935 switch (ConstraintLetter) {
3936 default: break; // This will fall through to the generic implementation
3937 case 'I': // Signed 16 bit constant
3938 // If this fails, the parent routine will give an error
3939 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3940 EVT Type = Op.getValueType();
3941 int64_t Val = C->getSExtValue();
3942 if (isInt<16>(Val)) {
3943 Result = DAG.getTargetConstant(Val, DL, Type);
3944 break;
3945 }
3946 }
3947 return;
3948 case 'J': // integer zero
3949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3950 EVT Type = Op.getValueType();
3951 int64_t Val = C->getZExtValue();
3952 if (Val == 0) {
3953 Result = DAG.getTargetConstant(0, DL, Type);
3954 break;
3955 }
3956 }
3957 return;
3958 case 'K': // unsigned 16 bit immediate
3959 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3960 EVT Type = Op.getValueType();
3961 uint64_t Val = (uint64_t)C->getZExtValue();
3962 if (isUInt<16>(Val)) {
3963 Result = DAG.getTargetConstant(Val, DL, Type);
3964 break;
3965 }
3966 }
3967 return;
3968 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3969 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3970 EVT Type = Op.getValueType();
3971 int64_t Val = C->getSExtValue();
3972 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3973 Result = DAG.getTargetConstant(Val, DL, Type);
3974 break;
3975 }
3976 }
3977 return;
3978 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3979 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3980 EVT Type = Op.getValueType();
3981 int64_t Val = C->getSExtValue();
3982 if ((Val >= -65535) && (Val <= -1)) {
3983 Result = DAG.getTargetConstant(Val, DL, Type);
3984 break;
3985 }
3986 }
3987 return;
3988 case 'O': // signed 15 bit immediate
3989 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3990 EVT Type = Op.getValueType();
3991 int64_t Val = C->getSExtValue();
3992 if ((isInt<15>(Val))) {
3993 Result = DAG.getTargetConstant(Val, DL, Type);
3994 break;
3995 }
3996 }
3997 return;
3998 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3999 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4000 EVT Type = Op.getValueType();
4001 int64_t Val = C->getSExtValue();
4002 if ((Val <= 65535) && (Val >= 1)) {
4003 Result = DAG.getTargetConstant(Val, DL, Type);
4004 break;
4005 }
4006 }
4007 return;
4008 }
4009
4010 if (Result.getNode()) {
4011 Ops.push_back(Result);
4012 return;
4013 }
4014
4015 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4016}
4017
4018bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
4019 const AddrMode &AM, Type *Ty,
4020 unsigned AS, Instruction *I) const {
4021 // No global is ever allowed as a base.
4022 if (AM.BaseGV)
4023 return false;
4024
4025 switch (AM.Scale) {
4026 case 0: // "r+i" or just "i", depending on HasBaseReg.
4027 break;
4028 case 1:
4029 if (!AM.HasBaseReg) // allow "r+i".
4030 break;
4031 return false; // disallow "r+r" or "r+r+i".
4032 default:
4033 return false;
4034 }
4035
4036 return true;
4037}
4038
4039bool
4040MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4041 // The Mips target isn't yet aware of offsets.
4042 return false;
4043}
4044
4045EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
4046 unsigned SrcAlign,
4047 bool IsMemset, bool ZeroMemset,
4048 bool MemcpyStrSrc,
4049 MachineFunction &MF) const {
4050 if (Subtarget.hasMips64())
4051 return MVT::i64;
4052
4053 return MVT::i32;
4054}
4055
4056bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4057 if (VT != MVT::f32 && VT != MVT::f64)
4058 return false;
4059 if (Imm.isNegZero())
4060 return false;
4061 return Imm.isZero();
4062}
4063
4064unsigned MipsTargetLowering::getJumpTableEncoding() const {
4065
4066 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
4067 if (ABI.IsN64() && isPositionIndependent())
4068 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4069
4070 return TargetLowering::getJumpTableEncoding();
4071}
4072
4073bool MipsTargetLowering::useSoftFloat() const {
4074 return Subtarget.useSoftFloat();
4075}
4076
4077void MipsTargetLowering::copyByValRegs(
4078 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4079 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4080 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4081 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4082 MipsCCState &State) const {
4083 MachineFunction &MF = DAG.getMachineFunction();
4084 MachineFrameInfo &MFI = MF.getFrameInfo();
4085 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4086 unsigned NumRegs = LastReg - FirstReg;
4087 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4088 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4089 int FrameObjOffset;
4090 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4091
4092 if (RegAreaSize)
4093 FrameObjOffset =
4094 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4095 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4096 else
4097 FrameObjOffset = VA.getLocMemOffset();
4098
4099 // Create frame object.
4100 EVT PtrTy = getPointerTy(DAG.getDataLayout());
4101 // Make the fixed object stored to mutable so that the load instructions
4102 // referencing it have their memory dependencies added.
4103 // Set the frame object as isAliased which clears the underlying objects
4104 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
4105 // stores as dependencies for loads referencing this fixed object.
4106 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true);
4107 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4108 InVals.push_back(FIN);
4109
4110 if (!NumRegs)
4111 return;
4112
4113 // Copy arg registers.
4114 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4115 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4116
4117 for (unsigned I = 0; I < NumRegs; ++I) {
4118 unsigned ArgReg = ByValArgRegs[FirstReg + I];
4119 unsigned VReg = addLiveIn(MF, ArgReg, RC);
4120 unsigned Offset = I * GPRSizeInBytes;
4121 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4122 DAG.getConstant(Offset, DL, PtrTy));
4123 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4124 StorePtr, MachinePointerInfo(FuncArg, Offset));
4125 OutChains.push_back(Store);
4126 }
4127}
4128
4129// Copy byVal arg to registers and stack.
4130void MipsTargetLowering::passByValArg(
4131 SDValue Chain, const SDLoc &DL,
4132 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4133 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4134 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4135 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4136 const CCValAssign &VA) const {
4137 unsigned ByValSizeInBytes = Flags.getByValSize();
4138 unsigned OffsetInBytes = 0; // From beginning of struct
4139 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4140 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
4141 EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4142 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4143 unsigned NumRegs = LastReg - FirstReg;
4144
4145 if (NumRegs) {
4146 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
4147 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4148 unsigned I = 0;
4149
4150 // Copy words to registers.
4151 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4152 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4153 DAG.getConstant(OffsetInBytes, DL, PtrTy));
4154 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4155 MachinePointerInfo(), Alignment);
4156 MemOpChains.push_back(LoadVal.getValue(1));
4157 unsigned ArgReg = ArgRegs[FirstReg + I];
4158 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4159 }
4160
4161 // Return if the struct has been fully copied.
4162 if (ByValSizeInBytes == OffsetInBytes)
4163 return;
4164
4165 // Copy the remainder of the byval argument with sub-word loads and shifts.
4166 if (LeftoverBytes) {
4167 SDValue Val;
4168
4169 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4170 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4171 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4172
4173 if (RemainingSizeInBytes < LoadSizeInBytes)
4174 continue;
4175
4176 // Load subword.
4177 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4178 DAG.getConstant(OffsetInBytes, DL,
4179 PtrTy));
4180 SDValue LoadVal = DAG.getExtLoad(
4181 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4182 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4183 MemOpChains.push_back(LoadVal.getValue(1));
4184
4185 // Shift the loaded value.
4186 unsigned Shamt;
4187
4188 if (isLittle)
4189 Shamt = TotalBytesLoaded * 8;
4190 else
4191 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4192
4193 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4194 DAG.getConstant(Shamt, DL, MVT::i32));
4195
4196 if (Val.getNode())
4197 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4198 else
4199 Val = Shift;
4200
4201 OffsetInBytes += LoadSizeInBytes;
4202 TotalBytesLoaded += LoadSizeInBytes;
4203 Alignment = std::min(Alignment, LoadSizeInBytes);
4204 }
4205
4206 unsigned ArgReg = ArgRegs[FirstReg + I];
4207 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4208 return;
4209 }
4210 }
4211
4212 // Copy remainder of byval arg to it with memcpy.
4213 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4214 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4215 DAG.getConstant(OffsetInBytes, DL, PtrTy));
4216 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4217 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4218 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4219 DAG.getConstant(MemCpySize, DL, PtrTy),
4220 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
4221 /*isTailCall=*/false,
4222 MachinePointerInfo(), MachinePointerInfo());
4223 MemOpChains.push_back(Chain);
4224}
4225
4226void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4227 SDValue Chain, const SDLoc &DL,
4228 SelectionDAG &DAG,
4229 CCState &State) const {
4230 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
4231 unsigned Idx = State.getFirstUnallocated(ArgRegs);
4232 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4233 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4234 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4235 MachineFunction &MF = DAG.getMachineFunction();
4236 MachineFrameInfo &MFI = MF.getFrameInfo();
4237 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4238
4239 // Offset of the first variable argument from stack pointer.
4240 int VaArgOffset;
4241
4242 if (ArgRegs.size() == Idx)
4243 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
4244 else {
4245 VaArgOffset =
4246 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4247 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4248 }
4249
4250 // Record the frame index of the first variable argument
4251 // which is a value necessary to VASTART.
4252 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4253 MipsFI->setVarArgsFrameIndex(FI);
4254
4255 // Copy the integer registers that have not been used for argument passing
4256 // to the argument register save area. For O32, the save area is allocated
4257 // in the caller's stack frame, while for N32/64, it is allocated in the
4258 // callee's stack frame.
4259 for (unsigned I = Idx; I < ArgRegs.size();
4260 ++I, VaArgOffset += RegSizeInBytes) {
4261 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4262 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4263 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4264 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4265 SDValue Store =
4266 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4267 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4268 (Value *)nullptr);
4269 OutChains.push_back(Store);
4270 }
4271}
4272
4273void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4274 unsigned Align) const {
4275 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
4276
4277 assert(Size && "Byval argument's size shouldn't be 0.")(static_cast <bool> (Size && "Byval argument's size shouldn't be 0."
) ? void (0) : __assert_fail ("Size && \"Byval argument's size shouldn't be 0.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 4277, __extension__ __PRETTY_FUNCTION__))
;
4278
4279 Align = std::min(Align, TFL->getStackAlignment());
4280
4281 unsigned FirstReg = 0;
4282 unsigned NumRegs = 0;
4283
4284 if (State->getCallingConv() != CallingConv::Fast) {
4285 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4286 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4287 // FIXME: The O32 case actually describes no shadow registers.
4288 const MCPhysReg *ShadowRegs =
4289 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4290
4291 // We used to check the size as well but we can't do that anymore since
4292 // CCState::HandleByVal() rounds up the size after calling this function.
4293 assert(!(Align % RegSizeInBytes) &&(static_cast <bool> (!(Align % RegSizeInBytes) &&
"Byval argument's alignment should be a multiple of" "RegSizeInBytes."
) ? void (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 4295, __extension__ __PRETTY_FUNCTION__))
4294 "Byval argument's alignment should be a multiple of"(static_cast <bool> (!(Align % RegSizeInBytes) &&
"Byval argument's alignment should be a multiple of" "RegSizeInBytes."
) ? void (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 4295, __extension__ __PRETTY_FUNCTION__))
4295 "RegSizeInBytes.")(static_cast <bool> (!(Align % RegSizeInBytes) &&
"Byval argument's alignment should be a multiple of" "RegSizeInBytes."
) ? void (0) : __assert_fail ("!(Align % RegSizeInBytes) && \"Byval argument's alignment should be a multiple of\" \"RegSizeInBytes.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 4295, __extension__ __PRETTY_FUNCTION__))
;
4296
4297 FirstReg = State->getFirstUnallocated(IntArgRegs);
4298
4299 // If Align > RegSizeInBytes, the first arg register must be even.
4300 // FIXME: This condition happens to do the right thing but it's not the
4301 // right way to test it. We want to check that the stack frame offset
4302 // of the register is aligned.
4303 if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
4304 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4305 ++FirstReg;
4306 }
4307
4308 // Mark the registers allocated.
4309 Size = alignTo(Size, RegSizeInBytes);
4310 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4311 Size -= RegSizeInBytes, ++I, ++NumRegs)
4312 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4313 }
4314
4315 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4316}
4317
4318MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4319 MachineBasicBlock *BB,
4320 bool isFPCmp,
4321 unsigned Opc) const {
4322 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&(static_cast <bool> (!(Subtarget.hasMips4() || Subtarget
.hasMips32()) && "Subtarget already supports SELECT nodes with the use of"
"conditional-move instructions.") ? void (0) : __assert_fail
("!(Subtarget.hasMips4() || Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 4324, __extension__ __PRETTY_FUNCTION__))
4323 "Subtarget already supports SELECT nodes with the use of"(static_cast <bool> (!(Subtarget.hasMips4() || Subtarget
.hasMips32()) && "Subtarget already supports SELECT nodes with the use of"
"conditional-move instructions.") ? void (0) : __assert_fail
("!(Subtarget.hasMips4() || Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 4324, __extension__ __PRETTY_FUNCTION__))
4324 "conditional-move instructions.")(static_cast <bool> (!(Subtarget.hasMips4() || Subtarget
.hasMips32()) && "Subtarget already supports SELECT nodes with the use of"
"conditional-move instructions.") ? void (0) : __assert_fail
("!(Subtarget.hasMips4() || Subtarget.hasMips32()) && \"Subtarget already supports SELECT nodes with the use of\" \"conditional-move instructions.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Mips/MipsISelLowering.cpp"
, 4324, __extension__ __PRETTY_FUNCTION__))
;
4325
4326 const TargetInstrInfo *TII =
4327 Subtarget.getInstrInfo();
4328 DebugLoc DL = MI.getDebugLoc();
4329
4330 // To "insert" a SELECT instruction, we actually have to insert the
4331 // diamond control-flow pattern. The incoming instruction knows the
4332 // destination vreg to set, the condition code register to branch on, the
4333 // true/false values to select between, and a branch opcode to use.
4334 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4335 MachineFunction::iterator It = ++BB->getIterator();
4336
4337 // thisMBB:
4338 // ...
4339 // TrueVal = ...
4340 // setcc r1, r2, r3
4341 // bNE r1, r0, copy1MBB
4342 // fallthrough --> copy0MBB
4343 MachineBasicBlock *thisMBB = BB;
4344 MachineFunction *F = BB->getParent();
4345 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4346 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4347 F->insert(It, copy0MBB);
4348 F->insert(It, sinkMBB);
4349
4350 // Transfer the remainder of BB and its successor edges to sinkMBB.
4351 sinkMBB->splice(sinkMBB->begin(), BB,
4352 std::next(MachineBasicBlock::iterator(MI)), BB->end());
4353 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4354
4355 // Next, add the true and fallthrough blocks as its successors.
4356 BB->addSuccessor(copy0MBB);
4357 BB->addSuccessor(sinkMBB);
4358
4359 if (isFPCmp) {
4360 // bc1[tf] cc, sinkMBB
4361 BuildMI(BB, DL, TII->get(Opc))
4362 .addReg(MI.getOperand(1).getReg())
4363 .addMBB(sinkMBB);
4364 } else {
4365 // bne rs, $0, sinkMBB
4366 BuildMI(BB, DL, TII->get(Opc))
4367 .addReg(MI.getOperand(1).getReg())
4368 .addReg(Mips::ZERO)
4369 .addMBB(sinkMBB);
4370 }
4371
4372 // copy0MBB:
4373 // %FalseValue = ...
4374 // # fallthrough to sinkMBB
4375 BB = copy0MBB;
4376
4377 // Update machine-CFG edges
4378 BB->addSuccessor(sinkMBB);
4379
4380 // sinkMBB:
4381 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4382 // ...
4383 BB = sinkMBB;
4384
4385 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4386 .addReg(MI.getOperand(2).getReg())
4387 .addMBB(thisMBB)
4388 .addReg(MI.getOperand(3).getReg())
4389 .addMBB(copy0MBB);
4390
4391 MI.eraseFromParent(); // The pseudo instruction is gone now.
4392
4393 return BB;
4394}
4395
4396// FIXME? Maybe this could be a TableGen attribute on some registers and
4397// this table could be generated automatically from RegInfo.
4398unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4399 SelectionDAG &DAG) const {
4400 // Named registers is expected to be fairly rare. For now, just support $28
4401 // since the linux kernel uses it.
4402 if (Subtarget.isGP64bit()) {
4403 unsigned Reg = StringSwitch<unsigned>(RegName)
4404 .Case("$28", Mips::GP_64)
4405 .Default(0);
4406 if (Reg)
4407 return Reg;
4408 } else {
4409 unsigned Reg = StringSwitch<unsigned>(RegName)
4410 .Case("$28", Mips::GP)
4411 .Default(0);
4412 if (Reg)
4413 return Reg;
4414 }
4415 report_fatal_error("Invalid register name global variable");
4416}