Bug Summary

File:lib/Target/Mips/MipsSEISelDAGToDAG.cpp
Warning:line 1056, column 15
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MipsSEISelDAGToDAG.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~svn372306/build-llvm/lib/Target/Mips -I /build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips -I /build/llvm-toolchain-snapshot-10~svn372306/build-llvm/include -I /build/llvm-toolchain-snapshot-10~svn372306/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~svn372306/build-llvm/lib/Target/Mips -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~svn372306=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-09-19-172240-30738-1 -x c++ /build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

1//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Subclass of MipsDAGToDAGISel specialized for mips32/64.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsSEISelDAGToDAG.h"
14#include "MCTargetDesc/MipsBaseInfo.h"
15#include "Mips.h"
16#include "MipsAnalyzeImmediate.h"
17#include "MipsMachineFunction.h"
18#include "MipsRegisterInfo.h"
19#include "llvm/CodeGen/MachineConstantPool.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/SelectionDAGNodes.h"
25#include "llvm/IR/CFG.h"
26#include "llvm/IR/Dominators.h"
27#include "llvm/IR/GlobalValue.h"
28#include "llvm/IR/Instructions.h"
29#include "llvm/IR/Intrinsics.h"
30#include "llvm/IR/Type.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
34#include "llvm/Target/TargetMachine.h"
35using namespace llvm;
36
37#define DEBUG_TYPE"mips-isel" "mips-isel"
38
39bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
41 if (Subtarget->inMips16Mode())
42 return false;
43 return MipsDAGToDAGISel::runOnMachineFunction(MF);
44}
45
46void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
47 AU.addRequired<DominatorTreeWrapperPass>();
48 SelectionDAGISel::getAnalysisUsage(AU);
49}
50
51void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
52 MachineFunction &MF) {
53 MachineInstrBuilder MIB(MF, &MI);
54 unsigned Mask = MI.getOperand(1).getImm();
55 unsigned Flag =
56 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
57
58 if (Mask & 1)
59 MIB.addReg(Mips::DSPPos, Flag);
60
61 if (Mask & 2)
62 MIB.addReg(Mips::DSPSCount, Flag);
63
64 if (Mask & 4)
65 MIB.addReg(Mips::DSPCarry, Flag);
66
67 if (Mask & 8)
68 MIB.addReg(Mips::DSPOutFlag, Flag);
69
70 if (Mask & 16)
71 MIB.addReg(Mips::DSPCCond, Flag);
72
73 if (Mask & 32)
74 MIB.addReg(Mips::DSPEFI, Flag);
75}
76
77unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
78 uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue();
79 return Mips::MSACtrlRegClass.getRegister(RegNum);
80}
81
82bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
83 const MachineInstr& MI) {
84 unsigned DstReg = 0, ZeroReg = 0;
85
86 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
87 if ((MI.getOpcode() == Mips::ADDiu) &&
88 (MI.getOperand(1).getReg() == Mips::ZERO) &&
89 (MI.getOperand(2).isImm()) &&
90 (MI.getOperand(2).getImm() == 0)) {
91 DstReg = MI.getOperand(0).getReg();
92 ZeroReg = Mips::ZERO;
93 } else if ((MI.getOpcode() == Mips::DADDiu) &&
94 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
95 (MI.getOperand(2).isImm()) &&
96 (MI.getOperand(2).getImm() == 0)) {
97 DstReg = MI.getOperand(0).getReg();
98 ZeroReg = Mips::ZERO_64;
99 }
100
101 if (!DstReg)
102 return false;
103
104 // Replace uses with ZeroReg.
105 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
106 E = MRI->use_end(); U != E;) {
107 MachineOperand &MO = *U;
108 unsigned OpNo = U.getOperandNo();
109 MachineInstr *MI = MO.getParent();
110 ++U;
111
112 // Do not replace if it is a phi's operand or is tied to def operand.
113 if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
114 continue;
115
116 // Also, we have to check that the register class of the operand
117 // contains the zero register.
118 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
119 continue;
120
121 MO.setReg(ZeroReg);
122 }
123
124 return true;
125}
126
127void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
128 MF.getInfo<MipsFunctionInfo>()->initGlobalBaseReg();
129
130 MachineRegisterInfo *MRI = &MF.getRegInfo();
131
132 for (auto &MBB: MF) {
133 for (auto &MI: MBB) {
134 switch (MI.getOpcode()) {
135 case Mips::RDDSP:
136 addDSPCtrlRegOperands(false, MI, MF);
137 break;
138 case Mips::WRDSP:
139 addDSPCtrlRegOperands(true, MI, MF);
140 break;
141 case Mips::BuildPairF64_64:
142 case Mips::ExtractElementF64_64:
143 if (!Subtarget->useOddSPReg()) {
144 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
145 break;
146 }
147 LLVM_FALLTHROUGH[[gnu::fallthrough]];
148 case Mips::BuildPairF64:
149 case Mips::ExtractElementF64:
150 if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
151 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
152 break;
153 default:
154 replaceUsesWithZeroReg(MRI, MI);
155 }
156 }
157 }
158}
159
160void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
161 SDValue InFlag = Node->getOperand(2);
162 unsigned Opc = InFlag.getOpcode();
163 SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
164 EVT VT = LHS.getValueType();
165
166 // In the base case, we can rely on the carry bit from the addsc
167 // instruction.
168 if (Opc == ISD::ADDC) {
169 SDValue Ops[3] = {LHS, RHS, InFlag};
170 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Ops);
171 return;
172 }
173
174 assert(Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!")((Opc == ISD::ADDE && "ISD::ADDE not in a chain of ADDE nodes!"
) ? static_cast<void> (0) : __assert_fail ("Opc == ISD::ADDE && \"ISD::ADDE not in a chain of ADDE nodes!\""
, "/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 174, __PRETTY_FUNCTION__))
;
175
176 // The more complex case is when there is a chain of ISD::ADDE nodes like:
177 // (adde (adde (adde (addc a b) c) d) e).
178 //
179 // The addwc instruction does not write to the carry bit, instead it writes
180 // to bit 20 of the dsp control register. To match this series of nodes, each
181 // intermediate adde node must be expanded to write the carry bit before the
182 // addition.
183
184 // Start by reading the overflow field for addsc and moving the value to the
185 // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
186 // corresponds to reading/writing the entire control register to/from a GPR.
187
188 SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32);
189
190 SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
191
192 SDNode *DSPCtrlField =
193 CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, MVT::Glue, CstOne, InFlag);
194
195 SDNode *Carry = CurDAG->getMachineNode(
196 Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
197
198 SDValue Ops[4] = {SDValue(DSPCtrlField, 0),
199 CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne,
200 SDValue(Carry, 0)};
201 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops);
202
203 // My reading of the MIPS DSP 3.01 specification isn't as clear as I
204 // would like about whether bit 20 always gets overwritten by addwc.
205 // Hence take an extremely conservative view and presume it's sticky. We
206 // therefore need to clear it.
207
208 SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
209
210 SDValue InsOps[4] = {Zero, OuFlag, CstOne, SDValue(DSPCFWithCarry, 0)};
211 SDNode *DSPCtrlFinal = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
212
213 SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
214 SDValue(DSPCtrlFinal, 0), CstOne);
215
216 SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};
217 CurDAG->SelectNodeTo(Node, Mips::ADDWC, VT, MVT::Glue, Operands);
218}
219
220/// Match frameindex
221bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
222 SDValue &Offset) const {
223 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
224 EVT ValTy = Addr.getValueType();
225
226 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
227 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
228 return true;
229 }
230 return false;
231}
232
233/// Match frameindex+offset and frameindex|offset
234bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
235 SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
236 unsigned ShiftAmount = 0) const {
237 if (CurDAG->isBaseWithConstantOffset(Addr)) {
238 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
239 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
240 EVT ValTy = Addr.getValueType();
241
242 // If the first operand is a FI, get the TargetFI Node
243 if (FrameIndexSDNode *FIN =
244 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
245 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
246 else {
247 Base = Addr.getOperand(0);
248 // If base is a FI, additional offset calculation is done in
249 // eliminateFrameIndex, otherwise we need to check the alignment
250 const llvm::Align Align(1ULL << ShiftAmount);
251 if (!isAligned(Align, CN->getZExtValue()))
252 return false;
253 }
254
255 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr),
256 ValTy);
257 return true;
258 }
259 }
260 return false;
261}
262
263/// ComplexPattern used on MipsInstrInfo
264/// Used on Mips Load/Store instructions
265bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
266 SDValue &Offset) const {
267 // if Address is FI, get the TargetFrameIndex.
268 if (selectAddrFrameIndex(Addr, Base, Offset))
269 return true;
270
271 // on PIC code Load GA
272 if (Addr.getOpcode() == MipsISD::Wrapper) {
273 Base = Addr.getOperand(0);
274 Offset = Addr.getOperand(1);
275 return true;
276 }
277
278 if (!TM.isPositionIndependent()) {
279 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
280 Addr.getOpcode() == ISD::TargetGlobalAddress))
281 return false;
282 }
283
284 // Addresses of the form FI+const or FI|const
285 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
286 return true;
287
288 // Operand is a result from an ADD.
289 if (Addr.getOpcode() == ISD::ADD) {
290 // When loading from constant pools, load the lower address part in
291 // the instruction itself. Example, instead of:
292 // lui $2, %hi($CPI1_0)
293 // addiu $2, $2, %lo($CPI1_0)
294 // lwc1 $f0, 0($2)
295 // Generate:
296 // lui $2, %hi($CPI1_0)
297 // lwc1 $f0, %lo($CPI1_0)($2)
298 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
299 Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
300 SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
301 if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
302 isa<JumpTableSDNode>(Opnd0)) {
303 Base = Addr.getOperand(0);
304 Offset = Opnd0;
305 return true;
306 }
307 }
308 }
309
310 return false;
311}
312
313/// ComplexPattern used on MipsInstrInfo
314/// Used on Mips Load/Store instructions
315bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
316 SDValue &Offset) const {
317 Base = Addr;
318 Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
319 return true;
320}
321
322bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
323 SDValue &Offset) const {
324 return selectAddrRegImm(Addr, Base, Offset) ||
325 selectAddrDefault(Addr, Base, Offset);
326}
327
328bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base,
329 SDValue &Offset) const {
330 if (selectAddrFrameIndex(Addr, Base, Offset))
331 return true;
332
333 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 9))
334 return true;
335
336 return false;
337}
338
339/// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
340bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base,
341 SDValue &Offset) const {
342 if (selectAddrFrameIndex(Addr, Base, Offset))
343 return true;
344
345 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 11))
346 return true;
347
348 return false;
349}
350
351/// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
352bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
353 SDValue &Offset) const {
354 if (selectAddrFrameIndex(Addr, Base, Offset))
355 return true;
356
357 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
358 return true;
359
360 return false;
361}
362
363bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr, SDValue &Base,
364 SDValue &Offset) const {
365 if (selectAddrFrameIndex(Addr, Base, Offset))
366 return true;
367
368 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
369 return true;
370
371 return false;
372}
373
374bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
375 SDValue &Offset) const {
376 return selectAddrRegImm11(Addr, Base, Offset) ||
377 selectAddrDefault(Addr, Base, Offset);
378}
379
380bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
381 SDValue &Offset) const {
382 return selectAddrRegImm12(Addr, Base, Offset) ||
383 selectAddrDefault(Addr, Base, Offset);
384}
385
386bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
387 SDValue &Offset) const {
388 return selectAddrRegImm16(Addr, Base, Offset) ||
389 selectAddrDefault(Addr, Base, Offset);
390}
391
392bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
393 SDValue &Offset) const {
394 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 7)) {
395 if (isa<FrameIndexSDNode>(Base))
396 return false;
397
398 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
399 unsigned CnstOff = CN->getZExtValue();
400 return (CnstOff == (CnstOff & 0x3c));
401 }
402
403 return false;
404 }
405
406 // For all other cases where "lw" would be selected, don't select "lw16"
407 // because it would result in additional instructions to prepare operands.
408 if (selectAddrRegImm(Addr, Base, Offset))
409 return false;
410
411 return selectAddrDefault(Addr, Base, Offset);
412}
413
414bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
415 SDValue &Offset) const {
416
417 if (selectAddrFrameIndex(Addr, Base, Offset))
418 return true;
419
420 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
421 return true;
422
423 return selectAddrDefault(Addr, Base, Offset);
424}
425
426bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
427 SDValue &Offset) const {
428 if (selectAddrFrameIndex(Addr, Base, Offset))
429 return true;
430
431 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1))
432 return true;
433
434 return selectAddrDefault(Addr, Base, Offset);
435}
436
437bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
438 SDValue &Offset) const {
439 if (selectAddrFrameIndex(Addr, Base, Offset))
440 return true;
441
442 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2))
443 return true;
444
445 return selectAddrDefault(Addr, Base, Offset);
446}
447
448bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
449 SDValue &Offset) const {
450 if (selectAddrFrameIndex(Addr, Base, Offset))
451 return true;
452
453 if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3))
454 return true;
455
456 return selectAddrDefault(Addr, Base, Offset);
457}
458
459// Select constant vector splats.
460//
461// Returns true and sets Imm if:
462// * MSA is enabled
463// * N is a ISD::BUILD_VECTOR representing a constant splat
464bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
465 unsigned MinSizeInBits) const {
466 if (!Subtarget->hasMSA())
467 return false;
468
469 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
470
471 if (!Node)
472 return false;
473
474 APInt SplatValue, SplatUndef;
475 unsigned SplatBitSize;
476 bool HasAnyUndefs;
477
478 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
479 MinSizeInBits, !Subtarget->isLittle()))
480 return false;
481
482 Imm = SplatValue;
483
484 return true;
485}
486
487// Select constant vector splats.
488//
489// In addition to the requirements of selectVSplat(), this function returns
490// true and sets Imm if:
491// * The splat value is the same width as the elements of the vector
492// * The splat value fits in an integer with the specified signed-ness and
493// width.
494//
495// This function looks through ISD::BITCAST nodes.
496// TODO: This might not be appropriate for big-endian MSA since BITCAST is
497// sometimes a shuffle in big-endian mode.
498//
499// It's worth noting that this function is not used as part of the selection
500// of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
501// instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
502// MipsSEDAGToDAGISel::selectNode.
503bool MipsSEDAGToDAGISel::
504selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
505 unsigned ImmBitSize) const {
506 APInt ImmValue;
507 EVT EltTy = N->getValueType(0).getVectorElementType();
508
509 if (N->getOpcode() == ISD::BITCAST)
510 N = N->getOperand(0);
511
512 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
513 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
514
515 if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
516 (!Signed && ImmValue.isIntN(ImmBitSize))) {
517 Imm = CurDAG->getTargetConstant(ImmValue, SDLoc(N), EltTy);
518 return true;
519 }
520 }
521
522 return false;
523}
524
525// Select constant vector splats.
526bool MipsSEDAGToDAGISel::
527selectVSplatUimm1(SDValue N, SDValue &Imm) const {
528 return selectVSplatCommon(N, Imm, false, 1);
529}
530
531bool MipsSEDAGToDAGISel::
532selectVSplatUimm2(SDValue N, SDValue &Imm) const {
533 return selectVSplatCommon(N, Imm, false, 2);
534}
535
536bool MipsSEDAGToDAGISel::
537selectVSplatUimm3(SDValue N, SDValue &Imm) const {
538 return selectVSplatCommon(N, Imm, false, 3);
539}
540
541// Select constant vector splats.
542bool MipsSEDAGToDAGISel::
543selectVSplatUimm4(SDValue N, SDValue &Imm) const {
544 return selectVSplatCommon(N, Imm, false, 4);
545}
546
547// Select constant vector splats.
548bool MipsSEDAGToDAGISel::
549selectVSplatUimm5(SDValue N, SDValue &Imm) const {
550 return selectVSplatCommon(N, Imm, false, 5);
551}
552
553// Select constant vector splats.
554bool MipsSEDAGToDAGISel::
555selectVSplatUimm6(SDValue N, SDValue &Imm) const {
556 return selectVSplatCommon(N, Imm, false, 6);
557}
558
559// Select constant vector splats.
560bool MipsSEDAGToDAGISel::
561selectVSplatUimm8(SDValue N, SDValue &Imm) const {
562 return selectVSplatCommon(N, Imm, false, 8);
563}
564
565// Select constant vector splats.
566bool MipsSEDAGToDAGISel::
567selectVSplatSimm5(SDValue N, SDValue &Imm) const {
568 return selectVSplatCommon(N, Imm, true, 5);
569}
570
571// Select constant vector splats whose value is a power of 2.
572//
573// In addition to the requirements of selectVSplat(), this function returns
574// true and sets Imm if:
575// * The splat value is the same width as the elements of the vector
576// * The splat value is a power of two.
577//
578// This function looks through ISD::BITCAST nodes.
579// TODO: This might not be appropriate for big-endian MSA since BITCAST is
580// sometimes a shuffle in big-endian mode.
581bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
582 APInt ImmValue;
583 EVT EltTy = N->getValueType(0).getVectorElementType();
584
585 if (N->getOpcode() == ISD::BITCAST)
586 N = N->getOperand(0);
587
588 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
589 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
590 int32_t Log2 = ImmValue.exactLogBase2();
591
592 if (Log2 != -1) {
593 Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
594 return true;
595 }
596 }
597
598 return false;
599}
600
601// Select constant vector splats whose value only has a consecutive sequence
602// of left-most bits set (e.g. 0b11...1100...00).
603//
604// In addition to the requirements of selectVSplat(), this function returns
605// true and sets Imm if:
606// * The splat value is the same width as the elements of the vector
607// * The splat value is a consecutive sequence of left-most bits.
608//
609// This function looks through ISD::BITCAST nodes.
610// TODO: This might not be appropriate for big-endian MSA since BITCAST is
611// sometimes a shuffle in big-endian mode.
612bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
613 APInt ImmValue;
614 EVT EltTy = N->getValueType(0).getVectorElementType();
615
616 if (N->getOpcode() == ISD::BITCAST)
617 N = N->getOperand(0);
618
619 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
620 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
621 // Extract the run of set bits starting with bit zero from the bitwise
622 // inverse of ImmValue, and test that the inverse of this is the same
623 // as the original value.
624 if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
625
626 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
627 EltTy);
628 return true;
629 }
630 }
631
632 return false;
633}
634
635// Select constant vector splats whose value only has a consecutive sequence
636// of right-most bits set (e.g. 0b00...0011...11).
637//
638// In addition to the requirements of selectVSplat(), this function returns
639// true and sets Imm if:
640// * The splat value is the same width as the elements of the vector
641// * The splat value is a consecutive sequence of right-most bits.
642//
643// This function looks through ISD::BITCAST nodes.
644// TODO: This might not be appropriate for big-endian MSA since BITCAST is
645// sometimes a shuffle in big-endian mode.
646bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
647 APInt ImmValue;
648 EVT EltTy = N->getValueType(0).getVectorElementType();
649
650 if (N->getOpcode() == ISD::BITCAST)
651 N = N->getOperand(0);
652
653 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
654 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
655 // Extract the run of set bits starting with bit zero, and test that the
656 // result is the same as the original value
657 if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
658 Imm = CurDAG->getTargetConstant(ImmValue.countPopulation() - 1, SDLoc(N),
659 EltTy);
660 return true;
661 }
662 }
663
664 return false;
665}
666
667bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
668 SDValue &Imm) const {
669 APInt ImmValue;
670 EVT EltTy = N->getValueType(0).getVectorElementType();
671
672 if (N->getOpcode() == ISD::BITCAST)
673 N = N->getOperand(0);
674
675 if (selectVSplat(N.getNode(), ImmValue, EltTy.getSizeInBits()) &&
676 ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
677 int32_t Log2 = (~ImmValue).exactLogBase2();
678
679 if (Log2 != -1) {
680 Imm = CurDAG->getTargetConstant(Log2, SDLoc(N), EltTy);
681 return true;
682 }
683 }
684
685 return false;
686}
687
688bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) {
689 unsigned Opcode = Node->getOpcode();
690 SDLoc DL(Node);
691
692 ///
693 // Instruction Selection not handled by the auto-generated
694 // tablegen selection should be handled here.
695 ///
696 switch(Opcode) {
1
Control jumps to 'case BUILD_VECTOR:' at line 920
697 default: break;
698
699 case Mips::PseudoD_SELECT_I:
700 case Mips::PseudoD_SELECT_I64: {
701 MVT VT = Subtarget->isGP64bit() ? MVT::i64 : MVT::i32;
702 SDValue cond = Node->getOperand(0);
703 SDValue Hi1 = Node->getOperand(1);
704 SDValue Lo1 = Node->getOperand(2);
705 SDValue Hi2 = Node->getOperand(3);
706 SDValue Lo2 = Node->getOperand(4);
707
708 SDValue ops[] = {cond, Hi1, Lo1, Hi2, Lo2};
709 EVT NodeTys[] = {VT, VT};
710 ReplaceNode(Node, CurDAG->getMachineNode(Subtarget->isGP64bit()
711 ? Mips::PseudoD_SELECT_I64
712 : Mips::PseudoD_SELECT_I,
713 DL, NodeTys, ops));
714 return true;
715 }
716
717 case ISD::ADDE: {
718 selectAddE(Node, DL);
719 return true;
720 }
721
722 case ISD::ConstantFP: {
723 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
724 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
725 if (Subtarget->isGP64bit()) {
726 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
727 Mips::ZERO_64, MVT::i64);
728 ReplaceNode(Node,
729 CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
730 } else if (Subtarget->isFP64bit()) {
731 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
732 Mips::ZERO, MVT::i32);
733 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64_64, DL,
734 MVT::f64, Zero, Zero));
735 } else {
736 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
737 Mips::ZERO, MVT::i32);
738 ReplaceNode(Node, CurDAG->getMachineNode(Mips::BuildPairF64, DL,
739 MVT::f64, Zero, Zero));
740 }
741 return true;
742 }
743 break;
744 }
745
746 case ISD::Constant: {
747 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
748 int64_t Imm = CN->getSExtValue();
749 unsigned Size = CN->getValueSizeInBits(0);
750
751 if (isInt<32>(Imm))
752 break;
753
754 MipsAnalyzeImmediate AnalyzeImm;
755
756 const MipsAnalyzeImmediate::InstSeq &Seq =
757 AnalyzeImm.Analyze(Imm, Size, false);
758
759 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
760 SDLoc DL(CN);
761 SDNode *RegOpnd;
762 SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
763 DL, MVT::i64);
764
765 // The first instruction can be a LUi which is different from other
766 // instructions (ADDiu, ORI and SLL) in that it does not have a register
767 // operand.
768 if (Inst->Opc == Mips::LUi64)
769 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
770 else
771 RegOpnd =
772 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
773 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
774 ImmOpnd);
775
776 // The remaining instructions in the sequence are handled here.
777 for (++Inst; Inst != Seq.end(); ++Inst) {
778 ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd), DL,
779 MVT::i64);
780 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
781 SDValue(RegOpnd, 0), ImmOpnd);
782 }
783
784 ReplaceNode(Node, RegOpnd);
785 return true;
786 }
787
788 case ISD::INTRINSIC_W_CHAIN: {
789 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
790 default:
791 break;
792
793 case Intrinsic::mips_cfcmsa: {
794 SDValue ChainIn = Node->getOperand(0);
795 SDValue RegIdx = Node->getOperand(2);
796 SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
797 getMSACtrlReg(RegIdx), MVT::i32);
798 ReplaceNode(Node, Reg.getNode());
799 return true;
800 }
801 }
802 break;
803 }
804
805 case ISD::INTRINSIC_WO_CHAIN: {
806 switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
807 default:
808 break;
809
810 case Intrinsic::mips_move_v:
811 // Like an assignment but will always produce a move.v even if
812 // unnecessary.
813 ReplaceNode(Node, CurDAG->getMachineNode(Mips::MOVE_V, DL,
814 Node->getValueType(0),
815 Node->getOperand(1)));
816 return true;
817 }
818 break;
819 }
820
821 case ISD::INTRINSIC_VOID: {
822 switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
823 default:
824 break;
825
826 case Intrinsic::mips_ctcmsa: {
827 SDValue ChainIn = Node->getOperand(0);
828 SDValue RegIdx = Node->getOperand(2);
829 SDValue Value = Node->getOperand(3);
830 SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
831 getMSACtrlReg(RegIdx), Value);
832 ReplaceNode(Node, ChainOut.getNode());
833 return true;
834 }
835 }
836 break;
837 }
838
839 // Manually match MipsISD::Ins nodes to get the correct instruction. It has
840 // to be done in this fashion so that we respect the differences between
841 // dins and dinsm, as the difference is that the size operand has the range
842 // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which
843 // means SelectionDAGISel would have to test all the operands at once to
844 // match the instruction.
845 case MipsISD::Ins: {
846
847 // Sanity checking for the node operands.
848 if (Node->getValueType(0) != MVT::i32 && Node->getValueType(0) != MVT::i64)
849 return false;
850
851 if (Node->getNumOperands() != 4)
852 return false;
853
854 if (Node->getOperand(1)->getOpcode() != ISD::Constant ||
855 Node->getOperand(2)->getOpcode() != ISD::Constant)
856 return false;
857
858 MVT ResTy = Node->getSimpleValueType(0);
859 uint64_t Pos = Node->getConstantOperandVal(1);
860 uint64_t Size = Node->getConstantOperandVal(2);
861
862 // Size has to be >0 for 'ins', 'dins' and 'dinsu'.
863 if (!Size)
864 return false;
865
866 if (Pos + Size > 64)
867 return false;
868
869 if (ResTy != MVT::i32 && ResTy != MVT::i64)
870 return false;
871
872 unsigned Opcode = 0;
873 if (ResTy == MVT::i32) {
874 if (Pos + Size <= 32)
875 Opcode = Mips::INS;
876 } else {
877 if (Pos + Size <= 32)
878 Opcode = Mips::DINS;
879 else if (Pos < 32 && 1 < Size)
880 Opcode = Mips::DINSM;
881 else
882 Opcode = Mips::DINSU;
883 }
884
885 if (Opcode) {
886 SDValue Ops[4] = {
887 Node->getOperand(0), CurDAG->getTargetConstant(Pos, DL, MVT::i32),
888 CurDAG->getTargetConstant(Size, DL, MVT::i32), Node->getOperand(3)};
889
890 ReplaceNode(Node, CurDAG->getMachineNode(Opcode, DL, ResTy, Ops));
891 return true;
892 }
893
894 return false;
895 }
896
897 case MipsISD::ThreadPointer: {
898 EVT PtrVT = getTargetLowering()->getPointerTy(CurDAG->getDataLayout());
899 unsigned RdhwrOpc, DestReg;
900
901 if (PtrVT == MVT::i32) {
902 RdhwrOpc = Mips::RDHWR;
903 DestReg = Mips::V1;
904 } else {
905 RdhwrOpc = Mips::RDHWR64;
906 DestReg = Mips::V1_64;
907 }
908
909 SDNode *Rdhwr =
910 CurDAG->getMachineNode(RdhwrOpc, DL, Node->getValueType(0),
911 CurDAG->getRegister(Mips::HWR29, MVT::i32),
912 CurDAG->getTargetConstant(0, DL, MVT::i32));
913 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
914 SDValue(Rdhwr, 0));
915 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
916 ReplaceNode(Node, ResNode.getNode());
917 return true;
918 }
919
920 case ISD::BUILD_VECTOR: {
921 // Select appropriate ldi.[bhwd] instructions for constant splats of
922 // 128-bit when MSA is enabled. Fixup any register class mismatches that
923 // occur as a result.
924 //
925 // This allows the compiler to use a wider range of immediates than would
926 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
927 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
928 // 0x01010101 } without using a constant pool. This would be sub-optimal
929 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
930 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
931 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
932
933 const MipsABIInfo &ABI =
934 static_cast<const MipsTargetMachine &>(TM).getABI();
935
936 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
2
'Node' is a 'BuildVectorSDNode'
937 APInt SplatValue, SplatUndef;
938 unsigned SplatBitSize;
939 bool HasAnyUndefs;
940 unsigned LdiOp;
941 EVT ResVecTy = BVN->getValueType(0);
942 EVT ViaVecTy;
943
944 if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
3
Assuming the condition is false
4
Assuming the condition is false
5
Taking false branch
945 return false;
946
947 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7
Assuming the condition is false
8
Taking false branch
948 HasAnyUndefs, 8,
949 !Subtarget->isLittle()))
6
Assuming the condition is false
950 return false;
951
952 switch (SplatBitSize) {
9
Control jumps to 'case 64:' at line 967
953 default:
954 return false;
955 case 8:
956 LdiOp = Mips::LDI_B;
957 ViaVecTy = MVT::v16i8;
958 break;
959 case 16:
960 LdiOp = Mips::LDI_H;
961 ViaVecTy = MVT::v8i16;
962 break;
963 case 32:
964 LdiOp = Mips::LDI_W;
965 ViaVecTy = MVT::v4i32;
966 break;
967 case 64:
968 LdiOp = Mips::LDI_D;
969 ViaVecTy = MVT::v2i64;
970 break;
10
Execution continues on line 973
971 }
972
973 SDNode *Res;
11
'Res' declared without an initial value
974
975 // If we have a signed 10 bit integer, we can splat it directly.
976 //
977 // If we have something bigger we can synthesize the value into a GPR and
978 // splat from there.
979 if (SplatValue.isSignedIntN(10)) {
12
Calling 'APInt::isSignedIntN'
16
Returning from 'APInt::isSignedIntN'
17
Taking false branch
980 SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
981 ViaVecTy.getVectorElementType());
982
983 Res = CurDAG->getMachineNode(LdiOp, DL, ViaVecTy, Imm);
984 } else if (SplatValue.isSignedIntN(16) &&
18
Calling 'APInt::isSignedIntN'
22
Returning from 'APInt::isSignedIntN'
985 ((ABI.IsO32() && SplatBitSize < 64) ||
986 (ABI.IsN32() || ABI.IsN64()))) {
987 // Only handle signed 16 bit values when the element size is GPR width.
988 // MIPS64 can handle all the cases but MIPS32 would need to handle
989 // negative cases specifically here. Instead, handle those cases as
990 // 64bit values.
991
992 bool Is32BitSplat = ABI.IsO32() || SplatBitSize < 64;
993 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu;
994 const MVT SplatMVT = Is32BitSplat ? MVT::i32 : MVT::i64;
995 SDValue ZeroVal = CurDAG->getRegister(
996 Is32BitSplat ? Mips::ZERO : Mips::ZERO_64, SplatMVT);
997
998 const unsigned FILLOp =
999 SplatBitSize == 16
1000 ? Mips::FILL_H
1001 : (SplatBitSize == 32 ? Mips::FILL_W
1002 : (SplatBitSize == 64 ? Mips::FILL_D : 0));
1003
1004 assert(FILLOp != 0 && "Unknown FILL Op for splat synthesis!")((FILLOp != 0 && "Unknown FILL Op for splat synthesis!"
) ? static_cast<void> (0) : __assert_fail ("FILLOp != 0 && \"Unknown FILL Op for splat synthesis!\""
, "/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1004, __PRETTY_FUNCTION__))
;
1005 assert((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) &&(((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) && "Attempting to use fill.d on MIPS32!"
) ? static_cast<void> (0) : __assert_fail ("(!ABI.IsO32() || (FILLOp != Mips::FILL_D)) && \"Attempting to use fill.d on MIPS32!\""
, "/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1006, __PRETTY_FUNCTION__))
1006 "Attempting to use fill.d on MIPS32!")(((!ABI.IsO32() || (FILLOp != Mips::FILL_D)) && "Attempting to use fill.d on MIPS32!"
) ? static_cast<void> (0) : __assert_fail ("(!ABI.IsO32() || (FILLOp != Mips::FILL_D)) && \"Attempting to use fill.d on MIPS32!\""
, "/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1006, __PRETTY_FUNCTION__))
;
1007
1008 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1009 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, SplatMVT);
1010
1011 Res = CurDAG->getMachineNode(ADDiuOp, DL, SplatMVT, ZeroVal, LoVal);
1012 Res = CurDAG->getMachineNode(FILLOp, DL, ViaVecTy, SDValue(Res, 0));
1013
1014 } else if (SplatValue.isSignedIntN(32) && SplatBitSize == 32) {
23
Calling 'APInt::isSignedIntN'
27
Returning from 'APInt::isSignedIntN'
1015 // Only handle the cases where the splat size agrees with the size
1016 // of the SplatValue here.
1017 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1018 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1019 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1020
1021 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1022 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1023
1024 if (Hi)
1025 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1026
1027 if (Lo)
1028 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1029 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1030
1031 assert((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!")(((Hi || Lo) && "Zero case reached 32 bit case splat synthesis!"
) ? static_cast<void> (0) : __assert_fail ("(Hi || Lo) && \"Zero case reached 32 bit case splat synthesis!\""
, "/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1031, __PRETTY_FUNCTION__))
;
1032 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32, SDValue(Res, 0));
1033
1034 } else if (SplatValue.isSignedIntN(32) && SplatBitSize
32.1
'SplatBitSize' is equal to 64
32.1
'SplatBitSize' is equal to 64
32.1
'SplatBitSize' is equal to 64
== 64 &&
28
Calling 'APInt::isSignedIntN'
32
Returning from 'APInt::isSignedIntN'
1035 (ABI.IsN32() || ABI.IsN64())) {
33
Calling 'MipsABIInfo::IsN32'
36
Returning from 'MipsABIInfo::IsN32'
1036 // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1037 // integers due to having 64bit registers. lui will cause the necessary
1038 // zero/sign extension.
1039 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1040 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1041 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1042
1043 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1044 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1045
1046 if (Hi)
37
Assuming 'Hi' is 0
38
Taking false branch
1047 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1048
1049 if (Lo)
39
Assuming 'Lo' is 0
40
Taking false branch
1050 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1051 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1052
1053 Res = CurDAG->getMachineNode(
1054 Mips::SUBREG_TO_REG, DL, MVT::i64,
1055 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1056 SDValue(Res, 0),
41
1st function call argument is an uninitialized value
1057 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1058
1059 Res =
1060 CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1061
1062 } else if (SplatValue.isSignedIntN(64)) {
1063 // If we have a 64 bit Splat value, we perform a similar sequence to the
1064 // above:
1065 //
1066 // MIPS32: MIPS64:
1067 // lui $res, %highest(val) lui $res, %highest(val)
1068 // ori $res, $res, %higher(val) ori $res, $res, %higher(val)
1069 // lui $res2, %hi(val) lui $res2, %hi(val)
1070 // ori $res2, %res2, %lo(val) ori $res2, %res2, %lo(val)
1071 // $res3 = fill $res2 dinsu $res, $res2, 0, 32
1072 // $res4 = insert.w $res3[1], $res fill.d $res
1073 // splat.d $res4, 0
1074 //
1075 // The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
1076 // having to materialize the value by shifts and ors.
1077 //
1078 // FIXME: Implement the preferred sequence for MIPS64R6:
1079 //
1080 // MIPS64R6:
1081 // ori $res, $zero, %lo(val)
1082 // daui $res, $res, %hi(val)
1083 // dahi $res, $res, %higher(val)
1084 // dati $res, $res, %highest(cal)
1085 // fill.d $res
1086 //
1087
1088 const unsigned Lo = SplatValue.getLoBits(16).getZExtValue();
1089 const unsigned Hi = SplatValue.lshr(16).getLoBits(16).getZExtValue();
1090 const unsigned Higher = SplatValue.lshr(32).getLoBits(16).getZExtValue();
1091 const unsigned Highest = SplatValue.lshr(48).getLoBits(16).getZExtValue();
1092
1093 SDValue LoVal = CurDAG->getTargetConstant(Lo, DL, MVT::i32);
1094 SDValue HiVal = CurDAG->getTargetConstant(Hi, DL, MVT::i32);
1095 SDValue HigherVal = CurDAG->getTargetConstant(Higher, DL, MVT::i32);
1096 SDValue HighestVal = CurDAG->getTargetConstant(Highest, DL, MVT::i32);
1097 SDValue ZeroVal = CurDAG->getRegister(Mips::ZERO, MVT::i32);
1098
1099 // Independent of whether we're targeting MIPS64 or not, the basic
1100 // operations are the same. Also, directly use the $zero register if
1101 // the 16 bit chunk is zero.
1102 //
1103 // For optimization purposes we always synthesize the splat value as
1104 // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1105 // just before combining the values with dinsu to produce an i64. This
1106 // enables SelectionDAG to aggressively share components of splat values
1107 // where possible.
1108 //
1109 // FIXME: This is the general constant synthesis problem. This code
1110 // should be factored out into a class shared between all the
1111 // classes that need it. Specifically, for a splat size of 64
1112 // bits that's a negative number we can do better than LUi/ORi
1113 // for the upper 32bits.
1114
1115 if (Hi)
1116 Res = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HiVal);
1117
1118 if (Lo)
1119 Res = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1120 Hi ? SDValue(Res, 0) : ZeroVal, LoVal);
1121
1122 SDNode *HiRes;
1123 if (Highest)
1124 HiRes = CurDAG->getMachineNode(Mips::LUi, DL, MVT::i32, HighestVal);
1125
1126 if (Higher)
1127 HiRes = CurDAG->getMachineNode(Mips::ORi, DL, MVT::i32,
1128 Highest ? SDValue(HiRes, 0) : ZeroVal,
1129 HigherVal);
1130
1131
1132 if (ABI.IsO32()) {
1133 Res = CurDAG->getMachineNode(Mips::FILL_W, DL, MVT::v4i32,
1134 (Hi || Lo) ? SDValue(Res, 0) : ZeroVal);
1135
1136 Res = CurDAG->getMachineNode(
1137 Mips::INSERT_W, DL, MVT::v4i32, SDValue(Res, 0),
1138 (Highest || Higher) ? SDValue(HiRes, 0) : ZeroVal,
1139 CurDAG->getTargetConstant(1, DL, MVT::i32));
1140
1141 const TargetLowering *TLI = getTargetLowering();
1142 const TargetRegisterClass *RC =
1143 TLI->getRegClassFor(ViaVecTy.getSimpleVT());
1144
1145 Res = CurDAG->getMachineNode(
1146 Mips::COPY_TO_REGCLASS, DL, ViaVecTy, SDValue(Res, 0),
1147 CurDAG->getTargetConstant(RC->getID(), DL, MVT::i32));
1148
1149 Res = CurDAG->getMachineNode(
1150 Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1151 CurDAG->getTargetConstant(0, DL, MVT::i32));
1152 } else if (ABI.IsN64() || ABI.IsN32()) {
1153
1154 SDValue Zero64Val = CurDAG->getRegister(Mips::ZERO_64, MVT::i64);
1155 const bool HiResNonZero = Highest || Higher;
1156 const bool ResNonZero = Hi || Lo;
1157
1158 if (HiResNonZero)
1159 HiRes = CurDAG->getMachineNode(
1160 Mips::SUBREG_TO_REG, DL, MVT::i64,
1161 CurDAG->getTargetConstant(((Highest >> 15) & 0x1), DL, MVT::i64),
1162 SDValue(HiRes, 0),
1163 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1164
1165 if (ResNonZero)
1166 Res = CurDAG->getMachineNode(
1167 Mips::SUBREG_TO_REG, DL, MVT::i64,
1168 CurDAG->getTargetConstant(((Hi >> 15) & 0x1), DL, MVT::i64),
1169 SDValue(Res, 0),
1170 CurDAG->getTargetConstant(Mips::sub_32, DL, MVT::i64));
1171
1172 // We have 3 cases:
1173 // The HiRes is nonzero but Res is $zero => dsll32 HiRes, 0
1174 // The Res is nonzero but HiRes is $zero => dinsu Res, $zero, 32, 32
1175 // Both are non zero => dinsu Res, HiRes, 32, 32
1176 //
1177 // The obvious "missing" case is when both are zero, but that case is
1178 // handled by the ldi case.
1179 if (ResNonZero) {
1180 IntegerType *Int32Ty =
1181 IntegerType::get(MF->getFunction().getContext(), 32);
1182 const ConstantInt *Const32 = ConstantInt::get(Int32Ty, 32);
1183 SDValue Ops[4] = {HiResNonZero ? SDValue(HiRes, 0) : Zero64Val,
1184 CurDAG->getConstant(*Const32, DL, MVT::i32),
1185 CurDAG->getConstant(*Const32, DL, MVT::i32),
1186 SDValue(Res, 0)};
1187
1188 Res = CurDAG->getMachineNode(Mips::DINSU, DL, MVT::i64, Ops);
1189 } else if (HiResNonZero) {
1190 Res = CurDAG->getMachineNode(
1191 Mips::DSLL32, DL, MVT::i64, SDValue(HiRes, 0),
1192 CurDAG->getTargetConstant(0, DL, MVT::i32));
1193 } else
1194 llvm_unreachable(::llvm::llvm_unreachable_internal("Zero splat value handled by non-zero 64bit splat synthesis!"
, "/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1195)
1195 "Zero splat value handled by non-zero 64bit splat synthesis!")::llvm::llvm_unreachable_internal("Zero splat value handled by non-zero 64bit splat synthesis!"
, "/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1195)
;
1196
1197 Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1198 } else
1199 llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!")::llvm::llvm_unreachable_internal("Unknown ABI in MipsISelDAGToDAG!"
, "/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1199)
;
1200
1201 } else
1202 return false;
1203
1204 if (ResVecTy != ViaVecTy) {
1205 // If LdiOp is writing to a different register class to ResVecTy, then
1206 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1207 // since the source and destination register sets contain the same
1208 // registers.
1209 const TargetLowering *TLI = getTargetLowering();
1210 MVT ResVecTySimple = ResVecTy.getSimpleVT();
1211 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
1212 Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, DL,
1213 ResVecTy, SDValue(Res, 0),
1214 CurDAG->getTargetConstant(RC->getID(), DL,
1215 MVT::i32));
1216 }
1217
1218 ReplaceNode(Node, Res);
1219 return true;
1220 }
1221
1222 }
1223
1224 return false;
1225}
1226
1227bool MipsSEDAGToDAGISel::
1228SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
1229 std::vector<SDValue> &OutOps) {
1230 SDValue Base, Offset;
1231
1232 switch(ConstraintID) {
1233 default:
1234 llvm_unreachable("Unexpected asm memory constraint")::llvm::llvm_unreachable_internal("Unexpected asm memory constraint"
, "/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MipsSEISelDAGToDAG.cpp"
, 1234)
;
1235 // All memory constraints can at least accept raw pointers.
1236 case InlineAsm::Constraint_i:
1237 OutOps.push_back(Op);
1238 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1239 return false;
1240 case InlineAsm::Constraint_m:
1241 case InlineAsm::Constraint_o:
1242 if (selectAddrRegImm16(Op, Base, Offset)) {
1243 OutOps.push_back(Base);
1244 OutOps.push_back(Offset);
1245 return false;
1246 }
1247 OutOps.push_back(Op);
1248 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1249 return false;
1250 case InlineAsm::Constraint_R:
1251 // The 'R' constraint is supposed to be much more complicated than this.
1252 // However, it's becoming less useful due to architectural changes and
1253 // ought to be replaced by other constraints such as 'ZC'.
1254 // For now, support 9-bit signed offsets which is supportable by all
1255 // subtargets for all instructions.
1256 if (selectAddrRegImm9(Op, Base, Offset)) {
1257 OutOps.push_back(Base);
1258 OutOps.push_back(Offset);
1259 return false;
1260 }
1261 OutOps.push_back(Op);
1262 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1263 return false;
1264 case InlineAsm::Constraint_ZC:
1265 // ZC matches whatever the pref, ll, and sc instructions can handle for the
1266 // given subtarget.
1267 if (Subtarget->inMicroMipsMode()) {
1268 // On microMIPS, they can handle 12-bit offsets.
1269 if (selectAddrRegImm12(Op, Base, Offset)) {
1270 OutOps.push_back(Base);
1271 OutOps.push_back(Offset);
1272 return false;
1273 }
1274 } else if (Subtarget->hasMips32r6()) {
1275 // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1276 if (selectAddrRegImm9(Op, Base, Offset)) {
1277 OutOps.push_back(Base);
1278 OutOps.push_back(Offset);
1279 return false;
1280 }
1281 } else if (selectAddrRegImm16(Op, Base, Offset)) {
1282 // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1283 OutOps.push_back(Base);
1284 OutOps.push_back(Offset);
1285 return false;
1286 }
1287 // In all cases, 0-bit offsets are acceptable.
1288 OutOps.push_back(Op);
1289 OutOps.push_back(CurDAG->getTargetConstant(0, SDLoc(Op), MVT::i32));
1290 return false;
1291 }
1292 return true;
1293}
1294
1295FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM,
1296 CodeGenOpt::Level OptLevel) {
1297 return new MipsSEDAGToDAGISel(TM, OptLevel);
1298}

/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h

1//===-- llvm/ADT/APInt.h - For Arbitrary Precision Integer -----*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements a class to represent arbitrary precision
11/// integral constant values and operations on them.
12///
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_ADT_APINT_H
16#define LLVM_ADT_APINT_H
17
18#include "llvm/Support/Compiler.h"
19#include "llvm/Support/MathExtras.h"
20#include <cassert>
21#include <climits>
22#include <cstring>
23#include <string>
24
25namespace llvm {
26class FoldingSetNodeID;
27class StringRef;
28class hash_code;
29class raw_ostream;
30
31template <typename T> class SmallVectorImpl;
32template <typename T> class ArrayRef;
33template <typename T> class Optional;
34
35class APInt;
36
37inline APInt operator-(APInt);
38
39//===----------------------------------------------------------------------===//
40// APInt Class
41//===----------------------------------------------------------------------===//
42
43/// Class for arbitrary precision integers.
44///
45/// APInt is a functional replacement for common case unsigned integer type like
46/// "unsigned", "unsigned long" or "uint64_t", but also allows non-byte-width
47/// integer sizes and large integer value types such as 3-bits, 15-bits, or more
48/// than 64-bits of precision. APInt provides a variety of arithmetic operators
49/// and methods to manipulate integer values of any bit-width. It supports both
50/// the typical integer arithmetic and comparison operations as well as bitwise
51/// manipulation.
52///
53/// The class has several invariants worth noting:
54/// * All bit, byte, and word positions are zero-based.
55/// * Once the bit width is set, it doesn't change except by the Truncate,
56/// SignExtend, or ZeroExtend operations.
57/// * All binary operators must be on APInt instances of the same bit width.
58/// Attempting to use these operators on instances with different bit
59/// widths will yield an assertion.
60/// * The value is stored canonically as an unsigned value. For operations
61/// where it makes a difference, there are both signed and unsigned variants
62/// of the operation. For example, sdiv and udiv. However, because the bit
63/// widths must be the same, operations such as Mul and Add produce the same
64/// results regardless of whether the values are interpreted as signed or
65/// not.
66/// * In general, the class tries to follow the style of computation that LLVM
67/// uses in its IR. This simplifies its use for LLVM.
68///
69class LLVM_NODISCARD[[clang::warn_unused_result]] APInt {
70public:
71 typedef uint64_t WordType;
72
73 /// This enum is used to hold the constants we needed for APInt.
74 enum : unsigned {
75 /// Byte size of a word.
76 APINT_WORD_SIZE = sizeof(WordType),
77 /// Bits in a word.
78 APINT_BITS_PER_WORD = APINT_WORD_SIZE * CHAR_BIT8
79 };
80
81 enum class Rounding {
82 DOWN,
83 TOWARD_ZERO,
84 UP,
85 };
86
87 static const WordType WORDTYPE_MAX = ~WordType(0);
88
89private:
90 /// This union is used to store the integer value. When the
91 /// integer bit-width <= 64, it uses VAL, otherwise it uses pVal.
92 union {
93 uint64_t VAL; ///< Used to store the <= 64 bits integer value.
94 uint64_t *pVal; ///< Used to store the >64 bits integer value.
95 } U;
96
97 unsigned BitWidth; ///< The number of bits in this APInt.
98
99 friend struct DenseMapAPIntKeyInfo;
100
101 friend class APSInt;
102
103 /// Fast internal constructor
104 ///
105 /// This constructor is used only internally for speed of construction of
106 /// temporaries. It is unsafe for general use so it is not public.
107 APInt(uint64_t *val, unsigned bits) : BitWidth(bits) {
108 U.pVal = val;
109 }
110
111 /// Determine if this APInt just has one word to store value.
112 ///
113 /// \returns true if the number of bits <= 64, false otherwise.
114 bool isSingleWord() const { return BitWidth <= APINT_BITS_PER_WORD; }
115
116 /// Determine which word a bit is in.
117 ///
118 /// \returns the word position for the specified bit position.
119 static unsigned whichWord(unsigned bitPosition) {
120 return bitPosition / APINT_BITS_PER_WORD;
121 }
122
123 /// Determine which bit in a word a bit is in.
124 ///
125 /// \returns the bit position in a word for the specified bit position
126 /// in the APInt.
127 static unsigned whichBit(unsigned bitPosition) {
128 return bitPosition % APINT_BITS_PER_WORD;
129 }
130
131 /// Get a single bit mask.
132 ///
133 /// \returns a uint64_t with only bit at "whichBit(bitPosition)" set
134 /// This method generates and returns a uint64_t (word) mask for a single
135 /// bit at a specific bit position. This is used to mask the bit in the
136 /// corresponding word.
137 static uint64_t maskBit(unsigned bitPosition) {
138 return 1ULL << whichBit(bitPosition);
139 }
140
141 /// Clear unused high order bits
142 ///
143 /// This method is used internally to clear the top "N" bits in the high order
144 /// word that are not used by the APInt. This is needed after the most
145 /// significant word is assigned a value to ensure that those bits are
146 /// zero'd out.
147 APInt &clearUnusedBits() {
148 // Compute how many bits are used in the final word
149 unsigned WordBits = ((BitWidth-1) % APINT_BITS_PER_WORD) + 1;
150
151 // Mask out the high bits.
152 uint64_t mask = WORDTYPE_MAX >> (APINT_BITS_PER_WORD - WordBits);
153 if (isSingleWord())
154 U.VAL &= mask;
155 else
156 U.pVal[getNumWords() - 1] &= mask;
157 return *this;
158 }
159
160 /// Get the word corresponding to a bit position
161 /// \returns the corresponding word for the specified bit position.
162 uint64_t getWord(unsigned bitPosition) const {
163 return isSingleWord() ? U.VAL : U.pVal[whichWord(bitPosition)];
164 }
165
166 /// Utility method to change the bit width of this APInt to new bit width,
167 /// allocating and/or deallocating as necessary. There is no guarantee on the
168 /// value of any bits upon return. Caller should populate the bits after.
169 void reallocate(unsigned NewBitWidth);
170
171 /// Convert a char array into an APInt
172 ///
173 /// \param radix 2, 8, 10, 16, or 36
174 /// Converts a string into a number. The string must be non-empty
175 /// and well-formed as a number of the given base. The bit-width
176 /// must be sufficient to hold the result.
177 ///
178 /// This is used by the constructors that take string arguments.
179 ///
180 /// StringRef::getAsInteger is superficially similar but (1) does
181 /// not assume that the string is well-formed and (2) grows the
182 /// result to hold the input.
183 void fromString(unsigned numBits, StringRef str, uint8_t radix);
184
185 /// An internal division function for dividing APInts.
186 ///
187 /// This is used by the toString method to divide by the radix. It simply
188 /// provides a more convenient form of divide for internal use since KnuthDiv
189 /// has specific constraints on its inputs. If those constraints are not met
190 /// then it provides a simpler form of divide.
191 static void divide(const WordType *LHS, unsigned lhsWords,
192 const WordType *RHS, unsigned rhsWords, WordType *Quotient,
193 WordType *Remainder);
194
195 /// out-of-line slow case for inline constructor
196 void initSlowCase(uint64_t val, bool isSigned);
197
198 /// shared code between two array constructors
199 void initFromArray(ArrayRef<uint64_t> array);
200
201 /// out-of-line slow case for inline copy constructor
202 void initSlowCase(const APInt &that);
203
204 /// out-of-line slow case for shl
205 void shlSlowCase(unsigned ShiftAmt);
206
207 /// out-of-line slow case for lshr.
208 void lshrSlowCase(unsigned ShiftAmt);
209
210 /// out-of-line slow case for ashr.
211 void ashrSlowCase(unsigned ShiftAmt);
212
213 /// out-of-line slow case for operator=
214 void AssignSlowCase(const APInt &RHS);
215
216 /// out-of-line slow case for operator==
217 bool EqualSlowCase(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__));
218
219 /// out-of-line slow case for countLeadingZeros
220 unsigned countLeadingZerosSlowCase() const LLVM_READONLY__attribute__((__pure__));
221
222 /// out-of-line slow case for countLeadingOnes.
223 unsigned countLeadingOnesSlowCase() const LLVM_READONLY__attribute__((__pure__));
224
225 /// out-of-line slow case for countTrailingZeros.
226 unsigned countTrailingZerosSlowCase() const LLVM_READONLY__attribute__((__pure__));
227
228 /// out-of-line slow case for countTrailingOnes
229 unsigned countTrailingOnesSlowCase() const LLVM_READONLY__attribute__((__pure__));
230
231 /// out-of-line slow case for countPopulation
232 unsigned countPopulationSlowCase() const LLVM_READONLY__attribute__((__pure__));
233
234 /// out-of-line slow case for intersects.
235 bool intersectsSlowCase(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__));
236
237 /// out-of-line slow case for isSubsetOf.
238 bool isSubsetOfSlowCase(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__));
239
240 /// out-of-line slow case for setBits.
241 void setBitsSlowCase(unsigned loBit, unsigned hiBit);
242
243 /// out-of-line slow case for flipAllBits.
244 void flipAllBitsSlowCase();
245
246 /// out-of-line slow case for operator&=.
247 void AndAssignSlowCase(const APInt& RHS);
248
249 /// out-of-line slow case for operator|=.
250 void OrAssignSlowCase(const APInt& RHS);
251
252 /// out-of-line slow case for operator^=.
253 void XorAssignSlowCase(const APInt& RHS);
254
255 /// Unsigned comparison. Returns -1, 0, or 1 if this APInt is less than, equal
256 /// to, or greater than RHS.
257 int compare(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__));
258
259 /// Signed comparison. Returns -1, 0, or 1 if this APInt is less than, equal
260 /// to, or greater than RHS.
261 int compareSigned(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__));
262
263public:
264 /// \name Constructors
265 /// @{
266
267 /// Create a new APInt of numBits width, initialized as val.
268 ///
269 /// If isSigned is true then val is treated as if it were a signed value
270 /// (i.e. as an int64_t) and the appropriate sign extension to the bit width
271 /// will be done. Otherwise, no sign extension occurs (high order bits beyond
272 /// the range of val are zero filled).
273 ///
274 /// \param numBits the bit width of the constructed APInt
275 /// \param val the initial value of the APInt
276 /// \param isSigned how to treat signedness of val
277 APInt(unsigned numBits, uint64_t val, bool isSigned = false)
278 : BitWidth(numBits) {
279 assert(BitWidth && "bitwidth too small")((BitWidth && "bitwidth too small") ? static_cast<
void> (0) : __assert_fail ("BitWidth && \"bitwidth too small\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 279, __PRETTY_FUNCTION__))
;
280 if (isSingleWord()) {
281 U.VAL = val;
282 clearUnusedBits();
283 } else {
284 initSlowCase(val, isSigned);
285 }
286 }
287
288 /// Construct an APInt of numBits width, initialized as bigVal[].
289 ///
290 /// Note that bigVal.size() can be smaller or larger than the corresponding
291 /// bit width but any extraneous bits will be dropped.
292 ///
293 /// \param numBits the bit width of the constructed APInt
294 /// \param bigVal a sequence of words to form the initial value of the APInt
295 APInt(unsigned numBits, ArrayRef<uint64_t> bigVal);
296
297 /// Equivalent to APInt(numBits, ArrayRef<uint64_t>(bigVal, numWords)), but
298 /// deprecated because this constructor is prone to ambiguity with the
299 /// APInt(unsigned, uint64_t, bool) constructor.
300 ///
301 /// If this overload is ever deleted, care should be taken to prevent calls
302 /// from being incorrectly captured by the APInt(unsigned, uint64_t, bool)
303 /// constructor.
304 APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[]);
305
306 /// Construct an APInt from a string representation.
307 ///
308 /// This constructor interprets the string \p str in the given radix. The
309 /// interpretation stops when the first character that is not suitable for the
310 /// radix is encountered, or the end of the string. Acceptable radix values
311 /// are 2, 8, 10, 16, and 36. It is an error for the value implied by the
312 /// string to require more bits than numBits.
313 ///
314 /// \param numBits the bit width of the constructed APInt
315 /// \param str the string to be interpreted
316 /// \param radix the radix to use for the conversion
317 APInt(unsigned numBits, StringRef str, uint8_t radix);
318
319 /// Simply makes *this a copy of that.
320 /// Copy Constructor.
321 APInt(const APInt &that) : BitWidth(that.BitWidth) {
322 if (isSingleWord())
323 U.VAL = that.U.VAL;
324 else
325 initSlowCase(that);
326 }
327
328 /// Move Constructor.
329 APInt(APInt &&that) : BitWidth(that.BitWidth) {
330 memcpy(&U, &that.U, sizeof(U));
331 that.BitWidth = 0;
332 }
333
334 /// Destructor.
335 ~APInt() {
336 if (needsCleanup())
337 delete[] U.pVal;
338 }
339
340 /// Default constructor that creates an uninteresting APInt
341 /// representing a 1-bit zero value.
342 ///
343 /// This is useful for object deserialization (pair this with the static
344 /// method Read).
345 explicit APInt() : BitWidth(1) { U.VAL = 0; }
346
347 /// Returns whether this instance allocated memory.
348 bool needsCleanup() const { return !isSingleWord(); }
349
350 /// Used to insert APInt objects, or objects that contain APInt objects, into
351 /// FoldingSets.
352 void Profile(FoldingSetNodeID &id) const;
353
354 /// @}
355 /// \name Value Tests
356 /// @{
357
358 /// Determine sign of this APInt.
359 ///
360 /// This tests the high bit of this APInt to determine if it is set.
361 ///
362 /// \returns true if this APInt is negative, false otherwise
363 bool isNegative() const { return (*this)[BitWidth - 1]; }
364
365 /// Determine if this APInt Value is non-negative (>= 0)
366 ///
367 /// This tests the high bit of the APInt to determine if it is unset.
368 bool isNonNegative() const { return !isNegative(); }
369
370 /// Determine if sign bit of this APInt is set.
371 ///
372 /// This tests the high bit of this APInt to determine if it is set.
373 ///
374 /// \returns true if this APInt has its sign bit set, false otherwise.
375 bool isSignBitSet() const { return (*this)[BitWidth-1]; }
376
377 /// Determine if sign bit of this APInt is clear.
378 ///
379 /// This tests the high bit of this APInt to determine if it is clear.
380 ///
381 /// \returns true if this APInt has its sign bit clear, false otherwise.
382 bool isSignBitClear() const { return !isSignBitSet(); }
383
384 /// Determine if this APInt Value is positive.
385 ///
386 /// This tests if the value of this APInt is positive (> 0). Note
387 /// that 0 is not a positive value.
388 ///
389 /// \returns true if this APInt is positive.
390 bool isStrictlyPositive() const { return isNonNegative() && !isNullValue(); }
391
392 /// Determine if all bits are set
393 ///
394 /// This checks to see if the value has all bits of the APInt are set or not.
395 bool isAllOnesValue() const {
396 if (isSingleWord())
397 return U.VAL == WORDTYPE_MAX >> (APINT_BITS_PER_WORD - BitWidth);
398 return countTrailingOnesSlowCase() == BitWidth;
399 }
400
401 /// Determine if all bits are clear
402 ///
403 /// This checks to see if the value has all bits of the APInt are clear or
404 /// not.
405 bool isNullValue() const { return !*this; }
406
407 /// Determine if this is a value of 1.
408 ///
409 /// This checks to see if the value of this APInt is one.
410 bool isOneValue() const {
411 if (isSingleWord())
412 return U.VAL == 1;
413 return countLeadingZerosSlowCase() == BitWidth - 1;
414 }
415
416 /// Determine if this is the largest unsigned value.
417 ///
418 /// This checks to see if the value of this APInt is the maximum unsigned
419 /// value for the APInt's bit width.
420 bool isMaxValue() const { return isAllOnesValue(); }
421
422 /// Determine if this is the largest signed value.
423 ///
424 /// This checks to see if the value of this APInt is the maximum signed
425 /// value for the APInt's bit width.
426 bool isMaxSignedValue() const {
427 if (isSingleWord())
428 return U.VAL == ((WordType(1) << (BitWidth - 1)) - 1);
429 return !isNegative() && countTrailingOnesSlowCase() == BitWidth - 1;
430 }
431
432 /// Determine if this is the smallest unsigned value.
433 ///
434 /// This checks to see if the value of this APInt is the minimum unsigned
435 /// value for the APInt's bit width.
436 bool isMinValue() const { return isNullValue(); }
437
438 /// Determine if this is the smallest signed value.
439 ///
440 /// This checks to see if the value of this APInt is the minimum signed
441 /// value for the APInt's bit width.
442 bool isMinSignedValue() const {
443 if (isSingleWord())
444 return U.VAL == (WordType(1) << (BitWidth - 1));
445 return isNegative() && countTrailingZerosSlowCase() == BitWidth - 1;
446 }
447
448 /// Check if this APInt has an N-bits unsigned integer value.
449 bool isIntN(unsigned N) const {
450 assert(N && "N == 0 ???")((N && "N == 0 ???") ? static_cast<void> (0) : __assert_fail
("N && \"N == 0 ???\"", "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 450, __PRETTY_FUNCTION__))
;
451 return getActiveBits() <= N;
452 }
453
454 /// Check if this APInt has an N-bits signed integer value.
455 bool isSignedIntN(unsigned N) const {
456 assert
12.1
'N' is 10
18.1
'N' is 16
23.1
'N' is 32
28.1
'N' is 32
12.1
'N' is 10
18.1
'N' is 16
23.1
'N' is 32
28.1
'N' is 32
12.1
'N' is 10
18.1
'N' is 16
23.1
'N' is 32
28.1
'N' is 32
(N && "N == 0 ???")((N && "N == 0 ???") ? static_cast<void> (0) : __assert_fail
("N && \"N == 0 ???\"", "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 456, __PRETTY_FUNCTION__))
;
13
'?' condition is true
19
'?' condition is true
24
'?' condition is true
29
'?' condition is true
457 return getMinSignedBits() <= N;
14
Assuming the condition is false
15
Returning zero, which participates in a condition later
20
Assuming the condition is false
21
Returning zero, which participates in a condition later
25
Assuming the condition is false
26
Returning zero, which participates in a condition later
30
Assuming the condition is true
31
Returning the value 1, which participates in a condition later
458 }
459
460 /// Check if this APInt's value is a power of two greater than zero.
461 ///
462 /// \returns true if the argument APInt value is a power of two > 0.
463 bool isPowerOf2() const {
464 if (isSingleWord())
465 return isPowerOf2_64(U.VAL);
466 return countPopulationSlowCase() == 1;
467 }
468
469 /// Check if the APInt's value is returned by getSignMask.
470 ///
471 /// \returns true if this is the value returned by getSignMask.
472 bool isSignMask() const { return isMinSignedValue(); }
473
474 /// Convert APInt to a boolean value.
475 ///
476 /// This converts the APInt to a boolean value as a test against zero.
477 bool getBoolValue() const { return !!*this; }
478
479 /// If this value is smaller than the specified limit, return it, otherwise
480 /// return the limit value. This causes the value to saturate to the limit.
481 uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) const {
482 return ugt(Limit) ? Limit : getZExtValue();
483 }
484
485 /// Check if the APInt consists of a repeated bit pattern.
486 ///
487 /// e.g. 0x01010101 satisfies isSplat(8).
488 /// \param SplatSizeInBits The size of the pattern in bits. Must divide bit
489 /// width without remainder.
490 bool isSplat(unsigned SplatSizeInBits) const;
491
492 /// \returns true if this APInt value is a sequence of \param numBits ones
493 /// starting at the least significant bit with the remainder zero.
494 bool isMask(unsigned numBits) const {
495 assert(numBits != 0 && "numBits must be non-zero")((numBits != 0 && "numBits must be non-zero") ? static_cast
<void> (0) : __assert_fail ("numBits != 0 && \"numBits must be non-zero\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 495, __PRETTY_FUNCTION__))
;
496 assert(numBits <= BitWidth && "numBits out of range")((numBits <= BitWidth && "numBits out of range") ?
static_cast<void> (0) : __assert_fail ("numBits <= BitWidth && \"numBits out of range\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 496, __PRETTY_FUNCTION__))
;
497 if (isSingleWord())
498 return U.VAL == (WORDTYPE_MAX >> (APINT_BITS_PER_WORD - numBits));
499 unsigned Ones = countTrailingOnesSlowCase();
500 return (numBits == Ones) &&
501 ((Ones + countLeadingZerosSlowCase()) == BitWidth);
502 }
503
504 /// \returns true if this APInt is a non-empty sequence of ones starting at
505 /// the least significant bit with the remainder zero.
506 /// Ex. isMask(0x0000FFFFU) == true.
507 bool isMask() const {
508 if (isSingleWord())
509 return isMask_64(U.VAL);
510 unsigned Ones = countTrailingOnesSlowCase();
511 return (Ones > 0) && ((Ones + countLeadingZerosSlowCase()) == BitWidth);
512 }
513
514 /// Return true if this APInt value contains a sequence of ones with
515 /// the remainder zero.
516 bool isShiftedMask() const {
517 if (isSingleWord())
518 return isShiftedMask_64(U.VAL);
519 unsigned Ones = countPopulationSlowCase();
520 unsigned LeadZ = countLeadingZerosSlowCase();
521 return (Ones + LeadZ + countTrailingZeros()) == BitWidth;
522 }
523
524 /// @}
525 /// \name Value Generators
526 /// @{
527
528 /// Gets maximum unsigned value of APInt for specific bit width.
529 static APInt getMaxValue(unsigned numBits) {
530 return getAllOnesValue(numBits);
531 }
532
533 /// Gets maximum signed value of APInt for a specific bit width.
534 static APInt getSignedMaxValue(unsigned numBits) {
535 APInt API = getAllOnesValue(numBits);
536 API.clearBit(numBits - 1);
537 return API;
538 }
539
540 /// Gets minimum unsigned value of APInt for a specific bit width.
541 static APInt getMinValue(unsigned numBits) { return APInt(numBits, 0); }
542
543 /// Gets minimum signed value of APInt for a specific bit width.
544 static APInt getSignedMinValue(unsigned numBits) {
545 APInt API(numBits, 0);
546 API.setBit(numBits - 1);
547 return API;
548 }
549
550 /// Get the SignMask for a specific bit width.
551 ///
552 /// This is just a wrapper function of getSignedMinValue(), and it helps code
553 /// readability when we want to get a SignMask.
554 static APInt getSignMask(unsigned BitWidth) {
555 return getSignedMinValue(BitWidth);
556 }
557
558 /// Get the all-ones value.
559 ///
560 /// \returns the all-ones value for an APInt of the specified bit-width.
561 static APInt getAllOnesValue(unsigned numBits) {
562 return APInt(numBits, WORDTYPE_MAX, true);
563 }
564
565 /// Get the '0' value.
566 ///
567 /// \returns the '0' value for an APInt of the specified bit-width.
568 static APInt getNullValue(unsigned numBits) { return APInt(numBits, 0); }
569
570 /// Compute an APInt containing numBits highbits from this APInt.
571 ///
572 /// Get an APInt with the same BitWidth as this APInt, just zero mask
573 /// the low bits and right shift to the least significant bit.
574 ///
575 /// \returns the high "numBits" bits of this APInt.
576 APInt getHiBits(unsigned numBits) const;
577
578 /// Compute an APInt containing numBits lowbits from this APInt.
579 ///
580 /// Get an APInt with the same BitWidth as this APInt, just zero mask
581 /// the high bits.
582 ///
583 /// \returns the low "numBits" bits of this APInt.
584 APInt getLoBits(unsigned numBits) const;
585
586 /// Return an APInt with exactly one bit set in the result.
587 static APInt getOneBitSet(unsigned numBits, unsigned BitNo) {
588 APInt Res(numBits, 0);
589 Res.setBit(BitNo);
590 return Res;
591 }
592
593 /// Get a value with a block of bits set.
594 ///
595 /// Constructs an APInt value that has a contiguous range of bits set. The
596 /// bits from loBit (inclusive) to hiBit (exclusive) will be set. All other
597 /// bits will be zero. For example, with parameters(32, 0, 16) you would get
598 /// 0x0000FFFF. If hiBit is less than loBit then the set bits "wrap". For
599 /// example, with parameters (32, 28, 4), you would get 0xF000000F.
600 ///
601 /// \param numBits the intended bit width of the result
602 /// \param loBit the index of the lowest bit set.
603 /// \param hiBit the index of the highest bit set.
604 ///
605 /// \returns An APInt value with the requested bits set.
606 static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit) {
607 APInt Res(numBits, 0);
608 Res.setBits(loBit, hiBit);
609 return Res;
610 }
611
612 /// Get a value with upper bits starting at loBit set.
613 ///
614 /// Constructs an APInt value that has a contiguous range of bits set. The
615 /// bits from loBit (inclusive) to numBits (exclusive) will be set. All other
616 /// bits will be zero. For example, with parameters(32, 12) you would get
617 /// 0xFFFFF000.
618 ///
619 /// \param numBits the intended bit width of the result
620 /// \param loBit the index of the lowest bit to set.
621 ///
622 /// \returns An APInt value with the requested bits set.
623 static APInt getBitsSetFrom(unsigned numBits, unsigned loBit) {
624 APInt Res(numBits, 0);
625 Res.setBitsFrom(loBit);
626 return Res;
627 }
628
629 /// Get a value with high bits set
630 ///
631 /// Constructs an APInt value that has the top hiBitsSet bits set.
632 ///
633 /// \param numBits the bitwidth of the result
634 /// \param hiBitsSet the number of high-order bits set in the result.
635 static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet) {
636 APInt Res(numBits, 0);
637 Res.setHighBits(hiBitsSet);
638 return Res;
639 }
640
641 /// Get a value with low bits set
642 ///
643 /// Constructs an APInt value that has the bottom loBitsSet bits set.
644 ///
645 /// \param numBits the bitwidth of the result
646 /// \param loBitsSet the number of low-order bits set in the result.
647 static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet) {
648 APInt Res(numBits, 0);
649 Res.setLowBits(loBitsSet);
650 return Res;
651 }
652
653 /// Return a value containing V broadcasted over NewLen bits.
654 static APInt getSplat(unsigned NewLen, const APInt &V);
655
656 /// Determine if two APInts have the same value, after zero-extending
657 /// one of them (if needed!) to ensure that the bit-widths match.
658 static bool isSameValue(const APInt &I1, const APInt &I2) {
659 if (I1.getBitWidth() == I2.getBitWidth())
660 return I1 == I2;
661
662 if (I1.getBitWidth() > I2.getBitWidth())
663 return I1 == I2.zext(I1.getBitWidth());
664
665 return I1.zext(I2.getBitWidth()) == I2;
666 }
667
668 /// Overload to compute a hash_code for an APInt value.
669 friend hash_code hash_value(const APInt &Arg);
670
671 /// This function returns a pointer to the internal storage of the APInt.
672 /// This is useful for writing out the APInt in binary form without any
673 /// conversions.
674 const uint64_t *getRawData() const {
675 if (isSingleWord())
676 return &U.VAL;
677 return &U.pVal[0];
678 }
679
680 /// @}
681 /// \name Unary Operators
682 /// @{
683
684 /// Postfix increment operator.
685 ///
686 /// Increments *this by 1.
687 ///
688 /// \returns a new APInt value representing the original value of *this.
689 const APInt operator++(int) {
690 APInt API(*this);
691 ++(*this);
692 return API;
693 }
694
695 /// Prefix increment operator.
696 ///
697 /// \returns *this incremented by one
698 APInt &operator++();
699
700 /// Postfix decrement operator.
701 ///
702 /// Decrements *this by 1.
703 ///
704 /// \returns a new APInt value representing the original value of *this.
705 const APInt operator--(int) {
706 APInt API(*this);
707 --(*this);
708 return API;
709 }
710
711 /// Prefix decrement operator.
712 ///
713 /// \returns *this decremented by one.
714 APInt &operator--();
715
716 /// Logical negation operator.
717 ///
718 /// Performs logical negation operation on this APInt.
719 ///
720 /// \returns true if *this is zero, false otherwise.
721 bool operator!() const {
722 if (isSingleWord())
723 return U.VAL == 0;
724 return countLeadingZerosSlowCase() == BitWidth;
725 }
726
727 /// @}
728 /// \name Assignment Operators
729 /// @{
730
731 /// Copy assignment operator.
732 ///
733 /// \returns *this after assignment of RHS.
734 APInt &operator=(const APInt &RHS) {
735 // If the bitwidths are the same, we can avoid mucking with memory
736 if (isSingleWord() && RHS.isSingleWord()) {
737 U.VAL = RHS.U.VAL;
738 BitWidth = RHS.BitWidth;
739 return clearUnusedBits();
740 }
741
742 AssignSlowCase(RHS);
743 return *this;
744 }
745
746 /// Move assignment operator.
747 APInt &operator=(APInt &&that) {
748#ifdef _MSC_VER
749 // The MSVC std::shuffle implementation still does self-assignment.
750 if (this == &that)
751 return *this;
752#endif
753 assert(this != &that && "Self-move not supported")((this != &that && "Self-move not supported") ? static_cast
<void> (0) : __assert_fail ("this != &that && \"Self-move not supported\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 753, __PRETTY_FUNCTION__))
;
754 if (!isSingleWord())
755 delete[] U.pVal;
756
757 // Use memcpy so that type based alias analysis sees both VAL and pVal
758 // as modified.
759 memcpy(&U, &that.U, sizeof(U));
760
761 BitWidth = that.BitWidth;
762 that.BitWidth = 0;
763
764 return *this;
765 }
766
767 /// Assignment operator.
768 ///
769 /// The RHS value is assigned to *this. If the significant bits in RHS exceed
770 /// the bit width, the excess bits are truncated. If the bit width is larger
771 /// than 64, the value is zero filled in the unspecified high order bits.
772 ///
773 /// \returns *this after assignment of RHS value.
774 APInt &operator=(uint64_t RHS) {
775 if (isSingleWord()) {
776 U.VAL = RHS;
777 clearUnusedBits();
778 } else {
779 U.pVal[0] = RHS;
780 memset(U.pVal+1, 0, (getNumWords() - 1) * APINT_WORD_SIZE);
781 }
782 return *this;
783 }
784
785 /// Bitwise AND assignment operator.
786 ///
787 /// Performs a bitwise AND operation on this APInt and RHS. The result is
788 /// assigned to *this.
789 ///
790 /// \returns *this after ANDing with RHS.
791 APInt &operator&=(const APInt &RHS) {
792 assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")((BitWidth == RHS.BitWidth && "Bit widths must be the same"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 792, __PRETTY_FUNCTION__))
;
793 if (isSingleWord())
794 U.VAL &= RHS.U.VAL;
795 else
796 AndAssignSlowCase(RHS);
797 return *this;
798 }
799
800 /// Bitwise AND assignment operator.
801 ///
802 /// Performs a bitwise AND operation on this APInt and RHS. RHS is
803 /// logically zero-extended or truncated to match the bit-width of
804 /// the LHS.
805 APInt &operator&=(uint64_t RHS) {
806 if (isSingleWord()) {
807 U.VAL &= RHS;
808 return *this;
809 }
810 U.pVal[0] &= RHS;
811 memset(U.pVal+1, 0, (getNumWords() - 1) * APINT_WORD_SIZE);
812 return *this;
813 }
814
815 /// Bitwise OR assignment operator.
816 ///
817 /// Performs a bitwise OR operation on this APInt and RHS. The result is
818 /// assigned *this;
819 ///
820 /// \returns *this after ORing with RHS.
821 APInt &operator|=(const APInt &RHS) {
822 assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")((BitWidth == RHS.BitWidth && "Bit widths must be the same"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 822, __PRETTY_FUNCTION__))
;
823 if (isSingleWord())
824 U.VAL |= RHS.U.VAL;
825 else
826 OrAssignSlowCase(RHS);
827 return *this;
828 }
829
830 /// Bitwise OR assignment operator.
831 ///
832 /// Performs a bitwise OR operation on this APInt and RHS. RHS is
833 /// logically zero-extended or truncated to match the bit-width of
834 /// the LHS.
835 APInt &operator|=(uint64_t RHS) {
836 if (isSingleWord()) {
837 U.VAL |= RHS;
838 clearUnusedBits();
839 } else {
840 U.pVal[0] |= RHS;
841 }
842 return *this;
843 }
844
845 /// Bitwise XOR assignment operator.
846 ///
847 /// Performs a bitwise XOR operation on this APInt and RHS. The result is
848 /// assigned to *this.
849 ///
850 /// \returns *this after XORing with RHS.
851 APInt &operator^=(const APInt &RHS) {
852 assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")((BitWidth == RHS.BitWidth && "Bit widths must be the same"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 852, __PRETTY_FUNCTION__))
;
853 if (isSingleWord())
854 U.VAL ^= RHS.U.VAL;
855 else
856 XorAssignSlowCase(RHS);
857 return *this;
858 }
859
860 /// Bitwise XOR assignment operator.
861 ///
862 /// Performs a bitwise XOR operation on this APInt and RHS. RHS is
863 /// logically zero-extended or truncated to match the bit-width of
864 /// the LHS.
865 APInt &operator^=(uint64_t RHS) {
866 if (isSingleWord()) {
867 U.VAL ^= RHS;
868 clearUnusedBits();
869 } else {
870 U.pVal[0] ^= RHS;
871 }
872 return *this;
873 }
874
875 /// Multiplication assignment operator.
876 ///
877 /// Multiplies this APInt by RHS and assigns the result to *this.
878 ///
879 /// \returns *this
880 APInt &operator*=(const APInt &RHS);
881 APInt &operator*=(uint64_t RHS);
882
883 /// Addition assignment operator.
884 ///
885 /// Adds RHS to *this and assigns the result to *this.
886 ///
887 /// \returns *this
888 APInt &operator+=(const APInt &RHS);
889 APInt &operator+=(uint64_t RHS);
890
891 /// Subtraction assignment operator.
892 ///
893 /// Subtracts RHS from *this and assigns the result to *this.
894 ///
895 /// \returns *this
896 APInt &operator-=(const APInt &RHS);
897 APInt &operator-=(uint64_t RHS);
898
899 /// Left-shift assignment function.
900 ///
901 /// Shifts *this left by shiftAmt and assigns the result to *this.
902 ///
903 /// \returns *this after shifting left by ShiftAmt
904 APInt &operator<<=(unsigned ShiftAmt) {
905 assert(ShiftAmt <= BitWidth && "Invalid shift amount")((ShiftAmt <= BitWidth && "Invalid shift amount") ?
static_cast<void> (0) : __assert_fail ("ShiftAmt <= BitWidth && \"Invalid shift amount\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 905, __PRETTY_FUNCTION__))
;
906 if (isSingleWord()) {
907 if (ShiftAmt == BitWidth)
908 U.VAL = 0;
909 else
910 U.VAL <<= ShiftAmt;
911 return clearUnusedBits();
912 }
913 shlSlowCase(ShiftAmt);
914 return *this;
915 }
916
917 /// Left-shift assignment function.
918 ///
919 /// Shifts *this left by shiftAmt and assigns the result to *this.
920 ///
921 /// \returns *this after shifting left by ShiftAmt
922 APInt &operator<<=(const APInt &ShiftAmt);
923
924 /// @}
925 /// \name Binary Operators
926 /// @{
927
928 /// Multiplication operator.
929 ///
930 /// Multiplies this APInt by RHS and returns the result.
931 APInt operator*(const APInt &RHS) const;
932
933 /// Left logical shift operator.
934 ///
935 /// Shifts this APInt left by \p Bits and returns the result.
936 APInt operator<<(unsigned Bits) const { return shl(Bits); }
937
938 /// Left logical shift operator.
939 ///
940 /// Shifts this APInt left by \p Bits and returns the result.
941 APInt operator<<(const APInt &Bits) const { return shl(Bits); }
942
943 /// Arithmetic right-shift function.
944 ///
945 /// Arithmetic right-shift this APInt by shiftAmt.
946 APInt ashr(unsigned ShiftAmt) const {
947 APInt R(*this);
948 R.ashrInPlace(ShiftAmt);
949 return R;
950 }
951
952 /// Arithmetic right-shift this APInt by ShiftAmt in place.
953 void ashrInPlace(unsigned ShiftAmt) {
954 assert(ShiftAmt <= BitWidth && "Invalid shift amount")((ShiftAmt <= BitWidth && "Invalid shift amount") ?
static_cast<void> (0) : __assert_fail ("ShiftAmt <= BitWidth && \"Invalid shift amount\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 954, __PRETTY_FUNCTION__))
;
955 if (isSingleWord()) {
956 int64_t SExtVAL = SignExtend64(U.VAL, BitWidth);
957 if (ShiftAmt == BitWidth)
958 U.VAL = SExtVAL >> (APINT_BITS_PER_WORD - 1); // Fill with sign bit.
959 else
960 U.VAL = SExtVAL >> ShiftAmt;
961 clearUnusedBits();
962 return;
963 }
964 ashrSlowCase(ShiftAmt);
965 }
966
967 /// Logical right-shift function.
968 ///
969 /// Logical right-shift this APInt by shiftAmt.
970 APInt lshr(unsigned shiftAmt) const {
971 APInt R(*this);
972 R.lshrInPlace(shiftAmt);
973 return R;
974 }
975
976 /// Logical right-shift this APInt by ShiftAmt in place.
977 void lshrInPlace(unsigned ShiftAmt) {
978 assert(ShiftAmt <= BitWidth && "Invalid shift amount")((ShiftAmt <= BitWidth && "Invalid shift amount") ?
static_cast<void> (0) : __assert_fail ("ShiftAmt <= BitWidth && \"Invalid shift amount\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 978, __PRETTY_FUNCTION__))
;
979 if (isSingleWord()) {
980 if (ShiftAmt == BitWidth)
981 U.VAL = 0;
982 else
983 U.VAL >>= ShiftAmt;
984 return;
985 }
986 lshrSlowCase(ShiftAmt);
987 }
988
989 /// Left-shift function.
990 ///
991 /// Left-shift this APInt by shiftAmt.
992 APInt shl(unsigned shiftAmt) const {
993 APInt R(*this);
994 R <<= shiftAmt;
995 return R;
996 }
997
998 /// Rotate left by rotateAmt.
999 APInt rotl(unsigned rotateAmt) const;
1000
1001 /// Rotate right by rotateAmt.
1002 APInt rotr(unsigned rotateAmt) const;
1003
1004 /// Arithmetic right-shift function.
1005 ///
1006 /// Arithmetic right-shift this APInt by shiftAmt.
1007 APInt ashr(const APInt &ShiftAmt) const {
1008 APInt R(*this);
1009 R.ashrInPlace(ShiftAmt);
1010 return R;
1011 }
1012
1013 /// Arithmetic right-shift this APInt by shiftAmt in place.
1014 void ashrInPlace(const APInt &shiftAmt);
1015
1016 /// Logical right-shift function.
1017 ///
1018 /// Logical right-shift this APInt by shiftAmt.
1019 APInt lshr(const APInt &ShiftAmt) const {
1020 APInt R(*this);
1021 R.lshrInPlace(ShiftAmt);
1022 return R;
1023 }
1024
1025 /// Logical right-shift this APInt by ShiftAmt in place.
1026 void lshrInPlace(const APInt &ShiftAmt);
1027
1028 /// Left-shift function.
1029 ///
1030 /// Left-shift this APInt by shiftAmt.
1031 APInt shl(const APInt &ShiftAmt) const {
1032 APInt R(*this);
1033 R <<= ShiftAmt;
1034 return R;
1035 }
1036
1037 /// Rotate left by rotateAmt.
1038 APInt rotl(const APInt &rotateAmt) const;
1039
1040 /// Rotate right by rotateAmt.
1041 APInt rotr(const APInt &rotateAmt) const;
1042
1043 /// Unsigned division operation.
1044 ///
1045 /// Perform an unsigned divide operation on this APInt by RHS. Both this and
1046 /// RHS are treated as unsigned quantities for purposes of this division.
1047 ///
1048 /// \returns a new APInt value containing the division result, rounded towards
1049 /// zero.
1050 APInt udiv(const APInt &RHS) const;
1051 APInt udiv(uint64_t RHS) const;
1052
1053 /// Signed division function for APInt.
1054 ///
1055 /// Signed divide this APInt by APInt RHS.
1056 ///
1057 /// The result is rounded towards zero.
1058 APInt sdiv(const APInt &RHS) const;
1059 APInt sdiv(int64_t RHS) const;
1060
1061 /// Unsigned remainder operation.
1062 ///
1063 /// Perform an unsigned remainder operation on this APInt with RHS being the
1064 /// divisor. Both this and RHS are treated as unsigned quantities for purposes
1065 /// of this operation. Note that this is a true remainder operation and not a
1066 /// modulo operation because the sign follows the sign of the dividend which
1067 /// is *this.
1068 ///
1069 /// \returns a new APInt value containing the remainder result
1070 APInt urem(const APInt &RHS) const;
1071 uint64_t urem(uint64_t RHS) const;
1072
1073 /// Function for signed remainder operation.
1074 ///
1075 /// Signed remainder operation on APInt.
1076 APInt srem(const APInt &RHS) const;
1077 int64_t srem(int64_t RHS) const;
1078
1079 /// Dual division/remainder interface.
1080 ///
1081 /// Sometimes it is convenient to divide two APInt values and obtain both the
1082 /// quotient and remainder. This function does both operations in the same
1083 /// computation making it a little more efficient. The pair of input arguments
1084 /// may overlap with the pair of output arguments. It is safe to call
1085 /// udivrem(X, Y, X, Y), for example.
1086 static void udivrem(const APInt &LHS, const APInt &RHS, APInt &Quotient,
1087 APInt &Remainder);
1088 static void udivrem(const APInt &LHS, uint64_t RHS, APInt &Quotient,
1089 uint64_t &Remainder);
1090
1091 static void sdivrem(const APInt &LHS, const APInt &RHS, APInt &Quotient,
1092 APInt &Remainder);
1093 static void sdivrem(const APInt &LHS, int64_t RHS, APInt &Quotient,
1094 int64_t &Remainder);
1095
1096 // Operations that return overflow indicators.
1097 APInt sadd_ov(const APInt &RHS, bool &Overflow) const;
1098 APInt uadd_ov(const APInt &RHS, bool &Overflow) const;
1099 APInt ssub_ov(const APInt &RHS, bool &Overflow) const;
1100 APInt usub_ov(const APInt &RHS, bool &Overflow) const;
1101 APInt sdiv_ov(const APInt &RHS, bool &Overflow) const;
1102 APInt smul_ov(const APInt &RHS, bool &Overflow) const;
1103 APInt umul_ov(const APInt &RHS, bool &Overflow) const;
1104 APInt sshl_ov(const APInt &Amt, bool &Overflow) const;
1105 APInt ushl_ov(const APInt &Amt, bool &Overflow) const;
1106
1107 // Operations that saturate
1108 APInt sadd_sat(const APInt &RHS) const;
1109 APInt uadd_sat(const APInt &RHS) const;
1110 APInt ssub_sat(const APInt &RHS) const;
1111 APInt usub_sat(const APInt &RHS) const;
1112
1113 /// Array-indexing support.
1114 ///
1115 /// \returns the bit value at bitPosition
1116 bool operator[](unsigned bitPosition) const {
1117 assert(bitPosition < getBitWidth() && "Bit position out of bounds!")((bitPosition < getBitWidth() && "Bit position out of bounds!"
) ? static_cast<void> (0) : __assert_fail ("bitPosition < getBitWidth() && \"Bit position out of bounds!\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1117, __PRETTY_FUNCTION__))
;
1118 return (maskBit(bitPosition) & getWord(bitPosition)) != 0;
1119 }
1120
1121 /// @}
1122 /// \name Comparison Operators
1123 /// @{
1124
1125 /// Equality operator.
1126 ///
1127 /// Compares this APInt with RHS for the validity of the equality
1128 /// relationship.
1129 bool operator==(const APInt &RHS) const {
1130 assert(BitWidth == RHS.BitWidth && "Comparison requires equal bit widths")((BitWidth == RHS.BitWidth && "Comparison requires equal bit widths"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Comparison requires equal bit widths\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1130, __PRETTY_FUNCTION__))
;
1131 if (isSingleWord())
1132 return U.VAL == RHS.U.VAL;
1133 return EqualSlowCase(RHS);
1134 }
1135
1136 /// Equality operator.
1137 ///
1138 /// Compares this APInt with a uint64_t for the validity of the equality
1139 /// relationship.
1140 ///
1141 /// \returns true if *this == Val
1142 bool operator==(uint64_t Val) const {
1143 return (isSingleWord() || getActiveBits() <= 64) && getZExtValue() == Val;
1144 }
1145
1146 /// Equality comparison.
1147 ///
1148 /// Compares this APInt with RHS for the validity of the equality
1149 /// relationship.
1150 ///
1151 /// \returns true if *this == Val
1152 bool eq(const APInt &RHS) const { return (*this) == RHS; }
1153
1154 /// Inequality operator.
1155 ///
1156 /// Compares this APInt with RHS for the validity of the inequality
1157 /// relationship.
1158 ///
1159 /// \returns true if *this != Val
1160 bool operator!=(const APInt &RHS) const { return !((*this) == RHS); }
1161
1162 /// Inequality operator.
1163 ///
1164 /// Compares this APInt with a uint64_t for the validity of the inequality
1165 /// relationship.
1166 ///
1167 /// \returns true if *this != Val
1168 bool operator!=(uint64_t Val) const { return !((*this) == Val); }
1169
1170 /// Inequality comparison
1171 ///
1172 /// Compares this APInt with RHS for the validity of the inequality
1173 /// relationship.
1174 ///
1175 /// \returns true if *this != Val
1176 bool ne(const APInt &RHS) const { return !((*this) == RHS); }
1177
1178 /// Unsigned less than comparison
1179 ///
1180 /// Regards both *this and RHS as unsigned quantities and compares them for
1181 /// the validity of the less-than relationship.
1182 ///
1183 /// \returns true if *this < RHS when both are considered unsigned.
1184 bool ult(const APInt &RHS) const { return compare(RHS) < 0; }
1185
1186 /// Unsigned less than comparison
1187 ///
1188 /// Regards both *this as an unsigned quantity and compares it with RHS for
1189 /// the validity of the less-than relationship.
1190 ///
1191 /// \returns true if *this < RHS when considered unsigned.
1192 bool ult(uint64_t RHS) const {
1193 // Only need to check active bits if not a single word.
1194 return (isSingleWord() || getActiveBits() <= 64) && getZExtValue() < RHS;
1195 }
1196
1197 /// Signed less than comparison
1198 ///
1199 /// Regards both *this and RHS as signed quantities and compares them for
1200 /// validity of the less-than relationship.
1201 ///
1202 /// \returns true if *this < RHS when both are considered signed.
1203 bool slt(const APInt &RHS) const { return compareSigned(RHS) < 0; }
1204
1205 /// Signed less than comparison
1206 ///
1207 /// Regards both *this as a signed quantity and compares it with RHS for
1208 /// the validity of the less-than relationship.
1209 ///
1210 /// \returns true if *this < RHS when considered signed.
1211 bool slt(int64_t RHS) const {
1212 return (!isSingleWord() && getMinSignedBits() > 64) ? isNegative()
1213 : getSExtValue() < RHS;
1214 }
1215
1216 /// Unsigned less or equal comparison
1217 ///
1218 /// Regards both *this and RHS as unsigned quantities and compares them for
1219 /// validity of the less-or-equal relationship.
1220 ///
1221 /// \returns true if *this <= RHS when both are considered unsigned.
1222 bool ule(const APInt &RHS) const { return compare(RHS) <= 0; }
1223
1224 /// Unsigned less or equal comparison
1225 ///
1226 /// Regards both *this as an unsigned quantity and compares it with RHS for
1227 /// the validity of the less-or-equal relationship.
1228 ///
1229 /// \returns true if *this <= RHS when considered unsigned.
1230 bool ule(uint64_t RHS) const { return !ugt(RHS); }
1231
1232 /// Signed less or equal comparison
1233 ///
1234 /// Regards both *this and RHS as signed quantities and compares them for
1235 /// validity of the less-or-equal relationship.
1236 ///
1237 /// \returns true if *this <= RHS when both are considered signed.
1238 bool sle(const APInt &RHS) const { return compareSigned(RHS) <= 0; }
1239
1240 /// Signed less or equal comparison
1241 ///
1242 /// Regards both *this as a signed quantity and compares it with RHS for the
1243 /// validity of the less-or-equal relationship.
1244 ///
1245 /// \returns true if *this <= RHS when considered signed.
1246 bool sle(uint64_t RHS) const { return !sgt(RHS); }
1247
1248 /// Unsigned greather than comparison
1249 ///
1250 /// Regards both *this and RHS as unsigned quantities and compares them for
1251 /// the validity of the greater-than relationship.
1252 ///
1253 /// \returns true if *this > RHS when both are considered unsigned.
1254 bool ugt(const APInt &RHS) const { return !ule(RHS); }
1255
1256 /// Unsigned greater than comparison
1257 ///
1258 /// Regards both *this as an unsigned quantity and compares it with RHS for
1259 /// the validity of the greater-than relationship.
1260 ///
1261 /// \returns true if *this > RHS when considered unsigned.
1262 bool ugt(uint64_t RHS) const {
1263 // Only need to check active bits if not a single word.
1264 return (!isSingleWord() && getActiveBits() > 64) || getZExtValue() > RHS;
1265 }
1266
1267 /// Signed greather than comparison
1268 ///
1269 /// Regards both *this and RHS as signed quantities and compares them for the
1270 /// validity of the greater-than relationship.
1271 ///
1272 /// \returns true if *this > RHS when both are considered signed.
1273 bool sgt(const APInt &RHS) const { return !sle(RHS); }
1274
1275 /// Signed greater than comparison
1276 ///
1277 /// Regards both *this as a signed quantity and compares it with RHS for
1278 /// the validity of the greater-than relationship.
1279 ///
1280 /// \returns true if *this > RHS when considered signed.
1281 bool sgt(int64_t RHS) const {
1282 return (!isSingleWord() && getMinSignedBits() > 64) ? !isNegative()
1283 : getSExtValue() > RHS;
1284 }
1285
1286 /// Unsigned greater or equal comparison
1287 ///
1288 /// Regards both *this and RHS as unsigned quantities and compares them for
1289 /// validity of the greater-or-equal relationship.
1290 ///
1291 /// \returns true if *this >= RHS when both are considered unsigned.
1292 bool uge(const APInt &RHS) const { return !ult(RHS); }
1293
1294 /// Unsigned greater or equal comparison
1295 ///
1296 /// Regards both *this as an unsigned quantity and compares it with RHS for
1297 /// the validity of the greater-or-equal relationship.
1298 ///
1299 /// \returns true if *this >= RHS when considered unsigned.
1300 bool uge(uint64_t RHS) const { return !ult(RHS); }
1301
1302 /// Signed greater or equal comparison
1303 ///
1304 /// Regards both *this and RHS as signed quantities and compares them for
1305 /// validity of the greater-or-equal relationship.
1306 ///
1307 /// \returns true if *this >= RHS when both are considered signed.
1308 bool sge(const APInt &RHS) const { return !slt(RHS); }
1309
1310 /// Signed greater or equal comparison
1311 ///
1312 /// Regards both *this as a signed quantity and compares it with RHS for
1313 /// the validity of the greater-or-equal relationship.
1314 ///
1315 /// \returns true if *this >= RHS when considered signed.
1316 bool sge(int64_t RHS) const { return !slt(RHS); }
1317
1318 /// This operation tests if there are any pairs of corresponding bits
1319 /// between this APInt and RHS that are both set.
1320 bool intersects(const APInt &RHS) const {
1321 assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")((BitWidth == RHS.BitWidth && "Bit widths must be the same"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1321, __PRETTY_FUNCTION__))
;
1322 if (isSingleWord())
1323 return (U.VAL & RHS.U.VAL) != 0;
1324 return intersectsSlowCase(RHS);
1325 }
1326
1327 /// This operation checks that all bits set in this APInt are also set in RHS.
1328 bool isSubsetOf(const APInt &RHS) const {
1329 assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")((BitWidth == RHS.BitWidth && "Bit widths must be the same"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1329, __PRETTY_FUNCTION__))
;
1330 if (isSingleWord())
1331 return (U.VAL & ~RHS.U.VAL) == 0;
1332 return isSubsetOfSlowCase(RHS);
1333 }
1334
1335 /// @}
1336 /// \name Resizing Operators
1337 /// @{
1338
1339 /// Truncate to new width.
1340 ///
1341 /// Truncate the APInt to a specified width. It is an error to specify a width
1342 /// that is greater than or equal to the current width.
1343 APInt trunc(unsigned width) const;
1344
1345 /// Sign extend to a new width.
1346 ///
1347 /// This operation sign extends the APInt to a new width. If the high order
1348 /// bit is set, the fill on the left will be done with 1 bits, otherwise zero.
1349 /// It is an error to specify a width that is less than or equal to the
1350 /// current width.
1351 APInt sext(unsigned width) const;
1352
1353 /// Zero extend to a new width.
1354 ///
1355 /// This operation zero extends the APInt to a new width. The high order bits
1356 /// are filled with 0 bits. It is an error to specify a width that is less
1357 /// than or equal to the current width.
1358 APInt zext(unsigned width) const;
1359
1360 /// Sign extend or truncate to width
1361 ///
1362 /// Make this APInt have the bit width given by \p width. The value is sign
1363 /// extended, truncated, or left alone to make it that width.
1364 APInt sextOrTrunc(unsigned width) const;
1365
1366 /// Zero extend or truncate to width
1367 ///
1368 /// Make this APInt have the bit width given by \p width. The value is zero
1369 /// extended, truncated, or left alone to make it that width.
1370 APInt zextOrTrunc(unsigned width) const;
1371
1372 /// Sign extend or truncate to width
1373 ///
1374 /// Make this APInt have the bit width given by \p width. The value is sign
1375 /// extended, or left alone to make it that width.
1376 APInt sextOrSelf(unsigned width) const;
1377
1378 /// Zero extend or truncate to width
1379 ///
1380 /// Make this APInt have the bit width given by \p width. The value is zero
1381 /// extended, or left alone to make it that width.
1382 APInt zextOrSelf(unsigned width) const;
1383
1384 /// @}
1385 /// \name Bit Manipulation Operators
1386 /// @{
1387
1388 /// Set every bit to 1.
1389 void setAllBits() {
1390 if (isSingleWord())
1391 U.VAL = WORDTYPE_MAX;
1392 else
1393 // Set all the bits in all the words.
1394 memset(U.pVal, -1, getNumWords() * APINT_WORD_SIZE);
1395 // Clear the unused ones
1396 clearUnusedBits();
1397 }
1398
1399 /// Set a given bit to 1.
1400 ///
1401 /// Set the given bit to 1 whose position is given as "bitPosition".
1402 void setBit(unsigned BitPosition) {
1403 assert(BitPosition < BitWidth && "BitPosition out of range")((BitPosition < BitWidth && "BitPosition out of range"
) ? static_cast<void> (0) : __assert_fail ("BitPosition < BitWidth && \"BitPosition out of range\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1403, __PRETTY_FUNCTION__))
;
1404 WordType Mask = maskBit(BitPosition);
1405 if (isSingleWord())
1406 U.VAL |= Mask;
1407 else
1408 U.pVal[whichWord(BitPosition)] |= Mask;
1409 }
1410
1411 /// Set the sign bit to 1.
1412 void setSignBit() {
1413 setBit(BitWidth - 1);
1414 }
1415
1416 /// Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
1417 void setBits(unsigned loBit, unsigned hiBit) {
1418 assert(hiBit <= BitWidth && "hiBit out of range")((hiBit <= BitWidth && "hiBit out of range") ? static_cast
<void> (0) : __assert_fail ("hiBit <= BitWidth && \"hiBit out of range\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1418, __PRETTY_FUNCTION__))
;
1419 assert(loBit <= BitWidth && "loBit out of range")((loBit <= BitWidth && "loBit out of range") ? static_cast
<void> (0) : __assert_fail ("loBit <= BitWidth && \"loBit out of range\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1419, __PRETTY_FUNCTION__))
;
1420 assert(loBit <= hiBit && "loBit greater than hiBit")((loBit <= hiBit && "loBit greater than hiBit") ? static_cast
<void> (0) : __assert_fail ("loBit <= hiBit && \"loBit greater than hiBit\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1420, __PRETTY_FUNCTION__))
;
1421 if (loBit == hiBit)
1422 return;
1423 if (loBit < APINT_BITS_PER_WORD && hiBit <= APINT_BITS_PER_WORD) {
1424 uint64_t mask = WORDTYPE_MAX >> (APINT_BITS_PER_WORD - (hiBit - loBit));
1425 mask <<= loBit;
1426 if (isSingleWord())
1427 U.VAL |= mask;
1428 else
1429 U.pVal[0] |= mask;
1430 } else {
1431 setBitsSlowCase(loBit, hiBit);
1432 }
1433 }
1434
1435 /// Set the top bits starting from loBit.
1436 void setBitsFrom(unsigned loBit) {
1437 return setBits(loBit, BitWidth);
1438 }
1439
1440 /// Set the bottom loBits bits.
1441 void setLowBits(unsigned loBits) {
1442 return setBits(0, loBits);
1443 }
1444
1445 /// Set the top hiBits bits.
1446 void setHighBits(unsigned hiBits) {
1447 return setBits(BitWidth - hiBits, BitWidth);
1448 }
1449
1450 /// Set every bit to 0.
1451 void clearAllBits() {
1452 if (isSingleWord())
1453 U.VAL = 0;
1454 else
1455 memset(U.pVal, 0, getNumWords() * APINT_WORD_SIZE);
1456 }
1457
1458 /// Set a given bit to 0.
1459 ///
1460 /// Set the given bit to 0 whose position is given as "bitPosition".
1461 void clearBit(unsigned BitPosition) {
1462 assert(BitPosition < BitWidth && "BitPosition out of range")((BitPosition < BitWidth && "BitPosition out of range"
) ? static_cast<void> (0) : __assert_fail ("BitPosition < BitWidth && \"BitPosition out of range\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1462, __PRETTY_FUNCTION__))
;
1463 WordType Mask = ~maskBit(BitPosition);
1464 if (isSingleWord())
1465 U.VAL &= Mask;
1466 else
1467 U.pVal[whichWord(BitPosition)] &= Mask;
1468 }
1469
1470 /// Set bottom loBits bits to 0.
1471 void clearLowBits(unsigned loBits) {
1472 assert(loBits <= BitWidth && "More bits than bitwidth")((loBits <= BitWidth && "More bits than bitwidth")
? static_cast<void> (0) : __assert_fail ("loBits <= BitWidth && \"More bits than bitwidth\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1472, __PRETTY_FUNCTION__))
;
1473 APInt Keep = getHighBitsSet(BitWidth, BitWidth - loBits);
1474 *this &= Keep;
1475 }
1476
1477 /// Set the sign bit to 0.
1478 void clearSignBit() {
1479 clearBit(BitWidth - 1);
1480 }
1481
1482 /// Toggle every bit to its opposite value.
1483 void flipAllBits() {
1484 if (isSingleWord()) {
1485 U.VAL ^= WORDTYPE_MAX;
1486 clearUnusedBits();
1487 } else {
1488 flipAllBitsSlowCase();
1489 }
1490 }
1491
1492 /// Toggles a given bit to its opposite value.
1493 ///
1494 /// Toggle a given bit to its opposite value whose position is given
1495 /// as "bitPosition".
1496 void flipBit(unsigned bitPosition);
1497
1498 /// Negate this APInt in place.
1499 void negate() {
1500 flipAllBits();
1501 ++(*this);
1502 }
1503
1504 /// Insert the bits from a smaller APInt starting at bitPosition.
1505 void insertBits(const APInt &SubBits, unsigned bitPosition);
1506 void insertBits(uint64_t SubBits, unsigned bitPosition, unsigned numBits);
1507
1508 /// Return an APInt with the extracted bits [bitPosition,bitPosition+numBits).
1509 APInt extractBits(unsigned numBits, unsigned bitPosition) const;
1510 uint64_t extractBitsAsZExtValue(unsigned numBits, unsigned bitPosition) const;
1511
1512 /// @}
1513 /// \name Value Characterization Functions
1514 /// @{
1515
1516 /// Return the number of bits in the APInt.
1517 unsigned getBitWidth() const { return BitWidth; }
1518
1519 /// Get the number of words.
1520 ///
1521 /// Here one word's bitwidth equals to that of uint64_t.
1522 ///
1523 /// \returns the number of words to hold the integer value of this APInt.
1524 unsigned getNumWords() const { return getNumWords(BitWidth); }
1525
1526 /// Get the number of words.
1527 ///
1528 /// *NOTE* Here one word's bitwidth equals to that of uint64_t.
1529 ///
1530 /// \returns the number of words to hold the integer value with a given bit
1531 /// width.
1532 static unsigned getNumWords(unsigned BitWidth) {
1533 return ((uint64_t)BitWidth + APINT_BITS_PER_WORD - 1) / APINT_BITS_PER_WORD;
1534 }
1535
1536 /// Compute the number of active bits in the value
1537 ///
1538 /// This function returns the number of active bits which is defined as the
1539 /// bit width minus the number of leading zeros. This is used in several
1540 /// computations to see how "wide" the value is.
1541 unsigned getActiveBits() const { return BitWidth - countLeadingZeros(); }
1542
1543 /// Compute the number of active words in the value of this APInt.
1544 ///
1545 /// This is used in conjunction with getActiveData to extract the raw value of
1546 /// the APInt.
1547 unsigned getActiveWords() const {
1548 unsigned numActiveBits = getActiveBits();
1549 return numActiveBits ? whichWord(numActiveBits - 1) + 1 : 1;
1550 }
1551
1552 /// Get the minimum bit size for this signed APInt
1553 ///
1554 /// Computes the minimum bit width for this APInt while considering it to be a
1555 /// signed (and probably negative) value. If the value is not negative, this
1556 /// function returns the same value as getActiveBits()+1. Otherwise, it
1557 /// returns the smallest bit width that will retain the negative value. For
1558 /// example, -1 can be written as 0b1 or 0xFFFFFFFFFF. 0b1 is shorter and so
1559 /// for -1, this function will always return 1.
1560 unsigned getMinSignedBits() const {
1561 if (isNegative())
1562 return BitWidth - countLeadingOnes() + 1;
1563 return getActiveBits() + 1;
1564 }
1565
1566 /// Get zero extended value
1567 ///
1568 /// This method attempts to return the value of this APInt as a zero extended
1569 /// uint64_t. The bitwidth must be <= 64 or the value must fit within a
1570 /// uint64_t. Otherwise an assertion will result.
1571 uint64_t getZExtValue() const {
1572 if (isSingleWord())
1573 return U.VAL;
1574 assert(getActiveBits() <= 64 && "Too many bits for uint64_t")((getActiveBits() <= 64 && "Too many bits for uint64_t"
) ? static_cast<void> (0) : __assert_fail ("getActiveBits() <= 64 && \"Too many bits for uint64_t\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1574, __PRETTY_FUNCTION__))
;
1575 return U.pVal[0];
1576 }
1577
1578 /// Get sign extended value
1579 ///
1580 /// This method attempts to return the value of this APInt as a sign extended
1581 /// int64_t. The bit width must be <= 64 or the value must fit within an
1582 /// int64_t. Otherwise an assertion will result.
1583 int64_t getSExtValue() const {
1584 if (isSingleWord())
1585 return SignExtend64(U.VAL, BitWidth);
1586 assert(getMinSignedBits() <= 64 && "Too many bits for int64_t")((getMinSignedBits() <= 64 && "Too many bits for int64_t"
) ? static_cast<void> (0) : __assert_fail ("getMinSignedBits() <= 64 && \"Too many bits for int64_t\""
, "/build/llvm-toolchain-snapshot-10~svn372306/include/llvm/ADT/APInt.h"
, 1586, __PRETTY_FUNCTION__))
;
1587 return int64_t(U.pVal[0]);
1588 }
1589
1590 /// Get bits required for string value.
1591 ///
1592 /// This method determines how many bits are required to hold the APInt
1593 /// equivalent of the string given by \p str.
1594 static unsigned getBitsNeeded(StringRef str, uint8_t radix);
1595
1596 /// The APInt version of the countLeadingZeros functions in
1597 /// MathExtras.h.
1598 ///
1599 /// It counts the number of zeros from the most significant bit to the first
1600 /// one bit.
1601 ///
1602 /// \returns BitWidth if the value is zero, otherwise returns the number of
1603 /// zeros from the most significant bit to the first one bits.
1604 unsigned countLeadingZeros() const {
1605 if (isSingleWord()) {
1606 unsigned unusedBits = APINT_BITS_PER_WORD - BitWidth;
1607 return llvm::countLeadingZeros(U.VAL) - unusedBits;
1608 }
1609 return countLeadingZerosSlowCase();
1610 }
1611
1612 /// Count the number of leading one bits.
1613 ///
1614 /// This function is an APInt version of the countLeadingOnes
1615 /// functions in MathExtras.h. It counts the number of ones from the most
1616 /// significant bit to the first zero bit.
1617 ///
1618 /// \returns 0 if the high order bit is not set, otherwise returns the number
1619 /// of 1 bits from the most significant to the least
1620 unsigned countLeadingOnes() const {
1621 if (isSingleWord())
1622 return llvm::countLeadingOnes(U.VAL << (APINT_BITS_PER_WORD - BitWidth));
1623 return countLeadingOnesSlowCase();
1624 }
1625
1626 /// Computes the number of leading bits of this APInt that are equal to its
1627 /// sign bit.
1628 unsigned getNumSignBits() const {
1629 return isNegative() ? countLeadingOnes() : countLeadingZeros();
1630 }
1631
1632 /// Count the number of trailing zero bits.
1633 ///
1634 /// This function is an APInt version of the countTrailingZeros
1635 /// functions in MathExtras.h. It counts the number of zeros from the least
1636 /// significant bit to the first set bit.
1637 ///
1638 /// \returns BitWidth if the value is zero, otherwise returns the number of
1639 /// zeros from the least significant bit to the first one bit.
1640 unsigned countTrailingZeros() const {
1641 if (isSingleWord())
1642 return std::min(unsigned(llvm::countTrailingZeros(U.VAL)), BitWidth);
1643 return countTrailingZerosSlowCase();
1644 }
1645
1646 /// Count the number of trailing one bits.
1647 ///
1648 /// This function is an APInt version of the countTrailingOnes
1649 /// functions in MathExtras.h. It counts the number of ones from the least
1650 /// significant bit to the first zero bit.
1651 ///
1652 /// \returns BitWidth if the value is all ones, otherwise returns the number
1653 /// of ones from the least significant bit to the first zero bit.
1654 unsigned countTrailingOnes() const {
1655 if (isSingleWord())
1656 return llvm::countTrailingOnes(U.VAL);
1657 return countTrailingOnesSlowCase();
1658 }
1659
1660 /// Count the number of bits set.
1661 ///
1662 /// This function is an APInt version of the countPopulation functions
1663 /// in MathExtras.h. It counts the number of 1 bits in the APInt value.
1664 ///
1665 /// \returns 0 if the value is zero, otherwise returns the number of set bits.
1666 unsigned countPopulation() const {
1667 if (isSingleWord())
1668 return llvm::countPopulation(U.VAL);
1669 return countPopulationSlowCase();
1670 }
1671
1672 /// @}
1673 /// \name Conversion Functions
1674 /// @{
1675 void print(raw_ostream &OS, bool isSigned) const;
1676
1677 /// Converts an APInt to a string and append it to Str. Str is commonly a
1678 /// SmallString.
1679 void toString(SmallVectorImpl<char> &Str, unsigned Radix, bool Signed,
1680 bool formatAsCLiteral = false) const;
1681
1682 /// Considers the APInt to be unsigned and converts it into a string in the
1683 /// radix given. The radix can be 2, 8, 10 16, or 36.
1684 void toStringUnsigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) const {
1685 toString(Str, Radix, false, false);
1686 }
1687
1688 /// Considers the APInt to be signed and converts it into a string in the
1689 /// radix given. The radix can be 2, 8, 10, 16, or 36.
1690 void toStringSigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) const {
1691 toString(Str, Radix, true, false);
1692 }
1693
1694 /// Return the APInt as a std::string.
1695 ///
1696 /// Note that this is an inefficient method. It is better to pass in a
1697 /// SmallVector/SmallString to the methods above to avoid thrashing the heap
1698 /// for the string.
1699 std::string toString(unsigned Radix, bool Signed) const;
1700
1701 /// \returns a byte-swapped representation of this APInt Value.
1702 APInt byteSwap() const;
1703
1704 /// \returns the value with the bit representation reversed of this APInt
1705 /// Value.
1706 APInt reverseBits() const;
1707
1708 /// Converts this APInt to a double value.
1709 double roundToDouble(bool isSigned) const;
1710
1711 /// Converts this unsigned APInt to a double value.
1712 double roundToDouble() const { return roundToDouble(false); }
1713
1714 /// Converts this signed APInt to a double value.
1715 double signedRoundToDouble() const { return roundToDouble(true); }
1716
1717 /// Converts APInt bits to a double
1718 ///
1719 /// The conversion does not do a translation from integer to double, it just
1720 /// re-interprets the bits as a double. Note that it is valid to do this on
1721 /// any bit width. Exactly 64 bits will be translated.
1722 double bitsToDouble() const {
1723 return BitsToDouble(getWord(0));
1724 }
1725
1726 /// Converts APInt bits to a double
1727 ///
1728 /// The conversion does not do a translation from integer to float, it just
1729 /// re-interprets the bits as a float. Note that it is valid to do this on
1730 /// any bit width. Exactly 32 bits will be translated.
1731 float bitsToFloat() const {
1732 return BitsToFloat(getWord(0));
1733 }
1734
1735 /// Converts a double to APInt bits.
1736 ///
1737 /// The conversion does not do a translation from double to integer, it just
1738 /// re-interprets the bits of the double.
1739 static APInt doubleToBits(double V) {
1740 return APInt(sizeof(double) * CHAR_BIT8, DoubleToBits(V));
1741 }
1742
1743 /// Converts a float to APInt bits.
1744 ///
1745 /// The conversion does not do a translation from float to integer, it just
1746 /// re-interprets the bits of the float.
1747 static APInt floatToBits(float V) {
1748 return APInt(sizeof(float) * CHAR_BIT8, FloatToBits(V));
1749 }
1750
1751 /// @}
1752 /// \name Mathematics Operations
1753 /// @{
1754
1755 /// \returns the floor log base 2 of this APInt.
1756 unsigned logBase2() const { return getActiveBits() - 1; }
1757
1758 /// \returns the ceil log base 2 of this APInt.
1759 unsigned ceilLogBase2() const {
1760 APInt temp(*this);
1761 --temp;
1762 return temp.getActiveBits();
1763 }
1764
1765 /// \returns the nearest log base 2 of this APInt. Ties round up.
1766 ///
1767 /// NOTE: When we have a BitWidth of 1, we define:
1768 ///
1769 /// log2(0) = UINT32_MAX
1770 /// log2(1) = 0
1771 ///
1772 /// to get around any mathematical concerns resulting from
1773 /// referencing 2 in a space where 2 does no exist.
1774 unsigned nearestLogBase2() const {
1775 // Special case when we have a bitwidth of 1. If VAL is 1, then we
1776 // get 0. If VAL is 0, we get WORDTYPE_MAX which gets truncated to
1777 // UINT32_MAX.
1778 if (BitWidth == 1)
1779 return U.VAL - 1;
1780
1781 // Handle the zero case.
1782 if (isNullValue())
1783 return UINT32_MAX(4294967295U);
1784
1785 // The non-zero case is handled by computing:
1786 //
1787 // nearestLogBase2(x) = logBase2(x) + x[logBase2(x)-1].
1788 //
1789 // where x[i] is referring to the value of the ith bit of x.
1790 unsigned lg = logBase2();
1791 return lg + unsigned((*this)[lg - 1]);
1792 }
1793
1794 /// \returns the log base 2 of this APInt if its an exact power of two, -1
1795 /// otherwise
1796 int32_t exactLogBase2() const {
1797 if (!isPowerOf2())
1798 return -1;
1799 return logBase2();
1800 }
1801
1802 /// Compute the square root
1803 APInt sqrt() const;
1804
1805 /// Get the absolute value;
1806 ///
1807 /// If *this is < 0 then return -(*this), otherwise *this;
1808 APInt abs() const {
1809 if (isNegative())
1810 return -(*this);
1811 return *this;
1812 }
1813
1814 /// \returns the multiplicative inverse for a given modulo.
1815 APInt multiplicativeInverse(const APInt &modulo) const;
1816
1817 /// @}
1818 /// \name Support for division by constant
1819 /// @{
1820
1821 /// Calculate the magic number for signed division by a constant.
1822 struct ms;
1823 ms magic() const;
1824
1825 /// Calculate the magic number for unsigned division by a constant.
1826 struct mu;
1827 mu magicu(unsigned LeadingZeros = 0) const;
1828
1829 /// @}
1830 /// \name Building-block Operations for APInt and APFloat
1831 /// @{
1832
1833 // These building block operations operate on a representation of arbitrary
1834 // precision, two's-complement, bignum integer values. They should be
1835 // sufficient to implement APInt and APFloat bignum requirements. Inputs are
1836 // generally a pointer to the base of an array of integer parts, representing
1837 // an unsigned bignum, and a count of how many parts there are.
1838
1839 /// Sets the least significant part of a bignum to the input value, and zeroes
1840 /// out higher parts.
1841 static void tcSet(WordType *, WordType, unsigned);
1842
1843 /// Assign one bignum to another.
1844 static void tcAssign(WordType *, const WordType *, unsigned);
1845
1846 /// Returns true if a bignum is zero, false otherwise.
1847 static bool tcIsZero(const WordType *, unsigned);
1848
1849 /// Extract the given bit of a bignum; returns 0 or 1. Zero-based.
1850 static int tcExtractBit(const WordType *, unsigned bit);
1851
1852 /// Copy the bit vector of width srcBITS from SRC, starting at bit srcLSB, to
1853 /// DST, of dstCOUNT parts, such that the bit srcLSB becomes the least
1854 /// significant bit of DST. All high bits above srcBITS in DST are
1855 /// zero-filled.
1856 static void tcExtract(WordType *, unsigned dstCount,
1857 const WordType *, unsigned srcBits,
1858 unsigned srcLSB);
1859
1860 /// Set the given bit of a bignum. Zero-based.
1861 static void tcSetBit(WordType *, unsigned bit);
1862
1863 /// Clear the given bit of a bignum. Zero-based.
1864 static void tcClearBit(WordType *, unsigned bit);
1865
1866 /// Returns the bit number of the least or most significant set bit of a
1867 /// number. If the input number has no bits set -1U is returned.
1868 static unsigned tcLSB(const WordType *, unsigned n);
1869 static unsigned tcMSB(const WordType *parts, unsigned n);
1870
1871 /// Negate a bignum in-place.
1872 static void tcNegate(WordType *, unsigned);
1873
1874 /// DST += RHS + CARRY where CARRY is zero or one. Returns the carry flag.
1875 static WordType tcAdd(WordType *, const WordType *,
1876 WordType carry, unsigned);
1877 /// DST += RHS. Returns the carry flag.
1878 static WordType tcAddPart(WordType *, WordType, unsigned);
1879
1880 /// DST -= RHS + CARRY where CARRY is zero or one. Returns the carry flag.
1881 static WordType tcSubtract(WordType *, const WordType *,
1882 WordType carry, unsigned);
1883 /// DST -= RHS. Returns the carry flag.
1884 static WordType tcSubtractPart(WordType *, WordType, unsigned);
1885
1886 /// DST += SRC * MULTIPLIER + PART if add is true
1887 /// DST = SRC * MULTIPLIER + PART if add is false
1888 ///
1889 /// Requires 0 <= DSTPARTS <= SRCPARTS + 1. If DST overlaps SRC they must
1890 /// start at the same point, i.e. DST == SRC.
1891 ///
1892 /// If DSTPARTS == SRC_PARTS + 1 no overflow occurs and zero is returned.
1893 /// Otherwise DST is filled with the least significant DSTPARTS parts of the
1894 /// result, and if all of the omitted higher parts were zero return zero,
1895 /// otherwise overflow occurred and return one.
1896 static int tcMultiplyPart(WordType *dst, const WordType *src,
1897 WordType multiplier, WordType carry,
1898 unsigned srcParts, unsigned dstParts,
1899 bool add);
1900
1901 /// DST = LHS * RHS, where DST has the same width as the operands and is
1902 /// filled with the least significant parts of the result. Returns one if
1903 /// overflow occurred, otherwise zero. DST must be disjoint from both
1904 /// operands.
1905 static int tcMultiply(WordType *, const WordType *, const WordType *,
1906 unsigned);
1907
1908 /// DST = LHS * RHS, where DST has width the sum of the widths of the
1909 /// operands. No overflow occurs. DST must be disjoint from both operands.
1910 static void tcFullMultiply(WordType *, const WordType *,
1911 const WordType *, unsigned, unsigned);
1912
1913 /// If RHS is zero LHS and REMAINDER are left unchanged, return one.
1914 /// Otherwise set LHS to LHS / RHS with the fractional part discarded, set
1915 /// REMAINDER to the remainder, return zero. i.e.
1916 ///
1917 /// OLD_LHS = RHS * LHS + REMAINDER
1918 ///
1919 /// SCRATCH is a bignum of the same size as the operands and result for use by
1920 /// the routine; its contents need not be initialized and are destroyed. LHS,
1921 /// REMAINDER and SCRATCH must be distinct.
1922 static int tcDivide(WordType *lhs, const WordType *rhs,
1923 WordType *remainder, WordType *scratch,
1924 unsigned parts);
1925
1926 /// Shift a bignum left Count bits. Shifted in bits are zero. There are no
1927 /// restrictions on Count.
1928 static void tcShiftLeft(WordType *, unsigned Words, unsigned Count);
1929
1930 /// Shift a bignum right Count bits. Shifted in bits are zero. There are no
1931 /// restrictions on Count.
1932 static void tcShiftRight(WordType *, unsigned Words, unsigned Count);
1933
1934 /// The obvious AND, OR and XOR and complement operations.
1935 static void tcAnd(WordType *, const WordType *, unsigned);
1936 static void tcOr(WordType *, const WordType *, unsigned);
1937 static void tcXor(WordType *, const WordType *, unsigned);
1938 static void tcComplement(WordType *, unsigned);
1939
1940 /// Comparison (unsigned) of two bignums.
1941 static int tcCompare(const WordType *, const WordType *, unsigned);
1942
1943 /// Increment a bignum in-place. Return the carry flag.
1944 static WordType tcIncrement(WordType *dst, unsigned parts) {
1945 return tcAddPart(dst, 1, parts);
1946 }
1947
1948 /// Decrement a bignum in-place. Return the borrow flag.
1949 static WordType tcDecrement(WordType *dst, unsigned parts) {
1950 return tcSubtractPart(dst, 1, parts);
1951 }
1952
1953 /// Set the least significant BITS and clear the rest.
1954 static void tcSetLeastSignificantBits(WordType *, unsigned, unsigned bits);
1955
1956 /// debug method
1957 void dump() const;
1958
1959 /// @}
1960};
1961
1962/// Magic data for optimising signed division by a constant.
1963struct APInt::ms {
1964 APInt m; ///< magic number
1965 unsigned s; ///< shift amount
1966};
1967
1968/// Magic data for optimising unsigned division by a constant.
1969struct APInt::mu {
1970 APInt m; ///< magic number
1971 bool a; ///< add indicator
1972 unsigned s; ///< shift amount
1973};
1974
1975inline bool operator==(uint64_t V1, const APInt &V2) { return V2 == V1; }
1976
1977inline bool operator!=(uint64_t V1, const APInt &V2) { return V2 != V1; }
1978
1979/// Unary bitwise complement operator.
1980///
1981/// \returns an APInt that is the bitwise complement of \p v.
1982inline APInt operator~(APInt v) {
1983 v.flipAllBits();
1984 return v;
1985}
1986
1987inline APInt operator&(APInt a, const APInt &b) {
1988 a &= b;
1989 return a;
1990}
1991
1992inline APInt operator&(const APInt &a, APInt &&b) {
1993 b &= a;
1994 return std::move(b);
1995}
1996
1997inline APInt operator&(APInt a, uint64_t RHS) {
1998 a &= RHS;
1999 return a;
2000}
2001
2002inline APInt operator&(uint64_t LHS, APInt b) {
2003 b &= LHS;
2004 return b;
2005}
2006
2007inline APInt operator|(APInt a, const APInt &b) {
2008 a |= b;
2009 return a;
2010}
2011
2012inline APInt operator|(const APInt &a, APInt &&b) {
2013 b |= a;
2014 return std::move(b);
2015}
2016
2017inline APInt operator|(APInt a, uint64_t RHS) {
2018 a |= RHS;
2019 return a;
2020}
2021
2022inline APInt operator|(uint64_t LHS, APInt b) {
2023 b |= LHS;
2024 return b;
2025}
2026
2027inline APInt operator^(APInt a, const APInt &b) {
2028 a ^= b;
2029 return a;
2030}
2031
2032inline APInt operator^(const APInt &a, APInt &&b) {
2033 b ^= a;
2034 return std::move(b);
2035}
2036
2037inline APInt operator^(APInt a, uint64_t RHS) {
2038 a ^= RHS;
2039 return a;
2040}
2041
2042inline APInt operator^(uint64_t LHS, APInt b) {
2043 b ^= LHS;
2044 return b;
2045}
2046
2047inline raw_ostream &operator<<(raw_ostream &OS, const APInt &I) {
2048 I.print(OS, true);
2049 return OS;
2050}
2051
2052inline APInt operator-(APInt v) {
2053 v.negate();
2054 return v;
2055}
2056
2057inline APInt operator+(APInt a, const APInt &b) {
2058 a += b;
2059 return a;
2060}
2061
2062inline APInt operator+(const APInt &a, APInt &&b) {
2063 b += a;
2064 return std::move(b);
2065}
2066
2067inline APInt operator+(APInt a, uint64_t RHS) {
2068 a += RHS;
2069 return a;
2070}
2071
2072inline APInt operator+(uint64_t LHS, APInt b) {
2073 b += LHS;
2074 return b;
2075}
2076
2077inline APInt operator-(APInt a, const APInt &b) {
2078 a -= b;
2079 return a;
2080}
2081
2082inline APInt operator-(const APInt &a, APInt &&b) {
2083 b.negate();
2084 b += a;
2085 return std::move(b);
2086}
2087
2088inline APInt operator-(APInt a, uint64_t RHS) {
2089 a -= RHS;
2090 return a;
2091}
2092
2093inline APInt operator-(uint64_t LHS, APInt b) {
2094 b.negate();
2095 b += LHS;
2096 return b;
2097}
2098
2099inline APInt operator*(APInt a, uint64_t RHS) {
2100 a *= RHS;
2101 return a;
2102}
2103
2104inline APInt operator*(uint64_t LHS, APInt b) {
2105 b *= LHS;
2106 return b;
2107}
2108
2109
2110namespace APIntOps {
2111
2112/// Determine the smaller of two APInts considered to be signed.
2113inline const APInt &smin(const APInt &A, const APInt &B) {
2114 return A.slt(B) ? A : B;
2115}
2116
2117/// Determine the larger of two APInts considered to be signed.
2118inline const APInt &smax(const APInt &A, const APInt &B) {
2119 return A.sgt(B) ? A : B;
2120}
2121
2122/// Determine the smaller of two APInts considered to be signed.
2123inline const APInt &umin(const APInt &A, const APInt &B) {
2124 return A.ult(B) ? A : B;
2125}
2126
2127/// Determine the larger of two APInts considered to be unsigned.
2128inline const APInt &umax(const APInt &A, const APInt &B) {
2129 return A.ugt(B) ? A : B;
2130}
2131
2132/// Compute GCD of two unsigned APInt values.
2133///
2134/// This function returns the greatest common divisor of the two APInt values
2135/// using Stein's algorithm.
2136///
2137/// \returns the greatest common divisor of A and B.
2138APInt GreatestCommonDivisor(APInt A, APInt B);
2139
2140/// Converts the given APInt to a double value.
2141///
2142/// Treats the APInt as an unsigned value for conversion purposes.
2143inline double RoundAPIntToDouble(const APInt &APIVal) {
2144 return APIVal.roundToDouble();
2145}
2146
2147/// Converts the given APInt to a double value.
2148///
2149/// Treats the APInt as a signed value for conversion purposes.
2150inline double RoundSignedAPIntToDouble(const APInt &APIVal) {
2151 return APIVal.signedRoundToDouble();
2152}
2153
2154/// Converts the given APInt to a float vlalue.
2155inline float RoundAPIntToFloat(const APInt &APIVal) {
2156 return float(RoundAPIntToDouble(APIVal));
2157}
2158
2159/// Converts the given APInt to a float value.
2160///
2161/// Treast the APInt as a signed value for conversion purposes.
2162inline float RoundSignedAPIntToFloat(const APInt &APIVal) {
2163 return float(APIVal.signedRoundToDouble());
2164}
2165
2166/// Converts the given double value into a APInt.
2167///
2168/// This function convert a double value to an APInt value.
2169APInt RoundDoubleToAPInt(double Double, unsigned width);
2170
2171/// Converts a float value into a APInt.
2172///
2173/// Converts a float value into an APInt value.
2174inline APInt RoundFloatToAPInt(float Float, unsigned width) {
2175 return RoundDoubleToAPInt(double(Float), width);
2176}
2177
2178/// Return A unsign-divided by B, rounded by the given rounding mode.
2179APInt RoundingUDiv(const APInt &A, const APInt &B, APInt::Rounding RM);
2180
2181/// Return A sign-divided by B, rounded by the given rounding mode.
2182APInt RoundingSDiv(const APInt &A, const APInt &B, APInt::Rounding RM);
2183
2184/// Let q(n) = An^2 + Bn + C, and BW = bit width of the value range
2185/// (e.g. 32 for i32).
2186/// This function finds the smallest number n, such that
2187/// (a) n >= 0 and q(n) = 0, or
2188/// (b) n >= 1 and q(n-1) and q(n), when evaluated in the set of all
2189/// integers, belong to two different intervals [Rk, Rk+R),
2190/// where R = 2^BW, and k is an integer.
2191/// The idea here is to find when q(n) "overflows" 2^BW, while at the
2192/// same time "allowing" subtraction. In unsigned modulo arithmetic a
2193/// subtraction (treated as addition of negated numbers) would always
2194/// count as an overflow, but here we want to allow values to decrease
2195/// and increase as long as they are within the same interval.
2196/// Specifically, adding of two negative numbers should not cause an
2197/// overflow (as long as the magnitude does not exceed the bith width).
2198/// On the other hand, given a positive number, adding a negative
2199/// number to it can give a negative result, which would cause the
2200/// value to go from [-2^BW, 0) to [0, 2^BW). In that sense, zero is
2201/// treated as a special case of an overflow.
2202///
2203/// This function returns None if after finding k that minimizes the
2204/// positive solution to q(n) = kR, both solutions are contained between
2205/// two consecutive integers.
2206///
2207/// There are cases where q(n) > T, and q(n+1) < T (assuming evaluation
2208/// in arithmetic modulo 2^BW, and treating the values as signed) by the
2209/// virtue of *signed* overflow. This function will *not* find such an n,
2210/// however it may find a value of n satisfying the inequalities due to
2211/// an *unsigned* overflow (if the values are treated as unsigned).
2212/// To find a solution for a signed overflow, treat it as a problem of
2213/// finding an unsigned overflow with a range with of BW-1.
2214///
2215/// The returned value may have a different bit width from the input
2216/// coefficients.
2217Optional<APInt> SolveQuadraticEquationWrap(APInt A, APInt B, APInt C,
2218 unsigned RangeWidth);
2219} // End of APIntOps namespace
2220
2221// See friend declaration above. This additional declaration is required in
2222// order to compile LLVM with IBM xlC compiler.
2223hash_code hash_value(const APInt &Arg);
2224
2225/// StoreIntToMemory - Fills the StoreBytes bytes of memory starting from Dst
2226/// with the integer held in IntVal.
2227void StoreIntToMemory(const APInt &IntVal, uint8_t *Dst, unsigned StoreBytes);
2228
2229/// LoadIntFromMemory - Loads the integer stored in the LoadBytes bytes starting
2230/// from Src into IntVal, which is assumed to be wide enough and to hold zero.
2231void LoadIntFromMemory(APInt &IntVal, uint8_t *Src, unsigned LoadBytes);
2232
2233} // namespace llvm
2234
2235#endif

/build/llvm-toolchain-snapshot-10~svn372306/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h

1//===---- MipsABIInfo.h - Information about MIPS ABI's --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
10#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIINFO_H
11
12#include "llvm/ADT/Triple.h"
13#include "llvm/IR/CallingConv.h"
14#include "llvm/MC/MCRegisterInfo.h"
15
16namespace llvm {
17
18template <typename T> class ArrayRef;
19class MCTargetOptions;
20class StringRef;
21class TargetRegisterClass;
22
23class MipsABIInfo {
24public:
25 enum class ABI { Unknown, O32, N32, N64 };
26
27protected:
28 ABI ThisABI;
29
30public:
31 MipsABIInfo(ABI ThisABI) : ThisABI(ThisABI) {}
32
33 static MipsABIInfo Unknown() { return MipsABIInfo(ABI::Unknown); }
34 static MipsABIInfo O32() { return MipsABIInfo(ABI::O32); }
35 static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); }
36 static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); }
37 static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU,
38 const MCTargetOptions &Options);
39
40 bool IsKnown() const { return ThisABI != ABI::Unknown; }
41 bool IsO32() const { return ThisABI == ABI::O32; }
42 bool IsN32() const { return ThisABI == ABI::N32; }
34
Assuming field 'ThisABI' is equal to N32
35
Returning the value 1, which participates in a condition later
43 bool IsN64() const { return ThisABI == ABI::N64; }
44 ABI GetEnumValue() const { return ThisABI; }
45
46 /// The registers to use for byval arguments.
47 ArrayRef<MCPhysReg> GetByValArgRegs() const;
48
49 /// The registers to use for the variable argument list.
50 ArrayRef<MCPhysReg> GetVarArgRegs() const;
51
52 /// Obtain the size of the area allocated by the callee for arguments.
53 /// CallingConv::FastCall affects the value for O32.
54 unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const;
55
56 /// Ordering of ABI's
57 /// MipsGenSubtargetInfo.inc will use this to resolve conflicts when given
58 /// multiple ABI options.
59 bool operator<(const MipsABIInfo Other) const {
60 return ThisABI < Other.GetEnumValue();
61 }
62
63 unsigned GetStackPtr() const;
64 unsigned GetFramePtr() const;
65 unsigned GetBasePtr() const;
66 unsigned GetGlobalPtr() const;
67 unsigned GetNullPtr() const;
68 unsigned GetZeroReg() const;
69 unsigned GetPtrAdduOp() const;
70 unsigned GetPtrAddiuOp() const;
71 unsigned GetPtrSubuOp() const;
72 unsigned GetPtrAndOp() const;
73 unsigned GetGPRMoveOp() const;
74 inline bool ArePtrs64bit() const { return IsN64(); }
75 inline bool AreGprs64bit() const { return IsN32() || IsN64(); }
76
77 unsigned GetEhDataReg(unsigned I) const;
78};
79}
80
81#endif