Bug Summary

File:llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
Warning:line 401, column 19
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCDisassembler.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/PowerPC/Disassembler -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/PowerPC/Disassembler -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/PowerPC/Disassembler -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/include -I /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/include -D NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/build-llvm/lib/Target/PowerPC/Disassembler -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-04-040900-46481-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210903100615+fd66b44ec19e/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
1//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "MCTargetDesc/PPCMCTargetDesc.h"
10#include "TargetInfo/PowerPCTargetInfo.h"
11#include "llvm/MC/MCDisassembler/MCDisassembler.h"
12#include "llvm/MC/MCFixedLenDisassembler.h"
13#include "llvm/MC/MCInst.h"
14#include "llvm/MC/MCSubtargetInfo.h"
15#include "llvm/Support/Endian.h"
16#include "llvm/Support/TargetRegistry.h"
17
18using namespace llvm;
19
20DEFINE_PPC_REGCLASSESstatic const MCPhysReg RRegs[32] = { PPC::R0, PPC::R1, PPC::R2
, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::
R9, PPC::R10, PPC::R11, PPC::R12, PPC::R13, PPC::R14, PPC::R15
, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21,
PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC
::R28, PPC::R29, PPC::R30, PPC::R31 }; static const MCPhysReg
XRegs[32] = { PPC::X0, PPC::X1, PPC::X2, PPC::X3, PPC::X4, PPC
::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11,
PPC::X12, PPC::X13, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC
::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::
X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30
, PPC::X31 }; static const MCPhysReg FRegs[32] = { PPC::F0, PPC
::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC
::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14
, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20,
PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC
::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31 }; static const
MCPhysReg VSRpRegs[32] = { PPC::VSRp0, PPC::VSRp1, PPC::VSRp2
, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7,
PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12
, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17
, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22
, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27
, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31 }; static
const MCPhysReg SPERegs[32] = { PPC::S0, PPC::S1, PPC::S2, PPC
::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC
::S10, PPC::S11, PPC::S12, PPC::S13, PPC::S14, PPC::S15, PPC::
S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22
, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28,
PPC::S29, PPC::S30, PPC::S31 }; static const MCPhysReg VFRegs
[32] = { PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, PPC::VF4, PPC
::VF5, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC
::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16
, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF20, PPC::VF21, PPC::
VF22, PPC::VF23, PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, PPC
::VF28, PPC::VF29, PPC::VF30, PPC::VF31 }; static const MCPhysReg
VRegs[32] = { PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC
::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11,
PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC
::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::
V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30
, PPC::V31 }; static const MCPhysReg RRegsNoR0[32] = { PPC::ZERO
, PPC::R1, PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::
R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R13,
PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC
::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::
R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31 }; static
const MCPhysReg XRegsNoX0[32] = { PPC::ZERO8, PPC::X1, PPC::
X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC
::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X13, PPC::X14, PPC::
X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21
, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27,
PPC::X28, PPC::X29, PPC::X30, PPC::X31 }; static const MCPhysReg
VSRegs[64] = { PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC
::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9
, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14,
PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC
::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::
VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30
, PPC::VSL31, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC
::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11,
PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC
::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::
V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30
, PPC::V31 }; static const MCPhysReg VSFRegs[64] = { PPC::F0,
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7
, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC
::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::
F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26
, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::VF0,
PPC::VF1, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF6, PPC
::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC
::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18
, PPC::VF19, PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, PPC::
VF24, PPC::VF25, PPC::VF26, PPC::VF27, PPC::VF28, PPC::VF29, PPC
::VF30, PPC::VF31 }; static const MCPhysReg VSSRegs[64] = { PPC
::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC
::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19,
PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC
::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::
VF0, PPC::VF1, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF6
, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12
, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::
VF18, PPC::VF19, PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, PPC
::VF24, PPC::VF25, PPC::VF26, PPC::VF27, PPC::VF28, PPC::VF29
, PPC::VF30, PPC::VF31 }; static const MCPhysReg CRBITRegs[32
] = { PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, PPC::CR1LT
, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR2LT, PPC::CR2GT,
PPC::CR2EQ, PPC::CR2UN, PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC
::CR3UN, PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, PPC::
CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT
, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ,
PPC::CR7UN}; static const MCPhysReg CRRegs[8] = { PPC::CR0, PPC
::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::
CR7 }; static const MCPhysReg ACCRegs[8] = { PPC::ACC0, PPC::
ACC1, PPC::ACC2, PPC::ACC3, PPC::ACC4, PPC::ACC5, PPC::ACC6, PPC
::ACC7 }
;
21
22#define DEBUG_TYPE"ppc-disassembler" "ppc-disassembler"
23
24typedef MCDisassembler::DecodeStatus DecodeStatus;
25
26namespace {
27class PPCDisassembler : public MCDisassembler {
28 bool IsLittleEndian;
29
30public:
31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
32 bool IsLittleEndian)
33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
34
35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
36 ArrayRef<uint8_t> Bytes, uint64_t Address,
37 raw_ostream &CStream) const override;
38};
39} // end anonymous namespace
40
41static MCDisassembler *createPPCDisassembler(const Target &T,
42 const MCSubtargetInfo &STI,
43 MCContext &Ctx) {
44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
45}
46
47static MCDisassembler *createPPCLEDisassembler(const Target &T,
48 const MCSubtargetInfo &STI,
49 MCContext &Ctx) {
50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
51}
52
53extern "C" LLVM_EXTERNAL_VISIBILITY__attribute__ ((visibility("default"))) void LLVMInitializePowerPCDisassembler() {
54 // Register the disassembler for each target.
55 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(),
56 createPPCDisassembler);
57 TargetRegistry::RegisterMCDisassembler(getThePPC32LETarget(),
58 createPPCLEDisassembler);
59 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(),
60 createPPCDisassembler);
61 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(),
62 createPPCLEDisassembler);
63}
64
65static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
66 uint64_t /*Address*/,
67 const void * /*Decoder*/) {
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
69 return MCDisassembler::Success;
70}
71
72static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
73 uint64_t /*Address*/,
74 const void * /*Decoder*/) {
75 int32_t Offset = SignExtend32<24>(Imm);
76 Inst.addOperand(MCOperand::createImm(Offset));
77 return MCDisassembler::Success;
78}
79
80// FIXME: These can be generated by TableGen from the existing register
81// encoding values!
82
83template <std::size_t N>
84static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
85 const MCPhysReg (&Regs)[N]) {
86 assert(RegNo < N && "Invalid register number")(static_cast<void> (0));
87 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
88 return MCDisassembler::Success;
89}
90
91static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
92 uint64_t Address,
93 const void *Decoder) {
94 return decodeRegisterClass(Inst, RegNo, CRRegs);
95}
96
97static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
98 uint64_t Address,
99 const void *Decoder) {
100 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
101}
102
103static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
104 uint64_t Address,
105 const void *Decoder) {
106 return decodeRegisterClass(Inst, RegNo, FRegs);
107}
108
109static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
110 uint64_t Address,
111 const void *Decoder) {
112 return decodeRegisterClass(Inst, RegNo, FRegs);
113}
114
115static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
116 uint64_t Address,
117 const void *Decoder) {
118 return decodeRegisterClass(Inst, RegNo, VFRegs);
119}
120
121static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
122 uint64_t Address,
123 const void *Decoder) {
124 return decodeRegisterClass(Inst, RegNo, VRegs);
125}
126
127static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
128 uint64_t Address,
129 const void *Decoder) {
130 return decodeRegisterClass(Inst, RegNo, VSRegs);
131}
132
133static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
134 uint64_t Address,
135 const void *Decoder) {
136 return decodeRegisterClass(Inst, RegNo, VSFRegs);
137}
138
139static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
140 uint64_t Address,
141 const void *Decoder) {
142 return decodeRegisterClass(Inst, RegNo, VSSRegs);
143}
144
145static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
146 uint64_t Address,
147 const void *Decoder) {
148 return decodeRegisterClass(Inst, RegNo, RRegs);
149}
150
151static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
152 uint64_t Address,
153 const void *Decoder) {
154 return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
155}
156
157static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
158 uint64_t Address,
159 const void *Decoder) {
160 return decodeRegisterClass(Inst, RegNo, XRegs);
161}
162
163static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo,
164 uint64_t Address,
165 const void *Decoder) {
166 return decodeRegisterClass(Inst, RegNo, XRegs);
167}
168
169static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
170 uint64_t Address,
171 const void *Decoder) {
172 return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
173}
174
175#define DecodePointerLikeRegClass0DecodeGPRCRegisterClass DecodeGPRCRegisterClass
176#define DecodePointerLikeRegClass1DecodeGPRC_NOR0RegisterClass DecodeGPRC_NOR0RegisterClass
177
178static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
179 uint64_t Address,
180 const void *Decoder) {
181 return decodeRegisterClass(Inst, RegNo, SPERegs);
182}
183
184static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
185 uint64_t Address,
186 const void *Decoder) {
187 return decodeRegisterClass(Inst, RegNo, ACCRegs);
188}
189
190static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
191 uint64_t Address,
192 const void *Decoder) {
193 return decodeRegisterClass(Inst, RegNo, VSRpRegs);
194}
195
196#define DecodeQSRCRegisterClassDecodeQFRCRegisterClass DecodeQFRCRegisterClass
197#define DecodeQBRCRegisterClassDecodeQFRCRegisterClass DecodeQFRCRegisterClass
198
199template<unsigned N>
200static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
201 int64_t Address, const void *Decoder) {
202 assert(isUInt<N>(Imm) && "Invalid immediate")(static_cast<void> (0));
203 Inst.addOperand(MCOperand::createImm(Imm));
204 return MCDisassembler::Success;
205}
206
207template<unsigned N>
208static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
209 int64_t Address, const void *Decoder) {
210 assert(isUInt<N>(Imm) && "Invalid immediate")(static_cast<void> (0));
211 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
212 return MCDisassembler::Success;
213}
214
215static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
216 int64_t Address, const void *Decoder) {
217 if (Imm != 0)
218 return MCDisassembler::Fail;
219 Inst.addOperand(MCOperand::createImm(Imm));
220 return MCDisassembler::Success;
221}
222
223static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
224 uint64_t Address,
225 const void *Decoder) {
226 if (RegNo & 1)
227 return MCDisassembler::Fail;
228 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
229 return MCDisassembler::Success;
230}
231
232static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
233 int64_t Address, const void *Decoder) {
234 // Decode the memri field (imm, reg), which has the low 16-bits as the
235 // displacement and the next 5 bits as the register #.
236
237 uint64_t Base = Imm >> 16;
238 uint64_t Disp = Imm & 0xFFFF;
239
240 assert(Base < 32 && "Invalid base register")(static_cast<void> (0));
241
242 switch (Inst.getOpcode()) {
243 default: break;
244 case PPC::LBZU:
245 case PPC::LHAU:
246 case PPC::LHZU:
247 case PPC::LWZU:
248 case PPC::LFSU:
249 case PPC::LFDU:
250 // Add the tied output operand.
251 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
252 break;
253 case PPC::STBU:
254 case PPC::STHU:
255 case PPC::STWU:
256 case PPC::STFSU:
257 case PPC::STFDU:
258 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
259 break;
260 }
261
262 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
263 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
264 return MCDisassembler::Success;
265}
266
267static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
268 int64_t Address, const void *Decoder) {
269 // Decode the memrix field (imm, reg), which has the low 14-bits as the
270 // displacement and the next 5 bits as the register #.
271
272 uint64_t Base = Imm >> 14;
273 uint64_t Disp = Imm & 0x3FFF;
274
275 assert(Base < 32 && "Invalid base register")(static_cast<void> (0));
276
277 if (Inst.getOpcode() == PPC::LDU)
278 // Add the tied output operand.
279 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
280 else if (Inst.getOpcode() == PPC::STDU)
281 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
282
283 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
284 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
285 return MCDisassembler::Success;
286}
287
288static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm,
289 int64_t Address,
290 const void *Decoder) {
291 // Decode the memrix field for a hash store or hash check operation.
292 // The field is composed of a register and an immediate value that is 6 bits
293 // and covers the range -8 to -512. The immediate is always negative and 2s
294 // complement which is why we sign extend a 7 bit value.
295 const uint64_t Base = Imm >> 6;
296 const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
297
298 assert(Base < 32 && "Invalid base register")(static_cast<void> (0));
299
300 Inst.addOperand(MCOperand::createImm(Disp));
301 Inst.addOperand(MCOperand::createReg(RRegs[Base]));
302 return MCDisassembler::Success;
303}
304
305static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
306 int64_t Address, const void *Decoder) {
307 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the
308 // displacement with 16-byte aligned, and the next 5 bits as the register #.
309
310 uint64_t Base = Imm >> 12;
311 uint64_t Disp = Imm & 0xFFF;
312
313 assert(Base < 32 && "Invalid base register")(static_cast<void> (0));
314
315 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
316 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
317 return MCDisassembler::Success;
318}
319
320static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
321 int64_t Address,
322 const void *Decoder) {
323 // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
324 // displacement, and the next 5 bits as an immediate 0.
325 uint64_t Base = Imm >> 34;
326 uint64_t Disp = Imm & 0x3FFFFFFFFUL;
327
328 assert(Base < 32 && "Invalid base register")(static_cast<void> (0));
329
330 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
331 return decodeImmZeroOperand(Inst, Base, Address, Decoder);
332}
333
334static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
335 int64_t Address,
336 const void *Decoder) {
337 // Decode the memri34 field (imm, reg), which has the low 34-bits as the
338 // displacement, and the next 5 bits as the register #.
339 uint64_t Base = Imm >> 34;
340 uint64_t Disp = Imm & 0x3FFFFFFFFUL;
341
342 assert(Base < 32 && "Invalid base register")(static_cast<void> (0));
343
344 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
345 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
346 return MCDisassembler::Success;
347}
348
349static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
350 int64_t Address, const void *Decoder) {
351 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
352 // displacement with 8-byte aligned, and the next 5 bits as the register #.
353
354 uint64_t Base = Imm >> 5;
355 uint64_t Disp = Imm & 0x1F;
356
357 assert(Base < 32 && "Invalid base register")(static_cast<void> (0));
358
359 Inst.addOperand(MCOperand::createImm(Disp << 3));
360 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
361 return MCDisassembler::Success;
362}
363
364static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
365 int64_t Address, const void *Decoder) {
366 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the
367 // displacement with 4-byte aligned, and the next 5 bits as the register #.
368
369 uint64_t Base = Imm >> 5;
370 uint64_t Disp = Imm & 0x1F;
371
372 assert(Base < 32 && "Invalid base register")(static_cast<void> (0));
373
374 Inst.addOperand(MCOperand::createImm(Disp << 2));
375 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
376 return MCDisassembler::Success;
377}
378
379static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
380 int64_t Address, const void *Decoder) {
381 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the
382 // displacement with 2-byte aligned, and the next 5 bits as the register #.
383
384 uint64_t Base = Imm >> 5;
385 uint64_t Disp = Imm & 0x1F;
386
387 assert(Base < 32 && "Invalid base register")(static_cast<void> (0));
388
389 Inst.addOperand(MCOperand::createImm(Disp << 1));
390 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
391 return MCDisassembler::Success;
392}
393
394static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
395 int64_t Address, const void *Decoder) {
396 // The cr bit encoding is 0x80 >> cr_reg_num.
397
398 unsigned Zeros = countTrailingZeros(Imm);
399 assert(Zeros < 8 && "Invalid CR bit value")(static_cast<void> (0));
400
401 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
1st function call argument is an uninitialized value
402 return MCDisassembler::Success;
403}
404
405#include "PPCGenDisassemblerTables.inc"
406
407DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
408 ArrayRef<uint8_t> Bytes,
409 uint64_t Address,
410 raw_ostream &CS) const {
411 auto *ReadFunc = IsLittleEndian ? support::endian::read32le
412 : support::endian::read32be;
413
414 // If this is an 8-byte prefixed instruction, handle it here.
415 // Note: prefixed instructions aren't technically 8-byte entities - the prefix
416 // appears in memory at an address 4 bytes prior to that of the base
417 // instruction regardless of endianness. So we read the two pieces and
418 // rebuild the 8-byte instruction.
419 // TODO: In this function we call decodeInstruction several times with
420 // different decoder tables. It may be possible to only call once by
421 // looking at the top 6 bits of the instruction.
422 if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) {
423 uint32_t Prefix = ReadFunc(Bytes.data());
424 uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
425 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
426 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
427 this, STI);
428 if (result != MCDisassembler::Fail) {
429 Size = 8;
430 return result;
431 }
432 }
433
434 // Get the four bytes of the instruction.
435 Size = 4;
436 if (Bytes.size() < 4) {
437 Size = 0;
438 return MCDisassembler::Fail;
439 }
440
441 // Read the instruction in the proper endianness.
442 uint64_t Inst = ReadFunc(Bytes.data());
443
444 if (STI.getFeatureBits()[PPC::FeatureSPE]) {
445 DecodeStatus result =
446 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
447 if (result != MCDisassembler::Fail)
448 return result;
449 }
450
451 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
452}