Bug Summary

File:llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Warning:line 10049, column 31
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/lib/Target/PowerPC -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-11-29-190409-37574-1 -x c++ /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
14#include "MCTargetDesc/PPCPredicates.h"
15#include "PPC.h"
16#include "PPCCCState.h"
17#include "PPCCallingConv.h"
18#include "PPCFrameLowering.h"
19#include "PPCInstrInfo.h"
20#include "PPCMachineFunctionInfo.h"
21#include "PPCPerfectShuffle.h"
22#include "PPCRegisterInfo.h"
23#include "PPCSubtarget.h"
24#include "PPCTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/None.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
36#include "llvm/ADT/StringSwitch.h"
37#include "llvm/CodeGen/CallingConvLower.h"
38#include "llvm/CodeGen/ISDOpcodes.h"
39#include "llvm/CodeGen/MachineBasicBlock.h"
40#include "llvm/CodeGen/MachineFrameInfo.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineInstr.h"
43#include "llvm/CodeGen/MachineInstrBuilder.h"
44#include "llvm/CodeGen/MachineJumpTableInfo.h"
45#include "llvm/CodeGen/MachineLoopInfo.h"
46#include "llvm/CodeGen/MachineMemOperand.h"
47#include "llvm/CodeGen/MachineModuleInfo.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/RuntimeLibcalls.h"
51#include "llvm/CodeGen/SelectionDAG.h"
52#include "llvm/CodeGen/SelectionDAGNodes.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetLowering.h"
55#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
56#include "llvm/CodeGen/TargetRegisterInfo.h"
57#include "llvm/CodeGen/ValueTypes.h"
58#include "llvm/IR/CallingConv.h"
59#include "llvm/IR/Constant.h"
60#include "llvm/IR/Constants.h"
61#include "llvm/IR/DataLayout.h"
62#include "llvm/IR/DebugLoc.h"
63#include "llvm/IR/DerivedTypes.h"
64#include "llvm/IR/Function.h"
65#include "llvm/IR/GlobalValue.h"
66#include "llvm/IR/IRBuilder.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/Intrinsics.h"
69#include "llvm/IR/IntrinsicsPowerPC.h"
70#include "llvm/IR/Module.h"
71#include "llvm/IR/Type.h"
72#include "llvm/IR/Use.h"
73#include "llvm/IR/Value.h"
74#include "llvm/MC/MCContext.h"
75#include "llvm/MC/MCExpr.h"
76#include "llvm/MC/MCRegisterInfo.h"
77#include "llvm/MC/MCSectionXCOFF.h"
78#include "llvm/MC/MCSymbolXCOFF.h"
79#include "llvm/Support/AtomicOrdering.h"
80#include "llvm/Support/BranchProbability.h"
81#include "llvm/Support/Casting.h"
82#include "llvm/Support/CodeGen.h"
83#include "llvm/Support/CommandLine.h"
84#include "llvm/Support/Compiler.h"
85#include "llvm/Support/Debug.h"
86#include "llvm/Support/ErrorHandling.h"
87#include "llvm/Support/Format.h"
88#include "llvm/Support/KnownBits.h"
89#include "llvm/Support/MachineValueType.h"
90#include "llvm/Support/MathExtras.h"
91#include "llvm/Support/raw_ostream.h"
92#include "llvm/Target/TargetMachine.h"
93#include "llvm/Target/TargetOptions.h"
94#include <algorithm>
95#include <cassert>
96#include <cstdint>
97#include <iterator>
98#include <list>
99#include <utility>
100#include <vector>
101
102using namespace llvm;
103
104#define DEBUG_TYPE"ppc-lowering" "ppc-lowering"
105
106static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
107cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
108
109static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
110cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
111
112static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
113cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
114
115static cl::opt<bool> DisableSCO("disable-ppc-sco",
116cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
117
118static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
119cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
120
121static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
122cl::desc("use absolute jump tables on ppc"), cl::Hidden);
123
124// TODO - Remove this option if soft fp128 has been fully supported .
125static cl::opt<bool>
126 EnableSoftFP128("enable-soft-fp128",
127 cl::desc("temp option to enable soft fp128"), cl::Hidden);
128
129STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"ppc-lowering", "NumTailCalls"
, "Number of tail calls"}
;
130STATISTIC(NumSiblingCalls, "Number of sibling calls")static llvm::Statistic NumSiblingCalls = {"ppc-lowering", "NumSiblingCalls"
, "Number of sibling calls"}
;
131STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM")static llvm::Statistic ShufflesHandledWithVPERM = {"ppc-lowering"
, "ShufflesHandledWithVPERM", "Number of shuffles lowered to a VPERM"
}
;
132STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed")static llvm::Statistic NumDynamicAllocaProbed = {"ppc-lowering"
, "NumDynamicAllocaProbed", "Number of dynamic stack allocation probed"
}
;
133
134static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
135
136static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
137
138// FIXME: Remove this once the bug has been fixed!
139extern cl::opt<bool> ANDIGlueBug;
140
141PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
142 const PPCSubtarget &STI)
143 : TargetLowering(TM), Subtarget(STI) {
144 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
145 // arguments are at least 4/8 bytes aligned.
146 bool isPPC64 = Subtarget.isPPC64();
147 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
148
149 // Set up the register classes.
150 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
151 if (!useSoftFloat()) {
152 if (hasSPE()) {
153 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
154 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
155 } else {
156 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
157 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
158 }
159 }
160
161 // Match BITREVERSE to customized fast code sequence in the td file.
162 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
163 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
164
165 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
166 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
167
168 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
169 for (MVT VT : MVT::integer_valuetypes()) {
170 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
171 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
172 }
173
174 if (Subtarget.isISA3_0()) {
175 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
176 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
177 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
178 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
179 } else {
180 // No extending loads from f16 or HW conversions back and forth.
181 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
182 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
183 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
184 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
185 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
186 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
187 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
188 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
189 }
190
191 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
192
193 // PowerPC has pre-inc load and store's.
194 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
195 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
196 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
197 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
198 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
199 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
200 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
201 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
202 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
203 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
204 if (!Subtarget.hasSPE()) {
205 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
206 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
207 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
208 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
209 }
210
211 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
212 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
213 for (MVT VT : ScalarIntVTs) {
214 setOperationAction(ISD::ADDC, VT, Legal);
215 setOperationAction(ISD::ADDE, VT, Legal);
216 setOperationAction(ISD::SUBC, VT, Legal);
217 setOperationAction(ISD::SUBE, VT, Legal);
218 }
219
220 if (Subtarget.useCRBits()) {
221 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
222
223 if (isPPC64 || Subtarget.hasFPCVT()) {
224 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Promote);
225 AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1,
226 isPPC64 ? MVT::i64 : MVT::i32);
227 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Promote);
228 AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1,
229 isPPC64 ? MVT::i64 : MVT::i32);
230
231 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
232 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
233 isPPC64 ? MVT::i64 : MVT::i32);
234 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
235 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
236 isPPC64 ? MVT::i64 : MVT::i32);
237 } else {
238 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom);
239 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom);
240 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
241 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
242 }
243
244 // PowerPC does not support direct load/store of condition registers.
245 setOperationAction(ISD::LOAD, MVT::i1, Custom);
246 setOperationAction(ISD::STORE, MVT::i1, Custom);
247
248 // FIXME: Remove this once the ANDI glue bug is fixed:
249 if (ANDIGlueBug)
250 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
251
252 for (MVT VT : MVT::integer_valuetypes()) {
253 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
254 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
255 setTruncStoreAction(VT, MVT::i1, Expand);
256 }
257
258 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
259 }
260
261 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
262 // PPC (the libcall is not available).
263 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
264 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
265 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::ppcf128, Custom);
266 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::ppcf128, Custom);
267
268 // We do not currently implement these libm ops for PowerPC.
269 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
270 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
271 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
272 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
273 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
274 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
275
276 // PowerPC has no SREM/UREM instructions unless we are on P9
277 // On P9 we may use a hardware instruction to compute the remainder.
278 // When the result of both the remainder and the division is required it is
279 // more efficient to compute the remainder from the result of the division
280 // rather than use the remainder instruction. The instructions are legalized
281 // directly because the DivRemPairsPass performs the transformation at the IR
282 // level.
283 if (Subtarget.isISA3_0()) {
284 setOperationAction(ISD::SREM, MVT::i32, Legal);
285 setOperationAction(ISD::UREM, MVT::i32, Legal);
286 setOperationAction(ISD::SREM, MVT::i64, Legal);
287 setOperationAction(ISD::UREM, MVT::i64, Legal);
288 } else {
289 setOperationAction(ISD::SREM, MVT::i32, Expand);
290 setOperationAction(ISD::UREM, MVT::i32, Expand);
291 setOperationAction(ISD::SREM, MVT::i64, Expand);
292 setOperationAction(ISD::UREM, MVT::i64, Expand);
293 }
294
295 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
296 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
297 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
298 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
299 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
300 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
301 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
302 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
303 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
304
305 // Handle constrained floating-point operations of scalar.
306 // TODO: Handle SPE specific operation.
307 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
308 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
309 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
310 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
311 setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal);
312 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
313
314 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
315 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
316 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
317 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
318 setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal);
319 if (Subtarget.hasVSX()) {
320 setOperationAction(ISD::STRICT_FRINT, MVT::f32, Legal);
321 setOperationAction(ISD::STRICT_FRINT, MVT::f64, Legal);
322 }
323
324 if (Subtarget.hasFSQRT()) {
325 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
326 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
327 }
328
329 if (Subtarget.hasFPRND()) {
330 setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal);
331 setOperationAction(ISD::STRICT_FCEIL, MVT::f32, Legal);
332 setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal);
333 setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal);
334
335 setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal);
336 setOperationAction(ISD::STRICT_FCEIL, MVT::f64, Legal);
337 setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal);
338 setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal);
339 }
340
341 // We don't support sin/cos/sqrt/fmod/pow
342 setOperationAction(ISD::FSIN , MVT::f64, Expand);
343 setOperationAction(ISD::FCOS , MVT::f64, Expand);
344 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
345 setOperationAction(ISD::FREM , MVT::f64, Expand);
346 setOperationAction(ISD::FPOW , MVT::f64, Expand);
347 setOperationAction(ISD::FSIN , MVT::f32, Expand);
348 setOperationAction(ISD::FCOS , MVT::f32, Expand);
349 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
350 setOperationAction(ISD::FREM , MVT::f32, Expand);
351 setOperationAction(ISD::FPOW , MVT::f32, Expand);
352 if (Subtarget.hasSPE()) {
353 setOperationAction(ISD::FMA , MVT::f64, Expand);
354 setOperationAction(ISD::FMA , MVT::f32, Expand);
355 } else {
356 setOperationAction(ISD::FMA , MVT::f64, Legal);
357 setOperationAction(ISD::FMA , MVT::f32, Legal);
358 }
359
360 if (Subtarget.hasSPE())
361 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
362
363 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
364
365 // If we're enabling GP optimizations, use hardware square root
366 if (!Subtarget.hasFSQRT() &&
367 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
368 Subtarget.hasFRE()))
369 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
370
371 if (!Subtarget.hasFSQRT() &&
372 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
373 Subtarget.hasFRES()))
374 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
375
376 if (Subtarget.hasFCPSGN()) {
377 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
378 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
379 } else {
380 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
381 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
382 }
383
384 if (Subtarget.hasFPRND()) {
385 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
386 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
387 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
388 setOperationAction(ISD::FROUND, MVT::f64, Legal);
389
390 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
391 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
392 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
393 setOperationAction(ISD::FROUND, MVT::f32, Legal);
394 }
395
396 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
397 // to speed up scalar BSWAP64.
398 // CTPOP or CTTZ were introduced in P8/P9 respectively
399 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
400 if (Subtarget.hasP9Vector())
401 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
402 else
403 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
404 if (Subtarget.isISA3_0()) {
405 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
406 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
407 } else {
408 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
409 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
410 }
411
412 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
413 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
414 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
415 } else {
416 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
417 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
418 }
419
420 // PowerPC does not have ROTR
421 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
422 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
423
424 if (!Subtarget.useCRBits()) {
425 // PowerPC does not have Select
426 setOperationAction(ISD::SELECT, MVT::i32, Expand);
427 setOperationAction(ISD::SELECT, MVT::i64, Expand);
428 setOperationAction(ISD::SELECT, MVT::f32, Expand);
429 setOperationAction(ISD::SELECT, MVT::f64, Expand);
430 }
431
432 // PowerPC wants to turn select_cc of FP into fsel when possible.
433 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
434 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
435
436 // PowerPC wants to optimize integer setcc a bit
437 if (!Subtarget.useCRBits())
438 setOperationAction(ISD::SETCC, MVT::i32, Custom);
439
440 if (Subtarget.hasFPU()) {
441 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal);
442 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal);
443 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal);
444
445 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
446 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
447 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal);
448 }
449
450 // PowerPC does not have BRCOND which requires SetCC
451 if (!Subtarget.useCRBits())
452 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
453
454 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
455
456 if (Subtarget.hasSPE()) {
457 // SPE has built-in conversions
458 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal);
459 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Legal);
460 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Legal);
461 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
462 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
463 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
464 } else {
465 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
466 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
467 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
468
469 // PowerPC does not have [U|S]INT_TO_FP
470 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Expand);
471 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Expand);
472 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
473 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
474 }
475
476 if (Subtarget.hasDirectMove() && isPPC64) {
477 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
478 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
479 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
480 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
481 if (TM.Options.UnsafeFPMath) {
482 setOperationAction(ISD::LRINT, MVT::f64, Legal);
483 setOperationAction(ISD::LRINT, MVT::f32, Legal);
484 setOperationAction(ISD::LLRINT, MVT::f64, Legal);
485 setOperationAction(ISD::LLRINT, MVT::f32, Legal);
486 setOperationAction(ISD::LROUND, MVT::f64, Legal);
487 setOperationAction(ISD::LROUND, MVT::f32, Legal);
488 setOperationAction(ISD::LLROUND, MVT::f64, Legal);
489 setOperationAction(ISD::LLROUND, MVT::f32, Legal);
490 }
491 } else {
492 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
493 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
494 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
495 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
496 }
497
498 // We cannot sextinreg(i1). Expand to shifts.
499 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
500
501 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
502 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
503 // support continuation, user-level threading, and etc.. As a result, no
504 // other SjLj exception interfaces are implemented and please don't build
505 // your own exception handling based on them.
506 // LLVM/Clang supports zero-cost DWARF exception handling.
507 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
508 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
509
510 // We want to legalize GlobalAddress and ConstantPool nodes into the
511 // appropriate instructions to materialize the address.
512 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
513 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
514 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
515 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
516 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
517 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
518 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
519 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
520 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
521 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
522
523 // TRAP is legal.
524 setOperationAction(ISD::TRAP, MVT::Other, Legal);
525
526 // TRAMPOLINE is custom lowered.
527 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
528 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
529
530 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
531 setOperationAction(ISD::VASTART , MVT::Other, Custom);
532
533 if (Subtarget.is64BitELFABI()) {
534 // VAARG always uses double-word chunks, so promote anything smaller.
535 setOperationAction(ISD::VAARG, MVT::i1, Promote);
536 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
537 setOperationAction(ISD::VAARG, MVT::i8, Promote);
538 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
539 setOperationAction(ISD::VAARG, MVT::i16, Promote);
540 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
541 setOperationAction(ISD::VAARG, MVT::i32, Promote);
542 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
543 setOperationAction(ISD::VAARG, MVT::Other, Expand);
544 } else if (Subtarget.is32BitELFABI()) {
545 // VAARG is custom lowered with the 32-bit SVR4 ABI.
546 setOperationAction(ISD::VAARG, MVT::Other, Custom);
547 setOperationAction(ISD::VAARG, MVT::i64, Custom);
548 } else
549 setOperationAction(ISD::VAARG, MVT::Other, Expand);
550
551 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
552 if (Subtarget.is32BitELFABI())
553 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
554 else
555 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
556
557 // Use the default implementation.
558 setOperationAction(ISD::VAEND , MVT::Other, Expand);
559 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
560 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
561 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
562 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
563 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
564 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
565 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
566 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
567
568 // We want to custom lower some of our intrinsics.
569 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
570
571 // To handle counter-based loop conditions.
572 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
573
574 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
575 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
576 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
578
579 // Comparisons that require checking two conditions.
580 if (Subtarget.hasSPE()) {
581 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
582 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
583 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
584 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
585 }
586 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
587 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
588 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
589 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
590 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
591 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
592 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
593 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
594 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
595 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
596 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
597 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
598
599 if (Subtarget.has64BitSupport()) {
600 // They also have instructions for converting between i64 and fp.
601 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
602 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand);
603 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
604 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand);
605 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
606 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
607 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
608 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
609 // This is just the low 32 bits of a (signed) fp->i64 conversion.
610 // We cannot do this with Promote because i64 is not a legal type.
611 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
612 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
613
614 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
615 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
616 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
617 }
618 } else {
619 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
620 if (Subtarget.hasSPE()) {
621 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal);
622 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
623 } else {
624 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand);
625 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
626 }
627 }
628
629 // With the instructions enabled under FPCVT, we can do everything.
630 if (Subtarget.hasFPCVT()) {
631 if (Subtarget.has64BitSupport()) {
632 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
633 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
634 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
635 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
636 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
637 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
638 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
639 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
640 }
641
642 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
643 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
644 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
645 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
646 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
647 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
648 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
649 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
650 }
651
652 if (Subtarget.use64BitRegs()) {
653 // 64-bit PowerPC implementations can support i64 types directly
654 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
655 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
656 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
657 // 64-bit PowerPC wants to expand i128 shifts itself.
658 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
659 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
660 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
661 } else {
662 // 32-bit PowerPC wants to expand i64 shifts itself.
663 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
664 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
665 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
666 }
667
668 // PowerPC has better expansions for funnel shifts than the generic
669 // TargetLowering::expandFunnelShift.
670 if (Subtarget.has64BitSupport()) {
671 setOperationAction(ISD::FSHL, MVT::i64, Custom);
672 setOperationAction(ISD::FSHR, MVT::i64, Custom);
673 }
674 setOperationAction(ISD::FSHL, MVT::i32, Custom);
675 setOperationAction(ISD::FSHR, MVT::i32, Custom);
676
677 if (Subtarget.hasVSX()) {
678 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
679 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
680 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
681 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
682 }
683
684 if (Subtarget.hasAltivec()) {
685 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
686 setOperationAction(ISD::SADDSAT, VT, Legal);
687 setOperationAction(ISD::SSUBSAT, VT, Legal);
688 setOperationAction(ISD::UADDSAT, VT, Legal);
689 setOperationAction(ISD::USUBSAT, VT, Legal);
690 }
691 // First set operation action for all vector types to expand. Then we
692 // will selectively turn on ones that can be effectively codegen'd.
693 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
694 // add/sub are legal for all supported vector VT's.
695 setOperationAction(ISD::ADD, VT, Legal);
696 setOperationAction(ISD::SUB, VT, Legal);
697
698 // For v2i64, these are only valid with P8Vector. This is corrected after
699 // the loop.
700 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
701 setOperationAction(ISD::SMAX, VT, Legal);
702 setOperationAction(ISD::SMIN, VT, Legal);
703 setOperationAction(ISD::UMAX, VT, Legal);
704 setOperationAction(ISD::UMIN, VT, Legal);
705 }
706 else {
707 setOperationAction(ISD::SMAX, VT, Expand);
708 setOperationAction(ISD::SMIN, VT, Expand);
709 setOperationAction(ISD::UMAX, VT, Expand);
710 setOperationAction(ISD::UMIN, VT, Expand);
711 }
712
713 if (Subtarget.hasVSX()) {
714 setOperationAction(ISD::FMAXNUM, VT, Legal);
715 setOperationAction(ISD::FMINNUM, VT, Legal);
716 }
717
718 // Vector instructions introduced in P8
719 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
720 setOperationAction(ISD::CTPOP, VT, Legal);
721 setOperationAction(ISD::CTLZ, VT, Legal);
722 }
723 else {
724 setOperationAction(ISD::CTPOP, VT, Expand);
725 setOperationAction(ISD::CTLZ, VT, Expand);
726 }
727
728 // Vector instructions introduced in P9
729 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
730 setOperationAction(ISD::CTTZ, VT, Legal);
731 else
732 setOperationAction(ISD::CTTZ, VT, Expand);
733
734 // We promote all shuffles to v16i8.
735 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
736 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
737
738 // We promote all non-typed operations to v4i32.
739 setOperationAction(ISD::AND , VT, Promote);
740 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
741 setOperationAction(ISD::OR , VT, Promote);
742 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
743 setOperationAction(ISD::XOR , VT, Promote);
744 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
745 setOperationAction(ISD::LOAD , VT, Promote);
746 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
747 setOperationAction(ISD::SELECT, VT, Promote);
748 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
749 setOperationAction(ISD::VSELECT, VT, Legal);
750 setOperationAction(ISD::SELECT_CC, VT, Promote);
751 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
752 setOperationAction(ISD::STORE, VT, Promote);
753 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
754
755 // No other operations are legal.
756 setOperationAction(ISD::MUL , VT, Expand);
757 setOperationAction(ISD::SDIV, VT, Expand);
758 setOperationAction(ISD::SREM, VT, Expand);
759 setOperationAction(ISD::UDIV, VT, Expand);
760 setOperationAction(ISD::UREM, VT, Expand);
761 setOperationAction(ISD::FDIV, VT, Expand);
762 setOperationAction(ISD::FREM, VT, Expand);
763 setOperationAction(ISD::FNEG, VT, Expand);
764 setOperationAction(ISD::FSQRT, VT, Expand);
765 setOperationAction(ISD::FLOG, VT, Expand);
766 setOperationAction(ISD::FLOG10, VT, Expand);
767 setOperationAction(ISD::FLOG2, VT, Expand);
768 setOperationAction(ISD::FEXP, VT, Expand);
769 setOperationAction(ISD::FEXP2, VT, Expand);
770 setOperationAction(ISD::FSIN, VT, Expand);
771 setOperationAction(ISD::FCOS, VT, Expand);
772 setOperationAction(ISD::FABS, VT, Expand);
773 setOperationAction(ISD::FFLOOR, VT, Expand);
774 setOperationAction(ISD::FCEIL, VT, Expand);
775 setOperationAction(ISD::FTRUNC, VT, Expand);
776 setOperationAction(ISD::FRINT, VT, Expand);
777 setOperationAction(ISD::FNEARBYINT, VT, Expand);
778 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
780 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
781 setOperationAction(ISD::MULHU, VT, Expand);
782 setOperationAction(ISD::MULHS, VT, Expand);
783 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
784 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
785 setOperationAction(ISD::UDIVREM, VT, Expand);
786 setOperationAction(ISD::SDIVREM, VT, Expand);
787 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
788 setOperationAction(ISD::FPOW, VT, Expand);
789 setOperationAction(ISD::BSWAP, VT, Expand);
790 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
791 setOperationAction(ISD::ROTL, VT, Expand);
792 setOperationAction(ISD::ROTR, VT, Expand);
793
794 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
795 setTruncStoreAction(VT, InnerVT, Expand);
796 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
797 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
798 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
799 }
800 }
801 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand);
802 if (!Subtarget.hasP8Vector()) {
803 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
804 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
805 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
806 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
807 }
808
809 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
810 // with merges, splats, etc.
811 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
812
813 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
814 // are cheap, so handle them before they get expanded to scalar.
815 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
816 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
817 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
818 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
819 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
820
821 setOperationAction(ISD::AND , MVT::v4i32, Legal);
822 setOperationAction(ISD::OR , MVT::v4i32, Legal);
823 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
824 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
825 setOperationAction(ISD::SELECT, MVT::v4i32,
826 Subtarget.useCRBits() ? Legal : Expand);
827 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
828 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
829 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
830 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
831 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
832 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
833 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
834 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
835 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
836 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
837 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
838 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
839 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
840
841 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
842 setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
843 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
844 if (Subtarget.hasAltivec())
845 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
846 setOperationAction(ISD::ROTL, VT, Legal);
847 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
848 if (Subtarget.hasP8Altivec())
849 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
850
851 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
852 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
853 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
854 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
855
856 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
857 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
858
859 if (Subtarget.hasVSX()) {
860 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
861 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
862 }
863
864 if (Subtarget.hasP8Altivec())
865 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
866 else
867 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
868
869 if (Subtarget.isISA3_1()) {
870 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
871 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
872 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
873 setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
874 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
875 setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
876 setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
877 setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
878 setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
879 setOperationAction(ISD::UREM, MVT::v2i64, Legal);
880 setOperationAction(ISD::SREM, MVT::v2i64, Legal);
881 setOperationAction(ISD::UREM, MVT::v4i32, Legal);
882 setOperationAction(ISD::SREM, MVT::v4i32, Legal);
883 setOperationAction(ISD::UREM, MVT::v1i128, Legal);
884 setOperationAction(ISD::SREM, MVT::v1i128, Legal);
885 setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
886 setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
887 setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
888 }
889
890 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
891 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
892
893 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
894 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
895
896 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
897 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
898 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
899 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
900
901 // Altivec does not contain unordered floating-point compare instructions
902 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
903 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
904 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
905 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
906
907 if (Subtarget.hasVSX()) {
908 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
909 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
910 if (Subtarget.hasP8Vector()) {
911 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
912 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
913 }
914 if (Subtarget.hasDirectMove() && isPPC64) {
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
919 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
920 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
921 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
922 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
923 }
924 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
925
926 // The nearbyint variants are not allowed to raise the inexact exception
927 // so we can only code-gen them with unsafe math.
928 if (TM.Options.UnsafeFPMath) {
929 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
930 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
931 }
932
933 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
934 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
935 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
936 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
937 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
938 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
939 setOperationAction(ISD::FROUND, MVT::f64, Legal);
940 setOperationAction(ISD::FRINT, MVT::f64, Legal);
941
942 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
943 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
944 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
945 setOperationAction(ISD::FROUND, MVT::f32, Legal);
946 setOperationAction(ISD::FRINT, MVT::f32, Legal);
947
948 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
949 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
950
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953
954 // Share the Altivec comparison restrictions.
955 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
956 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
957 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
958 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
959
960 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
961 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
962
963 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
964
965 if (Subtarget.hasP8Vector())
966 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
967
968 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
969
970 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
971 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
972 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
973
974 if (Subtarget.hasP8Altivec()) {
975 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
976 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
977 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
978
979 // 128 bit shifts can be accomplished via 3 instructions for SHL and
980 // SRL, but not for SRA because of the instructions available:
981 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
982 // doing
983 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
984 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
985 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
986
987 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
988 }
989 else {
990 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
991 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
992 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
993
994 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
995
996 // VSX v2i64 only supports non-arithmetic operations.
997 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
998 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
999 }
1000
1001 if (Subtarget.isISA3_1())
1002 setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
1003 else
1004 setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
1005
1006 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
1007 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
1008 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
1009 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
1010
1011 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
1012
1013 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
1014 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
1015 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
1016 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
1017 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1018 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1019 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1020 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1021
1022 // Custom handling for partial vectors of integers converted to
1023 // floating point. We already have optimal handling for v2i32 through
1024 // the DAG combine, so those aren't necessary.
1025 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom);
1026 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom);
1027 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
1028 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
1029 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom);
1030 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom);
1031 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
1032 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
1033 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
1034 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1035 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
1036 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1037 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom);
1038 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
1040 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
1041
1042 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1043 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1044 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
1045 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1046 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
1047 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
1048
1049 if (Subtarget.hasDirectMove())
1050 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1051 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1052
1053 // Handle constrained floating-point operations of vector.
1054 // The predictor is `hasVSX` because altivec instruction has
1055 // no exception but VSX vector instruction has.
1056 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
1057 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
1058 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
1059 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
1060 setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal);
1061 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
1062 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v4f32, Legal);
1063 setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal);
1064 setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal);
1065 setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
1066 setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal);
1067 setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
1068 setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
1069
1070 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
1071 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
1072 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
1073 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
1074 setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal);
1075 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1076 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v2f64, Legal);
1077 setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal);
1078 setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal);
1079 setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
1080 setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal);
1081 setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
1082 setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
1083
1084 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1085 }
1086
1087 if (Subtarget.hasP8Altivec()) {
1088 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
1089 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
1090 }
1091
1092 if (Subtarget.hasP9Vector()) {
1093 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1094 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1095
1096 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1097 // SRL, but not for SRA because of the instructions available:
1098 // VS{RL} and VS{RL}O.
1099 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1100 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
1101 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1102
1103 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1104 setOperationAction(ISD::FADD, MVT::f128, Legal);
1105 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1106 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1107 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1108 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1109 // No extending loads to f128 on PPC.
1110 for (MVT FPT : MVT::fp_valuetypes())
1111 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1112 setOperationAction(ISD::FMA, MVT::f128, Legal);
1113 setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
1114 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
1115 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
1116 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
1117 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
1118 setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
1119
1120 setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
1121 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1122 setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
1123 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1124 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
1125 setOperationAction(ISD::FROUND, MVT::f128, Legal);
1126
1127 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1128 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1129 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
1130 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1131 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1132 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
1133 // No implementation for these ops for PowerPC.
1134 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1135 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1136 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1137 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
1138 setOperationAction(ISD::FREM, MVT::f128, Expand);
1139
1140 // Handle constrained floating-point operations of fp128
1141 setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
1142 setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
1143 setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
1144 setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
1145 setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
1146 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
1147 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
1148 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
1149 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
1150 setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
1151 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
1152 setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
1153 setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
1154 setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
1155 setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
1156 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1157 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1158 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1159 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
1160 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
1161 } else if (Subtarget.hasAltivec() && EnableSoftFP128) {
1162 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1163
1164 for (MVT FPT : MVT::fp_valuetypes())
1165 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1166
1167 setOperationAction(ISD::LOAD, MVT::f128, Promote);
1168 setOperationAction(ISD::STORE, MVT::f128, Promote);
1169
1170 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
1171 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
1172
1173 setOperationAction(ISD::FADD, MVT::f128, Expand);
1174 setOperationAction(ISD::FSUB, MVT::f128, Expand);
1175 setOperationAction(ISD::FMUL, MVT::f128, Expand);
1176 setOperationAction(ISD::FDIV, MVT::f128, Expand);
1177 setOperationAction(ISD::FNEG, MVT::f128, Expand);
1178 setOperationAction(ISD::FABS, MVT::f128, Expand);
1179 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1180 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1181 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1182 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
1183 setOperationAction(ISD::FREM, MVT::f128, Expand);
1184 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
1185 setOperationAction(ISD::FMA, MVT::f128, Expand);
1186 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1187 }
1188
1189 if (Subtarget.hasP9Altivec()) {
1190 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1191 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1192
1193 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
1194 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
1195 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
1196 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
1197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
1199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
1200 }
1201 }
1202
1203 if (Subtarget.pairedVectorMemops()) {
1204 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
1205 setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
1206 setOperationAction(ISD::STORE, MVT::v256i1, Custom);
1207 }
1208 if (Subtarget.hasMMA()) {
1209 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1210 setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
1211 setOperationAction(ISD::STORE, MVT::v512i1, Custom);
1212 setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom);
1213 }
1214
1215 if (Subtarget.has64BitSupport())
1216 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
1217
1218 if (Subtarget.isISA3_1())
1219 setOperationAction(ISD::SRA, MVT::v1i128, Legal);
1220
1221 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1222
1223 if (!isPPC64) {
1224 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
1225 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
1226 }
1227
1228 setBooleanContents(ZeroOrOneBooleanContent);
1229
1230 if (Subtarget.hasAltivec()) {
1231 // Altivec instructions set fields to all zeros or all ones.
1232 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
1233 }
1234
1235 if (!isPPC64) {
1236 // These libcalls are not available in 32-bit.
1237 setLibcallName(RTLIB::SHL_I128, nullptr);
1238 setLibcallName(RTLIB::SRL_I128, nullptr);
1239 setLibcallName(RTLIB::SRA_I128, nullptr);
1240 }
1241
1242 if (!isPPC64)
1243 setMaxAtomicSizeInBitsSupported(32);
1244
1245 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1246
1247 // We have target-specific dag combine patterns for the following nodes:
1248 setTargetDAGCombine(ISD::ADD);
1249 setTargetDAGCombine(ISD::SHL);
1250 setTargetDAGCombine(ISD::SRA);
1251 setTargetDAGCombine(ISD::SRL);
1252 setTargetDAGCombine(ISD::MUL);
1253 setTargetDAGCombine(ISD::FMA);
1254 setTargetDAGCombine(ISD::SINT_TO_FP);
1255 setTargetDAGCombine(ISD::BUILD_VECTOR);
1256 if (Subtarget.hasFPCVT())
1257 setTargetDAGCombine(ISD::UINT_TO_FP);
1258 setTargetDAGCombine(ISD::LOAD);
1259 setTargetDAGCombine(ISD::STORE);
1260 setTargetDAGCombine(ISD::BR_CC);
1261 if (Subtarget.useCRBits())
1262 setTargetDAGCombine(ISD::BRCOND);
1263 setTargetDAGCombine(ISD::BSWAP);
1264 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1265 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
1266 setTargetDAGCombine(ISD::INTRINSIC_VOID);
1267
1268 setTargetDAGCombine(ISD::SIGN_EXTEND);
1269 setTargetDAGCombine(ISD::ZERO_EXTEND);
1270 setTargetDAGCombine(ISD::ANY_EXTEND);
1271
1272 setTargetDAGCombine(ISD::TRUNCATE);
1273 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1274
1275
1276 if (Subtarget.useCRBits()) {
1277 setTargetDAGCombine(ISD::TRUNCATE);
1278 setTargetDAGCombine(ISD::SETCC);
1279 setTargetDAGCombine(ISD::SELECT_CC);
1280 }
1281
1282 if (Subtarget.hasP9Altivec()) {
1283 setTargetDAGCombine(ISD::ABS);
1284 setTargetDAGCombine(ISD::VSELECT);
1285 }
1286
1287 setLibcallName(RTLIB::LOG_F128, "logf128");
1288 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1289 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1290 setLibcallName(RTLIB::EXP_F128, "expf128");
1291 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1292 setLibcallName(RTLIB::SIN_F128, "sinf128");
1293 setLibcallName(RTLIB::COS_F128, "cosf128");
1294 setLibcallName(RTLIB::POW_F128, "powf128");
1295 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1296 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1297 setLibcallName(RTLIB::POWI_F128, "__powikf2");
1298 setLibcallName(RTLIB::REM_F128, "fmodf128");
1299
1300 // With 32 condition bits, we don't need to sink (and duplicate) compares
1301 // aggressively in CodeGenPrep.
1302 if (Subtarget.useCRBits()) {
1303 setHasMultipleConditionRegisters();
1304 setJumpIsExpensive();
1305 }
1306
1307 setMinFunctionAlignment(Align(4));
1308
1309 switch (Subtarget.getCPUDirective()) {
1310 default: break;
1311 case PPC::DIR_970:
1312 case PPC::DIR_A2:
1313 case PPC::DIR_E500:
1314 case PPC::DIR_E500mc:
1315 case PPC::DIR_E5500:
1316 case PPC::DIR_PWR4:
1317 case PPC::DIR_PWR5:
1318 case PPC::DIR_PWR5X:
1319 case PPC::DIR_PWR6:
1320 case PPC::DIR_PWR6X:
1321 case PPC::DIR_PWR7:
1322 case PPC::DIR_PWR8:
1323 case PPC::DIR_PWR9:
1324 case PPC::DIR_PWR10:
1325 case PPC::DIR_PWR_FUTURE:
1326 setPrefLoopAlignment(Align(16));
1327 setPrefFunctionAlignment(Align(16));
1328 break;
1329 }
1330
1331 if (Subtarget.enableMachineScheduler())
1332 setSchedulingPreference(Sched::Source);
1333 else
1334 setSchedulingPreference(Sched::Hybrid);
1335
1336 computeRegisterProperties(STI.getRegisterInfo());
1337
1338 // The Freescale cores do better with aggressive inlining of memcpy and
1339 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1340 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1341 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1342 MaxStoresPerMemset = 32;
1343 MaxStoresPerMemsetOptSize = 16;
1344 MaxStoresPerMemcpy = 32;
1345 MaxStoresPerMemcpyOptSize = 8;
1346 MaxStoresPerMemmove = 32;
1347 MaxStoresPerMemmoveOptSize = 8;
1348 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1349 // The A2 also benefits from (very) aggressive inlining of memcpy and
1350 // friends. The overhead of a the function call, even when warm, can be
1351 // over one hundred cycles.
1352 MaxStoresPerMemset = 128;
1353 MaxStoresPerMemcpy = 128;
1354 MaxStoresPerMemmove = 128;
1355 MaxLoadsPerMemcmp = 128;
1356 } else {
1357 MaxLoadsPerMemcmp = 8;
1358 MaxLoadsPerMemcmpOptSize = 4;
1359 }
1360
1361 IsStrictFPEnabled = true;
1362
1363 // Let the subtarget (CPU) decide if a predictable select is more expensive
1364 // than the corresponding branch. This information is used in CGP to decide
1365 // when to convert selects into branches.
1366 PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive();
1367}
1368
1369/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1370/// the desired ByVal argument alignment.
1371static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
1372 if (MaxAlign == MaxMaxAlign)
1373 return;
1374 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1375 if (MaxMaxAlign >= 32 &&
1376 VTy->getPrimitiveSizeInBits().getFixedSize() >= 256)
1377 MaxAlign = Align(32);
1378 else if (VTy->getPrimitiveSizeInBits().getFixedSize() >= 128 &&
1379 MaxAlign < 16)
1380 MaxAlign = Align(16);
1381 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1382 Align EltAlign;
1383 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1384 if (EltAlign > MaxAlign)
1385 MaxAlign = EltAlign;
1386 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1387 for (auto *EltTy : STy->elements()) {
1388 Align EltAlign;
1389 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1390 if (EltAlign > MaxAlign)
1391 MaxAlign = EltAlign;
1392 if (MaxAlign == MaxMaxAlign)
1393 break;
1394 }
1395 }
1396}
1397
1398/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1399/// function arguments in the caller parameter area.
1400unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1401 const DataLayout &DL) const {
1402 // 16byte and wider vectors are passed on 16byte boundary.
1403 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1404 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1405 if (Subtarget.hasAltivec())
1406 getMaxByValAlign(Ty, Alignment, Align(16));
1407 return Alignment.value();
1408}
1409
1410bool PPCTargetLowering::useSoftFloat() const {
1411 return Subtarget.useSoftFloat();
1412}
1413
1414bool PPCTargetLowering::hasSPE() const {
1415 return Subtarget.hasSPE();
1416}
1417
1418bool PPCTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
1419 return VT.isScalarInteger();
1420}
1421
1422const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1423 switch ((PPCISD::NodeType)Opcode) {
1424 case PPCISD::FIRST_NUMBER: break;
1425 case PPCISD::FSEL: return "PPCISD::FSEL";
1426 case PPCISD::XSMAXCDP: return "PPCISD::XSMAXCDP";
1427 case PPCISD::XSMINCDP: return "PPCISD::XSMINCDP";
1428 case PPCISD::FCFID: return "PPCISD::FCFID";
1429 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1430 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1431 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1432 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1433 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1434 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1435 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1436 case PPCISD::FP_TO_UINT_IN_VSR:
1437 return "PPCISD::FP_TO_UINT_IN_VSR,";
1438 case PPCISD::FP_TO_SINT_IN_VSR:
1439 return "PPCISD::FP_TO_SINT_IN_VSR";
1440 case PPCISD::FRE: return "PPCISD::FRE";
1441 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1442 case PPCISD::FTSQRT:
1443 return "PPCISD::FTSQRT";
1444 case PPCISD::FSQRT:
1445 return "PPCISD::FSQRT";
1446 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1447 case PPCISD::VPERM: return "PPCISD::VPERM";
1448 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1449 case PPCISD::XXSPLTI_SP_TO_DP:
1450 return "PPCISD::XXSPLTI_SP_TO_DP";
1451 case PPCISD::XXSPLTI32DX:
1452 return "PPCISD::XXSPLTI32DX";
1453 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1454 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1455 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1456 case PPCISD::CMPB: return "PPCISD::CMPB";
1457 case PPCISD::Hi: return "PPCISD::Hi";
1458 case PPCISD::Lo: return "PPCISD::Lo";
1459 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1460 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1461 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1462 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1463 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1464 case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
1465 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1466 case PPCISD::SRL: return "PPCISD::SRL";
1467 case PPCISD::SRA: return "PPCISD::SRA";
1468 case PPCISD::SHL: return "PPCISD::SHL";
1469 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1470 case PPCISD::CALL: return "PPCISD::CALL";
1471 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1472 case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
1473 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1474 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1475 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1476 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1477 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1478 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1479 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1480 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1481 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1482 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1483 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1484 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1485 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1486 case PPCISD::SCALAR_TO_VECTOR_PERMUTED:
1487 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1488 case PPCISD::ANDI_rec_1_EQ_BIT:
1489 return "PPCISD::ANDI_rec_1_EQ_BIT";
1490 case PPCISD::ANDI_rec_1_GT_BIT:
1491 return "PPCISD::ANDI_rec_1_GT_BIT";
1492 case PPCISD::VCMP: return "PPCISD::VCMP";
1493 case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
1494 case PPCISD::LBRX: return "PPCISD::LBRX";
1495 case PPCISD::STBRX: return "PPCISD::STBRX";
1496 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1497 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1498 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1499 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1500 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1501 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1502 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1503 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1504 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1505 case PPCISD::ST_VSR_SCAL_INT:
1506 return "PPCISD::ST_VSR_SCAL_INT";
1507 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1508 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1509 case PPCISD::BDZ: return "PPCISD::BDZ";
1510 case PPCISD::MFFS: return "PPCISD::MFFS";
1511 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1512 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1513 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1514 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1515 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1516 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1517 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1518 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1519 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1520 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1521 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1522 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1523 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1524 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1525 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1526 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1527 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1528 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1529 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1530 case PPCISD::PADDI_DTPREL:
1531 return "PPCISD::PADDI_DTPREL";
1532 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1533 case PPCISD::SC: return "PPCISD::SC";
1534 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1535 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1536 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1537 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1538 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1539 case PPCISD::VABSD: return "PPCISD::VABSD";
1540 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1541 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1542 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1543 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1544 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1545 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1546 case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
1547 case PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR:
1548 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1549 case PPCISD::TLS_LOCAL_EXEC_MAT_ADDR:
1550 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1551 case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
1552 case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
1553 case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
1554 case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
1555 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1556 case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1557 case PPCISD::STRICT_FADDRTZ:
1558 return "PPCISD::STRICT_FADDRTZ";
1559 case PPCISD::STRICT_FCTIDZ:
1560 return "PPCISD::STRICT_FCTIDZ";
1561 case PPCISD::STRICT_FCTIWZ:
1562 return "PPCISD::STRICT_FCTIWZ";
1563 case PPCISD::STRICT_FCTIDUZ:
1564 return "PPCISD::STRICT_FCTIDUZ";
1565 case PPCISD::STRICT_FCTIWUZ:
1566 return "PPCISD::STRICT_FCTIWUZ";
1567 case PPCISD::STRICT_FCFID:
1568 return "PPCISD::STRICT_FCFID";
1569 case PPCISD::STRICT_FCFIDU:
1570 return "PPCISD::STRICT_FCFIDU";
1571 case PPCISD::STRICT_FCFIDS:
1572 return "PPCISD::STRICT_FCFIDS";
1573 case PPCISD::STRICT_FCFIDUS:
1574 return "PPCISD::STRICT_FCFIDUS";
1575 case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
1576 }
1577 return nullptr;
1578}
1579
1580EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1581 EVT VT) const {
1582 if (!VT.isVector())
1583 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1584
1585 return VT.changeVectorElementTypeToInteger();
1586}
1587
1588bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1589 assert(VT.isFloatingPoint() && "Non-floating-point FMA?")((VT.isFloatingPoint() && "Non-floating-point FMA?") ?
static_cast<void> (0) : __assert_fail ("VT.isFloatingPoint() && \"Non-floating-point FMA?\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1589, __PRETTY_FUNCTION__))
;
1590 return true;
1591}
1592
1593//===----------------------------------------------------------------------===//
1594// Node matching predicates, for use by the tblgen matching code.
1595//===----------------------------------------------------------------------===//
1596
1597/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1598static bool isFloatingPointZero(SDValue Op) {
1599 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1600 return CFP->getValueAPF().isZero();
1601 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1602 // Maybe this has already been legalized into the constant pool?
1603 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1604 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1605 return CFP->getValueAPF().isZero();
1606 }
1607 return false;
1608}
1609
1610/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1611/// true if Op is undef or if it matches the specified value.
1612static bool isConstantOrUndef(int Op, int Val) {
1613 return Op < 0 || Op == Val;
1614}
1615
1616/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1617/// VPKUHUM instruction.
1618/// The ShuffleKind distinguishes between big-endian operations with
1619/// two different inputs (0), either-endian operations with two identical
1620/// inputs (1), and little-endian operations with two different inputs (2).
1621/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1622bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1623 SelectionDAG &DAG) {
1624 bool IsLE = DAG.getDataLayout().isLittleEndian();
1625 if (ShuffleKind == 0) {
1626 if (IsLE)
1627 return false;
1628 for (unsigned i = 0; i != 16; ++i)
1629 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1630 return false;
1631 } else if (ShuffleKind == 2) {
1632 if (!IsLE)
1633 return false;
1634 for (unsigned i = 0; i != 16; ++i)
1635 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1636 return false;
1637 } else if (ShuffleKind == 1) {
1638 unsigned j = IsLE ? 0 : 1;
1639 for (unsigned i = 0; i != 8; ++i)
1640 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1641 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1642 return false;
1643 }
1644 return true;
1645}
1646
1647/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1648/// VPKUWUM instruction.
1649/// The ShuffleKind distinguishes between big-endian operations with
1650/// two different inputs (0), either-endian operations with two identical
1651/// inputs (1), and little-endian operations with two different inputs (2).
1652/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1653bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1654 SelectionDAG &DAG) {
1655 bool IsLE = DAG.getDataLayout().isLittleEndian();
1656 if (ShuffleKind == 0) {
1657 if (IsLE)
1658 return false;
1659 for (unsigned i = 0; i != 16; i += 2)
1660 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1661 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1662 return false;
1663 } else if (ShuffleKind == 2) {
1664 if (!IsLE)
1665 return false;
1666 for (unsigned i = 0; i != 16; i += 2)
1667 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1668 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1669 return false;
1670 } else if (ShuffleKind == 1) {
1671 unsigned j = IsLE ? 0 : 2;
1672 for (unsigned i = 0; i != 8; i += 2)
1673 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1674 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1675 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1676 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1677 return false;
1678 }
1679 return true;
1680}
1681
1682/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1683/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1684/// current subtarget.
1685///
1686/// The ShuffleKind distinguishes between big-endian operations with
1687/// two different inputs (0), either-endian operations with two identical
1688/// inputs (1), and little-endian operations with two different inputs (2).
1689/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1690bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1691 SelectionDAG &DAG) {
1692 const PPCSubtarget& Subtarget =
1693 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1694 if (!Subtarget.hasP8Vector())
1695 return false;
1696
1697 bool IsLE = DAG.getDataLayout().isLittleEndian();
1698 if (ShuffleKind == 0) {
1699 if (IsLE)
1700 return false;
1701 for (unsigned i = 0; i != 16; i += 4)
1702 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1703 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1704 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1705 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1706 return false;
1707 } else if (ShuffleKind == 2) {
1708 if (!IsLE)
1709 return false;
1710 for (unsigned i = 0; i != 16; i += 4)
1711 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1712 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1713 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1714 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1715 return false;
1716 } else if (ShuffleKind == 1) {
1717 unsigned j = IsLE ? 0 : 4;
1718 for (unsigned i = 0; i != 8; i += 4)
1719 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1720 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1721 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1722 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1723 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1724 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1725 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1726 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1727 return false;
1728 }
1729 return true;
1730}
1731
1732/// isVMerge - Common function, used to match vmrg* shuffles.
1733///
1734static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1735 unsigned LHSStart, unsigned RHSStart) {
1736 if (N->getValueType(0) != MVT::v16i8)
1737 return false;
1738 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1739, __PRETTY_FUNCTION__))
1739 "Unsupported merge size!")(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1739, __PRETTY_FUNCTION__))
;
1740
1741 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1742 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1743 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1744 LHSStart+j+i*UnitSize) ||
1745 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1746 RHSStart+j+i*UnitSize))
1747 return false;
1748 }
1749 return true;
1750}
1751
1752/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1753/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1754/// The ShuffleKind distinguishes between big-endian merges with two
1755/// different inputs (0), either-endian merges with two identical inputs (1),
1756/// and little-endian merges with two different inputs (2). For the latter,
1757/// the input operands are swapped (see PPCInstrAltivec.td).
1758bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1759 unsigned ShuffleKind, SelectionDAG &DAG) {
1760 if (DAG.getDataLayout().isLittleEndian()) {
1761 if (ShuffleKind == 1) // unary
1762 return isVMerge(N, UnitSize, 0, 0);
1763 else if (ShuffleKind == 2) // swapped
1764 return isVMerge(N, UnitSize, 0, 16);
1765 else
1766 return false;
1767 } else {
1768 if (ShuffleKind == 1) // unary
1769 return isVMerge(N, UnitSize, 8, 8);
1770 else if (ShuffleKind == 0) // normal
1771 return isVMerge(N, UnitSize, 8, 24);
1772 else
1773 return false;
1774 }
1775}
1776
1777/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1778/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1779/// The ShuffleKind distinguishes between big-endian merges with two
1780/// different inputs (0), either-endian merges with two identical inputs (1),
1781/// and little-endian merges with two different inputs (2). For the latter,
1782/// the input operands are swapped (see PPCInstrAltivec.td).
1783bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1784 unsigned ShuffleKind, SelectionDAG &DAG) {
1785 if (DAG.getDataLayout().isLittleEndian()) {
1786 if (ShuffleKind == 1) // unary
1787 return isVMerge(N, UnitSize, 8, 8);
1788 else if (ShuffleKind == 2) // swapped
1789 return isVMerge(N, UnitSize, 8, 24);
1790 else
1791 return false;
1792 } else {
1793 if (ShuffleKind == 1) // unary
1794 return isVMerge(N, UnitSize, 0, 0);
1795 else if (ShuffleKind == 0) // normal
1796 return isVMerge(N, UnitSize, 0, 16);
1797 else
1798 return false;
1799 }
1800}
1801
1802/**
1803 * Common function used to match vmrgew and vmrgow shuffles
1804 *
1805 * The indexOffset determines whether to look for even or odd words in
1806 * the shuffle mask. This is based on the of the endianness of the target
1807 * machine.
1808 * - Little Endian:
1809 * - Use offset of 0 to check for odd elements
1810 * - Use offset of 4 to check for even elements
1811 * - Big Endian:
1812 * - Use offset of 0 to check for even elements
1813 * - Use offset of 4 to check for odd elements
1814 * A detailed description of the vector element ordering for little endian and
1815 * big endian can be found at
1816 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1817 * Targeting your applications - what little endian and big endian IBM XL C/C++
1818 * compiler differences mean to you
1819 *
1820 * The mask to the shuffle vector instruction specifies the indices of the
1821 * elements from the two input vectors to place in the result. The elements are
1822 * numbered in array-access order, starting with the first vector. These vectors
1823 * are always of type v16i8, thus each vector will contain 16 elements of size
1824 * 8. More info on the shuffle vector can be found in the
1825 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1826 * Language Reference.
1827 *
1828 * The RHSStartValue indicates whether the same input vectors are used (unary)
1829 * or two different input vectors are used, based on the following:
1830 * - If the instruction uses the same vector for both inputs, the range of the
1831 * indices will be 0 to 15. In this case, the RHSStart value passed should
1832 * be 0.
1833 * - If the instruction has two different vectors then the range of the
1834 * indices will be 0 to 31. In this case, the RHSStart value passed should
1835 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1836 * to 31 specify elements in the second vector).
1837 *
1838 * \param[in] N The shuffle vector SD Node to analyze
1839 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1840 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1841 * vector to the shuffle_vector instruction
1842 * \return true iff this shuffle vector represents an even or odd word merge
1843 */
1844static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1845 unsigned RHSStartValue) {
1846 if (N->getValueType(0) != MVT::v16i8)
1847 return false;
1848
1849 for (unsigned i = 0; i < 2; ++i)
1850 for (unsigned j = 0; j < 4; ++j)
1851 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1852 i*RHSStartValue+j+IndexOffset) ||
1853 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1854 i*RHSStartValue+j+IndexOffset+8))
1855 return false;
1856 return true;
1857}
1858
1859/**
1860 * Determine if the specified shuffle mask is suitable for the vmrgew or
1861 * vmrgow instructions.
1862 *
1863 * \param[in] N The shuffle vector SD Node to analyze
1864 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1865 * \param[in] ShuffleKind Identify the type of merge:
1866 * - 0 = big-endian merge with two different inputs;
1867 * - 1 = either-endian merge with two identical inputs;
1868 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1869 * little-endian merges).
1870 * \param[in] DAG The current SelectionDAG
1871 * \return true iff this shuffle mask
1872 */
1873bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1874 unsigned ShuffleKind, SelectionDAG &DAG) {
1875 if (DAG.getDataLayout().isLittleEndian()) {
1876 unsigned indexOffset = CheckEven ? 4 : 0;
1877 if (ShuffleKind == 1) // Unary
1878 return isVMerge(N, indexOffset, 0);
1879 else if (ShuffleKind == 2) // swapped
1880 return isVMerge(N, indexOffset, 16);
1881 else
1882 return false;
1883 }
1884 else {
1885 unsigned indexOffset = CheckEven ? 0 : 4;
1886 if (ShuffleKind == 1) // Unary
1887 return isVMerge(N, indexOffset, 0);
1888 else if (ShuffleKind == 0) // Normal
1889 return isVMerge(N, indexOffset, 16);
1890 else
1891 return false;
1892 }
1893 return false;
1894}
1895
1896/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1897/// amount, otherwise return -1.
1898/// The ShuffleKind distinguishes between big-endian operations with two
1899/// different inputs (0), either-endian operations with two identical inputs
1900/// (1), and little-endian operations with two different inputs (2). For the
1901/// latter, the input operands are swapped (see PPCInstrAltivec.td).
1902int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1903 SelectionDAG &DAG) {
1904 if (N->getValueType(0) != MVT::v16i8)
1905 return -1;
1906
1907 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1908
1909 // Find the first non-undef value in the shuffle mask.
1910 unsigned i;
1911 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1912 /*search*/;
1913
1914 if (i == 16) return -1; // all undef.
1915
1916 // Otherwise, check to see if the rest of the elements are consecutively
1917 // numbered from this value.
1918 unsigned ShiftAmt = SVOp->getMaskElt(i);
1919 if (ShiftAmt < i) return -1;
1920
1921 ShiftAmt -= i;
1922 bool isLE = DAG.getDataLayout().isLittleEndian();
1923
1924 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1925 // Check the rest of the elements to see if they are consecutive.
1926 for (++i; i != 16; ++i)
1927 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1928 return -1;
1929 } else if (ShuffleKind == 1) {
1930 // Check the rest of the elements to see if they are consecutive.
1931 for (++i; i != 16; ++i)
1932 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1933 return -1;
1934 } else
1935 return -1;
1936
1937 if (isLE)
1938 ShiftAmt = 16 - ShiftAmt;
1939
1940 return ShiftAmt;
1941}
1942
1943/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1944/// specifies a splat of a single element that is suitable for input to
1945/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
1946bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1947 assert(N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) &&((N->getValueType(0) == MVT::v16i8 && isPowerOf2_32
(EltSize) && EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1948, __PRETTY_FUNCTION__))
1948 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes")((N->getValueType(0) == MVT::v16i8 && isPowerOf2_32
(EltSize) && EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1948, __PRETTY_FUNCTION__))
;
1949
1950 // The consecutive indices need to specify an element, not part of two
1951 // different elements. So abandon ship early if this isn't the case.
1952 if (N->getMaskElt(0) % EltSize != 0)
1953 return false;
1954
1955 // This is a splat operation if each element of the permute is the same, and
1956 // if the value doesn't reference the second vector.
1957 unsigned ElementBase = N->getMaskElt(0);
1958
1959 // FIXME: Handle UNDEF elements too!
1960 if (ElementBase >= 16)
1961 return false;
1962
1963 // Check that the indices are consecutive, in the case of a multi-byte element
1964 // splatted with a v16i8 mask.
1965 for (unsigned i = 1; i != EltSize; ++i)
1966 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1967 return false;
1968
1969 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1970 if (N->getMaskElt(i) < 0) continue;
1971 for (unsigned j = 0; j != EltSize; ++j)
1972 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1973 return false;
1974 }
1975 return true;
1976}
1977
1978/// Check that the mask is shuffling N byte elements. Within each N byte
1979/// element of the mask, the indices could be either in increasing or
1980/// decreasing order as long as they are consecutive.
1981/// \param[in] N the shuffle vector SD Node to analyze
1982/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
1983/// Word/DoubleWord/QuadWord).
1984/// \param[in] StepLen the delta indices number among the N byte element, if
1985/// the mask is in increasing/decreasing order then it is 1/-1.
1986/// \return true iff the mask is shuffling N byte elements.
1987static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
1988 int StepLen) {
1989 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1990, __PRETTY_FUNCTION__))
1990 "Unexpected element width.")(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1990, __PRETTY_FUNCTION__))
;
1991 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.")(((StepLen == 1 || StepLen == -1) && "Unexpected element width."
) ? static_cast<void> (0) : __assert_fail ("(StepLen == 1 || StepLen == -1) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1991, __PRETTY_FUNCTION__))
;
1992
1993 unsigned NumOfElem = 16 / Width;
1994 unsigned MaskVal[16]; // Width is never greater than 16
1995 for (unsigned i = 0; i < NumOfElem; ++i) {
1996 MaskVal[0] = N->getMaskElt(i * Width);
1997 if ((StepLen == 1) && (MaskVal[0] % Width)) {
1998 return false;
1999 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
2000 return false;
2001 }
2002
2003 for (unsigned int j = 1; j < Width; ++j) {
2004 MaskVal[j] = N->getMaskElt(i * Width + j);
2005 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
2006 return false;
2007 }
2008 }
2009 }
2010
2011 return true;
2012}
2013
2014bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2015 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
2016 if (!isNByteElemShuffleMask(N, 4, 1))
2017 return false;
2018
2019 // Now we look at mask elements 0,4,8,12
2020 unsigned M0 = N->getMaskElt(0) / 4;
2021 unsigned M1 = N->getMaskElt(4) / 4;
2022 unsigned M2 = N->getMaskElt(8) / 4;
2023 unsigned M3 = N->getMaskElt(12) / 4;
2024 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
2025 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
2026
2027 // Below, let H and L be arbitrary elements of the shuffle mask
2028 // where H is in the range [4,7] and L is in the range [0,3].
2029 // H, 1, 2, 3 or L, 5, 6, 7
2030 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
2031 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
2032 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2033 InsertAtByte = IsLE ? 12 : 0;
2034 Swap = M0 < 4;
2035 return true;
2036 }
2037 // 0, H, 2, 3 or 4, L, 6, 7
2038 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
2039 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
2040 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2041 InsertAtByte = IsLE ? 8 : 4;
2042 Swap = M1 < 4;
2043 return true;
2044 }
2045 // 0, 1, H, 3 or 4, 5, L, 7
2046 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
2047 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
2048 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2049 InsertAtByte = IsLE ? 4 : 8;
2050 Swap = M2 < 4;
2051 return true;
2052 }
2053 // 0, 1, 2, H or 4, 5, 6, L
2054 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
2055 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
2056 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2057 InsertAtByte = IsLE ? 0 : 12;
2058 Swap = M3 < 4;
2059 return true;
2060 }
2061
2062 // If both vector operands for the shuffle are the same vector, the mask will
2063 // contain only elements from the first one and the second one will be undef.
2064 if (N->getOperand(1).isUndef()) {
2065 ShiftElts = 0;
2066 Swap = true;
2067 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2068 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
2069 InsertAtByte = IsLE ? 12 : 0;
2070 return true;
2071 }
2072 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2073 InsertAtByte = IsLE ? 8 : 4;
2074 return true;
2075 }
2076 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2077 InsertAtByte = IsLE ? 4 : 8;
2078 return true;
2079 }
2080 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2081 InsertAtByte = IsLE ? 0 : 12;
2082 return true;
2083 }
2084 }
2085
2086 return false;
2087}
2088
2089bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2090 bool &Swap, bool IsLE) {
2091 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2091, __PRETTY_FUNCTION__))
;
25
'?' condition is true
2092 // Ensure each byte index of the word is consecutive.
2093 if (!isNByteElemShuffleMask(N, 4, 1))
26
Assuming the condition is false
27
Taking false branch
2094 return false;
2095
2096 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
2097 unsigned M0 = N->getMaskElt(0) / 4;
2098 unsigned M1 = N->getMaskElt(4) / 4;
2099 unsigned M2 = N->getMaskElt(8) / 4;
2100 unsigned M3 = N->getMaskElt(12) / 4;
2101
2102 // If both vector operands for the shuffle are the same vector, the mask will
2103 // contain only elements from the first one and the second one will be undef.
2104 if (N->getOperand(1).isUndef()) {
28
Calling 'SDValue::isUndef'
34
Returning from 'SDValue::isUndef'
35
Taking false branch
2105 assert(M0 < 4 && "Indexing into an undef vector?")((M0 < 4 && "Indexing into an undef vector?") ? static_cast
<void> (0) : __assert_fail ("M0 < 4 && \"Indexing into an undef vector?\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2105, __PRETTY_FUNCTION__))
;
2106 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2107 return false;
2108
2109 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2110 Swap = false;
2111 return true;
2112 }
2113
2114 // Ensure each word index of the ShuffleVector Mask is consecutive.
2115 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
36
Assuming the condition is false
37
Assuming the condition is false
38
Assuming the condition is false
39
Taking false branch
2116 return false;
2117
2118 if (IsLE) {
40
Assuming 'IsLE' is false
41
Taking false branch
2119 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2120 // Input vectors don't need to be swapped if the leading element
2121 // of the result is one of the 3 left elements of the second vector
2122 // (or if there is no shift to be done at all).
2123 Swap = false;
2124 ShiftElts = (8 - M0) % 8;
2125 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2126 // Input vectors need to be swapped if the leading element
2127 // of the result is one of the 3 left elements of the first vector
2128 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2129 Swap = true;
2130 ShiftElts = (4 - M0) % 4;
2131 }
2132
2133 return true;
2134 } else { // BE
2135 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
42
Assuming 'M0' is not equal to 0
43
Assuming 'M0' is not equal to 1
44
Assuming 'M0' is not equal to 2
45
Assuming 'M0' is not equal to 3
46
Taking false branch
2136 // Input vectors don't need to be swapped if the leading element
2137 // of the result is one of the 4 elements of the first vector.
2138 Swap = false;
2139 ShiftElts = M0;
2140 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
47
Assuming 'M0' is not equal to 4
48
Assuming 'M0' is not equal to 5
49
Assuming 'M0' is not equal to 6
50
Assuming 'M0' is not equal to 7
51
Taking false branch
2141 // Input vectors need to be swapped if the leading element
2142 // of the result is one of the 4 elements of the right vector.
2143 Swap = true;
2144 ShiftElts = M0 - 4;
2145 }
2146
2147 return true;
52
Returning without writing to 'ShiftElts'
53
Returning the value 1, which participates in a condition later
2148 }
2149}
2150
2151bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
2152 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2152, __PRETTY_FUNCTION__))
;
2153
2154 if (!isNByteElemShuffleMask(N, Width, -1))
2155 return false;
2156
2157 for (int i = 0; i < 16; i += Width)
2158 if (N->getMaskElt(i) != i + Width - 1)
2159 return false;
2160
2161 return true;
2162}
2163
2164bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
2165 return isXXBRShuffleMaskHelper(N, 2);
2166}
2167
2168bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
2169 return isXXBRShuffleMaskHelper(N, 4);
2170}
2171
2172bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
2173 return isXXBRShuffleMaskHelper(N, 8);
2174}
2175
2176bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
2177 return isXXBRShuffleMaskHelper(N, 16);
2178}
2179
2180/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2181/// if the inputs to the instruction should be swapped and set \p DM to the
2182/// value for the immediate.
2183/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2184/// AND element 0 of the result comes from the first input (LE) or second input
2185/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2186/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2187/// mask.
2188bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
2189 bool &Swap, bool IsLE) {
2190 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2190, __PRETTY_FUNCTION__))
;
2191
2192 // Ensure each byte index of the double word is consecutive.
2193 if (!isNByteElemShuffleMask(N, 8, 1))
2194 return false;
2195
2196 unsigned M0 = N->getMaskElt(0) / 8;
2197 unsigned M1 = N->getMaskElt(8) / 8;
2198 assert(((M0 | M1) < 4) && "A mask element out of bounds?")((((M0 | M1) < 4) && "A mask element out of bounds?"
) ? static_cast<void> (0) : __assert_fail ("((M0 | M1) < 4) && \"A mask element out of bounds?\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2198, __PRETTY_FUNCTION__))
;
2199
2200 // If both vector operands for the shuffle are the same vector, the mask will
2201 // contain only elements from the first one and the second one will be undef.
2202 if (N->getOperand(1).isUndef()) {
2203 if ((M0 | M1) < 2) {
2204 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2205 Swap = false;
2206 return true;
2207 } else
2208 return false;
2209 }
2210
2211 if (IsLE) {
2212 if (M0 > 1 && M1 < 2) {
2213 Swap = false;
2214 } else if (M0 < 2 && M1 > 1) {
2215 M0 = (M0 + 2) % 4;
2216 M1 = (M1 + 2) % 4;
2217 Swap = true;
2218 } else
2219 return false;
2220
2221 // Note: if control flow comes here that means Swap is already set above
2222 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2223 return true;
2224 } else { // BE
2225 if (M0 < 2 && M1 > 1) {
2226 Swap = false;
2227 } else if (M0 > 1 && M1 < 2) {
2228 M0 = (M0 + 2) % 4;
2229 M1 = (M1 + 2) % 4;
2230 Swap = true;
2231 } else
2232 return false;
2233
2234 // Note: if control flow comes here that means Swap is already set above
2235 DM = (M0 << 1) + (M1 & 1);
2236 return true;
2237 }
2238}
2239
2240
2241/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2242/// appropriate for PPC mnemonics (which have a big endian bias - namely
2243/// elements are counted from the left of the vector register).
2244unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2245 SelectionDAG &DAG) {
2246 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2247 assert(isSplatShuffleMask(SVOp, EltSize))((isSplatShuffleMask(SVOp, EltSize)) ? static_cast<void>
(0) : __assert_fail ("isSplatShuffleMask(SVOp, EltSize)", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2247, __PRETTY_FUNCTION__))
;
2248 if (DAG.getDataLayout().isLittleEndian())
2249 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2250 else
2251 return SVOp->getMaskElt(0) / EltSize;
2252}
2253
2254/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2255/// by using a vspltis[bhw] instruction of the specified element size, return
2256/// the constant being splatted. The ByteSize field indicates the number of
2257/// bytes of each element [124] -> [bhw].
2258SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2259 SDValue OpVal(nullptr, 0);
2260
2261 // If ByteSize of the splat is bigger than the element size of the
2262 // build_vector, then we have a case where we are checking for a splat where
2263 // multiple elements of the buildvector are folded together into a single
2264 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2265 unsigned EltSize = 16/N->getNumOperands();
2266 if (EltSize < ByteSize) {
2267 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2268 SDValue UniquedVals[4];
2269 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?")((Multiple > 1 && Multiple <= 4 && "How can this happen?"
) ? static_cast<void> (0) : __assert_fail ("Multiple > 1 && Multiple <= 4 && \"How can this happen?\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2269, __PRETTY_FUNCTION__))
;
2270
2271 // See if all of the elements in the buildvector agree across.
2272 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2273 if (N->getOperand(i).isUndef()) continue;
2274 // If the element isn't a constant, bail fully out.
2275 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2276
2277 if (!UniquedVals[i&(Multiple-1)].getNode())
2278 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2279 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2280 return SDValue(); // no match.
2281 }
2282
2283 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2284 // either constant or undef values that are identical for each chunk. See
2285 // if these chunks can form into a larger vspltis*.
2286
2287 // Check to see if all of the leading entries are either 0 or -1. If
2288 // neither, then this won't fit into the immediate field.
2289 bool LeadingZero = true;
2290 bool LeadingOnes = true;
2291 for (unsigned i = 0; i != Multiple-1; ++i) {
2292 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2293
2294 LeadingZero &= isNullConstant(UniquedVals[i]);
2295 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2296 }
2297 // Finally, check the least significant entry.
2298 if (LeadingZero) {
2299 if (!UniquedVals[Multiple-1].getNode())
2300 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2301 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2302 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2303 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2304 }
2305 if (LeadingOnes) {
2306 if (!UniquedVals[Multiple-1].getNode())
2307 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2308 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2309 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2310 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2311 }
2312
2313 return SDValue();
2314 }
2315
2316 // Check to see if this buildvec has a single non-undef value in its elements.
2317 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2318 if (N->getOperand(i).isUndef()) continue;
2319 if (!OpVal.getNode())
2320 OpVal = N->getOperand(i);
2321 else if (OpVal != N->getOperand(i))
2322 return SDValue();
2323 }
2324
2325 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2326
2327 unsigned ValSizeInBytes = EltSize;
2328 uint64_t Value = 0;
2329 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2330 Value = CN->getZExtValue();
2331 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2332 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!")((CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"
) ? static_cast<void> (0) : __assert_fail ("CN->getValueType(0) == MVT::f32 && \"Only one legal FP vector type!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2332, __PRETTY_FUNCTION__))
;
2333 Value = FloatToBits(CN->getValueAPF().convertToFloat());
2334 }
2335
2336 // If the splat value is larger than the element value, then we can never do
2337 // this splat. The only case that we could fit the replicated bits into our
2338 // immediate field for would be zero, and we prefer to use vxor for it.
2339 if (ValSizeInBytes < ByteSize) return SDValue();
2340
2341 // If the element value is larger than the splat value, check if it consists
2342 // of a repeated bit pattern of size ByteSize.
2343 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2344 return SDValue();
2345
2346 // Properly sign extend the value.
2347 int MaskVal = SignExtend32(Value, ByteSize * 8);
2348
2349 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2350 if (MaskVal == 0) return SDValue();
2351
2352 // Finally, if this value fits in a 5 bit sext field, return it
2353 if (SignExtend32<5>(MaskVal) == MaskVal)
2354 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2355 return SDValue();
2356}
2357
2358/// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
2359/// amount, otherwise return -1.
2360int PPC::isQVALIGNIShuffleMask(SDNode *N) {
2361 EVT VT = N->getValueType(0);
2362 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
2363 return -1;
2364
2365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2366
2367 // Find the first non-undef value in the shuffle mask.
2368 unsigned i;
2369 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
2370 /*search*/;
2371
2372 if (i == 4) return -1; // all undef.
2373
2374 // Otherwise, check to see if the rest of the elements are consecutively
2375 // numbered from this value.
2376 unsigned ShiftAmt = SVOp->getMaskElt(i);
2377 if (ShiftAmt < i) return -1;
2378 ShiftAmt -= i;
2379
2380 // Check the rest of the elements to see if they are consecutive.
2381 for (++i; i != 4; ++i)
2382 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2383 return -1;
2384
2385 return ShiftAmt;
2386}
2387
2388//===----------------------------------------------------------------------===//
2389// Addressing Mode Selection
2390//===----------------------------------------------------------------------===//
2391
2392/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2393/// or 64-bit immediate, and if the value can be accurately represented as a
2394/// sign extension from a 16-bit value. If so, this returns true and the
2395/// immediate.
2396bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2397 if (!isa<ConstantSDNode>(N))
2398 return false;
2399
2400 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2401 if (N->getValueType(0) == MVT::i32)
2402 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2403 else
2404 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2405}
2406bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2407 return isIntS16Immediate(Op.getNode(), Imm);
2408}
2409
2410
2411/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2412/// be represented as an indexed [r+r] operation.
2413bool PPCTargetLowering::SelectAddressEVXRegReg(SDValue N, SDValue &Base,
2414 SDValue &Index,
2415 SelectionDAG &DAG) const {
2416 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
2417 UI != E; ++UI) {
2418 if (MemSDNode *Memop = dyn_cast<MemSDNode>(*UI)) {
2419 if (Memop->getMemoryVT() == MVT::f64) {
2420 Base = N.getOperand(0);
2421 Index = N.getOperand(1);
2422 return true;
2423 }
2424 }
2425 }
2426 return false;
2427}
2428
2429/// isIntS34Immediate - This method tests if value of node given can be
2430/// accurately represented as a sign extension from a 34-bit value. If so,
2431/// this returns true and the immediate.
2432bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2433 if (!isa<ConstantSDNode>(N))
2434 return false;
2435
2436 Imm = (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2437 return isInt<34>(Imm);
2438}
2439bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) {
2440 return isIntS34Immediate(Op.getNode(), Imm);
2441}
2442
2443/// SelectAddressRegReg - Given the specified addressed, check to see if it
2444/// can be represented as an indexed [r+r] operation. Returns false if it
2445/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2446/// non-zero and N can be represented by a base register plus a signed 16-bit
2447/// displacement, make a more precise judgement by checking (displacement % \p
2448/// EncodingAlignment).
2449bool PPCTargetLowering::SelectAddressRegReg(
2450 SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG,
2451 MaybeAlign EncodingAlignment) const {
2452 // If we have a PC Relative target flag don't select as [reg+reg]. It will be
2453 // a [pc+imm].
2454 if (SelectAddressPCRel(N, Base))
2455 return false;
2456
2457 int16_t Imm = 0;
2458 if (N.getOpcode() == ISD::ADD) {
2459 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2460 // SPE load/store can only handle 8-bit offsets.
2461 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2462 return true;
2463 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2464 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2465 return false; // r+i
2466 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2467 return false; // r+i
2468
2469 Base = N.getOperand(0);
2470 Index = N.getOperand(1);
2471 return true;
2472 } else if (N.getOpcode() == ISD::OR) {
2473 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2474 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2475 return false; // r+i can fold it if we can.
2476
2477 // If this is an or of disjoint bitfields, we can codegen this as an add
2478 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2479 // disjoint.
2480 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2481
2482 if (LHSKnown.Zero.getBoolValue()) {
2483 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2484 // If all of the bits are known zero on the LHS or RHS, the add won't
2485 // carry.
2486 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2487 Base = N.getOperand(0);
2488 Index = N.getOperand(1);
2489 return true;
2490 }
2491 }
2492 }
2493
2494 return false;
2495}
2496
2497// If we happen to be doing an i64 load or store into a stack slot that has
2498// less than a 4-byte alignment, then the frame-index elimination may need to
2499// use an indexed load or store instruction (because the offset may not be a
2500// multiple of 4). The extra register needed to hold the offset comes from the
2501// register scavenger, and it is possible that the scavenger will need to use
2502// an emergency spill slot. As a result, we need to make sure that a spill slot
2503// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2504// stack slot.
2505static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2506 // FIXME: This does not handle the LWA case.
2507 if (VT != MVT::i64)
2508 return;
2509
2510 // NOTE: We'll exclude negative FIs here, which come from argument
2511 // lowering, because there are no known test cases triggering this problem
2512 // using packed structures (or similar). We can remove this exclusion if
2513 // we find such a test case. The reason why this is so test-case driven is
2514 // because this entire 'fixup' is only to prevent crashes (from the
2515 // register scavenger) on not-really-valid inputs. For example, if we have:
2516 // %a = alloca i1
2517 // %b = bitcast i1* %a to i64*
2518 // store i64* a, i64 b
2519 // then the store should really be marked as 'align 1', but is not. If it
2520 // were marked as 'align 1' then the indexed form would have been
2521 // instruction-selected initially, and the problem this 'fixup' is preventing
2522 // won't happen regardless.
2523 if (FrameIdx < 0)
2524 return;
2525
2526 MachineFunction &MF = DAG.getMachineFunction();
2527 MachineFrameInfo &MFI = MF.getFrameInfo();
2528
2529 if (MFI.getObjectAlign(FrameIdx) >= Align(4))
2530 return;
2531
2532 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2533 FuncInfo->setHasNonRISpills();
2534}
2535
2536/// Returns true if the address N can be represented by a base register plus
2537/// a signed 16-bit displacement [r+imm], and if it is not better
2538/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2539/// displacements that are multiples of that value.
2540bool PPCTargetLowering::SelectAddressRegImm(
2541 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2542 MaybeAlign EncodingAlignment) const {
2543 // FIXME dl should come from parent load or store, not from address
2544 SDLoc dl(N);
2545
2546 // If we have a PC Relative target flag don't select as [reg+imm]. It will be
2547 // a [pc+imm].
2548 if (SelectAddressPCRel(N, Base))
2549 return false;
2550
2551 // If this can be more profitably realized as r+r, fail.
2552 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2553 return false;
2554
2555 if (N.getOpcode() == ISD::ADD) {
2556 int16_t imm = 0;
2557 if (isIntS16Immediate(N.getOperand(1), imm) &&
2558 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2559 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2560 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2561 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2562 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2563 } else {
2564 Base = N.getOperand(0);
2565 }
2566 return true; // [r+i]
2567 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2568 // Match LOAD (ADD (X, Lo(G))).
2569 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2570, __PRETTY_FUNCTION__))
2570 && "Cannot handle constant offsets yet!")((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2570, __PRETTY_FUNCTION__))
;
2571 Disp = N.getOperand(1).getOperand(0); // The global address.
2572 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2575, __PRETTY_FUNCTION__))
2573 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2575, __PRETTY_FUNCTION__))
2574 Disp.getOpcode() == ISD::TargetConstantPool ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2575, __PRETTY_FUNCTION__))
2575 Disp.getOpcode() == ISD::TargetJumpTable)((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2575, __PRETTY_FUNCTION__))
;
2576 Base = N.getOperand(0);
2577 return true; // [&g+r]
2578 }
2579 } else if (N.getOpcode() == ISD::OR) {
2580 int16_t imm = 0;
2581 if (isIntS16Immediate(N.getOperand(1), imm) &&
2582 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2583 // If this is an or of disjoint bitfields, we can codegen this as an add
2584 // (for better address arithmetic) if the LHS and RHS of the OR are
2585 // provably disjoint.
2586 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2587
2588 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2589 // If all of the bits are known zero on the LHS or RHS, the add won't
2590 // carry.
2591 if (FrameIndexSDNode *FI =
2592 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2593 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2594 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2595 } else {
2596 Base = N.getOperand(0);
2597 }
2598 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2599 return true;
2600 }
2601 }
2602 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2603 // Loading from a constant address.
2604
2605 // If this address fits entirely in a 16-bit sext immediate field, codegen
2606 // this as "d, 0"
2607 int16_t Imm;
2608 if (isIntS16Immediate(CN, Imm) &&
2609 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2610 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2611 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2612 CN->getValueType(0));
2613 return true;
2614 }
2615
2616 // Handle 32-bit sext immediates with LIS + addr mode.
2617 if ((CN->getValueType(0) == MVT::i32 ||
2618 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2619 (!EncodingAlignment ||
2620 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2621 int Addr = (int)CN->getZExtValue();
2622
2623 // Otherwise, break this down into an LIS + disp.
2624 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2625
2626 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2627 MVT::i32);
2628 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2629 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2630 return true;
2631 }
2632 }
2633
2634 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2635 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2636 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2637 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2638 } else
2639 Base = N;
2640 return true; // [r+0]
2641}
2642
2643/// Similar to the 16-bit case but for instructions that take a 34-bit
2644/// displacement field (prefixed loads/stores).
2645bool PPCTargetLowering::SelectAddressRegImm34(SDValue N, SDValue &Disp,
2646 SDValue &Base,
2647 SelectionDAG &DAG) const {
2648 // Only on 64-bit targets.
2649 if (N.getValueType() != MVT::i64)
2650 return false;
2651
2652 SDLoc dl(N);
2653 int64_t Imm = 0;
2654
2655 if (N.getOpcode() == ISD::ADD) {
2656 if (!isIntS34Immediate(N.getOperand(1), Imm))
2657 return false;
2658 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2659 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2660 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2661 else
2662 Base = N.getOperand(0);
2663 return true;
2664 }
2665
2666 if (N.getOpcode() == ISD::OR) {
2667 if (!isIntS34Immediate(N.getOperand(1), Imm))
2668 return false;
2669 // If this is an or of disjoint bitfields, we can codegen this as an add
2670 // (for better address arithmetic) if the LHS and RHS of the OR are
2671 // provably disjoint.
2672 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2673 if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)Imm) != ~0ULL)
2674 return false;
2675 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2676 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2677 else
2678 Base = N.getOperand(0);
2679 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2680 return true;
2681 }
2682
2683 if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2684 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2685 Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2686 return true;
2687 }
2688
2689 return false;
2690}
2691
2692/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2693/// represented as an indexed [r+r] operation.
2694bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2695 SDValue &Index,
2696 SelectionDAG &DAG) const {
2697 // Check to see if we can easily represent this as an [r+r] address. This
2698 // will fail if it thinks that the address is more profitably represented as
2699 // reg+imm, e.g. where imm = 0.
2700 if (SelectAddressRegReg(N, Base, Index, DAG))
2701 return true;
2702
2703 // If the address is the result of an add, we will utilize the fact that the
2704 // address calculation includes an implicit add. However, we can reduce
2705 // register pressure if we do not materialize a constant just for use as the
2706 // index register. We only get rid of the add if it is not an add of a
2707 // value and a 16-bit signed constant and both have a single use.
2708 int16_t imm = 0;
2709 if (N.getOpcode() == ISD::ADD &&
2710 (!isIntS16Immediate(N.getOperand(1), imm) ||
2711 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2712 Base = N.getOperand(0);
2713 Index = N.getOperand(1);
2714 return true;
2715 }
2716
2717 // Otherwise, do it the hard way, using R0 as the base register.
2718 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2719 N.getValueType());
2720 Index = N;
2721 return true;
2722}
2723
2724template <typename Ty> static bool isValidPCRelNode(SDValue N) {
2725 Ty *PCRelCand = dyn_cast<Ty>(N);
2726 return PCRelCand && (PCRelCand->getTargetFlags() & PPCII::MO_PCREL_FLAG);
2727}
2728
2729/// Returns true if this address is a PC Relative address.
2730/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
2731/// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
2732bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
2733 // This is a materialize PC Relative node. Always select this as PC Relative.
2734 Base = N;
2735 if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
2736 return true;
2737 if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
2738 isValidPCRelNode<GlobalAddressSDNode>(N) ||
2739 isValidPCRelNode<JumpTableSDNode>(N) ||
2740 isValidPCRelNode<BlockAddressSDNode>(N))
2741 return true;
2742 return false;
2743}
2744
2745/// Returns true if we should use a direct load into vector instruction
2746/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2747static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
2748
2749 // If there are any other uses other than scalar to vector, then we should
2750 // keep it as a scalar load -> direct move pattern to prevent multiple
2751 // loads.
2752 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
2753 if (!LD)
2754 return false;
2755
2756 EVT MemVT = LD->getMemoryVT();
2757 if (!MemVT.isSimple())
2758 return false;
2759 switch(MemVT.getSimpleVT().SimpleTy) {
2760 case MVT::i64:
2761 break;
2762 case MVT::i32:
2763 if (!ST.hasP8Vector())
2764 return false;
2765 break;
2766 case MVT::i16:
2767 case MVT::i8:
2768 if (!ST.hasP9Vector())
2769 return false;
2770 break;
2771 default:
2772 return false;
2773 }
2774
2775 SDValue LoadedVal(N, 0);
2776 if (!LoadedVal.hasOneUse())
2777 return false;
2778
2779 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
2780 UI != UE; ++UI)
2781 if (UI.getUse().get().getResNo() == 0 &&
2782 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &&
2783 UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED)
2784 return false;
2785
2786 return true;
2787}
2788
2789/// getPreIndexedAddressParts - returns true by value, base pointer and
2790/// offset pointer and addressing mode by reference if the node's address
2791/// can be legally represented as pre-indexed load / store address.
2792bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2793 SDValue &Offset,
2794 ISD::MemIndexedMode &AM,
2795 SelectionDAG &DAG) const {
2796 if (DisablePPCPreinc) return false;
2797
2798 bool isLoad = true;
2799 SDValue Ptr;
2800 EVT VT;
2801 unsigned Alignment;
2802 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2803 Ptr = LD->getBasePtr();
2804 VT = LD->getMemoryVT();
2805 Alignment = LD->getAlignment();
2806 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2807 Ptr = ST->getBasePtr();
2808 VT = ST->getMemoryVT();
2809 Alignment = ST->getAlignment();
2810 isLoad = false;
2811 } else
2812 return false;
2813
2814 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
2815 // instructions because we can fold these into a more efficient instruction
2816 // instead, (such as LXSD).
2817 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
2818 return false;
2819 }
2820
2821 // PowerPC doesn't have preinc load/store instructions for vectors
2822 if (VT.isVector())
2823 return false;
2824
2825 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2826 // Common code will reject creating a pre-inc form if the base pointer
2827 // is a frame index, or if N is a store and the base pointer is either
2828 // the same as or a predecessor of the value being stored. Check for
2829 // those situations here, and try with swapped Base/Offset instead.
2830 bool Swap = false;
2831
2832 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2833 Swap = true;
2834 else if (!isLoad) {
2835 SDValue Val = cast<StoreSDNode>(N)->getValue();
2836 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2837 Swap = true;
2838 }
2839
2840 if (Swap)
2841 std::swap(Base, Offset);
2842
2843 AM = ISD::PRE_INC;
2844 return true;
2845 }
2846
2847 // LDU/STU can only handle immediates that are a multiple of 4.
2848 if (VT != MVT::i64) {
2849 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, None))
2850 return false;
2851 } else {
2852 // LDU/STU need an address with at least 4-byte alignment.
2853 if (Alignment < 4)
2854 return false;
2855
2856 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, Align(4)))
2857 return false;
2858 }
2859
2860 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2861 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2862 // sext i32 to i64 when addr mode is r+i.
2863 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2864 LD->getExtensionType() == ISD::SEXTLOAD &&
2865 isa<ConstantSDNode>(Offset))
2866 return false;
2867 }
2868
2869 AM = ISD::PRE_INC;
2870 return true;
2871}
2872
2873//===----------------------------------------------------------------------===//
2874// LowerOperation implementation
2875//===----------------------------------------------------------------------===//
2876
2877/// Return true if we should reference labels using a PICBase, set the HiOpFlags
2878/// and LoOpFlags to the target MO flags.
2879static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2880 unsigned &HiOpFlags, unsigned &LoOpFlags,
2881 const GlobalValue *GV = nullptr) {
2882 HiOpFlags = PPCII::MO_HA;
2883 LoOpFlags = PPCII::MO_LO;
2884
2885 // Don't use the pic base if not in PIC relocation model.
2886 if (IsPIC) {
2887 HiOpFlags |= PPCII::MO_PIC_FLAG;
2888 LoOpFlags |= PPCII::MO_PIC_FLAG;
2889 }
2890}
2891
2892static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2893 SelectionDAG &DAG) {
2894 SDLoc DL(HiPart);
2895 EVT PtrVT = HiPart.getValueType();
2896 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2897
2898 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2899 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2900
2901 // With PIC, the first instruction is actually "GR+hi(&G)".
2902 if (isPIC)
2903 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2904 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2905
2906 // Generate non-pic code that has direct accesses to the constant pool.
2907 // The address of the global is just (hi(&g)+lo(&g)).
2908 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2909}
2910
2911static void setUsesTOCBasePtr(MachineFunction &MF) {
2912 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2913 FuncInfo->setUsesTOCBasePtr();
2914}
2915
2916static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2917 setUsesTOCBasePtr(DAG.getMachineFunction());
2918}
2919
2920SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
2921 SDValue GA) const {
2922 const bool Is64Bit = Subtarget.isPPC64();
2923 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2924 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
2925 : Subtarget.isAIXABI()
2926 ? DAG.getRegister(PPC::R2, VT)
2927 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2928 SDValue Ops[] = { GA, Reg };
2929 return DAG.getMemIntrinsicNode(
2930 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2931 MachinePointerInfo::getGOT(DAG.getMachineFunction()), None,
2932 MachineMemOperand::MOLoad);
2933}
2934
2935SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2936 SelectionDAG &DAG) const {
2937 EVT PtrVT = Op.getValueType();
2938 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2939 const Constant *C = CP->getConstVal();
2940
2941 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
2942 // The actual address of the GlobalValue is stored in the TOC.
2943 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
2944 if (Subtarget.isUsingPCRelativeCalls()) {
2945 SDLoc DL(CP);
2946 EVT Ty = getPointerTy(DAG.getDataLayout());
2947 SDValue ConstPool = DAG.getTargetConstantPool(
2948 C, Ty, CP->getAlign(), CP->getOffset(), PPCII::MO_PCREL_FLAG);
2949 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
2950 }
2951 setUsesTOCBasePtr(DAG);
2952 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
2953 return getTOCEntry(DAG, SDLoc(CP), GA);
2954 }
2955
2956 unsigned MOHiFlag, MOLoFlag;
2957 bool IsPIC = isPositionIndependent();
2958 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2959
2960 if (IsPIC && Subtarget.isSVR4ABI()) {
2961 SDValue GA =
2962 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), PPCII::MO_PIC_FLAG);
2963 return getTOCEntry(DAG, SDLoc(CP), GA);
2964 }
2965
2966 SDValue CPIHi =
2967 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOHiFlag);
2968 SDValue CPILo =
2969 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOLoFlag);
2970 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
2971}
2972
2973// For 64-bit PowerPC, prefer the more compact relative encodings.
2974// This trades 32 bits per jump table entry for one or two instructions
2975// on the jump site.
2976unsigned PPCTargetLowering::getJumpTableEncoding() const {
2977 if (isJumpTableRelative())
2978 return MachineJumpTableInfo::EK_LabelDifference32;
2979
2980 return TargetLowering::getJumpTableEncoding();
2981}
2982
2983bool PPCTargetLowering::isJumpTableRelative() const {
2984 if (UseAbsoluteJumpTables)
2985 return false;
2986 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
2987 return true;
2988 return TargetLowering::isJumpTableRelative();
2989}
2990
2991SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2992 SelectionDAG &DAG) const {
2993 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
2994 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2995
2996 switch (getTargetMachine().getCodeModel()) {
2997 case CodeModel::Small:
2998 case CodeModel::Medium:
2999 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
3000 default:
3001 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
3002 getPointerTy(DAG.getDataLayout()));
3003 }
3004}
3005
3006const MCExpr *
3007PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
3008 unsigned JTI,
3009 MCContext &Ctx) const {
3010 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3011 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
3012
3013 switch (getTargetMachine().getCodeModel()) {
3014 case CodeModel::Small:
3015 case CodeModel::Medium:
3016 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
3017 default:
3018 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
3019 }
3020}
3021
3022SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
3023 EVT PtrVT = Op.getValueType();
3024 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3025
3026 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3027 if (Subtarget.isUsingPCRelativeCalls()) {
3028 SDLoc DL(JT);
3029 EVT Ty = getPointerTy(DAG.getDataLayout());
3030 SDValue GA =
3031 DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
3032 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3033 return MatAddr;
3034 }
3035
3036 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3037 // The actual address of the GlobalValue is stored in the TOC.
3038 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3039 setUsesTOCBasePtr(DAG);
3040 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3041 return getTOCEntry(DAG, SDLoc(JT), GA);
3042 }
3043
3044 unsigned MOHiFlag, MOLoFlag;
3045 bool IsPIC = isPositionIndependent();
3046 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3047
3048 if (IsPIC && Subtarget.isSVR4ABI()) {
3049 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3050 PPCII::MO_PIC_FLAG);
3051 return getTOCEntry(DAG, SDLoc(GA), GA);
3052 }
3053
3054 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3055 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3056 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
3057}
3058
3059SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3060 SelectionDAG &DAG) const {
3061 EVT PtrVT = Op.getValueType();
3062 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
3063 const BlockAddress *BA = BASDN->getBlockAddress();
3064
3065 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3066 if (Subtarget.isUsingPCRelativeCalls()) {
3067 SDLoc DL(BASDN);
3068 EVT Ty = getPointerTy(DAG.getDataLayout());
3069 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3070 PPCII::MO_PCREL_FLAG);
3071 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3072 return MatAddr;
3073 }
3074
3075 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3076 // The actual BlockAddress is stored in the TOC.
3077 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3078 setUsesTOCBasePtr(DAG);
3079 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3080 return getTOCEntry(DAG, SDLoc(BASDN), GA);
3081 }
3082
3083 // 32-bit position-independent ELF stores the BlockAddress in the .got.
3084 if (Subtarget.is32BitELFABI() && isPositionIndependent())
3085 return getTOCEntry(
3086 DAG, SDLoc(BASDN),
3087 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
3088
3089 unsigned MOHiFlag, MOLoFlag;
3090 bool IsPIC = isPositionIndependent();
3091 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3092 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3093 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3094 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
3095}
3096
3097SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3098 SelectionDAG &DAG) const {
3099 // FIXME: TLS addresses currently use medium model code sequences,
3100 // which is the most useful form. Eventually support for small and
3101 // large models could be added if users need it, at the cost of
3102 // additional complexity.
3103 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3104 if (DAG.getTarget().useEmulatedTLS())
3105 return LowerToTLSEmulatedModel(GA, DAG);
3106
3107 SDLoc dl(GA);
3108 const GlobalValue *GV = GA->getGlobal();
3109 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3110 bool is64bit = Subtarget.isPPC64();
3111 const Module *M = DAG.getMachineFunction().getFunction().getParent();
3112 PICLevel::Level picLevel = M->getPICLevel();
3113
3114 const TargetMachine &TM = getTargetMachine();
3115 TLSModel::Model Model = TM.getTLSModel(GV);
3116
3117 if (Model == TLSModel::LocalExec) {
3118 if (Subtarget.isUsingPCRelativeCalls()) {
3119 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3120 SDValue TGA = DAG.getTargetGlobalAddress(
3121 GV, dl, PtrVT, 0, (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG));
3122 SDValue MatAddr =
3123 DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
3124 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
3125 }
3126
3127 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3128 PPCII::MO_TPREL_HA);
3129 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3130 PPCII::MO_TPREL_LO);
3131 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3132 : DAG.getRegister(PPC::R2, MVT::i32);
3133
3134 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3135 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
3136 }
3137
3138 if (Model == TLSModel::InitialExec) {
3139 bool IsPCRel = Subtarget.isUsingPCRelativeCalls();
3140 SDValue TGA = DAG.getTargetGlobalAddress(
3141 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
3142 SDValue TGATLS = DAG.getTargetGlobalAddress(
3143 GV, dl, PtrVT, 0,
3144 IsPCRel ? (PPCII::MO_TLS | PPCII::MO_PCREL_FLAG) : PPCII::MO_TLS);
3145 SDValue TPOffset;
3146 if (IsPCRel) {
3147 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3148 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
3149 MachinePointerInfo());
3150 } else {
3151 SDValue GOTPtr;
3152 if (is64bit) {
3153 setUsesTOCBasePtr(DAG);
3154 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3155 GOTPtr =
3156 DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
3157 } else {
3158 if (!TM.isPositionIndependent())
3159 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
3160 else if (picLevel == PICLevel::SmallPIC)
3161 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3162 else
3163 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3164 }
3165 TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
3166 }
3167 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
3168 }
3169
3170 if (Model == TLSModel::GeneralDynamic) {
3171 if (Subtarget.isUsingPCRelativeCalls()) {
3172 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3173 PPCII::MO_GOT_TLSGD_PCREL_FLAG);
3174 return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3175 }
3176
3177 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3178 SDValue GOTPtr;
3179 if (is64bit) {
3180 setUsesTOCBasePtr(DAG);
3181 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3182 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
3183 GOTReg, TGA);
3184 } else {
3185 if (picLevel == PICLevel::SmallPIC)
3186 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3187 else
3188 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3189 }
3190 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
3191 GOTPtr, TGA, TGA);
3192 }
3193
3194 if (Model == TLSModel::LocalDynamic) {
3195 if (Subtarget.isUsingPCRelativeCalls()) {
3196 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3197 PPCII::MO_GOT_TLSLD_PCREL_FLAG);
3198 SDValue MatPCRel =
3199 DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3200 return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
3201 }
3202
3203 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3204 SDValue GOTPtr;
3205 if (is64bit) {
3206 setUsesTOCBasePtr(DAG);
3207 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3208 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
3209 GOTReg, TGA);
3210 } else {
3211 if (picLevel == PICLevel::SmallPIC)
3212 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3213 else
3214 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3215 }
3216 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3217 PtrVT, GOTPtr, TGA, TGA);
3218 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3219 PtrVT, TLSAddr, TGA);
3220 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
3221 }
3222
3223 llvm_unreachable("Unknown TLS model!")::llvm::llvm_unreachable_internal("Unknown TLS model!", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3223)
;
3224}
3225
3226SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3227 SelectionDAG &DAG) const {
3228 EVT PtrVT = Op.getValueType();
3229 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
3230 SDLoc DL(GSDN);
3231 const GlobalValue *GV = GSDN->getGlobal();
3232
3233 // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
3234 // The actual address of the GlobalValue is stored in the TOC.
3235 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3236 if (Subtarget.isUsingPCRelativeCalls()) {
3237 EVT Ty = getPointerTy(DAG.getDataLayout());
3238 if (isAccessedAsGotIndirect(Op)) {
3239 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3240 PPCII::MO_PCREL_FLAG |
3241 PPCII::MO_GOT_FLAG);
3242 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3243 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
3244 MachinePointerInfo());
3245 return Load;
3246 } else {
3247 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3248 PPCII::MO_PCREL_FLAG);
3249 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3250 }
3251 }
3252 setUsesTOCBasePtr(DAG);
3253 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
3254 return getTOCEntry(DAG, DL, GA);
3255 }
3256
3257 unsigned MOHiFlag, MOLoFlag;
3258 bool IsPIC = isPositionIndependent();
3259 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
3260
3261 if (IsPIC && Subtarget.isSVR4ABI()) {
3262 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3263 GSDN->getOffset(),
3264 PPCII::MO_PIC_FLAG);
3265 return getTOCEntry(DAG, DL, GA);
3266 }
3267
3268 SDValue GAHi =
3269 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
3270 SDValue GALo =
3271 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
3272
3273 return LowerLabelRef(GAHi, GALo, IsPIC, DAG);
3274}
3275
3276SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3277 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3278 SDLoc dl(Op);
3279
3280 if (Op.getValueType() == MVT::v2i64) {
3281 // When the operands themselves are v2i64 values, we need to do something
3282 // special because VSX has no underlying comparison operations for these.
3283 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
3284 // Equality can be handled by casting to the legal type for Altivec
3285 // comparisons, everything else needs to be expanded.
3286 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3287 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
3288 DAG.getSetCC(dl, MVT::v4i32,
3289 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
3290 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
3291 CC));
3292 }
3293
3294 return SDValue();
3295 }
3296
3297 // We handle most of these in the usual way.
3298 return Op;
3299 }
3300
3301 // If we're comparing for equality to zero, expose the fact that this is
3302 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
3303 // fold the new nodes.
3304 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
3305 return V;
3306
3307 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
3308 // Leave comparisons against 0 and -1 alone for now, since they're usually
3309 // optimized. FIXME: revisit this when we can custom lower all setcc
3310 // optimizations.
3311 if (C->isAllOnesValue() || C->isNullValue())
3312 return SDValue();
3313 }
3314
3315 // If we have an integer seteq/setne, turn it into a compare against zero
3316 // by xor'ing the rhs with the lhs, which is faster than setting a
3317 // condition register, reading it back out, and masking the correct bit. The
3318 // normal approach here uses sub to do this instead of xor. Using xor exposes
3319 // the result to other bit-twiddling opportunities.
3320 EVT LHSVT = Op.getOperand(0).getValueType();
3321 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
3322 EVT VT = Op.getValueType();
3323 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
3324 Op.getOperand(1));
3325 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
3326 }
3327 return SDValue();
3328}
3329
3330SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3331 SDNode *Node = Op.getNode();
3332 EVT VT = Node->getValueType(0);
3333 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3334 SDValue InChain = Node->getOperand(0);
3335 SDValue VAListPtr = Node->getOperand(1);
3336 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3337 SDLoc dl(Node);
3338
3339 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")((!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")
? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVAARG is PPC32 only\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3339, __PRETTY_FUNCTION__))
;
3340
3341 // gpr_index
3342 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3343 VAListPtr, MachinePointerInfo(SV), MVT::i8);
3344 InChain = GprIndex.getValue(1);
3345
3346 if (VT == MVT::i64) {
3347 // Check if GprIndex is even
3348 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
3349 DAG.getConstant(1, dl, MVT::i32));
3350 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
3351 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
3352 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
3353 DAG.getConstant(1, dl, MVT::i32));
3354 // Align GprIndex to be even if it isn't
3355 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
3356 GprIndex);
3357 }
3358
3359 // fpr index is 1 byte after gpr
3360 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3361 DAG.getConstant(1, dl, MVT::i32));
3362
3363 // fpr
3364 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3365 FprPtr, MachinePointerInfo(SV), MVT::i8);
3366 InChain = FprIndex.getValue(1);
3367
3368 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3369 DAG.getConstant(8, dl, MVT::i32));
3370
3371 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3372 DAG.getConstant(4, dl, MVT::i32));
3373
3374 // areas
3375 SDValue OverflowArea =
3376 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
3377 InChain = OverflowArea.getValue(1);
3378
3379 SDValue RegSaveArea =
3380 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
3381 InChain = RegSaveArea.getValue(1);
3382
3383 // select overflow_area if index > 8
3384 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3385 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
3386
3387 // adjustment constant gpr_index * 4/8
3388 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
3389 VT.isInteger() ? GprIndex : FprIndex,
3390 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3391 MVT::i32));
3392
3393 // OurReg = RegSaveArea + RegConstant
3394 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
3395 RegConstant);
3396
3397 // Floating types are 32 bytes into RegSaveArea
3398 if (VT.isFloatingPoint())
3399 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
3400 DAG.getConstant(32, dl, MVT::i32));
3401
3402 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
3403 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3404 VT.isInteger() ? GprIndex : FprIndex,
3405 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
3406 MVT::i32));
3407
3408 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
3409 VT.isInteger() ? VAListPtr : FprPtr,
3410 MachinePointerInfo(SV), MVT::i8);
3411
3412 // determine if we should load from reg_save_area or overflow_area
3413 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3414
3415 // increase overflow_area by 4/8 if gpr/fpr > 8
3416 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
3417 DAG.getConstant(VT.isInteger() ? 4 : 8,
3418 dl, MVT::i32));
3419
3420 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
3421 OverflowAreaPlusN);
3422
3423 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
3424 MachinePointerInfo(), MVT::i32);
3425
3426 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
3427}
3428
3429SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3430 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only")((!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVACOPY is PPC32 only\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3430, __PRETTY_FUNCTION__))
;
3431
3432 // We have to copy the entire va_list struct:
3433 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3434 return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2),
3435 DAG.getConstant(12, SDLoc(Op), MVT::i32), Align(8),
3436 false, true, false, MachinePointerInfo(),
3437 MachinePointerInfo());
3438}
3439
3440SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3441 SelectionDAG &DAG) const {
3442 if (Subtarget.isAIXABI())
3443 report_fatal_error("ADJUST_TRAMPOLINE operation is not supported on AIX.");
3444
3445 return Op.getOperand(0);
3446}
3447
3448SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3449 SelectionDAG &DAG) const {
3450 if (Subtarget.isAIXABI())
3451 report_fatal_error("INIT_TRAMPOLINE operation is not supported on AIX.");
3452
3453 SDValue Chain = Op.getOperand(0);
3454 SDValue Trmp = Op.getOperand(1); // trampoline
3455 SDValue FPtr = Op.getOperand(2); // nested function
3456 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3457 SDLoc dl(Op);
3458
3459 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3460 bool isPPC64 = (PtrVT == MVT::i64);
3461 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3462
3463 TargetLowering::ArgListTy Args;
3464 TargetLowering::ArgListEntry Entry;
3465
3466 Entry.Ty = IntPtrTy;
3467 Entry.Node = Trmp; Args.push_back(Entry);
3468
3469 // TrampSize == (isPPC64 ? 48 : 40);
3470 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3471 isPPC64 ? MVT::i64 : MVT::i32);
3472 Args.push_back(Entry);
3473
3474 Entry.Node = FPtr; Args.push_back(Entry);
3475 Entry.Node = Nest; Args.push_back(Entry);
3476
3477 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3478 TargetLowering::CallLoweringInfo CLI(DAG);
3479 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3480 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3481 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3482
3483 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3484 return CallResult.second;
3485}
3486
3487SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3488 MachineFunction &MF = DAG.getMachineFunction();
3489 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3490 EVT PtrVT = getPointerTy(MF.getDataLayout());
3491
3492 SDLoc dl(Op);
3493
3494 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) {
3495 // vastart just stores the address of the VarArgsFrameIndex slot into the
3496 // memory location argument.
3497 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3498 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3499 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3500 MachinePointerInfo(SV));
3501 }
3502
3503 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3504 // We suppose the given va_list is already allocated.
3505 //
3506 // typedef struct {
3507 // char gpr; /* index into the array of 8 GPRs
3508 // * stored in the register save area
3509 // * gpr=0 corresponds to r3,
3510 // * gpr=1 to r4, etc.
3511 // */
3512 // char fpr; /* index into the array of 8 FPRs
3513 // * stored in the register save area
3514 // * fpr=0 corresponds to f1,
3515 // * fpr=1 to f2, etc.
3516 // */
3517 // char *overflow_arg_area;
3518 // /* location on stack that holds
3519 // * the next overflow argument
3520 // */
3521 // char *reg_save_area;
3522 // /* where r3:r10 and f1:f8 (if saved)
3523 // * are stored
3524 // */
3525 // } va_list[1];
3526
3527 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3528 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3529 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3530 PtrVT);
3531 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3532 PtrVT);
3533
3534 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3535 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3536
3537 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3538 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3539
3540 uint64_t FPROffset = 1;
3541 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3542
3543 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3544
3545 // Store first byte : number of int regs
3546 SDValue firstStore =
3547 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3548 MachinePointerInfo(SV), MVT::i8);
3549 uint64_t nextOffset = FPROffset;
3550 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3551 ConstFPROffset);
3552
3553 // Store second byte : number of float regs
3554 SDValue secondStore =
3555 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3556 MachinePointerInfo(SV, nextOffset), MVT::i8);
3557 nextOffset += StackOffset;
3558 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3559
3560 // Store second word : arguments given on stack
3561 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3562 MachinePointerInfo(SV, nextOffset));
3563 nextOffset += FrameOffset;
3564 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3565
3566 // Store third word : arguments given in registers
3567 return DAG.getStore(thirdStore, dl, FR, nextPtr,
3568 MachinePointerInfo(SV, nextOffset));
3569}
3570
3571/// FPR - The set of FP registers that should be allocated for arguments
3572/// on Darwin and AIX.
3573static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3574 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3575 PPC::F11, PPC::F12, PPC::F13};
3576
3577/// CalculateStackSlotSize - Calculates the size reserved for this argument on
3578/// the stack.
3579static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3580 unsigned PtrByteSize) {
3581 unsigned ArgSize = ArgVT.getStoreSize();
3582 if (Flags.isByVal())
3583 ArgSize = Flags.getByValSize();
3584
3585 // Round up to multiples of the pointer size, except for array members,
3586 // which are always packed.
3587 if (!Flags.isInConsecutiveRegs())
3588 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3589
3590 return ArgSize;
3591}
3592
3593/// CalculateStackSlotAlignment - Calculates the alignment of this argument
3594/// on the stack.
3595static Align CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3596 ISD::ArgFlagsTy Flags,
3597 unsigned PtrByteSize) {
3598 Align Alignment(PtrByteSize);
3599
3600 // Altivec parameters are padded to a 16 byte boundary.
3601 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3602 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3603 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3604 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3605 Alignment = Align(16);
3606
3607 // ByVal parameters are aligned as requested.
3608 if (Flags.isByVal()) {
3609 auto BVAlign = Flags.getNonZeroByValAlign();
3610 if (BVAlign > PtrByteSize) {
3611 if (BVAlign.value() % PtrByteSize != 0)
3612 llvm_unreachable(::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3613)
3613 "ByVal alignment is not a multiple of the pointer size")::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3613)
;
3614
3615 Alignment = BVAlign;
3616 }
3617 }
3618
3619 // Array members are always packed to their original alignment.
3620 if (Flags.isInConsecutiveRegs()) {
3621 // If the array member was split into multiple registers, the first
3622 // needs to be aligned to the size of the full type. (Except for
3623 // ppcf128, which is only aligned as its f64 components.)
3624 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3625 Alignment = Align(OrigVT.getStoreSize());
3626 else
3627 Alignment = Align(ArgVT.getStoreSize());
3628 }
3629
3630 return Alignment;
3631}
3632
3633/// CalculateStackSlotUsed - Return whether this argument will use its
3634/// stack slot (instead of being passed in registers). ArgOffset,
3635/// AvailableFPRs, and AvailableVRs must hold the current argument
3636/// position, and will be updated to account for this argument.
3637static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags,
3638 unsigned PtrByteSize, unsigned LinkageSize,
3639 unsigned ParamAreaSize, unsigned &ArgOffset,
3640 unsigned &AvailableFPRs,
3641 unsigned &AvailableVRs) {
3642 bool UseMemory = false;
3643
3644 // Respect alignment of argument on the stack.
3645 Align Alignment =
3646 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3647 ArgOffset = alignTo(ArgOffset, Alignment);
3648 // If there's no space left in the argument save area, we must
3649 // use memory (this check also catches zero-sized arguments).
3650 if (ArgOffset >= LinkageSize + ParamAreaSize)
3651 UseMemory = true;
3652
3653 // Allocate argument on the stack.
3654 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3655 if (Flags.isInConsecutiveRegsLast())
3656 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3657 // If we overran the argument save area, we must use memory
3658 // (this check catches arguments passed partially in memory)
3659 if (ArgOffset > LinkageSize + ParamAreaSize)
3660 UseMemory = true;
3661
3662 // However, if the argument is actually passed in an FPR or a VR,
3663 // we don't use memory after all.
3664 if (!Flags.isByVal()) {
3665 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
3666 if (AvailableFPRs > 0) {
3667 --AvailableFPRs;
3668 return false;
3669 }
3670 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3671 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3672 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3673 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3674 if (AvailableVRs > 0) {
3675 --AvailableVRs;
3676 return false;
3677 }
3678 }
3679
3680 return UseMemory;
3681}
3682
3683/// EnsureStackAlignment - Round stack frame size up from NumBytes to
3684/// ensure minimum alignment required for target.
3685static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3686 unsigned NumBytes) {
3687 return alignTo(NumBytes, Lowering->getStackAlign());
3688}
3689
3690SDValue PPCTargetLowering::LowerFormalArguments(
3691 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3692 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3693 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3694 if (Subtarget.isAIXABI())
3695 return LowerFormalArguments_AIX(Chain, CallConv, isVarArg, Ins, dl, DAG,
3696 InVals);
3697 if (Subtarget.is64BitELFABI())
3698 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3699 InVals);
3700 if (Subtarget.is32BitELFABI())
3701 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3702 InVals);
3703
3704 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, dl, DAG,
3705 InVals);
3706}
3707
3708SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3709 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3710 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3711 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3712
3713 // 32-bit SVR4 ABI Stack Frame Layout:
3714 // +-----------------------------------+
3715 // +--> | Back chain |
3716 // | +-----------------------------------+
3717 // | | Floating-point register save area |
3718 // | +-----------------------------------+
3719 // | | General register save area |
3720 // | +-----------------------------------+
3721 // | | CR save word |
3722 // | +-----------------------------------+
3723 // | | VRSAVE save word |
3724 // | +-----------------------------------+
3725 // | | Alignment padding |
3726 // | +-----------------------------------+
3727 // | | Vector register save area |
3728 // | +-----------------------------------+
3729 // | | Local variable space |
3730 // | +-----------------------------------+
3731 // | | Parameter list area |
3732 // | +-----------------------------------+
3733 // | | LR save word |
3734 // | +-----------------------------------+
3735 // SP--> +--- | Back chain |
3736 // +-----------------------------------+
3737 //
3738 // Specifications:
3739 // System V Application Binary Interface PowerPC Processor Supplement
3740 // AltiVec Technology Programming Interface Manual
3741
3742 MachineFunction &MF = DAG.getMachineFunction();
3743 MachineFrameInfo &MFI = MF.getFrameInfo();
3744 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3745
3746 EVT PtrVT = getPointerTy(MF.getDataLayout());
3747 // Potential tail calls could cause overwriting of argument stack slots.
3748 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3749 (CallConv == CallingConv::Fast));
3750 const Align PtrAlign(4);
3751
3752 // Assign locations to all of the incoming arguments.
3753 SmallVector<CCValAssign, 16> ArgLocs;
3754 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3755 *DAG.getContext());
3756
3757 // Reserve space for the linkage area on the stack.
3758 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3759 CCInfo.AllocateStack(LinkageSize, PtrAlign);
3760 if (useSoftFloat())
3761 CCInfo.PreAnalyzeFormalArguments(Ins);
3762
3763 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3764 CCInfo.clearWasPPCF128();
3765
3766 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3767 CCValAssign &VA = ArgLocs[i];
3768
3769 // Arguments stored in registers.
3770 if (VA.isRegLoc()) {
3771 const TargetRegisterClass *RC;
3772 EVT ValVT = VA.getValVT();
3773
3774 switch (ValVT.getSimpleVT().SimpleTy) {
3775 default:
3776 llvm_unreachable("ValVT not supported by formal arguments Lowering")::llvm::llvm_unreachable_internal("ValVT not supported by formal arguments Lowering"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3776)
;
3777 case MVT::i1:
3778 case MVT::i32:
3779 RC = &PPC::GPRCRegClass;
3780 break;
3781 case MVT::f32:
3782 if (Subtarget.hasP8Vector())
3783 RC = &PPC::VSSRCRegClass;
3784 else if (Subtarget.hasSPE())
3785 RC = &PPC::GPRCRegClass;
3786 else
3787 RC = &PPC::F4RCRegClass;
3788 break;
3789 case MVT::f64:
3790 if (Subtarget.hasVSX())
3791 RC = &PPC::VSFRCRegClass;
3792 else if (Subtarget.hasSPE())
3793 // SPE passes doubles in GPR pairs.
3794 RC = &PPC::GPRCRegClass;
3795 else
3796 RC = &PPC::F8RCRegClass;
3797 break;
3798 case MVT::v16i8:
3799 case MVT::v8i16:
3800 case MVT::v4i32:
3801 RC = &PPC::VRRCRegClass;
3802 break;
3803 case MVT::v4f32:
3804 RC = &PPC::VRRCRegClass;
3805 break;
3806 case MVT::v2f64:
3807 case MVT::v2i64:
3808 RC = &PPC::VRRCRegClass;
3809 break;
3810 }
3811
3812 SDValue ArgValue;
3813 // Transform the arguments stored in physical registers into
3814 // virtual ones.
3815 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
3816 assert(i + 1 < e && "No second half of double precision argument")((i + 1 < e && "No second half of double precision argument"
) ? static_cast<void> (0) : __assert_fail ("i + 1 < e && \"No second half of double precision argument\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3816, __PRETTY_FUNCTION__))
;
3817 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC);
3818 unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC);
3819 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32);
3820 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32);
3821 if (!Subtarget.isLittleEndian())
3822 std::swap (ArgValueLo, ArgValueHi);
3823 ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo,
3824 ArgValueHi);
3825 } else {
3826 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3827 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3828 ValVT == MVT::i1 ? MVT::i32 : ValVT);
3829 if (ValVT == MVT::i1)
3830 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3831 }
3832
3833 InVals.push_back(ArgValue);
3834 } else {
3835 // Argument stored in memory.
3836 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3836, __PRETTY_FUNCTION__))
;
3837
3838 // Get the extended size of the argument type in stack
3839 unsigned ArgSize = VA.getLocVT().getStoreSize();
3840 // Get the actual size of the argument type
3841 unsigned ObjSize = VA.getValVT().getStoreSize();
3842 unsigned ArgOffset = VA.getLocMemOffset();
3843 // Stack objects in PPC32 are right justified.
3844 ArgOffset += ArgSize - ObjSize;
3845 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
3846
3847 // Create load nodes to retrieve arguments from the stack.
3848 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3849 InVals.push_back(
3850 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3851 }
3852 }
3853
3854 // Assign locations to all of the incoming aggregate by value arguments.
3855 // Aggregates passed by value are stored in the local variable space of the
3856 // caller's stack frame, right above the parameter list area.
3857 SmallVector<CCValAssign, 16> ByValArgLocs;
3858 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3859 ByValArgLocs, *DAG.getContext());
3860
3861 // Reserve stack space for the allocations in CCInfo.
3862 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrAlign);
3863
3864 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3865
3866 // Area that is at least reserved in the caller of this function.
3867 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3868 MinReservedArea = std::max(MinReservedArea, LinkageSize);
3869
3870 // Set the size that is at least reserved in caller of this function. Tail
3871 // call optimized function's reserved stack space needs to be aligned so that
3872 // taking the difference between two stack areas will result in an aligned
3873 // stack.
3874 MinReservedArea =
3875 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3876 FuncInfo->setMinReservedArea(MinReservedArea);
3877
3878 SmallVector<SDValue, 8> MemOps;
3879
3880 // If the function takes variable number of arguments, make a frame index for
3881 // the start of the first vararg value... for expansion of llvm.va_start.
3882 if (isVarArg) {
3883 static const MCPhysReg GPArgRegs[] = {
3884 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3885 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3886 };
3887 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3888
3889 static const MCPhysReg FPArgRegs[] = {
3890 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3891 PPC::F8
3892 };
3893 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3894
3895 if (useSoftFloat() || hasSPE())
3896 NumFPArgRegs = 0;
3897
3898 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3899 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3900
3901 // Make room for NumGPArgRegs and NumFPArgRegs.
3902 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3903 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3904
3905 FuncInfo->setVarArgsStackOffset(
3906 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3907 CCInfo.getNextStackOffset(), true));
3908
3909 FuncInfo->setVarArgsFrameIndex(
3910 MFI.CreateStackObject(Depth, Align(8), false));
3911 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3912
3913 // The fixed integer arguments of a variadic function are stored to the
3914 // VarArgsFrameIndex on the stack so that they may be loaded by
3915 // dereferencing the result of va_next.
3916 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
3917 // Get an existing live-in vreg, or add a new one.
3918 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
3919 if (!VReg)
3920 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3921
3922 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3923 SDValue Store =
3924 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3925 MemOps.push_back(Store);
3926 // Increment the address by four for the next argument to store
3927 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3928 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3929 }
3930
3931 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
3932 // is set.
3933 // The double arguments are stored to the VarArgsFrameIndex
3934 // on the stack.
3935 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
3936 // Get an existing live-in vreg, or add a new one.
3937 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
3938 if (!VReg)
3939 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3940
3941 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
3942 SDValue Store =
3943 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3944 MemOps.push_back(Store);
3945 // Increment the address by eight for the next argument to store
3946 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3947 PtrVT);
3948 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3949 }
3950 }
3951
3952 if (!MemOps.empty())
3953 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3954
3955 return Chain;
3956}
3957
3958// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3959// value to MVT::i64 and then truncate to the correct register size.
3960SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
3961 EVT ObjectVT, SelectionDAG &DAG,
3962 SDValue ArgVal,
3963 const SDLoc &dl) const {
3964 if (Flags.isSExt())
3965 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3966 DAG.getValueType(ObjectVT));
3967 else if (Flags.isZExt())
3968 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3969 DAG.getValueType(ObjectVT));
3970
3971 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3972}
3973
3974SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3975 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3976 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3977 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3978 // TODO: add description of PPC stack frame format, or at least some docs.
3979 //
3980 bool isELFv2ABI = Subtarget.isELFv2ABI();
3981 bool isLittleEndian = Subtarget.isLittleEndian();
3982 MachineFunction &MF = DAG.getMachineFunction();
3983 MachineFrameInfo &MFI = MF.getFrameInfo();
3984 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3985
3986 assert(!(CallConv == CallingConv::Fast && isVarArg) &&((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3987, __PRETTY_FUNCTION__))
3987 "fastcc not supported on varargs functions")((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3987, __PRETTY_FUNCTION__))
;
3988
3989 EVT PtrVT = getPointerTy(MF.getDataLayout());
3990 // Potential tail calls could cause overwriting of argument stack slots.
3991 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3992 (CallConv == CallingConv::Fast));
3993 unsigned PtrByteSize = 8;
3994 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3995
3996 static const MCPhysReg GPR[] = {
3997 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3998 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3999 };
4000 static const MCPhysReg VR[] = {
4001 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4002 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4003 };
4004
4005 const unsigned Num_GPR_Regs = array_lengthof(GPR);
4006 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4007 const unsigned Num_VR_Regs = array_lengthof(VR);
4008
4009 // Do a first pass over the arguments to determine whether the ABI
4010 // guarantees that our caller has allocated the parameter save area
4011 // on its stack frame. In the ELFv1 ABI, this is always the case;
4012 // in the ELFv2 ABI, it is true if this is a vararg function or if
4013 // any parameter is located in a stack slot.
4014
4015 bool HasParameterArea = !isELFv2ABI || isVarArg;
4016 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
4017 unsigned NumBytes = LinkageSize;
4018 unsigned AvailableFPRs = Num_FPR_Regs;
4019 unsigned AvailableVRs = Num_VR_Regs;
4020 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4021 if (Ins[i].Flags.isNest())
4022 continue;
4023
4024 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
4025 PtrByteSize, LinkageSize, ParamAreaSize,
4026 NumBytes, AvailableFPRs, AvailableVRs))
4027 HasParameterArea = true;
4028 }
4029
4030 // Add DAG nodes to load the arguments or copy them out of registers. On
4031 // entry to a function on PPC, the arguments start after the linkage area,
4032 // although the first ones are often in registers.
4033
4034 unsigned ArgOffset = LinkageSize;
4035 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4036 SmallVector<SDValue, 8> MemOps;
4037 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4038 unsigned CurArgIdx = 0;
4039 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4040 SDValue ArgVal;
4041 bool needsLoad = false;
4042 EVT ObjectVT = Ins[ArgNo].VT;
4043 EVT OrigVT = Ins[ArgNo].ArgVT;
4044 unsigned ObjSize = ObjectVT.getStoreSize();
4045 unsigned ArgSize = ObjSize;
4046 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4047 if (Ins[ArgNo].isOrigArg()) {
4048 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4049 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4050 }
4051 // We re-align the argument offset for each argument, except when using the
4052 // fast calling convention, when we need to make sure we do that only when
4053 // we'll actually use a stack slot.
4054 unsigned CurArgOffset;
4055 Align Alignment;
4056 auto ComputeArgOffset = [&]() {
4057 /* Respect alignment of argument on the stack. */
4058 Alignment =
4059 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
4060 ArgOffset = alignTo(ArgOffset, Alignment);
4061 CurArgOffset = ArgOffset;
4062 };
4063
4064 if (CallConv != CallingConv::Fast) {
4065 ComputeArgOffset();
4066
4067 /* Compute GPR index associated with argument offset. */
4068 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4069 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
4070 }
4071
4072 // FIXME the codegen can be much improved in some cases.
4073 // We do not have to keep everything in memory.
4074 if (Flags.isByVal()) {
4075 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4075, __PRETTY_FUNCTION__))
;
4076
4077 if (CallConv == CallingConv::Fast)
4078 ComputeArgOffset();
4079
4080 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4081 ObjSize = Flags.getByValSize();
4082 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4083 // Empty aggregate parameters do not take up registers. Examples:
4084 // struct { } a;
4085 // union { } b;
4086 // int c[0];
4087 // etc. However, we have to provide a place-holder in InVals, so
4088 // pretend we have an 8-byte item at the current address for that
4089 // purpose.
4090 if (!ObjSize) {
4091 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4092 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4093 InVals.push_back(FIN);
4094 continue;
4095 }
4096
4097 // Create a stack object covering all stack doublewords occupied
4098 // by the argument. If the argument is (fully or partially) on
4099 // the stack, or if the argument is fully in registers but the
4100 // caller has allocated the parameter save anyway, we can refer
4101 // directly to the caller's stack frame. Otherwise, create a
4102 // local copy in our own frame.
4103 int FI;
4104 if (HasParameterArea ||
4105 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
4106 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
4107 else
4108 FI = MFI.CreateStackObject(ArgSize, Alignment, false);
4109 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4110
4111 // Handle aggregates smaller than 8 bytes.
4112 if (ObjSize < PtrByteSize) {
4113 // The value of the object is its address, which differs from the
4114 // address of the enclosing doubleword on big-endian systems.
4115 SDValue Arg = FIN;
4116 if (!isLittleEndian) {
4117 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
4118 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
4119 }
4120 InVals.push_back(Arg);
4121
4122 if (GPR_idx != Num_GPR_Regs) {
4123 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4124 FuncInfo->addLiveInAttr(VReg, Flags);
4125 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4126 SDValue Store;
4127
4128 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
4129 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
4130 (ObjSize == 2 ? MVT::i16 : MVT::i32));
4131 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
4132 MachinePointerInfo(&*FuncArg), ObjType);
4133 } else {
4134 // For sizes that don't fit a truncating store (3, 5, 6, 7),
4135 // store the whole register as-is to the parameter save area
4136 // slot.
4137 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4138 MachinePointerInfo(&*FuncArg));
4139 }
4140
4141 MemOps.push_back(Store);
4142 }
4143 // Whether we copied from a register or not, advance the offset
4144 // into the parameter save area by a full doubleword.
4145 ArgOffset += PtrByteSize;
4146 continue;
4147 }
4148
4149 // The value of the object is its address, which is the address of
4150 // its first stack doubleword.
4151 InVals.push_back(FIN);
4152
4153 // Store whatever pieces of the object are in registers to memory.
4154 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4155 if (GPR_idx == Num_GPR_Regs)
4156 break;
4157
4158 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4159 FuncInfo->addLiveInAttr(VReg, Flags);
4160 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4161 SDValue Addr = FIN;
4162 if (j) {
4163 SDValue Off = DAG.getConstant(j, dl, PtrVT);
4164 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
4165 }
4166 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
4167 MachinePointerInfo(&*FuncArg, j));
4168 MemOps.push_back(Store);
4169 ++GPR_idx;
4170 }
4171 ArgOffset += ArgSize;
4172 continue;
4173 }
4174
4175 switch (ObjectVT.getSimpleVT().SimpleTy) {
4176 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4176)
;
4177 case MVT::i1:
4178 case MVT::i32:
4179 case MVT::i64:
4180 if (Flags.isNest()) {
4181 // The 'nest' parameter, if any, is passed in R11.
4182 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
4183 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4184
4185 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4186 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4187
4188 break;
4189 }
4190
4191 // These can be scalar arguments or elements of an integer array type
4192 // passed directly. Clang may use those instead of "byval" aggregate
4193 // types to avoid forcing arguments to memory unnecessarily.
4194 if (GPR_idx != Num_GPR_Regs) {
4195 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4196 FuncInfo->addLiveInAttr(VReg, Flags);
4197 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4198
4199 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4200 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4201 // value to MVT::i64 and then truncate to the correct register size.
4202 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4203 } else {
4204 if (CallConv == CallingConv::Fast)
4205 ComputeArgOffset();
4206
4207 needsLoad = true;
4208 ArgSize = PtrByteSize;
4209 }
4210 if (CallConv != CallingConv::Fast || needsLoad)
4211 ArgOffset += 8;
4212 break;
4213
4214 case MVT::f32:
4215 case MVT::f64:
4216 // These can be scalar arguments or elements of a float array type
4217 // passed directly. The latter are used to implement ELFv2 homogenous
4218 // float aggregates.
4219 if (FPR_idx != Num_FPR_Regs) {
4220 unsigned VReg;
4221
4222 if (ObjectVT == MVT::f32)
4223 VReg = MF.addLiveIn(FPR[FPR_idx],
4224 Subtarget.hasP8Vector()
4225 ? &PPC::VSSRCRegClass
4226 : &PPC::F4RCRegClass);
4227 else
4228 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
4229 ? &PPC::VSFRCRegClass
4230 : &PPC::F8RCRegClass);
4231
4232 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4233 ++FPR_idx;
4234 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
4235 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4236 // once we support fp <-> gpr moves.
4237
4238 // This can only ever happen in the presence of f32 array types,
4239 // since otherwise we never run out of FPRs before running out
4240 // of GPRs.
4241 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4242 FuncInfo->addLiveInAttr(VReg, Flags);
4243 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4244
4245 if (ObjectVT == MVT::f32) {
4246 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
4247 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
4248 DAG.getConstant(32, dl, MVT::i32));
4249 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
4250 }
4251
4252 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
4253 } else {
4254 if (CallConv == CallingConv::Fast)
4255 ComputeArgOffset();
4256
4257 needsLoad = true;
4258 }
4259
4260 // When passing an array of floats, the array occupies consecutive
4261 // space in the argument area; only round up to the next doubleword
4262 // at the end of the array. Otherwise, each float takes 8 bytes.
4263 if (CallConv != CallingConv::Fast || needsLoad) {
4264 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
4265 ArgOffset += ArgSize;
4266 if (Flags.isInConsecutiveRegsLast())
4267 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4268 }
4269 break;
4270 case MVT::v4f32:
4271 case MVT::v4i32:
4272 case MVT::v8i16:
4273 case MVT::v16i8:
4274 case MVT::v2f64:
4275 case MVT::v2i64:
4276 case MVT::v1i128:
4277 case MVT::f128:
4278 // These can be scalar arguments or elements of a vector array type
4279 // passed directly. The latter are used to implement ELFv2 homogenous
4280 // vector aggregates.
4281 if (VR_idx != Num_VR_Regs) {
4282 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4283 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4284 ++VR_idx;
4285 } else {
4286 if (CallConv == CallingConv::Fast)
4287 ComputeArgOffset();
4288 needsLoad = true;
4289 }
4290 if (CallConv != CallingConv::Fast || needsLoad)
4291 ArgOffset += 16;
4292 break;
4293 }
4294
4295 // We need to load the argument to a virtual register if we determined
4296 // above that we ran out of physical registers of the appropriate type.
4297 if (needsLoad) {
4298 if (ObjSize < ArgSize && !isLittleEndian)
4299 CurArgOffset += ArgSize - ObjSize;
4300 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
4301 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4302 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4303 }
4304
4305 InVals.push_back(ArgVal);
4306 }
4307
4308 // Area that is at least reserved in the caller of this function.
4309 unsigned MinReservedArea;
4310 if (HasParameterArea)
4311 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
4312 else
4313 MinReservedArea = LinkageSize;
4314
4315 // Set the size that is at least reserved in caller of this function. Tail
4316 // call optimized functions' reserved stack space needs to be aligned so that
4317 // taking the difference between two stack areas will result in an aligned
4318 // stack.
4319 MinReservedArea =
4320 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4321 FuncInfo->setMinReservedArea(MinReservedArea);
4322
4323 // If the function takes variable number of arguments, make a frame index for
4324 // the start of the first vararg value... for expansion of llvm.va_start.
4325 // On ELFv2ABI spec, it writes:
4326 // C programs that are intended to be *portable* across different compilers
4327 // and architectures must use the header file <stdarg.h> to deal with variable
4328 // argument lists.
4329 if (isVarArg && MFI.hasVAStart()) {
4330 int Depth = ArgOffset;
4331
4332 FuncInfo->setVarArgsFrameIndex(
4333 MFI.CreateFixedObject(PtrByteSize, Depth, true));
4334 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4335
4336 // If this function is vararg, store any remaining integer argument regs
4337 // to their spots on the stack so that they may be loaded by dereferencing
4338 // the result of va_next.
4339 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4340 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4341 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4342 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4343 SDValue Store =
4344 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4345 MemOps.push_back(Store);
4346 // Increment the address by four for the next argument to store
4347 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4348 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4349 }
4350 }
4351
4352 if (!MemOps.empty())
4353 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4354
4355 return Chain;
4356}
4357
4358SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
4359 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4360 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4361 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4362 // TODO: add description of PPC stack frame format, or at least some docs.
4363 //
4364 MachineFunction &MF = DAG.getMachineFunction();
4365 MachineFrameInfo &MFI = MF.getFrameInfo();
4366 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4367
4368 EVT PtrVT = getPointerTy(MF.getDataLayout());
4369 bool isPPC64 = PtrVT == MVT::i64;
4370 // Potential tail calls could cause overwriting of argument stack slots.
4371 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4372 (CallConv == CallingConv::Fast));
4373 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4374 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4375 unsigned ArgOffset = LinkageSize;
4376 // Area that is at least reserved in caller of this function.
4377 unsigned MinReservedArea = ArgOffset;
4378
4379 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4380 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4381 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4382 };
4383 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4384 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4385 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4386 };
4387 static const MCPhysReg VR[] = {
4388 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4389 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4390 };
4391
4392 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
4393 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4394 const unsigned Num_VR_Regs = array_lengthof( VR);
4395
4396 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4397
4398 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4399
4400 // In 32-bit non-varargs functions, the stack space for vectors is after the
4401 // stack space for non-vectors. We do not use this space unless we have
4402 // too many vectors to fit in registers, something that only occurs in
4403 // constructed examples:), but we have to walk the arglist to figure
4404 // that out...for the pathological case, compute VecArgOffset as the
4405 // start of the vector parameter area. Computing VecArgOffset is the
4406 // entire point of the following loop.
4407 unsigned VecArgOffset = ArgOffset;
4408 if (!isVarArg && !isPPC64) {
4409 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
4410 ++ArgNo) {
4411 EVT ObjectVT = Ins[ArgNo].VT;
4412 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4413
4414 if (Flags.isByVal()) {
4415 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
4416 unsigned ObjSize = Flags.getByValSize();
4417 unsigned ArgSize =
4418 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4419 VecArgOffset += ArgSize;
4420 continue;
4421 }
4422
4423 switch(ObjectVT.getSimpleVT().SimpleTy) {
4424 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4424)
;
4425 case MVT::i1:
4426 case MVT::i32:
4427 case MVT::f32:
4428 VecArgOffset += 4;
4429 break;
4430 case MVT::i64: // PPC64
4431 case MVT::f64:
4432 // FIXME: We are guaranteed to be !isPPC64 at this point.
4433 // Does MVT::i64 apply?
4434 VecArgOffset += 8;
4435 break;
4436 case MVT::v4f32:
4437 case MVT::v4i32:
4438 case MVT::v8i16:
4439 case MVT::v16i8:
4440 // Nothing to do, we're only looking at Nonvector args here.
4441 break;
4442 }
4443 }
4444 }
4445 // We've found where the vector parameter area in memory is. Skip the
4446 // first 12 parameters; these don't use that memory.
4447 VecArgOffset = ((VecArgOffset+15)/16)*16;
4448 VecArgOffset += 12*16;
4449
4450 // Add DAG nodes to load the arguments or copy them out of registers. On
4451 // entry to a function on PPC, the arguments start after the linkage area,
4452 // although the first ones are often in registers.
4453
4454 SmallVector<SDValue, 8> MemOps;
4455 unsigned nAltivecParamsAtEnd = 0;
4456 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4457 unsigned CurArgIdx = 0;
4458 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4459 SDValue ArgVal;
4460 bool needsLoad = false;
4461 EVT ObjectVT = Ins[ArgNo].VT;
4462 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
4463 unsigned ArgSize = ObjSize;
4464 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4465 if (Ins[ArgNo].isOrigArg()) {
4466 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4467 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4468 }
4469 unsigned CurArgOffset = ArgOffset;
4470
4471 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
4472 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
4473 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
4474 if (isVarArg || isPPC64) {
4475 MinReservedArea = ((MinReservedArea+15)/16)*16;
4476 MinReservedArea += CalculateStackSlotSize(ObjectVT,
4477 Flags,
4478 PtrByteSize);
4479 } else nAltivecParamsAtEnd++;
4480 } else
4481 // Calculate min reserved area.
4482 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
4483 Flags,
4484 PtrByteSize);
4485
4486 // FIXME the codegen can be much improved in some cases.
4487 // We do not have to keep everything in memory.
4488 if (Flags.isByVal()) {
4489 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4489, __PRETTY_FUNCTION__))
;
4490
4491 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4492 ObjSize = Flags.getByValSize();
4493 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4494 // Objects of size 1 and 2 are right justified, everything else is
4495 // left justified. This means the memory address is adjusted forwards.
4496 if (ObjSize==1 || ObjSize==2) {
4497 CurArgOffset = CurArgOffset + (4 - ObjSize);
4498 }
4499 // The value of the object is its address.
4500 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, false, true);
4501 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4502 InVals.push_back(FIN);
4503 if (ObjSize==1 || ObjSize==2) {
4504 if (GPR_idx != Num_GPR_Regs) {
4505 unsigned VReg;
4506 if (isPPC64)
4507 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4508 else
4509 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4510 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4511 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
4512 SDValue Store =
4513 DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
4514 MachinePointerInfo(&*FuncArg), ObjType);
4515 MemOps.push_back(Store);
4516 ++GPR_idx;
4517 }
4518
4519 ArgOffset += PtrByteSize;
4520
4521 continue;
4522 }
4523 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4524 // Store whatever pieces of the object are in registers
4525 // to memory. ArgOffset will be the address of the beginning
4526 // of the object.
4527 if (GPR_idx != Num_GPR_Regs) {
4528 unsigned VReg;
4529 if (isPPC64)
4530 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4531 else
4532 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4533 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4534 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4535 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4536 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4537 MachinePointerInfo(&*FuncArg, j));
4538 MemOps.push_back(Store);
4539 ++GPR_idx;
4540 ArgOffset += PtrByteSize;
4541 } else {
4542 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
4543 break;
4544 }
4545 }
4546 continue;
4547 }
4548
4549 switch (ObjectVT.getSimpleVT().SimpleTy) {
4550 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4550)
;
4551 case MVT::i1:
4552 case MVT::i32:
4553 if (!isPPC64) {
4554 if (GPR_idx != Num_GPR_Regs) {
4555 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4556 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4557
4558 if (ObjectVT == MVT::i1)
4559 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
4560
4561 ++GPR_idx;
4562 } else {
4563 needsLoad = true;
4564 ArgSize = PtrByteSize;
4565 }
4566 // All int arguments reserve stack space in the Darwin ABI.
4567 ArgOffset += PtrByteSize;
4568 break;
4569 }
4570 LLVM_FALLTHROUGH[[gnu::fallthrough]];
4571 case MVT::i64: // PPC64
4572 if (GPR_idx != Num_GPR_Regs) {
4573 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4574 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4575
4576 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4577 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4578 // value to MVT::i64 and then truncate to the correct register size.
4579 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4580
4581 ++GPR_idx;
4582 } else {
4583 needsLoad = true;
4584 ArgSize = PtrByteSize;
4585 }
4586 // All int arguments reserve stack space in the Darwin ABI.
4587 ArgOffset += 8;
4588 break;
4589
4590 case MVT::f32:
4591 case MVT::f64:
4592 // Every 4 bytes of argument space consumes one of the GPRs available for
4593 // argument passing.
4594 if (GPR_idx != Num_GPR_Regs) {
4595 ++GPR_idx;
4596 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
4597 ++GPR_idx;
4598 }
4599 if (FPR_idx != Num_FPR_Regs) {
4600 unsigned VReg;
4601
4602 if (ObjectVT == MVT::f32)
4603 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
4604 else
4605 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
4606
4607 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4608 ++FPR_idx;
4609 } else {
4610 needsLoad = true;
4611 }
4612
4613 // All FP arguments reserve stack space in the Darwin ABI.
4614 ArgOffset += isPPC64 ? 8 : ObjSize;
4615 break;
4616 case MVT::v4f32:
4617 case MVT::v4i32:
4618 case MVT::v8i16:
4619 case MVT::v16i8:
4620 // Note that vector arguments in registers don't reserve stack space,
4621 // except in varargs functions.
4622 if (VR_idx != Num_VR_Regs) {
4623 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4624 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4625 if (isVarArg) {
4626 while ((ArgOffset % 16) != 0) {
4627 ArgOffset += PtrByteSize;
4628 if (GPR_idx != Num_GPR_Regs)
4629 GPR_idx++;
4630 }
4631 ArgOffset += 16;
4632 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
4633 }
4634 ++VR_idx;
4635 } else {
4636 if (!isVarArg && !isPPC64) {
4637 // Vectors go after all the nonvectors.
4638 CurArgOffset = VecArgOffset;
4639 VecArgOffset += 16;
4640 } else {
4641 // Vectors are aligned.
4642 ArgOffset = ((ArgOffset+15)/16)*16;
4643 CurArgOffset = ArgOffset;
4644 ArgOffset += 16;
4645 }
4646 needsLoad = true;
4647 }
4648 break;
4649 }
4650
4651 // We need to load the argument to a virtual register if we determined above
4652 // that we ran out of physical registers of the appropriate type.
4653 if (needsLoad) {
4654 int FI = MFI.CreateFixedObject(ObjSize,
4655 CurArgOffset + (ArgSize - ObjSize),
4656 isImmutable);
4657 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4658 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4659 }
4660
4661 InVals.push_back(ArgVal);
4662 }
4663
4664 // Allow for Altivec parameters at the end, if needed.
4665 if (nAltivecParamsAtEnd) {
4666 MinReservedArea = ((MinReservedArea+15)/16)*16;
4667 MinReservedArea += 16*nAltivecParamsAtEnd;
4668 }
4669
4670 // Area that is at least reserved in the caller of this function.
4671 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
4672
4673 // Set the size that is at least reserved in caller of this function. Tail
4674 // call optimized functions' reserved stack space needs to be aligned so that
4675 // taking the difference between two stack areas will result in an aligned
4676 // stack.
4677 MinReservedArea =
4678 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4679 FuncInfo->setMinReservedArea(MinReservedArea);
4680
4681 // If the function takes variable number of arguments, make a frame index for
4682 // the start of the first vararg value... for expansion of llvm.va_start.
4683 if (isVarArg) {
4684 int Depth = ArgOffset;
4685
4686 FuncInfo->setVarArgsFrameIndex(
4687 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
4688 Depth, true));
4689 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4690
4691 // If this function is vararg, store any remaining integer argument regs
4692 // to their spots on the stack so that they may be loaded by dereferencing
4693 // the result of va_next.
4694 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
4695 unsigned VReg;
4696
4697 if (isPPC64)
4698 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4699 else
4700 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4701
4702 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4703 SDValue Store =
4704 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4705 MemOps.push_back(Store);
4706 // Increment the address by four for the next argument to store
4707 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4708 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4709 }
4710 }
4711
4712 if (!MemOps.empty())
4713 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4714
4715 return Chain;
4716}
4717
4718/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4719/// adjusted to accommodate the arguments for the tailcall.
4720static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4721 unsigned ParamSize) {
4722
4723 if (!isTailCall) return 0;
4724
4725 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4726 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4727 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4728 // Remember only if the new adjustment is bigger.
4729 if (SPDiff < FI->getTailCallSPDelta())
4730 FI->setTailCallSPDelta(SPDiff);
4731
4732 return SPDiff;
4733}
4734
4735static bool isFunctionGlobalAddress(SDValue Callee);
4736
4737static bool callsShareTOCBase(const Function *Caller, SDValue Callee,
4738 const TargetMachine &TM) {
4739 // It does not make sense to call callsShareTOCBase() with a caller that
4740 // is PC Relative since PC Relative callers do not have a TOC.
4741#ifndef NDEBUG
4742 const PPCSubtarget *STICaller = &TM.getSubtarget<PPCSubtarget>(*Caller);
4743 assert(!STICaller->isUsingPCRelativeCalls() &&((!STICaller->isUsingPCRelativeCalls() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? static_cast<void> (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4744, __PRETTY_FUNCTION__))
4744 "PC Relative callers do not have a TOC and cannot share a TOC Base")((!STICaller->isUsingPCRelativeCalls() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? static_cast<void> (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4744, __PRETTY_FUNCTION__))
;
4745#endif
4746
4747 // Callee is either a GlobalAddress or an ExternalSymbol. ExternalSymbols
4748 // don't have enough information to determine if the caller and callee share
4749 // the same TOC base, so we have to pessimistically assume they don't for
4750 // correctness.
4751 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4752 if (!G)
4753 return false;
4754
4755 const GlobalValue *GV = G->getGlobal();
4756
4757 // If the callee is preemptable, then the static linker will use a plt-stub
4758 // which saves the toc to the stack, and needs a nop after the call
4759 // instruction to convert to a toc-restore.
4760 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4761 return false;
4762
4763 // Functions with PC Relative enabled may clobber the TOC in the same DSO.
4764 // We may need a TOC restore in the situation where the caller requires a
4765 // valid TOC but the callee is PC Relative and does not.
4766 const Function *F = dyn_cast<Function>(GV);
4767 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
4768
4769 // If we have an Alias we can try to get the function from there.
4770 if (Alias) {
4771 const GlobalObject *GlobalObj = Alias->getBaseObject();
4772 F = dyn_cast<Function>(GlobalObj);
4773 }
4774
4775 // If we still have no valid function pointer we do not have enough
4776 // information to determine if the callee uses PC Relative calls so we must
4777 // assume that it does.
4778 if (!F)
4779 return false;
4780
4781 // If the callee uses PC Relative we cannot guarantee that the callee won't
4782 // clobber the TOC of the caller and so we must assume that the two
4783 // functions do not share a TOC base.
4784 const PPCSubtarget *STICallee = &TM.getSubtarget<PPCSubtarget>(*F);
4785 if (STICallee->isUsingPCRelativeCalls())
4786 return false;
4787
4788 // The medium and large code models are expected to provide a sufficiently
4789 // large TOC to provide all data addressing needs of a module with a
4790 // single TOC.
4791 if (CodeModel::Medium == TM.getCodeModel() ||
4792 CodeModel::Large == TM.getCodeModel())
4793 return true;
4794
4795 // Otherwise we need to ensure callee and caller are in the same section,
4796 // since the linker may allocate multiple TOCs, and we don't know which
4797 // sections will belong to the same TOC base.
4798 if (!GV->isStrongDefinitionForLinker())
4799 return false;
4800
4801 // Any explicitly-specified sections and section prefixes must also match.
4802 // Also, if we're using -ffunction-sections, then each function is always in
4803 // a different section (the same is true for COMDAT functions).
4804 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4805 GV->getSection() != Caller->getSection())
4806 return false;
4807 if (const auto *F = dyn_cast<Function>(GV)) {
4808 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4809 return false;
4810 }
4811
4812 return true;
4813}
4814
4815static bool
4816needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4817 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4818 assert(Subtarget.is64BitELFABI())((Subtarget.is64BitELFABI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.is64BitELFABI()", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4818, __PRETTY_FUNCTION__))
;
4819
4820 const unsigned PtrByteSize = 8;
4821 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4822
4823 static const MCPhysReg GPR[] = {
4824 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4825 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4826 };
4827 static const MCPhysReg VR[] = {
4828 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4829 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4830 };
4831
4832 const unsigned NumGPRs = array_lengthof(GPR);
4833 const unsigned NumFPRs = 13;
4834 const unsigned NumVRs = array_lengthof(VR);
4835 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4836
4837 unsigned NumBytes = LinkageSize;
4838 unsigned AvailableFPRs = NumFPRs;
4839 unsigned AvailableVRs = NumVRs;
4840
4841 for (const ISD::OutputArg& Param : Outs) {
4842 if (Param.Flags.isNest()) continue;
4843
4844 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags, PtrByteSize,
4845 LinkageSize, ParamAreaSize, NumBytes,
4846 AvailableFPRs, AvailableVRs))
4847 return true;
4848 }
4849 return false;
4850}
4851
4852static bool hasSameArgumentList(const Function *CallerFn, const CallBase &CB) {
4853 if (CB.arg_size() != CallerFn->arg_size())
4854 return false;
4855
4856 auto CalleeArgIter = CB.arg_begin();
4857 auto CalleeArgEnd = CB.arg_end();
4858 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4859
4860 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4861 const Value* CalleeArg = *CalleeArgIter;
4862 const Value* CallerArg = &(*CallerArgIter);
4863 if (CalleeArg == CallerArg)
4864 continue;
4865
4866 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4867 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4868 // }
4869 // 1st argument of callee is undef and has the same type as caller.
4870 if (CalleeArg->getType() == CallerArg->getType() &&
4871 isa<UndefValue>(CalleeArg))
4872 continue;
4873
4874 return false;
4875 }
4876
4877 return true;
4878}
4879
4880// Returns true if TCO is possible between the callers and callees
4881// calling conventions.
4882static bool
4883areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4884 CallingConv::ID CalleeCC) {
4885 // Tail calls are possible with fastcc and ccc.
4886 auto isTailCallableCC = [] (CallingConv::ID CC){
4887 return CC == CallingConv::C || CC == CallingConv::Fast;
4888 };
4889 if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC))
4890 return false;
4891
4892 // We can safely tail call both fastcc and ccc callees from a c calling
4893 // convention caller. If the caller is fastcc, we may have less stack space
4894 // than a non-fastcc caller with the same signature so disable tail-calls in
4895 // that case.
4896 return CallerCC == CallingConv::C || CallerCC == CalleeCC;
4897}
4898
4899bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4900 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, bool isVarArg,
4901 const SmallVectorImpl<ISD::OutputArg> &Outs,
4902 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4903 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4904
4905 if (DisableSCO && !TailCallOpt) return false;
4906
4907 // Variadic argument functions are not supported.
4908 if (isVarArg) return false;
4909
4910 auto &Caller = DAG.getMachineFunction().getFunction();
4911 // Check that the calling conventions are compatible for tco.
4912 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4913 return false;
4914
4915 // Caller contains any byval parameter is not supported.
4916 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4917 return false;
4918
4919 // Callee contains any byval parameter is not supported, too.
4920 // Note: This is a quick work around, because in some cases, e.g.
4921 // caller's stack size > callee's stack size, we are still able to apply
4922 // sibling call optimization. For example, gcc is able to do SCO for caller1
4923 // in the following example, but not for caller2.
4924 // struct test {
4925 // long int a;
4926 // char ary[56];
4927 // } gTest;
4928 // __attribute__((noinline)) int callee(struct test v, struct test *b) {
4929 // b->a = v.a;
4930 // return 0;
4931 // }
4932 // void caller1(struct test a, struct test c, struct test *b) {
4933 // callee(gTest, b); }
4934 // void caller2(struct test *b) { callee(gTest, b); }
4935 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4936 return false;
4937
4938 // If callee and caller use different calling conventions, we cannot pass
4939 // parameters on stack since offsets for the parameter area may be different.
4940 if (Caller.getCallingConv() != CalleeCC &&
4941 needStackSlotPassParameters(Subtarget, Outs))
4942 return false;
4943
4944 // All variants of 64-bit ELF ABIs without PC-Relative addressing require that
4945 // the caller and callee share the same TOC for TCO/SCO. If the caller and
4946 // callee potentially have different TOC bases then we cannot tail call since
4947 // we need to restore the TOC pointer after the call.
4948 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4949 // We cannot guarantee this for indirect calls or calls to external functions.
4950 // When PC-Relative addressing is used, the concept of the TOC is no longer
4951 // applicable so this check is not required.
4952 // Check first for indirect calls.
4953 if (!Subtarget.isUsingPCRelativeCalls() &&
4954 !isFunctionGlobalAddress(Callee) && !isa<ExternalSymbolSDNode>(Callee))
4955 return false;
4956
4957 // Check if we share the TOC base.
4958 if (!Subtarget.isUsingPCRelativeCalls() &&
4959 !callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4960 return false;
4961
4962 // TCO allows altering callee ABI, so we don't have to check further.
4963 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4964 return true;
4965
4966 if (DisableSCO) return false;
4967
4968 // If callee use the same argument list that caller is using, then we can
4969 // apply SCO on this case. If it is not, then we need to check if callee needs
4970 // stack for passing arguments.
4971 // PC Relative tail calls may not have a CallBase.
4972 // If there is no CallBase we cannot verify if we have the same argument
4973 // list so assume that we don't have the same argument list.
4974 if (CB && !hasSameArgumentList(&Caller, *CB) &&
4975 needStackSlotPassParameters(Subtarget, Outs))
4976 return false;
4977 else if (!CB && needStackSlotPassParameters(Subtarget, Outs))
4978 return false;
4979
4980 return true;
4981}
4982
4983/// IsEligibleForTailCallOptimization - Check whether the call is eligible
4984/// for tail call optimization. Targets which want to do tail call
4985/// optimization should implement this function.
4986bool
4987PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4988 CallingConv::ID CalleeCC,
4989 bool isVarArg,
4990 const SmallVectorImpl<ISD::InputArg> &Ins,
4991 SelectionDAG& DAG) const {
4992 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4993 return false;
4994
4995 // Variable argument functions are not supported.
4996 if (isVarArg)
4997 return false;
4998
4999 MachineFunction &MF = DAG.getMachineFunction();
5000 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
5001 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
5002 // Functions containing by val parameters are not supported.
5003 for (unsigned i = 0; i != Ins.size(); i++) {
5004 ISD::ArgFlagsTy Flags = Ins[i].Flags;
5005 if (Flags.isByVal()) return false;
5006 }
5007
5008 // Non-PIC/GOT tail calls are supported.
5009 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
5010 return true;
5011
5012 // At the moment we can only do local tail calls (in same module, hidden
5013 // or protected) if we are generating PIC.
5014 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
5015 return G->getGlobal()->hasHiddenVisibility()
5016 || G->getGlobal()->hasProtectedVisibility();
5017 }
5018
5019 return false;
5020}
5021
5022/// isCallCompatibleAddress - Return the immediate to use if the specified
5023/// 32-bit value is representable in the immediate field of a BxA instruction.
5024static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
5025 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5026 if (!C) return nullptr;
5027
5028 int Addr = C->getZExtValue();
5029 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
5030 SignExtend32<26>(Addr) != Addr)
5031 return nullptr; // Top 6 bits have to be sext of immediate.
5032
5033 return DAG
5034 .getConstant(
5035 (int)C->getZExtValue() >> 2, SDLoc(Op),
5036 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
5037 .getNode();
5038}
5039
5040namespace {
5041
5042struct TailCallArgumentInfo {
5043 SDValue Arg;
5044 SDValue FrameIdxOp;
5045 int FrameIdx = 0;
5046
5047 TailCallArgumentInfo() = default;
5048};
5049
5050} // end anonymous namespace
5051
5052/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
5053static void StoreTailCallArgumentsToStackSlot(
5054 SelectionDAG &DAG, SDValue Chain,
5055 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
5056 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
5057 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
5058 SDValue Arg = TailCallArgs[i].Arg;
5059 SDValue FIN = TailCallArgs[i].FrameIdxOp;
5060 int FI = TailCallArgs[i].FrameIdx;
5061 // Store relative to framepointer.
5062 MemOpChains.push_back(DAG.getStore(
5063 Chain, dl, Arg, FIN,
5064 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
5065 }
5066}
5067
5068/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
5069/// the appropriate stack slot for the tail call optimized function call.
5070static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
5071 SDValue OldRetAddr, SDValue OldFP,
5072 int SPDiff, const SDLoc &dl) {
5073 if (SPDiff) {
5074 // Calculate the new stack slot for the return address.
5075 MachineFunction &MF = DAG.getMachineFunction();
5076 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
5077 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
5078 bool isPPC64 = Subtarget.isPPC64();
5079 int SlotSize = isPPC64 ? 8 : 4;
5080 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
5081 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
5082 NewRetAddrLoc, true);
5083 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5084 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
5085 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
5086 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
5087 }
5088 return Chain;
5089}
5090
5091/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
5092/// the position of the argument.
5093static void
5094CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
5095 SDValue Arg, int SPDiff, unsigned ArgOffset,
5096 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
5097 int Offset = ArgOffset + SPDiff;
5098 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
5099 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
5100 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5101 SDValue FIN = DAG.getFrameIndex(FI, VT);
5102 TailCallArgumentInfo Info;
5103 Info.Arg = Arg;
5104 Info.FrameIdxOp = FIN;
5105 Info.FrameIdx = FI;
5106 TailCallArguments.push_back(Info);
5107}
5108
5109/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
5110/// stack slot. Returns the chain as result and the loaded frame pointers in
5111/// LROpOut/FPOpout. Used when tail calling.
5112SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
5113 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
5114 SDValue &FPOpOut, const SDLoc &dl) const {
5115 if (SPDiff) {
5116 // Load the LR and FP stack slot for later adjusting.
5117 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5118 LROpOut = getReturnAddrFrameIndex(DAG);
5119 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
5120 Chain = SDValue(LROpOut.getNode(), 1);
5121 }
5122 return Chain;
5123}
5124
5125/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
5126/// by "Src" to address "Dst" of size "Size". Alignment information is
5127/// specified by the specific parameter attribute. The copy will be passed as
5128/// a byval function parameter.
5129/// Sometimes what we are copying is the end of a larger object, the part that
5130/// does not fit in registers.
5131static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
5132 SDValue Chain, ISD::ArgFlagsTy Flags,
5133 SelectionDAG &DAG, const SDLoc &dl) {
5134 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
5135 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
5136 Flags.getNonZeroByValAlign(), false, false, false,
5137 MachinePointerInfo(), MachinePointerInfo());
5138}
5139
5140/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
5141/// tail calls.
5142static void LowerMemOpCallTo(
5143 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
5144 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
5145 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
5146 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
5147 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5148 if (!isTailCall) {
5149 if (isVector) {
5150 SDValue StackPtr;
5151 if (isPPC64)
5152 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5153 else
5154 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5155 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5156 DAG.getConstant(ArgOffset, dl, PtrVT));
5157 }
5158 MemOpChains.push_back(
5159 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5160 // Calculate and remember argument location.
5161 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
5162 TailCallArguments);
5163}
5164
5165static void
5166PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
5167 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
5168 SDValue FPOp,
5169 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
5170 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
5171 // might overwrite each other in case of tail call optimization.
5172 SmallVector<SDValue, 8> MemOpChains2;
5173 // Do not flag preceding copytoreg stuff together with the following stuff.
5174 InFlag = SDValue();
5175 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
5176 MemOpChains2, dl);
5177 if (!MemOpChains2.empty())
5178 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
5179
5180 // Store the return address to the appropriate stack slot.
5181 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
5182
5183 // Emit callseq_end just before tailcall node.
5184 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5185 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
5186 InFlag = Chain.getValue(1);
5187}
5188
5189// Is this global address that of a function that can be called by name? (as
5190// opposed to something that must hold a descriptor for an indirect call).
5191static bool isFunctionGlobalAddress(SDValue Callee) {
5192 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
5193 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
5194 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
5195 return false;
5196
5197 return G->getGlobal()->getValueType()->isFunctionTy();
5198 }
5199
5200 return false;
5201}
5202
5203SDValue PPCTargetLowering::LowerCallResult(
5204 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
5205 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5206 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5207 SmallVector<CCValAssign, 16> RVLocs;
5208 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5209 *DAG.getContext());
5210
5211 CCRetInfo.AnalyzeCallResult(
5212 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold)
5213 ? RetCC_PPC_Cold
5214 : RetCC_PPC);
5215
5216 // Copy all of the result registers out of their specified physreg.
5217 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
5218 CCValAssign &VA = RVLocs[i];
5219 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5219, __PRETTY_FUNCTION__))
;
5220
5221 SDValue Val;
5222
5223 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
5224 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5225 InFlag);
5226 Chain = Lo.getValue(1);
5227 InFlag = Lo.getValue(2);
5228 VA = RVLocs[++i]; // skip ahead to next loc
5229 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5230 InFlag);
5231 Chain = Hi.getValue(1);
5232 InFlag = Hi.getValue(2);
5233 if (!Subtarget.isLittleEndian())
5234 std::swap (Lo, Hi);
5235 Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi);
5236 } else {
5237 Val = DAG.getCopyFromReg(Chain, dl,
5238 VA.getLocReg(), VA.getLocVT(), InFlag);
5239 Chain = Val.getValue(1);
5240 InFlag = Val.getValue(2);
5241 }
5242
5243 switch (VA.getLocInfo()) {
5244 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5244)
;
5245 case CCValAssign::Full: break;
5246 case CCValAssign::AExt:
5247 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5248 break;
5249 case CCValAssign::ZExt:
5250 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
5251 DAG.getValueType(VA.getValVT()));
5252 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5253 break;
5254 case CCValAssign::SExt:
5255 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
5256 DAG.getValueType(VA.getValVT()));
5257 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5258 break;
5259 }
5260
5261 InVals.push_back(Val);
5262 }
5263
5264 return Chain;
5265}
5266
5267static bool isIndirectCall(const SDValue &Callee, SelectionDAG &DAG,
5268 const PPCSubtarget &Subtarget, bool isPatchPoint) {
5269 // PatchPoint calls are not indirect.
5270 if (isPatchPoint)
5271 return false;
5272
5273 if (isFunctionGlobalAddress(Callee) || dyn_cast<ExternalSymbolSDNode>(Callee))
5274 return false;
5275
5276 // Darwin, and 32-bit ELF can use a BLA. The descriptor based ABIs can not
5277 // becuase the immediate function pointer points to a descriptor instead of
5278 // a function entry point. The ELFv2 ABI cannot use a BLA because the function
5279 // pointer immediate points to the global entry point, while the BLA would
5280 // need to jump to the local entry point (see rL211174).
5281 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() &&
5282 isBLACompatibleAddress(Callee, DAG))
5283 return false;
5284
5285 return true;
5286}
5287
5288// AIX and 64-bit ELF ABIs w/o PCRel require a TOC save/restore around calls.
5289static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) {
5290 return Subtarget.isAIXABI() ||
5291 (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls());
5292}
5293
5294static unsigned getCallOpcode(PPCTargetLowering::CallFlags CFlags,
5295 const Function &Caller,
5296 const SDValue &Callee,
5297 const PPCSubtarget &Subtarget,
5298 const TargetMachine &TM) {
5299 if (CFlags.IsTailCall)
5300 return PPCISD::TC_RETURN;
5301
5302 // This is a call through a function pointer.
5303 if (CFlags.IsIndirect) {
5304 // AIX and the 64-bit ELF ABIs need to maintain the TOC pointer accross
5305 // indirect calls. The save of the caller's TOC pointer to the stack will be
5306 // inserted into the DAG as part of call lowering. The restore of the TOC
5307 // pointer is modeled by using a pseudo instruction for the call opcode that
5308 // represents the 2 instruction sequence of an indirect branch and link,
5309 // immediately followed by a load of the TOC pointer from the the stack save
5310 // slot into gpr2. For 64-bit ELFv2 ABI with PCRel, do not restore the TOC
5311 // as it is not saved or used.
5312 return isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC
5313 : PPCISD::BCTRL;
5314 }
5315
5316 if (Subtarget.isUsingPCRelativeCalls()) {
5317 assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI.")((Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.is64BitELFABI() && \"PC Relative is only on ELF ABI.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5317, __PRETTY_FUNCTION__))
;
5318 return PPCISD::CALL_NOTOC;
5319 }
5320
5321 // The ABIs that maintain a TOC pointer accross calls need to have a nop
5322 // immediately following the call instruction if the caller and callee may
5323 // have different TOC bases. At link time if the linker determines the calls
5324 // may not share a TOC base, the call is redirected to a trampoline inserted
5325 // by the linker. The trampoline will (among other things) save the callers
5326 // TOC pointer at an ABI designated offset in the linkage area and the linker
5327 // will rewrite the nop to be a load of the TOC pointer from the linkage area
5328 // into gpr2.
5329 if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
5330 return callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL
5331 : PPCISD::CALL_NOP;
5332
5333 return PPCISD::CALL;
5334}
5335
5336static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
5337 const SDLoc &dl, const PPCSubtarget &Subtarget) {
5338 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI())
5339 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
5340 return SDValue(Dest, 0);
5341
5342 // Returns true if the callee is local, and false otherwise.
5343 auto isLocalCallee = [&]() {
5344 const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
5345 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5346 const GlobalValue *GV = G ? G->getGlobal() : nullptr;
5347
5348 return DAG.getTarget().shouldAssumeDSOLocal(*Mod, GV) &&
5349 !dyn_cast_or_null<GlobalIFunc>(GV);
5350 };
5351
5352 // The PLT is only used in 32-bit ELF PIC mode. Attempting to use the PLT in
5353 // a static relocation model causes some versions of GNU LD (2.17.50, at
5354 // least) to force BSS-PLT, instead of secure-PLT, even if all objects are
5355 // built with secure-PLT.
5356 bool UsePlt =
5357 Subtarget.is32BitELFABI() && !isLocalCallee() &&
5358 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_;
5359
5360 const auto getAIXFuncEntryPointSymbolSDNode = [&](const GlobalValue *GV) {
5361 const TargetMachine &TM = Subtarget.getTargetMachine();
5362 const TargetLoweringObjectFile *TLOF = TM.getObjFileLowering();
5363 MCSymbolXCOFF *S =
5364 cast<MCSymbolXCOFF>(TLOF->getFunctionEntryPointSymbol(GV, TM));
5365
5366 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5367 return DAG.getMCSymbol(S, PtrVT);
5368 };
5369
5370 if (isFunctionGlobalAddress(Callee)) {
5371 const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
5372
5373 if (Subtarget.isAIXABI()) {
5374 assert(!isa<GlobalIFunc>(GV) && "IFunc is not supported on AIX.")((!isa<GlobalIFunc>(GV) && "IFunc is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("!isa<GlobalIFunc>(GV) && \"IFunc is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5374, __PRETTY_FUNCTION__))
;
5375 return getAIXFuncEntryPointSymbolSDNode(GV);
5376 }
5377 return DAG.getTargetGlobalAddress(GV, dl, Callee.getValueType(), 0,
5378 UsePlt ? PPCII::MO_PLT : 0);
5379 }
5380
5381 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
5382 const char *SymName = S->getSymbol();
5383 if (Subtarget.isAIXABI()) {
5384 // If there exists a user-declared function whose name is the same as the
5385 // ExternalSymbol's, then we pick up the user-declared version.
5386 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5387 if (const Function *F =
5388 dyn_cast_or_null<Function>(Mod->getNamedValue(SymName)))
5389 return getAIXFuncEntryPointSymbolSDNode(F);
5390
5391 // On AIX, direct function calls reference the symbol for the function's
5392 // entry point, which is named by prepending a "." before the function's
5393 // C-linkage name. A Qualname is returned here because an external
5394 // function entry point is a csect with XTY_ER property.
5395 const auto getExternalFunctionEntryPointSymbol = [&](StringRef SymName) {
5396 auto &Context = DAG.getMachineFunction().getMMI().getContext();
5397 MCSectionXCOFF *Sec = Context.getXCOFFSection(
5398 (Twine(".") + Twine(SymName)).str(), XCOFF::XMC_PR, XCOFF::XTY_ER,
5399 SectionKind::getMetadata());
5400 return Sec->getQualNameSymbol();
5401 };
5402
5403 SymName = getExternalFunctionEntryPointSymbol(SymName)->getName().data();
5404 }
5405 return DAG.getTargetExternalSymbol(SymName, Callee.getValueType(),
5406 UsePlt ? PPCII::MO_PLT : 0);
5407 }
5408
5409 // No transformation needed.
5410 assert(Callee.getNode() && "What no callee?")((Callee.getNode() && "What no callee?") ? static_cast
<void> (0) : __assert_fail ("Callee.getNode() && \"What no callee?\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5410, __PRETTY_FUNCTION__))
;
5411 return Callee;
5412}
5413
5414static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart) {
5415 assert(CallSeqStart.getOpcode() == ISD::CALLSEQ_START &&((CallSeqStart.getOpcode() == ISD::CALLSEQ_START && "Expected a CALLSEQ_STARTSDNode."
) ? static_cast<void> (0) : __assert_fail ("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5416, __PRETTY_FUNCTION__))
5416 "Expected a CALLSEQ_STARTSDNode.")((CallSeqStart.getOpcode() == ISD::CALLSEQ_START && "Expected a CALLSEQ_STARTSDNode."
) ? static_cast<void> (0) : __assert_fail ("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5416, __PRETTY_FUNCTION__))
;
5417
5418 // The last operand is the chain, except when the node has glue. If the node
5419 // has glue, then the last operand is the glue, and the chain is the second
5420 // last operand.
5421 SDValue LastValue = CallSeqStart.getValue(CallSeqStart->getNumValues() - 1);
5422 if (LastValue.getValueType() != MVT::Glue)
5423 return LastValue;
5424
5425 return CallSeqStart.getValue(CallSeqStart->getNumValues() - 2);
5426}
5427
5428// Creates the node that moves a functions address into the count register
5429// to prepare for an indirect call instruction.
5430static void prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5431 SDValue &Glue, SDValue &Chain,
5432 const SDLoc &dl) {
5433 SDValue MTCTROps[] = {Chain, Callee, Glue};
5434 EVT ReturnTypes[] = {MVT::Other, MVT::Glue};
5435 Chain = DAG.getNode(PPCISD::MTCTR, dl, makeArrayRef(ReturnTypes, 2),
5436 makeArrayRef(MTCTROps, Glue.getNode() ? 3 : 2));
5437 // The glue is the second value produced.
5438 Glue = Chain.getValue(1);
5439}
5440
5441static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5442 SDValue &Glue, SDValue &Chain,
5443 SDValue CallSeqStart,
5444 const CallBase *CB, const SDLoc &dl,
5445 bool hasNest,
5446 const PPCSubtarget &Subtarget) {
5447 // Function pointers in the 64-bit SVR4 ABI do not point to the function
5448 // entry point, but to the function descriptor (the function entry point
5449 // address is part of the function descriptor though).
5450 // The function descriptor is a three doubleword structure with the
5451 // following fields: function entry point, TOC base address and
5452 // environment pointer.
5453 // Thus for a call through a function pointer, the following actions need
5454 // to be performed:
5455 // 1. Save the TOC of the caller in the TOC save area of its stack
5456 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
5457 // 2. Load the address of the function entry point from the function
5458 // descriptor.
5459 // 3. Load the TOC of the callee from the function descriptor into r2.
5460 // 4. Load the environment pointer from the function descriptor into
5461 // r11.
5462 // 5. Branch to the function entry point address.
5463 // 6. On return of the callee, the TOC of the caller needs to be
5464 // restored (this is done in FinishCall()).
5465 //
5466 // The loads are scheduled at the beginning of the call sequence, and the
5467 // register copies are flagged together to ensure that no other
5468 // operations can be scheduled in between. E.g. without flagging the
5469 // copies together, a TOC access in the caller could be scheduled between
5470 // the assignment of the callee TOC and the branch to the callee, which leads
5471 // to incorrect code.
5472
5473 // Start by loading the function address from the descriptor.
5474 SDValue LDChain = getOutputChainFromCallSeq(CallSeqStart);
5475 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
5476 ? (MachineMemOperand::MODereferenceable |
5477 MachineMemOperand::MOInvariant)
5478 : MachineMemOperand::MONone;
5479
5480 MachinePointerInfo MPI(CB ? CB->getCalledOperand() : nullptr);
5481
5482 // Registers used in building the DAG.
5483 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister();
5484 const MCRegister TOCReg = Subtarget.getTOCPointerRegister();
5485
5486 // Offsets of descriptor members.
5487 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset();
5488 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset();
5489
5490 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5491 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4;
5492
5493 // One load for the functions entry point address.
5494 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5495 Alignment, MMOFlags);
5496
5497 // One for loading the TOC anchor for the module that contains the called
5498 // function.
5499 SDValue TOCOff = DAG.getIntPtrConstant(TOCAnchorOffset, dl);
5500 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5501 SDValue TOCPtr =
5502 DAG.getLoad(RegVT, dl, LDChain, AddTOC,
5503 MPI.getWithOffset(TOCAnchorOffset), Alignment, MMOFlags);
5504
5505 // One for loading the environment pointer.
5506 SDValue PtrOff = DAG.getIntPtrConstant(EnvPtrOffset, dl);
5507 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5508 SDValue LoadEnvPtr =
5509 DAG.getLoad(RegVT, dl, LDChain, AddPtr,
5510 MPI.getWithOffset(EnvPtrOffset), Alignment, MMOFlags);
5511
5512
5513 // Then copy the newly loaded TOC anchor to the TOC pointer.
5514 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, TOCReg, TOCPtr, Glue);
5515 Chain = TOCVal.getValue(0);
5516 Glue = TOCVal.getValue(1);
5517
5518 // If the function call has an explicit 'nest' parameter, it takes the
5519 // place of the environment pointer.
5520 assert((!hasNest || !Subtarget.isAIXABI()) &&(((!hasNest || !Subtarget.isAIXABI()) && "Nest parameter is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5521, __PRETTY_FUNCTION__))
5521 "Nest parameter is not supported on AIX.")(((!hasNest || !Subtarget.isAIXABI()) && "Nest parameter is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5521, __PRETTY_FUNCTION__))
;
5522 if (!hasNest) {
5523 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, EnvPtrReg, LoadEnvPtr, Glue);
5524 Chain = EnvVal.getValue(0);
5525 Glue = EnvVal.getValue(1);
5526 }
5527
5528 // The rest of the indirect call sequence is the same as the non-descriptor
5529 // DAG.
5530 prepareIndirectCall(DAG, LoadFuncPtr, Glue, Chain, dl);
5531}
5532
5533static void
5534buildCallOperands(SmallVectorImpl<SDValue> &Ops,
5535 PPCTargetLowering::CallFlags CFlags, const SDLoc &dl,
5536 SelectionDAG &DAG,
5537 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
5538 SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff,
5539 const PPCSubtarget &Subtarget) {
5540 const bool IsPPC64 = Subtarget.isPPC64();
5541 // MVT for a general purpose register.
5542 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5543
5544 // First operand is always the chain.
5545 Ops.push_back(Chain);
5546
5547 // If it's a direct call pass the callee as the second operand.
5548 if (!CFlags.IsIndirect)
5549 Ops.push_back(Callee);
5550 else {
5551 assert(!CFlags.IsPatchPoint && "Patch point calls are not indirect.")((!CFlags.IsPatchPoint && "Patch point calls are not indirect."
) ? static_cast<void> (0) : __assert_fail ("!CFlags.IsPatchPoint && \"Patch point calls are not indirect.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5551, __PRETTY_FUNCTION__))
;
5552
5553 // For the TOC based ABIs, we have saved the TOC pointer to the linkage area
5554 // on the stack (this would have been done in `LowerCall_64SVR4` or
5555 // `LowerCall_AIX`). The call instruction is a pseudo instruction that
5556 // represents both the indirect branch and a load that restores the TOC
5557 // pointer from the linkage area. The operand for the TOC restore is an add
5558 // of the TOC save offset to the stack pointer. This must be the second
5559 // operand: after the chain input but before any other variadic arguments.
5560 // For 64-bit ELFv2 ABI with PCRel, do not restore the TOC as it is not
5561 // saved or used.
5562 if (isTOCSaveRestoreRequired(Subtarget)) {
5563 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister();
5564
5565 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5566 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5567 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5568 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5569 Ops.push_back(AddTOC);
5570 }
5571
5572 // Add the register used for the environment pointer.
5573 if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest)
5574 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(),
5575 RegVT));
5576
5577
5578 // Add CTR register as callee so a bctr can be emitted later.
5579 if (CFlags.IsTailCall)
5580 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5581 }
5582
5583 // If this is a tail call add stack pointer delta.
5584 if (CFlags.IsTailCall)
5585 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
5586
5587 // Add argument registers to the end of the list so that they are known live
5588 // into the call.
5589 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
5590 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5591 RegsToPass[i].second.getValueType()));
5592
5593 // We cannot add R2/X2 as an operand here for PATCHPOINT, because there is
5594 // no way to mark dependencies as implicit here.
5595 // We will add the R2/X2 dependency in EmitInstrWithCustomInserter.
5596 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) &&
5597 !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls())
5598 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT));
5599
5600 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
5601 if (CFlags.IsVarArg && Subtarget.is32BitELFABI())
5602 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5603
5604 // Add a register mask operand representing the call-preserved registers.
5605 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
5606 const uint32_t *Mask =
5607 TRI->getCallPreservedMask(DAG.getMachineFunction(), CFlags.CallConv);
5608 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5608, __PRETTY_FUNCTION__))
;
5609 Ops.push_back(DAG.getRegisterMask(Mask));
5610
5611 // If the glue is valid, it is the last operand.
5612 if (Glue.getNode())
5613 Ops.push_back(Glue);
5614}
5615
5616SDValue PPCTargetLowering::FinishCall(
5617 CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
5618 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue,
5619 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5620 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
5621 SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const {
5622
5623 if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) ||
5624 Subtarget.isAIXABI())
5625 setUsesTOCBasePtr(DAG);
5626
5627 unsigned CallOpc =
5628 getCallOpcode(CFlags, DAG.getMachineFunction().getFunction(), Callee,
5629 Subtarget, DAG.getTarget());
5630
5631 if (!CFlags.IsIndirect)
5632 Callee = transformCallee(Callee, DAG, dl, Subtarget);
5633 else if (Subtarget.usesFunctionDescriptors())
5634 prepareDescriptorIndirectCall(DAG, Callee, Glue, Chain, CallSeqStart, CB,
5635 dl, CFlags.HasNest, Subtarget);
5636 else
5637 prepareIndirectCall(DAG, Callee, Glue, Chain, dl);
5638
5639 // Build the operand list for the call instruction.
5640 SmallVector<SDValue, 8> Ops;
5641 buildCallOperands(Ops, CFlags, dl, DAG, RegsToPass, Glue, Chain, Callee,
5642 SPDiff, Subtarget);
5643
5644 // Emit tail call.
5645 if (CFlags.IsTailCall) {
5646 // Indirect tail call when using PC Relative calls do not have the same
5647 // constraints.
5648 assert(((Callee.getOpcode() == ISD::Register &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5656, __PRETTY_FUNCTION__))
5649 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5656, __PRETTY_FUNCTION__))
5650 Callee.getOpcode() == ISD::TargetExternalSymbol ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5656, __PRETTY_FUNCTION__))
5651 Callee.getOpcode() == ISD::TargetGlobalAddress ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5656, __PRETTY_FUNCTION__))
5652 isa<ConstantSDNode>(Callee) ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5656, __PRETTY_FUNCTION__))
5653 (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5656, __PRETTY_FUNCTION__))
5654 "Expecting a global address, external symbol, absolute value, "((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5656, __PRETTY_FUNCTION__))
5655 "register or an indirect tail call when PC Relative calls are "((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5656, __PRETTY_FUNCTION__))
5656 "used.")((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5656, __PRETTY_FUNCTION__))
;
5657 // PC Relative calls also use TC_RETURN as the way to mark tail calls.
5658 assert(CallOpc == PPCISD::TC_RETURN &&((CallOpc == PPCISD::TC_RETURN && "Unexpected call opcode for a tail call."
) ? static_cast<void> (0) : __assert_fail ("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5659, __PRETTY_FUNCTION__))
5659 "Unexpected call opcode for a tail call.")((CallOpc == PPCISD::TC_RETURN && "Unexpected call opcode for a tail call."
) ? static_cast<void> (0) : __assert_fail ("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5659, __PRETTY_FUNCTION__))
;
5660 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
5661 return DAG.getNode(CallOpc, dl, MVT::Other, Ops);
5662 }
5663
5664 std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}};
5665 Chain = DAG.getNode(CallOpc, dl, ReturnTypes, Ops);
5666 DAG.addNoMergeSiteInfo(Chain.getNode(), CFlags.NoMerge);
5667 Glue = Chain.getValue(1);
5668
5669 // When performing tail call optimization the callee pops its arguments off
5670 // the stack. Account for this here so these bytes can be pushed back on in
5671 // PPCFrameLowering::eliminateCallFramePseudoInstr.
5672 int BytesCalleePops = (CFlags.CallConv == CallingConv::Fast &&
5673 getTargetMachine().Options.GuaranteedTailCallOpt)
5674 ? NumBytes
5675 : 0;
5676
5677 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5678 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5679 Glue, dl);
5680 Glue = Chain.getValue(1);
5681
5682 return LowerCallResult(Chain, Glue, CFlags.CallConv, CFlags.IsVarArg, Ins, dl,
5683 DAG, InVals);
5684}
5685
5686SDValue
5687PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5688 SmallVectorImpl<SDValue> &InVals) const {
5689 SelectionDAG &DAG = CLI.DAG;
5690 SDLoc &dl = CLI.DL;
5691 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5692 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5693 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5694 SDValue Chain = CLI.Chain;
5695 SDValue Callee = CLI.Callee;
5696 bool &isTailCall = CLI.IsTailCall;
5697 CallingConv::ID CallConv = CLI.CallConv;
5698 bool isVarArg = CLI.IsVarArg;
5699 bool isPatchPoint = CLI.IsPatchPoint;
5700 const CallBase *CB = CLI.CB;
5701
5702 if (isTailCall) {
5703 if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall()))
5704 isTailCall = false;
5705 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5706 isTailCall = IsEligibleForTailCallOptimization_64SVR4(
5707 Callee, CallConv, CB, isVarArg, Outs, Ins, DAG);
5708 else
5709 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5710 Ins, DAG);
5711 if (isTailCall) {
5712 ++NumTailCalls;
5713 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5714 ++NumSiblingCalls;
5715
5716 // PC Relative calls no longer guarantee that the callee is a Global
5717 // Address Node. The callee could be an indirect tail call in which
5718 // case the SDValue for the callee could be a load (to load the address
5719 // of a function pointer) or it may be a register copy (to move the
5720 // address of the callee from a function parameter into a virtual
5721 // register). It may also be an ExternalSymbolSDNode (ex memcopy).
5722 assert((Subtarget.isUsingPCRelativeCalls() ||(((Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode
>(Callee)) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5724, __PRETTY_FUNCTION__))
5723 isa<GlobalAddressSDNode>(Callee)) &&(((Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode
>(Callee)) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5724, __PRETTY_FUNCTION__))
5724 "Callee should be an llvm::Function object.")(((Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode
>(Callee)) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5724, __PRETTY_FUNCTION__))
;
5725
5726 LLVM_DEBUG(dbgs() << "TCO caller: " << DAG.getMachineFunction().getName()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
5727 << "\nTCO callee: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
;
5728 LLVM_DEBUG(Callee.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { Callee.dump(); } } while (false)
;
5729 }
5730 }
5731
5732 if (!isTailCall && CB && CB->isMustTailCall())
5733 report_fatal_error("failed to perform tail call elimination on a call "
5734 "site marked musttail");
5735
5736 // When long calls (i.e. indirect calls) are always used, calls are always
5737 // made via function pointer. If we have a function name, first translate it
5738 // into a pointer.
5739 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5740 !isTailCall)
5741 Callee = LowerGlobalAddress(Callee, DAG);
5742
5743 CallFlags CFlags(
5744 CallConv, isTailCall, isVarArg, isPatchPoint,
5745 isIndirectCall(Callee, DAG, Subtarget, isPatchPoint),
5746 // hasNest
5747 Subtarget.is64BitELFABI() &&
5748 any_of(Outs, [](ISD::OutputArg Arg) { return Arg.Flags.isNest(); }),
5749 CLI.NoMerge);
5750
5751 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5752 return LowerCall_64SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5753 InVals, CB);
5754
5755 if (Subtarget.isSVR4ABI())
5756 return LowerCall_32SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5757 InVals, CB);
5758
5759 if (Subtarget.isAIXABI())
5760 return LowerCall_AIX(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5761 InVals, CB);
5762
5763 return LowerCall_Darwin(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5764 InVals, CB);
5765}
5766
5767SDValue PPCTargetLowering::LowerCall_32SVR4(
5768 SDValue Chain, SDValue Callee, CallFlags CFlags,
5769 const SmallVectorImpl<ISD::OutputArg> &Outs,
5770 const SmallVectorImpl<SDValue> &OutVals,
5771 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5772 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5773 const CallBase *CB) const {
5774 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5775 // of the 32-bit SVR4 ABI stack frame layout.
5776
5777 const CallingConv::ID CallConv = CFlags.CallConv;
5778 const bool IsVarArg = CFlags.IsVarArg;
5779 const bool IsTailCall = CFlags.IsTailCall;
5780
5781 assert((CallConv == CallingConv::C ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5783, __PRETTY_FUNCTION__))
5782 CallConv == CallingConv::Cold ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5783, __PRETTY_FUNCTION__))
5783 CallConv == CallingConv::Fast) && "Unknown calling convention!")(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5783, __PRETTY_FUNCTION__))
;
5784
5785 const Align PtrAlign(4);
5786
5787 MachineFunction &MF = DAG.getMachineFunction();
5788
5789 // Mark this function as potentially containing a function that contains a
5790 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5791 // and restoring the callers stack pointer in this functions epilog. This is
5792 // done because by tail calling the called function might overwrite the value
5793 // in this function's (MF) stack pointer stack slot 0(SP).
5794 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5795 CallConv == CallingConv::Fast)
5796 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5797
5798 // Count how many bytes are to be pushed on the stack, including the linkage
5799 // area, parameter list area and the part of the local variable space which
5800 // contains copies of aggregates which are passed by value.
5801
5802 // Assign locations to all of the outgoing arguments.
5803 SmallVector<CCValAssign, 16> ArgLocs;
5804 PPCCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
5805
5806 // Reserve space for the linkage area on the stack.
5807 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5808 PtrAlign);
5809 if (useSoftFloat())
5810 CCInfo.PreAnalyzeCallOperands(Outs);
5811
5812 if (IsVarArg) {
5813 // Handle fixed and variable vector arguments differently.
5814 // Fixed vector arguments go into registers as long as registers are
5815 // available. Variable vector arguments always go into memory.
5816 unsigned NumArgs = Outs.size();
5817
5818 for (unsigned i = 0; i != NumArgs; ++i) {
5819 MVT ArgVT = Outs[i].VT;
5820 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5821 bool Result;
5822
5823 if (Outs[i].IsFixed) {
5824 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5825 CCInfo);
5826 } else {
5827 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
5828 ArgFlags, CCInfo);
5829 }
5830
5831 if (Result) {
5832#ifndef NDEBUG
5833 errs() << "Call operand #" << i << " has unhandled type "
5834 << EVT(ArgVT).getEVTString() << "\n";
5835#endif
5836 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5836)
;
5837 }
5838 }
5839 } else {
5840 // All arguments are treated the same.
5841 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
5842 }
5843 CCInfo.clearWasPPCF128();
5844
5845 // Assign locations to all of the outgoing aggregate by value arguments.
5846 SmallVector<CCValAssign, 16> ByValArgLocs;
5847 CCState CCByValInfo(CallConv, IsVarArg, MF, ByValArgLocs, *DAG.getContext());
5848
5849 // Reserve stack space for the allocations in CCInfo.
5850 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrAlign);
5851
5852 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
5853
5854 // Size of the linkage area, parameter list area and the part of the local
5855 // space variable where copies of aggregates which are passed by value are