Bug Summary

File:llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Warning:line 9657, column 31
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/lib/Target/PowerPC -resource-dir /usr/lib/llvm-13/lib/clang/13.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/include -I /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/lib/llvm-13/lib/clang/13.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/build-llvm/lib/Target/PowerPC -fdebug-prefix-map=/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-04-14-063029-18377-1 -x c++ /build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
14#include "MCTargetDesc/PPCPredicates.h"
15#include "PPC.h"
16#include "PPCCCState.h"
17#include "PPCCallingConv.h"
18#include "PPCFrameLowering.h"
19#include "PPCInstrInfo.h"
20#include "PPCMachineFunctionInfo.h"
21#include "PPCPerfectShuffle.h"
22#include "PPCRegisterInfo.h"
23#include "PPCSubtarget.h"
24#include "PPCTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/None.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
36#include "llvm/ADT/StringSwitch.h"
37#include "llvm/CodeGen/CallingConvLower.h"
38#include "llvm/CodeGen/ISDOpcodes.h"
39#include "llvm/CodeGen/MachineBasicBlock.h"
40#include "llvm/CodeGen/MachineFrameInfo.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineInstr.h"
43#include "llvm/CodeGen/MachineInstrBuilder.h"
44#include "llvm/CodeGen/MachineJumpTableInfo.h"
45#include "llvm/CodeGen/MachineLoopInfo.h"
46#include "llvm/CodeGen/MachineMemOperand.h"
47#include "llvm/CodeGen/MachineModuleInfo.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/RuntimeLibcalls.h"
51#include "llvm/CodeGen/SelectionDAG.h"
52#include "llvm/CodeGen/SelectionDAGNodes.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetLowering.h"
55#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
56#include "llvm/CodeGen/TargetRegisterInfo.h"
57#include "llvm/CodeGen/ValueTypes.h"
58#include "llvm/IR/CallingConv.h"
59#include "llvm/IR/Constant.h"
60#include "llvm/IR/Constants.h"
61#include "llvm/IR/DataLayout.h"
62#include "llvm/IR/DebugLoc.h"
63#include "llvm/IR/DerivedTypes.h"
64#include "llvm/IR/Function.h"
65#include "llvm/IR/GlobalValue.h"
66#include "llvm/IR/IRBuilder.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/Intrinsics.h"
69#include "llvm/IR/IntrinsicsPowerPC.h"
70#include "llvm/IR/Module.h"
71#include "llvm/IR/Type.h"
72#include "llvm/IR/Use.h"
73#include "llvm/IR/Value.h"
74#include "llvm/MC/MCContext.h"
75#include "llvm/MC/MCExpr.h"
76#include "llvm/MC/MCRegisterInfo.h"
77#include "llvm/MC/MCSectionXCOFF.h"
78#include "llvm/MC/MCSymbolXCOFF.h"
79#include "llvm/Support/AtomicOrdering.h"
80#include "llvm/Support/BranchProbability.h"
81#include "llvm/Support/Casting.h"
82#include "llvm/Support/CodeGen.h"
83#include "llvm/Support/CommandLine.h"
84#include "llvm/Support/Compiler.h"
85#include "llvm/Support/Debug.h"
86#include "llvm/Support/ErrorHandling.h"
87#include "llvm/Support/Format.h"
88#include "llvm/Support/KnownBits.h"
89#include "llvm/Support/MachineValueType.h"
90#include "llvm/Support/MathExtras.h"
91#include "llvm/Support/raw_ostream.h"
92#include "llvm/Target/TargetMachine.h"
93#include "llvm/Target/TargetOptions.h"
94#include <algorithm>
95#include <cassert>
96#include <cstdint>
97#include <iterator>
98#include <list>
99#include <utility>
100#include <vector>
101
102using namespace llvm;
103
104#define DEBUG_TYPE"ppc-lowering" "ppc-lowering"
105
106static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
107cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
108
109static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
110cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
111
112static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
113cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
114
115static cl::opt<bool> DisableSCO("disable-ppc-sco",
116cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
117
118static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
119cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
120
121static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
122cl::desc("use absolute jump tables on ppc"), cl::Hidden);
123
124// TODO - Remove this option if soft fp128 has been fully supported .
125static cl::opt<bool>
126 EnableSoftFP128("enable-soft-fp128",
127 cl::desc("temp option to enable soft fp128"), cl::Hidden);
128
129STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"ppc-lowering", "NumTailCalls"
, "Number of tail calls"}
;
130STATISTIC(NumSiblingCalls, "Number of sibling calls")static llvm::Statistic NumSiblingCalls = {"ppc-lowering", "NumSiblingCalls"
, "Number of sibling calls"}
;
131STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM")static llvm::Statistic ShufflesHandledWithVPERM = {"ppc-lowering"
, "ShufflesHandledWithVPERM", "Number of shuffles lowered to a VPERM"
}
;
132STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed")static llvm::Statistic NumDynamicAllocaProbed = {"ppc-lowering"
, "NumDynamicAllocaProbed", "Number of dynamic stack allocation probed"
}
;
133
134static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
135
136static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
137
138// FIXME: Remove this once the bug has been fixed!
139extern cl::opt<bool> ANDIGlueBug;
140
141PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
142 const PPCSubtarget &STI)
143 : TargetLowering(TM), Subtarget(STI) {
144 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
145 // arguments are at least 4/8 bytes aligned.
146 bool isPPC64 = Subtarget.isPPC64();
147 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
148
149 // Set up the register classes.
150 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
151 if (!useSoftFloat()) {
152 if (hasSPE()) {
153 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
154 // EFPU2 APU only supports f32
155 if (!Subtarget.hasEFPU2())
156 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
157 } else {
158 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
159 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
160 }
161 }
162
163 // Match BITREVERSE to customized fast code sequence in the td file.
164 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
165 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
166
167 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
168 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
169
170 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
171 for (MVT VT : MVT::integer_valuetypes()) {
172 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
173 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
174 }
175
176 if (Subtarget.isISA3_0()) {
177 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
178 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
179 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
180 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
181 } else {
182 // No extending loads from f16 or HW conversions back and forth.
183 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
184 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
185 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
186 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
187 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
188 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
189 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
190 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
191 }
192
193 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
194
195 // PowerPC has pre-inc load and store's.
196 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
197 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
198 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
199 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
200 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
201 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
202 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
203 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
204 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
205 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
206 if (!Subtarget.hasSPE()) {
207 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
208 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
209 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
210 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
211 }
212
213 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
214 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
215 for (MVT VT : ScalarIntVTs) {
216 setOperationAction(ISD::ADDC, VT, Legal);
217 setOperationAction(ISD::ADDE, VT, Legal);
218 setOperationAction(ISD::SUBC, VT, Legal);
219 setOperationAction(ISD::SUBE, VT, Legal);
220 }
221
222 if (Subtarget.useCRBits()) {
223 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
224
225 if (isPPC64 || Subtarget.hasFPCVT()) {
226 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Promote);
227 AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1,
228 isPPC64 ? MVT::i64 : MVT::i32);
229 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Promote);
230 AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1,
231 isPPC64 ? MVT::i64 : MVT::i32);
232
233 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
234 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
235 isPPC64 ? MVT::i64 : MVT::i32);
236 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
237 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
238 isPPC64 ? MVT::i64 : MVT::i32);
239
240 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i1, Promote);
241 AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1,
242 isPPC64 ? MVT::i64 : MVT::i32);
243 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i1, Promote);
244 AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1,
245 isPPC64 ? MVT::i64 : MVT::i32);
246
247 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
248 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1,
249 isPPC64 ? MVT::i64 : MVT::i32);
250 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
251 AddPromotedToType(ISD::FP_TO_UINT, MVT::i1,
252 isPPC64 ? MVT::i64 : MVT::i32);
253 } else {
254 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom);
255 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom);
256 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
258 }
259
260 // PowerPC does not support direct load/store of condition registers.
261 setOperationAction(ISD::LOAD, MVT::i1, Custom);
262 setOperationAction(ISD::STORE, MVT::i1, Custom);
263
264 // FIXME: Remove this once the ANDI glue bug is fixed:
265 if (ANDIGlueBug)
266 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
267
268 for (MVT VT : MVT::integer_valuetypes()) {
269 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
270 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
271 setTruncStoreAction(VT, MVT::i1, Expand);
272 }
273
274 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
275 }
276
277 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
278 // PPC (the libcall is not available).
279 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
280 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
281 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::ppcf128, Custom);
282 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::ppcf128, Custom);
283
284 // We do not currently implement these libm ops for PowerPC.
285 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
286 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
287 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
288 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
289 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
290 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
291
292 // PowerPC has no SREM/UREM instructions unless we are on P9
293 // On P9 we may use a hardware instruction to compute the remainder.
294 // When the result of both the remainder and the division is required it is
295 // more efficient to compute the remainder from the result of the division
296 // rather than use the remainder instruction. The instructions are legalized
297 // directly because the DivRemPairsPass performs the transformation at the IR
298 // level.
299 if (Subtarget.isISA3_0()) {
300 setOperationAction(ISD::SREM, MVT::i32, Legal);
301 setOperationAction(ISD::UREM, MVT::i32, Legal);
302 setOperationAction(ISD::SREM, MVT::i64, Legal);
303 setOperationAction(ISD::UREM, MVT::i64, Legal);
304 } else {
305 setOperationAction(ISD::SREM, MVT::i32, Expand);
306 setOperationAction(ISD::UREM, MVT::i32, Expand);
307 setOperationAction(ISD::SREM, MVT::i64, Expand);
308 setOperationAction(ISD::UREM, MVT::i64, Expand);
309 }
310
311 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
312 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
313 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
314 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
315 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
316 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
317 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
318 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
319 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
320
321 // Handle constrained floating-point operations of scalar.
322 // TODO: Handle SPE specific operation.
323 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
324 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
325 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
326 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
327 setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal);
328 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
329
330 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
331 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
332 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
333 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
334 setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal);
335 if (Subtarget.hasVSX()) {
336 setOperationAction(ISD::STRICT_FRINT, MVT::f32, Legal);
337 setOperationAction(ISD::STRICT_FRINT, MVT::f64, Legal);
338 }
339
340 if (Subtarget.hasFSQRT()) {
341 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
342 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
343 }
344
345 if (Subtarget.hasFPRND()) {
346 setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal);
347 setOperationAction(ISD::STRICT_FCEIL, MVT::f32, Legal);
348 setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal);
349 setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal);
350
351 setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal);
352 setOperationAction(ISD::STRICT_FCEIL, MVT::f64, Legal);
353 setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal);
354 setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal);
355 }
356
357 // We don't support sin/cos/sqrt/fmod/pow
358 setOperationAction(ISD::FSIN , MVT::f64, Expand);
359 setOperationAction(ISD::FCOS , MVT::f64, Expand);
360 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
361 setOperationAction(ISD::FREM , MVT::f64, Expand);
362 setOperationAction(ISD::FPOW , MVT::f64, Expand);
363 setOperationAction(ISD::FSIN , MVT::f32, Expand);
364 setOperationAction(ISD::FCOS , MVT::f32, Expand);
365 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
366 setOperationAction(ISD::FREM , MVT::f32, Expand);
367 setOperationAction(ISD::FPOW , MVT::f32, Expand);
368 if (Subtarget.hasSPE()) {
369 setOperationAction(ISD::FMA , MVT::f64, Expand);
370 setOperationAction(ISD::FMA , MVT::f32, Expand);
371 } else {
372 setOperationAction(ISD::FMA , MVT::f64, Legal);
373 setOperationAction(ISD::FMA , MVT::f32, Legal);
374 }
375
376 if (Subtarget.hasSPE())
377 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
378
379 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
380
381 // If we're enabling GP optimizations, use hardware square root
382 if (!Subtarget.hasFSQRT() &&
383 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
384 Subtarget.hasFRE()))
385 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
386
387 if (!Subtarget.hasFSQRT() &&
388 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
389 Subtarget.hasFRES()))
390 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
391
392 if (Subtarget.hasFCPSGN()) {
393 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
394 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
395 } else {
396 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
397 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
398 }
399
400 if (Subtarget.hasFPRND()) {
401 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
402 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
403 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
404 setOperationAction(ISD::FROUND, MVT::f64, Legal);
405
406 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
407 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
408 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
409 setOperationAction(ISD::FROUND, MVT::f32, Legal);
410 }
411
412 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
413 // to speed up scalar BSWAP64.
414 // CTPOP or CTTZ were introduced in P8/P9 respectively
415 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
416 if (Subtarget.hasP9Vector())
417 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
418 else
419 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
420 if (Subtarget.isISA3_0()) {
421 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
422 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
423 } else {
424 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
425 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
426 }
427
428 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
429 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
430 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
431 } else {
432 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
433 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
434 }
435
436 // PowerPC does not have ROTR
437 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
438 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
439
440 if (!Subtarget.useCRBits()) {
441 // PowerPC does not have Select
442 setOperationAction(ISD::SELECT, MVT::i32, Expand);
443 setOperationAction(ISD::SELECT, MVT::i64, Expand);
444 setOperationAction(ISD::SELECT, MVT::f32, Expand);
445 setOperationAction(ISD::SELECT, MVT::f64, Expand);
446 }
447
448 // PowerPC wants to turn select_cc of FP into fsel when possible.
449 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
450 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
451
452 // PowerPC wants to optimize integer setcc a bit
453 if (!Subtarget.useCRBits())
454 setOperationAction(ISD::SETCC, MVT::i32, Custom);
455
456 if (Subtarget.hasFPU()) {
457 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal);
458 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal);
459 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal);
460
461 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
462 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
463 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal);
464 }
465
466 // PowerPC does not have BRCOND which requires SetCC
467 if (!Subtarget.useCRBits())
468 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
469
470 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
471
472 if (Subtarget.hasSPE()) {
473 // SPE has built-in conversions
474 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal);
475 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Legal);
476 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Legal);
477 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
478 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
479 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
480 } else {
481 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
482 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
483 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
484
485 // PowerPC does not have [U|S]INT_TO_FP
486 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Expand);
487 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Expand);
488 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
489 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
490 }
491
492 if (Subtarget.hasDirectMove() && isPPC64) {
493 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
494 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
495 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
496 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
497 if (TM.Options.UnsafeFPMath) {
498 setOperationAction(ISD::LRINT, MVT::f64, Legal);
499 setOperationAction(ISD::LRINT, MVT::f32, Legal);
500 setOperationAction(ISD::LLRINT, MVT::f64, Legal);
501 setOperationAction(ISD::LLRINT, MVT::f32, Legal);
502 setOperationAction(ISD::LROUND, MVT::f64, Legal);
503 setOperationAction(ISD::LROUND, MVT::f32, Legal);
504 setOperationAction(ISD::LLROUND, MVT::f64, Legal);
505 setOperationAction(ISD::LLROUND, MVT::f32, Legal);
506 }
507 } else {
508 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
509 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
510 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
511 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
512 }
513
514 // We cannot sextinreg(i1). Expand to shifts.
515 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
516
517 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
518 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
519 // support continuation, user-level threading, and etc.. As a result, no
520 // other SjLj exception interfaces are implemented and please don't build
521 // your own exception handling based on them.
522 // LLVM/Clang supports zero-cost DWARF exception handling.
523 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
524 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
525
526 // We want to legalize GlobalAddress and ConstantPool nodes into the
527 // appropriate instructions to materialize the address.
528 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
529 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
530 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
531 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
532 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
533 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
534 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
535 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
536 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
537 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
538
539 // TRAP is legal.
540 setOperationAction(ISD::TRAP, MVT::Other, Legal);
541
542 // TRAMPOLINE is custom lowered.
543 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
544 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
545
546 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
547 setOperationAction(ISD::VASTART , MVT::Other, Custom);
548
549 if (Subtarget.is64BitELFABI()) {
550 // VAARG always uses double-word chunks, so promote anything smaller.
551 setOperationAction(ISD::VAARG, MVT::i1, Promote);
552 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
553 setOperationAction(ISD::VAARG, MVT::i8, Promote);
554 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
555 setOperationAction(ISD::VAARG, MVT::i16, Promote);
556 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
557 setOperationAction(ISD::VAARG, MVT::i32, Promote);
558 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
559 setOperationAction(ISD::VAARG, MVT::Other, Expand);
560 } else if (Subtarget.is32BitELFABI()) {
561 // VAARG is custom lowered with the 32-bit SVR4 ABI.
562 setOperationAction(ISD::VAARG, MVT::Other, Custom);
563 setOperationAction(ISD::VAARG, MVT::i64, Custom);
564 } else
565 setOperationAction(ISD::VAARG, MVT::Other, Expand);
566
567 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
568 if (Subtarget.is32BitELFABI())
569 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
570 else
571 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
572
573 // Use the default implementation.
574 setOperationAction(ISD::VAEND , MVT::Other, Expand);
575 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
576 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
577 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
578 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
579 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
580 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
581 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
582 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
583
584 // We want to custom lower some of our intrinsics.
585 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
586
587 // To handle counter-based loop conditions.
588 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
589
590 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
591 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
592 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
593 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
594
595 // Comparisons that require checking two conditions.
596 if (Subtarget.hasSPE()) {
597 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
598 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
599 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
600 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
601 }
602 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
603 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
604 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
605 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
606 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
607 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
608 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
609 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
610 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
611 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
612 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
613 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
614
615 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
616 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
617
618 if (Subtarget.has64BitSupport()) {
619 // They also have instructions for converting between i64 and fp.
620 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
621 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand);
622 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
623 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand);
624 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
625 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
626 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
627 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
628 // This is just the low 32 bits of a (signed) fp->i64 conversion.
629 // We cannot do this with Promote because i64 is not a legal type.
630 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
631 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
632
633 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
634 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
635 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
636 }
637 } else {
638 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
639 if (Subtarget.hasSPE()) {
640 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal);
641 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
642 } else {
643 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand);
644 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
645 }
646 }
647
648 // With the instructions enabled under FPCVT, we can do everything.
649 if (Subtarget.hasFPCVT()) {
650 if (Subtarget.has64BitSupport()) {
651 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
652 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
653 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
654 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
655 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
656 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
657 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
658 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
659 }
660
661 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
662 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
663 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
664 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
665 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
666 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
667 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
668 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
669 }
670
671 if (Subtarget.use64BitRegs()) {
672 // 64-bit PowerPC implementations can support i64 types directly
673 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
674 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
675 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
676 // 64-bit PowerPC wants to expand i128 shifts itself.
677 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
678 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
679 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
680 } else {
681 // 32-bit PowerPC wants to expand i64 shifts itself.
682 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
683 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
684 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
685 }
686
687 // PowerPC has better expansions for funnel shifts than the generic
688 // TargetLowering::expandFunnelShift.
689 if (Subtarget.has64BitSupport()) {
690 setOperationAction(ISD::FSHL, MVT::i64, Custom);
691 setOperationAction(ISD::FSHR, MVT::i64, Custom);
692 }
693 setOperationAction(ISD::FSHL, MVT::i32, Custom);
694 setOperationAction(ISD::FSHR, MVT::i32, Custom);
695
696 if (Subtarget.hasVSX()) {
697 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
698 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
699 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
700 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
701 }
702
703 if (Subtarget.hasAltivec()) {
704 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
705 setOperationAction(ISD::SADDSAT, VT, Legal);
706 setOperationAction(ISD::SSUBSAT, VT, Legal);
707 setOperationAction(ISD::UADDSAT, VT, Legal);
708 setOperationAction(ISD::USUBSAT, VT, Legal);
709 }
710 // First set operation action for all vector types to expand. Then we
711 // will selectively turn on ones that can be effectively codegen'd.
712 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
713 // add/sub are legal for all supported vector VT's.
714 setOperationAction(ISD::ADD, VT, Legal);
715 setOperationAction(ISD::SUB, VT, Legal);
716
717 // For v2i64, these are only valid with P8Vector. This is corrected after
718 // the loop.
719 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
720 setOperationAction(ISD::SMAX, VT, Legal);
721 setOperationAction(ISD::SMIN, VT, Legal);
722 setOperationAction(ISD::UMAX, VT, Legal);
723 setOperationAction(ISD::UMIN, VT, Legal);
724 }
725 else {
726 setOperationAction(ISD::SMAX, VT, Expand);
727 setOperationAction(ISD::SMIN, VT, Expand);
728 setOperationAction(ISD::UMAX, VT, Expand);
729 setOperationAction(ISD::UMIN, VT, Expand);
730 }
731
732 if (Subtarget.hasVSX()) {
733 setOperationAction(ISD::FMAXNUM, VT, Legal);
734 setOperationAction(ISD::FMINNUM, VT, Legal);
735 }
736
737 // Vector instructions introduced in P8
738 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
739 setOperationAction(ISD::CTPOP, VT, Legal);
740 setOperationAction(ISD::CTLZ, VT, Legal);
741 }
742 else {
743 setOperationAction(ISD::CTPOP, VT, Expand);
744 setOperationAction(ISD::CTLZ, VT, Expand);
745 }
746
747 // Vector instructions introduced in P9
748 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
749 setOperationAction(ISD::CTTZ, VT, Legal);
750 else
751 setOperationAction(ISD::CTTZ, VT, Expand);
752
753 // We promote all shuffles to v16i8.
754 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
755 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
756
757 // We promote all non-typed operations to v4i32.
758 setOperationAction(ISD::AND , VT, Promote);
759 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
760 setOperationAction(ISD::OR , VT, Promote);
761 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
762 setOperationAction(ISD::XOR , VT, Promote);
763 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
764 setOperationAction(ISD::LOAD , VT, Promote);
765 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
766 setOperationAction(ISD::SELECT, VT, Promote);
767 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
768 setOperationAction(ISD::VSELECT, VT, Legal);
769 setOperationAction(ISD::SELECT_CC, VT, Promote);
770 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
771 setOperationAction(ISD::STORE, VT, Promote);
772 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
773
774 // No other operations are legal.
775 setOperationAction(ISD::MUL , VT, Expand);
776 setOperationAction(ISD::SDIV, VT, Expand);
777 setOperationAction(ISD::SREM, VT, Expand);
778 setOperationAction(ISD::UDIV, VT, Expand);
779 setOperationAction(ISD::UREM, VT, Expand);
780 setOperationAction(ISD::FDIV, VT, Expand);
781 setOperationAction(ISD::FREM, VT, Expand);
782 setOperationAction(ISD::FNEG, VT, Expand);
783 setOperationAction(ISD::FSQRT, VT, Expand);
784 setOperationAction(ISD::FLOG, VT, Expand);
785 setOperationAction(ISD::FLOG10, VT, Expand);
786 setOperationAction(ISD::FLOG2, VT, Expand);
787 setOperationAction(ISD::FEXP, VT, Expand);
788 setOperationAction(ISD::FEXP2, VT, Expand);
789 setOperationAction(ISD::FSIN, VT, Expand);
790 setOperationAction(ISD::FCOS, VT, Expand);
791 setOperationAction(ISD::FABS, VT, Expand);
792 setOperationAction(ISD::FFLOOR, VT, Expand);
793 setOperationAction(ISD::FCEIL, VT, Expand);
794 setOperationAction(ISD::FTRUNC, VT, Expand);
795 setOperationAction(ISD::FRINT, VT, Expand);
796 setOperationAction(ISD::FNEARBYINT, VT, Expand);
797 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
798 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
799 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
800 setOperationAction(ISD::MULHU, VT, Expand);
801 setOperationAction(ISD::MULHS, VT, Expand);
802 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
803 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
804 setOperationAction(ISD::UDIVREM, VT, Expand);
805 setOperationAction(ISD::SDIVREM, VT, Expand);
806 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
807 setOperationAction(ISD::FPOW, VT, Expand);
808 setOperationAction(ISD::BSWAP, VT, Expand);
809 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
810 setOperationAction(ISD::ROTL, VT, Expand);
811 setOperationAction(ISD::ROTR, VT, Expand);
812
813 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
814 setTruncStoreAction(VT, InnerVT, Expand);
815 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
816 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
817 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
818 }
819 }
820 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand);
821 if (!Subtarget.hasP8Vector()) {
822 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
823 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
824 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
825 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
826 }
827
828 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
829 // with merges, splats, etc.
830 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
831
832 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
833 // are cheap, so handle them before they get expanded to scalar.
834 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
835 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
836 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
837 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
838 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
839
840 setOperationAction(ISD::AND , MVT::v4i32, Legal);
841 setOperationAction(ISD::OR , MVT::v4i32, Legal);
842 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
843 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
844 setOperationAction(ISD::SELECT, MVT::v4i32,
845 Subtarget.useCRBits() ? Legal : Expand);
846 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
847 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
848 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
849 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
850 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
851 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
852 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
853 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
854 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
855 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
856 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
857 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
858 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
859
860 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
861 setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
862 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
863 if (Subtarget.hasAltivec())
864 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
865 setOperationAction(ISD::ROTL, VT, Legal);
866 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
867 if (Subtarget.hasP8Altivec())
868 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
869
870 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
871 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
872 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
873 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
874
875 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
876 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
877
878 if (Subtarget.hasVSX()) {
879 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
880 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
881 }
882
883 if (Subtarget.hasP8Altivec())
884 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
885 else
886 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
887
888 if (Subtarget.isISA3_1()) {
889 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
890 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
891 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
892 setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
893 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
894 setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
895 setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
896 setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
897 setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
898 setOperationAction(ISD::UREM, MVT::v2i64, Legal);
899 setOperationAction(ISD::SREM, MVT::v2i64, Legal);
900 setOperationAction(ISD::UREM, MVT::v4i32, Legal);
901 setOperationAction(ISD::SREM, MVT::v4i32, Legal);
902 setOperationAction(ISD::UREM, MVT::v1i128, Legal);
903 setOperationAction(ISD::SREM, MVT::v1i128, Legal);
904 setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
905 setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
906 setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
907 }
908
909 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
910 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
911
912 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
913 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
914
915 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
916 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
917 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
918 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
919
920 // Altivec does not contain unordered floating-point compare instructions
921 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
922 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
923 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
924 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
925
926 if (Subtarget.hasVSX()) {
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
928 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
929 if (Subtarget.hasP8Vector()) {
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
931 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
932 }
933 if (Subtarget.hasDirectMove() && isPPC64) {
934 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
935 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
936 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
937 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
938 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
939 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
940 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
942 }
943 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
944
945 // The nearbyint variants are not allowed to raise the inexact exception
946 // so we can only code-gen them with unsafe math.
947 if (TM.Options.UnsafeFPMath) {
948 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
949 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
950 }
951
952 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
953 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
954 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
955 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
956 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
957 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
958 setOperationAction(ISD::FROUND, MVT::f64, Legal);
959 setOperationAction(ISD::FRINT, MVT::f64, Legal);
960
961 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
962 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
963 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
964 setOperationAction(ISD::FROUND, MVT::f32, Legal);
965 setOperationAction(ISD::FRINT, MVT::f32, Legal);
966
967 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
968 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
969
970 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
971 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
972
973 // Share the Altivec comparison restrictions.
974 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
975 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
976 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
977 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
978
979 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
980 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
981
982 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
983
984 if (Subtarget.hasP8Vector())
985 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
986
987 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
988
989 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
990 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
991 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
992
993 if (Subtarget.hasP8Altivec()) {
994 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
995 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
996 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
997
998 // 128 bit shifts can be accomplished via 3 instructions for SHL and
999 // SRL, but not for SRA because of the instructions available:
1000 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
1001 // doing
1002 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
1003 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
1004 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1005
1006 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
1007 }
1008 else {
1009 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1010 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
1011 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
1012
1013 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1014
1015 // VSX v2i64 only supports non-arithmetic operations.
1016 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
1017 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
1018 }
1019
1020 if (Subtarget.isISA3_1())
1021 setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
1022 else
1023 setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
1024
1025 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
1026 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
1027 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
1028 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
1029
1030 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
1031
1032 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
1033 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
1034 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
1035 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
1036 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1037 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1038 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1039 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1040
1041 // Custom handling for partial vectors of integers converted to
1042 // floating point. We already have optimal handling for v2i32 through
1043 // the DAG combine, so those aren't necessary.
1044 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom);
1045 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom);
1046 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
1047 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
1048 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom);
1049 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom);
1050 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
1051 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
1052 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
1053 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1054 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
1055 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1056 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom);
1057 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
1058 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
1059 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
1060
1061 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1062 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1063 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
1064 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1065 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
1066 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
1067
1068 if (Subtarget.hasDirectMove())
1069 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1070 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1071
1072 // Handle constrained floating-point operations of vector.
1073 // The predictor is `hasVSX` because altivec instruction has
1074 // no exception but VSX vector instruction has.
1075 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
1076 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
1077 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
1078 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
1079 setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal);
1080 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
1081 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v4f32, Legal);
1082 setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal);
1083 setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal);
1084 setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
1085 setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal);
1086 setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
1087 setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
1088
1089 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
1090 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
1091 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
1092 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
1093 setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal);
1094 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1095 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v2f64, Legal);
1096 setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal);
1097 setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal);
1098 setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
1099 setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal);
1100 setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
1101 setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
1102
1103 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1104 }
1105
1106 if (Subtarget.hasP8Altivec()) {
1107 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
1108 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
1109 }
1110
1111 if (Subtarget.hasP9Vector()) {
1112 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1113 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1114
1115 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1116 // SRL, but not for SRA because of the instructions available:
1117 // VS{RL} and VS{RL}O.
1118 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1119 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
1120 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1121
1122 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1123 setOperationAction(ISD::FADD, MVT::f128, Legal);
1124 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1125 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1126 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1127 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1128 // No extending loads to f128 on PPC.
1129 for (MVT FPT : MVT::fp_valuetypes())
1130 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1131 setOperationAction(ISD::FMA, MVT::f128, Legal);
1132 setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
1133 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
1134 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
1135 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
1136 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
1137 setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
1138
1139 setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
1140 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1141 setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
1142 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1143 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
1144 setOperationAction(ISD::FROUND, MVT::f128, Legal);
1145
1146 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1147 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1148 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
1149 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1150 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1151 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
1152 // No implementation for these ops for PowerPC.
1153 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1154 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1155 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1156 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
1157 setOperationAction(ISD::FREM, MVT::f128, Expand);
1158
1159 // Handle constrained floating-point operations of fp128
1160 setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
1161 setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
1162 setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
1163 setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
1164 setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
1165 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
1166 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
1167 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
1168 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
1169 setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
1170 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
1171 setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
1172 setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
1173 setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
1174 setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
1175 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1176 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1177 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1178 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
1179 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
1180 } else if (Subtarget.hasAltivec() && EnableSoftFP128) {
1181 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1182
1183 for (MVT FPT : MVT::fp_valuetypes())
1184 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1185
1186 setOperationAction(ISD::LOAD, MVT::f128, Promote);
1187 setOperationAction(ISD::STORE, MVT::f128, Promote);
1188
1189 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
1190 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
1191
1192 // Set FADD/FSUB as libcall to avoid the legalizer to expand the
1193 // fp_to_uint and int_to_fp.
1194 setOperationAction(ISD::FADD, MVT::f128, LibCall);
1195 setOperationAction(ISD::FSUB, MVT::f128, LibCall);
1196
1197 setOperationAction(ISD::FMUL, MVT::f128, Expand);
1198 setOperationAction(ISD::FDIV, MVT::f128, Expand);
1199 setOperationAction(ISD::FNEG, MVT::f128, Expand);
1200 setOperationAction(ISD::FABS, MVT::f128, Expand);
1201 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1202 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1203 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1204 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
1205 setOperationAction(ISD::FREM, MVT::f128, Expand);
1206 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
1207 setOperationAction(ISD::FMA, MVT::f128, Expand);
1208 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1209
1210 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1211 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1212
1213 // Expand the fp_extend if the target type is fp128.
1214 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
1215 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Expand);
1216
1217 // Expand the fp_round if the source type is fp128.
1218 for (MVT VT : {MVT::f32, MVT::f64}) {
1219 setOperationAction(ISD::FP_ROUND, VT, Custom);
1220 setOperationAction(ISD::STRICT_FP_ROUND, VT, Custom);
1221 }
1222
1223 setOperationAction(ISD::SETCC, MVT::f128, Custom);
1224 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Custom);
1225 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom);
1226 setOperationAction(ISD::BR_CC, MVT::f128, Expand);
1227
1228 // Lower following f128 select_cc pattern:
1229 // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv, NE
1230 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1231
1232 // We need to handle f128 SELECT_CC with integer result type.
1233 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1234 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1235 }
1236
1237 if (Subtarget.hasP9Altivec()) {
1238 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1239 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1240
1241 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
1242 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
1243 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
1244 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
1245 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1246 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
1247 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
1248 }
1249
1250 if (Subtarget.isISA3_1()) {
1251 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1252 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1253 }
1254 }
1255
1256 if (Subtarget.pairedVectorMemops()) {
1257 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
1258 setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
1259 setOperationAction(ISD::STORE, MVT::v256i1, Custom);
1260 }
1261 if (Subtarget.hasMMA()) {
1262 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1263 setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
1264 setOperationAction(ISD::STORE, MVT::v512i1, Custom);
1265 setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom);
1266 }
1267
1268 if (Subtarget.has64BitSupport())
1269 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
1270
1271 if (Subtarget.isISA3_1())
1272 setOperationAction(ISD::SRA, MVT::v1i128, Legal);
1273
1274 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1275
1276 if (!isPPC64) {
1277 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
1278 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
1279 }
1280
1281 setBooleanContents(ZeroOrOneBooleanContent);
1282
1283 if (Subtarget.hasAltivec()) {
1284 // Altivec instructions set fields to all zeros or all ones.
1285 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
1286 }
1287
1288 if (!isPPC64) {
1289 // These libcalls are not available in 32-bit.
1290 setLibcallName(RTLIB::SHL_I128, nullptr);
1291 setLibcallName(RTLIB::SRL_I128, nullptr);
1292 setLibcallName(RTLIB::SRA_I128, nullptr);
1293 }
1294
1295 if (!isPPC64)
1296 setMaxAtomicSizeInBitsSupported(32);
1297
1298 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1299
1300 // We have target-specific dag combine patterns for the following nodes:
1301 setTargetDAGCombine(ISD::ADD);
1302 setTargetDAGCombine(ISD::SHL);
1303 setTargetDAGCombine(ISD::SRA);
1304 setTargetDAGCombine(ISD::SRL);
1305 setTargetDAGCombine(ISD::MUL);
1306 setTargetDAGCombine(ISD::FMA);
1307 setTargetDAGCombine(ISD::SINT_TO_FP);
1308 setTargetDAGCombine(ISD::BUILD_VECTOR);
1309 if (Subtarget.hasFPCVT())
1310 setTargetDAGCombine(ISD::UINT_TO_FP);
1311 setTargetDAGCombine(ISD::LOAD);
1312 setTargetDAGCombine(ISD::STORE);
1313 setTargetDAGCombine(ISD::BR_CC);
1314 if (Subtarget.useCRBits())
1315 setTargetDAGCombine(ISD::BRCOND);
1316 setTargetDAGCombine(ISD::BSWAP);
1317 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1318 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
1319 setTargetDAGCombine(ISD::INTRINSIC_VOID);
1320
1321 setTargetDAGCombine(ISD::SIGN_EXTEND);
1322 setTargetDAGCombine(ISD::ZERO_EXTEND);
1323 setTargetDAGCombine(ISD::ANY_EXTEND);
1324
1325 setTargetDAGCombine(ISD::TRUNCATE);
1326 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1327
1328
1329 if (Subtarget.useCRBits()) {
1330 setTargetDAGCombine(ISD::TRUNCATE);
1331 setTargetDAGCombine(ISD::SETCC);
1332 setTargetDAGCombine(ISD::SELECT_CC);
1333 }
1334
1335 if (Subtarget.hasP9Altivec()) {
1336 setTargetDAGCombine(ISD::ABS);
1337 setTargetDAGCombine(ISD::VSELECT);
1338 }
1339
1340 setLibcallName(RTLIB::LOG_F128, "logf128");
1341 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1342 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1343 setLibcallName(RTLIB::EXP_F128, "expf128");
1344 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1345 setLibcallName(RTLIB::SIN_F128, "sinf128");
1346 setLibcallName(RTLIB::COS_F128, "cosf128");
1347 setLibcallName(RTLIB::POW_F128, "powf128");
1348 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1349 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1350 setLibcallName(RTLIB::REM_F128, "fmodf128");
1351 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
1352 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
1353 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
1354 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
1355 setLibcallName(RTLIB::ROUND_F128, "roundf128");
1356 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
1357 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
1358 setLibcallName(RTLIB::RINT_F128, "rintf128");
1359 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
1360 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
1361 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
1362 setLibcallName(RTLIB::FMA_F128, "fmaf128");
1363
1364 // With 32 condition bits, we don't need to sink (and duplicate) compares
1365 // aggressively in CodeGenPrep.
1366 if (Subtarget.useCRBits()) {
1367 setHasMultipleConditionRegisters();
1368 setJumpIsExpensive();
1369 }
1370
1371 setMinFunctionAlignment(Align(4));
1372
1373 switch (Subtarget.getCPUDirective()) {
1374 default: break;
1375 case PPC::DIR_970:
1376 case PPC::DIR_A2:
1377 case PPC::DIR_E500:
1378 case PPC::DIR_E500mc:
1379 case PPC::DIR_E5500:
1380 case PPC::DIR_PWR4:
1381 case PPC::DIR_PWR5:
1382 case PPC::DIR_PWR5X:
1383 case PPC::DIR_PWR6:
1384 case PPC::DIR_PWR6X:
1385 case PPC::DIR_PWR7:
1386 case PPC::DIR_PWR8:
1387 case PPC::DIR_PWR9:
1388 case PPC::DIR_PWR10:
1389 case PPC::DIR_PWR_FUTURE:
1390 setPrefLoopAlignment(Align(16));
1391 setPrefFunctionAlignment(Align(16));
1392 break;
1393 }
1394
1395 if (Subtarget.enableMachineScheduler())
1396 setSchedulingPreference(Sched::Source);
1397 else
1398 setSchedulingPreference(Sched::Hybrid);
1399
1400 computeRegisterProperties(STI.getRegisterInfo());
1401
1402 // The Freescale cores do better with aggressive inlining of memcpy and
1403 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1404 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1405 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1406 MaxStoresPerMemset = 32;
1407 MaxStoresPerMemsetOptSize = 16;
1408 MaxStoresPerMemcpy = 32;
1409 MaxStoresPerMemcpyOptSize = 8;
1410 MaxStoresPerMemmove = 32;
1411 MaxStoresPerMemmoveOptSize = 8;
1412 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1413 // The A2 also benefits from (very) aggressive inlining of memcpy and
1414 // friends. The overhead of a the function call, even when warm, can be
1415 // over one hundred cycles.
1416 MaxStoresPerMemset = 128;
1417 MaxStoresPerMemcpy = 128;
1418 MaxStoresPerMemmove = 128;
1419 MaxLoadsPerMemcmp = 128;
1420 } else {
1421 MaxLoadsPerMemcmp = 8;
1422 MaxLoadsPerMemcmpOptSize = 4;
1423 }
1424
1425 IsStrictFPEnabled = true;
1426
1427 // Let the subtarget (CPU) decide if a predictable select is more expensive
1428 // than the corresponding branch. This information is used in CGP to decide
1429 // when to convert selects into branches.
1430 PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive();
1431}
1432
1433/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1434/// the desired ByVal argument alignment.
1435static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
1436 if (MaxAlign == MaxMaxAlign)
1437 return;
1438 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1439 if (MaxMaxAlign >= 32 &&
1440 VTy->getPrimitiveSizeInBits().getFixedSize() >= 256)
1441 MaxAlign = Align(32);
1442 else if (VTy->getPrimitiveSizeInBits().getFixedSize() >= 128 &&
1443 MaxAlign < 16)
1444 MaxAlign = Align(16);
1445 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1446 Align EltAlign;
1447 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1448 if (EltAlign > MaxAlign)
1449 MaxAlign = EltAlign;
1450 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1451 for (auto *EltTy : STy->elements()) {
1452 Align EltAlign;
1453 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1454 if (EltAlign > MaxAlign)
1455 MaxAlign = EltAlign;
1456 if (MaxAlign == MaxMaxAlign)
1457 break;
1458 }
1459 }
1460}
1461
1462/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1463/// function arguments in the caller parameter area.
1464unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1465 const DataLayout &DL) const {
1466 // 16byte and wider vectors are passed on 16byte boundary.
1467 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1468 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1469 if (Subtarget.hasAltivec())
1470 getMaxByValAlign(Ty, Alignment, Align(16));
1471 return Alignment.value();
1472}
1473
1474bool PPCTargetLowering::useSoftFloat() const {
1475 return Subtarget.useSoftFloat();
1476}
1477
1478bool PPCTargetLowering::hasSPE() const {
1479 return Subtarget.hasSPE();
1480}
1481
1482bool PPCTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
1483 return VT.isScalarInteger();
1484}
1485
1486const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1487 switch ((PPCISD::NodeType)Opcode) {
1488 case PPCISD::FIRST_NUMBER: break;
1489 case PPCISD::FSEL: return "PPCISD::FSEL";
1490 case PPCISD::XSMAXCDP: return "PPCISD::XSMAXCDP";
1491 case PPCISD::XSMINCDP: return "PPCISD::XSMINCDP";
1492 case PPCISD::FCFID: return "PPCISD::FCFID";
1493 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1494 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1495 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1496 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1497 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1498 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1499 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1500 case PPCISD::FP_TO_UINT_IN_VSR:
1501 return "PPCISD::FP_TO_UINT_IN_VSR,";
1502 case PPCISD::FP_TO_SINT_IN_VSR:
1503 return "PPCISD::FP_TO_SINT_IN_VSR";
1504 case PPCISD::FRE: return "PPCISD::FRE";
1505 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1506 case PPCISD::FTSQRT:
1507 return "PPCISD::FTSQRT";
1508 case PPCISD::FSQRT:
1509 return "PPCISD::FSQRT";
1510 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1511 case PPCISD::VPERM: return "PPCISD::VPERM";
1512 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1513 case PPCISD::XXSPLTI_SP_TO_DP:
1514 return "PPCISD::XXSPLTI_SP_TO_DP";
1515 case PPCISD::XXSPLTI32DX:
1516 return "PPCISD::XXSPLTI32DX";
1517 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1518 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1519 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1520 case PPCISD::CMPB: return "PPCISD::CMPB";
1521 case PPCISD::Hi: return "PPCISD::Hi";
1522 case PPCISD::Lo: return "PPCISD::Lo";
1523 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1524 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1525 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1526 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1527 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1528 case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
1529 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1530 case PPCISD::SRL: return "PPCISD::SRL";
1531 case PPCISD::SRA: return "PPCISD::SRA";
1532 case PPCISD::SHL: return "PPCISD::SHL";
1533 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1534 case PPCISD::CALL: return "PPCISD::CALL";
1535 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1536 case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
1537 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1538 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1539 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1540 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1541 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1542 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1543 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1544 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1545 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1546 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1547 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1548 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1549 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1550 case PPCISD::SCALAR_TO_VECTOR_PERMUTED:
1551 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1552 case PPCISD::ANDI_rec_1_EQ_BIT:
1553 return "PPCISD::ANDI_rec_1_EQ_BIT";
1554 case PPCISD::ANDI_rec_1_GT_BIT:
1555 return "PPCISD::ANDI_rec_1_GT_BIT";
1556 case PPCISD::VCMP: return "PPCISD::VCMP";
1557 case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
1558 case PPCISD::LBRX: return "PPCISD::LBRX";
1559 case PPCISD::STBRX: return "PPCISD::STBRX";
1560 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1561 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1562 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1563 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1564 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1565 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1566 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1567 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1568 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1569 case PPCISD::ST_VSR_SCAL_INT:
1570 return "PPCISD::ST_VSR_SCAL_INT";
1571 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1572 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1573 case PPCISD::BDZ: return "PPCISD::BDZ";
1574 case PPCISD::MFFS: return "PPCISD::MFFS";
1575 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1576 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1577 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1578 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1579 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1580 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1581 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1582 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1583 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1584 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1585 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1586 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1587 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1588 case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX";
1589 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1590 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1591 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1592 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1593 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1594 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1595 case PPCISD::PADDI_DTPREL:
1596 return "PPCISD::PADDI_DTPREL";
1597 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1598 case PPCISD::SC: return "PPCISD::SC";
1599 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1600 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1601 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1602 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1603 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1604 case PPCISD::VABSD: return "PPCISD::VABSD";
1605 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1606 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1607 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1608 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1609 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1610 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1611 case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
1612 case PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR:
1613 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1614 case PPCISD::TLS_LOCAL_EXEC_MAT_ADDR:
1615 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1616 case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
1617 case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
1618 case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
1619 case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
1620 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1621 case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1622 case PPCISD::STRICT_FADDRTZ:
1623 return "PPCISD::STRICT_FADDRTZ";
1624 case PPCISD::STRICT_FCTIDZ:
1625 return "PPCISD::STRICT_FCTIDZ";
1626 case PPCISD::STRICT_FCTIWZ:
1627 return "PPCISD::STRICT_FCTIWZ";
1628 case PPCISD::STRICT_FCTIDUZ:
1629 return "PPCISD::STRICT_FCTIDUZ";
1630 case PPCISD::STRICT_FCTIWUZ:
1631 return "PPCISD::STRICT_FCTIWUZ";
1632 case PPCISD::STRICT_FCFID:
1633 return "PPCISD::STRICT_FCFID";
1634 case PPCISD::STRICT_FCFIDU:
1635 return "PPCISD::STRICT_FCFIDU";
1636 case PPCISD::STRICT_FCFIDS:
1637 return "PPCISD::STRICT_FCFIDS";
1638 case PPCISD::STRICT_FCFIDUS:
1639 return "PPCISD::STRICT_FCFIDUS";
1640 case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
1641 }
1642 return nullptr;
1643}
1644
1645EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1646 EVT VT) const {
1647 if (!VT.isVector())
1648 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1649
1650 return VT.changeVectorElementTypeToInteger();
1651}
1652
1653bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1654 assert(VT.isFloatingPoint() && "Non-floating-point FMA?")((VT.isFloatingPoint() && "Non-floating-point FMA?") ?
static_cast<void> (0) : __assert_fail ("VT.isFloatingPoint() && \"Non-floating-point FMA?\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1654, __PRETTY_FUNCTION__))
;
1655 return true;
1656}
1657
1658//===----------------------------------------------------------------------===//
1659// Node matching predicates, for use by the tblgen matching code.
1660//===----------------------------------------------------------------------===//
1661
1662/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1663static bool isFloatingPointZero(SDValue Op) {
1664 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1665 return CFP->getValueAPF().isZero();
1666 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1667 // Maybe this has already been legalized into the constant pool?
1668 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1669 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1670 return CFP->getValueAPF().isZero();
1671 }
1672 return false;
1673}
1674
1675/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1676/// true if Op is undef or if it matches the specified value.
1677static bool isConstantOrUndef(int Op, int Val) {
1678 return Op < 0 || Op == Val;
1679}
1680
1681/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1682/// VPKUHUM instruction.
1683/// The ShuffleKind distinguishes between big-endian operations with
1684/// two different inputs (0), either-endian operations with two identical
1685/// inputs (1), and little-endian operations with two different inputs (2).
1686/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1687bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1688 SelectionDAG &DAG) {
1689 bool IsLE = DAG.getDataLayout().isLittleEndian();
1690 if (ShuffleKind == 0) {
1691 if (IsLE)
1692 return false;
1693 for (unsigned i = 0; i != 16; ++i)
1694 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1695 return false;
1696 } else if (ShuffleKind == 2) {
1697 if (!IsLE)
1698 return false;
1699 for (unsigned i = 0; i != 16; ++i)
1700 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1701 return false;
1702 } else if (ShuffleKind == 1) {
1703 unsigned j = IsLE ? 0 : 1;
1704 for (unsigned i = 0; i != 8; ++i)
1705 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1706 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1707 return false;
1708 }
1709 return true;
1710}
1711
1712/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1713/// VPKUWUM instruction.
1714/// The ShuffleKind distinguishes between big-endian operations with
1715/// two different inputs (0), either-endian operations with two identical
1716/// inputs (1), and little-endian operations with two different inputs (2).
1717/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1718bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1719 SelectionDAG &DAG) {
1720 bool IsLE = DAG.getDataLayout().isLittleEndian();
1721 if (ShuffleKind == 0) {
1722 if (IsLE)
1723 return false;
1724 for (unsigned i = 0; i != 16; i += 2)
1725 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1726 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1727 return false;
1728 } else if (ShuffleKind == 2) {
1729 if (!IsLE)
1730 return false;
1731 for (unsigned i = 0; i != 16; i += 2)
1732 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1733 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1734 return false;
1735 } else if (ShuffleKind == 1) {
1736 unsigned j = IsLE ? 0 : 2;
1737 for (unsigned i = 0; i != 8; i += 2)
1738 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1739 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1740 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1741 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1742 return false;
1743 }
1744 return true;
1745}
1746
1747/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1748/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1749/// current subtarget.
1750///
1751/// The ShuffleKind distinguishes between big-endian operations with
1752/// two different inputs (0), either-endian operations with two identical
1753/// inputs (1), and little-endian operations with two different inputs (2).
1754/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1755bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1756 SelectionDAG &DAG) {
1757 const PPCSubtarget& Subtarget =
1758 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1759 if (!Subtarget.hasP8Vector())
1760 return false;
1761
1762 bool IsLE = DAG.getDataLayout().isLittleEndian();
1763 if (ShuffleKind == 0) {
1764 if (IsLE)
1765 return false;
1766 for (unsigned i = 0; i != 16; i += 4)
1767 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1768 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1769 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1770 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1771 return false;
1772 } else if (ShuffleKind == 2) {
1773 if (!IsLE)
1774 return false;
1775 for (unsigned i = 0; i != 16; i += 4)
1776 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1777 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1778 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1779 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1780 return false;
1781 } else if (ShuffleKind == 1) {
1782 unsigned j = IsLE ? 0 : 4;
1783 for (unsigned i = 0; i != 8; i += 4)
1784 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1785 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1786 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1787 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1788 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1789 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1790 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1791 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1792 return false;
1793 }
1794 return true;
1795}
1796
1797/// isVMerge - Common function, used to match vmrg* shuffles.
1798///
1799static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1800 unsigned LHSStart, unsigned RHSStart) {
1801 if (N->getValueType(0) != MVT::v16i8)
1802 return false;
1803 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1804, __PRETTY_FUNCTION__))
1804 "Unsupported merge size!")(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1804, __PRETTY_FUNCTION__))
;
1805
1806 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1807 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1808 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1809 LHSStart+j+i*UnitSize) ||
1810 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1811 RHSStart+j+i*UnitSize))
1812 return false;
1813 }
1814 return true;
1815}
1816
1817/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1818/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1819/// The ShuffleKind distinguishes between big-endian merges with two
1820/// different inputs (0), either-endian merges with two identical inputs (1),
1821/// and little-endian merges with two different inputs (2). For the latter,
1822/// the input operands are swapped (see PPCInstrAltivec.td).
1823bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1824 unsigned ShuffleKind, SelectionDAG &DAG) {
1825 if (DAG.getDataLayout().isLittleEndian()) {
1826 if (ShuffleKind == 1) // unary
1827 return isVMerge(N, UnitSize, 0, 0);
1828 else if (ShuffleKind == 2) // swapped
1829 return isVMerge(N, UnitSize, 0, 16);
1830 else
1831 return false;
1832 } else {
1833 if (ShuffleKind == 1) // unary
1834 return isVMerge(N, UnitSize, 8, 8);
1835 else if (ShuffleKind == 0) // normal
1836 return isVMerge(N, UnitSize, 8, 24);
1837 else
1838 return false;
1839 }
1840}
1841
1842/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1843/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1844/// The ShuffleKind distinguishes between big-endian merges with two
1845/// different inputs (0), either-endian merges with two identical inputs (1),
1846/// and little-endian merges with two different inputs (2). For the latter,
1847/// the input operands are swapped (see PPCInstrAltivec.td).
1848bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1849 unsigned ShuffleKind, SelectionDAG &DAG) {
1850 if (DAG.getDataLayout().isLittleEndian()) {
1851 if (ShuffleKind == 1) // unary
1852 return isVMerge(N, UnitSize, 8, 8);
1853 else if (ShuffleKind == 2) // swapped
1854 return isVMerge(N, UnitSize, 8, 24);
1855 else
1856 return false;
1857 } else {
1858 if (ShuffleKind == 1) // unary
1859 return isVMerge(N, UnitSize, 0, 0);
1860 else if (ShuffleKind == 0) // normal
1861 return isVMerge(N, UnitSize, 0, 16);
1862 else
1863 return false;
1864 }
1865}
1866
1867/**
1868 * Common function used to match vmrgew and vmrgow shuffles
1869 *
1870 * The indexOffset determines whether to look for even or odd words in
1871 * the shuffle mask. This is based on the of the endianness of the target
1872 * machine.
1873 * - Little Endian:
1874 * - Use offset of 0 to check for odd elements
1875 * - Use offset of 4 to check for even elements
1876 * - Big Endian:
1877 * - Use offset of 0 to check for even elements
1878 * - Use offset of 4 to check for odd elements
1879 * A detailed description of the vector element ordering for little endian and
1880 * big endian can be found at
1881 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1882 * Targeting your applications - what little endian and big endian IBM XL C/C++
1883 * compiler differences mean to you
1884 *
1885 * The mask to the shuffle vector instruction specifies the indices of the
1886 * elements from the two input vectors to place in the result. The elements are
1887 * numbered in array-access order, starting with the first vector. These vectors
1888 * are always of type v16i8, thus each vector will contain 16 elements of size
1889 * 8. More info on the shuffle vector can be found in the
1890 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1891 * Language Reference.
1892 *
1893 * The RHSStartValue indicates whether the same input vectors are used (unary)
1894 * or two different input vectors are used, based on the following:
1895 * - If the instruction uses the same vector for both inputs, the range of the
1896 * indices will be 0 to 15. In this case, the RHSStart value passed should
1897 * be 0.
1898 * - If the instruction has two different vectors then the range of the
1899 * indices will be 0 to 31. In this case, the RHSStart value passed should
1900 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1901 * to 31 specify elements in the second vector).
1902 *
1903 * \param[in] N The shuffle vector SD Node to analyze
1904 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1905 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1906 * vector to the shuffle_vector instruction
1907 * \return true iff this shuffle vector represents an even or odd word merge
1908 */
1909static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1910 unsigned RHSStartValue) {
1911 if (N->getValueType(0) != MVT::v16i8)
1912 return false;
1913
1914 for (unsigned i = 0; i < 2; ++i)
1915 for (unsigned j = 0; j < 4; ++j)
1916 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1917 i*RHSStartValue+j+IndexOffset) ||
1918 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1919 i*RHSStartValue+j+IndexOffset+8))
1920 return false;
1921 return true;
1922}
1923
1924/**
1925 * Determine if the specified shuffle mask is suitable for the vmrgew or
1926 * vmrgow instructions.
1927 *
1928 * \param[in] N The shuffle vector SD Node to analyze
1929 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1930 * \param[in] ShuffleKind Identify the type of merge:
1931 * - 0 = big-endian merge with two different inputs;
1932 * - 1 = either-endian merge with two identical inputs;
1933 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1934 * little-endian merges).
1935 * \param[in] DAG The current SelectionDAG
1936 * \return true iff this shuffle mask
1937 */
1938bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1939 unsigned ShuffleKind, SelectionDAG &DAG) {
1940 if (DAG.getDataLayout().isLittleEndian()) {
1941 unsigned indexOffset = CheckEven ? 4 : 0;
1942 if (ShuffleKind == 1) // Unary
1943 return isVMerge(N, indexOffset, 0);
1944 else if (ShuffleKind == 2) // swapped
1945 return isVMerge(N, indexOffset, 16);
1946 else
1947 return false;
1948 }
1949 else {
1950 unsigned indexOffset = CheckEven ? 0 : 4;
1951 if (ShuffleKind == 1) // Unary
1952 return isVMerge(N, indexOffset, 0);
1953 else if (ShuffleKind == 0) // Normal
1954 return isVMerge(N, indexOffset, 16);
1955 else
1956 return false;
1957 }
1958 return false;
1959}
1960
1961/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1962/// amount, otherwise return -1.
1963/// The ShuffleKind distinguishes between big-endian operations with two
1964/// different inputs (0), either-endian operations with two identical inputs
1965/// (1), and little-endian operations with two different inputs (2). For the
1966/// latter, the input operands are swapped (see PPCInstrAltivec.td).
1967int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1968 SelectionDAG &DAG) {
1969 if (N->getValueType(0) != MVT::v16i8)
1970 return -1;
1971
1972 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1973
1974 // Find the first non-undef value in the shuffle mask.
1975 unsigned i;
1976 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1977 /*search*/;
1978
1979 if (i == 16) return -1; // all undef.
1980
1981 // Otherwise, check to see if the rest of the elements are consecutively
1982 // numbered from this value.
1983 unsigned ShiftAmt = SVOp->getMaskElt(i);
1984 if (ShiftAmt < i) return -1;
1985
1986 ShiftAmt -= i;
1987 bool isLE = DAG.getDataLayout().isLittleEndian();
1988
1989 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1990 // Check the rest of the elements to see if they are consecutive.
1991 for (++i; i != 16; ++i)
1992 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1993 return -1;
1994 } else if (ShuffleKind == 1) {
1995 // Check the rest of the elements to see if they are consecutive.
1996 for (++i; i != 16; ++i)
1997 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1998 return -1;
1999 } else
2000 return -1;
2001
2002 if (isLE)
2003 ShiftAmt = 16 - ShiftAmt;
2004
2005 return ShiftAmt;
2006}
2007
2008/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
2009/// specifies a splat of a single element that is suitable for input to
2010/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
2011bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
2012 assert(N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) &&((N->getValueType(0) == MVT::v16i8 && isPowerOf2_32
(EltSize) && EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2013, __PRETTY_FUNCTION__))
2013 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes")((N->getValueType(0) == MVT::v16i8 && isPowerOf2_32
(EltSize) && EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2013, __PRETTY_FUNCTION__))
;
2014
2015 // The consecutive indices need to specify an element, not part of two
2016 // different elements. So abandon ship early if this isn't the case.
2017 if (N->getMaskElt(0) % EltSize != 0)
2018 return false;
2019
2020 // This is a splat operation if each element of the permute is the same, and
2021 // if the value doesn't reference the second vector.
2022 unsigned ElementBase = N->getMaskElt(0);
2023
2024 // FIXME: Handle UNDEF elements too!
2025 if (ElementBase >= 16)
2026 return false;
2027
2028 // Check that the indices are consecutive, in the case of a multi-byte element
2029 // splatted with a v16i8 mask.
2030 for (unsigned i = 1; i != EltSize; ++i)
2031 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
2032 return false;
2033
2034 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
2035 if (N->getMaskElt(i) < 0) continue;
2036 for (unsigned j = 0; j != EltSize; ++j)
2037 if (N->getMaskElt(i+j) != N->getMaskElt(j))
2038 return false;
2039 }
2040 return true;
2041}
2042
2043/// Check that the mask is shuffling N byte elements. Within each N byte
2044/// element of the mask, the indices could be either in increasing or
2045/// decreasing order as long as they are consecutive.
2046/// \param[in] N the shuffle vector SD Node to analyze
2047/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
2048/// Word/DoubleWord/QuadWord).
2049/// \param[in] StepLen the delta indices number among the N byte element, if
2050/// the mask is in increasing/decreasing order then it is 1/-1.
2051/// \return true iff the mask is shuffling N byte elements.
2052static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
2053 int StepLen) {
2054 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2055, __PRETTY_FUNCTION__))
2055 "Unexpected element width.")(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2055, __PRETTY_FUNCTION__))
;
2056 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.")(((StepLen == 1 || StepLen == -1) && "Unexpected element width."
) ? static_cast<void> (0) : __assert_fail ("(StepLen == 1 || StepLen == -1) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2056, __PRETTY_FUNCTION__))
;
2057
2058 unsigned NumOfElem = 16 / Width;
2059 unsigned MaskVal[16]; // Width is never greater than 16
2060 for (unsigned i = 0; i < NumOfElem; ++i) {
2061 MaskVal[0] = N->getMaskElt(i * Width);
2062 if ((StepLen == 1) && (MaskVal[0] % Width)) {
2063 return false;
2064 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
2065 return false;
2066 }
2067
2068 for (unsigned int j = 1; j < Width; ++j) {
2069 MaskVal[j] = N->getMaskElt(i * Width + j);
2070 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
2071 return false;
2072 }
2073 }
2074 }
2075
2076 return true;
2077}
2078
2079bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2080 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
2081 if (!isNByteElemShuffleMask(N, 4, 1))
2082 return false;
2083
2084 // Now we look at mask elements 0,4,8,12
2085 unsigned M0 = N->getMaskElt(0) / 4;
2086 unsigned M1 = N->getMaskElt(4) / 4;
2087 unsigned M2 = N->getMaskElt(8) / 4;
2088 unsigned M3 = N->getMaskElt(12) / 4;
2089 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
2090 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
2091
2092 // Below, let H and L be arbitrary elements of the shuffle mask
2093 // where H is in the range [4,7] and L is in the range [0,3].
2094 // H, 1, 2, 3 or L, 5, 6, 7
2095 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
2096 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
2097 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2098 InsertAtByte = IsLE ? 12 : 0;
2099 Swap = M0 < 4;
2100 return true;
2101 }
2102 // 0, H, 2, 3 or 4, L, 6, 7
2103 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
2104 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
2105 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2106 InsertAtByte = IsLE ? 8 : 4;
2107 Swap = M1 < 4;
2108 return true;
2109 }
2110 // 0, 1, H, 3 or 4, 5, L, 7
2111 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
2112 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
2113 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2114 InsertAtByte = IsLE ? 4 : 8;
2115 Swap = M2 < 4;
2116 return true;
2117 }
2118 // 0, 1, 2, H or 4, 5, 6, L
2119 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
2120 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
2121 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2122 InsertAtByte = IsLE ? 0 : 12;
2123 Swap = M3 < 4;
2124 return true;
2125 }
2126
2127 // If both vector operands for the shuffle are the same vector, the mask will
2128 // contain only elements from the first one and the second one will be undef.
2129 if (N->getOperand(1).isUndef()) {
2130 ShiftElts = 0;
2131 Swap = true;
2132 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2133 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
2134 InsertAtByte = IsLE ? 12 : 0;
2135 return true;
2136 }
2137 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2138 InsertAtByte = IsLE ? 8 : 4;
2139 return true;
2140 }
2141 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2142 InsertAtByte = IsLE ? 4 : 8;
2143 return true;
2144 }
2145 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2146 InsertAtByte = IsLE ? 0 : 12;
2147 return true;
2148 }
2149 }
2150
2151 return false;
2152}
2153
2154bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2155 bool &Swap, bool IsLE) {
2156 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2156, __PRETTY_FUNCTION__))
;
25
'?' condition is true
2157 // Ensure each byte index of the word is consecutive.
2158 if (!isNByteElemShuffleMask(N, 4, 1))
26
Assuming the condition is false
27
Taking false branch
2159 return false;
2160
2161 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
2162 unsigned M0 = N->getMaskElt(0) / 4;
2163 unsigned M1 = N->getMaskElt(4) / 4;
2164 unsigned M2 = N->getMaskElt(8) / 4;
2165 unsigned M3 = N->getMaskElt(12) / 4;
2166
2167 // If both vector operands for the shuffle are the same vector, the mask will
2168 // contain only elements from the first one and the second one will be undef.
2169 if (N->getOperand(1).isUndef()) {
28
Calling 'SDValue::isUndef'
34
Returning from 'SDValue::isUndef'
35
Taking false branch
2170 assert(M0 < 4 && "Indexing into an undef vector?")((M0 < 4 && "Indexing into an undef vector?") ? static_cast
<void> (0) : __assert_fail ("M0 < 4 && \"Indexing into an undef vector?\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2170, __PRETTY_FUNCTION__))
;
2171 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2172 return false;
2173
2174 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2175 Swap = false;
2176 return true;
2177 }
2178
2179 // Ensure each word index of the ShuffleVector Mask is consecutive.
2180 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
36
Assuming the condition is false
37
Assuming the condition is false
38
Assuming the condition is false
39
Taking false branch
2181 return false;
2182
2183 if (IsLE) {
40
Assuming 'IsLE' is false
41
Taking false branch
2184 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2185 // Input vectors don't need to be swapped if the leading element
2186 // of the result is one of the 3 left elements of the second vector
2187 // (or if there is no shift to be done at all).
2188 Swap = false;
2189 ShiftElts = (8 - M0) % 8;
2190 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2191 // Input vectors need to be swapped if the leading element
2192 // of the result is one of the 3 left elements of the first vector
2193 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2194 Swap = true;
2195 ShiftElts = (4 - M0) % 4;
2196 }
2197
2198 return true;
2199 } else { // BE
2200 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
42
Assuming 'M0' is not equal to 0
43
Assuming 'M0' is not equal to 1
44
Assuming 'M0' is not equal to 2
45
Assuming 'M0' is not equal to 3
46
Taking false branch
2201 // Input vectors don't need to be swapped if the leading element
2202 // of the result is one of the 4 elements of the first vector.
2203 Swap = false;
2204 ShiftElts = M0;
2205 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
47
Assuming 'M0' is not equal to 4
48
Assuming 'M0' is not equal to 5
49
Assuming 'M0' is not equal to 6
50
Assuming 'M0' is not equal to 7
51
Taking false branch
2206 // Input vectors need to be swapped if the leading element
2207 // of the result is one of the 4 elements of the right vector.
2208 Swap = true;
2209 ShiftElts = M0 - 4;
2210 }
2211
2212 return true;
52
Returning without writing to 'ShiftElts'
53
Returning the value 1, which participates in a condition later
2213 }
2214}
2215
2216bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
2217 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2217, __PRETTY_FUNCTION__))
;
2218
2219 if (!isNByteElemShuffleMask(N, Width, -1))
2220 return false;
2221
2222 for (int i = 0; i < 16; i += Width)
2223 if (N->getMaskElt(i) != i + Width - 1)
2224 return false;
2225
2226 return true;
2227}
2228
2229bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
2230 return isXXBRShuffleMaskHelper(N, 2);
2231}
2232
2233bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
2234 return isXXBRShuffleMaskHelper(N, 4);
2235}
2236
2237bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
2238 return isXXBRShuffleMaskHelper(N, 8);
2239}
2240
2241bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
2242 return isXXBRShuffleMaskHelper(N, 16);
2243}
2244
2245/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2246/// if the inputs to the instruction should be swapped and set \p DM to the
2247/// value for the immediate.
2248/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2249/// AND element 0 of the result comes from the first input (LE) or second input
2250/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2251/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2252/// mask.
2253bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
2254 bool &Swap, bool IsLE) {
2255 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2255, __PRETTY_FUNCTION__))
;
2256
2257 // Ensure each byte index of the double word is consecutive.
2258 if (!isNByteElemShuffleMask(N, 8, 1))
2259 return false;
2260
2261 unsigned M0 = N->getMaskElt(0) / 8;
2262 unsigned M1 = N->getMaskElt(8) / 8;
2263 assert(((M0 | M1) < 4) && "A mask element out of bounds?")((((M0 | M1) < 4) && "A mask element out of bounds?"
) ? static_cast<void> (0) : __assert_fail ("((M0 | M1) < 4) && \"A mask element out of bounds?\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2263, __PRETTY_FUNCTION__))
;
2264
2265 // If both vector operands for the shuffle are the same vector, the mask will
2266 // contain only elements from the first one and the second one will be undef.
2267 if (N->getOperand(1).isUndef()) {
2268 if ((M0 | M1) < 2) {
2269 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2270 Swap = false;
2271 return true;
2272 } else
2273 return false;
2274 }
2275
2276 if (IsLE) {
2277 if (M0 > 1 && M1 < 2) {
2278 Swap = false;
2279 } else if (M0 < 2 && M1 > 1) {
2280 M0 = (M0 + 2) % 4;
2281 M1 = (M1 + 2) % 4;
2282 Swap = true;
2283 } else
2284 return false;
2285
2286 // Note: if control flow comes here that means Swap is already set above
2287 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2288 return true;
2289 } else { // BE
2290 if (M0 < 2 && M1 > 1) {
2291 Swap = false;
2292 } else if (M0 > 1 && M1 < 2) {
2293 M0 = (M0 + 2) % 4;
2294 M1 = (M1 + 2) % 4;
2295 Swap = true;
2296 } else
2297 return false;
2298
2299 // Note: if control flow comes here that means Swap is already set above
2300 DM = (M0 << 1) + (M1 & 1);
2301 return true;
2302 }
2303}
2304
2305
2306/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2307/// appropriate for PPC mnemonics (which have a big endian bias - namely
2308/// elements are counted from the left of the vector register).
2309unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2310 SelectionDAG &DAG) {
2311 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2312 assert(isSplatShuffleMask(SVOp, EltSize))((isSplatShuffleMask(SVOp, EltSize)) ? static_cast<void>
(0) : __assert_fail ("isSplatShuffleMask(SVOp, EltSize)", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2312, __PRETTY_FUNCTION__))
;
2313 if (DAG.getDataLayout().isLittleEndian())
2314 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2315 else
2316 return SVOp->getMaskElt(0) / EltSize;
2317}
2318
2319/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2320/// by using a vspltis[bhw] instruction of the specified element size, return
2321/// the constant being splatted. The ByteSize field indicates the number of
2322/// bytes of each element [124] -> [bhw].
2323SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2324 SDValue OpVal(nullptr, 0);
2325
2326 // If ByteSize of the splat is bigger than the element size of the
2327 // build_vector, then we have a case where we are checking for a splat where
2328 // multiple elements of the buildvector are folded together into a single
2329 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2330 unsigned EltSize = 16/N->getNumOperands();
2331 if (EltSize < ByteSize) {
2332 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2333 SDValue UniquedVals[4];
2334 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?")((Multiple > 1 && Multiple <= 4 && "How can this happen?"
) ? static_cast<void> (0) : __assert_fail ("Multiple > 1 && Multiple <= 4 && \"How can this happen?\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2334, __PRETTY_FUNCTION__))
;
2335
2336 // See if all of the elements in the buildvector agree across.
2337 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2338 if (N->getOperand(i).isUndef()) continue;
2339 // If the element isn't a constant, bail fully out.
2340 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2341
2342 if (!UniquedVals[i&(Multiple-1)].getNode())
2343 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2344 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2345 return SDValue(); // no match.
2346 }
2347
2348 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2349 // either constant or undef values that are identical for each chunk. See
2350 // if these chunks can form into a larger vspltis*.
2351
2352 // Check to see if all of the leading entries are either 0 or -1. If
2353 // neither, then this won't fit into the immediate field.
2354 bool LeadingZero = true;
2355 bool LeadingOnes = true;
2356 for (unsigned i = 0; i != Multiple-1; ++i) {
2357 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2358
2359 LeadingZero &= isNullConstant(UniquedVals[i]);
2360 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2361 }
2362 // Finally, check the least significant entry.
2363 if (LeadingZero) {
2364 if (!UniquedVals[Multiple-1].getNode())
2365 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2366 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2367 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2368 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2369 }
2370 if (LeadingOnes) {
2371 if (!UniquedVals[Multiple-1].getNode())
2372 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2373 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2374 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2375 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2376 }
2377
2378 return SDValue();
2379 }
2380
2381 // Check to see if this buildvec has a single non-undef value in its elements.
2382 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2383 if (N->getOperand(i).isUndef()) continue;
2384 if (!OpVal.getNode())
2385 OpVal = N->getOperand(i);
2386 else if (OpVal != N->getOperand(i))
2387 return SDValue();
2388 }
2389
2390 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2391
2392 unsigned ValSizeInBytes = EltSize;
2393 uint64_t Value = 0;
2394 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2395 Value = CN->getZExtValue();
2396 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2397 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!")((CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"
) ? static_cast<void> (0) : __assert_fail ("CN->getValueType(0) == MVT::f32 && \"Only one legal FP vector type!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2397, __PRETTY_FUNCTION__))
;
2398 Value = FloatToBits(CN->getValueAPF().convertToFloat());
2399 }
2400
2401 // If the splat value is larger than the element value, then we can never do
2402 // this splat. The only case that we could fit the replicated bits into our
2403 // immediate field for would be zero, and we prefer to use vxor for it.
2404 if (ValSizeInBytes < ByteSize) return SDValue();
2405
2406 // If the element value is larger than the splat value, check if it consists
2407 // of a repeated bit pattern of size ByteSize.
2408 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2409 return SDValue();
2410
2411 // Properly sign extend the value.
2412 int MaskVal = SignExtend32(Value, ByteSize * 8);
2413
2414 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2415 if (MaskVal == 0) return SDValue();
2416
2417 // Finally, if this value fits in a 5 bit sext field, return it
2418 if (SignExtend32<5>(MaskVal) == MaskVal)
2419 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2420 return SDValue();
2421}
2422
2423//===----------------------------------------------------------------------===//
2424// Addressing Mode Selection
2425//===----------------------------------------------------------------------===//
2426
2427/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2428/// or 64-bit immediate, and if the value can be accurately represented as a
2429/// sign extension from a 16-bit value. If so, this returns true and the
2430/// immediate.
2431bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2432 if (!isa<ConstantSDNode>(N))
2433 return false;
2434
2435 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2436 if (N->getValueType(0) == MVT::i32)
2437 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2438 else
2439 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2440}
2441bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2442 return isIntS16Immediate(Op.getNode(), Imm);
2443}
2444
2445
2446/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2447/// be represented as an indexed [r+r] operation.
2448bool PPCTargetLowering::SelectAddressEVXRegReg(SDValue N, SDValue &Base,
2449 SDValue &Index,
2450 SelectionDAG &DAG) const {
2451 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
2452 UI != E; ++UI) {
2453 if (MemSDNode *Memop = dyn_cast<MemSDNode>(*UI)) {
2454 if (Memop->getMemoryVT() == MVT::f64) {
2455 Base = N.getOperand(0);
2456 Index = N.getOperand(1);
2457 return true;
2458 }
2459 }
2460 }
2461 return false;
2462}
2463
2464/// isIntS34Immediate - This method tests if value of node given can be
2465/// accurately represented as a sign extension from a 34-bit value. If so,
2466/// this returns true and the immediate.
2467bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2468 if (!isa<ConstantSDNode>(N))
2469 return false;
2470
2471 Imm = (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2472 return isInt<34>(Imm);
2473}
2474bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) {
2475 return isIntS34Immediate(Op.getNode(), Imm);
2476}
2477
2478/// SelectAddressRegReg - Given the specified addressed, check to see if it
2479/// can be represented as an indexed [r+r] operation. Returns false if it
2480/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2481/// non-zero and N can be represented by a base register plus a signed 16-bit
2482/// displacement, make a more precise judgement by checking (displacement % \p
2483/// EncodingAlignment).
2484bool PPCTargetLowering::SelectAddressRegReg(
2485 SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG,
2486 MaybeAlign EncodingAlignment) const {
2487 // If we have a PC Relative target flag don't select as [reg+reg]. It will be
2488 // a [pc+imm].
2489 if (SelectAddressPCRel(N, Base))
2490 return false;
2491
2492 int16_t Imm = 0;
2493 if (N.getOpcode() == ISD::ADD) {
2494 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2495 // SPE load/store can only handle 8-bit offsets.
2496 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2497 return true;
2498 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2499 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2500 return false; // r+i
2501 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2502 return false; // r+i
2503
2504 Base = N.getOperand(0);
2505 Index = N.getOperand(1);
2506 return true;
2507 } else if (N.getOpcode() == ISD::OR) {
2508 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2509 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2510 return false; // r+i can fold it if we can.
2511
2512 // If this is an or of disjoint bitfields, we can codegen this as an add
2513 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2514 // disjoint.
2515 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2516
2517 if (LHSKnown.Zero.getBoolValue()) {
2518 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2519 // If all of the bits are known zero on the LHS or RHS, the add won't
2520 // carry.
2521 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2522 Base = N.getOperand(0);
2523 Index = N.getOperand(1);
2524 return true;
2525 }
2526 }
2527 }
2528
2529 return false;
2530}
2531
2532// If we happen to be doing an i64 load or store into a stack slot that has
2533// less than a 4-byte alignment, then the frame-index elimination may need to
2534// use an indexed load or store instruction (because the offset may not be a
2535// multiple of 4). The extra register needed to hold the offset comes from the
2536// register scavenger, and it is possible that the scavenger will need to use
2537// an emergency spill slot. As a result, we need to make sure that a spill slot
2538// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2539// stack slot.
2540static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2541 // FIXME: This does not handle the LWA case.
2542 if (VT != MVT::i64)
2543 return;
2544
2545 // NOTE: We'll exclude negative FIs here, which come from argument
2546 // lowering, because there are no known test cases triggering this problem
2547 // using packed structures (or similar). We can remove this exclusion if
2548 // we find such a test case. The reason why this is so test-case driven is
2549 // because this entire 'fixup' is only to prevent crashes (from the
2550 // register scavenger) on not-really-valid inputs. For example, if we have:
2551 // %a = alloca i1
2552 // %b = bitcast i1* %a to i64*
2553 // store i64* a, i64 b
2554 // then the store should really be marked as 'align 1', but is not. If it
2555 // were marked as 'align 1' then the indexed form would have been
2556 // instruction-selected initially, and the problem this 'fixup' is preventing
2557 // won't happen regardless.
2558 if (FrameIdx < 0)
2559 return;
2560
2561 MachineFunction &MF = DAG.getMachineFunction();
2562 MachineFrameInfo &MFI = MF.getFrameInfo();
2563
2564 if (MFI.getObjectAlign(FrameIdx) >= Align(4))
2565 return;
2566
2567 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2568 FuncInfo->setHasNonRISpills();
2569}
2570
2571/// Returns true if the address N can be represented by a base register plus
2572/// a signed 16-bit displacement [r+imm], and if it is not better
2573/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2574/// displacements that are multiples of that value.
2575bool PPCTargetLowering::SelectAddressRegImm(
2576 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2577 MaybeAlign EncodingAlignment) const {
2578 // FIXME dl should come from parent load or store, not from address
2579 SDLoc dl(N);
2580
2581 // If we have a PC Relative target flag don't select as [reg+imm]. It will be
2582 // a [pc+imm].
2583 if (SelectAddressPCRel(N, Base))
2584 return false;
2585
2586 // If this can be more profitably realized as r+r, fail.
2587 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2588 return false;
2589
2590 if (N.getOpcode() == ISD::ADD) {
2591 int16_t imm = 0;
2592 if (isIntS16Immediate(N.getOperand(1), imm) &&
2593 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2594 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2595 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2596 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2597 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2598 } else {
2599 Base = N.getOperand(0);
2600 }
2601 return true; // [r+i]
2602 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2603 // Match LOAD (ADD (X, Lo(G))).
2604 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2605, __PRETTY_FUNCTION__))
2605 && "Cannot handle constant offsets yet!")((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2605, __PRETTY_FUNCTION__))
;
2606 Disp = N.getOperand(1).getOperand(0); // The global address.
2607 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2610, __PRETTY_FUNCTION__))
2608 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2610, __PRETTY_FUNCTION__))
2609 Disp.getOpcode() == ISD::TargetConstantPool ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2610, __PRETTY_FUNCTION__))
2610 Disp.getOpcode() == ISD::TargetJumpTable)((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2610, __PRETTY_FUNCTION__))
;
2611 Base = N.getOperand(0);
2612 return true; // [&g+r]
2613 }
2614 } else if (N.getOpcode() == ISD::OR) {
2615 int16_t imm = 0;
2616 if (isIntS16Immediate(N.getOperand(1), imm) &&
2617 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2618 // If this is an or of disjoint bitfields, we can codegen this as an add
2619 // (for better address arithmetic) if the LHS and RHS of the OR are
2620 // provably disjoint.
2621 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2622
2623 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2624 // If all of the bits are known zero on the LHS or RHS, the add won't
2625 // carry.
2626 if (FrameIndexSDNode *FI =
2627 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2628 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2629 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2630 } else {
2631 Base = N.getOperand(0);
2632 }
2633 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2634 return true;
2635 }
2636 }
2637 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2638 // Loading from a constant address.
2639
2640 // If this address fits entirely in a 16-bit sext immediate field, codegen
2641 // this as "d, 0"
2642 int16_t Imm;
2643 if (isIntS16Immediate(CN, Imm) &&
2644 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2645 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2646 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2647 CN->getValueType(0));
2648 return true;
2649 }
2650
2651 // Handle 32-bit sext immediates with LIS + addr mode.
2652 if ((CN->getValueType(0) == MVT::i32 ||
2653 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2654 (!EncodingAlignment ||
2655 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2656 int Addr = (int)CN->getZExtValue();
2657
2658 // Otherwise, break this down into an LIS + disp.
2659 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2660
2661 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2662 MVT::i32);
2663 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2664 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2665 return true;
2666 }
2667 }
2668
2669 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2670 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2671 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2672 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2673 } else
2674 Base = N;
2675 return true; // [r+0]
2676}
2677
2678/// Similar to the 16-bit case but for instructions that take a 34-bit
2679/// displacement field (prefixed loads/stores).
2680bool PPCTargetLowering::SelectAddressRegImm34(SDValue N, SDValue &Disp,
2681 SDValue &Base,
2682 SelectionDAG &DAG) const {
2683 // Only on 64-bit targets.
2684 if (N.getValueType() != MVT::i64)
2685 return false;
2686
2687 SDLoc dl(N);
2688 int64_t Imm = 0;
2689
2690 if (N.getOpcode() == ISD::ADD) {
2691 if (!isIntS34Immediate(N.getOperand(1), Imm))
2692 return false;
2693 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2694 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2695 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2696 else
2697 Base = N.getOperand(0);
2698 return true;
2699 }
2700
2701 if (N.getOpcode() == ISD::OR) {
2702 if (!isIntS34Immediate(N.getOperand(1), Imm))
2703 return false;
2704 // If this is an or of disjoint bitfields, we can codegen this as an add
2705 // (for better address arithmetic) if the LHS and RHS of the OR are
2706 // provably disjoint.
2707 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2708 if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)Imm) != ~0ULL)
2709 return false;
2710 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2711 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2712 else
2713 Base = N.getOperand(0);
2714 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2715 return true;
2716 }
2717
2718 if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2719 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2720 Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2721 return true;
2722 }
2723
2724 return false;
2725}
2726
2727/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2728/// represented as an indexed [r+r] operation.
2729bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2730 SDValue &Index,
2731 SelectionDAG &DAG) const {
2732 // Check to see if we can easily represent this as an [r+r] address. This
2733 // will fail if it thinks that the address is more profitably represented as
2734 // reg+imm, e.g. where imm = 0.
2735 if (SelectAddressRegReg(N, Base, Index, DAG))
2736 return true;
2737
2738 // If the address is the result of an add, we will utilize the fact that the
2739 // address calculation includes an implicit add. However, we can reduce
2740 // register pressure if we do not materialize a constant just for use as the
2741 // index register. We only get rid of the add if it is not an add of a
2742 // value and a 16-bit signed constant and both have a single use.
2743 int16_t imm = 0;
2744 if (N.getOpcode() == ISD::ADD &&
2745 (!isIntS16Immediate(N.getOperand(1), imm) ||
2746 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2747 Base = N.getOperand(0);
2748 Index = N.getOperand(1);
2749 return true;
2750 }
2751
2752 // Otherwise, do it the hard way, using R0 as the base register.
2753 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2754 N.getValueType());
2755 Index = N;
2756 return true;
2757}
2758
2759template <typename Ty> static bool isValidPCRelNode(SDValue N) {
2760 Ty *PCRelCand = dyn_cast<Ty>(N);
2761 return PCRelCand && (PCRelCand->getTargetFlags() & PPCII::MO_PCREL_FLAG);
2762}
2763
2764/// Returns true if this address is a PC Relative address.
2765/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
2766/// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
2767bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
2768 // This is a materialize PC Relative node. Always select this as PC Relative.
2769 Base = N;
2770 if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
2771 return true;
2772 if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
2773 isValidPCRelNode<GlobalAddressSDNode>(N) ||
2774 isValidPCRelNode<JumpTableSDNode>(N) ||
2775 isValidPCRelNode<BlockAddressSDNode>(N))
2776 return true;
2777 return false;
2778}
2779
2780/// Returns true if we should use a direct load into vector instruction
2781/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2782static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
2783
2784 // If there are any other uses other than scalar to vector, then we should
2785 // keep it as a scalar load -> direct move pattern to prevent multiple
2786 // loads.
2787 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
2788 if (!LD)
2789 return false;
2790
2791 EVT MemVT = LD->getMemoryVT();
2792 if (!MemVT.isSimple())
2793 return false;
2794 switch(MemVT.getSimpleVT().SimpleTy) {
2795 case MVT::i64:
2796 break;
2797 case MVT::i32:
2798 if (!ST.hasP8Vector())
2799 return false;
2800 break;
2801 case MVT::i16:
2802 case MVT::i8:
2803 if (!ST.hasP9Vector())
2804 return false;
2805 break;
2806 default:
2807 return false;
2808 }
2809
2810 SDValue LoadedVal(N, 0);
2811 if (!LoadedVal.hasOneUse())
2812 return false;
2813
2814 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
2815 UI != UE; ++UI)
2816 if (UI.getUse().get().getResNo() == 0 &&
2817 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &&
2818 UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED)
2819 return false;
2820
2821 return true;
2822}
2823
2824/// getPreIndexedAddressParts - returns true by value, base pointer and
2825/// offset pointer and addressing mode by reference if the node's address
2826/// can be legally represented as pre-indexed load / store address.
2827bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2828 SDValue &Offset,
2829 ISD::MemIndexedMode &AM,
2830 SelectionDAG &DAG) const {
2831 if (DisablePPCPreinc) return false;
2832
2833 bool isLoad = true;
2834 SDValue Ptr;
2835 EVT VT;
2836 unsigned Alignment;
2837 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2838 Ptr = LD->getBasePtr();
2839 VT = LD->getMemoryVT();
2840 Alignment = LD->getAlignment();
2841 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2842 Ptr = ST->getBasePtr();
2843 VT = ST->getMemoryVT();
2844 Alignment = ST->getAlignment();
2845 isLoad = false;
2846 } else
2847 return false;
2848
2849 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
2850 // instructions because we can fold these into a more efficient instruction
2851 // instead, (such as LXSD).
2852 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
2853 return false;
2854 }
2855
2856 // PowerPC doesn't have preinc load/store instructions for vectors
2857 if (VT.isVector())
2858 return false;
2859
2860 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2861 // Common code will reject creating a pre-inc form if the base pointer
2862 // is a frame index, or if N is a store and the base pointer is either
2863 // the same as or a predecessor of the value being stored. Check for
2864 // those situations here, and try with swapped Base/Offset instead.
2865 bool Swap = false;
2866
2867 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2868 Swap = true;
2869 else if (!isLoad) {
2870 SDValue Val = cast<StoreSDNode>(N)->getValue();
2871 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2872 Swap = true;
2873 }
2874
2875 if (Swap)
2876 std::swap(Base, Offset);
2877
2878 AM = ISD::PRE_INC;
2879 return true;
2880 }
2881
2882 // LDU/STU can only handle immediates that are a multiple of 4.
2883 if (VT != MVT::i64) {
2884 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, None))
2885 return false;
2886 } else {
2887 // LDU/STU need an address with at least 4-byte alignment.
2888 if (Alignment < 4)
2889 return false;
2890
2891 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, Align(4)))
2892 return false;
2893 }
2894
2895 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2896 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2897 // sext i32 to i64 when addr mode is r+i.
2898 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2899 LD->getExtensionType() == ISD::SEXTLOAD &&
2900 isa<ConstantSDNode>(Offset))
2901 return false;
2902 }
2903
2904 AM = ISD::PRE_INC;
2905 return true;
2906}
2907
2908//===----------------------------------------------------------------------===//
2909// LowerOperation implementation
2910//===----------------------------------------------------------------------===//
2911
2912/// Return true if we should reference labels using a PICBase, set the HiOpFlags
2913/// and LoOpFlags to the target MO flags.
2914static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2915 unsigned &HiOpFlags, unsigned &LoOpFlags,
2916 const GlobalValue *GV = nullptr) {
2917 HiOpFlags = PPCII::MO_HA;
2918 LoOpFlags = PPCII::MO_LO;
2919
2920 // Don't use the pic base if not in PIC relocation model.
2921 if (IsPIC) {
2922 HiOpFlags |= PPCII::MO_PIC_FLAG;
2923 LoOpFlags |= PPCII::MO_PIC_FLAG;
2924 }
2925}
2926
2927static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2928 SelectionDAG &DAG) {
2929 SDLoc DL(HiPart);
2930 EVT PtrVT = HiPart.getValueType();
2931 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2932
2933 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2934 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2935
2936 // With PIC, the first instruction is actually "GR+hi(&G)".
2937 if (isPIC)
2938 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2939 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2940
2941 // Generate non-pic code that has direct accesses to the constant pool.
2942 // The address of the global is just (hi(&g)+lo(&g)).
2943 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2944}
2945
2946static void setUsesTOCBasePtr(MachineFunction &MF) {
2947 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2948 FuncInfo->setUsesTOCBasePtr();
2949}
2950
2951static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2952 setUsesTOCBasePtr(DAG.getMachineFunction());
2953}
2954
2955SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
2956 SDValue GA) const {
2957 const bool Is64Bit = Subtarget.isPPC64();
2958 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2959 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
2960 : Subtarget.isAIXABI()
2961 ? DAG.getRegister(PPC::R2, VT)
2962 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2963 SDValue Ops[] = { GA, Reg };
2964 return DAG.getMemIntrinsicNode(
2965 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2966 MachinePointerInfo::getGOT(DAG.getMachineFunction()), None,
2967 MachineMemOperand::MOLoad);
2968}
2969
2970SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2971 SelectionDAG &DAG) const {
2972 EVT PtrVT = Op.getValueType();
2973 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2974 const Constant *C = CP->getConstVal();
2975
2976 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
2977 // The actual address of the GlobalValue is stored in the TOC.
2978 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
2979 if (Subtarget.isUsingPCRelativeCalls()) {
2980 SDLoc DL(CP);
2981 EVT Ty = getPointerTy(DAG.getDataLayout());
2982 SDValue ConstPool = DAG.getTargetConstantPool(
2983 C, Ty, CP->getAlign(), CP->getOffset(), PPCII::MO_PCREL_FLAG);
2984 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
2985 }
2986 setUsesTOCBasePtr(DAG);
2987 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
2988 return getTOCEntry(DAG, SDLoc(CP), GA);
2989 }
2990
2991 unsigned MOHiFlag, MOLoFlag;
2992 bool IsPIC = isPositionIndependent();
2993 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2994
2995 if (IsPIC && Subtarget.isSVR4ABI()) {
2996 SDValue GA =
2997 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), PPCII::MO_PIC_FLAG);
2998 return getTOCEntry(DAG, SDLoc(CP), GA);
2999 }
3000
3001 SDValue CPIHi =
3002 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOHiFlag);
3003 SDValue CPILo =
3004 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOLoFlag);
3005 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
3006}
3007
3008// For 64-bit PowerPC, prefer the more compact relative encodings.
3009// This trades 32 bits per jump table entry for one or two instructions
3010// on the jump site.
3011unsigned PPCTargetLowering::getJumpTableEncoding() const {
3012 if (isJumpTableRelative())
3013 return MachineJumpTableInfo::EK_LabelDifference32;
3014
3015 return TargetLowering::getJumpTableEncoding();
3016}
3017
3018bool PPCTargetLowering::isJumpTableRelative() const {
3019 if (UseAbsoluteJumpTables)
3020 return false;
3021 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
3022 return true;
3023 return TargetLowering::isJumpTableRelative();
3024}
3025
3026SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
3027 SelectionDAG &DAG) const {
3028 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3029 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
3030
3031 switch (getTargetMachine().getCodeModel()) {
3032 case CodeModel::Small:
3033 case CodeModel::Medium:
3034 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
3035 default:
3036 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
3037 getPointerTy(DAG.getDataLayout()));
3038 }
3039}
3040
3041const MCExpr *
3042PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
3043 unsigned JTI,
3044 MCContext &Ctx) const {
3045 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3046 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
3047
3048 switch (getTargetMachine().getCodeModel()) {
3049 case CodeModel::Small:
3050 case CodeModel::Medium:
3051 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
3052 default:
3053 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
3054 }
3055}
3056
3057SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
3058 EVT PtrVT = Op.getValueType();
3059 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3060
3061 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3062 if (Subtarget.isUsingPCRelativeCalls()) {
3063 SDLoc DL(JT);
3064 EVT Ty = getPointerTy(DAG.getDataLayout());
3065 SDValue GA =
3066 DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
3067 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3068 return MatAddr;
3069 }
3070
3071 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3072 // The actual address of the GlobalValue is stored in the TOC.
3073 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3074 setUsesTOCBasePtr(DAG);
3075 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3076 return getTOCEntry(DAG, SDLoc(JT), GA);
3077 }
3078
3079 unsigned MOHiFlag, MOLoFlag;
3080 bool IsPIC = isPositionIndependent();
3081 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3082
3083 if (IsPIC && Subtarget.isSVR4ABI()) {
3084 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3085 PPCII::MO_PIC_FLAG);
3086 return getTOCEntry(DAG, SDLoc(GA), GA);
3087 }
3088
3089 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3090 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3091 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
3092}
3093
3094SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3095 SelectionDAG &DAG) const {
3096 EVT PtrVT = Op.getValueType();
3097 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
3098 const BlockAddress *BA = BASDN->getBlockAddress();
3099
3100 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3101 if (Subtarget.isUsingPCRelativeCalls()) {
3102 SDLoc DL(BASDN);
3103 EVT Ty = getPointerTy(DAG.getDataLayout());
3104 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3105 PPCII::MO_PCREL_FLAG);
3106 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3107 return MatAddr;
3108 }
3109
3110 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3111 // The actual BlockAddress is stored in the TOC.
3112 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3113 setUsesTOCBasePtr(DAG);
3114 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3115 return getTOCEntry(DAG, SDLoc(BASDN), GA);
3116 }
3117
3118 // 32-bit position-independent ELF stores the BlockAddress in the .got.
3119 if (Subtarget.is32BitELFABI() && isPositionIndependent())
3120 return getTOCEntry(
3121 DAG, SDLoc(BASDN),
3122 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
3123
3124 unsigned MOHiFlag, MOLoFlag;
3125 bool IsPIC = isPositionIndependent();
3126 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3127 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3128 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3129 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
3130}
3131
3132SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3133 SelectionDAG &DAG) const {
3134 if (Subtarget.isAIXABI())
3135 return LowerGlobalTLSAddressAIX(Op, DAG);
3136
3137 return LowerGlobalTLSAddressLinux(Op, DAG);
3138}
3139
3140SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
3141 SelectionDAG &DAG) const {
3142 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3143
3144 if (DAG.getTarget().useEmulatedTLS())
3145 report_fatal_error("Emulated TLS is not yet supported on AIX");
3146
3147 SDLoc dl(GA);
3148 const GlobalValue *GV = GA->getGlobal();
3149 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3150
3151 // The general-dynamic model is the only access model supported for now, so
3152 // all the GlobalTLSAddress nodes are lowered with this model.
3153 // We need to generate two TOC entries, one for the variable offset, one for
3154 // the region handle. The global address for the TOC entry of the region
3155 // handle is created with the MO_TLSGD_FLAG flag so we can easily identify
3156 // this entry and add the right relocation.
3157 SDValue VariableOffsetTGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3158 SDValue RegionHandleTGA =
3159 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
3160 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3161 SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
3162 return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,
3163 RegionHandle);
3164}
3165
3166SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
3167 SelectionDAG &DAG) const {
3168 // FIXME: TLS addresses currently use medium model code sequences,
3169 // which is the most useful form. Eventually support for small and
3170 // large models could be added if users need it, at the cost of
3171 // additional complexity.
3172 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3173 if (DAG.getTarget().useEmulatedTLS())
3174 return LowerToTLSEmulatedModel(GA, DAG);
3175
3176 SDLoc dl(GA);
3177 const GlobalValue *GV = GA->getGlobal();
3178 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3179 bool is64bit = Subtarget.isPPC64();
3180 const Module *M = DAG.getMachineFunction().getFunction().getParent();
3181 PICLevel::Level picLevel = M->getPICLevel();
3182
3183 const TargetMachine &TM = getTargetMachine();
3184 TLSModel::Model Model = TM.getTLSModel(GV);
3185
3186 if (Model == TLSModel::LocalExec) {
3187 if (Subtarget.isUsingPCRelativeCalls()) {
3188 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3189 SDValue TGA = DAG.getTargetGlobalAddress(
3190 GV, dl, PtrVT, 0, (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG));
3191 SDValue MatAddr =
3192 DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
3193 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
3194 }
3195
3196 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3197 PPCII::MO_TPREL_HA);
3198 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3199 PPCII::MO_TPREL_LO);
3200 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3201 : DAG.getRegister(PPC::R2, MVT::i32);
3202
3203 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3204 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
3205 }
3206
3207 if (Model == TLSModel::InitialExec) {
3208 bool IsPCRel = Subtarget.isUsingPCRelativeCalls();
3209 SDValue TGA = DAG.getTargetGlobalAddress(
3210 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
3211 SDValue TGATLS = DAG.getTargetGlobalAddress(
3212 GV, dl, PtrVT, 0,
3213 IsPCRel ? (PPCII::MO_TLS | PPCII::MO_PCREL_FLAG) : PPCII::MO_TLS);
3214 SDValue TPOffset;
3215 if (IsPCRel) {
3216 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3217 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
3218 MachinePointerInfo());
3219 } else {
3220 SDValue GOTPtr;
3221 if (is64bit) {
3222 setUsesTOCBasePtr(DAG);
3223 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3224 GOTPtr =
3225 DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
3226 } else {
3227 if (!TM.isPositionIndependent())
3228 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
3229 else if (picLevel == PICLevel::SmallPIC)
3230 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3231 else
3232 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3233 }
3234 TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
3235 }
3236 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
3237 }
3238
3239 if (Model == TLSModel::GeneralDynamic) {
3240 if (Subtarget.isUsingPCRelativeCalls()) {
3241 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3242 PPCII::MO_GOT_TLSGD_PCREL_FLAG);
3243 return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3244 }
3245
3246 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3247 SDValue GOTPtr;
3248 if (is64bit) {
3249 setUsesTOCBasePtr(DAG);
3250 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3251 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
3252 GOTReg, TGA);
3253 } else {
3254 if (picLevel == PICLevel::SmallPIC)
3255 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3256 else
3257 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3258 }
3259 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
3260 GOTPtr, TGA, TGA);
3261 }
3262
3263 if (Model == TLSModel::LocalDynamic) {
3264 if (Subtarget.isUsingPCRelativeCalls()) {
3265 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3266 PPCII::MO_GOT_TLSLD_PCREL_FLAG);
3267 SDValue MatPCRel =
3268 DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3269 return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
3270 }
3271
3272 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3273 SDValue GOTPtr;
3274 if (is64bit) {
3275 setUsesTOCBasePtr(DAG);
3276 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3277 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
3278 GOTReg, TGA);
3279 } else {
3280 if (picLevel == PICLevel::SmallPIC)
3281 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3282 else
3283 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3284 }
3285 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3286 PtrVT, GOTPtr, TGA, TGA);
3287 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3288 PtrVT, TLSAddr, TGA);
3289 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
3290 }
3291
3292 llvm_unreachable("Unknown TLS model!")::llvm::llvm_unreachable_internal("Unknown TLS model!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3292)
;
3293}
3294
3295SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3296 SelectionDAG &DAG) const {
3297 EVT PtrVT = Op.getValueType();
3298 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
3299 SDLoc DL(GSDN);
3300 const GlobalValue *GV = GSDN->getGlobal();
3301
3302 // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
3303 // The actual address of the GlobalValue is stored in the TOC.
3304 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3305 if (Subtarget.isUsingPCRelativeCalls()) {
3306 EVT Ty = getPointerTy(DAG.getDataLayout());
3307 if (isAccessedAsGotIndirect(Op)) {
3308 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3309 PPCII::MO_PCREL_FLAG |
3310 PPCII::MO_GOT_FLAG);
3311 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3312 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
3313 MachinePointerInfo());
3314 return Load;
3315 } else {
3316 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3317 PPCII::MO_PCREL_FLAG);
3318 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3319 }
3320 }
3321 setUsesTOCBasePtr(DAG);
3322 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
3323 return getTOCEntry(DAG, DL, GA);
3324 }
3325
3326 unsigned MOHiFlag, MOLoFlag;
3327 bool IsPIC = isPositionIndependent();
3328 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
3329
3330 if (IsPIC && Subtarget.isSVR4ABI()) {
3331 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3332 GSDN->getOffset(),
3333 PPCII::MO_PIC_FLAG);
3334 return getTOCEntry(DAG, DL, GA);
3335 }
3336
3337 SDValue GAHi =
3338 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
3339 SDValue GALo =
3340 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
3341
3342 return LowerLabelRef(GAHi, GALo, IsPIC, DAG);
3343}
3344
3345SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3346 bool IsStrict = Op->isStrictFPOpcode();
3347 ISD::CondCode CC =
3348 cast<CondCodeSDNode>(Op.getOperand(IsStrict ? 3 : 2))->get();
3349 SDValue LHS = Op.getOperand(IsStrict ? 1 : 0);
3350 SDValue RHS = Op.getOperand(IsStrict ? 2 : 1);
3351 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
3352 EVT LHSVT = LHS.getValueType();
3353 SDLoc dl(Op);
3354
3355 // Soften the setcc with libcall if it is fp128.
3356 if (LHSVT == MVT::f128) {
3357 assert(!Subtarget.hasP9Vector() &&((!Subtarget.hasP9Vector() && "SETCC for f128 is already legal under Power9!"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasP9Vector() && \"SETCC for f128 is already legal under Power9!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3358, __PRETTY_FUNCTION__))
3358 "SETCC for f128 is already legal under Power9!")((!Subtarget.hasP9Vector() && "SETCC for f128 is already legal under Power9!"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.hasP9Vector() && \"SETCC for f128 is already legal under Power9!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3358, __PRETTY_FUNCTION__))
;
3359 softenSetCCOperands(DAG, LHSVT, LHS, RHS, CC, dl, LHS, RHS, Chain,
3360 Op->getOpcode() == ISD::STRICT_FSETCCS);
3361 if (RHS.getNode())
3362 LHS = DAG.getNode(ISD::SETCC, dl, Op.getValueType(), LHS, RHS,
3363 DAG.getCondCode(CC));
3364 if (IsStrict)
3365 return DAG.getMergeValues({LHS, Chain}, dl);
3366 return LHS;
3367 }
3368
3369 assert(!IsStrict && "Don't know how to handle STRICT_FSETCC!")((!IsStrict && "Don't know how to handle STRICT_FSETCC!"
) ? static_cast<void> (0) : __assert_fail ("!IsStrict && \"Don't know how to handle STRICT_FSETCC!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3369, __PRETTY_FUNCTION__))
;
3370
3371 if (Op.getValueType() == MVT::v2i64) {
3372 // When the operands themselves are v2i64 values, we need to do something
3373 // special because VSX has no underlying comparison operations for these.
3374 if (LHS.getValueType() == MVT::v2i64) {
3375 // Equality can be handled by casting to the legal type for Altivec
3376 // comparisons, everything else needs to be expanded.
3377 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3378 return DAG.getNode(
3379 ISD::BITCAST, dl, MVT::v2i64,
3380 DAG.getSetCC(dl, MVT::v4i32,
3381 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, LHS),
3382 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, RHS), CC));
3383 }
3384
3385 return SDValue();
3386 }
3387
3388 // We handle most of these in the usual way.
3389 return Op;
3390 }
3391
3392 // If we're comparing for equality to zero, expose the fact that this is
3393 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
3394 // fold the new nodes.
3395 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
3396 return V;
3397
3398 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
3399 // Leave comparisons against 0 and -1 alone for now, since they're usually
3400 // optimized. FIXME: revisit this when we can custom lower all setcc
3401 // optimizations.
3402 if (C->isAllOnesValue() || C->isNullValue())
3403 return SDValue();
3404 }
3405
3406 // If we have an integer seteq/setne, turn it into a compare against zero
3407 // by xor'ing the rhs with the lhs, which is faster than setting a
3408 // condition register, reading it back out, and masking the correct bit. The
3409 // normal approach here uses sub to do this instead of xor. Using xor exposes
3410 // the result to other bit-twiddling opportunities.
3411 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
3412 EVT VT = Op.getValueType();
3413 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, LHS, RHS);
3414 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
3415 }
3416 return SDValue();
3417}
3418
3419SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3420 SDNode *Node = Op.getNode();
3421 EVT VT = Node->getValueType(0);
3422 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3423 SDValue InChain = Node->getOperand(0);
3424 SDValue VAListPtr = Node->getOperand(1);
3425 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3426 SDLoc dl(Node);
3427
3428 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")((!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")
? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVAARG is PPC32 only\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3428, __PRETTY_FUNCTION__))
;
3429
3430 // gpr_index
3431 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3432 VAListPtr, MachinePointerInfo(SV), MVT::i8);
3433 InChain = GprIndex.getValue(1);
3434
3435 if (VT == MVT::i64) {
3436 // Check if GprIndex is even
3437 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
3438 DAG.getConstant(1, dl, MVT::i32));
3439 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
3440 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
3441 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
3442 DAG.getConstant(1, dl, MVT::i32));
3443 // Align GprIndex to be even if it isn't
3444 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
3445 GprIndex);
3446 }
3447
3448 // fpr index is 1 byte after gpr
3449 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3450 DAG.getConstant(1, dl, MVT::i32));
3451
3452 // fpr
3453 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3454 FprPtr, MachinePointerInfo(SV), MVT::i8);
3455 InChain = FprIndex.getValue(1);
3456
3457 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3458 DAG.getConstant(8, dl, MVT::i32));
3459
3460 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3461 DAG.getConstant(4, dl, MVT::i32));
3462
3463 // areas
3464 SDValue OverflowArea =
3465 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
3466 InChain = OverflowArea.getValue(1);
3467
3468 SDValue RegSaveArea =
3469 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
3470 InChain = RegSaveArea.getValue(1);
3471
3472 // select overflow_area if index > 8
3473 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3474 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
3475
3476 // adjustment constant gpr_index * 4/8
3477 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
3478 VT.isInteger() ? GprIndex : FprIndex,
3479 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3480 MVT::i32));
3481
3482 // OurReg = RegSaveArea + RegConstant
3483 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
3484 RegConstant);
3485
3486 // Floating types are 32 bytes into RegSaveArea
3487 if (VT.isFloatingPoint())
3488 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
3489 DAG.getConstant(32, dl, MVT::i32));
3490
3491 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
3492 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3493 VT.isInteger() ? GprIndex : FprIndex,
3494 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
3495 MVT::i32));
3496
3497 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
3498 VT.isInteger() ? VAListPtr : FprPtr,
3499 MachinePointerInfo(SV), MVT::i8);
3500
3501 // determine if we should load from reg_save_area or overflow_area
3502 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3503
3504 // increase overflow_area by 4/8 if gpr/fpr > 8
3505 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
3506 DAG.getConstant(VT.isInteger() ? 4 : 8,
3507 dl, MVT::i32));
3508
3509 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
3510 OverflowAreaPlusN);
3511
3512 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
3513 MachinePointerInfo(), MVT::i32);
3514
3515 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
3516}
3517
3518SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3519 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only")((!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVACOPY is PPC32 only\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3519, __PRETTY_FUNCTION__))
;
3520
3521 // We have to copy the entire va_list struct:
3522 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3523 return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2),
3524 DAG.getConstant(12, SDLoc(Op), MVT::i32), Align(8),
3525 false, true, false, MachinePointerInfo(),
3526 MachinePointerInfo());
3527}
3528
3529SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3530 SelectionDAG &DAG) const {
3531 if (Subtarget.isAIXABI())
3532 report_fatal_error("ADJUST_TRAMPOLINE operation is not supported on AIX.");
3533
3534 return Op.getOperand(0);
3535}
3536
3537SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3538 SelectionDAG &DAG) const {
3539 if (Subtarget.isAIXABI())
3540 report_fatal_error("INIT_TRAMPOLINE operation is not supported on AIX.");
3541
3542 SDValue Chain = Op.getOperand(0);
3543 SDValue Trmp = Op.getOperand(1); // trampoline
3544 SDValue FPtr = Op.getOperand(2); // nested function
3545 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3546 SDLoc dl(Op);
3547
3548 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3549 bool isPPC64 = (PtrVT == MVT::i64);
3550 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3551
3552 TargetLowering::ArgListTy Args;
3553 TargetLowering::ArgListEntry Entry;
3554
3555 Entry.Ty = IntPtrTy;
3556 Entry.Node = Trmp; Args.push_back(Entry);
3557
3558 // TrampSize == (isPPC64 ? 48 : 40);
3559 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3560 isPPC64 ? MVT::i64 : MVT::i32);
3561 Args.push_back(Entry);
3562
3563 Entry.Node = FPtr; Args.push_back(Entry);
3564 Entry.Node = Nest; Args.push_back(Entry);
3565
3566 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3567 TargetLowering::CallLoweringInfo CLI(DAG);
3568 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3569 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3570 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3571
3572 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3573 return CallResult.second;
3574}
3575
3576SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3577 MachineFunction &MF = DAG.getMachineFunction();
3578 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3579 EVT PtrVT = getPointerTy(MF.getDataLayout());
3580
3581 SDLoc dl(Op);
3582
3583 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) {
3584 // vastart just stores the address of the VarArgsFrameIndex slot into the
3585 // memory location argument.
3586 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3587 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3588 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3589 MachinePointerInfo(SV));
3590 }
3591
3592 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3593 // We suppose the given va_list is already allocated.
3594 //
3595 // typedef struct {
3596 // char gpr; /* index into the array of 8 GPRs
3597 // * stored in the register save area
3598 // * gpr=0 corresponds to r3,
3599 // * gpr=1 to r4, etc.
3600 // */
3601 // char fpr; /* index into the array of 8 FPRs
3602 // * stored in the register save area
3603 // * fpr=0 corresponds to f1,
3604 // * fpr=1 to f2, etc.
3605 // */
3606 // char *overflow_arg_area;
3607 // /* location on stack that holds
3608 // * the next overflow argument
3609 // */
3610 // char *reg_save_area;
3611 // /* where r3:r10 and f1:f8 (if saved)
3612 // * are stored
3613 // */
3614 // } va_list[1];
3615
3616 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3617 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3618 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3619 PtrVT);
3620 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3621 PtrVT);
3622
3623 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3624 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3625
3626 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3627 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3628
3629 uint64_t FPROffset = 1;
3630 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3631
3632 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3633
3634 // Store first byte : number of int regs
3635 SDValue firstStore =
3636 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3637 MachinePointerInfo(SV), MVT::i8);
3638 uint64_t nextOffset = FPROffset;
3639 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3640 ConstFPROffset);
3641
3642 // Store second byte : number of float regs
3643 SDValue secondStore =
3644 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3645 MachinePointerInfo(SV, nextOffset), MVT::i8);
3646 nextOffset += StackOffset;
3647 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3648
3649 // Store second word : arguments given on stack
3650 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3651 MachinePointerInfo(SV, nextOffset));
3652 nextOffset += FrameOffset;
3653 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3654
3655 // Store third word : arguments given in registers
3656 return DAG.getStore(thirdStore, dl, FR, nextPtr,
3657 MachinePointerInfo(SV, nextOffset));
3658}
3659
3660/// FPR - The set of FP registers that should be allocated for arguments
3661/// on Darwin and AIX.
3662static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3663 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3664 PPC::F11, PPC::F12, PPC::F13};
3665
3666/// CalculateStackSlotSize - Calculates the size reserved for this argument on
3667/// the stack.
3668static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3669 unsigned PtrByteSize) {
3670 unsigned ArgSize = ArgVT.getStoreSize();
3671 if (Flags.isByVal())
3672 ArgSize = Flags.getByValSize();
3673
3674 // Round up to multiples of the pointer size, except for array members,
3675 // which are always packed.
3676 if (!Flags.isInConsecutiveRegs())
3677 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3678
3679 return ArgSize;
3680}
3681
3682/// CalculateStackSlotAlignment - Calculates the alignment of this argument
3683/// on the stack.
3684static Align CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3685 ISD::ArgFlagsTy Flags,
3686 unsigned PtrByteSize) {
3687 Align Alignment(PtrByteSize);
3688
3689 // Altivec parameters are padded to a 16 byte boundary.
3690 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3691 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3692 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3693 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3694 Alignment = Align(16);
3695
3696 // ByVal parameters are aligned as requested.
3697 if (Flags.isByVal()) {
3698 auto BVAlign = Flags.getNonZeroByValAlign();
3699 if (BVAlign > PtrByteSize) {
3700 if (BVAlign.value() % PtrByteSize != 0)
3701 llvm_unreachable(::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3702)
3702 "ByVal alignment is not a multiple of the pointer size")::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3702)
;
3703
3704 Alignment = BVAlign;
3705 }
3706 }
3707
3708 // Array members are always packed to their original alignment.
3709 if (Flags.isInConsecutiveRegs()) {
3710 // If the array member was split into multiple registers, the first
3711 // needs to be aligned to the size of the full type. (Except for
3712 // ppcf128, which is only aligned as its f64 components.)
3713 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3714 Alignment = Align(OrigVT.getStoreSize());
3715 else
3716 Alignment = Align(ArgVT.getStoreSize());
3717 }
3718
3719 return Alignment;
3720}
3721
3722/// CalculateStackSlotUsed - Return whether this argument will use its
3723/// stack slot (instead of being passed in registers). ArgOffset,
3724/// AvailableFPRs, and AvailableVRs must hold the current argument
3725/// position, and will be updated to account for this argument.
3726static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags,
3727 unsigned PtrByteSize, unsigned LinkageSize,
3728 unsigned ParamAreaSize, unsigned &ArgOffset,
3729 unsigned &AvailableFPRs,
3730 unsigned &AvailableVRs) {
3731 bool UseMemory = false;
3732
3733 // Respect alignment of argument on the stack.
3734 Align Alignment =
3735 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3736 ArgOffset = alignTo(ArgOffset, Alignment);
3737 // If there's no space left in the argument save area, we must
3738 // use memory (this check also catches zero-sized arguments).
3739 if (ArgOffset >= LinkageSize + ParamAreaSize)
3740 UseMemory = true;
3741
3742 // Allocate argument on the stack.
3743 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3744 if (Flags.isInConsecutiveRegsLast())
3745 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3746 // If we overran the argument save area, we must use memory
3747 // (this check catches arguments passed partially in memory)
3748 if (ArgOffset > LinkageSize + ParamAreaSize)
3749 UseMemory = true;
3750
3751 // However, if the argument is actually passed in an FPR or a VR,
3752 // we don't use memory after all.
3753 if (!Flags.isByVal()) {
3754 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
3755 if (AvailableFPRs > 0) {
3756 --AvailableFPRs;
3757 return false;
3758 }
3759 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3760 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3761 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3762 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3763 if (AvailableVRs > 0) {
3764 --AvailableVRs;
3765 return false;
3766 }
3767 }
3768
3769 return UseMemory;
3770}
3771
3772/// EnsureStackAlignment - Round stack frame size up from NumBytes to
3773/// ensure minimum alignment required for target.
3774static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3775 unsigned NumBytes) {
3776 return alignTo(NumBytes, Lowering->getStackAlign());
3777}
3778
3779SDValue PPCTargetLowering::LowerFormalArguments(
3780 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3781 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3782 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3783 if (Subtarget.isAIXABI())
3784 return LowerFormalArguments_AIX(Chain, CallConv, isVarArg, Ins, dl, DAG,
3785 InVals);
3786 if (Subtarget.is64BitELFABI())
3787 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3788 InVals);
3789 assert(Subtarget.is32BitELFABI())((Subtarget.is32BitELFABI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.is32BitELFABI()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3789, __PRETTY_FUNCTION__))
;
3790 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3791 InVals);
3792}
3793
3794SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3795 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3796 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3797 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3798
3799 // 32-bit SVR4 ABI Stack Frame Layout:
3800 // +-----------------------------------+
3801 // +--> | Back chain |
3802 // | +-----------------------------------+
3803 // | | Floating-point register save area |
3804 // | +-----------------------------------+
3805 // | | General register save area |
3806 // | +-----------------------------------+
3807 // | | CR save word |
3808 // | +-----------------------------------+
3809 // | | VRSAVE save word |
3810 // | +-----------------------------------+
3811 // | | Alignment padding |
3812 // | +-----------------------------------+
3813 // | | Vector register save area |
3814 // | +-----------------------------------+
3815 // | | Local variable space |
3816 // | +-----------------------------------+
3817 // | | Parameter list area |
3818 // | +-----------------------------------+
3819 // | | LR save word |
3820 // | +-----------------------------------+
3821 // SP--> +--- | Back chain |
3822 // +-----------------------------------+
3823 //
3824 // Specifications:
3825 // System V Application Binary Interface PowerPC Processor Supplement
3826 // AltiVec Technology Programming Interface Manual
3827
3828 MachineFunction &MF = DAG.getMachineFunction();
3829 MachineFrameInfo &MFI = MF.getFrameInfo();
3830 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3831
3832 EVT PtrVT = getPointerTy(MF.getDataLayout());
3833 // Potential tail calls could cause overwriting of argument stack slots.
3834 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3835 (CallConv == CallingConv::Fast));
3836 const Align PtrAlign(4);
3837
3838 // Assign locations to all of the incoming arguments.
3839 SmallVector<CCValAssign, 16> ArgLocs;
3840 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3841 *DAG.getContext());
3842
3843 // Reserve space for the linkage area on the stack.
3844 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3845 CCInfo.AllocateStack(LinkageSize, PtrAlign);
3846 if (useSoftFloat())
3847 CCInfo.PreAnalyzeFormalArguments(Ins);
3848
3849 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3850 CCInfo.clearWasPPCF128();
3851
3852 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3853 CCValAssign &VA = ArgLocs[i];
3854
3855 // Arguments stored in registers.
3856 if (VA.isRegLoc()) {
3857 const TargetRegisterClass *RC;
3858 EVT ValVT = VA.getValVT();
3859
3860 switch (ValVT.getSimpleVT().SimpleTy) {
3861 default:
3862 llvm_unreachable("ValVT not supported by formal arguments Lowering")::llvm::llvm_unreachable_internal("ValVT not supported by formal arguments Lowering"
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3862)
;
3863 case MVT::i1:
3864 case MVT::i32:
3865 RC = &PPC::GPRCRegClass;
3866 break;
3867 case MVT::f32:
3868 if (Subtarget.hasP8Vector())
3869 RC = &PPC::VSSRCRegClass;
3870 else if (Subtarget.hasSPE())
3871 RC = &PPC::GPRCRegClass;
3872 else
3873 RC = &PPC::F4RCRegClass;
3874 break;
3875 case MVT::f64:
3876 if (Subtarget.hasVSX())
3877 RC = &PPC::VSFRCRegClass;
3878 else if (Subtarget.hasSPE())
3879 // SPE passes doubles in GPR pairs.
3880 RC = &PPC::GPRCRegClass;
3881 else
3882 RC = &PPC::F8RCRegClass;
3883 break;
3884 case MVT::v16i8:
3885 case MVT::v8i16:
3886 case MVT::v4i32:
3887 RC = &PPC::VRRCRegClass;
3888 break;
3889 case MVT::v4f32:
3890 RC = &PPC::VRRCRegClass;
3891 break;
3892 case MVT::v2f64:
3893 case MVT::v2i64:
3894 RC = &PPC::VRRCRegClass;
3895 break;
3896 }
3897
3898 SDValue ArgValue;
3899 // Transform the arguments stored in physical registers into
3900 // virtual ones.
3901 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
3902 assert(i + 1 < e && "No second half of double precision argument")((i + 1 < e && "No second half of double precision argument"
) ? static_cast<void> (0) : __assert_fail ("i + 1 < e && \"No second half of double precision argument\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3902, __PRETTY_FUNCTION__))
;
3903 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC);
3904 unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC);
3905 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32);
3906 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32);
3907 if (!Subtarget.isLittleEndian())
3908 std::swap (ArgValueLo, ArgValueHi);
3909 ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo,
3910 ArgValueHi);
3911 } else {
3912 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3913 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3914 ValVT == MVT::i1 ? MVT::i32 : ValVT);
3915 if (ValVT == MVT::i1)
3916 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3917 }
3918
3919 InVals.push_back(ArgValue);
3920 } else {
3921 // Argument stored in memory.
3922 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3922, __PRETTY_FUNCTION__))
;
3923
3924 // Get the extended size of the argument type in stack
3925 unsigned ArgSize = VA.getLocVT().getStoreSize();
3926 // Get the actual size of the argument type
3927 unsigned ObjSize = VA.getValVT().getStoreSize();
3928 unsigned ArgOffset = VA.getLocMemOffset();
3929 // Stack objects in PPC32 are right justified.
3930 ArgOffset += ArgSize - ObjSize;
3931 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
3932
3933 // Create load nodes to retrieve arguments from the stack.
3934 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3935 InVals.push_back(
3936 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3937 }
3938 }
3939
3940 // Assign locations to all of the incoming aggregate by value arguments.
3941 // Aggregates passed by value are stored in the local variable space of the
3942 // caller's stack frame, right above the parameter list area.
3943 SmallVector<CCValAssign, 16> ByValArgLocs;
3944 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3945 ByValArgLocs, *DAG.getContext());
3946
3947 // Reserve stack space for the allocations in CCInfo.
3948 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrAlign);
3949
3950 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3951
3952 // Area that is at least reserved in the caller of this function.
3953 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3954 MinReservedArea = std::max(MinReservedArea, LinkageSize);
3955
3956 // Set the size that is at least reserved in caller of this function. Tail
3957 // call optimized function's reserved stack space needs to be aligned so that
3958 // taking the difference between two stack areas will result in an aligned
3959 // stack.
3960 MinReservedArea =
3961 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3962 FuncInfo->setMinReservedArea(MinReservedArea);
3963
3964 SmallVector<SDValue, 8> MemOps;
3965
3966 // If the function takes variable number of arguments, make a frame index for
3967 // the start of the first vararg value... for expansion of llvm.va_start.
3968 if (isVarArg) {
3969 static const MCPhysReg GPArgRegs[] = {
3970 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3971 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3972 };
3973 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3974
3975 static const MCPhysReg FPArgRegs[] = {
3976 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3977 PPC::F8
3978 };
3979 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3980
3981 if (useSoftFloat() || hasSPE())
3982 NumFPArgRegs = 0;
3983
3984 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3985 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3986
3987 // Make room for NumGPArgRegs and NumFPArgRegs.
3988 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3989 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3990
3991 FuncInfo->setVarArgsStackOffset(
3992 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3993 CCInfo.getNextStackOffset(), true));
3994
3995 FuncInfo->setVarArgsFrameIndex(
3996 MFI.CreateStackObject(Depth, Align(8), false));
3997 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3998
3999 // The fixed integer arguments of a variadic function are stored to the
4000 // VarArgsFrameIndex on the stack so that they may be loaded by
4001 // dereferencing the result of va_next.
4002 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
4003 // Get an existing live-in vreg, or add a new one.
4004 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
4005 if (!VReg)
4006 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
4007
4008 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4009 SDValue Store =
4010 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4011 MemOps.push_back(Store);
4012 // Increment the address by four for the next argument to store
4013 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4014 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4015 }
4016
4017 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
4018 // is set.
4019 // The double arguments are stored to the VarArgsFrameIndex
4020 // on the stack.
4021 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
4022 // Get an existing live-in vreg, or add a new one.
4023 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
4024 if (!VReg)
4025 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
4026
4027 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
4028 SDValue Store =
4029 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4030 MemOps.push_back(Store);
4031 // Increment the address by eight for the next argument to store
4032 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
4033 PtrVT);
4034 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4035 }
4036 }
4037
4038 if (!MemOps.empty())
4039 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4040
4041 return Chain;
4042}
4043
4044// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4045// value to MVT::i64 and then truncate to the correct register size.
4046SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
4047 EVT ObjectVT, SelectionDAG &DAG,
4048 SDValue ArgVal,
4049 const SDLoc &dl) const {
4050 if (Flags.isSExt())
4051 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
4052 DAG.getValueType(ObjectVT));
4053 else if (Flags.isZExt())
4054 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
4055 DAG.getValueType(ObjectVT));
4056
4057 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
4058}
4059
4060SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
4061 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4062 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4063 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4064 // TODO: add description of PPC stack frame format, or at least some docs.
4065 //
4066 bool isELFv2ABI = Subtarget.isELFv2ABI();
4067 bool isLittleEndian = Subtarget.isLittleEndian();
4068 MachineFunction &MF = DAG.getMachineFunction();
4069 MachineFrameInfo &MFI = MF.getFrameInfo();
4070 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4071
4072 assert(!(CallConv == CallingConv::Fast && isVarArg) &&((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4073, __PRETTY_FUNCTION__))
4073 "fastcc not supported on varargs functions")((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4073, __PRETTY_FUNCTION__))
;
4074
4075 EVT PtrVT = getPointerTy(MF.getDataLayout());
4076 // Potential tail calls could cause overwriting of argument stack slots.
4077 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4078 (CallConv == CallingConv::Fast));
4079 unsigned PtrByteSize = 8;
4080 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4081
4082 static const MCPhysReg GPR[] = {
4083 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4084 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4085 };
4086 static const MCPhysReg VR[] = {
4087 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4088 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4089 };
4090
4091 const unsigned Num_GPR_Regs = array_lengthof(GPR);
4092 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4093 const unsigned Num_VR_Regs = array_lengthof(VR);
4094
4095 // Do a first pass over the arguments to determine whether the ABI
4096 // guarantees that our caller has allocated the parameter save area
4097 // on its stack frame. In the ELFv1 ABI, this is always the case;
4098 // in the ELFv2 ABI, it is true if this is a vararg function or if
4099 // any parameter is located in a stack slot.
4100
4101 bool HasParameterArea = !isELFv2ABI || isVarArg;
4102 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
4103 unsigned NumBytes = LinkageSize;
4104 unsigned AvailableFPRs = Num_FPR_Regs;
4105 unsigned AvailableVRs = Num_VR_Regs;
4106 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4107 if (Ins[i].Flags.isNest())
4108 continue;
4109
4110 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
4111 PtrByteSize, LinkageSize, ParamAreaSize,
4112 NumBytes, AvailableFPRs, AvailableVRs))
4113 HasParameterArea = true;
4114 }
4115
4116 // Add DAG nodes to load the arguments or copy them out of registers. On
4117 // entry to a function on PPC, the arguments start after the linkage area,
4118 // although the first ones are often in registers.
4119
4120 unsigned ArgOffset = LinkageSize;
4121 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4122 SmallVector<SDValue, 8> MemOps;
4123 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4124 unsigned CurArgIdx = 0;
4125 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4126 SDValue ArgVal;
4127 bool needsLoad = false;
4128 EVT ObjectVT = Ins[ArgNo].VT;
4129 EVT OrigVT = Ins[ArgNo].ArgVT;
4130 unsigned ObjSize = ObjectVT.getStoreSize();
4131 unsigned ArgSize = ObjSize;
4132 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4133 if (Ins[ArgNo].isOrigArg()) {
4134 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4135 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4136 }
4137 // We re-align the argument offset for each argument, except when using the
4138 // fast calling convention, when we need to make sure we do that only when
4139 // we'll actually use a stack slot.
4140 unsigned CurArgOffset;
4141 Align Alignment;
4142 auto ComputeArgOffset = [&]() {
4143 /* Respect alignment of argument on the stack. */
4144 Alignment =
4145 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
4146 ArgOffset = alignTo(ArgOffset, Alignment);
4147 CurArgOffset = ArgOffset;
4148 };
4149
4150 if (CallConv != CallingConv::Fast) {
4151 ComputeArgOffset();
4152
4153 /* Compute GPR index associated with argument offset. */
4154 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4155 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
4156 }
4157
4158 // FIXME the codegen can be much improved in some cases.
4159 // We do not have to keep everything in memory.
4160 if (Flags.isByVal()) {
4161 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4161, __PRETTY_FUNCTION__))
;
4162
4163 if (CallConv == CallingConv::Fast)
4164 ComputeArgOffset();
4165
4166 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4167 ObjSize = Flags.getByValSize();
4168 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4169 // Empty aggregate parameters do not take up registers. Examples:
4170 // struct { } a;
4171 // union { } b;
4172 // int c[0];
4173 // etc. However, we have to provide a place-holder in InVals, so
4174 // pretend we have an 8-byte item at the current address for that
4175 // purpose.
4176 if (!ObjSize) {
4177 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4178 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4179 InVals.push_back(FIN);
4180 continue;
4181 }
4182
4183 // Create a stack object covering all stack doublewords occupied
4184 // by the argument. If the argument is (fully or partially) on
4185 // the stack, or if the argument is fully in registers but the
4186 // caller has allocated the parameter save anyway, we can refer
4187 // directly to the caller's stack frame. Otherwise, create a
4188 // local copy in our own frame.
4189 int FI;
4190 if (HasParameterArea ||
4191 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
4192 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
4193 else
4194 FI = MFI.CreateStackObject(ArgSize, Alignment, false);
4195 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4196
4197 // Handle aggregates smaller than 8 bytes.
4198 if (ObjSize < PtrByteSize) {
4199 // The value of the object is its address, which differs from the
4200 // address of the enclosing doubleword on big-endian systems.
4201 SDValue Arg = FIN;
4202 if (!isLittleEndian) {
4203 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
4204 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
4205 }
4206 InVals.push_back(Arg);
4207
4208 if (GPR_idx != Num_GPR_Regs) {
4209 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4210 FuncInfo->addLiveInAttr(VReg, Flags);
4211 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4212 SDValue Store;
4213
4214 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
4215 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
4216 (ObjSize == 2 ? MVT::i16 : MVT::i32));
4217 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
4218 MachinePointerInfo(&*FuncArg), ObjType);
4219 } else {
4220 // For sizes that don't fit a truncating store (3, 5, 6, 7),
4221 // store the whole register as-is to the parameter save area
4222 // slot.
4223 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4224 MachinePointerInfo(&*FuncArg));
4225 }
4226
4227 MemOps.push_back(Store);
4228 }
4229 // Whether we copied from a register or not, advance the offset
4230 // into the parameter save area by a full doubleword.
4231 ArgOffset += PtrByteSize;
4232 continue;
4233 }
4234
4235 // The value of the object is its address, which is the address of
4236 // its first stack doubleword.
4237 InVals.push_back(FIN);
4238
4239 // Store whatever pieces of the object are in registers to memory.
4240 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4241 if (GPR_idx == Num_GPR_Regs)
4242 break;
4243
4244 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4245 FuncInfo->addLiveInAttr(VReg, Flags);
4246 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4247 SDValue Addr = FIN;
4248 if (j) {
4249 SDValue Off = DAG.getConstant(j, dl, PtrVT);
4250 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
4251 }
4252 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
4253 MachinePointerInfo(&*FuncArg, j));
4254 MemOps.push_back(Store);
4255 ++GPR_idx;
4256 }
4257 ArgOffset += ArgSize;
4258 continue;
4259 }
4260
4261 switch (ObjectVT.getSimpleVT().SimpleTy) {
4262 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4262)
;
4263 case MVT::i1:
4264 case MVT::i32:
4265 case MVT::i64:
4266 if (Flags.isNest()) {
4267 // The 'nest' parameter, if any, is passed in R11.
4268 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
4269 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4270
4271 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4272 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4273
4274 break;
4275 }
4276
4277 // These can be scalar arguments or elements of an integer array type
4278 // passed directly. Clang may use those instead of "byval" aggregate
4279 // types to avoid forcing arguments to memory unnecessarily.
4280 if (GPR_idx != Num_GPR_Regs) {
4281 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4282 FuncInfo->addLiveInAttr(VReg, Flags);
4283 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4284
4285 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4286 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4287 // value to MVT::i64 and then truncate to the correct register size.
4288 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4289 } else {
4290 if (CallConv == CallingConv::Fast)
4291 ComputeArgOffset();
4292
4293 needsLoad = true;
4294 ArgSize = PtrByteSize;
4295 }
4296 if (CallConv != CallingConv::Fast || needsLoad)
4297 ArgOffset += 8;
4298 break;
4299
4300 case MVT::f32:
4301 case MVT::f64:
4302 // These can be scalar arguments or elements of a float array type
4303 // passed directly. The latter are used to implement ELFv2 homogenous
4304 // float aggregates.
4305 if (FPR_idx != Num_FPR_Regs) {
4306 unsigned VReg;
4307
4308 if (ObjectVT == MVT::f32)
4309 VReg = MF.addLiveIn(FPR[FPR_idx],
4310 Subtarget.hasP8Vector()
4311 ? &PPC::VSSRCRegClass
4312 : &PPC::F4RCRegClass);
4313 else
4314 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
4315 ? &PPC::VSFRCRegClass
4316 : &PPC::F8RCRegClass);
4317
4318 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4319 ++FPR_idx;
4320 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
4321 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4322 // once we support fp <-> gpr moves.
4323
4324 // This can only ever happen in the presence of f32 array types,
4325 // since otherwise we never run out of FPRs before running out
4326 // of GPRs.
4327 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4328 FuncInfo->addLiveInAttr(VReg, Flags);
4329 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4330
4331 if (ObjectVT == MVT::f32) {
4332 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
4333 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
4334 DAG.getConstant(32, dl, MVT::i32));
4335 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
4336 }
4337
4338 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
4339 } else {
4340 if (CallConv == CallingConv::Fast)
4341 ComputeArgOffset();
4342
4343 needsLoad = true;
4344 }
4345
4346 // When passing an array of floats, the array occupies consecutive
4347 // space in the argument area; only round up to the next doubleword
4348 // at the end of the array. Otherwise, each float takes 8 bytes.
4349 if (CallConv != CallingConv::Fast || needsLoad) {
4350 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
4351 ArgOffset += ArgSize;
4352 if (Flags.isInConsecutiveRegsLast())
4353 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4354 }
4355 break;
4356 case MVT::v4f32:
4357 case MVT::v4i32:
4358 case MVT::v8i16:
4359 case MVT::v16i8:
4360 case MVT::v2f64:
4361 case MVT::v2i64:
4362 case MVT::v1i128:
4363 case MVT::f128:
4364 // These can be scalar arguments or elements of a vector array type
4365 // passed directly. The latter are used to implement ELFv2 homogenous
4366 // vector aggregates.
4367 if (VR_idx != Num_VR_Regs) {
4368 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4369 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4370 ++VR_idx;
4371 } else {
4372 if (CallConv == CallingConv::Fast)
4373 ComputeArgOffset();
4374 needsLoad = true;
4375 }
4376 if (CallConv != CallingConv::Fast || needsLoad)
4377 ArgOffset += 16;
4378 break;
4379 }
4380
4381 // We need to load the argument to a virtual register if we determined
4382 // above that we ran out of physical registers of the appropriate type.
4383 if (needsLoad) {
4384 if (ObjSize < ArgSize && !isLittleEndian)
4385 CurArgOffset += ArgSize - ObjSize;
4386 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
4387 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4388 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4389 }
4390
4391 InVals.push_back(ArgVal);
4392 }
4393
4394 // Area that is at least reserved in the caller of this function.
4395 unsigned MinReservedArea;
4396 if (HasParameterArea)
4397 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
4398 else
4399 MinReservedArea = LinkageSize;
4400
4401 // Set the size that is at least reserved in caller of this function. Tail
4402 // call optimized functions' reserved stack space needs to be aligned so that
4403 // taking the difference between two stack areas will result in an aligned
4404 // stack.
4405 MinReservedArea =
4406 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4407 FuncInfo->setMinReservedArea(MinReservedArea);
4408
4409 // If the function takes variable number of arguments, make a frame index for
4410 // the start of the first vararg value... for expansion of llvm.va_start.
4411 // On ELFv2ABI spec, it writes:
4412 // C programs that are intended to be *portable* across different compilers
4413 // and architectures must use the header file <stdarg.h> to deal with variable
4414 // argument lists.
4415 if (isVarArg && MFI.hasVAStart()) {
4416 int Depth = ArgOffset;
4417
4418 FuncInfo->setVarArgsFrameIndex(
4419 MFI.CreateFixedObject(PtrByteSize, Depth, true));
4420 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4421
4422 // If this function is vararg, store any remaining integer argument regs
4423 // to their spots on the stack so that they may be loaded by dereferencing
4424 // the result of va_next.
4425 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4426 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4427 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4428 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4429 SDValue Store =
4430 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4431 MemOps.push_back(Store);
4432 // Increment the address by four for the next argument to store
4433 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4434 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4435 }
4436 }
4437
4438 if (!MemOps.empty())
4439 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4440
4441 return Chain;
4442}
4443
4444/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4445/// adjusted to accommodate the arguments for the tailcall.
4446static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4447 unsigned ParamSize) {
4448
4449 if (!isTailCall) return 0;
4450
4451 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4452 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4453 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4454 // Remember only if the new adjustment is bigger.
4455 if (SPDiff < FI->getTailCallSPDelta())
4456 FI->setTailCallSPDelta(SPDiff);
4457
4458 return SPDiff;
4459}
4460
4461static bool isFunctionGlobalAddress(SDValue Callee);
4462
4463static bool callsShareTOCBase(const Function *Caller, SDValue Callee,
4464 const TargetMachine &TM) {
4465 // It does not make sense to call callsShareTOCBase() with a caller that
4466 // is PC Relative since PC Relative callers do not have a TOC.
4467#ifndef NDEBUG
4468 const PPCSubtarget *STICaller = &TM.getSubtarget<PPCSubtarget>(*Caller);
4469 assert(!STICaller->isUsingPCRelativeCalls() &&((!STICaller->isUsingPCRelativeCalls() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? static_cast<void> (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4470, __PRETTY_FUNCTION__))
4470 "PC Relative callers do not have a TOC and cannot share a TOC Base")((!STICaller->isUsingPCRelativeCalls() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? static_cast<void> (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4470, __PRETTY_FUNCTION__))
;
4471#endif
4472
4473 // Callee is either a GlobalAddress or an ExternalSymbol. ExternalSymbols
4474 // don't have enough information to determine if the caller and callee share
4475 // the same TOC base, so we have to pessimistically assume they don't for
4476 // correctness.
4477 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4478 if (!G)
4479 return false;
4480
4481 const GlobalValue *GV = G->getGlobal();
4482
4483 // If the callee is preemptable, then the static linker will use a plt-stub
4484 // which saves the toc to the stack, and needs a nop after the call
4485 // instruction to convert to a toc-restore.
4486 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4487 return false;
4488
4489 // Functions with PC Relative enabled may clobber the TOC in the same DSO.
4490 // We may need a TOC restore in the situation where the caller requires a
4491 // valid TOC but the callee is PC Relative and does not.
4492 const Function *F = dyn_cast<Function>(GV);
4493 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
4494
4495 // If we have an Alias we can try to get the function from there.
4496 if (Alias) {
4497 const GlobalObject *GlobalObj = Alias->getBaseObject();
4498 F = dyn_cast<Function>(GlobalObj);
4499 }
4500
4501 // If we still have no valid function pointer we do not have enough
4502 // information to determine if the callee uses PC Relative calls so we must
4503 // assume that it does.
4504 if (!F)
4505 return false;
4506
4507 // If the callee uses PC Relative we cannot guarantee that the callee won't
4508 // clobber the TOC of the caller and so we must assume that the two
4509 // functions do not share a TOC base.
4510 const PPCSubtarget *STICallee = &TM.getSubtarget<PPCSubtarget>(*F);
4511 if (STICallee->isUsingPCRelativeCalls())
4512 return false;
4513
4514 // If the GV is not a strong definition then we need to assume it can be
4515 // replaced by another function at link time. The function that replaces
4516 // it may not share the same TOC as the caller since the callee may be
4517 // replaced by a PC Relative version of the same function.
4518 if (!GV->isStrongDefinitionForLinker())
4519 return false;
4520
4521 // The medium and large code models are expected to provide a sufficiently
4522 // large TOC to provide all data addressing needs of a module with a
4523 // single TOC.
4524 if (CodeModel::Medium == TM.getCodeModel() ||
4525 CodeModel::Large == TM.getCodeModel())
4526 return true;
4527
4528 // Any explicitly-specified sections and section prefixes must also match.
4529 // Also, if we're using -ffunction-sections, then each function is always in
4530 // a different section (the same is true for COMDAT functions).
4531 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4532 GV->getSection() != Caller->getSection())
4533 return false;
4534 if (const auto *F = dyn_cast<Function>(GV)) {
4535 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4536 return false;
4537 }
4538
4539 return true;
4540}
4541
4542static bool
4543needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4544 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4545 assert(Subtarget.is64BitELFABI())((Subtarget.is64BitELFABI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.is64BitELFABI()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4545, __PRETTY_FUNCTION__))
;
4546
4547 const unsigned PtrByteSize = 8;
4548 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4549
4550 static const MCPhysReg GPR[] = {
4551 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4552 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4553 };
4554 static const MCPhysReg VR[] = {
4555 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4556 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4557 };
4558
4559 const unsigned NumGPRs = array_lengthof(GPR);
4560 const unsigned NumFPRs = 13;
4561 const unsigned NumVRs = array_lengthof(VR);
4562 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4563
4564 unsigned NumBytes = LinkageSize;
4565 unsigned AvailableFPRs = NumFPRs;
4566 unsigned AvailableVRs = NumVRs;
4567
4568 for (const ISD::OutputArg& Param : Outs) {
4569 if (Param.Flags.isNest()) continue;
4570
4571 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags, PtrByteSize,
4572 LinkageSize, ParamAreaSize, NumBytes,
4573 AvailableFPRs, AvailableVRs))
4574 return true;
4575 }
4576 return false;
4577}
4578
4579static bool hasSameArgumentList(const Function *CallerFn, const CallBase &CB) {
4580 if (CB.arg_size() != CallerFn->arg_size())
4581 return false;
4582
4583 auto CalleeArgIter = CB.arg_begin();
4584 auto CalleeArgEnd = CB.arg_end();
4585 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4586
4587 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4588 const Value* CalleeArg = *CalleeArgIter;
4589 const Value* CallerArg = &(*CallerArgIter);
4590 if (CalleeArg == CallerArg)
4591 continue;
4592
4593 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4594 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4595 // }
4596 // 1st argument of callee is undef and has the same type as caller.
4597 if (CalleeArg->getType() == CallerArg->getType() &&
4598 isa<UndefValue>(CalleeArg))
4599 continue;
4600
4601 return false;
4602 }
4603
4604 return true;
4605}
4606
4607// Returns true if TCO is possible between the callers and callees
4608// calling conventions.
4609static bool
4610areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4611 CallingConv::ID CalleeCC) {
4612 // Tail calls are possible with fastcc and ccc.
4613 auto isTailCallableCC = [] (CallingConv::ID CC){
4614 return CC == CallingConv::C || CC == CallingConv::Fast;
4615 };
4616 if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC))
4617 return false;
4618
4619 // We can safely tail call both fastcc and ccc callees from a c calling
4620 // convention caller. If the caller is fastcc, we may have less stack space
4621 // than a non-fastcc caller with the same signature so disable tail-calls in
4622 // that case.
4623 return CallerCC == CallingConv::C || CallerCC == CalleeCC;
4624}
4625
4626bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4627 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, bool isVarArg,
4628 const SmallVectorImpl<ISD::OutputArg> &Outs,
4629 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4630 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4631
4632 if (DisableSCO && !TailCallOpt) return false;
4633
4634 // Variadic argument functions are not supported.
4635 if (isVarArg) return false;
4636
4637 auto &Caller = DAG.getMachineFunction().getFunction();
4638 // Check that the calling conventions are compatible for tco.
4639 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4640 return false;
4641
4642 // Caller contains any byval parameter is not supported.
4643 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4644 return false;
4645
4646 // Callee contains any byval parameter is not supported, too.
4647 // Note: This is a quick work around, because in some cases, e.g.
4648 // caller's stack size > callee's stack size, we are still able to apply
4649 // sibling call optimization. For example, gcc is able to do SCO for caller1
4650 // in the following example, but not for caller2.
4651 // struct test {
4652 // long int a;
4653 // char ary[56];
4654 // } gTest;
4655 // __attribute__((noinline)) int callee(struct test v, struct test *b) {
4656 // b->a = v.a;
4657 // return 0;
4658 // }
4659 // void caller1(struct test a, struct test c, struct test *b) {
4660 // callee(gTest, b); }
4661 // void caller2(struct test *b) { callee(gTest, b); }
4662 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4663 return false;
4664
4665 // If callee and caller use different calling conventions, we cannot pass
4666 // parameters on stack since offsets for the parameter area may be different.
4667 if (Caller.getCallingConv() != CalleeCC &&
4668 needStackSlotPassParameters(Subtarget, Outs))
4669 return false;
4670
4671 // All variants of 64-bit ELF ABIs without PC-Relative addressing require that
4672 // the caller and callee share the same TOC for TCO/SCO. If the caller and
4673 // callee potentially have different TOC bases then we cannot tail call since
4674 // we need to restore the TOC pointer after the call.
4675 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4676 // We cannot guarantee this for indirect calls or calls to external functions.
4677 // When PC-Relative addressing is used, the concept of the TOC is no longer
4678 // applicable so this check is not required.
4679 // Check first for indirect calls.
4680 if (!Subtarget.isUsingPCRelativeCalls() &&
4681 !isFunctionGlobalAddress(Callee) && !isa<ExternalSymbolSDNode>(Callee))
4682 return false;
4683
4684 // Check if we share the TOC base.
4685 if (!Subtarget.isUsingPCRelativeCalls() &&
4686 !callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4687 return false;
4688
4689 // TCO allows altering callee ABI, so we don't have to check further.
4690 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4691 return true;
4692
4693 if (DisableSCO) return false;
4694
4695 // If callee use the same argument list that caller is using, then we can
4696 // apply SCO on this case. If it is not, then we need to check if callee needs
4697 // stack for passing arguments.
4698 // PC Relative tail calls may not have a CallBase.
4699 // If there is no CallBase we cannot verify if we have the same argument
4700 // list so assume that we don't have the same argument list.
4701 if (CB && !hasSameArgumentList(&Caller, *CB) &&
4702 needStackSlotPassParameters(Subtarget, Outs))
4703 return false;
4704 else if (!CB && needStackSlotPassParameters(Subtarget, Outs))
4705 return false;
4706
4707 return true;
4708}
4709
4710/// IsEligibleForTailCallOptimization - Check whether the call is eligible
4711/// for tail call optimization. Targets which want to do tail call
4712/// optimization should implement this function.
4713bool
4714PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4715 CallingConv::ID CalleeCC,
4716 bool isVarArg,
4717 const SmallVectorImpl<ISD::InputArg> &Ins,
4718 SelectionDAG& DAG) const {
4719 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4720 return false;
4721
4722 // Variable argument functions are not supported.
4723 if (isVarArg)
4724 return false;
4725
4726 MachineFunction &MF = DAG.getMachineFunction();
4727 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
4728 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4729 // Functions containing by val parameters are not supported.
4730 for (unsigned i = 0; i != Ins.size(); i++) {
4731 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4732 if (Flags.isByVal()) return false;
4733 }
4734
4735 // Non-PIC/GOT tail calls are supported.
4736 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4737 return true;
4738
4739 // At the moment we can only do local tail calls (in same module, hidden
4740 // or protected) if we are generating PIC.
4741 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4742 return G->getGlobal()->hasHiddenVisibility()
4743 || G->getGlobal()->hasProtectedVisibility();
4744 }
4745
4746 return false;
4747}
4748
4749/// isCallCompatibleAddress - Return the immediate to use if the specified
4750/// 32-bit value is representable in the immediate field of a BxA instruction.
4751static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4752 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4753 if (!C) return nullptr;
4754
4755 int Addr = C->getZExtValue();
4756 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
4757 SignExtend32<26>(Addr) != Addr)
4758 return nullptr; // Top 6 bits have to be sext of immediate.
4759
4760 return DAG
4761 .getConstant(
4762 (int)C->getZExtValue() >> 2, SDLoc(Op),
4763 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
4764 .getNode();
4765}
4766
4767namespace {
4768
4769struct TailCallArgumentInfo {
4770 SDValue Arg;
4771 SDValue FrameIdxOp;
4772 int FrameIdx = 0;
4773
4774 TailCallArgumentInfo() = default;
4775};
4776
4777} // end anonymous namespace
4778
4779/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
4780static void StoreTailCallArgumentsToStackSlot(
4781 SelectionDAG &DAG, SDValue Chain,
4782 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
4783 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
4784 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
4785 SDValue Arg = TailCallArgs[i].Arg;
4786 SDValue FIN = TailCallArgs[i].FrameIdxOp;
4787 int FI = TailCallArgs[i].FrameIdx;
4788 // Store relative to framepointer.
4789 MemOpChains.push_back(DAG.getStore(
4790 Chain, dl, Arg, FIN,
4791 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4792 }
4793}
4794
4795/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
4796/// the appropriate stack slot for the tail call optimized function call.
4797static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
4798 SDValue OldRetAddr, SDValue OldFP,
4799 int SPDiff, const SDLoc &dl) {
4800 if (SPDiff) {
4801 // Calculate the new stack slot for the return address.
4802 MachineFunction &MF = DAG.getMachineFunction();
4803 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
4804 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
4805 bool isPPC64 = Subtarget.isPPC64();
4806 int SlotSize = isPPC64 ? 8 : 4;
4807 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
4808 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
4809 NewRetAddrLoc, true);
4810 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4811 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
4812 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
4813 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
4814 }
4815 return Chain;
4816}
4817
4818/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
4819/// the position of the argument.
4820static void
4821CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
4822 SDValue Arg, int SPDiff, unsigned ArgOffset,
4823 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
4824 int Offset = ArgOffset + SPDiff;
4825 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
4826 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4827 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4828 SDValue FIN = DAG.getFrameIndex(FI, VT);
4829 TailCallArgumentInfo Info;
4830 Info.Arg = Arg;
4831 Info.FrameIdxOp = FIN;
4832 Info.FrameIdx = FI;
4833 TailCallArguments.push_back(Info);
4834}
4835
4836/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
4837/// stack slot. Returns the chain as result and the loaded frame pointers in
4838/// LROpOut/FPOpout. Used when tail calling.
4839SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
4840 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
4841 SDValue &FPOpOut, const SDLoc &dl) const {
4842 if (SPDiff) {
4843 // Load the LR and FP stack slot for later adjusting.
4844 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
4845 LROpOut = getReturnAddrFrameIndex(DAG);
4846 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
4847 Chain = SDValue(LROpOut.getNode(), 1);
4848 }
4849 return Chain;
4850}
4851
4852/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4853/// by "Src" to address "Dst" of size "Size". Alignment information is
4854/// specified by the specific parameter attribute. The copy will be passed as
4855/// a byval function parameter.
4856/// Sometimes what we are copying is the end of a larger object, the part that
4857/// does not fit in registers.
4858static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
4859 SDValue Chain, ISD::ArgFlagsTy Flags,
4860 SelectionDAG &DAG, const SDLoc &dl) {
4861 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4862 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
4863 Flags.getNonZeroByValAlign(), false, false, false,
4864 MachinePointerInfo(), MachinePointerInfo());
4865}
4866
4867/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4868/// tail calls.
4869static void LowerMemOpCallTo(
4870 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
4871 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
4872 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4873 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
4874 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4875 if (!isTailCall) {
4876 if (isVector) {
4877 SDValue StackPtr;
4878 if (isPPC64)
4879 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4880 else
4881 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4882 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4883 DAG.getConstant(ArgOffset, dl, PtrVT));
4884 }
4885 MemOpChains.push_back(
4886 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
4887 // Calculate and remember argument location.
4888 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4889 TailCallArguments);
4890}
4891
4892static void
4893PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4894 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
4895 SDValue FPOp,
4896 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4897 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4898 // might overwrite each other in case of tail call optimization.
4899 SmallVector<SDValue, 8> MemOpChains2;
4900 // Do not flag preceding copytoreg stuff together with the following stuff.
4901 InFlag = SDValue();
4902 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4903 MemOpChains2, dl);
4904 if (!MemOpChains2.empty())
4905 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4906
4907 // Store the return address to the appropriate stack slot.
4908 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
4909
4910 // Emit callseq_end just before tailcall node.
4911 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4912 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4913 InFlag = Chain.getValue(1);
4914}
4915
4916// Is this global address that of a function that can be called by name? (as
4917// opposed to something that must hold a descriptor for an indirect call).
4918static bool isFunctionGlobalAddress(SDValue Callee) {
4919 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4920 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4921 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4922 return false;
4923
4924 return G->getGlobal()->getValueType()->isFunctionTy();
4925 }
4926
4927 return false;
4928}
4929
4930SDValue PPCTargetLowering::LowerCallResult(
4931 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
4932 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4933 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4934 SmallVector<CCValAssign, 16> RVLocs;
4935 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4936 *DAG.getContext());
4937
4938 CCRetInfo.AnalyzeCallResult(
4939 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold)
4940 ? RetCC_PPC_Cold
4941 : RetCC_PPC);
4942
4943 // Copy all of the result registers out of their specified physreg.
4944 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4945 CCValAssign &VA = RVLocs[i];
4946 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4946, __PRETTY_FUNCTION__))
;
4947
4948 SDValue Val;
4949
4950 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
4951 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
4952 InFlag);
4953 Chain = Lo.getValue(1);
4954 InFlag = Lo.getValue(2);
4955 VA = RVLocs[++i]; // skip ahead to next loc
4956 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
4957 InFlag);
4958 Chain = Hi.getValue(1);
4959 InFlag = Hi.getValue(2);
4960 if (!Subtarget.isLittleEndian())
4961 std::swap (Lo, Hi);
4962 Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi);
4963 } else {
4964 Val = DAG.getCopyFromReg(Chain, dl,
4965 VA.getLocReg(), VA.getLocVT(), InFlag);
4966 Chain = Val.getValue(1);
4967 InFlag = Val.getValue(2);
4968 }
4969
4970 switch (VA.getLocInfo()) {
4971 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4971)
;
4972 case CCValAssign::Full: break;
4973 case CCValAssign::AExt:
4974 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4975 break;
4976 case CCValAssign::ZExt:
4977 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4978 DAG.getValueType(VA.getValVT()));
4979 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4980 break;
4981 case CCValAssign::SExt:
4982 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4983 DAG.getValueType(VA.getValVT()));
4984 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4985 break;
4986 }
4987
4988 InVals.push_back(Val);
4989 }
4990
4991 return Chain;
4992}
4993
4994static bool isIndirectCall(const SDValue &Callee, SelectionDAG &DAG,
4995 const PPCSubtarget &Subtarget, bool isPatchPoint) {
4996 // PatchPoint calls are not indirect.
4997 if (isPatchPoint)
4998 return false;
4999
5000 if (isFunctionGlobalAddress(Callee) || isa<ExternalSymbolSDNode>(Callee))
5001 return false;
5002
5003 // Darwin, and 32-bit ELF can use a BLA. The descriptor based ABIs can not
5004 // becuase the immediate function pointer points to a descriptor instead of
5005 // a function entry point. The ELFv2 ABI cannot use a BLA because the function
5006 // pointer immediate points to the global entry point, while the BLA would
5007 // need to jump to the local entry point (see rL211174).
5008 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() &&
5009 isBLACompatibleAddress(Callee, DAG))
5010 return false;
5011
5012 return true;
5013}
5014
5015// AIX and 64-bit ELF ABIs w/o PCRel require a TOC save/restore around calls.
5016static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) {
5017 return Subtarget.isAIXABI() ||
5018 (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls());
5019}
5020
5021static unsigned getCallOpcode(PPCTargetLowering::CallFlags CFlags,
5022 const Function &Caller,
5023 const SDValue &Callee,
5024 const PPCSubtarget &Subtarget,
5025 const TargetMachine &TM) {
5026 if (CFlags.IsTailCall)
5027 return PPCISD::TC_RETURN;
5028
5029 // This is a call through a function pointer.
5030 if (CFlags.IsIndirect) {
5031 // AIX and the 64-bit ELF ABIs need to maintain the TOC pointer accross
5032 // indirect calls. The save of the caller's TOC pointer to the stack will be
5033 // inserted into the DAG as part of call lowering. The restore of the TOC
5034 // pointer is modeled by using a pseudo instruction for the call opcode that
5035 // represents the 2 instruction sequence of an indirect branch and link,
5036 // immediately followed by a load of the TOC pointer from the the stack save
5037 // slot into gpr2. For 64-bit ELFv2 ABI with PCRel, do not restore the TOC
5038 // as it is not saved or used.
5039 return isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC
5040 : PPCISD::BCTRL;
5041 }
5042
5043 if (Subtarget.isUsingPCRelativeCalls()) {
5044 assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI.")((Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.is64BitELFABI() && \"PC Relative is only on ELF ABI.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5044, __PRETTY_FUNCTION__))
;
5045 return PPCISD::CALL_NOTOC;
5046 }
5047
5048 // The ABIs that maintain a TOC pointer accross calls need to have a nop
5049 // immediately following the call instruction if the caller and callee may
5050 // have different TOC bases. At link time if the linker determines the calls
5051 // may not share a TOC base, the call is redirected to a trampoline inserted
5052 // by the linker. The trampoline will (among other things) save the callers
5053 // TOC pointer at an ABI designated offset in the linkage area and the linker
5054 // will rewrite the nop to be a load of the TOC pointer from the linkage area
5055 // into gpr2.
5056 if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
5057 return callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL
5058 : PPCISD::CALL_NOP;
5059
5060 return PPCISD::CALL;
5061}
5062
5063static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
5064 const SDLoc &dl, const PPCSubtarget &Subtarget) {
5065 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI())
5066 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
5067 return SDValue(Dest, 0);
5068
5069 // Returns true if the callee is local, and false otherwise.
5070 auto isLocalCallee = [&]() {
5071 const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
5072 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5073 const GlobalValue *GV = G ? G->getGlobal() : nullptr;
5074
5075 return DAG.getTarget().shouldAssumeDSOLocal(*Mod, GV) &&
5076 !dyn_cast_or_null<GlobalIFunc>(GV);
5077 };
5078
5079 // The PLT is only used in 32-bit ELF PIC mode. Attempting to use the PLT in
5080 // a static relocation model causes some versions of GNU LD (2.17.50, at
5081 // least) to force BSS-PLT, instead of secure-PLT, even if all objects are
5082 // built with secure-PLT.
5083 bool UsePlt =
5084 Subtarget.is32BitELFABI() && !isLocalCallee() &&
5085 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_;
5086
5087 const auto getAIXFuncEntryPointSymbolSDNode = [&](const GlobalValue *GV) {
5088 const TargetMachine &TM = Subtarget.getTargetMachine();
5089 const TargetLoweringObjectFile *TLOF = TM.getObjFileLowering();
5090 MCSymbolXCOFF *S =
5091 cast<MCSymbolXCOFF>(TLOF->getFunctionEntryPointSymbol(GV, TM));
5092
5093 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5094 return DAG.getMCSymbol(S, PtrVT);
5095 };
5096
5097 if (isFunctionGlobalAddress(Callee)) {
5098 const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
5099
5100 if (Subtarget.isAIXABI()) {
5101 assert(!isa<GlobalIFunc>(GV) && "IFunc is not supported on AIX.")((!isa<GlobalIFunc>(GV) && "IFunc is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("!isa<GlobalIFunc>(GV) && \"IFunc is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5101, __PRETTY_FUNCTION__))
;
5102 return getAIXFuncEntryPointSymbolSDNode(GV);
5103 }
5104 return DAG.getTargetGlobalAddress(GV, dl, Callee.getValueType(), 0,
5105 UsePlt ? PPCII::MO_PLT : 0);
5106 }
5107
5108 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
5109 const char *SymName = S->getSymbol();
5110 if (Subtarget.isAIXABI()) {
5111 // If there exists a user-declared function whose name is the same as the
5112 // ExternalSymbol's, then we pick up the user-declared version.
5113 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5114 if (const Function *F =
5115 dyn_cast_or_null<Function>(Mod->getNamedValue(SymName)))
5116 return getAIXFuncEntryPointSymbolSDNode(F);
5117
5118 // On AIX, direct function calls reference the symbol for the function's
5119 // entry point, which is named by prepending a "." before the function's
5120 // C-linkage name. A Qualname is returned here because an external
5121 // function entry point is a csect with XTY_ER property.
5122 const auto getExternalFunctionEntryPointSymbol = [&](StringRef SymName) {
5123 auto &Context = DAG.getMachineFunction().getMMI().getContext();
5124 MCSectionXCOFF *Sec = Context.getXCOFFSection(
5125 (Twine(".") + Twine(SymName)).str(), SectionKind::getMetadata(),
5126 XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER));
5127 return Sec->getQualNameSymbol();
5128 };
5129
5130 SymName = getExternalFunctionEntryPointSymbol(SymName)->getName().data();
5131 }
5132 return DAG.getTargetExternalSymbol(SymName, Callee.getValueType(),
5133 UsePlt ? PPCII::MO_PLT : 0);
5134 }
5135
5136 // No transformation needed.
5137 assert(Callee.getNode() && "What no callee?")((Callee.getNode() && "What no callee?") ? static_cast
<void> (0) : __assert_fail ("Callee.getNode() && \"What no callee?\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5137, __PRETTY_FUNCTION__))
;
5138 return Callee;
5139}
5140
5141static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart) {
5142 assert(CallSeqStart.getOpcode() == ISD::CALLSEQ_START &&((CallSeqStart.getOpcode() == ISD::CALLSEQ_START && "Expected a CALLSEQ_STARTSDNode."
) ? static_cast<void> (0) : __assert_fail ("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5143, __PRETTY_FUNCTION__))
5143 "Expected a CALLSEQ_STARTSDNode.")((CallSeqStart.getOpcode() == ISD::CALLSEQ_START && "Expected a CALLSEQ_STARTSDNode."
) ? static_cast<void> (0) : __assert_fail ("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5143, __PRETTY_FUNCTION__))
;
5144
5145 // The last operand is the chain, except when the node has glue. If the node
5146 // has glue, then the last operand is the glue, and the chain is the second
5147 // last operand.
5148 SDValue LastValue = CallSeqStart.getValue(CallSeqStart->getNumValues() - 1);
5149 if (LastValue.getValueType() != MVT::Glue)
5150 return LastValue;
5151
5152 return CallSeqStart.getValue(CallSeqStart->getNumValues() - 2);
5153}
5154
5155// Creates the node that moves a functions address into the count register
5156// to prepare for an indirect call instruction.
5157static void prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5158 SDValue &Glue, SDValue &Chain,
5159 const SDLoc &dl) {
5160 SDValue MTCTROps[] = {Chain, Callee, Glue};
5161 EVT ReturnTypes[] = {MVT::Other, MVT::Glue};
5162 Chain = DAG.getNode(PPCISD::MTCTR, dl, makeArrayRef(ReturnTypes, 2),
5163 makeArrayRef(MTCTROps, Glue.getNode() ? 3 : 2));
5164 // The glue is the second value produced.
5165 Glue = Chain.getValue(1);
5166}
5167
5168static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5169 SDValue &Glue, SDValue &Chain,
5170 SDValue CallSeqStart,
5171 const CallBase *CB, const SDLoc &dl,
5172 bool hasNest,
5173 const PPCSubtarget &Subtarget) {
5174 // Function pointers in the 64-bit SVR4 ABI do not point to the function
5175 // entry point, but to the function descriptor (the function entry point
5176 // address is part of the function descriptor though).
5177 // The function descriptor is a three doubleword structure with the
5178 // following fields: function entry point, TOC base address and
5179 // environment pointer.
5180 // Thus for a call through a function pointer, the following actions need
5181 // to be performed:
5182 // 1. Save the TOC of the caller in the TOC save area of its stack
5183 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
5184 // 2. Load the address of the function entry point from the function
5185 // descriptor.
5186 // 3. Load the TOC of the callee from the function descriptor into r2.
5187 // 4. Load the environment pointer from the function descriptor into
5188 // r11.
5189 // 5. Branch to the function entry point address.
5190 // 6. On return of the callee, the TOC of the caller needs to be
5191 // restored (this is done in FinishCall()).
5192 //
5193 // The loads are scheduled at the beginning of the call sequence, and the
5194 // register copies are flagged together to ensure that no other
5195 // operations can be scheduled in between. E.g. without flagging the
5196 // copies together, a TOC access in the caller could be scheduled between
5197 // the assignment of the callee TOC and the branch to the callee, which leads
5198 // to incorrect code.
5199
5200 // Start by loading the function address from the descriptor.
5201 SDValue LDChain = getOutputChainFromCallSeq(CallSeqStart);
5202 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
5203 ? (MachineMemOperand::MODereferenceable |
5204 MachineMemOperand::MOInvariant)
5205 : MachineMemOperand::MONone;
5206
5207 MachinePointerInfo MPI(CB ? CB->getCalledOperand() : nullptr);
5208
5209 // Registers used in building the DAG.
5210 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister();
5211 const MCRegister TOCReg = Subtarget.getTOCPointerRegister();
5212
5213 // Offsets of descriptor members.
5214 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset();
5215 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset();
5216
5217 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5218 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4;
5219
5220 // One load for the functions entry point address.
5221 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5222 Alignment, MMOFlags);
5223
5224 // One for loading the TOC anchor for the module that contains the called
5225 // function.
5226 SDValue TOCOff = DAG.getIntPtrConstant(TOCAnchorOffset, dl);
5227 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5228 SDValue TOCPtr =
5229 DAG.getLoad(RegVT, dl, LDChain, AddTOC,
5230 MPI.getWithOffset(TOCAnchorOffset), Alignment, MMOFlags);
5231
5232 // One for loading the environment pointer.
5233 SDValue PtrOff = DAG.getIntPtrConstant(EnvPtrOffset, dl);
5234 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5235 SDValue LoadEnvPtr =
5236 DAG.getLoad(RegVT, dl, LDChain, AddPtr,
5237 MPI.getWithOffset(EnvPtrOffset), Alignment, MMOFlags);
5238
5239
5240 // Then copy the newly loaded TOC anchor to the TOC pointer.
5241 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, TOCReg, TOCPtr, Glue);
5242 Chain = TOCVal.getValue(0);
5243 Glue = TOCVal.getValue(1);
5244
5245 // If the function call has an explicit 'nest' parameter, it takes the
5246 // place of the environment pointer.
5247 assert((!hasNest || !Subtarget.isAIXABI()) &&(((!hasNest || !Subtarget.isAIXABI()) && "Nest parameter is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5248, __PRETTY_FUNCTION__))
5248 "Nest parameter is not supported on AIX.")(((!hasNest || !Subtarget.isAIXABI()) && "Nest parameter is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5248, __PRETTY_FUNCTION__))
;
5249 if (!hasNest) {
5250 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, EnvPtrReg, LoadEnvPtr, Glue);
5251 Chain = EnvVal.getValue(0);
5252 Glue = EnvVal.getValue(1);
5253 }
5254
5255 // The rest of the indirect call sequence is the same as the non-descriptor
5256 // DAG.
5257 prepareIndirectCall(DAG, LoadFuncPtr, Glue, Chain, dl);
5258}
5259
5260static void
5261buildCallOperands(SmallVectorImpl<SDValue> &Ops,
5262 PPCTargetLowering::CallFlags CFlags, const SDLoc &dl,
5263 SelectionDAG &DAG,
5264 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
5265 SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff,
5266 const PPCSubtarget &Subtarget) {
5267 const bool IsPPC64 = Subtarget.isPPC64();
5268 // MVT for a general purpose register.
5269 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5270
5271 // First operand is always the chain.
5272 Ops.push_back(Chain);
5273
5274 // If it's a direct call pass the callee as the second operand.
5275 if (!CFlags.IsIndirect)
5276 Ops.push_back(Callee);
5277 else {
5278 assert(!CFlags.IsPatchPoint && "Patch point calls are not indirect.")((!CFlags.IsPatchPoint && "Patch point calls are not indirect."
) ? static_cast<void> (0) : __assert_fail ("!CFlags.IsPatchPoint && \"Patch point calls are not indirect.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5278, __PRETTY_FUNCTION__))
;
5279
5280 // For the TOC based ABIs, we have saved the TOC pointer to the linkage area
5281 // on the stack (this would have been done in `LowerCall_64SVR4` or
5282 // `LowerCall_AIX`). The call instruction is a pseudo instruction that
5283 // represents both the indirect branch and a load that restores the TOC
5284 // pointer from the linkage area. The operand for the TOC restore is an add
5285 // of the TOC save offset to the stack pointer. This must be the second
5286 // operand: after the chain input but before any other variadic arguments.
5287 // For 64-bit ELFv2 ABI with PCRel, do not restore the TOC as it is not
5288 // saved or used.
5289 if (isTOCSaveRestoreRequired(Subtarget)) {
5290 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister();
5291
5292 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5293 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5294 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5295 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5296 Ops.push_back(AddTOC);
5297 }
5298
5299 // Add the register used for the environment pointer.
5300 if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest)
5301 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(),
5302 RegVT));
5303
5304
5305 // Add CTR register as callee so a bctr can be emitted later.
5306 if (CFlags.IsTailCall)
5307 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5308 }
5309
5310 // If this is a tail call add stack pointer delta.
5311 if (CFlags.IsTailCall)
5312 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
5313
5314 // Add argument registers to the end of the list so that they are known live
5315 // into the call.
5316 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
5317 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5318 RegsToPass[i].second.getValueType()));
5319
5320 // We cannot add R2/X2 as an operand here for PATCHPOINT, because there is
5321 // no way to mark dependencies as implicit here.
5322 // We will add the R2/X2 dependency in EmitInstrWithCustomInserter.
5323 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) &&
5324 !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls())
5325 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT));
5326
5327 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
5328 if (CFlags.IsVarArg && Subtarget.is32BitELFABI())
5329 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5330
5331 // Add a register mask operand representing the call-preserved registers.
5332 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
5333 const uint32_t *Mask =
5334 TRI->getCallPreservedMask(DAG.getMachineFunction(), CFlags.CallConv);
5335 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5335, __PRETTY_FUNCTION__))
;
5336 Ops.push_back(DAG.getRegisterMask(Mask));
5337
5338 // If the glue is valid, it is the last operand.
5339 if (Glue.getNode())
5340 Ops.push_back(Glue);
5341}
5342
5343SDValue PPCTargetLowering::FinishCall(
5344 CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
5345 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue,
5346 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5347 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
5348 SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const {
5349
5350 if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) ||
5351 Subtarget.isAIXABI())
5352 setUsesTOCBasePtr(DAG);
5353
5354 unsigned CallOpc =
5355 getCallOpcode(CFlags, DAG.getMachineFunction().getFunction(), Callee,
5356 Subtarget, DAG.getTarget());
5357
5358 if (!CFlags.IsIndirect)
5359 Callee = transformCallee(Callee, DAG, dl, Subtarget);
5360 else if (Subtarget.usesFunctionDescriptors())
5361 prepareDescriptorIndirectCall(DAG, Callee, Glue, Chain, CallSeqStart, CB,
5362 dl, CFlags.HasNest, Subtarget);
5363 else
5364 prepareIndirectCall(DAG, Callee, Glue, Chain, dl);
5365
5366 // Build the operand list for the call instruction.
5367 SmallVector<SDValue, 8> Ops;
5368 buildCallOperands(Ops, CFlags, dl, DAG, RegsToPass, Glue, Chain, Callee,
5369 SPDiff, Subtarget);
5370
5371 // Emit tail call.
5372 if (CFlags.IsTailCall) {
5373 // Indirect tail call when using PC Relative calls do not have the same
5374 // constraints.
5375 assert(((Callee.getOpcode() == ISD::Register &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5383, __PRETTY_FUNCTION__))
5376 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5383, __PRETTY_FUNCTION__))
5377 Callee.getOpcode() == ISD::TargetExternalSymbol ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5383, __PRETTY_FUNCTION__))
5378 Callee.getOpcode() == ISD::TargetGlobalAddress ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5383, __PRETTY_FUNCTION__))
5379 isa<ConstantSDNode>(Callee) ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5383, __PRETTY_FUNCTION__))
5380 (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5383, __PRETTY_FUNCTION__))
5381 "Expecting a global address, external symbol, absolute value, "((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5383, __PRETTY_FUNCTION__))
5382 "register or an indirect tail call when PC Relative calls are "((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5383, __PRETTY_FUNCTION__))
5383 "used.")((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect &&
Subtarget.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5383, __PRETTY_FUNCTION__))
;
5384 // PC Relative calls also use TC_RETURN as the way to mark tail calls.
5385 assert(CallOpc == PPCISD::TC_RETURN &&((CallOpc == PPCISD::TC_RETURN && "Unexpected call opcode for a tail call."
) ? static_cast<void> (0) : __assert_fail ("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5386, __PRETTY_FUNCTION__))
5386 "Unexpected call opcode for a tail call.")((CallOpc == PPCISD::TC_RETURN && "Unexpected call opcode for a tail call."
) ? static_cast<void> (0) : __assert_fail ("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5386, __PRETTY_FUNCTION__))
;
5387 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
5388 return DAG.getNode(CallOpc, dl, MVT::Other, Ops);
5389 }
5390
5391 std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}};
5392 Chain = DAG.getNode(CallOpc, dl, ReturnTypes, Ops);
5393 DAG.addNoMergeSiteInfo(Chain.getNode(), CFlags.NoMerge);
5394 Glue = Chain.getValue(1);
5395
5396 // When performing tail call optimization the callee pops its arguments off
5397 // the stack. Account for this here so these bytes can be pushed back on in
5398 // PPCFrameLowering::eliminateCallFramePseudoInstr.
5399 int BytesCalleePops = (CFlags.CallConv == CallingConv::Fast &&
5400 getTargetMachine().Options.GuaranteedTailCallOpt)
5401 ? NumBytes
5402 : 0;
5403
5404 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5405 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5406 Glue, dl);
5407 Glue = Chain.getValue(1);
5408
5409 return LowerCallResult(Chain, Glue, CFlags.CallConv, CFlags.IsVarArg, Ins, dl,
5410 DAG, InVals);
5411}
5412
5413SDValue
5414PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5415 SmallVectorImpl<SDValue> &InVals) const {
5416 SelectionDAG &DAG = CLI.DAG;
5417 SDLoc &dl = CLI.DL;
5418 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5419 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5420 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5421 SDValue Chain = CLI.Chain;
5422 SDValue Callee = CLI.Callee;
5423 bool &isTailCall = CLI.IsTailCall;
5424 CallingConv::ID CallConv = CLI.CallConv;
5425 bool isVarArg = CLI.IsVarArg;
5426 bool isPatchPoint = CLI.IsPatchPoint;
5427 const CallBase *CB = CLI.CB;
5428
5429 if (isTailCall) {
5430 if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall()))
5431 isTailCall = false;
5432 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5433 isTailCall = IsEligibleForTailCallOptimization_64SVR4(
5434 Callee, CallConv, CB, isVarArg, Outs, Ins, DAG);
5435 else
5436 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5437 Ins, DAG);
5438 if (isTailCall) {
5439 ++NumTailCalls;
5440 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5441 ++NumSiblingCalls;
5442
5443 // PC Relative calls no longer guarantee that the callee is a Global
5444 // Address Node. The callee could be an indirect tail call in which
5445 // case the SDValue for the callee could be a load (to load the address
5446 // of a function pointer) or it may be a register copy (to move the
5447 // address of the callee from a function parameter into a virtual
5448 // register). It may also be an ExternalSymbolSDNode (ex memcopy).
5449 assert((Subtarget.isUsingPCRelativeCalls() ||(((Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode
>(Callee)) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5451, __PRETTY_FUNCTION__))
5450 isa<GlobalAddressSDNode>(Callee)) &&(((Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode
>(Callee)) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5451, __PRETTY_FUNCTION__))
5451 "Callee should be an llvm::Function object.")(((Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode
>(Callee)) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5451, __PRETTY_FUNCTION__))
;
5452
5453 LLVM_DEBUG(dbgs() << "TCO caller: " << DAG.getMachineFunction().getName()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
5454 << "\nTCO callee: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
;
5455 LLVM_DEBUG(Callee.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { Callee.dump(); } } while (false)
;
5456 }
5457 }
5458
5459 if (!isTailCall && CB && CB->isMustTailCall())
5460 report_fatal_error("failed to perform tail call elimination on a call "
5461 "site marked musttail");
5462
5463 // When long calls (i.e. indirect calls) are always used, calls are always
5464 // made via function pointer. If we have a function name, first translate it
5465 // into a pointer.
5466 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5467 !isTailCall)
5468 Callee = LowerGlobalAddress(Callee, DAG);
5469
5470 CallFlags CFlags(
5471 CallConv, isTailCall, isVarArg, isPatchPoint,
5472 isIndirectCall(Callee, DAG, Subtarget, isPatchPoint),
5473 // hasNest
5474 Subtarget.is64BitELFABI() &&
5475 any_of(Outs, [](ISD::OutputArg Arg) { return Arg.Flags.isNest(); }),
5476 CLI.NoMerge);
5477
5478 if (Subtarget.isAIXABI())
5479 return LowerCall_AIX(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5480 InVals, CB);
5481
5482 assert(Subtarget.isSVR4ABI())((Subtarget.isSVR4ABI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.isSVR4ABI()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5482, __PRETTY_FUNCTION__))
;
5483 if (Subtarget.isPPC64())
5484 return LowerCall_64SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5485 InVals, CB);
5486 return LowerCall_32SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5487 InVals, CB);
5488}
5489
5490SDValue PPCTargetLowering::LowerCall_32SVR4(
5491 SDValue Chain, SDValue Callee, CallFlags CFlags,
5492 const SmallVectorImpl<ISD::OutputArg> &Outs,
5493 const SmallVectorImpl<SDValue> &OutVals,
5494 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5495 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5496 const CallBase *CB) const {
5497 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5498 // of the 32-bit SVR4 ABI stack frame layout.
5499
5500 const CallingConv::ID CallConv = CFlags.CallConv;
5501 const bool IsVarArg = CFlags.IsVarArg;
5502 const bool IsTailCall = CFlags.IsTailCall;
5503
5504 assert((CallConv == CallingConv::C ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5506, __PRETTY_FUNCTION__))
5505 CallConv == CallingConv::Cold ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5506, __PRETTY_FUNCTION__))
5506 CallConv == CallingConv::Fast) && "Unknown calling convention!")(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5506, __PRETTY_FUNCTION__))
;
5507
5508 const Align PtrAlign(4);
5509
5510 MachineFunction &MF = DAG.getMachineFunction();
5511
5512 // Mark this function as potentially containing a function that contains a
5513 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5514 // and restoring the callers stack pointer in this functions epilog. This is
5515 // done because by tail calling the called function might overwrite the value
5516 // in this function's (MF) stack pointer stack slot 0(SP).
5517 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5518 CallConv == CallingConv::Fast)
5519 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5520
5521 // Count how many bytes are to be pushed on the stack, including the linkage
5522 // area, parameter list area and the part of the local variable space which
5523 // contains copies of aggregates which are passed by value.
5524
5525 // Assign locations to all of the outgoing arguments.
5526 SmallVector<CCValAssign, 16> ArgLocs;
5527 PPCCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
5528
5529 // Reserve space for the linkage area on the stack.
5530 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5531 PtrAlign);
5532 if (useSoftFloat())
5533 CCInfo.PreAnalyzeCallOperands(Outs);
5534
5535 if (IsVarArg) {
5536 // Handle fixed and variable vector arguments differently.
5537 // Fixed vector arguments go into registers as long as registers are
5538 // available. Variable vector arguments always go into memory.
5539 unsigned NumArgs = Outs.size();
5540
5541 for (unsigned i = 0; i != NumArgs; ++i) {
5542 MVT ArgVT = Outs[i].VT;
5543 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5544 bool Result;
5545
5546 if (Outs[i].IsFixed) {
5547 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5548 CCInfo);
5549 } else {
5550 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
5551 ArgFlags, CCInfo);
5552 }
5553
5554 if (Result) {
5555#ifndef NDEBUG
5556 errs() << "Call operand #" << i << " has unhandled type "
5557 << EVT(ArgVT).getEVTString() << "\n";
5558#endif
5559 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5559)
;
5560 }
5561 }
5562 } else {
5563 // All arguments are treated the same.
5564 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
5565 }
5566 CCInfo.clearWasPPCF128();
5567
5568 // Assign locations to all of the outgoing aggregate by value arguments.
5569 SmallVector<CCValAssign, 16> ByValArgLocs;
5570 CCState CCByValInfo(CallConv, IsVarArg, MF, ByValArgLocs, *DAG.getContext());
5571
5572 // Reserve stack space for the allocations in CCInfo.
5573 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrAlign);
5574
5575 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
5576
5577 // Size of the linkage area, parameter list area and the part of the local
5578 // space variable where copies of aggregates which are passed by value are
5579 // stored.
5580 unsigned NumBytes = CCByValInfo.getNextStackOffset();
5581
5582 // Calculate by how many bytes the stack has to be adjusted in case of tail
5583 // call optimization.
5584 int SPDiff = CalculateTailCallSPDiff(DAG, IsTailCall, NumBytes);
5585
5586 // Adjust the stack pointer for the new arguments...
5587 // These operations are automatically eliminated by the prolog/epilog pass
5588 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5589 SDValue CallSeqStart = Chain;
5590
5591 // Load the return address and frame pointer so it can be moved somewhere else
5592 // later.
5593 SDValue LROp, FPOp;
5594 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5595
5596 // Set up a copy of the stack pointer for use loading and storing any
5597 // arguments that may not fit in the registers available for argument
5598 // passing.
5599 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5600
5601 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5602 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5603 SmallVector<SDValue, 8> MemOpChains;
5604
5605 bool seenFloatArg = false;
5606 // Walk the register/memloc assignments, inserting copies/loads.
5607 // i - Tracks the index into the list of registers allocated for the call
5608 // RealArgIdx - Tracks the index into the list of actual function arguments
5609 // j - Tracks the index into the list of byval arguments
5610 for (unsigned i = 0, RealArgIdx = 0, j = 0, e = ArgLocs.size();
5611 i != e;
5612 ++i, ++RealArgIdx) {
5613 CCValAssign &VA = ArgLocs[i];
5614 SDValue Arg = OutVals[RealArgIdx];
5615 ISD::ArgFlagsTy Flags = Outs[RealArgIdx].Flags;
5616
5617 if (Flags.isByVal()) {
5618 // Argument is an aggregate which is passed by value, thus we need to
5619 // create a copy of it in the local variable space of the current stack
5620 // frame (which is the stack frame of the caller) and pass the address of
5621 // this copy to the callee.
5622 assert((j < ByValArgLocs.size()) && "Index out of bounds!")(((j < ByValArgLocs.size()) && "Index out of bounds!"
) ? static_cast<void> (0) : __assert_fail ("(j < ByValArgLocs.size()) && \"Index out of bounds!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5622, __PRETTY_FUNCTION__))
;
5623 CCValAssign &ByValVA = ByValArgLocs[j++];
5624 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!")(((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"
) ? static_cast<void> (0) : __assert_fail ("(VA.getValNo() == ByValVA.getValNo()) && \"ValNo mismatch!\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5624, __PRETTY_FUNCTION__))
;
5625
5626 // Memory reserved in the local variable space of the callers stack frame.
5627 unsigned LocMemOffset = ByValVA.getLocMemOffset();
5628
5629 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5630 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5631 StackPtr, PtrOff);
5632
5633 // Create a copy of the argument in the local area of the current
5634 // stack frame.
5635 SDValue MemcpyCall =
5636 CreateCopyOfByValArgument(Arg, PtrOff,
5637 CallSeqStart.getNode()->getOperand(0),
5638 Flags, DAG, dl);
5639
5640 // This must go outside the CALLSEQ_START..END.
5641 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0,
5642 SDLoc(MemcpyCall));
5643 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5644 NewCallSeqStart.getNode());
5645 Chain = CallSeqStart = NewCallSeqStart;
5646
5647 // Pass the address of the aggregate copy on the stack either in a
5648 // physical register or in the parameter list area of the current stack
5649 // frame to the callee.
5650 Arg = PtrOff;
5651 }
5652
5653 // When useCRBits() is true, there can be i1 arguments.
5654 // It is because getRegisterType(MVT::i1) => MVT::i1,
5655 // and for other integer types getRegisterType() => MVT::i32.
5656 // Extend i1 and ensure callee will get i32.
5657 if (Arg.getValueType() == MVT::i1)
5658 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5659 dl, MVT::i32, Arg);
5660
5661 if (VA.isRegLoc()) {
5662 seenFloatArg |= VA.getLocVT().isFloatingPoint();
5663 // Put argument in a physical register.
5664 if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) {
5665 bool IsLE = Subtarget.isLittleEndian();
5666 SDValue SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
5667 DAG.getIntPtrConstant(IsLE ? 0 : 1, dl));
5668 RegsToPass.push_back(std::make_pair(VA.getLocReg(), SVal.getValue(0)));
5669 SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
5670 DAG.getIntPtrConstant(IsLE ? 1 : 0, dl));
5671 RegsToPass.push_back(std::make_pair(ArgLocs[++i].getLocReg(),
5672 SVal.getValue(0)));
5673 } else
5674 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
5675 } else {
5676 // Put argument in the parameter list area of the current stack frame.
5677 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5677, __PRETTY_FUNCTION__))
;
5678 unsigned LocMemOffset = VA.getLocMemOffset();
5679
5680 if (!IsTailCall) {
5681 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5682 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5683 StackPtr, PtrOff);
5684
5685 MemOpChains.push_back(
5686 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5687 } else {
5688 // Calculate and remember argument location.
5689 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
5690 TailCallArguments);
5691 }
5692 }
5693 }
5694
5695 if (!MemOpChains.empty())
5696 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5697
5698 // Build a sequence of copy-to-reg nodes chained together with token chain
5699 // and flag operands which copy the outgoing args into the appropriate regs.
5700 SDValue InFlag;
5701 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5702 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5703 RegsToPass[i].second, InFlag);
5704 InFlag = Chain.getValue(1);
5705 }
5706
5707 // Set CR bit 6 to true if this is a vararg call with floating args passed in
5708 // registers.
5709 if (IsVarArg) {
5710 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
5711 SDValue Ops[] = { Chain, InFlag };
5712
5713 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
5714 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
5715
5716 InFlag = Chain.getValue(1);
5717 }
5718
5719 if (IsTailCall)
5720 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
5721 TailCallArguments);
5722
5723 return FinishCall(CFlags, dl, DAG, RegsToPass, InFlag, Chain, CallSeqStart,
5724 Callee, SPDiff, NumBytes, Ins, InVals, CB);
5725}
5726
5727// Copy an argument into memory, being careful to do this outside the
5728// call sequence for the call to which the argument belongs.
5729SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
5730 SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
5731 SelectionDAG &DAG, const SDLoc &dl) const {
5732 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
5733 CallSeqStart.getNode()->getOperand(0),
5734 Flags, DAG, dl);
5735 // The MEMCPY must go outside the CALLSEQ_START..END.
5736 int64_t FrameSize = CallSeqStart.getConstantOperandVal(1);
5737 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0,
5738 SDLoc(MemcpyCall));
5739 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5740 NewCallSeqStart.getNode());
5741 return NewCallSeqStart;
5742}
5743
5744SDValue PPCTargetLowering::LowerCall_64SVR4(
5745 SDValue Chain, SDValue Callee, CallFlags CFlags,
5746 const SmallVectorImpl<ISD::OutputArg> &Outs,
5747 const SmallVectorImpl<SDValue> &OutVals,
5748 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5749 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5750 const CallBase *CB) const {
5751 bool isELFv2ABI = Subtarget.isELFv2ABI();
5752 bool isLittleEndian = Subtarget.isLittleEndian();
5753 unsigned NumOps = Outs.size();
5754 bool IsSibCall = false;
5755 bool IsFastCall = CFlags.CallConv == CallingConv::Fast;
5756
5757 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5758 unsigned PtrByteSize = 8;
5759
5760 MachineFunction &MF = DAG.getMachineFunction();
5761
5762 if (CFlags.IsTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt)
5763 IsSibCall = true;
5764
5765 // Mark this function as potentially containing a function that contains a
5766 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5767 // and restoring the callers stack pointer in this functions epilog. This is
5768 // done because by tail calling the called function might overwrite the value
5769 // in this function's (MF) stack pointer stack slot 0(SP).
5770 if (getTargetMachine().Options.GuaranteedTailCallOpt && IsFastCall)
5771 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5772
5773 assert(!(IsFastCall && CFlags.IsVarArg) &&((!(IsFastCall && CFlags.IsVarArg) && "fastcc not supported on varargs functions"
) ? static_cast<void> (0) : __assert_fail ("!(IsFastCall && CFlags.IsVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5774, __PRETTY_FUNCTION__))
5774 "fastcc not supported on varargs functions")((!(IsFastCall && CFlags.IsVarArg) && "fastcc not supported on varargs functions"
) ? static_cast<void> (0) : __assert_fail ("!(IsFastCall && CFlags.IsVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-13~++20210413100635+64c24f493e5f/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5774, __PRETTY_FUNCTION__))
;
5775
5776 // Count how many bytes are to be pushed on the stack, including the linkage
5777 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
5778 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
5779 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
5780 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5781 unsigned NumBytes = LinkageSize;
5782 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5783
5784 static const MCPhysReg GPR[] = {
5785 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5786 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5787 };
5788 static const MCPhysReg VR[] = {
5789 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5790 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5791 };
5792
5793 const unsigned NumGPRs = array_lengthof(GPR);
5794 const unsigned NumFPRs = useSoftFloat() ? 0 : 13;
5795 const unsigned NumVRs = array_lengthof(VR);
5796
5797 // On ELFv2, we can avoid allocating the parameter area if all the arguments
5798 // can be passed to the callee in registers.
5799 // For the fast calling convention, there is another check below.
5800 // Note: We should keep consistent with LowerFormalArguments_64SVR4()
5801 bool HasParameterArea = !isELFv2ABI || CFlags.IsVarArg || IsFastCall;
5802 if (!HasParameterArea) {
5803 unsigned ParamAreaSize = NumGPRs * PtrByteSize;
5804 unsigned AvailableFPRs = NumFPRs;
5805 unsigned AvailableVRs = NumVRs;
5806 unsigned NumBytesTmp = NumBytes;
5807 for (unsigned i = 0; i != NumOps; ++i) {
5808 if (Outs[i].Flags.isNest()) continue;
5809 if (CalculateStackSlotUsed(Outs[i].VT, Outs[i].ArgVT, Outs[i].Flags,
5810 PtrByteSize, LinkageSize, ParamAreaSize,
5811 NumBytesTmp, AvailableFPRs, AvailableVRs))
5812 HasParameterArea = true;
5813 }
5814 }
5815
5816 // When using the fast calling convention, we don't provide backing for
5817 // arguments that will be in registers.
5818 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
5819
5820 // Avoid allocating parameter area for fastcc functions if all the arguments
5821 // can be passed in the registers.
5822 if (IsFastCall)
5823 HasParameterArea = false;
5824
5825 // Add up all the space actually used.
5826 for (