Bug Summary

File:build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Warning:line 9973, column 31
1st function call argument is an uninitialized value

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name PPCISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-15/lib/clang/15.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/llvm/lib/Target/PowerPC -I include -I /build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-15/lib/clang/15.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/= -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-04-20-140412-16051-1 -x c++ /build/llvm-toolchain-snapshot-15~++20220420111733+e13d2efed663/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
14#include "MCTargetDesc/PPCPredicates.h"
15#include "PPC.h"
16#include "PPCCCState.h"
17#include "PPCCallingConv.h"
18#include "PPCFrameLowering.h"
19#include "PPCInstrInfo.h"
20#include "PPCMachineFunctionInfo.h"
21#include "PPCPerfectShuffle.h"
22#include "PPCRegisterInfo.h"
23#include "PPCSubtarget.h"
24#include "PPCTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/None.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
36#include "llvm/ADT/StringSwitch.h"
37#include "llvm/CodeGen/CallingConvLower.h"
38#include "llvm/CodeGen/ISDOpcodes.h"
39#include "llvm/CodeGen/MachineBasicBlock.h"
40#include "llvm/CodeGen/MachineFrameInfo.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineInstr.h"
43#include "llvm/CodeGen/MachineInstrBuilder.h"
44#include "llvm/CodeGen/MachineJumpTableInfo.h"
45#include "llvm/CodeGen/MachineLoopInfo.h"
46#include "llvm/CodeGen/MachineMemOperand.h"
47#include "llvm/CodeGen/MachineModuleInfo.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/RuntimeLibcalls.h"
51#include "llvm/CodeGen/SelectionDAG.h"
52#include "llvm/CodeGen/SelectionDAGNodes.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetLowering.h"
55#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
56#include "llvm/CodeGen/TargetRegisterInfo.h"
57#include "llvm/CodeGen/ValueTypes.h"
58#include "llvm/IR/CallingConv.h"
59#include "llvm/IR/Constant.h"
60#include "llvm/IR/Constants.h"
61#include "llvm/IR/DataLayout.h"
62#include "llvm/IR/DebugLoc.h"
63#include "llvm/IR/DerivedTypes.h"
64#include "llvm/IR/Function.h"
65#include "llvm/IR/GlobalValue.h"
66#include "llvm/IR/IRBuilder.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/Intrinsics.h"
69#include "llvm/IR/IntrinsicsPowerPC.h"
70#include "llvm/IR/Module.h"
71#include "llvm/IR/Type.h"
72#include "llvm/IR/Use.h"
73#include "llvm/IR/Value.h"
74#include "llvm/MC/MCContext.h"
75#include "llvm/MC/MCExpr.h"
76#include "llvm/MC/MCRegisterInfo.h"
77#include "llvm/MC/MCSectionXCOFF.h"
78#include "llvm/MC/MCSymbolXCOFF.h"
79#include "llvm/Support/AtomicOrdering.h"
80#include "llvm/Support/BranchProbability.h"
81#include "llvm/Support/Casting.h"
82#include "llvm/Support/CodeGen.h"
83#include "llvm/Support/CommandLine.h"
84#include "llvm/Support/Compiler.h"
85#include "llvm/Support/Debug.h"
86#include "llvm/Support/ErrorHandling.h"
87#include "llvm/Support/Format.h"
88#include "llvm/Support/KnownBits.h"
89#include "llvm/Support/MachineValueType.h"
90#include "llvm/Support/MathExtras.h"
91#include "llvm/Support/raw_ostream.h"
92#include "llvm/Target/TargetMachine.h"
93#include "llvm/Target/TargetOptions.h"
94#include <algorithm>
95#include <cassert>
96#include <cstdint>
97#include <iterator>
98#include <list>
99#include <utility>
100#include <vector>
101
102using namespace llvm;
103
104#define DEBUG_TYPE"ppc-lowering" "ppc-lowering"
105
106static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
107cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
108
109static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
110cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
111
112static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
113cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
114
115static cl::opt<bool> DisableSCO("disable-ppc-sco",
116cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
117
118static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
119cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
120
121static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
122cl::desc("use absolute jump tables on ppc"), cl::Hidden);
123
124static cl::opt<bool> EnableQuadwordAtomics(
125 "ppc-quadword-atomics",
126 cl::desc("enable quadword lock-free atomic operations"), cl::init(false),
127 cl::Hidden);
128
129static cl::opt<bool>
130 DisablePerfectShuffle("ppc-disable-perfect-shuffle",
131 cl::desc("disable vector permute decomposition"),
132 cl::init(true), cl::Hidden);
133
134STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"ppc-lowering", "NumTailCalls"
, "Number of tail calls"}
;
135STATISTIC(NumSiblingCalls, "Number of sibling calls")static llvm::Statistic NumSiblingCalls = {"ppc-lowering", "NumSiblingCalls"
, "Number of sibling calls"}
;
136STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM")static llvm::Statistic ShufflesHandledWithVPERM = {"ppc-lowering"
, "ShufflesHandledWithVPERM", "Number of shuffles lowered to a VPERM"
}
;
137STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed")static llvm::Statistic NumDynamicAllocaProbed = {"ppc-lowering"
, "NumDynamicAllocaProbed", "Number of dynamic stack allocation probed"
}
;
138
139static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
140
141static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
142
143static const char AIXSSPCanaryWordName[] = "__ssp_canary_word";
144
145// FIXME: Remove this once the bug has been fixed!
146extern cl::opt<bool> ANDIGlueBug;
147
148PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
149 const PPCSubtarget &STI)
150 : TargetLowering(TM), Subtarget(STI) {
151 // Initialize map that relates the PPC addressing modes to the computed flags
152 // of a load/store instruction. The map is used to determine the optimal
153 // addressing mode when selecting load and stores.
154 initializeAddrModeMap();
155 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
156 // arguments are at least 4/8 bytes aligned.
157 bool isPPC64 = Subtarget.isPPC64();
158 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
159
160 // Set up the register classes.
161 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
162 if (!useSoftFloat()) {
163 if (hasSPE()) {
164 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
165 // EFPU2 APU only supports f32
166 if (!Subtarget.hasEFPU2())
167 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
168 } else {
169 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
170 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
171 }
172 }
173
174 // Match BITREVERSE to customized fast code sequence in the td file.
175 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
176 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
177
178 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
179 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
180
181 // Custom lower inline assembly to check for special registers.
182 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
183 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom);
184
185 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
186 for (MVT VT : MVT::integer_valuetypes()) {
187 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
188 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
189 }
190
191 if (Subtarget.isISA3_0()) {
192 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
193 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
194 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
195 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
196 } else {
197 // No extending loads from f16 or HW conversions back and forth.
198 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
199 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
200 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
201 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
202 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
203 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
204 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
205 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
206 }
207
208 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
209
210 // PowerPC has pre-inc load and store's.
211 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
212 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
213 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
214 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
215 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
216 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
217 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
218 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
219 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
220 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
221 if (!Subtarget.hasSPE()) {
222 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
223 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
224 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
225 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
226 }
227
228 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
229 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
230 for (MVT VT : ScalarIntVTs) {
231 setOperationAction(ISD::ADDC, VT, Legal);
232 setOperationAction(ISD::ADDE, VT, Legal);
233 setOperationAction(ISD::SUBC, VT, Legal);
234 setOperationAction(ISD::SUBE, VT, Legal);
235 }
236
237 if (Subtarget.useCRBits()) {
238 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
239
240 if (isPPC64 || Subtarget.hasFPCVT()) {
241 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Promote);
242 AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1,
243 isPPC64 ? MVT::i64 : MVT::i32);
244 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Promote);
245 AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1,
246 isPPC64 ? MVT::i64 : MVT::i32);
247
248 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
249 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
250 isPPC64 ? MVT::i64 : MVT::i32);
251 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
252 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
253 isPPC64 ? MVT::i64 : MVT::i32);
254
255 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i1, Promote);
256 AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1,
257 isPPC64 ? MVT::i64 : MVT::i32);
258 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i1, Promote);
259 AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1,
260 isPPC64 ? MVT::i64 : MVT::i32);
261
262 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
263 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1,
264 isPPC64 ? MVT::i64 : MVT::i32);
265 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
266 AddPromotedToType(ISD::FP_TO_UINT, MVT::i1,
267 isPPC64 ? MVT::i64 : MVT::i32);
268 } else {
269 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom);
270 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom);
271 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
272 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
273 }
274
275 // PowerPC does not support direct load/store of condition registers.
276 setOperationAction(ISD::LOAD, MVT::i1, Custom);
277 setOperationAction(ISD::STORE, MVT::i1, Custom);
278
279 // FIXME: Remove this once the ANDI glue bug is fixed:
280 if (ANDIGlueBug)
281 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
282
283 for (MVT VT : MVT::integer_valuetypes()) {
284 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
285 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
286 setTruncStoreAction(VT, MVT::i1, Expand);
287 }
288
289 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
290 }
291
292 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
293 // PPC (the libcall is not available).
294 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
295 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
296 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::ppcf128, Custom);
297 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::ppcf128, Custom);
298
299 // We do not currently implement these libm ops for PowerPC.
300 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
301 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
302 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
303 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
304 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
305 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
306
307 // PowerPC has no SREM/UREM instructions unless we are on P9
308 // On P9 we may use a hardware instruction to compute the remainder.
309 // When the result of both the remainder and the division is required it is
310 // more efficient to compute the remainder from the result of the division
311 // rather than use the remainder instruction. The instructions are legalized
312 // directly because the DivRemPairsPass performs the transformation at the IR
313 // level.
314 if (Subtarget.isISA3_0()) {
315 setOperationAction(ISD::SREM, MVT::i32, Legal);
316 setOperationAction(ISD::UREM, MVT::i32, Legal);
317 setOperationAction(ISD::SREM, MVT::i64, Legal);
318 setOperationAction(ISD::UREM, MVT::i64, Legal);
319 } else {
320 setOperationAction(ISD::SREM, MVT::i32, Expand);
321 setOperationAction(ISD::UREM, MVT::i32, Expand);
322 setOperationAction(ISD::SREM, MVT::i64, Expand);
323 setOperationAction(ISD::UREM, MVT::i64, Expand);
324 }
325
326 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
327 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
328 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
329 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
330 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
331 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
332 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
333 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
334 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
335
336 // Handle constrained floating-point operations of scalar.
337 // TODO: Handle SPE specific operation.
338 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
339 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
340 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
341 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
342 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
343
344 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
345 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
346 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
347 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
348
349 if (!Subtarget.hasSPE()) {
350 setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal);
351 setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal);
352 }
353
354 if (Subtarget.hasVSX()) {
355 setOperationAction(ISD::STRICT_FRINT, MVT::f32, Legal);
356 setOperationAction(ISD::STRICT_FRINT, MVT::f64, Legal);
357 }
358
359 if (Subtarget.hasFSQRT()) {
360 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
361 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
362 }
363
364 if (Subtarget.hasFPRND()) {
365 setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal);
366 setOperationAction(ISD::STRICT_FCEIL, MVT::f32, Legal);
367 setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal);
368 setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal);
369
370 setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal);
371 setOperationAction(ISD::STRICT_FCEIL, MVT::f64, Legal);
372 setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal);
373 setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal);
374 }
375
376 // We don't support sin/cos/sqrt/fmod/pow
377 setOperationAction(ISD::FSIN , MVT::f64, Expand);
378 setOperationAction(ISD::FCOS , MVT::f64, Expand);
379 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
380 setOperationAction(ISD::FREM , MVT::f64, Expand);
381 setOperationAction(ISD::FPOW , MVT::f64, Expand);
382 setOperationAction(ISD::FSIN , MVT::f32, Expand);
383 setOperationAction(ISD::FCOS , MVT::f32, Expand);
384 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
385 setOperationAction(ISD::FREM , MVT::f32, Expand);
386 setOperationAction(ISD::FPOW , MVT::f32, Expand);
387
388 // MASS transformation for LLVM intrinsics with replicating fast-math flag
389 // to be consistent to PPCGenScalarMASSEntries pass
390 if (TM.getOptLevel() == CodeGenOpt::Aggressive &&
391 TM.Options.PPCGenScalarMASSEntries) {
392 setOperationAction(ISD::FSIN , MVT::f64, Custom);
393 setOperationAction(ISD::FCOS , MVT::f64, Custom);
394 setOperationAction(ISD::FPOW , MVT::f64, Custom);
395 setOperationAction(ISD::FLOG, MVT::f64, Custom);
396 setOperationAction(ISD::FLOG10, MVT::f64, Custom);
397 setOperationAction(ISD::FEXP, MVT::f64, Custom);
398 setOperationAction(ISD::FSIN , MVT::f32, Custom);
399 setOperationAction(ISD::FCOS , MVT::f32, Custom);
400 setOperationAction(ISD::FPOW , MVT::f32, Custom);
401 setOperationAction(ISD::FLOG, MVT::f32, Custom);
402 setOperationAction(ISD::FLOG10, MVT::f32, Custom);
403 setOperationAction(ISD::FEXP, MVT::f32, Custom);
404 }
405
406 if (Subtarget.hasSPE()) {
407 setOperationAction(ISD::FMA , MVT::f64, Expand);
408 setOperationAction(ISD::FMA , MVT::f32, Expand);
409 } else {
410 setOperationAction(ISD::FMA , MVT::f64, Legal);
411 setOperationAction(ISD::FMA , MVT::f32, Legal);
412 }
413
414 if (Subtarget.hasSPE())
415 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
416
417 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
418
419 // If we're enabling GP optimizations, use hardware square root
420 if (!Subtarget.hasFSQRT() &&
421 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
422 Subtarget.hasFRE()))
423 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
424
425 if (!Subtarget.hasFSQRT() &&
426 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
427 Subtarget.hasFRES()))
428 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
429
430 if (Subtarget.hasFCPSGN()) {
431 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
432 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
433 } else {
434 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
435 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
436 }
437
438 if (Subtarget.hasFPRND()) {
439 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
440 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
441 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
442 setOperationAction(ISD::FROUND, MVT::f64, Legal);
443
444 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
445 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
446 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
447 setOperationAction(ISD::FROUND, MVT::f32, Legal);
448 }
449
450 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
451 // to speed up scalar BSWAP64.
452 // CTPOP or CTTZ were introduced in P8/P9 respectively
453 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
454 if (Subtarget.hasP9Vector() && Subtarget.isPPC64())
455 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
456 else
457 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
458 if (Subtarget.isISA3_0()) {
459 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
460 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
461 } else {
462 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
463 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
464 }
465
466 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
467 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
468 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
469 } else {
470 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
471 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
472 }
473
474 // PowerPC does not have ROTR
475 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
476 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
477
478 if (!Subtarget.useCRBits()) {
479 // PowerPC does not have Select
480 setOperationAction(ISD::SELECT, MVT::i32, Expand);
481 setOperationAction(ISD::SELECT, MVT::i64, Expand);
482 setOperationAction(ISD::SELECT, MVT::f32, Expand);
483 setOperationAction(ISD::SELECT, MVT::f64, Expand);
484 }
485
486 // PowerPC wants to turn select_cc of FP into fsel when possible.
487 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
488 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
489
490 // PowerPC wants to optimize integer setcc a bit
491 if (!Subtarget.useCRBits())
492 setOperationAction(ISD::SETCC, MVT::i32, Custom);
493
494 if (Subtarget.hasFPU()) {
495 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal);
496 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal);
497 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal);
498
499 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
500 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
501 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal);
502 }
503
504 // PowerPC does not have BRCOND which requires SetCC
505 if (!Subtarget.useCRBits())
506 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
507
508 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
509
510 if (Subtarget.hasSPE()) {
511 // SPE has built-in conversions
512 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal);
513 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Legal);
514 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Legal);
515 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
516 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
517 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
518
519 // SPE supports signaling compare of f32/f64.
520 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
521 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
522 } else {
523 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
524 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
525 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
526
527 // PowerPC does not have [U|S]INT_TO_FP
528 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Expand);
529 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Expand);
530 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
531 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
532 }
533
534 if (Subtarget.hasDirectMove() && isPPC64) {
535 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
536 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
537 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
538 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
539 if (TM.Options.UnsafeFPMath) {
540 setOperationAction(ISD::LRINT, MVT::f64, Legal);
541 setOperationAction(ISD::LRINT, MVT::f32, Legal);
542 setOperationAction(ISD::LLRINT, MVT::f64, Legal);
543 setOperationAction(ISD::LLRINT, MVT::f32, Legal);
544 setOperationAction(ISD::LROUND, MVT::f64, Legal);
545 setOperationAction(ISD::LROUND, MVT::f32, Legal);
546 setOperationAction(ISD::LLROUND, MVT::f64, Legal);
547 setOperationAction(ISD::LLROUND, MVT::f32, Legal);
548 }
549 } else {
550 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
551 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
552 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
553 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
554 }
555
556 // We cannot sextinreg(i1). Expand to shifts.
557 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
558
559 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
560 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
561 // support continuation, user-level threading, and etc.. As a result, no
562 // other SjLj exception interfaces are implemented and please don't build
563 // your own exception handling based on them.
564 // LLVM/Clang supports zero-cost DWARF exception handling.
565 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
566 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
567
568 // We want to legalize GlobalAddress and ConstantPool nodes into the
569 // appropriate instructions to materialize the address.
570 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
571 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
572 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
573 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
574 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
575 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
577 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
578 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
579 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
580
581 // TRAP is legal.
582 setOperationAction(ISD::TRAP, MVT::Other, Legal);
583
584 // TRAMPOLINE is custom lowered.
585 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
586 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
587
588 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
589 setOperationAction(ISD::VASTART , MVT::Other, Custom);
590
591 if (Subtarget.is64BitELFABI()) {
592 // VAARG always uses double-word chunks, so promote anything smaller.
593 setOperationAction(ISD::VAARG, MVT::i1, Promote);
594 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
595 setOperationAction(ISD::VAARG, MVT::i8, Promote);
596 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
597 setOperationAction(ISD::VAARG, MVT::i16, Promote);
598 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
599 setOperationAction(ISD::VAARG, MVT::i32, Promote);
600 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
601 setOperationAction(ISD::VAARG, MVT::Other, Expand);
602 } else if (Subtarget.is32BitELFABI()) {
603 // VAARG is custom lowered with the 32-bit SVR4 ABI.
604 setOperationAction(ISD::VAARG, MVT::Other, Custom);
605 setOperationAction(ISD::VAARG, MVT::i64, Custom);
606 } else
607 setOperationAction(ISD::VAARG, MVT::Other, Expand);
608
609 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
610 if (Subtarget.is32BitELFABI())
611 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
612 else
613 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
614
615 // Use the default implementation.
616 setOperationAction(ISD::VAEND , MVT::Other, Expand);
617 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
618 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
619 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
620 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
621 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
622 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
623 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
624 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
625
626 // We want to custom lower some of our intrinsics.
627 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
628 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f64, Custom);
629 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::ppcf128, Custom);
630 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
631 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f64, Custom);
632
633 // To handle counter-based loop conditions.
634 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
635
636 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
637 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
638 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
639 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
640
641 // Comparisons that require checking two conditions.
642 if (Subtarget.hasSPE()) {
643 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
644 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
645 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
646 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
647 }
648 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
649 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
650 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
651 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
652 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
653 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
654 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
655 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
656 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
657 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
658 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
659 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
660
661 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
662 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
663
664 if (Subtarget.has64BitSupport()) {
665 // They also have instructions for converting between i64 and fp.
666 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
667 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand);
668 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
669 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand);
670 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
671 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
672 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
673 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
674 // This is just the low 32 bits of a (signed) fp->i64 conversion.
675 // We cannot do this with Promote because i64 is not a legal type.
676 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
677 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
678
679 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
680 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
681 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
682 }
683 } else {
684 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
685 if (Subtarget.hasSPE()) {
686 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal);
687 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
688 } else {
689 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand);
690 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
691 }
692 }
693
694 // With the instructions enabled under FPCVT, we can do everything.
695 if (Subtarget.hasFPCVT()) {
696 if (Subtarget.has64BitSupport()) {
697 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
698 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
699 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
700 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
701 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
702 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
703 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
704 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
705 }
706
707 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
708 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
709 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
710 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
711 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
712 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
713 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
714 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
715 }
716
717 if (Subtarget.use64BitRegs()) {
718 // 64-bit PowerPC implementations can support i64 types directly
719 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
720 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
721 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
722 // 64-bit PowerPC wants to expand i128 shifts itself.
723 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
724 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
725 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
726 } else {
727 // 32-bit PowerPC wants to expand i64 shifts itself.
728 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
729 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
730 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
731 }
732
733 // PowerPC has better expansions for funnel shifts than the generic
734 // TargetLowering::expandFunnelShift.
735 if (Subtarget.has64BitSupport()) {
736 setOperationAction(ISD::FSHL, MVT::i64, Custom);
737 setOperationAction(ISD::FSHR, MVT::i64, Custom);
738 }
739 setOperationAction(ISD::FSHL, MVT::i32, Custom);
740 setOperationAction(ISD::FSHR, MVT::i32, Custom);
741
742 if (Subtarget.hasVSX()) {
743 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
744 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
745 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
746 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
747 }
748
749 if (Subtarget.hasAltivec()) {
750 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
751 setOperationAction(ISD::SADDSAT, VT, Legal);
752 setOperationAction(ISD::SSUBSAT, VT, Legal);
753 setOperationAction(ISD::UADDSAT, VT, Legal);
754 setOperationAction(ISD::USUBSAT, VT, Legal);
755 }
756 // First set operation action for all vector types to expand. Then we
757 // will selectively turn on ones that can be effectively codegen'd.
758 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
759 // add/sub are legal for all supported vector VT's.
760 setOperationAction(ISD::ADD, VT, Legal);
761 setOperationAction(ISD::SUB, VT, Legal);
762
763 // For v2i64, these are only valid with P8Vector. This is corrected after
764 // the loop.
765 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
766 setOperationAction(ISD::SMAX, VT, Legal);
767 setOperationAction(ISD::SMIN, VT, Legal);
768 setOperationAction(ISD::UMAX, VT, Legal);
769 setOperationAction(ISD::UMIN, VT, Legal);
770 }
771 else {
772 setOperationAction(ISD::SMAX, VT, Expand);
773 setOperationAction(ISD::SMIN, VT, Expand);
774 setOperationAction(ISD::UMAX, VT, Expand);
775 setOperationAction(ISD::UMIN, VT, Expand);
776 }
777
778 if (Subtarget.hasVSX()) {
779 setOperationAction(ISD::FMAXNUM, VT, Legal);
780 setOperationAction(ISD::FMINNUM, VT, Legal);
781 }
782
783 // Vector instructions introduced in P8
784 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
785 setOperationAction(ISD::CTPOP, VT, Legal);
786 setOperationAction(ISD::CTLZ, VT, Legal);
787 }
788 else {
789 setOperationAction(ISD::CTPOP, VT, Expand);
790 setOperationAction(ISD::CTLZ, VT, Expand);
791 }
792
793 // Vector instructions introduced in P9
794 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
795 setOperationAction(ISD::CTTZ, VT, Legal);
796 else
797 setOperationAction(ISD::CTTZ, VT, Expand);
798
799 // We promote all shuffles to v16i8.
800 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
801 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
802
803 // We promote all non-typed operations to v4i32.
804 setOperationAction(ISD::AND , VT, Promote);
805 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
806 setOperationAction(ISD::OR , VT, Promote);
807 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
808 setOperationAction(ISD::XOR , VT, Promote);
809 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
810 setOperationAction(ISD::LOAD , VT, Promote);
811 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
812 setOperationAction(ISD::SELECT, VT, Promote);
813 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
814 setOperationAction(ISD::VSELECT, VT, Legal);
815 setOperationAction(ISD::SELECT_CC, VT, Promote);
816 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
817 setOperationAction(ISD::STORE, VT, Promote);
818 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
819
820 // No other operations are legal.
821 setOperationAction(ISD::MUL , VT, Expand);
822 setOperationAction(ISD::SDIV, VT, Expand);
823 setOperationAction(ISD::SREM, VT, Expand);
824 setOperationAction(ISD::UDIV, VT, Expand);
825 setOperationAction(ISD::UREM, VT, Expand);
826 setOperationAction(ISD::FDIV, VT, Expand);
827 setOperationAction(ISD::FREM, VT, Expand);
828 setOperationAction(ISD::FNEG, VT, Expand);
829 setOperationAction(ISD::FSQRT, VT, Expand);
830 setOperationAction(ISD::FLOG, VT, Expand);
831 setOperationAction(ISD::FLOG10, VT, Expand);
832 setOperationAction(ISD::FLOG2, VT, Expand);
833 setOperationAction(ISD::FEXP, VT, Expand);
834 setOperationAction(ISD::FEXP2, VT, Expand);
835 setOperationAction(ISD::FSIN, VT, Expand);
836 setOperationAction(ISD::FCOS, VT, Expand);
837 setOperationAction(ISD::FABS, VT, Expand);
838 setOperationAction(ISD::FFLOOR, VT, Expand);
839 setOperationAction(ISD::FCEIL, VT, Expand);
840 setOperationAction(ISD::FTRUNC, VT, Expand);
841 setOperationAction(ISD::FRINT, VT, Expand);
842 setOperationAction(ISD::FNEARBYINT, VT, Expand);
843 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
844 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
845 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
846 setOperationAction(ISD::MULHU, VT, Expand);
847 setOperationAction(ISD::MULHS, VT, Expand);
848 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
849 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
850 setOperationAction(ISD::UDIVREM, VT, Expand);
851 setOperationAction(ISD::SDIVREM, VT, Expand);
852 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
853 setOperationAction(ISD::FPOW, VT, Expand);
854 setOperationAction(ISD::BSWAP, VT, Expand);
855 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
856 setOperationAction(ISD::ROTL, VT, Expand);
857 setOperationAction(ISD::ROTR, VT, Expand);
858
859 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
860 setTruncStoreAction(VT, InnerVT, Expand);
861 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
862 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
863 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
864 }
865 }
866 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand);
867 if (!Subtarget.hasP8Vector()) {
868 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
869 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
870 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
871 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
872 }
873
874 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
875 // with merges, splats, etc.
876 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
877
878 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
879 // are cheap, so handle them before they get expanded to scalar.
880 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
881 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
882 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
883 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
884 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
885
886 setOperationAction(ISD::AND , MVT::v4i32, Legal);
887 setOperationAction(ISD::OR , MVT::v4i32, Legal);
888 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
889 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
890 setOperationAction(ISD::SELECT, MVT::v4i32,
891 Subtarget.useCRBits() ? Legal : Expand);
892 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
893 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
894 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
895 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
896 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
897 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
898 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
899 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
900 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
901 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
902 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
903 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
904 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
905
906 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
907 setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
908 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
909 if (Subtarget.hasAltivec())
910 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
911 setOperationAction(ISD::ROTL, VT, Legal);
912 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
913 if (Subtarget.hasP8Altivec())
914 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
915
916 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
917 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
918 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
919 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
920
921 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
922 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
923
924 if (Subtarget.hasVSX()) {
925 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
926 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
927 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
928 }
929
930 if (Subtarget.hasP8Altivec())
931 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
932 else
933 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
934
935 if (Subtarget.isISA3_1()) {
936 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
937 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
938 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
939 setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
940 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
941 setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
942 setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
943 setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
944 setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
945 setOperationAction(ISD::UREM, MVT::v2i64, Legal);
946 setOperationAction(ISD::SREM, MVT::v2i64, Legal);
947 setOperationAction(ISD::UREM, MVT::v4i32, Legal);
948 setOperationAction(ISD::SREM, MVT::v4i32, Legal);
949 setOperationAction(ISD::UREM, MVT::v1i128, Legal);
950 setOperationAction(ISD::SREM, MVT::v1i128, Legal);
951 setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
952 setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
953 setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
954 }
955
956 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
957 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
958
959 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
960 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
961
962 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
963 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
964 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
965 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
966
967 // Altivec does not contain unordered floating-point compare instructions
968 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
969 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
970 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
971 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
972
973 if (Subtarget.hasVSX()) {
974 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
975 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
976 if (Subtarget.hasP8Vector()) {
977 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
979 }
980 if (Subtarget.hasDirectMove() && isPPC64) {
981 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
982 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
983 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
985 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
988 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
989 }
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
991
992 // The nearbyint variants are not allowed to raise the inexact exception
993 // so we can only code-gen them with unsafe math.
994 if (TM.Options.UnsafeFPMath) {
995 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
996 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
997 }
998
999 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1000 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1001 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1002 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1003 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1004 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
1005 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1006 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1007
1008 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1009 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1010 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
1011 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1012 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1013
1014 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
1015 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1016
1017 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
1018 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
1019
1020 // Share the Altivec comparison restrictions.
1021 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
1022 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
1023 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
1024 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
1025
1026 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1027 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
1028
1029 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
1030
1031 if (Subtarget.hasP8Vector())
1032 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
1033
1034 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
1035
1036 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
1037 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
1038 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
1039
1040 if (Subtarget.hasP8Altivec()) {
1041 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1042 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
1043 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1044
1045 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1046 // SRL, but not for SRA because of the instructions available:
1047 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
1048 // doing
1049 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
1050 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
1051 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1052
1053 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
1054 }
1055 else {
1056 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1057 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
1058 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
1059
1060 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1061
1062 // VSX v2i64 only supports non-arithmetic operations.
1063 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
1064 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
1065 }
1066
1067 if (Subtarget.isISA3_1())
1068 setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
1069 else
1070 setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
1071
1072 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
1073 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
1074 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
1075 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
1076
1077 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
1078
1079 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
1080 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
1081 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
1082 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
1083 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1084 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1085 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1086 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1087
1088 // Custom handling for partial vectors of integers converted to
1089 // floating point. We already have optimal handling for v2i32 through
1090 // the DAG combine, so those aren't necessary.
1091 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom);
1092 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom);
1093 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
1094 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
1095 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom);
1096 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom);
1097 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
1098 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
1099 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
1100 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1103 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom);
1104 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
1105 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
1106 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
1107
1108 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1109 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
1111 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1112 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
1113 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
1114
1115 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1116 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1117
1118 // Handle constrained floating-point operations of vector.
1119 // The predictor is `hasVSX` because altivec instruction has
1120 // no exception but VSX vector instruction has.
1121 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
1122 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
1123 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
1124 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
1125 setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal);
1126 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
1127 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v4f32, Legal);
1128 setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal);
1129 setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal);
1130 setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
1131 setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal);
1132 setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
1133 setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
1134
1135 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
1136 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
1137 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
1138 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
1139 setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal);
1140 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1141 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v2f64, Legal);
1142 setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal);
1143 setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal);
1144 setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
1145 setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal);
1146 setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
1147 setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
1148
1149 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1150 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1151
1152 for (MVT FPT : MVT::fp_valuetypes())
1153 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1154
1155 // Expand the SELECT to SELECT_CC
1156 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1157
1158 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1159 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1160
1161 // No implementation for these ops for PowerPC.
1162 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1163 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1164 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1165 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
1166 setOperationAction(ISD::FREM, MVT::f128, Expand);
1167 }
1168
1169 if (Subtarget.hasP8Altivec()) {
1170 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
1171 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
1172 }
1173
1174 if (Subtarget.hasP9Vector()) {
1175 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1176 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1177
1178 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1179 // SRL, but not for SRA because of the instructions available:
1180 // VS{RL} and VS{RL}O.
1181 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1182 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
1183 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1184
1185 setOperationAction(ISD::FADD, MVT::f128, Legal);
1186 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1187 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1188 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1189 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1190
1191 setOperationAction(ISD::FMA, MVT::f128, Legal);
1192 setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
1193 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
1194 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
1195 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
1196 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
1197 setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
1198
1199 setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
1200 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1201 setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
1202 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1203 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
1204 setOperationAction(ISD::FROUND, MVT::f128, Legal);
1205
1206 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1207 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
1208 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
1209
1210 // Handle constrained floating-point operations of fp128
1211 setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
1212 setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
1213 setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
1214 setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
1215 setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
1216 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
1217 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
1218 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
1219 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
1220 setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
1221 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
1222 setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
1223 setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
1224 setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
1225 setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
1226 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1227 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1228 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1229 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
1230 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
1231 } else if (Subtarget.hasVSX()) {
1232 setOperationAction(ISD::LOAD, MVT::f128, Promote);
1233 setOperationAction(ISD::STORE, MVT::f128, Promote);
1234
1235 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
1236 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
1237
1238 // Set FADD/FSUB as libcall to avoid the legalizer to expand the
1239 // fp_to_uint and int_to_fp.
1240 setOperationAction(ISD::FADD, MVT::f128, LibCall);
1241 setOperationAction(ISD::FSUB, MVT::f128, LibCall);
1242
1243 setOperationAction(ISD::FMUL, MVT::f128, Expand);
1244 setOperationAction(ISD::FDIV, MVT::f128, Expand);
1245 setOperationAction(ISD::FNEG, MVT::f128, Expand);
1246 setOperationAction(ISD::FABS, MVT::f128, Expand);
1247 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
1248 setOperationAction(ISD::FMA, MVT::f128, Expand);
1249 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1250
1251 // Expand the fp_extend if the target type is fp128.
1252 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
1253 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Expand);
1254
1255 // Expand the fp_round if the source type is fp128.
1256 for (MVT VT : {MVT::f32, MVT::f64}) {
1257 setOperationAction(ISD::FP_ROUND, VT, Custom);
1258 setOperationAction(ISD::STRICT_FP_ROUND, VT, Custom);
1259 }
1260
1261 setOperationAction(ISD::SETCC, MVT::f128, Custom);
1262 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Custom);
1263 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom);
1264 setOperationAction(ISD::BR_CC, MVT::f128, Expand);
1265
1266 // Lower following f128 select_cc pattern:
1267 // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv, NE
1268 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1269
1270 // We need to handle f128 SELECT_CC with integer result type.
1271 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1272 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand);
1273 }
1274
1275 if (Subtarget.hasP9Altivec()) {
1276 if (Subtarget.isISA3_1()) {
1277 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
1278 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Legal);
1279 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Legal);
1280 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
1281 } else {
1282 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1283 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1284 }
1285 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
1286 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
1287 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
1288 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
1289 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1290 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
1291 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
1292 }
1293
1294 if (Subtarget.hasP10Vector()) {
1295 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1296 }
1297 }
1298
1299 if (Subtarget.pairedVectorMemops()) {
1300 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
1301 setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
1302 setOperationAction(ISD::STORE, MVT::v256i1, Custom);
1303 }
1304 if (Subtarget.hasMMA()) {
1305 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1306 setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
1307 setOperationAction(ISD::STORE, MVT::v512i1, Custom);
1308 setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom);
1309 }
1310
1311 if (Subtarget.has64BitSupport())
1312 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
1313
1314 if (Subtarget.isISA3_1())
1315 setOperationAction(ISD::SRA, MVT::v1i128, Legal);
1316
1317 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1318
1319 if (!isPPC64) {
1320 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
1321 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
1322 }
1323
1324 if (shouldInlineQuadwordAtomics()) {
1325 setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom);
1326 setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom);
1327 setOperationAction(ISD::INTRINSIC_VOID, MVT::i128, Custom);
1328 }
1329
1330 setBooleanContents(ZeroOrOneBooleanContent);
1331
1332 if (Subtarget.hasAltivec()) {
1333 // Altivec instructions set fields to all zeros or all ones.
1334 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
1335 }
1336
1337 setLibcallName(RTLIB::MULO_I128, nullptr);
1338 if (!isPPC64) {
1339 // These libcalls are not available in 32-bit.
1340 setLibcallName(RTLIB::SHL_I128, nullptr);
1341 setLibcallName(RTLIB::SRL_I128, nullptr);
1342 setLibcallName(RTLIB::SRA_I128, nullptr);
1343 setLibcallName(RTLIB::MUL_I128, nullptr);
1344 setLibcallName(RTLIB::MULO_I64, nullptr);
1345 }
1346
1347 if (!isPPC64)
1348 setMaxAtomicSizeInBitsSupported(32);
1349 else if (shouldInlineQuadwordAtomics())
1350 setMaxAtomicSizeInBitsSupported(128);
1351 else
1352 setMaxAtomicSizeInBitsSupported(64);
1353
1354 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1355
1356 // We have target-specific dag combine patterns for the following nodes:
1357 setTargetDAGCombine({ISD::ADD, ISD::SHL, ISD::SRA, ISD::SRL, ISD::MUL,
1358 ISD::FMA, ISD::SINT_TO_FP, ISD::BUILD_VECTOR});
1359 if (Subtarget.hasFPCVT())
1360 setTargetDAGCombine(ISD::UINT_TO_FP);
1361 setTargetDAGCombine({ISD::LOAD, ISD::STORE, ISD::BR_CC});
1362 if (Subtarget.useCRBits())
1363 setTargetDAGCombine(ISD::BRCOND);
1364 setTargetDAGCombine({ISD::BSWAP, ISD::INTRINSIC_WO_CHAIN,
1365 ISD::INTRINSIC_W_CHAIN, ISD::INTRINSIC_VOID});
1366
1367 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, ISD::ANY_EXTEND});
1368
1369 setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE});
1370
1371 if (Subtarget.useCRBits()) {
1372 setTargetDAGCombine({ISD::TRUNCATE, ISD::SETCC, ISD::SELECT_CC});
1373 }
1374
1375 if (Subtarget.hasP9Altivec()) {
1376 setTargetDAGCombine({ISD::ABS, ISD::VSELECT});
1377 }
1378
1379 setLibcallName(RTLIB::LOG_F128, "logf128");
1380 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1381 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1382 setLibcallName(RTLIB::EXP_F128, "expf128");
1383 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1384 setLibcallName(RTLIB::SIN_F128, "sinf128");
1385 setLibcallName(RTLIB::COS_F128, "cosf128");
1386 setLibcallName(RTLIB::POW_F128, "powf128");
1387 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1388 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1389 setLibcallName(RTLIB::REM_F128, "fmodf128");
1390 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
1391 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
1392 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
1393 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
1394 setLibcallName(RTLIB::ROUND_F128, "roundf128");
1395 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
1396 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
1397 setLibcallName(RTLIB::RINT_F128, "rintf128");
1398 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
1399 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
1400 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
1401 setLibcallName(RTLIB::FMA_F128, "fmaf128");
1402
1403 // With 32 condition bits, we don't need to sink (and duplicate) compares
1404 // aggressively in CodeGenPrep.
1405 if (Subtarget.useCRBits()) {
1406 setHasMultipleConditionRegisters();
1407 setJumpIsExpensive();
1408 }
1409
1410 setMinFunctionAlignment(Align(4));
1411
1412 switch (Subtarget.getCPUDirective()) {
1413 default: break;
1414 case PPC::DIR_970:
1415 case PPC::DIR_A2:
1416 case PPC::DIR_E500:
1417 case PPC::DIR_E500mc:
1418 case PPC::DIR_E5500:
1419 case PPC::DIR_PWR4:
1420 case PPC::DIR_PWR5:
1421 case PPC::DIR_PWR5X:
1422 case PPC::DIR_PWR6:
1423 case PPC::DIR_PWR6X:
1424 case PPC::DIR_PWR7:
1425 case PPC::DIR_PWR8:
1426 case PPC::DIR_PWR9:
1427 case PPC::DIR_PWR10:
1428 case PPC::DIR_PWR_FUTURE:
1429 setPrefLoopAlignment(Align(16));
1430 setPrefFunctionAlignment(Align(16));
1431 break;
1432 }
1433
1434 if (Subtarget.enableMachineScheduler())
1435 setSchedulingPreference(Sched::Source);
1436 else
1437 setSchedulingPreference(Sched::Hybrid);
1438
1439 computeRegisterProperties(STI.getRegisterInfo());
1440
1441 // The Freescale cores do better with aggressive inlining of memcpy and
1442 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1443 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1444 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1445 MaxStoresPerMemset = 32;
1446 MaxStoresPerMemsetOptSize = 16;
1447 MaxStoresPerMemcpy = 32;
1448 MaxStoresPerMemcpyOptSize = 8;
1449 MaxStoresPerMemmove = 32;
1450 MaxStoresPerMemmoveOptSize = 8;
1451 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1452 // The A2 also benefits from (very) aggressive inlining of memcpy and
1453 // friends. The overhead of a the function call, even when warm, can be
1454 // over one hundred cycles.
1455 MaxStoresPerMemset = 128;
1456 MaxStoresPerMemcpy = 128;
1457 MaxStoresPerMemmove = 128;
1458 MaxLoadsPerMemcmp = 128;
1459 } else {
1460 MaxLoadsPerMemcmp = 8;
1461 MaxLoadsPerMemcmpOptSize = 4;
1462 }
1463
1464 IsStrictFPEnabled = true;
1465
1466 // Let the subtarget (CPU) decide if a predictable select is more expensive
1467 // than the corresponding branch. This information is used in CGP to decide
1468 // when to convert selects into branches.
1469 PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive();
1470}
1471
1472// *********************************** NOTE ************************************
1473// For selecting load and store instructions, the addressing modes are defined
1474// as ComplexPatterns in PPCInstrInfo.td, which are then utilized in the TD
1475// patterns to match the load the store instructions.
1476//
1477// The TD definitions for the addressing modes correspond to their respective
1478// Select<AddrMode>Form() function in PPCISelDAGToDAG.cpp. These functions rely
1479// on SelectOptimalAddrMode(), which calls computeMOFlags() to compute the
1480// address mode flags of a particular node. Afterwards, the computed address
1481// flags are passed into getAddrModeForFlags() in order to retrieve the optimal
1482// addressing mode. SelectOptimalAddrMode() then sets the Base and Displacement
1483// accordingly, based on the preferred addressing mode.
1484//
1485// Within PPCISelLowering.h, there are two enums: MemOpFlags and AddrMode.
1486// MemOpFlags contains all the possible flags that can be used to compute the
1487// optimal addressing mode for load and store instructions.
1488// AddrMode contains all the possible load and store addressing modes available
1489// on Power (such as DForm, DSForm, DQForm, XForm, etc.)
1490//
1491// When adding new load and store instructions, it is possible that new address
1492// flags may need to be added into MemOpFlags, and a new addressing mode will
1493// need to be added to AddrMode. An entry of the new addressing mode (consisting
1494// of the minimal and main distinguishing address flags for the new load/store
1495// instructions) will need to be added into initializeAddrModeMap() below.
1496// Finally, when adding new addressing modes, the getAddrModeForFlags() will
1497// need to be updated to account for selecting the optimal addressing mode.
1498// *****************************************************************************
1499/// Initialize the map that relates the different addressing modes of the load
1500/// and store instructions to a set of flags. This ensures the load/store
1501/// instruction is correctly matched during instruction selection.
1502void PPCTargetLowering::initializeAddrModeMap() {
1503 AddrModesMap[PPC::AM_DForm] = {
1504 // LWZ, STW
1505 PPC::MOF_ZExt | PPC::MOF_RPlusSImm16 | PPC::MOF_WordInt,
1506 PPC::MOF_ZExt | PPC::MOF_RPlusLo | PPC::MOF_WordInt,
1507 PPC::MOF_ZExt | PPC::MOF_NotAddNorCst | PPC::MOF_WordInt,
1508 PPC::MOF_ZExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_WordInt,
1509 // LBZ, LHZ, STB, STH
1510 PPC::MOF_ZExt | PPC::MOF_RPlusSImm16 | PPC::MOF_SubWordInt,
1511 PPC::MOF_ZExt | PPC::MOF_RPlusLo | PPC::MOF_SubWordInt,
1512 PPC::MOF_ZExt | PPC::MOF_NotAddNorCst | PPC::MOF_SubWordInt,
1513 PPC::MOF_ZExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_SubWordInt,
1514 // LHA
1515 PPC::MOF_SExt | PPC::MOF_RPlusSImm16 | PPC::MOF_SubWordInt,
1516 PPC::MOF_SExt | PPC::MOF_RPlusLo | PPC::MOF_SubWordInt,
1517 PPC::MOF_SExt | PPC::MOF_NotAddNorCst | PPC::MOF_SubWordInt,
1518 PPC::MOF_SExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_SubWordInt,
1519 // LFS, LFD, STFS, STFD
1520 PPC::MOF_RPlusSImm16 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1521 PPC::MOF_RPlusLo | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1522 PPC::MOF_NotAddNorCst | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1523 PPC::MOF_AddrIsSImm32 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1524 };
1525 AddrModesMap[PPC::AM_DSForm] = {
1526 // LWA
1527 PPC::MOF_SExt | PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_WordInt,
1528 PPC::MOF_SExt | PPC::MOF_NotAddNorCst | PPC::MOF_WordInt,
1529 PPC::MOF_SExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_WordInt,
1530 // LD, STD
1531 PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_DoubleWordInt,
1532 PPC::MOF_NotAddNorCst | PPC::MOF_DoubleWordInt,
1533 PPC::MOF_AddrIsSImm32 | PPC::MOF_DoubleWordInt,
1534 // DFLOADf32, DFLOADf64, DSTOREf32, DSTOREf64
1535 PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9,
1536 PPC::MOF_NotAddNorCst | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9,
1537 PPC::MOF_AddrIsSImm32 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9,
1538 };
1539 AddrModesMap[PPC::AM_DQForm] = {
1540 // LXV, STXV
1541 PPC::MOF_RPlusSImm16Mult16 | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
1542 PPC::MOF_NotAddNorCst | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
1543 PPC::MOF_AddrIsSImm32 | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
1544 };
1545 AddrModesMap[PPC::AM_PrefixDForm] = {PPC::MOF_RPlusSImm34 |
1546 PPC::MOF_SubtargetP10};
1547 // TODO: Add mapping for quadword load/store.
1548}
1549
1550/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1551/// the desired ByVal argument alignment.
1552static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
1553 if (MaxAlign == MaxMaxAlign)
1554 return;
1555 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1556 if (MaxMaxAlign >= 32 &&
1557 VTy->getPrimitiveSizeInBits().getFixedSize() >= 256)
1558 MaxAlign = Align(32);
1559 else if (VTy->getPrimitiveSizeInBits().getFixedSize() >= 128 &&
1560 MaxAlign < 16)
1561 MaxAlign = Align(16);
1562 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1563 Align EltAlign;
1564 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1565 if (EltAlign > MaxAlign)
1566 MaxAlign = EltAlign;
1567 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1568 for (auto *EltTy : STy->elements()) {
1569 Align EltAlign;
1570 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1571 if (EltAlign > MaxAlign)
1572 MaxAlign = EltAlign;
1573 if (MaxAlign == MaxMaxAlign)
1574 break;
1575 }
1576 }
1577}
1578
1579/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1580/// function arguments in the caller parameter area.
1581uint64_t PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1582 const DataLayout &DL) const {
1583 // 16byte and wider vectors are passed on 16byte boundary.
1584 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1585 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1586 if (Subtarget.hasAltivec())
1587 getMaxByValAlign(Ty, Alignment, Align(16));
1588 return Alignment.value();
1589}
1590
1591bool PPCTargetLowering::useSoftFloat() const {
1592 return Subtarget.useSoftFloat();
1593}
1594
1595bool PPCTargetLowering::hasSPE() const {
1596 return Subtarget.hasSPE();
1597}
1598
1599bool PPCTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
1600 return VT.isScalarInteger();
1601}
1602
1603const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1604 switch ((PPCISD::NodeType)Opcode) {
1605 case PPCISD::FIRST_NUMBER: break;
1606 case PPCISD::FSEL: return "PPCISD::FSEL";
1607 case PPCISD::XSMAXC: return "PPCISD::XSMAXC";
1608 case PPCISD::XSMINC: return "PPCISD::XSMINC";
1609 case PPCISD::FCFID: return "PPCISD::FCFID";
1610 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1611 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1612 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1613 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1614 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1615 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1616 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1617 case PPCISD::FP_TO_UINT_IN_VSR:
1618 return "PPCISD::FP_TO_UINT_IN_VSR,";
1619 case PPCISD::FP_TO_SINT_IN_VSR:
1620 return "PPCISD::FP_TO_SINT_IN_VSR";
1621 case PPCISD::FRE: return "PPCISD::FRE";
1622 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1623 case PPCISD::FTSQRT:
1624 return "PPCISD::FTSQRT";
1625 case PPCISD::FSQRT:
1626 return "PPCISD::FSQRT";
1627 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1628 case PPCISD::VPERM: return "PPCISD::VPERM";
1629 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1630 case PPCISD::XXSPLTI_SP_TO_DP:
1631 return "PPCISD::XXSPLTI_SP_TO_DP";
1632 case PPCISD::XXSPLTI32DX:
1633 return "PPCISD::XXSPLTI32DX";
1634 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1635 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1636 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1637 case PPCISD::CMPB: return "PPCISD::CMPB";
1638 case PPCISD::Hi: return "PPCISD::Hi";
1639 case PPCISD::Lo: return "PPCISD::Lo";
1640 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1641 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1642 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1643 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1644 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1645 case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
1646 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1647 case PPCISD::SRL: return "PPCISD::SRL";
1648 case PPCISD::SRA: return "PPCISD::SRA";
1649 case PPCISD::SHL: return "PPCISD::SHL";
1650 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1651 case PPCISD::CALL: return "PPCISD::CALL";
1652 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1653 case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
1654 case PPCISD::CALL_RM:
1655 return "PPCISD::CALL_RM";
1656 case PPCISD::CALL_NOP_RM:
1657 return "PPCISD::CALL_NOP_RM";
1658 case PPCISD::CALL_NOTOC_RM:
1659 return "PPCISD::CALL_NOTOC_RM";
1660 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1661 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1662 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1663 case PPCISD::BCTRL_RM:
1664 return "PPCISD::BCTRL_RM";
1665 case PPCISD::BCTRL_LOAD_TOC_RM:
1666 return "PPCISD::BCTRL_LOAD_TOC_RM";
1667 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1668 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1669 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1670 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1671 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1672 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1673 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1674 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1675 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1676 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1677 case PPCISD::SCALAR_TO_VECTOR_PERMUTED:
1678 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1679 case PPCISD::ANDI_rec_1_EQ_BIT:
1680 return "PPCISD::ANDI_rec_1_EQ_BIT";
1681 case PPCISD::ANDI_rec_1_GT_BIT:
1682 return "PPCISD::ANDI_rec_1_GT_BIT";
1683 case PPCISD::VCMP: return "PPCISD::VCMP";
1684 case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
1685 case PPCISD::LBRX: return "PPCISD::LBRX";
1686 case PPCISD::STBRX: return "PPCISD::STBRX";
1687 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1688 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1689 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1690 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1691 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1692 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1693 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1694 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1695 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1696 case PPCISD::ST_VSR_SCAL_INT:
1697 return "PPCISD::ST_VSR_SCAL_INT";
1698 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1699 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1700 case PPCISD::BDZ: return "PPCISD::BDZ";
1701 case PPCISD::MFFS: return "PPCISD::MFFS";
1702 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1703 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1704 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1705 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1706 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1707 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1708 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1709 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1710 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1711 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1712 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1713 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1714 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1715 case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX";
1716 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1717 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1718 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1719 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1720 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1721 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1722 case PPCISD::PADDI_DTPREL:
1723 return "PPCISD::PADDI_DTPREL";
1724 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1725 case PPCISD::SC: return "PPCISD::SC";
1726 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1727 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1728 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1729 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1730 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1731 case PPCISD::VABSD: return "PPCISD::VABSD";
1732 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1733 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1734 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1735 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1736 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1737 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1738 case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
1739 case PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR:
1740 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1741 case PPCISD::TLS_LOCAL_EXEC_MAT_ADDR:
1742 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1743 case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
1744 case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
1745 case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
1746 case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
1747 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1748 case PPCISD::ZEXT_LD_SPLAT: return "PPCISD::ZEXT_LD_SPLAT";
1749 case PPCISD::SEXT_LD_SPLAT: return "PPCISD::SEXT_LD_SPLAT";
1750 case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1751 case PPCISD::STRICT_FADDRTZ:
1752 return "PPCISD::STRICT_FADDRTZ";
1753 case PPCISD::STRICT_FCTIDZ:
1754 return "PPCISD::STRICT_FCTIDZ";
1755 case PPCISD::STRICT_FCTIWZ:
1756 return "PPCISD::STRICT_FCTIWZ";
1757 case PPCISD::STRICT_FCTIDUZ:
1758 return "PPCISD::STRICT_FCTIDUZ";
1759 case PPCISD::STRICT_FCTIWUZ:
1760 return "PPCISD::STRICT_FCTIWUZ";
1761 case PPCISD::STRICT_FCFID:
1762 return "PPCISD::STRICT_FCFID";
1763 case PPCISD::STRICT_FCFIDU:
1764 return "PPCISD::STRICT_FCFIDU";
1765 case PPCISD::STRICT_FCFIDS:
1766 return "PPCISD::STRICT_FCFIDS";
1767 case PPCISD::STRICT_FCFIDUS:
1768 return "PPCISD::STRICT_FCFIDUS";
1769 case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
1770 }
1771 return nullptr;
1772}
1773
1774EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1775 EVT VT) const {
1776 if (!VT.isVector())
1777 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1778
1779 return VT.changeVectorElementTypeToInteger();
1780}
1781
1782bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1783 assert(VT.isFloatingPoint() && "Non-floating-point FMA?")(static_cast <bool> (VT.isFloatingPoint() && "Non-floating-point FMA?"
) ? void (0) : __assert_fail ("VT.isFloatingPoint() && \"Non-floating-point FMA?\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 1783, __extension__
__PRETTY_FUNCTION__))
;
1784 return true;
1785}
1786
1787//===----------------------------------------------------------------------===//
1788// Node matching predicates, for use by the tblgen matching code.
1789//===----------------------------------------------------------------------===//
1790
1791/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1792static bool isFloatingPointZero(SDValue Op) {
1793 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1794 return CFP->getValueAPF().isZero();
1795 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1796 // Maybe this has already been legalized into the constant pool?
1797 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1798 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1799 return CFP->getValueAPF().isZero();
1800 }
1801 return false;
1802}
1803
1804/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1805/// true if Op is undef or if it matches the specified value.
1806static bool isConstantOrUndef(int Op, int Val) {
1807 return Op < 0 || Op == Val;
1808}
1809
1810/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1811/// VPKUHUM instruction.
1812/// The ShuffleKind distinguishes between big-endian operations with
1813/// two different inputs (0), either-endian operations with two identical
1814/// inputs (1), and little-endian operations with two different inputs (2).
1815/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1816bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1817 SelectionDAG &DAG) {
1818 bool IsLE = DAG.getDataLayout().isLittleEndian();
1819 if (ShuffleKind == 0) {
1820 if (IsLE)
1821 return false;
1822 for (unsigned i = 0; i != 16; ++i)
1823 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1824 return false;
1825 } else if (ShuffleKind == 2) {
1826 if (!IsLE)
1827 return false;
1828 for (unsigned i = 0; i != 16; ++i)
1829 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1830 return false;
1831 } else if (ShuffleKind == 1) {
1832 unsigned j = IsLE ? 0 : 1;
1833 for (unsigned i = 0; i != 8; ++i)
1834 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1835 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1836 return false;
1837 }
1838 return true;
1839}
1840
1841/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1842/// VPKUWUM instruction.
1843/// The ShuffleKind distinguishes between big-endian operations with
1844/// two different inputs (0), either-endian operations with two identical
1845/// inputs (1), and little-endian operations with two different inputs (2).
1846/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1847bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1848 SelectionDAG &DAG) {
1849 bool IsLE = DAG.getDataLayout().isLittleEndian();
1850 if (ShuffleKind == 0) {
1851 if (IsLE)
1852 return false;
1853 for (unsigned i = 0; i != 16; i += 2)
1854 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1855 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1856 return false;
1857 } else if (ShuffleKind == 2) {
1858 if (!IsLE)
1859 return false;
1860 for (unsigned i = 0; i != 16; i += 2)
1861 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1862 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1863 return false;
1864 } else if (ShuffleKind == 1) {
1865 unsigned j = IsLE ? 0 : 2;
1866 for (unsigned i = 0; i != 8; i += 2)
1867 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1868 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1869 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1870 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1871 return false;
1872 }
1873 return true;
1874}
1875
1876/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1877/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1878/// current subtarget.
1879///
1880/// The ShuffleKind distinguishes between big-endian operations with
1881/// two different inputs (0), either-endian operations with two identical
1882/// inputs (1), and little-endian operations with two different inputs (2).
1883/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1884bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1885 SelectionDAG &DAG) {
1886 const PPCSubtarget& Subtarget =
1887 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1888 if (!Subtarget.hasP8Vector())
1889 return false;
1890
1891 bool IsLE = DAG.getDataLayout().isLittleEndian();
1892 if (ShuffleKind == 0) {
1893 if (IsLE)
1894 return false;
1895 for (unsigned i = 0; i != 16; i += 4)
1896 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1897 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1898 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1899 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1900 return false;
1901 } else if (ShuffleKind == 2) {
1902 if (!IsLE)
1903 return false;
1904 for (unsigned i = 0; i != 16; i += 4)
1905 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1906 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1907 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1908 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1909 return false;
1910 } else if (ShuffleKind == 1) {
1911 unsigned j = IsLE ? 0 : 4;
1912 for (unsigned i = 0; i != 8; i += 4)
1913 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1914 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1915 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1916 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1917 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1918 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1919 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1920 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1921 return false;
1922 }
1923 return true;
1924}
1925
1926/// isVMerge - Common function, used to match vmrg* shuffles.
1927///
1928static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1929 unsigned LHSStart, unsigned RHSStart) {
1930 if (N->getValueType(0) != MVT::v16i8)
1931 return false;
1932 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&(static_cast <bool> ((UnitSize == 1 || UnitSize == 2 ||
UnitSize == 4) && "Unsupported merge size!") ? void (
0) : __assert_fail ("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 1933, __extension__
__PRETTY_FUNCTION__))
1933 "Unsupported merge size!")(static_cast <bool> ((UnitSize == 1 || UnitSize == 2 ||
UnitSize == 4) && "Unsupported merge size!") ? void (
0) : __assert_fail ("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 1933, __extension__
__PRETTY_FUNCTION__))
;
1934
1935 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1936 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1937 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1938 LHSStart+j+i*UnitSize) ||
1939 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1940 RHSStart+j+i*UnitSize))
1941 return false;
1942 }
1943 return true;
1944}
1945
1946/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1947/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1948/// The ShuffleKind distinguishes between big-endian merges with two
1949/// different inputs (0), either-endian merges with two identical inputs (1),
1950/// and little-endian merges with two different inputs (2). For the latter,
1951/// the input operands are swapped (see PPCInstrAltivec.td).
1952bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1953 unsigned ShuffleKind, SelectionDAG &DAG) {
1954 if (DAG.getDataLayout().isLittleEndian()) {
1955 if (ShuffleKind == 1) // unary
1956 return isVMerge(N, UnitSize, 0, 0);
1957 else if (ShuffleKind == 2) // swapped
1958 return isVMerge(N, UnitSize, 0, 16);
1959 else
1960 return false;
1961 } else {
1962 if (ShuffleKind == 1) // unary
1963 return isVMerge(N, UnitSize, 8, 8);
1964 else if (ShuffleKind == 0) // normal
1965 return isVMerge(N, UnitSize, 8, 24);
1966 else
1967 return false;
1968 }
1969}
1970
1971/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1972/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1973/// The ShuffleKind distinguishes between big-endian merges with two
1974/// different inputs (0), either-endian merges with two identical inputs (1),
1975/// and little-endian merges with two different inputs (2). For the latter,
1976/// the input operands are swapped (see PPCInstrAltivec.td).
1977bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1978 unsigned ShuffleKind, SelectionDAG &DAG) {
1979 if (DAG.getDataLayout().isLittleEndian()) {
1980 if (ShuffleKind == 1) // unary
1981 return isVMerge(N, UnitSize, 8, 8);
1982 else if (ShuffleKind == 2) // swapped
1983 return isVMerge(N, UnitSize, 8, 24);
1984 else
1985 return false;
1986 } else {
1987 if (ShuffleKind == 1) // unary
1988 return isVMerge(N, UnitSize, 0, 0);
1989 else if (ShuffleKind == 0) // normal
1990 return isVMerge(N, UnitSize, 0, 16);
1991 else
1992 return false;
1993 }
1994}
1995
1996/**
1997 * Common function used to match vmrgew and vmrgow shuffles
1998 *
1999 * The indexOffset determines whether to look for even or odd words in
2000 * the shuffle mask. This is based on the of the endianness of the target
2001 * machine.
2002 * - Little Endian:
2003 * - Use offset of 0 to check for odd elements
2004 * - Use offset of 4 to check for even elements
2005 * - Big Endian:
2006 * - Use offset of 0 to check for even elements
2007 * - Use offset of 4 to check for odd elements
2008 * A detailed description of the vector element ordering for little endian and
2009 * big endian can be found at
2010 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
2011 * Targeting your applications - what little endian and big endian IBM XL C/C++
2012 * compiler differences mean to you
2013 *
2014 * The mask to the shuffle vector instruction specifies the indices of the
2015 * elements from the two input vectors to place in the result. The elements are
2016 * numbered in array-access order, starting with the first vector. These vectors
2017 * are always of type v16i8, thus each vector will contain 16 elements of size
2018 * 8. More info on the shuffle vector can be found in the
2019 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
2020 * Language Reference.
2021 *
2022 * The RHSStartValue indicates whether the same input vectors are used (unary)
2023 * or two different input vectors are used, based on the following:
2024 * - If the instruction uses the same vector for both inputs, the range of the
2025 * indices will be 0 to 15. In this case, the RHSStart value passed should
2026 * be 0.
2027 * - If the instruction has two different vectors then the range of the
2028 * indices will be 0 to 31. In this case, the RHSStart value passed should
2029 * be 16 (indices 0-15 specify elements in the first vector while indices 16
2030 * to 31 specify elements in the second vector).
2031 *
2032 * \param[in] N The shuffle vector SD Node to analyze
2033 * \param[in] IndexOffset Specifies whether to look for even or odd elements
2034 * \param[in] RHSStartValue Specifies the starting index for the righthand input
2035 * vector to the shuffle_vector instruction
2036 * \return true iff this shuffle vector represents an even or odd word merge
2037 */
2038static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
2039 unsigned RHSStartValue) {
2040 if (N->getValueType(0) != MVT::v16i8)
2041 return false;
2042
2043 for (unsigned i = 0; i < 2; ++i)
2044 for (unsigned j = 0; j < 4; ++j)
2045 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
2046 i*RHSStartValue+j+IndexOffset) ||
2047 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
2048 i*RHSStartValue+j+IndexOffset+8))
2049 return false;
2050 return true;
2051}
2052
2053/**
2054 * Determine if the specified shuffle mask is suitable for the vmrgew or
2055 * vmrgow instructions.
2056 *
2057 * \param[in] N The shuffle vector SD Node to analyze
2058 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
2059 * \param[in] ShuffleKind Identify the type of merge:
2060 * - 0 = big-endian merge with two different inputs;
2061 * - 1 = either-endian merge with two identical inputs;
2062 * - 2 = little-endian merge with two different inputs (inputs are swapped for
2063 * little-endian merges).
2064 * \param[in] DAG The current SelectionDAG
2065 * \return true iff this shuffle mask
2066 */
2067bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
2068 unsigned ShuffleKind, SelectionDAG &DAG) {
2069 if (DAG.getDataLayout().isLittleEndian()) {
2070 unsigned indexOffset = CheckEven ? 4 : 0;
2071 if (ShuffleKind == 1) // Unary
2072 return isVMerge(N, indexOffset, 0);
2073 else if (ShuffleKind == 2) // swapped
2074 return isVMerge(N, indexOffset, 16);
2075 else
2076 return false;
2077 }
2078 else {
2079 unsigned indexOffset = CheckEven ? 0 : 4;
2080 if (ShuffleKind == 1) // Unary
2081 return isVMerge(N, indexOffset, 0);
2082 else if (ShuffleKind == 0) // Normal
2083 return isVMerge(N, indexOffset, 16);
2084 else
2085 return false;
2086 }
2087 return false;
2088}
2089
2090/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
2091/// amount, otherwise return -1.
2092/// The ShuffleKind distinguishes between big-endian operations with two
2093/// different inputs (0), either-endian operations with two identical inputs
2094/// (1), and little-endian operations with two different inputs (2). For the
2095/// latter, the input operands are swapped (see PPCInstrAltivec.td).
2096int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
2097 SelectionDAG &DAG) {
2098 if (N->getValueType(0) != MVT::v16i8)
2099 return -1;
2100
2101 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2102
2103 // Find the first non-undef value in the shuffle mask.
2104 unsigned i;
2105 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
2106 /*search*/;
2107
2108 if (i == 16) return -1; // all undef.
2109
2110 // Otherwise, check to see if the rest of the elements are consecutively
2111 // numbered from this value.
2112 unsigned ShiftAmt = SVOp->getMaskElt(i);
2113 if (ShiftAmt < i) return -1;
2114
2115 ShiftAmt -= i;
2116 bool isLE = DAG.getDataLayout().isLittleEndian();
2117
2118 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
2119 // Check the rest of the elements to see if they are consecutive.
2120 for (++i; i != 16; ++i)
2121 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2122 return -1;
2123 } else if (ShuffleKind == 1) {
2124 // Check the rest of the elements to see if they are consecutive.
2125 for (++i; i != 16; ++i)
2126 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
2127 return -1;
2128 } else
2129 return -1;
2130
2131 if (isLE)
2132 ShiftAmt = 16 - ShiftAmt;
2133
2134 return ShiftAmt;
2135}
2136
2137/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
2138/// specifies a splat of a single element that is suitable for input to
2139/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
2140bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
2141 assert(N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) &&(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& isPowerOf2_32(EltSize) && EltSize <= 8
&& "Can only handle 1,2,4,8 byte element sizes") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2142, __extension__
__PRETTY_FUNCTION__))
2142 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& isPowerOf2_32(EltSize) && EltSize <= 8
&& "Can only handle 1,2,4,8 byte element sizes") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2142, __extension__
__PRETTY_FUNCTION__))
;
2143
2144 // The consecutive indices need to specify an element, not part of two
2145 // different elements. So abandon ship early if this isn't the case.
2146 if (N->getMaskElt(0) % EltSize != 0)
2147 return false;
2148
2149 // This is a splat operation if each element of the permute is the same, and
2150 // if the value doesn't reference the second vector.
2151 unsigned ElementBase = N->getMaskElt(0);
2152
2153 // FIXME: Handle UNDEF elements too!
2154 if (ElementBase >= 16)
2155 return false;
2156
2157 // Check that the indices are consecutive, in the case of a multi-byte element
2158 // splatted with a v16i8 mask.
2159 for (unsigned i = 1; i != EltSize; ++i)
2160 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
2161 return false;
2162
2163 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
2164 if (N->getMaskElt(i) < 0) continue;
2165 for (unsigned j = 0; j != EltSize; ++j)
2166 if (N->getMaskElt(i+j) != N->getMaskElt(j))
2167 return false;
2168 }
2169 return true;
2170}
2171
2172/// Check that the mask is shuffling N byte elements. Within each N byte
2173/// element of the mask, the indices could be either in increasing or
2174/// decreasing order as long as they are consecutive.
2175/// \param[in] N the shuffle vector SD Node to analyze
2176/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
2177/// Word/DoubleWord/QuadWord).
2178/// \param[in] StepLen the delta indices number among the N byte element, if
2179/// the mask is in increasing/decreasing order then it is 1/-1.
2180/// \return true iff the mask is shuffling N byte elements.
2181static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
2182 int StepLen) {
2183 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&(static_cast <bool> ((Width == 2 || Width == 4 || Width
== 8 || Width == 16) && "Unexpected element width.")
? void (0) : __assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2184, __extension__
__PRETTY_FUNCTION__))
2184 "Unexpected element width.")(static_cast <bool> ((Width == 2 || Width == 4 || Width
== 8 || Width == 16) && "Unexpected element width.")
? void (0) : __assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2184, __extension__
__PRETTY_FUNCTION__))
;
2185 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.")(static_cast <bool> ((StepLen == 1 || StepLen == -1) &&
"Unexpected element width.") ? void (0) : __assert_fail ("(StepLen == 1 || StepLen == -1) && \"Unexpected element width.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2185, __extension__
__PRETTY_FUNCTION__))
;
2186
2187 unsigned NumOfElem = 16 / Width;
2188 unsigned MaskVal[16]; // Width is never greater than 16
2189 for (unsigned i = 0; i < NumOfElem; ++i) {
2190 MaskVal[0] = N->getMaskElt(i * Width);
2191 if ((StepLen == 1) && (MaskVal[0] % Width)) {
2192 return false;
2193 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
2194 return false;
2195 }
2196
2197 for (unsigned int j = 1; j < Width; ++j) {
2198 MaskVal[j] = N->getMaskElt(i * Width + j);
2199 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
2200 return false;
2201 }
2202 }
2203 }
2204
2205 return true;
2206}
2207
2208bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2209 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
2210 if (!isNByteElemShuffleMask(N, 4, 1))
2211 return false;
2212
2213 // Now we look at mask elements 0,4,8,12
2214 unsigned M0 = N->getMaskElt(0) / 4;
2215 unsigned M1 = N->getMaskElt(4) / 4;
2216 unsigned M2 = N->getMaskElt(8) / 4;
2217 unsigned M3 = N->getMaskElt(12) / 4;
2218 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
2219 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
2220
2221 // Below, let H and L be arbitrary elements of the shuffle mask
2222 // where H is in the range [4,7] and L is in the range [0,3].
2223 // H, 1, 2, 3 or L, 5, 6, 7
2224 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
2225 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
2226 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2227 InsertAtByte = IsLE ? 12 : 0;
2228 Swap = M0 < 4;
2229 return true;
2230 }
2231 // 0, H, 2, 3 or 4, L, 6, 7
2232 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
2233 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
2234 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2235 InsertAtByte = IsLE ? 8 : 4;
2236 Swap = M1 < 4;
2237 return true;
2238 }
2239 // 0, 1, H, 3 or 4, 5, L, 7
2240 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
2241 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
2242 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2243 InsertAtByte = IsLE ? 4 : 8;
2244 Swap = M2 < 4;
2245 return true;
2246 }
2247 // 0, 1, 2, H or 4, 5, 6, L
2248 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
2249 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
2250 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2251 InsertAtByte = IsLE ? 0 : 12;
2252 Swap = M3 < 4;
2253 return true;
2254 }
2255
2256 // If both vector operands for the shuffle are the same vector, the mask will
2257 // contain only elements from the first one and the second one will be undef.
2258 if (N->getOperand(1).isUndef()) {
2259 ShiftElts = 0;
2260 Swap = true;
2261 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2262 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
2263 InsertAtByte = IsLE ? 12 : 0;
2264 return true;
2265 }
2266 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2267 InsertAtByte = IsLE ? 8 : 4;
2268 return true;
2269 }
2270 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2271 InsertAtByte = IsLE ? 4 : 8;
2272 return true;
2273 }
2274 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2275 InsertAtByte = IsLE ? 0 : 12;
2276 return true;
2277 }
2278 }
2279
2280 return false;
2281}
2282
2283bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2284 bool &Swap, bool IsLE) {
2285 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2285, __extension__
__PRETTY_FUNCTION__))
;
18
'?' condition is true
2286 // Ensure each byte index of the word is consecutive.
2287 if (!isNByteElemShuffleMask(N, 4, 1))
19
Assuming the condition is false
20
Taking false branch
2288 return false;
2289
2290 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
2291 unsigned M0 = N->getMaskElt(0) / 4;
2292 unsigned M1 = N->getMaskElt(4) / 4;
2293 unsigned M2 = N->getMaskElt(8) / 4;
2294 unsigned M3 = N->getMaskElt(12) / 4;
2295
2296 // If both vector operands for the shuffle are the same vector, the mask will
2297 // contain only elements from the first one and the second one will be undef.
2298 if (N->getOperand(1).isUndef()) {
2299 assert(M0 < 4 && "Indexing into an undef vector?")(static_cast <bool> (M0 < 4 && "Indexing into an undef vector?"
) ? void (0) : __assert_fail ("M0 < 4 && \"Indexing into an undef vector?\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2299, __extension__
__PRETTY_FUNCTION__))
;
2300 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2301 return false;
2302
2303 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2304 Swap = false;
2305 return true;
2306 }
2307
2308 // Ensure each word index of the ShuffleVector Mask is consecutive.
2309 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
21
Assuming the condition is false
22
Assuming the condition is false
23
Assuming the condition is false
24
Taking false branch
2310 return false;
2311
2312 if (IsLE) {
25
Assuming 'IsLE' is false
2313 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2314 // Input vectors don't need to be swapped if the leading element
2315 // of the result is one of the 3 left elements of the second vector
2316 // (or if there is no shift to be done at all).
2317 Swap = false;
2318 ShiftElts = (8 - M0) % 8;
2319 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2320 // Input vectors need to be swapped if the leading element
2321 // of the result is one of the 3 left elements of the first vector
2322 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2323 Swap = true;
2324 ShiftElts = (4 - M0) % 4;
2325 }
2326
2327 return true;
2328 } else { // BE
2329 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
26
Assuming 'M0' is not equal to 0
27
Assuming 'M0' is not equal to 1
28
Assuming 'M0' is not equal to 2
29
Assuming 'M0' is not equal to 3
2330 // Input vectors don't need to be swapped if the leading element
2331 // of the result is one of the 4 elements of the first vector.
2332 Swap = false;
2333 ShiftElts = M0;
2334 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
30
Assuming 'M0' is not equal to 4
31
Assuming 'M0' is not equal to 5
32
Assuming 'M0' is not equal to 6
33
Assuming 'M0' is not equal to 7
34
Taking false branch
2335 // Input vectors need to be swapped if the leading element
2336 // of the result is one of the 4 elements of the right vector.
2337 Swap = true;
2338 ShiftElts = M0 - 4;
2339 }
2340
2341 return true;
35
Returning without writing to 'ShiftElts'
2342 }
2343}
2344
2345bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
2346 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2346, __extension__
__PRETTY_FUNCTION__))
;
2347
2348 if (!isNByteElemShuffleMask(N, Width, -1))
2349 return false;
2350
2351 for (int i = 0; i < 16; i += Width)
2352 if (N->getMaskElt(i) != i + Width - 1)
2353 return false;
2354
2355 return true;
2356}
2357
2358bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
2359 return isXXBRShuffleMaskHelper(N, 2);
2360}
2361
2362bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
2363 return isXXBRShuffleMaskHelper(N, 4);
2364}
2365
2366bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
2367 return isXXBRShuffleMaskHelper(N, 8);
2368}
2369
2370bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
2371 return isXXBRShuffleMaskHelper(N, 16);
2372}
2373
2374/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2375/// if the inputs to the instruction should be swapped and set \p DM to the
2376/// value for the immediate.
2377/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2378/// AND element 0 of the result comes from the first input (LE) or second input
2379/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2380/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2381/// mask.
2382bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
2383 bool &Swap, bool IsLE) {
2384 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2384, __extension__
__PRETTY_FUNCTION__))
;
2385
2386 // Ensure each byte index of the double word is consecutive.
2387 if (!isNByteElemShuffleMask(N, 8, 1))
2388 return false;
2389
2390 unsigned M0 = N->getMaskElt(0) / 8;
2391 unsigned M1 = N->getMaskElt(8) / 8;
2392 assert(((M0 | M1) < 4) && "A mask element out of bounds?")(static_cast <bool> (((M0 | M1) < 4) && "A mask element out of bounds?"
) ? void (0) : __assert_fail ("((M0 | M1) < 4) && \"A mask element out of bounds?\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2392, __extension__
__PRETTY_FUNCTION__))
;
2393
2394 // If both vector operands for the shuffle are the same vector, the mask will
2395 // contain only elements from the first one and the second one will be undef.
2396 if (N->getOperand(1).isUndef()) {
2397 if ((M0 | M1) < 2) {
2398 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2399 Swap = false;
2400 return true;
2401 } else
2402 return false;
2403 }
2404
2405 if (IsLE) {
2406 if (M0 > 1 && M1 < 2) {
2407 Swap = false;
2408 } else if (M0 < 2 && M1 > 1) {
2409 M0 = (M0 + 2) % 4;
2410 M1 = (M1 + 2) % 4;
2411 Swap = true;
2412 } else
2413 return false;
2414
2415 // Note: if control flow comes here that means Swap is already set above
2416 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2417 return true;
2418 } else { // BE
2419 if (M0 < 2 && M1 > 1) {
2420 Swap = false;
2421 } else if (M0 > 1 && M1 < 2) {
2422 M0 = (M0 + 2) % 4;
2423 M1 = (M1 + 2) % 4;
2424 Swap = true;
2425 } else
2426 return false;
2427
2428 // Note: if control flow comes here that means Swap is already set above
2429 DM = (M0 << 1) + (M1 & 1);
2430 return true;
2431 }
2432}
2433
2434
2435/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2436/// appropriate for PPC mnemonics (which have a big endian bias - namely
2437/// elements are counted from the left of the vector register).
2438unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2439 SelectionDAG &DAG) {
2440 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2441 assert(isSplatShuffleMask(SVOp, EltSize))(static_cast <bool> (isSplatShuffleMask(SVOp, EltSize))
? void (0) : __assert_fail ("isSplatShuffleMask(SVOp, EltSize)"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2441, __extension__
__PRETTY_FUNCTION__))
;
2442 if (DAG.getDataLayout().isLittleEndian())
2443 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2444 else
2445 return SVOp->getMaskElt(0) / EltSize;
2446}
2447
2448/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2449/// by using a vspltis[bhw] instruction of the specified element size, return
2450/// the constant being splatted. The ByteSize field indicates the number of
2451/// bytes of each element [124] -> [bhw].
2452SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2453 SDValue OpVal;
2454
2455 // If ByteSize of the splat is bigger than the element size of the
2456 // build_vector, then we have a case where we are checking for a splat where
2457 // multiple elements of the buildvector are folded together into a single
2458 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2459 unsigned EltSize = 16/N->getNumOperands();
2460 if (EltSize < ByteSize) {
2461 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2462 SDValue UniquedVals[4];
2463 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?")(static_cast <bool> (Multiple > 1 && Multiple
<= 4 && "How can this happen?") ? void (0) : __assert_fail
("Multiple > 1 && Multiple <= 4 && \"How can this happen?\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2463, __extension__
__PRETTY_FUNCTION__))
;
2464
2465 // See if all of the elements in the buildvector agree across.
2466 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2467 if (N->getOperand(i).isUndef()) continue;
2468 // If the element isn't a constant, bail fully out.
2469 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2470
2471 if (!UniquedVals[i&(Multiple-1)].getNode())
2472 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2473 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2474 return SDValue(); // no match.
2475 }
2476
2477 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2478 // either constant or undef values that are identical for each chunk. See
2479 // if these chunks can form into a larger vspltis*.
2480
2481 // Check to see if all of the leading entries are either 0 or -1. If
2482 // neither, then this won't fit into the immediate field.
2483 bool LeadingZero = true;
2484 bool LeadingOnes = true;
2485 for (unsigned i = 0; i != Multiple-1; ++i) {
2486 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2487
2488 LeadingZero &= isNullConstant(UniquedVals[i]);
2489 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2490 }
2491 // Finally, check the least significant entry.
2492 if (LeadingZero) {
2493 if (!UniquedVals[Multiple-1].getNode())
2494 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2495 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2496 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2497 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2498 }
2499 if (LeadingOnes) {
2500 if (!UniquedVals[Multiple-1].getNode())
2501 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2502 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2503 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2504 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2505 }
2506
2507 return SDValue();
2508 }
2509
2510 // Check to see if this buildvec has a single non-undef value in its elements.
2511 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2512 if (N->getOperand(i).isUndef()) continue;
2513 if (!OpVal.getNode())
2514 OpVal = N->getOperand(i);
2515 else if (OpVal != N->getOperand(i))
2516 return SDValue();
2517 }
2518
2519 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2520
2521 unsigned ValSizeInBytes = EltSize;
2522 uint64_t Value = 0;
2523 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2524 Value = CN->getZExtValue();
2525 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2526 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!")(static_cast <bool> (CN->getValueType(0) == MVT::f32
&& "Only one legal FP vector type!") ? void (0) : __assert_fail
("CN->getValueType(0) == MVT::f32 && \"Only one legal FP vector type!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2526, __extension__
__PRETTY_FUNCTION__))
;
2527 Value = FloatToBits(CN->getValueAPF().convertToFloat());
2528 }
2529
2530 // If the splat value is larger than the element value, then we can never do
2531 // this splat. The only case that we could fit the replicated bits into our
2532 // immediate field for would be zero, and we prefer to use vxor for it.
2533 if (ValSizeInBytes < ByteSize) return SDValue();
2534
2535 // If the element value is larger than the splat value, check if it consists
2536 // of a repeated bit pattern of size ByteSize.
2537 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2538 return SDValue();
2539
2540 // Properly sign extend the value.
2541 int MaskVal = SignExtend32(Value, ByteSize * 8);
2542
2543 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2544 if (MaskVal == 0) return SDValue();
2545
2546 // Finally, if this value fits in a 5 bit sext field, return it
2547 if (SignExtend32<5>(MaskVal) == MaskVal)
2548 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2549 return SDValue();
2550}
2551
2552//===----------------------------------------------------------------------===//
2553// Addressing Mode Selection
2554//===----------------------------------------------------------------------===//
2555
2556/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2557/// or 64-bit immediate, and if the value can be accurately represented as a
2558/// sign extension from a 16-bit value. If so, this returns true and the
2559/// immediate.
2560bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2561 if (!isa<ConstantSDNode>(N))
2562 return false;
2563
2564 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2565 if (N->getValueType(0) == MVT::i32)
2566 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2567 else
2568 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2569}
2570bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2571 return isIntS16Immediate(Op.getNode(), Imm);
2572}
2573
2574/// Used when computing address flags for selecting loads and stores.
2575/// If we have an OR, check if the LHS and RHS are provably disjoint.
2576/// An OR of two provably disjoint values is equivalent to an ADD.
2577/// Most PPC load/store instructions compute the effective address as a sum,
2578/// so doing this conversion is useful.
2579static bool provablyDisjointOr(SelectionDAG &DAG, const SDValue &N) {
2580 if (N.getOpcode() != ISD::OR)
2581 return false;
2582 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2583 if (!LHSKnown.Zero.getBoolValue())
2584 return false;
2585 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2586 return (~(LHSKnown.Zero | RHSKnown.Zero) == 0);
2587}
2588
2589/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2590/// be represented as an indexed [r+r] operation.
2591bool PPCTargetLowering::SelectAddressEVXRegReg(SDValue N, SDValue &Base,
2592 SDValue &Index,
2593 SelectionDAG &DAG) const {
2594 for (SDNode *U : N->uses()) {
2595 if (MemSDNode *Memop = dyn_cast<MemSDNode>(U)) {
2596 if (Memop->getMemoryVT() == MVT::f64) {
2597 Base = N.getOperand(0);
2598 Index = N.getOperand(1);
2599 return true;
2600 }
2601 }
2602 }
2603 return false;
2604}
2605
2606/// isIntS34Immediate - This method tests if value of node given can be
2607/// accurately represented as a sign extension from a 34-bit value. If so,
2608/// this returns true and the immediate.
2609bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2610 if (!isa<ConstantSDNode>(N))
2611 return false;
2612
2613 Imm = (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2614 return isInt<34>(Imm);
2615}
2616bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) {
2617 return isIntS34Immediate(Op.getNode(), Imm);
2618}
2619
2620/// SelectAddressRegReg - Given the specified addressed, check to see if it
2621/// can be represented as an indexed [r+r] operation. Returns false if it
2622/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2623/// non-zero and N can be represented by a base register plus a signed 16-bit
2624/// displacement, make a more precise judgement by checking (displacement % \p
2625/// EncodingAlignment).
2626bool PPCTargetLowering::SelectAddressRegReg(
2627 SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG,
2628 MaybeAlign EncodingAlignment) const {
2629 // If we have a PC Relative target flag don't select as [reg+reg]. It will be
2630 // a [pc+imm].
2631 if (SelectAddressPCRel(N, Base))
2632 return false;
2633
2634 int16_t Imm = 0;
2635 if (N.getOpcode() == ISD::ADD) {
2636 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2637 // SPE load/store can only handle 8-bit offsets.
2638 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2639 return true;
2640 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2641 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2642 return false; // r+i
2643 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2644 return false; // r+i
2645
2646 Base = N.getOperand(0);
2647 Index = N.getOperand(1);
2648 return true;
2649 } else if (N.getOpcode() == ISD::OR) {
2650 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2651 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2652 return false; // r+i can fold it if we can.
2653
2654 // If this is an or of disjoint bitfields, we can codegen this as an add
2655 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2656 // disjoint.
2657 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2658
2659 if (LHSKnown.Zero.getBoolValue()) {
2660 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2661 // If all of the bits are known zero on the LHS or RHS, the add won't
2662 // carry.
2663 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2664 Base = N.getOperand(0);
2665 Index = N.getOperand(1);
2666 return true;
2667 }
2668 }
2669 }
2670
2671 return false;
2672}
2673
2674// If we happen to be doing an i64 load or store into a stack slot that has
2675// less than a 4-byte alignment, then the frame-index elimination may need to
2676// use an indexed load or store instruction (because the offset may not be a
2677// multiple of 4). The extra register needed to hold the offset comes from the
2678// register scavenger, and it is possible that the scavenger will need to use
2679// an emergency spill slot. As a result, we need to make sure that a spill slot
2680// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2681// stack slot.
2682static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2683 // FIXME: This does not handle the LWA case.
2684 if (VT != MVT::i64)
2685 return;
2686
2687 // NOTE: We'll exclude negative FIs here, which come from argument
2688 // lowering, because there are no known test cases triggering this problem
2689 // using packed structures (or similar). We can remove this exclusion if
2690 // we find such a test case. The reason why this is so test-case driven is
2691 // because this entire 'fixup' is only to prevent crashes (from the
2692 // register scavenger) on not-really-valid inputs. For example, if we have:
2693 // %a = alloca i1
2694 // %b = bitcast i1* %a to i64*
2695 // store i64* a, i64 b
2696 // then the store should really be marked as 'align 1', but is not. If it
2697 // were marked as 'align 1' then the indexed form would have been
2698 // instruction-selected initially, and the problem this 'fixup' is preventing
2699 // won't happen regardless.
2700 if (FrameIdx < 0)
2701 return;
2702
2703 MachineFunction &MF = DAG.getMachineFunction();
2704 MachineFrameInfo &MFI = MF.getFrameInfo();
2705
2706 if (MFI.getObjectAlign(FrameIdx) >= Align(4))
2707 return;
2708
2709 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2710 FuncInfo->setHasNonRISpills();
2711}
2712
2713/// Returns true if the address N can be represented by a base register plus
2714/// a signed 16-bit displacement [r+imm], and if it is not better
2715/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2716/// displacements that are multiples of that value.
2717bool PPCTargetLowering::SelectAddressRegImm(
2718 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2719 MaybeAlign EncodingAlignment) const {
2720 // FIXME dl should come from parent load or store, not from address
2721 SDLoc dl(N);
2722
2723 // If we have a PC Relative target flag don't select as [reg+imm]. It will be
2724 // a [pc+imm].
2725 if (SelectAddressPCRel(N, Base))
2726 return false;
2727
2728 // If this can be more profitably realized as r+r, fail.
2729 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2730 return false;
2731
2732 if (N.getOpcode() == ISD::ADD) {
2733 int16_t imm = 0;
2734 if (isIntS16Immediate(N.getOperand(1), imm) &&
2735 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2736 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2737 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2738 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2739 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2740 } else {
2741 Base = N.getOperand(0);
2742 }
2743 return true; // [r+i]
2744 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2745 // Match LOAD (ADD (X, Lo(G))).
2746 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()(static_cast <bool> (!cast<ConstantSDNode>(N.getOperand
(1).getOperand(1))->getZExtValue() && "Cannot handle constant offsets yet!"
) ? void (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2747, __extension__
__PRETTY_FUNCTION__))
2747 && "Cannot handle constant offsets yet!")(static_cast <bool> (!cast<ConstantSDNode>(N.getOperand
(1).getOperand(1))->getZExtValue() && "Cannot handle constant offsets yet!"
) ? void (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2747, __extension__
__PRETTY_FUNCTION__))
;
2748 Disp = N.getOperand(1).getOperand(0); // The global address.
2749 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2752, __extension__
__PRETTY_FUNCTION__))
2750 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2752, __extension__
__PRETTY_FUNCTION__))
2751 Disp.getOpcode() == ISD::TargetConstantPool ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2752, __extension__
__PRETTY_FUNCTION__))
2752 Disp.getOpcode() == ISD::TargetJumpTable)(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2752, __extension__
__PRETTY_FUNCTION__))
;
2753 Base = N.getOperand(0);
2754 return true; // [&g+r]
2755 }
2756 } else if (N.getOpcode() == ISD::OR) {
2757 int16_t imm = 0;
2758 if (isIntS16Immediate(N.getOperand(1), imm) &&
2759 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2760 // If this is an or of disjoint bitfields, we can codegen this as an add
2761 // (for better address arithmetic) if the LHS and RHS of the OR are
2762 // provably disjoint.
2763 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2764
2765 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2766 // If all of the bits are known zero on the LHS or RHS, the add won't
2767 // carry.
2768 if (FrameIndexSDNode *FI =
2769 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2770 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2771 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2772 } else {
2773 Base = N.getOperand(0);
2774 }
2775 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2776 return true;
2777 }
2778 }
2779 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2780 // Loading from a constant address.
2781
2782 // If this address fits entirely in a 16-bit sext immediate field, codegen
2783 // this as "d, 0"
2784 int16_t Imm;
2785 if (isIntS16Immediate(CN, Imm) &&
2786 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2787 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2788 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2789 CN->getValueType(0));
2790 return true;
2791 }
2792
2793 // Handle 32-bit sext immediates with LIS + addr mode.
2794 if ((CN->getValueType(0) == MVT::i32 ||
2795 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2796 (!EncodingAlignment ||
2797 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2798 int Addr = (int)CN->getZExtValue();
2799
2800 // Otherwise, break this down into an LIS + disp.
2801 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2802
2803 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2804 MVT::i32);
2805 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2806 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2807 return true;
2808 }
2809 }
2810
2811 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2812 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2813 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2814 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2815 } else
2816 Base = N;
2817 return true; // [r+0]
2818}
2819
2820/// Similar to the 16-bit case but for instructions that take a 34-bit
2821/// displacement field (prefixed loads/stores).
2822bool PPCTargetLowering::SelectAddressRegImm34(SDValue N, SDValue &Disp,
2823 SDValue &Base,
2824 SelectionDAG &DAG) const {
2825 // Only on 64-bit targets.
2826 if (N.getValueType() != MVT::i64)
2827 return false;
2828
2829 SDLoc dl(N);
2830 int64_t Imm = 0;
2831
2832 if (N.getOpcode() == ISD::ADD) {
2833 if (!isIntS34Immediate(N.getOperand(1), Imm))
2834 return false;
2835 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2836 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2837 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2838 else
2839 Base = N.getOperand(0);
2840 return true;
2841 }
2842
2843 if (N.getOpcode() == ISD::OR) {
2844 if (!isIntS34Immediate(N.getOperand(1), Imm))
2845 return false;
2846 // If this is an or of disjoint bitfields, we can codegen this as an add
2847 // (for better address arithmetic) if the LHS and RHS of the OR are
2848 // provably disjoint.
2849 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2850 if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)Imm) != ~0ULL)
2851 return false;
2852 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2853 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2854 else
2855 Base = N.getOperand(0);
2856 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2857 return true;
2858 }
2859
2860 if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2861 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2862 Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2863 return true;
2864 }
2865
2866 return false;
2867}
2868
2869/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2870/// represented as an indexed [r+r] operation.
2871bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2872 SDValue &Index,
2873 SelectionDAG &DAG) const {
2874 // Check to see if we can easily represent this as an [r+r] address. This
2875 // will fail if it thinks that the address is more profitably represented as
2876 // reg+imm, e.g. where imm = 0.
2877 if (SelectAddressRegReg(N, Base, Index, DAG))
2878 return true;
2879
2880 // If the address is the result of an add, we will utilize the fact that the
2881 // address calculation includes an implicit add. However, we can reduce
2882 // register pressure if we do not materialize a constant just for use as the
2883 // index register. We only get rid of the add if it is not an add of a
2884 // value and a 16-bit signed constant and both have a single use.
2885 int16_t imm = 0;
2886 if (N.getOpcode() == ISD::ADD &&
2887 (!isIntS16Immediate(N.getOperand(1), imm) ||
2888 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2889 Base = N.getOperand(0);
2890 Index = N.getOperand(1);
2891 return true;
2892 }
2893
2894 // Otherwise, do it the hard way, using R0 as the base register.
2895 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2896 N.getValueType());
2897 Index = N;
2898 return true;
2899}
2900
2901template <typename Ty> static bool isValidPCRelNode(SDValue N) {
2902 Ty *PCRelCand = dyn_cast<Ty>(N);
2903 return PCRelCand && (PCRelCand->getTargetFlags() & PPCII::MO_PCREL_FLAG);
2904}
2905
2906/// Returns true if this address is a PC Relative address.
2907/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
2908/// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
2909bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
2910 // This is a materialize PC Relative node. Always select this as PC Relative.
2911 Base = N;
2912 if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
2913 return true;
2914 if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
2915 isValidPCRelNode<GlobalAddressSDNode>(N) ||
2916 isValidPCRelNode<JumpTableSDNode>(N) ||
2917 isValidPCRelNode<BlockAddressSDNode>(N))
2918 return true;
2919 return false;
2920}
2921
2922/// Returns true if we should use a direct load into vector instruction
2923/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2924static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
2925
2926 // If there are any other uses other than scalar to vector, then we should
2927 // keep it as a scalar load -> direct move pattern to prevent multiple
2928 // loads.
2929 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
2930 if (!LD)
2931 return false;
2932
2933 EVT MemVT = LD->getMemoryVT();
2934 if (!MemVT.isSimple())
2935 return false;
2936 switch(MemVT.getSimpleVT().SimpleTy) {
2937 case MVT::i64:
2938 break;
2939 case MVT::i32:
2940 if (!ST.hasP8Vector())
2941 return false;
2942 break;
2943 case MVT::i16:
2944 case MVT::i8:
2945 if (!ST.hasP9Vector())
2946 return false;
2947 break;
2948 default:
2949 return false;
2950 }
2951
2952 SDValue LoadedVal(N, 0);
2953 if (!LoadedVal.hasOneUse())
2954 return false;
2955
2956 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
2957 UI != UE; ++UI)
2958 if (UI.getUse().get().getResNo() == 0 &&
2959 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &&
2960 UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED)
2961 return false;
2962
2963 return true;
2964}
2965
2966/// getPreIndexedAddressParts - returns true by value, base pointer and
2967/// offset pointer and addressing mode by reference if the node's address
2968/// can be legally represented as pre-indexed load / store address.
2969bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2970 SDValue &Offset,
2971 ISD::MemIndexedMode &AM,
2972 SelectionDAG &DAG) const {
2973 if (DisablePPCPreinc) return false;
2974
2975 bool isLoad = true;
2976 SDValue Ptr;
2977 EVT VT;
2978 unsigned Alignment;
2979 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2980 Ptr = LD->getBasePtr();
2981 VT = LD->getMemoryVT();
2982 Alignment = LD->getAlignment();
2983 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2984 Ptr = ST->getBasePtr();
2985 VT = ST->getMemoryVT();
2986 Alignment = ST->getAlignment();
2987 isLoad = false;
2988 } else
2989 return false;
2990
2991 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
2992 // instructions because we can fold these into a more efficient instruction
2993 // instead, (such as LXSD).
2994 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
2995 return false;
2996 }
2997
2998 // PowerPC doesn't have preinc load/store instructions for vectors
2999 if (VT.isVector())
3000 return false;
3001
3002 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
3003 // Common code will reject creating a pre-inc form if the base pointer
3004 // is a frame index, or if N is a store and the base pointer is either
3005 // the same as or a predecessor of the value being stored. Check for
3006 // those situations here, and try with swapped Base/Offset instead.
3007 bool Swap = false;
3008
3009 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
3010 Swap = true;
3011 else if (!isLoad) {
3012 SDValue Val = cast<StoreSDNode>(N)->getValue();
3013 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
3014 Swap = true;
3015 }
3016
3017 if (Swap)
3018 std::swap(Base, Offset);
3019
3020 AM = ISD::PRE_INC;
3021 return true;
3022 }
3023
3024 // LDU/STU can only handle immediates that are a multiple of 4.
3025 if (VT != MVT::i64) {
3026 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, None))
3027 return false;
3028 } else {
3029 // LDU/STU need an address with at least 4-byte alignment.
3030 if (Alignment < 4)
3031 return false;
3032
3033 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, Align(4)))
3034 return false;
3035 }
3036
3037 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3038 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
3039 // sext i32 to i64 when addr mode is r+i.
3040 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
3041 LD->getExtensionType() == ISD::SEXTLOAD &&
3042 isa<ConstantSDNode>(Offset))
3043 return false;
3044 }
3045
3046 AM = ISD::PRE_INC;
3047 return true;
3048}
3049
3050//===----------------------------------------------------------------------===//
3051// LowerOperation implementation
3052//===----------------------------------------------------------------------===//
3053
3054/// Return true if we should reference labels using a PICBase, set the HiOpFlags
3055/// and LoOpFlags to the target MO flags.
3056static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
3057 unsigned &HiOpFlags, unsigned &LoOpFlags,
3058 const GlobalValue *GV = nullptr) {
3059 HiOpFlags = PPCII::MO_HA;
3060 LoOpFlags = PPCII::MO_LO;
3061
3062 // Don't use the pic base if not in PIC relocation model.
3063 if (IsPIC) {
3064 HiOpFlags |= PPCII::MO_PIC_FLAG;
3065 LoOpFlags |= PPCII::MO_PIC_FLAG;
3066 }
3067}
3068
3069static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
3070 SelectionDAG &DAG) {
3071 SDLoc DL(HiPart);
3072 EVT PtrVT = HiPart.getValueType();
3073 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
3074
3075 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
3076 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
3077
3078 // With PIC, the first instruction is actually "GR+hi(&G)".
3079 if (isPIC)
3080 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
3081 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
3082
3083 // Generate non-pic code that has direct accesses to the constant pool.
3084 // The address of the global is just (hi(&g)+lo(&g)).
3085 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
3086}
3087
3088static void setUsesTOCBasePtr(MachineFunction &MF) {
3089 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3090 FuncInfo->setUsesTOCBasePtr();
3091}
3092
3093static void setUsesTOCBasePtr(SelectionDAG &DAG) {
3094 setUsesTOCBasePtr(DAG.getMachineFunction());
3095}
3096
3097SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
3098 SDValue GA) const {
3099 const bool Is64Bit = Subtarget.isPPC64();
3100 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
3101 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
3102 : Subtarget.isAIXABI()
3103 ? DAG.getRegister(PPC::R2, VT)
3104 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
3105 SDValue Ops[] = { GA, Reg };
3106 return DAG.getMemIntrinsicNode(
3107 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
3108 MachinePointerInfo::getGOT(DAG.getMachineFunction()), None,
3109 MachineMemOperand::MOLoad);
3110}
3111
3112SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
3113 SelectionDAG &DAG) const {
3114 EVT PtrVT = Op.getValueType();
3115 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3116 const Constant *C = CP->getConstVal();
3117
3118 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3119 // The actual address of the GlobalValue is stored in the TOC.
3120 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3121 if (Subtarget.isUsingPCRelativeCalls()) {
3122 SDLoc DL(CP);
3123 EVT Ty = getPointerTy(DAG.getDataLayout());
3124 SDValue ConstPool = DAG.getTargetConstantPool(
3125 C, Ty, CP->getAlign(), CP->getOffset(), PPCII::MO_PCREL_FLAG);
3126 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
3127 }
3128 setUsesTOCBasePtr(DAG);
3129 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
3130 return getTOCEntry(DAG, SDLoc(CP), GA);
3131 }
3132
3133 unsigned MOHiFlag, MOLoFlag;
3134 bool IsPIC = isPositionIndependent();
3135 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3136
3137 if (IsPIC && Subtarget.isSVR4ABI()) {
3138 SDValue GA =
3139 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), PPCII::MO_PIC_FLAG);
3140 return getTOCEntry(DAG, SDLoc(CP), GA);
3141 }
3142
3143 SDValue CPIHi =
3144 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOHiFlag);
3145 SDValue CPILo =
3146 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOLoFlag);
3147 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
3148}
3149
3150// For 64-bit PowerPC, prefer the more compact relative encodings.
3151// This trades 32 bits per jump table entry for one or two instructions
3152// on the jump site.
3153unsigned PPCTargetLowering::getJumpTableEncoding() const {
3154 if (isJumpTableRelative())
3155 return MachineJumpTableInfo::EK_LabelDifference32;
3156
3157 return TargetLowering::getJumpTableEncoding();
3158}
3159
3160bool PPCTargetLowering::isJumpTableRelative() const {
3161 if (UseAbsoluteJumpTables)
3162 return false;
3163 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
3164 return true;
3165 return TargetLowering::isJumpTableRelative();
3166}
3167
3168SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
3169 SelectionDAG &DAG) const {
3170 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3171 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
3172
3173 switch (getTargetMachine().getCodeModel()) {
3174 case CodeModel::Small:
3175 case CodeModel::Medium:
3176 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
3177 default:
3178 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
3179 getPointerTy(DAG.getDataLayout()));
3180 }
3181}
3182
3183const MCExpr *
3184PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
3185 unsigned JTI,
3186 MCContext &Ctx) const {
3187 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3188 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
3189
3190 switch (getTargetMachine().getCodeModel()) {
3191 case CodeModel::Small:
3192 case CodeModel::Medium:
3193 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
3194 default:
3195 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
3196 }
3197}
3198
3199SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
3200 EVT PtrVT = Op.getValueType();
3201 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3202
3203 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3204 if (Subtarget.isUsingPCRelativeCalls()) {
3205 SDLoc DL(JT);
3206 EVT Ty = getPointerTy(DAG.getDataLayout());
3207 SDValue GA =
3208 DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
3209 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3210 return MatAddr;
3211 }
3212
3213 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3214 // The actual address of the GlobalValue is stored in the TOC.
3215 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3216 setUsesTOCBasePtr(DAG);
3217 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3218 return getTOCEntry(DAG, SDLoc(JT), GA);
3219 }
3220
3221 unsigned MOHiFlag, MOLoFlag;
3222 bool IsPIC = isPositionIndependent();
3223 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3224
3225 if (IsPIC && Subtarget.isSVR4ABI()) {
3226 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3227 PPCII::MO_PIC_FLAG);
3228 return getTOCEntry(DAG, SDLoc(GA), GA);
3229 }
3230
3231 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3232 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3233 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
3234}
3235
3236SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3237 SelectionDAG &DAG) const {
3238 EVT PtrVT = Op.getValueType();
3239 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
3240 const BlockAddress *BA = BASDN->getBlockAddress();
3241
3242 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3243 if (Subtarget.isUsingPCRelativeCalls()) {
3244 SDLoc DL(BASDN);
3245 EVT Ty = getPointerTy(DAG.getDataLayout());
3246 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3247 PPCII::MO_PCREL_FLAG);
3248 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3249 return MatAddr;
3250 }
3251
3252 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3253 // The actual BlockAddress is stored in the TOC.
3254 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3255 setUsesTOCBasePtr(DAG);
3256 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3257 return getTOCEntry(DAG, SDLoc(BASDN), GA);
3258 }
3259
3260 // 32-bit position-independent ELF stores the BlockAddress in the .got.
3261 if (Subtarget.is32BitELFABI() && isPositionIndependent())
3262 return getTOCEntry(
3263 DAG, SDLoc(BASDN),
3264 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
3265
3266 unsigned MOHiFlag, MOLoFlag;
3267 bool IsPIC = isPositionIndependent();
3268 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3269 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3270 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3271 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
3272}
3273
3274SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3275 SelectionDAG &DAG) const {
3276 if (Subtarget.isAIXABI())
3277 return LowerGlobalTLSAddressAIX(Op, DAG);
3278
3279 return LowerGlobalTLSAddressLinux(Op, DAG);
3280}
3281
3282SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
3283 SelectionDAG &DAG) const {
3284 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3285
3286 if (DAG.getTarget().useEmulatedTLS())
3287 report_fatal_error("Emulated TLS is not yet supported on AIX");
3288
3289 SDLoc dl(GA);
3290 const GlobalValue *GV = GA->getGlobal();
3291 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3292
3293 // The general-dynamic model is the only access model supported for now, so
3294 // all the GlobalTLSAddress nodes are lowered with this model.
3295 // We need to generate two TOC entries, one for the variable offset, one for
3296 // the region handle. The global address for the TOC entry of the region
3297 // handle is created with the MO_TLSGDM_FLAG flag and the global address
3298 // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG.
3299 SDValue VariableOffsetTGA =
3300 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
3301 SDValue RegionHandleTGA =
3302 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGDM_FLAG);
3303 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3304 SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
3305 return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,
3306 RegionHandle);
3307}
3308
3309SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
3310 SelectionDAG &DAG) const {
3311 // FIXME: TLS addresses currently use medium model code sequences,
3312 // which is the most useful form. Eventually support for small and
3313 // large models could be added if users need it, at the cost of
3314 // additional complexity.
3315 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3316 if (DAG.getTarget().useEmulatedTLS())
3317 return LowerToTLSEmulatedModel(GA, DAG);
3318
3319 SDLoc dl(GA);
3320 const GlobalValue *GV = GA->getGlobal();
3321 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3322 bool is64bit = Subtarget.isPPC64();
3323 const Module *M = DAG.getMachineFunction().getFunction().getParent();
3324 PICLevel::Level picLevel = M->getPICLevel();
3325
3326 const TargetMachine &TM = getTargetMachine();
3327 TLSModel::Model Model = TM.getTLSModel(GV);
3328
3329 if (Model == TLSModel::LocalExec) {
3330 if (Subtarget.isUsingPCRelativeCalls()) {
3331 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3332 SDValue TGA = DAG.getTargetGlobalAddress(
3333 GV, dl, PtrVT, 0, (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG));
3334 SDValue MatAddr =
3335 DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
3336 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
3337 }
3338
3339 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3340 PPCII::MO_TPREL_HA);
3341 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3342 PPCII::MO_TPREL_LO);
3343 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3344 : DAG.getRegister(PPC::R2, MVT::i32);
3345
3346 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3347 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
3348 }
3349
3350 if (Model == TLSModel::InitialExec) {
3351 bool IsPCRel = Subtarget.isUsingPCRelativeCalls();
3352 SDValue TGA = DAG.getTargetGlobalAddress(
3353 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
3354 SDValue TGATLS = DAG.getTargetGlobalAddress(
3355 GV, dl, PtrVT, 0,
3356 IsPCRel ? (PPCII::MO_TLS | PPCII::MO_PCREL_FLAG) : PPCII::MO_TLS);
3357 SDValue TPOffset;
3358 if (IsPCRel) {
3359 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3360 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
3361 MachinePointerInfo());
3362 } else {
3363 SDValue GOTPtr;
3364 if (is64bit) {
3365 setUsesTOCBasePtr(DAG);
3366 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3367 GOTPtr =
3368 DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
3369 } else {
3370 if (!TM.isPositionIndependent())
3371 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
3372 else if (picLevel == PICLevel::SmallPIC)
3373 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3374 else
3375 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3376 }
3377 TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
3378 }
3379 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
3380 }
3381
3382 if (Model == TLSModel::GeneralDynamic) {
3383 if (Subtarget.isUsingPCRelativeCalls()) {
3384 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3385 PPCII::MO_GOT_TLSGD_PCREL_FLAG);
3386 return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3387 }
3388
3389 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3390 SDValue GOTPtr;
3391 if (is64bit) {
3392 setUsesTOCBasePtr(DAG);
3393 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3394 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
3395 GOTReg, TGA);
3396 } else {
3397 if (picLevel == PICLevel::SmallPIC)
3398 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3399 else
3400 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3401 }
3402 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
3403 GOTPtr, TGA, TGA);
3404 }
3405
3406 if (Model == TLSModel::LocalDynamic) {
3407 if (Subtarget.isUsingPCRelativeCalls()) {
3408 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3409 PPCII::MO_GOT_TLSLD_PCREL_FLAG);
3410 SDValue MatPCRel =
3411 DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3412 return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
3413 }
3414
3415 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3416 SDValue GOTPtr;
3417 if (is64bit) {
3418 setUsesTOCBasePtr(DAG);
3419 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3420 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
3421 GOTReg, TGA);
3422 } else {
3423 if (picLevel == PICLevel::SmallPIC)
3424 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3425 else
3426 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3427 }
3428 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3429 PtrVT, GOTPtr, TGA, TGA);
3430 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3431 PtrVT, TLSAddr, TGA);
3432 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
3433 }
3434
3435 llvm_unreachable("Unknown TLS model!")::llvm::llvm_unreachable_internal("Unknown TLS model!", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3435)
;
3436}
3437
3438SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3439 SelectionDAG &DAG) const {
3440 EVT PtrVT = Op.getValueType();
3441 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
3442 SDLoc DL(GSDN);
3443 const GlobalValue *GV = GSDN->getGlobal();
3444
3445 // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
3446 // The actual address of the GlobalValue is stored in the TOC.
3447 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3448 if (Subtarget.isUsingPCRelativeCalls()) {
3449 EVT Ty = getPointerTy(DAG.getDataLayout());
3450 if (isAccessedAsGotIndirect(Op)) {
3451 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3452 PPCII::MO_PCREL_FLAG |
3453 PPCII::MO_GOT_FLAG);
3454 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3455 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
3456 MachinePointerInfo());
3457 return Load;
3458 } else {
3459 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3460 PPCII::MO_PCREL_FLAG);
3461 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3462 }
3463 }
3464 setUsesTOCBasePtr(DAG);
3465 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
3466 return getTOCEntry(DAG, DL, GA);
3467 }
3468
3469 unsigned MOHiFlag, MOLoFlag;
3470 bool IsPIC = isPositionIndependent();
3471 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
3472
3473 if (IsPIC && Subtarget.isSVR4ABI()) {
3474 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3475 GSDN->getOffset(),
3476 PPCII::MO_PIC_FLAG);
3477 return getTOCEntry(DAG, DL, GA);
3478 }
3479
3480 SDValue GAHi =
3481 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
3482 SDValue GALo =
3483 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
3484
3485 return LowerLabelRef(GAHi, GALo, IsPIC, DAG);
3486}
3487
3488SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3489 bool IsStrict = Op->isStrictFPOpcode();
3490 ISD::CondCode CC =
3491 cast<CondCodeSDNode>(Op.getOperand(IsStrict ? 3 : 2))->get();
3492 SDValue LHS = Op.getOperand(IsStrict ? 1 : 0);
3493 SDValue RHS = Op.getOperand(IsStrict ? 2 : 1);
3494 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
3495 EVT LHSVT = LHS.getValueType();
3496 SDLoc dl(Op);
3497
3498 // Soften the setcc with libcall if it is fp128.
3499 if (LHSVT == MVT::f128) {
3500 assert(!Subtarget.hasP9Vector() &&(static_cast <bool> (!Subtarget.hasP9Vector() &&
"SETCC for f128 is already legal under Power9!") ? void (0) :
__assert_fail ("!Subtarget.hasP9Vector() && \"SETCC for f128 is already legal under Power9!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3501, __extension__
__PRETTY_FUNCTION__))
3501 "SETCC for f128 is already legal under Power9!")(static_cast <bool> (!Subtarget.hasP9Vector() &&
"SETCC for f128 is already legal under Power9!") ? void (0) :
__assert_fail ("!Subtarget.hasP9Vector() && \"SETCC for f128 is already legal under Power9!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3501, __extension__
__PRETTY_FUNCTION__))
;
3502 softenSetCCOperands(DAG, LHSVT, LHS, RHS, CC, dl, LHS, RHS, Chain,
3503 Op->getOpcode() == ISD::STRICT_FSETCCS);
3504 if (RHS.getNode())
3505 LHS = DAG.getNode(ISD::SETCC, dl, Op.getValueType(), LHS, RHS,
3506 DAG.getCondCode(CC));
3507 if (IsStrict)
3508 return DAG.getMergeValues({LHS, Chain}, dl);
3509 return LHS;
3510 }
3511
3512 assert(!IsStrict && "Don't know how to handle STRICT_FSETCC!")(static_cast <bool> (!IsStrict && "Don't know how to handle STRICT_FSETCC!"
) ? void (0) : __assert_fail ("!IsStrict && \"Don't know how to handle STRICT_FSETCC!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3512, __extension__
__PRETTY_FUNCTION__))
;
3513
3514 if (Op.getValueType() == MVT::v2i64) {
3515 // When the operands themselves are v2i64 values, we need to do something
3516 // special because VSX has no underlying comparison operations for these.
3517 if (LHS.getValueType() == MVT::v2i64) {
3518 // Equality can be handled by casting to the legal type for Altivec
3519 // comparisons, everything else needs to be expanded.
3520 if (CC != ISD::SETEQ && CC != ISD::SETNE)
3521 return SDValue();
3522 SDValue SetCC32 = DAG.getSetCC(
3523 dl, MVT::v4i32, DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, LHS),
3524 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, RHS), CC);
3525 int ShuffV[] = {1, 0, 3, 2};
3526 SDValue Shuff =
3527 DAG.getVectorShuffle(MVT::v4i32, dl, SetCC32, SetCC32, ShuffV);
3528 return DAG.getBitcast(MVT::v2i64,
3529 DAG.getNode(CC == ISD::SETEQ ? ISD::AND : ISD::OR,
3530 dl, MVT::v4i32, Shuff, SetCC32));
3531 }
3532
3533 // We handle most of these in the usual way.
3534 return Op;
3535 }
3536
3537 // If we're comparing for equality to zero, expose the fact that this is
3538 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
3539 // fold the new nodes.
3540 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
3541 return V;
3542
3543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
3544 // Leave comparisons against 0 and -1 alone for now, since they're usually
3545 // optimized. FIXME: revisit this when we can custom lower all setcc
3546 // optimizations.
3547 if (C->isAllOnes() || C->isZero())
3548 return SDValue();
3549 }
3550
3551 // If we have an integer seteq/setne, turn it into a compare against zero
3552 // by xor'ing the rhs with the lhs, which is faster than setting a
3553 // condition register, reading it back out, and masking the correct bit. The
3554 // normal approach here uses sub to do this instead of xor. Using xor exposes
3555 // the result to other bit-twiddling opportunities.
3556 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
3557 EVT VT = Op.getValueType();
3558 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, LHS, RHS);
3559 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
3560 }
3561 return SDValue();
3562}
3563
3564SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3565 SDNode *Node = Op.getNode();
3566 EVT VT = Node->getValueType(0);
3567 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3568 SDValue InChain = Node->getOperand(0);
3569 SDValue VAListPtr = Node->getOperand(1);
3570 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3571 SDLoc dl(Node);
3572
3573 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")(static_cast <bool> (!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"
) ? void (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVAARG is PPC32 only\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3573, __extension__
__PRETTY_FUNCTION__))
;
3574
3575 // gpr_index
3576 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3577 VAListPtr, MachinePointerInfo(SV), MVT::i8);
3578 InChain = GprIndex.getValue(1);
3579
3580 if (VT == MVT::i64) {
3581 // Check if GprIndex is even
3582 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
3583 DAG.getConstant(1, dl, MVT::i32));
3584 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
3585 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
3586 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
3587 DAG.getConstant(1, dl, MVT::i32));
3588 // Align GprIndex to be even if it isn't
3589 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
3590 GprIndex);
3591 }
3592
3593 // fpr index is 1 byte after gpr
3594 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3595 DAG.getConstant(1, dl, MVT::i32));
3596
3597 // fpr
3598 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3599 FprPtr, MachinePointerInfo(SV), MVT::i8);
3600 InChain = FprIndex.getValue(1);
3601
3602 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3603 DAG.getConstant(8, dl, MVT::i32));
3604
3605 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3606 DAG.getConstant(4, dl, MVT::i32));
3607
3608 // areas
3609 SDValue OverflowArea =
3610 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
3611 InChain = OverflowArea.getValue(1);
3612
3613 SDValue RegSaveArea =
3614 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
3615 InChain = RegSaveArea.getValue(1);
3616
3617 // select overflow_area if index > 8
3618 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3619 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
3620
3621 // adjustment constant gpr_index * 4/8
3622 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
3623 VT.isInteger() ? GprIndex : FprIndex,
3624 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3625 MVT::i32));
3626
3627 // OurReg = RegSaveArea + RegConstant
3628 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
3629 RegConstant);
3630
3631 // Floating types are 32 bytes into RegSaveArea
3632 if (VT.isFloatingPoint())
3633 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
3634 DAG.getConstant(32, dl, MVT::i32));
3635
3636 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
3637 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3638 VT.isInteger() ? GprIndex : FprIndex,
3639 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
3640 MVT::i32));
3641
3642 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
3643 VT.isInteger() ? VAListPtr : FprPtr,
3644 MachinePointerInfo(SV), MVT::i8);
3645
3646 // determine if we should load from reg_save_area or overflow_area
3647 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3648
3649 // increase overflow_area by 4/8 if gpr/fpr > 8
3650 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
3651 DAG.getConstant(VT.isInteger() ? 4 : 8,
3652 dl, MVT::i32));
3653
3654 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
3655 OverflowAreaPlusN);
3656
3657 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
3658 MachinePointerInfo(), MVT::i32);
3659
3660 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
3661}
3662
3663SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3664 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only")(static_cast <bool> (!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"
) ? void (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVACOPY is PPC32 only\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3664, __extension__
__PRETTY_FUNCTION__))
;
3665
3666 // We have to copy the entire va_list struct:
3667 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3668 return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2),
3669 DAG.getConstant(12, SDLoc(Op), MVT::i32), Align(8),
3670 false, true, false, MachinePointerInfo(),
3671 MachinePointerInfo());
3672}
3673
3674SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3675 SelectionDAG &DAG) const {
3676 if (Subtarget.isAIXABI())
3677 report_fatal_error("ADJUST_TRAMPOLINE operation is not supported on AIX.");
3678
3679 return Op.getOperand(0);
3680}
3681
3682SDValue PPCTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
3683 MachineFunction &MF = DAG.getMachineFunction();
3684 PPCFunctionInfo &MFI = *MF.getInfo<PPCFunctionInfo>();
3685
3686 assert((Op.getOpcode() == ISD::INLINEASM ||(static_cast <bool> ((Op.getOpcode() == ISD::INLINEASM ||
Op.getOpcode() == ISD::INLINEASM_BR) && "Expecting Inline ASM node."
) ? void (0) : __assert_fail ("(Op.getOpcode() == ISD::INLINEASM || Op.getOpcode() == ISD::INLINEASM_BR) && \"Expecting Inline ASM node.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3688, __extension__
__PRETTY_FUNCTION__))
3687 Op.getOpcode() == ISD::INLINEASM_BR) &&(static_cast <bool> ((Op.getOpcode() == ISD::INLINEASM ||
Op.getOpcode() == ISD::INLINEASM_BR) && "Expecting Inline ASM node."
) ? void (0) : __assert_fail ("(Op.getOpcode() == ISD::INLINEASM || Op.getOpcode() == ISD::INLINEASM_BR) && \"Expecting Inline ASM node.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3688, __extension__
__PRETTY_FUNCTION__))
3688 "Expecting Inline ASM node.")(static_cast <bool> ((Op.getOpcode() == ISD::INLINEASM ||
Op.getOpcode() == ISD::INLINEASM_BR) && "Expecting Inline ASM node."
) ? void (0) : __assert_fail ("(Op.getOpcode() == ISD::INLINEASM || Op.getOpcode() == ISD::INLINEASM_BR) && \"Expecting Inline ASM node.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3688, __extension__
__PRETTY_FUNCTION__))
;
3689
3690 // If an LR store is already known to be required then there is not point in
3691 // checking this ASM as well.
3692 if (MFI.isLRStoreRequired())
3693 return Op;
3694
3695 // Inline ASM nodes have an optional last operand that is an incoming Flag of
3696 // type MVT::Glue. We want to ignore this last operand if that is the case.
3697 unsigned NumOps = Op.getNumOperands();
3698 if (Op.getOperand(NumOps - 1).getValueType() == MVT::Glue)
3699 --NumOps;
3700
3701 // Check all operands that may contain the LR.
3702 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
3703 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
3704 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
3705 ++i; // Skip the ID value.
3706
3707 switch (InlineAsm::getKind(Flags)) {
3708 default:
3709 llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3709)
;
3710 case InlineAsm::Kind_RegUse:
3711 case InlineAsm::Kind_Imm:
3712 case InlineAsm::Kind_Mem:
3713 i += NumVals;
3714 break;
3715 case InlineAsm::Kind_Clobber:
3716 case InlineAsm::Kind_RegDef:
3717 case InlineAsm::Kind_RegDefEarlyClobber: {
3718 for (; NumVals; --NumVals, ++i) {
3719 Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
3720 if (Reg != PPC::LR && Reg != PPC::LR8)
3721 continue;
3722 MFI.setLRStoreRequired();
3723 return Op;
3724 }
3725 break;
3726 }
3727 }
3728 }
3729
3730 return Op;
3731}
3732
3733SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3734 SelectionDAG &DAG) const {
3735 if (Subtarget.isAIXABI())
3736 report_fatal_error("INIT_TRAMPOLINE operation is not supported on AIX.");
3737
3738 SDValue Chain = Op.getOperand(0);
3739 SDValue Trmp = Op.getOperand(1); // trampoline
3740 SDValue FPtr = Op.getOperand(2); // nested function
3741 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3742 SDLoc dl(Op);
3743
3744 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3745 bool isPPC64 = (PtrVT == MVT::i64);
3746 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3747
3748 TargetLowering::ArgListTy Args;
3749 TargetLowering::ArgListEntry Entry;
3750
3751 Entry.Ty = IntPtrTy;
3752 Entry.Node = Trmp; Args.push_back(Entry);
3753
3754 // TrampSize == (isPPC64 ? 48 : 40);
3755 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3756 isPPC64 ? MVT::i64 : MVT::i32);
3757 Args.push_back(Entry);
3758
3759 Entry.Node = FPtr; Args.push_back(Entry);
3760 Entry.Node = Nest; Args.push_back(Entry);
3761
3762 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3763 TargetLowering::CallLoweringInfo CLI(DAG);
3764 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3765 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3766 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3767
3768 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3769 return CallResult.second;
3770}
3771
3772SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3773 MachineFunction &MF = DAG.getMachineFunction();
3774 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3775 EVT PtrVT = getPointerTy(MF.getDataLayout());
3776
3777 SDLoc dl(Op);
3778
3779 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) {
3780 // vastart just stores the address of the VarArgsFrameIndex slot into the
3781 // memory location argument.
3782 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3783 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3784 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3785 MachinePointerInfo(SV));
3786 }
3787
3788 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3789 // We suppose the given va_list is already allocated.
3790 //
3791 // typedef struct {
3792 // char gpr; /* index into the array of 8 GPRs
3793 // * stored in the register save area
3794 // * gpr=0 corresponds to r3,
3795 // * gpr=1 to r4, etc.
3796 // */
3797 // char fpr; /* index into the array of 8 FPRs
3798 // * stored in the register save area
3799 // * fpr=0 corresponds to f1,
3800 // * fpr=1 to f2, etc.
3801 // */
3802 // char *overflow_arg_area;
3803 // /* location on stack that holds
3804 // * the next overflow argument
3805 // */
3806 // char *reg_save_area;
3807 // /* where r3:r10 and f1:f8 (if saved)
3808 // * are stored
3809 // */
3810 // } va_list[1];
3811
3812 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3813 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3814 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3815 PtrVT);
3816 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3817 PtrVT);
3818
3819 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3820 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3821
3822 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3823 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3824
3825 uint64_t FPROffset = 1;
3826 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3827
3828 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3829
3830 // Store first byte : number of int regs
3831 SDValue firstStore =
3832 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3833 MachinePointerInfo(SV), MVT::i8);
3834 uint64_t nextOffset = FPROffset;
3835 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3836 ConstFPROffset);
3837
3838 // Store second byte : number of float regs
3839 SDValue secondStore =
3840 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3841 MachinePointerInfo(SV, nextOffset), MVT::i8);
3842 nextOffset += StackOffset;
3843 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3844
3845 // Store second word : arguments given on stack
3846 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3847 MachinePointerInfo(SV, nextOffset));
3848 nextOffset += FrameOffset;
3849 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3850
3851 // Store third word : arguments given in registers
3852 return DAG.getStore(thirdStore, dl, FR, nextPtr,
3853 MachinePointerInfo(SV, nextOffset));
3854}
3855
3856/// FPR - The set of FP registers that should be allocated for arguments
3857/// on Darwin and AIX.
3858static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3859 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3860 PPC::F11, PPC::F12, PPC::F13};
3861
3862/// CalculateStackSlotSize - Calculates the size reserved for this argument on
3863/// the stack.
3864static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3865 unsigned PtrByteSize) {
3866 unsigned ArgSize = ArgVT.getStoreSize();
3867 if (Flags.isByVal())
3868 ArgSize = Flags.getByValSize();
3869
3870 // Round up to multiples of the pointer size, except for array members,
3871 // which are always packed.
3872 if (!Flags.isInConsecutiveRegs())
3873 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3874
3875 return ArgSize;
3876}
3877
3878/// CalculateStackSlotAlignment - Calculates the alignment of this argument
3879/// on the stack.
3880static Align CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3881 ISD::ArgFlagsTy Flags,
3882 unsigned PtrByteSize) {
3883 Align Alignment(PtrByteSize);
3884
3885 // Altivec parameters are padded to a 16 byte boundary.
3886 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3887 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3888 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3889 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3890 Alignment = Align(16);
3891
3892 // ByVal parameters are aligned as requested.
3893 if (Flags.isByVal()) {
3894 auto BVAlign = Flags.getNonZeroByValAlign();
3895 if (BVAlign > PtrByteSize) {
3896 if (BVAlign.value() % PtrByteSize != 0)
3897 llvm_unreachable(::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3898)
3898 "ByVal alignment is not a multiple of the pointer size")::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3898)
;
3899
3900 Alignment = BVAlign;
3901 }
3902 }
3903
3904 // Array members are always packed to their original alignment.
3905 if (Flags.isInConsecutiveRegs()) {
3906 // If the array member was split into multiple registers, the first
3907 // needs to be aligned to the size of the full type. (Except for
3908 // ppcf128, which is only aligned as its f64 components.)
3909 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3910 Alignment = Align(OrigVT.getStoreSize());
3911 else
3912 Alignment = Align(ArgVT.getStoreSize());
3913 }
3914
3915 return Alignment;
3916}
3917
3918/// CalculateStackSlotUsed - Return whether this argument will use its
3919/// stack slot (instead of being passed in registers). ArgOffset,
3920/// AvailableFPRs, and AvailableVRs must hold the current argument
3921/// position, and will be updated to account for this argument.
3922static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags,
3923 unsigned PtrByteSize, unsigned LinkageSize,
3924 unsigned ParamAreaSize, unsigned &ArgOffset,
3925 unsigned &AvailableFPRs,
3926 unsigned &AvailableVRs) {
3927 bool UseMemory = false;
3928
3929 // Respect alignment of argument on the stack.
3930 Align Alignment =
3931 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3932 ArgOffset = alignTo(ArgOffset, Alignment);
3933 // If there's no space left in the argument save area, we must
3934 // use memory (this check also catches zero-sized arguments).
3935 if (ArgOffset >= LinkageSize + ParamAreaSize)
3936 UseMemory = true;
3937
3938 // Allocate argument on the stack.
3939 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3940 if (Flags.isInConsecutiveRegsLast())
3941 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3942 // If we overran the argument save area, we must use memory
3943 // (this check catches arguments passed partially in memory)
3944 if (ArgOffset > LinkageSize + ParamAreaSize)
3945 UseMemory = true;
3946
3947 // However, if the argument is actually passed in an FPR or a VR,
3948 // we don't use memory after all.
3949 if (!Flags.isByVal()) {
3950 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
3951 if (AvailableFPRs > 0) {
3952 --AvailableFPRs;
3953 return false;
3954 }
3955 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3956 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3957 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3958 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3959 if (AvailableVRs > 0) {
3960 --AvailableVRs;
3961 return false;
3962 }
3963 }
3964
3965 return UseMemory;
3966}
3967
3968/// EnsureStackAlignment - Round stack frame size up from NumBytes to
3969/// ensure minimum alignment required for target.
3970static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3971 unsigned NumBytes) {
3972 return alignTo(NumBytes, Lowering->getStackAlign());
3973}
3974
3975SDValue PPCTargetLowering::LowerFormalArguments(
3976 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3977 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3978 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3979 if (Subtarget.isAIXABI())
3980 return LowerFormalArguments_AIX(Chain, CallConv, isVarArg, Ins, dl, DAG,
3981 InVals);
3982 if (Subtarget.is64BitELFABI())
3983 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3984 InVals);
3985 assert(Subtarget.is32BitELFABI())(static_cast <bool> (Subtarget.is32BitELFABI()) ? void (
0) : __assert_fail ("Subtarget.is32BitELFABI()", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3985, __extension__ __PRETTY_FUNCTION__))
;
3986 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3987 InVals);
3988}
3989
3990SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3991 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3992 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3993 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3994
3995 // 32-bit SVR4 ABI Stack Frame Layout:
3996 // +-----------------------------------+
3997 // +--> | Back chain |
3998 // | +-----------------------------------+
3999 // | | Floating-point register save area |
4000 // | +-----------------------------------+
4001 // | | General register save area |
4002 // | +-----------------------------------+
4003 // | | CR save word |
4004 // | +-----------------------------------+
4005 // | | VRSAVE save word |
4006 // | +-----------------------------------+
4007 // | | Alignment padding |
4008 // | +-----------------------------------+
4009 // | | Vector register save area |
4010 // | +-----------------------------------+
4011 // | | Local variable space |
4012 // | +-----------------------------------+
4013 // | | Parameter list area |
4014 // | +-----------------------------------+
4015 // | | LR save word |
4016 // | +-----------------------------------+
4017 // SP--> +--- | Back chain |
4018 // +-----------------------------------+
4019 //
4020 // Specifications:
4021 // System V Application Binary Interface PowerPC Processor Supplement
4022 // AltiVec Technology Programming Interface Manual
4023
4024 MachineFunction &MF = DAG.getMachineFunction();
4025 MachineFrameInfo &MFI = MF.getFrameInfo();
4026 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4027
4028 EVT PtrVT = getPointerTy(MF.getDataLayout());
4029 // Potential tail calls could cause overwriting of argument stack slots.
4030 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4031 (CallConv == CallingConv::Fast));
4032 const Align PtrAlign(4);
4033
4034 // Assign locations to all of the incoming arguments.
4035 SmallVector<CCValAssign, 16> ArgLocs;
4036 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4037 *DAG.getContext());
4038
4039 // Reserve space for the linkage area on the stack.
4040 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4041 CCInfo.AllocateStack(LinkageSize, PtrAlign);
4042 if (useSoftFloat())
4043 CCInfo.PreAnalyzeFormalArguments(Ins);
4044
4045 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
4046 CCInfo.clearWasPPCF128();
4047
4048 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4049 CCValAssign &VA = ArgLocs[i];
4050
4051 // Arguments stored in registers.
4052 if (VA.isRegLoc()) {
4053 const TargetRegisterClass *RC;
4054 EVT ValVT = VA.getValVT();
4055
4056 switch (ValVT.getSimpleVT().SimpleTy) {
4057 default:
4058 llvm_unreachable("ValVT not supported by formal arguments Lowering")::llvm::llvm_unreachable_internal("ValVT not supported by formal arguments Lowering"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4058)
;
4059 case MVT::i1:
4060 case MVT::i32:
4061 RC = &PPC::GPRCRegClass;
4062 break;
4063 case MVT::f32:
4064 if (Subtarget.hasP8Vector())
4065 RC = &PPC::VSSRCRegClass;
4066 else if (Subtarget.hasSPE())
4067 RC = &PPC::GPRCRegClass;
4068 else
4069 RC = &PPC::F4RCRegClass;
4070 break;
4071 case MVT::f64:
4072 if (Subtarget.hasVSX())
4073 RC = &PPC::VSFRCRegClass;
4074 else if (Subtarget.hasSPE())
4075 // SPE passes doubles in GPR pairs.
4076 RC = &PPC::GPRCRegClass;
4077 else
4078 RC = &PPC::F8RCRegClass;
4079 break;
4080 case MVT::v16i8:
4081 case MVT::v8i16:
4082 case MVT::v4i32:
4083 RC = &PPC::VRRCRegClass;
4084 break;
4085 case MVT::v4f32:
4086 RC = &PPC::VRRCRegClass;
4087 break;
4088 case MVT::v2f64:
4089 case MVT::v2i64:
4090 RC = &PPC::VRRCRegClass;
4091 break;
4092 }
4093
4094 SDValue ArgValue;
4095 // Transform the arguments stored in physical registers into
4096 // virtual ones.
4097 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
4098 assert(i + 1 < e && "No second half of double precision argument")(static_cast <bool> (i + 1 < e && "No second half of double precision argument"
) ? void (0) : __assert_fail ("i + 1 < e && \"No second half of double precision argument\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4098, __extension__
__PRETTY_FUNCTION__))
;
4099 Register RegLo = MF.addLiveIn(VA.getLocReg(), RC);
4100 Register RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC);
4101 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32);
4102 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32);
4103 if (!Subtarget.isLittleEndian())
4104 std::swap (ArgValueLo, ArgValueHi);
4105 ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo,
4106 ArgValueHi);
4107 } else {
4108 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
4109 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
4110 ValVT == MVT::i1 ? MVT::i32 : ValVT);
4111 if (ValVT == MVT::i1)
4112 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
4113 }
4114
4115 InVals.push_back(ArgValue);
4116 } else {
4117 // Argument stored in memory.
4118 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4118, __extension__ __PRETTY_FUNCTION__))
;
4119
4120 // Get the extended size of the argument type in stack
4121 unsigned ArgSize = VA.getLocVT().getStoreSize();
4122 // Get the actual size of the argument type
4123 unsigned ObjSize = VA.getValVT().getStoreSize();
4124 unsigned ArgOffset = VA.getLocMemOffset();
4125 // Stack objects in PPC32 are right justified.
4126 ArgOffset += ArgSize - ObjSize;
4127 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
4128
4129 // Create load nodes to retrieve arguments from the stack.
4130 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4131 InVals.push_back(
4132 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
4133 }
4134 }
4135
4136 // Assign locations to all of the incoming aggregate by value arguments.
4137 // Aggregates passed by value are stored in the local variable space of the
4138 // caller's stack frame, right above the parameter list area.
4139 SmallVector<CCValAssign, 16> ByValArgLocs;
4140 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4141 ByValArgLocs, *DAG.getContext());
4142
4143 // Reserve stack space for the allocations in CCInfo.
4144 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrAlign);
4145
4146 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
4147
4148 // Area that is at least reserved in the caller of this function.
4149 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
4150 MinReservedArea = std::max(MinReservedArea, LinkageSize);
4151
4152 // Set the size that is at least reserved in caller of this function. Tail
4153 // call optimized function's reserved stack space needs to be aligned so that
4154 // taking the difference between two stack areas will result in an aligned
4155 // stack.
4156 MinReservedArea =
4157 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4158 FuncInfo->setMinReservedArea(MinReservedArea);
4159
4160 SmallVector<SDValue, 8> MemOps;
4161
4162 // If the function takes variable number of arguments, make a frame index for
4163 // the start of the first vararg value... for expansion of llvm.va_start.
4164 if (isVarArg) {
4165 static const MCPhysReg GPArgRegs[] = {
4166 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4167 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4168 };
4169 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
4170
4171 static const MCPhysReg FPArgRegs[] = {
4172 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
4173 PPC::F8
4174 };
4175 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
4176
4177 if (useSoftFloat() || hasSPE())
4178 NumFPArgRegs = 0;
4179
4180 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
4181 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
4182
4183 // Make room for NumGPArgRegs and NumFPArgRegs.
4184 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
4185 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
4186
4187 FuncInfo->setVarArgsStackOffset(
4188 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
4189 CCInfo.getNextStackOffset(), true));
4190
4191 FuncInfo->setVarArgsFrameIndex(
4192 MFI.CreateStackObject(Depth, Align(8), false));
4193 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4194
4195 // The fixed integer arguments of a variadic function are stored to the
4196 // VarArgsFrameIndex on the stack so that they may be loaded by
4197 // dereferencing the result of va_next.
4198 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
4199 // Get an existing live-in vreg, or add a new one.
4200 Register VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
4201 if (!VReg)
4202 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
4203
4204 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4205 SDValue Store =
4206 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4207 MemOps.push_back(Store);
4208 // Increment the address by four for the next argument to store
4209 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4210 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4211 }
4212
4213 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
4214 // is set.
4215 // The double arguments are stored to the VarArgsFrameIndex
4216 // on the stack.
4217 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
4218 // Get an existing live-in vreg, or add a new one.
4219 Register VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
4220 if (!VReg)
4221 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
4222
4223 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
4224 SDValue Store =
4225 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4226 MemOps.push_back(Store);
4227 // Increment the address by eight for the next argument to store
4228 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
4229 PtrVT);
4230 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4231 }
4232 }
4233
4234 if (!MemOps.empty())
4235 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4236
4237 return Chain;
4238}
4239
4240// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4241// value to MVT::i64 and then truncate to the correct register size.
4242SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
4243 EVT ObjectVT, SelectionDAG &DAG,
4244 SDValue ArgVal,
4245 const SDLoc &dl) const {
4246 if (Flags.isSExt())
4247 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
4248 DAG.getValueType(ObjectVT));
4249 else if (Flags.isZExt())
4250 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
4251 DAG.getValueType(ObjectVT));
4252
4253 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
4254}
4255
4256SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
4257 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4258 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4259 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4260 // TODO: add description of PPC stack frame format, or at least some docs.
4261 //
4262 bool isELFv2ABI = Subtarget.isELFv2ABI();
4263 bool isLittleEndian = Subtarget.isLittleEndian();
4264 MachineFunction &MF = DAG.getMachineFunction();
4265 MachineFrameInfo &MFI = MF.getFrameInfo();
4266 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4267
4268 assert(!(CallConv == CallingConv::Fast && isVarArg) &&(static_cast <bool> (!(CallConv == CallingConv::Fast &&
isVarArg) && "fastcc not supported on varargs functions"
) ? void (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4269, __extension__
__PRETTY_FUNCTION__))
4269 "fastcc not supported on varargs functions")(static_cast <bool> (!(CallConv == CallingConv::Fast &&
isVarArg) && "fastcc not supported on varargs functions"
) ? void (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4269, __extension__
__PRETTY_FUNCTION__))
;
4270
4271 EVT PtrVT = getPointerTy(MF.getDataLayout());
4272 // Potential tail calls could cause overwriting of argument stack slots.
4273 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4274 (CallConv == CallingConv::Fast));
4275 unsigned PtrByteSize = 8;
4276 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4277
4278 static const MCPhysReg GPR[] = {
4279 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4280 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4281 };
4282 static const MCPhysReg VR[] = {
4283 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4284 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4285 };
4286
4287 const unsigned Num_GPR_Regs = array_lengthof(GPR);
4288 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4289 const unsigned Num_VR_Regs = array_lengthof(VR);
4290
4291 // Do a first pass over the arguments to determine whether the ABI
4292 // guarantees that our caller has allocated the parameter save area
4293 // on its stack frame. In the ELFv1 ABI, this is always the case;
4294 // in the ELFv2 ABI, it is true if this is a vararg function or if
4295 // any parameter is located in a stack slot.
4296
4297 bool HasParameterArea = !isELFv2ABI || isVarArg;
4298 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
4299 unsigned NumBytes = LinkageSize;
4300 unsigned AvailableFPRs = Num_FPR_Regs;
4301 unsigned AvailableVRs = Num_VR_Regs;
4302 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4303 if (Ins[i].Flags.isNest())
4304 continue;
4305
4306 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
4307 PtrByteSize, LinkageSize, ParamAreaSize,
4308 NumBytes, AvailableFPRs, AvailableVRs))
4309 HasParameterArea = true;
4310 }
4311
4312 // Add DAG nodes to load the arguments or copy them out of registers. On
4313 // entry to a function on PPC, the arguments start after the linkage area,
4314 // although the first ones are often in registers.
4315
4316 unsigned ArgOffset = LinkageSize;
4317 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4318 SmallVector<SDValue, 8> MemOps;
4319 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4320 unsigned CurArgIdx = 0;
4321 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4322 SDValue ArgVal;
4323 bool needsLoad = false;
4324 EVT ObjectVT = Ins[ArgNo].VT;
4325 EVT OrigVT = Ins[ArgNo].ArgVT;
4326 unsigned ObjSize = ObjectVT.getStoreSize();
4327 unsigned ArgSize = ObjSize;
4328 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4329 if (Ins[ArgNo].isOrigArg()) {
4330 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4331 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4332 }
4333 // We re-align the argument offset for each argument, except when using the
4334 // fast calling convention, when we need to make sure we do that only when
4335 // we'll actually use a stack slot.
4336 unsigned CurArgOffset;
4337 Align Alignment;
4338 auto ComputeArgOffset = [&]() {
4339 /* Respect alignment of argument on the stack. */
4340 Alignment =
4341 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
4342 ArgOffset = alignTo(ArgOffset, Alignment);
4343 CurArgOffset = ArgOffset;
4344 };
4345
4346 if (CallConv != CallingConv::Fast) {
4347 ComputeArgOffset();
4348
4349 /* Compute GPR index associated with argument offset. */
4350 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4351 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
4352 }
4353
4354 // FIXME the codegen can be much improved in some cases.
4355 // We do not have to keep everything in memory.
4356 if (Flags.isByVal()) {
4357 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")(static_cast <bool> (Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4357, __extension__
__PRETTY_FUNCTION__))
;
4358
4359 if (CallConv == CallingConv::Fast)
4360 ComputeArgOffset();
4361
4362 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4363 ObjSize = Flags.getByValSize();
4364 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4365 // Empty aggregate parameters do not take up registers. Examples:
4366 // struct { } a;
4367 // union { } b;
4368 // int c[0];
4369 // etc. However, we have to provide a place-holder in InVals, so
4370 // pretend we have an 8-byte item at the current address for that
4371 // purpose.
4372 if (!ObjSize) {
4373 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4374 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4375 InVals.push_back(FIN);
4376 continue;
4377 }
4378
4379 // Create a stack object covering all stack doublewords occupied
4380 // by the argument. If the argument is (fully or partially) on
4381 // the stack, or if the argument is fully in registers but the
4382 // caller has allocated the parameter save anyway, we can refer
4383 // directly to the caller's stack frame. Otherwise, create a
4384 // local copy in our own frame.
4385 int FI;
4386 if (HasParameterArea ||
4387 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
4388 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
4389 else
4390 FI = MFI.CreateStackObject(ArgSize, Alignment, false);
4391 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4392
4393 // Handle aggregates smaller than 8 bytes.
4394 if (ObjSize < PtrByteSize) {
4395 // The value of the object is its address, which differs from the
4396 // address of the enclosing doubleword on big-endian systems.
4397 SDValue Arg = FIN;
4398 if (!isLittleEndian) {
4399 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
4400 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
4401 }
4402 InVals.push_back(Arg);
4403
4404 if (GPR_idx != Num_GPR_Regs) {
4405 Register VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4406 FuncInfo->addLiveInAttr(VReg, Flags);
4407 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4408 EVT ObjType = EVT::getIntegerVT(*DAG.getContext(), ObjSize * 8);
4409 SDValue Store =
4410 DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
4411 MachinePointerInfo(&*FuncArg), ObjType);
4412 MemOps.push_back(Store);
4413 }
4414 // Whether we copied from a register or not, advance the offset
4415 // into the parameter save area by a full doubleword.
4416 ArgOffset += PtrByteSize;
4417 continue;
4418 }
4419
4420 // The value of the object is its address, which is the address of
4421 // its first stack doubleword.
4422 InVals.push_back(FIN);
4423
4424 // Store whatever pieces of the object are in registers to memory.
4425 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4426 if (GPR_idx == Num_GPR_Regs)
4427 break;
4428
4429 Register VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4430 FuncInfo->addLiveInAttr(VReg, Flags);
4431 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4432 SDValue Addr = FIN;
4433 if (j) {
4434 SDValue Off = DAG.getConstant(j, dl, PtrVT);
4435 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
4436 }
4437 unsigned StoreSizeInBits = std::min(PtrByteSize, (ObjSize - j)) * 8;
4438 EVT ObjType = EVT::getIntegerVT(*DAG.getContext(), StoreSizeInBits);
4439 SDValue Store =
4440 DAG.getTruncStore(Val.getValue(1), dl, Val, Addr,
4441 MachinePointerInfo(&*FuncArg, j), ObjType);
4442 MemOps.push_back(Store);
4443 ++GPR_idx;
4444 }
4445 ArgOffset += ArgSize;
4446 continue;
4447 }
4448
4449 switch (ObjectVT.getSimpleVT().SimpleTy) {
4450 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4450)
;
4451 case MVT::i1:
4452 case MVT::i32:
4453 case MVT::i64:
4454 if (Flags.isNest()) {
4455 // The 'nest' parameter, if any, is passed in R11.
4456 Register VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
4457 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4458
4459 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4460 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4461
4462 break;
4463 }
4464
4465 // These can be scalar arguments or elements of an integer array type
4466 // passed directly. Clang may use those instead of "byval" aggregate
4467 // types to avoid forcing arguments to memory unnecessarily.
4468 if (GPR_idx != Num_GPR_Regs) {
4469 Register VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4470 FuncInfo->addLiveInAttr(VReg, Flags);
4471 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4472
4473 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4474 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4475 // value to MVT::i64 and then truncate to the correct register size.
4476 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4477 } else {
4478 if (CallConv == CallingConv::Fast)
4479 ComputeArgOffset();
4480
4481 needsLoad = true;
4482 ArgSize = PtrByteSize;
4483 }
4484 if (CallConv != CallingConv::Fast || needsLoad)
4485 ArgOffset += 8;
4486 break;
4487
4488 case MVT::f32:
4489 case MVT::f64:
4490 // These can be scalar arguments or elements of a float array type
4491 // passed directly. The latter are used to implement ELFv2 homogenous
4492 // float aggregates.
4493 if (FPR_idx != Num_FPR_Regs) {
4494 unsigned VReg;
4495
4496 if (ObjectVT == MVT::f32)
4497 VReg = MF.addLiveIn(FPR[FPR_idx],
4498 Subtarget.hasP8Vector()
4499 ? &PPC::VSSRCRegClass
4500 : &PPC::F4RCRegClass);
4501 else
4502 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
4503 ? &PPC::VSFRCRegClass
4504 : &PPC::F8RCRegClass);
4505
4506 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4507 ++FPR_idx;
4508 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
4509 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4510 // once we support fp <-> gpr moves.
4511
4512 // This can only ever happen in the presence of f32 array types,
4513 // since otherwise we never run out of FPRs before running out
4514 // of GPRs.
4515 Register VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4516 FuncInfo->addLiveInAttr(VReg, Flags);
4517 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4518
4519 if (ObjectVT == MVT::f32) {
4520 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
4521 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
4522 DAG.getConstant(32, dl, MVT::i32));
4523 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
4524 }
4525
4526 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
4527 } else {
4528 if (CallConv == CallingConv::Fast)
4529 ComputeArgOffset();
4530
4531 needsLoad = true;
4532 }
4533
4534 // When passing an array of floats, the array occupies consecutive
4535 // space in the argument area; only round up to the next doubleword
4536 // at the end of the array. Otherwise, each float takes 8 bytes.
4537 if (CallConv != CallingConv::Fast || needsLoad) {
4538 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
4539 ArgOffset += ArgSize;
4540 if (Flags.isInConsecutiveRegsLast())
4541 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4542 }
4543 break;
4544 case MVT::v4f32:
4545 case MVT::v4i32:
4546 case MVT::v8i16:
4547 case MVT::v16i8:
4548 case MVT::v2f64:
4549 case MVT::v2i64:
4550 case MVT::v1i128:
4551 case MVT::f128:
4552 // These can be scalar arguments or elements of a vector array type
4553 // passed directly. The latter are used to implement ELFv2 homogenous
4554 // vector aggregates.
4555 if (VR_idx != Num_VR_Regs) {
4556 Register VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4557 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4558 ++VR_idx;
4559 } else {
4560 if (CallConv == CallingConv::Fast)
4561 ComputeArgOffset();
4562 needsLoad = true;
4563 }
4564 if (CallConv != CallingConv::Fast || needsLoad)
4565 ArgOffset += 16;
4566 break;
4567 }
4568
4569 // We need to load the argument to a virtual register if we determined
4570 // above that we ran out of physical registers of the appropriate type.
4571 if (needsLoad) {
4572 if (ObjSize < ArgSize && !isLittleEndian)
4573 CurArgOffset += ArgSize - ObjSize;
4574 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
4575 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4576 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4577 }
4578
4579 InVals.push_back(ArgVal);
4580 }
4581
4582 // Area that is at least reserved in the caller of this function.
4583 unsigned MinReservedArea;
4584 if (HasParameterArea)
4585 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
4586 else
4587 MinReservedArea = LinkageSize;
4588
4589 // Set the size that is at least reserved in caller of this function. Tail
4590 // call optimized functions' reserved stack space needs to be aligned so that
4591 // taking the difference between two stack areas will result in an aligned
4592 // stack.
4593 MinReservedArea =
4594 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4595 FuncInfo->setMinReservedArea(MinReservedArea);
4596
4597 // If the function takes variable number of arguments, make a frame index for
4598 // the start of the first vararg value... for expansion of llvm.va_start.
4599 // On ELFv2ABI spec, it writes:
4600 // C programs that are intended to be *portable* across different compilers
4601 // and architectures must use the header file <stdarg.h> to deal with variable
4602 // argument lists.
4603 if (isVarArg && MFI.hasVAStart()) {
4604 int Depth = ArgOffset;
4605
4606 FuncInfo->setVarArgsFrameIndex(
4607 MFI.CreateFixedObject(PtrByteSize, Depth, true));
4608 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4609
4610 // If this function is vararg, store any remaining integer argument regs
4611 // to their spots on the stack so that they may be loaded by dereferencing
4612 // the result of va_next.
4613 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4614 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4615 Register VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4616 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4617 SDValue Store =
4618 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4619 MemOps.push_back(Store);
4620 // Increment the address by four for the next argument to store
4621 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4622 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4623 }
4624 }
4625
4626 if (!MemOps.empty())
4627 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4628
4629 return Chain;
4630}
4631
4632/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4633/// adjusted to accommodate the arguments for the tailcall.
4634static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4635 unsigned ParamSize) {
4636
4637 if (!isTailCall) return 0;
4638
4639 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4640 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4641 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4642 // Remember only if the new adjustment is bigger.
4643 if (SPDiff < FI->getTailCallSPDelta())
4644 FI->setTailCallSPDelta(SPDiff);
4645
4646 return SPDiff;
4647}
4648
4649static bool isFunctionGlobalAddress(SDValue Callee);
4650
4651static bool callsShareTOCBase(const Function *Caller, SDValue Callee,
4652 const TargetMachine &TM) {
4653 // It does not make sense to call callsShareTOCBase() with a caller that
4654 // is PC Relative since PC Relative callers do not have a TOC.
4655#ifndef NDEBUG
4656 const PPCSubtarget *STICaller = &TM.getSubtarget<PPCSubtarget>(*Caller);
4657 assert(!STICaller->isUsingPCRelativeCalls() &&(static_cast <bool> (!STICaller->isUsingPCRelativeCalls
() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? void (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4658, __extension__
__PRETTY_FUNCTION__))
4658 "PC Relative callers do not have a TOC and cannot share a TOC Base")(static_cast <bool> (!STICaller->isUsingPCRelativeCalls
() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? void (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4658, __extension__
__PRETTY_FUNCTION__))
;
4659#endif
4660
4661 // Callee is either a GlobalAddress or an ExternalSymbol. ExternalSymbols
4662 // don't have enough information to determine if the caller and callee share
4663 // the same TOC base, so we have to pessimistically assume they don't for
4664 // correctness.
4665 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4666 if (!G)
4667 return false;
4668
4669 const GlobalValue *GV = G->getGlobal();
4670
4671 // If the callee is preemptable, then the static linker will use a plt-stub
4672 // which saves the toc to the stack, and needs a nop after the call
4673 // instruction to convert to a toc-restore.
4674 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4675 return false;
4676
4677 // Functions with PC Relative enabled may clobber the TOC in the same DSO.
4678 // We may need a TOC restore in the situation where the caller requires a
4679 // valid TOC but the callee is PC Relative and does not.
4680 const Function *F = dyn_cast<Function>(GV);
4681 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
4682
4683 // If we have an Alias we can try to get the function from there.
4684 if (Alias) {
4685 const GlobalObject *GlobalObj = Alias->getAliaseeObject();
4686 F = dyn_cast<Function>(GlobalObj);
4687 }
4688
4689 // If we still have no valid function pointer we do not have enough
4690 // information to determine if the callee uses PC Relative calls so we must
4691 // assume that it does.
4692 if (!F)
4693 return false;
4694
4695 // If the callee uses PC Relative we cannot guarantee that the callee won't
4696 // clobber the TOC of the caller and so we must assume that the two
4697 // functions do not share a TOC base.
4698 const PPCSubtarget *STICallee = &TM.getSubtarget<PPCSubtarget>(*F);
4699 if (STICallee->isUsingPCRelativeCalls())
4700 return false;
4701
4702 // If the GV is not a strong definition then we need to assume it can be
4703 // replaced by another function at link time. The function that replaces
4704 // it may not share the same TOC as the caller since the callee may be
4705 // replaced by a PC Relative version of the same function.
4706 if (!GV->isStrongDefinitionForLinker())
4707 return false;
4708
4709 // The medium and large code models are expected to provide a sufficiently
4710 // large TOC to provide all data addressing needs of a module with a
4711 // single TOC.
4712 if (CodeModel::Medium == TM.getCodeModel() ||
4713 CodeModel::Large == TM.getCodeModel())
4714 return true;
4715
4716 // Any explicitly-specified sections and section prefixes must also match.
4717 // Also, if we're using -ffunction-sections, then each function is always in
4718 // a different section (the same is true for COMDAT functions).
4719 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4720 GV->getSection() != Caller->getSection())
4721 return false;
4722 if (const auto *F = dyn_cast<Function>(GV)) {
4723 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4724 return false;
4725 }
4726
4727 return true;
4728}
4729
4730static bool
4731needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4732 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4733 assert(Subtarget.is64BitELFABI())(static_cast <bool> (Subtarget.is64BitELFABI()) ? void (
0) : __assert_fail ("Subtarget.is64BitELFABI()", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4733, __extension__ __PRETTY_FUNCTION__))
;
4734
4735 const unsigned PtrByteSize = 8;
4736 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4737
4738 static const MCPhysReg GPR[] = {
4739 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4740 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4741 };
4742 static const MCPhysReg VR[] = {
4743 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4744 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4745 };
4746
4747 const unsigned NumGPRs = array_lengthof(GPR);
4748 const unsigned NumFPRs = 13;
4749 const unsigned NumVRs = array_lengthof(VR);
4750 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4751
4752 unsigned NumBytes = LinkageSize;
4753 unsigned AvailableFPRs = NumFPRs;
4754 unsigned AvailableVRs = NumVRs;
4755
4756 for (const ISD::OutputArg& Param : Outs) {
4757 if (Param.Flags.isNest()) continue;
4758
4759 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags, PtrByteSize,
4760 LinkageSize, ParamAreaSize, NumBytes,
4761 AvailableFPRs, AvailableVRs))
4762 return true;
4763 }
4764 return false;
4765}
4766
4767static bool hasSameArgumentList(const Function *CallerFn, const CallBase &CB) {
4768 if (CB.arg_size() != CallerFn->arg_size())
4769 return false;
4770
4771 auto CalleeArgIter = CB.arg_begin();
4772 auto CalleeArgEnd = CB.arg_end();
4773 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4774
4775 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4776 const Value* CalleeArg = *CalleeArgIter;
4777 const Value* CallerArg = &(*CallerArgIter);
4778 if (CalleeArg == CallerArg)
4779 continue;
4780
4781 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4782 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4783 // }
4784 // 1st argument of callee is undef and has the same type as caller.
4785 if (CalleeArg->getType() == CallerArg->getType() &&
4786 isa<UndefValue>(CalleeArg))
4787 continue;
4788
4789 return false;
4790 }
4791
4792 return true;
4793}
4794
4795// Returns true if TCO is possible between the callers and callees
4796// calling conventions.
4797static bool
4798areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4799 CallingConv::ID CalleeCC) {
4800 // Tail calls are possible with fastcc and ccc.
4801 auto isTailCallableCC = [] (CallingConv::ID CC){
4802 return CC == CallingConv::C || CC == CallingConv::Fast;
4803 };
4804 if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC))
4805 return false;
4806
4807 // We can safely tail call both fastcc and ccc callees from a c calling
4808 // convention caller. If the caller is fastcc, we may have less stack space
4809 // than a non-fastcc caller with the same signature so disable tail-calls in
4810 // that case.
4811 return CallerCC == CallingConv::C || CallerCC == CalleeCC;
4812}
4813
4814bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4815 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, bool isVarArg,
4816 const SmallVectorImpl<ISD::OutputArg> &Outs,
4817 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4818 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4819
4820 if (DisableSCO && !TailCallOpt) return false;
4821
4822 // Variadic argument functions are not supported.
4823 if (isVarArg) return false;
4824
4825 auto &Caller = DAG.getMachineFunction().getFunction();
4826 // Check that the calling conventions are compatible for tco.
4827 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4828 return false;
4829
4830 // Caller contains any byval parameter is not supported.
4831 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4832 return false;
4833
4834 // Callee contains any byval parameter is not supported, too.
4835 // Note: This is a quick work around, because in some cases, e.g.
4836 // caller's stack size > callee's stack size, we are still able to apply
4837 // sibling call optimization. For example, gcc is able to do SCO for caller1
4838 // in the following example, but not for caller2.
4839 // struct test {
4840 // long int a;
4841 // char ary[56];
4842 // } gTest;
4843 // __attribute__((noinline)) int callee(struct test v, struct test *b) {
4844 // b->a = v.a;
4845 // return 0;
4846 // }
4847 // void caller1(struct test a, struct test c, struct test *b) {
4848 // callee(gTest, b); }
4849 // void caller2(struct test *b) { callee(gTest, b); }
4850 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4851 return false;
4852
4853 // If callee and caller use different calling conventions, we cannot pass
4854 // parameters on stack since offsets for the parameter area may be different.
4855 if (Caller.getCallingConv() != CalleeCC &&
4856 needStackSlotPassParameters(Subtarget, Outs))
4857 return false;
4858
4859 // All variants of 64-bit ELF ABIs without PC-Relative addressing require that
4860 // the caller and callee share the same TOC for TCO/SCO. If the caller and
4861 // callee potentially have different TOC bases then we cannot tail call since
4862 // we need to restore the TOC pointer after the call.
4863 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4864 // We cannot guarantee this for indirect calls or calls to external functions.
4865 // When PC-Relative addressing is used, the concept of the TOC is no longer
4866 // applicable so this check is not required.
4867 // Check first for indirect calls.
4868 if (!Subtarget.isUsingPCRelativeCalls() &&
4869 !isFunctionGlobalAddress(Callee) && !isa<ExternalSymbolSDNode>(Callee))
4870 return false;
4871
4872 // Check if we share the TOC base.
4873 if (!Subtarget.isUsingPCRelativeCalls() &&
4874 !callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4875 return false;
4876
4877 // TCO allows altering callee ABI, so we don't have to check further.
4878 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4879 return true;
4880
4881 if (DisableSCO) return false;
4882
4883 // If callee use the same argument list that caller is using, then we can
4884 // apply SCO on this case. If it is not, then we need to check if callee needs
4885 // stack for passing arguments.
4886 // PC Relative tail calls may not have a CallBase.
4887 // If there is no CallBase we cannot verify if we have the same argument
4888 // list so assume that we don't have the same argument list.
4889 if (CB && !hasSameArgumentList(&Caller, *CB) &&
4890 needStackSlotPassParameters(Subtarget, Outs))
4891 return false;
4892 else if (!CB && needStackSlotPassParameters(Subtarget, Outs))
4893 return false;
4894
4895 return true;
4896}
4897
4898/// IsEligibleForTailCallOptimization - Check whether the call is eligible
4899/// for tail call optimization. Targets which want to do tail call
4900/// optimization should implement this function.
4901bool
4902PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4903 CallingConv::ID CalleeCC,
4904 bool isVarArg,
4905 const SmallVectorImpl<ISD::InputArg> &Ins,
4906 SelectionDAG& DAG) const {
4907 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4908 return false;
4909
4910 // Variable argument functions are not supported.
4911 if (isVarArg)
4912 return false;
4913
4914 MachineFunction &MF = DAG.getMachineFunction();
4915 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
4916 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4917 // Functions containing by val parameters are not supported.
4918 for (unsigned i = 0; i != Ins.size(); i++) {
4919 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4920 if (Flags.isByVal()) return false;
4921 }
4922
4923 // Non-PIC/GOT tail calls are supported.
4924 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4925 return true;
4926
4927 // At the moment we can only do local tail calls (in same module, hidden
4928 // or protected) if we are generating PIC.
4929 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4930 return G->getGlobal()->hasHiddenVisibility()
4931 || G->getGlobal()->hasProtectedVisibility();
4932 }
4933
4934 return false;
4935}
4936
4937/// isCallCompatibleAddress - Return the immediate to use if the specified
4938/// 32-bit value is representable in the immediate field of a BxA instruction.
4939static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4940 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4941 if (!C) return nullptr;
4942
4943 int Addr = C->getZExtValue();
4944 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
4945 SignExtend32<26>(Addr) != Addr)
4946 return nullptr; // Top 6 bits have to be sext of immediate.
4947
4948 return DAG
4949 .getConstant(
4950 (int)C->getZExtValue() >> 2, SDLoc(Op),
4951 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
4952 .getNode();
4953}
4954
4955namespace {
4956
4957struct TailCallArgumentInfo {
4958 SDValue Arg;
4959 SDValue FrameIdxOp;
4960 int FrameIdx = 0;
4961
4962 TailCallArgumentInfo() = default;
4963};
4964
4965} // end anonymous namespace
4966
4967/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
4968static void StoreTailCallArgumentsToStackSlot(
4969 SelectionDAG &DAG, SDValue Chain,
4970 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
4971 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
4972 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
4973 SDValue Arg = TailCallArgs[i].Arg;
4974 SDValue FIN = TailCallArgs[i].FrameIdxOp;
4975 int FI = TailCallArgs[i].FrameIdx;
4976 // Store relative to framepointer.
4977 MemOpChains.push_back(DAG.getStore(
4978 Chain, dl, Arg, FIN,
4979 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4980 }
4981}
4982
4983/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
4984/// the appropriate stack slot for the tail call optimized function call.
4985static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
4986 SDValue OldRetAddr, SDValue OldFP,
4987 int SPDiff, const SDLoc &dl) {
4988 if (SPDiff) {
4989 // Calculate the new stack slot for the return address.
4990 MachineFunction &MF = DAG.getMachineFunction();
4991 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
4992 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
4993 bool isPPC64 = Subtarget.isPPC64();
4994 int SlotSize = isPPC64 ? 8 : 4;
4995 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
4996 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
4997 NewRetAddrLoc, true);
4998 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4999 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
5000 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
5001 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
5002 }
5003 return Chain;
5004}
5005
5006/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
5007/// the position of the argument.
5008static void
5009CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
5010 SDValue Arg, int SPDiff, unsigned ArgOffset,
5011 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
5012 int Offset = ArgOffset + SPDiff;
5013 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
5014 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
5015 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5016 SDValue FIN = DAG.getFrameIndex(FI, VT);
5017 TailCallArgumentInfo Info;
5018 Info.Arg = Arg;
5019 Info.FrameIdxOp = FIN;
5020 Info.FrameIdx = FI;
5021 TailCallArguments.push_back(Info);
5022}
5023
5024/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
5025/// stack slot. Returns the chain as result and the loaded frame pointers in
5026/// LROpOut/FPOpout. Used when tail calling.
5027SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
5028 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
5029 SDValue &FPOpOut, const SDLoc &dl) const {
5030 if (SPDiff) {
5031 // Load the LR and FP stack slot for later adjusting.
5032 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5033 LROpOut = getReturnAddrFrameIndex(DAG);
5034 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
5035 Chain = SDValue(LROpOut.getNode(), 1);
5036 }
5037 return Chain;
5038}
5039
5040/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
5041/// by "Src" to address "Dst" of size "Size". Alignment information is
5042/// specified by the specific parameter attribute. The copy will be passed as
5043/// a byval function parameter.
5044/// Sometimes what we are copying is the end of a larger object, the part that
5045/// does not fit in registers.
5046static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
5047 SDValue Chain, ISD::ArgFlagsTy Flags,
5048 SelectionDAG &DAG, const SDLoc &dl) {
5049 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
5050 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
5051 Flags.getNonZeroByValAlign(), false, false, false,
5052 MachinePointerInfo(), MachinePointerInfo());
5053}
5054
5055/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
5056/// tail calls.
5057static void LowerMemOpCallTo(
5058 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
5059 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
5060 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
5061 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
5062 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5063 if (!isTailCall) {
5064 if (isVector) {
5065 SDValue StackPtr;
5066 if (isPPC64)
5067 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5068 else
5069 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5070 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5071 DAG.getConstant(ArgOffset, dl, PtrVT));
5072 }
5073 MemOpChains.push_back(
5074 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5075 // Calculate and remember argument location.
5076 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
5077 TailCallArguments);
5078}
5079
5080static void
5081PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
5082 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
5083 SDValue FPOp,
5084 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
5085 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
5086 // might overwrite each other in case of tail call optimization.
5087 SmallVector<SDValue, 8> MemOpChains2;
5088 // Do not flag preceding copytoreg stuff together with the following stuff.
5089 InFlag = SDValue();
5090 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
5091 MemOpChains2, dl);
5092 if (!MemOpChains2.empty())
5093 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
5094
5095 // Store the return address to the appropriate stack slot.
5096 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
5097
5098 // Emit callseq_end just before tailcall node.
5099 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5100 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
5101 InFlag = Chain.getValue(1);
5102}
5103
5104// Is this global address that of a function that can be called by name? (as
5105// opposed to something that must hold a descriptor for an indirect call).
5106static bool isFunctionGlobalAddress(SDValue Callee) {
5107 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
5108 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
5109 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
5110 return false;
5111
5112 return G->getGlobal()->getValueType()->isFunctionTy();
5113 }
5114
5115 return false;
5116}
5117
5118SDValue PPCTargetLowering::LowerCallResult(
5119 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
5120 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5121 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5122 SmallVector<CCValAssign, 16> RVLocs;
5123 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5124 *DAG.getContext());
5125
5126 CCRetInfo.AnalyzeCallResult(
5127 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold)
5128 ? RetCC_PPC_Cold
5129 : RetCC_PPC);
5130
5131 // Copy all of the result registers out of their specified physreg.
5132 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
5133 CCValAssign &VA = RVLocs[i];
5134 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5134, __extension__
__PRETTY_FUNCTION__))
;
5135
5136 SDValue Val;
5137
5138 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
5139 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5140 InFlag);
5141 Chain = Lo.getValue(1);
5142 InFlag = Lo.getValue(2);
5143 VA = RVLocs[++i]; // skip ahead to next loc
5144 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5145 InFlag);
5146 Chain = Hi.getValue(1);
5147 InFlag = Hi.getValue(2);
5148 if (!Subtarget.isLittleEndian())
5149 std::swap (Lo, Hi);
5150 Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi);
5151 } else {
5152 Val = DAG.getCopyFromReg(Chain, dl,
5153 VA.getLocReg(), VA.getLocVT(), InFlag);
5154 Chain = Val.getValue(1);
5155 InFlag = Val.getValue(2);
5156 }
5157
5158 switch (VA.getLocInfo()) {
5159 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5159)
;
5160 case CCValAssign::Full: break;
5161 case CCValAssign::AExt:
5162 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5163 break;
5164 case CCValAssign::ZExt:
5165 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
5166 DAG.getValueType(VA.getValVT()));
5167 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5168 break;
5169 case CCValAssign::SExt:
5170 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
5171 DAG.getValueType(VA.getValVT()));
5172 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5173 break;
5174 }
5175
5176 InVals.push_back(Val);
5177 }
5178
5179 return Chain;
5180}
5181
5182static bool isIndirectCall(const SDValue &Callee, SelectionDAG &DAG,
5183 const PPCSubtarget &Subtarget, bool isPatchPoint) {
5184 // PatchPoint calls are not indirect.
5185 if (isPatchPoint)
5186 return false;
5187
5188 if (isFunctionGlobalAddress(Callee) || isa<ExternalSymbolSDNode>(Callee))
5189 return false;
5190
5191 // Darwin, and 32-bit ELF can use a BLA. The descriptor based ABIs can not
5192 // becuase the immediate function pointer points to a descriptor instead of
5193 // a function entry point. The ELFv2 ABI cannot use a BLA because the function
5194 // pointer immediate points to the global entry point, while the BLA would
5195 // need to jump to the local entry point (see rL211174).
5196 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() &&
5197 isBLACompatibleAddress(Callee, DAG))
5198 return false;
5199
5200 return true;
5201}
5202
5203// AIX and 64-bit ELF ABIs w/o PCRel require a TOC save/restore around calls.
5204static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) {
5205 return Subtarget.isAIXABI() ||
5206 (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls());
5207}
5208
5209static unsigned getCallOpcode(PPCTargetLowering::CallFlags CFlags,
5210 const Function &Caller, const SDValue &Callee,
5211 const PPCSubtarget &Subtarget,
5212 const TargetMachine &TM,
5213 bool IsStrictFPCall = false) {
5214 if (CFlags.IsTailCall)
5215 return PPCISD::TC_RETURN;
5216
5217 unsigned RetOpc = 0;
5218 // This is a call through a function pointer.
5219 if (CFlags.IsIndirect) {
5220 // AIX and the 64-bit ELF ABIs need to maintain the TOC pointer accross
5221 // indirect calls. The save of the caller's TOC pointer to the stack will be
5222 // inserted into the DAG as part of call lowering. The restore of the TOC
5223 // pointer is modeled by using a pseudo instruction for the call opcode that
5224 // represents the 2 instruction sequence of an indirect branch and link,
5225 // immediately followed by a load of the TOC pointer from the the stack save
5226 // slot into gpr2. For 64-bit ELFv2 ABI with PCRel, do not restore the TOC
5227 // as it is not saved or used.
5228 RetOpc = isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC
5229 : PPCISD::BCTRL;
5230 } else if (Subtarget.isUsingPCRelativeCalls()) {
5231 assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI.")(static_cast <bool> (Subtarget.is64BitELFABI() &&
"PC Relative is only on ELF ABI.") ? void (0) : __assert_fail
("Subtarget.is64BitELFABI() && \"PC Relative is only on ELF ABI.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5231, __extension__
__PRETTY_FUNCTION__))
;
5232 RetOpc = PPCISD::CALL_NOTOC;
5233 } else if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
5234 // The ABIs that maintain a TOC pointer accross calls need to have a nop
5235 // immediately following the call instruction if the caller and callee may
5236 // have different TOC bases. At link time if the linker determines the calls
5237 // may not share a TOC base, the call is redirected to a trampoline inserted
5238 // by the linker. The trampoline will (among other things) save the callers
5239 // TOC pointer at an ABI designated offset in the linkage area and the
5240 // linker will rewrite the nop to be a load of the TOC pointer from the
5241 // linkage area into gpr2.
5242 RetOpc = callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL
5243 : PPCISD::CALL_NOP;
5244 else
5245 RetOpc = PPCISD::CALL;
5246 if (IsStrictFPCall) {
5247 switch (RetOpc) {
5248 default:
5249 llvm_unreachable("Unknown call opcode")::llvm::llvm_unreachable_internal("Unknown call opcode", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5249)
;
5250 case PPCISD::BCTRL_LOAD_TOC:
5251 RetOpc = PPCISD::BCTRL_LOAD_TOC_RM;
5252 break;
5253 case PPCISD::BCTRL:
5254 RetOpc = PPCISD::BCTRL_RM;
5255 break;
5256 case PPCISD::CALL_NOTOC:
5257 RetOpc = PPCISD::CALL_NOTOC_RM;
5258 break;
5259 case PPCISD::CALL:
5260 RetOpc = PPCISD::CALL_RM;
5261 break;
5262 case PPCISD::CALL_NOP:
5263 RetOpc = PPCISD::CALL_NOP_RM;
5264 break;
5265 }
5266 }
5267 return RetOpc;
5268}
5269
5270static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
5271 const SDLoc &dl, const PPCSubtarget &Subtarget) {
5272 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI())
5273 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
5274 return SDValue(Dest, 0);
5275
5276 // Returns true if the callee is local, and false otherwise.
5277 auto isLocalCallee = [&]() {
5278 const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
5279 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5280 const GlobalValue *GV = G ? G->getGlobal() : nullptr;
5281
5282 return DAG.getTarget().shouldAssumeDSOLocal(*Mod, GV) &&
5283 !isa_and_nonnull<GlobalIFunc>(GV);
5284 };
5285
5286 // The PLT is only used in 32-bit ELF PIC mode. Attempting to use the PLT in
5287 // a static relocation model causes some versions of GNU LD (2.17.50, at
5288 // least) to force BSS-PLT, instead of secure-PLT, even if all objects are
5289 // built with secure-PLT.
5290 bool UsePlt =
5291 Subtarget.is32BitELFABI() && !isLocalCallee() &&
5292 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_;
5293
5294 const auto getAIXFuncEntryPointSymbolSDNode = [&](const GlobalValue *GV) {
5295 const TargetMachine &TM = Subtarget.getTargetMachine();
5296 const TargetLoweringObjectFile *TLOF = TM.getObjFileLowering();
5297 MCSymbolXCOFF *S =
5298 cast<MCSymbolXCOFF>(TLOF->getFunctionEntryPointSymbol(GV, TM));
5299
5300 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5301 return DAG.getMCSymbol(S, PtrVT);
5302 };
5303
5304 if (isFunctionGlobalAddress(Callee)) {
5305 const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
5306
5307 if (Subtarget.isAIXABI()) {
5308 assert(!isa<GlobalIFunc>(GV) && "IFunc is not supported on AIX.")(static_cast <bool> (!isa<GlobalIFunc>(GV) &&
"IFunc is not supported on AIX.") ? void (0) : __assert_fail
("!isa<GlobalIFunc>(GV) && \"IFunc is not supported on AIX.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5308, __extension__
__PRETTY_FUNCTION__))
;
5309 return getAIXFuncEntryPointSymbolSDNode(GV);
5310 }
5311 return DAG.getTargetGlobalAddress(GV, dl, Callee.getValueType(), 0,
5312 UsePlt ? PPCII::MO_PLT : 0);
5313 }
5314
5315 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
5316 const char *SymName = S->getSymbol();
5317 if (Subtarget.isAIXABI()) {
5318 // If there exists a user-declared function whose name is the same as the
5319 // ExternalSymbol's, then we pick up the user-declared version.
5320 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5321 if (const Function *F =
5322 dyn_cast_or_null<Function>(Mod->getNamedValue(SymName)))
5323 return getAIXFuncEntryPointSymbolSDNode(F);
5324
5325 // On AIX, direct function calls reference the symbol for the function's
5326 // entry point, which is named by prepending a "." before the function's
5327 // C-linkage name. A Qualname is returned here because an external
5328 // function entry point is a csect with XTY_ER property.
5329 const auto getExternalFunctionEntryPointSymbol = [&](StringRef SymName) {
5330 auto &Context = DAG.getMachineFunction().getMMI().getContext();
5331 MCSectionXCOFF *Sec = Context.getXCOFFSection(
5332 (Twine(".") + Twine(SymName)).str(), SectionKind::getMetadata(),
5333 XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER));
5334 return Sec->getQualNameSymbol();
5335 };
5336
5337 SymName = getExternalFunctionEntryPointSymbol(SymName)->getName().data();
5338 }
5339 return DAG.getTargetExternalSymbol(SymName, Callee.getValueType(),
5340 UsePlt ? PPCII::MO_PLT : 0);
5341 }
5342
5343 // No transformation needed.
5344 assert(Callee.getNode() && "What no callee?")(static_cast <bool> (Callee.getNode() && "What no callee?"
) ? void (0) : __assert_fail ("Callee.getNode() && \"What no callee?\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5344, __extension__
__PRETTY_FUNCTION__))
;
5345 return Callee;
5346}
5347
5348static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart) {
5349 assert(CallSeqStart.getOpcode() == ISD::CALLSEQ_START &&(static_cast <bool> (CallSeqStart.getOpcode() == ISD::CALLSEQ_START
&& "Expected a CALLSEQ_STARTSDNode.") ? void (0) : __assert_fail
("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5350, __extension__
__PRETTY_FUNCTION__))
5350 "Expected a CALLSEQ_STARTSDNode.")(static_cast <bool> (CallSeqStart.getOpcode() == ISD::CALLSEQ_START
&& "Expected a CALLSEQ_STARTSDNode.") ? void (0) : __assert_fail
("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5350, __extension__
__PRETTY_FUNCTION__))
;
5351
5352 // The last operand is the chain, except when the node has glue. If the node
5353 // has glue, then the last operand is the glue, and the chain is the second
5354 // last operand.
5355 SDValue LastValue = CallSeqStart.getValue(CallSeqStart->getNumValues() - 1);
5356 if (LastValue.getValueType() != MVT::Glue)
5357 return LastValue;
5358
5359 return CallSeqStart.getValue(CallSeqStart->getNumValues() - 2);
5360}
5361
5362// Creates the node that moves a functions address into the count register
5363// to prepare for an indirect call instruction.
5364static void prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5365 SDValue &Glue, SDValue &Chain,
5366 const SDLoc &dl) {
5367 SDValue MTCTROps[] = {Chain, Callee, Glue};
5368 EVT ReturnTypes[] = {MVT::Other, MVT::Glue};
5369 Chain = DAG.getNode(PPCISD::MTCTR, dl, makeArrayRef(ReturnTypes, 2),
5370 makeArrayRef(MTCTROps, Glue.getNode() ? 3 : 2));
5371 // The glue is the second value produced.
5372 Glue = Chain.getValue(1);
5373}
5374
5375static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5376 SDValue &Glue, SDValue &Chain,
5377 SDValue CallSeqStart,
5378 const CallBase *CB, const SDLoc &dl,
5379 bool hasNest,
5380 const PPCSubtarget &Subtarget) {
5381 // Function pointers in the 64-bit SVR4 ABI do not point to the function
5382 // entry point, but to the function descriptor (the function entry point
5383 // address is part of the function descriptor though).
5384 // The function descriptor is a three doubleword structure with the
5385 // following fields: function entry point, TOC base address and
5386 // environment pointer.
5387 // Thus for a call through a function pointer, the following actions need
5388 // to be performed:
5389 // 1. Save the TOC of the caller in the TOC save area of its stack
5390 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
5391 // 2. Load the address of the function entry point from the function
5392 // descriptor.
5393 // 3. Load the TOC of the callee from the function descriptor into r2.
5394 // 4. Load the environment pointer from the function descriptor into
5395 // r11.
5396 // 5. Branch to the function entry point address.
5397 // 6. On return of the callee, the TOC of the caller needs to be
5398 // restored (this is done in FinishCall()).
5399 //
5400 // The loads are scheduled at the beginning of the call sequence, and the
5401 // register copies are flagged together to ensure that no other
5402 // operations can be scheduled in between. E.g. without flagging the
5403 // copies together, a TOC access in the caller could be scheduled between
5404 // the assignment of the callee TOC and the branch to the callee, which leads
5405 // to incorrect code.
5406
5407 // Start by loading the function address from the descriptor.
5408 SDValue LDChain = getOutputChainFromCallSeq(CallSeqStart);
5409 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
5410 ? (MachineMemOperand::MODereferenceable |
5411 MachineMemOperand::MOInvariant)
5412 : MachineMemOperand::MONone;
5413
5414 MachinePointerInfo MPI(CB ? CB->getCalledOperand() : nullptr);
5415
5416 // Registers used in building the DAG.
5417 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister();
5418 const MCRegister TOCReg = Subtarget.getTOCPointerRegister();
5419
5420 // Offsets of descriptor members.
5421 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset();
5422 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset();
5423
5424 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5425 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4;
5426
5427 // One load for the functions entry point address.
5428 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5429 Alignment, MMOFlags);
5430
5431 // One for loading the TOC anchor for the module that contains the called
5432 // function.
5433 SDValue TOCOff = DAG.getIntPtrConstant(TOCAnchorOffset, dl);
5434 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5435 SDValue TOCPtr =
5436 DAG.getLoad(RegVT, dl, LDChain, AddTOC,
5437 MPI.getWithOffset(TOCAnchorOffset), Alignment, MMOFlags);
5438
5439 // One for loading the environment pointer.
5440 SDValue PtrOff = DAG.getIntPtrConstant(EnvPtrOffset, dl);
5441 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5442 SDValue LoadEnvPtr =
5443 DAG.getLoad(RegVT, dl, LDChain, AddPtr,
5444 MPI.getWithOffset(EnvPtrOffset), Alignment, MMOFlags);
5445
5446
5447 // Then copy the newly loaded TOC anchor to the TOC pointer.
5448 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, TOCReg, TOCPtr, Glue);
5449 Chain = TOCVal.getValue(0);
5450 Glue = TOCVal.getValue(1);
5451
5452 // If the function call has an explicit 'nest' parameter, it takes the
5453 // place of the environment pointer.
5454 assert((!hasNest || !Subtarget.isAIXABI()) &&(static_cast <bool> ((!hasNest || !Subtarget.isAIXABI()
) && "Nest parameter is not supported on AIX.") ? void
(0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5455, __extension__
__PRETTY_FUNCTION__))
5455 "Nest parameter is not supported on AIX.")(static_cast <bool> ((!hasNest || !Subtarget.isAIXABI()
) && "Nest parameter is not supported on AIX.") ? void
(0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5455, __extension__
__PRETTY_FUNCTION__))
;
5456 if (!hasNest) {
5457 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, EnvPtrReg, LoadEnvPtr, Glue);
5458 Chain = EnvVal.getValue(0);
5459 Glue = EnvVal.getValue(1);
5460 }
5461
5462 // The rest of the indirect call sequence is the same as the non-descriptor
5463 // DAG.
5464 prepareIndirectCall(DAG, LoadFuncPtr, Glue, Chain, dl);
5465}
5466
5467static void
5468buildCallOperands(SmallVectorImpl<SDValue> &Ops,
5469 PPCTargetLowering::CallFlags CFlags, const SDLoc &dl,
5470 SelectionDAG &DAG,
5471 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
5472 SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff,
5473 const PPCSubtarget &Subtarget) {
5474 const bool IsPPC64 = Subtarget.isPPC64();
5475 // MVT for a general purpose register.
5476 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5477
5478 // First operand is always the chain.
5479 Ops.push_back(Chain);
5480
5481 // If it's a direct call pass the callee as the second operand.
5482 if (!CFlags.IsIndirect)
5483 Ops.push_back(Callee);
5484 else {
5485 assert(!CFlags.IsPatchPoint && "Patch point calls are not indirect.")(static_cast <bool> (!CFlags.IsPatchPoint && "Patch point calls are not indirect."
) ? void (0) : __assert_fail ("!CFlags.IsPatchPoint && \"Patch point calls are not indirect.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5485, __extension__
__PRETTY_FUNCTION__))
;
5486
5487 // For the TOC based ABIs, we have saved the TOC pointer to the linkage area
5488 // on the stack (this would have been done in `LowerCall_64SVR4` or
5489 // `LowerCall_AIX`). The call instruction is a pseudo instruction that
5490 // represents both the indirect branch and a load that restores the TOC
5491 // pointer from the linkage area. The operand for the TOC restore is an add
5492 // of the TOC save offset to the stack pointer. This must be the second
5493 // operand: after the chain input but before any other variadic arguments.
5494 // For 64-bit ELFv2 ABI with PCRel, do not restore the TOC as it is not
5495 // saved or used.
5496 if (isTOCSaveRestoreRequired(Subtarget)) {
5497 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister();
5498
5499 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5500 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5501 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5502 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5503 Ops.push_back(AddTOC);
5504 }
5505
5506 // Add the register used for the environment pointer.
5507 if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest)
5508 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(),
5509 RegVT));
5510
5511
5512 // Add CTR register as callee so a bctr can be emitted later.
5513 if (CFlags.IsTailCall)
5514 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5515 }
5516
5517 // If this is a tail call add stack pointer delta.
5518 if (CFlags.IsTailCall)
5519 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
5520
5521 // Add argument registers to the end of the list so that they are known live
5522 // into the call.
5523 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
5524 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5525 RegsToPass[i].second.getValueType()));
5526
5527 // We cannot add R2/X2 as an operand here for PATCHPOINT, because there is
5528 // no way to mark dependencies as implicit here.
5529 // We will add the R2/X2 dependency in EmitInstrWithCustomInserter.
5530 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) &&
5531 !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls())
5532 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT));
5533
5534 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
5535 if (CFlags.IsVarArg && Subtarget.is32BitELFABI())
5536 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5537
5538 // Add a register mask operand representing the call-preserved registers.
5539 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
5540 const uint32_t *Mask =
5541 TRI->getCallPreservedMask(DAG.getMachineFunction(), CFlags.CallConv);
5542 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5542, __extension__
__PRETTY_FUNCTION__))
;
5543 Ops.push_back(DAG.getRegisterMask(Mask));
5544
5545 // If the glue is valid, it is the last operand.
5546 if (Glue.getNode())
5547 Ops.push_back(Glue);
5548}
5549
5550SDValue PPCTargetLowering::FinishCall(
5551 CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
5552 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue,
5553 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5554 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
5555 SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const {
5556
5557 if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) ||
5558 Subtarget.isAIXABI())
5559 setUsesTOCBasePtr(DAG);
5560
5561 unsigned CallOpc =
5562 getCallOpcode(CFlags, DAG.getMachineFunction().getFunction(), Callee,
5563 Subtarget, DAG.getTarget(), CB ? CB->isStrictFP() : false);
5564
5565 if (!CFlags.IsIndirect)
5566 Callee = transformCallee(Callee, DAG, dl, Subtarget);
5567 else if (Subtarget.usesFunctionDescriptors())
5568 prepareDescriptorIndirectCall(DAG, Callee, Glue, Chain, CallSeqStart, CB,
5569 dl, CFlags.HasNest, Subtarget);
5570 else
5571 prepareIndirectCall(DAG, Callee, Glue, Chain, dl);
5572
5573 // Build the operand list for the call instruction.
5574 SmallVector<SDValue, 8> Ops;
5575 buildCallOperands(Ops, CFlags, dl, DAG, RegsToPass, Glue, Chain, Callee,
5576 SPDiff, Subtarget);
5577
5578 // Emit tail call.
5579 if (CFlags.IsTailCall) {
5580 // Indirect tail call when using PC Relative calls do not have the same
5581 // constraints.
5582 assert(((Callee.getOpcode() == ISD::Register &&(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5590, __extension__
__PRETTY_FUNCTION__))
5583 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5590, __extension__
__PRETTY_FUNCTION__))
5584 Callee.getOpcode() == ISD::TargetExternalSymbol ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5590, __extension__
__PRETTY_FUNCTION__))
5585 Callee.getOpcode() == ISD::TargetGlobalAddress ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5590, __extension__
__PRETTY_FUNCTION__))
5586 isa<ConstantSDNode>(Callee) ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5590, __extension__
__PRETTY_FUNCTION__))
5587 (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) &&(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5590, __extension__
__PRETTY_FUNCTION__))
5588 "Expecting a global address, external symbol, absolute value, "(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5590, __extension__
__PRETTY_FUNCTION__))
5589 "register or an indirect tail call when PC Relative calls are "(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5590, __extension__
__PRETTY_FUNCTION__))
5590 "used.")(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5590, __extension__
__PRETTY_FUNCTION__))
;
5591 // PC Relative calls also use TC_RETURN as the way to mark tail calls.
5592 assert(CallOpc == PPCISD::TC_RETURN &&(static_cast <bool> (CallOpc == PPCISD::TC_RETURN &&
"Unexpected call opcode for a tail call.") ? void (0) : __assert_fail
("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5593, __extension__
__PRETTY_FUNCTION__))
5593 "Unexpected call opcode for a tail call.")(static_cast <bool> (CallOpc == PPCISD::TC_RETURN &&
"Unexpected call opcode for a tail call.") ? void (0) : __assert_fail
("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5593, __extension__
__PRETTY_FUNCTION__))
;
5594 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
5595 return DAG.getNode(CallOpc, dl, MVT::Other, Ops);
5596 }
5597
5598 std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}};
5599 Chain = DAG.getNode(CallOpc, dl, ReturnTypes, Ops);
5600 DAG.addNoMergeSiteInfo(Chain.getNode(), CFlags.NoMerge);
5601 Glue = Chain.getValue(1);
5602
5603 // When performing tail call optimization the callee pops its arguments off
5604 // the stack. Account for this here so these bytes can be pushed back on in
5605 // PPCFrameLowering::eliminateCallFramePseudoInstr.
5606 int BytesCalleePops = (CFlags.CallConv == CallingConv::Fast &&
5607 getTargetMachine().Options.GuaranteedTailCallOpt)
5608 ? NumBytes
5609 : 0;
5610
5611 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5612 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5613 Glue, dl);
5614 Glue = Chain.getValue(1);
5615
5616 return LowerCallResult(Chain, Glue, CFlags.CallConv, CFlags.IsVarArg, Ins, dl,
5617 DAG, InVals);
5618}
5619
5620SDValue
5621PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5622 SmallVectorImpl<SDValue> &InVals) const {
5623 SelectionDAG &DAG = CLI.DAG;
5624 SDLoc &dl = CLI.DL;
5625 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5626 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5627 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5628 SDValue Chain = CLI.Chain;
5629 SDValue Callee = CLI.Callee;
5630 bool &isTailCall = CLI.IsTailCall;
5631 CallingConv::ID CallConv = CLI.CallConv;
5632 bool isVarArg = CLI.IsVarArg;
5633 bool isPatchPoint = CLI.IsPatchPoint;
5634 const CallBase *CB = CLI.CB;
5635
5636 if (isTailCall) {
5637 if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall()))
5638 isTailCall = false;
5639 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5640 isTailCall = IsEligibleForTailCallOptimization_64SVR4(
5641 Callee, CallConv, CB, isVarArg, Outs, Ins, DAG);
5642 else
5643 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5644 Ins, DAG);
5645 if (isTailCall) {
5646 ++NumTailCalls;
5647 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5648 ++NumSiblingCalls;
5649
5650 // PC Relative calls no longer guarantee that the callee is a Global
5651 // Address Node. The callee could be an indirect tail call in which
5652 // case the SDValue for the callee could be a load (to load the address
5653 // of a function pointer) or it may be a register copy (to move the
5654 // address of the callee from a function parameter into a virtual
5655 // register). It may also be an ExternalSymbolSDNode (ex memcopy).
5656 assert((Subtarget.isUsingPCRelativeCalls() ||(static_cast <bool> ((Subtarget.isUsingPCRelativeCalls(
) || isa<GlobalAddressSDNode>(Callee)) && "Callee should be an llvm::Function object."
) ? void (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5658, __extension__
__PRETTY_FUNCTION__))
5657 isa<GlobalAddressSDNode>(Callee)) &&(static_cast <bool> ((Subtarget.isUsingPCRelativeCalls(
) || isa<GlobalAddressSDNode>(Callee)) && "Callee should be an llvm::Function object."
) ? void (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5658, __extension__
__PRETTY_FUNCTION__))
5658 "Callee should be an llvm::Function object.")(static_cast <bool> ((Subtarget.isUsingPCRelativeCalls(
) || isa<GlobalAddressSDNode>(Callee)) && "Callee should be an llvm::Function object."
) ? void (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5658, __extension__
__PRETTY_FUNCTION__))
;
5659
5660 LLVM_DEBUG(dbgs() << "TCO caller: " << DAG.getMachineFunction().getName()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
5661 << "\nTCO callee: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
;
5662 LLVM_DEBUG(Callee.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { Callee.dump(); } } while (false)
;
5663 }
5664 }
5665
5666 if (!isTailCall && CB && CB->isMustTailCall())
5667 report_fatal_error("failed to perform tail call elimination on a call "
5668 "site marked musttail");
5669
5670 // When long calls (i.e. indirect calls) are always used, calls are always
5671 // made via function pointer. If we have a function name, first translate it
5672 // into a pointer.
5673 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5674 !isTailCall)
5675 Callee = LowerGlobalAddress(Callee, DAG);
5676
5677 CallFlags CFlags(
5678 CallConv, isTailCall, isVarArg, isPatchPoint,
5679 isIndirectCall(Callee, DAG, Subtarget, isPatchPoint),
5680 // hasNest
5681 Subtarget.is64BitELFABI() &&
5682 any_of(Outs, [](ISD::OutputArg Arg) { return Arg.Flags.isNest(); }),
5683 CLI.NoMerge);
5684
5685 if (Subtarget.isAIXABI())
5686 return LowerCall_AIX(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5687 InVals, CB);
5688
5689 assert(Subtarget.isSVR4ABI())(static_cast <bool> (Subtarget.isSVR4ABI()) ? void (0) :
__assert_fail ("Subtarget.isSVR4ABI()", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5689, __extension__ __PRETTY_FUNCTION__))
;
5690 if (Subtarget.isPPC64())
5691 return LowerCall_64SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5692 InVals, CB);
5693 return LowerCall_32SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5694 InVals, CB);
5695}
5696
5697SDValue PPCTargetLowering::LowerCall_32SVR4(
5698 SDValue Chain, SDValue Callee, CallFlags CFlags,
5699 const SmallVectorImpl<ISD::OutputArg> &Outs,
5700 const SmallVectorImpl<SDValue> &OutVals,
5701 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5702 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5703 const CallBase *CB) const {
5704 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5705 // of the 32-bit SVR4 ABI stack frame layout.
5706
5707 const CallingConv::ID CallConv = CFlags.CallConv;
5708 const bool IsVarArg = CFlags.IsVarArg;
5709 const bool IsTailCall = CFlags.IsTailCall;
5710
5711 assert((CallConv == CallingConv::C ||(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5713, __extension__
__PRETTY_FUNCTION__))
5712 CallConv == CallingConv::Cold ||(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5713, __extension__
__PRETTY_FUNCTION__))
5713 CallConv == CallingConv::Fast) && "Unknown calling convention!")(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5713, __extension__
__PRETTY_FUNCTION__))
;
5714
5715 const Align PtrAlign(4);
5716
5717 MachineFunction &MF = DAG.getMachineFunction();
5718
5719 // Mark this function as potentially containing a function that contains a
5720 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5721 // and restoring the callers stack pointer in this functions epilog. This is
5722 // done because by tail calling the called function might overwrite the value
5723 // in this function's (MF) stack pointer stack slot 0(SP).
5724 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5725 CallConv == CallingConv::Fast)
5726 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5727
5728 // Count how many bytes are to be pushed on the stack, including the linkage
5729 // area, parameter list area and the part of the local variable space which
5730 // contains copies of aggregates which are passed by value.
5731
5732 // Assign locations to all of the outgoing arguments.
5733 SmallVector<CCValAssign, 16> ArgLocs;
5734 PPCCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
5735
5736 // Reserve space for the linkage area on the stack.
5737 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5738 PtrAlign);
5739 if (useSoftFloat())
5740 CCInfo.PreAnalyzeCallOperands(Outs);
5741
5742 if (IsVarArg) {
5743 // Handle fixed and variable vector arguments differently.
5744 // Fixed vector arguments go into registers as long as registers are
5745 // available. Variable vector arguments always go into memory.
5746 unsigned NumArgs = Outs.size();
5747
5748 for (unsigned i = 0; i != NumArgs; ++i) {
5749 MVT ArgVT = Outs[i].VT;
5750 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5751 bool Result;
5752
5753 if (Outs[i].IsFixed) {
5754 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5755 CCInfo);
5756 } else {
5757 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
5758 ArgFlags, CCInfo);
5759 }
5760
5761 if (Result) {
5762#ifndef NDEBUG
5763 errs() << "Call operand #" << i << " has unhandled type "
5764 << EVT(ArgVT).getEVTString() << "\n";
5765#endif
5766 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5766)
;