Bug Summary

File:llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Warning:line 9858, column 31
1st function call argument is an uninitialized value

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC -I include -I /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-command-line-argument -Wno-unknown-warning-option -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/build-llvm -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-09-26-234817-15343-1 -x c++ /build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
14#include "MCTargetDesc/PPCPredicates.h"
15#include "PPC.h"
16#include "PPCCCState.h"
17#include "PPCCallingConv.h"
18#include "PPCFrameLowering.h"
19#include "PPCInstrInfo.h"
20#include "PPCMachineFunctionInfo.h"
21#include "PPCPerfectShuffle.h"
22#include "PPCRegisterInfo.h"
23#include "PPCSubtarget.h"
24#include "PPCTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/None.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
36#include "llvm/ADT/StringSwitch.h"
37#include "llvm/CodeGen/CallingConvLower.h"
38#include "llvm/CodeGen/ISDOpcodes.h"
39#include "llvm/CodeGen/MachineBasicBlock.h"
40#include "llvm/CodeGen/MachineFrameInfo.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineInstr.h"
43#include "llvm/CodeGen/MachineInstrBuilder.h"
44#include "llvm/CodeGen/MachineJumpTableInfo.h"
45#include "llvm/CodeGen/MachineLoopInfo.h"
46#include "llvm/CodeGen/MachineMemOperand.h"
47#include "llvm/CodeGen/MachineModuleInfo.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/RuntimeLibcalls.h"
51#include "llvm/CodeGen/SelectionDAG.h"
52#include "llvm/CodeGen/SelectionDAGNodes.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetLowering.h"
55#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
56#include "llvm/CodeGen/TargetRegisterInfo.h"
57#include "llvm/CodeGen/ValueTypes.h"
58#include "llvm/IR/CallingConv.h"
59#include "llvm/IR/Constant.h"
60#include "llvm/IR/Constants.h"
61#include "llvm/IR/DataLayout.h"
62#include "llvm/IR/DebugLoc.h"
63#include "llvm/IR/DerivedTypes.h"
64#include "llvm/IR/Function.h"
65#include "llvm/IR/GlobalValue.h"
66#include "llvm/IR/IRBuilder.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/Intrinsics.h"
69#include "llvm/IR/IntrinsicsPowerPC.h"
70#include "llvm/IR/Module.h"
71#include "llvm/IR/Type.h"
72#include "llvm/IR/Use.h"
73#include "llvm/IR/Value.h"
74#include "llvm/MC/MCContext.h"
75#include "llvm/MC/MCExpr.h"
76#include "llvm/MC/MCRegisterInfo.h"
77#include "llvm/MC/MCSectionXCOFF.h"
78#include "llvm/MC/MCSymbolXCOFF.h"
79#include "llvm/Support/AtomicOrdering.h"
80#include "llvm/Support/BranchProbability.h"
81#include "llvm/Support/Casting.h"
82#include "llvm/Support/CodeGen.h"
83#include "llvm/Support/CommandLine.h"
84#include "llvm/Support/Compiler.h"
85#include "llvm/Support/Debug.h"
86#include "llvm/Support/ErrorHandling.h"
87#include "llvm/Support/Format.h"
88#include "llvm/Support/KnownBits.h"
89#include "llvm/Support/MachineValueType.h"
90#include "llvm/Support/MathExtras.h"
91#include "llvm/Support/raw_ostream.h"
92#include "llvm/Target/TargetMachine.h"
93#include "llvm/Target/TargetOptions.h"
94#include <algorithm>
95#include <cassert>
96#include <cstdint>
97#include <iterator>
98#include <list>
99#include <utility>
100#include <vector>
101
102using namespace llvm;
103
104#define DEBUG_TYPE"ppc-lowering" "ppc-lowering"
105
106static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
107cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
108
109static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
110cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
111
112static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
113cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
114
115static cl::opt<bool> DisableSCO("disable-ppc-sco",
116cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
117
118static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
119cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
120
121static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
122cl::desc("use absolute jump tables on ppc"), cl::Hidden);
123
124static cl::opt<bool> EnableQuadwordAtomics(
125 "ppc-quadword-atomics",
126 cl::desc("enable quadword lock-free atomic operations"), cl::init(false),
127 cl::Hidden);
128
129STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"ppc-lowering", "NumTailCalls"
, "Number of tail calls"}
;
130STATISTIC(NumSiblingCalls, "Number of sibling calls")static llvm::Statistic NumSiblingCalls = {"ppc-lowering", "NumSiblingCalls"
, "Number of sibling calls"}
;
131STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM")static llvm::Statistic ShufflesHandledWithVPERM = {"ppc-lowering"
, "ShufflesHandledWithVPERM", "Number of shuffles lowered to a VPERM"
}
;
132STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed")static llvm::Statistic NumDynamicAllocaProbed = {"ppc-lowering"
, "NumDynamicAllocaProbed", "Number of dynamic stack allocation probed"
}
;
133
134static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
135
136static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
137
138static const char AIXSSPCanaryWordName[] = "__ssp_canary_word";
139
140// FIXME: Remove this once the bug has been fixed!
141extern cl::opt<bool> ANDIGlueBug;
142
143PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
144 const PPCSubtarget &STI)
145 : TargetLowering(TM), Subtarget(STI) {
146 // Initialize map that relates the PPC addressing modes to the computed flags
147 // of a load/store instruction. The map is used to determine the optimal
148 // addressing mode when selecting load and stores.
149 initializeAddrModeMap();
150 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
151 // arguments are at least 4/8 bytes aligned.
152 bool isPPC64 = Subtarget.isPPC64();
153 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
154
155 // Set up the register classes.
156 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
157 if (!useSoftFloat()) {
158 if (hasSPE()) {
159 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
160 // EFPU2 APU only supports f32
161 if (!Subtarget.hasEFPU2())
162 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
163 } else {
164 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
165 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
166 }
167 }
168
169 // Match BITREVERSE to customized fast code sequence in the td file.
170 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
171 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
172
173 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
174 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
175
176 // Custom lower inline assembly to check for special registers.
177 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
178 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom);
179
180 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
181 for (MVT VT : MVT::integer_valuetypes()) {
182 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
183 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
184 }
185
186 if (Subtarget.isISA3_0()) {
187 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
188 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
189 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
190 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
191 } else {
192 // No extending loads from f16 or HW conversions back and forth.
193 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
194 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
195 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
196 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
197 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
198 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
199 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
200 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
201 }
202
203 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
204
205 // PowerPC has pre-inc load and store's.
206 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
207 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
208 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
209 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
210 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
211 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
212 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
213 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
214 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
215 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
216 if (!Subtarget.hasSPE()) {
217 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
218 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
219 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
220 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
221 }
222
223 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
224 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
225 for (MVT VT : ScalarIntVTs) {
226 setOperationAction(ISD::ADDC, VT, Legal);
227 setOperationAction(ISD::ADDE, VT, Legal);
228 setOperationAction(ISD::SUBC, VT, Legal);
229 setOperationAction(ISD::SUBE, VT, Legal);
230 }
231
232 if (Subtarget.useCRBits()) {
233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
234
235 if (isPPC64 || Subtarget.hasFPCVT()) {
236 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Promote);
237 AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1,
238 isPPC64 ? MVT::i64 : MVT::i32);
239 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Promote);
240 AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1,
241 isPPC64 ? MVT::i64 : MVT::i32);
242
243 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
244 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
245 isPPC64 ? MVT::i64 : MVT::i32);
246 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
247 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
248 isPPC64 ? MVT::i64 : MVT::i32);
249
250 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i1, Promote);
251 AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1,
252 isPPC64 ? MVT::i64 : MVT::i32);
253 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i1, Promote);
254 AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1,
255 isPPC64 ? MVT::i64 : MVT::i32);
256
257 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
258 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1,
259 isPPC64 ? MVT::i64 : MVT::i32);
260 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
261 AddPromotedToType(ISD::FP_TO_UINT, MVT::i1,
262 isPPC64 ? MVT::i64 : MVT::i32);
263 } else {
264 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom);
265 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom);
266 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
267 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
268 }
269
270 // PowerPC does not support direct load/store of condition registers.
271 setOperationAction(ISD::LOAD, MVT::i1, Custom);
272 setOperationAction(ISD::STORE, MVT::i1, Custom);
273
274 // FIXME: Remove this once the ANDI glue bug is fixed:
275 if (ANDIGlueBug)
276 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
277
278 for (MVT VT : MVT::integer_valuetypes()) {
279 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
280 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
281 setTruncStoreAction(VT, MVT::i1, Expand);
282 }
283
284 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
285 }
286
287 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
288 // PPC (the libcall is not available).
289 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
290 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
291 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::ppcf128, Custom);
292 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::ppcf128, Custom);
293
294 // We do not currently implement these libm ops for PowerPC.
295 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
296 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
297 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
298 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
299 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
300 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
301
302 // PowerPC has no SREM/UREM instructions unless we are on P9
303 // On P9 we may use a hardware instruction to compute the remainder.
304 // When the result of both the remainder and the division is required it is
305 // more efficient to compute the remainder from the result of the division
306 // rather than use the remainder instruction. The instructions are legalized
307 // directly because the DivRemPairsPass performs the transformation at the IR
308 // level.
309 if (Subtarget.isISA3_0()) {
310 setOperationAction(ISD::SREM, MVT::i32, Legal);
311 setOperationAction(ISD::UREM, MVT::i32, Legal);
312 setOperationAction(ISD::SREM, MVT::i64, Legal);
313 setOperationAction(ISD::UREM, MVT::i64, Legal);
314 } else {
315 setOperationAction(ISD::SREM, MVT::i32, Expand);
316 setOperationAction(ISD::UREM, MVT::i32, Expand);
317 setOperationAction(ISD::SREM, MVT::i64, Expand);
318 setOperationAction(ISD::UREM, MVT::i64, Expand);
319 }
320
321 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
322 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
323 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
324 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
325 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
326 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
327 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
328 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
329 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
330
331 // Handle constrained floating-point operations of scalar.
332 // TODO: Handle SPE specific operation.
333 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
334 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
335 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
336 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
337 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
338
339 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
340 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
341 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
342 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
343
344 if (!Subtarget.hasSPE()) {
345 setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal);
346 setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal);
347 }
348
349 if (Subtarget.hasVSX()) {
350 setOperationAction(ISD::STRICT_FRINT, MVT::f32, Legal);
351 setOperationAction(ISD::STRICT_FRINT, MVT::f64, Legal);
352 }
353
354 if (Subtarget.hasFSQRT()) {
355 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
356 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
357 }
358
359 if (Subtarget.hasFPRND()) {
360 setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal);
361 setOperationAction(ISD::STRICT_FCEIL, MVT::f32, Legal);
362 setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal);
363 setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal);
364
365 setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal);
366 setOperationAction(ISD::STRICT_FCEIL, MVT::f64, Legal);
367 setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal);
368 setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal);
369 }
370
371 // We don't support sin/cos/sqrt/fmod/pow
372 setOperationAction(ISD::FSIN , MVT::f64, Expand);
373 setOperationAction(ISD::FCOS , MVT::f64, Expand);
374 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
375 setOperationAction(ISD::FREM , MVT::f64, Expand);
376 setOperationAction(ISD::FPOW , MVT::f64, Expand);
377 setOperationAction(ISD::FSIN , MVT::f32, Expand);
378 setOperationAction(ISD::FCOS , MVT::f32, Expand);
379 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
380 setOperationAction(ISD::FREM , MVT::f32, Expand);
381 setOperationAction(ISD::FPOW , MVT::f32, Expand);
382 if (Subtarget.hasSPE()) {
383 setOperationAction(ISD::FMA , MVT::f64, Expand);
384 setOperationAction(ISD::FMA , MVT::f32, Expand);
385 } else {
386 setOperationAction(ISD::FMA , MVT::f64, Legal);
387 setOperationAction(ISD::FMA , MVT::f32, Legal);
388 }
389
390 if (Subtarget.hasSPE())
391 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
392
393 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
394
395 // If we're enabling GP optimizations, use hardware square root
396 if (!Subtarget.hasFSQRT() &&
397 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
398 Subtarget.hasFRE()))
399 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
400
401 if (!Subtarget.hasFSQRT() &&
402 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
403 Subtarget.hasFRES()))
404 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
405
406 if (Subtarget.hasFCPSGN()) {
407 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
408 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
409 } else {
410 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
411 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
412 }
413
414 if (Subtarget.hasFPRND()) {
415 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
416 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
417 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
418 setOperationAction(ISD::FROUND, MVT::f64, Legal);
419
420 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
421 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
422 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
423 setOperationAction(ISD::FROUND, MVT::f32, Legal);
424 }
425
426 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
427 // to speed up scalar BSWAP64.
428 // CTPOP or CTTZ were introduced in P8/P9 respectively
429 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
430 if (Subtarget.hasP9Vector() && Subtarget.isPPC64())
431 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
432 else
433 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
434 if (Subtarget.isISA3_0()) {
435 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
436 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
437 } else {
438 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
439 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
440 }
441
442 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
443 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
444 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
445 } else {
446 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
447 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
448 }
449
450 // PowerPC does not have ROTR
451 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
452 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
453
454 if (!Subtarget.useCRBits()) {
455 // PowerPC does not have Select
456 setOperationAction(ISD::SELECT, MVT::i32, Expand);
457 setOperationAction(ISD::SELECT, MVT::i64, Expand);
458 setOperationAction(ISD::SELECT, MVT::f32, Expand);
459 setOperationAction(ISD::SELECT, MVT::f64, Expand);
460 }
461
462 // PowerPC wants to turn select_cc of FP into fsel when possible.
463 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
464 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
465
466 // PowerPC wants to optimize integer setcc a bit
467 if (!Subtarget.useCRBits())
468 setOperationAction(ISD::SETCC, MVT::i32, Custom);
469
470 if (Subtarget.hasFPU()) {
471 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal);
472 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal);
473 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal);
474
475 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
476 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
477 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal);
478 }
479
480 // PowerPC does not have BRCOND which requires SetCC
481 if (!Subtarget.useCRBits())
482 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
483
484 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
485
486 if (Subtarget.hasSPE()) {
487 // SPE has built-in conversions
488 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal);
489 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Legal);
490 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Legal);
491 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
492 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
493 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
494
495 // SPE supports signaling compare of f32/f64.
496 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
497 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
498 } else {
499 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
500 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
501 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
502
503 // PowerPC does not have [U|S]INT_TO_FP
504 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Expand);
505 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Expand);
506 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
507 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
508 }
509
510 if (Subtarget.hasDirectMove() && isPPC64) {
511 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
512 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
513 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
514 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
515 if (TM.Options.UnsafeFPMath) {
516 setOperationAction(ISD::LRINT, MVT::f64, Legal);
517 setOperationAction(ISD::LRINT, MVT::f32, Legal);
518 setOperationAction(ISD::LLRINT, MVT::f64, Legal);
519 setOperationAction(ISD::LLRINT, MVT::f32, Legal);
520 setOperationAction(ISD::LROUND, MVT::f64, Legal);
521 setOperationAction(ISD::LROUND, MVT::f32, Legal);
522 setOperationAction(ISD::LLROUND, MVT::f64, Legal);
523 setOperationAction(ISD::LLROUND, MVT::f32, Legal);
524 }
525 } else {
526 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
527 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
528 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
529 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
530 }
531
532 // We cannot sextinreg(i1). Expand to shifts.
533 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
534
535 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
536 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
537 // support continuation, user-level threading, and etc.. As a result, no
538 // other SjLj exception interfaces are implemented and please don't build
539 // your own exception handling based on them.
540 // LLVM/Clang supports zero-cost DWARF exception handling.
541 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
542 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
543
544 // We want to legalize GlobalAddress and ConstantPool nodes into the
545 // appropriate instructions to materialize the address.
546 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
547 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
548 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
549 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
550 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
551 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
552 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
553 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
554 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
555 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
556
557 // TRAP is legal.
558 setOperationAction(ISD::TRAP, MVT::Other, Legal);
559
560 // TRAMPOLINE is custom lowered.
561 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
562 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
563
564 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
565 setOperationAction(ISD::VASTART , MVT::Other, Custom);
566
567 if (Subtarget.is64BitELFABI()) {
568 // VAARG always uses double-word chunks, so promote anything smaller.
569 setOperationAction(ISD::VAARG, MVT::i1, Promote);
570 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
571 setOperationAction(ISD::VAARG, MVT::i8, Promote);
572 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
573 setOperationAction(ISD::VAARG, MVT::i16, Promote);
574 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
575 setOperationAction(ISD::VAARG, MVT::i32, Promote);
576 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
577 setOperationAction(ISD::VAARG, MVT::Other, Expand);
578 } else if (Subtarget.is32BitELFABI()) {
579 // VAARG is custom lowered with the 32-bit SVR4 ABI.
580 setOperationAction(ISD::VAARG, MVT::Other, Custom);
581 setOperationAction(ISD::VAARG, MVT::i64, Custom);
582 } else
583 setOperationAction(ISD::VAARG, MVT::Other, Expand);
584
585 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
586 if (Subtarget.is32BitELFABI())
587 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
588 else
589 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
590
591 // Use the default implementation.
592 setOperationAction(ISD::VAEND , MVT::Other, Expand);
593 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
594 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
595 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
596 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
597 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
598 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
599 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
600 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
601
602 // We want to custom lower some of our intrinsics.
603 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
604
605 // To handle counter-based loop conditions.
606 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
607
608 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
609 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
610 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
611 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
612
613 // Comparisons that require checking two conditions.
614 if (Subtarget.hasSPE()) {
615 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
616 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
617 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
618 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
619 }
620 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
621 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
622 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
623 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
624 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
625 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
626 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
627 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
628 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
629 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
630 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
631 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
632
633 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
634 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
635
636 if (Subtarget.has64BitSupport()) {
637 // They also have instructions for converting between i64 and fp.
638 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
639 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand);
640 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
641 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand);
642 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
643 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
644 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
645 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
646 // This is just the low 32 bits of a (signed) fp->i64 conversion.
647 // We cannot do this with Promote because i64 is not a legal type.
648 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
649 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
650
651 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
652 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
653 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
654 }
655 } else {
656 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
657 if (Subtarget.hasSPE()) {
658 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal);
659 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
660 } else {
661 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand);
662 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
663 }
664 }
665
666 // With the instructions enabled under FPCVT, we can do everything.
667 if (Subtarget.hasFPCVT()) {
668 if (Subtarget.has64BitSupport()) {
669 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
670 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
671 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
672 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
673 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
674 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
675 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
676 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
677 }
678
679 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
680 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
681 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
682 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
683 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
684 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
685 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
686 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
687 }
688
689 if (Subtarget.use64BitRegs()) {
690 // 64-bit PowerPC implementations can support i64 types directly
691 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
692 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
693 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
694 // 64-bit PowerPC wants to expand i128 shifts itself.
695 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
696 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
697 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
698 } else {
699 // 32-bit PowerPC wants to expand i64 shifts itself.
700 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
701 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
702 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
703 }
704
705 // PowerPC has better expansions for funnel shifts than the generic
706 // TargetLowering::expandFunnelShift.
707 if (Subtarget.has64BitSupport()) {
708 setOperationAction(ISD::FSHL, MVT::i64, Custom);
709 setOperationAction(ISD::FSHR, MVT::i64, Custom);
710 }
711 setOperationAction(ISD::FSHL, MVT::i32, Custom);
712 setOperationAction(ISD::FSHR, MVT::i32, Custom);
713
714 if (Subtarget.hasVSX()) {
715 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
716 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
717 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
718 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
719 }
720
721 if (Subtarget.hasAltivec()) {
722 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
723 setOperationAction(ISD::SADDSAT, VT, Legal);
724 setOperationAction(ISD::SSUBSAT, VT, Legal);
725 setOperationAction(ISD::UADDSAT, VT, Legal);
726 setOperationAction(ISD::USUBSAT, VT, Legal);
727 }
728 // First set operation action for all vector types to expand. Then we
729 // will selectively turn on ones that can be effectively codegen'd.
730 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
731 // add/sub are legal for all supported vector VT's.
732 setOperationAction(ISD::ADD, VT, Legal);
733 setOperationAction(ISD::SUB, VT, Legal);
734
735 // For v2i64, these are only valid with P8Vector. This is corrected after
736 // the loop.
737 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
738 setOperationAction(ISD::SMAX, VT, Legal);
739 setOperationAction(ISD::SMIN, VT, Legal);
740 setOperationAction(ISD::UMAX, VT, Legal);
741 setOperationAction(ISD::UMIN, VT, Legal);
742 }
743 else {
744 setOperationAction(ISD::SMAX, VT, Expand);
745 setOperationAction(ISD::SMIN, VT, Expand);
746 setOperationAction(ISD::UMAX, VT, Expand);
747 setOperationAction(ISD::UMIN, VT, Expand);
748 }
749
750 if (Subtarget.hasVSX()) {
751 setOperationAction(ISD::FMAXNUM, VT, Legal);
752 setOperationAction(ISD::FMINNUM, VT, Legal);
753 }
754
755 // Vector instructions introduced in P8
756 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
757 setOperationAction(ISD::CTPOP, VT, Legal);
758 setOperationAction(ISD::CTLZ, VT, Legal);
759 }
760 else {
761 setOperationAction(ISD::CTPOP, VT, Expand);
762 setOperationAction(ISD::CTLZ, VT, Expand);
763 }
764
765 // Vector instructions introduced in P9
766 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
767 setOperationAction(ISD::CTTZ, VT, Legal);
768 else
769 setOperationAction(ISD::CTTZ, VT, Expand);
770
771 // We promote all shuffles to v16i8.
772 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
773 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
774
775 // We promote all non-typed operations to v4i32.
776 setOperationAction(ISD::AND , VT, Promote);
777 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
778 setOperationAction(ISD::OR , VT, Promote);
779 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
780 setOperationAction(ISD::XOR , VT, Promote);
781 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
782 setOperationAction(ISD::LOAD , VT, Promote);
783 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
784 setOperationAction(ISD::SELECT, VT, Promote);
785 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
786 setOperationAction(ISD::VSELECT, VT, Legal);
787 setOperationAction(ISD::SELECT_CC, VT, Promote);
788 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
789 setOperationAction(ISD::STORE, VT, Promote);
790 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
791
792 // No other operations are legal.
793 setOperationAction(ISD::MUL , VT, Expand);
794 setOperationAction(ISD::SDIV, VT, Expand);
795 setOperationAction(ISD::SREM, VT, Expand);
796 setOperationAction(ISD::UDIV, VT, Expand);
797 setOperationAction(ISD::UREM, VT, Expand);
798 setOperationAction(ISD::FDIV, VT, Expand);
799 setOperationAction(ISD::FREM, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSQRT, VT, Expand);
802 setOperationAction(ISD::FLOG, VT, Expand);
803 setOperationAction(ISD::FLOG10, VT, Expand);
804 setOperationAction(ISD::FLOG2, VT, Expand);
805 setOperationAction(ISD::FEXP, VT, Expand);
806 setOperationAction(ISD::FEXP2, VT, Expand);
807 setOperationAction(ISD::FSIN, VT, Expand);
808 setOperationAction(ISD::FCOS, VT, Expand);
809 setOperationAction(ISD::FABS, VT, Expand);
810 setOperationAction(ISD::FFLOOR, VT, Expand);
811 setOperationAction(ISD::FCEIL, VT, Expand);
812 setOperationAction(ISD::FTRUNC, VT, Expand);
813 setOperationAction(ISD::FRINT, VT, Expand);
814 setOperationAction(ISD::FNEARBYINT, VT, Expand);
815 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
816 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
817 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
818 setOperationAction(ISD::MULHU, VT, Expand);
819 setOperationAction(ISD::MULHS, VT, Expand);
820 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
821 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
822 setOperationAction(ISD::UDIVREM, VT, Expand);
823 setOperationAction(ISD::SDIVREM, VT, Expand);
824 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
825 setOperationAction(ISD::FPOW, VT, Expand);
826 setOperationAction(ISD::BSWAP, VT, Expand);
827 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
828 setOperationAction(ISD::ROTL, VT, Expand);
829 setOperationAction(ISD::ROTR, VT, Expand);
830
831 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
832 setTruncStoreAction(VT, InnerVT, Expand);
833 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
834 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
835 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
836 }
837 }
838 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand);
839 if (!Subtarget.hasP8Vector()) {
840 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
841 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
842 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
843 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
844 }
845
846 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
847 // with merges, splats, etc.
848 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
849
850 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
851 // are cheap, so handle them before they get expanded to scalar.
852 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
853 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
854 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
855 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
856 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
857
858 setOperationAction(ISD::AND , MVT::v4i32, Legal);
859 setOperationAction(ISD::OR , MVT::v4i32, Legal);
860 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
861 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
862 setOperationAction(ISD::SELECT, MVT::v4i32,
863 Subtarget.useCRBits() ? Legal : Expand);
864 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
865 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
866 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
867 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
868 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
869 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
870 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
871 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
872 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
873 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
874 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
875 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
876 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
877
878 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
879 setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
880 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
881 if (Subtarget.hasAltivec())
882 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
883 setOperationAction(ISD::ROTL, VT, Legal);
884 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
885 if (Subtarget.hasP8Altivec())
886 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
887
888 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
889 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
890 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
891 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
892
893 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
894 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
895
896 if (Subtarget.hasVSX()) {
897 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
898 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
899 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
900 }
901
902 if (Subtarget.hasP8Altivec())
903 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
904 else
905 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
906
907 if (Subtarget.isISA3_1()) {
908 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
909 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
910 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
911 setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
912 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
913 setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
914 setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
915 setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
916 setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
917 setOperationAction(ISD::UREM, MVT::v2i64, Legal);
918 setOperationAction(ISD::SREM, MVT::v2i64, Legal);
919 setOperationAction(ISD::UREM, MVT::v4i32, Legal);
920 setOperationAction(ISD::SREM, MVT::v4i32, Legal);
921 setOperationAction(ISD::UREM, MVT::v1i128, Legal);
922 setOperationAction(ISD::SREM, MVT::v1i128, Legal);
923 setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
924 setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
925 setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
926 }
927
928 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
929 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
930
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
932 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
933
934 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
935 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
936 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
937 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
938
939 // Altivec does not contain unordered floating-point compare instructions
940 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
941 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
942 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
943 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
944
945 if (Subtarget.hasVSX()) {
946 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
947 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
948 if (Subtarget.hasP8Vector()) {
949 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
950 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
951 }
952 if (Subtarget.hasDirectMove() && isPPC64) {
953 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
954 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
955 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
956 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
957 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
958 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
959 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
960 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
961 }
962 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
963
964 // The nearbyint variants are not allowed to raise the inexact exception
965 // so we can only code-gen them with unsafe math.
966 if (TM.Options.UnsafeFPMath) {
967 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
968 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
969 }
970
971 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
972 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
973 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
974 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
975 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
976 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
977 setOperationAction(ISD::FROUND, MVT::f64, Legal);
978 setOperationAction(ISD::FRINT, MVT::f64, Legal);
979
980 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
981 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
982 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
983 setOperationAction(ISD::FROUND, MVT::f32, Legal);
984 setOperationAction(ISD::FRINT, MVT::f32, Legal);
985
986 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
988
989 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
990 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
991
992 // Share the Altivec comparison restrictions.
993 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
994 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
995 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
996 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
997
998 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
999 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
1000
1001 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
1002
1003 if (Subtarget.hasP8Vector())
1004 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
1005
1006 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
1007
1008 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
1009 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
1010 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
1011
1012 if (Subtarget.hasP8Altivec()) {
1013 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1014 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
1015 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1016
1017 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1018 // SRL, but not for SRA because of the instructions available:
1019 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
1020 // doing
1021 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
1022 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
1023 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1024
1025 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
1026 }
1027 else {
1028 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1029 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
1030 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
1031
1032 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1033
1034 // VSX v2i64 only supports non-arithmetic operations.
1035 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
1036 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
1037 }
1038
1039 if (Subtarget.isISA3_1())
1040 setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
1041 else
1042 setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
1043
1044 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
1045 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
1046 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
1047 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
1048
1049 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
1050
1051 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
1052 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
1053 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
1054 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
1055 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1056 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1057 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1058 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1059
1060 // Custom handling for partial vectors of integers converted to
1061 // floating point. We already have optimal handling for v2i32 through
1062 // the DAG combine, so those aren't necessary.
1063 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom);
1064 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom);
1065 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
1066 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
1067 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom);
1068 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom);
1069 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
1070 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
1071 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
1074 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1075 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom);
1076 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
1077 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
1078 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
1079
1080 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1081 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1082 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
1083 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1084 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
1085 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
1086
1087 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1088 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1089
1090 // Handle constrained floating-point operations of vector.
1091 // The predictor is `hasVSX` because altivec instruction has
1092 // no exception but VSX vector instruction has.
1093 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
1094 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
1095 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
1096 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
1097 setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal);
1098 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
1099 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v4f32, Legal);
1100 setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal);
1101 setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal);
1102 setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
1103 setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal);
1104 setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
1105 setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
1106
1107 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
1108 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
1109 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
1110 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
1111 setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal);
1112 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1113 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v2f64, Legal);
1114 setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal);
1115 setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal);
1116 setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
1117 setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal);
1118 setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
1119 setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
1120
1121 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1122 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1123
1124 for (MVT FPT : MVT::fp_valuetypes())
1125 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1126
1127 // Expand the SELECT to SELECT_CC
1128 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1129
1130 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1131 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1132
1133 // No implementation for these ops for PowerPC.
1134 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1135 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1136 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1137 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
1138 setOperationAction(ISD::FREM, MVT::f128, Expand);
1139 }
1140
1141 if (Subtarget.hasP8Altivec()) {
1142 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
1143 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
1144 }
1145
1146 if (Subtarget.hasP9Vector()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1148 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1149
1150 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1151 // SRL, but not for SRA because of the instructions available:
1152 // VS{RL} and VS{RL}O.
1153 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1154 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
1155 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1156
1157 setOperationAction(ISD::FADD, MVT::f128, Legal);
1158 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1159 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1160 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1161 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1162
1163 setOperationAction(ISD::FMA, MVT::f128, Legal);
1164 setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
1165 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
1166 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
1167 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
1168 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
1169 setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
1170
1171 setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
1172 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1173 setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
1174 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1175 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
1176 setOperationAction(ISD::FROUND, MVT::f128, Legal);
1177
1178 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1179 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
1180 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
1181
1182 // Handle constrained floating-point operations of fp128
1183 setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
1184 setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
1185 setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
1186 setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
1187 setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
1188 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
1189 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
1190 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
1191 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
1192 setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
1193 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
1194 setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
1195 setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
1196 setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
1197 setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
1198 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1199 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1200 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1201 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
1202 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
1203 } else if (Subtarget.hasVSX()) {
1204 setOperationAction(ISD::LOAD, MVT::f128, Promote);
1205 setOperationAction(ISD::STORE, MVT::f128, Promote);
1206
1207 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
1208 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
1209
1210 // Set FADD/FSUB as libcall to avoid the legalizer to expand the
1211 // fp_to_uint and int_to_fp.
1212 setOperationAction(ISD::FADD, MVT::f128, LibCall);
1213 setOperationAction(ISD::FSUB, MVT::f128, LibCall);
1214
1215 setOperationAction(ISD::FMUL, MVT::f128, Expand);
1216 setOperationAction(ISD::FDIV, MVT::f128, Expand);
1217 setOperationAction(ISD::FNEG, MVT::f128, Expand);
1218 setOperationAction(ISD::FABS, MVT::f128, Expand);
1219 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
1220 setOperationAction(ISD::FMA, MVT::f128, Expand);
1221 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1222
1223 // Expand the fp_extend if the target type is fp128.
1224 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
1225 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Expand);
1226
1227 // Expand the fp_round if the source type is fp128.
1228 for (MVT VT : {MVT::f32, MVT::f64}) {
1229 setOperationAction(ISD::FP_ROUND, VT, Custom);
1230 setOperationAction(ISD::STRICT_FP_ROUND, VT, Custom);
1231 }
1232
1233 setOperationAction(ISD::SETCC, MVT::f128, Custom);
1234 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Custom);
1235 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom);
1236 setOperationAction(ISD::BR_CC, MVT::f128, Expand);
1237
1238 // Lower following f128 select_cc pattern:
1239 // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv, NE
1240 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1241
1242 // We need to handle f128 SELECT_CC with integer result type.
1243 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1244 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand);
1245 }
1246
1247 if (Subtarget.hasP9Altivec()) {
1248 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1249 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1250
1251 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
1252 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
1253 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
1254 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
1255 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1256 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
1257 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
1258 }
1259
1260 if (Subtarget.isISA3_1())
1261 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1262 }
1263
1264 if (Subtarget.pairedVectorMemops()) {
1265 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
1266 setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
1267 setOperationAction(ISD::STORE, MVT::v256i1, Custom);
1268 }
1269 if (Subtarget.hasMMA()) {
1270 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1271 setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
1272 setOperationAction(ISD::STORE, MVT::v512i1, Custom);
1273 setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom);
1274 }
1275
1276 if (Subtarget.has64BitSupport())
1277 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
1278
1279 if (Subtarget.isISA3_1())
1280 setOperationAction(ISD::SRA, MVT::v1i128, Legal);
1281
1282 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1283
1284 if (!isPPC64) {
1285 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
1286 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
1287 }
1288
1289 if (EnableQuadwordAtomics && Subtarget.hasQuadwordAtomics()) {
1290 setMaxAtomicSizeInBitsSupported(128);
1291 setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom);
1292 setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom);
1293 setOperationAction(ISD::INTRINSIC_VOID, MVT::i128, Custom);
1294 }
1295
1296 setBooleanContents(ZeroOrOneBooleanContent);
1297
1298 if (Subtarget.hasAltivec()) {
1299 // Altivec instructions set fields to all zeros or all ones.
1300 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
1301 }
1302
1303 if (!isPPC64) {
1304 // These libcalls are not available in 32-bit.
1305 setLibcallName(RTLIB::SHL_I128, nullptr);
1306 setLibcallName(RTLIB::SRL_I128, nullptr);
1307 setLibcallName(RTLIB::SRA_I128, nullptr);
1308 setLibcallName(RTLIB::MULO_I64, nullptr);
1309 }
1310
1311 if (!isPPC64)
1312 setMaxAtomicSizeInBitsSupported(32);
1313
1314 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1315
1316 // We have target-specific dag combine patterns for the following nodes:
1317 setTargetDAGCombine(ISD::ADD);
1318 setTargetDAGCombine(ISD::SHL);
1319 setTargetDAGCombine(ISD::SRA);
1320 setTargetDAGCombine(ISD::SRL);
1321 setTargetDAGCombine(ISD::MUL);
1322 setTargetDAGCombine(ISD::FMA);
1323 setTargetDAGCombine(ISD::SINT_TO_FP);
1324 setTargetDAGCombine(ISD::BUILD_VECTOR);
1325 if (Subtarget.hasFPCVT())
1326 setTargetDAGCombine(ISD::UINT_TO_FP);
1327 setTargetDAGCombine(ISD::LOAD);
1328 setTargetDAGCombine(ISD::STORE);
1329 setTargetDAGCombine(ISD::BR_CC);
1330 if (Subtarget.useCRBits())
1331 setTargetDAGCombine(ISD::BRCOND);
1332 setTargetDAGCombine(ISD::BSWAP);
1333 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1334 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
1335 setTargetDAGCombine(ISD::INTRINSIC_VOID);
1336
1337 setTargetDAGCombine(ISD::SIGN_EXTEND);
1338 setTargetDAGCombine(ISD::ZERO_EXTEND);
1339 setTargetDAGCombine(ISD::ANY_EXTEND);
1340
1341 setTargetDAGCombine(ISD::TRUNCATE);
1342 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1343
1344
1345 if (Subtarget.useCRBits()) {
1346 setTargetDAGCombine(ISD::TRUNCATE);
1347 setTargetDAGCombine(ISD::SETCC);
1348 setTargetDAGCombine(ISD::SELECT_CC);
1349 }
1350
1351 if (Subtarget.hasP9Altivec()) {
1352 setTargetDAGCombine(ISD::ABS);
1353 setTargetDAGCombine(ISD::VSELECT);
1354 }
1355
1356 setLibcallName(RTLIB::LOG_F128, "logf128");
1357 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1358 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1359 setLibcallName(RTLIB::EXP_F128, "expf128");
1360 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1361 setLibcallName(RTLIB::SIN_F128, "sinf128");
1362 setLibcallName(RTLIB::COS_F128, "cosf128");
1363 setLibcallName(RTLIB::POW_F128, "powf128");
1364 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1365 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1366 setLibcallName(RTLIB::REM_F128, "fmodf128");
1367 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
1368 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
1369 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
1370 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
1371 setLibcallName(RTLIB::ROUND_F128, "roundf128");
1372 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
1373 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
1374 setLibcallName(RTLIB::RINT_F128, "rintf128");
1375 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
1376 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
1377 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
1378 setLibcallName(RTLIB::FMA_F128, "fmaf128");
1379
1380 // With 32 condition bits, we don't need to sink (and duplicate) compares
1381 // aggressively in CodeGenPrep.
1382 if (Subtarget.useCRBits()) {
1383 setHasMultipleConditionRegisters();
1384 setJumpIsExpensive();
1385 }
1386
1387 setMinFunctionAlignment(Align(4));
1388
1389 switch (Subtarget.getCPUDirective()) {
1390 default: break;
1391 case PPC::DIR_970:
1392 case PPC::DIR_A2:
1393 case PPC::DIR_E500:
1394 case PPC::DIR_E500mc:
1395 case PPC::DIR_E5500:
1396 case PPC::DIR_PWR4:
1397 case PPC::DIR_PWR5:
1398 case PPC::DIR_PWR5X:
1399 case PPC::DIR_PWR6:
1400 case PPC::DIR_PWR6X:
1401 case PPC::DIR_PWR7:
1402 case PPC::DIR_PWR8:
1403 case PPC::DIR_PWR9:
1404 case PPC::DIR_PWR10:
1405 case PPC::DIR_PWR_FUTURE:
1406 setPrefLoopAlignment(Align(16));
1407 setPrefFunctionAlignment(Align(16));
1408 break;
1409 }
1410
1411 if (Subtarget.enableMachineScheduler())
1412 setSchedulingPreference(Sched::Source);
1413 else
1414 setSchedulingPreference(Sched::Hybrid);
1415
1416 computeRegisterProperties(STI.getRegisterInfo());
1417
1418 // The Freescale cores do better with aggressive inlining of memcpy and
1419 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1420 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1421 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1422 MaxStoresPerMemset = 32;
1423 MaxStoresPerMemsetOptSize = 16;
1424 MaxStoresPerMemcpy = 32;
1425 MaxStoresPerMemcpyOptSize = 8;
1426 MaxStoresPerMemmove = 32;
1427 MaxStoresPerMemmoveOptSize = 8;
1428 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1429 // The A2 also benefits from (very) aggressive inlining of memcpy and
1430 // friends. The overhead of a the function call, even when warm, can be
1431 // over one hundred cycles.
1432 MaxStoresPerMemset = 128;
1433 MaxStoresPerMemcpy = 128;
1434 MaxStoresPerMemmove = 128;
1435 MaxLoadsPerMemcmp = 128;
1436 } else {
1437 MaxLoadsPerMemcmp = 8;
1438 MaxLoadsPerMemcmpOptSize = 4;
1439 }
1440
1441 IsStrictFPEnabled = true;
1442
1443 // Let the subtarget (CPU) decide if a predictable select is more expensive
1444 // than the corresponding branch. This information is used in CGP to decide
1445 // when to convert selects into branches.
1446 PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive();
1447}
1448
1449// *********************************** NOTE ************************************
1450// For selecting load and store instructions, the addressing modes are defined
1451// as ComplexPatterns in PPCInstrInfo.td, which are then utilized in the TD
1452// patterns to match the load the store instructions.
1453//
1454// The TD definitions for the addressing modes correspond to their respective
1455// Select<AddrMode>Form() function in PPCISelDAGToDAG.cpp. These functions rely
1456// on SelectOptimalAddrMode(), which calls computeMOFlags() to compute the
1457// address mode flags of a particular node. Afterwards, the computed address
1458// flags are passed into getAddrModeForFlags() in order to retrieve the optimal
1459// addressing mode. SelectOptimalAddrMode() then sets the Base and Displacement
1460// accordingly, based on the preferred addressing mode.
1461//
1462// Within PPCISelLowering.h, there are two enums: MemOpFlags and AddrMode.
1463// MemOpFlags contains all the possible flags that can be used to compute the
1464// optimal addressing mode for load and store instructions.
1465// AddrMode contains all the possible load and store addressing modes available
1466// on Power (such as DForm, DSForm, DQForm, XForm, etc.)
1467//
1468// When adding new load and store instructions, it is possible that new address
1469// flags may need to be added into MemOpFlags, and a new addressing mode will
1470// need to be added to AddrMode. An entry of the new addressing mode (consisting
1471// of the minimal and main distinguishing address flags for the new load/store
1472// instructions) will need to be added into initializeAddrModeMap() below.
1473// Finally, when adding new addressing modes, the getAddrModeForFlags() will
1474// need to be updated to account for selecting the optimal addressing mode.
1475// *****************************************************************************
1476/// Initialize the map that relates the different addressing modes of the load
1477/// and store instructions to a set of flags. This ensures the load/store
1478/// instruction is correctly matched during instruction selection.
1479void PPCTargetLowering::initializeAddrModeMap() {
1480 AddrModesMap[PPC::AM_DForm] = {
1481 // LWZ, STW
1482 PPC::MOF_ZExt | PPC::MOF_RPlusSImm16 | PPC::MOF_WordInt,
1483 PPC::MOF_ZExt | PPC::MOF_RPlusLo | PPC::MOF_WordInt,
1484 PPC::MOF_ZExt | PPC::MOF_NotAddNorCst | PPC::MOF_WordInt,
1485 PPC::MOF_ZExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_WordInt,
1486 // LBZ, LHZ, STB, STH
1487 PPC::MOF_ZExt | PPC::MOF_RPlusSImm16 | PPC::MOF_SubWordInt,
1488 PPC::MOF_ZExt | PPC::MOF_RPlusLo | PPC::MOF_SubWordInt,
1489 PPC::MOF_ZExt | PPC::MOF_NotAddNorCst | PPC::MOF_SubWordInt,
1490 PPC::MOF_ZExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_SubWordInt,
1491 // LHA
1492 PPC::MOF_SExt | PPC::MOF_RPlusSImm16 | PPC::MOF_SubWordInt,
1493 PPC::MOF_SExt | PPC::MOF_RPlusLo | PPC::MOF_SubWordInt,
1494 PPC::MOF_SExt | PPC::MOF_NotAddNorCst | PPC::MOF_SubWordInt,
1495 PPC::MOF_SExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_SubWordInt,
1496 // LFS, LFD, STFS, STFD
1497 PPC::MOF_RPlusSImm16 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1498 PPC::MOF_RPlusLo | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1499 PPC::MOF_NotAddNorCst | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1500 PPC::MOF_AddrIsSImm32 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1501 };
1502 AddrModesMap[PPC::AM_DSForm] = {
1503 // LWA
1504 PPC::MOF_SExt | PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_WordInt,
1505 PPC::MOF_SExt | PPC::MOF_NotAddNorCst | PPC::MOF_WordInt,
1506 PPC::MOF_SExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_WordInt,
1507 // LD, STD
1508 PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_DoubleWordInt,
1509 PPC::MOF_NotAddNorCst | PPC::MOF_DoubleWordInt,
1510 PPC::MOF_AddrIsSImm32 | PPC::MOF_DoubleWordInt,
1511 // DFLOADf32, DFLOADf64, DSTOREf32, DSTOREf64
1512 PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9,
1513 PPC::MOF_NotAddNorCst | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9,
1514 PPC::MOF_AddrIsSImm32 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9,
1515 };
1516 AddrModesMap[PPC::AM_DQForm] = {
1517 // LXV, STXV
1518 PPC::MOF_RPlusSImm16Mult16 | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
1519 PPC::MOF_NotAddNorCst | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
1520 PPC::MOF_AddrIsSImm32 | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
1521 };
1522 AddrModesMap[PPC::AM_PrefixDForm] = {PPC::MOF_RPlusSImm34 |
1523 PPC::MOF_SubtargetP10};
1524 // TODO: Add mapping for quadword load/store.
1525}
1526
1527/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1528/// the desired ByVal argument alignment.
1529static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
1530 if (MaxAlign == MaxMaxAlign)
1531 return;
1532 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1533 if (MaxMaxAlign >= 32 &&
1534 VTy->getPrimitiveSizeInBits().getFixedSize() >= 256)
1535 MaxAlign = Align(32);
1536 else if (VTy->getPrimitiveSizeInBits().getFixedSize() >= 128 &&
1537 MaxAlign < 16)
1538 MaxAlign = Align(16);
1539 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1540 Align EltAlign;
1541 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1542 if (EltAlign > MaxAlign)
1543 MaxAlign = EltAlign;
1544 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1545 for (auto *EltTy : STy->elements()) {
1546 Align EltAlign;
1547 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1548 if (EltAlign > MaxAlign)
1549 MaxAlign = EltAlign;
1550 if (MaxAlign == MaxMaxAlign)
1551 break;
1552 }
1553 }
1554}
1555
1556/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1557/// function arguments in the caller parameter area.
1558unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1559 const DataLayout &DL) const {
1560 // 16byte and wider vectors are passed on 16byte boundary.
1561 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1562 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1563 if (Subtarget.hasAltivec())
1564 getMaxByValAlign(Ty, Alignment, Align(16));
1565 return Alignment.value();
1566}
1567
1568bool PPCTargetLowering::useSoftFloat() const {
1569 return Subtarget.useSoftFloat();
1570}
1571
1572bool PPCTargetLowering::hasSPE() const {
1573 return Subtarget.hasSPE();
1574}
1575
1576bool PPCTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
1577 return VT.isScalarInteger();
1578}
1579
1580const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1581 switch ((PPCISD::NodeType)Opcode) {
1582 case PPCISD::FIRST_NUMBER: break;
1583 case PPCISD::FSEL: return "PPCISD::FSEL";
1584 case PPCISD::XSMAXCDP: return "PPCISD::XSMAXCDP";
1585 case PPCISD::XSMINCDP: return "PPCISD::XSMINCDP";
1586 case PPCISD::FCFID: return "PPCISD::FCFID";
1587 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1588 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1589 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1590 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1591 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1592 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1593 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1594 case PPCISD::FP_TO_UINT_IN_VSR:
1595 return "PPCISD::FP_TO_UINT_IN_VSR,";
1596 case PPCISD::FP_TO_SINT_IN_VSR:
1597 return "PPCISD::FP_TO_SINT_IN_VSR";
1598 case PPCISD::FRE: return "PPCISD::FRE";
1599 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1600 case PPCISD::FTSQRT:
1601 return "PPCISD::FTSQRT";
1602 case PPCISD::FSQRT:
1603 return "PPCISD::FSQRT";
1604 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1605 case PPCISD::VPERM: return "PPCISD::VPERM";
1606 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1607 case PPCISD::XXSPLTI_SP_TO_DP:
1608 return "PPCISD::XXSPLTI_SP_TO_DP";
1609 case PPCISD::XXSPLTI32DX:
1610 return "PPCISD::XXSPLTI32DX";
1611 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1612 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1613 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1614 case PPCISD::CMPB: return "PPCISD::CMPB";
1615 case PPCISD::Hi: return "PPCISD::Hi";
1616 case PPCISD::Lo: return "PPCISD::Lo";
1617 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1618 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1619 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1620 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1621 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1622 case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
1623 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1624 case PPCISD::SRL: return "PPCISD::SRL";
1625 case PPCISD::SRA: return "PPCISD::SRA";
1626 case PPCISD::SHL: return "PPCISD::SHL";
1627 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1628 case PPCISD::CALL: return "PPCISD::CALL";
1629 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1630 case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
1631 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1632 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1633 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1634 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1635 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1636 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1637 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1638 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1639 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1640 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1641 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1642 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1643 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1644 case PPCISD::SCALAR_TO_VECTOR_PERMUTED:
1645 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1646 case PPCISD::ANDI_rec_1_EQ_BIT:
1647 return "PPCISD::ANDI_rec_1_EQ_BIT";
1648 case PPCISD::ANDI_rec_1_GT_BIT:
1649 return "PPCISD::ANDI_rec_1_GT_BIT";
1650 case PPCISD::VCMP: return "PPCISD::VCMP";
1651 case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
1652 case PPCISD::LBRX: return "PPCISD::LBRX";
1653 case PPCISD::STBRX: return "PPCISD::STBRX";
1654 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1655 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1656 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1657 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1658 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1659 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1660 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1661 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1662 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1663 case PPCISD::ST_VSR_SCAL_INT:
1664 return "PPCISD::ST_VSR_SCAL_INT";
1665 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1666 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1667 case PPCISD::BDZ: return "PPCISD::BDZ";
1668 case PPCISD::MFFS: return "PPCISD::MFFS";
1669 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1670 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1671 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1672 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1673 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1674 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1675 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1676 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1677 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1678 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1679 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1680 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1681 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1682 case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX";
1683 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1684 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1685 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1686 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1687 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1688 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1689 case PPCISD::PADDI_DTPREL:
1690 return "PPCISD::PADDI_DTPREL";
1691 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1692 case PPCISD::SC: return "PPCISD::SC";
1693 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1694 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1695 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1696 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1697 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1698 case PPCISD::VABSD: return "PPCISD::VABSD";
1699 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1700 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1701 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1702 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1703 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1704 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1705 case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
1706 case PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR:
1707 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1708 case PPCISD::TLS_LOCAL_EXEC_MAT_ADDR:
1709 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1710 case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
1711 case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
1712 case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
1713 case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
1714 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1715 case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1716 case PPCISD::STRICT_FADDRTZ:
1717 return "PPCISD::STRICT_FADDRTZ";
1718 case PPCISD::STRICT_FCTIDZ:
1719 return "PPCISD::STRICT_FCTIDZ";
1720 case PPCISD::STRICT_FCTIWZ:
1721 return "PPCISD::STRICT_FCTIWZ";
1722 case PPCISD::STRICT_FCTIDUZ:
1723 return "PPCISD::STRICT_FCTIDUZ";
1724 case PPCISD::STRICT_FCTIWUZ:
1725 return "PPCISD::STRICT_FCTIWUZ";
1726 case PPCISD::STRICT_FCFID:
1727 return "PPCISD::STRICT_FCFID";
1728 case PPCISD::STRICT_FCFIDU:
1729 return "PPCISD::STRICT_FCFIDU";
1730 case PPCISD::STRICT_FCFIDS:
1731 return "PPCISD::STRICT_FCFIDS";
1732 case PPCISD::STRICT_FCFIDUS:
1733 return "PPCISD::STRICT_FCFIDUS";
1734 case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
1735 }
1736 return nullptr;
1737}
1738
1739EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1740 EVT VT) const {
1741 if (!VT.isVector())
1742 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1743
1744 return VT.changeVectorElementTypeToInteger();
1745}
1746
1747bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1748 assert(VT.isFloatingPoint() && "Non-floating-point FMA?")(static_cast <bool> (VT.isFloatingPoint() && "Non-floating-point FMA?"
) ? void (0) : __assert_fail ("VT.isFloatingPoint() && \"Non-floating-point FMA?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1748, __extension__ __PRETTY_FUNCTION__))
;
1749 return true;
1750}
1751
1752//===----------------------------------------------------------------------===//
1753// Node matching predicates, for use by the tblgen matching code.
1754//===----------------------------------------------------------------------===//
1755
1756/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1757static bool isFloatingPointZero(SDValue Op) {
1758 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1759 return CFP->getValueAPF().isZero();
1760 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1761 // Maybe this has already been legalized into the constant pool?
1762 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1763 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1764 return CFP->getValueAPF().isZero();
1765 }
1766 return false;
1767}
1768
1769/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1770/// true if Op is undef or if it matches the specified value.
1771static bool isConstantOrUndef(int Op, int Val) {
1772 return Op < 0 || Op == Val;
1773}
1774
1775/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1776/// VPKUHUM instruction.
1777/// The ShuffleKind distinguishes between big-endian operations with
1778/// two different inputs (0), either-endian operations with two identical
1779/// inputs (1), and little-endian operations with two different inputs (2).
1780/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1781bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1782 SelectionDAG &DAG) {
1783 bool IsLE = DAG.getDataLayout().isLittleEndian();
1784 if (ShuffleKind == 0) {
1785 if (IsLE)
1786 return false;
1787 for (unsigned i = 0; i != 16; ++i)
1788 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1789 return false;
1790 } else if (ShuffleKind == 2) {
1791 if (!IsLE)
1792 return false;
1793 for (unsigned i = 0; i != 16; ++i)
1794 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1795 return false;
1796 } else if (ShuffleKind == 1) {
1797 unsigned j = IsLE ? 0 : 1;
1798 for (unsigned i = 0; i != 8; ++i)
1799 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1800 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1801 return false;
1802 }
1803 return true;
1804}
1805
1806/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1807/// VPKUWUM instruction.
1808/// The ShuffleKind distinguishes between big-endian operations with
1809/// two different inputs (0), either-endian operations with two identical
1810/// inputs (1), and little-endian operations with two different inputs (2).
1811/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1812bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1813 SelectionDAG &DAG) {
1814 bool IsLE = DAG.getDataLayout().isLittleEndian();
1815 if (ShuffleKind == 0) {
1816 if (IsLE)
1817 return false;
1818 for (unsigned i = 0; i != 16; i += 2)
1819 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1820 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1821 return false;
1822 } else if (ShuffleKind == 2) {
1823 if (!IsLE)
1824 return false;
1825 for (unsigned i = 0; i != 16; i += 2)
1826 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1827 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1828 return false;
1829 } else if (ShuffleKind == 1) {
1830 unsigned j = IsLE ? 0 : 2;
1831 for (unsigned i = 0; i != 8; i += 2)
1832 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1833 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1834 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1835 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1836 return false;
1837 }
1838 return true;
1839}
1840
1841/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1842/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1843/// current subtarget.
1844///
1845/// The ShuffleKind distinguishes between big-endian operations with
1846/// two different inputs (0), either-endian operations with two identical
1847/// inputs (1), and little-endian operations with two different inputs (2).
1848/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1849bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1850 SelectionDAG &DAG) {
1851 const PPCSubtarget& Subtarget =
1852 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1853 if (!Subtarget.hasP8Vector())
1854 return false;
1855
1856 bool IsLE = DAG.getDataLayout().isLittleEndian();
1857 if (ShuffleKind == 0) {
1858 if (IsLE)
1859 return false;
1860 for (unsigned i = 0; i != 16; i += 4)
1861 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1862 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1863 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1864 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1865 return false;
1866 } else if (ShuffleKind == 2) {
1867 if (!IsLE)
1868 return false;
1869 for (unsigned i = 0; i != 16; i += 4)
1870 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1871 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1872 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1873 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1874 return false;
1875 } else if (ShuffleKind == 1) {
1876 unsigned j = IsLE ? 0 : 4;
1877 for (unsigned i = 0; i != 8; i += 4)
1878 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1879 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1880 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1881 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1882 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1883 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1884 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1885 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1886 return false;
1887 }
1888 return true;
1889}
1890
1891/// isVMerge - Common function, used to match vmrg* shuffles.
1892///
1893static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1894 unsigned LHSStart, unsigned RHSStart) {
1895 if (N->getValueType(0) != MVT::v16i8)
1896 return false;
1897 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&(static_cast <bool> ((UnitSize == 1 || UnitSize == 2 ||
UnitSize == 4) && "Unsupported merge size!") ? void (
0) : __assert_fail ("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1898, __extension__ __PRETTY_FUNCTION__))
1898 "Unsupported merge size!")(static_cast <bool> ((UnitSize == 1 || UnitSize == 2 ||
UnitSize == 4) && "Unsupported merge size!") ? void (
0) : __assert_fail ("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1898, __extension__ __PRETTY_FUNCTION__))
;
1899
1900 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1901 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1902 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1903 LHSStart+j+i*UnitSize) ||
1904 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1905 RHSStart+j+i*UnitSize))
1906 return false;
1907 }
1908 return true;
1909}
1910
1911/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1912/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1913/// The ShuffleKind distinguishes between big-endian merges with two
1914/// different inputs (0), either-endian merges with two identical inputs (1),
1915/// and little-endian merges with two different inputs (2). For the latter,
1916/// the input operands are swapped (see PPCInstrAltivec.td).
1917bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1918 unsigned ShuffleKind, SelectionDAG &DAG) {
1919 if (DAG.getDataLayout().isLittleEndian()) {
1920 if (ShuffleKind == 1) // unary
1921 return isVMerge(N, UnitSize, 0, 0);
1922 else if (ShuffleKind == 2) // swapped
1923 return isVMerge(N, UnitSize, 0, 16);
1924 else
1925 return false;
1926 } else {
1927 if (ShuffleKind == 1) // unary
1928 return isVMerge(N, UnitSize, 8, 8);
1929 else if (ShuffleKind == 0) // normal
1930 return isVMerge(N, UnitSize, 8, 24);
1931 else
1932 return false;
1933 }
1934}
1935
1936/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1937/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1938/// The ShuffleKind distinguishes between big-endian merges with two
1939/// different inputs (0), either-endian merges with two identical inputs (1),
1940/// and little-endian merges with two different inputs (2). For the latter,
1941/// the input operands are swapped (see PPCInstrAltivec.td).
1942bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1943 unsigned ShuffleKind, SelectionDAG &DAG) {
1944 if (DAG.getDataLayout().isLittleEndian()) {
1945 if (ShuffleKind == 1) // unary
1946 return isVMerge(N, UnitSize, 8, 8);
1947 else if (ShuffleKind == 2) // swapped
1948 return isVMerge(N, UnitSize, 8, 24);
1949 else
1950 return false;
1951 } else {
1952 if (ShuffleKind == 1) // unary
1953 return isVMerge(N, UnitSize, 0, 0);
1954 else if (ShuffleKind == 0) // normal
1955 return isVMerge(N, UnitSize, 0, 16);
1956 else
1957 return false;
1958 }
1959}
1960
1961/**
1962 * Common function used to match vmrgew and vmrgow shuffles
1963 *
1964 * The indexOffset determines whether to look for even or odd words in
1965 * the shuffle mask. This is based on the of the endianness of the target
1966 * machine.
1967 * - Little Endian:
1968 * - Use offset of 0 to check for odd elements
1969 * - Use offset of 4 to check for even elements
1970 * - Big Endian:
1971 * - Use offset of 0 to check for even elements
1972 * - Use offset of 4 to check for odd elements
1973 * A detailed description of the vector element ordering for little endian and
1974 * big endian can be found at
1975 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1976 * Targeting your applications - what little endian and big endian IBM XL C/C++
1977 * compiler differences mean to you
1978 *
1979 * The mask to the shuffle vector instruction specifies the indices of the
1980 * elements from the two input vectors to place in the result. The elements are
1981 * numbered in array-access order, starting with the first vector. These vectors
1982 * are always of type v16i8, thus each vector will contain 16 elements of size
1983 * 8. More info on the shuffle vector can be found in the
1984 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1985 * Language Reference.
1986 *
1987 * The RHSStartValue indicates whether the same input vectors are used (unary)
1988 * or two different input vectors are used, based on the following:
1989 * - If the instruction uses the same vector for both inputs, the range of the
1990 * indices will be 0 to 15. In this case, the RHSStart value passed should
1991 * be 0.
1992 * - If the instruction has two different vectors then the range of the
1993 * indices will be 0 to 31. In this case, the RHSStart value passed should
1994 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1995 * to 31 specify elements in the second vector).
1996 *
1997 * \param[in] N The shuffle vector SD Node to analyze
1998 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1999 * \param[in] RHSStartValue Specifies the starting index for the righthand input
2000 * vector to the shuffle_vector instruction
2001 * \return true iff this shuffle vector represents an even or odd word merge
2002 */
2003static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
2004 unsigned RHSStartValue) {
2005 if (N->getValueType(0) != MVT::v16i8)
2006 return false;
2007
2008 for (unsigned i = 0; i < 2; ++i)
2009 for (unsigned j = 0; j < 4; ++j)
2010 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
2011 i*RHSStartValue+j+IndexOffset) ||
2012 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
2013 i*RHSStartValue+j+IndexOffset+8))
2014 return false;
2015 return true;
2016}
2017
2018/**
2019 * Determine if the specified shuffle mask is suitable for the vmrgew or
2020 * vmrgow instructions.
2021 *
2022 * \param[in] N The shuffle vector SD Node to analyze
2023 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
2024 * \param[in] ShuffleKind Identify the type of merge:
2025 * - 0 = big-endian merge with two different inputs;
2026 * - 1 = either-endian merge with two identical inputs;
2027 * - 2 = little-endian merge with two different inputs (inputs are swapped for
2028 * little-endian merges).
2029 * \param[in] DAG The current SelectionDAG
2030 * \return true iff this shuffle mask
2031 */
2032bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
2033 unsigned ShuffleKind, SelectionDAG &DAG) {
2034 if (DAG.getDataLayout().isLittleEndian()) {
2035 unsigned indexOffset = CheckEven ? 4 : 0;
2036 if (ShuffleKind == 1) // Unary
2037 return isVMerge(N, indexOffset, 0);
2038 else if (ShuffleKind == 2) // swapped
2039 return isVMerge(N, indexOffset, 16);
2040 else
2041 return false;
2042 }
2043 else {
2044 unsigned indexOffset = CheckEven ? 0 : 4;
2045 if (ShuffleKind == 1) // Unary
2046 return isVMerge(N, indexOffset, 0);
2047 else if (ShuffleKind == 0) // Normal
2048 return isVMerge(N, indexOffset, 16);
2049 else
2050 return false;
2051 }
2052 return false;
2053}
2054
2055/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
2056/// amount, otherwise return -1.
2057/// The ShuffleKind distinguishes between big-endian operations with two
2058/// different inputs (0), either-endian operations with two identical inputs
2059/// (1), and little-endian operations with two different inputs (2). For the
2060/// latter, the input operands are swapped (see PPCInstrAltivec.td).
2061int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
2062 SelectionDAG &DAG) {
2063 if (N->getValueType(0) != MVT::v16i8)
2064 return -1;
2065
2066 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2067
2068 // Find the first non-undef value in the shuffle mask.
2069 unsigned i;
2070 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
2071 /*search*/;
2072
2073 if (i == 16) return -1; // all undef.
2074
2075 // Otherwise, check to see if the rest of the elements are consecutively
2076 // numbered from this value.
2077 unsigned ShiftAmt = SVOp->getMaskElt(i);
2078 if (ShiftAmt < i) return -1;
2079
2080 ShiftAmt -= i;
2081 bool isLE = DAG.getDataLayout().isLittleEndian();
2082
2083 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
2084 // Check the rest of the elements to see if they are consecutive.
2085 for (++i; i != 16; ++i)
2086 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2087 return -1;
2088 } else if (ShuffleKind == 1) {
2089 // Check the rest of the elements to see if they are consecutive.
2090 for (++i; i != 16; ++i)
2091 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
2092 return -1;
2093 } else
2094 return -1;
2095
2096 if (isLE)
2097 ShiftAmt = 16 - ShiftAmt;
2098
2099 return ShiftAmt;
2100}
2101
2102/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
2103/// specifies a splat of a single element that is suitable for input to
2104/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
2105bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
2106 assert(N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) &&(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& isPowerOf2_32(EltSize) && EltSize <= 8
&& "Can only handle 1,2,4,8 byte element sizes") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2107, __extension__ __PRETTY_FUNCTION__))
2107 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& isPowerOf2_32(EltSize) && EltSize <= 8
&& "Can only handle 1,2,4,8 byte element sizes") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2107, __extension__ __PRETTY_FUNCTION__))
;
2108
2109 // The consecutive indices need to specify an element, not part of two
2110 // different elements. So abandon ship early if this isn't the case.
2111 if (N->getMaskElt(0) % EltSize != 0)
2112 return false;
2113
2114 // This is a splat operation if each element of the permute is the same, and
2115 // if the value doesn't reference the second vector.
2116 unsigned ElementBase = N->getMaskElt(0);
2117
2118 // FIXME: Handle UNDEF elements too!
2119 if (ElementBase >= 16)
2120 return false;
2121
2122 // Check that the indices are consecutive, in the case of a multi-byte element
2123 // splatted with a v16i8 mask.
2124 for (unsigned i = 1; i != EltSize; ++i)
2125 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
2126 return false;
2127
2128 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
2129 if (N->getMaskElt(i) < 0) continue;
2130 for (unsigned j = 0; j != EltSize; ++j)
2131 if (N->getMaskElt(i+j) != N->getMaskElt(j))
2132 return false;
2133 }
2134 return true;
2135}
2136
2137/// Check that the mask is shuffling N byte elements. Within each N byte
2138/// element of the mask, the indices could be either in increasing or
2139/// decreasing order as long as they are consecutive.
2140/// \param[in] N the shuffle vector SD Node to analyze
2141/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
2142/// Word/DoubleWord/QuadWord).
2143/// \param[in] StepLen the delta indices number among the N byte element, if
2144/// the mask is in increasing/decreasing order then it is 1/-1.
2145/// \return true iff the mask is shuffling N byte elements.
2146static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
2147 int StepLen) {
2148 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&(static_cast <bool> ((Width == 2 || Width == 4 || Width
== 8 || Width == 16) && "Unexpected element width.")
? void (0) : __assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2149, __extension__ __PRETTY_FUNCTION__))
2149 "Unexpected element width.")(static_cast <bool> ((Width == 2 || Width == 4 || Width
== 8 || Width == 16) && "Unexpected element width.")
? void (0) : __assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2149, __extension__ __PRETTY_FUNCTION__))
;
2150 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.")(static_cast <bool> ((StepLen == 1 || StepLen == -1) &&
"Unexpected element width.") ? void (0) : __assert_fail ("(StepLen == 1 || StepLen == -1) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2150, __extension__ __PRETTY_FUNCTION__))
;
2151
2152 unsigned NumOfElem = 16 / Width;
2153 unsigned MaskVal[16]; // Width is never greater than 16
2154 for (unsigned i = 0; i < NumOfElem; ++i) {
2155 MaskVal[0] = N->getMaskElt(i * Width);
2156 if ((StepLen == 1) && (MaskVal[0] % Width)) {
2157 return false;
2158 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
2159 return false;
2160 }
2161
2162 for (unsigned int j = 1; j < Width; ++j) {
2163 MaskVal[j] = N->getMaskElt(i * Width + j);
2164 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
2165 return false;
2166 }
2167 }
2168 }
2169
2170 return true;
2171}
2172
2173bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2174 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
2175 if (!isNByteElemShuffleMask(N, 4, 1))
2176 return false;
2177
2178 // Now we look at mask elements 0,4,8,12
2179 unsigned M0 = N->getMaskElt(0) / 4;
2180 unsigned M1 = N->getMaskElt(4) / 4;
2181 unsigned M2 = N->getMaskElt(8) / 4;
2182 unsigned M3 = N->getMaskElt(12) / 4;
2183 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
2184 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
2185
2186 // Below, let H and L be arbitrary elements of the shuffle mask
2187 // where H is in the range [4,7] and L is in the range [0,3].
2188 // H, 1, 2, 3 or L, 5, 6, 7
2189 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
2190 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
2191 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2192 InsertAtByte = IsLE ? 12 : 0;
2193 Swap = M0 < 4;
2194 return true;
2195 }
2196 // 0, H, 2, 3 or 4, L, 6, 7
2197 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
2198 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
2199 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2200 InsertAtByte = IsLE ? 8 : 4;
2201 Swap = M1 < 4;
2202 return true;
2203 }
2204 // 0, 1, H, 3 or 4, 5, L, 7
2205 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
2206 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
2207 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2208 InsertAtByte = IsLE ? 4 : 8;
2209 Swap = M2 < 4;
2210 return true;
2211 }
2212 // 0, 1, 2, H or 4, 5, 6, L
2213 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
2214 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
2215 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2216 InsertAtByte = IsLE ? 0 : 12;
2217 Swap = M3 < 4;
2218 return true;
2219 }
2220
2221 // If both vector operands for the shuffle are the same vector, the mask will
2222 // contain only elements from the first one and the second one will be undef.
2223 if (N->getOperand(1).isUndef()) {
2224 ShiftElts = 0;
2225 Swap = true;
2226 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2227 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
2228 InsertAtByte = IsLE ? 12 : 0;
2229 return true;
2230 }
2231 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2232 InsertAtByte = IsLE ? 8 : 4;
2233 return true;
2234 }
2235 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2236 InsertAtByte = IsLE ? 4 : 8;
2237 return true;
2238 }
2239 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2240 InsertAtByte = IsLE ? 0 : 12;
2241 return true;
2242 }
2243 }
2244
2245 return false;
2246}
2247
2248bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2249 bool &Swap, bool IsLE) {
2250 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2250, __extension__ __PRETTY_FUNCTION__))
;
22
'?' condition is true
2251 // Ensure each byte index of the word is consecutive.
2252 if (!isNByteElemShuffleMask(N, 4, 1))
23
Assuming the condition is false
24
Taking false branch
2253 return false;
2254
2255 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
2256 unsigned M0 = N->getMaskElt(0) / 4;
2257 unsigned M1 = N->getMaskElt(4) / 4;
2258 unsigned M2 = N->getMaskElt(8) / 4;
2259 unsigned M3 = N->getMaskElt(12) / 4;
2260
2261 // If both vector operands for the shuffle are the same vector, the mask will
2262 // contain only elements from the first one and the second one will be undef.
2263 if (N->getOperand(1).isUndef()) {
25
Calling 'SDValue::isUndef'
31
Returning from 'SDValue::isUndef'
2264 assert(M0 < 4 && "Indexing into an undef vector?")(static_cast <bool> (M0 < 4 && "Indexing into an undef vector?"
) ? void (0) : __assert_fail ("M0 < 4 && \"Indexing into an undef vector?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2264, __extension__ __PRETTY_FUNCTION__))
;
2265 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2266 return false;
2267
2268 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2269 Swap = false;
2270 return true;
2271 }
2272
2273 // Ensure each word index of the ShuffleVector Mask is consecutive.
2274 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
32
Assuming the condition is false
33
Assuming the condition is false
34
Assuming the condition is false
35
Taking false branch
2275 return false;
2276
2277 if (IsLE) {
36
Assuming 'IsLE' is false
2278 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2279 // Input vectors don't need to be swapped if the leading element
2280 // of the result is one of the 3 left elements of the second vector
2281 // (or if there is no shift to be done at all).
2282 Swap = false;
2283 ShiftElts = (8 - M0) % 8;
2284 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2285 // Input vectors need to be swapped if the leading element
2286 // of the result is one of the 3 left elements of the first vector
2287 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2288 Swap = true;
2289 ShiftElts = (4 - M0) % 4;
2290 }
2291
2292 return true;
2293 } else { // BE
2294 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
37
Assuming 'M0' is not equal to 0
38
Assuming 'M0' is not equal to 1
39
Assuming 'M0' is not equal to 2
40
Assuming 'M0' is not equal to 3
2295 // Input vectors don't need to be swapped if the leading element
2296 // of the result is one of the 4 elements of the first vector.
2297 Swap = false;
2298 ShiftElts = M0;
2299 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
41
Assuming 'M0' is not equal to 4
42
Assuming 'M0' is not equal to 5
43
Assuming 'M0' is not equal to 6
44
Assuming 'M0' is not equal to 7
45
Taking false branch
2300 // Input vectors need to be swapped if the leading element
2301 // of the result is one of the 4 elements of the right vector.
2302 Swap = true;
2303 ShiftElts = M0 - 4;
2304 }
2305
2306 return true;
46
Returning without writing to 'ShiftElts'
47
Returning the value 1, which participates in a condition later
2307 }
2308}
2309
2310bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
2311 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2311, __extension__ __PRETTY_FUNCTION__))
;
2312
2313 if (!isNByteElemShuffleMask(N, Width, -1))
2314 return false;
2315
2316 for (int i = 0; i < 16; i += Width)
2317 if (N->getMaskElt(i) != i + Width - 1)
2318 return false;
2319
2320 return true;
2321}
2322
2323bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
2324 return isXXBRShuffleMaskHelper(N, 2);
2325}
2326
2327bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
2328 return isXXBRShuffleMaskHelper(N, 4);
2329}
2330
2331bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
2332 return isXXBRShuffleMaskHelper(N, 8);
2333}
2334
2335bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
2336 return isXXBRShuffleMaskHelper(N, 16);
2337}
2338
2339/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2340/// if the inputs to the instruction should be swapped and set \p DM to the
2341/// value for the immediate.
2342/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2343/// AND element 0 of the result comes from the first input (LE) or second input
2344/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2345/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2346/// mask.
2347bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
2348 bool &Swap, bool IsLE) {
2349 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2349, __extension__ __PRETTY_FUNCTION__))
;
2350
2351 // Ensure each byte index of the double word is consecutive.
2352 if (!isNByteElemShuffleMask(N, 8, 1))
2353 return false;
2354
2355 unsigned M0 = N->getMaskElt(0) / 8;
2356 unsigned M1 = N->getMaskElt(8) / 8;
2357 assert(((M0 | M1) < 4) && "A mask element out of bounds?")(static_cast <bool> (((M0 | M1) < 4) && "A mask element out of bounds?"
) ? void (0) : __assert_fail ("((M0 | M1) < 4) && \"A mask element out of bounds?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2357, __extension__ __PRETTY_FUNCTION__))
;
2358
2359 // If both vector operands for the shuffle are the same vector, the mask will
2360 // contain only elements from the first one and the second one will be undef.
2361 if (N->getOperand(1).isUndef()) {
2362 if ((M0 | M1) < 2) {
2363 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2364 Swap = false;
2365 return true;
2366 } else
2367 return false;
2368 }
2369
2370 if (IsLE) {
2371 if (M0 > 1 && M1 < 2) {
2372 Swap = false;
2373 } else if (M0 < 2 && M1 > 1) {
2374 M0 = (M0 + 2) % 4;
2375 M1 = (M1 + 2) % 4;
2376 Swap = true;
2377 } else
2378 return false;
2379
2380 // Note: if control flow comes here that means Swap is already set above
2381 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2382 return true;
2383 } else { // BE
2384 if (M0 < 2 && M1 > 1) {
2385 Swap = false;
2386 } else if (M0 > 1 && M1 < 2) {
2387 M0 = (M0 + 2) % 4;
2388 M1 = (M1 + 2) % 4;
2389 Swap = true;
2390 } else
2391 return false;
2392
2393 // Note: if control flow comes here that means Swap is already set above
2394 DM = (M0 << 1) + (M1 & 1);
2395 return true;
2396 }
2397}
2398
2399
2400/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2401/// appropriate for PPC mnemonics (which have a big endian bias - namely
2402/// elements are counted from the left of the vector register).
2403unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2404 SelectionDAG &DAG) {
2405 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2406 assert(isSplatShuffleMask(SVOp, EltSize))(static_cast <bool> (isSplatShuffleMask(SVOp, EltSize))
? void (0) : __assert_fail ("isSplatShuffleMask(SVOp, EltSize)"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2406, __extension__ __PRETTY_FUNCTION__))
;
2407 if (DAG.getDataLayout().isLittleEndian())
2408 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2409 else
2410 return SVOp->getMaskElt(0) / EltSize;
2411}
2412
2413/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2414/// by using a vspltis[bhw] instruction of the specified element size, return
2415/// the constant being splatted. The ByteSize field indicates the number of
2416/// bytes of each element [124] -> [bhw].
2417SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2418 SDValue OpVal(nullptr, 0);
2419
2420 // If ByteSize of the splat is bigger than the element size of the
2421 // build_vector, then we have a case where we are checking for a splat where
2422 // multiple elements of the buildvector are folded together into a single
2423 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2424 unsigned EltSize = 16/N->getNumOperands();
2425 if (EltSize < ByteSize) {
2426 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2427 SDValue UniquedVals[4];
2428 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?")(static_cast <bool> (Multiple > 1 && Multiple
<= 4 && "How can this happen?") ? void (0) : __assert_fail
("Multiple > 1 && Multiple <= 4 && \"How can this happen?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2428, __extension__ __PRETTY_FUNCTION__))
;
2429
2430 // See if all of the elements in the buildvector agree across.
2431 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2432 if (N->getOperand(i).isUndef()) continue;
2433 // If the element isn't a constant, bail fully out.
2434 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2435
2436 if (!UniquedVals[i&(Multiple-1)].getNode())
2437 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2438 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2439 return SDValue(); // no match.
2440 }
2441
2442 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2443 // either constant or undef values that are identical for each chunk. See
2444 // if these chunks can form into a larger vspltis*.
2445
2446 // Check to see if all of the leading entries are either 0 or -1. If
2447 // neither, then this won't fit into the immediate field.
2448 bool LeadingZero = true;
2449 bool LeadingOnes = true;
2450 for (unsigned i = 0; i != Multiple-1; ++i) {
2451 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2452
2453 LeadingZero &= isNullConstant(UniquedVals[i]);
2454 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2455 }
2456 // Finally, check the least significant entry.
2457 if (LeadingZero) {
2458 if (!UniquedVals[Multiple-1].getNode())
2459 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2460 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2461 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2462 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2463 }
2464 if (LeadingOnes) {
2465 if (!UniquedVals[Multiple-1].getNode())
2466 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2467 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2468 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2469 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2470 }
2471
2472 return SDValue();
2473 }
2474
2475 // Check to see if this buildvec has a single non-undef value in its elements.
2476 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2477 if (N->getOperand(i).isUndef()) continue;
2478 if (!OpVal.getNode())
2479 OpVal = N->getOperand(i);
2480 else if (OpVal != N->getOperand(i))
2481 return SDValue();
2482 }
2483
2484 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2485
2486 unsigned ValSizeInBytes = EltSize;
2487 uint64_t Value = 0;
2488 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2489 Value = CN->getZExtValue();
2490 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2491 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!")(static_cast <bool> (CN->getValueType(0) == MVT::f32
&& "Only one legal FP vector type!") ? void (0) : __assert_fail
("CN->getValueType(0) == MVT::f32 && \"Only one legal FP vector type!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2491, __extension__ __PRETTY_FUNCTION__))
;
2492 Value = FloatToBits(CN->getValueAPF().convertToFloat());
2493 }
2494
2495 // If the splat value is larger than the element value, then we can never do
2496 // this splat. The only case that we could fit the replicated bits into our
2497 // immediate field for would be zero, and we prefer to use vxor for it.
2498 if (ValSizeInBytes < ByteSize) return SDValue();
2499
2500 // If the element value is larger than the splat value, check if it consists
2501 // of a repeated bit pattern of size ByteSize.
2502 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2503 return SDValue();
2504
2505 // Properly sign extend the value.
2506 int MaskVal = SignExtend32(Value, ByteSize * 8);
2507
2508 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2509 if (MaskVal == 0) return SDValue();
2510
2511 // Finally, if this value fits in a 5 bit sext field, return it
2512 if (SignExtend32<5>(MaskVal) == MaskVal)
2513 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2514 return SDValue();
2515}
2516
2517//===----------------------------------------------------------------------===//
2518// Addressing Mode Selection
2519//===----------------------------------------------------------------------===//
2520
2521/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2522/// or 64-bit immediate, and if the value can be accurately represented as a
2523/// sign extension from a 16-bit value. If so, this returns true and the
2524/// immediate.
2525bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2526 if (!isa<ConstantSDNode>(N))
2527 return false;
2528
2529 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2530 if (N->getValueType(0) == MVT::i32)
2531 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2532 else
2533 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2534}
2535bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2536 return isIntS16Immediate(Op.getNode(), Imm);
2537}
2538
2539/// Used when computing address flags for selecting loads and stores.
2540/// If we have an OR, check if the LHS and RHS are provably disjoint.
2541/// An OR of two provably disjoint values is equivalent to an ADD.
2542/// Most PPC load/store instructions compute the effective address as a sum,
2543/// so doing this conversion is useful.
2544static bool provablyDisjointOr(SelectionDAG &DAG, const SDValue &N) {
2545 if (N.getOpcode() != ISD::OR)
2546 return false;
2547 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2548 if (!LHSKnown.Zero.getBoolValue())
2549 return false;
2550 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2551 return (~(LHSKnown.Zero | RHSKnown.Zero) == 0);
2552}
2553
2554/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2555/// be represented as an indexed [r+r] operation.
2556bool PPCTargetLowering::SelectAddressEVXRegReg(SDValue N, SDValue &Base,
2557 SDValue &Index,
2558 SelectionDAG &DAG) const {
2559 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
2560 UI != E; ++UI) {
2561 if (MemSDNode *Memop = dyn_cast<MemSDNode>(*UI)) {
2562 if (Memop->getMemoryVT() == MVT::f64) {
2563 Base = N.getOperand(0);
2564 Index = N.getOperand(1);
2565 return true;
2566 }
2567 }
2568 }
2569 return false;
2570}
2571
2572/// isIntS34Immediate - This method tests if value of node given can be
2573/// accurately represented as a sign extension from a 34-bit value. If so,
2574/// this returns true and the immediate.
2575bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2576 if (!isa<ConstantSDNode>(N))
2577 return false;
2578
2579 Imm = (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2580 return isInt<34>(Imm);
2581}
2582bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) {
2583 return isIntS34Immediate(Op.getNode(), Imm);
2584}
2585
2586/// SelectAddressRegReg - Given the specified addressed, check to see if it
2587/// can be represented as an indexed [r+r] operation. Returns false if it
2588/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2589/// non-zero and N can be represented by a base register plus a signed 16-bit
2590/// displacement, make a more precise judgement by checking (displacement % \p
2591/// EncodingAlignment).
2592bool PPCTargetLowering::SelectAddressRegReg(
2593 SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG,
2594 MaybeAlign EncodingAlignment) const {
2595 // If we have a PC Relative target flag don't select as [reg+reg]. It will be
2596 // a [pc+imm].
2597 if (SelectAddressPCRel(N, Base))
2598 return false;
2599
2600 int16_t Imm = 0;
2601 if (N.getOpcode() == ISD::ADD) {
2602 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2603 // SPE load/store can only handle 8-bit offsets.
2604 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2605 return true;
2606 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2607 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2608 return false; // r+i
2609 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2610 return false; // r+i
2611
2612 Base = N.getOperand(0);
2613 Index = N.getOperand(1);
2614 return true;
2615 } else if (N.getOpcode() == ISD::OR) {
2616 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2617 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2618 return false; // r+i can fold it if we can.
2619
2620 // If this is an or of disjoint bitfields, we can codegen this as an add
2621 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2622 // disjoint.
2623 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2624
2625 if (LHSKnown.Zero.getBoolValue()) {
2626 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2627 // If all of the bits are known zero on the LHS or RHS, the add won't
2628 // carry.
2629 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2630 Base = N.getOperand(0);
2631 Index = N.getOperand(1);
2632 return true;
2633 }
2634 }
2635 }
2636
2637 return false;
2638}
2639
2640// If we happen to be doing an i64 load or store into a stack slot that has
2641// less than a 4-byte alignment, then the frame-index elimination may need to
2642// use an indexed load or store instruction (because the offset may not be a
2643// multiple of 4). The extra register needed to hold the offset comes from the
2644// register scavenger, and it is possible that the scavenger will need to use
2645// an emergency spill slot. As a result, we need to make sure that a spill slot
2646// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2647// stack slot.
2648static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2649 // FIXME: This does not handle the LWA case.
2650 if (VT != MVT::i64)
2651 return;
2652
2653 // NOTE: We'll exclude negative FIs here, which come from argument
2654 // lowering, because there are no known test cases triggering this problem
2655 // using packed structures (or similar). We can remove this exclusion if
2656 // we find such a test case. The reason why this is so test-case driven is
2657 // because this entire 'fixup' is only to prevent crashes (from the
2658 // register scavenger) on not-really-valid inputs. For example, if we have:
2659 // %a = alloca i1
2660 // %b = bitcast i1* %a to i64*
2661 // store i64* a, i64 b
2662 // then the store should really be marked as 'align 1', but is not. If it
2663 // were marked as 'align 1' then the indexed form would have been
2664 // instruction-selected initially, and the problem this 'fixup' is preventing
2665 // won't happen regardless.
2666 if (FrameIdx < 0)
2667 return;
2668
2669 MachineFunction &MF = DAG.getMachineFunction();
2670 MachineFrameInfo &MFI = MF.getFrameInfo();
2671
2672 if (MFI.getObjectAlign(FrameIdx) >= Align(4))
2673 return;
2674
2675 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2676 FuncInfo->setHasNonRISpills();
2677}
2678
2679/// Returns true if the address N can be represented by a base register plus
2680/// a signed 16-bit displacement [r+imm], and if it is not better
2681/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2682/// displacements that are multiples of that value.
2683bool PPCTargetLowering::SelectAddressRegImm(
2684 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2685 MaybeAlign EncodingAlignment) const {
2686 // FIXME dl should come from parent load or store, not from address
2687 SDLoc dl(N);
2688
2689 // If we have a PC Relative target flag don't select as [reg+imm]. It will be
2690 // a [pc+imm].
2691 if (SelectAddressPCRel(N, Base))
2692 return false;
2693
2694 // If this can be more profitably realized as r+r, fail.
2695 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2696 return false;
2697
2698 if (N.getOpcode() == ISD::ADD) {
2699 int16_t imm = 0;
2700 if (isIntS16Immediate(N.getOperand(1), imm) &&
2701 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2702 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2703 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2704 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2705 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2706 } else {
2707 Base = N.getOperand(0);
2708 }
2709 return true; // [r+i]
2710 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2711 // Match LOAD (ADD (X, Lo(G))).
2712 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()(static_cast <bool> (!cast<ConstantSDNode>(N.getOperand
(1).getOperand(1))->getZExtValue() && "Cannot handle constant offsets yet!"
) ? void (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2713, __extension__ __PRETTY_FUNCTION__))
2713 && "Cannot handle constant offsets yet!")(static_cast <bool> (!cast<ConstantSDNode>(N.getOperand
(1).getOperand(1))->getZExtValue() && "Cannot handle constant offsets yet!"
) ? void (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2713, __extension__ __PRETTY_FUNCTION__))
;
2714 Disp = N.getOperand(1).getOperand(0); // The global address.
2715 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2718, __extension__ __PRETTY_FUNCTION__))
2716 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2718, __extension__ __PRETTY_FUNCTION__))
2717 Disp.getOpcode() == ISD::TargetConstantPool ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2718, __extension__ __PRETTY_FUNCTION__))
2718 Disp.getOpcode() == ISD::TargetJumpTable)(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2718, __extension__ __PRETTY_FUNCTION__))
;
2719 Base = N.getOperand(0);
2720 return true; // [&g+r]
2721 }
2722 } else if (N.getOpcode() == ISD::OR) {
2723 int16_t imm = 0;
2724 if (isIntS16Immediate(N.getOperand(1), imm) &&
2725 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2726 // If this is an or of disjoint bitfields, we can codegen this as an add
2727 // (for better address arithmetic) if the LHS and RHS of the OR are
2728 // provably disjoint.
2729 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2730
2731 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2732 // If all of the bits are known zero on the LHS or RHS, the add won't
2733 // carry.
2734 if (FrameIndexSDNode *FI =
2735 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2736 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2737 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2738 } else {
2739 Base = N.getOperand(0);
2740 }
2741 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2742 return true;
2743 }
2744 }
2745 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2746 // Loading from a constant address.
2747
2748 // If this address fits entirely in a 16-bit sext immediate field, codegen
2749 // this as "d, 0"
2750 int16_t Imm;
2751 if (isIntS16Immediate(CN, Imm) &&
2752 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2753 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2754 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2755 CN->getValueType(0));
2756 return true;
2757 }
2758
2759 // Handle 32-bit sext immediates with LIS + addr mode.
2760 if ((CN->getValueType(0) == MVT::i32 ||
2761 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2762 (!EncodingAlignment ||
2763 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2764 int Addr = (int)CN->getZExtValue();
2765
2766 // Otherwise, break this down into an LIS + disp.
2767 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2768
2769 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2770 MVT::i32);
2771 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2772 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2773 return true;
2774 }
2775 }
2776
2777 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2778 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2779 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2780 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2781 } else
2782 Base = N;
2783 return true; // [r+0]
2784}
2785
2786/// Similar to the 16-bit case but for instructions that take a 34-bit
2787/// displacement field (prefixed loads/stores).
2788bool PPCTargetLowering::SelectAddressRegImm34(SDValue N, SDValue &Disp,
2789 SDValue &Base,
2790 SelectionDAG &DAG) const {
2791 // Only on 64-bit targets.
2792 if (N.getValueType() != MVT::i64)
2793 return false;
2794
2795 SDLoc dl(N);
2796 int64_t Imm = 0;
2797
2798 if (N.getOpcode() == ISD::ADD) {
2799 if (!isIntS34Immediate(N.getOperand(1), Imm))
2800 return false;
2801 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2802 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2803 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2804 else
2805 Base = N.getOperand(0);
2806 return true;
2807 }
2808
2809 if (N.getOpcode() == ISD::OR) {
2810 if (!isIntS34Immediate(N.getOperand(1), Imm))
2811 return false;
2812 // If this is an or of disjoint bitfields, we can codegen this as an add
2813 // (for better address arithmetic) if the LHS and RHS of the OR are
2814 // provably disjoint.
2815 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2816 if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)Imm) != ~0ULL)
2817 return false;
2818 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2819 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2820 else
2821 Base = N.getOperand(0);
2822 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2823 return true;
2824 }
2825
2826 if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2827 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2828 Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2829 return true;
2830 }
2831
2832 return false;
2833}
2834
2835/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2836/// represented as an indexed [r+r] operation.
2837bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2838 SDValue &Index,
2839 SelectionDAG &DAG) const {
2840 // Check to see if we can easily represent this as an [r+r] address. This
2841 // will fail if it thinks that the address is more profitably represented as
2842 // reg+imm, e.g. where imm = 0.
2843 if (SelectAddressRegReg(N, Base, Index, DAG))
2844 return true;
2845
2846 // If the address is the result of an add, we will utilize the fact that the
2847 // address calculation includes an implicit add. However, we can reduce
2848 // register pressure if we do not materialize a constant just for use as the
2849 // index register. We only get rid of the add if it is not an add of a
2850 // value and a 16-bit signed constant and both have a single use.
2851 int16_t imm = 0;
2852 if (N.getOpcode() == ISD::ADD &&
2853 (!isIntS16Immediate(N.getOperand(1), imm) ||
2854 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2855 Base = N.getOperand(0);
2856 Index = N.getOperand(1);
2857 return true;
2858 }
2859
2860 // Otherwise, do it the hard way, using R0 as the base register.
2861 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2862 N.getValueType());
2863 Index = N;
2864 return true;
2865}
2866
2867template <typename Ty> static bool isValidPCRelNode(SDValue N) {
2868 Ty *PCRelCand = dyn_cast<Ty>(N);
2869 return PCRelCand && (PCRelCand->getTargetFlags() & PPCII::MO_PCREL_FLAG);
2870}
2871
2872/// Returns true if this address is a PC Relative address.
2873/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
2874/// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
2875bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
2876 // This is a materialize PC Relative node. Always select this as PC Relative.
2877 Base = N;
2878 if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
2879 return true;
2880 if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
2881 isValidPCRelNode<GlobalAddressSDNode>(N) ||
2882 isValidPCRelNode<JumpTableSDNode>(N) ||
2883 isValidPCRelNode<BlockAddressSDNode>(N))
2884 return true;
2885 return false;
2886}
2887
2888/// Returns true if we should use a direct load into vector instruction
2889/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2890static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
2891
2892 // If there are any other uses other than scalar to vector, then we should
2893 // keep it as a scalar load -> direct move pattern to prevent multiple
2894 // loads.
2895 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
2896 if (!LD)
2897 return false;
2898
2899 EVT MemVT = LD->getMemoryVT();
2900 if (!MemVT.isSimple())
2901 return false;
2902 switch(MemVT.getSimpleVT().SimpleTy) {
2903 case MVT::i64:
2904 break;
2905 case MVT::i32:
2906 if (!ST.hasP8Vector())
2907 return false;
2908 break;
2909 case MVT::i16:
2910 case MVT::i8:
2911 if (!ST.hasP9Vector())
2912 return false;
2913 break;
2914 default:
2915 return false;
2916 }
2917
2918 SDValue LoadedVal(N, 0);
2919 if (!LoadedVal.hasOneUse())
2920 return false;
2921
2922 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
2923 UI != UE; ++UI)
2924 if (UI.getUse().get().getResNo() == 0 &&
2925 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &&
2926 UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED)
2927 return false;
2928
2929 return true;
2930}
2931
2932/// getPreIndexedAddressParts - returns true by value, base pointer and
2933/// offset pointer and addressing mode by reference if the node's address
2934/// can be legally represented as pre-indexed load / store address.
2935bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2936 SDValue &Offset,
2937 ISD::MemIndexedMode &AM,
2938 SelectionDAG &DAG) const {
2939 if (DisablePPCPreinc) return false;
2940
2941 bool isLoad = true;
2942 SDValue Ptr;
2943 EVT VT;
2944 unsigned Alignment;
2945 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2946 Ptr = LD->getBasePtr();
2947 VT = LD->getMemoryVT();
2948 Alignment = LD->getAlignment();
2949 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2950 Ptr = ST->getBasePtr();
2951 VT = ST->getMemoryVT();
2952 Alignment = ST->getAlignment();
2953 isLoad = false;
2954 } else
2955 return false;
2956
2957 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
2958 // instructions because we can fold these into a more efficient instruction
2959 // instead, (such as LXSD).
2960 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
2961 return false;
2962 }
2963
2964 // PowerPC doesn't have preinc load/store instructions for vectors
2965 if (VT.isVector())
2966 return false;
2967
2968 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2969 // Common code will reject creating a pre-inc form if the base pointer
2970 // is a frame index, or if N is a store and the base pointer is either
2971 // the same as or a predecessor of the value being stored. Check for
2972 // those situations here, and try with swapped Base/Offset instead.
2973 bool Swap = false;
2974
2975 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2976 Swap = true;
2977 else if (!isLoad) {
2978 SDValue Val = cast<StoreSDNode>(N)->getValue();
2979 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2980 Swap = true;
2981 }
2982
2983 if (Swap)
2984 std::swap(Base, Offset);
2985
2986 AM = ISD::PRE_INC;
2987 return true;
2988 }
2989
2990 // LDU/STU can only handle immediates that are a multiple of 4.
2991 if (VT != MVT::i64) {
2992 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, None))
2993 return false;
2994 } else {
2995 // LDU/STU need an address with at least 4-byte alignment.
2996 if (Alignment < 4)
2997 return false;
2998
2999 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, Align(4)))
3000 return false;
3001 }
3002
3003 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3004 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
3005 // sext i32 to i64 when addr mode is r+i.
3006 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
3007 LD->getExtensionType() == ISD::SEXTLOAD &&
3008 isa<ConstantSDNode>(Offset))
3009 return false;
3010 }
3011
3012 AM = ISD::PRE_INC;
3013 return true;
3014}
3015
3016//===----------------------------------------------------------------------===//
3017// LowerOperation implementation
3018//===----------------------------------------------------------------------===//
3019
3020/// Return true if we should reference labels using a PICBase, set the HiOpFlags
3021/// and LoOpFlags to the target MO flags.
3022static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
3023 unsigned &HiOpFlags, unsigned &LoOpFlags,
3024 const GlobalValue *GV = nullptr) {
3025 HiOpFlags = PPCII::MO_HA;
3026 LoOpFlags = PPCII::MO_LO;
3027
3028 // Don't use the pic base if not in PIC relocation model.
3029 if (IsPIC) {
3030 HiOpFlags |= PPCII::MO_PIC_FLAG;
3031 LoOpFlags |= PPCII::MO_PIC_FLAG;
3032 }
3033}
3034
3035static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
3036 SelectionDAG &DAG) {
3037 SDLoc DL(HiPart);
3038 EVT PtrVT = HiPart.getValueType();
3039 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
3040
3041 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
3042 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
3043
3044 // With PIC, the first instruction is actually "GR+hi(&G)".
3045 if (isPIC)
3046 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
3047 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
3048
3049 // Generate non-pic code that has direct accesses to the constant pool.
3050 // The address of the global is just (hi(&g)+lo(&g)).
3051 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
3052}
3053
3054static void setUsesTOCBasePtr(MachineFunction &MF) {
3055 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3056 FuncInfo->setUsesTOCBasePtr();
3057}
3058
3059static void setUsesTOCBasePtr(SelectionDAG &DAG) {
3060 setUsesTOCBasePtr(DAG.getMachineFunction());
3061}
3062
3063SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
3064 SDValue GA) const {
3065 const bool Is64Bit = Subtarget.isPPC64();
3066 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
3067 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
3068 : Subtarget.isAIXABI()
3069 ? DAG.getRegister(PPC::R2, VT)
3070 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
3071 SDValue Ops[] = { GA, Reg };
3072 return DAG.getMemIntrinsicNode(
3073 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
3074 MachinePointerInfo::getGOT(DAG.getMachineFunction()), None,
3075 MachineMemOperand::MOLoad);
3076}
3077
3078SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
3079 SelectionDAG &DAG) const {
3080 EVT PtrVT = Op.getValueType();
3081 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3082 const Constant *C = CP->getConstVal();
3083
3084 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3085 // The actual address of the GlobalValue is stored in the TOC.
3086 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3087 if (Subtarget.isUsingPCRelativeCalls()) {
3088 SDLoc DL(CP);
3089 EVT Ty = getPointerTy(DAG.getDataLayout());
3090 SDValue ConstPool = DAG.getTargetConstantPool(
3091 C, Ty, CP->getAlign(), CP->getOffset(), PPCII::MO_PCREL_FLAG);
3092 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
3093 }
3094 setUsesTOCBasePtr(DAG);
3095 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
3096 return getTOCEntry(DAG, SDLoc(CP), GA);
3097 }
3098
3099 unsigned MOHiFlag, MOLoFlag;
3100 bool IsPIC = isPositionIndependent();
3101 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3102
3103 if (IsPIC && Subtarget.isSVR4ABI()) {
3104 SDValue GA =
3105 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), PPCII::MO_PIC_FLAG);
3106 return getTOCEntry(DAG, SDLoc(CP), GA);
3107 }
3108
3109 SDValue CPIHi =
3110 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOHiFlag);
3111 SDValue CPILo =
3112 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOLoFlag);
3113 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
3114}
3115
3116// For 64-bit PowerPC, prefer the more compact relative encodings.
3117// This trades 32 bits per jump table entry for one or two instructions
3118// on the jump site.
3119unsigned PPCTargetLowering::getJumpTableEncoding() const {
3120 if (isJumpTableRelative())
3121 return MachineJumpTableInfo::EK_LabelDifference32;
3122
3123 return TargetLowering::getJumpTableEncoding();
3124}
3125
3126bool PPCTargetLowering::isJumpTableRelative() const {
3127 if (UseAbsoluteJumpTables)
3128 return false;
3129 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
3130 return true;
3131 return TargetLowering::isJumpTableRelative();
3132}
3133
3134SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
3135 SelectionDAG &DAG) const {
3136 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3137 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
3138
3139 switch (getTargetMachine().getCodeModel()) {
3140 case CodeModel::Small:
3141 case CodeModel::Medium:
3142 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
3143 default:
3144 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
3145 getPointerTy(DAG.getDataLayout()));
3146 }
3147}
3148
3149const MCExpr *
3150PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
3151 unsigned JTI,
3152 MCContext &Ctx) const {
3153 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3154 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
3155
3156 switch (getTargetMachine().getCodeModel()) {
3157 case CodeModel::Small:
3158 case CodeModel::Medium:
3159 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
3160 default:
3161 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
3162 }
3163}
3164
3165SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
3166 EVT PtrVT = Op.getValueType();
3167 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3168
3169 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3170 if (Subtarget.isUsingPCRelativeCalls()) {
3171 SDLoc DL(JT);
3172 EVT Ty = getPointerTy(DAG.getDataLayout());
3173 SDValue GA =
3174 DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
3175 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3176 return MatAddr;
3177 }
3178
3179 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3180 // The actual address of the GlobalValue is stored in the TOC.
3181 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3182 setUsesTOCBasePtr(DAG);
3183 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3184 return getTOCEntry(DAG, SDLoc(JT), GA);
3185 }
3186
3187 unsigned MOHiFlag, MOLoFlag;
3188 bool IsPIC = isPositionIndependent();
3189 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3190
3191 if (IsPIC && Subtarget.isSVR4ABI()) {
3192 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3193 PPCII::MO_PIC_FLAG);
3194 return getTOCEntry(DAG, SDLoc(GA), GA);
3195 }
3196
3197 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3198 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3199 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
3200}
3201
3202SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3203 SelectionDAG &DAG) const {
3204 EVT PtrVT = Op.getValueType();
3205 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
3206 const BlockAddress *BA = BASDN->getBlockAddress();
3207
3208 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3209 if (Subtarget.isUsingPCRelativeCalls()) {
3210 SDLoc DL(BASDN);
3211 EVT Ty = getPointerTy(DAG.getDataLayout());
3212 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3213 PPCII::MO_PCREL_FLAG);
3214 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3215 return MatAddr;
3216 }
3217
3218 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3219 // The actual BlockAddress is stored in the TOC.
3220 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3221 setUsesTOCBasePtr(DAG);
3222 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3223 return getTOCEntry(DAG, SDLoc(BASDN), GA);
3224 }
3225
3226 // 32-bit position-independent ELF stores the BlockAddress in the .got.
3227 if (Subtarget.is32BitELFABI() && isPositionIndependent())
3228 return getTOCEntry(
3229 DAG, SDLoc(BASDN),
3230 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
3231
3232 unsigned MOHiFlag, MOLoFlag;
3233 bool IsPIC = isPositionIndependent();
3234 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3235 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3236 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3237 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
3238}
3239
3240SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3241 SelectionDAG &DAG) const {
3242 if (Subtarget.isAIXABI())
3243 return LowerGlobalTLSAddressAIX(Op, DAG);
3244
3245 return LowerGlobalTLSAddressLinux(Op, DAG);
3246}
3247
3248SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
3249 SelectionDAG &DAG) const {
3250 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3251
3252 if (DAG.getTarget().useEmulatedTLS())
3253 report_fatal_error("Emulated TLS is not yet supported on AIX");
3254
3255 SDLoc dl(GA);
3256 const GlobalValue *GV = GA->getGlobal();
3257 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3258
3259 // The general-dynamic model is the only access model supported for now, so
3260 // all the GlobalTLSAddress nodes are lowered with this model.
3261 // We need to generate two TOC entries, one for the variable offset, one for
3262 // the region handle. The global address for the TOC entry of the region
3263 // handle is created with the MO_TLSGDM_FLAG flag and the global address
3264 // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG.
3265 SDValue VariableOffsetTGA =
3266 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
3267 SDValue RegionHandleTGA =
3268 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGDM_FLAG);
3269 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3270 SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
3271 return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,
3272 RegionHandle);
3273}
3274
3275SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
3276 SelectionDAG &DAG) const {
3277 // FIXME: TLS addresses currently use medium model code sequences,
3278 // which is the most useful form. Eventually support for small and
3279 // large models could be added if users need it, at the cost of
3280 // additional complexity.
3281 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3282 if (DAG.getTarget().useEmulatedTLS())
3283 return LowerToTLSEmulatedModel(GA, DAG);
3284
3285 SDLoc dl(GA);
3286 const GlobalValue *GV = GA->getGlobal();
3287 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3288 bool is64bit = Subtarget.isPPC64();
3289 const Module *M = DAG.getMachineFunction().getFunction().getParent();
3290 PICLevel::Level picLevel = M->getPICLevel();
3291
3292 const TargetMachine &TM = getTargetMachine();
3293 TLSModel::Model Model = TM.getTLSModel(GV);
3294
3295 if (Model == TLSModel::LocalExec) {
3296 if (Subtarget.isUsingPCRelativeCalls()) {
3297 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3298 SDValue TGA = DAG.getTargetGlobalAddress(
3299 GV, dl, PtrVT, 0, (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG));
3300 SDValue MatAddr =
3301 DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
3302 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
3303 }
3304
3305 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3306 PPCII::MO_TPREL_HA);
3307 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3308 PPCII::MO_TPREL_LO);
3309 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3310 : DAG.getRegister(PPC::R2, MVT::i32);
3311
3312 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3313 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
3314 }
3315
3316 if (Model == TLSModel::InitialExec) {
3317 bool IsPCRel = Subtarget.isUsingPCRelativeCalls();
3318 SDValue TGA = DAG.getTargetGlobalAddress(
3319 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
3320 SDValue TGATLS = DAG.getTargetGlobalAddress(
3321 GV, dl, PtrVT, 0,
3322 IsPCRel ? (PPCII::MO_TLS | PPCII::MO_PCREL_FLAG) : PPCII::MO_TLS);
3323 SDValue TPOffset;
3324 if (IsPCRel) {
3325 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3326 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
3327 MachinePointerInfo());
3328 } else {
3329 SDValue GOTPtr;
3330 if (is64bit) {
3331 setUsesTOCBasePtr(DAG);
3332 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3333 GOTPtr =
3334 DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
3335 } else {
3336 if (!TM.isPositionIndependent())
3337 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
3338 else if (picLevel == PICLevel::SmallPIC)
3339 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3340 else
3341 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3342 }
3343 TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
3344 }
3345 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
3346 }
3347
3348 if (Model == TLSModel::GeneralDynamic) {
3349 if (Subtarget.isUsingPCRelativeCalls()) {
3350 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3351 PPCII::MO_GOT_TLSGD_PCREL_FLAG);
3352 return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3353 }
3354
3355 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3356 SDValue GOTPtr;
3357 if (is64bit) {
3358 setUsesTOCBasePtr(DAG);
3359 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3360 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
3361 GOTReg, TGA);
3362 } else {
3363 if (picLevel == PICLevel::SmallPIC)
3364 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3365 else
3366 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3367 }
3368 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
3369 GOTPtr, TGA, TGA);
3370 }
3371
3372 if (Model == TLSModel::LocalDynamic) {
3373 if (Subtarget.isUsingPCRelativeCalls()) {
3374 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3375 PPCII::MO_GOT_TLSLD_PCREL_FLAG);
3376 SDValue MatPCRel =
3377 DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3378 return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
3379 }
3380
3381 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3382 SDValue GOTPtr;
3383 if (is64bit) {
3384 setUsesTOCBasePtr(DAG);
3385 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3386 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
3387 GOTReg, TGA);
3388 } else {
3389 if (picLevel == PICLevel::SmallPIC)
3390 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3391 else
3392 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3393 }
3394 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3395 PtrVT, GOTPtr, TGA, TGA);
3396 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3397 PtrVT, TLSAddr, TGA);
3398 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
3399 }
3400
3401 llvm_unreachable("Unknown TLS model!")::llvm::llvm_unreachable_internal("Unknown TLS model!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3401)
;
3402}
3403
3404SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3405 SelectionDAG &DAG) const {
3406 EVT PtrVT = Op.getValueType();
3407 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
3408 SDLoc DL(GSDN);
3409 const GlobalValue *GV = GSDN->getGlobal();
3410
3411 // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
3412 // The actual address of the GlobalValue is stored in the TOC.
3413 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3414 if (Subtarget.isUsingPCRelativeCalls()) {
3415 EVT Ty = getPointerTy(DAG.getDataLayout());
3416 if (isAccessedAsGotIndirect(Op)) {
3417 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3418 PPCII::MO_PCREL_FLAG |
3419 PPCII::MO_GOT_FLAG);
3420 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3421 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
3422 MachinePointerInfo());
3423 return Load;
3424 } else {
3425 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3426 PPCII::MO_PCREL_FLAG);
3427 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3428 }
3429 }
3430 setUsesTOCBasePtr(DAG);
3431 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
3432 return getTOCEntry(DAG, DL, GA);
3433 }
3434
3435 unsigned MOHiFlag, MOLoFlag;
3436 bool IsPIC = isPositionIndependent();
3437 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
3438
3439 if (IsPIC && Subtarget.isSVR4ABI()) {
3440 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3441 GSDN->getOffset(),
3442 PPCII::MO_PIC_FLAG);
3443 return getTOCEntry(DAG, DL, GA);
3444 }
3445
3446 SDValue GAHi =
3447 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
3448 SDValue GALo =
3449 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
3450
3451 return LowerLabelRef(GAHi, GALo, IsPIC, DAG);
3452}
3453
3454SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3455 bool IsStrict = Op->isStrictFPOpcode();
3456 ISD::CondCode CC =
3457 cast<CondCodeSDNode>(Op.getOperand(IsStrict ? 3 : 2))->get();
3458 SDValue LHS = Op.getOperand(IsStrict ? 1 : 0);
3459 SDValue RHS = Op.getOperand(IsStrict ? 2 : 1);
3460 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
3461 EVT LHSVT = LHS.getValueType();
3462 SDLoc dl(Op);
3463
3464 // Soften the setcc with libcall if it is fp128.
3465 if (LHSVT == MVT::f128) {
3466 assert(!Subtarget.hasP9Vector() &&(static_cast <bool> (!Subtarget.hasP9Vector() &&
"SETCC for f128 is already legal under Power9!") ? void (0) :
__assert_fail ("!Subtarget.hasP9Vector() && \"SETCC for f128 is already legal under Power9!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3467, __extension__ __PRETTY_FUNCTION__))
3467 "SETCC for f128 is already legal under Power9!")(static_cast <bool> (!Subtarget.hasP9Vector() &&
"SETCC for f128 is already legal under Power9!") ? void (0) :
__assert_fail ("!Subtarget.hasP9Vector() && \"SETCC for f128 is already legal under Power9!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3467, __extension__ __PRETTY_FUNCTION__))
;
3468 softenSetCCOperands(DAG, LHSVT, LHS, RHS, CC, dl, LHS, RHS, Chain,
3469 Op->getOpcode() == ISD::STRICT_FSETCCS);
3470 if (RHS.getNode())
3471 LHS = DAG.getNode(ISD::SETCC, dl, Op.getValueType(), LHS, RHS,
3472 DAG.getCondCode(CC));
3473 if (IsStrict)
3474 return DAG.getMergeValues({LHS, Chain}, dl);
3475 return LHS;
3476 }
3477
3478 assert(!IsStrict && "Don't know how to handle STRICT_FSETCC!")(static_cast <bool> (!IsStrict && "Don't know how to handle STRICT_FSETCC!"
) ? void (0) : __assert_fail ("!IsStrict && \"Don't know how to handle STRICT_FSETCC!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3478, __extension__ __PRETTY_FUNCTION__))
;
3479
3480 if (Op.getValueType() == MVT::v2i64) {
3481 // When the operands themselves are v2i64 values, we need to do something
3482 // special because VSX has no underlying comparison operations for these.
3483 if (LHS.getValueType() == MVT::v2i64) {
3484 // Equality can be handled by casting to the legal type for Altivec
3485 // comparisons, everything else needs to be expanded.
3486 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3487 return DAG.getNode(
3488 ISD::BITCAST, dl, MVT::v2i64,
3489 DAG.getSetCC(dl, MVT::v4i32,
3490 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, LHS),
3491 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, RHS), CC));
3492 }
3493
3494 return SDValue();
3495 }
3496
3497 // We handle most of these in the usual way.
3498 return Op;
3499 }
3500
3501 // If we're comparing for equality to zero, expose the fact that this is
3502 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
3503 // fold the new nodes.
3504 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
3505 return V;
3506
3507 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
3508 // Leave comparisons against 0 and -1 alone for now, since they're usually
3509 // optimized. FIXME: revisit this when we can custom lower all setcc
3510 // optimizations.
3511 if (C->isAllOnes() || C->isZero())
3512 return SDValue();
3513 }
3514
3515 // If we have an integer seteq/setne, turn it into a compare against zero
3516 // by xor'ing the rhs with the lhs, which is faster than setting a
3517 // condition register, reading it back out, and masking the correct bit. The
3518 // normal approach here uses sub to do this instead of xor. Using xor exposes
3519 // the result to other bit-twiddling opportunities.
3520 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
3521 EVT VT = Op.getValueType();
3522 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, LHS, RHS);
3523 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
3524 }
3525 return SDValue();
3526}
3527
3528SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3529 SDNode *Node = Op.getNode();
3530 EVT VT = Node->getValueType(0);
3531 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3532 SDValue InChain = Node->getOperand(0);
3533 SDValue VAListPtr = Node->getOperand(1);
3534 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3535 SDLoc dl(Node);
3536
3537 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")(static_cast <bool> (!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"
) ? void (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVAARG is PPC32 only\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3537, __extension__ __PRETTY_FUNCTION__))
;
3538
3539 // gpr_index
3540 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3541 VAListPtr, MachinePointerInfo(SV), MVT::i8);
3542 InChain = GprIndex.getValue(1);
3543
3544 if (VT == MVT::i64) {
3545 // Check if GprIndex is even
3546 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
3547 DAG.getConstant(1, dl, MVT::i32));
3548 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
3549 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
3550 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
3551 DAG.getConstant(1, dl, MVT::i32));
3552 // Align GprIndex to be even if it isn't
3553 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
3554 GprIndex);
3555 }
3556
3557 // fpr index is 1 byte after gpr
3558 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3559 DAG.getConstant(1, dl, MVT::i32));
3560
3561 // fpr
3562 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3563 FprPtr, MachinePointerInfo(SV), MVT::i8);
3564 InChain = FprIndex.getValue(1);
3565
3566 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3567 DAG.getConstant(8, dl, MVT::i32));
3568
3569 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3570 DAG.getConstant(4, dl, MVT::i32));
3571
3572 // areas
3573 SDValue OverflowArea =
3574 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
3575 InChain = OverflowArea.getValue(1);
3576
3577 SDValue RegSaveArea =
3578 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
3579 InChain = RegSaveArea.getValue(1);
3580
3581 // select overflow_area if index > 8
3582 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3583 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
3584
3585 // adjustment constant gpr_index * 4/8
3586 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
3587 VT.isInteger() ? GprIndex : FprIndex,
3588 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3589 MVT::i32));
3590
3591 // OurReg = RegSaveArea + RegConstant
3592 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
3593 RegConstant);
3594
3595 // Floating types are 32 bytes into RegSaveArea
3596 if (VT.isFloatingPoint())
3597 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
3598 DAG.getConstant(32, dl, MVT::i32));
3599
3600 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
3601 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3602 VT.isInteger() ? GprIndex : FprIndex,
3603 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
3604 MVT::i32));
3605
3606 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
3607 VT.isInteger() ? VAListPtr : FprPtr,
3608 MachinePointerInfo(SV), MVT::i8);
3609
3610 // determine if we should load from reg_save_area or overflow_area
3611 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3612
3613 // increase overflow_area by 4/8 if gpr/fpr > 8
3614 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
3615 DAG.getConstant(VT.isInteger() ? 4 : 8,
3616 dl, MVT::i32));
3617
3618 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
3619 OverflowAreaPlusN);
3620
3621 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
3622 MachinePointerInfo(), MVT::i32);
3623
3624 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
3625}
3626
3627SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3628 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only")(static_cast <bool> (!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"
) ? void (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVACOPY is PPC32 only\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3628, __extension__ __PRETTY_FUNCTION__))
;
3629
3630 // We have to copy the entire va_list struct:
3631 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3632 return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2),
3633 DAG.getConstant(12, SDLoc(Op), MVT::i32), Align(8),
3634 false, true, false, MachinePointerInfo(),
3635 MachinePointerInfo());
3636}
3637
3638SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3639 SelectionDAG &DAG) const {
3640 if (Subtarget.isAIXABI())
3641 report_fatal_error("ADJUST_TRAMPOLINE operation is not supported on AIX.");
3642
3643 return Op.getOperand(0);
3644}
3645
3646SDValue PPCTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
3647 MachineFunction &MF = DAG.getMachineFunction();
3648 PPCFunctionInfo &MFI = *MF.getInfo<PPCFunctionInfo>();
3649
3650 assert((Op.getOpcode() == ISD::INLINEASM ||(static_cast <bool> ((Op.getOpcode() == ISD::INLINEASM ||
Op.getOpcode() == ISD::INLINEASM_BR) && "Expecting Inline ASM node."
) ? void (0) : __assert_fail ("(Op.getOpcode() == ISD::INLINEASM || Op.getOpcode() == ISD::INLINEASM_BR) && \"Expecting Inline ASM node.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3652, __extension__ __PRETTY_FUNCTION__))
3651 Op.getOpcode() == ISD::INLINEASM_BR) &&(static_cast <bool> ((Op.getOpcode() == ISD::INLINEASM ||
Op.getOpcode() == ISD::INLINEASM_BR) && "Expecting Inline ASM node."
) ? void (0) : __assert_fail ("(Op.getOpcode() == ISD::INLINEASM || Op.getOpcode() == ISD::INLINEASM_BR) && \"Expecting Inline ASM node.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3652, __extension__ __PRETTY_FUNCTION__))
3652 "Expecting Inline ASM node.")(static_cast <bool> ((Op.getOpcode() == ISD::INLINEASM ||
Op.getOpcode() == ISD::INLINEASM_BR) && "Expecting Inline ASM node."
) ? void (0) : __assert_fail ("(Op.getOpcode() == ISD::INLINEASM || Op.getOpcode() == ISD::INLINEASM_BR) && \"Expecting Inline ASM node.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3652, __extension__ __PRETTY_FUNCTION__))
;
3653
3654 // If an LR store is already known to be required then there is not point in
3655 // checking this ASM as well.
3656 if (MFI.isLRStoreRequired())
3657 return Op;
3658
3659 // Inline ASM nodes have an optional last operand that is an incoming Flag of
3660 // type MVT::Glue. We want to ignore this last operand if that is the case.
3661 unsigned NumOps = Op.getNumOperands();
3662 if (Op.getOperand(NumOps - 1).getValueType() == MVT::Glue)
3663 --NumOps;
3664
3665 // Check all operands that may contain the LR.
3666 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
3667 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
3668 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
3669 ++i; // Skip the ID value.
3670
3671 switch (InlineAsm::getKind(Flags)) {
3672 default:
3673 llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3673)
;
3674 case InlineAsm::Kind_RegUse:
3675 case InlineAsm::Kind_Imm:
3676 case InlineAsm::Kind_Mem:
3677 i += NumVals;
3678 break;
3679 case InlineAsm::Kind_Clobber:
3680 case InlineAsm::Kind_RegDef:
3681 case InlineAsm::Kind_RegDefEarlyClobber: {
3682 for (; NumVals; --NumVals, ++i) {
3683 Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
3684 if (Reg != PPC::LR && Reg != PPC::LR8)
3685 continue;
3686 MFI.setLRStoreRequired();
3687 return Op;
3688 }
3689 break;
3690 }
3691 }
3692 }
3693
3694 return Op;
3695}
3696
3697SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3698 SelectionDAG &DAG) const {
3699 if (Subtarget.isAIXABI())
3700 report_fatal_error("INIT_TRAMPOLINE operation is not supported on AIX.");
3701
3702 SDValue Chain = Op.getOperand(0);
3703 SDValue Trmp = Op.getOperand(1); // trampoline
3704 SDValue FPtr = Op.getOperand(2); // nested function
3705 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3706 SDLoc dl(Op);
3707
3708 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3709 bool isPPC64 = (PtrVT == MVT::i64);
3710 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3711
3712 TargetLowering::ArgListTy Args;
3713 TargetLowering::ArgListEntry Entry;
3714
3715 Entry.Ty = IntPtrTy;
3716 Entry.Node = Trmp; Args.push_back(Entry);
3717
3718 // TrampSize == (isPPC64 ? 48 : 40);
3719 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3720 isPPC64 ? MVT::i64 : MVT::i32);
3721 Args.push_back(Entry);
3722
3723 Entry.Node = FPtr; Args.push_back(Entry);
3724 Entry.Node = Nest; Args.push_back(Entry);
3725
3726 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3727 TargetLowering::CallLoweringInfo CLI(DAG);
3728 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3729 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3730 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3731
3732 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3733 return CallResult.second;
3734}
3735
3736SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3737 MachineFunction &MF = DAG.getMachineFunction();
3738 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3739 EVT PtrVT = getPointerTy(MF.getDataLayout());
3740
3741 SDLoc dl(Op);
3742
3743 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) {
3744 // vastart just stores the address of the VarArgsFrameIndex slot into the
3745 // memory location argument.
3746 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3747 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3748 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3749 MachinePointerInfo(SV));
3750 }
3751
3752 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3753 // We suppose the given va_list is already allocated.
3754 //
3755 // typedef struct {
3756 // char gpr; /* index into the array of 8 GPRs
3757 // * stored in the register save area
3758 // * gpr=0 corresponds to r3,
3759 // * gpr=1 to r4, etc.
3760 // */
3761 // char fpr; /* index into the array of 8 FPRs
3762 // * stored in the register save area
3763 // * fpr=0 corresponds to f1,
3764 // * fpr=1 to f2, etc.
3765 // */
3766 // char *overflow_arg_area;
3767 // /* location on stack that holds
3768 // * the next overflow argument
3769 // */
3770 // char *reg_save_area;
3771 // /* where r3:r10 and f1:f8 (if saved)
3772 // * are stored
3773 // */
3774 // } va_list[1];
3775
3776 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3777 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3778 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3779 PtrVT);
3780 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3781 PtrVT);
3782
3783 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3784 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3785
3786 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3787 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3788
3789 uint64_t FPROffset = 1;
3790 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3791
3792 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3793
3794 // Store first byte : number of int regs
3795 SDValue firstStore =
3796 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3797 MachinePointerInfo(SV), MVT::i8);
3798 uint64_t nextOffset = FPROffset;
3799 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3800 ConstFPROffset);
3801
3802 // Store second byte : number of float regs
3803 SDValue secondStore =
3804 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3805 MachinePointerInfo(SV, nextOffset), MVT::i8);
3806 nextOffset += StackOffset;
3807 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3808
3809 // Store second word : arguments given on stack
3810 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3811 MachinePointerInfo(SV, nextOffset));
3812 nextOffset += FrameOffset;
3813 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3814
3815 // Store third word : arguments given in registers
3816 return DAG.getStore(thirdStore, dl, FR, nextPtr,
3817 MachinePointerInfo(SV, nextOffset));
3818}
3819
3820/// FPR - The set of FP registers that should be allocated for arguments
3821/// on Darwin and AIX.
3822static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3823 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3824 PPC::F11, PPC::F12, PPC::F13};
3825
3826/// CalculateStackSlotSize - Calculates the size reserved for this argument on
3827/// the stack.
3828static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3829 unsigned PtrByteSize) {
3830 unsigned ArgSize = ArgVT.getStoreSize();
3831 if (Flags.isByVal())
3832 ArgSize = Flags.getByValSize();
3833
3834 // Round up to multiples of the pointer size, except for array members,
3835 // which are always packed.
3836 if (!Flags.isInConsecutiveRegs())
3837 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3838
3839 return ArgSize;
3840}
3841
3842/// CalculateStackSlotAlignment - Calculates the alignment of this argument
3843/// on the stack.
3844static Align CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3845 ISD::ArgFlagsTy Flags,
3846 unsigned PtrByteSize) {
3847 Align Alignment(PtrByteSize);
3848
3849 // Altivec parameters are padded to a 16 byte boundary.
3850 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3851 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3852 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3853 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3854 Alignment = Align(16);
3855
3856 // ByVal parameters are aligned as requested.
3857 if (Flags.isByVal()) {
3858 auto BVAlign = Flags.getNonZeroByValAlign();
3859 if (BVAlign > PtrByteSize) {
3860 if (BVAlign.value() % PtrByteSize != 0)
3861 llvm_unreachable(::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3862)
3862 "ByVal alignment is not a multiple of the pointer size")::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3862)
;
3863
3864 Alignment = BVAlign;
3865 }
3866 }
3867
3868 // Array members are always packed to their original alignment.
3869 if (Flags.isInConsecutiveRegs()) {
3870 // If the array member was split into multiple registers, the first
3871 // needs to be aligned to the size of the full type. (Except for
3872 // ppcf128, which is only aligned as its f64 components.)
3873 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3874 Alignment = Align(OrigVT.getStoreSize());
3875 else
3876 Alignment = Align(ArgVT.getStoreSize());
3877 }
3878
3879 return Alignment;
3880}
3881
3882/// CalculateStackSlotUsed - Return whether this argument will use its
3883/// stack slot (instead of being passed in registers). ArgOffset,
3884/// AvailableFPRs, and AvailableVRs must hold the current argument
3885/// position, and will be updated to account for this argument.
3886static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags,
3887 unsigned PtrByteSize, unsigned LinkageSize,
3888 unsigned ParamAreaSize, unsigned &ArgOffset,
3889 unsigned &AvailableFPRs,
3890 unsigned &AvailableVRs) {
3891 bool UseMemory = false;
3892
3893 // Respect alignment of argument on the stack.
3894 Align Alignment =
3895 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3896 ArgOffset = alignTo(ArgOffset, Alignment);
3897 // If there's no space left in the argument save area, we must
3898 // use memory (this check also catches zero-sized arguments).
3899 if (ArgOffset >= LinkageSize + ParamAreaSize)
3900 UseMemory = true;
3901
3902 // Allocate argument on the stack.
3903 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3904 if (Flags.isInConsecutiveRegsLast())
3905 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3906 // If we overran the argument save area, we must use memory
3907 // (this check catches arguments passed partially in memory)
3908 if (ArgOffset > LinkageSize + ParamAreaSize)
3909 UseMemory = true;
3910
3911 // However, if the argument is actually passed in an FPR or a VR,
3912 // we don't use memory after all.
3913 if (!Flags.isByVal()) {
3914 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
3915 if (AvailableFPRs > 0) {
3916 --AvailableFPRs;
3917 return false;
3918 }
3919 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3920 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3921 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3922 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3923 if (AvailableVRs > 0) {
3924 --AvailableVRs;
3925 return false;
3926 }
3927 }
3928
3929 return UseMemory;
3930}
3931
3932/// EnsureStackAlignment - Round stack frame size up from NumBytes to
3933/// ensure minimum alignment required for target.
3934static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3935 unsigned NumBytes) {
3936 return alignTo(NumBytes, Lowering->getStackAlign());
3937}
3938
3939SDValue PPCTargetLowering::LowerFormalArguments(
3940 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3941 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3942 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3943 if (Subtarget.isAIXABI())
3944 return LowerFormalArguments_AIX(Chain, CallConv, isVarArg, Ins, dl, DAG,
3945 InVals);
3946 if (Subtarget.is64BitELFABI())
3947 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3948 InVals);
3949 assert(Subtarget.is32BitELFABI())(static_cast <bool> (Subtarget.is32BitELFABI()) ? void (
0) : __assert_fail ("Subtarget.is32BitELFABI()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3949, __extension__ __PRETTY_FUNCTION__))
;
3950 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3951 InVals);
3952}
3953
3954SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3955 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3956 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3957 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3958
3959 // 32-bit SVR4 ABI Stack Frame Layout:
3960 // +-----------------------------------+
3961 // +--> | Back chain |
3962 // | +-----------------------------------+
3963 // | | Floating-point register save area |
3964 // | +-----------------------------------+
3965 // | | General register save area |
3966 // | +-----------------------------------+
3967 // | | CR save word |
3968 // | +-----------------------------------+
3969 // | | VRSAVE save word |
3970 // | +-----------------------------------+
3971 // | | Alignment padding |
3972 // | +-----------------------------------+
3973 // | | Vector register save area |
3974 // | +-----------------------------------+
3975 // | | Local variable space |
3976 // | +-----------------------------------+
3977 // | | Parameter list area |
3978 // | +-----------------------------------+
3979 // | | LR save word |
3980 // | +-----------------------------------+
3981 // SP--> +--- | Back chain |
3982 // +-----------------------------------+
3983 //
3984 // Specifications:
3985 // System V Application Binary Interface PowerPC Processor Supplement
3986 // AltiVec Technology Programming Interface Manual
3987
3988 MachineFunction &MF = DAG.getMachineFunction();
3989 MachineFrameInfo &MFI = MF.getFrameInfo();
3990 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3991
3992 EVT PtrVT = getPointerTy(MF.getDataLayout());
3993 // Potential tail calls could cause overwriting of argument stack slots.
3994 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3995 (CallConv == CallingConv::Fast));
3996 const Align PtrAlign(4);
3997
3998 // Assign locations to all of the incoming arguments.
3999 SmallVector<CCValAssign, 16> ArgLocs;
4000 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4001 *DAG.getContext());
4002
4003 // Reserve space for the linkage area on the stack.
4004 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4005 CCInfo.AllocateStack(LinkageSize, PtrAlign);
4006 if (useSoftFloat())
4007 CCInfo.PreAnalyzeFormalArguments(Ins);
4008
4009 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
4010 CCInfo.clearWasPPCF128();
4011
4012 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4013 CCValAssign &VA = ArgLocs[i];
4014
4015 // Arguments stored in registers.
4016 if (VA.isRegLoc()) {
4017 const TargetRegisterClass *RC;
4018 EVT ValVT = VA.getValVT();
4019
4020 switch (ValVT.getSimpleVT().SimpleTy) {
4021 default:
4022 llvm_unreachable("ValVT not supported by formal arguments Lowering")::llvm::llvm_unreachable_internal("ValVT not supported by formal arguments Lowering"
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4022)
;
4023 case MVT::i1:
4024 case MVT::i32:
4025 RC = &PPC::GPRCRegClass;
4026 break;
4027 case MVT::f32:
4028 if (Subtarget.hasP8Vector())
4029 RC = &PPC::VSSRCRegClass;
4030 else if (Subtarget.hasSPE())
4031 RC = &PPC::GPRCRegClass;
4032 else
4033 RC = &PPC::F4RCRegClass;
4034 break;
4035 case MVT::f64:
4036 if (Subtarget.hasVSX())
4037 RC = &PPC::VSFRCRegClass;
4038 else if (Subtarget.hasSPE())
4039 // SPE passes doubles in GPR pairs.
4040 RC = &PPC::GPRCRegClass;
4041 else
4042 RC = &PPC::F8RCRegClass;
4043 break;
4044 case MVT::v16i8:
4045 case MVT::v8i16:
4046 case MVT::v4i32:
4047 RC = &PPC::VRRCRegClass;
4048 break;
4049 case MVT::v4f32:
4050 RC = &PPC::VRRCRegClass;
4051 break;
4052 case MVT::v2f64:
4053 case MVT::v2i64:
4054 RC = &PPC::VRRCRegClass;
4055 break;
4056 }
4057
4058 SDValue ArgValue;
4059 // Transform the arguments stored in physical registers into
4060 // virtual ones.
4061 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
4062 assert(i + 1 < e && "No second half of double precision argument")(static_cast <bool> (i + 1 < e && "No second half of double precision argument"
) ? void (0) : __assert_fail ("i + 1 < e && \"No second half of double precision argument\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4062, __extension__ __PRETTY_FUNCTION__))
;
4063 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC);
4064 unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC);
4065 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32);
4066 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32);
4067 if (!Subtarget.isLittleEndian())
4068 std::swap (ArgValueLo, ArgValueHi);
4069 ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo,
4070 ArgValueHi);
4071 } else {
4072 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4073 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
4074 ValVT == MVT::i1 ? MVT::i32 : ValVT);
4075 if (ValVT == MVT::i1)
4076 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
4077 }
4078
4079 InVals.push_back(ArgValue);
4080 } else {
4081 // Argument stored in memory.
4082 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4082, __extension__ __PRETTY_FUNCTION__))
;
4083
4084 // Get the extended size of the argument type in stack
4085 unsigned ArgSize = VA.getLocVT().getStoreSize();
4086 // Get the actual size of the argument type
4087 unsigned ObjSize = VA.getValVT().getStoreSize();
4088 unsigned ArgOffset = VA.getLocMemOffset();
4089 // Stack objects in PPC32 are right justified.
4090 ArgOffset += ArgSize - ObjSize;
4091 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
4092
4093 // Create load nodes to retrieve arguments from the stack.
4094 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4095 InVals.push_back(
4096 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
4097 }
4098 }
4099
4100 // Assign locations to all of the incoming aggregate by value arguments.
4101 // Aggregates passed by value are stored in the local variable space of the
4102 // caller's stack frame, right above the parameter list area.
4103 SmallVector<CCValAssign, 16> ByValArgLocs;
4104 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4105 ByValArgLocs, *DAG.getContext());
4106
4107 // Reserve stack space for the allocations in CCInfo.
4108 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrAlign);
4109
4110 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
4111
4112 // Area that is at least reserved in the caller of this function.
4113 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
4114 MinReservedArea = std::max(MinReservedArea, LinkageSize);
4115
4116 // Set the size that is at least reserved in caller of this function. Tail
4117 // call optimized function's reserved stack space needs to be aligned so that
4118 // taking the difference between two stack areas will result in an aligned
4119 // stack.
4120 MinReservedArea =
4121 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4122 FuncInfo->setMinReservedArea(MinReservedArea);
4123
4124 SmallVector<SDValue, 8> MemOps;
4125
4126 // If the function takes variable number of arguments, make a frame index for
4127 // the start of the first vararg value... for expansion of llvm.va_start.
4128 if (isVarArg) {
4129 static const MCPhysReg GPArgRegs[] = {
4130 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4131 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4132 };
4133 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
4134
4135 static const MCPhysReg FPArgRegs[] = {
4136 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
4137 PPC::F8
4138 };
4139 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
4140
4141 if (useSoftFloat() || hasSPE())
4142 NumFPArgRegs = 0;
4143
4144 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
4145 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
4146
4147 // Make room for NumGPArgRegs and NumFPArgRegs.
4148 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
4149 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
4150
4151 FuncInfo->setVarArgsStackOffset(
4152 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
4153 CCInfo.getNextStackOffset(), true));
4154
4155 FuncInfo->setVarArgsFrameIndex(
4156 MFI.CreateStackObject(Depth, Align(8), false));
4157 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4158
4159 // The fixed integer arguments of a variadic function are stored to the
4160 // VarArgsFrameIndex on the stack so that they may be loaded by
4161 // dereferencing the result of va_next.
4162 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
4163 // Get an existing live-in vreg, or add a new one.
4164 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
4165 if (!VReg)
4166 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
4167
4168 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4169 SDValue Store =
4170 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4171 MemOps.push_back(Store);
4172 // Increment the address by four for the next argument to store
4173 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4174 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4175 }
4176
4177 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
4178 // is set.
4179 // The double arguments are stored to the VarArgsFrameIndex
4180 // on the stack.
4181 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
4182 // Get an existing live-in vreg, or add a new one.
4183 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
4184 if (!VReg)
4185 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
4186
4187 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
4188 SDValue Store =
4189 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4190 MemOps.push_back(Store);
4191 // Increment the address by eight for the next argument to store
4192 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
4193 PtrVT);
4194 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4195 }
4196 }
4197
4198 if (!MemOps.empty())
4199 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4200
4201 return Chain;
4202}
4203
4204// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4205// value to MVT::i64 and then truncate to the correct register size.
4206SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
4207 EVT ObjectVT, SelectionDAG &DAG,
4208 SDValue ArgVal,
4209 const SDLoc &dl) const {
4210 if (Flags.isSExt())
4211 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
4212 DAG.getValueType(ObjectVT));
4213 else if (Flags.isZExt())
4214 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
4215 DAG.getValueType(ObjectVT));
4216
4217 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
4218}
4219
4220SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
4221 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4222 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4223 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4224 // TODO: add description of PPC stack frame format, or at least some docs.
4225 //
4226 bool isELFv2ABI = Subtarget.isELFv2ABI();
4227 bool isLittleEndian = Subtarget.isLittleEndian();
4228 MachineFunction &MF = DAG.getMachineFunction();
4229 MachineFrameInfo &MFI = MF.getFrameInfo();
4230 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4231
4232 assert(!(CallConv == CallingConv::Fast && isVarArg) &&(static_cast <bool> (!(CallConv == CallingConv::Fast &&
isVarArg) && "fastcc not supported on varargs functions"
) ? void (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4233, __extension__ __PRETTY_FUNCTION__))
4233 "fastcc not supported on varargs functions")(static_cast <bool> (!(CallConv == CallingConv::Fast &&
isVarArg) && "fastcc not supported on varargs functions"
) ? void (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4233, __extension__ __PRETTY_FUNCTION__))
;
4234
4235 EVT PtrVT = getPointerTy(MF.getDataLayout());
4236 // Potential tail calls could cause overwriting of argument stack slots.
4237 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4238 (CallConv == CallingConv::Fast));
4239 unsigned PtrByteSize = 8;
4240 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4241
4242 static const MCPhysReg GPR[] = {
4243 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4244 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4245 };
4246 static const MCPhysReg VR[] = {
4247 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4248 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4249 };
4250
4251 const unsigned Num_GPR_Regs = array_lengthof(GPR);
4252 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4253 const unsigned Num_VR_Regs = array_lengthof(VR);
4254
4255 // Do a first pass over the arguments to determine whether the ABI
4256 // guarantees that our caller has allocated the parameter save area
4257 // on its stack frame. In the ELFv1 ABI, this is always the case;
4258 // in the ELFv2 ABI, it is true if this is a vararg function or if
4259 // any parameter is located in a stack slot.
4260
4261 bool HasParameterArea = !isELFv2ABI || isVarArg;
4262 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
4263 unsigned NumBytes = LinkageSize;
4264 unsigned AvailableFPRs = Num_FPR_Regs;
4265 unsigned AvailableVRs = Num_VR_Regs;
4266 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4267 if (Ins[i].Flags.isNest())
4268 continue;
4269
4270 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
4271 PtrByteSize, LinkageSize, ParamAreaSize,
4272 NumBytes, AvailableFPRs, AvailableVRs))
4273 HasParameterArea = true;
4274 }
4275
4276 // Add DAG nodes to load the arguments or copy them out of registers. On
4277 // entry to a function on PPC, the arguments start after the linkage area,
4278 // although the first ones are often in registers.
4279
4280 unsigned ArgOffset = LinkageSize;
4281 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4282 SmallVector<SDValue, 8> MemOps;
4283 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4284 unsigned CurArgIdx = 0;
4285 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4286 SDValue ArgVal;
4287 bool needsLoad = false;
4288 EVT ObjectVT = Ins[ArgNo].VT;
4289 EVT OrigVT = Ins[ArgNo].ArgVT;
4290 unsigned ObjSize = ObjectVT.getStoreSize();
4291 unsigned ArgSize = ObjSize;
4292 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4293 if (Ins[ArgNo].isOrigArg()) {
4294 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4295 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4296 }
4297 // We re-align the argument offset for each argument, except when using the
4298 // fast calling convention, when we need to make sure we do that only when
4299 // we'll actually use a stack slot.
4300 unsigned CurArgOffset;
4301 Align Alignment;
4302 auto ComputeArgOffset = [&]() {
4303 /* Respect alignment of argument on the stack. */
4304 Alignment =
4305 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
4306 ArgOffset = alignTo(ArgOffset, Alignment);
4307 CurArgOffset = ArgOffset;
4308 };
4309
4310 if (CallConv != CallingConv::Fast) {
4311 ComputeArgOffset();
4312
4313 /* Compute GPR index associated with argument offset. */
4314 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4315 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
4316 }
4317
4318 // FIXME the codegen can be much improved in some cases.
4319 // We do not have to keep everything in memory.
4320 if (Flags.isByVal()) {
4321 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")(static_cast <bool> (Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4321, __extension__ __PRETTY_FUNCTION__))
;
4322
4323 if (CallConv == CallingConv::Fast)
4324 ComputeArgOffset();
4325
4326 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4327 ObjSize = Flags.getByValSize();
4328 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4329 // Empty aggregate parameters do not take up registers. Examples:
4330 // struct { } a;
4331 // union { } b;
4332 // int c[0];
4333 // etc. However, we have to provide a place-holder in InVals, so
4334 // pretend we have an 8-byte item at the current address for that
4335 // purpose.
4336 if (!ObjSize) {
4337 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4338 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4339 InVals.push_back(FIN);
4340 continue;
4341 }
4342
4343 // Create a stack object covering all stack doublewords occupied
4344 // by the argument. If the argument is (fully or partially) on
4345 // the stack, or if the argument is fully in registers but the
4346 // caller has allocated the parameter save anyway, we can refer
4347 // directly to the caller's stack frame. Otherwise, create a
4348 // local copy in our own frame.
4349 int FI;
4350 if (HasParameterArea ||
4351 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
4352 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
4353 else
4354 FI = MFI.CreateStackObject(ArgSize, Alignment, false);
4355 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4356
4357 // Handle aggregates smaller than 8 bytes.
4358 if (ObjSize < PtrByteSize) {
4359 // The value of the object is its address, which differs from the
4360 // address of the enclosing doubleword on big-endian systems.
4361 SDValue Arg = FIN;
4362 if (!isLittleEndian) {
4363 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
4364 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
4365 }
4366 InVals.push_back(Arg);
4367
4368 if (GPR_idx != Num_GPR_Regs) {
4369 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4370 FuncInfo->addLiveInAttr(VReg, Flags);
4371 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4372 SDValue Store;
4373
4374 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
4375 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
4376 (ObjSize == 2 ? MVT::i16 : MVT::i32));
4377 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
4378 MachinePointerInfo(&*FuncArg), ObjType);
4379 } else {
4380 // For sizes that don't fit a truncating store (3, 5, 6, 7),
4381 // store the whole register as-is to the parameter save area
4382 // slot.
4383 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4384 MachinePointerInfo(&*FuncArg));
4385 }
4386
4387 MemOps.push_back(Store);
4388 }
4389 // Whether we copied from a register or not, advance the offset
4390 // into the parameter save area by a full doubleword.
4391 ArgOffset += PtrByteSize;
4392 continue;
4393 }
4394
4395 // The value of the object is its address, which is the address of
4396 // its first stack doubleword.
4397 InVals.push_back(FIN);
4398
4399 // Store whatever pieces of the object are in registers to memory.
4400 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4401 if (GPR_idx == Num_GPR_Regs)
4402 break;
4403
4404 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4405 FuncInfo->addLiveInAttr(VReg, Flags);
4406 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4407 SDValue Addr = FIN;
4408 if (j) {
4409 SDValue Off = DAG.getConstant(j, dl, PtrVT);
4410 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
4411 }
4412 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
4413 MachinePointerInfo(&*FuncArg, j));
4414 MemOps.push_back(Store);
4415 ++GPR_idx;
4416 }
4417 ArgOffset += ArgSize;
4418 continue;
4419 }
4420
4421 switch (ObjectVT.getSimpleVT().SimpleTy) {
4422 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4422)
;
4423 case MVT::i1:
4424 case MVT::i32:
4425 case MVT::i64:
4426 if (Flags.isNest()) {
4427 // The 'nest' parameter, if any, is passed in R11.
4428 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
4429 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4430
4431 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4432 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4433
4434 break;
4435 }
4436
4437 // These can be scalar arguments or elements of an integer array type
4438 // passed directly. Clang may use those instead of "byval" aggregate
4439 // types to avoid forcing arguments to memory unnecessarily.
4440 if (GPR_idx != Num_GPR_Regs) {
4441 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4442 FuncInfo->addLiveInAttr(VReg, Flags);
4443 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4444
4445 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4446 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4447 // value to MVT::i64 and then truncate to the correct register size.
4448 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4449 } else {
4450 if (CallConv == CallingConv::Fast)
4451 ComputeArgOffset();
4452
4453 needsLoad = true;
4454 ArgSize = PtrByteSize;
4455 }
4456 if (CallConv != CallingConv::Fast || needsLoad)
4457 ArgOffset += 8;
4458 break;
4459
4460 case MVT::f32:
4461 case MVT::f64:
4462 // These can be scalar arguments or elements of a float array type
4463 // passed directly. The latter are used to implement ELFv2 homogenous
4464 // float aggregates.
4465 if (FPR_idx != Num_FPR_Regs) {
4466 unsigned VReg;
4467
4468 if (ObjectVT == MVT::f32)
4469 VReg = MF.addLiveIn(FPR[FPR_idx],
4470 Subtarget.hasP8Vector()
4471 ? &PPC::VSSRCRegClass
4472 : &PPC::F4RCRegClass);
4473 else
4474 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
4475 ? &PPC::VSFRCRegClass
4476 : &PPC::F8RCRegClass);
4477
4478 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4479 ++FPR_idx;
4480 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
4481 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4482 // once we support fp <-> gpr moves.
4483
4484 // This can only ever happen in the presence of f32 array types,
4485 // since otherwise we never run out of FPRs before running out
4486 // of GPRs.
4487 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4488 FuncInfo->addLiveInAttr(VReg, Flags);
4489 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4490
4491 if (ObjectVT == MVT::f32) {
4492 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
4493 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
4494 DAG.getConstant(32, dl, MVT::i32));
4495 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
4496 }
4497
4498 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
4499 } else {
4500 if (CallConv == CallingConv::Fast)
4501 ComputeArgOffset();
4502
4503 needsLoad = true;
4504 }
4505
4506 // When passing an array of floats, the array occupies consecutive
4507 // space in the argument area; only round up to the next doubleword
4508 // at the end of the array. Otherwise, each float takes 8 bytes.
4509 if (CallConv != CallingConv::Fast || needsLoad) {
4510 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
4511 ArgOffset += ArgSize;
4512 if (Flags.isInConsecutiveRegsLast())
4513 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4514 }
4515 break;
4516 case MVT::v4f32:
4517 case MVT::v4i32:
4518 case MVT::v8i16:
4519 case MVT::v16i8:
4520 case MVT::v2f64:
4521 case MVT::v2i64:
4522 case MVT::v1i128:
4523 case MVT::f128:
4524 // These can be scalar arguments or elements of a vector array type
4525 // passed directly. The latter are used to implement ELFv2 homogenous
4526 // vector aggregates.
4527 if (VR_idx != Num_VR_Regs) {
4528 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4529 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4530 ++VR_idx;
4531 } else {
4532 if (CallConv == CallingConv::Fast)
4533 ComputeArgOffset();
4534 needsLoad = true;
4535 }
4536 if (CallConv != CallingConv::Fast || needsLoad)
4537 ArgOffset += 16;
4538 break;
4539 }
4540
4541 // We need to load the argument to a virtual register if we determined
4542 // above that we ran out of physical registers of the appropriate type.
4543 if (needsLoad) {
4544 if (ObjSize < ArgSize && !isLittleEndian)
4545 CurArgOffset += ArgSize - ObjSize;
4546 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
4547 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4548 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4549 }
4550
4551 InVals.push_back(ArgVal);
4552 }
4553
4554 // Area that is at least reserved in the caller of this function.
4555 unsigned MinReservedArea;
4556 if (HasParameterArea)
4557 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
4558 else
4559 MinReservedArea = LinkageSize;
4560
4561 // Set the size that is at least reserved in caller of this function. Tail
4562 // call optimized functions' reserved stack space needs to be aligned so that
4563 // taking the difference between two stack areas will result in an aligned
4564 // stack.
4565 MinReservedArea =
4566 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4567 FuncInfo->setMinReservedArea(MinReservedArea);
4568
4569 // If the function takes variable number of arguments, make a frame index for
4570 // the start of the first vararg value... for expansion of llvm.va_start.
4571 // On ELFv2ABI spec, it writes:
4572 // C programs that are intended to be *portable* across different compilers
4573 // and architectures must use the header file <stdarg.h> to deal with variable
4574 // argument lists.
4575 if (isVarArg && MFI.hasVAStart()) {
4576 int Depth = ArgOffset;
4577
4578 FuncInfo->setVarArgsFrameIndex(
4579 MFI.CreateFixedObject(PtrByteSize, Depth, true));
4580 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4581
4582 // If this function is vararg, store any remaining integer argument regs
4583 // to their spots on the stack so that they may be loaded by dereferencing
4584 // the result of va_next.
4585 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4586 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4587 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4588 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4589 SDValue Store =
4590 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4591 MemOps.push_back(Store);
4592 // Increment the address by four for the next argument to store
4593 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4594 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4595 }
4596 }
4597
4598 if (!MemOps.empty())
4599 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4600
4601 return Chain;
4602}
4603
4604/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4605/// adjusted to accommodate the arguments for the tailcall.
4606static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4607 unsigned ParamSize) {
4608
4609 if (!isTailCall) return 0;
4610
4611 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4612 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4613 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4614 // Remember only if the new adjustment is bigger.
4615 if (SPDiff < FI->getTailCallSPDelta())
4616 FI->setTailCallSPDelta(SPDiff);
4617
4618 return SPDiff;
4619}
4620
4621static bool isFunctionGlobalAddress(SDValue Callee);
4622
4623static bool callsShareTOCBase(const Function *Caller, SDValue Callee,
4624 const TargetMachine &TM) {
4625 // It does not make sense to call callsShareTOCBase() with a caller that
4626 // is PC Relative since PC Relative callers do not have a TOC.
4627#ifndef NDEBUG
4628 const PPCSubtarget *STICaller = &TM.getSubtarget<PPCSubtarget>(*Caller);
4629 assert(!STICaller->isUsingPCRelativeCalls() &&(static_cast <bool> (!STICaller->isUsingPCRelativeCalls
() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? void (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4630, __extension__ __PRETTY_FUNCTION__))
4630 "PC Relative callers do not have a TOC and cannot share a TOC Base")(static_cast <bool> (!STICaller->isUsingPCRelativeCalls
() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? void (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4630, __extension__ __PRETTY_FUNCTION__))
;
4631#endif
4632
4633 // Callee is either a GlobalAddress or an ExternalSymbol. ExternalSymbols
4634 // don't have enough information to determine if the caller and callee share
4635 // the same TOC base, so we have to pessimistically assume they don't for
4636 // correctness.
4637 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4638 if (!G)
4639 return false;
4640
4641 const GlobalValue *GV = G->getGlobal();
4642
4643 // If the callee is preemptable, then the static linker will use a plt-stub
4644 // which saves the toc to the stack, and needs a nop after the call
4645 // instruction to convert to a toc-restore.
4646 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4647 return false;
4648
4649 // Functions with PC Relative enabled may clobber the TOC in the same DSO.
4650 // We may need a TOC restore in the situation where the caller requires a
4651 // valid TOC but the callee is PC Relative and does not.
4652 const Function *F = dyn_cast<Function>(GV);
4653 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
4654
4655 // If we have an Alias we can try to get the function from there.
4656 if (Alias) {
4657 const GlobalObject *GlobalObj = Alias->getBaseObject();
4658 F = dyn_cast<Function>(GlobalObj);
4659 }
4660
4661 // If we still have no valid function pointer we do not have enough
4662 // information to determine if the callee uses PC Relative calls so we must
4663 // assume that it does.
4664 if (!F)
4665 return false;
4666
4667 // If the callee uses PC Relative we cannot guarantee that the callee won't
4668 // clobber the TOC of the caller and so we must assume that the two
4669 // functions do not share a TOC base.
4670 const PPCSubtarget *STICallee = &TM.getSubtarget<PPCSubtarget>(*F);
4671 if (STICallee->isUsingPCRelativeCalls())
4672 return false;
4673
4674 // If the GV is not a strong definition then we need to assume it can be
4675 // replaced by another function at link time. The function that replaces
4676 // it may not share the same TOC as the caller since the callee may be
4677 // replaced by a PC Relative version of the same function.
4678 if (!GV->isStrongDefinitionForLinker())
4679 return false;
4680
4681 // The medium and large code models are expected to provide a sufficiently
4682 // large TOC to provide all data addressing needs of a module with a
4683 // single TOC.
4684 if (CodeModel::Medium == TM.getCodeModel() ||
4685 CodeModel::Large == TM.getCodeModel())
4686 return true;
4687
4688 // Any explicitly-specified sections and section prefixes must also match.
4689 // Also, if we're using -ffunction-sections, then each function is always in
4690 // a different section (the same is true for COMDAT functions).
4691 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4692 GV->getSection() != Caller->getSection())
4693 return false;
4694 if (const auto *F = dyn_cast<Function>(GV)) {
4695 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4696 return false;
4697 }
4698
4699 return true;
4700}
4701
4702static bool
4703needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4704 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4705 assert(Subtarget.is64BitELFABI())(static_cast <bool> (Subtarget.is64BitELFABI()) ? void (
0) : __assert_fail ("Subtarget.is64BitELFABI()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4705, __extension__ __PRETTY_FUNCTION__))
;
4706
4707 const unsigned PtrByteSize = 8;
4708 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4709
4710 static const MCPhysReg GPR[] = {
4711 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4712 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4713 };
4714 static const MCPhysReg VR[] = {
4715 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4716 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4717 };
4718
4719 const unsigned NumGPRs = array_lengthof(GPR);
4720 const unsigned NumFPRs = 13;
4721 const unsigned NumVRs = array_lengthof(VR);
4722 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4723
4724 unsigned NumBytes = LinkageSize;
4725 unsigned AvailableFPRs = NumFPRs;
4726 unsigned AvailableVRs = NumVRs;
4727
4728 for (const ISD::OutputArg& Param : Outs) {
4729 if (Param.Flags.isNest()) continue;
4730
4731 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags, PtrByteSize,
4732 LinkageSize, ParamAreaSize, NumBytes,
4733 AvailableFPRs, AvailableVRs))
4734 return true;
4735 }
4736 return false;
4737}
4738
4739static bool hasSameArgumentList(const Function *CallerFn, const CallBase &CB) {
4740 if (CB.arg_size() != CallerFn->arg_size())
4741 return false;
4742
4743 auto CalleeArgIter = CB.arg_begin();
4744 auto CalleeArgEnd = CB.arg_end();
4745 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4746
4747 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4748 const Value* CalleeArg = *CalleeArgIter;
4749 const Value* CallerArg = &(*CallerArgIter);
4750 if (CalleeArg == CallerArg)
4751 continue;
4752
4753 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4754 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4755 // }
4756 // 1st argument of callee is undef and has the same type as caller.
4757 if (CalleeArg->getType() == CallerArg->getType() &&
4758 isa<UndefValue>(CalleeArg))
4759 continue;
4760
4761 return false;
4762 }
4763
4764 return true;
4765}
4766
4767// Returns true if TCO is possible between the callers and callees
4768// calling conventions.
4769static bool
4770areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4771 CallingConv::ID CalleeCC) {
4772 // Tail calls are possible with fastcc and ccc.
4773 auto isTailCallableCC = [] (CallingConv::ID CC){
4774 return CC == CallingConv::C || CC == CallingConv::Fast;
4775 };
4776 if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC))
4777 return false;
4778
4779 // We can safely tail call both fastcc and ccc callees from a c calling
4780 // convention caller. If the caller is fastcc, we may have less stack space
4781 // than a non-fastcc caller with the same signature so disable tail-calls in
4782 // that case.
4783 return CallerCC == CallingConv::C || CallerCC == CalleeCC;
4784}
4785
4786bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4787 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, bool isVarArg,
4788 const SmallVectorImpl<ISD::OutputArg> &Outs,
4789 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4790 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4791
4792 if (DisableSCO && !TailCallOpt) return false;
4793
4794 // Variadic argument functions are not supported.
4795 if (isVarArg) return false;
4796
4797 auto &Caller = DAG.getMachineFunction().getFunction();
4798 // Check that the calling conventions are compatible for tco.
4799 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4800 return false;
4801
4802 // Caller contains any byval parameter is not supported.
4803 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4804 return false;
4805
4806 // Callee contains any byval parameter is not supported, too.
4807 // Note: This is a quick work around, because in some cases, e.g.
4808 // caller's stack size > callee's stack size, we are still able to apply
4809 // sibling call optimization. For example, gcc is able to do SCO for caller1
4810 // in the following example, but not for caller2.
4811 // struct test {
4812 // long int a;
4813 // char ary[56];
4814 // } gTest;
4815 // __attribute__((noinline)) int callee(struct test v, struct test *b) {
4816 // b->a = v.a;
4817 // return 0;
4818 // }
4819 // void caller1(struct test a, struct test c, struct test *b) {
4820 // callee(gTest, b); }
4821 // void caller2(struct test *b) { callee(gTest, b); }
4822 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4823 return false;
4824
4825 // If callee and caller use different calling conventions, we cannot pass
4826 // parameters on stack since offsets for the parameter area may be different.
4827 if (Caller.getCallingConv() != CalleeCC &&
4828 needStackSlotPassParameters(Subtarget, Outs))
4829 return false;
4830
4831 // All variants of 64-bit ELF ABIs without PC-Relative addressing require that
4832 // the caller and callee share the same TOC for TCO/SCO. If the caller and
4833 // callee potentially have different TOC bases then we cannot tail call since
4834 // we need to restore the TOC pointer after the call.
4835 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4836 // We cannot guarantee this for indirect calls or calls to external functions.
4837 // When PC-Relative addressing is used, the concept of the TOC is no longer
4838 // applicable so this check is not required.
4839 // Check first for indirect calls.
4840 if (!Subtarget.isUsingPCRelativeCalls() &&
4841 !isFunctionGlobalAddress(Callee) && !isa<ExternalSymbolSDNode>(Callee))
4842 return false;
4843
4844 // Check if we share the TOC base.
4845 if (!Subtarget.isUsingPCRelativeCalls() &&
4846 !callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4847 return false;
4848
4849 // TCO allows altering callee ABI, so we don't have to check further.
4850 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4851 return true;
4852
4853 if (DisableSCO) return false;
4854
4855 // If callee use the same argument list that caller is using, then we can
4856 // apply SCO on this case. If it is not, then we need to check if callee needs
4857 // stack for passing arguments.
4858 // PC Relative tail calls may not have a CallBase.
4859 // If there is no CallBase we cannot verify if we have the same argument
4860 // list so assume that we don't have the same argument list.
4861 if (CB && !hasSameArgumentList(&Caller, *CB) &&
4862 needStackSlotPassParameters(Subtarget, Outs))
4863 return false;
4864 else if (!CB && needStackSlotPassParameters(Subtarget, Outs))
4865 return false;
4866
4867 return true;
4868}
4869
4870/// IsEligibleForTailCallOptimization - Check whether the call is eligible
4871/// for tail call optimization. Targets which want to do tail call
4872/// optimization should implement this function.
4873bool
4874PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4875 CallingConv::ID CalleeCC,
4876 bool isVarArg,
4877 const SmallVectorImpl<ISD::InputArg> &Ins,
4878 SelectionDAG& DAG) const {
4879 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4880 return false;
4881
4882 // Variable argument functions are not supported.
4883 if (isVarArg)
4884 return false;
4885
4886 MachineFunction &MF = DAG.getMachineFunction();
4887 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
4888 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4889 // Functions containing by val parameters are not supported.
4890 for (unsigned i = 0; i != Ins.size(); i++) {
4891 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4892 if (Flags.isByVal()) return false;
4893 }
4894
4895 // Non-PIC/GOT tail calls are supported.
4896 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4897 return true;
4898
4899 // At the moment we can only do local tail calls (in same module, hidden
4900 // or protected) if we are generating PIC.
4901 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4902 return G->getGlobal()->hasHiddenVisibility()
4903 || G->getGlobal()->hasProtectedVisibility();
4904 }
4905
4906 return false;
4907}
4908
4909/// isCallCompatibleAddress - Return the immediate to use if the specified
4910/// 32-bit value is representable in the immediate field of a BxA instruction.
4911static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4912 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4913 if (!C) return nullptr;
4914
4915 int Addr = C->getZExtValue();
4916 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
4917 SignExtend32<26>(Addr) != Addr)
4918 return nullptr; // Top 6 bits have to be sext of immediate.
4919
4920 return DAG
4921 .getConstant(
4922 (int)C->getZExtValue() >> 2, SDLoc(Op),
4923 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
4924 .getNode();
4925}
4926
4927namespace {
4928
4929struct TailCallArgumentInfo {
4930 SDValue Arg;
4931 SDValue FrameIdxOp;
4932 int FrameIdx = 0;
4933
4934 TailCallArgumentInfo() = default;
4935};
4936
4937} // end anonymous namespace
4938
4939/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
4940static void StoreTailCallArgumentsToStackSlot(
4941 SelectionDAG &DAG, SDValue Chain,
4942 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
4943 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
4944 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
4945 SDValue Arg = TailCallArgs[i].Arg;
4946 SDValue FIN = TailCallArgs[i].FrameIdxOp;
4947 int FI = TailCallArgs[i].FrameIdx;
4948 // Store relative to framepointer.
4949 MemOpChains.push_back(DAG.getStore(
4950 Chain, dl, Arg, FIN,
4951 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4952 }
4953}
4954
4955/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
4956/// the appropriate stack slot for the tail call optimized function call.
4957static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
4958 SDValue OldRetAddr, SDValue OldFP,
4959 int SPDiff, const SDLoc &dl) {
4960 if (SPDiff) {
4961 // Calculate the new stack slot for the return address.
4962 MachineFunction &MF = DAG.getMachineFunction();
4963 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
4964 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
4965 bool isPPC64 = Subtarget.isPPC64();
4966 int SlotSize = isPPC64 ? 8 : 4;
4967 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
4968 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
4969 NewRetAddrLoc, true);
4970 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4971 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
4972 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
4973 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
4974 }
4975 return Chain;
4976}
4977
4978/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
4979/// the position of the argument.
4980static void
4981CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
4982 SDValue Arg, int SPDiff, unsigned ArgOffset,
4983 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
4984 int Offset = ArgOffset + SPDiff;
4985 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
4986 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4987 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4988 SDValue FIN = DAG.getFrameIndex(FI, VT);
4989 TailCallArgumentInfo Info;
4990 Info.Arg = Arg;
4991 Info.FrameIdxOp = FIN;
4992 Info.FrameIdx = FI;
4993 TailCallArguments.push_back(Info);
4994}
4995
4996/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
4997/// stack slot. Returns the chain as result and the loaded frame pointers in
4998/// LROpOut/FPOpout. Used when tail calling.
4999SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
5000 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
5001 SDValue &FPOpOut, const SDLoc &dl) const {
5002 if (SPDiff) {
5003 // Load the LR and FP stack slot for later adjusting.
5004 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5005 LROpOut = getReturnAddrFrameIndex(DAG);
5006 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
5007 Chain = SDValue(LROpOut.getNode(), 1);
5008 }
5009 return Chain;
5010}
5011
5012/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
5013/// by "Src" to address "Dst" of size "Size". Alignment information is
5014/// specified by the specific parameter attribute. The copy will be passed as
5015/// a byval function parameter.
5016/// Sometimes what we are copying is the end of a larger object, the part that
5017/// does not fit in registers.
5018static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
5019 SDValue Chain, ISD::ArgFlagsTy Flags,
5020 SelectionDAG &DAG, const SDLoc &dl) {
5021 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
5022 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
5023 Flags.getNonZeroByValAlign(), false, false, false,
5024 MachinePointerInfo(), MachinePointerInfo());
5025}
5026
5027/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
5028/// tail calls.
5029static void LowerMemOpCallTo(
5030 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
5031 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
5032 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
5033 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
5034 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5035 if (!isTailCall) {
5036 if (isVector) {
5037 SDValue StackPtr;
5038 if (isPPC64)
5039 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5040 else
5041 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5042 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5043 DAG.getConstant(ArgOffset, dl, PtrVT));
5044 }
5045 MemOpChains.push_back(
5046 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5047 // Calculate and remember argument location.
5048 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
5049 TailCallArguments);
5050}
5051
5052static void
5053PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
5054 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
5055 SDValue FPOp,
5056 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
5057 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
5058 // might overwrite each other in case of tail call optimization.
5059 SmallVector<SDValue, 8> MemOpChains2;
5060 // Do not flag preceding copytoreg stuff together with the following stuff.
5061 InFlag = SDValue();
5062 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
5063 MemOpChains2, dl);
5064 if (!MemOpChains2.empty())
5065 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
5066
5067 // Store the return address to the appropriate stack slot.
5068 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
5069
5070 // Emit callseq_end just before tailcall node.
5071 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5072 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
5073 InFlag = Chain.getValue(1);
5074}
5075
5076// Is this global address that of a function that can be called by name? (as
5077// opposed to something that must hold a descriptor for an indirect call).
5078static bool isFunctionGlobalAddress(SDValue Callee) {
5079 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
5080 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
5081 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
5082 return false;
5083
5084 return G->getGlobal()->getValueType()->isFunctionTy();
5085 }
5086
5087 return false;
5088}
5089
5090SDValue PPCTargetLowering::LowerCallResult(
5091 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
5092 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5093 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5094 SmallVector<CCValAssign, 16> RVLocs;
5095 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5096 *DAG.getContext());
5097
5098 CCRetInfo.AnalyzeCallResult(
5099 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold)
5100 ? RetCC_PPC_Cold
5101 : RetCC_PPC);
5102
5103 // Copy all of the result registers out of their specified physreg.
5104 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
5105 CCValAssign &VA = RVLocs[i];
5106 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5106, __extension__ __PRETTY_FUNCTION__))
;
5107
5108 SDValue Val;
5109
5110 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
5111 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5112 InFlag);
5113 Chain = Lo.getValue(1);
5114 InFlag = Lo.getValue(2);
5115 VA = RVLocs[++i]; // skip ahead to next loc
5116 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5117 InFlag);
5118 Chain = Hi.getValue(1);
5119 InFlag = Hi.getValue(2);
5120 if (!Subtarget.isLittleEndian())
5121 std::swap (Lo, Hi);
5122 Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi);
5123 } else {
5124 Val = DAG.getCopyFromReg(Chain, dl,
5125 VA.getLocReg(), VA.getLocVT(), InFlag);
5126 Chain = Val.getValue(1);
5127 InFlag = Val.getValue(2);
5128 }
5129
5130 switch (VA.getLocInfo()) {
5131 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5131)
;
5132 case CCValAssign::Full: break;
5133 case CCValAssign::AExt:
5134 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5135 break;
5136 case CCValAssign::ZExt:
5137 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
5138 DAG.getValueType(VA.getValVT()));
5139 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5140 break;
5141 case CCValAssign::SExt:
5142 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
5143 DAG.getValueType(VA.getValVT()));
5144 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5145 break;
5146 }
5147
5148 InVals.push_back(Val);
5149 }
5150
5151 return Chain;
5152}
5153
5154static bool isIndirectCall(const SDValue &Callee, SelectionDAG &DAG,
5155 const PPCSubtarget &Subtarget, bool isPatchPoint) {
5156 // PatchPoint calls are not indirect.
5157 if (isPatchPoint)
5158 return false;
5159
5160 if (isFunctionGlobalAddress(Callee) || isa<ExternalSymbolSDNode>(Callee))
5161 return false;
5162
5163 // Darwin, and 32-bit ELF can use a BLA. The descriptor based ABIs can not
5164 // becuase the immediate function pointer points to a descriptor instead of
5165 // a function entry point. The ELFv2 ABI cannot use a BLA because the function
5166 // pointer immediate points to the global entry point, while the BLA would
5167 // need to jump to the local entry point (see rL211174).
5168 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() &&
5169 isBLACompatibleAddress(Callee, DAG))
5170 return false;
5171
5172 return true;
5173}
5174
5175// AIX and 64-bit ELF ABIs w/o PCRel require a TOC save/restore around calls.
5176static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) {
5177 return Subtarget.isAIXABI() ||
5178 (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls());
5179}
5180
5181static unsigned getCallOpcode(PPCTargetLowering::CallFlags CFlags,
5182 const Function &Caller,
5183 const SDValue &Callee,
5184 const PPCSubtarget &Subtarget,
5185 const TargetMachine &TM) {
5186 if (CFlags.IsTailCall)
5187 return PPCISD::TC_RETURN;
5188
5189 // This is a call through a function pointer.
5190 if (CFlags.IsIndirect) {
5191 // AIX and the 64-bit ELF ABIs need to maintain the TOC pointer accross
5192 // indirect calls. The save of the caller's TOC pointer to the stack will be
5193 // inserted into the DAG as part of call lowering. The restore of the TOC
5194 // pointer is modeled by using a pseudo instruction for the call opcode that
5195 // represents the 2 instruction sequence of an indirect branch and link,
5196 // immediately followed by a load of the TOC pointer from the the stack save
5197 // slot into gpr2. For 64-bit ELFv2 ABI with PCRel, do not restore the TOC
5198 // as it is not saved or used.
5199 return isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC
5200 : PPCISD::BCTRL;
5201 }
5202
5203 if (Subtarget.isUsingPCRelativeCalls()) {
5204 assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI.")(static_cast <bool> (Subtarget.is64BitELFABI() &&
"PC Relative is only on ELF ABI.") ? void (0) : __assert_fail
("Subtarget.is64BitELFABI() && \"PC Relative is only on ELF ABI.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5204, __extension__ __PRETTY_FUNCTION__))
;
5205 return PPCISD::CALL_NOTOC;
5206 }
5207
5208 // The ABIs that maintain a TOC pointer accross calls need to have a nop
5209 // immediately following the call instruction if the caller and callee may
5210 // have different TOC bases. At link time if the linker determines the calls
5211 // may not share a TOC base, the call is redirected to a trampoline inserted
5212 // by the linker. The trampoline will (among other things) save the callers
5213 // TOC pointer at an ABI designated offset in the linkage area and the linker
5214 // will rewrite the nop to be a load of the TOC pointer from the linkage area
5215 // into gpr2.
5216 if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
5217 return callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL
5218 : PPCISD::CALL_NOP;
5219
5220 return PPCISD::CALL;
5221}
5222
5223static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
5224 const SDLoc &dl, const PPCSubtarget &Subtarget) {
5225 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI())
5226 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
5227 return SDValue(Dest, 0);
5228
5229 // Returns true if the callee is local, and false otherwise.
5230 auto isLocalCallee = [&]() {
5231 const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
5232 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5233 const GlobalValue *GV = G ? G->getGlobal() : nullptr;
5234
5235 return DAG.getTarget().shouldAssumeDSOLocal(*Mod, GV) &&
5236 !dyn_cast_or_null<GlobalIFunc>(GV);
5237 };
5238
5239 // The PLT is only used in 32-bit ELF PIC mode. Attempting to use the PLT in
5240 // a static relocation model causes some versions of GNU LD (2.17.50, at
5241 // least) to force BSS-PLT, instead of secure-PLT, even if all objects are
5242 // built with secure-PLT.
5243 bool UsePlt =
5244 Subtarget.is32BitELFABI() && !isLocalCallee() &&
5245 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_;
5246
5247 const auto getAIXFuncEntryPointSymbolSDNode = [&](const GlobalValue *GV) {
5248 const TargetMachine &TM = Subtarget.getTargetMachine();
5249 const TargetLoweringObjectFile *TLOF = TM.getObjFileLowering();
5250 MCSymbolXCOFF *S =
5251 cast<MCSymbolXCOFF>(TLOF->getFunctionEntryPointSymbol(GV, TM));
5252
5253 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5254 return DAG.getMCSymbol(S, PtrVT);
5255 };
5256
5257 if (isFunctionGlobalAddress(Callee)) {
5258 const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
5259
5260 if (Subtarget.isAIXABI()) {
5261 assert(!isa<GlobalIFunc>(GV) && "IFunc is not supported on AIX.")(static_cast <bool> (!isa<GlobalIFunc>(GV) &&
"IFunc is not supported on AIX.") ? void (0) : __assert_fail
("!isa<GlobalIFunc>(GV) && \"IFunc is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5261, __extension__ __PRETTY_FUNCTION__))
;
5262 return getAIXFuncEntryPointSymbolSDNode(GV);
5263 }
5264 return DAG.getTargetGlobalAddress(GV, dl, Callee.getValueType(), 0,
5265 UsePlt ? PPCII::MO_PLT : 0);
5266 }
5267
5268 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
5269 const char *SymName = S->getSymbol();
5270 if (Subtarget.isAIXABI()) {
5271 // If there exists a user-declared function whose name is the same as the
5272 // ExternalSymbol's, then we pick up the user-declared version.
5273 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5274 if (const Function *F =
5275 dyn_cast_or_null<Function>(Mod->getNamedValue(SymName)))
5276 return getAIXFuncEntryPointSymbolSDNode(F);
5277
5278 // On AIX, direct function calls reference the symbol for the function's
5279 // entry point, which is named by prepending a "." before the function's
5280 // C-linkage name. A Qualname is returned here because an external
5281 // function entry point is a csect with XTY_ER property.
5282 const auto getExternalFunctionEntryPointSymbol = [&](StringRef SymName) {
5283 auto &Context = DAG.getMachineFunction().getMMI().getContext();
5284 MCSectionXCOFF *Sec = Context.getXCOFFSection(
5285 (Twine(".") + Twine(SymName)).str(), SectionKind::getMetadata(),
5286 XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER));
5287 return Sec->getQualNameSymbol();
5288 };
5289
5290 SymName = getExternalFunctionEntryPointSymbol(SymName)->getName().data();
5291 }
5292 return DAG.getTargetExternalSymbol(SymName, Callee.getValueType(),
5293 UsePlt ? PPCII::MO_PLT : 0);
5294 }
5295
5296 // No transformation needed.
5297 assert(Callee.getNode() && "What no callee?")(static_cast <bool> (Callee.getNode() && "What no callee?"
) ? void (0) : __assert_fail ("Callee.getNode() && \"What no callee?\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5297, __extension__ __PRETTY_FUNCTION__))
;
5298 return Callee;
5299}
5300
5301static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart) {
5302 assert(CallSeqStart.getOpcode() == ISD::CALLSEQ_START &&(static_cast <bool> (CallSeqStart.getOpcode() == ISD::CALLSEQ_START
&& "Expected a CALLSEQ_STARTSDNode.") ? void (0) : __assert_fail
("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5303, __extension__ __PRETTY_FUNCTION__))
5303 "Expected a CALLSEQ_STARTSDNode.")(static_cast <bool> (CallSeqStart.getOpcode() == ISD::CALLSEQ_START
&& "Expected a CALLSEQ_STARTSDNode.") ? void (0) : __assert_fail
("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5303, __extension__ __PRETTY_FUNCTION__))
;
5304
5305 // The last operand is the chain, except when the node has glue. If the node
5306 // has glue, then the last operand is the glue, and the chain is the second
5307 // last operand.
5308 SDValue LastValue = CallSeqStart.getValue(CallSeqStart->getNumValues() - 1);
5309 if (LastValue.getValueType() != MVT::Glue)
5310 return LastValue;
5311
5312 return CallSeqStart.getValue(CallSeqStart->getNumValues() - 2);
5313}
5314
5315// Creates the node that moves a functions address into the count register
5316// to prepare for an indirect call instruction.
5317static void prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5318 SDValue &Glue, SDValue &Chain,
5319 const SDLoc &dl) {
5320 SDValue MTCTROps[] = {Chain, Callee, Glue};
5321 EVT ReturnTypes[] = {MVT::Other, MVT::Glue};
5322 Chain = DAG.getNode(PPCISD::MTCTR, dl, makeArrayRef(ReturnTypes, 2),
5323 makeArrayRef(MTCTROps, Glue.getNode() ? 3 : 2));
5324 // The glue is the second value produced.
5325 Glue = Chain.getValue(1);
5326}
5327
5328static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5329 SDValue &Glue, SDValue &Chain,
5330 SDValue CallSeqStart,
5331 const CallBase *CB, const SDLoc &dl,
5332 bool hasNest,
5333 const PPCSubtarget &Subtarget) {
5334 // Function pointers in the 64-bit SVR4 ABI do not point to the function
5335 // entry point, but to the function descriptor (the function entry point
5336 // address is part of the function descriptor though).
5337 // The function descriptor is a three doubleword structure with the
5338 // following fields: function entry point, TOC base address and
5339 // environment pointer.
5340 // Thus for a call through a function pointer, the following actions need
5341 // to be performed:
5342 // 1. Save the TOC of the caller in the TOC save area of its stack
5343 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
5344 // 2. Load the address of the function entry point from the function
5345 // descriptor.
5346 // 3. Load the TOC of the callee from the function descriptor into r2.
5347 // 4. Load the environment pointer from the function descriptor into
5348 // r11.
5349 // 5. Branch to the function entry point address.
5350 // 6. On return of the callee, the TOC of the caller needs to be
5351 // restored (this is done in FinishCall()).
5352 //
5353 // The loads are scheduled at the beginning of the call sequence, and the
5354 // register copies are flagged together to ensure that no other
5355 // operations can be scheduled in between. E.g. without flagging the
5356 // copies together, a TOC access in the caller could be scheduled between
5357 // the assignment of the callee TOC and the branch to the callee, which leads
5358 // to incorrect code.
5359
5360 // Start by loading the function address from the descriptor.
5361 SDValue LDChain = getOutputChainFromCallSeq(CallSeqStart);
5362 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
5363 ? (MachineMemOperand::MODereferenceable |
5364 MachineMemOperand::MOInvariant)
5365 : MachineMemOperand::MONone;
5366
5367 MachinePointerInfo MPI(CB ? CB->getCalledOperand() : nullptr);
5368
5369 // Registers used in building the DAG.
5370 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister();
5371 const MCRegister TOCReg = Subtarget.getTOCPointerRegister();
5372
5373 // Offsets of descriptor members.
5374 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset();
5375 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset();
5376
5377 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5378 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4;
5379
5380 // One load for the functions entry point address.
5381 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5382 Alignment, MMOFlags);
5383
5384 // One for loading the TOC anchor for the module that contains the called
5385 // function.
5386 SDValue TOCOff = DAG.getIntPtrConstant(TOCAnchorOffset, dl);
5387 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5388 SDValue TOCPtr =
5389 DAG.getLoad(RegVT, dl, LDChain, AddTOC,
5390 MPI.getWithOffset(TOCAnchorOffset), Alignment, MMOFlags);
5391
5392 // One for loading the environment pointer.
5393 SDValue PtrOff = DAG.getIntPtrConstant(EnvPtrOffset, dl);
5394 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5395 SDValue LoadEnvPtr =
5396 DAG.getLoad(RegVT, dl, LDChain, AddPtr,
5397 MPI.getWithOffset(EnvPtrOffset), Alignment, MMOFlags);
5398
5399
5400 // Then copy the newly loaded TOC anchor to the TOC pointer.
5401 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, TOCReg, TOCPtr, Glue);
5402 Chain = TOCVal.getValue(0);
5403 Glue = TOCVal.getValue(1);
5404
5405 // If the function call has an explicit 'nest' parameter, it takes the
5406 // place of the environment pointer.
5407 assert((!hasNest || !Subtarget.isAIXABI()) &&(static_cast <bool> ((!hasNest || !Subtarget.isAIXABI()
) && "Nest parameter is not supported on AIX.") ? void
(0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5408, __extension__ __PRETTY_FUNCTION__))
5408 "Nest parameter is not supported on AIX.")(static_cast <bool> ((!hasNest || !Subtarget.isAIXABI()
) && "Nest parameter is not supported on AIX.") ? void
(0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5408, __extension__ __PRETTY_FUNCTION__))
;
5409 if (!hasNest) {
5410 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, EnvPtrReg, LoadEnvPtr, Glue);
5411 Chain = EnvVal.getValue(0);
5412 Glue = EnvVal.getValue(1);
5413 }
5414
5415 // The rest of the indirect call sequence is the same as the non-descriptor
5416 // DAG.
5417 prepareIndirectCall(DAG, LoadFuncPtr, Glue, Chain, dl);
5418}
5419
5420static void
5421buildCallOperands(SmallVectorImpl<SDValue> &Ops,
5422 PPCTargetLowering::CallFlags CFlags, const SDLoc &dl,
5423 SelectionDAG &DAG,
5424 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
5425 SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff,
5426 const PPCSubtarget &Subtarget) {
5427 const bool IsPPC64 = Subtarget.isPPC64();
5428 // MVT for a general purpose register.
5429 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5430
5431 // First operand is always the chain.
5432 Ops.push_back(Chain);
5433
5434 // If it's a direct call pass the callee as the second operand.
5435 if (!CFlags.IsIndirect)
5436 Ops.push_back(Callee);
5437 else {
5438 assert(!CFlags.IsPatchPoint && "Patch point calls are not indirect.")(static_cast <bool> (!CFlags.IsPatchPoint && "Patch point calls are not indirect."
) ? void (0) : __assert_fail ("!CFlags.IsPatchPoint && \"Patch point calls are not indirect.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5438, __extension__ __PRETTY_FUNCTION__))
;
5439
5440 // For the TOC based ABIs, we have saved the TOC pointer to the linkage area
5441 // on the stack (this would have been done in `LowerCall_64SVR4` or
5442 // `LowerCall_AIX`). The call instruction is a pseudo instruction that
5443 // represents both the indirect branch and a load that restores the TOC
5444 // pointer from the linkage area. The operand for the TOC restore is an add
5445 // of the TOC save offset to the stack pointer. This must be the second
5446 // operand: after the chain input but before any other variadic arguments.
5447 // For 64-bit ELFv2 ABI with PCRel, do not restore the TOC as it is not
5448 // saved or used.
5449 if (isTOCSaveRestoreRequired(Subtarget)) {
5450 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister();
5451
5452 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5453 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5454 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5455 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5456 Ops.push_back(AddTOC);
5457 }
5458
5459 // Add the register used for the environment pointer.
5460 if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest)
5461 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(),
5462 RegVT));
5463
5464
5465 // Add CTR register as callee so a bctr can be emitted later.
5466 if (CFlags.IsTailCall)
5467 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5468 }
5469
5470 // If this is a tail call add stack pointer delta.
5471 if (CFlags.IsTailCall)
5472 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
5473
5474 // Add argument registers to the end of the list so that they are known live
5475 // into the call.
5476 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
5477 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5478 RegsToPass[i].second.getValueType()));
5479
5480 // We cannot add R2/X2 as an operand here for PATCHPOINT, because there is
5481 // no way to mark dependencies as implicit here.
5482 // We will add the R2/X2 dependency in EmitInstrWithCustomInserter.
5483 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) &&
5484 !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls())
5485 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT));
5486
5487 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
5488 if (CFlags.IsVarArg && Subtarget.is32BitELFABI())
5489 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5490
5491 // Add a register mask operand representing the call-preserved registers.
5492 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
5493 const uint32_t *Mask =
5494 TRI->getCallPreservedMask(DAG.getMachineFunction(), CFlags.CallConv);
5495 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5495, __extension__ __PRETTY_FUNCTION__))
;
5496 Ops.push_back(DAG.getRegisterMask(Mask));
5497
5498 // If the glue is valid, it is the last operand.
5499 if (Glue.getNode())
5500 Ops.push_back(Glue);
5501}
5502
5503SDValue PPCTargetLowering::FinishCall(
5504 CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
5505 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue,
5506 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5507 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
5508 SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const {
5509
5510 if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) ||
5511 Subtarget.isAIXABI())
5512 setUsesTOCBasePtr(DAG);
5513
5514 unsigned CallOpc =
5515 getCallOpcode(CFlags, DAG.getMachineFunction().getFunction(), Callee,
5516 Subtarget, DAG.getTarget());
5517
5518 if (!CFlags.IsIndirect)
5519 Callee = transformCallee(Callee, DAG, dl, Subtarget);
5520 else if (Subtarget.usesFunctionDescriptors())
5521 prepareDescriptorIndirectCall(DAG, Callee, Glue, Chain, CallSeqStart, CB,
5522 dl, CFlags.HasNest, Subtarget);
5523 else
5524 prepareIndirectCall(DAG, Callee, Glue, Chain, dl);
5525
5526 // Build the operand list for the call instruction.
5527 SmallVector<SDValue, 8> Ops;
5528 buildCallOperands(Ops, CFlags, dl, DAG, RegsToPass, Glue, Chain, Callee,
5529 SPDiff, Subtarget);
5530
5531 // Emit tail call.
5532 if (CFlags.IsTailCall) {
5533 // Indirect tail call when using PC Relative calls do not have the same
5534 // constraints.
5535 assert(((Callee.getOpcode() == ISD::Register &&(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
5536 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
5537 Callee.getOpcode() == ISD::TargetExternalSymbol ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
5538 Callee.getOpcode() == ISD::TargetGlobalAddress ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
5539 isa<ConstantSDNode>(Callee) ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
5540 (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) &&(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
5541 "Expecting a global address, external symbol, absolute value, "(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
5542 "register or an indirect tail call when PC Relative calls are "(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
5543 "used.")(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
;
5544 // PC Relative calls also use TC_RETURN as the way to mark tail calls.
5545 assert(CallOpc == PPCISD::TC_RETURN &&(static_cast <bool> (CallOpc == PPCISD::TC_RETURN &&
"Unexpected call opcode for a tail call.") ? void (0) : __assert_fail
("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5546, __extension__ __PRETTY_FUNCTION__))
5546 "Unexpected call opcode for a tail call.")(static_cast <bool> (CallOpc == PPCISD::TC_RETURN &&
"Unexpected call opcode for a tail call.") ? void (0) : __assert_fail
("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5546, __extension__ __PRETTY_FUNCTION__))
;
5547 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
5548 return DAG.getNode(CallOpc, dl, MVT::Other, Ops);
5549 }
5550
5551 std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}};
5552 Chain = DAG.getNode(CallOpc, dl, ReturnTypes, Ops);
5553 DAG.addNoMergeSiteInfo(Chain.getNode(), CFlags.NoMerge);
5554 Glue = Chain.getValue(1);
5555
5556 // When performing tail call optimization the callee pops its arguments off
5557 // the stack. Account for this here so these bytes can be pushed back on in
5558 // PPCFrameLowering::eliminateCallFramePseudoInstr.
5559 int BytesCalleePops = (CFlags.CallConv == CallingConv::Fast &&
5560 getTargetMachine().Options.GuaranteedTailCallOpt)
5561 ? NumBytes
5562 : 0;
5563
5564 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5565 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5566 Glue, dl);
5567 Glue = Chain.getValue(1);
5568
5569 return LowerCallResult(Chain, Glue, CFlags.CallConv, CFlags.IsVarArg, Ins, dl,
5570 DAG, InVals);
5571}
5572
5573SDValue
5574PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5575 SmallVectorImpl<SDValue> &InVals) const {
5576 SelectionDAG &DAG = CLI.DAG;
5577 SDLoc &dl = CLI.DL;
5578 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5579 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5580 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5581 SDValue Chain = CLI.Chain;
5582 SDValue Callee = CLI.Callee;
5583 bool &isTailCall = CLI.IsTailCall;
5584 CallingConv::ID CallConv = CLI.CallConv;
5585 bool isVarArg = CLI.IsVarArg;
5586 bool isPatchPoint = CLI.IsPatchPoint;
5587 const CallBase *CB = CLI.CB;
5588
5589 if (isTailCall) {
5590 if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall()))
5591 isTailCall = false;
5592 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5593 isTailCall = IsEligibleForTailCallOptimization_64SVR4(
5594 Callee, CallConv, CB, isVarArg, Outs, Ins, DAG);
5595 else
5596 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5597 Ins, DAG);
5598 if (isTailCall) {
5599 ++NumTailCalls;
5600 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5601 ++NumSiblingCalls;
5602
5603 // PC Relative calls no longer guarantee that the callee is a Global
5604 // Address Node. The callee could be an indirect tail call in which
5605 // case the SDValue for the callee could be a load (to load the address
5606 // of a function pointer) or it may be a register copy (to move the
5607 // address of the callee from a function parameter into a virtual
5608 // register). It may also be an ExternalSymbolSDNode (ex memcopy).
5609 assert((Subtarget.isUsingPCRelativeCalls() ||(static_cast <bool> ((Subtarget.isUsingPCRelativeCalls(
) || isa<GlobalAddressSDNode>(Callee)) && "Callee should be an llvm::Function object."
) ? void (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5611, __extension__ __PRETTY_FUNCTION__))
5610 isa<GlobalAddressSDNode>(Callee)) &&(static_cast <bool> ((Subtarget.isUsingPCRelativeCalls(
) || isa<GlobalAddressSDNode>(Callee)) && "Callee should be an llvm::Function object."
) ? void (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5611, __extension__ __PRETTY_FUNCTION__))
5611 "Callee should be an llvm::Function object.")(static_cast <bool> ((Subtarget.isUsingPCRelativeCalls(
) || isa<GlobalAddressSDNode>(Callee)) && "Callee should be an llvm::Function object."
) ? void (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5611, __extension__ __PRETTY_FUNCTION__))
;
5612
5613 LLVM_DEBUG(dbgs() << "TCO caller: " << DAG.getMachineFunction().getName()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
5614 << "\nTCO callee: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
;
5615 LLVM_DEBUG(Callee.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { Callee.dump(); } } while (false)
;
5616 }
5617 }
5618
5619 if (!isTailCall && CB && CB->isMustTailCall())
5620 report_fatal_error("failed to perform tail call elimination on a call "
5621 "site marked musttail");
5622
5623 // When long calls (i.e. indirect calls) are always used, calls are always
5624 // made via function pointer. If we have a function name, first translate it
5625 // into a pointer.
5626 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5627 !isTailCall)
5628 Callee = LowerGlobalAddress(Callee, DAG);
5629
5630 CallFlags CFlags(
5631 CallConv, isTailCall, isVarArg, isPatchPoint,
5632 isIndirectCall(Callee, DAG, Subtarget, isPatchPoint),
5633 // hasNest
5634 Subtarget.is64BitELFABI() &&
5635 any_of(Outs, [](ISD::OutputArg Arg) { return Arg.Flags.isNest(); }),
5636 CLI.NoMerge);
5637
5638 if (Subtarget.isAIXABI())
5639 return LowerCall_AIX(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5640 InVals, CB);
5641
5642 assert(Subtarget.isSVR4ABI())(static_cast <bool> (Subtarget.isSVR4ABI()) ? void (0) :
__assert_fail ("Subtarget.isSVR4ABI()", "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5642, __extension__ __PRETTY_FUNCTION__))
;
5643 if (Subtarget.isPPC64())
5644 return LowerCall_64SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5645 InVals, CB);
5646 return LowerCall_32SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5647 InVals, CB);
5648}
5649
5650SDValue PPCTargetLowering::LowerCall_32SVR4(
5651 SDValue Chain, SDValue Callee, CallFlags CFlags,
5652 const SmallVectorImpl<ISD::OutputArg> &Outs,
5653 const SmallVectorImpl<SDValue> &OutVals,
5654 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5655 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5656 const CallBase *CB) const {
5657 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5658 // of the 32-bit SVR4 ABI stack frame layout.
5659
5660 const CallingConv::ID CallConv = CFlags.CallConv;
5661 const bool IsVarArg = CFlags.IsVarArg;
5662 const bool IsTailCall = CFlags.IsTailCall;
5663
5664 assert((CallConv == CallingConv::C ||(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5666, __extension__ __PRETTY_FUNCTION__))
5665 CallConv == CallingConv::Cold ||(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5666, __extension__ __PRETTY_FUNCTION__))
5666 CallConv == CallingConv::Fast) && "Unknown calling convention!")(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5666, __extension__ __PRETTY_FUNCTION__))
;
5667
5668 const Align PtrAlign(4);
5669
5670 MachineFunction &MF = DAG.getMachineFunction();
5671
5672 // Mark this function as potentially containing a function that contains a
5673 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5674 // and restoring the callers stack pointer in this functions epilog. This is
5675 // done because by tail calling the called function might overwrite the value
5676 // in this function's (MF) stack pointer stack slot 0(SP).
5677 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5678 CallConv == CallingConv::Fast)
5679 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5680
5681 // Count how many bytes are to be pushed on the stack, including the linkage
5682 // area, parameter list area and the part of the local variable space which
5683 // contains copies of aggregates which are passed by value.
5684
5685 // Assign locations to all of the outgoing arguments.
5686 SmallVector<CCValAssign, 16> ArgLocs;
5687 PPCCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
5688
5689 // Reserve space for the linkage area on the stack.
5690 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5691 PtrAlign);
5692 if (useSoftFloat())
5693 CCInfo.PreAnalyzeCallOperands(Outs);
5694
5695 if (IsVarArg) {
5696 // Handle fixed and variable vector arguments differently.
5697 // Fixed vector arguments go into registers as long as registers are
5698 // available. Variable vector arguments always go into memory.
5699 unsigned NumArgs = Outs.size();
5700
5701 for (unsigned i = 0; i != NumArgs; ++i) {
5702 MVT ArgVT = Outs[i].VT;
5703 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5704 bool Result;
5705
5706 if (Outs[i].IsFixed) {
5707 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5708 CCInfo);
5709 } else {
5710 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
5711 ArgFlags, CCInfo);
5712 }
5713
5714 if (Result) {
5715#ifndef NDEBUG
5716 errs() << "Call operand #" << i << " has unhandled type "
5717 << EVT(ArgVT).getEVTString() << "\n";
5718#endif
5719 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-14~++20210926122410+d23fd8ae8906/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5719)
;
5720 }
5721 }
5722 } else {
5723 // All arguments are treated the same.
5724 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
5725 }
5726 CCInfo.clearWasPPCF128();
5727
5728 // Assign locations to all of the outgoing aggregate by value arguments.
5729 SmallVector<CCValAssign, 16> ByValArgLocs;
5730 CCState CCByValInfo(CallConv, IsVarArg, MF, ByValArgLocs, *DAG.getContext());
5731
5732 // Reserve stack space for the allocations in CCInfo.
5733 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrAlign);
5734
5735 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
5736
5737 // Size of the linkage area, parameter list area and the part of the local
5738 // space variable where copies of aggregates which are passed by value