Bug Summary

File:build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Warning:line 9989, column 31
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name PPCISelLowering.cpp -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-16/lib/clang/16.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/lib/Target/PowerPC -I include -I /build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-16/lib/clang/16.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/= -O2 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -Wno-misleading-indentation -std=c++17 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/= -ferror-limit 19 -fvisibility=hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-09-04-125545-48738-1 -x c++ /build/llvm-toolchain-snapshot-16~++20220904122748+c444af1c20b3/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
14#include "MCTargetDesc/PPCPredicates.h"
15#include "PPC.h"
16#include "PPCCCState.h"
17#include "PPCCallingConv.h"
18#include "PPCFrameLowering.h"
19#include "PPCInstrInfo.h"
20#include "PPCMachineFunctionInfo.h"
21#include "PPCPerfectShuffle.h"
22#include "PPCRegisterInfo.h"
23#include "PPCSubtarget.h"
24#include "PPCTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/None.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
36#include "llvm/ADT/StringSwitch.h"
37#include "llvm/CodeGen/CallingConvLower.h"
38#include "llvm/CodeGen/ISDOpcodes.h"
39#include "llvm/CodeGen/MachineBasicBlock.h"
40#include "llvm/CodeGen/MachineFrameInfo.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineInstr.h"
43#include "llvm/CodeGen/MachineInstrBuilder.h"
44#include "llvm/CodeGen/MachineJumpTableInfo.h"
45#include "llvm/CodeGen/MachineLoopInfo.h"
46#include "llvm/CodeGen/MachineMemOperand.h"
47#include "llvm/CodeGen/MachineModuleInfo.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/RuntimeLibcalls.h"
51#include "llvm/CodeGen/SelectionDAG.h"
52#include "llvm/CodeGen/SelectionDAGNodes.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetLowering.h"
55#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
56#include "llvm/CodeGen/TargetRegisterInfo.h"
57#include "llvm/CodeGen/ValueTypes.h"
58#include "llvm/IR/CallingConv.h"
59#include "llvm/IR/Constant.h"
60#include "llvm/IR/Constants.h"
61#include "llvm/IR/DataLayout.h"
62#include "llvm/IR/DebugLoc.h"
63#include "llvm/IR/DerivedTypes.h"
64#include "llvm/IR/Function.h"
65#include "llvm/IR/GlobalValue.h"
66#include "llvm/IR/IRBuilder.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/Intrinsics.h"
69#include "llvm/IR/IntrinsicsPowerPC.h"
70#include "llvm/IR/Module.h"
71#include "llvm/IR/Type.h"
72#include "llvm/IR/Use.h"
73#include "llvm/IR/Value.h"
74#include "llvm/MC/MCContext.h"
75#include "llvm/MC/MCExpr.h"
76#include "llvm/MC/MCRegisterInfo.h"
77#include "llvm/MC/MCSectionXCOFF.h"
78#include "llvm/MC/MCSymbolXCOFF.h"
79#include "llvm/Support/AtomicOrdering.h"
80#include "llvm/Support/BranchProbability.h"
81#include "llvm/Support/Casting.h"
82#include "llvm/Support/CodeGen.h"
83#include "llvm/Support/CommandLine.h"
84#include "llvm/Support/Compiler.h"
85#include "llvm/Support/Debug.h"
86#include "llvm/Support/ErrorHandling.h"
87#include "llvm/Support/Format.h"
88#include "llvm/Support/KnownBits.h"
89#include "llvm/Support/MachineValueType.h"
90#include "llvm/Support/MathExtras.h"
91#include "llvm/Support/raw_ostream.h"
92#include "llvm/Target/TargetMachine.h"
93#include "llvm/Target/TargetOptions.h"
94#include <algorithm>
95#include <cassert>
96#include <cstdint>
97#include <iterator>
98#include <list>
99#include <utility>
100#include <vector>
101
102using namespace llvm;
103
104#define DEBUG_TYPE"ppc-lowering" "ppc-lowering"
105
106static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
107cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
108
109static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
110cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
111
112static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
113cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
114
115static cl::opt<bool> DisableSCO("disable-ppc-sco",
116cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
117
118static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
119cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
120
121static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
122cl::desc("use absolute jump tables on ppc"), cl::Hidden);
123
124static cl::opt<bool> EnableQuadwordAtomics(
125 "ppc-quadword-atomics",
126 cl::desc("enable quadword lock-free atomic operations"), cl::init(false),
127 cl::Hidden);
128
129static cl::opt<bool>
130 DisablePerfectShuffle("ppc-disable-perfect-shuffle",
131 cl::desc("disable vector permute decomposition"),
132 cl::init(true), cl::Hidden);
133
134cl::opt<bool> DisableAutoPairedVecSt(
135 "disable-auto-paired-vec-st",
136 cl::desc("disable automatically generated 32byte paired vector stores"),
137 cl::init(true), cl::Hidden);
138
139STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"ppc-lowering", "NumTailCalls"
, "Number of tail calls"}
;
140STATISTIC(NumSiblingCalls, "Number of sibling calls")static llvm::Statistic NumSiblingCalls = {"ppc-lowering", "NumSiblingCalls"
, "Number of sibling calls"}
;
141STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM")static llvm::Statistic ShufflesHandledWithVPERM = {"ppc-lowering"
, "ShufflesHandledWithVPERM", "Number of shuffles lowered to a VPERM"
}
;
142STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed")static llvm::Statistic NumDynamicAllocaProbed = {"ppc-lowering"
, "NumDynamicAllocaProbed", "Number of dynamic stack allocation probed"
}
;
143
144static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
145
146static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
147
148static const char AIXSSPCanaryWordName[] = "__ssp_canary_word";
149
150// FIXME: Remove this once the bug has been fixed!
151extern cl::opt<bool> ANDIGlueBug;
152
153PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
154 const PPCSubtarget &STI)
155 : TargetLowering(TM), Subtarget(STI) {
156 // Initialize map that relates the PPC addressing modes to the computed flags
157 // of a load/store instruction. The map is used to determine the optimal
158 // addressing mode when selecting load and stores.
159 initializeAddrModeMap();
160 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
161 // arguments are at least 4/8 bytes aligned.
162 bool isPPC64 = Subtarget.isPPC64();
163 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
164
165 // Set up the register classes.
166 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
167 if (!useSoftFloat()) {
168 if (hasSPE()) {
169 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
170 // EFPU2 APU only supports f32
171 if (!Subtarget.hasEFPU2())
172 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
173 } else {
174 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
175 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
176 }
177 }
178
179 // Match BITREVERSE to customized fast code sequence in the td file.
180 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
181 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
182
183 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
184 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
185
186 // Custom lower inline assembly to check for special registers.
187 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
188 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom);
189
190 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
191 for (MVT VT : MVT::integer_valuetypes()) {
192 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
193 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
194 }
195
196 if (Subtarget.isISA3_0()) {
197 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal);
198 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal);
199 setTruncStoreAction(MVT::f64, MVT::f16, Legal);
200 setTruncStoreAction(MVT::f32, MVT::f16, Legal);
201 } else {
202 // No extending loads from f16 or HW conversions back and forth.
203 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
204 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
205 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
206 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
207 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
208 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
209 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
210 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
211 }
212
213 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
214
215 // PowerPC has pre-inc load and store's.
216 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
217 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
218 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
219 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
220 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
221 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
222 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
223 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
224 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
225 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
226 if (!Subtarget.hasSPE()) {
227 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
228 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
229 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
230 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
231 }
232
233 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
234 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
235 for (MVT VT : ScalarIntVTs) {
236 setOperationAction(ISD::ADDC, VT, Legal);
237 setOperationAction(ISD::ADDE, VT, Legal);
238 setOperationAction(ISD::SUBC, VT, Legal);
239 setOperationAction(ISD::SUBE, VT, Legal);
240 }
241
242 if (Subtarget.useCRBits()) {
243 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
244
245 if (isPPC64 || Subtarget.hasFPCVT()) {
246 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Promote);
247 AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1,
248 isPPC64 ? MVT::i64 : MVT::i32);
249 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Promote);
250 AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1,
251 isPPC64 ? MVT::i64 : MVT::i32);
252
253 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
254 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
255 isPPC64 ? MVT::i64 : MVT::i32);
256 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
257 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
258 isPPC64 ? MVT::i64 : MVT::i32);
259
260 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i1, Promote);
261 AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1,
262 isPPC64 ? MVT::i64 : MVT::i32);
263 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i1, Promote);
264 AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1,
265 isPPC64 ? MVT::i64 : MVT::i32);
266
267 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
268 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1,
269 isPPC64 ? MVT::i64 : MVT::i32);
270 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
271 AddPromotedToType(ISD::FP_TO_UINT, MVT::i1,
272 isPPC64 ? MVT::i64 : MVT::i32);
273 } else {
274 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom);
275 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom);
276 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
277 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
278 }
279
280 // PowerPC does not support direct load/store of condition registers.
281 setOperationAction(ISD::LOAD, MVT::i1, Custom);
282 setOperationAction(ISD::STORE, MVT::i1, Custom);
283
284 // FIXME: Remove this once the ANDI glue bug is fixed:
285 if (ANDIGlueBug)
286 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
287
288 for (MVT VT : MVT::integer_valuetypes()) {
289 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
290 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
291 setTruncStoreAction(VT, MVT::i1, Expand);
292 }
293
294 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
295 }
296
297 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
298 // PPC (the libcall is not available).
299 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
300 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
301 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::ppcf128, Custom);
302 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::ppcf128, Custom);
303
304 // We do not currently implement these libm ops for PowerPC.
305 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
306 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
307 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
308 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
309 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
310 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
311
312 // PowerPC has no SREM/UREM instructions unless we are on P9
313 // On P9 we may use a hardware instruction to compute the remainder.
314 // When the result of both the remainder and the division is required it is
315 // more efficient to compute the remainder from the result of the division
316 // rather than use the remainder instruction. The instructions are legalized
317 // directly because the DivRemPairsPass performs the transformation at the IR
318 // level.
319 if (Subtarget.isISA3_0()) {
320 setOperationAction(ISD::SREM, MVT::i32, Legal);
321 setOperationAction(ISD::UREM, MVT::i32, Legal);
322 setOperationAction(ISD::SREM, MVT::i64, Legal);
323 setOperationAction(ISD::UREM, MVT::i64, Legal);
324 } else {
325 setOperationAction(ISD::SREM, MVT::i32, Expand);
326 setOperationAction(ISD::UREM, MVT::i32, Expand);
327 setOperationAction(ISD::SREM, MVT::i64, Expand);
328 setOperationAction(ISD::UREM, MVT::i64, Expand);
329 }
330
331 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
332 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
333 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
334 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
335 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
336 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
337 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
338 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
339 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
340
341 // Handle constrained floating-point operations of scalar.
342 // TODO: Handle SPE specific operation.
343 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
344 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
345 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
346 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
347 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
348
349 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
350 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
351 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
352 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
353
354 if (!Subtarget.hasSPE()) {
355 setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal);
356 setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal);
357 }
358
359 if (Subtarget.hasVSX()) {
360 setOperationAction(ISD::STRICT_FRINT, MVT::f32, Legal);
361 setOperationAction(ISD::STRICT_FRINT, MVT::f64, Legal);
362 }
363
364 if (Subtarget.hasFSQRT()) {
365 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
366 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
367 }
368
369 if (Subtarget.hasFPRND()) {
370 setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal);
371 setOperationAction(ISD::STRICT_FCEIL, MVT::f32, Legal);
372 setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal);
373 setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal);
374
375 setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal);
376 setOperationAction(ISD::STRICT_FCEIL, MVT::f64, Legal);
377 setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal);
378 setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal);
379 }
380
381 // We don't support sin/cos/sqrt/fmod/pow
382 setOperationAction(ISD::FSIN , MVT::f64, Expand);
383 setOperationAction(ISD::FCOS , MVT::f64, Expand);
384 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
385 setOperationAction(ISD::FREM , MVT::f64, Expand);
386 setOperationAction(ISD::FPOW , MVT::f64, Expand);
387 setOperationAction(ISD::FSIN , MVT::f32, Expand);
388 setOperationAction(ISD::FCOS , MVT::f32, Expand);
389 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
390 setOperationAction(ISD::FREM , MVT::f32, Expand);
391 setOperationAction(ISD::FPOW , MVT::f32, Expand);
392
393 // MASS transformation for LLVM intrinsics with replicating fast-math flag
394 // to be consistent to PPCGenScalarMASSEntries pass
395 if (TM.getOptLevel() == CodeGenOpt::Aggressive) {
396 setOperationAction(ISD::FSIN , MVT::f64, Custom);
397 setOperationAction(ISD::FCOS , MVT::f64, Custom);
398 setOperationAction(ISD::FPOW , MVT::f64, Custom);
399 setOperationAction(ISD::FLOG, MVT::f64, Custom);
400 setOperationAction(ISD::FLOG10, MVT::f64, Custom);
401 setOperationAction(ISD::FEXP, MVT::f64, Custom);
402 setOperationAction(ISD::FSIN , MVT::f32, Custom);
403 setOperationAction(ISD::FCOS , MVT::f32, Custom);
404 setOperationAction(ISD::FPOW , MVT::f32, Custom);
405 setOperationAction(ISD::FLOG, MVT::f32, Custom);
406 setOperationAction(ISD::FLOG10, MVT::f32, Custom);
407 setOperationAction(ISD::FEXP, MVT::f32, Custom);
408 }
409
410 if (Subtarget.hasSPE()) {
411 setOperationAction(ISD::FMA , MVT::f64, Expand);
412 setOperationAction(ISD::FMA , MVT::f32, Expand);
413 } else {
414 setOperationAction(ISD::FMA , MVT::f64, Legal);
415 setOperationAction(ISD::FMA , MVT::f32, Legal);
416 }
417
418 if (Subtarget.hasSPE())
419 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
420
421 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
422
423 // If we're enabling GP optimizations, use hardware square root
424 if (!Subtarget.hasFSQRT() &&
425 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
426 Subtarget.hasFRE()))
427 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
428
429 if (!Subtarget.hasFSQRT() &&
430 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
431 Subtarget.hasFRES()))
432 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
433
434 if (Subtarget.hasFCPSGN()) {
435 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
436 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
437 } else {
438 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
439 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
440 }
441
442 if (Subtarget.hasFPRND()) {
443 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
444 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
445 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
446 setOperationAction(ISD::FROUND, MVT::f64, Legal);
447
448 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
449 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
450 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
451 setOperationAction(ISD::FROUND, MVT::f32, Legal);
452 }
453
454 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
455 // to speed up scalar BSWAP64.
456 // CTPOP or CTTZ were introduced in P8/P9 respectively
457 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
458 if (Subtarget.hasP9Vector() && Subtarget.isPPC64())
459 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
460 else
461 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
462 if (Subtarget.isISA3_0()) {
463 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
464 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
465 } else {
466 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
467 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
468 }
469
470 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
471 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
472 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
473 } else {
474 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
475 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
476 }
477
478 // PowerPC does not have ROTR
479 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
480 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
481
482 if (!Subtarget.useCRBits()) {
483 // PowerPC does not have Select
484 setOperationAction(ISD::SELECT, MVT::i32, Expand);
485 setOperationAction(ISD::SELECT, MVT::i64, Expand);
486 setOperationAction(ISD::SELECT, MVT::f32, Expand);
487 setOperationAction(ISD::SELECT, MVT::f64, Expand);
488 }
489
490 // PowerPC wants to turn select_cc of FP into fsel when possible.
491 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
492 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
493
494 // PowerPC wants to optimize integer setcc a bit
495 if (!Subtarget.useCRBits())
496 setOperationAction(ISD::SETCC, MVT::i32, Custom);
497
498 if (Subtarget.hasFPU()) {
499 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal);
500 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal);
501 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal);
502
503 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
504 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
505 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal);
506 }
507
508 // PowerPC does not have BRCOND which requires SetCC
509 if (!Subtarget.useCRBits())
510 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
511
512 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
513
514 if (Subtarget.hasSPE()) {
515 // SPE has built-in conversions
516 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal);
517 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Legal);
518 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Legal);
519 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
520 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
521 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
522
523 // SPE supports signaling compare of f32/f64.
524 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
525 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
526 } else {
527 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
528 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
529 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
530
531 // PowerPC does not have [U|S]INT_TO_FP
532 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Expand);
533 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Expand);
534 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
535 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
536 }
537
538 if (Subtarget.hasDirectMove() && isPPC64) {
539 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
540 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
541 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
542 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
543 if (TM.Options.UnsafeFPMath) {
544 setOperationAction(ISD::LRINT, MVT::f64, Legal);
545 setOperationAction(ISD::LRINT, MVT::f32, Legal);
546 setOperationAction(ISD::LLRINT, MVT::f64, Legal);
547 setOperationAction(ISD::LLRINT, MVT::f32, Legal);
548 setOperationAction(ISD::LROUND, MVT::f64, Legal);
549 setOperationAction(ISD::LROUND, MVT::f32, Legal);
550 setOperationAction(ISD::LLROUND, MVT::f64, Legal);
551 setOperationAction(ISD::LLROUND, MVT::f32, Legal);
552 }
553 } else {
554 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
555 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
556 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
557 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
558 }
559
560 // We cannot sextinreg(i1). Expand to shifts.
561 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
562
563 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
564 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
565 // support continuation, user-level threading, and etc.. As a result, no
566 // other SjLj exception interfaces are implemented and please don't build
567 // your own exception handling based on them.
568 // LLVM/Clang supports zero-cost DWARF exception handling.
569 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
570 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
571
572 // We want to legalize GlobalAddress and ConstantPool nodes into the
573 // appropriate instructions to materialize the address.
574 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
576 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
577 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
578 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
579 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
580 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
581 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
582 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
583 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
584
585 // TRAP is legal.
586 setOperationAction(ISD::TRAP, MVT::Other, Legal);
587
588 // TRAMPOLINE is custom lowered.
589 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
590 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
591
592 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
593 setOperationAction(ISD::VASTART , MVT::Other, Custom);
594
595 if (Subtarget.is64BitELFABI()) {
596 // VAARG always uses double-word chunks, so promote anything smaller.
597 setOperationAction(ISD::VAARG, MVT::i1, Promote);
598 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
599 setOperationAction(ISD::VAARG, MVT::i8, Promote);
600 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
601 setOperationAction(ISD::VAARG, MVT::i16, Promote);
602 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
603 setOperationAction(ISD::VAARG, MVT::i32, Promote);
604 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
605 setOperationAction(ISD::VAARG, MVT::Other, Expand);
606 } else if (Subtarget.is32BitELFABI()) {
607 // VAARG is custom lowered with the 32-bit SVR4 ABI.
608 setOperationAction(ISD::VAARG, MVT::Other, Custom);
609 setOperationAction(ISD::VAARG, MVT::i64, Custom);
610 } else
611 setOperationAction(ISD::VAARG, MVT::Other, Expand);
612
613 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
614 if (Subtarget.is32BitELFABI())
615 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
616 else
617 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
618
619 // Use the default implementation.
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
621 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
622 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
623 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
624 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
625 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
626 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
627 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
628 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
629
630 // We want to custom lower some of our intrinsics.
631 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
632 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f64, Custom);
633 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::ppcf128, Custom);
634 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
635 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f64, Custom);
636
637 // To handle counter-based loop conditions.
638 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
639
640 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
641 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
642 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
643 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
644
645 // Comparisons that require checking two conditions.
646 if (Subtarget.hasSPE()) {
647 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
648 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
649 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
650 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
651 }
652 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
653 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
654 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
655 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
656 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
657 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
658 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
659 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
660 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
661 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
662 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
663 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
664
665 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
666 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
667
668 if (Subtarget.has64BitSupport()) {
669 // They also have instructions for converting between i64 and fp.
670 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
671 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand);
672 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
673 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand);
674 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
675 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
676 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
677 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
678 // This is just the low 32 bits of a (signed) fp->i64 conversion.
679 // We cannot do this with Promote because i64 is not a legal type.
680 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
681 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
682
683 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
684 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
685 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
686 }
687 } else {
688 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
689 if (Subtarget.hasSPE()) {
690 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal);
691 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
692 } else {
693 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand);
694 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
695 }
696 }
697
698 // With the instructions enabled under FPCVT, we can do everything.
699 if (Subtarget.hasFPCVT()) {
700 if (Subtarget.has64BitSupport()) {
701 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom);
702 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom);
703 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom);
704 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom);
705 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
706 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
707 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
708 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
709 }
710
711 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
712 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
713 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
714 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom);
715 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
716 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
717 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
718 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
719 }
720
721 if (Subtarget.use64BitRegs()) {
722 // 64-bit PowerPC implementations can support i64 types directly
723 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
724 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
725 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
726 // 64-bit PowerPC wants to expand i128 shifts itself.
727 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
728 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
729 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
730 } else {
731 // 32-bit PowerPC wants to expand i64 shifts itself.
732 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
733 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
734 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
735 }
736
737 // PowerPC has better expansions for funnel shifts than the generic
738 // TargetLowering::expandFunnelShift.
739 if (Subtarget.has64BitSupport()) {
740 setOperationAction(ISD::FSHL, MVT::i64, Custom);
741 setOperationAction(ISD::FSHR, MVT::i64, Custom);
742 }
743 setOperationAction(ISD::FSHL, MVT::i32, Custom);
744 setOperationAction(ISD::FSHR, MVT::i32, Custom);
745
746 if (Subtarget.hasVSX()) {
747 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
748 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
749 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
750 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
751 }
752
753 if (Subtarget.hasAltivec()) {
754 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
755 setOperationAction(ISD::SADDSAT, VT, Legal);
756 setOperationAction(ISD::SSUBSAT, VT, Legal);
757 setOperationAction(ISD::UADDSAT, VT, Legal);
758 setOperationAction(ISD::USUBSAT, VT, Legal);
759 }
760 // First set operation action for all vector types to expand. Then we
761 // will selectively turn on ones that can be effectively codegen'd.
762 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
763 // add/sub are legal for all supported vector VT's.
764 setOperationAction(ISD::ADD, VT, Legal);
765 setOperationAction(ISD::SUB, VT, Legal);
766
767 // For v2i64, these are only valid with P8Vector. This is corrected after
768 // the loop.
769 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
770 setOperationAction(ISD::SMAX, VT, Legal);
771 setOperationAction(ISD::SMIN, VT, Legal);
772 setOperationAction(ISD::UMAX, VT, Legal);
773 setOperationAction(ISD::UMIN, VT, Legal);
774 }
775 else {
776 setOperationAction(ISD::SMAX, VT, Expand);
777 setOperationAction(ISD::SMIN, VT, Expand);
778 setOperationAction(ISD::UMAX, VT, Expand);
779 setOperationAction(ISD::UMIN, VT, Expand);
780 }
781
782 if (Subtarget.hasVSX()) {
783 setOperationAction(ISD::FMAXNUM, VT, Legal);
784 setOperationAction(ISD::FMINNUM, VT, Legal);
785 }
786
787 // Vector instructions introduced in P8
788 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
789 setOperationAction(ISD::CTPOP, VT, Legal);
790 setOperationAction(ISD::CTLZ, VT, Legal);
791 }
792 else {
793 setOperationAction(ISD::CTPOP, VT, Expand);
794 setOperationAction(ISD::CTLZ, VT, Expand);
795 }
796
797 // Vector instructions introduced in P9
798 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
799 setOperationAction(ISD::CTTZ, VT, Legal);
800 else
801 setOperationAction(ISD::CTTZ, VT, Expand);
802
803 // We promote all shuffles to v16i8.
804 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
805 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
806
807 // We promote all non-typed operations to v4i32.
808 setOperationAction(ISD::AND , VT, Promote);
809 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
810 setOperationAction(ISD::OR , VT, Promote);
811 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
812 setOperationAction(ISD::XOR , VT, Promote);
813 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
814 setOperationAction(ISD::LOAD , VT, Promote);
815 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
816 setOperationAction(ISD::SELECT, VT, Promote);
817 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
818 setOperationAction(ISD::VSELECT, VT, Legal);
819 setOperationAction(ISD::SELECT_CC, VT, Promote);
820 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
821 setOperationAction(ISD::STORE, VT, Promote);
822 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
823
824 // No other operations are legal.
825 setOperationAction(ISD::MUL , VT, Expand);
826 setOperationAction(ISD::SDIV, VT, Expand);
827 setOperationAction(ISD::SREM, VT, Expand);
828 setOperationAction(ISD::UDIV, VT, Expand);
829 setOperationAction(ISD::UREM, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::FREM, VT, Expand);
832 setOperationAction(ISD::FNEG, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FLOG, VT, Expand);
835 setOperationAction(ISD::FLOG10, VT, Expand);
836 setOperationAction(ISD::FLOG2, VT, Expand);
837 setOperationAction(ISD::FEXP, VT, Expand);
838 setOperationAction(ISD::FEXP2, VT, Expand);
839 setOperationAction(ISD::FSIN, VT, Expand);
840 setOperationAction(ISD::FCOS, VT, Expand);
841 setOperationAction(ISD::FABS, VT, Expand);
842 setOperationAction(ISD::FFLOOR, VT, Expand);
843 setOperationAction(ISD::FCEIL, VT, Expand);
844 setOperationAction(ISD::FTRUNC, VT, Expand);
845 setOperationAction(ISD::FRINT, VT, Expand);
846 setOperationAction(ISD::FNEARBYINT, VT, Expand);
847 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
849 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
850 setOperationAction(ISD::MULHU, VT, Expand);
851 setOperationAction(ISD::MULHS, VT, Expand);
852 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
853 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
854 setOperationAction(ISD::UDIVREM, VT, Expand);
855 setOperationAction(ISD::SDIVREM, VT, Expand);
856 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
857 setOperationAction(ISD::FPOW, VT, Expand);
858 setOperationAction(ISD::BSWAP, VT, Expand);
859 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
860 setOperationAction(ISD::ROTL, VT, Expand);
861 setOperationAction(ISD::ROTR, VT, Expand);
862
863 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
864 setTruncStoreAction(VT, InnerVT, Expand);
865 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
866 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
867 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
868 }
869 }
870 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand);
871 if (!Subtarget.hasP8Vector()) {
872 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
873 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
874 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
875 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
876 }
877
878 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
879 // with merges, splats, etc.
880 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
881
882 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
883 // are cheap, so handle them before they get expanded to scalar.
884 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
885 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
886 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
887 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
888 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
889
890 setOperationAction(ISD::AND , MVT::v4i32, Legal);
891 setOperationAction(ISD::OR , MVT::v4i32, Legal);
892 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
893 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
894 setOperationAction(ISD::SELECT, MVT::v4i32,
895 Subtarget.useCRBits() ? Legal : Expand);
896 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
897 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal);
898 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal);
899 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal);
900 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal);
901 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
902 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
903 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
904 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
905 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
906 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
907 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
908 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
909
910 // Custom lowering ROTL v1i128 to VECTOR_SHUFFLE v16i8.
911 setOperationAction(ISD::ROTL, MVT::v1i128, Custom);
912 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
913 if (Subtarget.hasAltivec())
914 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
915 setOperationAction(ISD::ROTL, VT, Legal);
916 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
917 if (Subtarget.hasP8Altivec())
918 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
919
920 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
921 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
922 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
923 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
924
925 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
926 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
927
928 if (Subtarget.hasVSX()) {
929 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
930 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
931 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
932 }
933
934 if (Subtarget.hasP8Altivec())
935 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
936 else
937 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
938
939 if (Subtarget.isISA3_1()) {
940 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
941 setOperationAction(ISD::MULHS, MVT::v2i64, Legal);
942 setOperationAction(ISD::MULHU, MVT::v2i64, Legal);
943 setOperationAction(ISD::MULHS, MVT::v4i32, Legal);
944 setOperationAction(ISD::MULHU, MVT::v4i32, Legal);
945 setOperationAction(ISD::UDIV, MVT::v2i64, Legal);
946 setOperationAction(ISD::SDIV, MVT::v2i64, Legal);
947 setOperationAction(ISD::UDIV, MVT::v4i32, Legal);
948 setOperationAction(ISD::SDIV, MVT::v4i32, Legal);
949 setOperationAction(ISD::UREM, MVT::v2i64, Legal);
950 setOperationAction(ISD::SREM, MVT::v2i64, Legal);
951 setOperationAction(ISD::UREM, MVT::v4i32, Legal);
952 setOperationAction(ISD::SREM, MVT::v4i32, Legal);
953 setOperationAction(ISD::UREM, MVT::v1i128, Legal);
954 setOperationAction(ISD::SREM, MVT::v1i128, Legal);
955 setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
956 setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
957 setOperationAction(ISD::ROTL, MVT::v1i128, Legal);
958 }
959
960 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
961 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
962
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
964 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
965
966 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
967 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
968 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
969 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
970
971 // Altivec does not contain unordered floating-point compare instructions
972 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
973 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
974 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
975 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
976
977 if (Subtarget.hasVSX()) {
978 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
979 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
980 if (Subtarget.hasP8Vector()) {
981 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
982 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
983 }
984 if (Subtarget.hasDirectMove() && isPPC64) {
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
986 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
987 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
989 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
991 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
993 }
994 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
995
996 // The nearbyint variants are not allowed to raise the inexact exception
997 // so we can only code-gen them with unsafe math.
998 if (TM.Options.UnsafeFPMath) {
999 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1000 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1001 }
1002
1003 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1004 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1005 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1006 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1007 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1008 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
1009 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1010 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1011
1012 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1013 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1014 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
1015 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1016 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1017
1018 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
1019 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1020
1021 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
1022 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
1023
1024 // Share the Altivec comparison restrictions.
1025 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
1026 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
1027 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
1028 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
1029
1030 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1031 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
1032
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034
1035 if (Subtarget.hasP8Vector())
1036 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
1037
1038 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
1039
1040 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
1041 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
1042 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
1043
1044 if (Subtarget.hasP8Altivec()) {
1045 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1046 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
1047 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1048
1049 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1050 // SRL, but not for SRA because of the instructions available:
1051 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
1052 // doing
1053 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
1054 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
1055 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1056
1057 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
1058 }
1059 else {
1060 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1061 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
1062 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
1063
1064 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1065
1066 // VSX v2i64 only supports non-arithmetic operations.
1067 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
1068 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
1069 }
1070
1071 if (Subtarget.isISA3_1())
1072 setOperationAction(ISD::SETCC, MVT::v1i128, Legal);
1073 else
1074 setOperationAction(ISD::SETCC, MVT::v1i128, Expand);
1075
1076 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
1077 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
1078 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
1079 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
1080
1081 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1082
1083 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
1084 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
1085 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
1086 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
1087 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1088 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1089 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1090 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1091
1092 // Custom handling for partial vectors of integers converted to
1093 // floating point. We already have optimal handling for v2i32 through
1094 // the DAG combine, so those aren't necessary.
1095 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom);
1096 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom);
1097 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom);
1098 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom);
1099 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom);
1100 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom);
1101 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom);
1102 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom);
1103 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
1104 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1105 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
1106 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1107 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom);
1108 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
1109 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
1110 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
1111
1112 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
1113 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
1114 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
1115 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
1116 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
1117 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
1118
1119 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1120 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1121
1122 // Handle constrained floating-point operations of vector.
1123 // The predictor is `hasVSX` because altivec instruction has
1124 // no exception but VSX vector instruction has.
1125 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
1126 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
1127 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
1128 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
1129 setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal);
1130 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
1131 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v4f32, Legal);
1132 setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal);
1133 setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal);
1134 setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
1135 setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal);
1136 setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
1137 setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
1138
1139 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
1140 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
1141 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
1142 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
1143 setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal);
1144 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
1145 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v2f64, Legal);
1146 setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal);
1147 setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal);
1148 setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
1149 setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal);
1150 setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
1151 setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
1152
1153 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
1154 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
1155
1156 for (MVT FPT : MVT::fp_valuetypes())
1157 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
1158
1159 // Expand the SELECT to SELECT_CC
1160 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1161
1162 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1163 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1164
1165 // No implementation for these ops for PowerPC.
1166 setOperationAction(ISD::FSIN, MVT::f128, Expand);
1167 setOperationAction(ISD::FCOS, MVT::f128, Expand);
1168 setOperationAction(ISD::FPOW, MVT::f128, Expand);
1169 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
1170 setOperationAction(ISD::FREM, MVT::f128, Expand);
1171 }
1172
1173 if (Subtarget.hasP8Altivec()) {
1174 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
1175 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
1176 }
1177
1178 if (Subtarget.hasP9Vector()) {
1179 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1180 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1181
1182 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1183 // SRL, but not for SRA because of the instructions available:
1184 // VS{RL} and VS{RL}O.
1185 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1186 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
1187 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
1188
1189 setOperationAction(ISD::FADD, MVT::f128, Legal);
1190 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1191 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1192 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1193 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1194
1195 setOperationAction(ISD::FMA, MVT::f128, Legal);
1196 setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
1197 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
1198 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
1199 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
1200 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
1201 setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
1202
1203 setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
1204 setOperationAction(ISD::FRINT, MVT::f128, Legal);
1205 setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
1206 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
1208 setOperationAction(ISD::FROUND, MVT::f128, Legal);
1209
1210 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1211 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
1212 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
1213
1214 // Handle constrained floating-point operations of fp128
1215 setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
1216 setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
1217 setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
1218 setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
1219 setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
1220 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
1221 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
1222 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
1223 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
1224 setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
1225 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
1226 setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
1227 setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal);
1228 setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
1229 setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
1230 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1231 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1232 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
1233 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
1234 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
1235 } else if (Subtarget.hasVSX()) {
1236 setOperationAction(ISD::LOAD, MVT::f128, Promote);
1237 setOperationAction(ISD::STORE, MVT::f128, Promote);
1238
1239 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32);
1240 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32);
1241
1242 // Set FADD/FSUB as libcall to avoid the legalizer to expand the
1243 // fp_to_uint and int_to_fp.
1244 setOperationAction(ISD::FADD, MVT::f128, LibCall);
1245 setOperationAction(ISD::FSUB, MVT::f128, LibCall);
1246
1247 setOperationAction(ISD::FMUL, MVT::f128, Expand);
1248 setOperationAction(ISD::FDIV, MVT::f128, Expand);
1249 setOperationAction(ISD::FNEG, MVT::f128, Expand);
1250 setOperationAction(ISD::FABS, MVT::f128, Expand);
1251 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
1252 setOperationAction(ISD::FMA, MVT::f128, Expand);
1253 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1254
1255 // Expand the fp_extend if the target type is fp128.
1256 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
1257 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Expand);
1258
1259 // Expand the fp_round if the source type is fp128.
1260 for (MVT VT : {MVT::f32, MVT::f64}) {
1261 setOperationAction(ISD::FP_ROUND, VT, Custom);
1262 setOperationAction(ISD::STRICT_FP_ROUND, VT, Custom);
1263 }
1264
1265 setOperationAction(ISD::SETCC, MVT::f128, Custom);
1266 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Custom);
1267 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom);
1268 setOperationAction(ISD::BR_CC, MVT::f128, Expand);
1269
1270 // Lower following f128 select_cc pattern:
1271 // select_cc x, y, tv, fv, cc -> select_cc (setcc x, y, cc), 0, tv, fv, NE
1272 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1273
1274 // We need to handle f128 SELECT_CC with integer result type.
1275 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1276 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand);
1277 }
1278
1279 if (Subtarget.hasP9Altivec()) {
1280 if (Subtarget.isISA3_1()) {
1281 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
1282 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Legal);
1283 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Legal);
1284 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
1285 } else {
1286 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1287 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1288 }
1289 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
1290 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
1291 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
1292 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
1293 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
1294 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
1295 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
1296 }
1297
1298 if (Subtarget.hasP10Vector()) {
1299 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1300 }
1301 }
1302
1303 if (Subtarget.pairedVectorMemops()) {
1304 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass);
1305 setOperationAction(ISD::LOAD, MVT::v256i1, Custom);
1306 setOperationAction(ISD::STORE, MVT::v256i1, Custom);
1307 }
1308 if (Subtarget.hasMMA()) {
1309 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass);
1310 setOperationAction(ISD::LOAD, MVT::v512i1, Custom);
1311 setOperationAction(ISD::STORE, MVT::v512i1, Custom);
1312 setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom);
1313 }
1314
1315 if (Subtarget.has64BitSupport())
1316 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
1317
1318 if (Subtarget.isISA3_1())
1319 setOperationAction(ISD::SRA, MVT::v1i128, Legal);
1320
1321 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1322
1323 if (!isPPC64) {
1324 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
1325 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
1326 }
1327
1328 if (shouldInlineQuadwordAtomics()) {
1329 setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom);
1330 setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom);
1331 setOperationAction(ISD::INTRINSIC_VOID, MVT::i128, Custom);
1332 }
1333
1334 setBooleanContents(ZeroOrOneBooleanContent);
1335
1336 if (Subtarget.hasAltivec()) {
1337 // Altivec instructions set fields to all zeros or all ones.
1338 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
1339 }
1340
1341 setLibcallName(RTLIB::MULO_I128, nullptr);
1342 if (!isPPC64) {
1343 // These libcalls are not available in 32-bit.
1344 setLibcallName(RTLIB::SHL_I128, nullptr);
1345 setLibcallName(RTLIB::SRL_I128, nullptr);
1346 setLibcallName(RTLIB::SRA_I128, nullptr);
1347 setLibcallName(RTLIB::MUL_I128, nullptr);
1348 setLibcallName(RTLIB::MULO_I64, nullptr);
1349 }
1350
1351 if (!isPPC64)
1352 setMaxAtomicSizeInBitsSupported(32);
1353 else if (shouldInlineQuadwordAtomics())
1354 setMaxAtomicSizeInBitsSupported(128);
1355 else
1356 setMaxAtomicSizeInBitsSupported(64);
1357
1358 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1359
1360 // We have target-specific dag combine patterns for the following nodes:
1361 setTargetDAGCombine({ISD::ADD, ISD::SHL, ISD::SRA, ISD::SRL, ISD::MUL,
1362 ISD::FMA, ISD::SINT_TO_FP, ISD::BUILD_VECTOR});
1363 if (Subtarget.hasFPCVT())
1364 setTargetDAGCombine(ISD::UINT_TO_FP);
1365 setTargetDAGCombine({ISD::LOAD, ISD::STORE, ISD::BR_CC});
1366 if (Subtarget.useCRBits())
1367 setTargetDAGCombine(ISD::BRCOND);
1368 setTargetDAGCombine({ISD::BSWAP, ISD::INTRINSIC_WO_CHAIN,
1369 ISD::INTRINSIC_W_CHAIN, ISD::INTRINSIC_VOID});
1370
1371 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, ISD::ANY_EXTEND});
1372
1373 setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE});
1374
1375 if (Subtarget.useCRBits()) {
1376 setTargetDAGCombine({ISD::TRUNCATE, ISD::SETCC, ISD::SELECT_CC});
1377 }
1378
1379 if (Subtarget.hasP9Altivec()) {
1380 setTargetDAGCombine({ISD::ABS, ISD::VSELECT});
1381 }
1382
1383 setLibcallName(RTLIB::LOG_F128, "logf128");
1384 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1385 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1386 setLibcallName(RTLIB::EXP_F128, "expf128");
1387 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1388 setLibcallName(RTLIB::SIN_F128, "sinf128");
1389 setLibcallName(RTLIB::COS_F128, "cosf128");
1390 setLibcallName(RTLIB::POW_F128, "powf128");
1391 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1392 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1393 setLibcallName(RTLIB::REM_F128, "fmodf128");
1394 setLibcallName(RTLIB::SQRT_F128, "sqrtf128");
1395 setLibcallName(RTLIB::CEIL_F128, "ceilf128");
1396 setLibcallName(RTLIB::FLOOR_F128, "floorf128");
1397 setLibcallName(RTLIB::TRUNC_F128, "truncf128");
1398 setLibcallName(RTLIB::ROUND_F128, "roundf128");
1399 setLibcallName(RTLIB::LROUND_F128, "lroundf128");
1400 setLibcallName(RTLIB::LLROUND_F128, "llroundf128");
1401 setLibcallName(RTLIB::RINT_F128, "rintf128");
1402 setLibcallName(RTLIB::LRINT_F128, "lrintf128");
1403 setLibcallName(RTLIB::LLRINT_F128, "llrintf128");
1404 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128");
1405 setLibcallName(RTLIB::FMA_F128, "fmaf128");
1406
1407 // With 32 condition bits, we don't need to sink (and duplicate) compares
1408 // aggressively in CodeGenPrep.
1409 if (Subtarget.useCRBits()) {
1410 setHasMultipleConditionRegisters();
1411 setJumpIsExpensive();
1412 }
1413
1414 setMinFunctionAlignment(Align(4));
1415
1416 switch (Subtarget.getCPUDirective()) {
1417 default: break;
1418 case PPC::DIR_970:
1419 case PPC::DIR_A2:
1420 case PPC::DIR_E500:
1421 case PPC::DIR_E500mc:
1422 case PPC::DIR_E5500:
1423 case PPC::DIR_PWR4:
1424 case PPC::DIR_PWR5:
1425 case PPC::DIR_PWR5X:
1426 case PPC::DIR_PWR6:
1427 case PPC::DIR_PWR6X:
1428 case PPC::DIR_PWR7:
1429 case PPC::DIR_PWR8:
1430 case PPC::DIR_PWR9:
1431 case PPC::DIR_PWR10:
1432 case PPC::DIR_PWR_FUTURE:
1433 setPrefLoopAlignment(Align(16));
1434 setPrefFunctionAlignment(Align(16));
1435 break;
1436 }
1437
1438 if (Subtarget.enableMachineScheduler())
1439 setSchedulingPreference(Sched::Source);
1440 else
1441 setSchedulingPreference(Sched::Hybrid);
1442
1443 computeRegisterProperties(STI.getRegisterInfo());
1444
1445 // The Freescale cores do better with aggressive inlining of memcpy and
1446 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1447 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1448 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1449 MaxStoresPerMemset = 32;
1450 MaxStoresPerMemsetOptSize = 16;
1451 MaxStoresPerMemcpy = 32;
1452 MaxStoresPerMemcpyOptSize = 8;
1453 MaxStoresPerMemmove = 32;
1454 MaxStoresPerMemmoveOptSize = 8;
1455 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1456 // The A2 also benefits from (very) aggressive inlining of memcpy and
1457 // friends. The overhead of a the function call, even when warm, can be
1458 // over one hundred cycles.
1459 MaxStoresPerMemset = 128;
1460 MaxStoresPerMemcpy = 128;
1461 MaxStoresPerMemmove = 128;
1462 MaxLoadsPerMemcmp = 128;
1463 } else {
1464 MaxLoadsPerMemcmp = 8;
1465 MaxLoadsPerMemcmpOptSize = 4;
1466 }
1467
1468 IsStrictFPEnabled = true;
1469
1470 // Let the subtarget (CPU) decide if a predictable select is more expensive
1471 // than the corresponding branch. This information is used in CGP to decide
1472 // when to convert selects into branches.
1473 PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive();
1474}
1475
1476// *********************************** NOTE ************************************
1477// For selecting load and store instructions, the addressing modes are defined
1478// as ComplexPatterns in PPCInstrInfo.td, which are then utilized in the TD
1479// patterns to match the load the store instructions.
1480//
1481// The TD definitions for the addressing modes correspond to their respective
1482// Select<AddrMode>Form() function in PPCISelDAGToDAG.cpp. These functions rely
1483// on SelectOptimalAddrMode(), which calls computeMOFlags() to compute the
1484// address mode flags of a particular node. Afterwards, the computed address
1485// flags are passed into getAddrModeForFlags() in order to retrieve the optimal
1486// addressing mode. SelectOptimalAddrMode() then sets the Base and Displacement
1487// accordingly, based on the preferred addressing mode.
1488//
1489// Within PPCISelLowering.h, there are two enums: MemOpFlags and AddrMode.
1490// MemOpFlags contains all the possible flags that can be used to compute the
1491// optimal addressing mode for load and store instructions.
1492// AddrMode contains all the possible load and store addressing modes available
1493// on Power (such as DForm, DSForm, DQForm, XForm, etc.)
1494//
1495// When adding new load and store instructions, it is possible that new address
1496// flags may need to be added into MemOpFlags, and a new addressing mode will
1497// need to be added to AddrMode. An entry of the new addressing mode (consisting
1498// of the minimal and main distinguishing address flags for the new load/store
1499// instructions) will need to be added into initializeAddrModeMap() below.
1500// Finally, when adding new addressing modes, the getAddrModeForFlags() will
1501// need to be updated to account for selecting the optimal addressing mode.
1502// *****************************************************************************
1503/// Initialize the map that relates the different addressing modes of the load
1504/// and store instructions to a set of flags. This ensures the load/store
1505/// instruction is correctly matched during instruction selection.
1506void PPCTargetLowering::initializeAddrModeMap() {
1507 AddrModesMap[PPC::AM_DForm] = {
1508 // LWZ, STW
1509 PPC::MOF_ZExt | PPC::MOF_RPlusSImm16 | PPC::MOF_WordInt,
1510 PPC::MOF_ZExt | PPC::MOF_RPlusLo | PPC::MOF_WordInt,
1511 PPC::MOF_ZExt | PPC::MOF_NotAddNorCst | PPC::MOF_WordInt,
1512 PPC::MOF_ZExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_WordInt,
1513 // LBZ, LHZ, STB, STH
1514 PPC::MOF_ZExt | PPC::MOF_RPlusSImm16 | PPC::MOF_SubWordInt,
1515 PPC::MOF_ZExt | PPC::MOF_RPlusLo | PPC::MOF_SubWordInt,
1516 PPC::MOF_ZExt | PPC::MOF_NotAddNorCst | PPC::MOF_SubWordInt,
1517 PPC::MOF_ZExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_SubWordInt,
1518 // LHA
1519 PPC::MOF_SExt | PPC::MOF_RPlusSImm16 | PPC::MOF_SubWordInt,
1520 PPC::MOF_SExt | PPC::MOF_RPlusLo | PPC::MOF_SubWordInt,
1521 PPC::MOF_SExt | PPC::MOF_NotAddNorCst | PPC::MOF_SubWordInt,
1522 PPC::MOF_SExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_SubWordInt,
1523 // LFS, LFD, STFS, STFD
1524 PPC::MOF_RPlusSImm16 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1525 PPC::MOF_RPlusLo | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1526 PPC::MOF_NotAddNorCst | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1527 PPC::MOF_AddrIsSImm32 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetBeforeP9,
1528 };
1529 AddrModesMap[PPC::AM_DSForm] = {
1530 // LWA
1531 PPC::MOF_SExt | PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_WordInt,
1532 PPC::MOF_SExt | PPC::MOF_NotAddNorCst | PPC::MOF_WordInt,
1533 PPC::MOF_SExt | PPC::MOF_AddrIsSImm32 | PPC::MOF_WordInt,
1534 // LD, STD
1535 PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_DoubleWordInt,
1536 PPC::MOF_NotAddNorCst | PPC::MOF_DoubleWordInt,
1537 PPC::MOF_AddrIsSImm32 | PPC::MOF_DoubleWordInt,
1538 // DFLOADf32, DFLOADf64, DSTOREf32, DSTOREf64
1539 PPC::MOF_RPlusSImm16Mult4 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9,
1540 PPC::MOF_NotAddNorCst | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9,
1541 PPC::MOF_AddrIsSImm32 | PPC::MOF_ScalarFloat | PPC::MOF_SubtargetP9,
1542 };
1543 AddrModesMap[PPC::AM_DQForm] = {
1544 // LXV, STXV
1545 PPC::MOF_RPlusSImm16Mult16 | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
1546 PPC::MOF_NotAddNorCst | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
1547 PPC::MOF_AddrIsSImm32 | PPC::MOF_Vector | PPC::MOF_SubtargetP9,
1548 };
1549 AddrModesMap[PPC::AM_PrefixDForm] = {PPC::MOF_RPlusSImm34 |
1550 PPC::MOF_SubtargetP10};
1551 // TODO: Add mapping for quadword load/store.
1552}
1553
1554/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1555/// the desired ByVal argument alignment.
1556static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
1557 if (MaxAlign == MaxMaxAlign)
1558 return;
1559 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1560 if (MaxMaxAlign >= 32 &&
1561 VTy->getPrimitiveSizeInBits().getFixedSize() >= 256)
1562 MaxAlign = Align(32);
1563 else if (VTy->getPrimitiveSizeInBits().getFixedSize() >= 128 &&
1564 MaxAlign < 16)
1565 MaxAlign = Align(16);
1566 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1567 Align EltAlign;
1568 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1569 if (EltAlign > MaxAlign)
1570 MaxAlign = EltAlign;
1571 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1572 for (auto *EltTy : STy->elements()) {
1573 Align EltAlign;
1574 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1575 if (EltAlign > MaxAlign)
1576 MaxAlign = EltAlign;
1577 if (MaxAlign == MaxMaxAlign)
1578 break;
1579 }
1580 }
1581}
1582
1583/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1584/// function arguments in the caller parameter area.
1585uint64_t PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1586 const DataLayout &DL) const {
1587 // 16byte and wider vectors are passed on 16byte boundary.
1588 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1589 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
1590 if (Subtarget.hasAltivec())
1591 getMaxByValAlign(Ty, Alignment, Align(16));
1592 return Alignment.value();
1593}
1594
1595bool PPCTargetLowering::useSoftFloat() const {
1596 return Subtarget.useSoftFloat();
1597}
1598
1599bool PPCTargetLowering::hasSPE() const {
1600 return Subtarget.hasSPE();
1601}
1602
1603bool PPCTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
1604 return VT.isScalarInteger();
1605}
1606
1607const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1608 switch ((PPCISD::NodeType)Opcode) {
1609 case PPCISD::FIRST_NUMBER: break;
1610 case PPCISD::FSEL: return "PPCISD::FSEL";
1611 case PPCISD::XSMAXC: return "PPCISD::XSMAXC";
1612 case PPCISD::XSMINC: return "PPCISD::XSMINC";
1613 case PPCISD::FCFID: return "PPCISD::FCFID";
1614 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1615 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1616 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1617 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1618 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1619 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1620 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1621 case PPCISD::FP_TO_UINT_IN_VSR:
1622 return "PPCISD::FP_TO_UINT_IN_VSR,";
1623 case PPCISD::FP_TO_SINT_IN_VSR:
1624 return "PPCISD::FP_TO_SINT_IN_VSR";
1625 case PPCISD::FRE: return "PPCISD::FRE";
1626 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1627 case PPCISD::FTSQRT:
1628 return "PPCISD::FTSQRT";
1629 case PPCISD::FSQRT:
1630 return "PPCISD::FSQRT";
1631 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1632 case PPCISD::VPERM: return "PPCISD::VPERM";
1633 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1634 case PPCISD::XXSPLTI_SP_TO_DP:
1635 return "PPCISD::XXSPLTI_SP_TO_DP";
1636 case PPCISD::XXSPLTI32DX:
1637 return "PPCISD::XXSPLTI32DX";
1638 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1639 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1640 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1641 case PPCISD::CMPB: return "PPCISD::CMPB";
1642 case PPCISD::Hi: return "PPCISD::Hi";
1643 case PPCISD::Lo: return "PPCISD::Lo";
1644 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1645 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1646 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1647 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1648 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1649 case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
1650 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1651 case PPCISD::SRL: return "PPCISD::SRL";
1652 case PPCISD::SRA: return "PPCISD::SRA";
1653 case PPCISD::SHL: return "PPCISD::SHL";
1654 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1655 case PPCISD::CALL: return "PPCISD::CALL";
1656 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1657 case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC";
1658 case PPCISD::CALL_RM:
1659 return "PPCISD::CALL_RM";
1660 case PPCISD::CALL_NOP_RM:
1661 return "PPCISD::CALL_NOP_RM";
1662 case PPCISD::CALL_NOTOC_RM:
1663 return "PPCISD::CALL_NOTOC_RM";
1664 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1665 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1666 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1667 case PPCISD::BCTRL_RM:
1668 return "PPCISD::BCTRL_RM";
1669 case PPCISD::BCTRL_LOAD_TOC_RM:
1670 return "PPCISD::BCTRL_LOAD_TOC_RM";
1671 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1672 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1673 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1674 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1675 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1676 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1677 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1678 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1679 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1680 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1681 case PPCISD::SCALAR_TO_VECTOR_PERMUTED:
1682 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1683 case PPCISD::ANDI_rec_1_EQ_BIT:
1684 return "PPCISD::ANDI_rec_1_EQ_BIT";
1685 case PPCISD::ANDI_rec_1_GT_BIT:
1686 return "PPCISD::ANDI_rec_1_GT_BIT";
1687 case PPCISD::VCMP: return "PPCISD::VCMP";
1688 case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec";
1689 case PPCISD::LBRX: return "PPCISD::LBRX";
1690 case PPCISD::STBRX: return "PPCISD::STBRX";
1691 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1692 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1693 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1694 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1695 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1696 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1697 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1698 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1699 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1700 case PPCISD::ST_VSR_SCAL_INT:
1701 return "PPCISD::ST_VSR_SCAL_INT";
1702 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1703 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1704 case PPCISD::BDZ: return "PPCISD::BDZ";
1705 case PPCISD::MFFS: return "PPCISD::MFFS";
1706 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1707 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1708 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1709 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1710 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1711 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1712 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1713 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1714 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1715 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1716 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1717 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1718 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1719 case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX";
1720 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1721 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1722 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1723 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1724 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1725 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1726 case PPCISD::PADDI_DTPREL:
1727 return "PPCISD::PADDI_DTPREL";
1728 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1729 case PPCISD::SC: return "PPCISD::SC";
1730 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1731 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1732 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1733 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1734 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1735 case PPCISD::VABSD: return "PPCISD::VABSD";
1736 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1737 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1738 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1739 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1740 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1741 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1742 case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
1743 case PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR:
1744 return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR";
1745 case PPCISD::TLS_LOCAL_EXEC_MAT_ADDR:
1746 return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR";
1747 case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD";
1748 case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD";
1749 case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG";
1750 case PPCISD::XXMFACC: return "PPCISD::XXMFACC";
1751 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1752 case PPCISD::ZEXT_LD_SPLAT: return "PPCISD::ZEXT_LD_SPLAT";
1753 case PPCISD::SEXT_LD_SPLAT: return "PPCISD::SEXT_LD_SPLAT";
1754 case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
1755 case PPCISD::STRICT_FADDRTZ:
1756 return "PPCISD::STRICT_FADDRTZ";
1757 case PPCISD::STRICT_FCTIDZ:
1758 return "PPCISD::STRICT_FCTIDZ";
1759 case PPCISD::STRICT_FCTIWZ:
1760 return "PPCISD::STRICT_FCTIWZ";
1761 case PPCISD::STRICT_FCTIDUZ:
1762 return "PPCISD::STRICT_FCTIDUZ";
1763 case PPCISD::STRICT_FCTIWUZ:
1764 return "PPCISD::STRICT_FCTIWUZ";
1765 case PPCISD::STRICT_FCFID:
1766 return "PPCISD::STRICT_FCFID";
1767 case PPCISD::STRICT_FCFIDU:
1768 return "PPCISD::STRICT_FCFIDU";
1769 case PPCISD::STRICT_FCFIDS:
1770 return "PPCISD::STRICT_FCFIDS";
1771 case PPCISD::STRICT_FCFIDUS:
1772 return "PPCISD::STRICT_FCFIDUS";
1773 case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
1774 }
1775 return nullptr;
1776}
1777
1778EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1779 EVT VT) const {
1780 if (!VT.isVector())
1781 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1782
1783 return VT.changeVectorElementTypeToInteger();
1784}
1785
1786bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1787 assert(VT.isFloatingPoint() && "Non-floating-point FMA?")(static_cast <bool> (VT.isFloatingPoint() && "Non-floating-point FMA?"
) ? void (0) : __assert_fail ("VT.isFloatingPoint() && \"Non-floating-point FMA?\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 1787, __extension__
__PRETTY_FUNCTION__))
;
1788 return true;
1789}
1790
1791//===----------------------------------------------------------------------===//
1792// Node matching predicates, for use by the tblgen matching code.
1793//===----------------------------------------------------------------------===//
1794
1795/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1796static bool isFloatingPointZero(SDValue Op) {
1797 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1798 return CFP->getValueAPF().isZero();
1799 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1800 // Maybe this has already been legalized into the constant pool?
1801 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1802 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1803 return CFP->getValueAPF().isZero();
1804 }
1805 return false;
1806}
1807
1808/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1809/// true if Op is undef or if it matches the specified value.
1810static bool isConstantOrUndef(int Op, int Val) {
1811 return Op < 0 || Op == Val;
1812}
1813
1814/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1815/// VPKUHUM instruction.
1816/// The ShuffleKind distinguishes between big-endian operations with
1817/// two different inputs (0), either-endian operations with two identical
1818/// inputs (1), and little-endian operations with two different inputs (2).
1819/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1820bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1821 SelectionDAG &DAG) {
1822 bool IsLE = DAG.getDataLayout().isLittleEndian();
1823 if (ShuffleKind == 0) {
1824 if (IsLE)
1825 return false;
1826 for (unsigned i = 0; i != 16; ++i)
1827 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1828 return false;
1829 } else if (ShuffleKind == 2) {
1830 if (!IsLE)
1831 return false;
1832 for (unsigned i = 0; i != 16; ++i)
1833 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1834 return false;
1835 } else if (ShuffleKind == 1) {
1836 unsigned j = IsLE ? 0 : 1;
1837 for (unsigned i = 0; i != 8; ++i)
1838 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1839 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1840 return false;
1841 }
1842 return true;
1843}
1844
1845/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1846/// VPKUWUM instruction.
1847/// The ShuffleKind distinguishes between big-endian operations with
1848/// two different inputs (0), either-endian operations with two identical
1849/// inputs (1), and little-endian operations with two different inputs (2).
1850/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1851bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1852 SelectionDAG &DAG) {
1853 bool IsLE = DAG.getDataLayout().isLittleEndian();
1854 if (ShuffleKind == 0) {
1855 if (IsLE)
1856 return false;
1857 for (unsigned i = 0; i != 16; i += 2)
1858 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1859 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1860 return false;
1861 } else if (ShuffleKind == 2) {
1862 if (!IsLE)
1863 return false;
1864 for (unsigned i = 0; i != 16; i += 2)
1865 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1866 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1867 return false;
1868 } else if (ShuffleKind == 1) {
1869 unsigned j = IsLE ? 0 : 2;
1870 for (unsigned i = 0; i != 8; i += 2)
1871 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1872 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1873 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1874 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1875 return false;
1876 }
1877 return true;
1878}
1879
1880/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1881/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1882/// current subtarget.
1883///
1884/// The ShuffleKind distinguishes between big-endian operations with
1885/// two different inputs (0), either-endian operations with two identical
1886/// inputs (1), and little-endian operations with two different inputs (2).
1887/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1888bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1889 SelectionDAG &DAG) {
1890 const PPCSubtarget &Subtarget = DAG.getSubtarget<PPCSubtarget>();
1891 if (!Subtarget.hasP8Vector())
1892 return false;
1893
1894 bool IsLE = DAG.getDataLayout().isLittleEndian();
1895 if (ShuffleKind == 0) {
1896 if (IsLE)
1897 return false;
1898 for (unsigned i = 0; i != 16; i += 4)
1899 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1900 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1901 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1902 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1903 return false;
1904 } else if (ShuffleKind == 2) {
1905 if (!IsLE)
1906 return false;
1907 for (unsigned i = 0; i != 16; i += 4)
1908 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1909 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1910 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1911 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1912 return false;
1913 } else if (ShuffleKind == 1) {
1914 unsigned j = IsLE ? 0 : 4;
1915 for (unsigned i = 0; i != 8; i += 4)
1916 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1917 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1918 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1919 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1920 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1921 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1922 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1923 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1924 return false;
1925 }
1926 return true;
1927}
1928
1929/// isVMerge - Common function, used to match vmrg* shuffles.
1930///
1931static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1932 unsigned LHSStart, unsigned RHSStart) {
1933 if (N->getValueType(0) != MVT::v16i8)
1934 return false;
1935 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&(static_cast <bool> ((UnitSize == 1 || UnitSize == 2 ||
UnitSize == 4) && "Unsupported merge size!") ? void (
0) : __assert_fail ("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 1936, __extension__
__PRETTY_FUNCTION__))
1936 "Unsupported merge size!")(static_cast <bool> ((UnitSize == 1 || UnitSize == 2 ||
UnitSize == 4) && "Unsupported merge size!") ? void (
0) : __assert_fail ("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 1936, __extension__
__PRETTY_FUNCTION__))
;
1937
1938 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1939 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1940 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1941 LHSStart+j+i*UnitSize) ||
1942 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1943 RHSStart+j+i*UnitSize))
1944 return false;
1945 }
1946 return true;
1947}
1948
1949/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1950/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1951/// The ShuffleKind distinguishes between big-endian merges with two
1952/// different inputs (0), either-endian merges with two identical inputs (1),
1953/// and little-endian merges with two different inputs (2). For the latter,
1954/// the input operands are swapped (see PPCInstrAltivec.td).
1955bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1956 unsigned ShuffleKind, SelectionDAG &DAG) {
1957 if (DAG.getDataLayout().isLittleEndian()) {
1958 if (ShuffleKind == 1) // unary
1959 return isVMerge(N, UnitSize, 0, 0);
1960 else if (ShuffleKind == 2) // swapped
1961 return isVMerge(N, UnitSize, 0, 16);
1962 else
1963 return false;
1964 } else {
1965 if (ShuffleKind == 1) // unary
1966 return isVMerge(N, UnitSize, 8, 8);
1967 else if (ShuffleKind == 0) // normal
1968 return isVMerge(N, UnitSize, 8, 24);
1969 else
1970 return false;
1971 }
1972}
1973
1974/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1975/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1976/// The ShuffleKind distinguishes between big-endian merges with two
1977/// different inputs (0), either-endian merges with two identical inputs (1),
1978/// and little-endian merges with two different inputs (2). For the latter,
1979/// the input operands are swapped (see PPCInstrAltivec.td).
1980bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1981 unsigned ShuffleKind, SelectionDAG &DAG) {
1982 if (DAG.getDataLayout().isLittleEndian()) {
1983 if (ShuffleKind == 1) // unary
1984 return isVMerge(N, UnitSize, 8, 8);
1985 else if (ShuffleKind == 2) // swapped
1986 return isVMerge(N, UnitSize, 8, 24);
1987 else
1988 return false;
1989 } else {
1990 if (ShuffleKind == 1) // unary
1991 return isVMerge(N, UnitSize, 0, 0);
1992 else if (ShuffleKind == 0) // normal
1993 return isVMerge(N, UnitSize, 0, 16);
1994 else
1995 return false;
1996 }
1997}
1998
1999/**
2000 * Common function used to match vmrgew and vmrgow shuffles
2001 *
2002 * The indexOffset determines whether to look for even or odd words in
2003 * the shuffle mask. This is based on the of the endianness of the target
2004 * machine.
2005 * - Little Endian:
2006 * - Use offset of 0 to check for odd elements
2007 * - Use offset of 4 to check for even elements
2008 * - Big Endian:
2009 * - Use offset of 0 to check for even elements
2010 * - Use offset of 4 to check for odd elements
2011 * A detailed description of the vector element ordering for little endian and
2012 * big endian can be found at
2013 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
2014 * Targeting your applications - what little endian and big endian IBM XL C/C++
2015 * compiler differences mean to you
2016 *
2017 * The mask to the shuffle vector instruction specifies the indices of the
2018 * elements from the two input vectors to place in the result. The elements are
2019 * numbered in array-access order, starting with the first vector. These vectors
2020 * are always of type v16i8, thus each vector will contain 16 elements of size
2021 * 8. More info on the shuffle vector can be found in the
2022 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
2023 * Language Reference.
2024 *
2025 * The RHSStartValue indicates whether the same input vectors are used (unary)
2026 * or two different input vectors are used, based on the following:
2027 * - If the instruction uses the same vector for both inputs, the range of the
2028 * indices will be 0 to 15. In this case, the RHSStart value passed should
2029 * be 0.
2030 * - If the instruction has two different vectors then the range of the
2031 * indices will be 0 to 31. In this case, the RHSStart value passed should
2032 * be 16 (indices 0-15 specify elements in the first vector while indices 16
2033 * to 31 specify elements in the second vector).
2034 *
2035 * \param[in] N The shuffle vector SD Node to analyze
2036 * \param[in] IndexOffset Specifies whether to look for even or odd elements
2037 * \param[in] RHSStartValue Specifies the starting index for the righthand input
2038 * vector to the shuffle_vector instruction
2039 * \return true iff this shuffle vector represents an even or odd word merge
2040 */
2041static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
2042 unsigned RHSStartValue) {
2043 if (N->getValueType(0) != MVT::v16i8)
2044 return false;
2045
2046 for (unsigned i = 0; i < 2; ++i)
2047 for (unsigned j = 0; j < 4; ++j)
2048 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
2049 i*RHSStartValue+j+IndexOffset) ||
2050 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
2051 i*RHSStartValue+j+IndexOffset+8))
2052 return false;
2053 return true;
2054}
2055
2056/**
2057 * Determine if the specified shuffle mask is suitable for the vmrgew or
2058 * vmrgow instructions.
2059 *
2060 * \param[in] N The shuffle vector SD Node to analyze
2061 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
2062 * \param[in] ShuffleKind Identify the type of merge:
2063 * - 0 = big-endian merge with two different inputs;
2064 * - 1 = either-endian merge with two identical inputs;
2065 * - 2 = little-endian merge with two different inputs (inputs are swapped for
2066 * little-endian merges).
2067 * \param[in] DAG The current SelectionDAG
2068 * \return true iff this shuffle mask
2069 */
2070bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
2071 unsigned ShuffleKind, SelectionDAG &DAG) {
2072 if (DAG.getDataLayout().isLittleEndian()) {
2073 unsigned indexOffset = CheckEven ? 4 : 0;
2074 if (ShuffleKind == 1) // Unary
2075 return isVMerge(N, indexOffset, 0);
2076 else if (ShuffleKind == 2) // swapped
2077 return isVMerge(N, indexOffset, 16);
2078 else
2079 return false;
2080 }
2081 else {
2082 unsigned indexOffset = CheckEven ? 0 : 4;
2083 if (ShuffleKind == 1) // Unary
2084 return isVMerge(N, indexOffset, 0);
2085 else if (ShuffleKind == 0) // Normal
2086 return isVMerge(N, indexOffset, 16);
2087 else
2088 return false;
2089 }
2090 return false;
2091}
2092
2093/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
2094/// amount, otherwise return -1.
2095/// The ShuffleKind distinguishes between big-endian operations with two
2096/// different inputs (0), either-endian operations with two identical inputs
2097/// (1), and little-endian operations with two different inputs (2). For the
2098/// latter, the input operands are swapped (see PPCInstrAltivec.td).
2099int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
2100 SelectionDAG &DAG) {
2101 if (N->getValueType(0) != MVT::v16i8)
2102 return -1;
2103
2104 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2105
2106 // Find the first non-undef value in the shuffle mask.
2107 unsigned i;
2108 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
2109 /*search*/;
2110
2111 if (i == 16) return -1; // all undef.
2112
2113 // Otherwise, check to see if the rest of the elements are consecutively
2114 // numbered from this value.
2115 unsigned ShiftAmt = SVOp->getMaskElt(i);
2116 if (ShiftAmt < i) return -1;
2117
2118 ShiftAmt -= i;
2119 bool isLE = DAG.getDataLayout().isLittleEndian();
2120
2121 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
2122 // Check the rest of the elements to see if they are consecutive.
2123 for (++i; i != 16; ++i)
2124 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2125 return -1;
2126 } else if (ShuffleKind == 1) {
2127 // Check the rest of the elements to see if they are consecutive.
2128 for (++i; i != 16; ++i)
2129 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
2130 return -1;
2131 } else
2132 return -1;
2133
2134 if (isLE)
2135 ShiftAmt = 16 - ShiftAmt;
2136
2137 return ShiftAmt;
2138}
2139
2140/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
2141/// specifies a splat of a single element that is suitable for input to
2142/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
2143bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
2144 EVT VT = N->getValueType(0);
2145 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2146 return EltSize == 8 && N->getMaskElt(0) == N->getMaskElt(1);
2147
2148 assert(VT == MVT::v16i8 && isPowerOf2_32(EltSize) &&(static_cast <bool> (VT == MVT::v16i8 && isPowerOf2_32
(EltSize) && EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"
) ? void (0) : __assert_fail ("VT == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2149, __extension__
__PRETTY_FUNCTION__))
2149 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes")(static_cast <bool> (VT == MVT::v16i8 && isPowerOf2_32
(EltSize) && EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"
) ? void (0) : __assert_fail ("VT == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2149, __extension__
__PRETTY_FUNCTION__))
;
2150
2151 // The consecutive indices need to specify an element, not part of two
2152 // different elements. So abandon ship early if this isn't the case.
2153 if (N->getMaskElt(0) % EltSize != 0)
2154 return false;
2155
2156 // This is a splat operation if each element of the permute is the same, and
2157 // if the value doesn't reference the second vector.
2158 unsigned ElementBase = N->getMaskElt(0);
2159
2160 // FIXME: Handle UNDEF elements too!
2161 if (ElementBase >= 16)
2162 return false;
2163
2164 // Check that the indices are consecutive, in the case of a multi-byte element
2165 // splatted with a v16i8 mask.
2166 for (unsigned i = 1; i != EltSize; ++i)
2167 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
2168 return false;
2169
2170 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
2171 if (N->getMaskElt(i) < 0) continue;
2172 for (unsigned j = 0; j != EltSize; ++j)
2173 if (N->getMaskElt(i+j) != N->getMaskElt(j))
2174 return false;
2175 }
2176 return true;
2177}
2178
2179/// Check that the mask is shuffling N byte elements. Within each N byte
2180/// element of the mask, the indices could be either in increasing or
2181/// decreasing order as long as they are consecutive.
2182/// \param[in] N the shuffle vector SD Node to analyze
2183/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
2184/// Word/DoubleWord/QuadWord).
2185/// \param[in] StepLen the delta indices number among the N byte element, if
2186/// the mask is in increasing/decreasing order then it is 1/-1.
2187/// \return true iff the mask is shuffling N byte elements.
2188static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
2189 int StepLen) {
2190 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&(static_cast <bool> ((Width == 2 || Width == 4 || Width
== 8 || Width == 16) && "Unexpected element width.")
? void (0) : __assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2191, __extension__
__PRETTY_FUNCTION__))
2191 "Unexpected element width.")(static_cast <bool> ((Width == 2 || Width == 4 || Width
== 8 || Width == 16) && "Unexpected element width.")
? void (0) : __assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2191, __extension__
__PRETTY_FUNCTION__))
;
2192 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.")(static_cast <bool> ((StepLen == 1 || StepLen == -1) &&
"Unexpected element width.") ? void (0) : __assert_fail ("(StepLen == 1 || StepLen == -1) && \"Unexpected element width.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2192, __extension__
__PRETTY_FUNCTION__))
;
2193
2194 unsigned NumOfElem = 16 / Width;
2195 unsigned MaskVal[16]; // Width is never greater than 16
2196 for (unsigned i = 0; i < NumOfElem; ++i) {
2197 MaskVal[0] = N->getMaskElt(i * Width);
2198 if ((StepLen == 1) && (MaskVal[0] % Width)) {
2199 return false;
2200 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
2201 return false;
2202 }
2203
2204 for (unsigned int j = 1; j < Width; ++j) {
2205 MaskVal[j] = N->getMaskElt(i * Width + j);
2206 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
2207 return false;
2208 }
2209 }
2210 }
2211
2212 return true;
2213}
2214
2215bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2216 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
2217 if (!isNByteElemShuffleMask(N, 4, 1))
2218 return false;
2219
2220 // Now we look at mask elements 0,4,8,12
2221 unsigned M0 = N->getMaskElt(0) / 4;
2222 unsigned M1 = N->getMaskElt(4) / 4;
2223 unsigned M2 = N->getMaskElt(8) / 4;
2224 unsigned M3 = N->getMaskElt(12) / 4;
2225 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
2226 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
2227
2228 // Below, let H and L be arbitrary elements of the shuffle mask
2229 // where H is in the range [4,7] and L is in the range [0,3].
2230 // H, 1, 2, 3 or L, 5, 6, 7
2231 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
2232 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
2233 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
2234 InsertAtByte = IsLE ? 12 : 0;
2235 Swap = M0 < 4;
2236 return true;
2237 }
2238 // 0, H, 2, 3 or 4, L, 6, 7
2239 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
2240 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
2241 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
2242 InsertAtByte = IsLE ? 8 : 4;
2243 Swap = M1 < 4;
2244 return true;
2245 }
2246 // 0, 1, H, 3 or 4, 5, L, 7
2247 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
2248 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
2249 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
2250 InsertAtByte = IsLE ? 4 : 8;
2251 Swap = M2 < 4;
2252 return true;
2253 }
2254 // 0, 1, 2, H or 4, 5, 6, L
2255 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
2256 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
2257 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
2258 InsertAtByte = IsLE ? 0 : 12;
2259 Swap = M3 < 4;
2260 return true;
2261 }
2262
2263 // If both vector operands for the shuffle are the same vector, the mask will
2264 // contain only elements from the first one and the second one will be undef.
2265 if (N->getOperand(1).isUndef()) {
2266 ShiftElts = 0;
2267 Swap = true;
2268 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
2269 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
2270 InsertAtByte = IsLE ? 12 : 0;
2271 return true;
2272 }
2273 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
2274 InsertAtByte = IsLE ? 8 : 4;
2275 return true;
2276 }
2277 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
2278 InsertAtByte = IsLE ? 4 : 8;
2279 return true;
2280 }
2281 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
2282 InsertAtByte = IsLE ? 0 : 12;
2283 return true;
2284 }
2285 }
2286
2287 return false;
2288}
2289
2290bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
2291 bool &Swap, bool IsLE) {
2292 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2292, __extension__
__PRETTY_FUNCTION__))
;
14
'?' condition is true
2293 // Ensure each byte index of the word is consecutive.
2294 if (!isNByteElemShuffleMask(N, 4, 1))
15
Assuming the condition is false
16
Taking false branch
2295 return false;
2296
2297 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
2298 unsigned M0 = N->getMaskElt(0) / 4;
2299 unsigned M1 = N->getMaskElt(4) / 4;
2300 unsigned M2 = N->getMaskElt(8) / 4;
2301 unsigned M3 = N->getMaskElt(12) / 4;
2302
2303 // If both vector operands for the shuffle are the same vector, the mask will
2304 // contain only elements from the first one and the second one will be undef.
2305 if (N->getOperand(1).isUndef()) {
2306 assert(M0 < 4 && "Indexing into an undef vector?")(static_cast <bool> (M0 < 4 && "Indexing into an undef vector?"
) ? void (0) : __assert_fail ("M0 < 4 && \"Indexing into an undef vector?\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2306, __extension__
__PRETTY_FUNCTION__))
;
2307 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
2308 return false;
2309
2310 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
2311 Swap = false;
2312 return true;
2313 }
2314
2315 // Ensure each word index of the ShuffleVector Mask is consecutive.
2316 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
17
Assuming the condition is false
18
Assuming the condition is false
19
Assuming the condition is false
20
Taking false branch
2317 return false;
2318
2319 if (IsLE
20.1
'IsLE' is false
) {
2320 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2321 // Input vectors don't need to be swapped if the leading element
2322 // of the result is one of the 3 left elements of the second vector
2323 // (or if there is no shift to be done at all).
2324 Swap = false;
2325 ShiftElts = (8 - M0) % 8;
2326 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2327 // Input vectors need to be swapped if the leading element
2328 // of the result is one of the 3 left elements of the first vector
2329 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2330 Swap = true;
2331 ShiftElts = (4 - M0) % 4;
2332 }
2333
2334 return true;
2335 } else { // BE
2336 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
21
Assuming 'M0' is not equal to 0
22
Assuming 'M0' is not equal to 1
23
Assuming 'M0' is not equal to 2
24
Assuming 'M0' is not equal to 3
2337 // Input vectors don't need to be swapped if the leading element
2338 // of the result is one of the 4 elements of the first vector.
2339 Swap = false;
2340 ShiftElts = M0;
2341 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
25
Assuming 'M0' is not equal to 4
26
Assuming 'M0' is not equal to 5
27
Assuming 'M0' is not equal to 6
28
Assuming 'M0' is not equal to 7
29
Taking false branch
2342 // Input vectors need to be swapped if the leading element
2343 // of the result is one of the 4 elements of the right vector.
2344 Swap = true;
2345 ShiftElts = M0 - 4;
2346 }
2347
2348 return true;
30
Returning without writing to 'ShiftElts'
2349 }
2350}
2351
2352bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
2353 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2353, __extension__
__PRETTY_FUNCTION__))
;
2354
2355 if (!isNByteElemShuffleMask(N, Width, -1))
2356 return false;
2357
2358 for (int i = 0; i < 16; i += Width)
2359 if (N->getMaskElt(i) != i + Width - 1)
2360 return false;
2361
2362 return true;
2363}
2364
2365bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
2366 return isXXBRShuffleMaskHelper(N, 2);
2367}
2368
2369bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
2370 return isXXBRShuffleMaskHelper(N, 4);
2371}
2372
2373bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
2374 return isXXBRShuffleMaskHelper(N, 8);
2375}
2376
2377bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
2378 return isXXBRShuffleMaskHelper(N, 16);
2379}
2380
2381/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2382/// if the inputs to the instruction should be swapped and set \p DM to the
2383/// value for the immediate.
2384/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2385/// AND element 0 of the result comes from the first input (LE) or second input
2386/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2387/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2388/// mask.
2389bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
2390 bool &Swap, bool IsLE) {
2391 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")(static_cast <bool> (N->getValueType(0) == MVT::v16i8
&& "Shuffle vector expects v16i8") ? void (0) : __assert_fail
("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2391, __extension__
__PRETTY_FUNCTION__))
;
2392
2393 // Ensure each byte index of the double word is consecutive.
2394 if (!isNByteElemShuffleMask(N, 8, 1))
2395 return false;
2396
2397 unsigned M0 = N->getMaskElt(0) / 8;
2398 unsigned M1 = N->getMaskElt(8) / 8;
2399 assert(((M0 | M1) < 4) && "A mask element out of bounds?")(static_cast <bool> (((M0 | M1) < 4) && "A mask element out of bounds?"
) ? void (0) : __assert_fail ("((M0 | M1) < 4) && \"A mask element out of bounds?\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2399, __extension__
__PRETTY_FUNCTION__))
;
2400
2401 // If both vector operands for the shuffle are the same vector, the mask will
2402 // contain only elements from the first one and the second one will be undef.
2403 if (N->getOperand(1).isUndef()) {
2404 if ((M0 | M1) < 2) {
2405 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2406 Swap = false;
2407 return true;
2408 } else
2409 return false;
2410 }
2411
2412 if (IsLE) {
2413 if (M0 > 1 && M1 < 2) {
2414 Swap = false;
2415 } else if (M0 < 2 && M1 > 1) {
2416 M0 = (M0 + 2) % 4;
2417 M1 = (M1 + 2) % 4;
2418 Swap = true;
2419 } else
2420 return false;
2421
2422 // Note: if control flow comes here that means Swap is already set above
2423 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2424 return true;
2425 } else { // BE
2426 if (M0 < 2 && M1 > 1) {
2427 Swap = false;
2428 } else if (M0 > 1 && M1 < 2) {
2429 M0 = (M0 + 2) % 4;
2430 M1 = (M1 + 2) % 4;
2431 Swap = true;
2432 } else
2433 return false;
2434
2435 // Note: if control flow comes here that means Swap is already set above
2436 DM = (M0 << 1) + (M1 & 1);
2437 return true;
2438 }
2439}
2440
2441
2442/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2443/// appropriate for PPC mnemonics (which have a big endian bias - namely
2444/// elements are counted from the left of the vector register).
2445unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2446 SelectionDAG &DAG) {
2447 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2448 assert(isSplatShuffleMask(SVOp, EltSize))(static_cast <bool> (isSplatShuffleMask(SVOp, EltSize))
? void (0) : __assert_fail ("isSplatShuffleMask(SVOp, EltSize)"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2448, __extension__
__PRETTY_FUNCTION__))
;
2449 EVT VT = SVOp->getValueType(0);
2450
2451 if (VT == MVT::v2i64 || VT == MVT::v2f64)
2452 return DAG.getDataLayout().isLittleEndian() ? 1 - SVOp->getMaskElt(0)
2453 : SVOp->getMaskElt(0);
2454
2455 if (DAG.getDataLayout().isLittleEndian())
2456 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2457 else
2458 return SVOp->getMaskElt(0) / EltSize;
2459}
2460
2461/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2462/// by using a vspltis[bhw] instruction of the specified element size, return
2463/// the constant being splatted. The ByteSize field indicates the number of
2464/// bytes of each element [124] -> [bhw].
2465SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2466 SDValue OpVal;
2467
2468 // If ByteSize of the splat is bigger than the element size of the
2469 // build_vector, then we have a case where we are checking for a splat where
2470 // multiple elements of the buildvector are folded together into a single
2471 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2472 unsigned EltSize = 16/N->getNumOperands();
2473 if (EltSize < ByteSize) {
2474 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2475 SDValue UniquedVals[4];
2476 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?")(static_cast <bool> (Multiple > 1 && Multiple
<= 4 && "How can this happen?") ? void (0) : __assert_fail
("Multiple > 1 && Multiple <= 4 && \"How can this happen?\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2476, __extension__
__PRETTY_FUNCTION__))
;
2477
2478 // See if all of the elements in the buildvector agree across.
2479 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2480 if (N->getOperand(i).isUndef()) continue;
2481 // If the element isn't a constant, bail fully out.
2482 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2483
2484 if (!UniquedVals[i&(Multiple-1)].getNode())
2485 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2486 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2487 return SDValue(); // no match.
2488 }
2489
2490 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2491 // either constant or undef values that are identical for each chunk. See
2492 // if these chunks can form into a larger vspltis*.
2493
2494 // Check to see if all of the leading entries are either 0 or -1. If
2495 // neither, then this won't fit into the immediate field.
2496 bool LeadingZero = true;
2497 bool LeadingOnes = true;
2498 for (unsigned i = 0; i != Multiple-1; ++i) {
2499 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2500
2501 LeadingZero &= isNullConstant(UniquedVals[i]);
2502 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2503 }
2504 // Finally, check the least significant entry.
2505 if (LeadingZero) {
2506 if (!UniquedVals[Multiple-1].getNode())
2507 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2508 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2509 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2510 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2511 }
2512 if (LeadingOnes) {
2513 if (!UniquedVals[Multiple-1].getNode())
2514 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2515 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2516 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2517 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2518 }
2519
2520 return SDValue();
2521 }
2522
2523 // Check to see if this buildvec has a single non-undef value in its elements.
2524 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2525 if (N->getOperand(i).isUndef()) continue;
2526 if (!OpVal.getNode())
2527 OpVal = N->getOperand(i);
2528 else if (OpVal != N->getOperand(i))
2529 return SDValue();
2530 }
2531
2532 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2533
2534 unsigned ValSizeInBytes = EltSize;
2535 uint64_t Value = 0;
2536 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2537 Value = CN->getZExtValue();
2538 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2539 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!")(static_cast <bool> (CN->getValueType(0) == MVT::f32
&& "Only one legal FP vector type!") ? void (0) : __assert_fail
("CN->getValueType(0) == MVT::f32 && \"Only one legal FP vector type!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2539, __extension__
__PRETTY_FUNCTION__))
;
2540 Value = FloatToBits(CN->getValueAPF().convertToFloat());
2541 }
2542
2543 // If the splat value is larger than the element value, then we can never do
2544 // this splat. The only case that we could fit the replicated bits into our
2545 // immediate field for would be zero, and we prefer to use vxor for it.
2546 if (ValSizeInBytes < ByteSize) return SDValue();
2547
2548 // If the element value is larger than the splat value, check if it consists
2549 // of a repeated bit pattern of size ByteSize.
2550 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2551 return SDValue();
2552
2553 // Properly sign extend the value.
2554 int MaskVal = SignExtend32(Value, ByteSize * 8);
2555
2556 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2557 if (MaskVal == 0) return SDValue();
2558
2559 // Finally, if this value fits in a 5 bit sext field, return it
2560 if (SignExtend32<5>(MaskVal) == MaskVal)
2561 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2562 return SDValue();
2563}
2564
2565//===----------------------------------------------------------------------===//
2566// Addressing Mode Selection
2567//===----------------------------------------------------------------------===//
2568
2569/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2570/// or 64-bit immediate, and if the value can be accurately represented as a
2571/// sign extension from a 16-bit value. If so, this returns true and the
2572/// immediate.
2573bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2574 if (!isa<ConstantSDNode>(N))
2575 return false;
2576
2577 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2578 if (N->getValueType(0) == MVT::i32)
2579 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2580 else
2581 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2582}
2583bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2584 return isIntS16Immediate(Op.getNode(), Imm);
2585}
2586
2587/// Used when computing address flags for selecting loads and stores.
2588/// If we have an OR, check if the LHS and RHS are provably disjoint.
2589/// An OR of two provably disjoint values is equivalent to an ADD.
2590/// Most PPC load/store instructions compute the effective address as a sum,
2591/// so doing this conversion is useful.
2592static bool provablyDisjointOr(SelectionDAG &DAG, const SDValue &N) {
2593 if (N.getOpcode() != ISD::OR)
2594 return false;
2595 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2596 if (!LHSKnown.Zero.getBoolValue())
2597 return false;
2598 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2599 return (~(LHSKnown.Zero | RHSKnown.Zero) == 0);
2600}
2601
2602/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2603/// be represented as an indexed [r+r] operation.
2604bool PPCTargetLowering::SelectAddressEVXRegReg(SDValue N, SDValue &Base,
2605 SDValue &Index,
2606 SelectionDAG &DAG) const {
2607 for (SDNode *U : N->uses()) {
2608 if (MemSDNode *Memop = dyn_cast<MemSDNode>(U)) {
2609 if (Memop->getMemoryVT() == MVT::f64) {
2610 Base = N.getOperand(0);
2611 Index = N.getOperand(1);
2612 return true;
2613 }
2614 }
2615 }
2616 return false;
2617}
2618
2619/// isIntS34Immediate - This method tests if value of node given can be
2620/// accurately represented as a sign extension from a 34-bit value. If so,
2621/// this returns true and the immediate.
2622bool llvm::isIntS34Immediate(SDNode *N, int64_t &Imm) {
2623 if (!isa<ConstantSDNode>(N))
2624 return false;
2625
2626 Imm = (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2627 return isInt<34>(Imm);
2628}
2629bool llvm::isIntS34Immediate(SDValue Op, int64_t &Imm) {
2630 return isIntS34Immediate(Op.getNode(), Imm);
2631}
2632
2633/// SelectAddressRegReg - Given the specified addressed, check to see if it
2634/// can be represented as an indexed [r+r] operation. Returns false if it
2635/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2636/// non-zero and N can be represented by a base register plus a signed 16-bit
2637/// displacement, make a more precise judgement by checking (displacement % \p
2638/// EncodingAlignment).
2639bool PPCTargetLowering::SelectAddressRegReg(
2640 SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG,
2641 MaybeAlign EncodingAlignment) const {
2642 // If we have a PC Relative target flag don't select as [reg+reg]. It will be
2643 // a [pc+imm].
2644 if (SelectAddressPCRel(N, Base))
2645 return false;
2646
2647 int16_t Imm = 0;
2648 if (N.getOpcode() == ISD::ADD) {
2649 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2650 // SPE load/store can only handle 8-bit offsets.
2651 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2652 return true;
2653 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2654 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2655 return false; // r+i
2656 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2657 return false; // r+i
2658
2659 Base = N.getOperand(0);
2660 Index = N.getOperand(1);
2661 return true;
2662 } else if (N.getOpcode() == ISD::OR) {
2663 if (isIntS16Immediate(N.getOperand(1), Imm) &&
2664 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm)))
2665 return false; // r+i can fold it if we can.
2666
2667 // If this is an or of disjoint bitfields, we can codegen this as an add
2668 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2669 // disjoint.
2670 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2671
2672 if (LHSKnown.Zero.getBoolValue()) {
2673 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2674 // If all of the bits are known zero on the LHS or RHS, the add won't
2675 // carry.
2676 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2677 Base = N.getOperand(0);
2678 Index = N.getOperand(1);
2679 return true;
2680 }
2681 }
2682 }
2683
2684 return false;
2685}
2686
2687// If we happen to be doing an i64 load or store into a stack slot that has
2688// less than a 4-byte alignment, then the frame-index elimination may need to
2689// use an indexed load or store instruction (because the offset may not be a
2690// multiple of 4). The extra register needed to hold the offset comes from the
2691// register scavenger, and it is possible that the scavenger will need to use
2692// an emergency spill slot. As a result, we need to make sure that a spill slot
2693// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2694// stack slot.
2695static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2696 // FIXME: This does not handle the LWA case.
2697 if (VT != MVT::i64)
2698 return;
2699
2700 // NOTE: We'll exclude negative FIs here, which come from argument
2701 // lowering, because there are no known test cases triggering this problem
2702 // using packed structures (or similar). We can remove this exclusion if
2703 // we find such a test case. The reason why this is so test-case driven is
2704 // because this entire 'fixup' is only to prevent crashes (from the
2705 // register scavenger) on not-really-valid inputs. For example, if we have:
2706 // %a = alloca i1
2707 // %b = bitcast i1* %a to i64*
2708 // store i64* a, i64 b
2709 // then the store should really be marked as 'align 1', but is not. If it
2710 // were marked as 'align 1' then the indexed form would have been
2711 // instruction-selected initially, and the problem this 'fixup' is preventing
2712 // won't happen regardless.
2713 if (FrameIdx < 0)
2714 return;
2715
2716 MachineFunction &MF = DAG.getMachineFunction();
2717 MachineFrameInfo &MFI = MF.getFrameInfo();
2718
2719 if (MFI.getObjectAlign(FrameIdx) >= Align(4))
2720 return;
2721
2722 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2723 FuncInfo->setHasNonRISpills();
2724}
2725
2726/// Returns true if the address N can be represented by a base register plus
2727/// a signed 16-bit displacement [r+imm], and if it is not better
2728/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2729/// displacements that are multiples of that value.
2730bool PPCTargetLowering::SelectAddressRegImm(
2731 SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG,
2732 MaybeAlign EncodingAlignment) const {
2733 // FIXME dl should come from parent load or store, not from address
2734 SDLoc dl(N);
2735
2736 // If we have a PC Relative target flag don't select as [reg+imm]. It will be
2737 // a [pc+imm].
2738 if (SelectAddressPCRel(N, Base))
2739 return false;
2740
2741 // If this can be more profitably realized as r+r, fail.
2742 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2743 return false;
2744
2745 if (N.getOpcode() == ISD::ADD) {
2746 int16_t imm = 0;
2747 if (isIntS16Immediate(N.getOperand(1), imm) &&
2748 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2749 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2750 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2751 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2752 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2753 } else {
2754 Base = N.getOperand(0);
2755 }
2756 return true; // [r+i]
2757 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2758 // Match LOAD (ADD (X, Lo(G))).
2759 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()(static_cast <bool> (!cast<ConstantSDNode>(N.getOperand
(1).getOperand(1))->getZExtValue() && "Cannot handle constant offsets yet!"
) ? void (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2760, __extension__
__PRETTY_FUNCTION__))
2760 && "Cannot handle constant offsets yet!")(static_cast <bool> (!cast<ConstantSDNode>(N.getOperand
(1).getOperand(1))->getZExtValue() && "Cannot handle constant offsets yet!"
) ? void (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2760, __extension__
__PRETTY_FUNCTION__))
;
2761 Disp = N.getOperand(1).getOperand(0); // The global address.
2762 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2765, __extension__
__PRETTY_FUNCTION__))
2763 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2765, __extension__
__PRETTY_FUNCTION__))
2764 Disp.getOpcode() == ISD::TargetConstantPool ||(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2765, __extension__
__PRETTY_FUNCTION__))
2765 Disp.getOpcode() == ISD::TargetJumpTable)(static_cast <bool> (Disp.getOpcode() == ISD::TargetGlobalAddress
|| Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode
() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? void (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 2765, __extension__
__PRETTY_FUNCTION__))
;
2766 Base = N.getOperand(0);
2767 return true; // [&g+r]
2768 }
2769 } else if (N.getOpcode() == ISD::OR) {
2770 int16_t imm = 0;
2771 if (isIntS16Immediate(N.getOperand(1), imm) &&
2772 (!EncodingAlignment || isAligned(*EncodingAlignment, imm))) {
2773 // If this is an or of disjoint bitfields, we can codegen this as an add
2774 // (for better address arithmetic) if the LHS and RHS of the OR are
2775 // provably disjoint.
2776 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2777
2778 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2779 // If all of the bits are known zero on the LHS or RHS, the add won't
2780 // carry.
2781 if (FrameIndexSDNode *FI =
2782 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2783 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2784 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2785 } else {
2786 Base = N.getOperand(0);
2787 }
2788 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2789 return true;
2790 }
2791 }
2792 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2793 // Loading from a constant address.
2794
2795 // If this address fits entirely in a 16-bit sext immediate field, codegen
2796 // this as "d, 0"
2797 int16_t Imm;
2798 if (isIntS16Immediate(CN, Imm) &&
2799 (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) {
2800 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2801 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2802 CN->getValueType(0));
2803 return true;
2804 }
2805
2806 // Handle 32-bit sext immediates with LIS + addr mode.
2807 if ((CN->getValueType(0) == MVT::i32 ||
2808 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2809 (!EncodingAlignment ||
2810 isAligned(*EncodingAlignment, CN->getZExtValue()))) {
2811 int Addr = (int)CN->getZExtValue();
2812
2813 // Otherwise, break this down into an LIS + disp.
2814 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2815
2816 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2817 MVT::i32);
2818 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2819 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2820 return true;
2821 }
2822 }
2823
2824 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2825 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2826 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2827 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2828 } else
2829 Base = N;
2830 return true; // [r+0]
2831}
2832
2833/// Similar to the 16-bit case but for instructions that take a 34-bit
2834/// displacement field (prefixed loads/stores).
2835bool PPCTargetLowering::SelectAddressRegImm34(SDValue N, SDValue &Disp,
2836 SDValue &Base,
2837 SelectionDAG &DAG) const {
2838 // Only on 64-bit targets.
2839 if (N.getValueType() != MVT::i64)
2840 return false;
2841
2842 SDLoc dl(N);
2843 int64_t Imm = 0;
2844
2845 if (N.getOpcode() == ISD::ADD) {
2846 if (!isIntS34Immediate(N.getOperand(1), Imm))
2847 return false;
2848 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2849 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2850 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2851 else
2852 Base = N.getOperand(0);
2853 return true;
2854 }
2855
2856 if (N.getOpcode() == ISD::OR) {
2857 if (!isIntS34Immediate(N.getOperand(1), Imm))
2858 return false;
2859 // If this is an or of disjoint bitfields, we can codegen this as an add
2860 // (for better address arithmetic) if the LHS and RHS of the OR are
2861 // provably disjoint.
2862 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2863 if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)Imm) != ~0ULL)
2864 return false;
2865 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0)))
2866 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2867 else
2868 Base = N.getOperand(0);
2869 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2870 return true;
2871 }
2872
2873 if (isIntS34Immediate(N, Imm)) { // If the address is a 34-bit const.
2874 Disp = DAG.getTargetConstant(Imm, dl, N.getValueType());
2875 Base = DAG.getRegister(PPC::ZERO8, N.getValueType());
2876 return true;
2877 }
2878
2879 return false;
2880}
2881
2882/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2883/// represented as an indexed [r+r] operation.
2884bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2885 SDValue &Index,
2886 SelectionDAG &DAG) const {
2887 // Check to see if we can easily represent this as an [r+r] address. This
2888 // will fail if it thinks that the address is more profitably represented as
2889 // reg+imm, e.g. where imm = 0.
2890 if (SelectAddressRegReg(N, Base, Index, DAG))
2891 return true;
2892
2893 // If the address is the result of an add, we will utilize the fact that the
2894 // address calculation includes an implicit add. However, we can reduce
2895 // register pressure if we do not materialize a constant just for use as the
2896 // index register. We only get rid of the add if it is not an add of a
2897 // value and a 16-bit signed constant and both have a single use.
2898 int16_t imm = 0;
2899 if (N.getOpcode() == ISD::ADD &&
2900 (!isIntS16Immediate(N.getOperand(1), imm) ||
2901 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2902 Base = N.getOperand(0);
2903 Index = N.getOperand(1);
2904 return true;
2905 }
2906
2907 // Otherwise, do it the hard way, using R0 as the base register.
2908 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2909 N.getValueType());
2910 Index = N;
2911 return true;
2912}
2913
2914template <typename Ty> static bool isValidPCRelNode(SDValue N) {
2915 Ty *PCRelCand = dyn_cast<Ty>(N);
2916 return PCRelCand && (PCRelCand->getTargetFlags() & PPCII::MO_PCREL_FLAG);
2917}
2918
2919/// Returns true if this address is a PC Relative address.
2920/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG
2921/// or if the node opcode is PPCISD::MAT_PCREL_ADDR.
2922bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
2923 // This is a materialize PC Relative node. Always select this as PC Relative.
2924 Base = N;
2925 if (N.getOpcode() == PPCISD::MAT_PCREL_ADDR)
2926 return true;
2927 if (isValidPCRelNode<ConstantPoolSDNode>(N) ||
2928 isValidPCRelNode<GlobalAddressSDNode>(N) ||
2929 isValidPCRelNode<JumpTableSDNode>(N) ||
2930 isValidPCRelNode<BlockAddressSDNode>(N))
2931 return true;
2932 return false;
2933}
2934
2935/// Returns true if we should use a direct load into vector instruction
2936/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2937static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
2938
2939 // If there are any other uses other than scalar to vector, then we should
2940 // keep it as a scalar load -> direct move pattern to prevent multiple
2941 // loads.
2942 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
2943 if (!LD)
2944 return false;
2945
2946 EVT MemVT = LD->getMemoryVT();
2947 if (!MemVT.isSimple())
2948 return false;
2949 switch(MemVT.getSimpleVT().SimpleTy) {
2950 case MVT::i64:
2951 break;
2952 case MVT::i32:
2953 if (!ST.hasP8Vector())
2954 return false;
2955 break;
2956 case MVT::i16:
2957 case MVT::i8:
2958 if (!ST.hasP9Vector())
2959 return false;
2960 break;
2961 default:
2962 return false;
2963 }
2964
2965 SDValue LoadedVal(N, 0);
2966 if (!LoadedVal.hasOneUse())
2967 return false;
2968
2969 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
2970 UI != UE; ++UI)
2971 if (UI.getUse().get().getResNo() == 0 &&
2972 UI->getOpcode() != ISD::SCALAR_TO_VECTOR &&
2973 UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED)
2974 return false;
2975
2976 return true;
2977}
2978
2979/// getPreIndexedAddressParts - returns true by value, base pointer and
2980/// offset pointer and addressing mode by reference if the node's address
2981/// can be legally represented as pre-indexed load / store address.
2982bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2983 SDValue &Offset,
2984 ISD::MemIndexedMode &AM,
2985 SelectionDAG &DAG) const {
2986 if (DisablePPCPreinc) return false;
2987
2988 bool isLoad = true;
2989 SDValue Ptr;
2990 EVT VT;
2991 Align Alignment;
2992 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2993 Ptr = LD->getBasePtr();
2994 VT = LD->getMemoryVT();
2995 Alignment = LD->getAlign();
2996 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2997 Ptr = ST->getBasePtr();
2998 VT = ST->getMemoryVT();
2999 Alignment = ST->getAlign();
3000 isLoad = false;
3001 } else
3002 return false;
3003
3004 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
3005 // instructions because we can fold these into a more efficient instruction
3006 // instead, (such as LXSD).
3007 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
3008 return false;
3009 }
3010
3011 // PowerPC doesn't have preinc load/store instructions for vectors
3012 if (VT.isVector())
3013 return false;
3014
3015 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
3016 // Common code will reject creating a pre-inc form if the base pointer
3017 // is a frame index, or if N is a store and the base pointer is either
3018 // the same as or a predecessor of the value being stored. Check for
3019 // those situations here, and try with swapped Base/Offset instead.
3020 bool Swap = false;
3021
3022 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
3023 Swap = true;
3024 else if (!isLoad) {
3025 SDValue Val = cast<StoreSDNode>(N)->getValue();
3026 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
3027 Swap = true;
3028 }
3029
3030 if (Swap)
3031 std::swap(Base, Offset);
3032
3033 AM = ISD::PRE_INC;
3034 return true;
3035 }
3036
3037 // LDU/STU can only handle immediates that are a multiple of 4.
3038 if (VT != MVT::i64) {
3039 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, None))
3040 return false;
3041 } else {
3042 // LDU/STU need an address with at least 4-byte alignment.
3043 if (Alignment < Align(4))
3044 return false;
3045
3046 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, Align(4)))
3047 return false;
3048 }
3049
3050 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3051 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
3052 // sext i32 to i64 when addr mode is r+i.
3053 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
3054 LD->getExtensionType() == ISD::SEXTLOAD &&
3055 isa<ConstantSDNode>(Offset))
3056 return false;
3057 }
3058
3059 AM = ISD::PRE_INC;
3060 return true;
3061}
3062
3063//===----------------------------------------------------------------------===//
3064// LowerOperation implementation
3065//===----------------------------------------------------------------------===//
3066
3067/// Return true if we should reference labels using a PICBase, set the HiOpFlags
3068/// and LoOpFlags to the target MO flags.
3069static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
3070 unsigned &HiOpFlags, unsigned &LoOpFlags,
3071 const GlobalValue *GV = nullptr) {
3072 HiOpFlags = PPCII::MO_HA;
3073 LoOpFlags = PPCII::MO_LO;
3074
3075 // Don't use the pic base if not in PIC relocation model.
3076 if (IsPIC) {
3077 HiOpFlags |= PPCII::MO_PIC_FLAG;
3078 LoOpFlags |= PPCII::MO_PIC_FLAG;
3079 }
3080}
3081
3082static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
3083 SelectionDAG &DAG) {
3084 SDLoc DL(HiPart);
3085 EVT PtrVT = HiPart.getValueType();
3086 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
3087
3088 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
3089 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
3090
3091 // With PIC, the first instruction is actually "GR+hi(&G)".
3092 if (isPIC)
3093 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
3094 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
3095
3096 // Generate non-pic code that has direct accesses to the constant pool.
3097 // The address of the global is just (hi(&g)+lo(&g)).
3098 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
3099}
3100
3101static void setUsesTOCBasePtr(MachineFunction &MF) {
3102 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3103 FuncInfo->setUsesTOCBasePtr();
3104}
3105
3106static void setUsesTOCBasePtr(SelectionDAG &DAG) {
3107 setUsesTOCBasePtr(DAG.getMachineFunction());
3108}
3109
3110SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
3111 SDValue GA) const {
3112 const bool Is64Bit = Subtarget.isPPC64();
3113 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
3114 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
3115 : Subtarget.isAIXABI()
3116 ? DAG.getRegister(PPC::R2, VT)
3117 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
3118 SDValue Ops[] = { GA, Reg };
3119 return DAG.getMemIntrinsicNode(
3120 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
3121 MachinePointerInfo::getGOT(DAG.getMachineFunction()), None,
3122 MachineMemOperand::MOLoad);
3123}
3124
3125SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
3126 SelectionDAG &DAG) const {
3127 EVT PtrVT = Op.getValueType();
3128 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3129 const Constant *C = CP->getConstVal();
3130
3131 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3132 // The actual address of the GlobalValue is stored in the TOC.
3133 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3134 if (Subtarget.isUsingPCRelativeCalls()) {
3135 SDLoc DL(CP);
3136 EVT Ty = getPointerTy(DAG.getDataLayout());
3137 SDValue ConstPool = DAG.getTargetConstantPool(
3138 C, Ty, CP->getAlign(), CP->getOffset(), PPCII::MO_PCREL_FLAG);
3139 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
3140 }
3141 setUsesTOCBasePtr(DAG);
3142 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0);
3143 return getTOCEntry(DAG, SDLoc(CP), GA);
3144 }
3145
3146 unsigned MOHiFlag, MOLoFlag;
3147 bool IsPIC = isPositionIndependent();
3148 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3149
3150 if (IsPIC && Subtarget.isSVR4ABI()) {
3151 SDValue GA =
3152 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), PPCII::MO_PIC_FLAG);
3153 return getTOCEntry(DAG, SDLoc(CP), GA);
3154 }
3155
3156 SDValue CPIHi =
3157 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOHiFlag);
3158 SDValue CPILo =
3159 DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0, MOLoFlag);
3160 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
3161}
3162
3163// For 64-bit PowerPC, prefer the more compact relative encodings.
3164// This trades 32 bits per jump table entry for one or two instructions
3165// on the jump site.
3166unsigned PPCTargetLowering::getJumpTableEncoding() const {
3167 if (isJumpTableRelative())
3168 return MachineJumpTableInfo::EK_LabelDifference32;
3169
3170 return TargetLowering::getJumpTableEncoding();
3171}
3172
3173bool PPCTargetLowering::isJumpTableRelative() const {
3174 if (UseAbsoluteJumpTables)
3175 return false;
3176 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
3177 return true;
3178 return TargetLowering::isJumpTableRelative();
3179}
3180
3181SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
3182 SelectionDAG &DAG) const {
3183 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3184 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
3185
3186 switch (getTargetMachine().getCodeModel()) {
3187 case CodeModel::Small:
3188 case CodeModel::Medium:
3189 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
3190 default:
3191 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
3192 getPointerTy(DAG.getDataLayout()));
3193 }
3194}
3195
3196const MCExpr *
3197PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
3198 unsigned JTI,
3199 MCContext &Ctx) const {
3200 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
3201 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
3202
3203 switch (getTargetMachine().getCodeModel()) {
3204 case CodeModel::Small:
3205 case CodeModel::Medium:
3206 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
3207 default:
3208 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
3209 }
3210}
3211
3212SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
3213 EVT PtrVT = Op.getValueType();
3214 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3215
3216 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3217 if (Subtarget.isUsingPCRelativeCalls()) {
3218 SDLoc DL(JT);
3219 EVT Ty = getPointerTy(DAG.getDataLayout());
3220 SDValue GA =
3221 DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
3222 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3223 return MatAddr;
3224 }
3225
3226 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3227 // The actual address of the GlobalValue is stored in the TOC.
3228 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3229 setUsesTOCBasePtr(DAG);
3230 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
3231 return getTOCEntry(DAG, SDLoc(JT), GA);
3232 }
3233
3234 unsigned MOHiFlag, MOLoFlag;
3235 bool IsPIC = isPositionIndependent();
3236 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3237
3238 if (IsPIC && Subtarget.isSVR4ABI()) {
3239 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3240 PPCII::MO_PIC_FLAG);
3241 return getTOCEntry(DAG, SDLoc(GA), GA);
3242 }
3243
3244 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
3245 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
3246 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
3247}
3248
3249SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
3250 SelectionDAG &DAG) const {
3251 EVT PtrVT = Op.getValueType();
3252 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
3253 const BlockAddress *BA = BASDN->getBlockAddress();
3254
3255 // isUsingPCRelativeCalls() returns true when PCRelative is enabled
3256 if (Subtarget.isUsingPCRelativeCalls()) {
3257 SDLoc DL(BASDN);
3258 EVT Ty = getPointerTy(DAG.getDataLayout());
3259 SDValue GA = DAG.getTargetBlockAddress(BA, Ty, BASDN->getOffset(),
3260 PPCII::MO_PCREL_FLAG);
3261 SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3262 return MatAddr;
3263 }
3264
3265 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
3266 // The actual BlockAddress is stored in the TOC.
3267 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3268 setUsesTOCBasePtr(DAG);
3269 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
3270 return getTOCEntry(DAG, SDLoc(BASDN), GA);
3271 }
3272
3273 // 32-bit position-independent ELF stores the BlockAddress in the .got.
3274 if (Subtarget.is32BitELFABI() && isPositionIndependent())
3275 return getTOCEntry(
3276 DAG, SDLoc(BASDN),
3277 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
3278
3279 unsigned MOHiFlag, MOLoFlag;
3280 bool IsPIC = isPositionIndependent();
3281 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
3282 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
3283 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
3284 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
3285}
3286
3287SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
3288 SelectionDAG &DAG) const {
3289 if (Subtarget.isAIXABI())
3290 return LowerGlobalTLSAddressAIX(Op, DAG);
3291
3292 return LowerGlobalTLSAddressLinux(Op, DAG);
3293}
3294
3295SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
3296 SelectionDAG &DAG) const {
3297 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3298
3299 if (DAG.getTarget().useEmulatedTLS())
3300 report_fatal_error("Emulated TLS is not yet supported on AIX");
3301
3302 SDLoc dl(GA);
3303 const GlobalValue *GV = GA->getGlobal();
3304 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3305
3306 // The general-dynamic model is the only access model supported for now, so
3307 // all the GlobalTLSAddress nodes are lowered with this model.
3308 // We need to generate two TOC entries, one for the variable offset, one for
3309 // the region handle. The global address for the TOC entry of the region
3310 // handle is created with the MO_TLSGDM_FLAG flag and the global address
3311 // for the TOC entry of the variable offset is created with MO_TLSGD_FLAG.
3312 SDValue VariableOffsetTGA =
3313 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGD_FLAG);
3314 SDValue RegionHandleTGA =
3315 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TLSGDM_FLAG);
3316 SDValue VariableOffset = getTOCEntry(DAG, dl, VariableOffsetTGA);
3317 SDValue RegionHandle = getTOCEntry(DAG, dl, RegionHandleTGA);
3318 return DAG.getNode(PPCISD::TLSGD_AIX, dl, PtrVT, VariableOffset,
3319 RegionHandle);
3320}
3321
3322SDValue PPCTargetLowering::LowerGlobalTLSAddressLinux(SDValue Op,
3323 SelectionDAG &DAG) const {
3324 // FIXME: TLS addresses currently use medium model code sequences,
3325 // which is the most useful form. Eventually support for small and
3326 // large models could be added if users need it, at the cost of
3327 // additional complexity.
3328 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3329 if (DAG.getTarget().useEmulatedTLS())
3330 return LowerToTLSEmulatedModel(GA, DAG);
3331
3332 SDLoc dl(GA);
3333 const GlobalValue *GV = GA->getGlobal();
3334 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3335 bool is64bit = Subtarget.isPPC64();
3336 const Module *M = DAG.getMachineFunction().getFunction().getParent();
3337 PICLevel::Level picLevel = M->getPICLevel();
3338
3339 const TargetMachine &TM = getTargetMachine();
3340 TLSModel::Model Model = TM.getTLSModel(GV);
3341
3342 if (Model == TLSModel::LocalExec) {
3343 if (Subtarget.isUsingPCRelativeCalls()) {
3344 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64);
3345 SDValue TGA = DAG.getTargetGlobalAddress(
3346 GV, dl, PtrVT, 0, (PPCII::MO_PCREL_FLAG | PPCII::MO_TPREL_FLAG));
3347 SDValue MatAddr =
3348 DAG.getNode(PPCISD::TLS_LOCAL_EXEC_MAT_ADDR, dl, PtrVT, TGA);
3349 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr);
3350 }
3351
3352 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3353 PPCII::MO_TPREL_HA);
3354 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3355 PPCII::MO_TPREL_LO);
3356 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
3357 : DAG.getRegister(PPC::R2, MVT::i32);
3358
3359 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
3360 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
3361 }
3362
3363 if (Model == TLSModel::InitialExec) {
3364 bool IsPCRel = Subtarget.isUsingPCRelativeCalls();
3365 SDValue TGA = DAG.getTargetGlobalAddress(
3366 GV, dl, PtrVT, 0, IsPCRel ? PPCII::MO_GOT_TPREL_PCREL_FLAG : 0);
3367 SDValue TGATLS = DAG.getTargetGlobalAddress(
3368 GV, dl, PtrVT, 0,
3369 IsPCRel ? (PPCII::MO_TLS | PPCII::MO_PCREL_FLAG) : PPCII::MO_TLS);
3370 SDValue TPOffset;
3371 if (IsPCRel) {
3372 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, dl, PtrVT, TGA);
3373 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel,
3374 MachinePointerInfo());
3375 } else {
3376 SDValue GOTPtr;
3377 if (is64bit) {
3378 setUsesTOCBasePtr(DAG);
3379 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3380 GOTPtr =
3381 DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl, PtrVT, GOTReg, TGA);
3382 } else {
3383 if (!TM.isPositionIndependent())
3384 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
3385 else if (picLevel == PICLevel::SmallPIC)
3386 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3387 else
3388 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3389 }
3390 TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl, PtrVT, TGA, GOTPtr);
3391 }
3392 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
3393 }
3394
3395 if (Model == TLSModel::GeneralDynamic) {
3396 if (Subtarget.isUsingPCRelativeCalls()) {
3397 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3398 PPCII::MO_GOT_TLSGD_PCREL_FLAG);
3399 return DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3400 }
3401
3402 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3403 SDValue GOTPtr;
3404 if (is64bit) {
3405 setUsesTOCBasePtr(DAG);
3406 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3407 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
3408 GOTReg, TGA);
3409 } else {
3410 if (picLevel == PICLevel::SmallPIC)
3411 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3412 else
3413 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3414 }
3415 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
3416 GOTPtr, TGA, TGA);
3417 }
3418
3419 if (Model == TLSModel::LocalDynamic) {
3420 if (Subtarget.isUsingPCRelativeCalls()) {
3421 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3422 PPCII::MO_GOT_TLSLD_PCREL_FLAG);
3423 SDValue MatPCRel =
3424 DAG.getNode(PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR, dl, PtrVT, TGA);
3425 return DAG.getNode(PPCISD::PADDI_DTPREL, dl, PtrVT, MatPCRel, TGA);
3426 }
3427
3428 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
3429 SDValue GOTPtr;
3430 if (is64bit) {
3431 setUsesTOCBasePtr(DAG);
3432 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
3433 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
3434 GOTReg, TGA);
3435 } else {
3436 if (picLevel == PICLevel::SmallPIC)
3437 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
3438 else
3439 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
3440 }
3441 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
3442 PtrVT, GOTPtr, TGA, TGA);
3443 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
3444 PtrVT, TLSAddr, TGA);
3445 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
3446 }
3447
3448 llvm_unreachable("Unknown TLS model!")::llvm::llvm_unreachable_internal("Unknown TLS model!", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3448)
;
3449}
3450
3451SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
3452 SelectionDAG &DAG) const {
3453 EVT PtrVT = Op.getValueType();
3454 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
3455 SDLoc DL(GSDN);
3456 const GlobalValue *GV = GSDN->getGlobal();
3457
3458 // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
3459 // The actual address of the GlobalValue is stored in the TOC.
3460 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
3461 if (Subtarget.isUsingPCRelativeCalls()) {
3462 EVT Ty = getPointerTy(DAG.getDataLayout());
3463 if (isAccessedAsGotIndirect(Op)) {
3464 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3465 PPCII::MO_PCREL_FLAG |
3466 PPCII::MO_GOT_FLAG);
3467 SDValue MatPCRel = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3468 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel,
3469 MachinePointerInfo());
3470 return Load;
3471 } else {
3472 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, Ty, GSDN->getOffset(),
3473 PPCII::MO_PCREL_FLAG);
3474 return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
3475 }
3476 }
3477 setUsesTOCBasePtr(DAG);
3478 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
3479 return getTOCEntry(DAG, DL, GA);
3480 }
3481
3482 unsigned MOHiFlag, MOLoFlag;
3483 bool IsPIC = isPositionIndependent();
3484 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
3485
3486 if (IsPIC && Subtarget.isSVR4ABI()) {
3487 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3488 GSDN->getOffset(),
3489 PPCII::MO_PIC_FLAG);
3490 return getTOCEntry(DAG, DL, GA);
3491 }
3492
3493 SDValue GAHi =
3494 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
3495 SDValue GALo =
3496 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
3497
3498 return LowerLabelRef(GAHi, GALo, IsPIC, DAG);
3499}
3500
3501SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3502 bool IsStrict = Op->isStrictFPOpcode();
3503 ISD::CondCode CC =
3504 cast<CondCodeSDNode>(Op.getOperand(IsStrict ? 3 : 2))->get();
3505 SDValue LHS = Op.getOperand(IsStrict ? 1 : 0);
3506 SDValue RHS = Op.getOperand(IsStrict ? 2 : 1);
3507 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
3508 EVT LHSVT = LHS.getValueType();
3509 SDLoc dl(Op);
3510
3511 // Soften the setcc with libcall if it is fp128.
3512 if (LHSVT == MVT::f128) {
3513 assert(!Subtarget.hasP9Vector() &&(static_cast <bool> (!Subtarget.hasP9Vector() &&
"SETCC for f128 is already legal under Power9!") ? void (0) :
__assert_fail ("!Subtarget.hasP9Vector() && \"SETCC for f128 is already legal under Power9!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3514, __extension__
__PRETTY_FUNCTION__))
3514 "SETCC for f128 is already legal under Power9!")(static_cast <bool> (!Subtarget.hasP9Vector() &&
"SETCC for f128 is already legal under Power9!") ? void (0) :
__assert_fail ("!Subtarget.hasP9Vector() && \"SETCC for f128 is already legal under Power9!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3514, __extension__
__PRETTY_FUNCTION__))
;
3515 softenSetCCOperands(DAG, LHSVT, LHS, RHS, CC, dl, LHS, RHS, Chain,
3516 Op->getOpcode() == ISD::STRICT_FSETCCS);
3517 if (RHS.getNode())
3518 LHS = DAG.getNode(ISD::SETCC, dl, Op.getValueType(), LHS, RHS,
3519 DAG.getCondCode(CC));
3520 if (IsStrict)
3521 return DAG.getMergeValues({LHS, Chain}, dl);
3522 return LHS;
3523 }
3524
3525 assert(!IsStrict && "Don't know how to handle STRICT_FSETCC!")(static_cast <bool> (!IsStrict && "Don't know how to handle STRICT_FSETCC!"
) ? void (0) : __assert_fail ("!IsStrict && \"Don't know how to handle STRICT_FSETCC!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3525, __extension__
__PRETTY_FUNCTION__))
;
3526
3527 if (Op.getValueType() == MVT::v2i64) {
3528 // When the operands themselves are v2i64 values, we need to do something
3529 // special because VSX has no underlying comparison operations for these.
3530 if (LHS.getValueType() == MVT::v2i64) {
3531 // Equality can be handled by casting to the legal type for Altivec
3532 // comparisons, everything else needs to be expanded.
3533 if (CC != ISD::SETEQ && CC != ISD::SETNE)
3534 return SDValue();
3535 SDValue SetCC32 = DAG.getSetCC(
3536 dl, MVT::v4i32, DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, LHS),
3537 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, RHS), CC);
3538 int ShuffV[] = {1, 0, 3, 2};
3539 SDValue Shuff =
3540 DAG.getVectorShuffle(MVT::v4i32, dl, SetCC32, SetCC32, ShuffV);
3541 return DAG.getBitcast(MVT::v2i64,
3542 DAG.getNode(CC == ISD::SETEQ ? ISD::AND : ISD::OR,
3543 dl, MVT::v4i32, Shuff, SetCC32));
3544 }
3545
3546 // We handle most of these in the usual way.
3547 return Op;
3548 }
3549
3550 // If we're comparing for equality to zero, expose the fact that this is
3551 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
3552 // fold the new nodes.
3553 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
3554 return V;
3555
3556 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) {
3557 // Leave comparisons against 0 and -1 alone for now, since they're usually
3558 // optimized. FIXME: revisit this when we can custom lower all setcc
3559 // optimizations.
3560 if (C->isAllOnes() || C->isZero())
3561 return SDValue();
3562 }
3563
3564 // If we have an integer seteq/setne, turn it into a compare against zero
3565 // by xor'ing the rhs with the lhs, which is faster than setting a
3566 // condition register, reading it back out, and masking the correct bit. The
3567 // normal approach here uses sub to do this instead of xor. Using xor exposes
3568 // the result to other bit-twiddling opportunities.
3569 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
3570 EVT VT = Op.getValueType();
3571 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, LHS, RHS);
3572 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
3573 }
3574 return SDValue();
3575}
3576
3577SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3578 SDNode *Node = Op.getNode();
3579 EVT VT = Node->getValueType(0);
3580 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3581 SDValue InChain = Node->getOperand(0);
3582 SDValue VAListPtr = Node->getOperand(1);
3583 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3584 SDLoc dl(Node);
3585
3586 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")(static_cast <bool> (!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"
) ? void (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVAARG is PPC32 only\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3586, __extension__
__PRETTY_FUNCTION__))
;
3587
3588 // gpr_index
3589 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3590 VAListPtr, MachinePointerInfo(SV), MVT::i8);
3591 InChain = GprIndex.getValue(1);
3592
3593 if (VT == MVT::i64) {
3594 // Check if GprIndex is even
3595 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
3596 DAG.getConstant(1, dl, MVT::i32));
3597 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
3598 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
3599 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
3600 DAG.getConstant(1, dl, MVT::i32));
3601 // Align GprIndex to be even if it isn't
3602 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
3603 GprIndex);
3604 }
3605
3606 // fpr index is 1 byte after gpr
3607 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3608 DAG.getConstant(1, dl, MVT::i32));
3609
3610 // fpr
3611 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3612 FprPtr, MachinePointerInfo(SV), MVT::i8);
3613 InChain = FprIndex.getValue(1);
3614
3615 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3616 DAG.getConstant(8, dl, MVT::i32));
3617
3618 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3619 DAG.getConstant(4, dl, MVT::i32));
3620
3621 // areas
3622 SDValue OverflowArea =
3623 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
3624 InChain = OverflowArea.getValue(1);
3625
3626 SDValue RegSaveArea =
3627 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
3628 InChain = RegSaveArea.getValue(1);
3629
3630 // select overflow_area if index > 8
3631 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3632 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
3633
3634 // adjustment constant gpr_index * 4/8
3635 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
3636 VT.isInteger() ? GprIndex : FprIndex,
3637 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3638 MVT::i32));
3639
3640 // OurReg = RegSaveArea + RegConstant
3641 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
3642 RegConstant);
3643
3644 // Floating types are 32 bytes into RegSaveArea
3645 if (VT.isFloatingPoint())
3646 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
3647 DAG.getConstant(32, dl, MVT::i32));
3648
3649 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
3650 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3651 VT.isInteger() ? GprIndex : FprIndex,
3652 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
3653 MVT::i32));
3654
3655 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
3656 VT.isInteger() ? VAListPtr : FprPtr,
3657 MachinePointerInfo(SV), MVT::i8);
3658
3659 // determine if we should load from reg_save_area or overflow_area
3660 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3661
3662 // increase overflow_area by 4/8 if gpr/fpr > 8
3663 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
3664 DAG.getConstant(VT.isInteger() ? 4 : 8,
3665 dl, MVT::i32));
3666
3667 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
3668 OverflowAreaPlusN);
3669
3670 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
3671 MachinePointerInfo(), MVT::i32);
3672
3673 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
3674}
3675
3676SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3677 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only")(static_cast <bool> (!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"
) ? void (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVACOPY is PPC32 only\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3677, __extension__
__PRETTY_FUNCTION__))
;
3678
3679 // We have to copy the entire va_list struct:
3680 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3681 return DAG.getMemcpy(Op.getOperand(0), Op, Op.getOperand(1), Op.getOperand(2),
3682 DAG.getConstant(12, SDLoc(Op), MVT::i32), Align(8),
3683 false, true, false, MachinePointerInfo(),
3684 MachinePointerInfo());
3685}
3686
3687SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3688 SelectionDAG &DAG) const {
3689 if (Subtarget.isAIXABI())
3690 report_fatal_error("ADJUST_TRAMPOLINE operation is not supported on AIX.");
3691
3692 return Op.getOperand(0);
3693}
3694
3695SDValue PPCTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
3696 MachineFunction &MF = DAG.getMachineFunction();
3697 PPCFunctionInfo &MFI = *MF.getInfo<PPCFunctionInfo>();
3698
3699 assert((Op.getOpcode() == ISD::INLINEASM ||(static_cast <bool> ((Op.getOpcode() == ISD::INLINEASM ||
Op.getOpcode() == ISD::INLINEASM_BR) && "Expecting Inline ASM node."
) ? void (0) : __assert_fail ("(Op.getOpcode() == ISD::INLINEASM || Op.getOpcode() == ISD::INLINEASM_BR) && \"Expecting Inline ASM node.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3701, __extension__
__PRETTY_FUNCTION__))
3700 Op.getOpcode() == ISD::INLINEASM_BR) &&(static_cast <bool> ((Op.getOpcode() == ISD::INLINEASM ||
Op.getOpcode() == ISD::INLINEASM_BR) && "Expecting Inline ASM node."
) ? void (0) : __assert_fail ("(Op.getOpcode() == ISD::INLINEASM || Op.getOpcode() == ISD::INLINEASM_BR) && \"Expecting Inline ASM node.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3701, __extension__
__PRETTY_FUNCTION__))
3701 "Expecting Inline ASM node.")(static_cast <bool> ((Op.getOpcode() == ISD::INLINEASM ||
Op.getOpcode() == ISD::INLINEASM_BR) && "Expecting Inline ASM node."
) ? void (0) : __assert_fail ("(Op.getOpcode() == ISD::INLINEASM || Op.getOpcode() == ISD::INLINEASM_BR) && \"Expecting Inline ASM node.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3701, __extension__
__PRETTY_FUNCTION__))
;
3702
3703 // If an LR store is already known to be required then there is not point in
3704 // checking this ASM as well.
3705 if (MFI.isLRStoreRequired())
3706 return Op;
3707
3708 // Inline ASM nodes have an optional last operand that is an incoming Flag of
3709 // type MVT::Glue. We want to ignore this last operand if that is the case.
3710 unsigned NumOps = Op.getNumOperands();
3711 if (Op.getOperand(NumOps - 1).getValueType() == MVT::Glue)
3712 --NumOps;
3713
3714 // Check all operands that may contain the LR.
3715 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
3716 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
3717 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
3718 ++i; // Skip the ID value.
3719
3720 switch (InlineAsm::getKind(Flags)) {
3721 default:
3722 llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3722)
;
3723 case InlineAsm::Kind_RegUse:
3724 case InlineAsm::Kind_Imm:
3725 case InlineAsm::Kind_Mem:
3726 i += NumVals;
3727 break;
3728 case InlineAsm::Kind_Clobber:
3729 case InlineAsm::Kind_RegDef:
3730 case InlineAsm::Kind_RegDefEarlyClobber: {
3731 for (; NumVals; --NumVals, ++i) {
3732 Register Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
3733 if (Reg != PPC::LR && Reg != PPC::LR8)
3734 continue;
3735 MFI.setLRStoreRequired();
3736 return Op;
3737 }
3738 break;
3739 }
3740 }
3741 }
3742
3743 return Op;
3744}
3745
3746SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3747 SelectionDAG &DAG) const {
3748 if (Subtarget.isAIXABI())
3749 report_fatal_error("INIT_TRAMPOLINE operation is not supported on AIX.");
3750
3751 SDValue Chain = Op.getOperand(0);
3752 SDValue Trmp = Op.getOperand(1); // trampoline
3753 SDValue FPtr = Op.getOperand(2); // nested function
3754 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3755 SDLoc dl(Op);
3756
3757 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3758 bool isPPC64 = (PtrVT == MVT::i64);
3759 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3760
3761 TargetLowering::ArgListTy Args;
3762 TargetLowering::ArgListEntry Entry;
3763
3764 Entry.Ty = IntPtrTy;
3765 Entry.Node = Trmp; Args.push_back(Entry);
3766
3767 // TrampSize == (isPPC64 ? 48 : 40);
3768 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3769 isPPC64 ? MVT::i64 : MVT::i32);
3770 Args.push_back(Entry);
3771
3772 Entry.Node = FPtr; Args.push_back(Entry);
3773 Entry.Node = Nest; Args.push_back(Entry);
3774
3775 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3776 TargetLowering::CallLoweringInfo CLI(DAG);
3777 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3778 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3779 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3780
3781 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3782 return CallResult.second;
3783}
3784
3785SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3786 MachineFunction &MF = DAG.getMachineFunction();
3787 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3788 EVT PtrVT = getPointerTy(MF.getDataLayout());
3789
3790 SDLoc dl(Op);
3791
3792 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) {
3793 // vastart just stores the address of the VarArgsFrameIndex slot into the
3794 // memory location argument.
3795 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3796 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3797 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3798 MachinePointerInfo(SV));
3799 }
3800
3801 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3802 // We suppose the given va_list is already allocated.
3803 //
3804 // typedef struct {
3805 // char gpr; /* index into the array of 8 GPRs
3806 // * stored in the register save area
3807 // * gpr=0 corresponds to r3,
3808 // * gpr=1 to r4, etc.
3809 // */
3810 // char fpr; /* index into the array of 8 FPRs
3811 // * stored in the register save area
3812 // * fpr=0 corresponds to f1,
3813 // * fpr=1 to f2, etc.
3814 // */
3815 // char *overflow_arg_area;
3816 // /* location on stack that holds
3817 // * the next overflow argument
3818 // */
3819 // char *reg_save_area;
3820 // /* where r3:r10 and f1:f8 (if saved)
3821 // * are stored
3822 // */
3823 // } va_list[1];
3824
3825 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3826 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3827 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3828 PtrVT);
3829 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3830 PtrVT);
3831
3832 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3833 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3834
3835 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3836 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3837
3838 uint64_t FPROffset = 1;
3839 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3840
3841 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3842
3843 // Store first byte : number of int regs
3844 SDValue firstStore =
3845 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3846 MachinePointerInfo(SV), MVT::i8);
3847 uint64_t nextOffset = FPROffset;
3848 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3849 ConstFPROffset);
3850
3851 // Store second byte : number of float regs
3852 SDValue secondStore =
3853 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3854 MachinePointerInfo(SV, nextOffset), MVT::i8);
3855 nextOffset += StackOffset;
3856 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3857
3858 // Store second word : arguments given on stack
3859 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3860 MachinePointerInfo(SV, nextOffset));
3861 nextOffset += FrameOffset;
3862 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3863
3864 // Store third word : arguments given in registers
3865 return DAG.getStore(thirdStore, dl, FR, nextPtr,
3866 MachinePointerInfo(SV, nextOffset));
3867}
3868
3869/// FPR - The set of FP registers that should be allocated for arguments
3870/// on Darwin and AIX.
3871static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3872 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3873 PPC::F11, PPC::F12, PPC::F13};
3874
3875/// CalculateStackSlotSize - Calculates the size reserved for this argument on
3876/// the stack.
3877static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3878 unsigned PtrByteSize) {
3879 unsigned ArgSize = ArgVT.getStoreSize();
3880 if (Flags.isByVal())
3881 ArgSize = Flags.getByValSize();
3882
3883 // Round up to multiples of the pointer size, except for array members,
3884 // which are always packed.
3885 if (!Flags.isInConsecutiveRegs())
3886 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3887
3888 return ArgSize;
3889}
3890
3891/// CalculateStackSlotAlignment - Calculates the alignment of this argument
3892/// on the stack.
3893static Align CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3894 ISD::ArgFlagsTy Flags,
3895 unsigned PtrByteSize) {
3896 Align Alignment(PtrByteSize);
3897
3898 // Altivec parameters are padded to a 16 byte boundary.
3899 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3900 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3901 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3902 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3903 Alignment = Align(16);
3904
3905 // ByVal parameters are aligned as requested.
3906 if (Flags.isByVal()) {
3907 auto BVAlign = Flags.getNonZeroByValAlign();
3908 if (BVAlign > PtrByteSize) {
3909 if (BVAlign.value() % PtrByteSize != 0)
3910 llvm_unreachable(::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3911)
3911 "ByVal alignment is not a multiple of the pointer size")::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 3911)
;
3912
3913 Alignment = BVAlign;
3914 }
3915 }
3916
3917 // Array members are always packed to their original alignment.
3918 if (Flags.isInConsecutiveRegs()) {
3919 // If the array member was split into multiple registers, the first
3920 // needs to be aligned to the size of the full type. (Except for
3921 // ppcf128, which is only aligned as its f64 components.)
3922 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3923 Alignment = Align(OrigVT.getStoreSize());
3924 else
3925 Alignment = Align(ArgVT.getStoreSize());
3926 }
3927
3928 return Alignment;
3929}
3930
3931/// CalculateStackSlotUsed - Return whether this argument will use its
3932/// stack slot (instead of being passed in registers). ArgOffset,
3933/// AvailableFPRs, and AvailableVRs must hold the current argument
3934/// position, and will be updated to account for this argument.
3935static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags,
3936 unsigned PtrByteSize, unsigned LinkageSize,
3937 unsigned ParamAreaSize, unsigned &ArgOffset,
3938 unsigned &AvailableFPRs,
3939 unsigned &AvailableVRs) {
3940 bool UseMemory = false;
3941
3942 // Respect alignment of argument on the stack.
3943 Align Alignment =
3944 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3945 ArgOffset = alignTo(ArgOffset, Alignment);
3946 // If there's no space left in the argument save area, we must
3947 // use memory (this check also catches zero-sized arguments).
3948 if (ArgOffset >= LinkageSize + ParamAreaSize)
3949 UseMemory = true;
3950
3951 // Allocate argument on the stack.
3952 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3953 if (Flags.isInConsecutiveRegsLast())
3954 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3955 // If we overran the argument save area, we must use memory
3956 // (this check catches arguments passed partially in memory)
3957 if (ArgOffset > LinkageSize + ParamAreaSize)
3958 UseMemory = true;
3959
3960 // However, if the argument is actually passed in an FPR or a VR,
3961 // we don't use memory after all.
3962 if (!Flags.isByVal()) {
3963 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
3964 if (AvailableFPRs > 0) {
3965 --AvailableFPRs;
3966 return false;
3967 }
3968 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3969 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3970 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3971 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3972 if (AvailableVRs > 0) {
3973 --AvailableVRs;
3974 return false;
3975 }
3976 }
3977
3978 return UseMemory;
3979}
3980
3981/// EnsureStackAlignment - Round stack frame size up from NumBytes to
3982/// ensure minimum alignment required for target.
3983static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3984 unsigned NumBytes) {
3985 return alignTo(NumBytes, Lowering->getStackAlign());
3986}
3987
3988SDValue PPCTargetLowering::LowerFormalArguments(
3989 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3990 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3991 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3992 if (Subtarget.isAIXABI())
3993 return LowerFormalArguments_AIX(Chain, CallConv, isVarArg, Ins, dl, DAG,
3994 InVals);
3995 if (Subtarget.is64BitELFABI())
3996 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3997 InVals);
3998 assert(Subtarget.is32BitELFABI())(static_cast <bool> (Subtarget.is32BitELFABI()) ? void (
0) : __assert_fail ("Subtarget.is32BitELFABI()", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3998, __extension__ __PRETTY_FUNCTION__))
;
3999 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
4000 InVals);
4001}
4002
4003SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
4004 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4005 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4006 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4007
4008 // 32-bit SVR4 ABI Stack Frame Layout:
4009 // +-----------------------------------+
4010 // +--> | Back chain |
4011 // | +-----------------------------------+
4012 // | | Floating-point register save area |
4013 // | +-----------------------------------+
4014 // | | General register save area |
4015 // | +-----------------------------------+
4016 // | | CR save word |
4017 // | +-----------------------------------+
4018 // | | VRSAVE save word |
4019 // | +-----------------------------------+
4020 // | | Alignment padding |
4021 // | +-----------------------------------+
4022 // | | Vector register save area |
4023 // | +-----------------------------------+
4024 // | | Local variable space |
4025 // | +-----------------------------------+
4026 // | | Parameter list area |
4027 // | +-----------------------------------+
4028 // | | LR save word |
4029 // | +-----------------------------------+
4030 // SP--> +--- | Back chain |
4031 // +-----------------------------------+
4032 //
4033 // Specifications:
4034 // System V Application Binary Interface PowerPC Processor Supplement
4035 // AltiVec Technology Programming Interface Manual
4036
4037 MachineFunction &MF = DAG.getMachineFunction();
4038 MachineFrameInfo &MFI = MF.getFrameInfo();
4039 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4040
4041 EVT PtrVT = getPointerTy(MF.getDataLayout());
4042 // Potential tail calls could cause overwriting of argument stack slots.
4043 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4044 (CallConv == CallingConv::Fast));
4045 const Align PtrAlign(4);
4046
4047 // Assign locations to all of the incoming arguments.
4048 SmallVector<CCValAssign, 16> ArgLocs;
4049 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4050 *DAG.getContext());
4051
4052 // Reserve space for the linkage area on the stack.
4053 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4054 CCInfo.AllocateStack(LinkageSize, PtrAlign);
4055 if (useSoftFloat())
4056 CCInfo.PreAnalyzeFormalArguments(Ins);
4057
4058 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
4059 CCInfo.clearWasPPCF128();
4060
4061 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4062 CCValAssign &VA = ArgLocs[i];
4063
4064 // Arguments stored in registers.
4065 if (VA.isRegLoc()) {
4066 const TargetRegisterClass *RC;
4067 EVT ValVT = VA.getValVT();
4068
4069 switch (ValVT.getSimpleVT().SimpleTy) {
4070 default:
4071 llvm_unreachable("ValVT not supported by formal arguments Lowering")::llvm::llvm_unreachable_internal("ValVT not supported by formal arguments Lowering"
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4071)
;
4072 case MVT::i1:
4073 case MVT::i32:
4074 RC = &PPC::GPRCRegClass;
4075 break;
4076 case MVT::f32:
4077 if (Subtarget.hasP8Vector())
4078 RC = &PPC::VSSRCRegClass;
4079 else if (Subtarget.hasSPE())
4080 RC = &PPC::GPRCRegClass;
4081 else
4082 RC = &PPC::F4RCRegClass;
4083 break;
4084 case MVT::f64:
4085 if (Subtarget.hasVSX())
4086 RC = &PPC::VSFRCRegClass;
4087 else if (Subtarget.hasSPE())
4088 // SPE passes doubles in GPR pairs.
4089 RC = &PPC::GPRCRegClass;
4090 else
4091 RC = &PPC::F8RCRegClass;
4092 break;
4093 case MVT::v16i8:
4094 case MVT::v8i16:
4095 case MVT::v4i32:
4096 RC = &PPC::VRRCRegClass;
4097 break;
4098 case MVT::v4f32:
4099 RC = &PPC::VRRCRegClass;
4100 break;
4101 case MVT::v2f64:
4102 case MVT::v2i64:
4103 RC = &PPC::VRRCRegClass;
4104 break;
4105 }
4106
4107 SDValue ArgValue;
4108 // Transform the arguments stored in physical registers into
4109 // virtual ones.
4110 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
4111 assert(i + 1 < e && "No second half of double precision argument")(static_cast <bool> (i + 1 < e && "No second half of double precision argument"
) ? void (0) : __assert_fail ("i + 1 < e && \"No second half of double precision argument\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4111, __extension__
__PRETTY_FUNCTION__))
;
4112 Register RegLo = MF.addLiveIn(VA.getLocReg(), RC);
4113 Register RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC);
4114 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32);
4115 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32);
4116 if (!Subtarget.isLittleEndian())
4117 std::swap (ArgValueLo, ArgValueHi);
4118 ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo,
4119 ArgValueHi);
4120 } else {
4121 Register Reg = MF.addLiveIn(VA.getLocReg(), RC);
4122 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
4123 ValVT == MVT::i1 ? MVT::i32 : ValVT);
4124 if (ValVT == MVT::i1)
4125 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
4126 }
4127
4128 InVals.push_back(ArgValue);
4129 } else {
4130 // Argument stored in memory.
4131 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4131, __extension__ __PRETTY_FUNCTION__))
;
4132
4133 // Get the extended size of the argument type in stack
4134 unsigned ArgSize = VA.getLocVT().getStoreSize();
4135 // Get the actual size of the argument type
4136 unsigned ObjSize = VA.getValVT().getStoreSize();
4137 unsigned ArgOffset = VA.getLocMemOffset();
4138 // Stack objects in PPC32 are right justified.
4139 ArgOffset += ArgSize - ObjSize;
4140 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
4141
4142 // Create load nodes to retrieve arguments from the stack.
4143 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4144 InVals.push_back(
4145 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
4146 }
4147 }
4148
4149 // Assign locations to all of the incoming aggregate by value arguments.
4150 // Aggregates passed by value are stored in the local variable space of the
4151 // caller's stack frame, right above the parameter list area.
4152 SmallVector<CCValAssign, 16> ByValArgLocs;
4153 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4154 ByValArgLocs, *DAG.getContext());
4155
4156 // Reserve stack space for the allocations in CCInfo.
4157 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrAlign);
4158
4159 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
4160
4161 // Area that is at least reserved in the caller of this function.
4162 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
4163 MinReservedArea = std::max(MinReservedArea, LinkageSize);
4164
4165 // Set the size that is at least reserved in caller of this function. Tail
4166 // call optimized function's reserved stack space needs to be aligned so that
4167 // taking the difference between two stack areas will result in an aligned
4168 // stack.
4169 MinReservedArea =
4170 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4171 FuncInfo->setMinReservedArea(MinReservedArea);
4172
4173 SmallVector<SDValue, 8> MemOps;
4174
4175 // If the function takes variable number of arguments, make a frame index for
4176 // the start of the first vararg value... for expansion of llvm.va_start.
4177 if (isVarArg) {
4178 static const MCPhysReg GPArgRegs[] = {
4179 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4180 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4181 };
4182 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
4183
4184 static const MCPhysReg FPArgRegs[] = {
4185 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
4186 PPC::F8
4187 };
4188 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
4189
4190 if (useSoftFloat() || hasSPE())
4191 NumFPArgRegs = 0;
4192
4193 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
4194 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
4195
4196 // Make room for NumGPArgRegs and NumFPArgRegs.
4197 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
4198 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
4199
4200 FuncInfo->setVarArgsStackOffset(
4201 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
4202 CCInfo.getNextStackOffset(), true));
4203
4204 FuncInfo->setVarArgsFrameIndex(
4205 MFI.CreateStackObject(Depth, Align(8), false));
4206 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4207
4208 // The fixed integer arguments of a variadic function are stored to the
4209 // VarArgsFrameIndex on the stack so that they may be loaded by
4210 // dereferencing the result of va_next.
4211 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
4212 // Get an existing live-in vreg, or add a new one.
4213 Register VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
4214 if (!VReg)
4215 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
4216
4217 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4218 SDValue Store =
4219 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4220 MemOps.push_back(Store);
4221 // Increment the address by four for the next argument to store
4222 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4223 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4224 }
4225
4226 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
4227 // is set.
4228 // The double arguments are stored to the VarArgsFrameIndex
4229 // on the stack.
4230 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
4231 // Get an existing live-in vreg, or add a new one.
4232 Register VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
4233 if (!VReg)
4234 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
4235
4236 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
4237 SDValue Store =
4238 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4239 MemOps.push_back(Store);
4240 // Increment the address by eight for the next argument to store
4241 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
4242 PtrVT);
4243 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4244 }
4245 }
4246
4247 if (!MemOps.empty())
4248 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4249
4250 return Chain;
4251}
4252
4253// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4254// value to MVT::i64 and then truncate to the correct register size.
4255SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
4256 EVT ObjectVT, SelectionDAG &DAG,
4257 SDValue ArgVal,
4258 const SDLoc &dl) const {
4259 if (Flags.isSExt())
4260 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
4261 DAG.getValueType(ObjectVT));
4262 else if (Flags.isZExt())
4263 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
4264 DAG.getValueType(ObjectVT));
4265
4266 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
4267}
4268
4269SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
4270 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4271 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4272 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4273 // TODO: add description of PPC stack frame format, or at least some docs.
4274 //
4275 bool isELFv2ABI = Subtarget.isELFv2ABI();
4276 bool isLittleEndian = Subtarget.isLittleEndian();
4277 MachineFunction &MF = DAG.getMachineFunction();
4278 MachineFrameInfo &MFI = MF.getFrameInfo();
4279 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4280
4281 assert(!(CallConv == CallingConv::Fast && isVarArg) &&(static_cast <bool> (!(CallConv == CallingConv::Fast &&
isVarArg) && "fastcc not supported on varargs functions"
) ? void (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4282, __extension__
__PRETTY_FUNCTION__))
4282 "fastcc not supported on varargs functions")(static_cast <bool> (!(CallConv == CallingConv::Fast &&
isVarArg) && "fastcc not supported on varargs functions"
) ? void (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4282, __extension__
__PRETTY_FUNCTION__))
;
4283
4284 EVT PtrVT = getPointerTy(MF.getDataLayout());
4285 // Potential tail calls could cause overwriting of argument stack slots.
4286 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4287 (CallConv == CallingConv::Fast));
4288 unsigned PtrByteSize = 8;
4289 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4290
4291 static const MCPhysReg GPR[] = {
4292 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4293 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4294 };
4295 static const MCPhysReg VR[] = {
4296 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4297 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4298 };
4299
4300 const unsigned Num_GPR_Regs = array_lengthof(GPR);
4301 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4302 const unsigned Num_VR_Regs = array_lengthof(VR);
4303
4304 // Do a first pass over the arguments to determine whether the ABI
4305 // guarantees that our caller has allocated the parameter save area
4306 // on its stack frame. In the ELFv1 ABI, this is always the case;
4307 // in the ELFv2 ABI, it is true if this is a vararg function or if
4308 // any parameter is located in a stack slot.
4309
4310 bool HasParameterArea = !isELFv2ABI || isVarArg;
4311 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
4312 unsigned NumBytes = LinkageSize;
4313 unsigned AvailableFPRs = Num_FPR_Regs;
4314 unsigned AvailableVRs = Num_VR_Regs;
4315 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
4316 if (Ins[i].Flags.isNest())
4317 continue;
4318
4319 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
4320 PtrByteSize, LinkageSize, ParamAreaSize,
4321 NumBytes, AvailableFPRs, AvailableVRs))
4322 HasParameterArea = true;
4323 }
4324
4325 // Add DAG nodes to load the arguments or copy them out of registers. On
4326 // entry to a function on PPC, the arguments start after the linkage area,
4327 // although the first ones are often in registers.
4328
4329 unsigned ArgOffset = LinkageSize;
4330 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4331 SmallVector<SDValue, 8> MemOps;
4332 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4333 unsigned CurArgIdx = 0;
4334 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4335 SDValue ArgVal;
4336 bool needsLoad = false;
4337 EVT ObjectVT = Ins[ArgNo].VT;
4338 EVT OrigVT = Ins[ArgNo].ArgVT;
4339 unsigned ObjSize = ObjectVT.getStoreSize();
4340 unsigned ArgSize = ObjSize;
4341 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4342 if (Ins[ArgNo].isOrigArg()) {
4343 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4344 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4345 }
4346 // We re-align the argument offset for each argument, except when using the
4347 // fast calling convention, when we need to make sure we do that only when
4348 // we'll actually use a stack slot.
4349 unsigned CurArgOffset;
4350 Align Alignment;
4351 auto ComputeArgOffset = [&]() {
4352 /* Respect alignment of argument on the stack. */
4353 Alignment =
4354 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
4355 ArgOffset = alignTo(ArgOffset, Alignment);
4356 CurArgOffset = ArgOffset;
4357 };
4358
4359 if (CallConv != CallingConv::Fast) {
4360 ComputeArgOffset();
4361
4362 /* Compute GPR index associated with argument offset. */
4363 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4364 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
4365 }
4366
4367 // FIXME the codegen can be much improved in some cases.
4368 // We do not have to keep everything in memory.
4369 if (Flags.isByVal()) {
4370 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")(static_cast <bool> (Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4370, __extension__
__PRETTY_FUNCTION__))
;
4371
4372 if (CallConv == CallingConv::Fast)
4373 ComputeArgOffset();
4374
4375 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4376 ObjSize = Flags.getByValSize();
4377 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4378 // Empty aggregate parameters do not take up registers. Examples:
4379 // struct { } a;
4380 // union { } b;
4381 // int c[0];
4382 // etc. However, we have to provide a place-holder in InVals, so
4383 // pretend we have an 8-byte item at the current address for that
4384 // purpose.
4385 if (!ObjSize) {
4386 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4387 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4388 InVals.push_back(FIN);
4389 continue;
4390 }
4391
4392 // Create a stack object covering all stack doublewords occupied
4393 // by the argument. If the argument is (fully or partially) on
4394 // the stack, or if the argument is fully in registers but the
4395 // caller has allocated the parameter save anyway, we can refer
4396 // directly to the caller's stack frame. Otherwise, create a
4397 // local copy in our own frame.
4398 int FI;
4399 if (HasParameterArea ||
4400 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
4401 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
4402 else
4403 FI = MFI.CreateStackObject(ArgSize, Alignment, false);
4404 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4405
4406 // Handle aggregates smaller than 8 bytes.
4407 if (ObjSize < PtrByteSize) {
4408 // The value of the object is its address, which differs from the
4409 // address of the enclosing doubleword on big-endian systems.
4410 SDValue Arg = FIN;
4411 if (!isLittleEndian) {
4412 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
4413 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
4414 }
4415 InVals.push_back(Arg);
4416
4417 if (GPR_idx != Num_GPR_Regs) {
4418 Register VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4419 FuncInfo->addLiveInAttr(VReg, Flags);
4420 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4421 EVT ObjType = EVT::getIntegerVT(*DAG.getContext(), ObjSize * 8);
4422 SDValue Store =
4423 DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
4424 MachinePointerInfo(&*FuncArg), ObjType);
4425 MemOps.push_back(Store);
4426 }
4427 // Whether we copied from a register or not, advance the offset
4428 // into the parameter save area by a full doubleword.
4429 ArgOffset += PtrByteSize;
4430 continue;
4431 }
4432
4433 // The value of the object is its address, which is the address of
4434 // its first stack doubleword.
4435 InVals.push_back(FIN);
4436
4437 // Store whatever pieces of the object are in registers to memory.
4438 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4439 if (GPR_idx == Num_GPR_Regs)
4440 break;
4441
4442 Register VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4443 FuncInfo->addLiveInAttr(VReg, Flags);
4444 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4445 SDValue Addr = FIN;
4446 if (j) {
4447 SDValue Off = DAG.getConstant(j, dl, PtrVT);
4448 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
4449 }
4450 unsigned StoreSizeInBits = std::min(PtrByteSize, (ObjSize - j)) * 8;
4451 EVT ObjType = EVT::getIntegerVT(*DAG.getContext(), StoreSizeInBits);
4452 SDValue Store =
4453 DAG.getTruncStore(Val.getValue(1), dl, Val, Addr,
4454 MachinePointerInfo(&*FuncArg, j), ObjType);
4455 MemOps.push_back(Store);
4456 ++GPR_idx;
4457 }
4458 ArgOffset += ArgSize;
4459 continue;
4460 }
4461
4462 switch (ObjectVT.getSimpleVT().SimpleTy) {
4463 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4463)
;
4464 case MVT::i1:
4465 case MVT::i32:
4466 case MVT::i64:
4467 if (Flags.isNest()) {
4468 // The 'nest' parameter, if any, is passed in R11.
4469 Register VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
4470 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4471
4472 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4473 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4474
4475 break;
4476 }
4477
4478 // These can be scalar arguments or elements of an integer array type
4479 // passed directly. Clang may use those instead of "byval" aggregate
4480 // types to avoid forcing arguments to memory unnecessarily.
4481 if (GPR_idx != Num_GPR_Regs) {
4482 Register VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4483 FuncInfo->addLiveInAttr(VReg, Flags);
4484 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4485
4486 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4487 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4488 // value to MVT::i64 and then truncate to the correct register size.
4489 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4490 } else {
4491 if (CallConv == CallingConv::Fast)
4492 ComputeArgOffset();
4493
4494 needsLoad = true;
4495 ArgSize = PtrByteSize;
4496 }
4497 if (CallConv != CallingConv::Fast || needsLoad)
4498 ArgOffset += 8;
4499 break;
4500
4501 case MVT::f32:
4502 case MVT::f64:
4503 // These can be scalar arguments or elements of a float array type
4504 // passed directly. The latter are used to implement ELFv2 homogenous
4505 // float aggregates.
4506 if (FPR_idx != Num_FPR_Regs) {
4507 unsigned VReg;
4508
4509 if (ObjectVT == MVT::f32)
4510 VReg = MF.addLiveIn(FPR[FPR_idx],
4511 Subtarget.hasP8Vector()
4512 ? &PPC::VSSRCRegClass
4513 : &PPC::F4RCRegClass);
4514 else
4515 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
4516 ? &PPC::VSFRCRegClass
4517 : &PPC::F8RCRegClass);
4518
4519 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4520 ++FPR_idx;
4521 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
4522 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4523 // once we support fp <-> gpr moves.
4524
4525 // This can only ever happen in the presence of f32 array types,
4526 // since otherwise we never run out of FPRs before running out
4527 // of GPRs.
4528 Register VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4529 FuncInfo->addLiveInAttr(VReg, Flags);
4530 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4531
4532 if (ObjectVT == MVT::f32) {
4533 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
4534 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
4535 DAG.getConstant(32, dl, MVT::i32));
4536 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
4537 }
4538
4539 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
4540 } else {
4541 if (CallConv == CallingConv::Fast)
4542 ComputeArgOffset();
4543
4544 needsLoad = true;
4545 }
4546
4547 // When passing an array of floats, the array occupies consecutive
4548 // space in the argument area; only round up to the next doubleword
4549 // at the end of the array. Otherwise, each float takes 8 bytes.
4550 if (CallConv != CallingConv::Fast || needsLoad) {
4551 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
4552 ArgOffset += ArgSize;
4553 if (Flags.isInConsecutiveRegsLast())
4554 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4555 }
4556 break;
4557 case MVT::v4f32:
4558 case MVT::v4i32:
4559 case MVT::v8i16:
4560 case MVT::v16i8:
4561 case MVT::v2f64:
4562 case MVT::v2i64:
4563 case MVT::v1i128:
4564 case MVT::f128:
4565 // These can be scalar arguments or elements of a vector array type
4566 // passed directly. The latter are used to implement ELFv2 homogenous
4567 // vector aggregates.
4568 if (VR_idx != Num_VR_Regs) {
4569 Register VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4570 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4571 ++VR_idx;
4572 } else {
4573 if (CallConv == CallingConv::Fast)
4574 ComputeArgOffset();
4575 needsLoad = true;
4576 }
4577 if (CallConv != CallingConv::Fast || needsLoad)
4578 ArgOffset += 16;
4579 break;
4580 }
4581
4582 // We need to load the argument to a virtual register if we determined
4583 // above that we ran out of physical registers of the appropriate type.
4584 if (needsLoad) {
4585 if (ObjSize < ArgSize && !isLittleEndian)
4586 CurArgOffset += ArgSize - ObjSize;
4587 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
4588 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4589 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4590 }
4591
4592 InVals.push_back(ArgVal);
4593 }
4594
4595 // Area that is at least reserved in the caller of this function.
4596 unsigned MinReservedArea;
4597 if (HasParameterArea)
4598 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
4599 else
4600 MinReservedArea = LinkageSize;
4601
4602 // Set the size that is at least reserved in caller of this function. Tail
4603 // call optimized functions' reserved stack space needs to be aligned so that
4604 // taking the difference between two stack areas will result in an aligned
4605 // stack.
4606 MinReservedArea =
4607 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4608 FuncInfo->setMinReservedArea(MinReservedArea);
4609
4610 // If the function takes variable number of arguments, make a frame index for
4611 // the start of the first vararg value... for expansion of llvm.va_start.
4612 // On ELFv2ABI spec, it writes:
4613 // C programs that are intended to be *portable* across different compilers
4614 // and architectures must use the header file <stdarg.h> to deal with variable
4615 // argument lists.
4616 if (isVarArg && MFI.hasVAStart()) {
4617 int Depth = ArgOffset;
4618
4619 FuncInfo->setVarArgsFrameIndex(
4620 MFI.CreateFixedObject(PtrByteSize, Depth, true));
4621 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4622
4623 // If this function is vararg, store any remaining integer argument regs
4624 // to their spots on the stack so that they may be loaded by dereferencing
4625 // the result of va_next.
4626 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4627 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4628 Register VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4629 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4630 SDValue Store =
4631 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4632 MemOps.push_back(Store);
4633 // Increment the address by four for the next argument to store
4634 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4635 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4636 }
4637 }
4638
4639 if (!MemOps.empty())
4640 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4641
4642 return Chain;
4643}
4644
4645/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4646/// adjusted to accommodate the arguments for the tailcall.
4647static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4648 unsigned ParamSize) {
4649
4650 if (!isTailCall) return 0;
4651
4652 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4653 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4654 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4655 // Remember only if the new adjustment is bigger.
4656 if (SPDiff < FI->getTailCallSPDelta())
4657 FI->setTailCallSPDelta(SPDiff);
4658
4659 return SPDiff;
4660}
4661
4662static bool isFunctionGlobalAddress(SDValue Callee);
4663
4664static bool callsShareTOCBase(const Function *Caller, SDValue Callee,
4665 const TargetMachine &TM) {
4666 // It does not make sense to call callsShareTOCBase() with a caller that
4667 // is PC Relative since PC Relative callers do not have a TOC.
4668#ifndef NDEBUG
4669 const PPCSubtarget *STICaller = &TM.getSubtarget<PPCSubtarget>(*Caller);
4670 assert(!STICaller->isUsingPCRelativeCalls() &&(static_cast <bool> (!STICaller->isUsingPCRelativeCalls
() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? void (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4671, __extension__
__PRETTY_FUNCTION__))
4671 "PC Relative callers do not have a TOC and cannot share a TOC Base")(static_cast <bool> (!STICaller->isUsingPCRelativeCalls
() && "PC Relative callers do not have a TOC and cannot share a TOC Base"
) ? void (0) : __assert_fail ("!STICaller->isUsingPCRelativeCalls() && \"PC Relative callers do not have a TOC and cannot share a TOC Base\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 4671, __extension__
__PRETTY_FUNCTION__))
;
4672#endif
4673
4674 // Callee is either a GlobalAddress or an ExternalSymbol. ExternalSymbols
4675 // don't have enough information to determine if the caller and callee share
4676 // the same TOC base, so we have to pessimistically assume they don't for
4677 // correctness.
4678 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4679 if (!G)
4680 return false;
4681
4682 const GlobalValue *GV = G->getGlobal();
4683
4684 // If the callee is preemptable, then the static linker will use a plt-stub
4685 // which saves the toc to the stack, and needs a nop after the call
4686 // instruction to convert to a toc-restore.
4687 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4688 return false;
4689
4690 // Functions with PC Relative enabled may clobber the TOC in the same DSO.
4691 // We may need a TOC restore in the situation where the caller requires a
4692 // valid TOC but the callee is PC Relative and does not.
4693 const Function *F = dyn_cast<Function>(GV);
4694 const GlobalAlias *Alias = dyn_cast<GlobalAlias>(GV);
4695
4696 // If we have an Alias we can try to get the function from there.
4697 if (Alias) {
4698 const GlobalObject *GlobalObj = Alias->getAliaseeObject();
4699 F = dyn_cast<Function>(GlobalObj);
4700 }
4701
4702 // If we still have no valid function pointer we do not have enough
4703 // information to determine if the callee uses PC Relative calls so we must
4704 // assume that it does.
4705 if (!F)
4706 return false;
4707
4708 // If the callee uses PC Relative we cannot guarantee that the callee won't
4709 // clobber the TOC of the caller and so we must assume that the two
4710 // functions do not share a TOC base.
4711 const PPCSubtarget *STICallee = &TM.getSubtarget<PPCSubtarget>(*F);
4712 if (STICallee->isUsingPCRelativeCalls())
4713 return false;
4714
4715 // If the GV is not a strong definition then we need to assume it can be
4716 // replaced by another function at link time. The function that replaces
4717 // it may not share the same TOC as the caller since the callee may be
4718 // replaced by a PC Relative version of the same function.
4719 if (!GV->isStrongDefinitionForLinker())
4720 return false;
4721
4722 // The medium and large code models are expected to provide a sufficiently
4723 // large TOC to provide all data addressing needs of a module with a
4724 // single TOC.
4725 if (CodeModel::Medium == TM.getCodeModel() ||
4726 CodeModel::Large == TM.getCodeModel())
4727 return true;
4728
4729 // Any explicitly-specified sections and section prefixes must also match.
4730 // Also, if we're using -ffunction-sections, then each function is always in
4731 // a different section (the same is true for COMDAT functions).
4732 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4733 GV->getSection() != Caller->getSection())
4734 return false;
4735 if (const auto *F = dyn_cast<Function>(GV)) {
4736 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4737 return false;
4738 }
4739
4740 return true;
4741}
4742
4743static bool
4744needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4745 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4746 assert(Subtarget.is64BitELFABI())(static_cast <bool> (Subtarget.is64BitELFABI()) ? void (
0) : __assert_fail ("Subtarget.is64BitELFABI()", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4746, __extension__ __PRETTY_FUNCTION__))
;
4747
4748 const unsigned PtrByteSize = 8;
4749 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4750
4751 static const MCPhysReg GPR[] = {
4752 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4753 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4754 };
4755 static const MCPhysReg VR[] = {
4756 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4757 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4758 };
4759
4760 const unsigned NumGPRs = array_lengthof(GPR);
4761 const unsigned NumFPRs = 13;
4762 const unsigned NumVRs = array_lengthof(VR);
4763 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4764
4765 unsigned NumBytes = LinkageSize;
4766 unsigned AvailableFPRs = NumFPRs;
4767 unsigned AvailableVRs = NumVRs;
4768
4769 for (const ISD::OutputArg& Param : Outs) {
4770 if (Param.Flags.isNest()) continue;
4771
4772 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags, PtrByteSize,
4773 LinkageSize, ParamAreaSize, NumBytes,
4774 AvailableFPRs, AvailableVRs))
4775 return true;
4776 }
4777 return false;
4778}
4779
4780static bool hasSameArgumentList(const Function *CallerFn, const CallBase &CB) {
4781 if (CB.arg_size() != CallerFn->arg_size())
4782 return false;
4783
4784 auto CalleeArgIter = CB.arg_begin();
4785 auto CalleeArgEnd = CB.arg_end();
4786 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4787
4788 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4789 const Value* CalleeArg = *CalleeArgIter;
4790 const Value* CallerArg = &(*CallerArgIter);
4791 if (CalleeArg == CallerArg)
4792 continue;
4793
4794 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4795 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4796 // }
4797 // 1st argument of callee is undef and has the same type as caller.
4798 if (CalleeArg->getType() == CallerArg->getType() &&
4799 isa<UndefValue>(CalleeArg))
4800 continue;
4801
4802 return false;
4803 }
4804
4805 return true;
4806}
4807
4808// Returns true if TCO is possible between the callers and callees
4809// calling conventions.
4810static bool
4811areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4812 CallingConv::ID CalleeCC) {
4813 // Tail calls are possible with fastcc and ccc.
4814 auto isTailCallableCC = [] (CallingConv::ID CC){
4815 return CC == CallingConv::C || CC == CallingConv::Fast;
4816 };
4817 if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC))
4818 return false;
4819
4820 // We can safely tail call both fastcc and ccc callees from a c calling
4821 // convention caller. If the caller is fastcc, we may have less stack space
4822 // than a non-fastcc caller with the same signature so disable tail-calls in
4823 // that case.
4824 return CallerCC == CallingConv::C || CallerCC == CalleeCC;
4825}
4826
4827bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4828 SDValue Callee, CallingConv::ID CalleeCC, const CallBase *CB, bool isVarArg,
4829 const SmallVectorImpl<ISD::OutputArg> &Outs,
4830 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
4831 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4832
4833 if (DisableSCO && !TailCallOpt) return false;
4834
4835 // Variadic argument functions are not supported.
4836 if (isVarArg) return false;
4837
4838 auto &Caller = DAG.getMachineFunction().getFunction();
4839 // Check that the calling conventions are compatible for tco.
4840 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4841 return false;
4842
4843 // Caller contains any byval parameter is not supported.
4844 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4845 return false;
4846
4847 // Callee contains any byval parameter is not supported, too.
4848 // Note: This is a quick work around, because in some cases, e.g.
4849 // caller's stack size > callee's stack size, we are still able to apply
4850 // sibling call optimization. For example, gcc is able to do SCO for caller1
4851 // in the following example, but not for caller2.
4852 // struct test {
4853 // long int a;
4854 // char ary[56];
4855 // } gTest;
4856 // __attribute__((noinline)) int callee(struct test v, struct test *b) {
4857 // b->a = v.a;
4858 // return 0;
4859 // }
4860 // void caller1(struct test a, struct test c, struct test *b) {
4861 // callee(gTest, b); }
4862 // void caller2(struct test *b) { callee(gTest, b); }
4863 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4864 return false;
4865
4866 // If callee and caller use different calling conventions, we cannot pass
4867 // parameters on stack since offsets for the parameter area may be different.
4868 if (Caller.getCallingConv() != CalleeCC &&
4869 needStackSlotPassParameters(Subtarget, Outs))
4870 return false;
4871
4872 // All variants of 64-bit ELF ABIs without PC-Relative addressing require that
4873 // the caller and callee share the same TOC for TCO/SCO. If the caller and
4874 // callee potentially have different TOC bases then we cannot tail call since
4875 // we need to restore the TOC pointer after the call.
4876 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4877 // We cannot guarantee this for indirect calls or calls to external functions.
4878 // When PC-Relative addressing is used, the concept of the TOC is no longer
4879 // applicable so this check is not required.
4880 // Check first for indirect calls.
4881 if (!Subtarget.isUsingPCRelativeCalls() &&
4882 !isFunctionGlobalAddress(Callee) && !isa<ExternalSymbolSDNode>(Callee))
4883 return false;
4884
4885 // Check if we share the TOC base.
4886 if (!Subtarget.isUsingPCRelativeCalls() &&
4887 !callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4888 return false;
4889
4890 // TCO allows altering callee ABI, so we don't have to check further.
4891 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4892 return true;
4893
4894 if (DisableSCO) return false;
4895
4896 // If callee use the same argument list that caller is using, then we can
4897 // apply SCO on this case. If it is not, then we need to check if callee needs
4898 // stack for passing arguments.
4899 // PC Relative tail calls may not have a CallBase.
4900 // If there is no CallBase we cannot verify if we have the same argument
4901 // list so assume that we don't have the same argument list.
4902 if (CB && !hasSameArgumentList(&Caller, *CB) &&
4903 needStackSlotPassParameters(Subtarget, Outs))
4904 return false;
4905 else if (!CB && needStackSlotPassParameters(Subtarget, Outs))
4906 return false;
4907
4908 return true;
4909}
4910
4911/// IsEligibleForTailCallOptimization - Check whether the call is eligible
4912/// for tail call optimization. Targets which want to do tail call
4913/// optimization should implement this function.
4914bool
4915PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4916 CallingConv::ID CalleeCC,
4917 bool isVarArg,
4918 const SmallVectorImpl<ISD::InputArg> &Ins,
4919 SelectionDAG& DAG) const {
4920 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4921 return false;
4922
4923 // Variable argument functions are not supported.
4924 if (isVarArg)
4925 return false;
4926
4927 MachineFunction &MF = DAG.getMachineFunction();
4928 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
4929 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4930 // Functions containing by val parameters are not supported.
4931 for (unsigned i = 0; i != Ins.size(); i++) {
4932 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4933 if (Flags.isByVal()) return false;
4934 }
4935
4936 // Non-PIC/GOT tail calls are supported.
4937 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4938 return true;
4939
4940 // At the moment we can only do local tail calls (in same module, hidden
4941 // or protected) if we are generating PIC.
4942 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4943 return G->getGlobal()->hasHiddenVisibility()
4944 || G->getGlobal()->hasProtectedVisibility();
4945 }
4946
4947 return false;
4948}
4949
4950/// isCallCompatibleAddress - Return the immediate to use if the specified
4951/// 32-bit value is representable in the immediate field of a BxA instruction.
4952static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4953 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4954 if (!C) return nullptr;
4955
4956 int Addr = C->getZExtValue();
4957 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
4958 SignExtend32<26>(Addr) != Addr)
4959 return nullptr; // Top 6 bits have to be sext of immediate.
4960
4961 return DAG
4962 .getConstant(
4963 (int)C->getZExtValue() >> 2, SDLoc(Op),
4964 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
4965 .getNode();
4966}
4967
4968namespace {
4969
4970struct TailCallArgumentInfo {
4971 SDValue Arg;
4972 SDValue FrameIdxOp;
4973 int FrameIdx = 0;
4974
4975 TailCallArgumentInfo() = default;
4976};
4977
4978} // end anonymous namespace
4979
4980/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
4981static void StoreTailCallArgumentsToStackSlot(
4982 SelectionDAG &DAG, SDValue Chain,
4983 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
4984 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
4985 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
4986 SDValue Arg = TailCallArgs[i].Arg;
4987 SDValue FIN = TailCallArgs[i].FrameIdxOp;
4988 int FI = TailCallArgs[i].FrameIdx;
4989 // Store relative to framepointer.
4990 MemOpChains.push_back(DAG.getStore(
4991 Chain, dl, Arg, FIN,
4992 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4993 }
4994}
4995
4996/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
4997/// the appropriate stack slot for the tail call optimized function call.
4998static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
4999 SDValue OldRetAddr, SDValue OldFP,
5000 int SPDiff, const SDLoc &dl) {
5001 if (SPDiff) {
5002 // Calculate the new stack slot for the return address.
5003 MachineFunction &MF = DAG.getMachineFunction();
5004 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
5005 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
5006 bool isPPC64 = Subtarget.isPPC64();
5007 int SlotSize = isPPC64 ? 8 : 4;
5008 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
5009 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
5010 NewRetAddrLoc, true);
5011 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5012 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
5013 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
5014 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
5015 }
5016 return Chain;
5017}
5018
5019/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
5020/// the position of the argument.
5021static void
5022CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
5023 SDValue Arg, int SPDiff, unsigned ArgOffset,
5024 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
5025 int Offset = ArgOffset + SPDiff;
5026 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
5027 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
5028 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
5029 SDValue FIN = DAG.getFrameIndex(FI, VT);
5030 TailCallArgumentInfo Info;
5031 Info.Arg = Arg;
5032 Info.FrameIdxOp = FIN;
5033 Info.FrameIdx = FI;
5034 TailCallArguments.push_back(Info);
5035}
5036
5037/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
5038/// stack slot. Returns the chain as result and the loaded frame pointers in
5039/// LROpOut/FPOpout. Used when tail calling.
5040SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
5041 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
5042 SDValue &FPOpOut, const SDLoc &dl) const {
5043 if (SPDiff) {
5044 // Load the LR and FP stack slot for later adjusting.
5045 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5046 LROpOut = getReturnAddrFrameIndex(DAG);
5047 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
5048 Chain = SDValue(LROpOut.getNode(), 1);
5049 }
5050 return Chain;
5051}
5052
5053/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
5054/// by "Src" to address "Dst" of size "Size". Alignment information is
5055/// specified by the specific parameter attribute. The copy will be passed as
5056/// a byval function parameter.
5057/// Sometimes what we are copying is the end of a larger object, the part that
5058/// does not fit in registers.
5059static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
5060 SDValue Chain, ISD::ArgFlagsTy Flags,
5061 SelectionDAG &DAG, const SDLoc &dl) {
5062 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
5063 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
5064 Flags.getNonZeroByValAlign(), false, false, false,
5065 MachinePointerInfo(), MachinePointerInfo());
5066}
5067
5068/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
5069/// tail calls.
5070static void LowerMemOpCallTo(
5071 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
5072 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
5073 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
5074 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
5075 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5076 if (!isTailCall) {
5077 if (isVector) {
5078 SDValue StackPtr;
5079 if (isPPC64)
5080 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5081 else
5082 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5083 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5084 DAG.getConstant(ArgOffset, dl, PtrVT));
5085 }
5086 MemOpChains.push_back(
5087 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5088 // Calculate and remember argument location.
5089 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
5090 TailCallArguments);
5091}
5092
5093static void
5094PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
5095 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
5096 SDValue FPOp,
5097 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
5098 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
5099 // might overwrite each other in case of tail call optimization.
5100 SmallVector<SDValue, 8> MemOpChains2;
5101 // Do not flag preceding copytoreg stuff together with the following stuff.
5102 InFlag = SDValue();
5103 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
5104 MemOpChains2, dl);
5105 if (!MemOpChains2.empty())
5106 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
5107
5108 // Store the return address to the appropriate stack slot.
5109 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
5110
5111 // Emit callseq_end just before tailcall node.
5112 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5113 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
5114 InFlag = Chain.getValue(1);
5115}
5116
5117// Is this global address that of a function that can be called by name? (as
5118// opposed to something that must hold a descriptor for an indirect call).
5119static bool isFunctionGlobalAddress(SDValue Callee) {
5120 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
5121 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
5122 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
5123 return false;
5124
5125 return G->getGlobal()->getValueType()->isFunctionTy();
5126 }
5127
5128 return false;
5129}
5130
5131SDValue PPCTargetLowering::LowerCallResult(
5132 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
5133 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5134 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5135 SmallVector<CCValAssign, 16> RVLocs;
5136 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5137 *DAG.getContext());
5138
5139 CCRetInfo.AnalyzeCallResult(
5140 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold)
5141 ? RetCC_PPC_Cold
5142 : RetCC_PPC);
5143
5144 // Copy all of the result registers out of their specified physreg.
5145 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
5146 CCValAssign &VA = RVLocs[i];
5147 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5147, __extension__
__PRETTY_FUNCTION__))
;
5148
5149 SDValue Val;
5150
5151 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
5152 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5153 InFlag);
5154 Chain = Lo.getValue(1);
5155 InFlag = Lo.getValue(2);
5156 VA = RVLocs[++i]; // skip ahead to next loc
5157 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5158 InFlag);
5159 Chain = Hi.getValue(1);
5160 InFlag = Hi.getValue(2);
5161 if (!Subtarget.isLittleEndian())
5162 std::swap (Lo, Hi);
5163 Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi);
5164 } else {
5165 Val = DAG.getCopyFromReg(Chain, dl,
5166 VA.getLocReg(), VA.getLocVT(), InFlag);
5167 Chain = Val.getValue(1);
5168 InFlag = Val.getValue(2);
5169 }
5170
5171 switch (VA.getLocInfo()) {
5172 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5172)
;
5173 case CCValAssign::Full: break;
5174 case CCValAssign::AExt:
5175 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5176 break;
5177 case CCValAssign::ZExt:
5178 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
5179 DAG.getValueType(VA.getValVT()));
5180 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5181 break;
5182 case CCValAssign::SExt:
5183 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
5184 DAG.getValueType(VA.getValVT()));
5185 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5186 break;
5187 }
5188
5189 InVals.push_back(Val);
5190 }
5191
5192 return Chain;
5193}
5194
5195static bool isIndirectCall(const SDValue &Callee, SelectionDAG &DAG,
5196 const PPCSubtarget &Subtarget, bool isPatchPoint) {
5197 // PatchPoint calls are not indirect.
5198 if (isPatchPoint)
5199 return false;
5200
5201 if (isFunctionGlobalAddress(Callee) || isa<ExternalSymbolSDNode>(Callee))
5202 return false;
5203
5204 // Darwin, and 32-bit ELF can use a BLA. The descriptor based ABIs can not
5205 // becuase the immediate function pointer points to a descriptor instead of
5206 // a function entry point. The ELFv2 ABI cannot use a BLA because the function
5207 // pointer immediate points to the global entry point, while the BLA would
5208 // need to jump to the local entry point (see rL211174).
5209 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() &&
5210 isBLACompatibleAddress(Callee, DAG))
5211 return false;
5212
5213 return true;
5214}
5215
5216// AIX and 64-bit ELF ABIs w/o PCRel require a TOC save/restore around calls.
5217static inline bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget) {
5218 return Subtarget.isAIXABI() ||
5219 (Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls());
5220}
5221
5222static unsigned getCallOpcode(PPCTargetLowering::CallFlags CFlags,
5223 const Function &Caller, const SDValue &Callee,
5224 const PPCSubtarget &Subtarget,
5225 const TargetMachine &TM,
5226 bool IsStrictFPCall = false) {
5227 if (CFlags.IsTailCall)
5228 return PPCISD::TC_RETURN;
5229
5230 unsigned RetOpc = 0;
5231 // This is a call through a function pointer.
5232 if (CFlags.IsIndirect) {
5233 // AIX and the 64-bit ELF ABIs need to maintain the TOC pointer accross
5234 // indirect calls. The save of the caller's TOC pointer to the stack will be
5235 // inserted into the DAG as part of call lowering. The restore of the TOC
5236 // pointer is modeled by using a pseudo instruction for the call opcode that
5237 // represents the 2 instruction sequence of an indirect branch and link,
5238 // immediately followed by a load of the TOC pointer from the the stack save
5239 // slot into gpr2. For 64-bit ELFv2 ABI with PCRel, do not restore the TOC
5240 // as it is not saved or used.
5241 RetOpc = isTOCSaveRestoreRequired(Subtarget) ? PPCISD::BCTRL_LOAD_TOC
5242 : PPCISD::BCTRL;
5243 } else if (Subtarget.isUsingPCRelativeCalls()) {
5244 assert(Subtarget.is64BitELFABI() && "PC Relative is only on ELF ABI.")(static_cast <bool> (Subtarget.is64BitELFABI() &&
"PC Relative is only on ELF ABI.") ? void (0) : __assert_fail
("Subtarget.is64BitELFABI() && \"PC Relative is only on ELF ABI.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5244, __extension__
__PRETTY_FUNCTION__))
;
5245 RetOpc = PPCISD::CALL_NOTOC;
5246 } else if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
5247 // The ABIs that maintain a TOC pointer accross calls need to have a nop
5248 // immediately following the call instruction if the caller and callee may
5249 // have different TOC bases. At link time if the linker determines the calls
5250 // may not share a TOC base, the call is redirected to a trampoline inserted
5251 // by the linker. The trampoline will (among other things) save the callers
5252 // TOC pointer at an ABI designated offset in the linkage area and the
5253 // linker will rewrite the nop to be a load of the TOC pointer from the
5254 // linkage area into gpr2.
5255 RetOpc = callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL
5256 : PPCISD::CALL_NOP;
5257 else
5258 RetOpc = PPCISD::CALL;
5259 if (IsStrictFPCall) {
5260 switch (RetOpc) {
5261 default:
5262 llvm_unreachable("Unknown call opcode")::llvm::llvm_unreachable_internal("Unknown call opcode", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5262)
;
5263 case PPCISD::BCTRL_LOAD_TOC:
5264 RetOpc = PPCISD::BCTRL_LOAD_TOC_RM;
5265 break;
5266 case PPCISD::BCTRL:
5267 RetOpc = PPCISD::BCTRL_RM;
5268 break;
5269 case PPCISD::CALL_NOTOC:
5270 RetOpc = PPCISD::CALL_NOTOC_RM;
5271 break;
5272 case PPCISD::CALL:
5273 RetOpc = PPCISD::CALL_RM;
5274 break;
5275 case PPCISD::CALL_NOP:
5276 RetOpc = PPCISD::CALL_NOP_RM;
5277 break;
5278 }
5279 }
5280 return RetOpc;
5281}
5282
5283static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
5284 const SDLoc &dl, const PPCSubtarget &Subtarget) {
5285 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI())
5286 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
5287 return SDValue(Dest, 0);
5288
5289 // Returns true if the callee is local, and false otherwise.
5290 auto isLocalCallee = [&]() {
5291 const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
5292 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5293 const GlobalValue *GV = G ? G->getGlobal() : nullptr;
5294
5295 return DAG.getTarget().shouldAssumeDSOLocal(*Mod, GV) &&
5296 !isa_and_nonnull<GlobalIFunc>(GV);
5297 };
5298
5299 // The PLT is only used in 32-bit ELF PIC mode. Attempting to use the PLT in
5300 // a static relocation model causes some versions of GNU LD (2.17.50, at
5301 // least) to force BSS-PLT, instead of secure-PLT, even if all objects are
5302 // built with secure-PLT.
5303 bool UsePlt =
5304 Subtarget.is32BitELFABI() && !isLocalCallee() &&
5305 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_;
5306
5307 const auto getAIXFuncEntryPointSymbolSDNode = [&](const GlobalValue *GV) {
5308 const TargetMachine &TM = Subtarget.getTargetMachine();
5309 const TargetLoweringObjectFile *TLOF = TM.getObjFileLowering();
5310 MCSymbolXCOFF *S =
5311 cast<MCSymbolXCOFF>(TLOF->getFunctionEntryPointSymbol(GV, TM));
5312
5313 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5314 return DAG.getMCSymbol(S, PtrVT);
5315 };
5316
5317 if (isFunctionGlobalAddress(Callee)) {
5318 const GlobalValue *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
5319
5320 if (Subtarget.isAIXABI()) {
5321 assert(!isa<GlobalIFunc>(GV) && "IFunc is not supported on AIX.")(static_cast <bool> (!isa<GlobalIFunc>(GV) &&
"IFunc is not supported on AIX.") ? void (0) : __assert_fail
("!isa<GlobalIFunc>(GV) && \"IFunc is not supported on AIX.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5321, __extension__
__PRETTY_FUNCTION__))
;
5322 return getAIXFuncEntryPointSymbolSDNode(GV);
5323 }
5324 return DAG.getTargetGlobalAddress(GV, dl, Callee.getValueType(), 0,
5325 UsePlt ? PPCII::MO_PLT : 0);
5326 }
5327
5328 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
5329 const char *SymName = S->getSymbol();
5330 if (Subtarget.isAIXABI()) {
5331 // If there exists a user-declared function whose name is the same as the
5332 // ExternalSymbol's, then we pick up the user-declared version.
5333 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5334 if (const Function *F =
5335 dyn_cast_or_null<Function>(Mod->getNamedValue(SymName)))
5336 return getAIXFuncEntryPointSymbolSDNode(F);
5337
5338 // On AIX, direct function calls reference the symbol for the function's
5339 // entry point, which is named by prepending a "." before the function's
5340 // C-linkage name. A Qualname is returned here because an external
5341 // function entry point is a csect with XTY_ER property.
5342 const auto getExternalFunctionEntryPointSymbol = [&](StringRef SymName) {
5343 auto &Context = DAG.getMachineFunction().getMMI().getContext();
5344 MCSectionXCOFF *Sec = Context.getXCOFFSection(
5345 (Twine(".") + Twine(SymName)).str(), SectionKind::getMetadata(),
5346 XCOFF::CsectProperties(XCOFF::XMC_PR, XCOFF::XTY_ER));
5347 return Sec->getQualNameSymbol();
5348 };
5349
5350 SymName = getExternalFunctionEntryPointSymbol(SymName)->getName().data();
5351 }
5352 return DAG.getTargetExternalSymbol(SymName, Callee.getValueType(),
5353 UsePlt ? PPCII::MO_PLT : 0);
5354 }
5355
5356 // No transformation needed.
5357 assert(Callee.getNode() && "What no callee?")(static_cast <bool> (Callee.getNode() && "What no callee?"
) ? void (0) : __assert_fail ("Callee.getNode() && \"What no callee?\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5357, __extension__
__PRETTY_FUNCTION__))
;
5358 return Callee;
5359}
5360
5361static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart) {
5362 assert(CallSeqStart.getOpcode() == ISD::CALLSEQ_START &&(static_cast <bool> (CallSeqStart.getOpcode() == ISD::CALLSEQ_START
&& "Expected a CALLSEQ_STARTSDNode.") ? void (0) : __assert_fail
("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5363, __extension__
__PRETTY_FUNCTION__))
5363 "Expected a CALLSEQ_STARTSDNode.")(static_cast <bool> (CallSeqStart.getOpcode() == ISD::CALLSEQ_START
&& "Expected a CALLSEQ_STARTSDNode.") ? void (0) : __assert_fail
("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5363, __extension__
__PRETTY_FUNCTION__))
;
5364
5365 // The last operand is the chain, except when the node has glue. If the node
5366 // has glue, then the last operand is the glue, and the chain is the second
5367 // last operand.
5368 SDValue LastValue = CallSeqStart.getValue(CallSeqStart->getNumValues() - 1);
5369 if (LastValue.getValueType() != MVT::Glue)
5370 return LastValue;
5371
5372 return CallSeqStart.getValue(CallSeqStart->getNumValues() - 2);
5373}
5374
5375// Creates the node that moves a functions address into the count register
5376// to prepare for an indirect call instruction.
5377static void prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5378 SDValue &Glue, SDValue &Chain,
5379 const SDLoc &dl) {
5380 SDValue MTCTROps[] = {Chain, Callee, Glue};
5381 EVT ReturnTypes[] = {MVT::Other, MVT::Glue};
5382 Chain = DAG.getNode(PPCISD::MTCTR, dl, makeArrayRef(ReturnTypes, 2),
5383 makeArrayRef(MTCTROps, Glue.getNode() ? 3 : 2));
5384 // The glue is the second value produced.
5385 Glue = Chain.getValue(1);
5386}
5387
5388static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5389 SDValue &Glue, SDValue &Chain,
5390 SDValue CallSeqStart,
5391 const CallBase *CB, const SDLoc &dl,
5392 bool hasNest,
5393 const PPCSubtarget &Subtarget) {
5394 // Function pointers in the 64-bit SVR4 ABI do not point to the function
5395 // entry point, but to the function descriptor (the function entry point
5396 // address is part of the function descriptor though).
5397 // The function descriptor is a three doubleword structure with the
5398 // following fields: function entry point, TOC base address and
5399 // environment pointer.
5400 // Thus for a call through a function pointer, the following actions need
5401 // to be performed:
5402 // 1. Save the TOC of the caller in the TOC save area of its stack
5403 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
5404 // 2. Load the address of the function entry point from the function
5405 // descriptor.
5406 // 3. Load the TOC of the callee from the function descriptor into r2.
5407 // 4. Load the environment pointer from the function descriptor into
5408 // r11.
5409 // 5. Branch to the function entry point address.
5410 // 6. On return of the callee, the TOC of the caller needs to be
5411 // restored (this is done in FinishCall()).
5412 //
5413 // The loads are scheduled at the beginning of the call sequence, and the
5414 // register copies are flagged together to ensure that no other
5415 // operations can be scheduled in between. E.g. without flagging the
5416 // copies together, a TOC access in the caller could be scheduled between
5417 // the assignment of the callee TOC and the branch to the callee, which leads
5418 // to incorrect code.
5419
5420 // Start by loading the function address from the descriptor.
5421 SDValue LDChain = getOutputChainFromCallSeq(CallSeqStart);
5422 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
5423 ? (MachineMemOperand::MODereferenceable |
5424 MachineMemOperand::MOInvariant)
5425 : MachineMemOperand::MONone;
5426
5427 MachinePointerInfo MPI(CB ? CB->getCalledOperand() : nullptr);
5428
5429 // Registers used in building the DAG.
5430 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister();
5431 const MCRegister TOCReg = Subtarget.getTOCPointerRegister();
5432
5433 // Offsets of descriptor members.
5434 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset();
5435 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset();
5436
5437 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5438 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4;
5439
5440 // One load for the functions entry point address.
5441 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5442 Alignment, MMOFlags);
5443
5444 // One for loading the TOC anchor for the module that contains the called
5445 // function.
5446 SDValue TOCOff = DAG.getIntPtrConstant(TOCAnchorOffset, dl);
5447 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5448 SDValue TOCPtr =
5449 DAG.getLoad(RegVT, dl, LDChain, AddTOC,
5450 MPI.getWithOffset(TOCAnchorOffset), Alignment, MMOFlags);
5451
5452 // One for loading the environment pointer.
5453 SDValue PtrOff = DAG.getIntPtrConstant(EnvPtrOffset, dl);
5454 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5455 SDValue LoadEnvPtr =
5456 DAG.getLoad(RegVT, dl, LDChain, AddPtr,
5457 MPI.getWithOffset(EnvPtrOffset), Alignment, MMOFlags);
5458
5459
5460 // Then copy the newly loaded TOC anchor to the TOC pointer.
5461 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, TOCReg, TOCPtr, Glue);
5462 Chain = TOCVal.getValue(0);
5463 Glue = TOCVal.getValue(1);
5464
5465 // If the function call has an explicit 'nest' parameter, it takes the
5466 // place of the environment pointer.
5467 assert((!hasNest || !Subtarget.isAIXABI()) &&(static_cast <bool> ((!hasNest || !Subtarget.isAIXABI()
) && "Nest parameter is not supported on AIX.") ? void
(0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5468, __extension__
__PRETTY_FUNCTION__))
5468 "Nest parameter is not supported on AIX.")(static_cast <bool> ((!hasNest || !Subtarget.isAIXABI()
) && "Nest parameter is not supported on AIX.") ? void
(0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5468, __extension__
__PRETTY_FUNCTION__))
;
5469 if (!hasNest) {
5470 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, EnvPtrReg, LoadEnvPtr, Glue);
5471 Chain = EnvVal.getValue(0);
5472 Glue = EnvVal.getValue(1);
5473 }
5474
5475 // The rest of the indirect call sequence is the same as the non-descriptor
5476 // DAG.
5477 prepareIndirectCall(DAG, LoadFuncPtr, Glue, Chain, dl);
5478}
5479
5480static void
5481buildCallOperands(SmallVectorImpl<SDValue> &Ops,
5482 PPCTargetLowering::CallFlags CFlags, const SDLoc &dl,
5483 SelectionDAG &DAG,
5484 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
5485 SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff,
5486 const PPCSubtarget &Subtarget) {
5487 const bool IsPPC64 = Subtarget.isPPC64();
5488 // MVT for a general purpose register.
5489 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5490
5491 // First operand is always the chain.
5492 Ops.push_back(Chain);
5493
5494 // If it's a direct call pass the callee as the second operand.
5495 if (!CFlags.IsIndirect)
5496 Ops.push_back(Callee);
5497 else {
5498 assert(!CFlags.IsPatchPoint && "Patch point calls are not indirect.")(static_cast <bool> (!CFlags.IsPatchPoint && "Patch point calls are not indirect."
) ? void (0) : __assert_fail ("!CFlags.IsPatchPoint && \"Patch point calls are not indirect.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5498, __extension__
__PRETTY_FUNCTION__))
;
5499
5500 // For the TOC based ABIs, we have saved the TOC pointer to the linkage area
5501 // on the stack (this would have been done in `LowerCall_64SVR4` or
5502 // `LowerCall_AIX`). The call instruction is a pseudo instruction that
5503 // represents both the indirect branch and a load that restores the TOC
5504 // pointer from the linkage area. The operand for the TOC restore is an add
5505 // of the TOC save offset to the stack pointer. This must be the second
5506 // operand: after the chain input but before any other variadic arguments.
5507 // For 64-bit ELFv2 ABI with PCRel, do not restore the TOC as it is not
5508 // saved or used.
5509 if (isTOCSaveRestoreRequired(Subtarget)) {
5510 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister();
5511
5512 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5513 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5514 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5515 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5516 Ops.push_back(AddTOC);
5517 }
5518
5519 // Add the register used for the environment pointer.
5520 if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest)
5521 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(),
5522 RegVT));
5523
5524
5525 // Add CTR register as callee so a bctr can be emitted later.
5526 if (CFlags.IsTailCall)
5527 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5528 }
5529
5530 // If this is a tail call add stack pointer delta.
5531 if (CFlags.IsTailCall)
5532 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
5533
5534 // Add argument registers to the end of the list so that they are known live
5535 // into the call.
5536 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
5537 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5538 RegsToPass[i].second.getValueType()));
5539
5540 // We cannot add R2/X2 as an operand here for PATCHPOINT, because there is
5541 // no way to mark dependencies as implicit here.
5542 // We will add the R2/X2 dependency in EmitInstrWithCustomInserter.
5543 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) &&
5544 !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls())
5545 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT));
5546
5547 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
5548 if (CFlags.IsVarArg && Subtarget.is32BitELFABI())
5549 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5550
5551 // Add a register mask operand representing the call-preserved registers.
5552 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
5553 const uint32_t *Mask =
5554 TRI->getCallPreservedMask(DAG.getMachineFunction(), CFlags.CallConv);
5555 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5555, __extension__
__PRETTY_FUNCTION__))
;
5556 Ops.push_back(DAG.getRegisterMask(Mask));
5557
5558 // If the glue is valid, it is the last operand.
5559 if (Glue.getNode())
5560 Ops.push_back(Glue);
5561}
5562
5563SDValue PPCTargetLowering::FinishCall(
5564 CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG,
5565 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue,
5566 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5567 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
5568 SmallVectorImpl<SDValue> &InVals, const CallBase *CB) const {
5569
5570 if ((Subtarget.is64BitELFABI() && !Subtarget.isUsingPCRelativeCalls()) ||
5571 Subtarget.isAIXABI())
5572 setUsesTOCBasePtr(DAG);
5573
5574 unsigned CallOpc =
5575 getCallOpcode(CFlags, DAG.getMachineFunction().getFunction(), Callee,
5576 Subtarget, DAG.getTarget(), CB ? CB->isStrictFP() : false);
5577
5578 if (!CFlags.IsIndirect)
5579 Callee = transformCallee(Callee, DAG, dl, Subtarget);
5580 else if (Subtarget.usesFunctionDescriptors())
5581 prepareDescriptorIndirectCall(DAG, Callee, Glue, Chain, CallSeqStart, CB,
5582 dl, CFlags.HasNest, Subtarget);
5583 else
5584 prepareIndirectCall(DAG, Callee, Glue, Chain, dl);
5585
5586 // Build the operand list for the call instruction.
5587 SmallVector<SDValue, 8> Ops;
5588 buildCallOperands(Ops, CFlags, dl, DAG, RegsToPass, Glue, Chain, Callee,
5589 SPDiff, Subtarget);
5590
5591 // Emit tail call.
5592 if (CFlags.IsTailCall) {
5593 // Indirect tail call when using PC Relative calls do not have the same
5594 // constraints.
5595 assert(((Callee.getOpcode() == ISD::Register &&(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5603, __extension__
__PRETTY_FUNCTION__))
5596 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5603, __extension__
__PRETTY_FUNCTION__))
5597 Callee.getOpcode() == ISD::TargetExternalSymbol ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5603, __extension__
__PRETTY_FUNCTION__))
5598 Callee.getOpcode() == ISD::TargetGlobalAddress ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5603, __extension__
__PRETTY_FUNCTION__))
5599 isa<ConstantSDNode>(Callee) ||(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5603, __extension__
__PRETTY_FUNCTION__))
5600 (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) &&(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5603, __extension__
__PRETTY_FUNCTION__))
5601 "Expecting a global address, external symbol, absolute value, "(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5603, __extension__
__PRETTY_FUNCTION__))
5602 "register or an indirect tail call when PC Relative calls are "(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5603, __extension__
__PRETTY_FUNCTION__))
5603 "used.")(static_cast <bool> (((Callee.getOpcode() == ISD::Register
&& cast<RegisterSDNode>(Callee)->getReg() ==
PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol
|| Callee.getOpcode() == ISD::TargetGlobalAddress || isa<
ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget
.isUsingPCRelativeCalls())) && "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are "
"used.") ? void (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee) || (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && \"Expecting a global address, external symbol, absolute value, \" \"register or an indirect tail call when PC Relative calls are \" \"used.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5603, __extension__
__PRETTY_FUNCTION__))
;
5604 // PC Relative calls also use TC_RETURN as the way to mark tail calls.
5605 assert(CallOpc == PPCISD::TC_RETURN &&(static_cast <bool> (CallOpc == PPCISD::TC_RETURN &&
"Unexpected call opcode for a tail call.") ? void (0) : __assert_fail
("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5606, __extension__
__PRETTY_FUNCTION__))
5606 "Unexpected call opcode for a tail call.")(static_cast <bool> (CallOpc == PPCISD::TC_RETURN &&
"Unexpected call opcode for a tail call.") ? void (0) : __assert_fail
("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5606, __extension__
__PRETTY_FUNCTION__))
;
5607 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
5608 return DAG.getNode(CallOpc, dl, MVT::Other, Ops);
5609 }
5610
5611 std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}};
5612 Chain = DAG.getNode(CallOpc, dl, ReturnTypes, Ops);
5613 DAG.addNoMergeSiteInfo(Chain.getNode(), CFlags.NoMerge);
5614 Glue = Chain.getValue(1);
5615
5616 // When performing tail call optimization the callee pops its arguments off
5617 // the stack. Account for this here so these bytes can be pushed back on in
5618 // PPCFrameLowering::eliminateCallFramePseudoInstr.
5619 int BytesCalleePops = (CFlags.CallConv == CallingConv::Fast &&
5620 getTargetMachine().Options.GuaranteedTailCallOpt)
5621 ? NumBytes
5622 : 0;
5623
5624 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5625 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5626 Glue, dl);
5627 Glue = Chain.getValue(1);
5628
5629 return LowerCallResult(Chain, Glue, CFlags.CallConv, CFlags.IsVarArg, Ins, dl,
5630 DAG, InVals);
5631}
5632
5633SDValue
5634PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5635 SmallVectorImpl<SDValue> &InVals) const {
5636 SelectionDAG &DAG = CLI.DAG;
5637 SDLoc &dl = CLI.DL;
5638 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5639 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5640 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5641 SDValue Chain = CLI.Chain;
5642 SDValue Callee = CLI.Callee;
5643 bool &isTailCall = CLI.IsTailCall;
5644 CallingConv::ID CallConv = CLI.CallConv;
5645 bool isVarArg = CLI.IsVarArg;
5646 bool isPatchPoint = CLI.IsPatchPoint;
5647 const CallBase *CB = CLI.CB;
5648
5649 if (isTailCall) {
5650 if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall()))
5651 isTailCall = false;
5652 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5653 isTailCall = IsEligibleForTailCallOptimization_64SVR4(
5654 Callee, CallConv, CB, isVarArg, Outs, Ins, DAG);
5655 else
5656 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5657 Ins, DAG);
5658 if (isTailCall) {
5659 ++NumTailCalls;
5660 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5661 ++NumSiblingCalls;
5662
5663 // PC Relative calls no longer guarantee that the callee is a Global
5664 // Address Node. The callee could be an indirect tail call in which
5665 // case the SDValue for the callee could be a load (to load the address
5666 // of a function pointer) or it may be a register copy (to move the
5667 // address of the callee from a function parameter into a virtual
5668 // register). It may also be an ExternalSymbolSDNode (ex memcopy).
5669 assert((Subtarget.isUsingPCRelativeCalls() ||(static_cast <bool> ((Subtarget.isUsingPCRelativeCalls(
) || isa<GlobalAddressSDNode>(Callee)) && "Callee should be an llvm::Function object."
) ? void (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5671, __extension__
__PRETTY_FUNCTION__))
5670 isa<GlobalAddressSDNode>(Callee)) &&(static_cast <bool> ((Subtarget.isUsingPCRelativeCalls(
) || isa<GlobalAddressSDNode>(Callee)) && "Callee should be an llvm::Function object."
) ? void (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5671, __extension__
__PRETTY_FUNCTION__))
5671 "Callee should be an llvm::Function object.")(static_cast <bool> ((Subtarget.isUsingPCRelativeCalls(
) || isa<GlobalAddressSDNode>(Callee)) && "Callee should be an llvm::Function object."
) ? void (0) : __assert_fail ("(Subtarget.isUsingPCRelativeCalls() || isa<GlobalAddressSDNode>(Callee)) && \"Callee should be an llvm::Function object.\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5671, __extension__
__PRETTY_FUNCTION__))
;
5672
5673 LLVM_DEBUG(dbgs() << "TCO caller: " << DAG.getMachineFunction().getName()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
5674 << "\nTCO callee: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { dbgs() << "TCO caller: " << DAG
.getMachineFunction().getName() << "\nTCO callee: "; } }
while (false)
;
5675 LLVM_DEBUG(Callee.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { Callee.dump(); } } while (false)
;
5676 }
5677 }
5678
5679 if (!isTailCall && CB && CB->isMustTailCall())
5680 report_fatal_error("failed to perform tail call elimination on a call "
5681 "site marked musttail");
5682
5683 // When long calls (i.e. indirect calls) are always used, calls are always
5684 // made via function pointer. If we have a function name, first translate it
5685 // into a pointer.
5686 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5687 !isTailCall)
5688 Callee = LowerGlobalAddress(Callee, DAG);
5689
5690 CallFlags CFlags(
5691 CallConv, isTailCall, isVarArg, isPatchPoint,
5692 isIndirectCall(Callee, DAG, Subtarget, isPatchPoint),
5693 // hasNest
5694 Subtarget.is64BitELFABI() &&
5695 any_of(Outs, [](ISD::OutputArg Arg) { return Arg.Flags.isNest(); }),
5696 CLI.NoMerge);
5697
5698 if (Subtarget.isAIXABI())
5699 return LowerCall_AIX(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5700 InVals, CB);
5701
5702 assert(Subtarget.isSVR4ABI())(static_cast <bool> (Subtarget.isSVR4ABI()) ? void (0) :
__assert_fail ("Subtarget.isSVR4ABI()", "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5702, __extension__ __PRETTY_FUNCTION__))
;
5703 if (Subtarget.isPPC64())
5704 return LowerCall_64SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5705 InVals, CB);
5706 return LowerCall_32SVR4(Chain, Callee, CFlags, Outs, OutVals, Ins, dl, DAG,
5707 InVals, CB);
5708}
5709
5710SDValue PPCTargetLowering::LowerCall_32SVR4(
5711 SDValue Chain, SDValue Callee, CallFlags CFlags,
5712 const SmallVectorImpl<ISD::OutputArg> &Outs,
5713 const SmallVectorImpl<SDValue> &OutVals,
5714 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5715 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5716 const CallBase *CB) const {
5717 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5718 // of the 32-bit SVR4 ABI stack frame layout.
5719
5720 const CallingConv::ID CallConv = CFlags.CallConv;
5721 const bool IsVarArg = CFlags.IsVarArg;
5722 const bool IsTailCall = CFlags.IsTailCall;
5723
5724 assert((CallConv == CallingConv::C ||(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5726, __extension__
__PRETTY_FUNCTION__))
5725 CallConv == CallingConv::Cold ||(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5726, __extension__
__PRETTY_FUNCTION__))
5726 CallConv == CallingConv::Fast) && "Unknown calling convention!")(static_cast <bool> ((CallConv == CallingConv::C || CallConv
== CallingConv::Cold || CallConv == CallingConv::Fast) &&
"Unknown calling convention!") ? void (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "llvm/lib/Target/PowerPC/PPCISelLowering.cpp", 5726, __extension__
__PRETTY_FUNCTION__))
;
5727
5728 const Align PtrAlign(4);
5729
5730 MachineFunction &MF = DAG.getMachineFunction();
5731
5732 // Mark this function as potentially containing a function that contains a
5733 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5734 // and restoring the callers stack pointer in this functions epilog. This is
5735 // done because by tail calling the called function might overwrite the value
5736 // in this function's (MF) stack pointer stack slot 0(SP).
5737 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5738 CallConv == CallingConv::Fast)
5739 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5740
5741 // Count how many bytes are to be pushed on the stack, including the linkage
5742 // area, parameter list area and the part of the local variable space which
5743 // contains copies of aggregates which are passed by value.
5744
5745 // Assign locations to all of the outgoing arguments.
5746 SmallVector<CCValAssign, 16> ArgLocs;
5747 PPCCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
5748
5749 // Reserve space for the linkage area on the stack.
5750 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5751 PtrAlign);
5752 if (useSoftFloat())
5753 CCInfo.PreAnalyzeCallOperands(Outs);
5754
5755 if (IsVarArg) {
5756 // Handle fixed and variable vector arguments differently.
5757 // Fixed vector arguments go into registers as long as registers are
5758 // available. Variable vector arguments always go into memory.
5759 unsigned NumArgs = Outs.size();
5760
5761 for (unsigned i = 0; i != NumArgs; ++i) {
5762 MVT ArgVT = Outs[i].VT;
5763 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5764 bool Result;
5765
5766 if (Outs[i].IsFixed) {
5767 Result = CC_PPC32_SVR4(i, ArgVT, ArgV