Bug Summary

File:include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1106, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn345461/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/PowerPC -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-10-27-211344-32123-1 -x c++ /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp -faddrsig

/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp

1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPCISelLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCISelLowering.h"
15#include "MCTargetDesc/PPCPredicates.h"
16#include "PPC.h"
17#include "PPCCCState.h"
18#include "PPCCallingConv.h"
19#include "PPCFrameLowering.h"
20#include "PPCInstrInfo.h"
21#include "PPCMachineFunctionInfo.h"
22#include "PPCPerfectShuffle.h"
23#include "PPCRegisterInfo.h"
24#include "PPCSubtarget.h"
25#include "PPCTargetMachine.h"
26#include "llvm/ADT/APFloat.h"
27#include "llvm/ADT/APInt.h"
28#include "llvm/ADT/ArrayRef.h"
29#include "llvm/ADT/DenseMap.h"
30#include "llvm/ADT/None.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallPtrSet.h"
33#include "llvm/ADT/SmallSet.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/StringRef.h"
37#include "llvm/ADT/StringSwitch.h"
38#include "llvm/CodeGen/CallingConvLower.h"
39#include "llvm/CodeGen/ISDOpcodes.h"
40#include "llvm/CodeGen/MachineBasicBlock.h"
41#include "llvm/CodeGen/MachineFrameInfo.h"
42#include "llvm/CodeGen/MachineFunction.h"
43#include "llvm/CodeGen/MachineInstr.h"
44#include "llvm/CodeGen/MachineInstrBuilder.h"
45#include "llvm/CodeGen/MachineJumpTableInfo.h"
46#include "llvm/CodeGen/MachineLoopInfo.h"
47#include "llvm/CodeGen/MachineMemOperand.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/RuntimeLibcalls.h"
51#include "llvm/CodeGen/SelectionDAG.h"
52#include "llvm/CodeGen/SelectionDAGNodes.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetLowering.h"
55#include "llvm/CodeGen/TargetRegisterInfo.h"
56#include "llvm/CodeGen/ValueTypes.h"
57#include "llvm/IR/CallSite.h"
58#include "llvm/IR/CallingConv.h"
59#include "llvm/IR/Constant.h"
60#include "llvm/IR/Constants.h"
61#include "llvm/IR/DataLayout.h"
62#include "llvm/IR/DebugLoc.h"
63#include "llvm/IR/DerivedTypes.h"
64#include "llvm/IR/Function.h"
65#include "llvm/IR/GlobalValue.h"
66#include "llvm/IR/IRBuilder.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/Intrinsics.h"
69#include "llvm/IR/Module.h"
70#include "llvm/IR/Type.h"
71#include "llvm/IR/Use.h"
72#include "llvm/IR/Value.h"
73#include "llvm/MC/MCExpr.h"
74#include "llvm/MC/MCRegisterInfo.h"
75#include "llvm/Support/AtomicOrdering.h"
76#include "llvm/Support/BranchProbability.h"
77#include "llvm/Support/Casting.h"
78#include "llvm/Support/CodeGen.h"
79#include "llvm/Support/CommandLine.h"
80#include "llvm/Support/Compiler.h"
81#include "llvm/Support/Debug.h"
82#include "llvm/Support/ErrorHandling.h"
83#include "llvm/Support/Format.h"
84#include "llvm/Support/KnownBits.h"
85#include "llvm/Support/MachineValueType.h"
86#include "llvm/Support/MathExtras.h"
87#include "llvm/Support/raw_ostream.h"
88#include "llvm/Target/TargetMachine.h"
89#include "llvm/Target/TargetOptions.h"
90#include <algorithm>
91#include <cassert>
92#include <cstdint>
93#include <iterator>
94#include <list>
95#include <utility>
96#include <vector>
97
98using namespace llvm;
99
100#define DEBUG_TYPE"ppc-lowering" "ppc-lowering"
101
102static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
103cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
104
105static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
106cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
107
108static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
109cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
110
111static cl::opt<bool> DisableSCO("disable-ppc-sco",
112cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
113
114static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
115cl::desc("enable quad precision float support on ppc"), cl::Hidden);
116
117STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"ppc-lowering", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
118STATISTIC(NumSiblingCalls, "Number of sibling calls")static llvm::Statistic NumSiblingCalls = {"ppc-lowering", "NumSiblingCalls"
, "Number of sibling calls", {0}, {false}}
;
119
120static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
121
122// FIXME: Remove this once the bug has been fixed!
123extern cl::opt<bool> ANDIGlueBug;
124
125PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
126 const PPCSubtarget &STI)
127 : TargetLowering(TM), Subtarget(STI) {
128 // Use _setjmp/_longjmp instead of setjmp/longjmp.
129 setUseUnderscoreSetJmp(true);
130 setUseUnderscoreLongJmp(true);
131
132 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
133 // arguments are at least 4/8 bytes aligned.
134 bool isPPC64 = Subtarget.isPPC64();
135 setMinStackArgumentAlignment(isPPC64 ? 8:4);
136
137 // Set up the register classes.
138 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
139 if (!useSoftFloat()) {
140 if (hasSPE()) {
141 addRegisterClass(MVT::f32, &PPC::SPE4RCRegClass);
142 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
143 } else {
144 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
145 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
146 }
147 }
148
149 // Match BITREVERSE to customized fast code sequence in the td file.
150 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
151 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
152
153 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
154 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
155
156 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
157 for (MVT VT : MVT::integer_valuetypes()) {
158 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
160 }
161
162 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
163
164 // PowerPC has pre-inc load and store's.
165 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
166 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
167 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
168 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
169 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
170 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
171 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
172 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
173 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
174 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
175 if (!Subtarget.hasSPE()) {
176 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
177 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
178 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
179 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
180 }
181
182 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
183 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
184 for (MVT VT : ScalarIntVTs) {
185 setOperationAction(ISD::ADDC, VT, Legal);
186 setOperationAction(ISD::ADDE, VT, Legal);
187 setOperationAction(ISD::SUBC, VT, Legal);
188 setOperationAction(ISD::SUBE, VT, Legal);
189 }
190
191 if (Subtarget.useCRBits()) {
192 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
193
194 if (isPPC64 || Subtarget.hasFPCVT()) {
195 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
196 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
197 isPPC64 ? MVT::i64 : MVT::i32);
198 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
199 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
200 isPPC64 ? MVT::i64 : MVT::i32);
201 } else {
202 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
203 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
204 }
205
206 // PowerPC does not support direct load/store of condition registers.
207 setOperationAction(ISD::LOAD, MVT::i1, Custom);
208 setOperationAction(ISD::STORE, MVT::i1, Custom);
209
210 // FIXME: Remove this once the ANDI glue bug is fixed:
211 if (ANDIGlueBug)
212 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
213
214 for (MVT VT : MVT::integer_valuetypes()) {
215 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
216 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
217 setTruncStoreAction(VT, MVT::i1, Expand);
218 }
219
220 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
221 }
222
223 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
224 // PPC (the libcall is not available).
225 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
226 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
227
228 // We do not currently implement these libm ops for PowerPC.
229 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
230 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
231 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
232 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
233 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
234 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
235
236 // PowerPC has no SREM/UREM instructions unless we are on P9
237 // On P9 we may use a hardware instruction to compute the remainder.
238 // The instructions are not legalized directly because in the cases where the
239 // result of both the remainder and the division is required it is more
240 // efficient to compute the remainder from the result of the division rather
241 // than use the remainder instruction.
242 if (Subtarget.isISA3_0()) {
243 setOperationAction(ISD::SREM, MVT::i32, Custom);
244 setOperationAction(ISD::UREM, MVT::i32, Custom);
245 setOperationAction(ISD::SREM, MVT::i64, Custom);
246 setOperationAction(ISD::UREM, MVT::i64, Custom);
247 } else {
248 setOperationAction(ISD::SREM, MVT::i32, Expand);
249 setOperationAction(ISD::UREM, MVT::i32, Expand);
250 setOperationAction(ISD::SREM, MVT::i64, Expand);
251 setOperationAction(ISD::UREM, MVT::i64, Expand);
252 }
253
254 if (Subtarget.hasP9Vector()) {
255 setOperationAction(ISD::ABS, MVT::v4i32, Legal);
256 setOperationAction(ISD::ABS, MVT::v8i16, Legal);
257 setOperationAction(ISD::ABS, MVT::v16i8, Legal);
258 }
259
260 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
261 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
262 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
263 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
264 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
265 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
266 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
267 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
268 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
269
270 // We don't support sin/cos/sqrt/fmod/pow
271 setOperationAction(ISD::FSIN , MVT::f64, Expand);
272 setOperationAction(ISD::FCOS , MVT::f64, Expand);
273 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
274 setOperationAction(ISD::FREM , MVT::f64, Expand);
275 setOperationAction(ISD::FPOW , MVT::f64, Expand);
276 setOperationAction(ISD::FSIN , MVT::f32, Expand);
277 setOperationAction(ISD::FCOS , MVT::f32, Expand);
278 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
279 setOperationAction(ISD::FREM , MVT::f32, Expand);
280 setOperationAction(ISD::FPOW , MVT::f32, Expand);
281 if (Subtarget.hasSPE()) {
282 setOperationAction(ISD::FMA , MVT::f64, Expand);
283 setOperationAction(ISD::FMA , MVT::f32, Expand);
284 } else {
285 setOperationAction(ISD::FMA , MVT::f64, Legal);
286 setOperationAction(ISD::FMA , MVT::f32, Legal);
287 }
288
289 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
290
291 // If we're enabling GP optimizations, use hardware square root
292 if (!Subtarget.hasFSQRT() &&
293 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
294 Subtarget.hasFRE()))
295 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
296
297 if (!Subtarget.hasFSQRT() &&
298 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
299 Subtarget.hasFRES()))
300 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
301
302 if (Subtarget.hasFCPSGN()) {
303 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
304 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
305 } else {
306 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
307 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
308 }
309
310 if (Subtarget.hasFPRND()) {
311 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
312 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
313 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
314 setOperationAction(ISD::FROUND, MVT::f64, Legal);
315
316 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
317 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
318 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
319 setOperationAction(ISD::FROUND, MVT::f32, Legal);
320 }
321
322 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
323 // to speed up scalar BSWAP64.
324 // CTPOP or CTTZ were introduced in P8/P9 respectively
325 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
326 if (Subtarget.isISA3_0()) {
327 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
328 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
329 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
330 } else {
331 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
332 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
333 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
334 }
335
336 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
337 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
338 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
339 } else {
340 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
341 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
342 }
343
344 // PowerPC does not have ROTR
345 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
346 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
347
348 if (!Subtarget.useCRBits()) {
349 // PowerPC does not have Select
350 setOperationAction(ISD::SELECT, MVT::i32, Expand);
351 setOperationAction(ISD::SELECT, MVT::i64, Expand);
352 setOperationAction(ISD::SELECT, MVT::f32, Expand);
353 setOperationAction(ISD::SELECT, MVT::f64, Expand);
354 }
355
356 // PowerPC wants to turn select_cc of FP into fsel when possible.
357 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
358 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
359
360 // PowerPC wants to optimize integer setcc a bit
361 if (!Subtarget.useCRBits())
362 setOperationAction(ISD::SETCC, MVT::i32, Custom);
363
364 // PowerPC does not have BRCOND which requires SetCC
365 if (!Subtarget.useCRBits())
366 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
367
368 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
369
370 if (Subtarget.hasSPE()) {
371 // SPE has built-in conversions
372 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
373 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
374 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
375 } else {
376 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
377 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
378
379 // PowerPC does not have [U|S]INT_TO_FP
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
382 }
383
384 if (Subtarget.hasDirectMove() && isPPC64) {
385 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
386 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
387 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
388 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
389 } else {
390 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
391 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
392 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
393 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
394 }
395
396 // We cannot sextinreg(i1). Expand to shifts.
397 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
398
399 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
400 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
401 // support continuation, user-level threading, and etc.. As a result, no
402 // other SjLj exception interfaces are implemented and please don't build
403 // your own exception handling based on them.
404 // LLVM/Clang supports zero-cost DWARF exception handling.
405 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
406 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
407
408 // We want to legalize GlobalAddress and ConstantPool nodes into the
409 // appropriate instructions to materialize the address.
410 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
411 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
412 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
413 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
414 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
415 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
416 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
417 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
418 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
419 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
420
421 // TRAP is legal.
422 setOperationAction(ISD::TRAP, MVT::Other, Legal);
423
424 // TRAMPOLINE is custom lowered.
425 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
426 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
427
428 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
429 setOperationAction(ISD::VASTART , MVT::Other, Custom);
430
431 if (Subtarget.isSVR4ABI()) {
432 if (isPPC64) {
433 // VAARG always uses double-word chunks, so promote anything smaller.
434 setOperationAction(ISD::VAARG, MVT::i1, Promote);
435 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
436 setOperationAction(ISD::VAARG, MVT::i8, Promote);
437 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
438 setOperationAction(ISD::VAARG, MVT::i16, Promote);
439 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
440 setOperationAction(ISD::VAARG, MVT::i32, Promote);
441 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
442 setOperationAction(ISD::VAARG, MVT::Other, Expand);
443 } else {
444 // VAARG is custom lowered with the 32-bit SVR4 ABI.
445 setOperationAction(ISD::VAARG, MVT::Other, Custom);
446 setOperationAction(ISD::VAARG, MVT::i64, Custom);
447 }
448 } else
449 setOperationAction(ISD::VAARG, MVT::Other, Expand);
450
451 if (Subtarget.isSVR4ABI() && !isPPC64)
452 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
453 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
454 else
455 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
456
457 // Use the default implementation.
458 setOperationAction(ISD::VAEND , MVT::Other, Expand);
459 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
460 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
461 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
462 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
463 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
464 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
465 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
466 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
467
468 // We want to custom lower some of our intrinsics.
469 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
470
471 // To handle counter-based loop conditions.
472 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
473
474 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
475 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
476 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
477 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
478
479 // Comparisons that require checking two conditions.
480 if (Subtarget.hasSPE()) {
481 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
482 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
483 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
484 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
485 }
486 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
487 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
488 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
489 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
490 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
491 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
492 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
493 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
494 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
495 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
496 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
497 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
498
499 if (Subtarget.has64BitSupport()) {
500 // They also have instructions for converting between i64 and fp.
501 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
502 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
503 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
504 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
505 // This is just the low 32 bits of a (signed) fp->i64 conversion.
506 // We cannot do this with Promote because i64 is not a legal type.
507 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
508
509 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
510 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
511 } else {
512 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
513 if (Subtarget.hasSPE())
514 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
515 else
516 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
517 }
518
519 // With the instructions enabled under FPCVT, we can do everything.
520 if (Subtarget.hasFPCVT()) {
521 if (Subtarget.has64BitSupport()) {
522 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
523 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
524 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
525 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
526 }
527
528 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
529 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
530 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
531 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
532 }
533
534 if (Subtarget.use64BitRegs()) {
535 // 64-bit PowerPC implementations can support i64 types directly
536 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
537 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
538 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
539 // 64-bit PowerPC wants to expand i128 shifts itself.
540 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
541 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
542 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
543 } else {
544 // 32-bit PowerPC wants to expand i64 shifts itself.
545 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
546 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
547 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
548 }
549
550 if (Subtarget.hasAltivec()) {
551 // First set operation action for all vector types to expand. Then we
552 // will selectively turn on ones that can be effectively codegen'd.
553 for (MVT VT : MVT::vector_valuetypes()) {
554 // add/sub are legal for all supported vector VT's.
555 setOperationAction(ISD::ADD, VT, Legal);
556 setOperationAction(ISD::SUB, VT, Legal);
557
558 // Vector instructions introduced in P8
559 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
560 setOperationAction(ISD::CTPOP, VT, Legal);
561 setOperationAction(ISD::CTLZ, VT, Legal);
562 }
563 else {
564 setOperationAction(ISD::CTPOP, VT, Expand);
565 setOperationAction(ISD::CTLZ, VT, Expand);
566 }
567
568 // Vector instructions introduced in P9
569 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
570 setOperationAction(ISD::CTTZ, VT, Legal);
571 else
572 setOperationAction(ISD::CTTZ, VT, Expand);
573
574 // We promote all shuffles to v16i8.
575 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
576 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
577
578 // We promote all non-typed operations to v4i32.
579 setOperationAction(ISD::AND , VT, Promote);
580 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
581 setOperationAction(ISD::OR , VT, Promote);
582 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
583 setOperationAction(ISD::XOR , VT, Promote);
584 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
585 setOperationAction(ISD::LOAD , VT, Promote);
586 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
587 setOperationAction(ISD::SELECT, VT, Promote);
588 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
589 setOperationAction(ISD::SELECT_CC, VT, Promote);
590 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
591 setOperationAction(ISD::STORE, VT, Promote);
592 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
593
594 // No other operations are legal.
595 setOperationAction(ISD::MUL , VT, Expand);
596 setOperationAction(ISD::SDIV, VT, Expand);
597 setOperationAction(ISD::SREM, VT, Expand);
598 setOperationAction(ISD::UDIV, VT, Expand);
599 setOperationAction(ISD::UREM, VT, Expand);
600 setOperationAction(ISD::FDIV, VT, Expand);
601 setOperationAction(ISD::FREM, VT, Expand);
602 setOperationAction(ISD::FNEG, VT, Expand);
603 setOperationAction(ISD::FSQRT, VT, Expand);
604 setOperationAction(ISD::FLOG, VT, Expand);
605 setOperationAction(ISD::FLOG10, VT, Expand);
606 setOperationAction(ISD::FLOG2, VT, Expand);
607 setOperationAction(ISD::FEXP, VT, Expand);
608 setOperationAction(ISD::FEXP2, VT, Expand);
609 setOperationAction(ISD::FSIN, VT, Expand);
610 setOperationAction(ISD::FCOS, VT, Expand);
611 setOperationAction(ISD::FABS, VT, Expand);
612 setOperationAction(ISD::FFLOOR, VT, Expand);
613 setOperationAction(ISD::FCEIL, VT, Expand);
614 setOperationAction(ISD::FTRUNC, VT, Expand);
615 setOperationAction(ISD::FRINT, VT, Expand);
616 setOperationAction(ISD::FNEARBYINT, VT, Expand);
617 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
618 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
619 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
620 setOperationAction(ISD::MULHU, VT, Expand);
621 setOperationAction(ISD::MULHS, VT, Expand);
622 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
623 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
624 setOperationAction(ISD::UDIVREM, VT, Expand);
625 setOperationAction(ISD::SDIVREM, VT, Expand);
626 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
627 setOperationAction(ISD::FPOW, VT, Expand);
628 setOperationAction(ISD::BSWAP, VT, Expand);
629 setOperationAction(ISD::VSELECT, VT, Expand);
630 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
631 setOperationAction(ISD::ROTL, VT, Expand);
632 setOperationAction(ISD::ROTR, VT, Expand);
633
634 for (MVT InnerVT : MVT::vector_valuetypes()) {
635 setTruncStoreAction(VT, InnerVT, Expand);
636 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
637 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
638 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
639 }
640 }
641
642 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
643 // with merges, splats, etc.
644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
645
646 setOperationAction(ISD::AND , MVT::v4i32, Legal);
647 setOperationAction(ISD::OR , MVT::v4i32, Legal);
648 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
649 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
650 setOperationAction(ISD::SELECT, MVT::v4i32,
651 Subtarget.useCRBits() ? Legal : Expand);
652 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
653 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
654 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
655 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
656 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
657 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
658 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
659 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
660 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
661
662 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
663 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
664 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
665 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
666
667 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
668 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
669
670 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
671 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
672 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
673 }
674
675 if (Subtarget.hasP8Altivec())
676 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
677 else
678 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
679
680 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
681 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
682
683 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
684 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
685
686 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
687 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
688 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
689 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
690
691 // Altivec does not contain unordered floating-point compare instructions
692 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
693 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
694 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
695 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
696
697 if (Subtarget.hasVSX()) {
698 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
699 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
700 if (Subtarget.hasP8Vector()) {
701 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
702 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
703 }
704 if (Subtarget.hasDirectMove() && isPPC64) {
705 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
706 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
707 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
708 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
709 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
710 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
711 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
712 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
713 }
714 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
715
716 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
717 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
718 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
719 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
720 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
721
722 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
723
724 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
725 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
726
727 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
728 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
729
730 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
731 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
732 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
733 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
734 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
735
736 // Share the Altivec comparison restrictions.
737 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
738 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
739 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
740 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
741
742 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
743 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
744
745 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
746
747 if (Subtarget.hasP8Vector())
748 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
749
750 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
751
752 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
753 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
754 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
755
756 if (Subtarget.hasP8Altivec()) {
757 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
758 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
759 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
760
761 // 128 bit shifts can be accomplished via 3 instructions for SHL and
762 // SRL, but not for SRA because of the instructions available:
763 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
764 // doing
765 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
766 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
767 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
768
769 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
770 }
771 else {
772 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
773 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
774 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
775
776 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
777
778 // VSX v2i64 only supports non-arithmetic operations.
779 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
780 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
781 }
782
783 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
784 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
785 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
786 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
787
788 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
789
790 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
791 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
792 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
793 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
794
795 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
796 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
797
798 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
799 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
800 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
801 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
802
803 if (Subtarget.hasDirectMove())
804 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
805 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
806
807 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
808 }
809
810 if (Subtarget.hasP8Altivec()) {
811 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
812 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
813 }
814
815 if (Subtarget.hasP9Vector()) {
816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
817 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
818
819 // 128 bit shifts can be accomplished via 3 instructions for SHL and
820 // SRL, but not for SRA because of the instructions available:
821 // VS{RL} and VS{RL}O.
822 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
823 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
824 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
825
826 if (EnableQuadPrecision) {
827 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
828 setOperationAction(ISD::FADD, MVT::f128, Legal);
829 setOperationAction(ISD::FSUB, MVT::f128, Legal);
830 setOperationAction(ISD::FDIV, MVT::f128, Legal);
831 setOperationAction(ISD::FMUL, MVT::f128, Legal);
832 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
833 // No extending loads to f128 on PPC.
834 for (MVT FPT : MVT::fp_valuetypes())
835 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
836 setOperationAction(ISD::FMA, MVT::f128, Legal);
837 setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
838 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
839 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
840 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
841 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
842 setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
843
844 setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
845 setOperationAction(ISD::FRINT, MVT::f128, Legal);
846 setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
847 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
848 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
849 setOperationAction(ISD::FROUND, MVT::f128, Legal);
850
851 setOperationAction(ISD::SELECT, MVT::f128, Expand);
852 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
853 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
854 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
855 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
856 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
857 // No implementation for these ops for PowerPC.
858 setOperationAction(ISD::FSIN , MVT::f128, Expand);
859 setOperationAction(ISD::FCOS , MVT::f128, Expand);
860 setOperationAction(ISD::FPOW, MVT::f128, Expand);
861 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
862 setOperationAction(ISD::FREM, MVT::f128, Expand);
863 }
864
865 }
866
867 if (Subtarget.hasP9Altivec()) {
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
870 }
871 }
872
873 if (Subtarget.hasQPX()) {
874 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
875 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
876 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
877 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
878
879 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
880 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
881
882 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
883 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
884
885 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
886 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
887
888 if (!Subtarget.useCRBits())
889 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
890 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
891
892 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
893 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
894 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
895 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
896 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
898 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
899
900 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
901 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
902
903 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
904 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
905 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
906
907 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
908 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
909 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
910 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
911 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
912 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
913 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
914 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
915 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
916 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
917
918 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
919 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
920
921 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
922 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
923
924 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
925
926 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
927 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
928 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
929 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
930
931 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
932 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
933
934 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
935 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
936
937 if (!Subtarget.useCRBits())
938 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
939 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
940
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
942 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
943 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
944 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
945 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
946 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
947 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
948
949 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
950 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
951
952 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
953 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
954 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
955 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
956 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
957 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
958 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
959 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
960 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
961 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
962
963 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
964 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
965
966 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
967 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
968
969 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
970
971 setOperationAction(ISD::AND , MVT::v4i1, Legal);
972 setOperationAction(ISD::OR , MVT::v4i1, Legal);
973 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
974
975 if (!Subtarget.useCRBits())
976 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
977 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
978
979 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
980 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
981
982 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
983 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
984 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
985 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
986 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
987 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
988 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
989
990 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
991 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
992
993 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
994
995 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
996 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
997 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
998 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
999
1000 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1001 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1002 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1003 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
1004
1005 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
1006 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
1007
1008 // These need to set FE_INEXACT, and so cannot be vectorized here.
1009 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
1010 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
1011
1012 if (TM.Options.UnsafeFPMath) {
1013 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1014 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1015
1016 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
1017 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
1018 } else {
1019 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
1020 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
1021
1022 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
1023 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
1024 }
1025 }
1026
1027 if (Subtarget.has64BitSupport())
1028 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
1029
1030 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1031
1032 if (!isPPC64) {
1033 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
1034 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
1035 }
1036
1037 setBooleanContents(ZeroOrOneBooleanContent);
1038
1039 if (Subtarget.hasAltivec()) {
1040 // Altivec instructions set fields to all zeros or all ones.
1041 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
1042 }
1043
1044 if (!isPPC64) {
1045 // These libcalls are not available in 32-bit.
1046 setLibcallName(RTLIB::SHL_I128, nullptr);
1047 setLibcallName(RTLIB::SRL_I128, nullptr);
1048 setLibcallName(RTLIB::SRA_I128, nullptr);
1049 }
1050
1051 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1052
1053 // We have target-specific dag combine patterns for the following nodes:
1054 setTargetDAGCombine(ISD::ADD);
1055 setTargetDAGCombine(ISD::SHL);
1056 setTargetDAGCombine(ISD::SRA);
1057 setTargetDAGCombine(ISD::SRL);
1058 setTargetDAGCombine(ISD::SINT_TO_FP);
1059 setTargetDAGCombine(ISD::BUILD_VECTOR);
1060 if (Subtarget.hasFPCVT())
1061 setTargetDAGCombine(ISD::UINT_TO_FP);
1062 setTargetDAGCombine(ISD::LOAD);
1063 setTargetDAGCombine(ISD::STORE);
1064 setTargetDAGCombine(ISD::BR_CC);
1065 if (Subtarget.useCRBits())
1066 setTargetDAGCombine(ISD::BRCOND);
1067 setTargetDAGCombine(ISD::BSWAP);
1068 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1069 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
1070 setTargetDAGCombine(ISD::INTRINSIC_VOID);
1071
1072 setTargetDAGCombine(ISD::SIGN_EXTEND);
1073 setTargetDAGCombine(ISD::ZERO_EXTEND);
1074 setTargetDAGCombine(ISD::ANY_EXTEND);
1075
1076 setTargetDAGCombine(ISD::TRUNCATE);
1077
1078 if (Subtarget.useCRBits()) {
1079 setTargetDAGCombine(ISD::TRUNCATE);
1080 setTargetDAGCombine(ISD::SETCC);
1081 setTargetDAGCombine(ISD::SELECT_CC);
1082 }
1083
1084 // Use reciprocal estimates.
1085 if (TM.Options.UnsafeFPMath) {
1086 setTargetDAGCombine(ISD::FDIV);
1087 setTargetDAGCombine(ISD::FSQRT);
1088 }
1089
1090 // Darwin long double math library functions have $LDBL128 appended.
1091 if (Subtarget.isDarwin()) {
1092 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
1093 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
1094 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
1095 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
1096 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
1097 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
1098 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
1099 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
1100 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
1101 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
1102 }
1103
1104 if (EnableQuadPrecision) {
1105 setLibcallName(RTLIB::LOG_F128, "logf128");
1106 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1107 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1108 setLibcallName(RTLIB::EXP_F128, "expf128");
1109 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1110 setLibcallName(RTLIB::SIN_F128, "sinf128");
1111 setLibcallName(RTLIB::COS_F128, "cosf128");
1112 setLibcallName(RTLIB::POW_F128, "powf128");
1113 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1114 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1115 setLibcallName(RTLIB::POWI_F128, "__powikf2");
1116 setLibcallName(RTLIB::REM_F128, "fmodf128");
1117 }
1118
1119 // With 32 condition bits, we don't need to sink (and duplicate) compares
1120 // aggressively in CodeGenPrep.
1121 if (Subtarget.useCRBits()) {
1122 setHasMultipleConditionRegisters();
1123 setJumpIsExpensive();
1124 }
1125
1126 setMinFunctionAlignment(2);
1127 if (Subtarget.isDarwin())
1128 setPrefFunctionAlignment(4);
1129
1130 switch (Subtarget.getDarwinDirective()) {
1131 default: break;
1132 case PPC::DIR_970:
1133 case PPC::DIR_A2:
1134 case PPC::DIR_E500:
1135 case PPC::DIR_E500mc:
1136 case PPC::DIR_E5500:
1137 case PPC::DIR_PWR4:
1138 case PPC::DIR_PWR5:
1139 case PPC::DIR_PWR5X:
1140 case PPC::DIR_PWR6:
1141 case PPC::DIR_PWR6X:
1142 case PPC::DIR_PWR7:
1143 case PPC::DIR_PWR8:
1144 case PPC::DIR_PWR9:
1145 setPrefFunctionAlignment(4);
1146 setPrefLoopAlignment(4);
1147 break;
1148 }
1149
1150 if (Subtarget.enableMachineScheduler())
1151 setSchedulingPreference(Sched::Source);
1152 else
1153 setSchedulingPreference(Sched::Hybrid);
1154
1155 computeRegisterProperties(STI.getRegisterInfo());
1156
1157 // The Freescale cores do better with aggressive inlining of memcpy and
1158 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1159 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
1160 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
1161 MaxStoresPerMemset = 32;
1162 MaxStoresPerMemsetOptSize = 16;
1163 MaxStoresPerMemcpy = 32;
1164 MaxStoresPerMemcpyOptSize = 8;
1165 MaxStoresPerMemmove = 32;
1166 MaxStoresPerMemmoveOptSize = 8;
1167 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
1168 // The A2 also benefits from (very) aggressive inlining of memcpy and
1169 // friends. The overhead of a the function call, even when warm, can be
1170 // over one hundred cycles.
1171 MaxStoresPerMemset = 128;
1172 MaxStoresPerMemcpy = 128;
1173 MaxStoresPerMemmove = 128;
1174 MaxLoadsPerMemcmp = 128;
1175 } else {
1176 MaxLoadsPerMemcmp = 8;
1177 MaxLoadsPerMemcmpOptSize = 4;
1178 }
1179}
1180
1181/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1182/// the desired ByVal argument alignment.
1183static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
1184 unsigned MaxMaxAlign) {
1185 if (MaxAlign == MaxMaxAlign)
1186 return;
1187 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1188 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
1189 MaxAlign = 32;
1190 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
1191 MaxAlign = 16;
1192 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1193 unsigned EltAlign = 0;
1194 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1195 if (EltAlign > MaxAlign)
1196 MaxAlign = EltAlign;
1197 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1198 for (auto *EltTy : STy->elements()) {
1199 unsigned EltAlign = 0;
1200 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1201 if (EltAlign > MaxAlign)
1202 MaxAlign = EltAlign;
1203 if (MaxAlign == MaxMaxAlign)
1204 break;
1205 }
1206 }
1207}
1208
1209/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1210/// function arguments in the caller parameter area.
1211unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1212 const DataLayout &DL) const {
1213 // Darwin passes everything on 4 byte boundary.
1214 if (Subtarget.isDarwin())
1215 return 4;
1216
1217 // 16byte and wider vectors are passed on 16byte boundary.
1218 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1219 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
1220 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
1221 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
1222 return Align;
1223}
1224
1225unsigned PPCTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
1226 CallingConv:: ID CC,
1227 EVT VT) const {
1228 if (Subtarget.hasSPE() && VT == MVT::f64)
1229 return 2;
1230 return PPCTargetLowering::getNumRegisters(Context, VT);
1231}
1232
1233MVT PPCTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
1234 CallingConv:: ID CC,
1235 EVT VT) const {
1236 if (Subtarget.hasSPE() && VT == MVT::f64)
1237 return MVT::i32;
1238 return PPCTargetLowering::getRegisterType(Context, VT);
1239}
1240
1241bool PPCTargetLowering::useSoftFloat() const {
1242 return Subtarget.useSoftFloat();
1243}
1244
1245bool PPCTargetLowering::hasSPE() const {
1246 return Subtarget.hasSPE();
1247}
1248
1249const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1250 switch ((PPCISD::NodeType)Opcode) {
1251 case PPCISD::FIRST_NUMBER: break;
1252 case PPCISD::FSEL: return "PPCISD::FSEL";
1253 case PPCISD::FCFID: return "PPCISD::FCFID";
1254 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1255 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1256 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1257 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1258 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1259 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1260 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1261 case PPCISD::FP_TO_UINT_IN_VSR:
1262 return "PPCISD::FP_TO_UINT_IN_VSR,";
1263 case PPCISD::FP_TO_SINT_IN_VSR:
1264 return "PPCISD::FP_TO_SINT_IN_VSR";
1265 case PPCISD::FRE: return "PPCISD::FRE";
1266 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1267 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1268 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
1269 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
1270 case PPCISD::VPERM: return "PPCISD::VPERM";
1271 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1272 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1273 case PPCISD::XXREVERSE: return "PPCISD::XXREVERSE";
1274 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1275 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1276 case PPCISD::CMPB: return "PPCISD::CMPB";
1277 case PPCISD::Hi: return "PPCISD::Hi";
1278 case PPCISD::Lo: return "PPCISD::Lo";
1279 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1280 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1281 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1282 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1283 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1284 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1285 case PPCISD::SRL: return "PPCISD::SRL";
1286 case PPCISD::SRA: return "PPCISD::SRA";
1287 case PPCISD::SHL: return "PPCISD::SHL";
1288 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1289 case PPCISD::CALL: return "PPCISD::CALL";
1290 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1291 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1292 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1293 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1294 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1295 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1296 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1297 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1298 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1299 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1300 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1301 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1302 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1303 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1304 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1305 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1306 case PPCISD::VCMP: return "PPCISD::VCMP";
1307 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1308 case PPCISD::LBRX: return "PPCISD::LBRX";
1309 case PPCISD::STBRX: return "PPCISD::STBRX";
1310 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1311 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1312 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1313 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1314 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1315 case PPCISD::SExtVElems: return "PPCISD::SExtVElems";
1316 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1317 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1318 case PPCISD::ST_VSR_SCAL_INT:
1319 return "PPCISD::ST_VSR_SCAL_INT";
1320 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1321 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1322 case PPCISD::BDZ: return "PPCISD::BDZ";
1323 case PPCISD::MFFS: return "PPCISD::MFFS";
1324 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1325 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1326 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1327 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1328 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1329 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1330 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1331 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1332 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1333 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1334 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1335 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1336 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1337 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1338 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1339 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1340 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1341 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1342 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1343 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1344 case PPCISD::SC: return "PPCISD::SC";
1345 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1346 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1347 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1348 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1349 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1350 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1351 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1352 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1353 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1354 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1355 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1356 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1357 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1358 }
1359 return nullptr;
1360}
1361
1362EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1363 EVT VT) const {
1364 if (!VT.isVector())
1365 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1366
1367 if (Subtarget.hasQPX())
1368 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1369
1370 return VT.changeVectorElementTypeToInteger();
1371}
1372
1373bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1374 assert(VT.isFloatingPoint() && "Non-floating-point FMA?")((VT.isFloatingPoint() && "Non-floating-point FMA?") ?
static_cast<void> (0) : __assert_fail ("VT.isFloatingPoint() && \"Non-floating-point FMA?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1374, __PRETTY_FUNCTION__))
;
1375 return true;
1376}
1377
1378//===----------------------------------------------------------------------===//
1379// Node matching predicates, for use by the tblgen matching code.
1380//===----------------------------------------------------------------------===//
1381
1382/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1383static bool isFloatingPointZero(SDValue Op) {
1384 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1385 return CFP->getValueAPF().isZero();
1386 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1387 // Maybe this has already been legalized into the constant pool?
1388 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1389 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1390 return CFP->getValueAPF().isZero();
1391 }
1392 return false;
1393}
1394
1395/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1396/// true if Op is undef or if it matches the specified value.
1397static bool isConstantOrUndef(int Op, int Val) {
1398 return Op < 0 || Op == Val;
1399}
1400
1401/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1402/// VPKUHUM instruction.
1403/// The ShuffleKind distinguishes between big-endian operations with
1404/// two different inputs (0), either-endian operations with two identical
1405/// inputs (1), and little-endian operations with two different inputs (2).
1406/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1407bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1408 SelectionDAG &DAG) {
1409 bool IsLE = DAG.getDataLayout().isLittleEndian();
1410 if (ShuffleKind == 0) {
1411 if (IsLE)
1412 return false;
1413 for (unsigned i = 0; i != 16; ++i)
1414 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1415 return false;
1416 } else if (ShuffleKind == 2) {
1417 if (!IsLE)
1418 return false;
1419 for (unsigned i = 0; i != 16; ++i)
1420 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1421 return false;
1422 } else if (ShuffleKind == 1) {
1423 unsigned j = IsLE ? 0 : 1;
1424 for (unsigned i = 0; i != 8; ++i)
1425 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1426 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1427 return false;
1428 }
1429 return true;
1430}
1431
1432/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1433/// VPKUWUM instruction.
1434/// The ShuffleKind distinguishes between big-endian operations with
1435/// two different inputs (0), either-endian operations with two identical
1436/// inputs (1), and little-endian operations with two different inputs (2).
1437/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1438bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1439 SelectionDAG &DAG) {
1440 bool IsLE = DAG.getDataLayout().isLittleEndian();
1441 if (ShuffleKind == 0) {
1442 if (IsLE)
1443 return false;
1444 for (unsigned i = 0; i != 16; i += 2)
1445 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1446 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1447 return false;
1448 } else if (ShuffleKind == 2) {
1449 if (!IsLE)
1450 return false;
1451 for (unsigned i = 0; i != 16; i += 2)
1452 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1453 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1454 return false;
1455 } else if (ShuffleKind == 1) {
1456 unsigned j = IsLE ? 0 : 2;
1457 for (unsigned i = 0; i != 8; i += 2)
1458 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1459 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1460 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1461 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1462 return false;
1463 }
1464 return true;
1465}
1466
1467/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1468/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1469/// current subtarget.
1470///
1471/// The ShuffleKind distinguishes between big-endian operations with
1472/// two different inputs (0), either-endian operations with two identical
1473/// inputs (1), and little-endian operations with two different inputs (2).
1474/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1475bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1476 SelectionDAG &DAG) {
1477 const PPCSubtarget& Subtarget =
1478 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1479 if (!Subtarget.hasP8Vector())
1480 return false;
1481
1482 bool IsLE = DAG.getDataLayout().isLittleEndian();
1483 if (ShuffleKind == 0) {
1484 if (IsLE)
1485 return false;
1486 for (unsigned i = 0; i != 16; i += 4)
1487 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1488 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1489 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1490 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1491 return false;
1492 } else if (ShuffleKind == 2) {
1493 if (!IsLE)
1494 return false;
1495 for (unsigned i = 0; i != 16; i += 4)
1496 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1497 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1498 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1499 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1500 return false;
1501 } else if (ShuffleKind == 1) {
1502 unsigned j = IsLE ? 0 : 4;
1503 for (unsigned i = 0; i != 8; i += 4)
1504 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1505 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1506 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1507 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1508 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1509 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1510 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1511 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1512 return false;
1513 }
1514 return true;
1515}
1516
1517/// isVMerge - Common function, used to match vmrg* shuffles.
1518///
1519static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1520 unsigned LHSStart, unsigned RHSStart) {
1521 if (N->getValueType(0) != MVT::v16i8)
1522 return false;
1523 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1524, __PRETTY_FUNCTION__))
1524 "Unsupported merge size!")(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1524, __PRETTY_FUNCTION__))
;
1525
1526 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1527 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1528 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1529 LHSStart+j+i*UnitSize) ||
1530 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1531 RHSStart+j+i*UnitSize))
1532 return false;
1533 }
1534 return true;
1535}
1536
1537/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1538/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1539/// The ShuffleKind distinguishes between big-endian merges with two
1540/// different inputs (0), either-endian merges with two identical inputs (1),
1541/// and little-endian merges with two different inputs (2). For the latter,
1542/// the input operands are swapped (see PPCInstrAltivec.td).
1543bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1544 unsigned ShuffleKind, SelectionDAG &DAG) {
1545 if (DAG.getDataLayout().isLittleEndian()) {
1546 if (ShuffleKind == 1) // unary
1547 return isVMerge(N, UnitSize, 0, 0);
1548 else if (ShuffleKind == 2) // swapped
1549 return isVMerge(N, UnitSize, 0, 16);
1550 else
1551 return false;
1552 } else {
1553 if (ShuffleKind == 1) // unary
1554 return isVMerge(N, UnitSize, 8, 8);
1555 else if (ShuffleKind == 0) // normal
1556 return isVMerge(N, UnitSize, 8, 24);
1557 else
1558 return false;
1559 }
1560}
1561
1562/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1563/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1564/// The ShuffleKind distinguishes between big-endian merges with two
1565/// different inputs (0), either-endian merges with two identical inputs (1),
1566/// and little-endian merges with two different inputs (2). For the latter,
1567/// the input operands are swapped (see PPCInstrAltivec.td).
1568bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1569 unsigned ShuffleKind, SelectionDAG &DAG) {
1570 if (DAG.getDataLayout().isLittleEndian()) {
1571 if (ShuffleKind == 1) // unary
1572 return isVMerge(N, UnitSize, 8, 8);
1573 else if (ShuffleKind == 2) // swapped
1574 return isVMerge(N, UnitSize, 8, 24);
1575 else
1576 return false;
1577 } else {
1578 if (ShuffleKind == 1) // unary
1579 return isVMerge(N, UnitSize, 0, 0);
1580 else if (ShuffleKind == 0) // normal
1581 return isVMerge(N, UnitSize, 0, 16);
1582 else
1583 return false;
1584 }
1585}
1586
1587/**
1588 * Common function used to match vmrgew and vmrgow shuffles
1589 *
1590 * The indexOffset determines whether to look for even or odd words in
1591 * the shuffle mask. This is based on the of the endianness of the target
1592 * machine.
1593 * - Little Endian:
1594 * - Use offset of 0 to check for odd elements
1595 * - Use offset of 4 to check for even elements
1596 * - Big Endian:
1597 * - Use offset of 0 to check for even elements
1598 * - Use offset of 4 to check for odd elements
1599 * A detailed description of the vector element ordering for little endian and
1600 * big endian can be found at
1601 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1602 * Targeting your applications - what little endian and big endian IBM XL C/C++
1603 * compiler differences mean to you
1604 *
1605 * The mask to the shuffle vector instruction specifies the indices of the
1606 * elements from the two input vectors to place in the result. The elements are
1607 * numbered in array-access order, starting with the first vector. These vectors
1608 * are always of type v16i8, thus each vector will contain 16 elements of size
1609 * 8. More info on the shuffle vector can be found in the
1610 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1611 * Language Reference.
1612 *
1613 * The RHSStartValue indicates whether the same input vectors are used (unary)
1614 * or two different input vectors are used, based on the following:
1615 * - If the instruction uses the same vector for both inputs, the range of the
1616 * indices will be 0 to 15. In this case, the RHSStart value passed should
1617 * be 0.
1618 * - If the instruction has two different vectors then the range of the
1619 * indices will be 0 to 31. In this case, the RHSStart value passed should
1620 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1621 * to 31 specify elements in the second vector).
1622 *
1623 * \param[in] N The shuffle vector SD Node to analyze
1624 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1625 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1626 * vector to the shuffle_vector instruction
1627 * \return true iff this shuffle vector represents an even or odd word merge
1628 */
1629static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1630 unsigned RHSStartValue) {
1631 if (N->getValueType(0) != MVT::v16i8)
1632 return false;
1633
1634 for (unsigned i = 0; i < 2; ++i)
1635 for (unsigned j = 0; j < 4; ++j)
1636 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1637 i*RHSStartValue+j+IndexOffset) ||
1638 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1639 i*RHSStartValue+j+IndexOffset+8))
1640 return false;
1641 return true;
1642}
1643
1644/**
1645 * Determine if the specified shuffle mask is suitable for the vmrgew or
1646 * vmrgow instructions.
1647 *
1648 * \param[in] N The shuffle vector SD Node to analyze
1649 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1650 * \param[in] ShuffleKind Identify the type of merge:
1651 * - 0 = big-endian merge with two different inputs;
1652 * - 1 = either-endian merge with two identical inputs;
1653 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1654 * little-endian merges).
1655 * \param[in] DAG The current SelectionDAG
1656 * \return true iff this shuffle mask
1657 */
1658bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1659 unsigned ShuffleKind, SelectionDAG &DAG) {
1660 if (DAG.getDataLayout().isLittleEndian()) {
1661 unsigned indexOffset = CheckEven ? 4 : 0;
1662 if (ShuffleKind == 1) // Unary
1663 return isVMerge(N, indexOffset, 0);
1664 else if (ShuffleKind == 2) // swapped
1665 return isVMerge(N, indexOffset, 16);
1666 else
1667 return false;
1668 }
1669 else {
1670 unsigned indexOffset = CheckEven ? 0 : 4;
1671 if (ShuffleKind == 1) // Unary
1672 return isVMerge(N, indexOffset, 0);
1673 else if (ShuffleKind == 0) // Normal
1674 return isVMerge(N, indexOffset, 16);
1675 else
1676 return false;
1677 }
1678 return false;
1679}
1680
1681/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1682/// amount, otherwise return -1.
1683/// The ShuffleKind distinguishes between big-endian operations with two
1684/// different inputs (0), either-endian operations with two identical inputs
1685/// (1), and little-endian operations with two different inputs (2). For the
1686/// latter, the input operands are swapped (see PPCInstrAltivec.td).
1687int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1688 SelectionDAG &DAG) {
1689 if (N->getValueType(0) != MVT::v16i8)
1690 return -1;
1691
1692 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1693
1694 // Find the first non-undef value in the shuffle mask.
1695 unsigned i;
1696 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1697 /*search*/;
1698
1699 if (i == 16) return -1; // all undef.
1700
1701 // Otherwise, check to see if the rest of the elements are consecutively
1702 // numbered from this value.
1703 unsigned ShiftAmt = SVOp->getMaskElt(i);
1704 if (ShiftAmt < i) return -1;
1705
1706 ShiftAmt -= i;
1707 bool isLE = DAG.getDataLayout().isLittleEndian();
1708
1709 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1710 // Check the rest of the elements to see if they are consecutive.
1711 for (++i; i != 16; ++i)
1712 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1713 return -1;
1714 } else if (ShuffleKind == 1) {
1715 // Check the rest of the elements to see if they are consecutive.
1716 for (++i; i != 16; ++i)
1717 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1718 return -1;
1719 } else
1720 return -1;
1721
1722 if (isLE)
1723 ShiftAmt = 16 - ShiftAmt;
1724
1725 return ShiftAmt;
1726}
1727
1728/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1729/// specifies a splat of a single element that is suitable for input to
1730/// VSPLTB/VSPLTH/VSPLTW.
1731bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1732 assert(N->getValueType(0) == MVT::v16i8 &&((N->getValueType(0) == MVT::v16i8 && (EltSize == 1
|| EltSize == 2 || EltSize == 4)) ? static_cast<void> (
0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && (EltSize == 1 || EltSize == 2 || EltSize == 4)"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1733, __PRETTY_FUNCTION__))
1733 (EltSize == 1 || EltSize == 2 || EltSize == 4))((N->getValueType(0) == MVT::v16i8 && (EltSize == 1
|| EltSize == 2 || EltSize == 4)) ? static_cast<void> (
0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && (EltSize == 1 || EltSize == 2 || EltSize == 4)"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1733, __PRETTY_FUNCTION__))
;
1734
1735 // The consecutive indices need to specify an element, not part of two
1736 // different elements. So abandon ship early if this isn't the case.
1737 if (N->getMaskElt(0) % EltSize != 0)
1738 return false;
1739
1740 // This is a splat operation if each element of the permute is the same, and
1741 // if the value doesn't reference the second vector.
1742 unsigned ElementBase = N->getMaskElt(0);
1743
1744 // FIXME: Handle UNDEF elements too!
1745 if (ElementBase >= 16)
1746 return false;
1747
1748 // Check that the indices are consecutive, in the case of a multi-byte element
1749 // splatted with a v16i8 mask.
1750 for (unsigned i = 1; i != EltSize; ++i)
1751 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1752 return false;
1753
1754 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1755 if (N->getMaskElt(i) < 0) continue;
1756 for (unsigned j = 0; j != EltSize; ++j)
1757 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1758 return false;
1759 }
1760 return true;
1761}
1762
1763/// Check that the mask is shuffling N byte elements. Within each N byte
1764/// element of the mask, the indices could be either in increasing or
1765/// decreasing order as long as they are consecutive.
1766/// \param[in] N the shuffle vector SD Node to analyze
1767/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
1768/// Word/DoubleWord/QuadWord).
1769/// \param[in] StepLen the delta indices number among the N byte element, if
1770/// the mask is in increasing/decreasing order then it is 1/-1.
1771/// \return true iff the mask is shuffling N byte elements.
1772static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
1773 int StepLen) {
1774 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1775, __PRETTY_FUNCTION__))
1775 "Unexpected element width.")(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1775, __PRETTY_FUNCTION__))
;
1776 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.")(((StepLen == 1 || StepLen == -1) && "Unexpected element width."
) ? static_cast<void> (0) : __assert_fail ("(StepLen == 1 || StepLen == -1) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1776, __PRETTY_FUNCTION__))
;
1777
1778 unsigned NumOfElem = 16 / Width;
1779 unsigned MaskVal[16]; // Width is never greater than 16
1780 for (unsigned i = 0; i < NumOfElem; ++i) {
1781 MaskVal[0] = N->getMaskElt(i * Width);
1782 if ((StepLen == 1) && (MaskVal[0] % Width)) {
1783 return false;
1784 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
1785 return false;
1786 }
1787
1788 for (unsigned int j = 1; j < Width; ++j) {
1789 MaskVal[j] = N->getMaskElt(i * Width + j);
1790 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
1791 return false;
1792 }
1793 }
1794 }
1795
1796 return true;
1797}
1798
1799bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1800 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
1801 if (!isNByteElemShuffleMask(N, 4, 1))
1802 return false;
1803
1804 // Now we look at mask elements 0,4,8,12
1805 unsigned M0 = N->getMaskElt(0) / 4;
1806 unsigned M1 = N->getMaskElt(4) / 4;
1807 unsigned M2 = N->getMaskElt(8) / 4;
1808 unsigned M3 = N->getMaskElt(12) / 4;
1809 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
1810 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
1811
1812 // Below, let H and L be arbitrary elements of the shuffle mask
1813 // where H is in the range [4,7] and L is in the range [0,3].
1814 // H, 1, 2, 3 or L, 5, 6, 7
1815 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
1816 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
1817 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
1818 InsertAtByte = IsLE ? 12 : 0;
1819 Swap = M0 < 4;
1820 return true;
1821 }
1822 // 0, H, 2, 3 or 4, L, 6, 7
1823 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
1824 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
1825 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
1826 InsertAtByte = IsLE ? 8 : 4;
1827 Swap = M1 < 4;
1828 return true;
1829 }
1830 // 0, 1, H, 3 or 4, 5, L, 7
1831 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
1832 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
1833 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
1834 InsertAtByte = IsLE ? 4 : 8;
1835 Swap = M2 < 4;
1836 return true;
1837 }
1838 // 0, 1, 2, H or 4, 5, 6, L
1839 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
1840 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
1841 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
1842 InsertAtByte = IsLE ? 0 : 12;
1843 Swap = M3 < 4;
1844 return true;
1845 }
1846
1847 // If both vector operands for the shuffle are the same vector, the mask will
1848 // contain only elements from the first one and the second one will be undef.
1849 if (N->getOperand(1).isUndef()) {
1850 ShiftElts = 0;
1851 Swap = true;
1852 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
1853 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
1854 InsertAtByte = IsLE ? 12 : 0;
1855 return true;
1856 }
1857 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
1858 InsertAtByte = IsLE ? 8 : 4;
1859 return true;
1860 }
1861 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
1862 InsertAtByte = IsLE ? 4 : 8;
1863 return true;
1864 }
1865 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
1866 InsertAtByte = IsLE ? 0 : 12;
1867 return true;
1868 }
1869 }
1870
1871 return false;
1872}
1873
1874bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1875 bool &Swap, bool IsLE) {
1876 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1876, __PRETTY_FUNCTION__))
;
1877 // Ensure each byte index of the word is consecutive.
1878 if (!isNByteElemShuffleMask(N, 4, 1))
1879 return false;
1880
1881 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
1882 unsigned M0 = N->getMaskElt(0) / 4;
1883 unsigned M1 = N->getMaskElt(4) / 4;
1884 unsigned M2 = N->getMaskElt(8) / 4;
1885 unsigned M3 = N->getMaskElt(12) / 4;
1886
1887 // If both vector operands for the shuffle are the same vector, the mask will
1888 // contain only elements from the first one and the second one will be undef.
1889 if (N->getOperand(1).isUndef()) {
1890 assert(M0 < 4 && "Indexing into an undef vector?")((M0 < 4 && "Indexing into an undef vector?") ? static_cast
<void> (0) : __assert_fail ("M0 < 4 && \"Indexing into an undef vector?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1890, __PRETTY_FUNCTION__))
;
1891 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
1892 return false;
1893
1894 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
1895 Swap = false;
1896 return true;
1897 }
1898
1899 // Ensure each word index of the ShuffleVector Mask is consecutive.
1900 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
1901 return false;
1902
1903 if (IsLE) {
1904 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
1905 // Input vectors don't need to be swapped if the leading element
1906 // of the result is one of the 3 left elements of the second vector
1907 // (or if there is no shift to be done at all).
1908 Swap = false;
1909 ShiftElts = (8 - M0) % 8;
1910 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
1911 // Input vectors need to be swapped if the leading element
1912 // of the result is one of the 3 left elements of the first vector
1913 // (or if we're shifting by 4 - thereby simply swapping the vectors).
1914 Swap = true;
1915 ShiftElts = (4 - M0) % 4;
1916 }
1917
1918 return true;
1919 } else { // BE
1920 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
1921 // Input vectors don't need to be swapped if the leading element
1922 // of the result is one of the 4 elements of the first vector.
1923 Swap = false;
1924 ShiftElts = M0;
1925 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
1926 // Input vectors need to be swapped if the leading element
1927 // of the result is one of the 4 elements of the right vector.
1928 Swap = true;
1929 ShiftElts = M0 - 4;
1930 }
1931
1932 return true;
1933 }
1934}
1935
1936bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
1937 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1937, __PRETTY_FUNCTION__))
;
1938
1939 if (!isNByteElemShuffleMask(N, Width, -1))
1940 return false;
1941
1942 for (int i = 0; i < 16; i += Width)
1943 if (N->getMaskElt(i) != i + Width - 1)
1944 return false;
1945
1946 return true;
1947}
1948
1949bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
1950 return isXXBRShuffleMaskHelper(N, 2);
1951}
1952
1953bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
1954 return isXXBRShuffleMaskHelper(N, 4);
1955}
1956
1957bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
1958 return isXXBRShuffleMaskHelper(N, 8);
1959}
1960
1961bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
1962 return isXXBRShuffleMaskHelper(N, 16);
1963}
1964
1965/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
1966/// if the inputs to the instruction should be swapped and set \p DM to the
1967/// value for the immediate.
1968/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
1969/// AND element 0 of the result comes from the first input (LE) or second input
1970/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
1971/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
1972/// mask.
1973bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
1974 bool &Swap, bool IsLE) {
1975 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1975, __PRETTY_FUNCTION__))
;
1976
1977 // Ensure each byte index of the double word is consecutive.
1978 if (!isNByteElemShuffleMask(N, 8, 1))
1979 return false;
1980
1981 unsigned M0 = N->getMaskElt(0) / 8;
1982 unsigned M1 = N->getMaskElt(8) / 8;
1983 assert(((M0 | M1) < 4) && "A mask element out of bounds?")((((M0 | M1) < 4) && "A mask element out of bounds?"
) ? static_cast<void> (0) : __assert_fail ("((M0 | M1) < 4) && \"A mask element out of bounds?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1983, __PRETTY_FUNCTION__))
;
1984
1985 // If both vector operands for the shuffle are the same vector, the mask will
1986 // contain only elements from the first one and the second one will be undef.
1987 if (N->getOperand(1).isUndef()) {
1988 if ((M0 | M1) < 2) {
1989 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
1990 Swap = false;
1991 return true;
1992 } else
1993 return false;
1994 }
1995
1996 if (IsLE) {
1997 if (M0 > 1 && M1 < 2) {
1998 Swap = false;
1999 } else if (M0 < 2 && M1 > 1) {
2000 M0 = (M0 + 2) % 4;
2001 M1 = (M1 + 2) % 4;
2002 Swap = true;
2003 } else
2004 return false;
2005
2006 // Note: if control flow comes here that means Swap is already set above
2007 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2008 return true;
2009 } else { // BE
2010 if (M0 < 2 && M1 > 1) {
2011 Swap = false;
2012 } else if (M0 > 1 && M1 < 2) {
2013 M0 = (M0 + 2) % 4;
2014 M1 = (M1 + 2) % 4;
2015 Swap = true;
2016 } else
2017 return false;
2018
2019 // Note: if control flow comes here that means Swap is already set above
2020 DM = (M0 << 1) + (M1 & 1);
2021 return true;
2022 }
2023}
2024
2025
2026/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
2027/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
2028unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
2029 SelectionDAG &DAG) {
2030 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2031 assert(isSplatShuffleMask(SVOp, EltSize))((isSplatShuffleMask(SVOp, EltSize)) ? static_cast<void>
(0) : __assert_fail ("isSplatShuffleMask(SVOp, EltSize)", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2031, __PRETTY_FUNCTION__))
;
2032 if (DAG.getDataLayout().isLittleEndian())
2033 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2034 else
2035 return SVOp->getMaskElt(0) / EltSize;
2036}
2037
2038/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2039/// by using a vspltis[bhw] instruction of the specified element size, return
2040/// the constant being splatted. The ByteSize field indicates the number of
2041/// bytes of each element [124] -> [bhw].
2042SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2043 SDValue OpVal(nullptr, 0);
2044
2045 // If ByteSize of the splat is bigger than the element size of the
2046 // build_vector, then we have a case where we are checking for a splat where
2047 // multiple elements of the buildvector are folded together into a single
2048 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2049 unsigned EltSize = 16/N->getNumOperands();
2050 if (EltSize < ByteSize) {
2051 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2052 SDValue UniquedVals[4];
2053 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?")((Multiple > 1 && Multiple <= 4 && "How can this happen?"
) ? static_cast<void> (0) : __assert_fail ("Multiple > 1 && Multiple <= 4 && \"How can this happen?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2053, __PRETTY_FUNCTION__))
;
2054
2055 // See if all of the elements in the buildvector agree across.
2056 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2057 if (N->getOperand(i).isUndef()) continue;
2058 // If the element isn't a constant, bail fully out.
2059 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2060
2061 if (!UniquedVals[i&(Multiple-1)].getNode())
2062 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2063 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2064 return SDValue(); // no match.
2065 }
2066
2067 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2068 // either constant or undef values that are identical for each chunk. See
2069 // if these chunks can form into a larger vspltis*.
2070
2071 // Check to see if all of the leading entries are either 0 or -1. If
2072 // neither, then this won't fit into the immediate field.
2073 bool LeadingZero = true;
2074 bool LeadingOnes = true;
2075 for (unsigned i = 0; i != Multiple-1; ++i) {
2076 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2077
2078 LeadingZero &= isNullConstant(UniquedVals[i]);
2079 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2080 }
2081 // Finally, check the least significant entry.
2082 if (LeadingZero) {
2083 if (!UniquedVals[Multiple-1].getNode())
2084 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2085 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2086 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2087 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2088 }
2089 if (LeadingOnes) {
2090 if (!UniquedVals[Multiple-1].getNode())
2091 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2092 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2093 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2094 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2095 }
2096
2097 return SDValue();
2098 }
2099
2100 // Check to see if this buildvec has a single non-undef value in its elements.
2101 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2102 if (N->getOperand(i).isUndef()) continue;
2103 if (!OpVal.getNode())
2104 OpVal = N->getOperand(i);
2105 else if (OpVal != N->getOperand(i))
2106 return SDValue();
2107 }
2108
2109 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2110
2111 unsigned ValSizeInBytes = EltSize;
2112 uint64_t Value = 0;
2113 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2114 Value = CN->getZExtValue();
2115 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2116 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!")((CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"
) ? static_cast<void> (0) : __assert_fail ("CN->getValueType(0) == MVT::f32 && \"Only one legal FP vector type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2116, __PRETTY_FUNCTION__))
;
2117 Value = FloatToBits(CN->getValueAPF().convertToFloat());
2118 }
2119
2120 // If the splat value is larger than the element value, then we can never do
2121 // this splat. The only case that we could fit the replicated bits into our
2122 // immediate field for would be zero, and we prefer to use vxor for it.
2123 if (ValSizeInBytes < ByteSize) return SDValue();
2124
2125 // If the element value is larger than the splat value, check if it consists
2126 // of a repeated bit pattern of size ByteSize.
2127 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2128 return SDValue();
2129
2130 // Properly sign extend the value.
2131 int MaskVal = SignExtend32(Value, ByteSize * 8);
2132
2133 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2134 if (MaskVal == 0) return SDValue();
2135
2136 // Finally, if this value fits in a 5 bit sext field, return it
2137 if (SignExtend32<5>(MaskVal) == MaskVal)
2138 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2139 return SDValue();
2140}
2141
2142/// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
2143/// amount, otherwise return -1.
2144int PPC::isQVALIGNIShuffleMask(SDNode *N) {
2145 EVT VT = N->getValueType(0);
2146 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
2147 return -1;
2148
2149 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2150
2151 // Find the first non-undef value in the shuffle mask.
2152 unsigned i;
2153 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
2154 /*search*/;
2155
2156 if (i == 4) return -1; // all undef.
2157
2158 // Otherwise, check to see if the rest of the elements are consecutively
2159 // numbered from this value.
2160 unsigned ShiftAmt = SVOp->getMaskElt(i);
2161 if (ShiftAmt < i) return -1;
2162 ShiftAmt -= i;
2163
2164 // Check the rest of the elements to see if they are consecutive.
2165 for (++i; i != 4; ++i)
2166 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2167 return -1;
2168
2169 return ShiftAmt;
2170}
2171
2172//===----------------------------------------------------------------------===//
2173// Addressing Mode Selection
2174//===----------------------------------------------------------------------===//
2175
2176/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2177/// or 64-bit immediate, and if the value can be accurately represented as a
2178/// sign extension from a 16-bit value. If so, this returns true and the
2179/// immediate.
2180bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2181 if (!isa<ConstantSDNode>(N))
2182 return false;
2183
2184 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2185 if (N->getValueType(0) == MVT::i32)
2186 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2187 else
2188 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2189}
2190bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2191 return isIntS16Immediate(Op.getNode(), Imm);
2192}
2193
2194/// SelectAddressRegReg - Given the specified addressed, check to see if it
2195/// can be represented as an indexed [r+r] operation. Returns false if it
2196/// can be more efficiently represented with [r+imm].
2197bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
2198 SDValue &Index,
2199 SelectionDAG &DAG) const {
2200 int16_t imm = 0;
2201 if (N.getOpcode() == ISD::ADD) {
2202 if (isIntS16Immediate(N.getOperand(1), imm))
2203 return false; // r+i
2204 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2205 return false; // r+i
2206
2207 Base = N.getOperand(0);
2208 Index = N.getOperand(1);
2209 return true;
2210 } else if (N.getOpcode() == ISD::OR) {
2211 if (isIntS16Immediate(N.getOperand(1), imm))
2212 return false; // r+i can fold it if we can.
2213
2214 // If this is an or of disjoint bitfields, we can codegen this as an add
2215 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2216 // disjoint.
2217 KnownBits LHSKnown, RHSKnown;
2218 DAG.computeKnownBits(N.getOperand(0), LHSKnown);
2219
2220 if (LHSKnown.Zero.getBoolValue()) {
2221 DAG.computeKnownBits(N.getOperand(1), RHSKnown);
2222 // If all of the bits are known zero on the LHS or RHS, the add won't
2223 // carry.
2224 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2225 Base = N.getOperand(0);
2226 Index = N.getOperand(1);
2227 return true;
2228 }
2229 }
2230 }
2231
2232 return false;
2233}
2234
2235// If we happen to be doing an i64 load or store into a stack slot that has
2236// less than a 4-byte alignment, then the frame-index elimination may need to
2237// use an indexed load or store instruction (because the offset may not be a
2238// multiple of 4). The extra register needed to hold the offset comes from the
2239// register scavenger, and it is possible that the scavenger will need to use
2240// an emergency spill slot. As a result, we need to make sure that a spill slot
2241// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2242// stack slot.
2243static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2244 // FIXME: This does not handle the LWA case.
2245 if (VT != MVT::i64)
2246 return;
2247
2248 // NOTE: We'll exclude negative FIs here, which come from argument
2249 // lowering, because there are no known test cases triggering this problem
2250 // using packed structures (or similar). We can remove this exclusion if
2251 // we find such a test case. The reason why this is so test-case driven is
2252 // because this entire 'fixup' is only to prevent crashes (from the
2253 // register scavenger) on not-really-valid inputs. For example, if we have:
2254 // %a = alloca i1
2255 // %b = bitcast i1* %a to i64*
2256 // store i64* a, i64 b
2257 // then the store should really be marked as 'align 1', but is not. If it
2258 // were marked as 'align 1' then the indexed form would have been
2259 // instruction-selected initially, and the problem this 'fixup' is preventing
2260 // won't happen regardless.
2261 if (FrameIdx < 0)
2262 return;
2263
2264 MachineFunction &MF = DAG.getMachineFunction();
2265 MachineFrameInfo &MFI = MF.getFrameInfo();
2266
2267 unsigned Align = MFI.getObjectAlignment(FrameIdx);
2268 if (Align >= 4)
2269 return;
2270
2271 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2272 FuncInfo->setHasNonRISpills();
2273}
2274
2275/// Returns true if the address N can be represented by a base register plus
2276/// a signed 16-bit displacement [r+imm], and if it is not better
2277/// represented as reg+reg. If \p Alignment is non-zero, only accept
2278/// displacements that are multiples of that value.
2279bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
2280 SDValue &Base,
2281 SelectionDAG &DAG,
2282 unsigned Alignment) const {
2283 // FIXME dl should come from parent load or store, not from address
2284 SDLoc dl(N);
2285 // If this can be more profitably realized as r+r, fail.
2286 if (SelectAddressRegReg(N, Disp, Base, DAG))
2287 return false;
2288
2289 if (N.getOpcode() == ISD::ADD) {
2290 int16_t imm = 0;
2291 if (isIntS16Immediate(N.getOperand(1), imm) &&
2292 (!Alignment || (imm % Alignment) == 0)) {
2293 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2294 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2295 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2296 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2297 } else {
2298 Base = N.getOperand(0);
2299 }
2300 return true; // [r+i]
2301 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2302 // Match LOAD (ADD (X, Lo(G))).
2303 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2304, __PRETTY_FUNCTION__))
2304 && "Cannot handle constant offsets yet!")((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2304, __PRETTY_FUNCTION__))
;
2305 Disp = N.getOperand(1).getOperand(0); // The global address.
2306 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2309, __PRETTY_FUNCTION__))
2307 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2309, __PRETTY_FUNCTION__))
2308 Disp.getOpcode() == ISD::TargetConstantPool ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2309, __PRETTY_FUNCTION__))
2309 Disp.getOpcode() == ISD::TargetJumpTable)((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2309, __PRETTY_FUNCTION__))
;
2310 Base = N.getOperand(0);
2311 return true; // [&g+r]
2312 }
2313 } else if (N.getOpcode() == ISD::OR) {
2314 int16_t imm = 0;
2315 if (isIntS16Immediate(N.getOperand(1), imm) &&
2316 (!Alignment || (imm % Alignment) == 0)) {
2317 // If this is an or of disjoint bitfields, we can codegen this as an add
2318 // (for better address arithmetic) if the LHS and RHS of the OR are
2319 // provably disjoint.
2320 KnownBits LHSKnown;
2321 DAG.computeKnownBits(N.getOperand(0), LHSKnown);
2322
2323 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2324 // If all of the bits are known zero on the LHS or RHS, the add won't
2325 // carry.
2326 if (FrameIndexSDNode *FI =
2327 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2328 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2329 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2330 } else {
2331 Base = N.getOperand(0);
2332 }
2333 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2334 return true;
2335 }
2336 }
2337 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2338 // Loading from a constant address.
2339
2340 // If this address fits entirely in a 16-bit sext immediate field, codegen
2341 // this as "d, 0"
2342 int16_t Imm;
2343 if (isIntS16Immediate(CN, Imm) && (!Alignment || (Imm % Alignment) == 0)) {
2344 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2345 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2346 CN->getValueType(0));
2347 return true;
2348 }
2349
2350 // Handle 32-bit sext immediates with LIS + addr mode.
2351 if ((CN->getValueType(0) == MVT::i32 ||
2352 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2353 (!Alignment || (CN->getZExtValue() % Alignment) == 0)) {
2354 int Addr = (int)CN->getZExtValue();
2355
2356 // Otherwise, break this down into an LIS + disp.
2357 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2358
2359 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2360 MVT::i32);
2361 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2362 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2363 return true;
2364 }
2365 }
2366
2367 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2368 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2369 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2370 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2371 } else
2372 Base = N;
2373 return true; // [r+0]
2374}
2375
2376/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2377/// represented as an indexed [r+r] operation.
2378bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2379 SDValue &Index,
2380 SelectionDAG &DAG) const {
2381 // Check to see if we can easily represent this as an [r+r] address. This
2382 // will fail if it thinks that the address is more profitably represented as
2383 // reg+imm, e.g. where imm = 0.
2384 if (SelectAddressRegReg(N, Base, Index, DAG))
2385 return true;
2386
2387 // If the address is the result of an add, we will utilize the fact that the
2388 // address calculation includes an implicit add. However, we can reduce
2389 // register pressure if we do not materialize a constant just for use as the
2390 // index register. We only get rid of the add if it is not an add of a
2391 // value and a 16-bit signed constant and both have a single use.
2392 int16_t imm = 0;
2393 if (N.getOpcode() == ISD::ADD &&
2394 (!isIntS16Immediate(N.getOperand(1), imm) ||
2395 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2396 Base = N.getOperand(0);
2397 Index = N.getOperand(1);
2398 return true;
2399 }
2400
2401 // Otherwise, do it the hard way, using R0 as the base register.
2402 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2403 N.getValueType());
2404 Index = N;
2405 return true;
2406}
2407
2408/// Returns true if we should use a direct load into vector instruction
2409/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2410static bool usePartialVectorLoads(SDNode *N) {
2411 if (!N->hasOneUse())
2412 return false;
2413
2414 // If there are any other uses other than scalar to vector, then we should
2415 // keep it as a scalar load -> direct move pattern to prevent multiple
2416 // loads. Currently, only check for i64 since we have lxsd/lfd to do this
2417 // efficiently, but no update equivalent.
2418 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2419 EVT MemVT = LD->getMemoryVT();
2420 if (MemVT.isSimple() && MemVT.getSimpleVT().SimpleTy == MVT::i64) {
2421 SDNode *User = *(LD->use_begin());
2422 if (User->getOpcode() == ISD::SCALAR_TO_VECTOR)
2423 return true;
2424 }
2425 }
2426
2427 return false;
2428}
2429
2430/// getPreIndexedAddressParts - returns true by value, base pointer and
2431/// offset pointer and addressing mode by reference if the node's address
2432/// can be legally represented as pre-indexed load / store address.
2433bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2434 SDValue &Offset,
2435 ISD::MemIndexedMode &AM,
2436 SelectionDAG &DAG) const {
2437 if (DisablePPCPreinc) return false;
2438
2439 bool isLoad = true;
2440 SDValue Ptr;
2441 EVT VT;
2442 unsigned Alignment;
2443 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2444 Ptr = LD->getBasePtr();
2445 VT = LD->getMemoryVT();
2446 Alignment = LD->getAlignment();
2447 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2448 Ptr = ST->getBasePtr();
2449 VT = ST->getMemoryVT();
2450 Alignment = ST->getAlignment();
2451 isLoad = false;
2452 } else
2453 return false;
2454
2455 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
2456 // instructions because we can fold these into a more efficient instruction
2457 // instead, (such as LXSD).
2458 if (isLoad && usePartialVectorLoads(N)) {
2459 return false;
2460 }
2461
2462 // PowerPC doesn't have preinc load/store instructions for vectors (except
2463 // for QPX, which does have preinc r+r forms).
2464 if (VT.isVector()) {
2465 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
2466 return false;
2467 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
2468 AM = ISD::PRE_INC;
2469 return true;
2470 }
2471 }
2472
2473 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2474 // Common code will reject creating a pre-inc form if the base pointer
2475 // is a frame index, or if N is a store and the base pointer is either
2476 // the same as or a predecessor of the value being stored. Check for
2477 // those situations here, and try with swapped Base/Offset instead.
2478 bool Swap = false;
2479
2480 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2481 Swap = true;
2482 else if (!isLoad) {
2483 SDValue Val = cast<StoreSDNode>(N)->getValue();
2484 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2485 Swap = true;
2486 }
2487
2488 if (Swap)
2489 std::swap(Base, Offset);
2490
2491 AM = ISD::PRE_INC;
2492 return true;
2493 }
2494
2495 // LDU/STU can only handle immediates that are a multiple of 4.
2496 if (VT != MVT::i64) {
2497 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 0))
2498 return false;
2499 } else {
2500 // LDU/STU need an address with at least 4-byte alignment.
2501 if (Alignment < 4)
2502 return false;
2503
2504 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 4))
2505 return false;
2506 }
2507
2508 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2509 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2510 // sext i32 to i64 when addr mode is r+i.
2511 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2512 LD->getExtensionType() == ISD::SEXTLOAD &&
2513 isa<ConstantSDNode>(Offset))
2514 return false;
2515 }
2516
2517 AM = ISD::PRE_INC;
2518 return true;
2519}
2520
2521//===----------------------------------------------------------------------===//
2522// LowerOperation implementation
2523//===----------------------------------------------------------------------===//
2524
2525/// Return true if we should reference labels using a PICBase, set the HiOpFlags
2526/// and LoOpFlags to the target MO flags.
2527static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2528 unsigned &HiOpFlags, unsigned &LoOpFlags,
2529 const GlobalValue *GV = nullptr) {
2530 HiOpFlags = PPCII::MO_HA;
2531 LoOpFlags = PPCII::MO_LO;
2532
2533 // Don't use the pic base if not in PIC relocation model.
2534 if (IsPIC) {
2535 HiOpFlags |= PPCII::MO_PIC_FLAG;
2536 LoOpFlags |= PPCII::MO_PIC_FLAG;
2537 }
2538
2539 // If this is a reference to a global value that requires a non-lazy-ptr, make
2540 // sure that instruction lowering adds it.
2541 if (GV && Subtarget.hasLazyResolverStub(GV)) {
2542 HiOpFlags |= PPCII::MO_NLP_FLAG;
2543 LoOpFlags |= PPCII::MO_NLP_FLAG;
2544
2545 if (GV->hasHiddenVisibility()) {
2546 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2547 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2548 }
2549 }
2550}
2551
2552static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2553 SelectionDAG &DAG) {
2554 SDLoc DL(HiPart);
2555 EVT PtrVT = HiPart.getValueType();
2556 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2557
2558 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2559 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2560
2561 // With PIC, the first instruction is actually "GR+hi(&G)".
2562 if (isPIC)
2563 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2564 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2565
2566 // Generate non-pic code that has direct accesses to the constant pool.
2567 // The address of the global is just (hi(&g)+lo(&g)).
2568 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2569}
2570
2571static void setUsesTOCBasePtr(MachineFunction &MF) {
2572 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2573 FuncInfo->setUsesTOCBasePtr();
2574}
2575
2576static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2577 setUsesTOCBasePtr(DAG.getMachineFunction());
2578}
2579
2580static SDValue getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, bool Is64Bit,
2581 SDValue GA) {
2582 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2583 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2584 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2585
2586 SDValue Ops[] = { GA, Reg };
2587 return DAG.getMemIntrinsicNode(
2588 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2589 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0,
2590 MachineMemOperand::MOLoad);
2591}
2592
2593SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2594 SelectionDAG &DAG) const {
2595 EVT PtrVT = Op.getValueType();
2596 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2597 const Constant *C = CP->getConstVal();
2598
2599 // 64-bit SVR4 ABI code is always position-independent.
2600 // The actual address of the GlobalValue is stored in the TOC.
2601 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2602 setUsesTOCBasePtr(DAG);
2603 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2604 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2605 }
2606
2607 unsigned MOHiFlag, MOLoFlag;
2608 bool IsPIC = isPositionIndependent();
2609 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2610
2611 if (IsPIC && Subtarget.isSVR4ABI()) {
2612 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2613 PPCII::MO_PIC_FLAG);
2614 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2615 }
2616
2617 SDValue CPIHi =
2618 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2619 SDValue CPILo =
2620 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2621 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
2622}
2623
2624// For 64-bit PowerPC, prefer the more compact relative encodings.
2625// This trades 32 bits per jump table entry for one or two instructions
2626// on the jump site.
2627unsigned PPCTargetLowering::getJumpTableEncoding() const {
2628 if (isJumpTableRelative())
2629 return MachineJumpTableInfo::EK_LabelDifference32;
2630
2631 return TargetLowering::getJumpTableEncoding();
2632}
2633
2634bool PPCTargetLowering::isJumpTableRelative() const {
2635 if (Subtarget.isPPC64())
2636 return true;
2637 return TargetLowering::isJumpTableRelative();
2638}
2639
2640SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2641 SelectionDAG &DAG) const {
2642 if (!Subtarget.isPPC64())
2643 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2644
2645 switch (getTargetMachine().getCodeModel()) {
2646 case CodeModel::Small:
2647 case CodeModel::Medium:
2648 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2649 default:
2650 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
2651 getPointerTy(DAG.getDataLayout()));
2652 }
2653}
2654
2655const MCExpr *
2656PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2657 unsigned JTI,
2658 MCContext &Ctx) const {
2659 if (!Subtarget.isPPC64())
2660 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2661
2662 switch (getTargetMachine().getCodeModel()) {
2663 case CodeModel::Small:
2664 case CodeModel::Medium:
2665 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2666 default:
2667 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2668 }
2669}
2670
2671SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2672 EVT PtrVT = Op.getValueType();
2673 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2674
2675 // 64-bit SVR4 ABI code is always position-independent.
2676 // The actual address of the GlobalValue is stored in the TOC.
2677 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2678 setUsesTOCBasePtr(DAG);
2679 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2680 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2681 }
2682
2683 unsigned MOHiFlag, MOLoFlag;
2684 bool IsPIC = isPositionIndependent();
2685 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2686
2687 if (IsPIC && Subtarget.isSVR4ABI()) {
2688 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2689 PPCII::MO_PIC_FLAG);
2690 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2691 }
2692
2693 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2694 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2695 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
2696}
2697
2698SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2699 SelectionDAG &DAG) const {
2700 EVT PtrVT = Op.getValueType();
2701 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2702 const BlockAddress *BA = BASDN->getBlockAddress();
2703
2704 // 64-bit SVR4 ABI code is always position-independent.
2705 // The actual BlockAddress is stored in the TOC.
2706 if (Subtarget.isSVR4ABI() &&
2707 (Subtarget.isPPC64() || isPositionIndependent())) {
2708 if (Subtarget.isPPC64())
2709 setUsesTOCBasePtr(DAG);
2710 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2711 return getTOCEntry(DAG, SDLoc(BASDN), Subtarget.isPPC64(), GA);
2712 }
2713
2714 unsigned MOHiFlag, MOLoFlag;
2715 bool IsPIC = isPositionIndependent();
2716 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2717 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2718 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2719 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
2720}
2721
2722SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2723 SelectionDAG &DAG) const {
2724 // FIXME: TLS addresses currently use medium model code sequences,
2725 // which is the most useful form. Eventually support for small and
2726 // large models could be added if users need it, at the cost of
2727 // additional complexity.
2728 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2729 if (DAG.getTarget().useEmulatedTLS())
2730 return LowerToTLSEmulatedModel(GA, DAG);
2731
2732 SDLoc dl(GA);
2733 const GlobalValue *GV = GA->getGlobal();
2734 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2735 bool is64bit = Subtarget.isPPC64();
2736 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2737 PICLevel::Level picLevel = M->getPICLevel();
2738
2739 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2740
2741 if (Model == TLSModel::LocalExec) {
2742 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2743 PPCII::MO_TPREL_HA);
2744 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2745 PPCII::MO_TPREL_LO);
2746 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
2747 : DAG.getRegister(PPC::R2, MVT::i32);
2748
2749 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2750 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2751 }
2752
2753 if (Model == TLSModel::InitialExec) {
2754 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2755 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2756 PPCII::MO_TLS);
2757 SDValue GOTPtr;
2758 if (is64bit) {
2759 setUsesTOCBasePtr(DAG);
2760 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2761 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2762 PtrVT, GOTReg, TGA);
2763 } else
2764 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2765 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2766 PtrVT, TGA, GOTPtr);
2767 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2768 }
2769
2770 if (Model == TLSModel::GeneralDynamic) {
2771 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2772 SDValue GOTPtr;
2773 if (is64bit) {
2774 setUsesTOCBasePtr(DAG);
2775 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2776 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2777 GOTReg, TGA);
2778 } else {
2779 if (picLevel == PICLevel::SmallPIC)
2780 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2781 else
2782 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2783 }
2784 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2785 GOTPtr, TGA, TGA);
2786 }
2787
2788 if (Model == TLSModel::LocalDynamic) {
2789 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2790 SDValue GOTPtr;
2791 if (is64bit) {
2792 setUsesTOCBasePtr(DAG);
2793 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2794 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2795 GOTReg, TGA);
2796 } else {
2797 if (picLevel == PICLevel::SmallPIC)
2798 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2799 else
2800 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2801 }
2802 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2803 PtrVT, GOTPtr, TGA, TGA);
2804 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2805 PtrVT, TLSAddr, TGA);
2806 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2807 }
2808
2809 llvm_unreachable("Unknown TLS model!")::llvm::llvm_unreachable_internal("Unknown TLS model!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2809)
;
2810}
2811
2812SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2813 SelectionDAG &DAG) const {
2814 EVT PtrVT = Op.getValueType();
2815 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2816 SDLoc DL(GSDN);
2817 const GlobalValue *GV = GSDN->getGlobal();
2818
2819 // 64-bit SVR4 ABI code is always position-independent.
2820 // The actual address of the GlobalValue is stored in the TOC.
2821 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2822 setUsesTOCBasePtr(DAG);
2823 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2824 return getTOCEntry(DAG, DL, true, GA);
2825 }
2826
2827 unsigned MOHiFlag, MOLoFlag;
2828 bool IsPIC = isPositionIndependent();
2829 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
2830
2831 if (IsPIC && Subtarget.isSVR4ABI()) {
2832 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2833 GSDN->getOffset(),
2834 PPCII::MO_PIC_FLAG);
2835 return getTOCEntry(DAG, DL, false, GA);
2836 }
2837
2838 SDValue GAHi =
2839 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2840 SDValue GALo =
2841 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2842
2843 SDValue Ptr = LowerLabelRef(GAHi, GALo, IsPIC, DAG);
2844
2845 // If the global reference is actually to a non-lazy-pointer, we have to do an
2846 // extra load to get the address of the global.
2847 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2848 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2849 return Ptr;
2850}
2851
2852SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2853 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2854 SDLoc dl(Op);
2855
2856 if (Op.getValueType() == MVT::v2i64) {
2857 // When the operands themselves are v2i64 values, we need to do something
2858 // special because VSX has no underlying comparison operations for these.
2859 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2860 // Equality can be handled by casting to the legal type for Altivec
2861 // comparisons, everything else needs to be expanded.
2862 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2863 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2864 DAG.getSetCC(dl, MVT::v4i32,
2865 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2866 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2867 CC));
2868 }
2869
2870 return SDValue();
2871 }
2872
2873 // We handle most of these in the usual way.
2874 return Op;
2875 }
2876
2877 // If we're comparing for equality to zero, expose the fact that this is
2878 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
2879 // fold the new nodes.
2880 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
2881 return V;
2882
2883 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2884 // Leave comparisons against 0 and -1 alone for now, since they're usually
2885 // optimized. FIXME: revisit this when we can custom lower all setcc
2886 // optimizations.
2887 if (C->isAllOnesValue() || C->isNullValue())
2888 return SDValue();
2889 }
2890
2891 // If we have an integer seteq/setne, turn it into a compare against zero
2892 // by xor'ing the rhs with the lhs, which is faster than setting a
2893 // condition register, reading it back out, and masking the correct bit. The
2894 // normal approach here uses sub to do this instead of xor. Using xor exposes
2895 // the result to other bit-twiddling opportunities.
2896 EVT LHSVT = Op.getOperand(0).getValueType();
2897 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2898 EVT VT = Op.getValueType();
2899 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2900 Op.getOperand(1));
2901 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2902 }
2903 return SDValue();
2904}
2905
2906SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2907 SDNode *Node = Op.getNode();
2908 EVT VT = Node->getValueType(0);
2909 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2910 SDValue InChain = Node->getOperand(0);
2911 SDValue VAListPtr = Node->getOperand(1);
2912 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2913 SDLoc dl(Node);
2914
2915 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")((!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")
? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVAARG is PPC32 only\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2915, __PRETTY_FUNCTION__))
;
2916
2917 // gpr_index
2918 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2919 VAListPtr, MachinePointerInfo(SV), MVT::i8);
2920 InChain = GprIndex.getValue(1);
2921
2922 if (VT == MVT::i64) {
2923 // Check if GprIndex is even
2924 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2925 DAG.getConstant(1, dl, MVT::i32));
2926 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2927 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2928 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2929 DAG.getConstant(1, dl, MVT::i32));
2930 // Align GprIndex to be even if it isn't
2931 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2932 GprIndex);
2933 }
2934
2935 // fpr index is 1 byte after gpr
2936 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2937 DAG.getConstant(1, dl, MVT::i32));
2938
2939 // fpr
2940 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2941 FprPtr, MachinePointerInfo(SV), MVT::i8);
2942 InChain = FprIndex.getValue(1);
2943
2944 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2945 DAG.getConstant(8, dl, MVT::i32));
2946
2947 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2948 DAG.getConstant(4, dl, MVT::i32));
2949
2950 // areas
2951 SDValue OverflowArea =
2952 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
2953 InChain = OverflowArea.getValue(1);
2954
2955 SDValue RegSaveArea =
2956 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
2957 InChain = RegSaveArea.getValue(1);
2958
2959 // select overflow_area if index > 8
2960 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2961 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2962
2963 // adjustment constant gpr_index * 4/8
2964 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2965 VT.isInteger() ? GprIndex : FprIndex,
2966 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2967 MVT::i32));
2968
2969 // OurReg = RegSaveArea + RegConstant
2970 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2971 RegConstant);
2972
2973 // Floating types are 32 bytes into RegSaveArea
2974 if (VT.isFloatingPoint())
2975 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2976 DAG.getConstant(32, dl, MVT::i32));
2977
2978 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2979 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2980 VT.isInteger() ? GprIndex : FprIndex,
2981 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2982 MVT::i32));
2983
2984 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2985 VT.isInteger() ? VAListPtr : FprPtr,
2986 MachinePointerInfo(SV), MVT::i8);
2987
2988 // determine if we should load from reg_save_area or overflow_area
2989 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2990
2991 // increase overflow_area by 4/8 if gpr/fpr > 8
2992 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2993 DAG.getConstant(VT.isInteger() ? 4 : 8,
2994 dl, MVT::i32));
2995
2996 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2997 OverflowAreaPlusN);
2998
2999 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
3000 MachinePointerInfo(), MVT::i32);
3001
3002 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
3003}
3004
3005SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3006 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only")((!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVACOPY is PPC32 only\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3006, __PRETTY_FUNCTION__))
;
3007
3008 // We have to copy the entire va_list struct:
3009 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3010 return DAG.getMemcpy(Op.getOperand(0), Op,
3011 Op.getOperand(1), Op.getOperand(2),
3012 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
3013 false, MachinePointerInfo(), MachinePointerInfo());
3014}
3015
3016SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3017 SelectionDAG &DAG) const {
3018 return Op.getOperand(0);
3019}
3020
3021SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3022 SelectionDAG &DAG) const {
3023 SDValue Chain = Op.getOperand(0);
3024 SDValue Trmp = Op.getOperand(1); // trampoline
3025 SDValue FPtr = Op.getOperand(2); // nested function
3026 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3027 SDLoc dl(Op);
3028
3029 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3030 bool isPPC64 = (PtrVT == MVT::i64);
3031 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3032
3033 TargetLowering::ArgListTy Args;
3034 TargetLowering::ArgListEntry Entry;
3035
3036 Entry.Ty = IntPtrTy;
3037 Entry.Node = Trmp; Args.push_back(Entry);
3038
3039 // TrampSize == (isPPC64 ? 48 : 40);
3040 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3041 isPPC64 ? MVT::i64 : MVT::i32);
3042 Args.push_back(Entry);
3043
3044 Entry.Node = FPtr; Args.push_back(Entry);
3045 Entry.Node = Nest; Args.push_back(Entry);
3046
3047 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3048 TargetLowering::CallLoweringInfo CLI(DAG);
3049 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3050 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3051 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3052
3053 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3054 return CallResult.second;
3055}
3056
3057SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3058 MachineFunction &MF = DAG.getMachineFunction();
3059 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3060 EVT PtrVT = getPointerTy(MF.getDataLayout());
3061
3062 SDLoc dl(Op);
3063
3064 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
3065 // vastart just stores the address of the VarArgsFrameIndex slot into the
3066 // memory location argument.
3067 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3068 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3069 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3070 MachinePointerInfo(SV));
3071 }
3072
3073 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3074 // We suppose the given va_list is already allocated.
3075 //
3076 // typedef struct {
3077 // char gpr; /* index into the array of 8 GPRs
3078 // * stored in the register save area
3079 // * gpr=0 corresponds to r3,
3080 // * gpr=1 to r4, etc.
3081 // */
3082 // char fpr; /* index into the array of 8 FPRs
3083 // * stored in the register save area
3084 // * fpr=0 corresponds to f1,
3085 // * fpr=1 to f2, etc.
3086 // */
3087 // char *overflow_arg_area;
3088 // /* location on stack that holds
3089 // * the next overflow argument
3090 // */
3091 // char *reg_save_area;
3092 // /* where r3:r10 and f1:f8 (if saved)
3093 // * are stored
3094 // */
3095 // } va_list[1];
3096
3097 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3098 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3099 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3100 PtrVT);
3101 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3102 PtrVT);
3103
3104 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3105 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3106
3107 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3108 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3109
3110 uint64_t FPROffset = 1;
3111 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3112
3113 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3114
3115 // Store first byte : number of int regs
3116 SDValue firstStore =
3117 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3118 MachinePointerInfo(SV), MVT::i8);
3119 uint64_t nextOffset = FPROffset;
3120 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3121 ConstFPROffset);
3122
3123 // Store second byte : number of float regs
3124 SDValue secondStore =
3125 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3126 MachinePointerInfo(SV, nextOffset), MVT::i8);
3127 nextOffset += StackOffset;
3128 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3129
3130 // Store second word : arguments given on stack
3131 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3132 MachinePointerInfo(SV, nextOffset));
3133 nextOffset += FrameOffset;
3134 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3135
3136 // Store third word : arguments given in registers
3137 return DAG.getStore(thirdStore, dl, FR, nextPtr,
3138 MachinePointerInfo(SV, nextOffset));
3139}
3140
3141#include "PPCGenCallingConv.inc"
3142
3143// Function whose sole purpose is to kill compiler warnings
3144// stemming from unused functions included from PPCGenCallingConv.inc.
3145CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
3146 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
3147}
3148
3149bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
3150 CCValAssign::LocInfo &LocInfo,
3151 ISD::ArgFlagsTy &ArgFlags,
3152 CCState &State) {
3153 return true;
3154}
3155
3156bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
3157 MVT &LocVT,
3158 CCValAssign::LocInfo &LocInfo,
3159 ISD::ArgFlagsTy &ArgFlags,
3160 CCState &State) {
3161 static const MCPhysReg ArgRegs[] = {
3162 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3163 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3164 };
3165 const unsigned NumArgRegs = array_lengthof(ArgRegs);
3166
3167 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3168
3169 // Skip one register if the first unallocated register has an even register
3170 // number and there are still argument registers available which have not been
3171 // allocated yet. RegNum is actually an index into ArgRegs, which means we
3172 // need to skip a register if RegNum is odd.
3173 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
3174 State.AllocateReg(ArgRegs[RegNum]);
3175 }
3176
3177 // Always return false here, as this function only makes sure that the first
3178 // unallocated register has an odd register number and does not actually
3179 // allocate a register for the current argument.
3180 return false;
3181}
3182
3183bool
3184llvm::CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(unsigned &ValNo, MVT &ValVT,
3185 MVT &LocVT,
3186 CCValAssign::LocInfo &LocInfo,
3187 ISD::ArgFlagsTy &ArgFlags,
3188 CCState &State) {
3189 static const MCPhysReg ArgRegs[] = {
3190 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3191 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3192 };
3193 const unsigned NumArgRegs = array_lengthof(ArgRegs);
3194
3195 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3196 int RegsLeft = NumArgRegs - RegNum;
3197
3198 // Skip if there is not enough registers left for long double type (4 gpr regs
3199 // in soft float mode) and put long double argument on the stack.
3200 if (RegNum != NumArgRegs && RegsLeft < 4) {
3201 for (int i = 0; i < RegsLeft; i++) {
3202 State.AllocateReg(ArgRegs[RegNum + i]);
3203 }
3204 }
3205
3206 return false;
3207}
3208
3209bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
3210 MVT &LocVT,
3211 CCValAssign::LocInfo &LocInfo,
3212 ISD::ArgFlagsTy &ArgFlags,
3213 CCState &State) {
3214 static const MCPhysReg ArgRegs[] = {
3215 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3216 PPC::F8
3217 };
3218
3219 const unsigned NumArgRegs = array_lengthof(ArgRegs);
3220
3221 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
3222
3223 // If there is only one Floating-point register left we need to put both f64
3224 // values of a split ppc_fp128 value on the stack.
3225 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
3226 State.AllocateReg(ArgRegs[RegNum]);
3227 }
3228
3229 // Always return false here, as this function only makes sure that the two f64
3230 // values a ppc_fp128 value is split into are both passed in registers or both
3231 // passed on the stack and does not actually allocate a register for the
3232 // current argument.
3233 return false;
3234}
3235
3236/// FPR - The set of FP registers that should be allocated for arguments,
3237/// on Darwin.
3238static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3239 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3240 PPC::F11, PPC::F12, PPC::F13};
3241
3242/// QFPR - The set of QPX registers that should be allocated for arguments.
3243static const MCPhysReg QFPR[] = {
3244 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
3245 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
3246
3247/// CalculateStackSlotSize - Calculates the size reserved for this argument on
3248/// the stack.
3249static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3250 unsigned PtrByteSize) {
3251 unsigned ArgSize = ArgVT.getStoreSize();
3252 if (Flags.isByVal())
3253 ArgSize = Flags.getByValSize();
3254
3255 // Round up to multiples of the pointer size, except for array members,
3256 // which are always packed.
3257 if (!Flags.isInConsecutiveRegs())
3258 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3259
3260 return ArgSize;
3261}
3262
3263/// CalculateStackSlotAlignment - Calculates the alignment of this argument
3264/// on the stack.
3265static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3266 ISD::ArgFlagsTy Flags,
3267 unsigned PtrByteSize) {
3268 unsigned Align = PtrByteSize;
3269
3270 // Altivec parameters are padded to a 16 byte boundary.
3271 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3272 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3273 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3274 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3275 Align = 16;
3276 // QPX vector types stored in double-precision are padded to a 32 byte
3277 // boundary.
3278 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
3279 Align = 32;
3280
3281 // ByVal parameters are aligned as requested.
3282 if (Flags.isByVal()) {
3283 unsigned BVAlign = Flags.getByValAlign();
3284 if (BVAlign > PtrByteSize) {
3285 if (BVAlign % PtrByteSize != 0)
3286 llvm_unreachable(::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3287)
3287 "ByVal alignment is not a multiple of the pointer size")::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3287)
;
3288
3289 Align = BVAlign;
3290 }
3291 }
3292
3293 // Array members are always packed to their original alignment.
3294 if (Flags.isInConsecutiveRegs()) {
3295 // If the array member was split into multiple registers, the first
3296 // needs to be aligned to the size of the full type. (Except for
3297 // ppcf128, which is only aligned as its f64 components.)
3298 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3299 Align = OrigVT.getStoreSize();
3300 else
3301 Align = ArgVT.getStoreSize();
3302 }
3303
3304 return Align;
3305}
3306
3307/// CalculateStackSlotUsed - Return whether this argument will use its
3308/// stack slot (instead of being passed in registers). ArgOffset,
3309/// AvailableFPRs, and AvailableVRs must hold the current argument
3310/// position, and will be updated to account for this argument.
3311static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
3312 ISD::ArgFlagsTy Flags,
3313 unsigned PtrByteSize,
3314 unsigned LinkageSize,
3315 unsigned ParamAreaSize,
3316 unsigned &ArgOffset,
3317 unsigned &AvailableFPRs,
3318 unsigned &AvailableVRs, bool HasQPX) {
3319 bool UseMemory = false;
3320
3321 // Respect alignment of argument on the stack.
3322 unsigned Align =
3323 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3324 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3325 // If there's no space left in the argument save area, we must
3326 // use memory (this check also catches zero-sized arguments).
3327 if (ArgOffset >= LinkageSize + ParamAreaSize)
3328 UseMemory = true;
3329
3330 // Allocate argument on the stack.
3331 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3332 if (Flags.isInConsecutiveRegsLast())
3333 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3334 // If we overran the argument save area, we must use memory
3335 // (this check catches arguments passed partially in memory)
3336 if (ArgOffset > LinkageSize + ParamAreaSize)
3337 UseMemory = true;
3338
3339 // However, if the argument is actually passed in an FPR or a VR,
3340 // we don't use memory after all.
3341 if (!Flags.isByVal()) {
3342 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
3343 // QPX registers overlap with the scalar FP registers.
3344 (HasQPX && (ArgVT == MVT::v4f32 ||
3345 ArgVT == MVT::v4f64 ||
3346 ArgVT == MVT::v4i1)))
3347 if (AvailableFPRs > 0) {
3348 --AvailableFPRs;
3349 return false;
3350 }
3351 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3352 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3353 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3354 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3355 if (AvailableVRs > 0) {
3356 --AvailableVRs;
3357 return false;
3358 }
3359 }
3360
3361 return UseMemory;
3362}
3363
3364/// EnsureStackAlignment - Round stack frame size up from NumBytes to
3365/// ensure minimum alignment required for target.
3366static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3367 unsigned NumBytes) {
3368 unsigned TargetAlign = Lowering->getStackAlignment();
3369 unsigned AlignMask = TargetAlign - 1;
3370 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3371 return NumBytes;
3372}
3373
3374SDValue PPCTargetLowering::LowerFormalArguments(
3375 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3376 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3377 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3378 if (Subtarget.isSVR4ABI()) {
3379 if (Subtarget.isPPC64())
3380 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
3381 dl, DAG, InVals);
3382 else
3383 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
3384 dl, DAG, InVals);
3385 } else {
3386 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
3387 dl, DAG, InVals);
3388 }
3389}
3390
3391SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3392 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3393 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3394 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3395
3396 // 32-bit SVR4 ABI Stack Frame Layout:
3397 // +-----------------------------------+
3398 // +--> | Back chain |
3399 // | +-----------------------------------+
3400 // | | Floating-point register save area |
3401 // | +-----------------------------------+
3402 // | | General register save area |
3403 // | +-----------------------------------+
3404 // | | CR save word |
3405 // | +-----------------------------------+
3406 // | | VRSAVE save word |
3407 // | +-----------------------------------+
3408 // | | Alignment padding |
3409 // | +-----------------------------------+
3410 // | | Vector register save area |
3411 // | +-----------------------------------+
3412 // | | Local variable space |
3413 // | +-----------------------------------+
3414 // | | Parameter list area |
3415 // | +-----------------------------------+
3416 // | | LR save word |
3417 // | +-----------------------------------+
3418 // SP--> +--- | Back chain |
3419 // +-----------------------------------+
3420 //
3421 // Specifications:
3422 // System V Application Binary Interface PowerPC Processor Supplement
3423 // AltiVec Technology Programming Interface Manual
3424
3425 MachineFunction &MF = DAG.getMachineFunction();
3426 MachineFrameInfo &MFI = MF.getFrameInfo();
3427 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3428
3429 EVT PtrVT = getPointerTy(MF.getDataLayout());
3430 // Potential tail calls could cause overwriting of argument stack slots.
3431 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3432 (CallConv == CallingConv::Fast));
3433 unsigned PtrByteSize = 4;
3434
3435 // Assign locations to all of the incoming arguments.
3436 SmallVector<CCValAssign, 16> ArgLocs;
3437 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3438 *DAG.getContext());
3439
3440 // Reserve space for the linkage area on the stack.
3441 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3442 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
3443 if (useSoftFloat() || hasSPE())
3444 CCInfo.PreAnalyzeFormalArguments(Ins);
3445
3446 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3447 CCInfo.clearWasPPCF128();
3448
3449 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3450 CCValAssign &VA = ArgLocs[i];
3451
3452 // Arguments stored in registers.
3453 if (VA.isRegLoc()) {
3454 const TargetRegisterClass *RC;
3455 EVT ValVT = VA.getValVT();
3456
3457 switch (ValVT.getSimpleVT().SimpleTy) {
3458 default:
3459 llvm_unreachable("ValVT not supported by formal arguments Lowering")::llvm::llvm_unreachable_internal("ValVT not supported by formal arguments Lowering"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3459)
;
3460 case MVT::i1:
3461 case MVT::i32:
3462 RC = &PPC::GPRCRegClass;
3463 break;
3464 case MVT::f32:
3465 if (Subtarget.hasP8Vector())
3466 RC = &PPC::VSSRCRegClass;
3467 else if (Subtarget.hasSPE())
3468 RC = &PPC::SPE4RCRegClass;
3469 else
3470 RC = &PPC::F4RCRegClass;
3471 break;
3472 case MVT::f64:
3473 if (Subtarget.hasVSX())
3474 RC = &PPC::VSFRCRegClass;
3475 else if (Subtarget.hasSPE())
3476 RC = &PPC::SPERCRegClass;
3477 else
3478 RC = &PPC::F8RCRegClass;
3479 break;
3480 case MVT::v16i8:
3481 case MVT::v8i16:
3482 case MVT::v4i32:
3483 RC = &PPC::VRRCRegClass;
3484 break;
3485 case MVT::v4f32:
3486 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
3487 break;
3488 case MVT::v2f64:
3489 case MVT::v2i64:
3490 RC = &PPC::VRRCRegClass;
3491 break;
3492 case MVT::v4f64:
3493 RC = &PPC::QFRCRegClass;
3494 break;
3495 case MVT::v4i1:
3496 RC = &PPC::QBRCRegClass;
3497 break;
3498 }
3499
3500 // Transform the arguments stored in physical registers into virtual ones.
3501 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3502 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3503 ValVT == MVT::i1 ? MVT::i32 : ValVT);
3504
3505 if (ValVT == MVT::i1)
3506 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3507
3508 InVals.push_back(ArgValue);
3509 } else {
3510 // Argument stored in memory.
3511 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3511, __PRETTY_FUNCTION__))
;
3512
3513 // Get the extended size of the argument type in stack
3514 unsigned ArgSize = VA.getLocVT().getStoreSize();
3515 // Get the actual size of the argument type
3516 unsigned ObjSize = VA.getValVT().getStoreSize();
3517 unsigned ArgOffset = VA.getLocMemOffset();
3518 // Stack objects in PPC32 are right justified.
3519 ArgOffset += ArgSize - ObjSize;
3520 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
3521
3522 // Create load nodes to retrieve arguments from the stack.
3523 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3524 InVals.push_back(
3525 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3526 }
3527 }
3528
3529 // Assign locations to all of the incoming aggregate by value arguments.
3530 // Aggregates passed by value are stored in the local variable space of the
3531 // caller's stack frame, right above the parameter list area.
3532 SmallVector<CCValAssign, 16> ByValArgLocs;
3533 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3534 ByValArgLocs, *DAG.getContext());
3535
3536 // Reserve stack space for the allocations in CCInfo.
3537 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3538
3539 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3540
3541 // Area that is at least reserved in the caller of this function.
3542 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3543 MinReservedArea = std::max(MinReservedArea, LinkageSize);
3544
3545 // Set the size that is at least reserved in caller of this function. Tail
3546 // call optimized function's reserved stack space needs to be aligned so that
3547 // taking the difference between two stack areas will result in an aligned
3548 // stack.
3549 MinReservedArea =
3550 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3551 FuncInfo->setMinReservedArea(MinReservedArea);
3552
3553 SmallVector<SDValue, 8> MemOps;
3554
3555 // If the function takes variable number of arguments, make a frame index for
3556 // the start of the first vararg value... for expansion of llvm.va_start.
3557 if (isVarArg) {
3558 static const MCPhysReg GPArgRegs[] = {
3559 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3560 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3561 };
3562 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3563
3564 static const MCPhysReg FPArgRegs[] = {
3565 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3566 PPC::F8
3567 };
3568 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3569
3570 if (useSoftFloat() || hasSPE())
3571 NumFPArgRegs = 0;
3572
3573 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3574 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3575
3576 // Make room for NumGPArgRegs and NumFPArgRegs.
3577 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3578 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3579
3580 FuncInfo->setVarArgsStackOffset(
3581 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3582 CCInfo.getNextStackOffset(), true));
3583
3584 FuncInfo->setVarArgsFrameIndex(MFI.CreateStackObject(Depth, 8, false));
3585 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3586
3587 // The fixed integer arguments of a variadic function are stored to the
3588 // VarArgsFrameIndex on the stack so that they may be loaded by
3589 // dereferencing the result of va_next.
3590 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
3591 // Get an existing live-in vreg, or add a new one.
3592 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
3593 if (!VReg)
3594 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3595
3596 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3597 SDValue Store =
3598 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3599 MemOps.push_back(Store);
3600 // Increment the address by four for the next argument to store
3601 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3602 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3603 }
3604
3605 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
3606 // is set.
3607 // The double arguments are stored to the VarArgsFrameIndex
3608 // on the stack.
3609 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
3610 // Get an existing live-in vreg, or add a new one.
3611 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
3612 if (!VReg)
3613 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3614
3615 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
3616 SDValue Store =
3617 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3618 MemOps.push_back(Store);
3619 // Increment the address by eight for the next argument to store
3620 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3621 PtrVT);
3622 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3623 }
3624 }
3625
3626 if (!MemOps.empty())
3627 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3628
3629 return Chain;
3630}
3631
3632// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3633// value to MVT::i64 and then truncate to the correct register size.
3634SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
3635 EVT ObjectVT, SelectionDAG &DAG,
3636 SDValue ArgVal,
3637 const SDLoc &dl) const {
3638 if (Flags.isSExt())
3639 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3640 DAG.getValueType(ObjectVT));
3641 else if (Flags.isZExt())
3642 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3643 DAG.getValueType(ObjectVT));
3644
3645 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3646}
3647
3648SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3649 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3650 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3651 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3652 // TODO: add description of PPC stack frame format, or at least some docs.
3653 //
3654 bool isELFv2ABI = Subtarget.isELFv2ABI();
3655 bool isLittleEndian = Subtarget.isLittleEndian();
3656 MachineFunction &MF = DAG.getMachineFunction();
3657 MachineFrameInfo &MFI = MF.getFrameInfo();
3658 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3659
3660 assert(!(CallConv == CallingConv::Fast && isVarArg) &&((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3661, __PRETTY_FUNCTION__))
3661 "fastcc not supported on varargs functions")((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3661, __PRETTY_FUNCTION__))
;
3662
3663 EVT PtrVT = getPointerTy(MF.getDataLayout());
3664 // Potential tail calls could cause overwriting of argument stack slots.
3665 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3666 (CallConv == CallingConv::Fast));
3667 unsigned PtrByteSize = 8;
3668 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3669
3670 static const MCPhysReg GPR[] = {
3671 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3672 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3673 };
3674 static const MCPhysReg VR[] = {
3675 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3676 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3677 };
3678
3679 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3680 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3681 const unsigned Num_VR_Regs = array_lengthof(VR);
3682 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3683
3684 // Do a first pass over the arguments to determine whether the ABI
3685 // guarantees that our caller has allocated the parameter save area
3686 // on its stack frame. In the ELFv1 ABI, this is always the case;
3687 // in the ELFv2 ABI, it is true if this is a vararg function or if
3688 // any parameter is located in a stack slot.
3689
3690 bool HasParameterArea = !isELFv2ABI || isVarArg;
3691 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3692 unsigned NumBytes = LinkageSize;
3693 unsigned AvailableFPRs = Num_FPR_Regs;
3694 unsigned AvailableVRs = Num_VR_Regs;
3695 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3696 if (Ins[i].Flags.isNest())
3697 continue;
3698
3699 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3700 PtrByteSize, LinkageSize, ParamAreaSize,
3701 NumBytes, AvailableFPRs, AvailableVRs,
3702 Subtarget.hasQPX()))
3703 HasParameterArea = true;
3704 }
3705
3706 // Add DAG nodes to load the arguments or copy them out of registers. On
3707 // entry to a function on PPC, the arguments start after the linkage area,
3708 // although the first ones are often in registers.
3709
3710 unsigned ArgOffset = LinkageSize;
3711 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3712 unsigned &QFPR_idx = FPR_idx;
3713 SmallVector<SDValue, 8> MemOps;
3714 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
3715 unsigned CurArgIdx = 0;
3716 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3717 SDValue ArgVal;
3718 bool needsLoad = false;
3719 EVT ObjectVT = Ins[ArgNo].VT;
3720 EVT OrigVT = Ins[ArgNo].ArgVT;
3721 unsigned ObjSize = ObjectVT.getStoreSize();
3722 unsigned ArgSize = ObjSize;
3723 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3724 if (Ins[ArgNo].isOrigArg()) {
3725 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3726 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3727 }
3728 // We re-align the argument offset for each argument, except when using the
3729 // fast calling convention, when we need to make sure we do that only when
3730 // we'll actually use a stack slot.
3731 unsigned CurArgOffset, Align;
3732 auto ComputeArgOffset = [&]() {
3733 /* Respect alignment of argument on the stack. */
3734 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3735 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3736 CurArgOffset = ArgOffset;
3737 };
3738
3739 if (CallConv != CallingConv::Fast) {
3740 ComputeArgOffset();
3741
3742 /* Compute GPR index associated with argument offset. */
3743 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3744 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3745 }
3746
3747 // FIXME the codegen can be much improved in some cases.
3748 // We do not have to keep everything in memory.
3749 if (Flags.isByVal()) {
3750 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3750, __PRETTY_FUNCTION__))
;
3751
3752 if (CallConv == CallingConv::Fast)
3753 ComputeArgOffset();
3754
3755 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3756 ObjSize = Flags.getByValSize();
3757 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3758 // Empty aggregate parameters do not take up registers. Examples:
3759 // struct { } a;
3760 // union { } b;
3761 // int c[0];
3762 // etc. However, we have to provide a place-holder in InVals, so
3763 // pretend we have an 8-byte item at the current address for that
3764 // purpose.
3765 if (!ObjSize) {
3766 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
3767 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3768 InVals.push_back(FIN);
3769 continue;
3770 }
3771
3772 // Create a stack object covering all stack doublewords occupied
3773 // by the argument. If the argument is (fully or partially) on
3774 // the stack, or if the argument is fully in registers but the
3775 // caller has allocated the parameter save anyway, we can refer
3776 // directly to the caller's stack frame. Otherwise, create a
3777 // local copy in our own frame.
3778 int FI;
3779 if (HasParameterArea ||
3780 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3781 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
3782 else
3783 FI = MFI.CreateStackObject(ArgSize, Align, false);
3784 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3785
3786 // Handle aggregates smaller than 8 bytes.
3787 if (ObjSize < PtrByteSize) {
3788 // The value of the object is its address, which differs from the
3789 // address of the enclosing doubleword on big-endian systems.
3790 SDValue Arg = FIN;
3791 if (!isLittleEndian) {
3792 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3793 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3794 }
3795 InVals.push_back(Arg);
3796
3797 if (GPR_idx != Num_GPR_Regs) {
3798 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3799 FuncInfo->addLiveInAttr(VReg, Flags);
3800 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3801 SDValue Store;
3802
3803 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3804 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3805 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3806 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3807 MachinePointerInfo(&*FuncArg), ObjType);
3808 } else {
3809 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3810 // store the whole register as-is to the parameter save area
3811 // slot.
3812 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3813 MachinePointerInfo(&*FuncArg));
3814 }
3815
3816 MemOps.push_back(Store);
3817 }
3818 // Whether we copied from a register or not, advance the offset
3819 // into the parameter save area by a full doubleword.
3820 ArgOffset += PtrByteSize;
3821 continue;
3822 }
3823
3824 // The value of the object is its address, which is the address of
3825 // its first stack doubleword.
3826 InVals.push_back(FIN);
3827
3828 // Store whatever pieces of the object are in registers to memory.
3829 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3830 if (GPR_idx == Num_GPR_Regs)
3831 break;
3832
3833 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3834 FuncInfo->addLiveInAttr(VReg, Flags);
3835 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3836 SDValue Addr = FIN;
3837 if (j) {
3838 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3839 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3840 }
3841 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3842 MachinePointerInfo(&*FuncArg, j));
3843 MemOps.push_back(Store);
3844 ++GPR_idx;
3845 }
3846 ArgOffset += ArgSize;
3847 continue;
3848 }
3849
3850 switch (ObjectVT.getSimpleVT().SimpleTy) {
3851 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3851)
;
3852 case MVT::i1:
3853 case MVT::i32:
3854 case MVT::i64:
3855 if (Flags.isNest()) {
3856 // The 'nest' parameter, if any, is passed in R11.
3857 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3858 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3859
3860 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3861 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3862
3863 break;
3864 }
3865
3866 // These can be scalar arguments or elements of an integer array type
3867 // passed directly. Clang may use those instead of "byval" aggregate
3868 // types to avoid forcing arguments to memory unnecessarily.
3869 if (GPR_idx != Num_GPR_Regs) {
3870 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3871 FuncInfo->addLiveInAttr(VReg, Flags);
3872 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3873
3874 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3875 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3876 // value to MVT::i64 and then truncate to the correct register size.
3877 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3878 } else {
3879 if (CallConv == CallingConv::Fast)
3880 ComputeArgOffset();
3881
3882 needsLoad = true;
3883 ArgSize = PtrByteSize;
3884 }
3885 if (CallConv != CallingConv::Fast || needsLoad)
3886 ArgOffset += 8;
3887 break;
3888
3889 case MVT::f32:
3890 case MVT::f64:
3891 // These can be scalar arguments or elements of a float array type
3892 // passed directly. The latter are used to implement ELFv2 homogenous
3893 // float aggregates.
3894 if (FPR_idx != Num_FPR_Regs) {
3895 unsigned VReg;
3896
3897 if (ObjectVT == MVT::f32)
3898 VReg = MF.addLiveIn(FPR[FPR_idx],
3899 Subtarget.hasP8Vector()
3900 ? &PPC::VSSRCRegClass
3901 : &PPC::F4RCRegClass);
3902 else
3903 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3904 ? &PPC::VSFRCRegClass
3905 : &PPC::F8RCRegClass);
3906
3907 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3908 ++FPR_idx;
3909 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3910 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3911 // once we support fp <-> gpr moves.
3912
3913 // This can only ever happen in the presence of f32 array types,
3914 // since otherwise we never run out of FPRs before running out
3915 // of GPRs.
3916 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3917 FuncInfo->addLiveInAttr(VReg, Flags);
3918 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3919
3920 if (ObjectVT == MVT::f32) {
3921 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3922 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3923 DAG.getConstant(32, dl, MVT::i32));
3924 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3925 }
3926
3927 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3928 } else {
3929 if (CallConv == CallingConv::Fast)
3930 ComputeArgOffset();
3931
3932 needsLoad = true;
3933 }
3934
3935 // When passing an array of floats, the array occupies consecutive
3936 // space in the argument area; only round up to the next doubleword
3937 // at the end of the array. Otherwise, each float takes 8 bytes.
3938 if (CallConv != CallingConv::Fast || needsLoad) {
3939 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3940 ArgOffset += ArgSize;
3941 if (Flags.isInConsecutiveRegsLast())
3942 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3943 }
3944 break;
3945 case MVT::v4f32:
3946 case MVT::v4i32:
3947 case MVT::v8i16:
3948 case MVT::v16i8:
3949 case MVT::v2f64:
3950 case MVT::v2i64:
3951 case MVT::v1i128:
3952 case MVT::f128:
3953 if (!Subtarget.hasQPX()) {
3954 // These can be scalar arguments or elements of a vector array type
3955 // passed directly. The latter are used to implement ELFv2 homogenous
3956 // vector aggregates.
3957 if (VR_idx != Num_VR_Regs) {
3958 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3959 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3960 ++VR_idx;
3961 } else {
3962 if (CallConv == CallingConv::Fast)
3963 ComputeArgOffset();
3964 needsLoad = true;
3965 }
3966 if (CallConv != CallingConv::Fast || needsLoad)
3967 ArgOffset += 16;
3968 break;
3969 } // not QPX
3970
3971 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&((ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && "Invalid QPX parameter type"
) ? static_cast<void> (0) : __assert_fail ("ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && \"Invalid QPX parameter type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3972, __PRETTY_FUNCTION__))
3972 "Invalid QPX parameter type")((ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && "Invalid QPX parameter type"
) ? static_cast<void> (0) : __assert_fail ("ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && \"Invalid QPX parameter type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3972, __PRETTY_FUNCTION__))
;
3973 /* fall through */
3974
3975 case MVT::v4f64:
3976 case MVT::v4i1:
3977 // QPX vectors are treated like their scalar floating-point subregisters
3978 // (except that they're larger).
3979 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3980 if (QFPR_idx != Num_QFPR_Regs) {
3981 const TargetRegisterClass *RC;
3982 switch (ObjectVT.getSimpleVT().SimpleTy) {
3983 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3984 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3985 default: RC = &PPC::QBRCRegClass; break;
3986 }
3987
3988 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3989 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3990 ++QFPR_idx;
3991 } else {
3992 if (CallConv == CallingConv::Fast)
3993 ComputeArgOffset();
3994 needsLoad = true;
3995 }
3996 if (CallConv != CallingConv::Fast || needsLoad)
3997 ArgOffset += Sz;
3998 break;
3999 }
4000
4001 // We need to load the argument to a virtual register if we determined
4002 // above that we ran out of physical registers of the appropriate type.
4003 if (needsLoad) {
4004 if (ObjSize < ArgSize && !isLittleEndian)
4005 CurArgOffset += ArgSize - ObjSize;
4006 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
4007 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4008 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4009 }
4010
4011 InVals.push_back(ArgVal);
4012 }
4013
4014 // Area that is at least reserved in the caller of this function.
4015 unsigned MinReservedArea;
4016 if (HasParameterArea)
4017 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
4018 else
4019 MinReservedArea = LinkageSize;
4020
4021 // Set the size that is at least reserved in caller of this function. Tail
4022 // call optimized functions' reserved stack space needs to be aligned so that
4023 // taking the difference between two stack areas will result in an aligned
4024 // stack.
4025 MinReservedArea =
4026 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4027 FuncInfo->setMinReservedArea(MinReservedArea);
4028
4029 // If the function takes variable number of arguments, make a frame index for
4030 // the start of the first vararg value... for expansion of llvm.va_start.
4031 if (isVarArg) {
4032 int Depth = ArgOffset;
4033
4034 FuncInfo->setVarArgsFrameIndex(
4035 MFI.CreateFixedObject(PtrByteSize, Depth, true));
4036 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4037
4038 // If this function is vararg, store any remaining integer argument regs
4039 // to their spots on the stack so that they may be loaded by dereferencing
4040 // the result of va_next.
4041 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4042 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4043 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4044 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4045 SDValue Store =
4046 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4047 MemOps.push_back(Store);
4048 // Increment the address by four for the next argument to store
4049 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4050 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4051 }
4052 }
4053
4054 if (!MemOps.empty())
4055 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4056
4057 return Chain;
4058}
4059
4060SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
4061 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4062 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4063 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4064 // TODO: add description of PPC stack frame format, or at least some docs.
4065 //
4066 MachineFunction &MF = DAG.getMachineFunction();
4067 MachineFrameInfo &MFI = MF.getFrameInfo();
4068 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4069
4070 EVT PtrVT = getPointerTy(MF.getDataLayout());
4071 bool isPPC64 = PtrVT == MVT::i64;
4072 // Potential tail calls could cause overwriting of argument stack slots.
4073 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4074 (CallConv == CallingConv::Fast));
4075 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4076 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4077 unsigned ArgOffset = LinkageSize;
4078 // Area that is at least reserved in caller of this function.
4079 unsigned MinReservedArea = ArgOffset;
4080
4081 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4082 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4083 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4084 };
4085 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4086 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4087 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4088 };
4089 static const MCPhysReg VR[] = {
4090 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4091 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4092 };
4093
4094 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
4095 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4096 const unsigned Num_VR_Regs = array_lengthof( VR);
4097
4098 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4099
4100 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4101
4102 // In 32-bit non-varargs functions, the stack space for vectors is after the
4103 // stack space for non-vectors. We do not use this space unless we have
4104 // too many vectors to fit in registers, something that only occurs in
4105 // constructed examples:), but we have to walk the arglist to figure
4106 // that out...for the pathological case, compute VecArgOffset as the
4107 // start of the vector parameter area. Computing VecArgOffset is the
4108 // entire point of the following loop.
4109 unsigned VecArgOffset = ArgOffset;
4110 if (!isVarArg && !isPPC64) {
4111 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
4112 ++ArgNo) {
4113 EVT ObjectVT = Ins[ArgNo].VT;
4114 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4115
4116 if (Flags.isByVal()) {
4117 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
4118 unsigned ObjSize = Flags.getByValSize();
4119 unsigned ArgSize =
4120 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4121 VecArgOffset += ArgSize;
4122 continue;
4123 }
4124
4125 switch(ObjectVT.getSimpleVT().SimpleTy) {
4126 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4126)
;
4127 case MVT::i1:
4128 case MVT::i32:
4129 case MVT::f32:
4130 VecArgOffset += 4;
4131 break;
4132 case MVT::i64: // PPC64
4133 case MVT::f64:
4134 // FIXME: We are guaranteed to be !isPPC64 at this point.
4135 // Does MVT::i64 apply?
4136 VecArgOffset += 8;
4137 break;
4138 case MVT::v4f32:
4139 case MVT::v4i32:
4140 case MVT::v8i16:
4141 case MVT::v16i8:
4142 // Nothing to do, we're only looking at Nonvector args here.
4143 break;
4144 }
4145 }
4146 }
4147 // We've found where the vector parameter area in memory is. Skip the
4148 // first 12 parameters; these don't use that memory.
4149 VecArgOffset = ((VecArgOffset+15)/16)*16;
4150 VecArgOffset += 12*16;
4151
4152 // Add DAG nodes to load the arguments or copy them out of registers. On
4153 // entry to a function on PPC, the arguments start after the linkage area,
4154 // although the first ones are often in registers.
4155
4156 SmallVector<SDValue, 8> MemOps;
4157 unsigned nAltivecParamsAtEnd = 0;
4158 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4159 unsigned CurArgIdx = 0;
4160 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4161 SDValue ArgVal;
4162 bool needsLoad = false;
4163 EVT ObjectVT = Ins[ArgNo].VT;
4164 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
4165 unsigned ArgSize = ObjSize;
4166 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4167 if (Ins[ArgNo].isOrigArg()) {
4168 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4169 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4170 }
4171 unsigned CurArgOffset = ArgOffset;
4172
4173 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
4174 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
4175 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
4176 if (isVarArg || isPPC64) {
4177 MinReservedArea = ((MinReservedArea+15)/16)*16;
4178 MinReservedArea += CalculateStackSlotSize(ObjectVT,
4179 Flags,
4180 PtrByteSize);
4181 } else nAltivecParamsAtEnd++;
4182 } else
4183 // Calculate min reserved area.
4184 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
4185 Flags,
4186 PtrByteSize);
4187
4188 // FIXME the codegen can be much improved in some cases.
4189 // We do not have to keep everything in memory.
4190 if (Flags.isByVal()) {
4191 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4191, __PRETTY_FUNCTION__))
;
4192
4193 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4194 ObjSize = Flags.getByValSize();
4195 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4196 // Objects of size 1 and 2 are right justified, everything else is
4197 // left justified. This means the memory address is adjusted forwards.
4198 if (ObjSize==1 || ObjSize==2) {
4199 CurArgOffset = CurArgOffset + (4 - ObjSize);
4200 }
4201 // The value of the object is its address.
4202 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, false, true);
4203 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4204 InVals.push_back(FIN);
4205 if (ObjSize==1 || ObjSize==2) {
4206 if (GPR_idx != Num_GPR_Regs) {
4207 unsigned VReg;
4208 if (isPPC64)
4209 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4210 else
4211 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4212 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4213 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
4214 SDValue Store =
4215 DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
4216 MachinePointerInfo(&*FuncArg), ObjType);
4217 MemOps.push_back(Store);
4218 ++GPR_idx;
4219 }
4220
4221 ArgOffset += PtrByteSize;
4222
4223 continue;
4224 }
4225 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4226 // Store whatever pieces of the object are in registers
4227 // to memory. ArgOffset will be the address of the beginning
4228 // of the object.
4229 if (GPR_idx != Num_GPR_Regs) {
4230 unsigned VReg;
4231 if (isPPC64)
4232 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4233 else
4234 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4235 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4236 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4237 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4238 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4239 MachinePointerInfo(&*FuncArg, j));
4240 MemOps.push_back(Store);
4241 ++GPR_idx;
4242 ArgOffset += PtrByteSize;
4243 } else {
4244 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
4245 break;
4246 }
4247 }
4248 continue;
4249 }
4250
4251 switch (ObjectVT.getSimpleVT().SimpleTy) {
4252 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4252)
;
4253 case MVT::i1:
4254 case MVT::i32:
4255 if (!isPPC64) {
4256 if (GPR_idx != Num_GPR_Regs) {
4257 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4258 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4259
4260 if (ObjectVT == MVT::i1)
4261 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
4262
4263 ++GPR_idx;
4264 } else {
4265 needsLoad = true;
4266 ArgSize = PtrByteSize;
4267 }
4268 // All int arguments reserve stack space in the Darwin ABI.
4269 ArgOffset += PtrByteSize;
4270 break;
4271 }
4272 LLVM_FALLTHROUGH[[clang::fallthrough]];
4273 case MVT::i64: // PPC64
4274 if (GPR_idx != Num_GPR_Regs) {
4275 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4276 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4277
4278 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4279 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4280 // value to MVT::i64 and then truncate to the correct register size.
4281 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4282
4283 ++GPR_idx;
4284 } else {
4285 needsLoad = true;
4286 ArgSize = PtrByteSize;
4287 }
4288 // All int arguments reserve stack space in the Darwin ABI.
4289 ArgOffset += 8;
4290 break;
4291
4292 case MVT::f32:
4293 case MVT::f64:
4294 // Every 4 bytes of argument space consumes one of the GPRs available for
4295 // argument passing.
4296 if (GPR_idx != Num_GPR_Regs) {
4297 ++GPR_idx;
4298 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
4299 ++GPR_idx;
4300 }
4301 if (FPR_idx != Num_FPR_Regs) {
4302 unsigned VReg;
4303
4304 if (ObjectVT == MVT::f32)
4305 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
4306 else
4307 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
4308
4309 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4310 ++FPR_idx;
4311 } else {
4312 needsLoad = true;
4313 }
4314
4315 // All FP arguments reserve stack space in the Darwin ABI.
4316 ArgOffset += isPPC64 ? 8 : ObjSize;
4317 break;
4318 case MVT::v4f32:
4319 case MVT::v4i32:
4320 case MVT::v8i16:
4321 case MVT::v16i8:
4322 // Note that vector arguments in registers don't reserve stack space,
4323 // except in varargs functions.
4324 if (VR_idx != Num_VR_Regs) {
4325 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4326 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4327 if (isVarArg) {
4328 while ((ArgOffset % 16) != 0) {
4329 ArgOffset += PtrByteSize;
4330 if (GPR_idx != Num_GPR_Regs)
4331 GPR_idx++;
4332 }
4333 ArgOffset += 16;
4334 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
4335 }
4336 ++VR_idx;
4337 } else {
4338 if (!isVarArg && !isPPC64) {
4339 // Vectors go after all the nonvectors.
4340 CurArgOffset = VecArgOffset;
4341 VecArgOffset += 16;
4342 } else {
4343 // Vectors are aligned.
4344 ArgOffset = ((ArgOffset+15)/16)*16;
4345 CurArgOffset = ArgOffset;
4346 ArgOffset += 16;
4347 }
4348 needsLoad = true;
4349 }
4350 break;
4351 }
4352
4353 // We need to load the argument to a virtual register if we determined above
4354 // that we ran out of physical registers of the appropriate type.
4355 if (needsLoad) {
4356 int FI = MFI.CreateFixedObject(ObjSize,
4357 CurArgOffset + (ArgSize - ObjSize),
4358 isImmutable);
4359 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4360 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4361 }
4362
4363 InVals.push_back(ArgVal);
4364 }
4365
4366 // Allow for Altivec parameters at the end, if needed.
4367 if (nAltivecParamsAtEnd) {
4368 MinReservedArea = ((MinReservedArea+15)/16)*16;
4369 MinReservedArea += 16*nAltivecParamsAtEnd;
4370 }
4371
4372 // Area that is at least reserved in the caller of this function.
4373 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
4374
4375 // Set the size that is at least reserved in caller of this function. Tail
4376 // call optimized functions' reserved stack space needs to be aligned so that
4377 // taking the difference between two stack areas will result in an aligned
4378 // stack.
4379 MinReservedArea =
4380 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4381 FuncInfo->setMinReservedArea(MinReservedArea);
4382
4383 // If the function takes variable number of arguments, make a frame index for
4384 // the start of the first vararg value... for expansion of llvm.va_start.
4385 if (isVarArg) {
4386 int Depth = ArgOffset;
4387
4388 FuncInfo->setVarArgsFrameIndex(
4389 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
4390 Depth, true));
4391 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4392
4393 // If this function is vararg, store any remaining integer argument regs
4394 // to their spots on the stack so that they may be loaded by dereferencing
4395 // the result of va_next.
4396 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
4397 unsigned VReg;
4398
4399 if (isPPC64)
4400 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4401 else
4402 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4403
4404 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4405 SDValue Store =
4406 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4407 MemOps.push_back(Store);
4408 // Increment the address by four for the next argument to store
4409 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4410 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4411 }
4412 }
4413
4414 if (!MemOps.empty())
4415 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4416
4417 return Chain;
4418}
4419
4420/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4421/// adjusted to accommodate the arguments for the tailcall.
4422static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4423 unsigned ParamSize) {
4424
4425 if (!isTailCall) return 0;
4426
4427 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4428 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4429 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4430 // Remember only if the new adjustment is bigger.
4431 if (SPDiff < FI->getTailCallSPDelta())
4432 FI->setTailCallSPDelta(SPDiff);
4433
4434 return SPDiff;
4435}
4436
4437static bool isFunctionGlobalAddress(SDValue Callee);
4438
4439static bool
4440callsShareTOCBase(const Function *Caller, SDValue Callee,
4441 const TargetMachine &TM) {
4442 // If !G, Callee can be an external symbol.
4443 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4444 if (!G)
4445 return false;
4446
4447 // The medium and large code models are expected to provide a sufficiently
4448 // large TOC to provide all data addressing needs of a module with a
4449 // single TOC. Since each module will be addressed with a single TOC then we
4450 // only need to check that caller and callee don't cross dso boundaries.
4451 if (CodeModel::Medium == TM.getCodeModel() ||
4452 CodeModel::Large == TM.getCodeModel())
4453 return TM.shouldAssumeDSOLocal(*Caller->getParent(), G->getGlobal());
4454
4455 // Otherwise we need to ensure callee and caller are in the same section,
4456 // since the linker may allocate multiple TOCs, and we don't know which
4457 // sections will belong to the same TOC base.
4458
4459 const GlobalValue *GV = G->getGlobal();
4460 if (!GV->isStrongDefinitionForLinker())
4461 return false;
4462
4463 // Any explicitly-specified sections and section prefixes must also match.
4464 // Also, if we're using -ffunction-sections, then each function is always in
4465 // a different section (the same is true for COMDAT functions).
4466 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4467 GV->getSection() != Caller->getSection())
4468 return false;
4469 if (const auto *F = dyn_cast<Function>(GV)) {
4470 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4471 return false;
4472 }
4473
4474 // If the callee might be interposed, then we can't assume the ultimate call
4475 // target will be in the same section. Even in cases where we can assume that
4476 // interposition won't happen, in any case where the linker might insert a
4477 // stub to allow for interposition, we must generate code as though
4478 // interposition might occur. To understand why this matters, consider a
4479 // situation where: a -> b -> c where the arrows indicate calls. b and c are
4480 // in the same section, but a is in a different module (i.e. has a different
4481 // TOC base pointer). If the linker allows for interposition between b and c,
4482 // then it will generate a stub for the call edge between b and c which will
4483 // save the TOC pointer into the designated stack slot allocated by b. If we
4484 // return true here, and therefore allow a tail call between b and c, that
4485 // stack slot won't exist and the b -> c stub will end up saving b'c TOC base
4486 // pointer into the stack slot allocated by a (where the a -> b stub saved
4487 // a's TOC base pointer). If we're not considering a tail call, but rather,
4488 // whether a nop is needed after the call instruction in b, because the linker
4489 // will insert a stub, it might complain about a missing nop if we omit it
4490 // (although many don't complain in this case).
4491 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4492 return false;
4493
4494 return true;
4495}
4496
4497static bool
4498needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4499 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4500 assert(Subtarget.isSVR4ABI() && Subtarget.isPPC64())((Subtarget.isSVR4ABI() && Subtarget.isPPC64()) ? static_cast
<void> (0) : __assert_fail ("Subtarget.isSVR4ABI() && Subtarget.isPPC64()"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4500, __PRETTY_FUNCTION__))
;
4501
4502 const unsigned PtrByteSize = 8;
4503 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4504
4505 static const MCPhysReg GPR[] = {
4506 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4507 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4508 };
4509 static const MCPhysReg VR[] = {
4510 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4511 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4512 };
4513
4514 const unsigned NumGPRs = array_lengthof(GPR);
4515 const unsigned NumFPRs = 13;
4516 const unsigned NumVRs = array_lengthof(VR);
4517 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4518
4519 unsigned NumBytes = LinkageSize;
4520 unsigned AvailableFPRs = NumFPRs;
4521 unsigned AvailableVRs = NumVRs;
4522
4523 for (const ISD::OutputArg& Param : Outs) {
4524 if (Param.Flags.isNest()) continue;
4525
4526 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags,
4527 PtrByteSize, LinkageSize, ParamAreaSize,
4528 NumBytes, AvailableFPRs, AvailableVRs,
4529 Subtarget.hasQPX()))
4530 return true;
4531 }
4532 return false;
4533}
4534
4535static bool
4536hasSameArgumentList(const Function *CallerFn, ImmutableCallSite CS) {
4537 if (CS.arg_size() != CallerFn->arg_size())
4538 return false;
4539
4540 ImmutableCallSite::arg_iterator CalleeArgIter = CS.arg_begin();
4541 ImmutableCallSite::arg_iterator CalleeArgEnd = CS.arg_end();
4542 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4543
4544 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4545 const Value* CalleeArg = *CalleeArgIter;
4546 const Value* CallerArg = &(*CallerArgIter);
4547 if (CalleeArg == CallerArg)
4548 continue;
4549
4550 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4551 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4552 // }
4553 // 1st argument of callee is undef and has the same type as caller.
4554 if (CalleeArg->getType() == CallerArg->getType() &&
4555 isa<UndefValue>(CalleeArg))
4556 continue;
4557
4558 return false;
4559 }
4560
4561 return true;
4562}
4563
4564// Returns true if TCO is possible between the callers and callees
4565// calling conventions.
4566static bool
4567areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4568 CallingConv::ID CalleeCC) {
4569 // Tail calls are possible with fastcc and ccc.
4570 auto isTailCallableCC = [] (CallingConv::ID CC){
4571 return CC == CallingConv::C || CC == CallingConv::Fast;
4572 };
4573 if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC))
4574 return false;
4575
4576 // We can safely tail call both fastcc and ccc callees from a c calling
4577 // convention caller. If the caller is fastcc, we may have less stack space
4578 // than a non-fastcc caller with the same signature so disable tail-calls in
4579 // that case.
4580 return CallerCC == CallingConv::C || CallerCC == CalleeCC;
4581}
4582
4583bool
4584PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4585 SDValue Callee,
4586 CallingConv::ID CalleeCC,
4587 ImmutableCallSite CS,
4588 bool isVarArg,
4589 const SmallVectorImpl<ISD::OutputArg> &Outs,
4590 const SmallVectorImpl<ISD::InputArg> &Ins,
4591 SelectionDAG& DAG) const {
4592 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4593
4594 if (DisableSCO && !TailCallOpt) return false;
4595
4596 // Variadic argument functions are not supported.
4597 if (isVarArg) return false;
4598
4599 auto &Caller = DAG.getMachineFunction().getFunction();
4600 // Check that the calling conventions are compatible for tco.
4601 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4602 return false;
4603
4604 // Caller contains any byval parameter is not supported.
4605 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4606 return false;
4607
4608 // Callee contains any byval parameter is not supported, too.
4609 // Note: This is a quick work around, because in some cases, e.g.
4610 // caller's stack size > callee's stack size, we are still able to apply
4611 // sibling call optimization. For example, gcc is able to do SCO for caller1
4612 // in the following example, but not for caller2.
4613 // struct test {
4614 // long int a;
4615 // char ary[56];
4616 // } gTest;
4617 // __attribute__((noinline)) int callee(struct test v, struct test *b) {
4618 // b->a = v.a;
4619 // return 0;
4620 // }
4621 // void caller1(struct test a, struct test c, struct test *b) {
4622 // callee(gTest, b); }
4623 // void caller2(struct test *b) { callee(gTest, b); }
4624 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4625 return false;
4626
4627 // If callee and caller use different calling conventions, we cannot pass
4628 // parameters on stack since offsets for the parameter area may be different.
4629 if (Caller.getCallingConv() != CalleeCC &&
4630 needStackSlotPassParameters(Subtarget, Outs))
4631 return false;
4632
4633 // No TCO/SCO on indirect call because Caller have to restore its TOC
4634 if (!isFunctionGlobalAddress(Callee) &&
4635 !isa<ExternalSymbolSDNode>(Callee))
4636 return false;
4637
4638 // If the caller and callee potentially have different TOC bases then we
4639 // cannot tail call since we need to restore the TOC pointer after the call.
4640 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4641 if (!callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4642 return false;
4643
4644 // TCO allows altering callee ABI, so we don't have to check further.
4645 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4646 return true;
4647
4648 if (DisableSCO) return false;
4649
4650 // If callee use the same argument list that caller is using, then we can
4651 // apply SCO on this case. If it is not, then we need to check if callee needs
4652 // stack for passing arguments.
4653 if (!hasSameArgumentList(&Caller, CS) &&
4654 needStackSlotPassParameters(Subtarget, Outs)) {
4655 return false;
4656 }
4657
4658 return true;
4659}
4660
4661/// IsEligibleForTailCallOptimization - Check whether the call is eligible
4662/// for tail call optimization. Targets which want to do tail call
4663/// optimization should implement this function.
4664bool
4665PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4666 CallingConv::ID CalleeCC,
4667 bool isVarArg,
4668 const SmallVectorImpl<ISD::InputArg> &Ins,
4669 SelectionDAG& DAG) const {
4670 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4671 return false;
4672
4673 // Variable argument functions are not supported.
4674 if (isVarArg)
4675 return false;
4676
4677 MachineFunction &MF = DAG.getMachineFunction();
4678 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
4679 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4680 // Functions containing by val parameters are not supported.
4681 for (unsigned i = 0; i != Ins.size(); i++) {
4682 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4683 if (Flags.isByVal()) return false;
4684 }
4685
4686 // Non-PIC/GOT tail calls are supported.
4687 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4688 return true;
4689
4690 // At the moment we can only do local tail calls (in same module, hidden
4691 // or protected) if we are generating PIC.
4692 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4693 return G->getGlobal()->hasHiddenVisibility()
4694 || G->getGlobal()->hasProtectedVisibility();
4695 }
4696
4697 return false;
4698}
4699
4700/// isCallCompatibleAddress - Return the immediate to use if the specified
4701/// 32-bit value is representable in the immediate field of a BxA instruction.
4702static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4703 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4704 if (!C) return nullptr;
4705
4706 int Addr = C->getZExtValue();
4707 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
4708 SignExtend32<26>(Addr) != Addr)
4709 return nullptr; // Top 6 bits have to be sext of immediate.
4710
4711 return DAG
4712 .getConstant(
4713 (int)C->getZExtValue() >> 2, SDLoc(Op),
4714 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
4715 .getNode();
4716}
4717
4718namespace {
4719
4720struct TailCallArgumentInfo {
4721 SDValue Arg;
4722 SDValue FrameIdxOp;
4723 int FrameIdx = 0;
4724
4725 TailCallArgumentInfo() = default;
4726};
4727
4728} // end anonymous namespace
4729
4730/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
4731static void StoreTailCallArgumentsToStackSlot(
4732 SelectionDAG &DAG, SDValue Chain,
4733 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
4734 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
4735 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
4736 SDValue Arg = TailCallArgs[i].Arg;
4737 SDValue FIN = TailCallArgs[i].FrameIdxOp;
4738 int FI = TailCallArgs[i].FrameIdx;
4739 // Store relative to framepointer.
4740 MemOpChains.push_back(DAG.getStore(
4741 Chain, dl, Arg, FIN,
4742 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4743 }
4744}
4745
4746/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
4747/// the appropriate stack slot for the tail call optimized function call.
4748static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
4749 SDValue OldRetAddr, SDValue OldFP,
4750 int SPDiff, const SDLoc &dl) {
4751 if (SPDiff) {
4752 // Calculate the new stack slot for the return address.
4753 MachineFunction &MF = DAG.getMachineFunction();
4754 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
4755 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
4756 bool isPPC64 = Subtarget.isPPC64();
4757 int SlotSize = isPPC64 ? 8 : 4;
4758 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
4759 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
4760 NewRetAddrLoc, true);
4761 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4762 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
4763 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
4764 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
4765
4766 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
4767 // slot as the FP is never overwritten.
4768 if (Subtarget.isDarwinABI()) {
4769 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
4770 int NewFPIdx = MF.getFrameInfo().CreateFixedObject(SlotSize, NewFPLoc,
4771 true);
4772 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
4773 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
4774 MachinePointerInfo::getFixedStack(
4775 DAG.getMachineFunction(), NewFPIdx));
4776 }
4777 }
4778 return Chain;
4779}
4780
4781/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
4782/// the position of the argument.
4783static void
4784CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
4785 SDValue Arg, int SPDiff, unsigned ArgOffset,
4786 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
4787 int Offset = ArgOffset + SPDiff;
4788 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
4789 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4790 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4791 SDValue FIN = DAG.getFrameIndex(FI, VT);
4792 TailCallArgumentInfo Info;
4793 Info.Arg = Arg;
4794 Info.FrameIdxOp = FIN;
4795 Info.FrameIdx = FI;
4796 TailCallArguments.push_back(Info);
4797}
4798
4799/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
4800/// stack slot. Returns the chain as result and the loaded frame pointers in
4801/// LROpOut/FPOpout. Used when tail calling.
4802SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
4803 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
4804 SDValue &FPOpOut, const SDLoc &dl) const {
4805 if (SPDiff) {
4806 // Load the LR and FP stack slot for later adjusting.
4807 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
4808 LROpOut = getReturnAddrFrameIndex(DAG);
4809 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
4810 Chain = SDValue(LROpOut.getNode(), 1);
4811
4812 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
4813 // slot as the FP is never overwritten.
4814 if (Subtarget.isDarwinABI()) {
4815 FPOpOut = getFramePointerFrameIndex(DAG);
4816 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo());
4817 Chain = SDValue(FPOpOut.getNode(), 1);
4818 }
4819 }
4820 return Chain;
4821}
4822
4823/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4824/// by "Src" to address "Dst" of size "Size". Alignment information is
4825/// specified by the specific parameter attribute. The copy will be passed as
4826/// a byval function parameter.
4827/// Sometimes what we are copying is the end of a larger object, the part that
4828/// does not fit in registers.
4829static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
4830 SDValue Chain, ISD::ArgFlagsTy Flags,
4831 SelectionDAG &DAG, const SDLoc &dl) {
4832 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4833 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4834 false, false, false, MachinePointerInfo(),
4835 MachinePointerInfo());
4836}
4837
4838/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4839/// tail calls.
4840static void LowerMemOpCallTo(
4841 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
4842 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
4843 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4844 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
4845 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4846 if (!isTailCall) {
4847 if (isVector) {
4848 SDValue StackPtr;
4849 if (isPPC64)
4850 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4851 else
4852 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4853 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4854 DAG.getConstant(ArgOffset, dl, PtrVT));
4855 }
4856 MemOpChains.push_back(
4857 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
4858 // Calculate and remember argument location.
4859 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4860 TailCallArguments);
4861}
4862
4863static void
4864PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4865 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
4866 SDValue FPOp,
4867 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4868 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4869 // might overwrite each other in case of tail call optimization.
4870 SmallVector<SDValue, 8> MemOpChains2;
4871 // Do not flag preceding copytoreg stuff together with the following stuff.
4872 InFlag = SDValue();
4873 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4874 MemOpChains2, dl);
4875 if (!MemOpChains2.empty())
4876 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4877
4878 // Store the return address to the appropriate stack slot.
4879 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
4880
4881 // Emit callseq_end just before tailcall node.
4882 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4883 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4884 InFlag = Chain.getValue(1);
4885}
4886
4887// Is this global address that of a function that can be called by name? (as
4888// opposed to something that must hold a descriptor for an indirect call).
4889static bool isFunctionGlobalAddress(SDValue Callee) {
4890 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4891 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4892 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4893 return false;
4894
4895 return G->getGlobal()->getValueType()->isFunctionTy();
4896 }
4897
4898 return false;
4899}
4900
4901static unsigned
4902PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain,
4903 SDValue CallSeqStart, const SDLoc &dl, int SPDiff, bool isTailCall,
4904 bool isPatchPoint, bool hasNest,
4905 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
4906 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4907 ImmutableCallSite CS, const PPCSubtarget &Subtarget) {
4908 bool isPPC64 = Subtarget.isPPC64();
4909 bool isSVR4ABI = Subtarget.isSVR4ABI();
4910 bool isELFv2ABI = Subtarget.isELFv2ABI();
4911
4912 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4913 NodeTys.push_back(MVT::Other); // Returns a chain
4914 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4915
4916 unsigned CallOpc = PPCISD::CALL;
4917
4918 bool needIndirectCall = true;
4919 if (!isSVR4ABI || !isPPC64)
17
Assuming 'isPPC64' is not equal to 0
18
Taking false branch
4920 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4921 // If this is an absolute destination address, use the munged value.
4922 Callee = SDValue(Dest, 0);
4923 needIndirectCall = false;
4924 }
4925
4926 // PC-relative references to external symbols should go through $stub, unless
4927 // we're building with the leopard linker or later, which automatically
4928 // synthesizes these stubs.
4929 const TargetMachine &TM = DAG.getTarget();
4930 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
4931 const GlobalValue *GV = nullptr;
4932 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee))
19
Calling 'dyn_cast<llvm::GlobalAddressSDNode, llvm::SDValue>'
23
Returning from 'dyn_cast<llvm::GlobalAddressSDNode, llvm::SDValue>'
24
Taking false branch
4933 GV = G->getGlobal();
4934 bool Local = TM.shouldAssumeDSOLocal(*Mod, GV);
4935 bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64;
25
Assuming 'Local' is not equal to 0
4936
4937 if (isFunctionGlobalAddress(Callee)) {
26
Taking false branch
4938 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4939 // A call to a TLS address is actually an indirect call to a
4940 // thread-specific pointer.
4941 unsigned OpFlags = 0;
4942 if (UsePlt)
4943 OpFlags = PPCII::MO_PLT;
4944
4945 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4946 // every direct call is) turn it into a TargetGlobalAddress /
4947 // TargetExternalSymbol node so that legalize doesn't hack it.
4948 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4949 Callee.getValueType(), 0, OpFlags);
4950 needIndirectCall = false;
4951 }
4952
4953 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
27
Calling 'dyn_cast<llvm::ExternalSymbolSDNode, llvm::SDValue>'
31
Returning from 'dyn_cast<llvm::ExternalSymbolSDNode, llvm::SDValue>'
32
Taking false branch
4954 unsigned char OpFlags = 0;
4955
4956 if (UsePlt)
4957 OpFlags = PPCII::MO_PLT;
4958
4959 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4960 OpFlags);
4961 needIndirectCall = false;
4962 }
4963
4964 if (isPatchPoint) {
33
Assuming 'isPatchPoint' is 0
34
Taking false branch
4965 // We'll form an invalid direct call when lowering a patchpoint; the full
4966 // sequence for an indirect call is complicated, and many of the
4967 // instructions introduced might have side effects (and, thus, can't be
4968 // removed later). The call itself will be removed as soon as the
4969 // argument/return lowering is complete, so the fact that it has the wrong
4970 // kind of operands should not really matter.
4971 needIndirectCall = false;
4972 }
4973
4974 if (needIndirectCall) {
35
Taking true branch
4975 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4976 // to do the call, we can't use PPCISD::CALL.
4977 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4978
4979 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
36
Assuming 'isELFv2ABI' is not equal to 0
37
Taking false branch
4980 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4981 // entry point, but to the function descriptor (the function entry point
4982 // address is part of the function descriptor though).
4983 // The function descriptor is a three doubleword structure with the
4984 // following fields: function entry point, TOC base address and
4985 // environment pointer.
4986 // Thus for a call through a function pointer, the following actions need
4987 // to be performed:
4988 // 1. Save the TOC of the caller in the TOC save area of its stack
4989 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4990 // 2. Load the address of the function entry point from the function
4991 // descriptor.
4992 // 3. Load the TOC of the callee from the function descriptor into r2.
4993 // 4. Load the environment pointer from the function descriptor into
4994 // r11.
4995 // 5. Branch to the function entry point address.
4996 // 6. On return of the callee, the TOC of the caller needs to be
4997 // restored (this is done in FinishCall()).
4998 //
4999 // The loads are scheduled at the beginning of the call sequence, and the
5000 // register copies are flagged together to ensure that no other
5001 // operations can be scheduled in between. E.g. without flagging the
5002 // copies together, a TOC access in the caller could be scheduled between
5003 // the assignment of the callee TOC and the branch to the callee, which
5004 // results in the TOC access going through the TOC of the callee instead
5005 // of going through the TOC of the caller, which leads to incorrect code.
5006
5007 // Load the address of the function entry point from the function
5008 // descriptor.
5009 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
5010 if (LDChain.getValueType() == MVT::Glue)
5011 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
5012
5013 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
5014 ? (MachineMemOperand::MODereferenceable |
5015 MachineMemOperand::MOInvariant)
5016 : MachineMemOperand::MONone;
5017
5018 MachinePointerInfo MPI(CS ? CS.getCalledValue() : nullptr);
5019 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
5020 /* Alignment = */ 8, MMOFlags);
5021
5022 // Load environment pointer into r11.
5023 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
5024 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
5025 SDValue LoadEnvPtr =
5026 DAG.getLoad(MVT::i64, dl, LDChain, AddPtr, MPI.getWithOffset(16),
5027 /* Alignment = */ 8, MMOFlags);
5028
5029 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
5030 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
5031 SDValue TOCPtr =
5032 DAG.getLoad(MVT::i64, dl, LDChain, AddTOC, MPI.getWithOffset(8),
5033 /* Alignment = */ 8, MMOFlags);
5034
5035 setUsesTOCBasePtr(DAG);
5036 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
5037 InFlag);
5038 Chain = TOCVal.getValue(0);
5039 InFlag = TOCVal.getValue(1);
5040
5041 // If the function call has an explicit 'nest' parameter, it takes the
5042 // place of the environment pointer.
5043 if (!hasNest) {
5044 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
5045 InFlag);
5046
5047 Chain = EnvVal.getValue(0);
5048 InFlag = EnvVal.getValue(1);
5049 }
5050
5051 MTCTROps[0] = Chain;
5052 MTCTROps[1] = LoadFuncPtr;
5053 MTCTROps[2] = InFlag;
5054 }
5055
5056 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
5057 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
38
'?' condition is true
5058 InFlag = Chain.getValue(1);
5059
5060 NodeTys.clear();
5061 NodeTys.push_back(MVT::Other);
5062 NodeTys.push_back(MVT::Glue);
5063 Ops.push_back(Chain);
5064 CallOpc = PPCISD::BCTRL;
5065 Callee.setNode(nullptr);
39
Passing null pointer value via 1st parameter 'N'
40
Calling 'SDValue::setNode'
42
Returning from 'SDValue::setNode'
5066 // Add use of X11 (holding environment pointer)
5067 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
5068 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
5069 // Add CTR register as callee so a bctr can be emitted later.
5070 if (isTailCall)
43
Taking true branch
5071 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
44
'?' condition is true
5072 }
5073
5074 // If this is a direct call, pass the chain and the callee.
5075 if (Callee.getNode()) {
45
Taking false branch
5076 Ops.push_back(Chain);
5077 Ops.push_back(Callee);
5078 }
5079 // If this is a tail call add stack pointer delta.
5080 if (isTailCall)
46
Taking true branch
5081 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
5082
5083 // Add argument registers to the end of the list so that they are known live
5084 // into the call.
5085 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
47
Loop condition is false. Execution continues on line 5091
5086 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5087 RegsToPass[i].second.getValueType()));
5088
5089 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
5090 // into the call.
5091 if (isSVR4ABI && isPPC64 && !isPatchPoint) {
48
Taking true branch
5092 setUsesTOCBasePtr(DAG);
5093 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
5094 }
5095
5096 return CallOpc;
5097}
5098
5099SDValue PPCTargetLowering::LowerCallResult(
5100 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
5101 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5102 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5103 SmallVector<CCValAssign, 16> RVLocs;
5104 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5105 *DAG.getContext());
5106
5107 CCRetInfo.AnalyzeCallResult(
5108 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold)
5109 ? RetCC_PPC_Cold
5110 : RetCC_PPC);
5111
5112 // Copy all of the result registers out of their specified physreg.
5113 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
5114 CCValAssign &VA = RVLocs[i];
5115 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5115, __PRETTY_FUNCTION__))
;
5116
5117 SDValue Val = DAG.getCopyFromReg(Chain, dl,
5118 VA.getLocReg(), VA.getLocVT(), InFlag);
5119 Chain = Val.getValue(1);
5120 InFlag = Val.getValue(2);
5121
5122 switch (VA.getLocInfo()) {
5123 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5123)
;
5124 case CCValAssign::Full: break;
5125 case CCValAssign::AExt:
5126 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5127 break;
5128 case CCValAssign::ZExt:
5129 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
5130 DAG.getValueType(VA.getValVT()));
5131 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5132 break;
5133 case CCValAssign::SExt:
5134 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
5135 DAG.getValueType(VA.getValVT()));
5136 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5137 break;
5138 }
5139
5140 InVals.push_back(Val);
5141 }
5142
5143 return Chain;
5144}
5145
5146SDValue PPCTargetLowering::FinishCall(
5147 CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg,
5148 bool isPatchPoint, bool hasNest, SelectionDAG &DAG,
5149 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag,
5150 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5151 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
5152 SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const {
5153 std::vector<EVT> NodeTys;
5154 SmallVector<SDValue, 8> Ops;
5155 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
16
Calling 'PrepareCall'
49
Returning from 'PrepareCall'
5156 SPDiff, isTailCall, isPatchPoint, hasNest,
5157 RegsToPass, Ops, NodeTys, CS, Subtarget);
5158
5159 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
5160 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
50
Assuming the condition is false
51
Taking false branch
5161 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5162
5163 // When performing tail call optimization the callee pops its arguments off
5164 // the stack. Account for this here so these bytes can be pushed back on in
5165 // PPCFrameLowering::eliminateCallFramePseudoInstr.
5166 int BytesCalleePops =
5167 (CallConv == CallingConv::Fast &&
52
Assuming 'CallConv' is not equal to Fast
5168 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
5169
5170 // Add a register mask operand representing the call-preserved registers.
5171 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
5172 const uint32_t *Mask =
5173 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
5174 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5174, __PRETTY_FUNCTION__))
;
5175 Ops.push_back(DAG.getRegisterMask(Mask));
5176
5177 if (InFlag.getNode())
53
Taking false branch
5178 Ops.push_back(InFlag);
5179
5180 // Emit tail call.
5181 if (isTailCall) {
54
Taking true branch
5182 assert(((Callee.getOpcode() == ISD::Register &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5187, __PRETTY_FUNCTION__))
55
Within the expansion of the macro 'assert':
a
Calling 'SDValue::getOpcode'
5183 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5187, __PRETTY_FUNCTION__))
5184 Callee.getOpcode() == ISD::TargetExternalSymbol ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5187, __PRETTY_FUNCTION__))
5185 Callee.getOpcode() == ISD::TargetGlobalAddress ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5187, __PRETTY_FUNCTION__))
5186 isa<ConstantSDNode>(Callee)) &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5187, __PRETTY_FUNCTION__))
5187 "Expecting an global address, external symbol, absolute value or register")((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"
) ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting an global address, external symbol, absolute value or register\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5187, __PRETTY_FUNCTION__))
;
5188
5189 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
5190 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
5191 }
5192
5193 // Add a NOP immediately after the branch instruction when using the 64-bit
5194 // SVR4 ABI. At link time, if caller and callee are in a different module and
5195 // thus have a different TOC, the call will be replaced with a call to a stub
5196 // function which saves the current TOC, loads the TOC of the callee and
5197 // branches to the callee. The NOP will be replaced with a load instruction
5198 // which restores the TOC of the caller from the TOC save slot of the current
5199 // stack frame. If caller and callee belong to the same module (and have the
5200 // same TOC), the NOP will remain unchanged.
5201
5202 MachineFunction &MF = DAG.getMachineFunction();
5203 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
5204 !isPatchPoint) {
5205 if (CallOpc == PPCISD::BCTRL) {
5206 // This is a call through a function pointer.
5207 // Restore the caller TOC from the save area into R2.
5208 // See PrepareCall() for more information about calls through function
5209 // pointers in the 64-bit SVR4 ABI.
5210 // We are using a target-specific load with r2 hard coded, because the
5211 // result of a target-independent load would never go directly into r2,
5212 // since r2 is a reserved register (which prevents the register allocator
5213 // from allocating it), resulting in an additional register being
5214 // allocated and an unnecessary move instruction being generated.
5215 CallOpc = PPCISD::BCTRL_LOAD_TOC;
5216
5217 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5218 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
5219 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5220 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5221 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
5222
5223 // The address needs to go after the chain input but before the flag (or
5224 // any other variadic arguments).
5225 Ops.insert(std::next(Ops.begin()), AddTOC);
5226 } else if (CallOpc == PPCISD::CALL &&
5227 !callsShareTOCBase(&MF.getFunction(), Callee, DAG.getTarget())) {
5228 // Otherwise insert NOP for non-local calls.
5229 CallOpc = PPCISD::CALL_NOP;
5230 }
5231 }
5232
5233 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
5234 InFlag = Chain.getValue(1);
5235
5236 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5237 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5238 InFlag, dl);
5239 if (!Ins.empty())
5240 InFlag = Chain.getValue(1);
5241
5242 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
5243 Ins, dl, DAG, InVals);
5244}
5245
5246SDValue
5247PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5248 SmallVectorImpl<SDValue> &InVals) const {
5249 SelectionDAG &DAG = CLI.DAG;
5250 SDLoc &dl = CLI.DL;
5251 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5252 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5253 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5254 SDValue Chain = CLI.Chain;
5255 SDValue Callee = CLI.Callee;
5256 bool &isTailCall = CLI.IsTailCall;
5257 CallingConv::ID CallConv = CLI.CallConv;
5258 bool isVarArg = CLI.IsVarArg;
5259 bool isPatchPoint = CLI.IsPatchPoint;
5260 ImmutableCallSite CS = CLI.CS;
5261
5262 if (isTailCall) {
5263 if (Subtarget.useLongCalls() && !(CS && CS.isMustTailCall()))
5264 isTailCall = false;
5265 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5266 isTailCall =
5267 IsEligibleForTailCallOptimization_64SVR4(Callee, CallConv, CS,
5268 isVarArg, Outs, Ins, DAG);
5269 else
5270 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5271 Ins, DAG);
5272 if (isTailCall) {
5273 ++NumTailCalls;
5274 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5275 ++NumSiblingCalls;
5276
5277 assert(isa<GlobalAddressSDNode>(Callee) &&((isa<GlobalAddressSDNode>(Callee) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("isa<GlobalAddressSDNode>(Callee) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5278, __PRETTY_FUNCTION__))
5278 "Callee should be an llvm::Function object.")((isa<GlobalAddressSDNode>(Callee) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("isa<GlobalAddressSDNode>(Callee) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5278, __PRETTY_FUNCTION__))
;
5279 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5280 const GlobalValue *GV =do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5281 cast<GlobalAddressSDNode>(Callee)->getGlobal();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5282 const unsigned Width =do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5283 80 - strlen("TCO caller: ") - strlen(", callee linkage: 0, 0");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5284 dbgs() << "TCO caller: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5285 << left_justify(DAG.getMachineFunction().getName(), Width)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5286 << ", callee linkage: " << GV->getVisibility() << ", "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5287 << GV->getLinkage() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
;
5288 }
5289 }
5290
5291 if (!isTailCall && CS && CS.isMustTailCall())
5292 report_fatal_error("failed to perform tail call elimination on a call "
5293 "site marked musttail");
5294
5295 // When long calls (i.e. indirect calls) are always used, calls are always
5296 // made via function pointer. If we have a function name, first translate it
5297 // into a pointer.
5298 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5299 !isTailCall)
5300 Callee = LowerGlobalAddress(Callee, DAG);
5301
5302 if (Subtarget.isSVR4ABI()) {
5303 if (Subtarget.isPPC64())
5304 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
5305 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5306 dl, DAG, InVals, CS);
5307 else
5308 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
5309 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5310 dl, DAG, InVals, CS);
5311 }
5312
5313 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
5314 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5315 dl, DAG, InVals, CS);
5316}
5317
5318SDValue PPCTargetLowering::LowerCall_32SVR4(
5319 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5320 bool isTailCall, bool isPatchPoint,
5321 const SmallVectorImpl<ISD::OutputArg> &Outs,
5322 const SmallVectorImpl<SDValue> &OutVals,
5323 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5324 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5325 ImmutableCallSite CS) const {
5326 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5327 // of the 32-bit SVR4 ABI stack frame layout.
5328
5329 assert((CallConv == CallingConv::C ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5331, __PRETTY_FUNCTION__))
5330 CallConv == CallingConv::Cold ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5331, __PRETTY_FUNCTION__))
5331 CallConv == CallingConv::Fast) && "Unknown calling convention!")(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5331, __PRETTY_FUNCTION__))
;
5332
5333 unsigned PtrByteSize = 4;
5334
5335 MachineFunction &MF = DAG.getMachineFunction();
5336
5337 // Mark this function as potentially containing a function that contains a
5338 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5339 // and restoring the callers stack pointer in this functions epilog. This is
5340 // done because by tail calling the called function might overwrite the value
5341 // in this function's (MF) stack pointer stack slot 0(SP).
5342 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5343 CallConv == CallingConv::Fast)
5344 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5345
5346 // Count how many bytes are to be pushed on the stack, including the linkage
5347 // area, parameter list area and the part of the local variable space which
5348 // contains copies of aggregates which are passed by value.
5349
5350 // Assign locations to all of the outgoing arguments.
5351 SmallVector<CCValAssign, 16> ArgLocs;
5352 PPCCCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
5353
5354 // Reserve space for the linkage area on the stack.
5355 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5356 PtrByteSize);
5357 if (useSoftFloat())
5358 CCInfo.PreAnalyzeCallOperands(Outs);
5359
5360 if (isVarArg) {
5361 // Handle fixed and variable vector arguments differently.
5362 // Fixed vector arguments go into registers as long as registers are
5363 // available. Variable vector arguments always go into memory.
5364 unsigned NumArgs = Outs.size();
5365
5366 for (unsigned i = 0; i != NumArgs; ++i) {
5367 MVT ArgVT = Outs[i].VT;
5368 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5369 bool Result;
5370
5371 if (Outs[i].IsFixed) {
5372 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5373 CCInfo);
5374 } else {
5375 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
5376 ArgFlags, CCInfo);
5377 }
5378
5379 if (Result) {
5380#ifndef NDEBUG
5381 errs() << "Call operand #" << i << " has unhandled type "
5382 << EVT(ArgVT).getEVTString() << "\n";
5383#endif
5384 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5384)
;
5385 }
5386 }
5387 } else {
5388 // All arguments are treated the same.
5389 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
5390 }
5391 CCInfo.clearWasPPCF128();
5392
5393 // Assign locations to all of the outgoing aggregate by value arguments.
5394 SmallVector<CCValAssign, 16> ByValArgLocs;
5395 CCState CCByValInfo(CallConv, isVarArg, MF, ByValArgLocs, *DAG.getContext());
5396
5397 // Reserve stack space for the allocations in CCInfo.
5398 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
5399
5400 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
5401
5402 // Size of the linkage area, parameter list area and the part of the local
5403 // space variable where copies of aggregates which are passed by value are
5404 // stored.
5405 unsigned NumBytes = CCByValInfo.getNextStackOffset();
5406
5407 // Calculate by how many bytes the stack has to be adjusted in case of tail
5408 // call optimization.
5409 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5410
5411 // Adjust the stack pointer for the new arguments...
5412 // These operations are automatically eliminated by the prolog/epilog pass
5413 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5414 SDValue CallSeqStart = Chain;
5415
5416 // Load the return address and frame pointer so it can be moved somewhere else
5417 // later.
5418 SDValue LROp, FPOp;
5419 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5420
5421 // Set up a copy of the stack pointer for use loading and storing any
5422 // arguments that may not fit in the registers available for argument
5423 // passing.
5424 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5425
5426 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5427 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5428 SmallVector<SDValue, 8> MemOpChains;
5429
5430 bool seenFloatArg = false;
5431 // Walk the register/memloc assignments, inserting copies/loads.
5432 for (unsigned i = 0, j = 0, e = ArgLocs.size();
5433 i != e;
5434 ++i) {
5435 CCValAssign &VA = ArgLocs[i];
5436 SDValue Arg = OutVals[i];
5437 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5438
5439 if (Flags.isByVal()) {
5440 // Argument is an aggregate which is passed by value, thus we need to
5441 // create a copy of it in the local variable space of the current stack
5442 // frame (which is the stack frame of the caller) and pass the address of
5443 // this copy to the callee.
5444 assert((j < ByValArgLocs.size()) && "Index out of bounds!")(((j < ByValArgLocs.size()) && "Index out of bounds!"
) ? static_cast<void> (0) : __assert_fail ("(j < ByValArgLocs.size()) && \"Index out of bounds!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5444, __PRETTY_FUNCTION__))
;
5445 CCValAssign &ByValVA = ByValArgLocs[j++];
5446 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!")(((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"
) ? static_cast<void> (0) : __assert_fail ("(VA.getValNo() == ByValVA.getValNo()) && \"ValNo mismatch!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5446, __PRETTY_FUNCTION__))
;
5447
5448 // Memory reserved in the local variable space of the callers stack frame.
5449 unsigned LocMemOffset = ByValVA.getLocMemOffset();
5450
5451 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5452 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5453 StackPtr, PtrOff);
5454
5455 // Create a copy of the argument in the local area of the current
5456 // stack frame.
5457 SDValue MemcpyCall =
5458 CreateCopyOfByValArgument(Arg, PtrOff,
5459 CallSeqStart.getNode()->getOperand(0),
5460 Flags, DAG, dl);
5461
5462 // This must go outside the CALLSEQ_START..END.
5463 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0,
5464 SDLoc(MemcpyCall));
5465 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5466 NewCallSeqStart.getNode());
5467 Chain = CallSeqStart = NewCallSeqStart;
5468
5469 // Pass the address of the aggregate copy on the stack either in a
5470 // physical register or in the parameter list area of the current stack
5471 // frame to the callee.
5472 Arg = PtrOff;
5473 }
5474
5475 // When useCRBits() is true, there can be i1 arguments.
5476 // It is because getRegisterType(MVT::i1) => MVT::i1,
5477 // and for other integer types getRegisterType() => MVT::i32.
5478 // Extend i1 and ensure callee will get i32.
5479 if (Arg.getValueType() == MVT::i1)
5480 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5481 dl, MVT::i32, Arg);
5482
5483 if (VA.isRegLoc()) {
5484 seenFloatArg |= VA.getLocVT().isFloatingPoint();
5485 // Put argument in a physical register.
5486 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
5487 } else {
5488 // Put argument in the parameter list area of the current stack frame.
5489 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5489, __PRETTY_FUNCTION__))
;
5490 unsigned LocMemOffset = VA.getLocMemOffset();
5491
5492 if (!isTailCall) {
5493 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5494 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5495 StackPtr, PtrOff);
5496
5497 MemOpChains.push_back(
5498 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5499 } else {
5500 // Calculate and remember argument location.
5501 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
5502 TailCallArguments);
5503 }
5504 }
5505 }
5506
5507 if (!MemOpChains.empty())
5508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5509
5510 // Build a sequence of copy-to-reg nodes chained together with token chain
5511 // and flag operands which copy the outgoing args into the appropriate regs.
5512 SDValue InFlag;
5513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5514 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5515 RegsToPass[i].second, InFlag);
5516 InFlag = Chain.getValue(1);
5517 }
5518
5519 // Set CR bit 6 to true if this is a vararg call with floating args passed in
5520 // registers.
5521 if (isVarArg) {
5522 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
5523 SDValue Ops[] = { Chain, InFlag };
5524
5525 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
5526 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
5527
5528 InFlag = Chain.getValue(1);
5529 }
5530
5531 if (isTailCall)
5532 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
5533 TailCallArguments);
5534
5535 return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint,
5536 /* unused except on PPC64 ELFv1 */ false, DAG,
5537 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5538 NumBytes, Ins, InVals, CS);
5539}
5540
5541// Copy an argument into memory, being careful to do this outside the
5542// call sequence for the call to which the argument belongs.
5543SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
5544 SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
5545 SelectionDAG &DAG, const SDLoc &dl) const {
5546 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
5547 CallSeqStart.getNode()->getOperand(0),
5548 Flags, DAG, dl);
5549 // The MEMCPY must go outside the CALLSEQ_START..END.
5550 int64_t FrameSize = CallSeqStart.getConstantOperandVal(1);
5551 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0,
5552 SDLoc(MemcpyCall));
5553 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5554 NewCallSeqStart.getNode());
5555 return NewCallSeqStart;
5556}
5557
5558SDValue PPCTargetLowering::LowerCall_64SVR4(
5559 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5560 bool isTailCall, bool isPatchPoint,
5561 const SmallVectorImpl<ISD::OutputArg> &Outs,
5562 const SmallVectorImpl<SDValue> &OutVals,
5563 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5564 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5565 ImmutableCallSite CS) const {
5566 bool isELFv2ABI = Subtarget.isELFv2ABI();
5567 bool isLittleEndian = Subtarget.isLittleEndian();
5568 unsigned NumOps = Outs.size();
5569 bool hasNest = false;
5570 bool IsSibCall = false;
5571
5572 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5573 unsigned PtrByteSize = 8;
5574
5575 MachineFunction &MF = DAG.getMachineFunction();
5576
5577 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt)
5578 IsSibCall = true;
5579
5580 // Mark this function as potentially containing a function that contains a
5581 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5582 // and restoring the callers stack pointer in this functions epilog. This is
5583 // done because by tail calling the called function might overwrite the value
5584 // in this function's (MF) stack pointer stack slot 0(SP).
5585 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5586 CallConv == CallingConv::Fast)
5587 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5588
5589 assert(!(CallConv == CallingConv::Fast && isVarArg) &&((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5590, __PRETTY_FUNCTION__))
5590 "fastcc not supported on varargs functions")((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5590, __PRETTY_FUNCTION__))
;
5591
5592 // Count how many bytes are to be pushed on the stack, including the linkage
5593 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
5594 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
5595 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
5596 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5597 unsigned NumBytes = LinkageSize;
5598 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5599 unsigned &QFPR_idx = FPR_idx;
5600
5601 static const MCPhysReg GPR[] = {
5602 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5603 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5604 };
5605 static const MCPhysReg VR[] = {
5606 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5607 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5608 };
5609
5610 const unsigned NumGPRs = array_lengthof(GPR);
5611 const unsigned NumFPRs = useSoftFloat() ? 0 : 13;
5612 const unsigned NumVRs = array_lengthof(VR);
5613 const unsigned NumQFPRs = NumFPRs;
5614
5615 // On ELFv2, we can avoid allocating the parameter area if all the arguments
5616 // can be passed to the callee in registers.
5617 // For the fast calling convention, there is another check below.
5618 // Note: We should keep consistent with LowerFormalArguments_64SVR4()
5619 bool HasParameterArea = !isELFv2ABI || isVarArg || CallConv == CallingConv::Fast;
5620 if (!HasParameterArea) {
5621 unsigned ParamAreaSize = NumGPRs * PtrByteSize;
5622 unsigned AvailableFPRs = NumFPRs;
5623 unsigned AvailableVRs = NumVRs;
5624 unsigned NumBytesTmp = NumBytes;
5625 for (unsigned i = 0; i != NumOps; ++i) {
5626 if (Outs[i].Flags.isNest()) continue;
5627 if (CalculateStackSlotUsed(Outs[i].VT, Outs[i].ArgVT, Outs[i].Flags,
5628 PtrByteSize, LinkageSize, ParamAreaSize,
5629 NumBytesTmp, AvailableFPRs, AvailableVRs,
5630 Subtarget.hasQPX()))
5631 HasParameterArea = true;
5632 }
5633 }
5634
5635 // When using the fast calling convention, we don't provide backing for
5636 // arguments that will be in registers.
5637 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
5638
5639 // Avoid allocating parameter area for fastcc functions if all the arguments
5640 // can be passed in the registers.
5641 if (CallConv == CallingConv::Fast)
5642 HasParameterArea = false;
5643
5644 // Add up all the space actually used.
5645 for (unsigned i = 0; i != NumOps; ++i) {
5646 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5647 EVT ArgVT = Outs[i].VT;
5648 EVT OrigVT = Outs[i].ArgVT;
5649
5650 if (Flags.isNest())
5651 continue;
5652
5653 if (CallConv == CallingConv::Fast) {
5654 if (Flags.isByVal()) {
5655 NumGPRsUsed += (Flags.getByValSize()+7)/8;
5656 if (NumGPRsUsed > NumGPRs)
5657 HasParameterArea = true;
5658 } else {
5659 switch (ArgVT.getSimpleVT().SimpleTy) {
5660 default: llvm_unreachable("Unexpected ValueType for argument!")::llvm::llvm_unreachable_internal("Unexpected ValueType for argument!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5660)
;
5661 case MVT::i1:
5662 case MVT::i32:
5663 case MVT::i64:
5664 if (++NumGPRsUsed <= NumGPRs)
5665 continue;
5666 break;
5667 case MVT::v4i32:
5668 case MVT::v8i16:
5669 case MVT::v16i8:
5670 case MVT::v2f64:
5671 case MVT::v2i64:
5672 case MVT::v1i128:
5673 case MVT::f128:
5674 if (++NumVRsUsed <= NumVRs)
5675 continue;
5676 break;
5677 case MVT::v4f32:
5678 // When using QPX, this is handled like a FP register, otherwise, it
5679 // is an Altivec register.
5680 if (Subtarget.hasQPX()) {
5681 if (++NumFPRsUsed <= NumFPRs)
5682 continue;
5683 } else {
5684 if (++NumVRsUsed <= NumVRs)
5685 continue;
5686 }
5687 break;
5688 case MVT::f32:
5689 case MVT::f64:
5690 case MVT::v4f64: // QPX
5691 case MVT::v4i1: // QPX
5692 if (++NumFPRsUsed <= NumFPRs)
5693 continue;
5694 break;
5695 }
5696 HasParameterArea = true;
5697 }
5698 }
5699
5700 /* Respect alignment of argument on the stack. */
5701 unsigned Align =
5702 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5703 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
5704
5705 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5706 if (Flags.isInConsecutiveRegsLast())
5707 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5708 }
5709
5710 unsigned NumBytesActuallyUsed = NumBytes;
5711
5712 // In the old ELFv1 ABI,
5713 // the prolog code of the callee may store up to 8 GPR argument registers to
5714 // the stack, allowing va_start to index over them in memory if its varargs.
5715 // Because we cannot tell if this is needed on the caller side, we have to
5716 // conservatively assume that it is needed. As such, make sure we have at
5717 // least enough stack space for the caller to store the 8 GPRs.
5718 // In the ELFv2 ABI, we allocate the parameter area iff a callee
5719 // really requires memory operands, e.g. a vararg function.
5720 if (HasParameterArea)
5721 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5722 else
5723 NumBytes = LinkageSize;
5724
5725 // Tail call needs the stack to be aligned.
5726 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5727 CallConv == CallingConv::Fast)
5728 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5729
5730 int SPDiff = 0;
5731
5732 // Calculate by how many bytes the stack has to be adjusted in case of tail
5733 // call optimization.
5734 if (!IsSibCall)
5735 SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5736
5737 // To protect arguments on the stack from being clobbered in a tail call,
5738 // force all the loads to happen before doing any other lowering.
5739 if (isTailCall)
5740 Chain = DAG.getStackArgumentTokenFactor(Chain);
5741
5742 // Adjust the stack pointer for the new arguments...
5743 // These operations are automatically eliminated by the prolog/epilog pass
5744 if (!IsSibCall)
5745 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5746 SDValue CallSeqStart = Chain;
5747
5748 // Load the return address and frame pointer so it can be move somewhere else
5749 // later.
5750 SDValue LROp, FPOp;
5751 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5752
5753 // Set up a copy of the stack pointer for use loading and storing any
5754 // arguments that may not fit in the registers available for argument
5755 // passing.
5756 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5757
5758 // Figure out which arguments are going to go in registers, and which in
5759 // memory. Also, if this is a vararg function, floating point operations
5760 // must be stored to our stack, and loaded into integer regs as well, if
5761 // any integer regs are available for argument passing.
5762 unsigned ArgOffset = LinkageSize;
5763
5764 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5765 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5766
5767 SmallVector<SDValue, 8> MemOpChains;
5768 for (unsigned i = 0; i != NumOps; ++i) {
5769 SDValue Arg = OutVals[i];
5770 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5771 EVT ArgVT = Outs[i].VT;
5772 EVT OrigVT = Outs[i].ArgVT;
5773
5774 // PtrOff will be used to store the current argument to the stack if a
5775 // register cannot be found for it.
5776 SDValue PtrOff;
5777
5778 // We re-align the argument offset for each argument, except when using the
5779 // fast calling convention, when we need to make sure we do that only when
5780 // we'll actually use a stack slot.
5781 auto ComputePtrOff = [&]() {
5782 /* Respect alignment of argument on the stack. */
5783 unsigned Align =
5784 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
5785 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
5786
5787 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5788
5789 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5790 };
5791
5792 if (CallConv != CallingConv::Fast) {
5793 ComputePtrOff();
5794
5795 /* Compute GPR index associated with argument offset. */
5796 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
5797 GPR_idx = std::min(GPR_idx, NumGPRs);
5798 }
5799
5800 // Promote integers to 64-bit values.
5801 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
5802 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5803 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5804 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5805 }
5806
5807 // FIXME memcpy is used way more than necessary. Correctness first.
5808 // Note: "by value" is code for passing a structure by value, not
5809 // basic types.
5810 if (Flags.isByVal()) {
5811 // Note: Size includes alignment padding, so
5812 // struct x { short a; char b; }
5813 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
5814 // These are the proper values we need for right-justifying the
5815 // aggregate in a parameter register.
5816 unsigned Size = Flags.getByValSize();
5817
5818 // An empty aggregate parameter takes up no storage and no
5819 // registers.
5820 if (Size == 0)
5821 continue;
5822
5823 if (CallConv == CallingConv::Fast)
5824 ComputePtrOff();
5825
5826 // All aggregates smaller than 8 bytes must be passed right-justified.
5827 if (Size==1 || Size==2 || Size==4) {
5828 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
5829 if (GPR_idx != NumGPRs) {
5830 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5831 MachinePointerInfo(), VT);
5832 MemOpChains.push_back(Load.getValue(1));
5833 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5834
5835 ArgOffset += PtrByteSize;
5836 continue;
5837 }
5838 }
5839
5840 if (GPR_idx == NumGPRs && Size < 8) {
5841 SDValue AddPtr = PtrOff;
5842 if (!isLittleEndian) {
5843 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5844 PtrOff.getValueType());
5845 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5846 }
5847 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5848 CallSeqStart,
5849 Flags, DAG, dl);
5850 ArgOffset += PtrByteSize;
5851 continue;
5852 }
5853 // Copy entire object into memory. There are cases where gcc-generated
5854 // code assumes it is there, even if it could be put entirely into
5855 // registers. (This is not what the doc says.)
5856
5857 // FIXME: The above statement is likely due to a misunderstanding of the
5858 // documents. All arguments must be copied into the parameter area BY
5859 // THE CALLEE in the event that the callee takes the address of any
5860 // formal argument. That has not yet been implemented. However, it is
5861 // reasonable to use the stack area as a staging area for the register
5862 // load.
5863
5864 // Skip this for small aggregates, as we will use the same slot for a
5865 // right-justified copy, below.
5866 if (Size >= 8)
5867 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5868 CallSeqStart,
5869 Flags, DAG, dl);
5870
5871 // When a register is available, pass a small aggregate right-justified.
5872 if (Size < 8 && GPR_idx != NumGPRs) {
5873 // The easiest way to get this right-justified in a register
5874 // is to copy the structure into the rightmost portion of a
5875 // local variable slot, then load the whole slot into the
5876 // register.
5877 // FIXME: The memcpy seems to produce pretty awful code for
5878 // small aggregates, particularly for packed ones.
5879 // FIXME: It would be preferable to use the slot in the
5880 // parameter save area instead of a new local variable.
5881 SDValue AddPtr = PtrOff;
5882 if (!isLittleEndian) {
5883 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5884 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5885 }
5886 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg,