Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1162, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/include -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/PowerPC -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-01-13-084841-49055-1 -x c++ /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp

1//===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the PPCISelLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "PPCISelLowering.h"
14#include "MCTargetDesc/PPCPredicates.h"
15#include "PPC.h"
16#include "PPCCCState.h"
17#include "PPCCallingConv.h"
18#include "PPCFrameLowering.h"
19#include "PPCInstrInfo.h"
20#include "PPCMachineFunctionInfo.h"
21#include "PPCPerfectShuffle.h"
22#include "PPCRegisterInfo.h"
23#include "PPCSubtarget.h"
24#include "PPCTargetMachine.h"
25#include "llvm/ADT/APFloat.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/ArrayRef.h"
28#include "llvm/ADT/DenseMap.h"
29#include "llvm/ADT/None.h"
30#include "llvm/ADT/STLExtras.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
36#include "llvm/ADT/StringSwitch.h"
37#include "llvm/CodeGen/CallingConvLower.h"
38#include "llvm/CodeGen/ISDOpcodes.h"
39#include "llvm/CodeGen/MachineBasicBlock.h"
40#include "llvm/CodeGen/MachineFrameInfo.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineInstr.h"
43#include "llvm/CodeGen/MachineInstrBuilder.h"
44#include "llvm/CodeGen/MachineJumpTableInfo.h"
45#include "llvm/CodeGen/MachineLoopInfo.h"
46#include "llvm/CodeGen/MachineMemOperand.h"
47#include "llvm/CodeGen/MachineModuleInfo.h"
48#include "llvm/CodeGen/MachineOperand.h"
49#include "llvm/CodeGen/MachineRegisterInfo.h"
50#include "llvm/CodeGen/RuntimeLibcalls.h"
51#include "llvm/CodeGen/SelectionDAG.h"
52#include "llvm/CodeGen/SelectionDAGNodes.h"
53#include "llvm/CodeGen/TargetInstrInfo.h"
54#include "llvm/CodeGen/TargetLowering.h"
55#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
56#include "llvm/CodeGen/TargetRegisterInfo.h"
57#include "llvm/CodeGen/ValueTypes.h"
58#include "llvm/IR/CallSite.h"
59#include "llvm/IR/CallingConv.h"
60#include "llvm/IR/Constant.h"
61#include "llvm/IR/Constants.h"
62#include "llvm/IR/DataLayout.h"
63#include "llvm/IR/DebugLoc.h"
64#include "llvm/IR/DerivedTypes.h"
65#include "llvm/IR/Function.h"
66#include "llvm/IR/GlobalValue.h"
67#include "llvm/IR/IRBuilder.h"
68#include "llvm/IR/Instructions.h"
69#include "llvm/IR/Intrinsics.h"
70#include "llvm/IR/IntrinsicsPowerPC.h"
71#include "llvm/IR/Module.h"
72#include "llvm/IR/Type.h"
73#include "llvm/IR/Use.h"
74#include "llvm/IR/Value.h"
75#include "llvm/MC/MCContext.h"
76#include "llvm/MC/MCExpr.h"
77#include "llvm/MC/MCRegisterInfo.h"
78#include "llvm/MC/MCSymbolXCOFF.h"
79#include "llvm/Support/AtomicOrdering.h"
80#include "llvm/Support/BranchProbability.h"
81#include "llvm/Support/Casting.h"
82#include "llvm/Support/CodeGen.h"
83#include "llvm/Support/CommandLine.h"
84#include "llvm/Support/Compiler.h"
85#include "llvm/Support/Debug.h"
86#include "llvm/Support/ErrorHandling.h"
87#include "llvm/Support/Format.h"
88#include "llvm/Support/KnownBits.h"
89#include "llvm/Support/MachineValueType.h"
90#include "llvm/Support/MathExtras.h"
91#include "llvm/Support/raw_ostream.h"
92#include "llvm/Target/TargetMachine.h"
93#include "llvm/Target/TargetOptions.h"
94#include <algorithm>
95#include <cassert>
96#include <cstdint>
97#include <iterator>
98#include <list>
99#include <utility>
100#include <vector>
101
102using namespace llvm;
103
104#define DEBUG_TYPE"ppc-lowering" "ppc-lowering"
105
106static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
107cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
108
109static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
110cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
111
112static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
113cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
114
115static cl::opt<bool> DisableSCO("disable-ppc-sco",
116cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
117
118static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
119cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
120
121static cl::opt<bool> EnableQuadPrecision("enable-ppc-quad-precision",
122cl::desc("enable quad precision float support on ppc"), cl::Hidden);
123
124static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
125cl::desc("use absolute jump tables on ppc"), cl::Hidden);
126
127STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"ppc-lowering", "NumTailCalls"
, "Number of tail calls"}
;
128STATISTIC(NumSiblingCalls, "Number of sibling calls")static llvm::Statistic NumSiblingCalls = {"ppc-lowering", "NumSiblingCalls"
, "Number of sibling calls"}
;
129
130static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
131
132static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
133
134// FIXME: Remove this once the bug has been fixed!
135extern cl::opt<bool> ANDIGlueBug;
136
137PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
138 const PPCSubtarget &STI)
139 : TargetLowering(TM), Subtarget(STI) {
140 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
141 // arguments are at least 4/8 bytes aligned.
142 bool isPPC64 = Subtarget.isPPC64();
143 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
144
145 // Set up the register classes.
146 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
147 if (!useSoftFloat()) {
148 if (hasSPE()) {
149 addRegisterClass(MVT::f32, &PPC::GPRCRegClass);
150 addRegisterClass(MVT::f64, &PPC::SPERCRegClass);
151 } else {
152 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
153 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
154 }
155 }
156
157 // Match BITREVERSE to customized fast code sequence in the td file.
158 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
159 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
160
161 // Sub-word ATOMIC_CMP_SWAP need to ensure that the input is zero-extended.
162 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
163
164 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD.
165 for (MVT VT : MVT::integer_valuetypes()) {
166 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
167 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
168 }
169
170 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
171
172 // PowerPC has pre-inc load and store's.
173 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
174 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
175 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
176 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
177 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
178 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
179 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
180 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
181 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
182 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
183 if (!Subtarget.hasSPE()) {
184 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
185 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
186 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
187 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
188 }
189
190 // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
191 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
192 for (MVT VT : ScalarIntVTs) {
193 setOperationAction(ISD::ADDC, VT, Legal);
194 setOperationAction(ISD::ADDE, VT, Legal);
195 setOperationAction(ISD::SUBC, VT, Legal);
196 setOperationAction(ISD::SUBE, VT, Legal);
197 }
198
199 if (Subtarget.useCRBits()) {
200 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
201
202 if (isPPC64 || Subtarget.hasFPCVT()) {
203 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
204 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
205 isPPC64 ? MVT::i64 : MVT::i32);
206 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
207 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
208 isPPC64 ? MVT::i64 : MVT::i32);
209 } else {
210 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
211 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
212 }
213
214 // PowerPC does not support direct load/store of condition registers.
215 setOperationAction(ISD::LOAD, MVT::i1, Custom);
216 setOperationAction(ISD::STORE, MVT::i1, Custom);
217
218 // FIXME: Remove this once the ANDI glue bug is fixed:
219 if (ANDIGlueBug)
220 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
221
222 for (MVT VT : MVT::integer_valuetypes()) {
223 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
224 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
225 setTruncStoreAction(VT, MVT::i1, Expand);
226 }
227
228 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
229 }
230
231 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
232 // PPC (the libcall is not available).
233 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom);
234 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom);
235
236 // We do not currently implement these libm ops for PowerPC.
237 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
238 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
239 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
240 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
241 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
242 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
243
244 // PowerPC has no SREM/UREM instructions unless we are on P9
245 // On P9 we may use a hardware instruction to compute the remainder.
246 // The instructions are not legalized directly because in the cases where the
247 // result of both the remainder and the division is required it is more
248 // efficient to compute the remainder from the result of the division rather
249 // than use the remainder instruction.
250 if (Subtarget.isISA3_0()) {
251 setOperationAction(ISD::SREM, MVT::i32, Custom);
252 setOperationAction(ISD::UREM, MVT::i32, Custom);
253 setOperationAction(ISD::SREM, MVT::i64, Custom);
254 setOperationAction(ISD::UREM, MVT::i64, Custom);
255 } else {
256 setOperationAction(ISD::SREM, MVT::i32, Expand);
257 setOperationAction(ISD::UREM, MVT::i32, Expand);
258 setOperationAction(ISD::SREM, MVT::i64, Expand);
259 setOperationAction(ISD::UREM, MVT::i64, Expand);
260 }
261
262 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
263 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
264 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
265 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
266 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
267 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
268 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
269 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
270 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
271
272 // We don't support sin/cos/sqrt/fmod/pow
273 setOperationAction(ISD::FSIN , MVT::f64, Expand);
274 setOperationAction(ISD::FCOS , MVT::f64, Expand);
275 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
276 setOperationAction(ISD::FREM , MVT::f64, Expand);
277 setOperationAction(ISD::FPOW , MVT::f64, Expand);
278 setOperationAction(ISD::FSIN , MVT::f32, Expand);
279 setOperationAction(ISD::FCOS , MVT::f32, Expand);
280 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
281 setOperationAction(ISD::FREM , MVT::f32, Expand);
282 setOperationAction(ISD::FPOW , MVT::f32, Expand);
283 if (Subtarget.hasSPE()) {
284 setOperationAction(ISD::FMA , MVT::f64, Expand);
285 setOperationAction(ISD::FMA , MVT::f32, Expand);
286 } else {
287 setOperationAction(ISD::FMA , MVT::f64, Legal);
288 setOperationAction(ISD::FMA , MVT::f32, Legal);
289 }
290
291 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
292
293 // If we're enabling GP optimizations, use hardware square root
294 if (!Subtarget.hasFSQRT() &&
295 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
296 Subtarget.hasFRE()))
297 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
298
299 if (!Subtarget.hasFSQRT() &&
300 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
301 Subtarget.hasFRES()))
302 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
303
304 if (Subtarget.hasFCPSGN()) {
305 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
306 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
307 } else {
308 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
309 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
310 }
311
312 if (Subtarget.hasFPRND()) {
313 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
314 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
315 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
316 setOperationAction(ISD::FROUND, MVT::f64, Legal);
317
318 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
319 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
320 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
321 setOperationAction(ISD::FROUND, MVT::f32, Legal);
322 }
323
324 // PowerPC does not have BSWAP, but we can use vector BSWAP instruction xxbrd
325 // to speed up scalar BSWAP64.
326 // CTPOP or CTTZ were introduced in P8/P9 respectively
327 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
328 if (Subtarget.hasP9Vector())
329 setOperationAction(ISD::BSWAP, MVT::i64 , Custom);
330 else
331 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
332 if (Subtarget.isISA3_0()) {
333 setOperationAction(ISD::CTTZ , MVT::i32 , Legal);
334 setOperationAction(ISD::CTTZ , MVT::i64 , Legal);
335 } else {
336 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
337 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
338 }
339
340 if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) {
341 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
342 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
343 } else {
344 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
345 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
346 }
347
348 // PowerPC does not have ROTR
349 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
350 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
351
352 if (!Subtarget.useCRBits()) {
353 // PowerPC does not have Select
354 setOperationAction(ISD::SELECT, MVT::i32, Expand);
355 setOperationAction(ISD::SELECT, MVT::i64, Expand);
356 setOperationAction(ISD::SELECT, MVT::f32, Expand);
357 setOperationAction(ISD::SELECT, MVT::f64, Expand);
358 }
359
360 // PowerPC wants to turn select_cc of FP into fsel when possible.
361 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
362 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
363
364 // PowerPC wants to optimize integer setcc a bit
365 if (!Subtarget.useCRBits())
366 setOperationAction(ISD::SETCC, MVT::i32, Custom);
367
368 // PowerPC does not have BRCOND which requires SetCC
369 if (!Subtarget.useCRBits())
370 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
371
372 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
373
374 if (Subtarget.hasSPE()) {
375 // SPE has built-in conversions
376 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
377 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
378 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
379 } else {
380 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
381 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
382
383 // PowerPC does not have [U|S]INT_TO_FP
384 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
385 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
386 }
387
388 if (Subtarget.hasDirectMove() && isPPC64) {
389 setOperationAction(ISD::BITCAST, MVT::f32, Legal);
390 setOperationAction(ISD::BITCAST, MVT::i32, Legal);
391 setOperationAction(ISD::BITCAST, MVT::i64, Legal);
392 setOperationAction(ISD::BITCAST, MVT::f64, Legal);
393 if (TM.Options.UnsafeFPMath) {
394 setOperationAction(ISD::LRINT, MVT::f64, Legal);
395 setOperationAction(ISD::LRINT, MVT::f32, Legal);
396 setOperationAction(ISD::LLRINT, MVT::f64, Legal);
397 setOperationAction(ISD::LLRINT, MVT::f32, Legal);
398 setOperationAction(ISD::LROUND, MVT::f64, Legal);
399 setOperationAction(ISD::LROUND, MVT::f32, Legal);
400 setOperationAction(ISD::LLROUND, MVT::f64, Legal);
401 setOperationAction(ISD::LLROUND, MVT::f32, Legal);
402 }
403 } else {
404 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
405 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
406 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
407 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
408 }
409
410 // We cannot sextinreg(i1). Expand to shifts.
411 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
412
413 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
414 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
415 // support continuation, user-level threading, and etc.. As a result, no
416 // other SjLj exception interfaces are implemented and please don't build
417 // your own exception handling based on them.
418 // LLVM/Clang supports zero-cost DWARF exception handling.
419 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
420 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
421
422 // We want to legalize GlobalAddress and ConstantPool nodes into the
423 // appropriate instructions to materialize the address.
424 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
425 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
426 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
427 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
428 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
429 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
430 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
431 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
432 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
433 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
434
435 // TRAP is legal.
436 setOperationAction(ISD::TRAP, MVT::Other, Legal);
437
438 // TRAMPOLINE is custom lowered.
439 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
440 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
441
442 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
443 setOperationAction(ISD::VASTART , MVT::Other, Custom);
444
445 if (Subtarget.is64BitELFABI()) {
446 // VAARG always uses double-word chunks, so promote anything smaller.
447 setOperationAction(ISD::VAARG, MVT::i1, Promote);
448 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64);
449 setOperationAction(ISD::VAARG, MVT::i8, Promote);
450 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64);
451 setOperationAction(ISD::VAARG, MVT::i16, Promote);
452 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64);
453 setOperationAction(ISD::VAARG, MVT::i32, Promote);
454 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64);
455 setOperationAction(ISD::VAARG, MVT::Other, Expand);
456 } else if (Subtarget.is32BitELFABI()) {
457 // VAARG is custom lowered with the 32-bit SVR4 ABI.
458 setOperationAction(ISD::VAARG, MVT::Other, Custom);
459 setOperationAction(ISD::VAARG, MVT::i64, Custom);
460 } else
461 setOperationAction(ISD::VAARG, MVT::Other, Expand);
462
463 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
464 if (Subtarget.is32BitELFABI())
465 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
466 else
467 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
468
469 // Use the default implementation.
470 setOperationAction(ISD::VAEND , MVT::Other, Expand);
471 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
472 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
473 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
474 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
475 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom);
476 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom);
477 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
478 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
479
480 // We want to custom lower some of our intrinsics.
481 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
482
483 // To handle counter-based loop conditions.
484 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
485
486 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
487 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
488 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
489 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
490
491 // Comparisons that require checking two conditions.
492 if (Subtarget.hasSPE()) {
493 setCondCodeAction(ISD::SETO, MVT::f32, Expand);
494 setCondCodeAction(ISD::SETO, MVT::f64, Expand);
495 setCondCodeAction(ISD::SETUO, MVT::f32, Expand);
496 setCondCodeAction(ISD::SETUO, MVT::f64, Expand);
497 }
498 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
499 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
500 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
501 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
502 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
503 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
504 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
505 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
506 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
507 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
508 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
509 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
510
511 if (Subtarget.has64BitSupport()) {
512 // They also have instructions for converting between i64 and fp.
513 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
514 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
515 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
516 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
517 // This is just the low 32 bits of a (signed) fp->i64 conversion.
518 // We cannot do this with Promote because i64 is not a legal type.
519 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
520
521 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
522 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
523 } else {
524 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
525 if (Subtarget.hasSPE())
526 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
527 else
528 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
529 }
530
531 // With the instructions enabled under FPCVT, we can do everything.
532 if (Subtarget.hasFPCVT()) {
533 if (Subtarget.has64BitSupport()) {
534 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
535 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
536 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
537 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
538 }
539
540 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
541 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
542 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
543 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
544 }
545
546 if (Subtarget.use64BitRegs()) {
547 // 64-bit PowerPC implementations can support i64 types directly
548 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
549 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
550 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
551 // 64-bit PowerPC wants to expand i128 shifts itself.
552 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
553 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
554 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
555 } else {
556 // 32-bit PowerPC wants to expand i64 shifts itself.
557 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
558 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
559 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
560 }
561
562 if (Subtarget.hasVSX()) {
563 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
564 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
565 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
566 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
567 }
568
569 if (Subtarget.hasAltivec()) {
570 // First set operation action for all vector types to expand. Then we
571 // will selectively turn on ones that can be effectively codegen'd.
572 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
573 // add/sub are legal for all supported vector VT's.
574 setOperationAction(ISD::ADD, VT, Legal);
575 setOperationAction(ISD::SUB, VT, Legal);
576
577 // For v2i64, these are only valid with P8Vector. This is corrected after
578 // the loop.
579 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
580 setOperationAction(ISD::SMAX, VT, Legal);
581 setOperationAction(ISD::SMIN, VT, Legal);
582 setOperationAction(ISD::UMAX, VT, Legal);
583 setOperationAction(ISD::UMIN, VT, Legal);
584 }
585 else {
586 setOperationAction(ISD::SMAX, VT, Expand);
587 setOperationAction(ISD::SMIN, VT, Expand);
588 setOperationAction(ISD::UMAX, VT, Expand);
589 setOperationAction(ISD::UMIN, VT, Expand);
590 }
591
592 if (Subtarget.hasVSX()) {
593 setOperationAction(ISD::FMAXNUM, VT, Legal);
594 setOperationAction(ISD::FMINNUM, VT, Legal);
595 }
596
597 // Vector instructions introduced in P8
598 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
599 setOperationAction(ISD::CTPOP, VT, Legal);
600 setOperationAction(ISD::CTLZ, VT, Legal);
601 }
602 else {
603 setOperationAction(ISD::CTPOP, VT, Expand);
604 setOperationAction(ISD::CTLZ, VT, Expand);
605 }
606
607 // Vector instructions introduced in P9
608 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128))
609 setOperationAction(ISD::CTTZ, VT, Legal);
610 else
611 setOperationAction(ISD::CTTZ, VT, Expand);
612
613 // We promote all shuffles to v16i8.
614 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
615 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
616
617 // We promote all non-typed operations to v4i32.
618 setOperationAction(ISD::AND , VT, Promote);
619 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
620 setOperationAction(ISD::OR , VT, Promote);
621 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
622 setOperationAction(ISD::XOR , VT, Promote);
623 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
624 setOperationAction(ISD::LOAD , VT, Promote);
625 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
626 setOperationAction(ISD::SELECT, VT, Promote);
627 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
628 setOperationAction(ISD::VSELECT, VT, Legal);
629 setOperationAction(ISD::SELECT_CC, VT, Promote);
630 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
631 setOperationAction(ISD::STORE, VT, Promote);
632 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
633
634 // No other operations are legal.
635 setOperationAction(ISD::MUL , VT, Expand);
636 setOperationAction(ISD::SDIV, VT, Expand);
637 setOperationAction(ISD::SREM, VT, Expand);
638 setOperationAction(ISD::UDIV, VT, Expand);
639 setOperationAction(ISD::UREM, VT, Expand);
640 setOperationAction(ISD::FDIV, VT, Expand);
641 setOperationAction(ISD::FREM, VT, Expand);
642 setOperationAction(ISD::FNEG, VT, Expand);
643 setOperationAction(ISD::FSQRT, VT, Expand);
644 setOperationAction(ISD::FLOG, VT, Expand);
645 setOperationAction(ISD::FLOG10, VT, Expand);
646 setOperationAction(ISD::FLOG2, VT, Expand);
647 setOperationAction(ISD::FEXP, VT, Expand);
648 setOperationAction(ISD::FEXP2, VT, Expand);
649 setOperationAction(ISD::FSIN, VT, Expand);
650 setOperationAction(ISD::FCOS, VT, Expand);
651 setOperationAction(ISD::FABS, VT, Expand);
652 setOperationAction(ISD::FFLOOR, VT, Expand);
653 setOperationAction(ISD::FCEIL, VT, Expand);
654 setOperationAction(ISD::FTRUNC, VT, Expand);
655 setOperationAction(ISD::FRINT, VT, Expand);
656 setOperationAction(ISD::FNEARBYINT, VT, Expand);
657 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
658 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
659 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
660 setOperationAction(ISD::MULHU, VT, Expand);
661 setOperationAction(ISD::MULHS, VT, Expand);
662 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
663 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
664 setOperationAction(ISD::UDIVREM, VT, Expand);
665 setOperationAction(ISD::SDIVREM, VT, Expand);
666 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
667 setOperationAction(ISD::FPOW, VT, Expand);
668 setOperationAction(ISD::BSWAP, VT, Expand);
669 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
670 setOperationAction(ISD::ROTL, VT, Expand);
671 setOperationAction(ISD::ROTR, VT, Expand);
672
673 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
674 setTruncStoreAction(VT, InnerVT, Expand);
675 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
676 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
677 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
678 }
679 }
680 if (!Subtarget.hasP8Vector()) {
681 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
682 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
683 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
684 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
685 }
686
687 for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8})
688 setOperationAction(ISD::ABS, VT, Custom);
689
690 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
691 // with merges, splats, etc.
692 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
693
694 // Vector truncates to sub-word integer that fit in an Altivec/VSX register
695 // are cheap, so handle them before they get expanded to scalar.
696 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
697 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
698 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
699 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
700 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
701
702 setOperationAction(ISD::AND , MVT::v4i32, Legal);
703 setOperationAction(ISD::OR , MVT::v4i32, Legal);
704 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
705 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
706 setOperationAction(ISD::SELECT, MVT::v4i32,
707 Subtarget.useCRBits() ? Legal : Expand);
708 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
709 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
710 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
711 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
712 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
713 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
714 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
715 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
716 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
717
718 // Without hasP8Altivec set, v2i64 SMAX isn't available.
719 // But ABS custom lowering requires SMAX support.
720 if (!Subtarget.hasP8Altivec())
721 setOperationAction(ISD::ABS, MVT::v2i64, Expand);
722
723 // With hasAltivec set, we can lower ISD::ROTL to vrl(b|h|w).
724 if (Subtarget.hasAltivec())
725 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
726 setOperationAction(ISD::ROTL, VT, Legal);
727 // With hasP8Altivec set, we can lower ISD::ROTL to vrld.
728 if (Subtarget.hasP8Altivec())
729 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
730
731 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
732 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
733 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
734 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
735
736 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
737 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
738
739 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
740 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
741 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
742 }
743
744 if (Subtarget.hasP8Altivec())
745 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
746 else
747 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
748
749 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
750 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
751
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
754
755 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
756 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
757 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
758 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
759
760 // Altivec does not contain unordered floating-point compare instructions
761 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
762 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
763 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
764 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
765
766 if (Subtarget.hasVSX()) {
767 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
768 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
769 if (Subtarget.hasP8Vector()) {
770 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
771 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
772 }
773 if (Subtarget.hasDirectMove() && isPPC64) {
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
776 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
777 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
778 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
779 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
781 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
782 }
783 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
784
785 // The nearbyint variants are not allowed to raise the inexact exception
786 // so we can only code-gen them with unsafe math.
787 if (TM.Options.UnsafeFPMath) {
788 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
789 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
790 }
791
792 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
793 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
794 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
795 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
796 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
797 setOperationAction(ISD::FROUND, MVT::f64, Legal);
798
799 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
800 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
801 setOperationAction(ISD::FROUND, MVT::f32, Legal);
802
803 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
804 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
805
806 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
807 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
808
809 // Share the Altivec comparison restrictions.
810 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
811 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
812 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
813 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
814
815 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
816 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
817
818 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
819
820 if (Subtarget.hasP8Vector())
821 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
822
823 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
824
825 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
826 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
827 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
828
829 if (Subtarget.hasP8Altivec()) {
830 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
831 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
832 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
833
834 // 128 bit shifts can be accomplished via 3 instructions for SHL and
835 // SRL, but not for SRA because of the instructions available:
836 // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth
837 // doing
838 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
839 setOperationAction(ISD::SRL, MVT::v1i128, Expand);
840 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
841
842 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
843 }
844 else {
845 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
846 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
847 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
848
849 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
850
851 // VSX v2i64 only supports non-arithmetic operations.
852 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
853 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
854 }
855
856 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
857 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
858 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
859 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
860
861 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
862
863 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
864 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
865 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
866 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
867
868 // Custom handling for partial vectors of integers converted to
869 // floating point. We already have optimal handling for v2i32 through
870 // the DAG combine, so those aren't necessary.
871 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom);
872 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
873 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
874 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
875 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom);
876 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom);
877 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
878 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
879
880 setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
881 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
882 setOperationAction(ISD::FABS, MVT::v4f32, Legal);
883 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
884 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
885 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal);
886
887 if (Subtarget.hasDirectMove())
888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
890
891 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
892 }
893
894 if (Subtarget.hasP8Altivec()) {
895 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
896 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
897 }
898
899 if (Subtarget.hasP9Vector()) {
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
902
903 // 128 bit shifts can be accomplished via 3 instructions for SHL and
904 // SRL, but not for SRA because of the instructions available:
905 // VS{RL} and VS{RL}O.
906 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
907 setOperationAction(ISD::SRL, MVT::v1i128, Legal);
908 setOperationAction(ISD::SRA, MVT::v1i128, Expand);
909
910 if (EnableQuadPrecision) {
911 addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
912 setOperationAction(ISD::FADD, MVT::f128, Legal);
913 setOperationAction(ISD::FSUB, MVT::f128, Legal);
914 setOperationAction(ISD::FDIV, MVT::f128, Legal);
915 setOperationAction(ISD::FMUL, MVT::f128, Legal);
916 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
917 // No extending loads to f128 on PPC.
918 for (MVT FPT : MVT::fp_valuetypes())
919 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand);
920 setOperationAction(ISD::FMA, MVT::f128, Legal);
921 setCondCodeAction(ISD::SETULT, MVT::f128, Expand);
922 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand);
923 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand);
924 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand);
925 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand);
926 setCondCodeAction(ISD::SETONE, MVT::f128, Expand);
927
928 setOperationAction(ISD::FTRUNC, MVT::f128, Legal);
929 setOperationAction(ISD::FRINT, MVT::f128, Legal);
930 setOperationAction(ISD::FFLOOR, MVT::f128, Legal);
931 setOperationAction(ISD::FCEIL, MVT::f128, Legal);
932 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal);
933 setOperationAction(ISD::FROUND, MVT::f128, Legal);
934
935 setOperationAction(ISD::SELECT, MVT::f128, Expand);
936 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
937 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
938 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
939 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::i128, Custom);
941 // No implementation for these ops for PowerPC.
942 setOperationAction(ISD::FSIN , MVT::f128, Expand);
943 setOperationAction(ISD::FCOS , MVT::f128, Expand);
944 setOperationAction(ISD::FPOW, MVT::f128, Expand);
945 setOperationAction(ISD::FPOWI, MVT::f128, Expand);
946 setOperationAction(ISD::FREM, MVT::f128, Expand);
947 }
948 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
949 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
950 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
951 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
952 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
953 }
954
955 if (Subtarget.hasP9Altivec()) {
956 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
957 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
958
959 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
960 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
961 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
962 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal);
963 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal);
964 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
965 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
966 }
967 }
968
969 if (Subtarget.hasQPX()) {
970 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
971 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
972 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
973 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
974
975 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
976 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
977
978 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
979 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
980
981 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
982 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
983
984 if (!Subtarget.useCRBits())
985 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
986 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
987
988 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
989 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
990 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
991 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
992 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
993 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
994 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
995
996 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
997 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
998
999 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
1000 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
1001
1002 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
1003 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
1004 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
1005 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
1006 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
1007 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
1008 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
1009 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
1010 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
1011 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
1012
1013 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
1014 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
1015
1016 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
1017 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
1018
1019 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
1020
1021 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
1022 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
1023 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
1024 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
1025
1026 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
1027 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
1028
1029 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
1030 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
1031
1032 if (!Subtarget.useCRBits())
1033 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
1034 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1035
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
1037 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
1038 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
1039 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
1040 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
1041 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
1042 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
1043
1044 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
1045 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
1046
1047 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
1048 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
1049 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
1050 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
1051 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
1052 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
1053 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
1054 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
1055 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
1056 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
1057
1058 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1059 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1060
1061 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
1062 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
1063
1064 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
1065
1066 setOperationAction(ISD::AND , MVT::v4i1, Legal);
1067 setOperationAction(ISD::OR , MVT::v4i1, Legal);
1068 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
1069
1070 if (!Subtarget.useCRBits())
1071 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
1072 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
1073
1074 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
1075 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
1076
1077 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
1078 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
1079 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
1080 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
1081 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
1082 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
1083 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1084
1085 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
1086 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
1087
1088 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
1089
1090 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1093 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
1094
1095 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1098 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
1099
1100 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
1101 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
1102
1103 // These need to set FE_INEXACT, and so cannot be vectorized here.
1104 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
1105 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
1106
1107 if (TM.Options.UnsafeFPMath) {
1108 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1109 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1110
1111 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
1112 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
1113 } else {
1114 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
1115 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
1116
1117 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
1118 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
1119 }
1120 }
1121
1122 if (Subtarget.has64BitSupport())
1123 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
1124
1125 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
1126
1127 if (!isPPC64) {
1128 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
1129 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
1130 }
1131
1132 setBooleanContents(ZeroOrOneBooleanContent);
1133
1134 if (Subtarget.hasAltivec()) {
1135 // Altivec instructions set fields to all zeros or all ones.
1136 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
1137 }
1138
1139 if (!isPPC64) {
1140 // These libcalls are not available in 32-bit.
1141 setLibcallName(RTLIB::SHL_I128, nullptr);
1142 setLibcallName(RTLIB::SRL_I128, nullptr);
1143 setLibcallName(RTLIB::SRA_I128, nullptr);
1144 }
1145
1146 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
1147
1148 // We have target-specific dag combine patterns for the following nodes:
1149 setTargetDAGCombine(ISD::ADD);
1150 setTargetDAGCombine(ISD::SHL);
1151 setTargetDAGCombine(ISD::SRA);
1152 setTargetDAGCombine(ISD::SRL);
1153 setTargetDAGCombine(ISD::MUL);
1154 setTargetDAGCombine(ISD::SINT_TO_FP);
1155 setTargetDAGCombine(ISD::BUILD_VECTOR);
1156 if (Subtarget.hasFPCVT())
1157 setTargetDAGCombine(ISD::UINT_TO_FP);
1158 setTargetDAGCombine(ISD::LOAD);
1159 setTargetDAGCombine(ISD::STORE);
1160 setTargetDAGCombine(ISD::BR_CC);
1161 if (Subtarget.useCRBits())
1162 setTargetDAGCombine(ISD::BRCOND);
1163 setTargetDAGCombine(ISD::BSWAP);
1164 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1165 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
1166 setTargetDAGCombine(ISD::INTRINSIC_VOID);
1167
1168 setTargetDAGCombine(ISD::SIGN_EXTEND);
1169 setTargetDAGCombine(ISD::ZERO_EXTEND);
1170 setTargetDAGCombine(ISD::ANY_EXTEND);
1171
1172 setTargetDAGCombine(ISD::TRUNCATE);
1173 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1174
1175
1176 if (Subtarget.useCRBits()) {
1177 setTargetDAGCombine(ISD::TRUNCATE);
1178 setTargetDAGCombine(ISD::SETCC);
1179 setTargetDAGCombine(ISD::SELECT_CC);
1180 }
1181
1182 // Use reciprocal estimates.
1183 if (TM.Options.UnsafeFPMath) {
1184 setTargetDAGCombine(ISD::FDIV);
1185 setTargetDAGCombine(ISD::FSQRT);
1186 }
1187
1188 if (Subtarget.hasP9Altivec()) {
1189 setTargetDAGCombine(ISD::ABS);
1190 setTargetDAGCombine(ISD::VSELECT);
1191 }
1192
1193 // Darwin long double math library functions have $LDBL128 appended.
1194 if (Subtarget.isDarwin()) {
1195 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
1196 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
1197 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
1198 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
1199 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
1200 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
1201 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
1202 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
1203 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
1204 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
1205 }
1206
1207 if (EnableQuadPrecision) {
1208 setLibcallName(RTLIB::LOG_F128, "logf128");
1209 setLibcallName(RTLIB::LOG2_F128, "log2f128");
1210 setLibcallName(RTLIB::LOG10_F128, "log10f128");
1211 setLibcallName(RTLIB::EXP_F128, "expf128");
1212 setLibcallName(RTLIB::EXP2_F128, "exp2f128");
1213 setLibcallName(RTLIB::SIN_F128, "sinf128");
1214 setLibcallName(RTLIB::COS_F128, "cosf128");
1215 setLibcallName(RTLIB::POW_F128, "powf128");
1216 setLibcallName(RTLIB::FMIN_F128, "fminf128");
1217 setLibcallName(RTLIB::FMAX_F128, "fmaxf128");
1218 setLibcallName(RTLIB::POWI_F128, "__powikf2");
1219 setLibcallName(RTLIB::REM_F128, "fmodf128");
1220 }
1221
1222 // With 32 condition bits, we don't need to sink (and duplicate) compares
1223 // aggressively in CodeGenPrep.
1224 if (Subtarget.useCRBits()) {
1225 setHasMultipleConditionRegisters();
1226 setJumpIsExpensive();
1227 }
1228
1229 setMinFunctionAlignment(Align(4));
1230 if (Subtarget.isDarwin())
1231 setPrefFunctionAlignment(Align(16));
1232
1233 switch (Subtarget.getCPUDirective()) {
1234 default: break;
1235 case PPC::DIR_970:
1236 case PPC::DIR_A2:
1237 case PPC::DIR_E500:
1238 case PPC::DIR_E500mc:
1239 case PPC::DIR_E5500:
1240 case PPC::DIR_PWR4:
1241 case PPC::DIR_PWR5:
1242 case PPC::DIR_PWR5X:
1243 case PPC::DIR_PWR6:
1244 case PPC::DIR_PWR6X:
1245 case PPC::DIR_PWR7:
1246 case PPC::DIR_PWR8:
1247 case PPC::DIR_PWR9:
1248 case PPC::DIR_PWR_FUTURE:
1249 setPrefLoopAlignment(Align(16));
1250 setPrefFunctionAlignment(Align(16));
1251 break;
1252 }
1253
1254 if (Subtarget.enableMachineScheduler())
1255 setSchedulingPreference(Sched::Source);
1256 else
1257 setSchedulingPreference(Sched::Hybrid);
1258
1259 computeRegisterProperties(STI.getRegisterInfo());
1260
1261 // The Freescale cores do better with aggressive inlining of memcpy and
1262 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
1263 if (Subtarget.getCPUDirective() == PPC::DIR_E500mc ||
1264 Subtarget.getCPUDirective() == PPC::DIR_E5500) {
1265 MaxStoresPerMemset = 32;
1266 MaxStoresPerMemsetOptSize = 16;
1267 MaxStoresPerMemcpy = 32;
1268 MaxStoresPerMemcpyOptSize = 8;
1269 MaxStoresPerMemmove = 32;
1270 MaxStoresPerMemmoveOptSize = 8;
1271 } else if (Subtarget.getCPUDirective() == PPC::DIR_A2) {
1272 // The A2 also benefits from (very) aggressive inlining of memcpy and
1273 // friends. The overhead of a the function call, even when warm, can be
1274 // over one hundred cycles.
1275 MaxStoresPerMemset = 128;
1276 MaxStoresPerMemcpy = 128;
1277 MaxStoresPerMemmove = 128;
1278 MaxLoadsPerMemcmp = 128;
1279 } else {
1280 MaxLoadsPerMemcmp = 8;
1281 MaxLoadsPerMemcmpOptSize = 4;
1282 }
1283}
1284
1285/// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1286/// the desired ByVal argument alignment.
1287static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
1288 unsigned MaxMaxAlign) {
1289 if (MaxAlign == MaxMaxAlign)
1290 return;
1291 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1292 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
1293 MaxAlign = 32;
1294 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
1295 MaxAlign = 16;
1296 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1297 unsigned EltAlign = 0;
1298 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
1299 if (EltAlign > MaxAlign)
1300 MaxAlign = EltAlign;
1301 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1302 for (auto *EltTy : STy->elements()) {
1303 unsigned EltAlign = 0;
1304 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
1305 if (EltAlign > MaxAlign)
1306 MaxAlign = EltAlign;
1307 if (MaxAlign == MaxMaxAlign)
1308 break;
1309 }
1310 }
1311}
1312
1313/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1314/// function arguments in the caller parameter area.
1315unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
1316 const DataLayout &DL) const {
1317 // Darwin passes everything on 4 byte boundary.
1318 if (Subtarget.isDarwin())
1319 return 4;
1320
1321 // 16byte and wider vectors are passed on 16byte boundary.
1322 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
1323 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
1324 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
1325 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
1326 return Align;
1327}
1328
1329bool PPCTargetLowering::useSoftFloat() const {
1330 return Subtarget.useSoftFloat();
1331}
1332
1333bool PPCTargetLowering::hasSPE() const {
1334 return Subtarget.hasSPE();
1335}
1336
1337bool PPCTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const {
1338 return VT.isScalarInteger();
1339}
1340
1341const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
1342 switch ((PPCISD::NodeType)Opcode) {
1343 case PPCISD::FIRST_NUMBER: break;
1344 case PPCISD::FSEL: return "PPCISD::FSEL";
1345 case PPCISD::XSMAXCDP: return "PPCISD::XSMAXCDP";
1346 case PPCISD::XSMINCDP: return "PPCISD::XSMINCDP";
1347 case PPCISD::FCFID: return "PPCISD::FCFID";
1348 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1349 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1350 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1351 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1352 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1353 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1354 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1355 case PPCISD::FP_TO_UINT_IN_VSR:
1356 return "PPCISD::FP_TO_UINT_IN_VSR,";
1357 case PPCISD::FP_TO_SINT_IN_VSR:
1358 return "PPCISD::FP_TO_SINT_IN_VSR";
1359 case PPCISD::FRE: return "PPCISD::FRE";
1360 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
1361 case PPCISD::STFIWX: return "PPCISD::STFIWX";
1362 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
1363 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
1364 case PPCISD::VPERM: return "PPCISD::VPERM";
1365 case PPCISD::XXSPLT: return "PPCISD::XXSPLT";
1366 case PPCISD::VECINSERT: return "PPCISD::VECINSERT";
1367 case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI";
1368 case PPCISD::VECSHL: return "PPCISD::VECSHL";
1369 case PPCISD::CMPB: return "PPCISD::CMPB";
1370 case PPCISD::Hi: return "PPCISD::Hi";
1371 case PPCISD::Lo: return "PPCISD::Lo";
1372 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1373 case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8";
1374 case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
1375 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1376 case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
1377 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1378 case PPCISD::SRL: return "PPCISD::SRL";
1379 case PPCISD::SRA: return "PPCISD::SRA";
1380 case PPCISD::SHL: return "PPCISD::SHL";
1381 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1382 case PPCISD::CALL: return "PPCISD::CALL";
1383 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1384 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1385 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1386 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1387 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1388 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1389 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1390 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1391 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1392 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1393 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1394 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1395 case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP";
1396 case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP";
1397 case PPCISD::ANDI_rec_1_EQ_BIT:
1398 return "PPCISD::ANDI_rec_1_EQ_BIT";
1399 case PPCISD::ANDI_rec_1_GT_BIT:
1400 return "PPCISD::ANDI_rec_1_GT_BIT";
1401 case PPCISD::VCMP: return "PPCISD::VCMP";
1402 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1403 case PPCISD::LBRX: return "PPCISD::LBRX";
1404 case PPCISD::STBRX: return "PPCISD::STBRX";
1405 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1406 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1407 case PPCISD::LXSIZX: return "PPCISD::LXSIZX";
1408 case PPCISD::STXSIX: return "PPCISD::STXSIX";
1409 case PPCISD::VEXTS: return "PPCISD::VEXTS";
1410 case PPCISD::SExtVElems: return "PPCISD::SExtVElems";
1411 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1412 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1413 case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE";
1414 case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE";
1415 case PPCISD::ST_VSR_SCAL_INT:
1416 return "PPCISD::ST_VSR_SCAL_INT";
1417 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1418 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1419 case PPCISD::BDZ: return "PPCISD::BDZ";
1420 case PPCISD::MFFS: return "PPCISD::MFFS";
1421 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1422 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1423 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1424 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1425 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1426 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1427 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1428 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1429 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1430 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1431 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1432 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1433 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1434 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1435 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1436 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1437 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1438 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1439 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1440 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1441 case PPCISD::SC: return "PPCISD::SC";
1442 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1443 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1444 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1445 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1446 case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
1447 case PPCISD::VABSD: return "PPCISD::VABSD";
1448 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1449 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1450 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1451 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1452 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1453 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1454 case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
1455 case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64";
1456 case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE";
1457 case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
1458 case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
1459 case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
1460 case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
1461 }
1462 return nullptr;
1463}
1464
1465EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1466 EVT VT) const {
1467 if (!VT.isVector())
1468 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1469
1470 if (Subtarget.hasQPX())
1471 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1472
1473 return VT.changeVectorElementTypeToInteger();
1474}
1475
1476bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1477 assert(VT.isFloatingPoint() && "Non-floating-point FMA?")((VT.isFloatingPoint() && "Non-floating-point FMA?") ?
static_cast<void> (0) : __assert_fail ("VT.isFloatingPoint() && \"Non-floating-point FMA?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1477, __PRETTY_FUNCTION__))
;
1478 return true;
1479}
1480
1481//===----------------------------------------------------------------------===//
1482// Node matching predicates, for use by the tblgen matching code.
1483//===----------------------------------------------------------------------===//
1484
1485/// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1486static bool isFloatingPointZero(SDValue Op) {
1487 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
9
Calling 'dyn_cast<llvm::ConstantFPSDNode, llvm::SDValue>'
24
Returning from 'dyn_cast<llvm::ConstantFPSDNode, llvm::SDValue>'
25
Assuming 'CFP' is null
26
Taking false branch
1488 return CFP->getValueAPF().isZero();
1489 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1490 // Maybe this has already been legalized into the constant pool?
1491 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
27
Calling 'SDValue::getOperand'
1492 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1493 return CFP->getValueAPF().isZero();
1494 }
1495 return false;
1496}
1497
1498/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1499/// true if Op is undef or if it matches the specified value.
1500static bool isConstantOrUndef(int Op, int Val) {
1501 return Op < 0 || Op == Val;
1502}
1503
1504/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1505/// VPKUHUM instruction.
1506/// The ShuffleKind distinguishes between big-endian operations with
1507/// two different inputs (0), either-endian operations with two identical
1508/// inputs (1), and little-endian operations with two different inputs (2).
1509/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1510bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1511 SelectionDAG &DAG) {
1512 bool IsLE = DAG.getDataLayout().isLittleEndian();
1513 if (ShuffleKind == 0) {
1514 if (IsLE)
1515 return false;
1516 for (unsigned i = 0; i != 16; ++i)
1517 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1518 return false;
1519 } else if (ShuffleKind == 2) {
1520 if (!IsLE)
1521 return false;
1522 for (unsigned i = 0; i != 16; ++i)
1523 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1524 return false;
1525 } else if (ShuffleKind == 1) {
1526 unsigned j = IsLE ? 0 : 1;
1527 for (unsigned i = 0; i != 8; ++i)
1528 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1529 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1530 return false;
1531 }
1532 return true;
1533}
1534
1535/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1536/// VPKUWUM instruction.
1537/// The ShuffleKind distinguishes between big-endian operations with
1538/// two different inputs (0), either-endian operations with two identical
1539/// inputs (1), and little-endian operations with two different inputs (2).
1540/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1541bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1542 SelectionDAG &DAG) {
1543 bool IsLE = DAG.getDataLayout().isLittleEndian();
1544 if (ShuffleKind == 0) {
1545 if (IsLE)
1546 return false;
1547 for (unsigned i = 0; i != 16; i += 2)
1548 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1549 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1550 return false;
1551 } else if (ShuffleKind == 2) {
1552 if (!IsLE)
1553 return false;
1554 for (unsigned i = 0; i != 16; i += 2)
1555 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1556 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1557 return false;
1558 } else if (ShuffleKind == 1) {
1559 unsigned j = IsLE ? 0 : 2;
1560 for (unsigned i = 0; i != 8; i += 2)
1561 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1562 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1563 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1564 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1565 return false;
1566 }
1567 return true;
1568}
1569
1570/// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1571/// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1572/// current subtarget.
1573///
1574/// The ShuffleKind distinguishes between big-endian operations with
1575/// two different inputs (0), either-endian operations with two identical
1576/// inputs (1), and little-endian operations with two different inputs (2).
1577/// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1578bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1579 SelectionDAG &DAG) {
1580 const PPCSubtarget& Subtarget =
1581 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1582 if (!Subtarget.hasP8Vector())
1583 return false;
1584
1585 bool IsLE = DAG.getDataLayout().isLittleEndian();
1586 if (ShuffleKind == 0) {
1587 if (IsLE)
1588 return false;
1589 for (unsigned i = 0; i != 16; i += 4)
1590 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1591 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1592 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1593 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1594 return false;
1595 } else if (ShuffleKind == 2) {
1596 if (!IsLE)
1597 return false;
1598 for (unsigned i = 0; i != 16; i += 4)
1599 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1600 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1601 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1602 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1603 return false;
1604 } else if (ShuffleKind == 1) {
1605 unsigned j = IsLE ? 0 : 4;
1606 for (unsigned i = 0; i != 8; i += 4)
1607 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1608 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1609 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1610 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1611 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1612 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1613 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1614 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1615 return false;
1616 }
1617 return true;
1618}
1619
1620/// isVMerge - Common function, used to match vmrg* shuffles.
1621///
1622static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1623 unsigned LHSStart, unsigned RHSStart) {
1624 if (N->getValueType(0) != MVT::v16i8)
1625 return false;
1626 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1627, __PRETTY_FUNCTION__))
1627 "Unsupported merge size!")(((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
"Unsupported merge size!") ? static_cast<void> (0) : __assert_fail
("(UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && \"Unsupported merge size!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1627, __PRETTY_FUNCTION__))
;
1628
1629 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1630 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1631 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1632 LHSStart+j+i*UnitSize) ||
1633 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1634 RHSStart+j+i*UnitSize))
1635 return false;
1636 }
1637 return true;
1638}
1639
1640/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1641/// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1642/// The ShuffleKind distinguishes between big-endian merges with two
1643/// different inputs (0), either-endian merges with two identical inputs (1),
1644/// and little-endian merges with two different inputs (2). For the latter,
1645/// the input operands are swapped (see PPCInstrAltivec.td).
1646bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1647 unsigned ShuffleKind, SelectionDAG &DAG) {
1648 if (DAG.getDataLayout().isLittleEndian()) {
1649 if (ShuffleKind == 1) // unary
1650 return isVMerge(N, UnitSize, 0, 0);
1651 else if (ShuffleKind == 2) // swapped
1652 return isVMerge(N, UnitSize, 0, 16);
1653 else
1654 return false;
1655 } else {
1656 if (ShuffleKind == 1) // unary
1657 return isVMerge(N, UnitSize, 8, 8);
1658 else if (ShuffleKind == 0) // normal
1659 return isVMerge(N, UnitSize, 8, 24);
1660 else
1661 return false;
1662 }
1663}
1664
1665/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1666/// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1667/// The ShuffleKind distinguishes between big-endian merges with two
1668/// different inputs (0), either-endian merges with two identical inputs (1),
1669/// and little-endian merges with two different inputs (2). For the latter,
1670/// the input operands are swapped (see PPCInstrAltivec.td).
1671bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1672 unsigned ShuffleKind, SelectionDAG &DAG) {
1673 if (DAG.getDataLayout().isLittleEndian()) {
1674 if (ShuffleKind == 1) // unary
1675 return isVMerge(N, UnitSize, 8, 8);
1676 else if (ShuffleKind == 2) // swapped
1677 return isVMerge(N, UnitSize, 8, 24);
1678 else
1679 return false;
1680 } else {
1681 if (ShuffleKind == 1) // unary
1682 return isVMerge(N, UnitSize, 0, 0);
1683 else if (ShuffleKind == 0) // normal
1684 return isVMerge(N, UnitSize, 0, 16);
1685 else
1686 return false;
1687 }
1688}
1689
1690/**
1691 * Common function used to match vmrgew and vmrgow shuffles
1692 *
1693 * The indexOffset determines whether to look for even or odd words in
1694 * the shuffle mask. This is based on the of the endianness of the target
1695 * machine.
1696 * - Little Endian:
1697 * - Use offset of 0 to check for odd elements
1698 * - Use offset of 4 to check for even elements
1699 * - Big Endian:
1700 * - Use offset of 0 to check for even elements
1701 * - Use offset of 4 to check for odd elements
1702 * A detailed description of the vector element ordering for little endian and
1703 * big endian can be found at
1704 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1705 * Targeting your applications - what little endian and big endian IBM XL C/C++
1706 * compiler differences mean to you
1707 *
1708 * The mask to the shuffle vector instruction specifies the indices of the
1709 * elements from the two input vectors to place in the result. The elements are
1710 * numbered in array-access order, starting with the first vector. These vectors
1711 * are always of type v16i8, thus each vector will contain 16 elements of size
1712 * 8. More info on the shuffle vector can be found in the
1713 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1714 * Language Reference.
1715 *
1716 * The RHSStartValue indicates whether the same input vectors are used (unary)
1717 * or two different input vectors are used, based on the following:
1718 * - If the instruction uses the same vector for both inputs, the range of the
1719 * indices will be 0 to 15. In this case, the RHSStart value passed should
1720 * be 0.
1721 * - If the instruction has two different vectors then the range of the
1722 * indices will be 0 to 31. In this case, the RHSStart value passed should
1723 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1724 * to 31 specify elements in the second vector).
1725 *
1726 * \param[in] N The shuffle vector SD Node to analyze
1727 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1728 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1729 * vector to the shuffle_vector instruction
1730 * \return true iff this shuffle vector represents an even or odd word merge
1731 */
1732static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1733 unsigned RHSStartValue) {
1734 if (N->getValueType(0) != MVT::v16i8)
1735 return false;
1736
1737 for (unsigned i = 0; i < 2; ++i)
1738 for (unsigned j = 0; j < 4; ++j)
1739 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1740 i*RHSStartValue+j+IndexOffset) ||
1741 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1742 i*RHSStartValue+j+IndexOffset+8))
1743 return false;
1744 return true;
1745}
1746
1747/**
1748 * Determine if the specified shuffle mask is suitable for the vmrgew or
1749 * vmrgow instructions.
1750 *
1751 * \param[in] N The shuffle vector SD Node to analyze
1752 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1753 * \param[in] ShuffleKind Identify the type of merge:
1754 * - 0 = big-endian merge with two different inputs;
1755 * - 1 = either-endian merge with two identical inputs;
1756 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1757 * little-endian merges).
1758 * \param[in] DAG The current SelectionDAG
1759 * \return true iff this shuffle mask
1760 */
1761bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1762 unsigned ShuffleKind, SelectionDAG &DAG) {
1763 if (DAG.getDataLayout().isLittleEndian()) {
1764 unsigned indexOffset = CheckEven ? 4 : 0;
1765 if (ShuffleKind == 1) // Unary
1766 return isVMerge(N, indexOffset, 0);
1767 else if (ShuffleKind == 2) // swapped
1768 return isVMerge(N, indexOffset, 16);
1769 else
1770 return false;
1771 }
1772 else {
1773 unsigned indexOffset = CheckEven ? 0 : 4;
1774 if (ShuffleKind == 1) // Unary
1775 return isVMerge(N, indexOffset, 0);
1776 else if (ShuffleKind == 0) // Normal
1777 return isVMerge(N, indexOffset, 16);
1778 else
1779 return false;
1780 }
1781 return false;
1782}
1783
1784/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1785/// amount, otherwise return -1.
1786/// The ShuffleKind distinguishes between big-endian operations with two
1787/// different inputs (0), either-endian operations with two identical inputs
1788/// (1), and little-endian operations with two different inputs (2). For the
1789/// latter, the input operands are swapped (see PPCInstrAltivec.td).
1790int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1791 SelectionDAG &DAG) {
1792 if (N->getValueType(0) != MVT::v16i8)
1793 return -1;
1794
1795 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1796
1797 // Find the first non-undef value in the shuffle mask.
1798 unsigned i;
1799 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1800 /*search*/;
1801
1802 if (i == 16) return -1; // all undef.
1803
1804 // Otherwise, check to see if the rest of the elements are consecutively
1805 // numbered from this value.
1806 unsigned ShiftAmt = SVOp->getMaskElt(i);
1807 if (ShiftAmt < i) return -1;
1808
1809 ShiftAmt -= i;
1810 bool isLE = DAG.getDataLayout().isLittleEndian();
1811
1812 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1813 // Check the rest of the elements to see if they are consecutive.
1814 for (++i; i != 16; ++i)
1815 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1816 return -1;
1817 } else if (ShuffleKind == 1) {
1818 // Check the rest of the elements to see if they are consecutive.
1819 for (++i; i != 16; ++i)
1820 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1821 return -1;
1822 } else
1823 return -1;
1824
1825 if (isLE)
1826 ShiftAmt = 16 - ShiftAmt;
1827
1828 return ShiftAmt;
1829}
1830
1831/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1832/// specifies a splat of a single element that is suitable for input to
1833/// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
1834bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1835 assert(N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) &&((N->getValueType(0) == MVT::v16i8 && isPowerOf2_32
(EltSize) && EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1836, __PRETTY_FUNCTION__))
1836 EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes")((N->getValueType(0) == MVT::v16i8 && isPowerOf2_32
(EltSize) && EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && \"Can only handle 1,2,4,8 byte element sizes\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1836, __PRETTY_FUNCTION__))
;
1837
1838 // The consecutive indices need to specify an element, not part of two
1839 // different elements. So abandon ship early if this isn't the case.
1840 if (N->getMaskElt(0) % EltSize != 0)
1841 return false;
1842
1843 // This is a splat operation if each element of the permute is the same, and
1844 // if the value doesn't reference the second vector.
1845 unsigned ElementBase = N->getMaskElt(0);
1846
1847 // FIXME: Handle UNDEF elements too!
1848 if (ElementBase >= 16)
1849 return false;
1850
1851 // Check that the indices are consecutive, in the case of a multi-byte element
1852 // splatted with a v16i8 mask.
1853 for (unsigned i = 1; i != EltSize; ++i)
1854 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1855 return false;
1856
1857 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1858 if (N->getMaskElt(i) < 0) continue;
1859 for (unsigned j = 0; j != EltSize; ++j)
1860 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1861 return false;
1862 }
1863 return true;
1864}
1865
1866/// Check that the mask is shuffling N byte elements. Within each N byte
1867/// element of the mask, the indices could be either in increasing or
1868/// decreasing order as long as they are consecutive.
1869/// \param[in] N the shuffle vector SD Node to analyze
1870/// \param[in] Width the element width in bytes, could be 2/4/8/16 (HalfWord/
1871/// Word/DoubleWord/QuadWord).
1872/// \param[in] StepLen the delta indices number among the N byte element, if
1873/// the mask is in increasing/decreasing order then it is 1/-1.
1874/// \return true iff the mask is shuffling N byte elements.
1875static bool isNByteElemShuffleMask(ShuffleVectorSDNode *N, unsigned Width,
1876 int StepLen) {
1877 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1878, __PRETTY_FUNCTION__))
1878 "Unexpected element width.")(((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
"Unexpected element width.") ? static_cast<void> (0) :
__assert_fail ("(Width == 2 || Width == 4 || Width == 8 || Width == 16) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1878, __PRETTY_FUNCTION__))
;
1879 assert((StepLen == 1 || StepLen == -1) && "Unexpected element width.")(((StepLen == 1 || StepLen == -1) && "Unexpected element width."
) ? static_cast<void> (0) : __assert_fail ("(StepLen == 1 || StepLen == -1) && \"Unexpected element width.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1879, __PRETTY_FUNCTION__))
;
1880
1881 unsigned NumOfElem = 16 / Width;
1882 unsigned MaskVal[16]; // Width is never greater than 16
1883 for (unsigned i = 0; i < NumOfElem; ++i) {
1884 MaskVal[0] = N->getMaskElt(i * Width);
1885 if ((StepLen == 1) && (MaskVal[0] % Width)) {
1886 return false;
1887 } else if ((StepLen == -1) && ((MaskVal[0] + 1) % Width)) {
1888 return false;
1889 }
1890
1891 for (unsigned int j = 1; j < Width; ++j) {
1892 MaskVal[j] = N->getMaskElt(i * Width + j);
1893 if (MaskVal[j] != MaskVal[j-1] + StepLen) {
1894 return false;
1895 }
1896 }
1897 }
1898
1899 return true;
1900}
1901
1902bool PPC::isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1903 unsigned &InsertAtByte, bool &Swap, bool IsLE) {
1904 if (!isNByteElemShuffleMask(N, 4, 1))
1905 return false;
1906
1907 // Now we look at mask elements 0,4,8,12
1908 unsigned M0 = N->getMaskElt(0) / 4;
1909 unsigned M1 = N->getMaskElt(4) / 4;
1910 unsigned M2 = N->getMaskElt(8) / 4;
1911 unsigned M3 = N->getMaskElt(12) / 4;
1912 unsigned LittleEndianShifts[] = { 2, 1, 0, 3 };
1913 unsigned BigEndianShifts[] = { 3, 0, 1, 2 };
1914
1915 // Below, let H and L be arbitrary elements of the shuffle mask
1916 // where H is in the range [4,7] and L is in the range [0,3].
1917 // H, 1, 2, 3 or L, 5, 6, 7
1918 if ((M0 > 3 && M1 == 1 && M2 == 2 && M3 == 3) ||
1919 (M0 < 4 && M1 == 5 && M2 == 6 && M3 == 7)) {
1920 ShiftElts = IsLE ? LittleEndianShifts[M0 & 0x3] : BigEndianShifts[M0 & 0x3];
1921 InsertAtByte = IsLE ? 12 : 0;
1922 Swap = M0 < 4;
1923 return true;
1924 }
1925 // 0, H, 2, 3 or 4, L, 6, 7
1926 if ((M1 > 3 && M0 == 0 && M2 == 2 && M3 == 3) ||
1927 (M1 < 4 && M0 == 4 && M2 == 6 && M3 == 7)) {
1928 ShiftElts = IsLE ? LittleEndianShifts[M1 & 0x3] : BigEndianShifts[M1 & 0x3];
1929 InsertAtByte = IsLE ? 8 : 4;
1930 Swap = M1 < 4;
1931 return true;
1932 }
1933 // 0, 1, H, 3 or 4, 5, L, 7
1934 if ((M2 > 3 && M0 == 0 && M1 == 1 && M3 == 3) ||
1935 (M2 < 4 && M0 == 4 && M1 == 5 && M3 == 7)) {
1936 ShiftElts = IsLE ? LittleEndianShifts[M2 & 0x3] : BigEndianShifts[M2 & 0x3];
1937 InsertAtByte = IsLE ? 4 : 8;
1938 Swap = M2 < 4;
1939 return true;
1940 }
1941 // 0, 1, 2, H or 4, 5, 6, L
1942 if ((M3 > 3 && M0 == 0 && M1 == 1 && M2 == 2) ||
1943 (M3 < 4 && M0 == 4 && M1 == 5 && M2 == 6)) {
1944 ShiftElts = IsLE ? LittleEndianShifts[M3 & 0x3] : BigEndianShifts[M3 & 0x3];
1945 InsertAtByte = IsLE ? 0 : 12;
1946 Swap = M3 < 4;
1947 return true;
1948 }
1949
1950 // If both vector operands for the shuffle are the same vector, the mask will
1951 // contain only elements from the first one and the second one will be undef.
1952 if (N->getOperand(1).isUndef()) {
1953 ShiftElts = 0;
1954 Swap = true;
1955 unsigned XXINSERTWSrcElem = IsLE ? 2 : 1;
1956 if (M0 == XXINSERTWSrcElem && M1 == 1 && M2 == 2 && M3 == 3) {
1957 InsertAtByte = IsLE ? 12 : 0;
1958 return true;
1959 }
1960 if (M0 == 0 && M1 == XXINSERTWSrcElem && M2 == 2 && M3 == 3) {
1961 InsertAtByte = IsLE ? 8 : 4;
1962 return true;
1963 }
1964 if (M0 == 0 && M1 == 1 && M2 == XXINSERTWSrcElem && M3 == 3) {
1965 InsertAtByte = IsLE ? 4 : 8;
1966 return true;
1967 }
1968 if (M0 == 0 && M1 == 1 && M2 == 2 && M3 == XXINSERTWSrcElem) {
1969 InsertAtByte = IsLE ? 0 : 12;
1970 return true;
1971 }
1972 }
1973
1974 return false;
1975}
1976
1977bool PPC::isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
1978 bool &Swap, bool IsLE) {
1979 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1979, __PRETTY_FUNCTION__))
;
1980 // Ensure each byte index of the word is consecutive.
1981 if (!isNByteElemShuffleMask(N, 4, 1))
1982 return false;
1983
1984 // Now we look at mask elements 0,4,8,12, which are the beginning of words.
1985 unsigned M0 = N->getMaskElt(0) / 4;
1986 unsigned M1 = N->getMaskElt(4) / 4;
1987 unsigned M2 = N->getMaskElt(8) / 4;
1988 unsigned M3 = N->getMaskElt(12) / 4;
1989
1990 // If both vector operands for the shuffle are the same vector, the mask will
1991 // contain only elements from the first one and the second one will be undef.
1992 if (N->getOperand(1).isUndef()) {
1993 assert(M0 < 4 && "Indexing into an undef vector?")((M0 < 4 && "Indexing into an undef vector?") ? static_cast
<void> (0) : __assert_fail ("M0 < 4 && \"Indexing into an undef vector?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 1993, __PRETTY_FUNCTION__))
;
1994 if (M1 != (M0 + 1) % 4 || M2 != (M1 + 1) % 4 || M3 != (M2 + 1) % 4)
1995 return false;
1996
1997 ShiftElts = IsLE ? (4 - M0) % 4 : M0;
1998 Swap = false;
1999 return true;
2000 }
2001
2002 // Ensure each word index of the ShuffleVector Mask is consecutive.
2003 if (M1 != (M0 + 1) % 8 || M2 != (M1 + 1) % 8 || M3 != (M2 + 1) % 8)
2004 return false;
2005
2006 if (IsLE) {
2007 if (M0 == 0 || M0 == 7 || M0 == 6 || M0 == 5) {
2008 // Input vectors don't need to be swapped if the leading element
2009 // of the result is one of the 3 left elements of the second vector
2010 // (or if there is no shift to be done at all).
2011 Swap = false;
2012 ShiftElts = (8 - M0) % 8;
2013 } else if (M0 == 4 || M0 == 3 || M0 == 2 || M0 == 1) {
2014 // Input vectors need to be swapped if the leading element
2015 // of the result is one of the 3 left elements of the first vector
2016 // (or if we're shifting by 4 - thereby simply swapping the vectors).
2017 Swap = true;
2018 ShiftElts = (4 - M0) % 4;
2019 }
2020
2021 return true;
2022 } else { // BE
2023 if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) {
2024 // Input vectors don't need to be swapped if the leading element
2025 // of the result is one of the 4 elements of the first vector.
2026 Swap = false;
2027 ShiftElts = M0;
2028 } else if (M0 == 4 || M0 == 5 || M0 == 6 || M0 == 7) {
2029 // Input vectors need to be swapped if the leading element
2030 // of the result is one of the 4 elements of the right vector.
2031 Swap = true;
2032 ShiftElts = M0 - 4;
2033 }
2034
2035 return true;
2036 }
2037}
2038
2039bool static isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width) {
2040 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2040, __PRETTY_FUNCTION__))
;
2041
2042 if (!isNByteElemShuffleMask(N, Width, -1))
2043 return false;
2044
2045 for (int i = 0; i < 16; i += Width)
2046 if (N->getMaskElt(i) != i + Width - 1)
2047 return false;
2048
2049 return true;
2050}
2051
2052bool PPC::isXXBRHShuffleMask(ShuffleVectorSDNode *N) {
2053 return isXXBRShuffleMaskHelper(N, 2);
2054}
2055
2056bool PPC::isXXBRWShuffleMask(ShuffleVectorSDNode *N) {
2057 return isXXBRShuffleMaskHelper(N, 4);
2058}
2059
2060bool PPC::isXXBRDShuffleMask(ShuffleVectorSDNode *N) {
2061 return isXXBRShuffleMaskHelper(N, 8);
2062}
2063
2064bool PPC::isXXBRQShuffleMask(ShuffleVectorSDNode *N) {
2065 return isXXBRShuffleMaskHelper(N, 16);
2066}
2067
2068/// Can node \p N be lowered to an XXPERMDI instruction? If so, set \p Swap
2069/// if the inputs to the instruction should be swapped and set \p DM to the
2070/// value for the immediate.
2071/// Specifically, set \p Swap to true only if \p N can be lowered to XXPERMDI
2072/// AND element 0 of the result comes from the first input (LE) or second input
2073/// (BE). Set \p DM to the calculated result (0-3) only if \p N can be lowered.
2074/// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle
2075/// mask.
2076bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM,
2077 bool &Swap, bool IsLE) {
2078 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8")((N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v16i8 && \"Shuffle vector expects v16i8\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2078, __PRETTY_FUNCTION__))
;
2079
2080 // Ensure each byte index of the double word is consecutive.
2081 if (!isNByteElemShuffleMask(N, 8, 1))
2082 return false;
2083
2084 unsigned M0 = N->getMaskElt(0) / 8;
2085 unsigned M1 = N->getMaskElt(8) / 8;
2086 assert(((M0 | M1) < 4) && "A mask element out of bounds?")((((M0 | M1) < 4) && "A mask element out of bounds?"
) ? static_cast<void> (0) : __assert_fail ("((M0 | M1) < 4) && \"A mask element out of bounds?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2086, __PRETTY_FUNCTION__))
;
2087
2088 // If both vector operands for the shuffle are the same vector, the mask will
2089 // contain only elements from the first one and the second one will be undef.
2090 if (N->getOperand(1).isUndef()) {
2091 if ((M0 | M1) < 2) {
2092 DM = IsLE ? (((~M1) & 1) << 1) + ((~M0) & 1) : (M0 << 1) + (M1 & 1);
2093 Swap = false;
2094 return true;
2095 } else
2096 return false;
2097 }
2098
2099 if (IsLE) {
2100 if (M0 > 1 && M1 < 2) {
2101 Swap = false;
2102 } else if (M0 < 2 && M1 > 1) {
2103 M0 = (M0 + 2) % 4;
2104 M1 = (M1 + 2) % 4;
2105 Swap = true;
2106 } else
2107 return false;
2108
2109 // Note: if control flow comes here that means Swap is already set above
2110 DM = (((~M1) & 1) << 1) + ((~M0) & 1);
2111 return true;
2112 } else { // BE
2113 if (M0 < 2 && M1 > 1) {
2114 Swap = false;
2115 } else if (M0 > 1 && M1 < 2) {
2116 M0 = (M0 + 2) % 4;
2117 M1 = (M1 + 2) % 4;
2118 Swap = true;
2119 } else
2120 return false;
2121
2122 // Note: if control flow comes here that means Swap is already set above
2123 DM = (M0 << 1) + (M1 & 1);
2124 return true;
2125 }
2126}
2127
2128
2129/// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2130/// appropriate for PPC mnemonics (which have a big endian bias - namely
2131/// elements are counted from the left of the vector register).
2132unsigned PPC::getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize,
2133 SelectionDAG &DAG) {
2134 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2135 assert(isSplatShuffleMask(SVOp, EltSize))((isSplatShuffleMask(SVOp, EltSize)) ? static_cast<void>
(0) : __assert_fail ("isSplatShuffleMask(SVOp, EltSize)", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2135, __PRETTY_FUNCTION__))
;
2136 if (DAG.getDataLayout().isLittleEndian())
2137 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
2138 else
2139 return SVOp->getMaskElt(0) / EltSize;
2140}
2141
2142/// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
2143/// by using a vspltis[bhw] instruction of the specified element size, return
2144/// the constant being splatted. The ByteSize field indicates the number of
2145/// bytes of each element [124] -> [bhw].
2146SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2147 SDValue OpVal(nullptr, 0);
2148
2149 // If ByteSize of the splat is bigger than the element size of the
2150 // build_vector, then we have a case where we are checking for a splat where
2151 // multiple elements of the buildvector are folded together into a single
2152 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2153 unsigned EltSize = 16/N->getNumOperands();
2154 if (EltSize < ByteSize) {
2155 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
2156 SDValue UniquedVals[4];
2157 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?")((Multiple > 1 && Multiple <= 4 && "How can this happen?"
) ? static_cast<void> (0) : __assert_fail ("Multiple > 1 && Multiple <= 4 && \"How can this happen?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2157, __PRETTY_FUNCTION__))
;
2158
2159 // See if all of the elements in the buildvector agree across.
2160 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2161 if (N->getOperand(i).isUndef()) continue;
2162 // If the element isn't a constant, bail fully out.
2163 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
2164
2165 if (!UniquedVals[i&(Multiple-1)].getNode())
2166 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
2167 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
2168 return SDValue(); // no match.
2169 }
2170
2171 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
2172 // either constant or undef values that are identical for each chunk. See
2173 // if these chunks can form into a larger vspltis*.
2174
2175 // Check to see if all of the leading entries are either 0 or -1. If
2176 // neither, then this won't fit into the immediate field.
2177 bool LeadingZero = true;
2178 bool LeadingOnes = true;
2179 for (unsigned i = 0; i != Multiple-1; ++i) {
2180 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
2181
2182 LeadingZero &= isNullConstant(UniquedVals[i]);
2183 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
2184 }
2185 // Finally, check the least significant entry.
2186 if (LeadingZero) {
2187 if (!UniquedVals[Multiple-1].getNode())
2188 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
2189 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
2190 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
2191 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2192 }
2193 if (LeadingOnes) {
2194 if (!UniquedVals[Multiple-1].getNode())
2195 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
2196 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
2197 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
2198 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
2199 }
2200
2201 return SDValue();
2202 }
2203
2204 // Check to see if this buildvec has a single non-undef value in its elements.
2205 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2206 if (N->getOperand(i).isUndef()) continue;
2207 if (!OpVal.getNode())
2208 OpVal = N->getOperand(i);
2209 else if (OpVal != N->getOperand(i))
2210 return SDValue();
2211 }
2212
2213 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
2214
2215 unsigned ValSizeInBytes = EltSize;
2216 uint64_t Value = 0;
2217 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2218 Value = CN->getZExtValue();
2219 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2220 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!")((CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"
) ? static_cast<void> (0) : __assert_fail ("CN->getValueType(0) == MVT::f32 && \"Only one legal FP vector type!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2220, __PRETTY_FUNCTION__))
;
2221 Value = FloatToBits(CN->getValueAPF().convertToFloat());
2222 }
2223
2224 // If the splat value is larger than the element value, then we can never do
2225 // this splat. The only case that we could fit the replicated bits into our
2226 // immediate field for would be zero, and we prefer to use vxor for it.
2227 if (ValSizeInBytes < ByteSize) return SDValue();
2228
2229 // If the element value is larger than the splat value, check if it consists
2230 // of a repeated bit pattern of size ByteSize.
2231 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
2232 return SDValue();
2233
2234 // Properly sign extend the value.
2235 int MaskVal = SignExtend32(Value, ByteSize * 8);
2236
2237 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
2238 if (MaskVal == 0) return SDValue();
2239
2240 // Finally, if this value fits in a 5 bit sext field, return it
2241 if (SignExtend32<5>(MaskVal) == MaskVal)
2242 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
2243 return SDValue();
2244}
2245
2246/// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
2247/// amount, otherwise return -1.
2248int PPC::isQVALIGNIShuffleMask(SDNode *N) {
2249 EVT VT = N->getValueType(0);
2250 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
2251 return -1;
2252
2253 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2254
2255 // Find the first non-undef value in the shuffle mask.
2256 unsigned i;
2257 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
2258 /*search*/;
2259
2260 if (i == 4) return -1; // all undef.
2261
2262 // Otherwise, check to see if the rest of the elements are consecutively
2263 // numbered from this value.
2264 unsigned ShiftAmt = SVOp->getMaskElt(i);
2265 if (ShiftAmt < i) return -1;
2266 ShiftAmt -= i;
2267
2268 // Check the rest of the elements to see if they are consecutive.
2269 for (++i; i != 4; ++i)
2270 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
2271 return -1;
2272
2273 return ShiftAmt;
2274}
2275
2276//===----------------------------------------------------------------------===//
2277// Addressing Mode Selection
2278//===----------------------------------------------------------------------===//
2279
2280/// isIntS16Immediate - This method tests to see if the node is either a 32-bit
2281/// or 64-bit immediate, and if the value can be accurately represented as a
2282/// sign extension from a 16-bit value. If so, this returns true and the
2283/// immediate.
2284bool llvm::isIntS16Immediate(SDNode *N, int16_t &Imm) {
2285 if (!isa<ConstantSDNode>(N))
2286 return false;
2287
2288 Imm = (int16_t)cast<ConstantSDNode>(N)->getZExtValue();
2289 if (N->getValueType(0) == MVT::i32)
2290 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
2291 else
2292 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
2293}
2294bool llvm::isIntS16Immediate(SDValue Op, int16_t &Imm) {
2295 return isIntS16Immediate(Op.getNode(), Imm);
2296}
2297
2298
2299/// SelectAddressEVXRegReg - Given the specified address, check to see if it can
2300/// be represented as an indexed [r+r] operation.
2301bool PPCTargetLowering::SelectAddressEVXRegReg(SDValue N, SDValue &Base,
2302 SDValue &Index,
2303 SelectionDAG &DAG) const {
2304 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
2305 UI != E; ++UI) {
2306 if (MemSDNode *Memop = dyn_cast<MemSDNode>(*UI)) {
2307 if (Memop->getMemoryVT() == MVT::f64) {
2308 Base = N.getOperand(0);
2309 Index = N.getOperand(1);
2310 return true;
2311 }
2312 }
2313 }
2314 return false;
2315}
2316
2317/// SelectAddressRegReg - Given the specified addressed, check to see if it
2318/// can be represented as an indexed [r+r] operation. Returns false if it
2319/// can be more efficiently represented as [r+imm]. If \p EncodingAlignment is
2320/// non-zero and N can be represented by a base register plus a signed 16-bit
2321/// displacement, make a more precise judgement by checking (displacement % \p
2322/// EncodingAlignment).
2323bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
2324 SDValue &Index, SelectionDAG &DAG,
2325 unsigned EncodingAlignment) const {
2326 int16_t imm = 0;
2327 if (N.getOpcode() == ISD::ADD) {
2328 // Is there any SPE load/store (f64), which can't handle 16bit offset?
2329 // SPE load/store can only handle 8-bit offsets.
2330 if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG))
2331 return true;
2332 if (isIntS16Immediate(N.getOperand(1), imm) &&
2333 (!EncodingAlignment || !(imm % EncodingAlignment)))
2334 return false; // r+i
2335 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
2336 return false; // r+i
2337
2338 Base = N.getOperand(0);
2339 Index = N.getOperand(1);
2340 return true;
2341 } else if (N.getOpcode() == ISD::OR) {
2342 if (isIntS16Immediate(N.getOperand(1), imm) &&
2343 (!EncodingAlignment || !(imm % EncodingAlignment)))
2344 return false; // r+i can fold it if we can.
2345
2346 // If this is an or of disjoint bitfields, we can codegen this as an add
2347 // (for better address arithmetic) if the LHS and RHS of the OR are provably
2348 // disjoint.
2349 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2350
2351 if (LHSKnown.Zero.getBoolValue()) {
2352 KnownBits RHSKnown = DAG.computeKnownBits(N.getOperand(1));
2353 // If all of the bits are known zero on the LHS or RHS, the add won't
2354 // carry.
2355 if (~(LHSKnown.Zero | RHSKnown.Zero) == 0) {
2356 Base = N.getOperand(0);
2357 Index = N.getOperand(1);
2358 return true;
2359 }
2360 }
2361 }
2362
2363 return false;
2364}
2365
2366// If we happen to be doing an i64 load or store into a stack slot that has
2367// less than a 4-byte alignment, then the frame-index elimination may need to
2368// use an indexed load or store instruction (because the offset may not be a
2369// multiple of 4). The extra register needed to hold the offset comes from the
2370// register scavenger, and it is possible that the scavenger will need to use
2371// an emergency spill slot. As a result, we need to make sure that a spill slot
2372// is allocated when doing an i64 load/store into a less-than-4-byte-aligned
2373// stack slot.
2374static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
2375 // FIXME: This does not handle the LWA case.
2376 if (VT != MVT::i64)
2377 return;
2378
2379 // NOTE: We'll exclude negative FIs here, which come from argument
2380 // lowering, because there are no known test cases triggering this problem
2381 // using packed structures (or similar). We can remove this exclusion if
2382 // we find such a test case. The reason why this is so test-case driven is
2383 // because this entire 'fixup' is only to prevent crashes (from the
2384 // register scavenger) on not-really-valid inputs. For example, if we have:
2385 // %a = alloca i1
2386 // %b = bitcast i1* %a to i64*
2387 // store i64* a, i64 b
2388 // then the store should really be marked as 'align 1', but is not. If it
2389 // were marked as 'align 1' then the indexed form would have been
2390 // instruction-selected initially, and the problem this 'fixup' is preventing
2391 // won't happen regardless.
2392 if (FrameIdx < 0)
2393 return;
2394
2395 MachineFunction &MF = DAG.getMachineFunction();
2396 MachineFrameInfo &MFI = MF.getFrameInfo();
2397
2398 unsigned Align = MFI.getObjectAlignment(FrameIdx);
2399 if (Align >= 4)
2400 return;
2401
2402 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2403 FuncInfo->setHasNonRISpills();
2404}
2405
2406/// Returns true if the address N can be represented by a base register plus
2407/// a signed 16-bit displacement [r+imm], and if it is not better
2408/// represented as reg+reg. If \p EncodingAlignment is non-zero, only accept
2409/// displacements that are multiples of that value.
2410bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
2411 SDValue &Base,
2412 SelectionDAG &DAG,
2413 unsigned EncodingAlignment) const {
2414 // FIXME dl should come from parent load or store, not from address
2415 SDLoc dl(N);
2416 // If this can be more profitably realized as r+r, fail.
2417 if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
2418 return false;
2419
2420 if (N.getOpcode() == ISD::ADD) {
2421 int16_t imm = 0;
2422 if (isIntS16Immediate(N.getOperand(1), imm) &&
2423 (!EncodingAlignment || (imm % EncodingAlignment) == 0)) {
2424 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2425 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2426 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2427 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2428 } else {
2429 Base = N.getOperand(0);
2430 }
2431 return true; // [r+i]
2432 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
2433 // Match LOAD (ADD (X, Lo(G))).
2434 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2435, __PRETTY_FUNCTION__))
2435 && "Cannot handle constant offsets yet!")((!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->
getZExtValue() && "Cannot handle constant offsets yet!"
) ? static_cast<void> (0) : __assert_fail ("!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue() && \"Cannot handle constant offsets yet!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2435, __PRETTY_FUNCTION__))
;
2436 Disp = N.getOperand(1).getOperand(0); // The global address.
2437 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2440, __PRETTY_FUNCTION__))
2438 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2440, __PRETTY_FUNCTION__))
2439 Disp.getOpcode() == ISD::TargetConstantPool ||((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2440, __PRETTY_FUNCTION__))
2440 Disp.getOpcode() == ISD::TargetJumpTable)((Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode
() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::
TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable
) ? static_cast<void> (0) : __assert_fail ("Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2440, __PRETTY_FUNCTION__))
;
2441 Base = N.getOperand(0);
2442 return true; // [&g+r]
2443 }
2444 } else if (N.getOpcode() == ISD::OR) {
2445 int16_t imm = 0;
2446 if (isIntS16Immediate(N.getOperand(1), imm) &&
2447 (!EncodingAlignment || (imm % EncodingAlignment) == 0)) {
2448 // If this is an or of disjoint bitfields, we can codegen this as an add
2449 // (for better address arithmetic) if the LHS and RHS of the OR are
2450 // provably disjoint.
2451 KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0));
2452
2453 if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
2454 // If all of the bits are known zero on the LHS or RHS, the add won't
2455 // carry.
2456 if (FrameIndexSDNode *FI =
2457 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
2458 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2459 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2460 } else {
2461 Base = N.getOperand(0);
2462 }
2463 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
2464 return true;
2465 }
2466 }
2467 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
2468 // Loading from a constant address.
2469
2470 // If this address fits entirely in a 16-bit sext immediate field, codegen
2471 // this as "d, 0"
2472 int16_t Imm;
2473 if (isIntS16Immediate(CN, Imm) &&
2474 (!EncodingAlignment || (Imm % EncodingAlignment) == 0)) {
2475 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
2476 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2477 CN->getValueType(0));
2478 return true;
2479 }
2480
2481 // Handle 32-bit sext immediates with LIS + addr mode.
2482 if ((CN->getValueType(0) == MVT::i32 ||
2483 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
2484 (!EncodingAlignment || (CN->getZExtValue() % EncodingAlignment) == 0)) {
2485 int Addr = (int)CN->getZExtValue();
2486
2487 // Otherwise, break this down into an LIS + disp.
2488 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
2489
2490 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
2491 MVT::i32);
2492 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
2493 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
2494 return true;
2495 }
2496 }
2497
2498 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
2499 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
2500 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
2501 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
2502 } else
2503 Base = N;
2504 return true; // [r+0]
2505}
2506
2507/// SelectAddressRegRegOnly - Given the specified addressed, force it to be
2508/// represented as an indexed [r+r] operation.
2509bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
2510 SDValue &Index,
2511 SelectionDAG &DAG) const {
2512 // Check to see if we can easily represent this as an [r+r] address. This
2513 // will fail if it thinks that the address is more profitably represented as
2514 // reg+imm, e.g. where imm = 0.
2515 if (SelectAddressRegReg(N, Base, Index, DAG))
2516 return true;
2517
2518 // If the address is the result of an add, we will utilize the fact that the
2519 // address calculation includes an implicit add. However, we can reduce
2520 // register pressure if we do not materialize a constant just for use as the
2521 // index register. We only get rid of the add if it is not an add of a
2522 // value and a 16-bit signed constant and both have a single use.
2523 int16_t imm = 0;
2524 if (N.getOpcode() == ISD::ADD &&
2525 (!isIntS16Immediate(N.getOperand(1), imm) ||
2526 !N.getOperand(1).hasOneUse() || !N.getOperand(0).hasOneUse())) {
2527 Base = N.getOperand(0);
2528 Index = N.getOperand(1);
2529 return true;
2530 }
2531
2532 // Otherwise, do it the hard way, using R0 as the base register.
2533 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
2534 N.getValueType());
2535 Index = N;
2536 return true;
2537}
2538
2539/// Returns true if we should use a direct load into vector instruction
2540/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
2541static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
2542
2543 // If there are any other uses other than scalar to vector, then we should
2544 // keep it as a scalar load -> direct move pattern to prevent multiple
2545 // loads.
2546 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
2547 if (!LD)
2548 return false;
2549
2550 EVT MemVT = LD->getMemoryVT();
2551 if (!MemVT.isSimple())
2552 return false;
2553 switch(MemVT.getSimpleVT().SimpleTy) {
2554 case MVT::i64:
2555 break;
2556 case MVT::i32:
2557 if (!ST.hasP8Vector())
2558 return false;
2559 break;
2560 case MVT::i16:
2561 case MVT::i8:
2562 if (!ST.hasP9Vector())
2563 return false;
2564 break;
2565 default:
2566 return false;
2567 }
2568
2569 SDValue LoadedVal(N, 0);
2570 if (!LoadedVal.hasOneUse())
2571 return false;
2572
2573 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end();
2574 UI != UE; ++UI)
2575 if (UI.getUse().get().getResNo() == 0 &&
2576 UI->getOpcode() != ISD::SCALAR_TO_VECTOR)
2577 return false;
2578
2579 return true;
2580}
2581
2582/// getPreIndexedAddressParts - returns true by value, base pointer and
2583/// offset pointer and addressing mode by reference if the node's address
2584/// can be legally represented as pre-indexed load / store address.
2585bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
2586 SDValue &Offset,
2587 ISD::MemIndexedMode &AM,
2588 SelectionDAG &DAG) const {
2589 if (DisablePPCPreinc) return false;
2590
2591 bool isLoad = true;
2592 SDValue Ptr;
2593 EVT VT;
2594 unsigned Alignment;
2595 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2596 Ptr = LD->getBasePtr();
2597 VT = LD->getMemoryVT();
2598 Alignment = LD->getAlignment();
2599 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2600 Ptr = ST->getBasePtr();
2601 VT = ST->getMemoryVT();
2602 Alignment = ST->getAlignment();
2603 isLoad = false;
2604 } else
2605 return false;
2606
2607 // Do not generate pre-inc forms for specific loads that feed scalar_to_vector
2608 // instructions because we can fold these into a more efficient instruction
2609 // instead, (such as LXSD).
2610 if (isLoad && usePartialVectorLoads(N, Subtarget)) {
2611 return false;
2612 }
2613
2614 // PowerPC doesn't have preinc load/store instructions for vectors (except
2615 // for QPX, which does have preinc r+r forms).
2616 if (VT.isVector()) {
2617 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
2618 return false;
2619 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
2620 AM = ISD::PRE_INC;
2621 return true;
2622 }
2623 }
2624
2625 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
2626 // Common code will reject creating a pre-inc form if the base pointer
2627 // is a frame index, or if N is a store and the base pointer is either
2628 // the same as or a predecessor of the value being stored. Check for
2629 // those situations here, and try with swapped Base/Offset instead.
2630 bool Swap = false;
2631
2632 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
2633 Swap = true;
2634 else if (!isLoad) {
2635 SDValue Val = cast<StoreSDNode>(N)->getValue();
2636 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
2637 Swap = true;
2638 }
2639
2640 if (Swap)
2641 std::swap(Base, Offset);
2642
2643 AM = ISD::PRE_INC;
2644 return true;
2645 }
2646
2647 // LDU/STU can only handle immediates that are a multiple of 4.
2648 if (VT != MVT::i64) {
2649 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 0))
2650 return false;
2651 } else {
2652 // LDU/STU need an address with at least 4-byte alignment.
2653 if (Alignment < 4)
2654 return false;
2655
2656 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, 4))
2657 return false;
2658 }
2659
2660 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2661 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
2662 // sext i32 to i64 when addr mode is r+i.
2663 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
2664 LD->getExtensionType() == ISD::SEXTLOAD &&
2665 isa<ConstantSDNode>(Offset))
2666 return false;
2667 }
2668
2669 AM = ISD::PRE_INC;
2670 return true;
2671}
2672
2673//===----------------------------------------------------------------------===//
2674// LowerOperation implementation
2675//===----------------------------------------------------------------------===//
2676
2677/// Return true if we should reference labels using a PICBase, set the HiOpFlags
2678/// and LoOpFlags to the target MO flags.
2679static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget,
2680 unsigned &HiOpFlags, unsigned &LoOpFlags,
2681 const GlobalValue *GV = nullptr) {
2682 HiOpFlags = PPCII::MO_HA;
2683 LoOpFlags = PPCII::MO_LO;
2684
2685 // Don't use the pic base if not in PIC relocation model.
2686 if (IsPIC) {
2687 HiOpFlags |= PPCII::MO_PIC_FLAG;
2688 LoOpFlags |= PPCII::MO_PIC_FLAG;
2689 }
2690
2691 // If this is a reference to a global value that requires a non-lazy-ptr, make
2692 // sure that instruction lowering adds it.
2693 if (GV && Subtarget.hasLazyResolverStub(GV)) {
2694 HiOpFlags |= PPCII::MO_NLP_FLAG;
2695 LoOpFlags |= PPCII::MO_NLP_FLAG;
2696
2697 if (GV->hasHiddenVisibility()) {
2698 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2699 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
2700 }
2701 }
2702}
2703
2704static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
2705 SelectionDAG &DAG) {
2706 SDLoc DL(HiPart);
2707 EVT PtrVT = HiPart.getValueType();
2708 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
2709
2710 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
2711 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
2712
2713 // With PIC, the first instruction is actually "GR+hi(&G)".
2714 if (isPIC)
2715 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
2716 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
2717
2718 // Generate non-pic code that has direct accesses to the constant pool.
2719 // The address of the global is just (hi(&g)+lo(&g)).
2720 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2721}
2722
2723static void setUsesTOCBasePtr(MachineFunction &MF) {
2724 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2725 FuncInfo->setUsesTOCBasePtr();
2726}
2727
2728static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2729 setUsesTOCBasePtr(DAG.getMachineFunction());
2730}
2731
2732SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
2733 SDValue GA) const {
2734 const bool Is64Bit = Subtarget.isPPC64();
2735 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2736 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
2737 : Subtarget.isAIXABI()
2738 ? DAG.getRegister(PPC::R2, VT)
2739 : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2740 SDValue Ops[] = { GA, Reg };
2741 return DAG.getMemIntrinsicNode(
2742 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2743 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0,
2744 MachineMemOperand::MOLoad);
2745}
2746
2747SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2748 SelectionDAG &DAG) const {
2749 EVT PtrVT = Op.getValueType();
2750 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2751 const Constant *C = CP->getConstVal();
2752
2753 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
2754 // The actual address of the GlobalValue is stored in the TOC.
2755 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
2756 setUsesTOCBasePtr(DAG);
2757 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2758 return getTOCEntry(DAG, SDLoc(CP), GA);
2759 }
2760
2761 unsigned MOHiFlag, MOLoFlag;
2762 bool IsPIC = isPositionIndependent();
2763 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2764
2765 if (IsPIC && Subtarget.isSVR4ABI()) {
2766 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2767 PPCII::MO_PIC_FLAG);
2768 return getTOCEntry(DAG, SDLoc(CP), GA);
2769 }
2770
2771 SDValue CPIHi =
2772 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2773 SDValue CPILo =
2774 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2775 return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
2776}
2777
2778// For 64-bit PowerPC, prefer the more compact relative encodings.
2779// This trades 32 bits per jump table entry for one or two instructions
2780// on the jump site.
2781unsigned PPCTargetLowering::getJumpTableEncoding() const {
2782 if (isJumpTableRelative())
2783 return MachineJumpTableInfo::EK_LabelDifference32;
2784
2785 return TargetLowering::getJumpTableEncoding();
2786}
2787
2788bool PPCTargetLowering::isJumpTableRelative() const {
2789 if (UseAbsoluteJumpTables)
2790 return false;
2791 if (Subtarget.isPPC64() || Subtarget.isAIXABI())
2792 return true;
2793 return TargetLowering::isJumpTableRelative();
2794}
2795
2796SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2797 SelectionDAG &DAG) const {
2798 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
2799 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2800
2801 switch (getTargetMachine().getCodeModel()) {
2802 case CodeModel::Small:
2803 case CodeModel::Medium:
2804 return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
2805 default:
2806 return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
2807 getPointerTy(DAG.getDataLayout()));
2808 }
2809}
2810
2811const MCExpr *
2812PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2813 unsigned JTI,
2814 MCContext &Ctx) const {
2815 if (!Subtarget.isPPC64() || Subtarget.isAIXABI())
2816 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2817
2818 switch (getTargetMachine().getCodeModel()) {
2819 case CodeModel::Small:
2820 case CodeModel::Medium:
2821 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2822 default:
2823 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2824 }
2825}
2826
2827SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2828 EVT PtrVT = Op.getValueType();
2829 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2830
2831 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
2832 // The actual address of the GlobalValue is stored in the TOC.
2833 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
2834 setUsesTOCBasePtr(DAG);
2835 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2836 return getTOCEntry(DAG, SDLoc(JT), GA);
2837 }
2838
2839 unsigned MOHiFlag, MOLoFlag;
2840 bool IsPIC = isPositionIndependent();
2841 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2842
2843 if (IsPIC && Subtarget.isSVR4ABI()) {
2844 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2845 PPCII::MO_PIC_FLAG);
2846 return getTOCEntry(DAG, SDLoc(GA), GA);
2847 }
2848
2849 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2850 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2851 return LowerLabelRef(JTIHi, JTILo, IsPIC, DAG);
2852}
2853
2854SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2855 SelectionDAG &DAG) const {
2856 EVT PtrVT = Op.getValueType();
2857 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2858 const BlockAddress *BA = BASDN->getBlockAddress();
2859
2860 // 64-bit SVR4 ABI and AIX ABI code are always position-independent.
2861 // The actual BlockAddress is stored in the TOC.
2862 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
2863 setUsesTOCBasePtr(DAG);
2864 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2865 return getTOCEntry(DAG, SDLoc(BASDN), GA);
2866 }
2867
2868 // 32-bit position-independent ELF stores the BlockAddress in the .got.
2869 if (Subtarget.is32BitELFABI() && isPositionIndependent())
2870 return getTOCEntry(
2871 DAG, SDLoc(BASDN),
2872 DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset()));
2873
2874 unsigned MOHiFlag, MOLoFlag;
2875 bool IsPIC = isPositionIndependent();
2876 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag);
2877 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2878 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2879 return LowerLabelRef(TgtBAHi, TgtBALo, IsPIC, DAG);
2880}
2881
2882SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2883 SelectionDAG &DAG) const {
2884 // FIXME: TLS addresses currently use medium model code sequences,
2885 // which is the most useful form. Eventually support for small and
2886 // large models could be added if users need it, at the cost of
2887 // additional complexity.
2888 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2889 if (DAG.getTarget().useEmulatedTLS())
2890 return LowerToTLSEmulatedModel(GA, DAG);
2891
2892 SDLoc dl(GA);
2893 const GlobalValue *GV = GA->getGlobal();
2894 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2895 bool is64bit = Subtarget.isPPC64();
2896 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2897 PICLevel::Level picLevel = M->getPICLevel();
2898
2899 const TargetMachine &TM = getTargetMachine();
2900 TLSModel::Model Model = TM.getTLSModel(GV);
2901
2902 if (Model == TLSModel::LocalExec) {
2903 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2904 PPCII::MO_TPREL_HA);
2905 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2906 PPCII::MO_TPREL_LO);
2907 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64)
2908 : DAG.getRegister(PPC::R2, MVT::i32);
2909
2910 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2911 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2912 }
2913
2914 if (Model == TLSModel::InitialExec) {
2915 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2916 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2917 PPCII::MO_TLS);
2918 SDValue GOTPtr;
2919 if (is64bit) {
2920 setUsesTOCBasePtr(DAG);
2921 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2922 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2923 PtrVT, GOTReg, TGA);
2924 } else {
2925 if (!TM.isPositionIndependent())
2926 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2927 else if (picLevel == PICLevel::SmallPIC)
2928 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2929 else
2930 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2931 }
2932 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2933 PtrVT, TGA, GOTPtr);
2934 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2935 }
2936
2937 if (Model == TLSModel::GeneralDynamic) {
2938 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2939 SDValue GOTPtr;
2940 if (is64bit) {
2941 setUsesTOCBasePtr(DAG);
2942 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2943 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2944 GOTReg, TGA);
2945 } else {
2946 if (picLevel == PICLevel::SmallPIC)
2947 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2948 else
2949 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2950 }
2951 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2952 GOTPtr, TGA, TGA);
2953 }
2954
2955 if (Model == TLSModel::LocalDynamic) {
2956 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2957 SDValue GOTPtr;
2958 if (is64bit) {
2959 setUsesTOCBasePtr(DAG);
2960 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2961 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2962 GOTReg, TGA);
2963 } else {
2964 if (picLevel == PICLevel::SmallPIC)
2965 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2966 else
2967 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2968 }
2969 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2970 PtrVT, GOTPtr, TGA, TGA);
2971 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2972 PtrVT, TLSAddr, TGA);
2973 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2974 }
2975
2976 llvm_unreachable("Unknown TLS model!")::llvm::llvm_unreachable_internal("Unknown TLS model!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 2976)
;
2977}
2978
2979SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2980 SelectionDAG &DAG) const {
2981 EVT PtrVT = Op.getValueType();
2982 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2983 SDLoc DL(GSDN);
2984 const GlobalValue *GV = GSDN->getGlobal();
2985
2986 // 64-bit SVR4 ABI & AIX ABI code is always position-independent.
2987 // The actual address of the GlobalValue is stored in the TOC.
2988 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
2989 setUsesTOCBasePtr(DAG);
2990 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2991 return getTOCEntry(DAG, DL, GA);
2992 }
2993
2994 unsigned MOHiFlag, MOLoFlag;
2995 bool IsPIC = isPositionIndependent();
2996 getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV);
2997
2998 if (IsPIC && Subtarget.isSVR4ABI()) {
2999 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
3000 GSDN->getOffset(),
3001 PPCII::MO_PIC_FLAG);
3002 return getTOCEntry(DAG, DL, GA);
3003 }
3004
3005 SDValue GAHi =
3006 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
3007 SDValue GALo =
3008 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
3009
3010 SDValue Ptr = LowerLabelRef(GAHi, GALo, IsPIC, DAG);
3011
3012 // If the global reference is actually to a non-lazy-pointer, we have to do an
3013 // extra load to get the address of the global.
3014 if (MOHiFlag & PPCII::MO_NLP_FLAG)
3015 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo());
3016 return Ptr;
3017}
3018
3019SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3020 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3021 SDLoc dl(Op);
3022
3023 if (Op.getValueType() == MVT::v2i64) {
3024 // When the operands themselves are v2i64 values, we need to do something
3025 // special because VSX has no underlying comparison operations for these.
3026 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
3027 // Equality can be handled by casting to the legal type for Altivec
3028 // comparisons, everything else needs to be expanded.
3029 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
3030 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
3031 DAG.getSetCC(dl, MVT::v4i32,
3032 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
3033 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
3034 CC));
3035 }
3036
3037 return SDValue();
3038 }
3039
3040 // We handle most of these in the usual way.
3041 return Op;
3042 }
3043
3044 // If we're comparing for equality to zero, expose the fact that this is
3045 // implemented as a ctlz/srl pair on ppc, so that the dag combiner can
3046 // fold the new nodes.
3047 if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
3048 return V;
3049
3050 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
3051 // Leave comparisons against 0 and -1 alone for now, since they're usually
3052 // optimized. FIXME: revisit this when we can custom lower all setcc
3053 // optimizations.
3054 if (C->isAllOnesValue() || C->isNullValue())
3055 return SDValue();
3056 }
3057
3058 // If we have an integer seteq/setne, turn it into a compare against zero
3059 // by xor'ing the rhs with the lhs, which is faster than setting a
3060 // condition register, reading it back out, and masking the correct bit. The
3061 // normal approach here uses sub to do this instead of xor. Using xor exposes
3062 // the result to other bit-twiddling opportunities.
3063 EVT LHSVT = Op.getOperand(0).getValueType();
3064 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
3065 EVT VT = Op.getValueType();
3066 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
3067 Op.getOperand(1));
3068 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
3069 }
3070 return SDValue();
3071}
3072
3073SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3074 SDNode *Node = Op.getNode();
3075 EVT VT = Node->getValueType(0);
3076 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3077 SDValue InChain = Node->getOperand(0);
3078 SDValue VAListPtr = Node->getOperand(1);
3079 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3080 SDLoc dl(Node);
3081
3082 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")((!Subtarget.isPPC64() && "LowerVAARG is PPC32 only")
? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVAARG is PPC32 only\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3082, __PRETTY_FUNCTION__))
;
3083
3084 // gpr_index
3085 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3086 VAListPtr, MachinePointerInfo(SV), MVT::i8);
3087 InChain = GprIndex.getValue(1);
3088
3089 if (VT == MVT::i64) {
3090 // Check if GprIndex is even
3091 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
3092 DAG.getConstant(1, dl, MVT::i32));
3093 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
3094 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
3095 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
3096 DAG.getConstant(1, dl, MVT::i32));
3097 // Align GprIndex to be even if it isn't
3098 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
3099 GprIndex);
3100 }
3101
3102 // fpr index is 1 byte after gpr
3103 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3104 DAG.getConstant(1, dl, MVT::i32));
3105
3106 // fpr
3107 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3108 FprPtr, MachinePointerInfo(SV), MVT::i8);
3109 InChain = FprIndex.getValue(1);
3110
3111 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3112 DAG.getConstant(8, dl, MVT::i32));
3113
3114 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
3115 DAG.getConstant(4, dl, MVT::i32));
3116
3117 // areas
3118 SDValue OverflowArea =
3119 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo());
3120 InChain = OverflowArea.getValue(1);
3121
3122 SDValue RegSaveArea =
3123 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo());
3124 InChain = RegSaveArea.getValue(1);
3125
3126 // select overflow_area if index > 8
3127 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
3128 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
3129
3130 // adjustment constant gpr_index * 4/8
3131 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
3132 VT.isInteger() ? GprIndex : FprIndex,
3133 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3134 MVT::i32));
3135
3136 // OurReg = RegSaveArea + RegConstant
3137 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
3138 RegConstant);
3139
3140 // Floating types are 32 bytes into RegSaveArea
3141 if (VT.isFloatingPoint())
3142 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
3143 DAG.getConstant(32, dl, MVT::i32));
3144
3145 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
3146 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3147 VT.isInteger() ? GprIndex : FprIndex,
3148 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
3149 MVT::i32));
3150
3151 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
3152 VT.isInteger() ? VAListPtr : FprPtr,
3153 MachinePointerInfo(SV), MVT::i8);
3154
3155 // determine if we should load from reg_save_area or overflow_area
3156 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
3157
3158 // increase overflow_area by 4/8 if gpr/fpr > 8
3159 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
3160 DAG.getConstant(VT.isInteger() ? 4 : 8,
3161 dl, MVT::i32));
3162
3163 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
3164 OverflowAreaPlusN);
3165
3166 InChain = DAG.getTruncStore(InChain, dl, OverflowArea, OverflowAreaPtr,
3167 MachinePointerInfo(), MVT::i32);
3168
3169 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo());
3170}
3171
3172SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3173 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only")((!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.isPPC64() && \"LowerVACOPY is PPC32 only\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3173, __PRETTY_FUNCTION__))
;
3174
3175 // We have to copy the entire va_list struct:
3176 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
3177 return DAG.getMemcpy(Op.getOperand(0), Op,
3178 Op.getOperand(1), Op.getOperand(2),
3179 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
3180 false, MachinePointerInfo(), MachinePointerInfo());
3181}
3182
3183SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
3184 SelectionDAG &DAG) const {
3185 if (Subtarget.isAIXABI())
3186 report_fatal_error("ADJUST_TRAMPOLINE operation is not supported on AIX.");
3187
3188 return Op.getOperand(0);
3189}
3190
3191SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
3192 SelectionDAG &DAG) const {
3193 if (Subtarget.isAIXABI())
3194 report_fatal_error("INIT_TRAMPOLINE operation is not supported on AIX.");
3195
3196 SDValue Chain = Op.getOperand(0);
3197 SDValue Trmp = Op.getOperand(1); // trampoline
3198 SDValue FPtr = Op.getOperand(2); // nested function
3199 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
3200 SDLoc dl(Op);
3201
3202 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3203 bool isPPC64 = (PtrVT == MVT::i64);
3204 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
3205
3206 TargetLowering::ArgListTy Args;
3207 TargetLowering::ArgListEntry Entry;
3208
3209 Entry.Ty = IntPtrTy;
3210 Entry.Node = Trmp; Args.push_back(Entry);
3211
3212 // TrampSize == (isPPC64 ? 48 : 40);
3213 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
3214 isPPC64 ? MVT::i64 : MVT::i32);
3215 Args.push_back(Entry);
3216
3217 Entry.Node = FPtr; Args.push_back(Entry);
3218 Entry.Node = Nest; Args.push_back(Entry);
3219
3220 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
3221 TargetLowering::CallLoweringInfo CLI(DAG);
3222 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3223 CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3224 DAG.getExternalSymbol("__trampoline_setup", PtrVT), std::move(Args));
3225
3226 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3227 return CallResult.second;
3228}
3229
3230SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3231 MachineFunction &MF = DAG.getMachineFunction();
3232 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3233 EVT PtrVT = getPointerTy(MF.getDataLayout());
3234
3235 SDLoc dl(Op);
3236
3237 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
3238 // vastart just stores the address of the VarArgsFrameIndex slot into the
3239 // memory location argument.
3240 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3241 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3242 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3243 MachinePointerInfo(SV));
3244 }
3245
3246 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
3247 // We suppose the given va_list is already allocated.
3248 //
3249 // typedef struct {
3250 // char gpr; /* index into the array of 8 GPRs
3251 // * stored in the register save area
3252 // * gpr=0 corresponds to r3,
3253 // * gpr=1 to r4, etc.
3254 // */
3255 // char fpr; /* index into the array of 8 FPRs
3256 // * stored in the register save area
3257 // * fpr=0 corresponds to f1,
3258 // * fpr=1 to f2, etc.
3259 // */
3260 // char *overflow_arg_area;
3261 // /* location on stack that holds
3262 // * the next overflow argument
3263 // */
3264 // char *reg_save_area;
3265 // /* where r3:r10 and f1:f8 (if saved)
3266 // * are stored
3267 // */
3268 // } va_list[1];
3269
3270 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
3271 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
3272 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
3273 PtrVT);
3274 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
3275 PtrVT);
3276
3277 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
3278 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
3279
3280 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
3281 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
3282
3283 uint64_t FPROffset = 1;
3284 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
3285
3286 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3287
3288 // Store first byte : number of int regs
3289 SDValue firstStore =
3290 DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1),
3291 MachinePointerInfo(SV), MVT::i8);
3292 uint64_t nextOffset = FPROffset;
3293 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
3294 ConstFPROffset);
3295
3296 // Store second byte : number of float regs
3297 SDValue secondStore =
3298 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
3299 MachinePointerInfo(SV, nextOffset), MVT::i8);
3300 nextOffset += StackOffset;
3301 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
3302
3303 // Store second word : arguments given on stack
3304 SDValue thirdStore = DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
3305 MachinePointerInfo(SV, nextOffset));
3306 nextOffset += FrameOffset;
3307 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
3308
3309 // Store third word : arguments given in registers
3310 return DAG.getStore(thirdStore, dl, FR, nextPtr,
3311 MachinePointerInfo(SV, nextOffset));
3312}
3313
3314/// FPR - The set of FP registers that should be allocated for arguments
3315/// on Darwin and AIX.
3316static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3317 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3318 PPC::F11, PPC::F12, PPC::F13};
3319
3320/// QFPR - The set of QPX registers that should be allocated for arguments.
3321static const MCPhysReg QFPR[] = {
3322 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
3323 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
3324
3325/// CalculateStackSlotSize - Calculates the size reserved for this argument on
3326/// the stack.
3327static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
3328 unsigned PtrByteSize) {
3329 unsigned ArgSize = ArgVT.getStoreSize();
3330 if (Flags.isByVal())
3331 ArgSize = Flags.getByValSize();
3332
3333 // Round up to multiples of the pointer size, except for array members,
3334 // which are always packed.
3335 if (!Flags.isInConsecutiveRegs())
3336 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3337
3338 return ArgSize;
3339}
3340
3341/// CalculateStackSlotAlignment - Calculates the alignment of this argument
3342/// on the stack.
3343static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
3344 ISD::ArgFlagsTy Flags,
3345 unsigned PtrByteSize) {
3346 unsigned Align = PtrByteSize;
3347
3348 // Altivec parameters are padded to a 16 byte boundary.
3349 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3350 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3351 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3352 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3353 Align = 16;
3354 // QPX vector types stored in double-precision are padded to a 32 byte
3355 // boundary.
3356 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
3357 Align = 32;
3358
3359 // ByVal parameters are aligned as requested.
3360 if (Flags.isByVal()) {
3361 unsigned BVAlign = Flags.getByValAlign();
3362 if (BVAlign > PtrByteSize) {
3363 if (BVAlign % PtrByteSize != 0)
3364 llvm_unreachable(::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3365)
3365 "ByVal alignment is not a multiple of the pointer size")::llvm::llvm_unreachable_internal("ByVal alignment is not a multiple of the pointer size"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3365)
;
3366
3367 Align = BVAlign;
3368 }
3369 }
3370
3371 // Array members are always packed to their original alignment.
3372 if (Flags.isInConsecutiveRegs()) {
3373 // If the array member was split into multiple registers, the first
3374 // needs to be aligned to the size of the full type. (Except for
3375 // ppcf128, which is only aligned as its f64 components.)
3376 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
3377 Align = OrigVT.getStoreSize();
3378 else
3379 Align = ArgVT.getStoreSize();
3380 }
3381
3382 return Align;
3383}
3384
3385/// CalculateStackSlotUsed - Return whether this argument will use its
3386/// stack slot (instead of being passed in registers). ArgOffset,
3387/// AvailableFPRs, and AvailableVRs must hold the current argument
3388/// position, and will be updated to account for this argument.
3389static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
3390 ISD::ArgFlagsTy Flags,
3391 unsigned PtrByteSize,
3392 unsigned LinkageSize,
3393 unsigned ParamAreaSize,
3394 unsigned &ArgOffset,
3395 unsigned &AvailableFPRs,
3396 unsigned &AvailableVRs, bool HasQPX) {
3397 bool UseMemory = false;
3398
3399 // Respect alignment of argument on the stack.
3400 unsigned Align =
3401 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
3402 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3403 // If there's no space left in the argument save area, we must
3404 // use memory (this check also catches zero-sized arguments).
3405 if (ArgOffset >= LinkageSize + ParamAreaSize)
3406 UseMemory = true;
3407
3408 // Allocate argument on the stack.
3409 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3410 if (Flags.isInConsecutiveRegsLast())
3411 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3412 // If we overran the argument save area, we must use memory
3413 // (this check catches arguments passed partially in memory)
3414 if (ArgOffset > LinkageSize + ParamAreaSize)
3415 UseMemory = true;
3416
3417 // However, if the argument is actually passed in an FPR or a VR,
3418 // we don't use memory after all.
3419 if (!Flags.isByVal()) {
3420 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
3421 // QPX registers overlap with the scalar FP registers.
3422 (HasQPX && (ArgVT == MVT::v4f32 ||
3423 ArgVT == MVT::v4f64 ||
3424 ArgVT == MVT::v4i1)))
3425 if (AvailableFPRs > 0) {
3426 --AvailableFPRs;
3427 return false;
3428 }
3429 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3430 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3431 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
3432 ArgVT == MVT::v1i128 || ArgVT == MVT::f128)
3433 if (AvailableVRs > 0) {
3434 --AvailableVRs;
3435 return false;
3436 }
3437 }
3438
3439 return UseMemory;
3440}
3441
3442/// EnsureStackAlignment - Round stack frame size up from NumBytes to
3443/// ensure minimum alignment required for target.
3444static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
3445 unsigned NumBytes) {
3446 unsigned TargetAlign = Lowering->getStackAlignment();
3447 unsigned AlignMask = TargetAlign - 1;
3448 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3449 return NumBytes;
3450}
3451
3452SDValue PPCTargetLowering::LowerFormalArguments(
3453 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3454 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3455 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3456 if (Subtarget.isAIXABI())
3457 return LowerFormalArguments_AIX(Chain, CallConv, isVarArg, Ins, dl, DAG,
3458 InVals);
3459 if (Subtarget.is64BitELFABI())
3460 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3461 InVals);
3462 if (Subtarget.is32BitELFABI())
3463 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3464 InVals);
3465
3466 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, dl, DAG,
3467 InVals);
3468}
3469
3470SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3471 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3472 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3473 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3474
3475 // 32-bit SVR4 ABI Stack Frame Layout:
3476 // +-----------------------------------+
3477 // +--> | Back chain |
3478 // | +-----------------------------------+
3479 // | | Floating-point register save area |
3480 // | +-----------------------------------+
3481 // | | General register save area |
3482 // | +-----------------------------------+
3483 // | | CR save word |
3484 // | +-----------------------------------+
3485 // | | VRSAVE save word |
3486 // | +-----------------------------------+
3487 // | | Alignment padding |
3488 // | +-----------------------------------+
3489 // | | Vector register save area |
3490 // | +-----------------------------------+
3491 // | | Local variable space |
3492 // | +-----------------------------------+
3493 // | | Parameter list area |
3494 // | +-----------------------------------+
3495 // | | LR save word |
3496 // | +-----------------------------------+
3497 // SP--> +--- | Back chain |
3498 // +-----------------------------------+
3499 //
3500 // Specifications:
3501 // System V Application Binary Interface PowerPC Processor Supplement
3502 // AltiVec Technology Programming Interface Manual
3503
3504 MachineFunction &MF = DAG.getMachineFunction();
3505 MachineFrameInfo &MFI = MF.getFrameInfo();
3506 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3507
3508 EVT PtrVT = getPointerTy(MF.getDataLayout());
3509 // Potential tail calls could cause overwriting of argument stack slots.
3510 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3511 (CallConv == CallingConv::Fast));
3512 unsigned PtrByteSize = 4;
3513
3514 // Assign locations to all of the incoming arguments.
3515 SmallVector<CCValAssign, 16> ArgLocs;
3516 PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3517 *DAG.getContext());
3518
3519 // Reserve space for the linkage area on the stack.
3520 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3521 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
3522 if (useSoftFloat())
3523 CCInfo.PreAnalyzeFormalArguments(Ins);
3524
3525 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
3526 CCInfo.clearWasPPCF128();
3527
3528 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3529 CCValAssign &VA = ArgLocs[i];
3530
3531 // Arguments stored in registers.
3532 if (VA.isRegLoc()) {
3533 const TargetRegisterClass *RC;
3534 EVT ValVT = VA.getValVT();
3535
3536 switch (ValVT.getSimpleVT().SimpleTy) {
3537 default:
3538 llvm_unreachable("ValVT not supported by formal arguments Lowering")::llvm::llvm_unreachable_internal("ValVT not supported by formal arguments Lowering"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3538)
;
3539 case MVT::i1:
3540 case MVT::i32:
3541 RC = &PPC::GPRCRegClass;
3542 break;
3543 case MVT::f32:
3544 if (Subtarget.hasP8Vector())
3545 RC = &PPC::VSSRCRegClass;
3546 else if (Subtarget.hasSPE())
3547 RC = &PPC::GPRCRegClass;
3548 else
3549 RC = &PPC::F4RCRegClass;
3550 break;
3551 case MVT::f64:
3552 if (Subtarget.hasVSX())
3553 RC = &PPC::VSFRCRegClass;
3554 else if (Subtarget.hasSPE())
3555 // SPE passes doubles in GPR pairs.
3556 RC = &PPC::GPRCRegClass;
3557 else
3558 RC = &PPC::F8RCRegClass;
3559 break;
3560 case MVT::v16i8:
3561 case MVT::v8i16:
3562 case MVT::v4i32:
3563 RC = &PPC::VRRCRegClass;
3564 break;
3565 case MVT::v4f32:
3566 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
3567 break;
3568 case MVT::v2f64:
3569 case MVT::v2i64:
3570 RC = &PPC::VRRCRegClass;
3571 break;
3572 case MVT::v4f64:
3573 RC = &PPC::QFRCRegClass;
3574 break;
3575 case MVT::v4i1:
3576 RC = &PPC::QBRCRegClass;
3577 break;
3578 }
3579
3580 SDValue ArgValue;
3581 // Transform the arguments stored in physical registers into
3582 // virtual ones.
3583 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) {
3584 assert(i + 1 < e && "No second half of double precision argument")((i + 1 < e && "No second half of double precision argument"
) ? static_cast<void> (0) : __assert_fail ("i + 1 < e && \"No second half of double precision argument\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3584, __PRETTY_FUNCTION__))
;
3585 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC);
3586 unsigned RegHi = MF.addLiveIn(ArgLocs[++i].getLocReg(), RC);
3587 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32);
3588 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32);
3589 if (!Subtarget.isLittleEndian())
3590 std::swap (ArgValueLo, ArgValueHi);
3591 ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo,
3592 ArgValueHi);
3593 } else {
3594 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3595 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
3596 ValVT == MVT::i1 ? MVT::i32 : ValVT);
3597 if (ValVT == MVT::i1)
3598 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
3599 }
3600
3601 InVals.push_back(ArgValue);
3602 } else {
3603 // Argument stored in memory.
3604 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3604, __PRETTY_FUNCTION__))
;
3605
3606 // Get the extended size of the argument type in stack
3607 unsigned ArgSize = VA.getLocVT().getStoreSize();
3608 // Get the actual size of the argument type
3609 unsigned ObjSize = VA.getValVT().getStoreSize();
3610 unsigned ArgOffset = VA.getLocMemOffset();
3611 // Stack objects in PPC32 are right justified.
3612 ArgOffset += ArgSize - ObjSize;
3613 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, isImmutable);
3614
3615 // Create load nodes to retrieve arguments from the stack.
3616 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3617 InVals.push_back(
3618 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
3619 }
3620 }
3621
3622 // Assign locations to all of the incoming aggregate by value arguments.
3623 // Aggregates passed by value are stored in the local variable space of the
3624 // caller's stack frame, right above the parameter list area.
3625 SmallVector<CCValAssign, 16> ByValArgLocs;
3626 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3627 ByValArgLocs, *DAG.getContext());
3628
3629 // Reserve stack space for the allocations in CCInfo.
3630 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3631
3632 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
3633
3634 // Area that is at least reserved in the caller of this function.
3635 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
3636 MinReservedArea = std::max(MinReservedArea, LinkageSize);
3637
3638 // Set the size that is at least reserved in caller of this function. Tail
3639 // call optimized function's reserved stack space needs to be aligned so that
3640 // taking the difference between two stack areas will result in an aligned
3641 // stack.
3642 MinReservedArea =
3643 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3644 FuncInfo->setMinReservedArea(MinReservedArea);
3645
3646 SmallVector<SDValue, 8> MemOps;
3647
3648 // If the function takes variable number of arguments, make a frame index for
3649 // the start of the first vararg value... for expansion of llvm.va_start.
3650 if (isVarArg) {
3651 static const MCPhysReg GPArgRegs[] = {
3652 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3653 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3654 };
3655 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
3656
3657 static const MCPhysReg FPArgRegs[] = {
3658 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3659 PPC::F8
3660 };
3661 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
3662
3663 if (useSoftFloat() || hasSPE())
3664 NumFPArgRegs = 0;
3665
3666 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
3667 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
3668
3669 // Make room for NumGPArgRegs and NumFPArgRegs.
3670 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
3671 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
3672
3673 FuncInfo->setVarArgsStackOffset(
3674 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
3675 CCInfo.getNextStackOffset(), true));
3676
3677 FuncInfo->setVarArgsFrameIndex(MFI.CreateStackObject(Depth, 8, false));
3678 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3679
3680 // The fixed integer arguments of a variadic function are stored to the
3681 // VarArgsFrameIndex on the stack so that they may be loaded by
3682 // dereferencing the result of va_next.
3683 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
3684 // Get an existing live-in vreg, or add a new one.
3685 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
3686 if (!VReg)
3687 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
3688
3689 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3690 SDValue Store =
3691 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3692 MemOps.push_back(Store);
3693 // Increment the address by four for the next argument to store
3694 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3695 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3696 }
3697
3698 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
3699 // is set.
3700 // The double arguments are stored to the VarArgsFrameIndex
3701 // on the stack.
3702 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
3703 // Get an existing live-in vreg, or add a new one.
3704 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
3705 if (!VReg)
3706 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
3707
3708 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
3709 SDValue Store =
3710 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
3711 MemOps.push_back(Store);
3712 // Increment the address by eight for the next argument to store
3713 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3714 PtrVT);
3715 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3716 }
3717 }
3718
3719 if (!MemOps.empty())
3720 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3721
3722 return Chain;
3723}
3724
3725// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3726// value to MVT::i64 and then truncate to the correct register size.
3727SDValue PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags,
3728 EVT ObjectVT, SelectionDAG &DAG,
3729 SDValue ArgVal,
3730 const SDLoc &dl) const {
3731 if (Flags.isSExt())
3732 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3733 DAG.getValueType(ObjectVT));
3734 else if (Flags.isZExt())
3735 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3736 DAG.getValueType(ObjectVT));
3737
3738 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3739}
3740
3741SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3742 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3743 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3744 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3745 // TODO: add description of PPC stack frame format, or at least some docs.
3746 //
3747 bool isELFv2ABI = Subtarget.isELFv2ABI();
3748 bool isLittleEndian = Subtarget.isLittleEndian();
3749 MachineFunction &MF = DAG.getMachineFunction();
3750 MachineFrameInfo &MFI = MF.getFrameInfo();
3751 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3752
3753 assert(!(CallConv == CallingConv::Fast && isVarArg) &&((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3754, __PRETTY_FUNCTION__))
3754 "fastcc not supported on varargs functions")((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3754, __PRETTY_FUNCTION__))
;
3755
3756 EVT PtrVT = getPointerTy(MF.getDataLayout());
3757 // Potential tail calls could cause overwriting of argument stack slots.
3758 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3759 (CallConv == CallingConv::Fast));
3760 unsigned PtrByteSize = 8;
3761 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3762
3763 static const MCPhysReg GPR[] = {
3764 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3765 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3766 };
3767 static const MCPhysReg VR[] = {
3768 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3769 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3770 };
3771
3772 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3773 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
3774 const unsigned Num_VR_Regs = array_lengthof(VR);
3775 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3776
3777 // Do a first pass over the arguments to determine whether the ABI
3778 // guarantees that our caller has allocated the parameter save area
3779 // on its stack frame. In the ELFv1 ABI, this is always the case;
3780 // in the ELFv2 ABI, it is true if this is a vararg function or if
3781 // any parameter is located in a stack slot.
3782
3783 bool HasParameterArea = !isELFv2ABI || isVarArg;
3784 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3785 unsigned NumBytes = LinkageSize;
3786 unsigned AvailableFPRs = Num_FPR_Regs;
3787 unsigned AvailableVRs = Num_VR_Regs;
3788 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3789 if (Ins[i].Flags.isNest())
3790 continue;
3791
3792 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3793 PtrByteSize, LinkageSize, ParamAreaSize,
3794 NumBytes, AvailableFPRs, AvailableVRs,
3795 Subtarget.hasQPX()))
3796 HasParameterArea = true;
3797 }
3798
3799 // Add DAG nodes to load the arguments or copy them out of registers. On
3800 // entry to a function on PPC, the arguments start after the linkage area,
3801 // although the first ones are often in registers.
3802
3803 unsigned ArgOffset = LinkageSize;
3804 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3805 unsigned &QFPR_idx = FPR_idx;
3806 SmallVector<SDValue, 8> MemOps;
3807 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
3808 unsigned CurArgIdx = 0;
3809 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3810 SDValue ArgVal;
3811 bool needsLoad = false;
3812 EVT ObjectVT = Ins[ArgNo].VT;
3813 EVT OrigVT = Ins[ArgNo].ArgVT;
3814 unsigned ObjSize = ObjectVT.getStoreSize();
3815 unsigned ArgSize = ObjSize;
3816 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3817 if (Ins[ArgNo].isOrigArg()) {
3818 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3819 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3820 }
3821 // We re-align the argument offset for each argument, except when using the
3822 // fast calling convention, when we need to make sure we do that only when
3823 // we'll actually use a stack slot.
3824 unsigned CurArgOffset, Align;
3825 auto ComputeArgOffset = [&]() {
3826 /* Respect alignment of argument on the stack. */
3827 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3828 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3829 CurArgOffset = ArgOffset;
3830 };
3831
3832 if (CallConv != CallingConv::Fast) {
3833 ComputeArgOffset();
3834
3835 /* Compute GPR index associated with argument offset. */
3836 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3837 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3838 }
3839
3840 // FIXME the codegen can be much improved in some cases.
3841 // We do not have to keep everything in memory.
3842 if (Flags.isByVal()) {
3843 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3843, __PRETTY_FUNCTION__))
;
3844
3845 if (CallConv == CallingConv::Fast)
3846 ComputeArgOffset();
3847
3848 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3849 ObjSize = Flags.getByValSize();
3850 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3851 // Empty aggregate parameters do not take up registers. Examples:
3852 // struct { } a;
3853 // union { } b;
3854 // int c[0];
3855 // etc. However, we have to provide a place-holder in InVals, so
3856 // pretend we have an 8-byte item at the current address for that
3857 // purpose.
3858 if (!ObjSize) {
3859 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
3860 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3861 InVals.push_back(FIN);
3862 continue;
3863 }
3864
3865 // Create a stack object covering all stack doublewords occupied
3866 // by the argument. If the argument is (fully or partially) on
3867 // the stack, or if the argument is fully in registers but the
3868 // caller has allocated the parameter save anyway, we can refer
3869 // directly to the caller's stack frame. Otherwise, create a
3870 // local copy in our own frame.
3871 int FI;
3872 if (HasParameterArea ||
3873 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3874 FI = MFI.CreateFixedObject(ArgSize, ArgOffset, false, true);
3875 else
3876 FI = MFI.CreateStackObject(ArgSize, Align, false);
3877 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3878
3879 // Handle aggregates smaller than 8 bytes.
3880 if (ObjSize < PtrByteSize) {
3881 // The value of the object is its address, which differs from the
3882 // address of the enclosing doubleword on big-endian systems.
3883 SDValue Arg = FIN;
3884 if (!isLittleEndian) {
3885 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3886 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3887 }
3888 InVals.push_back(Arg);
3889
3890 if (GPR_idx != Num_GPR_Regs) {
3891 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3892 FuncInfo->addLiveInAttr(VReg, Flags);
3893 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3894 SDValue Store;
3895
3896 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3897 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3898 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3899 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3900 MachinePointerInfo(&*FuncArg), ObjType);
3901 } else {
3902 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3903 // store the whole register as-is to the parameter save area
3904 // slot.
3905 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3906 MachinePointerInfo(&*FuncArg));
3907 }
3908
3909 MemOps.push_back(Store);
3910 }
3911 // Whether we copied from a register or not, advance the offset
3912 // into the parameter save area by a full doubleword.
3913 ArgOffset += PtrByteSize;
3914 continue;
3915 }
3916
3917 // The value of the object is its address, which is the address of
3918 // its first stack doubleword.
3919 InVals.push_back(FIN);
3920
3921 // Store whatever pieces of the object are in registers to memory.
3922 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3923 if (GPR_idx == Num_GPR_Regs)
3924 break;
3925
3926 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3927 FuncInfo->addLiveInAttr(VReg, Flags);
3928 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3929 SDValue Addr = FIN;
3930 if (j) {
3931 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3932 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3933 }
3934 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3935 MachinePointerInfo(&*FuncArg, j));
3936 MemOps.push_back(Store);
3937 ++GPR_idx;
3938 }
3939 ArgOffset += ArgSize;
3940 continue;
3941 }
3942
3943 switch (ObjectVT.getSimpleVT().SimpleTy) {
3944 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 3944)
;
3945 case MVT::i1:
3946 case MVT::i32:
3947 case MVT::i64:
3948 if (Flags.isNest()) {
3949 // The 'nest' parameter, if any, is passed in R11.
3950 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3951 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3952
3953 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3954 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3955
3956 break;
3957 }
3958
3959 // These can be scalar arguments or elements of an integer array type
3960 // passed directly. Clang may use those instead of "byval" aggregate
3961 // types to avoid forcing arguments to memory unnecessarily.
3962 if (GPR_idx != Num_GPR_Regs) {
3963 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3964 FuncInfo->addLiveInAttr(VReg, Flags);
3965 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3966
3967 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3968 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3969 // value to MVT::i64 and then truncate to the correct register size.
3970 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3971 } else {
3972 if (CallConv == CallingConv::Fast)
3973 ComputeArgOffset();
3974
3975 needsLoad = true;
3976 ArgSize = PtrByteSize;
3977 }
3978 if (CallConv != CallingConv::Fast || needsLoad)
3979 ArgOffset += 8;
3980 break;
3981
3982 case MVT::f32:
3983 case MVT::f64:
3984 // These can be scalar arguments or elements of a float array type
3985 // passed directly. The latter are used to implement ELFv2 homogenous
3986 // float aggregates.
3987 if (FPR_idx != Num_FPR_Regs) {
3988 unsigned VReg;
3989
3990 if (ObjectVT == MVT::f32)
3991 VReg = MF.addLiveIn(FPR[FPR_idx],
3992 Subtarget.hasP8Vector()
3993 ? &PPC::VSSRCRegClass
3994 : &PPC::F4RCRegClass);
3995 else
3996 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3997 ? &PPC::VSFRCRegClass
3998 : &PPC::F8RCRegClass);
3999
4000 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4001 ++FPR_idx;
4002 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
4003 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4004 // once we support fp <-> gpr moves.
4005
4006 // This can only ever happen in the presence of f32 array types,
4007 // since otherwise we never run out of FPRs before running out
4008 // of GPRs.
4009 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
4010 FuncInfo->addLiveInAttr(VReg, Flags);
4011 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4012
4013 if (ObjectVT == MVT::f32) {
4014 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
4015 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
4016 DAG.getConstant(32, dl, MVT::i32));
4017 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
4018 }
4019
4020 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
4021 } else {
4022 if (CallConv == CallingConv::Fast)
4023 ComputeArgOffset();
4024
4025 needsLoad = true;
4026 }
4027
4028 // When passing an array of floats, the array occupies consecutive
4029 // space in the argument area; only round up to the next doubleword
4030 // at the end of the array. Otherwise, each float takes 8 bytes.
4031 if (CallConv != CallingConv::Fast || needsLoad) {
4032 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
4033 ArgOffset += ArgSize;
4034 if (Flags.isInConsecutiveRegsLast())
4035 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4036 }
4037 break;
4038 case MVT::v4f32:
4039 case MVT::v4i32:
4040 case MVT::v8i16:
4041 case MVT::v16i8:
4042 case MVT::v2f64:
4043 case MVT::v2i64:
4044 case MVT::v1i128:
4045 case MVT::f128:
4046 if (!Subtarget.hasQPX()) {
4047 // These can be scalar arguments or elements of a vector array type
4048 // passed directly. The latter are used to implement ELFv2 homogenous
4049 // vector aggregates.
4050 if (VR_idx != Num_VR_Regs) {
4051 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4052 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4053 ++VR_idx;
4054 } else {
4055 if (CallConv == CallingConv::Fast)
4056 ComputeArgOffset();
4057 needsLoad = true;
4058 }
4059 if (CallConv != CallingConv::Fast || needsLoad)
4060 ArgOffset += 16;
4061 break;
4062 } // not QPX
4063
4064 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&((ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && "Invalid QPX parameter type"
) ? static_cast<void> (0) : __assert_fail ("ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && \"Invalid QPX parameter type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4065, __PRETTY_FUNCTION__))
4065 "Invalid QPX parameter type")((ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && "Invalid QPX parameter type"
) ? static_cast<void> (0) : __assert_fail ("ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 && \"Invalid QPX parameter type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4065, __PRETTY_FUNCTION__))
;
4066 LLVM_FALLTHROUGH[[gnu::fallthrough]];
4067
4068 case MVT::v4f64:
4069 case MVT::v4i1:
4070 // QPX vectors are treated like their scalar floating-point subregisters
4071 // (except that they're larger).
4072 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
4073 if (QFPR_idx != Num_QFPR_Regs) {
4074 const TargetRegisterClass *RC;
4075 switch (ObjectVT.getSimpleVT().SimpleTy) {
4076 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
4077 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
4078 default: RC = &PPC::QBRCRegClass; break;
4079 }
4080
4081 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
4082 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4083 ++QFPR_idx;
4084 } else {
4085 if (CallConv == CallingConv::Fast)
4086 ComputeArgOffset();
4087 needsLoad = true;
4088 }
4089 if (CallConv != CallingConv::Fast || needsLoad)
4090 ArgOffset += Sz;
4091 break;
4092 }
4093
4094 // We need to load the argument to a virtual register if we determined
4095 // above that we ran out of physical registers of the appropriate type.
4096 if (needsLoad) {
4097 if (ObjSize < ArgSize && !isLittleEndian)
4098 CurArgOffset += ArgSize - ObjSize;
4099 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
4100 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4101 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4102 }
4103
4104 InVals.push_back(ArgVal);
4105 }
4106
4107 // Area that is at least reserved in the caller of this function.
4108 unsigned MinReservedArea;
4109 if (HasParameterArea)
4110 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
4111 else
4112 MinReservedArea = LinkageSize;
4113
4114 // Set the size that is at least reserved in caller of this function. Tail
4115 // call optimized functions' reserved stack space needs to be aligned so that
4116 // taking the difference between two stack areas will result in an aligned
4117 // stack.
4118 MinReservedArea =
4119 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4120 FuncInfo->setMinReservedArea(MinReservedArea);
4121
4122 // If the function takes variable number of arguments, make a frame index for
4123 // the start of the first vararg value... for expansion of llvm.va_start.
4124 if (isVarArg) {
4125 int Depth = ArgOffset;
4126
4127 FuncInfo->setVarArgsFrameIndex(
4128 MFI.CreateFixedObject(PtrByteSize, Depth, true));
4129 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4130
4131 // If this function is vararg, store any remaining integer argument regs
4132 // to their spots on the stack so that they may be loaded by dereferencing
4133 // the result of va_next.
4134 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4135 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
4136 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4137 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4138 SDValue Store =
4139 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4140 MemOps.push_back(Store);
4141 // Increment the address by four for the next argument to store
4142 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
4143 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4144 }
4145 }
4146
4147 if (!MemOps.empty())
4148 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4149
4150 return Chain;
4151}
4152
4153SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
4154 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4155 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4156 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4157 // TODO: add description of PPC stack frame format, or at least some docs.
4158 //
4159 MachineFunction &MF = DAG.getMachineFunction();
4160 MachineFrameInfo &MFI = MF.getFrameInfo();
4161 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4162
4163 EVT PtrVT = getPointerTy(MF.getDataLayout());
4164 bool isPPC64 = PtrVT == MVT::i64;
4165 // Potential tail calls could cause overwriting of argument stack slots.
4166 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
4167 (CallConv == CallingConv::Fast));
4168 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4169 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4170 unsigned ArgOffset = LinkageSize;
4171 // Area that is at least reserved in caller of this function.
4172 unsigned MinReservedArea = ArgOffset;
4173
4174 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4175 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4176 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4177 };
4178 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4179 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4180 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4181 };
4182 static const MCPhysReg VR[] = {
4183 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4184 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4185 };
4186
4187 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
4188 const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13;
4189 const unsigned Num_VR_Regs = array_lengthof( VR);
4190
4191 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4192
4193 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4194
4195 // In 32-bit non-varargs functions, the stack space for vectors is after the
4196 // stack space for non-vectors. We do not use this space unless we have
4197 // too many vectors to fit in registers, something that only occurs in
4198 // constructed examples:), but we have to walk the arglist to figure
4199 // that out...for the pathological case, compute VecArgOffset as the
4200 // start of the vector parameter area. Computing VecArgOffset is the
4201 // entire point of the following loop.
4202 unsigned VecArgOffset = ArgOffset;
4203 if (!isVarArg && !isPPC64) {
4204 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
4205 ++ArgNo) {
4206 EVT ObjectVT = Ins[ArgNo].VT;
4207 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4208
4209 if (Flags.isByVal()) {
4210 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
4211 unsigned ObjSize = Flags.getByValSize();
4212 unsigned ArgSize =
4213 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4214 VecArgOffset += ArgSize;
4215 continue;
4216 }
4217
4218 switch(ObjectVT.getSimpleVT().SimpleTy) {
4219 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4219)
;
4220 case MVT::i1:
4221 case MVT::i32:
4222 case MVT::f32:
4223 VecArgOffset += 4;
4224 break;
4225 case MVT::i64: // PPC64
4226 case MVT::f64:
4227 // FIXME: We are guaranteed to be !isPPC64 at this point.
4228 // Does MVT::i64 apply?
4229 VecArgOffset += 8;
4230 break;
4231 case MVT::v4f32:
4232 case MVT::v4i32:
4233 case MVT::v8i16:
4234 case MVT::v16i8:
4235 // Nothing to do, we're only looking at Nonvector args here.
4236 break;
4237 }
4238 }
4239 }
4240 // We've found where the vector parameter area in memory is. Skip the
4241 // first 12 parameters; these don't use that memory.
4242 VecArgOffset = ((VecArgOffset+15)/16)*16;
4243 VecArgOffset += 12*16;
4244
4245 // Add DAG nodes to load the arguments or copy them out of registers. On
4246 // entry to a function on PPC, the arguments start after the linkage area,
4247 // although the first ones are often in registers.
4248
4249 SmallVector<SDValue, 8> MemOps;
4250 unsigned nAltivecParamsAtEnd = 0;
4251 Function::const_arg_iterator FuncArg = MF.getFunction().arg_begin();
4252 unsigned CurArgIdx = 0;
4253 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
4254 SDValue ArgVal;
4255 bool needsLoad = false;
4256 EVT ObjectVT = Ins[ArgNo].VT;
4257 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
4258 unsigned ArgSize = ObjSize;
4259 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
4260 if (Ins[ArgNo].isOrigArg()) {
4261 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
4262 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
4263 }
4264 unsigned CurArgOffset = ArgOffset;
4265
4266 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
4267 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
4268 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
4269 if (isVarArg || isPPC64) {
4270 MinReservedArea = ((MinReservedArea+15)/16)*16;
4271 MinReservedArea += CalculateStackSlotSize(ObjectVT,
4272 Flags,
4273 PtrByteSize);
4274 } else nAltivecParamsAtEnd++;
4275 } else
4276 // Calculate min reserved area.
4277 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
4278 Flags,
4279 PtrByteSize);
4280
4281 // FIXME the codegen can be much improved in some cases.
4282 // We do not have to keep everything in memory.
4283 if (Flags.isByVal()) {
4284 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit")((Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[ArgNo].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4284, __PRETTY_FUNCTION__))
;
4285
4286 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
4287 ObjSize = Flags.getByValSize();
4288 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4289 // Objects of size 1 and 2 are right justified, everything else is
4290 // left justified. This means the memory address is adjusted forwards.
4291 if (ObjSize==1 || ObjSize==2) {
4292 CurArgOffset = CurArgOffset + (4 - ObjSize);
4293 }
4294 // The value of the object is its address.
4295 int FI = MFI.CreateFixedObject(ObjSize, CurArgOffset, false, true);
4296 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4297 InVals.push_back(FIN);
4298 if (ObjSize==1 || ObjSize==2) {
4299 if (GPR_idx != Num_GPR_Regs) {
4300 unsigned VReg;
4301 if (isPPC64)
4302 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4303 else
4304 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4305 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4306 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
4307 SDValue Store =
4308 DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
4309 MachinePointerInfo(&*FuncArg), ObjType);
4310 MemOps.push_back(Store);
4311 ++GPR_idx;
4312 }
4313
4314 ArgOffset += PtrByteSize;
4315
4316 continue;
4317 }
4318 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
4319 // Store whatever pieces of the object are in registers
4320 // to memory. ArgOffset will be the address of the beginning
4321 // of the object.
4322 if (GPR_idx != Num_GPR_Regs) {
4323 unsigned VReg;
4324 if (isPPC64)
4325 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4326 else
4327 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4328 int FI = MFI.CreateFixedObject(PtrByteSize, ArgOffset, true);
4329 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4330 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4331 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4332 MachinePointerInfo(&*FuncArg, j));
4333 MemOps.push_back(Store);
4334 ++GPR_idx;
4335 ArgOffset += PtrByteSize;
4336 } else {
4337 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
4338 break;
4339 }
4340 }
4341 continue;
4342 }
4343
4344 switch (ObjectVT.getSimpleVT().SimpleTy) {
4345 default: llvm_unreachable("Unhandled argument type!")::llvm::llvm_unreachable_internal("Unhandled argument type!",
"/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4345)
;
4346 case MVT::i1:
4347 case MVT::i32:
4348 if (!isPPC64) {
4349 if (GPR_idx != Num_GPR_Regs) {
4350 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4351 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4352
4353 if (ObjectVT == MVT::i1)
4354 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
4355
4356 ++GPR_idx;
4357 } else {
4358 needsLoad = true;
4359 ArgSize = PtrByteSize;
4360 }
4361 // All int arguments reserve stack space in the Darwin ABI.
4362 ArgOffset += PtrByteSize;
4363 break;
4364 }
4365 LLVM_FALLTHROUGH[[gnu::fallthrough]];
4366 case MVT::i64: // PPC64
4367 if (GPR_idx != Num_GPR_Regs) {
4368 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4369 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
4370
4371 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
4372 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
4373 // value to MVT::i64 and then truncate to the correct register size.
4374 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
4375
4376 ++GPR_idx;
4377 } else {
4378 needsLoad = true;
4379 ArgSize = PtrByteSize;
4380 }
4381 // All int arguments reserve stack space in the Darwin ABI.
4382 ArgOffset += 8;
4383 break;
4384
4385 case MVT::f32:
4386 case MVT::f64:
4387 // Every 4 bytes of argument space consumes one of the GPRs available for
4388 // argument passing.
4389 if (GPR_idx != Num_GPR_Regs) {
4390 ++GPR_idx;
4391 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
4392 ++GPR_idx;
4393 }
4394 if (FPR_idx != Num_FPR_Regs) {
4395 unsigned VReg;
4396
4397 if (ObjectVT == MVT::f32)
4398 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
4399 else
4400 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
4401
4402 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4403 ++FPR_idx;
4404 } else {
4405 needsLoad = true;
4406 }
4407
4408 // All FP arguments reserve stack space in the Darwin ABI.
4409 ArgOffset += isPPC64 ? 8 : ObjSize;
4410 break;
4411 case MVT::v4f32:
4412 case MVT::v4i32:
4413 case MVT::v8i16:
4414 case MVT::v16i8:
4415 // Note that vector arguments in registers don't reserve stack space,
4416 // except in varargs functions.
4417 if (VR_idx != Num_VR_Regs) {
4418 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
4419 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
4420 if (isVarArg) {
4421 while ((ArgOffset % 16) != 0) {
4422 ArgOffset += PtrByteSize;
4423 if (GPR_idx != Num_GPR_Regs)
4424 GPR_idx++;
4425 }
4426 ArgOffset += 16;
4427 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
4428 }
4429 ++VR_idx;
4430 } else {
4431 if (!isVarArg && !isPPC64) {
4432 // Vectors go after all the nonvectors.
4433 CurArgOffset = VecArgOffset;
4434 VecArgOffset += 16;
4435 } else {
4436 // Vectors are aligned.
4437 ArgOffset = ((ArgOffset+15)/16)*16;
4438 CurArgOffset = ArgOffset;
4439 ArgOffset += 16;
4440 }
4441 needsLoad = true;
4442 }
4443 break;
4444 }
4445
4446 // We need to load the argument to a virtual register if we determined above
4447 // that we ran out of physical registers of the appropriate type.
4448 if (needsLoad) {
4449 int FI = MFI.CreateFixedObject(ObjSize,
4450 CurArgOffset + (ArgSize - ObjSize),
4451 isImmutable);
4452 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4453 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo());
4454 }
4455
4456 InVals.push_back(ArgVal);
4457 }
4458
4459 // Allow for Altivec parameters at the end, if needed.
4460 if (nAltivecParamsAtEnd) {
4461 MinReservedArea = ((MinReservedArea+15)/16)*16;
4462 MinReservedArea += 16*nAltivecParamsAtEnd;
4463 }
4464
4465 // Area that is at least reserved in the caller of this function.
4466 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
4467
4468 // Set the size that is at least reserved in caller of this function. Tail
4469 // call optimized functions' reserved stack space needs to be aligned so that
4470 // taking the difference between two stack areas will result in an aligned
4471 // stack.
4472 MinReservedArea =
4473 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
4474 FuncInfo->setMinReservedArea(MinReservedArea);
4475
4476 // If the function takes variable number of arguments, make a frame index for
4477 // the start of the first vararg value... for expansion of llvm.va_start.
4478 if (isVarArg) {
4479 int Depth = ArgOffset;
4480
4481 FuncInfo->setVarArgsFrameIndex(
4482 MFI.CreateFixedObject(PtrVT.getSizeInBits()/8,
4483 Depth, true));
4484 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4485
4486 // If this function is vararg, store any remaining integer argument regs
4487 // to their spots on the stack so that they may be loaded by dereferencing
4488 // the result of va_next.
4489 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
4490 unsigned VReg;
4491
4492 if (isPPC64)
4493 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
4494 else
4495 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
4496
4497 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
4498 SDValue Store =
4499 DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo());
4500 MemOps.push_back(Store);
4501 // Increment the address by four for the next argument to store
4502 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
4503 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
4504 }
4505 }
4506
4507 if (!MemOps.empty())
4508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4509
4510 return Chain;
4511}
4512
4513/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
4514/// adjusted to accommodate the arguments for the tailcall.
4515static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
4516 unsigned ParamSize) {
4517
4518 if (!isTailCall) return 0;
4519
4520 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
4521 unsigned CallerMinReservedArea = FI->getMinReservedArea();
4522 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
4523 // Remember only if the new adjustment is bigger.
4524 if (SPDiff < FI->getTailCallSPDelta())
4525 FI->setTailCallSPDelta(SPDiff);
4526
4527 return SPDiff;
4528}
4529
4530static bool isFunctionGlobalAddress(SDValue Callee);
4531
4532static bool
4533callsShareTOCBase(const Function *Caller, SDValue Callee,
4534 const TargetMachine &TM) {
4535 // Callee is either a GlobalAddress or an ExternalSymbol. ExternalSymbols
4536 // don't have enough information to determine if the caller and calle share
4537 // the same TOC base, so we have to pessimistically assume they don't for
4538 // correctness.
4539 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
4540 if (!G)
4541 return false;
4542
4543 const GlobalValue *GV = G->getGlobal();
4544 // The medium and large code models are expected to provide a sufficiently
4545 // large TOC to provide all data addressing needs of a module with a
4546 // single TOC. Since each module will be addressed with a single TOC then we
4547 // only need to check that caller and callee don't cross dso boundaries.
4548 if (CodeModel::Medium == TM.getCodeModel() ||
4549 CodeModel::Large == TM.getCodeModel())
4550 return TM.shouldAssumeDSOLocal(*Caller->getParent(), GV);
4551
4552 // Otherwise we need to ensure callee and caller are in the same section,
4553 // since the linker may allocate multiple TOCs, and we don't know which
4554 // sections will belong to the same TOC base.
4555
4556 if (!GV->isStrongDefinitionForLinker())
4557 return false;
4558
4559 // Any explicitly-specified sections and section prefixes must also match.
4560 // Also, if we're using -ffunction-sections, then each function is always in
4561 // a different section (the same is true for COMDAT functions).
4562 if (TM.getFunctionSections() || GV->hasComdat() || Caller->hasComdat() ||
4563 GV->getSection() != Caller->getSection())
4564 return false;
4565 if (const auto *F = dyn_cast<Function>(GV)) {
4566 if (F->getSectionPrefix() != Caller->getSectionPrefix())
4567 return false;
4568 }
4569
4570 // If the callee might be interposed, then we can't assume the ultimate call
4571 // target will be in the same section. Even in cases where we can assume that
4572 // interposition won't happen, in any case where the linker might insert a
4573 // stub to allow for interposition, we must generate code as though
4574 // interposition might occur. To understand why this matters, consider a
4575 // situation where: a -> b -> c where the arrows indicate calls. b and c are
4576 // in the same section, but a is in a different module (i.e. has a different
4577 // TOC base pointer). If the linker allows for interposition between b and c,
4578 // then it will generate a stub for the call edge between b and c which will
4579 // save the TOC pointer into the designated stack slot allocated by b. If we
4580 // return true here, and therefore allow a tail call between b and c, that
4581 // stack slot won't exist and the b -> c stub will end up saving b'c TOC base
4582 // pointer into the stack slot allocated by a (where the a -> b stub saved
4583 // a's TOC base pointer). If we're not considering a tail call, but rather,
4584 // whether a nop is needed after the call instruction in b, because the linker
4585 // will insert a stub, it might complain about a missing nop if we omit it
4586 // (although many don't complain in this case).
4587 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4588 return false;
4589
4590 return true;
4591}
4592
4593static bool
4594needStackSlotPassParameters(const PPCSubtarget &Subtarget,
4595 const SmallVectorImpl<ISD::OutputArg> &Outs) {
4596 assert(Subtarget.is64BitELFABI())((Subtarget.is64BitELFABI()) ? static_cast<void> (0) : __assert_fail
("Subtarget.is64BitELFABI()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 4596, __PRETTY_FUNCTION__))
;
4597
4598 const unsigned PtrByteSize = 8;
4599 const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4600
4601 static const MCPhysReg GPR[] = {
4602 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4603 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4604 };
4605 static const MCPhysReg VR[] = {
4606 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4607 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4608 };
4609
4610 const unsigned NumGPRs = array_lengthof(GPR);
4611 const unsigned NumFPRs = 13;
4612 const unsigned NumVRs = array_lengthof(VR);
4613 const unsigned ParamAreaSize = NumGPRs * PtrByteSize;
4614
4615 unsigned NumBytes = LinkageSize;
4616 unsigned AvailableFPRs = NumFPRs;
4617 unsigned AvailableVRs = NumVRs;
4618
4619 for (const ISD::OutputArg& Param : Outs) {
4620 if (Param.Flags.isNest()) continue;
4621
4622 if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags,
4623 PtrByteSize, LinkageSize, ParamAreaSize,
4624 NumBytes, AvailableFPRs, AvailableVRs,
4625 Subtarget.hasQPX()))
4626 return true;
4627 }
4628 return false;
4629}
4630
4631static bool
4632hasSameArgumentList(const Function *CallerFn, ImmutableCallSite CS) {
4633 if (CS.arg_size() != CallerFn->arg_size())
4634 return false;
4635
4636 ImmutableCallSite::arg_iterator CalleeArgIter = CS.arg_begin();
4637 ImmutableCallSite::arg_iterator CalleeArgEnd = CS.arg_end();
4638 Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin();
4639
4640 for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) {
4641 const Value* CalleeArg = *CalleeArgIter;
4642 const Value* CallerArg = &(*CallerArgIter);
4643 if (CalleeArg == CallerArg)
4644 continue;
4645
4646 // e.g. @caller([4 x i64] %a, [4 x i64] %b) {
4647 // tail call @callee([4 x i64] undef, [4 x i64] %b)
4648 // }
4649 // 1st argument of callee is undef and has the same type as caller.
4650 if (CalleeArg->getType() == CallerArg->getType() &&
4651 isa<UndefValue>(CalleeArg))
4652 continue;
4653
4654 return false;
4655 }
4656
4657 return true;
4658}
4659
4660// Returns true if TCO is possible between the callers and callees
4661// calling conventions.
4662static bool
4663areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC,
4664 CallingConv::ID CalleeCC) {
4665 // Tail calls are possible with fastcc and ccc.
4666 auto isTailCallableCC = [] (CallingConv::ID CC){
4667 return CC == CallingConv::C || CC == CallingConv::Fast;
4668 };
4669 if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC))
4670 return false;
4671
4672 // We can safely tail call both fastcc and ccc callees from a c calling
4673 // convention caller. If the caller is fastcc, we may have less stack space
4674 // than a non-fastcc caller with the same signature so disable tail-calls in
4675 // that case.
4676 return CallerCC == CallingConv::C || CallerCC == CalleeCC;
4677}
4678
4679bool
4680PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4681 SDValue Callee,
4682 CallingConv::ID CalleeCC,
4683 ImmutableCallSite CS,
4684 bool isVarArg,
4685 const SmallVectorImpl<ISD::OutputArg> &Outs,
4686 const SmallVectorImpl<ISD::InputArg> &Ins,
4687 SelectionDAG& DAG) const {
4688 bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt;
4689
4690 if (DisableSCO && !TailCallOpt) return false;
4691
4692 // Variadic argument functions are not supported.
4693 if (isVarArg) return false;
4694
4695 auto &Caller = DAG.getMachineFunction().getFunction();
4696 // Check that the calling conventions are compatible for tco.
4697 if (!areCallingConvEligibleForTCO_64SVR4(Caller.getCallingConv(), CalleeCC))
4698 return false;
4699
4700 // Caller contains any byval parameter is not supported.
4701 if (any_of(Ins, [](const ISD::InputArg &IA) { return IA.Flags.isByVal(); }))
4702 return false;
4703
4704 // Callee contains any byval parameter is not supported, too.
4705 // Note: This is a quick work around, because in some cases, e.g.
4706 // caller's stack size > callee's stack size, we are still able to apply
4707 // sibling call optimization. For example, gcc is able to do SCO for caller1
4708 // in the following example, but not for caller2.
4709 // struct test {
4710 // long int a;
4711 // char ary[56];
4712 // } gTest;
4713 // __attribute__((noinline)) int callee(struct test v, struct test *b) {
4714 // b->a = v.a;
4715 // return 0;
4716 // }
4717 // void caller1(struct test a, struct test c, struct test *b) {
4718 // callee(gTest, b); }
4719 // void caller2(struct test *b) { callee(gTest, b); }
4720 if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); }))
4721 return false;
4722
4723 // If callee and caller use different calling conventions, we cannot pass
4724 // parameters on stack since offsets for the parameter area may be different.
4725 if (Caller.getCallingConv() != CalleeCC &&
4726 needStackSlotPassParameters(Subtarget, Outs))
4727 return false;
4728
4729 // No TCO/SCO on indirect call because Caller have to restore its TOC
4730 if (!isFunctionGlobalAddress(Callee) &&
4731 !isa<ExternalSymbolSDNode>(Callee))
4732 return false;
4733
4734 // If the caller and callee potentially have different TOC bases then we
4735 // cannot tail call since we need to restore the TOC pointer after the call.
4736 // ref: https://bugzilla.mozilla.org/show_bug.cgi?id=973977
4737 if (!callsShareTOCBase(&Caller, Callee, getTargetMachine()))
4738 return false;
4739
4740 // TCO allows altering callee ABI, so we don't have to check further.
4741 if (CalleeCC == CallingConv::Fast && TailCallOpt)
4742 return true;
4743
4744 if (DisableSCO) return false;
4745
4746 // If callee use the same argument list that caller is using, then we can
4747 // apply SCO on this case. If it is not, then we need to check if callee needs
4748 // stack for passing arguments.
4749 if (!hasSameArgumentList(&Caller, CS) &&
4750 needStackSlotPassParameters(Subtarget, Outs)) {
4751 return false;
4752 }
4753
4754 return true;
4755}
4756
4757/// IsEligibleForTailCallOptimization - Check whether the call is eligible
4758/// for tail call optimization. Targets which want to do tail call
4759/// optimization should implement this function.
4760bool
4761PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
4762 CallingConv::ID CalleeCC,
4763 bool isVarArg,
4764 const SmallVectorImpl<ISD::InputArg> &Ins,
4765 SelectionDAG& DAG) const {
4766 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
4767 return false;
4768
4769 // Variable argument functions are not supported.
4770 if (isVarArg)
4771 return false;
4772
4773 MachineFunction &MF = DAG.getMachineFunction();
4774 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
4775 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
4776 // Functions containing by val parameters are not supported.
4777 for (unsigned i = 0; i != Ins.size(); i++) {
4778 ISD::ArgFlagsTy Flags = Ins[i].Flags;
4779 if (Flags.isByVal()) return false;
4780 }
4781
4782 // Non-PIC/GOT tail calls are supported.
4783 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
4784 return true;
4785
4786 // At the moment we can only do local tail calls (in same module, hidden
4787 // or protected) if we are generating PIC.
4788 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4789 return G->getGlobal()->hasHiddenVisibility()
4790 || G->getGlobal()->hasProtectedVisibility();
4791 }
4792
4793 return false;
4794}
4795
4796/// isCallCompatibleAddress - Return the immediate to use if the specified
4797/// 32-bit value is representable in the immediate field of a BxA instruction.
4798static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
4799 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4800 if (!C) return nullptr;
4801
4802 int Addr = C->getZExtValue();
4803 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
4804 SignExtend32<26>(Addr) != Addr)
4805 return nullptr; // Top 6 bits have to be sext of immediate.
4806
4807 return DAG
4808 .getConstant(
4809 (int)C->getZExtValue() >> 2, SDLoc(Op),
4810 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()))
4811 .getNode();
4812}
4813
4814namespace {
4815
4816struct TailCallArgumentInfo {
4817 SDValue Arg;
4818 SDValue FrameIdxOp;
4819 int FrameIdx = 0;
4820
4821 TailCallArgumentInfo() = default;
4822};
4823
4824} // end anonymous namespace
4825
4826/// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
4827static void StoreTailCallArgumentsToStackSlot(
4828 SelectionDAG &DAG, SDValue Chain,
4829 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
4830 SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) {
4831 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
4832 SDValue Arg = TailCallArgs[i].Arg;
4833 SDValue FIN = TailCallArgs[i].FrameIdxOp;
4834 int FI = TailCallArgs[i].FrameIdx;
4835 // Store relative to framepointer.
4836 MemOpChains.push_back(DAG.getStore(
4837 Chain, dl, Arg, FIN,
4838 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)));
4839 }
4840}
4841
4842/// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
4843/// the appropriate stack slot for the tail call optimized function call.
4844static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
4845 SDValue OldRetAddr, SDValue OldFP,
4846 int SPDiff, const SDLoc &dl) {
4847 if (SPDiff) {
4848 // Calculate the new stack slot for the return address.
4849 MachineFunction &MF = DAG.getMachineFunction();
4850 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
4851 const PPCFrameLowering *FL = Subtarget.getFrameLowering();
4852 bool isPPC64 = Subtarget.isPPC64();
4853 int SlotSize = isPPC64 ? 8 : 4;
4854 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
4855 int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
4856 NewRetAddrLoc, true);
4857 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4858 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
4859 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
4860 MachinePointerInfo::getFixedStack(MF, NewRetAddr));
4861
4862 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
4863 // slot as the FP is never overwritten.
4864 if (Subtarget.isDarwinABI()) {
4865 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
4866 int NewFPIdx = MF.getFrameInfo().CreateFixedObject(SlotSize, NewFPLoc,
4867 true);
4868 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
4869 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
4870 MachinePointerInfo::getFixedStack(
4871 DAG.getMachineFunction(), NewFPIdx));
4872 }
4873 }
4874 return Chain;
4875}
4876
4877/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
4878/// the position of the argument.
4879static void
4880CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
4881 SDValue Arg, int SPDiff, unsigned ArgOffset,
4882 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
4883 int Offset = ArgOffset + SPDiff;
4884 uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
4885 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
4886 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
4887 SDValue FIN = DAG.getFrameIndex(FI, VT);
4888 TailCallArgumentInfo Info;
4889 Info.Arg = Arg;
4890 Info.FrameIdxOp = FIN;
4891 Info.FrameIdx = FI;
4892 TailCallArguments.push_back(Info);
4893}
4894
4895/// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
4896/// stack slot. Returns the chain as result and the loaded frame pointers in
4897/// LROpOut/FPOpout. Used when tail calling.
4898SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
4899 SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut,
4900 SDValue &FPOpOut, const SDLoc &dl) const {
4901 if (SPDiff) {
4902 // Load the LR and FP stack slot for later adjusting.
4903 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
4904 LROpOut = getReturnAddrFrameIndex(DAG);
4905 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
4906 Chain = SDValue(LROpOut.getNode(), 1);
4907
4908 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
4909 // slot as the FP is never overwritten.
4910 if (Subtarget.isDarwinABI()) {
4911 FPOpOut = getFramePointerFrameIndex(DAG);
4912 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo());
4913 Chain = SDValue(FPOpOut.getNode(), 1);
4914 }
4915 }
4916 return Chain;
4917}
4918
4919/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4920/// by "Src" to address "Dst" of size "Size". Alignment information is
4921/// specified by the specific parameter attribute. The copy will be passed as
4922/// a byval function parameter.
4923/// Sometimes what we are copying is the end of a larger object, the part that
4924/// does not fit in registers.
4925static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
4926 SDValue Chain, ISD::ArgFlagsTy Flags,
4927 SelectionDAG &DAG, const SDLoc &dl) {
4928 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4929 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4930 false, false, false, MachinePointerInfo(),
4931 MachinePointerInfo());
4932}
4933
4934/// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4935/// tail calls.
4936static void LowerMemOpCallTo(
4937 SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg,
4938 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64,
4939 bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4940 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) {
4941 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4942 if (!isTailCall) {
4943 if (isVector) {
4944 SDValue StackPtr;
4945 if (isPPC64)
4946 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4947 else
4948 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4949 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4950 DAG.getConstant(ArgOffset, dl, PtrVT));
4951 }
4952 MemOpChains.push_back(
4953 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
4954 // Calculate and remember argument location.
4955 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4956 TailCallArguments);
4957}
4958
4959static void
4960PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4961 const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp,
4962 SDValue FPOp,
4963 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4964 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4965 // might overwrite each other in case of tail call optimization.
4966 SmallVector<SDValue, 8> MemOpChains2;
4967 // Do not flag preceding copytoreg stuff together with the following stuff.
4968 InFlag = SDValue();
4969 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4970 MemOpChains2, dl);
4971 if (!MemOpChains2.empty())
4972 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4973
4974 // Store the return address to the appropriate stack slot.
4975 Chain = EmitTailCallStoreFPAndRetAddr(DAG, Chain, LROp, FPOp, SPDiff, dl);
4976
4977 // Emit callseq_end just before tailcall node.
4978 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4979 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4980 InFlag = Chain.getValue(1);
4981}
4982
4983// Is this global address that of a function that can be called by name? (as
4984// opposed to something that must hold a descriptor for an indirect call).
4985static bool isFunctionGlobalAddress(SDValue Callee) {
4986 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4987 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4988 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4989 return false;
4990
4991 return G->getGlobal()->getValueType()->isFunctionTy();
4992 }
4993
4994 return false;
4995}
4996
4997SDValue PPCTargetLowering::LowerCallResult(
4998 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
4999 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5000 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
5001 SmallVector<CCValAssign, 16> RVLocs;
5002 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5003 *DAG.getContext());
5004
5005 CCRetInfo.AnalyzeCallResult(
5006 Ins, (Subtarget.isSVR4ABI() && CallConv == CallingConv::Cold)
5007 ? RetCC_PPC_Cold
5008 : RetCC_PPC);
5009
5010 // Copy all of the result registers out of their specified physreg.
5011 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
5012 CCValAssign &VA = RVLocs[i];
5013 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5013, __PRETTY_FUNCTION__))
;
5014
5015 SDValue Val;
5016
5017 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) {
5018 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5019 InFlag);
5020 Chain = Lo.getValue(1);
5021 InFlag = Lo.getValue(2);
5022 VA = RVLocs[++i]; // skip ahead to next loc
5023 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
5024 InFlag);
5025 Chain = Hi.getValue(1);
5026 InFlag = Hi.getValue(2);
5027 if (!Subtarget.isLittleEndian())
5028 std::swap (Lo, Hi);
5029 Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi);
5030 } else {
5031 Val = DAG.getCopyFromReg(Chain, dl,
5032 VA.getLocReg(), VA.getLocVT(), InFlag);
5033 Chain = Val.getValue(1);
5034 InFlag = Val.getValue(2);
5035 }
5036
5037 switch (VA.getLocInfo()) {
5038 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5038)
;
5039 case CCValAssign::Full: break;
5040 case CCValAssign::AExt:
5041 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5042 break;
5043 case CCValAssign::ZExt:
5044 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
5045 DAG.getValueType(VA.getValVT()));
5046 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5047 break;
5048 case CCValAssign::SExt:
5049 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
5050 DAG.getValueType(VA.getValVT()));
5051 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
5052 break;
5053 }
5054
5055 InVals.push_back(Val);
5056 }
5057
5058 return Chain;
5059}
5060
5061static bool isIndirectCall(const SDValue &Callee, SelectionDAG &DAG,
5062 const PPCSubtarget &Subtarget, bool isPatchPoint) {
5063 // PatchPoint calls are not indirect.
5064 if (isPatchPoint)
5065 return false;
5066
5067 if (isFunctionGlobalAddress(Callee) || dyn_cast<ExternalSymbolSDNode>(Callee))
5068 return false;
5069
5070 // Darwin, and 32-bit ELF can use a BLA. The descriptor based ABIs can not
5071 // becuase the immediate function pointer points to a descriptor instead of
5072 // a function entry point. The ELFv2 ABI cannot use a BLA because the function
5073 // pointer immediate points to the global entry point, while the BLA would
5074 // need to jump to the local entry point (see rL211174).
5075 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI() &&
5076 isBLACompatibleAddress(Callee, DAG))
5077 return false;
5078
5079 return true;
5080}
5081
5082static unsigned getCallOpcode(bool isIndirectCall, bool isPatchPoint,
5083 bool isTailCall, const Function &Caller,
5084 const SDValue &Callee,
5085 const PPCSubtarget &Subtarget,
5086 const TargetMachine &TM) {
5087 if (isTailCall)
5088 return PPCISD::TC_RETURN;
5089
5090 // This is a call through a function pointer.
5091 if (isIndirectCall) {
5092 // AIX and the 64-bit ELF ABIs need to maintain the TOC pointer accross
5093 // indirect calls. The save of the caller's TOC pointer to the stack will be
5094 // inserted into the DAG as part of call lowering. The restore of the TOC
5095 // pointer is modeled by using a pseudo instruction for the call opcode that
5096 // represents the 2 instruction sequence of an indirect branch and link,
5097 // immediately followed by a load of the TOC pointer from the the stack save
5098 // slot into gpr2.
5099 if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
5100 return PPCISD::BCTRL_LOAD_TOC;
5101
5102 // An indirect call that does not need a TOC restore.
5103 return PPCISD::BCTRL;
5104 }
5105
5106 // The ABIs that maintain a TOC pointer accross calls need to have a nop
5107 // immediately following the call instruction if the caller and callee may
5108 // have different TOC bases. At link time if the linker determines the calls
5109 // may not share a TOC base, the call is redirected to a trampoline inserted
5110 // by the linker. The trampoline will (among other things) save the callers
5111 // TOC pointer at an ABI designated offset in the linkage area and the linker
5112 // will rewrite the nop to be a load of the TOC pointer from the linkage area
5113 // into gpr2.
5114 if (Subtarget.isAIXABI() || Subtarget.is64BitELFABI())
5115 return callsShareTOCBase(&Caller, Callee, TM) ? PPCISD::CALL
5116 : PPCISD::CALL_NOP;
5117
5118 return PPCISD::CALL;
5119}
5120static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG,
5121 const SDLoc &dl, const PPCSubtarget &Subtarget) {
5122 if (!Subtarget.usesFunctionDescriptors() && !Subtarget.isELFv2ABI())
5123 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
5124 return SDValue(Dest, 0);
5125
5126 // Returns true if the callee is local, and false otherwise.
5127 auto isLocalCallee = [&]() {
5128 const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
5129 const Module *Mod = DAG.getMachineFunction().getFunction().getParent();
5130 const GlobalValue *GV = G ? G->getGlobal() : nullptr;
5131
5132 return DAG.getTarget().shouldAssumeDSOLocal(*Mod, GV) &&
5133 !dyn_cast_or_null<GlobalIFunc>(GV);
5134 };
5135
5136 // The PLT is only used in 32-bit ELF PIC mode. Attempting to use the PLT in
5137 // a static relocation model causes some versions of GNU LD (2.17.50, at
5138 // least) to force BSS-PLT, instead of secure-PLT, even if all objects are
5139 // built with secure-PLT.
5140 bool UsePlt =
5141 Subtarget.is32BitELFABI() && !isLocalCallee() &&
5142 Subtarget.getTargetMachine().getRelocationModel() == Reloc::PIC_;
5143
5144 if (isFunctionGlobalAddress(Callee)) {
5145 const GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
5146 if (!Subtarget.isAIXABI())
5147 return DAG.getTargetGlobalAddress(G->getGlobal(), dl,
5148 Callee.getValueType(), 0,
5149 UsePlt ? PPCII::MO_PLT : 0);
5150
5151 // On AIX, direct function calls reference the symbol for the function's
5152 // entry point, which is named by prepending a "." before the function's
5153 // C-linkage name.
5154 auto &Context = DAG.getMachineFunction().getMMI().getContext();
5155
5156 const GlobalObject *GO = cast<GlobalObject>(G->getGlobal());
5157 MCSymbolXCOFF *S = cast<MCSymbolXCOFF>(
5158 Context.getOrCreateSymbol(Twine(".") + Twine(GO->getName())));
5159
5160 if (GO && GO->isDeclaration() && !S->hasContainingCsect()) {
5161 // On AIX, an undefined symbol needs to be associated with a
5162 // MCSectionXCOFF to get the correct storage mapping class.
5163 // In this case, XCOFF::XMC_PR.
5164 const XCOFF::StorageClass SC =
5165 TargetLoweringObjectFileXCOFF::getStorageClassForGlobal(GO);
5166 MCSectionXCOFF *Sec =
5167 Context.getXCOFFSection(S->getName(), XCOFF::XMC_PR, XCOFF::XTY_ER,
5168 SC, SectionKind::getMetadata());
5169 S->setContainingCsect(Sec);
5170 }
5171
5172 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5173 return DAG.getMCSymbol(S, PtrVT);
5174 }
5175
5176 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
5177 return DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
5178 UsePlt ? PPCII::MO_PLT : 0);
5179
5180 // No transformation needed.
5181 assert(Callee.getNode() && "What no callee?")((Callee.getNode() && "What no callee?") ? static_cast
<void> (0) : __assert_fail ("Callee.getNode() && \"What no callee?\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5181, __PRETTY_FUNCTION__))
;
5182 return Callee;
5183}
5184
5185static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart) {
5186 assert(CallSeqStart.getOpcode() == ISD::CALLSEQ_START &&((CallSeqStart.getOpcode() == ISD::CALLSEQ_START && "Expected a CALLSEQ_STARTSDNode."
) ? static_cast<void> (0) : __assert_fail ("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5187, __PRETTY_FUNCTION__))
5187 "Expected a CALLSEQ_STARTSDNode.")((CallSeqStart.getOpcode() == ISD::CALLSEQ_START && "Expected a CALLSEQ_STARTSDNode."
) ? static_cast<void> (0) : __assert_fail ("CallSeqStart.getOpcode() == ISD::CALLSEQ_START && \"Expected a CALLSEQ_STARTSDNode.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5187, __PRETTY_FUNCTION__))
;
5188
5189 // The last operand is the chain, except when the node has glue. If the node
5190 // has glue, then the last operand is the glue, and the chain is the second
5191 // last operand.
5192 SDValue LastValue = CallSeqStart.getValue(CallSeqStart->getNumValues() - 1);
5193 if (LastValue.getValueType() != MVT::Glue)
5194 return LastValue;
5195
5196 return CallSeqStart.getValue(CallSeqStart->getNumValues() - 2);
5197}
5198
5199// Creates the node that moves a functions address into the count register
5200// to prepare for an indirect call instruction.
5201static void prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5202 SDValue &Glue, SDValue &Chain,
5203 const SDLoc &dl) {
5204 SDValue MTCTROps[] = {Chain, Callee, Glue};
5205 EVT ReturnTypes[] = {MVT::Other, MVT::Glue};
5206 Chain = DAG.getNode(PPCISD::MTCTR, dl, makeArrayRef(ReturnTypes, 2),
5207 makeArrayRef(MTCTROps, Glue.getNode() ? 3 : 2));
5208 // The glue is the second value produced.
5209 Glue = Chain.getValue(1);
5210}
5211
5212static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee,
5213 SDValue &Glue, SDValue &Chain,
5214 SDValue CallSeqStart,
5215 ImmutableCallSite CS, const SDLoc &dl,
5216 bool hasNest,
5217 const PPCSubtarget &Subtarget) {
5218 // Function pointers in the 64-bit SVR4 ABI do not point to the function
5219 // entry point, but to the function descriptor (the function entry point
5220 // address is part of the function descriptor though).
5221 // The function descriptor is a three doubleword structure with the
5222 // following fields: function entry point, TOC base address and
5223 // environment pointer.
5224 // Thus for a call through a function pointer, the following actions need
5225 // to be performed:
5226 // 1. Save the TOC of the caller in the TOC save area of its stack
5227 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
5228 // 2. Load the address of the function entry point from the function
5229 // descriptor.
5230 // 3. Load the TOC of the callee from the function descriptor into r2.
5231 // 4. Load the environment pointer from the function descriptor into
5232 // r11.
5233 // 5. Branch to the function entry point address.
5234 // 6. On return of the callee, the TOC of the caller needs to be
5235 // restored (this is done in FinishCall()).
5236 //
5237 // The loads are scheduled at the beginning of the call sequence, and the
5238 // register copies are flagged together to ensure that no other
5239 // operations can be scheduled in between. E.g. without flagging the
5240 // copies together, a TOC access in the caller could be scheduled between
5241 // the assignment of the callee TOC and the branch to the callee, which leads
5242 // to incorrect code.
5243
5244 // Start by loading the function address from the descriptor.
5245 SDValue LDChain = getOutputChainFromCallSeq(CallSeqStart);
5246 auto MMOFlags = Subtarget.hasInvariantFunctionDescriptors()
5247 ? (MachineMemOperand::MODereferenceable |
5248 MachineMemOperand::MOInvariant)
5249 : MachineMemOperand::MONone;
5250
5251 MachinePointerInfo MPI(CS ? CS.getCalledValue() : nullptr);
5252
5253 // Registers used in building the DAG.
5254 const MCRegister EnvPtrReg = Subtarget.getEnvironmentPointerRegister();
5255 const MCRegister TOCReg = Subtarget.getTOCPointerRegister();
5256
5257 // Offsets of descriptor members.
5258 const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset();
5259 const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset();
5260
5261 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
5262 const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4;
5263
5264 // One load for the functions entry point address.
5265 SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI,
5266 Alignment, MMOFlags);
5267
5268 // One for loading the TOC anchor for the module that contains the called
5269 // function.
5270 SDValue TOCOff = DAG.getIntPtrConstant(TOCAnchorOffset, dl);
5271 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, Callee, TOCOff);
5272 SDValue TOCPtr =
5273 DAG.getLoad(RegVT, dl, LDChain, AddTOC,
5274 MPI.getWithOffset(TOCAnchorOffset), Alignment, MMOFlags);
5275
5276 // One for loading the environment pointer.
5277 SDValue PtrOff = DAG.getIntPtrConstant(EnvPtrOffset, dl);
5278 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff);
5279 SDValue LoadEnvPtr =
5280 DAG.getLoad(RegVT, dl, LDChain, AddPtr,
5281 MPI.getWithOffset(EnvPtrOffset), Alignment, MMOFlags);
5282
5283
5284 // Then copy the newly loaded TOC anchor to the TOC pointer.
5285 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, TOCReg, TOCPtr, Glue);
5286 Chain = TOCVal.getValue(0);
5287 Glue = TOCVal.getValue(1);
5288
5289 // If the function call has an explicit 'nest' parameter, it takes the
5290 // place of the environment pointer.
5291 assert((!hasNest || !Subtarget.isAIXABI()) &&(((!hasNest || !Subtarget.isAIXABI()) && "Nest parameter is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5292, __PRETTY_FUNCTION__))
5292 "Nest parameter is not supported on AIX.")(((!hasNest || !Subtarget.isAIXABI()) && "Nest parameter is not supported on AIX."
) ? static_cast<void> (0) : __assert_fail ("(!hasNest || !Subtarget.isAIXABI()) && \"Nest parameter is not supported on AIX.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5292, __PRETTY_FUNCTION__))
;
5293 if (!hasNest) {
5294 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, EnvPtrReg, LoadEnvPtr, Glue);
5295 Chain = EnvVal.getValue(0);
5296 Glue = EnvVal.getValue(1);
5297 }
5298
5299 // The rest of the indirect call sequence is the same as the non-descriptor
5300 // DAG.
5301 prepareIndirectCall(DAG, LoadFuncPtr, Glue, Chain, dl);
5302}
5303
5304static void
5305buildCallOperands(SmallVectorImpl<SDValue> &Ops, CallingConv::ID CallConv,
5306 const SDLoc &dl, bool isTailCall, bool isVarArg,
5307 bool isPatchPoint, bool hasNest, SelectionDAG &DAG,
5308 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
5309 SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff,
5310 const PPCSubtarget &Subtarget, bool isIndirect) {
5311 const bool IsPPC64 = Subtarget.isPPC64();
5312 // MVT for a general purpose register.
5313 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
5314
5315 // First operand is always the chain.
5316 Ops.push_back(Chain);
5317
5318 // If it's a direct call pass the callee as the second operand.
5319 if (!isIndirect)
5320 Ops.push_back(Callee);
5321 else {
5322 assert(!isPatchPoint && "Patch point call are not indirect.")((!isPatchPoint && "Patch point call are not indirect."
) ? static_cast<void> (0) : __assert_fail ("!isPatchPoint && \"Patch point call are not indirect.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5322, __PRETTY_FUNCTION__))
;
5323
5324 // For the TOC based ABIs, we have saved the TOC pointer to the linkage area
5325 // on the stack (this would have been done in `LowerCall_64SVR4` or
5326 // `LowerCall_AIX`). The call instruction is a pseudo instruction that
5327 // represents both the indirect branch and a load that restores the TOC
5328 // pointer from the linkage area. The operand for the TOC restore is an add
5329 // of the TOC save offset to the stack pointer. This must be the second
5330 // operand: after the chain input but before any other variadic arguments.
5331 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
5332 const MCRegister StackPtrReg = Subtarget.getStackPointerRegister();
5333
5334 SDValue StackPtr = DAG.getRegister(StackPtrReg, RegVT);
5335 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5336 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5337 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, RegVT, StackPtr, TOCOff);
5338 Ops.push_back(AddTOC);
5339 }
5340
5341 // Add the register used for the environment pointer.
5342 if (Subtarget.usesFunctionDescriptors() && !hasNest)
5343 Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(),
5344 RegVT));
5345
5346
5347 // Add CTR register as callee so a bctr can be emitted later.
5348 if (isTailCall)
5349 Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5350 }
5351
5352 // If this is a tail call add stack pointer delta.
5353 if (isTailCall)
5354 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
5355
5356 // Add argument registers to the end of the list so that they are known live
5357 // into the call.
5358 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
5359 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
5360 RegsToPass[i].second.getValueType()));
5361
5362 // We cannot add R2/X2 as an operand here for PATCHPOINT, because there is
5363 // no way to mark dependencies as implicit here.
5364 // We will add the R2/X2 dependency in EmitInstrWithCustomInserter.
5365 if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) && !isPatchPoint)
5366 Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT));
5367
5368 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
5369 if (isVarArg && Subtarget.is32BitELFABI())
5370 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
5371
5372 // Add a register mask operand representing the call-preserved registers.
5373 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
5374 const uint32_t *Mask =
5375 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
5376 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5376, __PRETTY_FUNCTION__))
;
5377 Ops.push_back(DAG.getRegisterMask(Mask));
5378
5379 // If the glue is valid, it is the last operand.
5380 if (Glue.getNode())
5381 Ops.push_back(Glue);
5382}
5383
5384SDValue PPCTargetLowering::FinishCall(
5385 CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg,
5386 bool isPatchPoint, bool hasNest, SelectionDAG &DAG,
5387 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue,
5388 SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff,
5389 unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins,
5390 SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const {
5391
5392 if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI())
5393 setUsesTOCBasePtr(DAG);
5394
5395 const bool isIndirect = isIndirectCall(Callee, DAG, Subtarget, isPatchPoint);
5396 unsigned CallOpc = getCallOpcode(isIndirect, isPatchPoint, isTailCall,
5397 DAG.getMachineFunction().getFunction(),
5398 Callee, Subtarget, DAG.getTarget());
5399
5400 if (!isIndirect)
5401 Callee = transformCallee(Callee, DAG, dl, Subtarget);
5402 else if (Subtarget.usesFunctionDescriptors())
5403 prepareDescriptorIndirectCall(DAG, Callee, Glue, Chain, CallSeqStart, CS,
5404 dl, hasNest, Subtarget);
5405 else
5406 prepareIndirectCall(DAG, Callee, Glue, Chain, dl);
5407
5408 // Build the operand list for the call instruction.
5409 SmallVector<SDValue, 8> Ops;
5410 buildCallOperands(Ops, CallConv, dl, isTailCall, isVarArg, isPatchPoint,
5411 hasNest, DAG, RegsToPass, Glue, Chain, Callee, SPDiff,
5412 Subtarget, isIndirect);
5413
5414 // Emit tail call.
5415 if (isTailCall) {
5416 assert(((Callee.getOpcode() == ISD::Register &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting a global address, external symbol, absolute value or "
"register") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting a global address, external symbol, absolute value or \" \"register\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5422, __PRETTY_FUNCTION__))
5417 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting a global address, external symbol, absolute value or "
"register") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting a global address, external symbol, absolute value or \" \"register\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5422, __PRETTY_FUNCTION__))
5418 Callee.getOpcode() == ISD::TargetExternalSymbol ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting a global address, external symbol, absolute value or "
"register") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting a global address, external symbol, absolute value or \" \"register\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5422, __PRETTY_FUNCTION__))
5419 Callee.getOpcode() == ISD::TargetGlobalAddress ||((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting a global address, external symbol, absolute value or "
"register") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting a global address, external symbol, absolute value or \" \"register\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5422, __PRETTY_FUNCTION__))
5420 isa<ConstantSDNode>(Callee)) &&((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting a global address, external symbol, absolute value or "
"register") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting a global address, external symbol, absolute value or \" \"register\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5422, __PRETTY_FUNCTION__))
5421 "Expecting a global address, external symbol, absolute value or "((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting a global address, external symbol, absolute value or "
"register") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting a global address, external symbol, absolute value or \" \"register\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5422, __PRETTY_FUNCTION__))
5422 "register")((((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode
>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() ==
ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress
|| isa<ConstantSDNode>(Callee)) && "Expecting a global address, external symbol, absolute value or "
"register") ? static_cast<void> (0) : __assert_fail ("((Callee.getOpcode() == ISD::Register && cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) || Callee.getOpcode() == ISD::TargetExternalSymbol || Callee.getOpcode() == ISD::TargetGlobalAddress || isa<ConstantSDNode>(Callee)) && \"Expecting a global address, external symbol, absolute value or \" \"register\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5422, __PRETTY_FUNCTION__))
;
5423 assert(CallOpc == PPCISD::TC_RETURN &&((CallOpc == PPCISD::TC_RETURN && "Unexpected call opcode for a tail call."
) ? static_cast<void> (0) : __assert_fail ("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5424, __PRETTY_FUNCTION__))
5424 "Unexpected call opcode for a tail call.")((CallOpc == PPCISD::TC_RETURN && "Unexpected call opcode for a tail call."
) ? static_cast<void> (0) : __assert_fail ("CallOpc == PPCISD::TC_RETURN && \"Unexpected call opcode for a tail call.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5424, __PRETTY_FUNCTION__))
;
5425 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
5426 return DAG.getNode(CallOpc, dl, MVT::Other, Ops);
5427 }
5428
5429 std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}};
5430 Chain = DAG.getNode(CallOpc, dl, ReturnTypes, Ops);
5431 Glue = Chain.getValue(1);
5432
5433 // When performing tail call optimization the callee pops its arguments off
5434 // the stack. Account for this here so these bytes can be pushed back on in
5435 // PPCFrameLowering::eliminateCallFramePseudoInstr.
5436 int BytesCalleePops = (CallConv == CallingConv::Fast &&
5437 getTargetMachine().Options.GuaranteedTailCallOpt)
5438 ? NumBytes
5439 : 0;
5440
5441 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5442 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
5443 Glue, dl);
5444 Glue = Chain.getValue(1);
5445
5446 return LowerCallResult(Chain, Glue, CallConv, isVarArg, Ins, dl, DAG, InVals);
5447}
5448
5449SDValue
5450PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
5451 SmallVectorImpl<SDValue> &InVals) const {
5452 SelectionDAG &DAG = CLI.DAG;
5453 SDLoc &dl = CLI.DL;
5454 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
5455 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
5456 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
5457 SDValue Chain = CLI.Chain;
5458 SDValue Callee = CLI.Callee;
5459 bool &isTailCall = CLI.IsTailCall;
5460 CallingConv::ID CallConv = CLI.CallConv;
5461 bool isVarArg = CLI.IsVarArg;
5462 bool isPatchPoint = CLI.IsPatchPoint;
5463 ImmutableCallSite CS = CLI.CS;
5464
5465 if (isTailCall) {
5466 if (Subtarget.useLongCalls() && !(CS && CS.isMustTailCall()))
5467 isTailCall = false;
5468 else if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5469 isTailCall =
5470 IsEligibleForTailCallOptimization_64SVR4(Callee, CallConv, CS,
5471 isVarArg, Outs, Ins, DAG);
5472 else
5473 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
5474 Ins, DAG);
5475 if (isTailCall) {
5476 ++NumTailCalls;
5477 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
5478 ++NumSiblingCalls;
5479
5480 assert(isa<GlobalAddressSDNode>(Callee) &&((isa<GlobalAddressSDNode>(Callee) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("isa<GlobalAddressSDNode>(Callee) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5481, __PRETTY_FUNCTION__))
5481 "Callee should be an llvm::Function object.")((isa<GlobalAddressSDNode>(Callee) && "Callee should be an llvm::Function object."
) ? static_cast<void> (0) : __assert_fail ("isa<GlobalAddressSDNode>(Callee) && \"Callee should be an llvm::Function object.\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5481, __PRETTY_FUNCTION__))
;
5482 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5483 const GlobalValue *GV =do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5484 cast<GlobalAddressSDNode>(Callee)->getGlobal();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5485 const unsigned Width =do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5486 80 - strlen("TCO caller: ") - strlen(", callee linkage: 0, 0");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5487 dbgs() << "TCO caller: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5488 << left_justify(DAG.getMachineFunction().getName(), Width)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5489 << ", callee linkage: " << GV->getVisibility() << ", "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
5490 << GV->getLinkage() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-lowering")) { const GlobalValue *GV = cast<GlobalAddressSDNode
>(Callee)->getGlobal(); const unsigned Width = 80 - strlen
("TCO caller: ") - strlen(", callee linkage: 0, 0"); dbgs() <<
"TCO caller: " << left_justify(DAG.getMachineFunction(
).getName(), Width) << ", callee linkage: " << GV
->getVisibility() << ", " << GV->getLinkage
() << "\n"; } } while (false)
;
5491 }
5492 }
5493
5494 if (!isTailCall && CS && CS.isMustTailCall())
5495 report_fatal_error("failed to perform tail call elimination on a call "
5496 "site marked musttail");
5497
5498 // When long calls (i.e. indirect calls) are always used, calls are always
5499 // made via function pointer. If we have a function name, first translate it
5500 // into a pointer.
5501 if (Subtarget.useLongCalls() && isa<GlobalAddressSDNode>(Callee) &&
5502 !isTailCall)
5503 Callee = LowerGlobalAddress(Callee, DAG);
5504
5505 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64())
5506 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
5507 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5508 dl, DAG, InVals, CS);
5509
5510 if (Subtarget.isSVR4ABI())
5511 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
5512 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5513 dl, DAG, InVals, CS);
5514
5515 if (Subtarget.isAIXABI())
5516 return LowerCall_AIX(Chain, Callee, CallConv, isVarArg,
5517 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5518 dl, DAG, InVals, CS);
5519
5520 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
5521 isTailCall, isPatchPoint, Outs, OutVals, Ins,
5522 dl, DAG, InVals, CS);
5523}
5524
5525SDValue PPCTargetLowering::LowerCall_32SVR4(
5526 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5527 bool isTailCall, bool isPatchPoint,
5528 const SmallVectorImpl<ISD::OutputArg> &Outs,
5529 const SmallVectorImpl<SDValue> &OutVals,
5530 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5531 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5532 ImmutableCallSite CS) const {
5533 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
5534 // of the 32-bit SVR4 ABI stack frame layout.
5535
5536 assert((CallConv == CallingConv::C ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5538, __PRETTY_FUNCTION__))
5537 CallConv == CallingConv::Cold ||(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5538, __PRETTY_FUNCTION__))
5538 CallConv == CallingConv::Fast) && "Unknown calling convention!")(((CallConv == CallingConv::C || CallConv == CallingConv::Cold
|| CallConv == CallingConv::Fast) && "Unknown calling convention!"
) ? static_cast<void> (0) : __assert_fail ("(CallConv == CallingConv::C || CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && \"Unknown calling convention!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5538, __PRETTY_FUNCTION__))
;
5539
5540 unsigned PtrByteSize = 4;
5541
5542 MachineFunction &MF = DAG.getMachineFunction();
5543
5544 // Mark this function as potentially containing a function that contains a
5545 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5546 // and restoring the callers stack pointer in this functions epilog. This is
5547 // done because by tail calling the called function might overwrite the value
5548 // in this function's (MF) stack pointer stack slot 0(SP).
5549 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5550 CallConv == CallingConv::Fast)
5551 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5552
5553 // Count how many bytes are to be pushed on the stack, including the linkage
5554 // area, parameter list area and the part of the local variable space which
5555 // contains copies of aggregates which are passed by value.
5556
5557 // Assign locations to all of the outgoing arguments.
5558 SmallVector<CCValAssign, 16> ArgLocs;
5559 PPCCCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
5560
5561 // Reserve space for the linkage area on the stack.
5562 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
5563 PtrByteSize);
5564 if (useSoftFloat())
5565 CCInfo.PreAnalyzeCallOperands(Outs);
5566
5567 if (isVarArg) {
5568 // Handle fixed and variable vector arguments differently.
5569 // Fixed vector arguments go into registers as long as registers are
5570 // available. Variable vector arguments always go into memory.
5571 unsigned NumArgs = Outs.size();
5572
5573 for (unsigned i = 0; i != NumArgs; ++i) {
5574 MVT ArgVT = Outs[i].VT;
5575 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
5576 bool Result;
5577
5578 if (Outs[i].IsFixed) {
5579 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
5580 CCInfo);
5581 } else {
5582 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
5583 ArgFlags, CCInfo);
5584 }
5585
5586 if (Result) {
5587#ifndef NDEBUG
5588 errs() << "Call operand #" << i << " has unhandled type "
5589 << EVT(ArgVT).getEVTString() << "\n";
5590#endif
5591 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5591)
;
5592 }
5593 }
5594 } else {
5595 // All arguments are treated the same.
5596 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
5597 }
5598 CCInfo.clearWasPPCF128();
5599
5600 // Assign locations to all of the outgoing aggregate by value arguments.
5601 SmallVector<CCValAssign, 16> ByValArgLocs;
5602 CCState CCByValInfo(CallConv, isVarArg, MF, ByValArgLocs, *DAG.getContext());
5603
5604 // Reserve stack space for the allocations in CCInfo.
5605 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
5606
5607 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
5608
5609 // Size of the linkage area, parameter list area and the part of the local
5610 // space variable where copies of aggregates which are passed by value are
5611 // stored.
5612 unsigned NumBytes = CCByValInfo.getNextStackOffset();
5613
5614 // Calculate by how many bytes the stack has to be adjusted in case of tail
5615 // call optimization.
5616 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5617
5618 // Adjust the stack pointer for the new arguments...
5619 // These operations are automatically eliminated by the prolog/epilog pass
5620 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
5621 SDValue CallSeqStart = Chain;
5622
5623 // Load the return address and frame pointer so it can be moved somewhere else
5624 // later.
5625 SDValue LROp, FPOp;
5626 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
5627
5628 // Set up a copy of the stack pointer for use loading and storing any
5629 // arguments that may not fit in the registers available for argument
5630 // passing.
5631 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5632
5633 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5634 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5635 SmallVector<SDValue, 8> MemOpChains;
5636
5637 bool seenFloatArg = false;
5638 // Walk the register/memloc assignments, inserting copies/loads.
5639 // i - Tracks the index into the list of registers allocated for the call
5640 // RealArgIdx - Tracks the index into the list of actual function arguments
5641 // j - Tracks the index into the list of byval arguments
5642 for (unsigned i = 0, RealArgIdx = 0, j = 0, e = ArgLocs.size();
5643 i != e;
5644 ++i, ++RealArgIdx) {
5645 CCValAssign &VA = ArgLocs[i];
5646 SDValue Arg = OutVals[RealArgIdx];
5647 ISD::ArgFlagsTy Flags = Outs[RealArgIdx].Flags;
5648
5649 if (Flags.isByVal()) {
5650 // Argument is an aggregate which is passed by value, thus we need to
5651 // create a copy of it in the local variable space of the current stack
5652 // frame (which is the stack frame of the caller) and pass the address of
5653 // this copy to the callee.
5654 assert((j < ByValArgLocs.size()) && "Index out of bounds!")(((j < ByValArgLocs.size()) && "Index out of bounds!"
) ? static_cast<void> (0) : __assert_fail ("(j < ByValArgLocs.size()) && \"Index out of bounds!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5654, __PRETTY_FUNCTION__))
;
5655 CCValAssign &ByValVA = ByValArgLocs[j++];
5656 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!")(((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!"
) ? static_cast<void> (0) : __assert_fail ("(VA.getValNo() == ByValVA.getValNo()) && \"ValNo mismatch!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5656, __PRETTY_FUNCTION__))
;
5657
5658 // Memory reserved in the local variable space of the callers stack frame.
5659 unsigned LocMemOffset = ByValVA.getLocMemOffset();
5660
5661 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5662 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5663 StackPtr, PtrOff);
5664
5665 // Create a copy of the argument in the local area of the current
5666 // stack frame.
5667 SDValue MemcpyCall =
5668 CreateCopyOfByValArgument(Arg, PtrOff,
5669 CallSeqStart.getNode()->getOperand(0),
5670 Flags, DAG, dl);
5671
5672 // This must go outside the CALLSEQ_START..END.
5673 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0,
5674 SDLoc(MemcpyCall));
5675 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5676 NewCallSeqStart.getNode());
5677 Chain = CallSeqStart = NewCallSeqStart;
5678
5679 // Pass the address of the aggregate copy on the stack either in a
5680 // physical register or in the parameter list area of the current stack
5681 // frame to the callee.
5682 Arg = PtrOff;
5683 }
5684
5685 // When useCRBits() is true, there can be i1 arguments.
5686 // It is because getRegisterType(MVT::i1) => MVT::i1,
5687 // and for other integer types getRegisterType() => MVT::i32.
5688 // Extend i1 and ensure callee will get i32.
5689 if (Arg.getValueType() == MVT::i1)
5690 Arg = DAG.getNode(Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5691 dl, MVT::i32, Arg);
5692
5693 if (VA.isRegLoc()) {
5694 seenFloatArg |= VA.getLocVT().isFloatingPoint();
5695 // Put argument in a physical register.
5696 if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) {
5697 bool IsLE = Subtarget.isLittleEndian();
5698 SDValue SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
5699 DAG.getIntPtrConstant(IsLE ? 0 : 1, dl));
5700 RegsToPass.push_back(std::make_pair(VA.getLocReg(), SVal.getValue(0)));
5701 SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg,
5702 DAG.getIntPtrConstant(IsLE ? 1 : 0, dl));
5703 RegsToPass.push_back(std::make_pair(ArgLocs[++i].getLocReg(),
5704 SVal.getValue(0)));
5705 } else
5706 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
5707 } else {
5708 // Put argument in the parameter list area of the current stack frame.
5709 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5709, __PRETTY_FUNCTION__))
;
5710 unsigned LocMemOffset = VA.getLocMemOffset();
5711
5712 if (!isTailCall) {
5713 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
5714 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
5715 StackPtr, PtrOff);
5716
5717 MemOpChains.push_back(
5718 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
5719 } else {
5720 // Calculate and remember argument location.
5721 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
5722 TailCallArguments);
5723 }
5724 }
5725 }
5726
5727 if (!MemOpChains.empty())
5728 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5729
5730 // Build a sequence of copy-to-reg nodes chained together with token chain
5731 // and flag operands which copy the outgoing args into the appropriate regs.
5732 SDValue InFlag;
5733 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5734 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5735 RegsToPass[i].second, InFlag);
5736 InFlag = Chain.getValue(1);
5737 }
5738
5739 // Set CR bit 6 to true if this is a vararg call with floating args passed in
5740 // registers.
5741 if (isVarArg) {
5742 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
5743 SDValue Ops[] = { Chain, InFlag };
5744
5745 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
5746 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
5747
5748 InFlag = Chain.getValue(1);
5749 }
5750
5751 if (isTailCall)
5752 PrepareTailCall(DAG, InFlag, Chain, dl, SPDiff, NumBytes, LROp, FPOp,
5753 TailCallArguments);
5754
5755 return FinishCall(CallConv, dl, isTailCall, isVarArg, isPatchPoint,
5756 /* unused except on PPC64 ELFv1 */ false, DAG,
5757 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5758 NumBytes, Ins, InVals, CS);
5759}
5760
5761// Copy an argument into memory, being careful to do this outside the
5762// call sequence for the call to which the argument belongs.
5763SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
5764 SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
5765 SelectionDAG &DAG, const SDLoc &dl) const {
5766 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
5767 CallSeqStart.getNode()->getOperand(0),
5768 Flags, DAG, dl);
5769 // The MEMCPY must go outside the CALLSEQ_START..END.
5770 int64_t FrameSize = CallSeqStart.getConstantOperandVal(1);
5771 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0,
5772 SDLoc(MemcpyCall));
5773 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
5774 NewCallSeqStart.getNode());
5775 return NewCallSeqStart;
5776}
5777
5778SDValue PPCTargetLowering::LowerCall_64SVR4(
5779 SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
5780 bool isTailCall, bool isPatchPoint,
5781 const SmallVectorImpl<ISD::OutputArg> &Outs,
5782 const SmallVectorImpl<SDValue> &OutVals,
5783 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
5784 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
5785 ImmutableCallSite CS) const {
5786 bool isELFv2ABI = Subtarget.isELFv2ABI();
5787 bool isLittleEndian = Subtarget.isLittleEndian();
5788 unsigned NumOps = Outs.size();
5789 bool hasNest = false;
5790 bool IsSibCall = false;
5791
5792 EVT PtrVT = getPointerTy(DAG.getDataLayout());
5793 unsigned PtrByteSize = 8;
5794
5795 MachineFunction &MF = DAG.getMachineFunction();
5796
5797 if (isTailCall && !getTargetMachine().Options.GuaranteedTailCallOpt)
5798 IsSibCall = true;
5799
5800 // Mark this function as potentially containing a function that contains a
5801 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5802 // and restoring the callers stack pointer in this functions epilog. This is
5803 // done because by tail calling the called function might overwrite the value
5804 // in this function's (MF) stack pointer stack slot 0(SP).
5805 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5806 CallConv == CallingConv::Fast)
5807 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5808
5809 assert(!(CallConv == CallingConv::Fast && isVarArg) &&((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5810, __PRETTY_FUNCTION__))
5810 "fastcc not supported on varargs functions")((!(CallConv == CallingConv::Fast && isVarArg) &&
"fastcc not supported on varargs functions") ? static_cast<
void> (0) : __assert_fail ("!(CallConv == CallingConv::Fast && isVarArg) && \"fastcc not supported on varargs functions\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5810, __PRETTY_FUNCTION__))
;
5811
5812 // Count how many bytes are to be pushed on the stack, including the linkage
5813 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
5814 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
5815 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
5816 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5817 unsigned NumBytes = LinkageSize;
5818 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5819 unsigned &QFPR_idx = FPR_idx;
5820
5821 static const MCPhysReg GPR[] = {
5822 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5823 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5824 };
5825 static const MCPhysReg VR[] = {
5826 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5827 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5828 };
5829
5830 const unsigned NumGPRs = array_lengthof(GPR);
5831 const unsigned NumFPRs = useSoftFloat() ? 0 : 13;
5832 const unsigned NumVRs = array_lengthof(VR);
5833 const unsigned NumQFPRs = NumFPRs;
5834
5835 // On ELFv2, we can avoid allocating the parameter area if all the arguments
5836 // can be passed to the callee in registers.
5837 // For the fast calling convention, there is another check below.
5838 // Note: We should keep consistent with LowerFormalArguments_64SVR4()
5839 bool HasParameterArea = !isELFv2ABI || isVarArg || CallConv == CallingConv::Fast;
5840 if (!HasParameterArea) {
5841 unsigned ParamAreaSize = NumGPRs * PtrByteSize;
5842 unsigned AvailableFPRs = NumFPRs;
5843 unsigned AvailableVRs = NumVRs;
5844 unsigned NumBytesTmp = NumBytes;
5845 for (unsigned i = 0; i != NumOps; ++i) {
5846 if (Outs[i].Flags.isNest()) continue;
5847 if (CalculateStackSlotUsed(Outs[i].VT, Outs[i].ArgVT, Outs[i].Flags,
5848 PtrByteSize, LinkageSize, ParamAreaSize,
5849 NumBytesTmp, AvailableFPRs, AvailableVRs,
5850 Subtarget.hasQPX()))
5851 HasParameterArea = true;
5852 }
5853 }
5854
5855 // When using the fast calling convention, we don't provide backing for
5856 // arguments that will be in registers.
5857 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
5858
5859 // Avoid allocating parameter area for fastcc functions if all the arguments
5860 // can be passed in the registers.
5861 if (CallConv == CallingConv::Fast)
5862 HasParameterArea = false;
5863
5864 // Add up all the space actually used.
5865 for (unsigned i = 0; i != NumOps; ++i) {
5866 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5867 EVT ArgVT = Outs[i].VT;
5868 EVT OrigVT = Outs[i].ArgVT;
5869
5870 if (Flags.isNest())
5871 continue;
5872
5873 if (CallConv == CallingConv::Fast) {
5874 if (Flags.isByVal()) {
5875 NumGPRsUsed += (Flags.getByValSize()+7)/8;
5876 if (NumGPRsUsed > NumGPRs)
5877 HasParameterArea = true;
5878 } else {
5879 switch (ArgVT.getSimpleVT().SimpleTy) {
5880 default: llvm_unreachable("Unexpected ValueType for argument!")::llvm::llvm_unreachable_internal("Unexpected ValueType for argument!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
, 5880)
;
5881 case MVT::i1:
5882 case MVT::i32:
5883 case MVT::i64:
5884 if (++NumGPRsUsed <= NumGPRs)
5885 continue;
5886 break;
5887 case MVT::v4i32:
5888 case MVT::v8i16:
5889 case MVT::v16i8:
5890 case MVT::v2f64:
5891 case MVT::v2i64:
5892 case MVT::v1i128:
5893 case MVT::f128:
5894 if (++NumVRsUsed <= NumVRs)
5895 continue;
5896 break;
5897 case MVT::v4f32:
5898 // When using QPX, this is handled like a FP register, otherwise, it
5899 // is an Altivec register.
5900 if (Subtarget.hasQPX()) {
5901 if (++NumFPRsUsed <= NumFPRs)
5902 continue;
5903 } else {
5904 if (++NumVRsUsed <= NumVRs)
5905 continue;
5906 }
5907 break;
5908 case MVT::f32:
5909 case MVT::f64:
5910 case MVT::v4f64: // QPX
5911 case MVT::v4i1: // QPX
5912 if (++NumFPRsUsed <= NumFPRs)
5913