Bug Summary

File:lib/Target/PowerPC/PPCInstrInfo.cpp
Warning:line 1752, column 20
Value stored to 'NewPred' during its initialization is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCInstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn345461/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/PowerPC -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-10-27-211344-32123-1 -x c++ /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp -faddrsig
1//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "MCTargetDesc/PPCPredicates.h"
16#include "PPC.h"
17#include "PPCHazardRecognizers.h"
18#include "PPCInstrBuilder.h"
19#include "PPCMachineFunctionInfo.h"
20#include "PPCTargetMachine.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/CodeGen/LiveIntervals.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunctionPass.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/PseudoSourceValue.h"
30#include "llvm/CodeGen/ScheduleDAG.h"
31#include "llvm/CodeGen/SlotIndexes.h"
32#include "llvm/CodeGen/StackMaps.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCInst.h"
35#include "llvm/Support/CommandLine.h"
36#include "llvm/Support/Debug.h"
37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/TargetRegistry.h"
39#include "llvm/Support/raw_ostream.h"
40
41using namespace llvm;
42
43#define DEBUG_TYPE"ppc-instr-info" "ppc-instr-info"
44
45#define GET_INSTRMAP_INFO
46#define GET_INSTRINFO_CTOR_DTOR
47#include "PPCGenInstrInfo.inc"
48
49STATISTIC(NumStoreSPILLVSRRCAsVec,static llvm::Statistic NumStoreSPILLVSRRCAsVec = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsVec", "Number of spillvsrrc spilled to stack as vec"
, {0}, {false}}
50 "Number of spillvsrrc spilled to stack as vec")static llvm::Statistic NumStoreSPILLVSRRCAsVec = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsVec", "Number of spillvsrrc spilled to stack as vec"
, {0}, {false}}
;
51STATISTIC(NumStoreSPILLVSRRCAsGpr,static llvm::Statistic NumStoreSPILLVSRRCAsGpr = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsGpr", "Number of spillvsrrc spilled to stack as gpr"
, {0}, {false}}
52 "Number of spillvsrrc spilled to stack as gpr")static llvm::Statistic NumStoreSPILLVSRRCAsGpr = {"ppc-instr-info"
, "NumStoreSPILLVSRRCAsGpr", "Number of spillvsrrc spilled to stack as gpr"
, {0}, {false}}
;
53STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc")static llvm::Statistic NumGPRtoVSRSpill = {"ppc-instr-info", "NumGPRtoVSRSpill"
, "Number of gpr spills to spillvsrrc", {0}, {false}}
;
54STATISTIC(CmpIselsConverted,static llvm::Statistic CmpIselsConverted = {"ppc-instr-info",
"CmpIselsConverted", "Number of ISELs that depend on comparison of constants converted"
, {0}, {false}}
55 "Number of ISELs that depend on comparison of constants converted")static llvm::Statistic CmpIselsConverted = {"ppc-instr-info",
"CmpIselsConverted", "Number of ISELs that depend on comparison of constants converted"
, {0}, {false}}
;
56STATISTIC(MissedConvertibleImmediateInstrs,static llvm::Statistic MissedConvertibleImmediateInstrs = {"ppc-instr-info"
, "MissedConvertibleImmediateInstrs", "Number of compare-immediate instructions fed by constants"
, {0}, {false}}
57 "Number of compare-immediate instructions fed by constants")static llvm::Statistic MissedConvertibleImmediateInstrs = {"ppc-instr-info"
, "MissedConvertibleImmediateInstrs", "Number of compare-immediate instructions fed by constants"
, {0}, {false}}
;
58STATISTIC(NumRcRotatesConvertedToRcAnd,static llvm::Statistic NumRcRotatesConvertedToRcAnd = {"ppc-instr-info"
, "NumRcRotatesConvertedToRcAnd", "Number of record-form rotates converted to record-form andi"
, {0}, {false}}
59 "Number of record-form rotates converted to record-form andi")static llvm::Statistic NumRcRotatesConvertedToRcAnd = {"ppc-instr-info"
, "NumRcRotatesConvertedToRcAnd", "Number of record-form rotates converted to record-form andi"
, {0}, {false}}
;
60
61static cl::
62opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
63 cl::desc("Disable analysis for CTR loops"));
64
65static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
66cl::desc("Disable compare instruction optimization"), cl::Hidden);
67
68static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
69cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
70cl::Hidden);
71
72static cl::opt<bool>
73UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
74 cl::desc("Use the old (incorrect) instruction latency calculation"));
75
76// Index into the OpcodesForSpill array.
77enum SpillOpcodeKey {
78 SOK_Int4Spill,
79 SOK_Int8Spill,
80 SOK_Float8Spill,
81 SOK_Float4Spill,
82 SOK_CRSpill,
83 SOK_CRBitSpill,
84 SOK_VRVectorSpill,
85 SOK_VSXVectorSpill,
86 SOK_VectorFloat8Spill,
87 SOK_VectorFloat4Spill,
88 SOK_VRSaveSpill,
89 SOK_QuadFloat8Spill,
90 SOK_QuadFloat4Spill,
91 SOK_QuadBitSpill,
92 SOK_SpillToVSR,
93 SOK_SPESpill,
94 SOK_SPE4Spill,
95 SOK_LastOpcodeSpill // This must be last on the enum.
96};
97
98// Pin the vtable to this file.
99void PPCInstrInfo::anchor() {}
100
101PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
102 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
103 /* CatchRetOpcode */ -1,
104 STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
105 Subtarget(STI), RI(STI.getTargetMachine()) {}
106
107/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
108/// this target when scheduling the DAG.
109ScheduleHazardRecognizer *
110PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
111 const ScheduleDAG *DAG) const {
112 unsigned Directive =
113 static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
114 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
115 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
116 const InstrItineraryData *II =
117 static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
118 return new ScoreboardHazardRecognizer(II, DAG);
119 }
120
121 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
122}
123
124/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
125/// to use for this target when scheduling the DAG.
126ScheduleHazardRecognizer *
127PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
128 const ScheduleDAG *DAG) const {
129 unsigned Directive =
130 DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
131
132 // FIXME: Leaving this as-is until we have POWER9 scheduling info
133 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
134 return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
135
136 // Most subtargets use a PPC970 recognizer.
137 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
138 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
139 assert(DAG->TII && "No InstrInfo?")((DAG->TII && "No InstrInfo?") ? static_cast<void
> (0) : __assert_fail ("DAG->TII && \"No InstrInfo?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 139, __PRETTY_FUNCTION__))
;
140
141 return new PPCHazardRecognizer970(*DAG);
142 }
143
144 return new ScoreboardHazardRecognizer(II, DAG);
145}
146
147unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
148 const MachineInstr &MI,
149 unsigned *PredCost) const {
150 if (!ItinData || UseOldLatencyCalc)
151 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
152
153 // The default implementation of getInstrLatency calls getStageLatency, but
154 // getStageLatency does not do the right thing for us. While we have
155 // itinerary, most cores are fully pipelined, and so the itineraries only
156 // express the first part of the pipeline, not every stage. Instead, we need
157 // to use the listed output operand cycle number (using operand 0 here, which
158 // is an output).
159
160 unsigned Latency = 1;
161 unsigned DefClass = MI.getDesc().getSchedClass();
162 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
163 const MachineOperand &MO = MI.getOperand(i);
164 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
165 continue;
166
167 int Cycle = ItinData->getOperandCycle(DefClass, i);
168 if (Cycle < 0)
169 continue;
170
171 Latency = std::max(Latency, (unsigned) Cycle);
172 }
173
174 return Latency;
175}
176
177int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
178 const MachineInstr &DefMI, unsigned DefIdx,
179 const MachineInstr &UseMI,
180 unsigned UseIdx) const {
181 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
182 UseMI, UseIdx);
183
184 if (!DefMI.getParent())
185 return Latency;
186
187 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
188 unsigned Reg = DefMO.getReg();
189
190 bool IsRegCR;
191 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
192 const MachineRegisterInfo *MRI =
193 &DefMI.getParent()->getParent()->getRegInfo();
194 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) ||
195 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
196 } else {
197 IsRegCR = PPC::CRRCRegClass.contains(Reg) ||
198 PPC::CRBITRCRegClass.contains(Reg);
199 }
200
201 if (UseMI.isBranch() && IsRegCR) {
202 if (Latency < 0)
203 Latency = getInstrLatency(ItinData, DefMI);
204
205 // On some cores, there is an additional delay between writing to a condition
206 // register, and using it from a branch.
207 unsigned Directive = Subtarget.getDarwinDirective();
208 switch (Directive) {
209 default: break;
210 case PPC::DIR_7400:
211 case PPC::DIR_750:
212 case PPC::DIR_970:
213 case PPC::DIR_E5500:
214 case PPC::DIR_PWR4:
215 case PPC::DIR_PWR5:
216 case PPC::DIR_PWR5X:
217 case PPC::DIR_PWR6:
218 case PPC::DIR_PWR6X:
219 case PPC::DIR_PWR7:
220 case PPC::DIR_PWR8:
221 // FIXME: Is this needed for POWER9?
222 Latency += 2;
223 break;
224 }
225 }
226
227 return Latency;
228}
229
230// This function does not list all associative and commutative operations, but
231// only those worth feeding through the machine combiner in an attempt to
232// reduce the critical path. Mostly, this means floating-point operations,
233// because they have high latencies (compared to other operations, such and
234// and/or, which are also associative and commutative, but have low latencies).
235bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
236 switch (Inst.getOpcode()) {
237 // FP Add:
238 case PPC::FADD:
239 case PPC::FADDS:
240 // FP Multiply:
241 case PPC::FMUL:
242 case PPC::FMULS:
243 // Altivec Add:
244 case PPC::VADDFP:
245 // VSX Add:
246 case PPC::XSADDDP:
247 case PPC::XVADDDP:
248 case PPC::XVADDSP:
249 case PPC::XSADDSP:
250 // VSX Multiply:
251 case PPC::XSMULDP:
252 case PPC::XVMULDP:
253 case PPC::XVMULSP:
254 case PPC::XSMULSP:
255 // QPX Add:
256 case PPC::QVFADD:
257 case PPC::QVFADDS:
258 case PPC::QVFADDSs:
259 // QPX Multiply:
260 case PPC::QVFMUL:
261 case PPC::QVFMULS:
262 case PPC::QVFMULSs:
263 return true;
264 default:
265 return false;
266 }
267}
268
269bool PPCInstrInfo::getMachineCombinerPatterns(
270 MachineInstr &Root,
271 SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
272 // Using the machine combiner in this way is potentially expensive, so
273 // restrict to when aggressive optimizations are desired.
274 if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
275 return false;
276
277 // FP reassociation is only legal when we don't need strict IEEE semantics.
278 if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
279 return false;
280
281 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
282}
283
284// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
285bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
286 unsigned &SrcReg, unsigned &DstReg,
287 unsigned &SubIdx) const {
288 switch (MI.getOpcode()) {
289 default: return false;
290 case PPC::EXTSW:
291 case PPC::EXTSW_32:
292 case PPC::EXTSW_32_64:
293 SrcReg = MI.getOperand(1).getReg();
294 DstReg = MI.getOperand(0).getReg();
295 SubIdx = PPC::sub_32;
296 return true;
297 }
298}
299
300unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
301 int &FrameIndex) const {
302 unsigned Opcode = MI.getOpcode();
303 const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
304 const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
305
306 if (End != std::find(OpcodesForSpill, End, Opcode)) {
307 // Check for the operands added by addFrameReference (the immediate is the
308 // offset which defaults to 0).
309 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
310 MI.getOperand(2).isFI()) {
311 FrameIndex = MI.getOperand(2).getIndex();
312 return MI.getOperand(0).getReg();
313 }
314 }
315 return 0;
316}
317
318// For opcodes with the ReMaterializable flag set, this function is called to
319// verify the instruction is really rematable.
320bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
321 AliasAnalysis *AA) const {
322 switch (MI.getOpcode()) {
323 default:
324 // This function should only be called for opcodes with the ReMaterializable
325 // flag set.
326 llvm_unreachable("Unknown rematerializable operation!")::llvm::llvm_unreachable_internal("Unknown rematerializable operation!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 326)
;
327 break;
328 case PPC::LI:
329 case PPC::LI8:
330 case PPC::LIS:
331 case PPC::LIS8:
332 case PPC::QVGPCI:
333 case PPC::ADDIStocHA:
334 case PPC::ADDItocL:
335 case PPC::LOAD_STACK_GUARD:
336 return true;
337 }
338 return false;
339}
340
341unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
342 int &FrameIndex) const {
343 unsigned Opcode = MI.getOpcode();
344 const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
345 const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
346
347 if (End != std::find(OpcodesForSpill, End, Opcode)) {
348 if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
349 MI.getOperand(2).isFI()) {
350 FrameIndex = MI.getOperand(2).getIndex();
351 return MI.getOperand(0).getReg();
352 }
353 }
354 return 0;
355}
356
357MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
358 unsigned OpIdx1,
359 unsigned OpIdx2) const {
360 MachineFunction &MF = *MI.getParent()->getParent();
361
362 // Normal instructions can be commuted the obvious way.
363 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
364 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
365 // Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
366 // 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
367 // changing the relative order of the mask operands might change what happens
368 // to the high-bits of the mask (and, thus, the result).
369
370 // Cannot commute if it has a non-zero rotate count.
371 if (MI.getOperand(3).getImm() != 0)
372 return nullptr;
373
374 // If we have a zero rotate count, we have:
375 // M = mask(MB,ME)
376 // Op0 = (Op1 & ~M) | (Op2 & M)
377 // Change this to:
378 // M = mask((ME+1)&31, (MB-1)&31)
379 // Op0 = (Op2 & ~M) | (Op1 & M)
380
381 // Swap op1/op2
382 assert(((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) &&((((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 &&
OpIdx2 == 1)) && "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo."
) ? static_cast<void> (0) : __assert_fail ("((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) && \"Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 383, __PRETTY_FUNCTION__))
383 "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.")((((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 &&
OpIdx2 == 1)) && "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo."
) ? static_cast<void> (0) : __assert_fail ("((OpIdx1 == 1 && OpIdx2 == 2) || (OpIdx1 == 2 && OpIdx2 == 1)) && \"Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 383, __PRETTY_FUNCTION__))
;
384 unsigned Reg0 = MI.getOperand(0).getReg();
385 unsigned Reg1 = MI.getOperand(1).getReg();
386 unsigned Reg2 = MI.getOperand(2).getReg();
387 unsigned SubReg1 = MI.getOperand(1).getSubReg();
388 unsigned SubReg2 = MI.getOperand(2).getSubReg();
389 bool Reg1IsKill = MI.getOperand(1).isKill();
390 bool Reg2IsKill = MI.getOperand(2).isKill();
391 bool ChangeReg0 = false;
392 // If machine instrs are no longer in two-address forms, update
393 // destination register as well.
394 if (Reg0 == Reg1) {
395 // Must be two address instruction!
396 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&((MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
"Expecting a two-address instruction!") ? static_cast<void
> (0) : __assert_fail ("MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && \"Expecting a two-address instruction!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 397, __PRETTY_FUNCTION__))
397 "Expecting a two-address instruction!")((MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
"Expecting a two-address instruction!") ? static_cast<void
> (0) : __assert_fail ("MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && \"Expecting a two-address instruction!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 397, __PRETTY_FUNCTION__))
;
398 assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch")((MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).getSubReg() == SubReg1 && \"Tied subreg mismatch\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 398, __PRETTY_FUNCTION__))
;
399 Reg2IsKill = false;
400 ChangeReg0 = true;
401 }
402
403 // Masks.
404 unsigned MB = MI.getOperand(4).getImm();
405 unsigned ME = MI.getOperand(5).getImm();
406
407 // We can't commute a trivial mask (there is no way to represent an all-zero
408 // mask).
409 if (MB == 0 && ME == 31)
410 return nullptr;
411
412 if (NewMI) {
413 // Create a new instruction.
414 unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
415 bool Reg0IsDead = MI.getOperand(0).isDead();
416 return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
417 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
418 .addReg(Reg2, getKillRegState(Reg2IsKill))
419 .addReg(Reg1, getKillRegState(Reg1IsKill))
420 .addImm((ME + 1) & 31)
421 .addImm((MB - 1) & 31);
422 }
423
424 if (ChangeReg0) {
425 MI.getOperand(0).setReg(Reg2);
426 MI.getOperand(0).setSubReg(SubReg2);
427 }
428 MI.getOperand(2).setReg(Reg1);
429 MI.getOperand(1).setReg(Reg2);
430 MI.getOperand(2).setSubReg(SubReg1);
431 MI.getOperand(1).setSubReg(SubReg2);
432 MI.getOperand(2).setIsKill(Reg1IsKill);
433 MI.getOperand(1).setIsKill(Reg2IsKill);
434
435 // Swap the mask around.
436 MI.getOperand(4).setImm((ME + 1) & 31);
437 MI.getOperand(5).setImm((MB - 1) & 31);
438 return &MI;
439}
440
441bool PPCInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
442 unsigned &SrcOpIdx2) const {
443 // For VSX A-Type FMA instructions, it is the first two operands that can be
444 // commuted, however, because the non-encoded tied input operand is listed
445 // first, the operands to swap are actually the second and third.
446
447 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
448 if (AltOpc == -1)
449 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
450
451 // The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
452 // and SrcOpIdx2.
453 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
454}
455
456void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
457 MachineBasicBlock::iterator MI) const {
458 // This function is used for scheduling, and the nop wanted here is the type
459 // that terminates dispatch groups on the POWER cores.
460 unsigned Directive = Subtarget.getDarwinDirective();
461 unsigned Opcode;
462 switch (Directive) {
463 default: Opcode = PPC::NOP; break;
464 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
465 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
466 case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
467 // FIXME: Update when POWER9 scheduling model is ready.
468 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
469 }
470
471 DebugLoc DL;
472 BuildMI(MBB, MI, DL, get(Opcode));
473}
474
475/// Return the noop instruction to use for a noop.
476void PPCInstrInfo::getNoop(MCInst &NopInst) const {
477 NopInst.setOpcode(PPC::NOP);
478}
479
480// Branch analysis.
481// Note: If the condition register is set to CTR or CTR8 then this is a
482// BDNZ (imm == 1) or BDZ (imm == 0) branch.
483bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
484 MachineBasicBlock *&TBB,
485 MachineBasicBlock *&FBB,
486 SmallVectorImpl<MachineOperand> &Cond,
487 bool AllowModify) const {
488 bool isPPC64 = Subtarget.isPPC64();
489
490 // If the block has no terminators, it just falls into the block after it.
491 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
492 if (I == MBB.end())
493 return false;
494
495 if (!isUnpredicatedTerminator(*I))
496 return false;
497
498 if (AllowModify) {
499 // If the BB ends with an unconditional branch to the fallthrough BB,
500 // we eliminate the branch instruction.
501 if (I->getOpcode() == PPC::B &&
502 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
503 I->eraseFromParent();
504
505 // We update iterator after deleting the last branch.
506 I = MBB.getLastNonDebugInstr();
507 if (I == MBB.end() || !isUnpredicatedTerminator(*I))
508 return false;
509 }
510 }
511
512 // Get the last instruction in the block.
513 MachineInstr &LastInst = *I;
514
515 // If there is only one terminator instruction, process it.
516 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
517 if (LastInst.getOpcode() == PPC::B) {
518 if (!LastInst.getOperand(0).isMBB())
519 return true;
520 TBB = LastInst.getOperand(0).getMBB();
521 return false;
522 } else if (LastInst.getOpcode() == PPC::BCC) {
523 if (!LastInst.getOperand(2).isMBB())
524 return true;
525 // Block ends with fall-through condbranch.
526 TBB = LastInst.getOperand(2).getMBB();
527 Cond.push_back(LastInst.getOperand(0));
528 Cond.push_back(LastInst.getOperand(1));
529 return false;
530 } else if (LastInst.getOpcode() == PPC::BC) {
531 if (!LastInst.getOperand(1).isMBB())
532 return true;
533 // Block ends with fall-through condbranch.
534 TBB = LastInst.getOperand(1).getMBB();
535 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
536 Cond.push_back(LastInst.getOperand(0));
537 return false;
538 } else if (LastInst.getOpcode() == PPC::BCn) {
539 if (!LastInst.getOperand(1).isMBB())
540 return true;
541 // Block ends with fall-through condbranch.
542 TBB = LastInst.getOperand(1).getMBB();
543 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
544 Cond.push_back(LastInst.getOperand(0));
545 return false;
546 } else if (LastInst.getOpcode() == PPC::BDNZ8 ||
547 LastInst.getOpcode() == PPC::BDNZ) {
548 if (!LastInst.getOperand(0).isMBB())
549 return true;
550 if (DisableCTRLoopAnal)
551 return true;
552 TBB = LastInst.getOperand(0).getMBB();
553 Cond.push_back(MachineOperand::CreateImm(1));
554 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
555 true));
556 return false;
557 } else if (LastInst.getOpcode() == PPC::BDZ8 ||
558 LastInst.getOpcode() == PPC::BDZ) {
559 if (!LastInst.getOperand(0).isMBB())
560 return true;
561 if (DisableCTRLoopAnal)
562 return true;
563 TBB = LastInst.getOperand(0).getMBB();
564 Cond.push_back(MachineOperand::CreateImm(0));
565 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
566 true));
567 return false;
568 }
569
570 // Otherwise, don't know what this is.
571 return true;
572 }
573
574 // Get the instruction before it if it's a terminator.
575 MachineInstr &SecondLastInst = *I;
576
577 // If there are three terminators, we don't know what sort of block this is.
578 if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
579 return true;
580
581 // If the block ends with PPC::B and PPC:BCC, handle it.
582 if (SecondLastInst.getOpcode() == PPC::BCC &&
583 LastInst.getOpcode() == PPC::B) {
584 if (!SecondLastInst.getOperand(2).isMBB() ||
585 !LastInst.getOperand(0).isMBB())
586 return true;
587 TBB = SecondLastInst.getOperand(2).getMBB();
588 Cond.push_back(SecondLastInst.getOperand(0));
589 Cond.push_back(SecondLastInst.getOperand(1));
590 FBB = LastInst.getOperand(0).getMBB();
591 return false;
592 } else if (SecondLastInst.getOpcode() == PPC::BC &&
593 LastInst.getOpcode() == PPC::B) {
594 if (!SecondLastInst.getOperand(1).isMBB() ||
595 !LastInst.getOperand(0).isMBB())
596 return true;
597 TBB = SecondLastInst.getOperand(1).getMBB();
598 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
599 Cond.push_back(SecondLastInst.getOperand(0));
600 FBB = LastInst.getOperand(0).getMBB();
601 return false;
602 } else if (SecondLastInst.getOpcode() == PPC::BCn &&
603 LastInst.getOpcode() == PPC::B) {
604 if (!SecondLastInst.getOperand(1).isMBB() ||
605 !LastInst.getOperand(0).isMBB())
606 return true;
607 TBB = SecondLastInst.getOperand(1).getMBB();
608 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
609 Cond.push_back(SecondLastInst.getOperand(0));
610 FBB = LastInst.getOperand(0).getMBB();
611 return false;
612 } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 ||
613 SecondLastInst.getOpcode() == PPC::BDNZ) &&
614 LastInst.getOpcode() == PPC::B) {
615 if (!SecondLastInst.getOperand(0).isMBB() ||
616 !LastInst.getOperand(0).isMBB())
617 return true;
618 if (DisableCTRLoopAnal)
619 return true;
620 TBB = SecondLastInst.getOperand(0).getMBB();
621 Cond.push_back(MachineOperand::CreateImm(1));
622 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
623 true));
624 FBB = LastInst.getOperand(0).getMBB();
625 return false;
626 } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 ||
627 SecondLastInst.getOpcode() == PPC::BDZ) &&
628 LastInst.getOpcode() == PPC::B) {
629 if (!SecondLastInst.getOperand(0).isMBB() ||
630 !LastInst.getOperand(0).isMBB())
631 return true;
632 if (DisableCTRLoopAnal)
633 return true;
634 TBB = SecondLastInst.getOperand(0).getMBB();
635 Cond.push_back(MachineOperand::CreateImm(0));
636 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
637 true));
638 FBB = LastInst.getOperand(0).getMBB();
639 return false;
640 }
641
642 // If the block ends with two PPC:Bs, handle it. The second one is not
643 // executed, so remove it.
644 if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
645 if (!SecondLastInst.getOperand(0).isMBB())
646 return true;
647 TBB = SecondLastInst.getOperand(0).getMBB();
648 I = LastInst;
649 if (AllowModify)
650 I->eraseFromParent();
651 return false;
652 }
653
654 // Otherwise, can't handle this.
655 return true;
656}
657
658unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB,
659 int *BytesRemoved) const {
660 assert(!BytesRemoved && "code size not handled")((!BytesRemoved && "code size not handled") ? static_cast
<void> (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 660, __PRETTY_FUNCTION__))
;
661
662 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
663 if (I == MBB.end())
664 return 0;
665
666 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
667 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
668 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
669 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
670 return 0;
671
672 // Remove the branch.
673 I->eraseFromParent();
674
675 I = MBB.end();
676
677 if (I == MBB.begin()) return 1;
678 --I;
679 if (I->getOpcode() != PPC::BCC &&
680 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
681 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
682 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
683 return 1;
684
685 // Remove the branch.
686 I->eraseFromParent();
687 return 2;
688}
689
690unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB,
691 MachineBasicBlock *TBB,
692 MachineBasicBlock *FBB,
693 ArrayRef<MachineOperand> Cond,
694 const DebugLoc &DL,
695 int *BytesAdded) const {
696 // Shouldn't be a fall through.
697 assert(TBB && "insertBranch must not be told to insert a fallthrough")((TBB && "insertBranch must not be told to insert a fallthrough"
) ? static_cast<void> (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 697, __PRETTY_FUNCTION__))
;
698 assert((Cond.size() == 2 || Cond.size() == 0) &&(((Cond.size() == 2 || Cond.size() == 0) && "PPC branch conditions have two components!"
) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 2 || Cond.size() == 0) && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 699, __PRETTY_FUNCTION__))
699 "PPC branch conditions have two components!")(((Cond.size() == 2 || Cond.size() == 0) && "PPC branch conditions have two components!"
) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 2 || Cond.size() == 0) && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 699, __PRETTY_FUNCTION__))
;
700 assert(!BytesAdded && "code size not handled")((!BytesAdded && "code size not handled") ? static_cast
<void> (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 700, __PRETTY_FUNCTION__))
;
701
702 bool isPPC64 = Subtarget.isPPC64();
703
704 // One-way branch.
705 if (!FBB) {
706 if (Cond.empty()) // Unconditional branch
707 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
708 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
709 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
710 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
711 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
712 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
713 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
714 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
715 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
716 else // Conditional branch
717 BuildMI(&MBB, DL, get(PPC::BCC))
718 .addImm(Cond[0].getImm())
719 .add(Cond[1])
720 .addMBB(TBB);
721 return 1;
722 }
723
724 // Two-way Conditional Branch.
725 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
726 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
727 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
728 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
729 else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
730 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
731 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
732 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
733 else
734 BuildMI(&MBB, DL, get(PPC::BCC))
735 .addImm(Cond[0].getImm())
736 .add(Cond[1])
737 .addMBB(TBB);
738 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
739 return 2;
740}
741
742// Select analysis.
743bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
744 ArrayRef<MachineOperand> Cond,
745 unsigned TrueReg, unsigned FalseReg,
746 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
747 if (Cond.size() != 2)
748 return false;
749
750 // If this is really a bdnz-like condition, then it cannot be turned into a
751 // select.
752 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
753 return false;
754
755 // Check register classes.
756 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
757 const TargetRegisterClass *RC =
758 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
759 if (!RC)
760 return false;
761
762 // isel is for regular integer GPRs only.
763 if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
764 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
765 !PPC::G8RCRegClass.hasSubClassEq(RC) &&
766 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
767 return false;
768
769 // FIXME: These numbers are for the A2, how well they work for other cores is
770 // an open question. On the A2, the isel instruction has a 2-cycle latency
771 // but single-cycle throughput. These numbers are used in combination with
772 // the MispredictPenalty setting from the active SchedMachineModel.
773 CondCycles = 1;
774 TrueCycles = 1;
775 FalseCycles = 1;
776
777 return true;
778}
779
780void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
781 MachineBasicBlock::iterator MI,
782 const DebugLoc &dl, unsigned DestReg,
783 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
784 unsigned FalseReg) const {
785 assert(Cond.size() == 2 &&((Cond.size() == 2 && "PPC branch conditions have two components!"
) ? static_cast<void> (0) : __assert_fail ("Cond.size() == 2 && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 786, __PRETTY_FUNCTION__))
786 "PPC branch conditions have two components!")((Cond.size() == 2 && "PPC branch conditions have two components!"
) ? static_cast<void> (0) : __assert_fail ("Cond.size() == 2 && \"PPC branch conditions have two components!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 786, __PRETTY_FUNCTION__))
;
787
788 // Get the register classes.
789 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
790 const TargetRegisterClass *RC =
791 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
792 assert(RC && "TrueReg and FalseReg must have overlapping register classes")((RC && "TrueReg and FalseReg must have overlapping register classes"
) ? static_cast<void> (0) : __assert_fail ("RC && \"TrueReg and FalseReg must have overlapping register classes\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 792, __PRETTY_FUNCTION__))
;
793
794 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) ||
795 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
796 assert((Is64Bit ||(((Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass
.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? static_cast<void> (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 799, __PRETTY_FUNCTION__))
797 PPC::GPRCRegClass.hasSubClassEq(RC) ||(((Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass
.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? static_cast<void> (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 799, __PRETTY_FUNCTION__))
798 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&(((Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass
.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? static_cast<void> (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 799, __PRETTY_FUNCTION__))
799 "isel is for regular integer GPRs only")(((Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass
.hasSubClassEq(RC)) && "isel is for regular integer GPRs only"
) ? static_cast<void> (0) : __assert_fail ("(Is64Bit || PPC::GPRCRegClass.hasSubClassEq(RC) || PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 799, __PRETTY_FUNCTION__))
;
800
801 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
802 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
803
804 unsigned SubIdx = 0;
805 bool SwapOps = false;
806 switch (SelectPred) {
807 case PPC::PRED_EQ:
808 case PPC::PRED_EQ_MINUS:
809 case PPC::PRED_EQ_PLUS:
810 SubIdx = PPC::sub_eq; SwapOps = false; break;
811 case PPC::PRED_NE:
812 case PPC::PRED_NE_MINUS:
813 case PPC::PRED_NE_PLUS:
814 SubIdx = PPC::sub_eq; SwapOps = true; break;
815 case PPC::PRED_LT:
816 case PPC::PRED_LT_MINUS:
817 case PPC::PRED_LT_PLUS:
818 SubIdx = PPC::sub_lt; SwapOps = false; break;
819 case PPC::PRED_GE:
820 case PPC::PRED_GE_MINUS:
821 case PPC::PRED_GE_PLUS:
822 SubIdx = PPC::sub_lt; SwapOps = true; break;
823 case PPC::PRED_GT:
824 case PPC::PRED_GT_MINUS:
825 case PPC::PRED_GT_PLUS:
826 SubIdx = PPC::sub_gt; SwapOps = false; break;
827 case PPC::PRED_LE:
828 case PPC::PRED_LE_MINUS:
829 case PPC::PRED_LE_PLUS:
830 SubIdx = PPC::sub_gt; SwapOps = true; break;
831 case PPC::PRED_UN:
832 case PPC::PRED_UN_MINUS:
833 case PPC::PRED_UN_PLUS:
834 SubIdx = PPC::sub_un; SwapOps = false; break;
835 case PPC::PRED_NU:
836 case PPC::PRED_NU_MINUS:
837 case PPC::PRED_NU_PLUS:
838 SubIdx = PPC::sub_un; SwapOps = true; break;
839 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
840 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
841 }
842
843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
844 SecondReg = SwapOps ? TrueReg : FalseReg;
845
846 // The first input register of isel cannot be r0. If it is a member
847 // of a register class that can be r0, then copy it first (the
848 // register allocator should eliminate the copy).
849 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) ||
850 MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
851 const TargetRegisterClass *FirstRC =
852 MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
853 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
854 unsigned OldFirstReg = FirstReg;
855 FirstReg = MRI.createVirtualRegister(FirstRC);
856 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
857 .addReg(OldFirstReg);
858 }
859
860 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
861 .addReg(FirstReg).addReg(SecondReg)
862 .addReg(Cond[1].getReg(), 0, SubIdx);
863}
864
865static unsigned getCRBitValue(unsigned CRBit) {
866 unsigned Ret = 4;
867 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT ||
868 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT ||
869 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT ||
870 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT)
871 Ret = 3;
872 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT ||
873 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT ||
874 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT ||
875 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT)
876 Ret = 2;
877 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ ||
878 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ ||
879 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ ||
880 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ)
881 Ret = 1;
882 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN ||
883 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN ||
884 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN ||
885 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN)
886 Ret = 0;
887
888 assert(Ret != 4 && "Invalid CR bit register")((Ret != 4 && "Invalid CR bit register") ? static_cast
<void> (0) : __assert_fail ("Ret != 4 && \"Invalid CR bit register\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 888, __PRETTY_FUNCTION__))
;
889 return Ret;
890}
891
892void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
893 MachineBasicBlock::iterator I,
894 const DebugLoc &DL, unsigned DestReg,
895 unsigned SrcReg, bool KillSrc) const {
896 // We can end up with self copies and similar things as a result of VSX copy
897 // legalization. Promote them here.
898 const TargetRegisterInfo *TRI = &getRegisterInfo();
899 if (PPC::F8RCRegClass.contains(DestReg) &&
900 PPC::VSRCRegClass.contains(SrcReg)) {
901 unsigned SuperReg =
902 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
903
904 if (VSXSelfCopyCrash && SrcReg == SuperReg)
905 llvm_unreachable("nop VSX copy")::llvm::llvm_unreachable_internal("nop VSX copy", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 905)
;
906
907 DestReg = SuperReg;
908 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
909 PPC::VSRCRegClass.contains(DestReg)) {
910 unsigned SuperReg =
911 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
912
913 if (VSXSelfCopyCrash && DestReg == SuperReg)
914 llvm_unreachable("nop VSX copy")::llvm::llvm_unreachable_internal("nop VSX copy", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 914)
;
915
916 SrcReg = SuperReg;
917 }
918
919 // Different class register copy
920 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
921 PPC::GPRCRegClass.contains(DestReg)) {
922 unsigned CRReg = getCRFromCRBit(SrcReg);
923 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
924 getKillRegState(KillSrc);
925 // Rotate the CR bit in the CR fields to be the least significant bit and
926 // then mask with 0x1 (MB = ME = 31).
927 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
928 .addReg(DestReg, RegState::Kill)
929 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
930 .addImm(31)
931 .addImm(31);
932 return;
933 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
934 PPC::G8RCRegClass.contains(DestReg)) {
935 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
936 getKillRegState(KillSrc);
937 return;
938 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
939 PPC::GPRCRegClass.contains(DestReg)) {
940 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
941 getKillRegState(KillSrc);
942 return;
943 } else if (PPC::G8RCRegClass.contains(SrcReg) &&
944 PPC::VSFRCRegClass.contains(DestReg)) {
945 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
946 NumGPRtoVSRSpill++;
947 getKillRegState(KillSrc);
948 return;
949 } else if (PPC::VSFRCRegClass.contains(SrcReg) &&
950 PPC::G8RCRegClass.contains(DestReg)) {
951 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
952 getKillRegState(KillSrc);
953 return;
954 } else if (PPC::SPERCRegClass.contains(SrcReg) &&
955 PPC::SPE4RCRegClass.contains(DestReg)) {
956 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
957 getKillRegState(KillSrc);
958 return;
959 } else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
960 PPC::SPERCRegClass.contains(DestReg)) {
961 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
962 getKillRegState(KillSrc);
963 return;
964 }
965
966
967 unsigned Opc;
968 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
969 Opc = PPC::OR;
970 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
971 Opc = PPC::OR8;
972 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
973 Opc = PPC::FMR;
974 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
975 Opc = PPC::MCRF;
976 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
977 Opc = PPC::VOR;
978 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
979 // There are two different ways this can be done:
980 // 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
981 // issue in VSU pipeline 0.
982 // 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
983 // can go to either pipeline.
984 // We'll always use xxlor here, because in practically all cases where
985 // copies are generated, they are close enough to some use that the
986 // lower-latency form is preferable.
987 Opc = PPC::XXLOR;
988 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
989 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
990 Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
991 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
992 Opc = PPC::QVFMR;
993 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
994 Opc = PPC::QVFMRs;
995 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
996 Opc = PPC::QVFMRb;
997 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
998 Opc = PPC::CROR;
999 else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1000 Opc = PPC::EVOR;
1001 else
1002 llvm_unreachable("Impossible reg-to-reg copy")::llvm::llvm_unreachable_internal("Impossible reg-to-reg copy"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1002)
;
1003
1004 const MCInstrDesc &MCID = get(Opc);
1005 if (MCID.getNumOperands() == 3)
1006 BuildMI(MBB, I, DL, MCID, DestReg)
1007 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1008 else
1009 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1010}
1011
1012unsigned PPCInstrInfo::getStoreOpcodeForSpill(unsigned Reg,
1013 const TargetRegisterClass *RC)
1014 const {
1015 const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1016 int OpcodeIndex = 0;
1017
1018 if (RC != nullptr) {
1019 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1020 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1021 OpcodeIndex = SOK_Int4Spill;
1022 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1023 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1024 OpcodeIndex = SOK_Int8Spill;
1025 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1026 OpcodeIndex = SOK_Float8Spill;
1027 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1028 OpcodeIndex = SOK_Float4Spill;
1029 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1030 OpcodeIndex = SOK_SPESpill;
1031 } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1032 OpcodeIndex = SOK_SPE4Spill;
1033 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1034 OpcodeIndex = SOK_CRSpill;
1035 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1036 OpcodeIndex = SOK_CRBitSpill;
1037 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1038 OpcodeIndex = SOK_VRVectorSpill;
1039 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1040 OpcodeIndex = SOK_VSXVectorSpill;
1041 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1042 OpcodeIndex = SOK_VectorFloat8Spill;
1043 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1044 OpcodeIndex = SOK_VectorFloat4Spill;
1045 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1046 OpcodeIndex = SOK_VRSaveSpill;
1047 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1048 OpcodeIndex = SOK_QuadFloat8Spill;
1049 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1050 OpcodeIndex = SOK_QuadFloat4Spill;
1051 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1052 OpcodeIndex = SOK_QuadBitSpill;
1053 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1054 OpcodeIndex = SOK_SpillToVSR;
1055 } else {
1056 llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1056)
;
1057 }
1058 } else {
1059 if (PPC::GPRCRegClass.contains(Reg) ||
1060 PPC::GPRC_NOR0RegClass.contains(Reg)) {
1061 OpcodeIndex = SOK_Int4Spill;
1062 } else if (PPC::G8RCRegClass.contains(Reg) ||
1063 PPC::G8RC_NOX0RegClass.contains(Reg)) {
1064 OpcodeIndex = SOK_Int8Spill;
1065 } else if (PPC::F8RCRegClass.contains(Reg)) {
1066 OpcodeIndex = SOK_Float8Spill;
1067 } else if (PPC::F4RCRegClass.contains(Reg)) {
1068 OpcodeIndex = SOK_Float4Spill;
1069 } else if (PPC::CRRCRegClass.contains(Reg)) {
1070 OpcodeIndex = SOK_CRSpill;
1071 } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1072 OpcodeIndex = SOK_CRBitSpill;
1073 } else if (PPC::VRRCRegClass.contains(Reg)) {
1074 OpcodeIndex = SOK_VRVectorSpill;
1075 } else if (PPC::VSRCRegClass.contains(Reg)) {
1076 OpcodeIndex = SOK_VSXVectorSpill;
1077 } else if (PPC::VSFRCRegClass.contains(Reg)) {
1078 OpcodeIndex = SOK_VectorFloat8Spill;
1079 } else if (PPC::VSSRCRegClass.contains(Reg)) {
1080 OpcodeIndex = SOK_VectorFloat4Spill;
1081 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1082 OpcodeIndex = SOK_VRSaveSpill;
1083 } else if (PPC::QFRCRegClass.contains(Reg)) {
1084 OpcodeIndex = SOK_QuadFloat8Spill;
1085 } else if (PPC::QSRCRegClass.contains(Reg)) {
1086 OpcodeIndex = SOK_QuadFloat4Spill;
1087 } else if (PPC::QBRCRegClass.contains(Reg)) {
1088 OpcodeIndex = SOK_QuadBitSpill;
1089 } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1090 OpcodeIndex = SOK_SpillToVSR;
1091 } else {
1092 llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1092)
;
1093 }
1094 }
1095 return OpcodesForSpill[OpcodeIndex];
1096}
1097
1098unsigned
1099PPCInstrInfo::getLoadOpcodeForSpill(unsigned Reg,
1100 const TargetRegisterClass *RC) const {
1101 const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1102 int OpcodeIndex = 0;
1103
1104 if (RC != nullptr) {
1105 if (PPC::GPRCRegClass.hasSubClassEq(RC) ||
1106 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1107 OpcodeIndex = SOK_Int4Spill;
1108 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) ||
1109 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1110 OpcodeIndex = SOK_Int8Spill;
1111 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1112 OpcodeIndex = SOK_Float8Spill;
1113 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1114 OpcodeIndex = SOK_Float4Spill;
1115 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1116 OpcodeIndex = SOK_SPESpill;
1117 } else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1118 OpcodeIndex = SOK_SPE4Spill;
1119 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1120 OpcodeIndex = SOK_CRSpill;
1121 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1122 OpcodeIndex = SOK_CRBitSpill;
1123 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1124 OpcodeIndex = SOK_VRVectorSpill;
1125 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1126 OpcodeIndex = SOK_VSXVectorSpill;
1127 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1128 OpcodeIndex = SOK_VectorFloat8Spill;
1129 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1130 OpcodeIndex = SOK_VectorFloat4Spill;
1131 } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1132 OpcodeIndex = SOK_VRSaveSpill;
1133 } else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1134 OpcodeIndex = SOK_QuadFloat8Spill;
1135 } else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1136 OpcodeIndex = SOK_QuadFloat4Spill;
1137 } else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1138 OpcodeIndex = SOK_QuadBitSpill;
1139 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1140 OpcodeIndex = SOK_SpillToVSR;
1141 } else {
1142 llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1142)
;
1143 }
1144 } else {
1145 if (PPC::GPRCRegClass.contains(Reg) ||
1146 PPC::GPRC_NOR0RegClass.contains(Reg)) {
1147 OpcodeIndex = SOK_Int4Spill;
1148 } else if (PPC::G8RCRegClass.contains(Reg) ||
1149 PPC::G8RC_NOX0RegClass.contains(Reg)) {
1150 OpcodeIndex = SOK_Int8Spill;
1151 } else if (PPC::F8RCRegClass.contains(Reg)) {
1152 OpcodeIndex = SOK_Float8Spill;
1153 } else if (PPC::F4RCRegClass.contains(Reg)) {
1154 OpcodeIndex = SOK_Float4Spill;
1155 } else if (PPC::CRRCRegClass.contains(Reg)) {
1156 OpcodeIndex = SOK_CRSpill;
1157 } else if (PPC::CRBITRCRegClass.contains(Reg)) {
1158 OpcodeIndex = SOK_CRBitSpill;
1159 } else if (PPC::VRRCRegClass.contains(Reg)) {
1160 OpcodeIndex = SOK_VRVectorSpill;
1161 } else if (PPC::VSRCRegClass.contains(Reg)) {
1162 OpcodeIndex = SOK_VSXVectorSpill;
1163 } else if (PPC::VSFRCRegClass.contains(Reg)) {
1164 OpcodeIndex = SOK_VectorFloat8Spill;
1165 } else if (PPC::VSSRCRegClass.contains(Reg)) {
1166 OpcodeIndex = SOK_VectorFloat4Spill;
1167 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1168 OpcodeIndex = SOK_VRSaveSpill;
1169 } else if (PPC::QFRCRegClass.contains(Reg)) {
1170 OpcodeIndex = SOK_QuadFloat8Spill;
1171 } else if (PPC::QSRCRegClass.contains(Reg)) {
1172 OpcodeIndex = SOK_QuadFloat4Spill;
1173 } else if (PPC::QBRCRegClass.contains(Reg)) {
1174 OpcodeIndex = SOK_QuadBitSpill;
1175 } else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1176 OpcodeIndex = SOK_SpillToVSR;
1177 } else {
1178 llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1178)
;
1179 }
1180 }
1181 return OpcodesForSpill[OpcodeIndex];
1182}
1183
1184void PPCInstrInfo::StoreRegToStackSlot(
1185 MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1186 const TargetRegisterClass *RC,
1187 SmallVectorImpl<MachineInstr *> &NewMIs) const {
1188 unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1189 DebugLoc DL;
1190
1191 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1192 FuncInfo->setHasSpills();
1193
1194 NewMIs.push_back(addFrameReference(
1195 BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1196 FrameIdx));
1197
1198 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1199 PPC::CRBITRCRegClass.hasSubClassEq(RC))
1200 FuncInfo->setSpillsCR();
1201
1202 if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1203 FuncInfo->setSpillsVRSAVE();
1204
1205 if (isXFormMemOp(Opcode))
1206 FuncInfo->setHasNonRISpills();
1207}
1208
1209void PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1210 MachineBasicBlock::iterator MI,
1211 unsigned SrcReg, bool isKill,
1212 int FrameIdx,
1213 const TargetRegisterClass *RC,
1214 const TargetRegisterInfo *TRI) const {
1215 MachineFunction &MF = *MBB.getParent();
1216 SmallVector<MachineInstr *, 4> NewMIs;
1217
1218 // We need to avoid a situation in which the value from a VRRC register is
1219 // spilled using an Altivec instruction and reloaded into a VSRC register
1220 // using a VSX instruction. The issue with this is that the VSX
1221 // load/store instructions swap the doublewords in the vector and the Altivec
1222 // ones don't. The register classes on the spill/reload may be different if
1223 // the register is defined using an Altivec instruction and is then used by a
1224 // VSX instruction.
1225 RC = updatedRC(RC);
1226
1227 StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1228
1229 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1230 MBB.insert(MI, NewMIs[i]);
1231
1232 const MachineFrameInfo &MFI = MF.getFrameInfo();
1233 MachineMemOperand *MMO = MF.getMachineMemOperand(
1234 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1235 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
1236 MFI.getObjectAlignment(FrameIdx));
1237 NewMIs.back()->addMemOperand(MF, MMO);
1238}
1239
1240void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1241 unsigned DestReg, int FrameIdx,
1242 const TargetRegisterClass *RC,
1243 SmallVectorImpl<MachineInstr *> &NewMIs)
1244 const {
1245 unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1246 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1247 FrameIdx));
1248 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1249
1250 if (PPC::CRRCRegClass.hasSubClassEq(RC) ||
1251 PPC::CRBITRCRegClass.hasSubClassEq(RC))
1252 FuncInfo->setSpillsCR();
1253
1254 if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1255 FuncInfo->setSpillsVRSAVE();
1256
1257 if (isXFormMemOp(Opcode))
1258 FuncInfo->setHasNonRISpills();
1259}
1260
1261void
1262PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1263 MachineBasicBlock::iterator MI,
1264 unsigned DestReg, int FrameIdx,
1265 const TargetRegisterClass *RC,
1266 const TargetRegisterInfo *TRI) const {
1267 MachineFunction &MF = *MBB.getParent();
1268 SmallVector<MachineInstr*, 4> NewMIs;
1269 DebugLoc DL;
1270 if (MI != MBB.end()) DL = MI->getDebugLoc();
1271
1272 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1273 FuncInfo->setHasSpills();
1274
1275 // We need to avoid a situation in which the value from a VRRC register is
1276 // spilled using an Altivec instruction and reloaded into a VSRC register
1277 // using a VSX instruction. The issue with this is that the VSX
1278 // load/store instructions swap the doublewords in the vector and the Altivec
1279 // ones don't. The register classes on the spill/reload may be different if
1280 // the register is defined using an Altivec instruction and is then used by a
1281 // VSX instruction.
1282 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1283 RC = &PPC::VSRCRegClass;
1284
1285 LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1286
1287 for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1288 MBB.insert(MI, NewMIs[i]);
1289
1290 const MachineFrameInfo &MFI = MF.getFrameInfo();
1291 MachineMemOperand *MMO = MF.getMachineMemOperand(
1292 MachinePointerInfo::getFixedStack(MF, FrameIdx),
1293 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
1294 MFI.getObjectAlignment(FrameIdx));
1295 NewMIs.back()->addMemOperand(MF, MMO);
1296}
1297
1298bool PPCInstrInfo::
1299reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1300 assert(Cond.size() == 2 && "Invalid PPC branch opcode!")((Cond.size() == 2 && "Invalid PPC branch opcode!") ?
static_cast<void> (0) : __assert_fail ("Cond.size() == 2 && \"Invalid PPC branch opcode!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1300, __PRETTY_FUNCTION__))
;
1301 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1302 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1303 else
1304 // Leave the CR# the same, but invert the condition.
1305 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1306 return false;
1307}
1308
1309bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1310 unsigned Reg, MachineRegisterInfo *MRI) const {
1311 // For some instructions, it is legal to fold ZERO into the RA register field.
1312 // A zero immediate should always be loaded with a single li.
1313 unsigned DefOpc = DefMI.getOpcode();
1314 if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1315 return false;
1316 if (!DefMI.getOperand(1).isImm())
1317 return false;
1318 if (DefMI.getOperand(1).getImm() != 0)
1319 return false;
1320
1321 // Note that we cannot here invert the arguments of an isel in order to fold
1322 // a ZERO into what is presented as the second argument. All we have here
1323 // is the condition bit, and that might come from a CR-logical bit operation.
1324
1325 const MCInstrDesc &UseMCID = UseMI.getDesc();
1326
1327 // Only fold into real machine instructions.
1328 if (UseMCID.isPseudo())
1329 return false;
1330
1331 unsigned UseIdx;
1332 for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1333 if (UseMI.getOperand(UseIdx).isReg() &&
1334 UseMI.getOperand(UseIdx).getReg() == Reg)
1335 break;
1336
1337 assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI")((UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI"
) ? static_cast<void> (0) : __assert_fail ("UseIdx < UseMI.getNumOperands() && \"Cannot find Reg in UseMI\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1337, __PRETTY_FUNCTION__))
;
1338 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg")((UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"
) ? static_cast<void> (0) : __assert_fail ("UseIdx < UseMCID.getNumOperands() && \"No operand description for Reg\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1338, __PRETTY_FUNCTION__))
;
1339
1340 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1341
1342 // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1343 // register (which might also be specified as a pointer class kind).
1344 if (UseInfo->isLookupPtrRegClass()) {
1345 if (UseInfo->RegClass /* Kind */ != 1)
1346 return false;
1347 } else {
1348 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1349 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1350 return false;
1351 }
1352
1353 // Make sure this is not tied to an output register (or otherwise
1354 // constrained). This is true for ST?UX registers, for example, which
1355 // are tied to their output registers.
1356 if (UseInfo->Constraints != 0)
1357 return false;
1358
1359 unsigned ZeroReg;
1360 if (UseInfo->isLookupPtrRegClass()) {
1361 bool isPPC64 = Subtarget.isPPC64();
1362 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1363 } else {
1364 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1365 PPC::ZERO8 : PPC::ZERO;
1366 }
1367
1368 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1369 UseMI.getOperand(UseIdx).setReg(ZeroReg);
1370
1371 if (DeleteDef)
1372 DefMI.eraseFromParent();
1373
1374 return true;
1375}
1376
1377static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1378 for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1379 I != IE; ++I)
1380 if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
1381 return true;
1382 return false;
1383}
1384
1385// We should make sure that, if we're going to predicate both sides of a
1386// condition (a diamond), that both sides don't define the counter register. We
1387// can predicate counter-decrement-based branches, but while that predicates
1388// the branching, it does not predicate the counter decrement. If we tried to
1389// merge the triangle into one predicated block, we'd decrement the counter
1390// twice.
1391bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1392 unsigned NumT, unsigned ExtraT,
1393 MachineBasicBlock &FMBB,
1394 unsigned NumF, unsigned ExtraF,
1395 BranchProbability Probability) const {
1396 return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1397}
1398
1399
1400bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const {
1401 // The predicated branches are identified by their type, not really by the
1402 // explicit presence of a predicate. Furthermore, some of them can be
1403 // predicated more than once. Because if conversion won't try to predicate
1404 // any instruction which already claims to be predicated (by returning true
1405 // here), always return false. In doing so, we let isPredicable() be the
1406 // final word on whether not the instruction can be (further) predicated.
1407
1408 return false;
1409}
1410
1411bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
1412 if (!MI.isTerminator())
1413 return false;
1414
1415 // Conditional branch is a special case.
1416 if (MI.isBranch() && !MI.isBarrier())
1417 return true;
1418
1419 return !isPredicated(MI);
1420}
1421
1422bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
1423 ArrayRef<MachineOperand> Pred) const {
1424 unsigned OpC = MI.getOpcode();
1425 if (OpC == PPC::BLR || OpC == PPC::BLR8) {
1426 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1427 bool isPPC64 = Subtarget.isPPC64();
1428 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1429 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1430 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1431 MI.setDesc(get(PPC::BCLR));
1432 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1433 .addReg(Pred[1].getReg());
1434 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1435 MI.setDesc(get(PPC::BCLRn));
1436 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1437 .addReg(Pred[1].getReg());
1438 } else {
1439 MI.setDesc(get(PPC::BCCLR));
1440 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1441 .addImm(Pred[0].getImm())
1442 .addReg(Pred[1].getReg());
1443 }
1444
1445 return true;
1446 } else if (OpC == PPC::B) {
1447 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1448 bool isPPC64 = Subtarget.isPPC64();
1449 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1450 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1451 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1452 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1453 MI.RemoveOperand(0);
1454
1455 MI.setDesc(get(PPC::BC));
1456 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1457 .addReg(Pred[1].getReg())
1458 .addMBB(MBB);
1459 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1460 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1461 MI.RemoveOperand(0);
1462
1463 MI.setDesc(get(PPC::BCn));
1464 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1465 .addReg(Pred[1].getReg())
1466 .addMBB(MBB);
1467 } else {
1468 MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1469 MI.RemoveOperand(0);
1470
1471 MI.setDesc(get(PPC::BCC));
1472 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1473 .addImm(Pred[0].getImm())
1474 .addReg(Pred[1].getReg())
1475 .addMBB(MBB);
1476 }
1477
1478 return true;
1479 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 ||
1480 OpC == PPC::BCTRL || OpC == PPC::BCTRL8) {
1481 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1482 llvm_unreachable("Cannot predicate bctr[l] on the ctr register")::llvm::llvm_unreachable_internal("Cannot predicate bctr[l] on the ctr register"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1482)
;
1483
1484 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8;
1485 bool isPPC64 = Subtarget.isPPC64();
1486
1487 if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1488 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1489 : (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1490 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1491 .addReg(Pred[1].getReg());
1492 return true;
1493 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1494 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1495 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1496 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1497 .addReg(Pred[1].getReg());
1498 return true;
1499 }
1500
1501 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1502 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1503 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1504 .addImm(Pred[0].getImm())
1505 .addReg(Pred[1].getReg());
1506 return true;
1507 }
1508
1509 return false;
1510}
1511
1512bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1513 ArrayRef<MachineOperand> Pred2) const {
1514 assert(Pred1.size() == 2 && "Invalid PPC first predicate")((Pred1.size() == 2 && "Invalid PPC first predicate")
? static_cast<void> (0) : __assert_fail ("Pred1.size() == 2 && \"Invalid PPC first predicate\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1514, __PRETTY_FUNCTION__))
;
1515 assert(Pred2.size() == 2 && "Invalid PPC second predicate")((Pred2.size() == 2 && "Invalid PPC second predicate"
) ? static_cast<void> (0) : __assert_fail ("Pred2.size() == 2 && \"Invalid PPC second predicate\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1515, __PRETTY_FUNCTION__))
;
1516
1517 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1518 return false;
1519 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1520 return false;
1521
1522 // P1 can only subsume P2 if they test the same condition register.
1523 if (Pred1[1].getReg() != Pred2[1].getReg())
1524 return false;
1525
1526 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1527 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1528
1529 if (P1 == P2)
1530 return true;
1531
1532 // Does P1 subsume P2, e.g. GE subsumes GT.
1533 if (P1 == PPC::PRED_LE &&
1534 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
1535 return true;
1536 if (P1 == PPC::PRED_GE &&
1537 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
1538 return true;
1539
1540 return false;
1541}
1542
1543bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI,
1544 std::vector<MachineOperand> &Pred) const {
1545 // Note: At the present time, the contents of Pred from this function is
1546 // unused by IfConversion. This implementation follows ARM by pushing the
1547 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1548 // predicate, instructions defining CTR or CTR8 are also included as
1549 // predicate-defining instructions.
1550
1551 const TargetRegisterClass *RCs[] =
1552 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1553 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1554
1555 bool Found = false;
1556 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1557 const MachineOperand &MO = MI.getOperand(i);
1558 for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1559 const TargetRegisterClass *RC = RCs[c];
1560 if (MO.isReg()) {
1561 if (MO.isDef() && RC->contains(MO.getReg())) {
1562 Pred.push_back(MO);
1563 Found = true;
1564 }
1565 } else if (MO.isRegMask()) {
1566 for (TargetRegisterClass::iterator I = RC->begin(),
1567 IE = RC->end(); I != IE; ++I)
1568 if (MO.clobbersPhysReg(*I)) {
1569 Pred.push_back(MO);
1570 Found = true;
1571 }
1572 }
1573 }
1574 }
1575
1576 return Found;
1577}
1578
1579bool PPCInstrInfo::isPredicable(const MachineInstr &MI) const {
1580 unsigned OpC = MI.getOpcode();
1581 switch (OpC) {
1582 default:
1583 return false;
1584 case PPC::B:
1585 case PPC::BLR:
1586 case PPC::BLR8:
1587 case PPC::BCTR:
1588 case PPC::BCTR8:
1589 case PPC::BCTRL:
1590 case PPC::BCTRL8:
1591 return true;
1592 }
1593}
1594
1595bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1596 unsigned &SrcReg2, int &Mask,
1597 int &Value) const {
1598 unsigned Opc = MI.getOpcode();
1599
1600 switch (Opc) {
1601 default: return false;
1602 case PPC::CMPWI:
1603 case PPC::CMPLWI:
1604 case PPC::CMPDI:
1605 case PPC::CMPLDI:
1606 SrcReg = MI.getOperand(1).getReg();
1607 SrcReg2 = 0;
1608 Value = MI.getOperand(2).getImm();
1609 Mask = 0xFFFF;
1610 return true;
1611 case PPC::CMPW:
1612 case PPC::CMPLW:
1613 case PPC::CMPD:
1614 case PPC::CMPLD:
1615 case PPC::FCMPUS:
1616 case PPC::FCMPUD:
1617 SrcReg = MI.getOperand(1).getReg();
1618 SrcReg2 = MI.getOperand(2).getReg();
1619 Value = 0;
1620 Mask = 0;
1621 return true;
1622 }
1623}
1624
1625bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1626 unsigned SrcReg2, int Mask, int Value,
1627 const MachineRegisterInfo *MRI) const {
1628 if (DisableCmpOpt)
1629 return false;
1630
1631 int OpC = CmpInstr.getOpcode();
1632 unsigned CRReg = CmpInstr.getOperand(0).getReg();
1633
1634 // FP record forms set CR1 based on the exception status bits, not a
1635 // comparison with zero.
1636 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
1637 return false;
1638
1639 // The record forms set the condition register based on a signed comparison
1640 // with zero (so says the ISA manual). This is not as straightforward as it
1641 // seems, however, because this is always a 64-bit comparison on PPC64, even
1642 // for instructions that are 32-bit in nature (like slw for example).
1643 // So, on PPC32, for unsigned comparisons, we can use the record forms only
1644 // for equality checks (as those don't depend on the sign). On PPC64,
1645 // we are restricted to equality for unsigned 64-bit comparisons and for
1646 // signed 32-bit comparisons the applicability is more restricted.
1647 bool isPPC64 = Subtarget.isPPC64();
1648 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
1649 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
1650 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
1651
1652 // Get the unique definition of SrcReg.
1653 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1654 if (!MI) return false;
1655
1656 bool equalityOnly = false;
1657 bool noSub = false;
1658 if (isPPC64) {
1659 if (is32BitSignedCompare) {
1660 // We can perform this optimization only if MI is sign-extending.
1661 if (isSignExtended(*MI))
1662 noSub = true;
1663 else
1664 return false;
1665 } else if (is32BitUnsignedCompare) {
1666 // We can perform this optimization, equality only, if MI is
1667 // zero-extending.
1668 if (isZeroExtended(*MI)) {
1669 noSub = true;
1670 equalityOnly = true;
1671 } else
1672 return false;
1673 } else
1674 equalityOnly = is64BitUnsignedCompare;
1675 } else
1676 equalityOnly = is32BitUnsignedCompare;
1677
1678 if (equalityOnly) {
1679 // We need to check the uses of the condition register in order to reject
1680 // non-equality comparisons.
1681 for (MachineRegisterInfo::use_instr_iterator
1682 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1683 I != IE; ++I) {
1684 MachineInstr *UseMI = &*I;
1685 if (UseMI->getOpcode() == PPC::BCC) {
1686 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1687 unsigned PredCond = PPC::getPredicateCondition(Pred);
1688 // We ignore hint bits when checking for non-equality comparisons.
1689 if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1690 return false;
1691 } else if (UseMI->getOpcode() == PPC::ISEL ||
1692 UseMI->getOpcode() == PPC::ISEL8) {
1693 unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1694 if (SubIdx != PPC::sub_eq)
1695 return false;
1696 } else
1697 return false;
1698 }
1699 }
1700
1701 MachineBasicBlock::iterator I = CmpInstr;
1702
1703 // Scan forward to find the first use of the compare.
1704 for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1705 ++I) {
1706 bool FoundUse = false;
1707 for (MachineRegisterInfo::use_instr_iterator
1708 J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1709 J != JE; ++J)
1710 if (&*J == &*I) {
1711 FoundUse = true;
1712 break;
1713 }
1714
1715 if (FoundUse)
1716 break;
1717 }
1718
1719 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1720 SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1721
1722 // There are two possible candidates which can be changed to set CR[01].
1723 // One is MI, the other is a SUB instruction.
1724 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1725 MachineInstr *Sub = nullptr;
1726 if (SrcReg2 != 0)
1727 // MI is not a candidate for CMPrr.
1728 MI = nullptr;
1729 // FIXME: Conservatively refuse to convert an instruction which isn't in the
1730 // same BB as the comparison. This is to allow the check below to avoid calls
1731 // (and other explicit clobbers); instead we should really check for these
1732 // more explicitly (in at least a few predecessors).
1733 else if (MI->getParent() != CmpInstr.getParent())
1734 return false;
1735 else if (Value != 0) {
1736 // The record-form instructions set CR bit based on signed comparison
1737 // against 0. We try to convert a compare against 1 or -1 into a compare
1738 // against 0 to exploit record-form instructions. For example, we change
1739 // the condition "greater than -1" into "greater than or equal to 0"
1740 // and "less than 1" into "less than or equal to 0".
1741
1742 // Since we optimize comparison based on a specific branch condition,
1743 // we don't optimize if condition code is used by more than once.
1744 if (equalityOnly || !MRI->hasOneUse(CRReg))
1745 return false;
1746
1747 MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);
1748 if (UseMI->getOpcode() != PPC::BCC)
1749 return false;
1750
1751 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1752 PPC::Predicate NewPred = Pred;
Value stored to 'NewPred' during its initialization is never read
1753 unsigned PredCond = PPC::getPredicateCondition(Pred);
1754 unsigned PredHint = PPC::getPredicateHint(Pred);
1755 int16_t Immed = (int16_t)Value;
1756
1757 // When modifying the condition in the predicate, we propagate hint bits
1758 // from the original predicate to the new one.
1759 if (Immed == -1 && PredCond == PPC::PRED_GT)
1760 // We convert "greater than -1" into "greater than or equal to 0",
1761 // since we are assuming signed comparison by !equalityOnly
1762 NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1763 else if (Immed == -1 && PredCond == PPC::PRED_LE)
1764 // We convert "less than or equal to -1" into "less than 0".
1765 NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1766 else if (Immed == 1 && PredCond == PPC::PRED_LT)
1767 // We convert "less than 1" into "less than or equal to 0".
1768 NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1769 else if (Immed == 1 && PredCond == PPC::PRED_GE)
1770 // We convert "greater than or equal to 1" into "greater than 0".
1771 NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1772 else
1773 return false;
1774
1775 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1776 NewPred));
1777 }
1778
1779 // Search for Sub.
1780 const TargetRegisterInfo *TRI = &getRegisterInfo();
1781 --I;
1782
1783 // Get ready to iterate backward from CmpInstr.
1784 MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1785
1786 for (; I != E && !noSub; --I) {
1787 const MachineInstr &Instr = *I;
1788 unsigned IOpC = Instr.getOpcode();
1789
1790 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) ||
1791 Instr.readsRegister(PPC::CR0, TRI)))
1792 // This instruction modifies or uses the record condition register after
1793 // the one we want to change. While we could do this transformation, it
1794 // would likely not be profitable. This transformation removes one
1795 // instruction, and so even forcing RA to generate one move probably
1796 // makes it unprofitable.
1797 return false;
1798
1799 // Check whether CmpInstr can be made redundant by the current instruction.
1800 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
1801 OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
1802 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
1803 ((Instr.getOperand(1).getReg() == SrcReg &&
1804 Instr.getOperand(2).getReg() == SrcReg2) ||
1805 (Instr.getOperand(1).getReg() == SrcReg2 &&
1806 Instr.getOperand(2).getReg() == SrcReg))) {
1807 Sub = &*I;
1808 break;
1809 }
1810
1811 if (I == B)
1812 // The 'and' is below the comparison instruction.
1813 return false;
1814 }
1815
1816 // Return false if no candidates exist.
1817 if (!MI && !Sub)
1818 return false;
1819
1820 // The single candidate is called MI.
1821 if (!MI) MI = Sub;
1822
1823 int NewOpC = -1;
1824 int MIOpC = MI->getOpcode();
1825 if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
1826 MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
1827 NewOpC = MIOpC;
1828 else {
1829 NewOpC = PPC::getRecordFormOpcode(MIOpC);
1830 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1831 NewOpC = MIOpC;
1832 }
1833
1834 // FIXME: On the non-embedded POWER architectures, only some of the record
1835 // forms are fast, and we should use only the fast ones.
1836
1837 // The defining instruction has a record form (or is already a record
1838 // form). It is possible, however, that we'll need to reverse the condition
1839 // code of the users.
1840 if (NewOpC == -1)
1841 return false;
1842
1843 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1844 // needs to be updated to be based on SUB. Push the condition code
1845 // operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1846 // condition code of these operands will be modified.
1847 // Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1848 // comparison against 0, which may modify predicate.
1849 bool ShouldSwap = false;
1850 if (Sub && Value == 0) {
1851 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1852 Sub->getOperand(2).getReg() == SrcReg;
1853
1854 // The operands to subf are the opposite of sub, so only in the fixed-point
1855 // case, invert the order.
1856 ShouldSwap = !ShouldSwap;
1857 }
1858
1859 if (ShouldSwap)
1860 for (MachineRegisterInfo::use_instr_iterator
1861 I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1862 I != IE; ++I) {
1863 MachineInstr *UseMI = &*I;
1864 if (UseMI->getOpcode() == PPC::BCC) {
1865 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1866 unsigned PredCond = PPC::getPredicateCondition(Pred);
1867 assert((!equalityOnly ||(((!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC
::PRED_NE) && "Invalid predicate for equality-only optimization"
) ? static_cast<void> (0) : __assert_fail ("(!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1869, __PRETTY_FUNCTION__))
1868 PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) &&(((!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC
::PRED_NE) && "Invalid predicate for equality-only optimization"
) ? static_cast<void> (0) : __assert_fail ("(!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1869, __PRETTY_FUNCTION__))
1869 "Invalid predicate for equality-only optimization")(((!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC
::PRED_NE) && "Invalid predicate for equality-only optimization"
) ? static_cast<void> (0) : __assert_fail ("(!equalityOnly || PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1869, __PRETTY_FUNCTION__))
;
1870 (void)PredCond; // To suppress warning in release build.
1871 PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1872 PPC::getSwappedPredicate(Pred)));
1873 } else if (UseMI->getOpcode() == PPC::ISEL ||
1874 UseMI->getOpcode() == PPC::ISEL8) {
1875 unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1876 assert((!equalityOnly || NewSubReg == PPC::sub_eq) &&(((!equalityOnly || NewSubReg == PPC::sub_eq) && "Invalid CR bit for equality-only optimization"
) ? static_cast<void> (0) : __assert_fail ("(!equalityOnly || NewSubReg == PPC::sub_eq) && \"Invalid CR bit for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1877, __PRETTY_FUNCTION__))
1877 "Invalid CR bit for equality-only optimization")(((!equalityOnly || NewSubReg == PPC::sub_eq) && "Invalid CR bit for equality-only optimization"
) ? static_cast<void> (0) : __assert_fail ("(!equalityOnly || NewSubReg == PPC::sub_eq) && \"Invalid CR bit for equality-only optimization\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1877, __PRETTY_FUNCTION__))
;
1878
1879 if (NewSubReg == PPC::sub_lt)
1880 NewSubReg = PPC::sub_gt;
1881 else if (NewSubReg == PPC::sub_gt)
1882 NewSubReg = PPC::sub_lt;
1883
1884 SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1885 NewSubReg));
1886 } else // We need to abort on a user we don't understand.
1887 return false;
1888 }
1889 assert(!(Value != 0 && ShouldSwap) &&((!(Value != 0 && ShouldSwap) && "Non-zero immediate support and ShouldSwap"
"may conflict in updating predicate") ? static_cast<void>
(0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1891, __PRETTY_FUNCTION__))
1890 "Non-zero immediate support and ShouldSwap"((!(Value != 0 && ShouldSwap) && "Non-zero immediate support and ShouldSwap"
"may conflict in updating predicate") ? static_cast<void>
(0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1891, __PRETTY_FUNCTION__))
1891 "may conflict in updating predicate")((!(Value != 0 && ShouldSwap) && "Non-zero immediate support and ShouldSwap"
"may conflict in updating predicate") ? static_cast<void>
(0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1891, __PRETTY_FUNCTION__))
;
1892
1893 // Create a new virtual register to hold the value of the CR set by the
1894 // record-form instruction. If the instruction was not previously in
1895 // record form, then set the kill flag on the CR.
1896 CmpInstr.eraseFromParent();
1897
1898 MachineBasicBlock::iterator MII = MI;
1899 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1900 get(TargetOpcode::COPY), CRReg)
1901 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1902
1903 // Even if CR0 register were dead before, it is alive now since the
1904 // instruction we just built uses it.
1905 MI->clearRegisterDeads(PPC::CR0);
1906
1907 if (MIOpC != NewOpC) {
1908 // We need to be careful here: we're replacing one instruction with
1909 // another, and we need to make sure that we get all of the right
1910 // implicit uses and defs. On the other hand, the caller may be holding
1911 // an iterator to this instruction, and so we can't delete it (this is
1912 // specifically the case if this is the instruction directly after the
1913 // compare).
1914
1915 // Rotates are expensive instructions. If we're emitting a record-form
1916 // rotate that can just be an andi/andis, we should just emit that.
1917 if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) {
1918 unsigned GPRRes = MI->getOperand(0).getReg();
1919 int64_t SH = MI->getOperand(2).getImm();
1920 int64_t MB = MI->getOperand(3).getImm();
1921 int64_t ME = MI->getOperand(4).getImm();
1922 // We can only do this if both the start and end of the mask are in the
1923 // same halfword.
1924 bool MBInLoHWord = MB >= 16;
1925 bool MEInLoHWord = ME >= 16;
1926 uint64_t Mask = ~0LLU;
1927
1928 if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
1929 Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1930 // The mask value needs to shift right 16 if we're emitting andis.
1931 Mask >>= MBInLoHWord ? 0 : 16;
1932 NewOpC = MIOpC == PPC::RLWINM ?
1933 (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
1934 (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
1935 } else if (MRI->use_empty(GPRRes) && (ME == 31) &&
1936 (ME - MB + 1 == SH) && (MB >= 16)) {
1937 // If we are rotating by the exact number of bits as are in the mask
1938 // and the mask is in the least significant bits of the register,
1939 // that's just an andis. (as long as the GPR result has no uses).
1940 Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
1941 Mask >>= 16;
1942 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
1943 }
1944 // If we've set the mask, we can transform.
1945 if (Mask != ~0LLU) {
1946 MI->RemoveOperand(4);
1947 MI->RemoveOperand(3);
1948 MI->getOperand(2).setImm(Mask);
1949 NumRcRotatesConvertedToRcAnd++;
1950 }
1951 } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1952 int64_t MB = MI->getOperand(3).getImm();
1953 if (MB >= 48) {
1954 uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1955 NewOpC = PPC::ANDIo8;
1956 MI->RemoveOperand(3);
1957 MI->getOperand(2).setImm(Mask);
1958 NumRcRotatesConvertedToRcAnd++;
1959 }
1960 }
1961
1962 const MCInstrDesc &NewDesc = get(NewOpC);
1963 MI->setDesc(NewDesc);
1964
1965 if (NewDesc.ImplicitDefs)
1966 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1967 *ImpDefs; ++ImpDefs)
1968 if (!MI->definesRegister(*ImpDefs))
1969 MI->addOperand(*MI->getParent()->getParent(),
1970 MachineOperand::CreateReg(*ImpDefs, true, true));
1971 if (NewDesc.ImplicitUses)
1972 for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1973 *ImpUses; ++ImpUses)
1974 if (!MI->readsRegister(*ImpUses))
1975 MI->addOperand(*MI->getParent()->getParent(),
1976 MachineOperand::CreateReg(*ImpUses, false, true));
1977 }
1978 assert(MI->definesRegister(PPC::CR0) &&((MI->definesRegister(PPC::CR0) && "Record-form instruction does not define cr0?"
) ? static_cast<void> (0) : __assert_fail ("MI->definesRegister(PPC::CR0) && \"Record-form instruction does not define cr0?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1979, __PRETTY_FUNCTION__))
1979 "Record-form instruction does not define cr0?")((MI->definesRegister(PPC::CR0) && "Record-form instruction does not define cr0?"
) ? static_cast<void> (0) : __assert_fail ("MI->definesRegister(PPC::CR0) && \"Record-form instruction does not define cr0?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 1979, __PRETTY_FUNCTION__))
;
1980
1981 // Modify the condition code of operands in OperandsToUpdate.
1982 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
1983 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
1984 for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
1985 PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
1986
1987 for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
1988 SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
1989
1990 return true;
1991}
1992
1993/// GetInstSize - Return the number of bytes of code the specified
1994/// instruction may be. This returns the maximum number of bytes.
1995///
1996unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1997 unsigned Opcode = MI.getOpcode();
1998
1999 if (Opcode == PPC::INLINEASM) {
2000 const MachineFunction *MF = MI.getParent()->getParent();
2001 const char *AsmStr = MI.getOperand(0).getSymbolName();
2002 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
2003 } else if (Opcode == TargetOpcode::STACKMAP) {
2004 StackMapOpers Opers(&MI);
2005 return Opers.getNumPatchBytes();
2006 } else if (Opcode == TargetOpcode::PATCHPOINT) {
2007 PatchPointOpers Opers(&MI);
2008 return Opers.getNumPatchBytes();
2009 } else {
2010 return get(Opcode).getSize();
2011 }
2012}
2013
2014std::pair<unsigned, unsigned>
2015PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
2016 const unsigned Mask = PPCII::MO_ACCESS_MASK;
2017 return std::make_pair(TF & Mask, TF & ~Mask);
2018}
2019
2020ArrayRef<std::pair<unsigned, const char *>>
2021PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
2022 using namespace PPCII;
2023 static const std::pair<unsigned, const char *> TargetFlags[] = {
2024 {MO_LO, "ppc-lo"},
2025 {MO_HA, "ppc-ha"},
2026 {MO_TPREL_LO, "ppc-tprel-lo"},
2027 {MO_TPREL_HA, "ppc-tprel-ha"},
2028 {MO_DTPREL_LO, "ppc-dtprel-lo"},
2029 {MO_TLSLD_LO, "ppc-tlsld-lo"},
2030 {MO_TOC_LO, "ppc-toc-lo"},
2031 {MO_TLS, "ppc-tls"}};
2032 return makeArrayRef(TargetFlags);
2033}
2034
2035ArrayRef<std::pair<unsigned, const char *>>
2036PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2037 using namespace PPCII;
2038 static const std::pair<unsigned, const char *> TargetFlags[] = {
2039 {MO_PLT, "ppc-plt"},
2040 {MO_PIC_FLAG, "ppc-pic"},
2041 {MO_NLP_FLAG, "ppc-nlp"},
2042 {MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2043 return makeArrayRef(TargetFlags);
2044}
2045
2046// Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2047// The VSX versions have the advantage of a full 64-register target whereas
2048// the FP ones have the advantage of lower latency and higher throughput. So
2049// what we are after is using the faster instructions in low register pressure
2050// situations and using the larger register file in high register pressure
2051// situations.
2052bool PPCInstrInfo::expandVSXMemPseudo(MachineInstr &MI) const {
2053 unsigned UpperOpcode, LowerOpcode;
2054 switch (MI.getOpcode()) {
2055 case PPC::DFLOADf32:
2056 UpperOpcode = PPC::LXSSP;
2057 LowerOpcode = PPC::LFS;
2058 break;
2059 case PPC::DFLOADf64:
2060 UpperOpcode = PPC::LXSD;
2061 LowerOpcode = PPC::LFD;
2062 break;
2063 case PPC::DFSTOREf32:
2064 UpperOpcode = PPC::STXSSP;
2065 LowerOpcode = PPC::STFS;
2066 break;
2067 case PPC::DFSTOREf64:
2068 UpperOpcode = PPC::STXSD;
2069 LowerOpcode = PPC::STFD;
2070 break;
2071 case PPC::XFLOADf32:
2072 UpperOpcode = PPC::LXSSPX;
2073 LowerOpcode = PPC::LFSX;
2074 break;
2075 case PPC::XFLOADf64:
2076 UpperOpcode = PPC::LXSDX;
2077 LowerOpcode = PPC::LFDX;
2078 break;
2079 case PPC::XFSTOREf32:
2080 UpperOpcode = PPC::STXSSPX;
2081 LowerOpcode = PPC::STFSX;
2082 break;
2083 case PPC::XFSTOREf64:
2084 UpperOpcode = PPC::STXSDX;
2085 LowerOpcode = PPC::STFDX;
2086 break;
2087 case PPC::LIWAX:
2088 UpperOpcode = PPC::LXSIWAX;
2089 LowerOpcode = PPC::LFIWAX;
2090 break;
2091 case PPC::LIWZX:
2092 UpperOpcode = PPC::LXSIWZX;
2093 LowerOpcode = PPC::LFIWZX;
2094 break;
2095 case PPC::STIWX:
2096 UpperOpcode = PPC::STXSIWX;
2097 LowerOpcode = PPC::STFIWX;
2098 break;
2099 default:
2100 llvm_unreachable("Unknown Operation!")::llvm::llvm_unreachable_internal("Unknown Operation!", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2100)
;
2101 }
2102
2103 unsigned TargetReg = MI.getOperand(0).getReg();
2104 unsigned Opcode;
2105 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) ||
2106 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2107 Opcode = LowerOpcode;
2108 else
2109 Opcode = UpperOpcode;
2110 MI.setDesc(get(Opcode));
2111 return true;
2112}
2113
2114static bool isAnImmediateOperand(const MachineOperand &MO) {
2115 return MO.isCPI() || MO.isGlobal() || MO.isImm();
2116}
2117
2118bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
2119 auto &MBB = *MI.getParent();
2120 auto DL = MI.getDebugLoc();
2121
2122 switch (MI.getOpcode()) {
2123 case TargetOpcode::LOAD_STACK_GUARD: {
2124 assert(Subtarget.isTargetLinux() &&((Subtarget.isTargetLinux() && "Only Linux target is expected to contain LOAD_STACK_GUARD"
) ? static_cast<void> (0) : __assert_fail ("Subtarget.isTargetLinux() && \"Only Linux target is expected to contain LOAD_STACK_GUARD\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2125, __PRETTY_FUNCTION__))
2125 "Only Linux target is expected to contain LOAD_STACK_GUARD")((Subtarget.isTargetLinux() && "Only Linux target is expected to contain LOAD_STACK_GUARD"
) ? static_cast<void> (0) : __assert_fail ("Subtarget.isTargetLinux() && \"Only Linux target is expected to contain LOAD_STACK_GUARD\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2125, __PRETTY_FUNCTION__))
;
2126 const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2127 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2128 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2129 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2130 .addImm(Offset)
2131 .addReg(Reg);
2132 return true;
2133 }
2134 case PPC::DFLOADf32:
2135 case PPC::DFLOADf64:
2136 case PPC::DFSTOREf32:
2137 case PPC::DFSTOREf64: {
2138 assert(Subtarget.hasP9Vector() &&((Subtarget.hasP9Vector() && "Invalid D-Form Pseudo-ops on Pre-P9 target."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasP9Vector() && \"Invalid D-Form Pseudo-ops on Pre-P9 target.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2139, __PRETTY_FUNCTION__))
2139 "Invalid D-Form Pseudo-ops on Pre-P9 target.")((Subtarget.hasP9Vector() && "Invalid D-Form Pseudo-ops on Pre-P9 target."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasP9Vector() && \"Invalid D-Form Pseudo-ops on Pre-P9 target.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2139, __PRETTY_FUNCTION__))
;
2140 assert(MI.getOperand(2).isReg() &&((MI.getOperand(2).isReg() && isAnImmediateOperand(MI
.getOperand(1)) && "D-form op must have register and immediate operands"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && isAnImmediateOperand(MI.getOperand(1)) && \"D-form op must have register and immediate operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2142, __PRETTY_FUNCTION__))
2141 isAnImmediateOperand(MI.getOperand(1)) &&((MI.getOperand(2).isReg() && isAnImmediateOperand(MI
.getOperand(1)) && "D-form op must have register and immediate operands"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && isAnImmediateOperand(MI.getOperand(1)) && \"D-form op must have register and immediate operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2142, __PRETTY_FUNCTION__))
2142 "D-form op must have register and immediate operands")((MI.getOperand(2).isReg() && isAnImmediateOperand(MI
.getOperand(1)) && "D-form op must have register and immediate operands"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && isAnImmediateOperand(MI.getOperand(1)) && \"D-form op must have register and immediate operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2142, __PRETTY_FUNCTION__))
;
2143 return expandVSXMemPseudo(MI);
2144 }
2145 case PPC::XFLOADf32:
2146 case PPC::XFSTOREf32:
2147 case PPC::LIWAX:
2148 case PPC::LIWZX:
2149 case PPC::STIWX: {
2150 assert(Subtarget.hasP8Vector() &&((Subtarget.hasP8Vector() && "Invalid X-Form Pseudo-ops on Pre-P8 target."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasP8Vector() && \"Invalid X-Form Pseudo-ops on Pre-P8 target.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2151, __PRETTY_FUNCTION__))
2151 "Invalid X-Form Pseudo-ops on Pre-P8 target.")((Subtarget.hasP8Vector() && "Invalid X-Form Pseudo-ops on Pre-P8 target."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasP8Vector() && \"Invalid X-Form Pseudo-ops on Pre-P8 target.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2151, __PRETTY_FUNCTION__))
;
2152 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&((MI.getOperand(2).isReg() && MI.getOperand(1).isReg(
) && "X-form op must have register and register operands"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2153, __PRETTY_FUNCTION__))
2153 "X-form op must have register and register operands")((MI.getOperand(2).isReg() && MI.getOperand(1).isReg(
) && "X-form op must have register and register operands"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2153, __PRETTY_FUNCTION__))
;
2154 return expandVSXMemPseudo(MI);
2155 }
2156 case PPC::XFLOADf64:
2157 case PPC::XFSTOREf64: {
2158 assert(Subtarget.hasVSX() &&((Subtarget.hasVSX() && "Invalid X-Form Pseudo-ops on target that has no VSX."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasVSX() && \"Invalid X-Form Pseudo-ops on target that has no VSX.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2159, __PRETTY_FUNCTION__))
2159 "Invalid X-Form Pseudo-ops on target that has no VSX.")((Subtarget.hasVSX() && "Invalid X-Form Pseudo-ops on target that has no VSX."
) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasVSX() && \"Invalid X-Form Pseudo-ops on target that has no VSX.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2159, __PRETTY_FUNCTION__))
;
2160 assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&((MI.getOperand(2).isReg() && MI.getOperand(1).isReg(
) && "X-form op must have register and register operands"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2161, __PRETTY_FUNCTION__))
2161 "X-form op must have register and register operands")((MI.getOperand(2).isReg() && MI.getOperand(1).isReg(
) && "X-form op must have register and register operands"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2161, __PRETTY_FUNCTION__))
;
2162 return expandVSXMemPseudo(MI);
2163 }
2164 case PPC::SPILLTOVSR_LD: {
2165 unsigned TargetReg = MI.getOperand(0).getReg();
2166 if (PPC::VSFRCRegClass.contains(TargetReg)) {
2167 MI.setDesc(get(PPC::DFLOADf64));
2168 return expandPostRAPseudo(MI);
2169 }
2170 else
2171 MI.setDesc(get(PPC::LD));
2172 return true;
2173 }
2174 case PPC::SPILLTOVSR_ST: {
2175 unsigned SrcReg = MI.getOperand(0).getReg();
2176 if (PPC::VSFRCRegClass.contains(SrcReg)) {
2177 NumStoreSPILLVSRRCAsVec++;
2178 MI.setDesc(get(PPC::DFSTOREf64));
2179 return expandPostRAPseudo(MI);
2180 } else {
2181 NumStoreSPILLVSRRCAsGpr++;
2182 MI.setDesc(get(PPC::STD));
2183 }
2184 return true;
2185 }
2186 case PPC::SPILLTOVSR_LDX: {
2187 unsigned TargetReg = MI.getOperand(0).getReg();
2188 if (PPC::VSFRCRegClass.contains(TargetReg))
2189 MI.setDesc(get(PPC::LXSDX));
2190 else
2191 MI.setDesc(get(PPC::LDX));
2192 return true;
2193 }
2194 case PPC::SPILLTOVSR_STX: {
2195 unsigned SrcReg = MI.getOperand(0).getReg();
2196 if (PPC::VSFRCRegClass.contains(SrcReg)) {
2197 NumStoreSPILLVSRRCAsVec++;
2198 MI.setDesc(get(PPC::STXSDX));
2199 } else {
2200 NumStoreSPILLVSRRCAsGpr++;
2201 MI.setDesc(get(PPC::STDX));
2202 }
2203 return true;
2204 }
2205
2206 case PPC::CFENCE8: {
2207 auto Val = MI.getOperand(0).getReg();
2208 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2209 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2210 .addImm(PPC::PRED_NE_MINUS)
2211 .addReg(PPC::CR7)
2212 .addImm(1);
2213 MI.setDesc(get(PPC::ISYNC));
2214 MI.RemoveOperand(0);
2215 return true;
2216 }
2217 }
2218 return false;
2219}
2220
2221// Essentially a compile-time implementation of a compare->isel sequence.
2222// It takes two constants to compare, along with the true/false registers
2223// and the comparison type (as a subreg to a CR field) and returns one
2224// of the true/false registers, depending on the comparison results.
2225static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2226 unsigned TrueReg, unsigned FalseReg,
2227 unsigned CRSubReg) {
2228 // Signed comparisons. The immediates are assumed to be sign-extended.
2229 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) {
2230 switch (CRSubReg) {
2231 default: llvm_unreachable("Unknown integer comparison type.")::llvm::llvm_unreachable_internal("Unknown integer comparison type."
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2231)
;
2232 case PPC::sub_lt:
2233 return Imm1 < Imm2 ? TrueReg : FalseReg;
2234 case PPC::sub_gt:
2235 return Imm1 > Imm2 ? TrueReg : FalseReg;
2236 case PPC::sub_eq:
2237 return Imm1 == Imm2 ? TrueReg : FalseReg;
2238 }
2239 }
2240 // Unsigned comparisons.
2241 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) {
2242 switch (CRSubReg) {
2243 default: llvm_unreachable("Unknown integer comparison type.")::llvm::llvm_unreachable_internal("Unknown integer comparison type."
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2243)
;
2244 case PPC::sub_lt:
2245 return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2246 case PPC::sub_gt:
2247 return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2248 case PPC::sub_eq:
2249 return Imm1 == Imm2 ? TrueReg : FalseReg;
2250 }
2251 }
2252 return PPC::NoRegister;
2253}
2254
2255// Replace an instruction with one that materializes a constant (and sets
2256// CR0 if the original instruction was a record-form instruction).
2257void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI,
2258 const LoadImmediateInfo &LII) const {
2259 // Remove existing operands.
2260 int OperandToKeep = LII.SetCR ? 1 : 0;
2261 for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2262 MI.RemoveOperand(i);
2263
2264 // Replace the instruction.
2265 if (LII.SetCR) {
2266 MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2267 // Set the immediate.
2268 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2269 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2270 return;
2271 }
2272 else
2273 MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2274
2275 // Set the immediate.
2276 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2277 .addImm(LII.Imm);
2278}
2279
2280MachineInstr *PPCInstrInfo::getForwardingDefMI(
2281 MachineInstr &MI,
2282 unsigned &OpNoForForwarding,
2283 bool &SeenIntermediateUse) const {
2284 OpNoForForwarding = ~0U;
2285 MachineInstr *DefMI = nullptr;
2286 MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
2287 const TargetRegisterInfo *TRI = &getRegisterInfo();
2288 // If we're in SSA, get the defs through the MRI. Otherwise, only look
2289 // within the basic block to see if the register is defined using an LI/LI8.
2290 if (MRI->isSSA()) {
2291 for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2292 if (!MI.getOperand(i).isReg())
2293 continue;
2294 unsigned Reg = MI.getOperand(i).getReg();
2295 if (!TargetRegisterInfo::isVirtualRegister(Reg))
2296 continue;
2297 unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2298 if (TargetRegisterInfo::isVirtualRegister(TrueReg)) {
2299 DefMI = MRI->getVRegDef(TrueReg);
2300 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) {
2301 OpNoForForwarding = i;
2302 break;
2303 }
2304 }
2305 }
2306 } else {
2307 // Looking back through the definition for each operand could be expensive,
2308 // so exit early if this isn't an instruction that either has an immediate
2309 // form or is already an immediate form that we can handle.
2310 ImmInstrInfo III;
2311 unsigned Opc = MI.getOpcode();
2312 bool ConvertibleImmForm =
2313 Opc == PPC::CMPWI || Opc == PPC::CMPLWI ||
2314 Opc == PPC::CMPDI || Opc == PPC::CMPLDI ||
2315 Opc == PPC::ADDI || Opc == PPC::ADDI8 ||
2316 Opc == PPC::ORI || Opc == PPC::ORI8 ||
2317 Opc == PPC::XORI || Opc == PPC::XORI8 ||
2318 Opc == PPC::RLDICL || Opc == PPC::RLDICLo ||
2319 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 ||
2320 Opc == PPC::RLWINM || Opc == PPC::RLWINMo ||
2321 Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2322 if (!instrHasImmForm(MI, III, true) && !ConvertibleImmForm)
2323 return nullptr;
2324
2325 // Don't convert or %X, %Y, %Y since that's just a register move.
2326 if ((Opc == PPC::OR || Opc == PPC::OR8) &&
2327 MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2328 return nullptr;
2329 for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2330 MachineOperand &MO = MI.getOperand(i);
2331 SeenIntermediateUse = false;
2332 if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2333 MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI;
2334 It++;
2335 unsigned Reg = MI.getOperand(i).getReg();
2336 // MachineInstr::readsRegister only returns true if the machine
2337 // instruction reads the exact register or its super-register. It
2338 // does not consider uses of sub-registers which seems like strange
2339 // behaviour. Nonetheless, if we end up with a 64-bit register here,
2340 // get the corresponding 32-bit register to check.
2341 if (PPC::G8RCRegClass.contains(Reg))
2342 Reg = Reg - PPC::X0 + PPC::R0;
2343
2344 // Is this register defined by some form of add-immediate (including
2345 // load-immediate) within this basic block?
2346 for ( ; It != E; ++It) {
2347 if (It->modifiesRegister(Reg, &getRegisterInfo())) {
2348 switch (It->getOpcode()) {
2349 default: break;
2350 case PPC::LI:
2351 case PPC::LI8:
2352 case PPC::ADDItocL:
2353 case PPC::ADDI:
2354 case PPC::ADDI8:
2355 OpNoForForwarding = i;
2356 return &*It;
2357 }
2358 break;
2359 } else if (It->readsRegister(Reg, &getRegisterInfo()))
2360 // If we see another use of this reg between the def and the MI,
2361 // we want to flat it so the def isn't deleted.
2362 SeenIntermediateUse = true;
2363 }
2364 }
2365 }
2366 }
2367 return OpNoForForwarding == ~0U ? nullptr : DefMI;
2368}
2369
2370const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2371 static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2372 // Power 8
2373 {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2374 PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2375 PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2376 PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
2377 // Power 9
2378 {PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2379 PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2380 PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2381 PPC::SPILLTOVSR_ST}};
2382
2383 return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2384}
2385
2386const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2387 static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2388 // Power 8
2389 {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2390 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2391 PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2392 PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
2393 // Power 9
2394 {PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2395 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2396 PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2397 PPC::SPILLTOVSR_LD}};
2398
2399 return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2400}
2401
2402// If this instruction has an immediate form and one of its operands is a
2403// result of a load-immediate or an add-immediate, convert it to
2404// the immediate form if the constant is in range.
2405bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
2406 MachineInstr **KilledDef) const {
2407 MachineFunction *MF = MI.getParent()->getParent();
2408 MachineRegisterInfo *MRI = &MF->getRegInfo();
2409 bool PostRA = !MRI->isSSA();
2410 bool SeenIntermediateUse = true;
2411 unsigned ForwardingOperand = ~0U;
2412 MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
2413 SeenIntermediateUse);
2414 if (!DefMI)
2415 return false;
2416 assert(ForwardingOperand < MI.getNumOperands() &&((ForwardingOperand < MI.getNumOperands() && "The forwarding operand needs to be valid at this point"
) ? static_cast<void> (0) : __assert_fail ("ForwardingOperand < MI.getNumOperands() && \"The forwarding operand needs to be valid at this point\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2417, __PRETTY_FUNCTION__))
2417 "The forwarding operand needs to be valid at this point")((ForwardingOperand < MI.getNumOperands() && "The forwarding operand needs to be valid at this point"
) ? static_cast<void> (0) : __assert_fail ("ForwardingOperand < MI.getNumOperands() && \"The forwarding operand needs to be valid at this point\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2417, __PRETTY_FUNCTION__))
;
2418 bool KillFwdDefMI = !SeenIntermediateUse &&
2419 MI.getOperand(ForwardingOperand).isKill();
2420 if (KilledDef && KillFwdDefMI)
2421 *KilledDef = DefMI;
2422
2423 ImmInstrInfo III;
2424 bool HasImmForm = instrHasImmForm(MI, III, PostRA);
2425 // If this is a reg+reg instruction that has a reg+imm form,
2426 // and one of the operands is produced by an add-immediate,
2427 // try to convert it.
2428 if (HasImmForm && transformToImmFormFedByAdd(MI, III, ForwardingOperand,
2429 *DefMI, KillFwdDefMI))
2430 return true;
2431
2432 if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) ||
2433 !DefMI->getOperand(1).isImm())
2434 return false;
2435
2436 int64_t Immediate = DefMI->getOperand(1).getImm();
2437 // Sign-extend to 64-bits.
2438 int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2439 (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
2440
2441 // If this is a reg+reg instruction that has a reg+imm form,
2442 // and one of the operands is produced by LI, convert it now.
2443 if (HasImmForm)
2444 return transformToImmFormFedByLI(MI, III, ForwardingOperand, SExtImm);
2445
2446 bool ReplaceWithLI = false;
2447 bool Is64BitLI = false;
2448 int64_t NewImm = 0;
2449 bool SetCR = false;
2450 unsigned Opc = MI.getOpcode();
2451 switch (Opc) {
2452 default: return false;
2453
2454 // FIXME: Any branches conditional on such a comparison can be made
2455 // unconditional. At this time, this happens too infrequently to be worth
2456 // the implementation effort, but if that ever changes, we could convert
2457 // such a pattern here.
2458 case PPC::CMPWI:
2459 case PPC::CMPLWI:
2460 case PPC::CMPDI:
2461 case PPC::CMPLDI: {
2462 // Doing this post-RA would require dataflow analysis to reliably find uses
2463 // of the CR register set by the compare.
2464 if (PostRA)
2465 return false;
2466 // If a compare-immediate is fed by an immediate and is itself an input of
2467 // an ISEL (the most common case) into a COPY of the correct register.
2468 bool Changed = false;
2469 unsigned DefReg = MI.getOperand(0).getReg();
2470 int64_t Comparand = MI.getOperand(2).getImm();
2471 int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2472 (Comparand | 0xFFFFFFFFFFFF0000) : Comparand;
2473
2474 for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2475 unsigned UseOpc = CompareUseMI.getOpcode();
2476 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2477 continue;
2478 unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2479 unsigned TrueReg = CompareUseMI.getOperand(1).getReg();
2480 unsigned FalseReg = CompareUseMI.getOperand(2).getReg();
2481 unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2482 FalseReg, CRSubReg);
2483 if (RegToCopy == PPC::NoRegister)
2484 continue;
2485 // Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2486 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) {
2487 CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2488 CompareUseMI.getOperand(1).ChangeToImmediate(0);
2489 CompareUseMI.RemoveOperand(3);
2490 CompareUseMI.RemoveOperand(2);
2491 continue;
2492 }
2493 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n"
; } } while (false)
2494 dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n"
; } } while (false)
;
2495 LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { DefMI->dump(); MI.dump(); CompareUseMI
.dump(); } } while (false)
;
2496 LLVM_DEBUG(dbgs() << "Is converted to:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Is converted to:\n"; }
} while (false)
;
2497 // Convert to copy and remove unneeded operands.
2498 CompareUseMI.setDesc(get(PPC::COPY));
2499 CompareUseMI.RemoveOperand(3);
2500 CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2501 CmpIselsConverted++;
2502 Changed = true;
2503 LLVM_DEBUG(CompareUseMI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { CompareUseMI.dump(); } } while (false)
;
2504 }
2505 if (Changed)
2506 return true;
2507 // This may end up incremented multiple times since this function is called
2508 // during a fixed-point transformation, but it is only meant to indicate the
2509 // presence of this opportunity.
2510 MissedConvertibleImmediateInstrs++;
2511 return false;
2512 }
2513
2514 // Immediate forms - may simply be convertable to an LI.
2515 case PPC::ADDI:
2516 case PPC::ADDI8: {
2517 // Does the sum fit in a 16-bit signed field?
2518 int64_t Addend = MI.getOperand(2).getImm();
2519 if (isInt<16>(Addend + SExtImm)) {
2520 ReplaceWithLI = true;
2521 Is64BitLI = Opc == PPC::ADDI8;
2522 NewImm = Addend + SExtImm;
2523 break;
2524 }
2525 return false;
2526 }
2527 case PPC::RLDICL:
2528 case PPC::RLDICLo:
2529 case PPC::RLDICL_32:
2530 case PPC::RLDICL_32_64: {
2531 // Use APInt's rotate function.
2532 int64_t SH = MI.getOperand(2).getImm();
2533 int64_t MB = MI.getOperand(3).getImm();
2534 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICLo) ?
2535 64 : 32, SExtImm, true);
2536 InVal = InVal.rotl(SH);
2537 uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2538 InVal &= Mask;
2539 // Can't replace negative values with an LI as that will sign-extend
2540 // and not clear the left bits. If we're setting the CR bit, we will use
2541 // ANDIo which won't sign extend, so that's safe.
2542 if (isUInt<15>(InVal.getSExtValue()) ||
2543 (Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2544 ReplaceWithLI = true;
2545 Is64BitLI = Opc != PPC::RLDICL_32;
2546 NewImm = InVal.getSExtValue();
2547 SetCR = Opc == PPC::RLDICLo;
2548 break;
2549 }
2550 return false;
2551 }
2552 case PPC::RLWINM:
2553 case PPC::RLWINM8:
2554 case PPC::RLWINMo:
2555 case PPC::RLWINM8o: {
2556 int64_t SH = MI.getOperand(2).getImm();
2557 int64_t MB = MI.getOperand(3).getImm();
2558 int64_t ME = MI.getOperand(4).getImm();
2559 APInt InVal(32, SExtImm, true);
2560 InVal = InVal.rotl(SH);
2561 // Set the bits ( MB + 32 ) to ( ME + 32 ).
2562 uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2563 InVal &= Mask;
2564 // Can't replace negative values with an LI as that will sign-extend
2565 // and not clear the left bits. If we're setting the CR bit, we will use
2566 // ANDIo which won't sign extend, so that's safe.
2567 bool ValueFits = isUInt<15>(InVal.getSExtValue());
2568 ValueFits |= ((Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o) &&
2569 isUInt<16>(InVal.getSExtValue()));
2570 if (ValueFits) {
2571 ReplaceWithLI = true;
2572 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8o;
2573 NewImm = InVal.getSExtValue();
2574 SetCR = Opc == PPC::RLWINMo || Opc == PPC::RLWINM8o;
2575 break;
2576 }
2577 return false;
2578 }
2579 case PPC::ORI:
2580 case PPC::ORI8:
2581 case PPC::XORI:
2582 case PPC::XORI8: {
2583 int64_t LogicalImm = MI.getOperand(2).getImm();
2584 int64_t Result = 0;
2585 if (Opc == PPC::ORI || Opc == PPC::ORI8)
2586 Result = LogicalImm | SExtImm;
2587 else
2588 Result = LogicalImm ^ SExtImm;
2589 if (isInt<16>(Result)) {
2590 ReplaceWithLI = true;
2591 Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8;
2592 NewImm = Result;
2593 break;
2594 }
2595 return false;
2596 }
2597 }
2598
2599 if (ReplaceWithLI) {
2600 // We need to be careful with CR-setting instructions we're replacing.
2601 if (SetCR) {
2602 // We don't know anything about uses when we're out of SSA, so only
2603 // replace if the new immediate will be reproduced.
2604 bool ImmChanged = (SExtImm & NewImm) != NewImm;
2605 if (PostRA && ImmChanged)
2606 return false;
2607
2608 if (!PostRA) {
2609 // If the defining load-immediate has no other uses, we can just replace
2610 // the immediate with the new immediate.
2611 if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2612 DefMI->getOperand(1).setImm(NewImm);
2613
2614 // If we're not using the GPR result of the CR-setting instruction, we
2615 // just need to and with zero/non-zero depending on the new immediate.
2616 else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2617 if (NewImm) {
2618 assert(Immediate && "Transformation converted zero to non-zero?")((Immediate && "Transformation converted zero to non-zero?"
) ? static_cast<void> (0) : __assert_fail ("Immediate && \"Transformation converted zero to non-zero?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2618, __PRETTY_FUNCTION__))
;
2619 NewImm = Immediate;
2620 }
2621 }
2622 else if (ImmChanged)
2623 return false;
2624 }
2625 }
2626
2627 LLVM_DEBUG(dbgs() << "Replacing instruction:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Replacing instruction:\n"
; } } while (false)
;
2628 LLVM_DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { MI.dump(); } } while (false)
;
2629 LLVM_DEBUG(dbgs() << "Fed by:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Fed by:\n"; } } while (
false)
;
2630 LLVM_DEBUG(DefMI->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { DefMI->dump(); } } while (false)
;
2631 LoadImmediateInfo LII;
2632 LII.Imm = NewImm;
2633 LII.Is64Bit = Is64BitLI;
2634 LII.SetCR = SetCR;
2635 // If we're setting the CR, the original load-immediate must be kept (as an
2636 // operand to ANDIo/ANDI8o).
2637 if (KilledDef && SetCR)
2638 *KilledDef = nullptr;
2639 replaceInstrWithLI(MI, LII);
2640 LLVM_DEBUG(dbgs() << "With:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "With:\n"; } } while (false
)
;
2641 LLVM_DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { MI.dump(); } } while (false)
;
2642 return true;
2643 }
2644 return false;
2645}
2646
2647static bool isVFReg(unsigned Reg) {
2648 return PPC::VFRCRegClass.contains(Reg);
2649}
2650
2651bool PPCInstrInfo::instrHasImmForm(const MachineInstr &MI,
2652 ImmInstrInfo &III, bool PostRA) const {
2653 unsigned Opc = MI.getOpcode();
2654 // The vast majority of the instructions would need their operand 2 replaced
2655 // with an immediate when switching to the reg+imm form. A marked exception
2656 // are the update form loads/stores for which a constant operand 2 would need
2657 // to turn into a displacement and move operand 1 to the operand 2 position.
2658 III.ImmOpNo = 2;
2659 III.OpNoForForwarding = 2;
2660 III.ImmWidth = 16;
2661 III.ImmMustBeMultipleOf = 1;
2662 III.TruncateImmTo = 0;
2663 III.IsSummingOperands = false;
2664 switch (Opc) {
2665 default: return false;
2666 case PPC::ADD4:
2667 case PPC::ADD8:
2668 III.SignedImm = true;
2669 III.ZeroIsSpecialOrig = 0;
2670 III.ZeroIsSpecialNew = 1;
2671 III.IsCommutative = true;
2672 III.IsSummingOperands = true;
2673 III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2674 break;
2675 case PPC::ADDC:
2676 case PPC::ADDC8:
2677 III.SignedImm = true;
2678 III.ZeroIsSpecialOrig = 0;
2679 III.ZeroIsSpecialNew = 0;
2680 III.IsCommutative = true;
2681 III.IsSummingOperands = true;
2682 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2683 break;
2684 case PPC::ADDCo:
2685 III.SignedImm = true;
2686 III.ZeroIsSpecialOrig = 0;
2687 III.ZeroIsSpecialNew = 0;
2688 III.IsCommutative = true;
2689 III.IsSummingOperands = true;
2690 III.ImmOpcode = PPC::ADDICo;
2691 break;
2692 case PPC::SUBFC:
2693 case PPC::SUBFC8:
2694 III.SignedImm = true;
2695 III.ZeroIsSpecialOrig = 0;
2696 III.ZeroIsSpecialNew = 0;
2697 III.IsCommutative = false;
2698 III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2699 break;
2700 case PPC::CMPW:
2701 case PPC::CMPD:
2702 III.SignedImm = true;
2703 III.ZeroIsSpecialOrig = 0;
2704 III.ZeroIsSpecialNew = 0;
2705 III.IsCommutative = false;
2706 III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2707 break;
2708 case PPC::CMPLW:
2709 case PPC::CMPLD:
2710 III.SignedImm = false;
2711 III.ZeroIsSpecialOrig = 0;
2712 III.ZeroIsSpecialNew = 0;
2713 III.IsCommutative = false;
2714 III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2715 break;
2716 case PPC::ANDo:
2717 case PPC::AND8o:
2718 case PPC::OR:
2719 case PPC::OR8:
2720 case PPC::XOR:
2721 case PPC::XOR8:
2722 III.SignedImm = false;
2723 III.ZeroIsSpecialOrig = 0;
2724 III.ZeroIsSpecialNew = 0;
2725 III.IsCommutative = true;
2726 switch(Opc) {
2727 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2727)
;
2728 case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2729 case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2730 case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2731 case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2732 case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2733 case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2734 }
2735 break;
2736 case PPC::RLWNM:
2737 case PPC::RLWNM8:
2738 case PPC::RLWNMo:
2739 case PPC::RLWNM8o:
2740 case PPC::SLW:
2741 case PPC::SLW8:
2742 case PPC::SLWo:
2743 case PPC::SLW8o:
2744 case PPC::SRW:
2745 case PPC::SRW8:
2746 case PPC::SRWo:
2747 case PPC::SRW8o:
2748 case PPC::SRAW:
2749 case PPC::SRAWo:
2750 III.SignedImm = false;
2751 III.ZeroIsSpecialOrig = 0;
2752 III.ZeroIsSpecialNew = 0;
2753 III.IsCommutative = false;
2754 // This isn't actually true, but the instructions ignore any of the
2755 // upper bits, so any immediate loaded with an LI is acceptable.
2756 // This does not apply to shift right algebraic because a value
2757 // out of range will produce a -1/0.
2758 III.ImmWidth = 16;
2759 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 ||
2760 Opc == PPC::RLWNMo || Opc == PPC::RLWNM8o)
2761 III.TruncateImmTo = 5;
2762 else
2763 III.TruncateImmTo = 6;
2764 switch(Opc) {
2765 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2765)
;
2766 case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2767 case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2768 case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2769 case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2770 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2771 case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2772 case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2773 case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2774 case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2775 case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2776 case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2777 case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2778 case PPC::SRAW:
2779 III.ImmWidth = 5;
2780 III.TruncateImmTo = 0;
2781 III.ImmOpcode = PPC::SRAWI;
2782 break;
2783 case PPC::SRAWo:
2784 III.ImmWidth = 5;
2785 III.TruncateImmTo = 0;
2786 III.ImmOpcode = PPC::SRAWIo;
2787 break;
2788 }
2789 break;
2790 case PPC::RLDCL:
2791 case PPC::RLDCLo:
2792 case PPC::RLDCR:
2793 case PPC::RLDCRo:
2794 case PPC::SLD:
2795 case PPC::SLDo:
2796 case PPC::SRD:
2797 case PPC::SRDo:
2798 case PPC::SRAD:
2799 case PPC::SRADo:
2800 III.SignedImm = false;
2801 III.ZeroIsSpecialOrig = 0;
2802 III.ZeroIsSpecialNew = 0;
2803 III.IsCommutative = false;
2804 // This isn't actually true, but the instructions ignore any of the
2805 // upper bits, so any immediate loaded with an LI is acceptable.
2806 // This does not apply to shift right algebraic because a value
2807 // out of range will produce a -1/0.
2808 III.ImmWidth = 16;
2809 if (Opc == PPC::RLDCL || Opc == PPC::RLDCLo ||
2810 Opc == PPC::RLDCR || Opc == PPC::RLDCRo)
2811 III.TruncateImmTo = 6;
2812 else
2813 III.TruncateImmTo = 7;
2814 switch(Opc) {
2815 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2815)
;
2816 case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2817 case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2818 case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2819 case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2820 case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2821 case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2822 case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2823 case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2824 case PPC::SRAD:
2825 III.ImmWidth = 6;
2826 III.TruncateImmTo = 0;
2827 III.ImmOpcode = PPC::SRADI;
2828 break;
2829 case PPC::SRADo:
2830 III.ImmWidth = 6;
2831 III.TruncateImmTo = 0;
2832 III.ImmOpcode = PPC::SRADIo;
2833 break;
2834 }
2835 break;
2836 // Loads and stores:
2837 case PPC::LBZX:
2838 case PPC::LBZX8:
2839 case PPC::LHZX:
2840 case PPC::LHZX8:
2841 case PPC::LHAX:
2842 case PPC::LHAX8:
2843 case PPC::LWZX:
2844 case PPC::LWZX8:
2845 case PPC::LWAX:
2846 case PPC::LDX:
2847 case PPC::LFSX:
2848 case PPC::LFDX:
2849 case PPC::STBX:
2850 case PPC::STBX8:
2851 case PPC::STHX:
2852 case PPC::STHX8:
2853 case PPC::STWX:
2854 case PPC::STWX8:
2855 case PPC::STDX:
2856 case PPC::STFSX:
2857 case PPC::STFDX:
2858 III.SignedImm = true;
2859 III.ZeroIsSpecialOrig = 1;
2860 III.ZeroIsSpecialNew = 2;
2861 III.IsCommutative = true;
2862 III.IsSummingOperands = true;
2863 III.ImmOpNo = 1;
2864 III.OpNoForForwarding = 2;
2865 switch(Opc) {
2866 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2866)
;
2867 case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
2868 case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
2869 case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
2870 case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
2871 case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
2872 case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
2873 case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
2874 case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
2875 case PPC::LWAX:
2876 III.ImmOpcode = PPC::LWA;
2877 III.ImmMustBeMultipleOf = 4;
2878 break;
2879 case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
2880 case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
2881 case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
2882 case PPC::STBX: III.ImmOpcode = PPC::STB; break;
2883 case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
2884 case PPC::STHX: III.ImmOpcode = PPC::STH; break;
2885 case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
2886 case PPC::STWX: III.ImmOpcode = PPC::STW; break;
2887 case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
2888 case PPC::STDX:
2889 III.ImmOpcode = PPC::STD;
2890 III.ImmMustBeMultipleOf = 4;
2891 break;
2892 case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
2893 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
2894 }
2895 break;
2896 case PPC::LBZUX:
2897 case PPC::LBZUX8:
2898 case PPC::LHZUX:
2899 case PPC::LHZUX8:
2900 case PPC::LHAUX:
2901 case PPC::LHAUX8:
2902 case PPC::LWZUX:
2903 case PPC::LWZUX8:
2904 case PPC::LDUX:
2905 case PPC::LFSUX:
2906 case PPC::LFDUX:
2907 case PPC::STBUX:
2908 case PPC::STBUX8:
2909 case PPC::STHUX:
2910 case PPC::STHUX8:
2911 case PPC::STWUX:
2912 case PPC::STWUX8:
2913 case PPC::STDUX:
2914 case PPC::STFSUX:
2915 case PPC::STFDUX:
2916 III.SignedImm = true;
2917 III.ZeroIsSpecialOrig = 2;
2918 III.ZeroIsSpecialNew = 3;
2919 III.IsCommutative = false;
2920 III.IsSummingOperands = true;
2921 III.ImmOpNo = 2;
2922 III.OpNoForForwarding = 3;
2923 switch(Opc) {
2924 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2924)
;
2925 case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
2926 case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
2927 case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
2928 case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
2929 case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
2930 case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
2931 case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
2932 case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
2933 case PPC::LDUX:
2934 III.ImmOpcode = PPC::LDU;
2935 III.ImmMustBeMultipleOf = 4;
2936 break;
2937 case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
2938 case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
2939 case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
2940 case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
2941 case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
2942 case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
2943 case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
2944 case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
2945 case PPC::STDUX:
2946 III.ImmOpcode = PPC::STDU;
2947 III.ImmMustBeMultipleOf = 4;
2948 break;
2949 case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
2950 case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
2951 }
2952 break;
2953 // Power9 and up only. For some of these, the X-Form version has access to all
2954 // 64 VSR's whereas the D-Form only has access to the VR's. We replace those
2955 // with pseudo-ops pre-ra and for post-ra, we check that the register loaded
2956 // into or stored from is one of the VR registers.
2957 case PPC::LXVX:
2958 case PPC::LXSSPX:
2959 case PPC::LXSDX:
2960 case PPC::STXVX:
2961 case PPC::STXSSPX:
2962 case PPC::STXSDX:
2963 case PPC::XFLOADf32:
2964 case PPC::XFLOADf64:
2965 case PPC::XFSTOREf32:
2966 case PPC::XFSTOREf64:
2967 if (!Subtarget.hasP9Vector())
2968 return false;
2969 III.SignedImm = true;
2970 III.ZeroIsSpecialOrig = 1;
2971 III.ZeroIsSpecialNew = 2;
2972 III.IsCommutative = true;
2973 III.IsSummingOperands = true;
2974 III.ImmOpNo = 1;
2975 III.OpNoForForwarding = 2;
2976 III.ImmMustBeMultipleOf = 4;
2977 switch(Opc) {
2978 default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 2978)
;
2979 case PPC::LXVX:
2980 III.ImmOpcode = PPC::LXV;
2981 III.ImmMustBeMultipleOf = 16;
2982 break;
2983 case PPC::LXSSPX:
2984 if (PostRA) {
2985 if (isVFReg(MI.getOperand(0).getReg()))
2986 III.ImmOpcode = PPC::LXSSP;
2987 else
2988 III.ImmOpcode = PPC::LFS;
2989 break;
2990 }
2991 LLVM_FALLTHROUGH[[clang::fallthrough]];
2992 case PPC::XFLOADf32:
2993 III.ImmOpcode = PPC::DFLOADf32;
2994 break;
2995 case PPC::LXSDX:
2996 if (PostRA) {
2997 if (isVFReg(MI.getOperand(0).getReg()))
2998 III.ImmOpcode = PPC::LXSD;
2999 else
3000 III.ImmOpcode = PPC::LFD;
3001 break;
3002 }
3003 LLVM_FALLTHROUGH[[clang::fallthrough]];
3004 case PPC::XFLOADf64:
3005 III.ImmOpcode = PPC::DFLOADf64;
3006 break;
3007 case PPC::STXVX:
3008 III.ImmOpcode = PPC::STXV;
3009 III.ImmMustBeMultipleOf = 16;
3010 break;
3011 case PPC::STXSSPX:
3012 if (PostRA) {
3013 if (isVFReg(MI.getOperand(0).getReg()))
3014 III.ImmOpcode = PPC::STXSSP;
3015 else
3016 III.ImmOpcode = PPC::STFS;
3017 break;
3018 }
3019 LLVM_FALLTHROUGH[[clang::fallthrough]];
3020 case PPC::XFSTOREf32:
3021 III.ImmOpcode = PPC::DFSTOREf32;
3022 break;
3023 case PPC::STXSDX:
3024 if (PostRA) {
3025 if (isVFReg(MI.getOperand(0).getReg()))
3026 III.ImmOpcode = PPC::STXSD;
3027 else
3028 III.ImmOpcode = PPC::STFD;
3029 break;
3030 }
3031 LLVM_FALLTHROUGH[[clang::fallthrough]];
3032 case PPC::XFSTOREf64:
3033 III.ImmOpcode = PPC::DFSTOREf64;
3034 break;
3035 }
3036 break;
3037 }
3038 return true;
3039}
3040
3041// Utility function for swaping two arbitrary operands of an instruction.
3042static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
3043 assert(Op1 != Op2 && "Cannot swap operand with itself.")((Op1 != Op2 && "Cannot swap operand with itself.") ?
static_cast<void> (0) : __assert_fail ("Op1 != Op2 && \"Cannot swap operand with itself.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3043, __PRETTY_FUNCTION__))
;
3044
3045 unsigned MaxOp = std::max(Op1, Op2);
3046 unsigned MinOp = std::min(Op1, Op2);
3047 MachineOperand MOp1 = MI.getOperand(MinOp);
3048 MachineOperand MOp2 = MI.getOperand(MaxOp);
3049 MI.RemoveOperand(std::max(Op1, Op2));
3050 MI.RemoveOperand(std::min(Op1, Op2));
3051
3052 // If the operands we are swapping are the two at the end (the common case)
3053 // we can just remove both and add them in the opposite order.
3054 if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
3055 MI.addOperand(MOp2);
3056 MI.addOperand(MOp1);
3057 } else {
3058 // Store all operands in a temporary vector, remove them and re-add in the
3059 // right order.
3060 SmallVector<MachineOperand, 2> MOps;
3061 unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
3062 for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
3063 MOps.push_back(MI.getOperand(i));
3064 MI.RemoveOperand(i);
3065 }
3066 // MOp2 needs to be added next.
3067 MI.addOperand(MOp2);
3068 // Now add the rest.
3069 for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
3070 if (i == MaxOp)
3071 MI.addOperand(MOp1);
3072 else {
3073 MI.addOperand(MOps.back());
3074 MOps.pop_back();
3075 }
3076 }
3077 }
3078}
3079
3080// Check if the 'MI' that has the index OpNoForForwarding
3081// meets the requirement described in the ImmInstrInfo.
3082bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
3083 const ImmInstrInfo &III,
3084 unsigned OpNoForForwarding
3085 ) const {
3086 // As the algorithm of checking for PPC::ZERO/PPC::ZERO8
3087 // would not work pre-RA, we can only do the check post RA.
3088 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3089 if (MRI.isSSA())
3090 return false;
3091
3092 // Cannot do the transform if MI isn't summing the operands.
3093 if (!III.IsSummingOperands)
3094 return false;
3095
3096 // The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
3097 if (!III.ZeroIsSpecialOrig)
3098 return false;
3099
3100 // We cannot do the transform if the operand we are trying to replace
3101 // isn't the same as the operand the instruction allows.
3102 if (OpNoForForwarding != III.OpNoForForwarding)
3103 return false;
3104
3105 // Check if the instruction we are trying to transform really has
3106 // the special zero register as its operand.
3107 if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3108 MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3109 return false;
3110
3111 // This machine instruction is convertible if it is,
3112 // 1. summing the operands.
3113 // 2. one of the operands is special zero register.
3114 // 3. the operand we are trying to replace is allowed by the MI.
3115 return true;
3116}
3117
3118// Check if the DefMI is the add inst and set the ImmMO and RegMO
3119// accordingly.
3120bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
3121 const ImmInstrInfo &III,
3122 MachineOperand *&ImmMO,
3123 MachineOperand *&RegMO) const {
3124 unsigned Opc = DefMI.getOpcode();
3125 if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
3126 return false;
3127
3128 assert(DefMI.getNumOperands() >= 3 &&((DefMI.getNumOperands() >= 3 && "Add inst must have at least three operands"
) ? static_cast<void> (0) : __assert_fail ("DefMI.getNumOperands() >= 3 && \"Add inst must have at least three operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3129, __PRETTY_FUNCTION__))
3129 "Add inst must have at least three operands")((DefMI.getNumOperands() >= 3 && "Add inst must have at least three operands"
) ? static_cast<void> (0) : __assert_fail ("DefMI.getNumOperands() >= 3 && \"Add inst must have at least three operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3129, __PRETTY_FUNCTION__))
;
3130 RegMO = &DefMI.getOperand(1);
3131 ImmMO = &DefMI.getOperand(2);
3132
3133 // This DefMI is elgible for forwarding if it is:
3134 // 1. add inst
3135 // 2. one of the operands is Imm/CPI/Global.
3136 return isAnImmediateOperand(*ImmMO);
3137}
3138
3139bool PPCInstrInfo::isRegElgibleForForwarding(const MachineOperand &RegMO,
3140 const MachineInstr &DefMI,
3141 const MachineInstr &MI,
3142 bool KillDefMI
3143 ) const {
3144 // x = addi y, imm
3145 // ...
3146 // z = lfdx 0, x -> z = lfd imm(y)
3147 // The Reg "y" can be forwarded to the MI(z) only when there is no DEF
3148 // of "y" between the DEF of "x" and "z".
3149 // The query is only valid post RA.
3150 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3151 if (MRI.isSSA())
3152 return false;
3153
3154 // MachineInstr::readsRegister only returns true if the machine
3155 // instruction reads the exact register or its super-register. It
3156 // does not consider uses of sub-registers which seems like strange
3157 // behaviour. Nonetheless, if we end up with a 64-bit register here,
3158 // get the corresponding 32-bit register to check.
3159 unsigned Reg = RegMO.getReg();
3160 if (PPC::G8RCRegClass.contains(Reg))
3161 Reg = Reg - PPC::X0 + PPC::R0;
3162
3163 // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
3164 MachineBasicBlock::const_reverse_iterator It = MI;
3165 MachineBasicBlock::const_reverse_iterator E = MI.getParent()->rend();
3166 It++;
3167 for (; It != E; ++It) {
3168 if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3169 return false;
3170 // Made it to DefMI without encountering a clobber.
3171 if ((&*It) == &DefMI)
3172 break;
3173 }
3174 assert((&*It) == &DefMI && "DefMI is missing")(((&*It) == &DefMI && "DefMI is missing") ? static_cast
<void> (0) : __assert_fail ("(&*It) == &DefMI && \"DefMI is missing\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3174, __PRETTY_FUNCTION__))
;
3175
3176 // If DefMI also uses the register to be forwarded, we can only forward it
3177 // if DefMI is being erased.
3178 if (DefMI.readsRegister(Reg, &getRegisterInfo()))
3179 return KillDefMI;
3180
3181 return true;
3182}
3183
3184bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3185 const MachineInstr &DefMI,
3186 const ImmInstrInfo &III,
3187 int64_t &Imm) const {
3188 assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate")((isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate"
) ? static_cast<void> (0) : __assert_fail ("isAnImmediateOperand(ImmMO) && \"ImmMO is NOT an immediate\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3188, __PRETTY_FUNCTION__))
;
3189 if (DefMI.getOpcode() == PPC::ADDItocL) {
3190 // The operand for ADDItocL is CPI, which isn't imm at compiling time,
3191 // However, we know that, it is 16-bit width, and has the alignment of 4.
3192 // Check if the instruction met the requirement.
3193 if (III.ImmMustBeMultipleOf > 4 ||
3194 III.TruncateImmTo || III.ImmWidth != 16)
3195 return false;
3196
3197 // Going from XForm to DForm loads means that the displacement needs to be
3198 // not just an immediate but also a multiple of 4, or 16 depending on the
3199 // load. A DForm load cannot be represented if it is a multiple of say 2.
3200 // XForm loads do not have this restriction.
3201 if (ImmMO.isGlobal() &&
3202 ImmMO.getGlobal()->getAlignment() < III.ImmMustBeMultipleOf)
3203 return false;
3204
3205 return true;
3206 }
3207
3208 if (ImmMO.isImm()) {
3209 // It is Imm, we need to check if the Imm fit the range.
3210 int64_t Immediate = ImmMO.getImm();
3211 // Sign-extend to 64-bits.
3212 Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
3213 (Immediate | 0xFFFFFFFFFFFF0000) : Immediate;
3214
3215 if (Imm % III.ImmMustBeMultipleOf)
3216 return false;
3217 if (III.TruncateImmTo)
3218 Imm &= ((1 << III.TruncateImmTo) - 1);
3219 if (III.SignedImm) {
3220 APInt ActualValue(64, Imm, true);
3221 if (!ActualValue.isSignedIntN(III.ImmWidth))
3222 return false;
3223 } else {
3224 uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3225 if ((uint64_t)Imm > UnsignedMax)
3226 return false;
3227 }
3228 }
3229 else
3230 return false;
3231
3232 // This ImmMO is forwarded if it meets the requriement describle
3233 // in ImmInstrInfo
3234 return true;
3235}
3236
3237// If an X-Form instruction is fed by an add-immediate and one of its operands
3238// is the literal zero, attempt to forward the source of the add-immediate to
3239// the corresponding D-Form instruction with the displacement coming from
3240// the immediate being added.
3241bool PPCInstrInfo::transformToImmFormFedByAdd(MachineInstr &MI,
3242 const ImmInstrInfo &III,
3243 unsigned OpNoForForwarding,
3244 MachineInstr &DefMI,
3245 bool KillDefMI) const {
3246 // RegMO ImmMO
3247 // | |
3248 // x = addi reg, imm <----- DefMI
3249 // y = op 0 , x <----- MI
3250 // |
3251 // OpNoForForwarding
3252 // Check if the MI meet the requirement described in the III.
3253 if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
3254 return false;
3255
3256 // Check if the DefMI meet the requirement
3257 // described in the III. If yes, set the ImmMO and RegMO accordingly.
3258 MachineOperand *ImmMO = nullptr;
3259 MachineOperand *RegMO = nullptr;
3260 if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
3261 return false;
3262 assert(ImmMO && RegMO && "Imm and Reg operand must have been set")((ImmMO && RegMO && "Imm and Reg operand must have been set"
) ? static_cast<void> (0) : __assert_fail ("ImmMO && RegMO && \"Imm and Reg operand must have been set\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3262, __PRETTY_FUNCTION__))
;
3263
3264 // As we get the Imm operand now, we need to check if the ImmMO meet
3265 // the requirement described in the III. If yes set the Imm.
3266 int64_t Imm = 0;
3267 if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
3268 return false;
3269
3270 // Check if the RegMO can be forwarded to MI.
3271 if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI))
3272 return false;
3273
3274 // We know that, the MI and DefMI both meet the pattern, and
3275 // the Imm also meet the requirement with the new Imm-form.
3276 // It is safe to do the transformation now.
3277 LLVM_DEBUG(dbgs() << "Replacing instruction:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Replacing instruction:\n"
; } } while (false)
;
3278 LLVM_DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { MI.dump(); } } while (false)
;
3279 LLVM_DEBUG(dbgs() << "Fed by:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "Fed by:\n"; } } while (
false)
;
3280 LLVM_DEBUG(DefMI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { DefMI.dump(); } } while (false)
;
3281
3282 // Update the base reg first.
3283 MI.getOperand(III.OpNoForForwarding).ChangeToRegister(RegMO->getReg(),
3284 false, false,
3285 RegMO->isKill());
3286
3287 // Then, update the imm.
3288 if (ImmMO->isImm()) {
3289 // If the ImmMO is Imm, change the operand that has ZERO to that Imm
3290 // directly.
3291 MI.getOperand(III.ZeroIsSpecialOrig).ChangeToImmediate(Imm);
3292 }
3293 else {
3294 // Otherwise, it is Constant Pool Index(CPI) or Global,
3295 // which is relocation in fact. We need to replace the special zero
3296 // register with ImmMO.
3297 // Before that, we need to fixup the target flags for imm.
3298 // For some reason, we miss to set the flag for the ImmMO if it is CPI.
3299 if (DefMI.getOpcode() == PPC::ADDItocL)
3300 ImmMO->setTargetFlags(PPCII::MO_TOC_LO);
3301
3302 // MI didn't have the interface such as MI.setOperand(i) though
3303 // it has MI.getOperand(i). To repalce the ZERO MachineOperand with
3304 // ImmMO, we need to remove ZERO operand and all the operands behind it,
3305 // and, add the ImmMO, then, move back all the operands behind ZERO.
3306 SmallVector<MachineOperand, 2> MOps;
3307 for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
3308 MOps.push_back(MI.getOperand(i));
3309 MI.RemoveOperand(i);
3310 }
3311
3312 // Remove the last MO in the list, which is ZERO operand in fact.
3313 MOps.pop_back();
3314 // Add the imm operand.
3315 MI.addOperand(*ImmMO);
3316 // Now add the rest back.
3317 for (auto &MO : MOps)
3318 MI.addOperand(MO);
3319 }
3320
3321 // Update the opcode.
3322 MI.setDesc(get(III.ImmOpcode));
3323
3324 LLVM_DEBUG(dbgs() << "With:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { dbgs() << "With:\n"; } } while (false
)
;
3325 LLVM_DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("ppc-instr-info")) { MI.dump(); } } while (false)
;
3326
3327 return true;
3328}
3329
3330bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
3331 const ImmInstrInfo &III,
3332 unsigned ConstantOpNo,
3333 int64_t Imm) const {
3334 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3335 bool PostRA = !MRI.isSSA();
3336 // Exit early if we can't convert this.
3337 if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
3338 return false;
3339 if (Imm % III.ImmMustBeMultipleOf)
3340 return false;
3341 if (III.TruncateImmTo)
3342 Imm &= ((1 << III.TruncateImmTo) - 1);
3343 if (III.SignedImm) {
3344 APInt ActualValue(64, Imm, true);
3345 if (!ActualValue.isSignedIntN(III.ImmWidth))
3346 return false;
3347 } else {
3348 uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3349 if ((uint64_t)Imm > UnsignedMax)
3350 return false;
3351 }
3352
3353 // If we're post-RA, the instructions don't agree on whether register zero is
3354 // special, we can transform this as long as the register operand that will
3355 // end up in the location where zero is special isn't R0.
3356 if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3357 unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3358 III.ZeroIsSpecialNew + 1;
3359 unsigned OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3360 unsigned NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3361 // If R0 is in the operand where zero is special for the new instruction,
3362 // it is unsafe to transform if the constant operand isn't that operand.
3363 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
3364 ConstantOpNo != III.ZeroIsSpecialNew)
3365 return false;
3366 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
3367 ConstantOpNo != PosForOrigZero)
3368 return false;
3369 }
3370
3371 unsigned Opc = MI.getOpcode();
3372 bool SpecialShift32 =
3373 Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo;
3374 bool SpecialShift64 =
3375 Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo;
3376 bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||
3377 Opc == PPC::SLDo || Opc == PPC::SRDo;
3378 bool RightShift =
3379 Opc == PPC::SRW || Opc == PPC::SRWo || Opc == PPC::SRD || Opc == PPC::SRDo;
3380
3381 MI.setDesc(get(III.ImmOpcode));
3382 if (ConstantOpNo == III.OpNoForForwarding) {
3383 // Converting shifts to immediate form is a bit tricky since they may do
3384 // one of three things:
3385 // 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3386 // 2. If the shift amount is zero, the result is unchanged (save for maybe
3387 // setting CR0)
3388 // 3. If the shift amount is in [1, OpSize), it's just a shift
3389 if (SpecialShift32 || SpecialShift64) {
3390 LoadImmediateInfo LII;
3391 LII.Imm = 0;
3392 LII.SetCR = SetCR;
3393 LII.Is64Bit = SpecialShift64;
3394 uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3395 if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3396 replaceInstrWithLI(MI, LII);
3397 // Shifts by zero don't change the value. If we don't need to set CR0,
3398 // just convert this to a COPY. Can't do this post-RA since we've already
3399 // cleaned up the copies.
3400 else if (!SetCR && ShAmt == 0 && !PostRA) {
3401 MI.RemoveOperand(2);
3402 MI.setDesc(get(PPC::COPY));
3403 } else {
3404 // The 32 bit and 64 bit instructions are quite different.
3405 if (SpecialShift32) {
3406 // Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3407 uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3408 uint64_t MB = RightShift ? ShAmt : 0;
3409 uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3410 MI.getOperand(III.OpNoForForwarding).ChangeToImmediate(SH);
3411 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3412 .addImm(ME);
3413 } else {
3414 // Left shifts use (N, 63-N), right shifts use (64-N, N).
3415 uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3416 uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3417 MI.getOperand(III.OpNoForForwarding).ChangeToImmediate(SH);
3418 MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3419 }
3420 }
3421 } else
3422 MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3423 }
3424 // Convert commutative instructions (switch the operands and convert the
3425 // desired one to an immediate.
3426 else if (III.IsCommutative) {
3427 MI.getOperand(ConstantOpNo).ChangeToImmediate(Imm);
3428 swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
3429 } else
3430 llvm_unreachable("Should have exited early!")::llvm::llvm_unreachable_internal("Should have exited early!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3430)
;
3431
3432 // For instructions for which the constant register replaces a different
3433 // operand than where the immediate goes, we need to swap them.
3434 if (III.OpNoForForwarding != III.ImmOpNo)
3435 swapMIOperands(MI, III.OpNoForForwarding, III.ImmOpNo);
3436
3437 // If the R0/X0 register is special for the original instruction and not for
3438 // the new instruction (or vice versa), we need to fix up the register class.
3439 if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3440 if (!III.ZeroIsSpecialOrig) {
3441 unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3442 const TargetRegisterClass *NewRC =
3443 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3444 &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3445 MRI.setRegClass(RegToModify, NewRC);
3446 }
3447 }
3448 return true;
3449}
3450
3451const TargetRegisterClass *
3452PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
3453 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3454 return &PPC::VSRCRegClass;
3455 return RC;
3456}
3457
3458int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) {
3459 return PPC::getRecordFormOpcode(Opcode);
3460}
3461
3462// This function returns true if the machine instruction
3463// always outputs a value by sign-extending a 32 bit value,
3464// i.e. 0 to 31-th bits are same as 32-th bit.
3465static bool isSignExtendingOp(const MachineInstr &MI) {
3466 int Opcode = MI.getOpcode();
3467 if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3468 Opcode == PPC::LIS || Opcode == PPC::LIS8 ||
3469 Opcode == PPC::SRAW || Opcode == PPC::SRAWo ||
3470 Opcode == PPC::SRAWI || Opcode == PPC::SRAWIo ||
3471 Opcode == PPC::LWA || Opcode == PPC::LWAX ||
3472 Opcode == PPC::LWA_32 || Opcode == PPC::LWAX_32 ||
3473 Opcode == PPC::LHA || Opcode == PPC::LHAX ||
3474 Opcode == PPC::LHA8 || Opcode == PPC::LHAX8 ||
3475 Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3476 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3477 Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3478 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3479 Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3480 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3481 Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3482 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3483 Opcode == PPC::EXTSB || Opcode == PPC::EXTSBo ||
3484 Opcode == PPC::EXTSH || Opcode == PPC::EXTSHo ||
3485 Opcode == PPC::EXTSB8 || Opcode == PPC::EXTSH8 ||
3486 Opcode == PPC::EXTSW || Opcode == PPC::EXTSWo ||
3487 Opcode == PPC::EXTSH8_32_64 || Opcode == PPC::EXTSW_32_64 ||
3488 Opcode == PPC::EXTSB8_32_64)
3489 return true;
3490
3491 if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3492 return true;
3493
3494 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3495 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo) &&
3496 MI.getOperand(3).getImm() > 0 &&
3497 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3498 return true;
3499
3500 return false;
3501}
3502
3503// This function returns true if the machine instruction
3504// always outputs zeros in higher 32 bits.
3505static bool isZeroExtendingOp(const MachineInstr &MI) {
3506 int Opcode = MI.getOpcode();
3507 // The 16-bit immediate is sign-extended in li/lis.
3508 // If the most significant bit is zero, all higher bits are zero.
3509 if (Opcode == PPC::LI || Opcode == PPC::LI8 ||
3510 Opcode == PPC::LIS || Opcode == PPC::LIS8) {
3511 int64_t Imm = MI.getOperand(1).getImm();
3512 if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3513 return true;
3514 }
3515
3516 // We have some variations of rotate-and-mask instructions
3517 // that clear higher 32-bits.
3518 if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo ||
3519 Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo ||
3520 Opcode == PPC::RLDICL_32_64) &&
3521 MI.getOperand(3).getImm() >= 32)
3522 return true;
3523
3524 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) &&
3525 MI.getOperand(3).getImm() >= 32 &&
3526 MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3527 return true;
3528
3529 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo ||
3530 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo ||
3531 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) &&
3532 MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3533 return true;
3534
3535 // There are other instructions that clear higher 32-bits.
3536 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo ||
3537 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo ||
3538 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8 ||
3539 Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZDo ||
3540 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZDo ||
3541 Opcode == PPC::POPCNTD || Opcode == PPC::POPCNTW ||
3542 Opcode == PPC::SLW || Opcode == PPC::SLWo ||
3543 Opcode == PPC::SRW || Opcode == PPC::SRWo ||
3544 Opcode == PPC::SLW8 || Opcode == PPC::SRW8 ||
3545 Opcode == PPC::SLWI || Opcode == PPC::SLWIo ||
3546 Opcode == PPC::SRWI || Opcode == PPC::SRWIo ||
3547 Opcode == PPC::LWZ || Opcode == PPC::LWZX ||
3548 Opcode == PPC::LWZU || Opcode == PPC::LWZUX ||
3549 Opcode == PPC::LWBRX || Opcode == PPC::LHBRX ||
3550 Opcode == PPC::LHZ || Opcode == PPC::LHZX ||
3551 Opcode == PPC::LHZU || Opcode == PPC::LHZUX ||
3552 Opcode == PPC::LBZ || Opcode == PPC::LBZX ||
3553 Opcode == PPC::LBZU || Opcode == PPC::LBZUX ||
3554 Opcode == PPC::LWZ8 || Opcode == PPC::LWZX8 ||
3555 Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8 ||
3556 Opcode == PPC::LWBRX8 || Opcode == PPC::LHBRX8 ||
3557 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 ||
3558 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8 ||
3559 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 ||
3560 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8 ||
3561 Opcode == PPC::ANDIo || Opcode == PPC::ANDISo ||
3562 Opcode == PPC::ROTRWI || Opcode == PPC::ROTRWIo ||
3563 Opcode == PPC::EXTLWI || Opcode == PPC::EXTLWIo ||
3564 Opcode == PPC::MFVSRWZ)
3565 return true;
3566
3567 return false;
3568}
3569
3570// This function returns true if the input MachineInstr is a TOC save
3571// instruction.
3572bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
3573 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isReg())
3574 return false;
3575 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3576 unsigned StackOffset = MI.getOperand(1).getImm();
3577 unsigned StackReg = MI.getOperand(2).getReg();
3578 if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3579 return true;
3580
3581 return false;
3582}
3583
3584// We limit the max depth to track incoming values of PHIs or binary ops
3585// (e.g. AND) to avoid excessive cost.
3586const unsigned MAX_DEPTH = 1;
3587
3588bool
3589PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
3590 const unsigned Depth) const {
3591 const MachineFunction *MF = MI.getParent()->getParent();
3592 const MachineRegisterInfo *MRI = &MF->getRegInfo();
3593
3594 // If we know this instruction returns sign- or zero-extended result,
3595 // return true.
3596 if (SignExt ? isSignExtendingOp(MI):
3597 isZeroExtendingOp(MI))
3598 return true;
3599
3600 switch (MI.getOpcode()) {
3601 case PPC::COPY: {
3602 unsigned SrcReg = MI.getOperand(1).getReg();
3603
3604 // In both ELFv1 and v2 ABI, method parameters and the return value
3605 // are sign- or zero-extended.
3606 if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3607 const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3608 // We check the ZExt/SExt flags for a method parameter.
3609 if (MI.getParent()->getBasicBlock() ==
3610 &MF->getFunction().getEntryBlock()) {
3611 unsigned VReg = MI.getOperand(0).getReg();
3612 if (MF->getRegInfo().isLiveIn(VReg))
3613 return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3614 FuncInfo->isLiveInZExt(VReg);
3615 }
3616
3617 // For a method return value, we check the ZExt/SExt flags in attribute.
3618 // We assume the following code sequence for method call.
3619 // ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3620 // BL8_NOP @func,...
3621 // ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3622 // %5 = COPY %x3; G8RC:%5
3623 if (SrcReg == PPC::X3) {
3624 const MachineBasicBlock *MBB = MI.getParent();
3625 MachineBasicBlock::const_instr_iterator II =
3626 MachineBasicBlock::const_instr_iterator(&MI);
3627 if (II != MBB->instr_begin() &&
3628 (--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3629 const MachineInstr &CallMI = *(--II);
3630 if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3631 const Function *CalleeFn =
3632 dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3633 if (!CalleeFn)
3634 return false;
3635 const IntegerType *IntTy =
3636 dyn_cast<IntegerType>(CalleeFn->getReturnType());
3637 const AttributeSet &Attrs =
3638 CalleeFn->getAttributes().getRetAttributes();
3639 if (IntTy && IntTy->getBitWidth() <= 32)
3640 return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3641 Attribute::ZExt);
3642 }
3643 }
3644 }
3645 }
3646
3647 // If this is a copy from another register, we recursively check source.
3648 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3649 return false;
3650 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3651 if (SrcMI != NULL__null)
3652 return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3653
3654 return false;
3655 }
3656
3657 case PPC::ANDIo:
3658 case PPC::ANDISo:
3659 case PPC::ORI:
3660 case PPC::ORIS:
3661 case PPC::XORI:
3662 case PPC::XORIS:
3663 case PPC::ANDIo8:
3664 case PPC::ANDISo8:
3665 case PPC::ORI8:
3666 case PPC::ORIS8:
3667 case PPC::XORI8:
3668 case PPC::XORIS8: {
3669 // logical operation with 16-bit immediate does not change the upper bits.
3670 // So, we track the operand register as we do for register copy.
3671 unsigned SrcReg = MI.getOperand(1).getReg();
3672 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3673 return false;
3674 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3675 if (SrcMI != NULL__null)
3676 return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3677
3678 return false;
3679 }
3680
3681 // If all incoming values are sign-/zero-extended,
3682 // the output of OR, ISEL or PHI is also sign-/zero-extended.
3683 case PPC::OR:
3684 case PPC::OR8:
3685 case PPC::ISEL:
3686 case PPC::PHI: {
3687 if (Depth >= MAX_DEPTH)
3688 return false;
3689
3690 // The input registers for PHI are operand 1, 3, ...
3691 // The input registers for others are operand 1 and 2.
3692 unsigned E = 3, D = 1;
3693 if (MI.getOpcode() == PPC::PHI) {
3694 E = MI.getNumOperands();
3695 D = 2;
3696 }
3697
3698 for (unsigned I = 1; I != E; I += D) {
3699 if (MI.getOperand(I).isReg()) {
3700 unsigned SrcReg = MI.getOperand(I).getReg();
3701 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3702 return false;
3703 const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3704 if (SrcMI == NULL__null || !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3705 return false;
3706 }
3707 else
3708 return false;
3709 }
3710 return true;
3711 }
3712
3713 // If at least one of the incoming values of an AND is zero extended
3714 // then the output is also zero-extended. If both of the incoming values
3715 // are sign-extended then the output is also sign extended.
3716 case PPC::AND:
3717 case PPC::AND8: {
3718 if (Depth >= MAX_DEPTH)
3719 return false;
3720
3721 assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg())((MI.getOperand(1).isReg() && MI.getOperand(2).isReg(
)) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(1).isReg() && MI.getOperand(2).isReg()"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/PowerPC/PPCInstrInfo.cpp"
, 3721, __PRETTY_FUNCTION__))
;
3722
3723 unsigned SrcReg1 = MI.getOperand(1).getReg();
3724 unsigned SrcReg2 = MI.getOperand(2).getReg();
3725
3726 if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) ||
3727 !TargetRegisterInfo::isVirtualRegister(SrcReg2))
3728 return false;
3729
3730 const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3731 const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3732 if (!MISrc1 || !MISrc2)
3733 return false;
3734
3735 if(SignExt)
3736 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3737 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3738 else
3739 return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) ||
3740 isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3741 }
3742
3743 default:
3744 break;
3745 }
3746 return false;
3747}