/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp

Bug Summary

File:	lib/Target/PowerPC/PPCInstrInfo.cpp
Warning:	line 1775, column 20 Value stored to 'NewPred' during its initialization is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCInstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-9/lib/clang/9.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/include -I /build/llvm-toolchain-snapshot-9~svn362543/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/9.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-9/lib/clang/9.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/lib/Target/PowerPC -fdebug-prefix-map=/build/llvm-toolchain-snapshot-9~svn362543=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2019-06-05-060531-1271-1 -x c++ /build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp -faddrsig

1	//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2	//
3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4	// See https://llvm.org/LICENSE.txt for license information.
5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6	//
7	//===----------------------------------------------------------------------===//
8	//
9	// This file contains the PowerPC implementation of the TargetInstrInfo class.
10	//
11	//===----------------------------------------------------------------------===//
12
13	#include "PPCInstrInfo.h"
14	#include "MCTargetDesc/PPCPredicates.h"
15	#include "PPC.h"
16	#include "PPCHazardRecognizers.h"
17	#include "PPCInstrBuilder.h"
18	#include "PPCMachineFunctionInfo.h"
19	#include "PPCTargetMachine.h"
20	#include "llvm/ADT/STLExtras.h"
21	#include "llvm/ADT/Statistic.h"
22	#include "llvm/CodeGen/LiveIntervals.h"
23	#include "llvm/CodeGen/MachineFrameInfo.h"
24	#include "llvm/CodeGen/MachineFunctionPass.h"
25	#include "llvm/CodeGen/MachineInstrBuilder.h"
26	#include "llvm/CodeGen/MachineMemOperand.h"
27	#include "llvm/CodeGen/MachineRegisterInfo.h"
28	#include "llvm/CodeGen/PseudoSourceValue.h"
29	#include "llvm/CodeGen/ScheduleDAG.h"
30	#include "llvm/CodeGen/SlotIndexes.h"
31	#include "llvm/CodeGen/StackMaps.h"
32	#include "llvm/MC/MCAsmInfo.h"
33	#include "llvm/MC/MCInst.h"
34	#include "llvm/Support/CommandLine.h"
35	#include "llvm/Support/Debug.h"
36	#include "llvm/Support/ErrorHandling.h"
37	#include "llvm/Support/TargetRegistry.h"
38	#include "llvm/Support/raw_ostream.h"
39
40	using namespace llvm;
41
42	#define DEBUG_TYPE"ppc-instr-info" "ppc-instr-info"
43
44	#define GET_INSTRMAP_INFO
45	#define GET_INSTRINFO_CTOR_DTOR
46	#include "PPCGenInstrInfo.inc"
47
48	STATISTIC(NumStoreSPILLVSRRCAsVec,static llvm::Statistic NumStoreSPILLVSRRCAsVec = {"ppc-instr-info" , "NumStoreSPILLVSRRCAsVec", "Number of spillvsrrc spilled to stack as vec" , {0}, {false}}
49	"Number of spillvsrrc spilled to stack as vec")static llvm::Statistic NumStoreSPILLVSRRCAsVec = {"ppc-instr-info" , "NumStoreSPILLVSRRCAsVec", "Number of spillvsrrc spilled to stack as vec" , {0}, {false}};
50	STATISTIC(NumStoreSPILLVSRRCAsGpr,static llvm::Statistic NumStoreSPILLVSRRCAsGpr = {"ppc-instr-info" , "NumStoreSPILLVSRRCAsGpr", "Number of spillvsrrc spilled to stack as gpr" , {0}, {false}}
51	"Number of spillvsrrc spilled to stack as gpr")static llvm::Statistic NumStoreSPILLVSRRCAsGpr = {"ppc-instr-info" , "NumStoreSPILLVSRRCAsGpr", "Number of spillvsrrc spilled to stack as gpr" , {0}, {false}};
52	STATISTIC(NumGPRtoVSRSpill, "Number of gpr spills to spillvsrrc")static llvm::Statistic NumGPRtoVSRSpill = {"ppc-instr-info", "NumGPRtoVSRSpill" , "Number of gpr spills to spillvsrrc", {0}, {false}};
53	STATISTIC(CmpIselsConverted,static llvm::Statistic CmpIselsConverted = {"ppc-instr-info", "CmpIselsConverted", "Number of ISELs that depend on comparison of constants converted" , {0}, {false}}
54	"Number of ISELs that depend on comparison of constants converted")static llvm::Statistic CmpIselsConverted = {"ppc-instr-info", "CmpIselsConverted", "Number of ISELs that depend on comparison of constants converted" , {0}, {false}};
55	STATISTIC(MissedConvertibleImmediateInstrs,static llvm::Statistic MissedConvertibleImmediateInstrs = {"ppc-instr-info" , "MissedConvertibleImmediateInstrs", "Number of compare-immediate instructions fed by constants" , {0}, {false}}
56	"Number of compare-immediate instructions fed by constants")static llvm::Statistic MissedConvertibleImmediateInstrs = {"ppc-instr-info" , "MissedConvertibleImmediateInstrs", "Number of compare-immediate instructions fed by constants" , {0}, {false}};
57	STATISTIC(NumRcRotatesConvertedToRcAnd,static llvm::Statistic NumRcRotatesConvertedToRcAnd = {"ppc-instr-info" , "NumRcRotatesConvertedToRcAnd", "Number of record-form rotates converted to record-form andi" , {0}, {false}}
58	"Number of record-form rotates converted to record-form andi")static llvm::Statistic NumRcRotatesConvertedToRcAnd = {"ppc-instr-info" , "NumRcRotatesConvertedToRcAnd", "Number of record-form rotates converted to record-form andi" , {0}, {false}};
59
60	static cl::
61	opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
62	cl::desc("Disable analysis for CTR loops"));
63
64	static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt",
65	cl::desc("Disable compare instruction optimization"), cl::Hidden);
66
67	static cl::opt<bool> VSXSelfCopyCrash("crash-on-ppc-vsx-self-copy",
68	cl::desc("Causes the backend to crash instead of generating a nop VSX copy"),
69	cl::Hidden);
70
71	static cl::opt<bool>
72	UseOldLatencyCalc("ppc-old-latency-calc", cl::Hidden,
73	cl::desc("Use the old (incorrect) instruction latency calculation"));
74
75	// Index into the OpcodesForSpill array.
76	enum SpillOpcodeKey {
77	SOK_Int4Spill,
78	SOK_Int8Spill,
79	SOK_Float8Spill,
80	SOK_Float4Spill,
81	SOK_CRSpill,
82	SOK_CRBitSpill,
83	SOK_VRVectorSpill,
84	SOK_VSXVectorSpill,
85	SOK_VectorFloat8Spill,
86	SOK_VectorFloat4Spill,
87	SOK_VRSaveSpill,
88	SOK_QuadFloat8Spill,
89	SOK_QuadFloat4Spill,
90	SOK_QuadBitSpill,
91	SOK_SpillToVSR,
92	SOK_SPESpill,
93	SOK_SPE4Spill,
94	SOK_LastOpcodeSpill // This must be last on the enum.
95	};
96
97	// Pin the vtable to this file.
98	void PPCInstrInfo::anchor() {}
99
100	PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
101	: PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP,
102	/* CatchRetOpcode */ -1,
103	STI.isPPC64() ? PPC::BLR8 : PPC::BLR),
104	Subtarget(STI), RI(STI.getTargetMachine()) {}
105
106	/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
107	/// this target when scheduling the DAG.
108	ScheduleHazardRecognizer *
109	PPCInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
110	const ScheduleDAG *DAG) const {
111	unsigned Directive =
112	static_cast<const PPCSubtarget *>(STI)->getDarwinDirective();
113	if (Directive == PPC::DIR_440 \|\| Directive == PPC::DIR_A2 \|\|
114	Directive == PPC::DIR_E500mc \|\| Directive == PPC::DIR_E5500) {
115	const InstrItineraryData *II =
116	static_cast<const PPCSubtarget *>(STI)->getInstrItineraryData();
117	return new ScoreboardHazardRecognizer(II, DAG);
118	}
119
120	return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
121	}
122
123	/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
124	/// to use for this target when scheduling the DAG.
125	ScheduleHazardRecognizer *
126	PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
127	const ScheduleDAG *DAG) const {
128	unsigned Directive =
129	DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
130
131	// FIXME: Leaving this as-is until we have POWER9 scheduling info
132	if (Directive == PPC::DIR_PWR7 \|\| Directive == PPC::DIR_PWR8)
133	return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
134
135	// Most subtargets use a PPC970 recognizer.
136	if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
137	Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
138	assert(DAG->TII && "No InstrInfo?")((DAG->TII && "No InstrInfo?") ? static_cast<void > (0) : __assert_fail ("DAG->TII && \"No InstrInfo?\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 138, __PRETTY_FUNCTION__));
139
140	return new PPCHazardRecognizer970(*DAG);
141	}
142
143	return new ScoreboardHazardRecognizer(II, DAG);
144	}
145
146	unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
147	const MachineInstr &MI,
148	unsigned *PredCost) const {
149	if (!ItinData \|\| UseOldLatencyCalc)
150	return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
151
152	// The default implementation of getInstrLatency calls getStageLatency, but
153	// getStageLatency does not do the right thing for us. While we have
154	// itinerary, most cores are fully pipelined, and so the itineraries only
155	// express the first part of the pipeline, not every stage. Instead, we need
156	// to use the listed output operand cycle number (using operand 0 here, which
157	// is an output).
158
159	unsigned Latency = 1;
160	unsigned DefClass = MI.getDesc().getSchedClass();
161	for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
162	const MachineOperand &MO = MI.getOperand(i);
163	if (!MO.isReg() \|\| !MO.isDef() \|\| MO.isImplicit())
164	continue;
165
166	int Cycle = ItinData->getOperandCycle(DefClass, i);
167	if (Cycle < 0)
168	continue;
169
170	Latency = std::max(Latency, (unsigned) Cycle);
171	}
172
173	return Latency;
174	}
175
176	int PPCInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
177	const MachineInstr &DefMI, unsigned DefIdx,
178	const MachineInstr &UseMI,
179	unsigned UseIdx) const {
180	int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
181	UseMI, UseIdx);
182
183	if (!DefMI.getParent())
184	return Latency;
185
186	const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
187	unsigned Reg = DefMO.getReg();
188
189	bool IsRegCR;
190	if (TargetRegisterInfo::isVirtualRegister(Reg)) {
191	const MachineRegisterInfo *MRI =
192	&DefMI.getParent()->getParent()->getRegInfo();
193	IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) \|\|
194	MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass);
195	} else {
196	IsRegCR = PPC::CRRCRegClass.contains(Reg) \|\|
197	PPC::CRBITRCRegClass.contains(Reg);
198	}
199
200	if (UseMI.isBranch() && IsRegCR) {
201	if (Latency < 0)
202	Latency = getInstrLatency(ItinData, DefMI);
203
204	// On some cores, there is an additional delay between writing to a condition
205	// register, and using it from a branch.
206	unsigned Directive = Subtarget.getDarwinDirective();
207	switch (Directive) {
208	default: break;
209	case PPC::DIR_7400:
210	case PPC::DIR_750:
211	case PPC::DIR_970:
212	case PPC::DIR_E5500:
213	case PPC::DIR_PWR4:
214	case PPC::DIR_PWR5:
215	case PPC::DIR_PWR5X:
216	case PPC::DIR_PWR6:
217	case PPC::DIR_PWR6X:
218	case PPC::DIR_PWR7:
219	case PPC::DIR_PWR8:
220	// FIXME: Is this needed for POWER9?
221	Latency += 2;
222	break;
223	}
224	}
225
226	return Latency;
227	}
228
229	// This function does not list all associative and commutative operations, but
230	// only those worth feeding through the machine combiner in an attempt to
231	// reduce the critical path. Mostly, this means floating-point operations,
232	// because they have high latencies (compared to other operations, such and
233	// and/or, which are also associative and commutative, but have low latencies).
234	bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
235	switch (Inst.getOpcode()) {
236	// FP Add:
237	case PPC::FADD:
238	case PPC::FADDS:
239	// FP Multiply:
240	case PPC::FMUL:
241	case PPC::FMULS:
242	// Altivec Add:
243	case PPC::VADDFP:
244	// VSX Add:
245	case PPC::XSADDDP:
246	case PPC::XVADDDP:
247	case PPC::XVADDSP:
248	case PPC::XSADDSP:
249	// VSX Multiply:
250	case PPC::XSMULDP:
251	case PPC::XVMULDP:
252	case PPC::XVMULSP:
253	case PPC::XSMULSP:
254	// QPX Add:
255	case PPC::QVFADD:
256	case PPC::QVFADDS:
257	case PPC::QVFADDSs:
258	// QPX Multiply:
259	case PPC::QVFMUL:
260	case PPC::QVFMULS:
261	case PPC::QVFMULSs:
262	return true;
263	default:
264	return false;
265	}
266	}
267
268	bool PPCInstrInfo::getMachineCombinerPatterns(
269	MachineInstr &Root,
270	SmallVectorImpl<MachineCombinerPattern> &Patterns) const {
271	// Using the machine combiner in this way is potentially expensive, so
272	// restrict to when aggressive optimizations are desired.
273	if (Subtarget.getTargetMachine().getOptLevel() != CodeGenOpt::Aggressive)
274	return false;
275
276	// FP reassociation is only legal when we don't need strict IEEE semantics.
277	if (!Root.getParent()->getParent()->getTarget().Options.UnsafeFPMath)
278	return false;
279
280	return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns);
281	}
282
283	// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
284	bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
285	unsigned &SrcReg, unsigned &DstReg,
286	unsigned &SubIdx) const {
287	switch (MI.getOpcode()) {
288	default: return false;
289	case PPC::EXTSW:
290	case PPC::EXTSW_32:
291	case PPC::EXTSW_32_64:
292	SrcReg = MI.getOperand(1).getReg();
293	DstReg = MI.getOperand(0).getReg();
294	SubIdx = PPC::sub_32;
295	return true;
296	}
297	}
298
299	unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
300	int &FrameIndex) const {
301	unsigned Opcode = MI.getOpcode();
302	const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
303	const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
304
305	if (End != std::find(OpcodesForSpill, End, Opcode)) {
306	// Check for the operands added by addFrameReference (the immediate is the
307	// offset which defaults to 0).
308	if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
309	MI.getOperand(2).isFI()) {
310	FrameIndex = MI.getOperand(2).getIndex();
311	return MI.getOperand(0).getReg();
312	}
313	}
314	return 0;
315	}
316
317	// For opcodes with the ReMaterializable flag set, this function is called to
318	// verify the instruction is really rematable.
319	bool PPCInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
320	AliasAnalysis *AA) const {
321	switch (MI.getOpcode()) {
322	default:
323	// This function should only be called for opcodes with the ReMaterializable
324	// flag set.
325	llvm_unreachable("Unknown rematerializable operation!")::llvm::llvm_unreachable_internal("Unknown rematerializable operation!" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 325);
326	break;
327	case PPC::LI:
328	case PPC::LI8:
329	case PPC::LIS:
330	case PPC::LIS8:
331	case PPC::QVGPCI:
332	case PPC::ADDIStocHA:
333	case PPC::ADDItocL:
334	case PPC::LOAD_STACK_GUARD:
335	case PPC::XXLXORz:
336	case PPC::XXLXORspz:
337	case PPC::XXLXORdpz:
338	case PPC::V_SET0B:
339	case PPC::V_SET0H:
340	case PPC::V_SET0:
341	case PPC::V_SETALLONESB:
342	case PPC::V_SETALLONESH:
343	case PPC::V_SETALLONES:
344	case PPC::CRSET:
345	case PPC::CRUNSET:
346	return true;
347	}
348	return false;
349	}
350
351	unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
352	int &FrameIndex) const {
353	unsigned Opcode = MI.getOpcode();
354	const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
355	const unsigned *End = OpcodesForSpill + SOK_LastOpcodeSpill;
356
357	if (End != std::find(OpcodesForSpill, End, Opcode)) {
358	if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() &&
359	MI.getOperand(2).isFI()) {
360	FrameIndex = MI.getOperand(2).getIndex();
361	return MI.getOperand(0).getReg();
362	}
363	}
364	return 0;
365	}
366
367	MachineInstr *PPCInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
368	unsigned OpIdx1,
369	unsigned OpIdx2) const {
370	MachineFunction &MF = *MI.getParent()->getParent();
371
372	// Normal instructions can be commuted the obvious way.
373	if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMIo)
374	return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
375	// Note that RLWIMI can be commuted as a 32-bit instruction, but not as a
376	// 64-bit instruction (so we don't handle PPC::RLWIMI8 here), because
377	// changing the relative order of the mask operands might change what happens
378	// to the high-bits of the mask (and, thus, the result).
379
380	// Cannot commute if it has a non-zero rotate count.
381	if (MI.getOperand(3).getImm() != 0)
382	return nullptr;
383
384	// If we have a zero rotate count, we have:
385	// M = mask(MB,ME)
386	// Op0 = (Op1 & ~M) \| (Op2 & M)
387	// Change this to:
388	// M = mask((ME+1)&31, (MB-1)&31)
389	// Op0 = (Op2 & ~M) \| (Op1 & M)
390
391	// Swap op1/op2
392	assert(((OpIdx1 == 1 && OpIdx2 == 2) \|\| (OpIdx1 == 2 && OpIdx2 == 1)) &&((((OpIdx1 == 1 && OpIdx2 == 2) \|\| (OpIdx1 == 2 && OpIdx2 == 1)) && "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo." ) ? static_cast<void> (0) : __assert_fail ("((OpIdx1 == 1 && OpIdx2 == 2) \|\| (OpIdx1 == 2 && OpIdx2 == 1)) && \"Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 393, __PRETTY_FUNCTION__))
393	"Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.")((((OpIdx1 == 1 && OpIdx2 == 2) \|\| (OpIdx1 == 2 && OpIdx2 == 1)) && "Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo." ) ? static_cast<void> (0) : __assert_fail ("((OpIdx1 == 1 && OpIdx2 == 2) \|\| (OpIdx1 == 2 && OpIdx2 == 1)) && \"Only the operands 1 and 2 can be swapped in RLSIMI/RLWIMIo.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 393, __PRETTY_FUNCTION__));
394	unsigned Reg0 = MI.getOperand(0).getReg();
395	unsigned Reg1 = MI.getOperand(1).getReg();
396	unsigned Reg2 = MI.getOperand(2).getReg();
397	unsigned SubReg1 = MI.getOperand(1).getSubReg();
398	unsigned SubReg2 = MI.getOperand(2).getSubReg();
399	bool Reg1IsKill = MI.getOperand(1).isKill();
400	bool Reg2IsKill = MI.getOperand(2).isKill();
401	bool ChangeReg0 = false;
402	// If machine instrs are no longer in two-address forms, update
403	// destination register as well.
404	if (Reg0 == Reg1) {
405	// Must be two address instruction!
406	assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&((MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && "Expecting a two-address instruction!") ? static_cast<void > (0) : __assert_fail ("MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && \"Expecting a two-address instruction!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 407, __PRETTY_FUNCTION__))
407	"Expecting a two-address instruction!")((MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && "Expecting a two-address instruction!") ? static_cast<void > (0) : __assert_fail ("MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && \"Expecting a two-address instruction!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 407, __PRETTY_FUNCTION__));
408	assert(MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch")((MI.getOperand(0).getSubReg() == SubReg1 && "Tied subreg mismatch" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).getSubReg() == SubReg1 && \"Tied subreg mismatch\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 408, __PRETTY_FUNCTION__));
409	Reg2IsKill = false;
410	ChangeReg0 = true;
411	}
412
413	// Masks.
414	unsigned MB = MI.getOperand(4).getImm();
415	unsigned ME = MI.getOperand(5).getImm();
416
417	// We can't commute a trivial mask (there is no way to represent an all-zero
418	// mask).
419	if (MB == 0 && ME == 31)
420	return nullptr;
421
422	if (NewMI) {
423	// Create a new instruction.
424	unsigned Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
425	bool Reg0IsDead = MI.getOperand(0).isDead();
426	return BuildMI(MF, MI.getDebugLoc(), MI.getDesc())
427	.addReg(Reg0, RegState::Define \| getDeadRegState(Reg0IsDead))
428	.addReg(Reg2, getKillRegState(Reg2IsKill))
429	.addReg(Reg1, getKillRegState(Reg1IsKill))
430	.addImm((ME + 1) & 31)
431	.addImm((MB - 1) & 31);
432	}
433
434	if (ChangeReg0) {
435	MI.getOperand(0).setReg(Reg2);
436	MI.getOperand(0).setSubReg(SubReg2);
437	}
438	MI.getOperand(2).setReg(Reg1);
439	MI.getOperand(1).setReg(Reg2);
440	MI.getOperand(2).setSubReg(SubReg1);
441	MI.getOperand(1).setSubReg(SubReg2);
442	MI.getOperand(2).setIsKill(Reg1IsKill);
443	MI.getOperand(1).setIsKill(Reg2IsKill);
444
445	// Swap the mask around.
446	MI.getOperand(4).setImm((ME + 1) & 31);
447	MI.getOperand(5).setImm((MB - 1) & 31);
448	return &MI;
449	}
450
451	bool PPCInstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
452	unsigned &SrcOpIdx2) const {
453	// For VSX A-Type FMA instructions, it is the first two operands that can be
454	// commuted, however, because the non-encoded tied input operand is listed
455	// first, the operands to swap are actually the second and third.
456
457	int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode());
458	if (AltOpc == -1)
459	return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
460
461	// The commutable operand indices are 2 and 3. Return them in SrcOpIdx1
462	// and SrcOpIdx2.
463	return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
464	}
465
466	void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
467	MachineBasicBlock::iterator MI) const {
468	// This function is used for scheduling, and the nop wanted here is the type
469	// that terminates dispatch groups on the POWER cores.
470	unsigned Directive = Subtarget.getDarwinDirective();
471	unsigned Opcode;
472	switch (Directive) {
473	default: Opcode = PPC::NOP; break;
474	case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
475	case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
476	case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
477	// FIXME: Update when POWER9 scheduling model is ready.
478	case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
479	}
480
481	DebugLoc DL;
482	BuildMI(MBB, MI, DL, get(Opcode));
483	}
484
485	/// Return the noop instruction to use for a noop.
486	void PPCInstrInfo::getNoop(MCInst &NopInst) const {
487	NopInst.setOpcode(PPC::NOP);
488	}
489
490	// Branch analysis.
491	// Note: If the condition register is set to CTR or CTR8 then this is a
492	// BDNZ (imm == 1) or BDZ (imm == 0) branch.
493	bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
494	MachineBasicBlock *&TBB,
495	MachineBasicBlock *&FBB,
496	SmallVectorImpl<MachineOperand> &Cond,
497	bool AllowModify) const {
498	bool isPPC64 = Subtarget.isPPC64();
499
500	// If the block has no terminators, it just falls into the block after it.
501	MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
502	if (I == MBB.end())
503	return false;
504
505	if (!isUnpredicatedTerminator(*I))
506	return false;
507
508	if (AllowModify) {
509	// If the BB ends with an unconditional branch to the fallthrough BB,
510	// we eliminate the branch instruction.
511	if (I->getOpcode() == PPC::B &&
512	MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
513	I->eraseFromParent();
514
515	// We update iterator after deleting the last branch.
516	I = MBB.getLastNonDebugInstr();
517	if (I == MBB.end() \|\| !isUnpredicatedTerminator(*I))
518	return false;
519	}
520	}
521
522	// Get the last instruction in the block.
523	MachineInstr &LastInst = *I;
524
525	// If there is only one terminator instruction, process it.
526	if (I == MBB.begin() \|\| !isUnpredicatedTerminator(*--I)) {
527	if (LastInst.getOpcode() == PPC::B) {
528	if (!LastInst.getOperand(0).isMBB())
529	return true;
530	TBB = LastInst.getOperand(0).getMBB();
531	return false;
532	} else if (LastInst.getOpcode() == PPC::BCC) {
533	if (!LastInst.getOperand(2).isMBB())
534	return true;
535	// Block ends with fall-through condbranch.
536	TBB = LastInst.getOperand(2).getMBB();
537	Cond.push_back(LastInst.getOperand(0));
538	Cond.push_back(LastInst.getOperand(1));
539	return false;
540	} else if (LastInst.getOpcode() == PPC::BC) {
541	if (!LastInst.getOperand(1).isMBB())
542	return true;
543	// Block ends with fall-through condbranch.
544	TBB = LastInst.getOperand(1).getMBB();
545	Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
546	Cond.push_back(LastInst.getOperand(0));
547	return false;
548	} else if (LastInst.getOpcode() == PPC::BCn) {
549	if (!LastInst.getOperand(1).isMBB())
550	return true;
551	// Block ends with fall-through condbranch.
552	TBB = LastInst.getOperand(1).getMBB();
553	Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
554	Cond.push_back(LastInst.getOperand(0));
555	return false;
556	} else if (LastInst.getOpcode() == PPC::BDNZ8 \|\|
557	LastInst.getOpcode() == PPC::BDNZ) {
558	if (!LastInst.getOperand(0).isMBB())
559	return true;
560	if (DisableCTRLoopAnal)
561	return true;
562	TBB = LastInst.getOperand(0).getMBB();
563	Cond.push_back(MachineOperand::CreateImm(1));
564	Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
565	true));
566	return false;
567	} else if (LastInst.getOpcode() == PPC::BDZ8 \|\|
568	LastInst.getOpcode() == PPC::BDZ) {
569	if (!LastInst.getOperand(0).isMBB())
570	return true;
571	if (DisableCTRLoopAnal)
572	return true;
573	TBB = LastInst.getOperand(0).getMBB();
574	Cond.push_back(MachineOperand::CreateImm(0));
575	Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
576	true));
577	return false;
578	}
579
580	// Otherwise, don't know what this is.
581	return true;
582	}
583
584	// Get the instruction before it if it's a terminator.
585	MachineInstr &SecondLastInst = *I;
586
587	// If there are three terminators, we don't know what sort of block this is.
588	if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
589	return true;
590
591	// If the block ends with PPC::B and PPC:BCC, handle it.
592	if (SecondLastInst.getOpcode() == PPC::BCC &&
593	LastInst.getOpcode() == PPC::B) {
594	if (!SecondLastInst.getOperand(2).isMBB() \|\|
595	!LastInst.getOperand(0).isMBB())
596	return true;
597	TBB = SecondLastInst.getOperand(2).getMBB();
598	Cond.push_back(SecondLastInst.getOperand(0));
599	Cond.push_back(SecondLastInst.getOperand(1));
600	FBB = LastInst.getOperand(0).getMBB();
601	return false;
602	} else if (SecondLastInst.getOpcode() == PPC::BC &&
603	LastInst.getOpcode() == PPC::B) {
604	if (!SecondLastInst.getOperand(1).isMBB() \|\|
605	!LastInst.getOperand(0).isMBB())
606	return true;
607	TBB = SecondLastInst.getOperand(1).getMBB();
608	Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
609	Cond.push_back(SecondLastInst.getOperand(0));
610	FBB = LastInst.getOperand(0).getMBB();
611	return false;
612	} else if (SecondLastInst.getOpcode() == PPC::BCn &&
613	LastInst.getOpcode() == PPC::B) {
614	if (!SecondLastInst.getOperand(1).isMBB() \|\|
615	!LastInst.getOperand(0).isMBB())
616	return true;
617	TBB = SecondLastInst.getOperand(1).getMBB();
618	Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET));
619	Cond.push_back(SecondLastInst.getOperand(0));
620	FBB = LastInst.getOperand(0).getMBB();
621	return false;
622	} else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 \|\|
623	SecondLastInst.getOpcode() == PPC::BDNZ) &&
624	LastInst.getOpcode() == PPC::B) {
625	if (!SecondLastInst.getOperand(0).isMBB() \|\|
626	!LastInst.getOperand(0).isMBB())
627	return true;
628	if (DisableCTRLoopAnal)
629	return true;
630	TBB = SecondLastInst.getOperand(0).getMBB();
631	Cond.push_back(MachineOperand::CreateImm(1));
632	Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
633	true));
634	FBB = LastInst.getOperand(0).getMBB();
635	return false;
636	} else if ((SecondLastInst.getOpcode() == PPC::BDZ8 \|\|
637	SecondLastInst.getOpcode() == PPC::BDZ) &&
638	LastInst.getOpcode() == PPC::B) {
639	if (!SecondLastInst.getOperand(0).isMBB() \|\|
640	!LastInst.getOperand(0).isMBB())
641	return true;
642	if (DisableCTRLoopAnal)
643	return true;
644	TBB = SecondLastInst.getOperand(0).getMBB();
645	Cond.push_back(MachineOperand::CreateImm(0));
646	Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
647	true));
648	FBB = LastInst.getOperand(0).getMBB();
649	return false;
650	}
651
652	// If the block ends with two PPC:Bs, handle it. The second one is not
653	// executed, so remove it.
654	if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) {
655	if (!SecondLastInst.getOperand(0).isMBB())
656	return true;
657	TBB = SecondLastInst.getOperand(0).getMBB();
658	I = LastInst;
659	if (AllowModify)
660	I->eraseFromParent();
661	return false;
662	}
663
664	// Otherwise, can't handle this.
665	return true;
666	}
667
668	unsigned PPCInstrInfo::removeBranch(MachineBasicBlock &MBB,
669	int *BytesRemoved) const {
670	assert(!BytesRemoved && "code size not handled")((!BytesRemoved && "code size not handled") ? static_cast <void> (0) : __assert_fail ("!BytesRemoved && \"code size not handled\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 670, __PRETTY_FUNCTION__));
671
672	MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
673	if (I == MBB.end())
674	return 0;
675
676	if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
677	I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
678	I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
679	I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
680	return 0;
681
682	// Remove the branch.
683	I->eraseFromParent();
684
685	I = MBB.end();
686
687	if (I == MBB.begin()) return 1;
688	--I;
689	if (I->getOpcode() != PPC::BCC &&
690	I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn &&
691	I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
692	I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ)
693	return 1;
694
695	// Remove the branch.
696	I->eraseFromParent();
697	return 2;
698	}
699
700	unsigned PPCInstrInfo::insertBranch(MachineBasicBlock &MBB,
701	MachineBasicBlock *TBB,
702	MachineBasicBlock *FBB,
703	ArrayRef<MachineOperand> Cond,
704	const DebugLoc &DL,
705	int *BytesAdded) const {
706	// Shouldn't be a fall through.
707	assert(TBB && "insertBranch must not be told to insert a fallthrough")((TBB && "insertBranch must not be told to insert a fallthrough" ) ? static_cast<void> (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 707, __PRETTY_FUNCTION__));
708	assert((Cond.size() == 2 \|\| Cond.size() == 0) &&(((Cond.size() == 2 \|\| Cond.size() == 0) && "PPC branch conditions have two components!" ) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 2 \|\| Cond.size() == 0) && \"PPC branch conditions have two components!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 709, __PRETTY_FUNCTION__))
709	"PPC branch conditions have two components!")(((Cond.size() == 2 \|\| Cond.size() == 0) && "PPC branch conditions have two components!" ) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 2 \|\| Cond.size() == 0) && \"PPC branch conditions have two components!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 709, __PRETTY_FUNCTION__));
710	assert(!BytesAdded && "code size not handled")((!BytesAdded && "code size not handled") ? static_cast <void> (0) : __assert_fail ("!BytesAdded && \"code size not handled\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 710, __PRETTY_FUNCTION__));
711
712	bool isPPC64 = Subtarget.isPPC64();
713
714	// One-way branch.
715	if (!FBB) {
716	if (Cond.empty()) // Unconditional branch
717	BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
718	else if (Cond[1].getReg() == PPC::CTR \|\| Cond[1].getReg() == PPC::CTR8)
719	BuildMI(&MBB, DL, get(Cond[0].getImm() ?
720	(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
721	(isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
722	else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
723	BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
724	else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
725	BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
726	else // Conditional branch
727	BuildMI(&MBB, DL, get(PPC::BCC))
728	.addImm(Cond[0].getImm())
729	.add(Cond[1])
730	.addMBB(TBB);
731	return 1;
732	}
733
734	// Two-way Conditional Branch.
735	if (Cond[1].getReg() == PPC::CTR \|\| Cond[1].getReg() == PPC::CTR8)
736	BuildMI(&MBB, DL, get(Cond[0].getImm() ?
737	(isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
738	(isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
739	else if (Cond[0].getImm() == PPC::PRED_BIT_SET)
740	BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
741	else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET)
742	BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
743	else
744	BuildMI(&MBB, DL, get(PPC::BCC))
745	.addImm(Cond[0].getImm())
746	.add(Cond[1])
747	.addMBB(TBB);
748	BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
749	return 2;
750	}
751
752	// Select analysis.
753	bool PPCInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
754	ArrayRef<MachineOperand> Cond,
755	unsigned TrueReg, unsigned FalseReg,
756	int &CondCycles, int &TrueCycles, int &FalseCycles) const {
757	if (Cond.size() != 2)
758	return false;
759
760	// If this is really a bdnz-like condition, then it cannot be turned into a
761	// select.
762	if (Cond[1].getReg() == PPC::CTR \|\| Cond[1].getReg() == PPC::CTR8)
763	return false;
764
765	// Check register classes.
766	const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
767	const TargetRegisterClass *RC =
768	RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
769	if (!RC)
770	return false;
771
772	// isel is for regular integer GPRs only.
773	if (!PPC::GPRCRegClass.hasSubClassEq(RC) &&
774	!PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) &&
775	!PPC::G8RCRegClass.hasSubClassEq(RC) &&
776	!PPC::G8RC_NOX0RegClass.hasSubClassEq(RC))
777	return false;
778
779	// FIXME: These numbers are for the A2, how well they work for other cores is
780	// an open question. On the A2, the isel instruction has a 2-cycle latency
781	// but single-cycle throughput. These numbers are used in combination with
782	// the MispredictPenalty setting from the active SchedMachineModel.
783	CondCycles = 1;
784	TrueCycles = 1;
785	FalseCycles = 1;
786
787	return true;
788	}
789
790	void PPCInstrInfo::insertSelect(MachineBasicBlock &MBB,
791	MachineBasicBlock::iterator MI,
792	const DebugLoc &dl, unsigned DestReg,
793	ArrayRef<MachineOperand> Cond, unsigned TrueReg,
794	unsigned FalseReg) const {
795	assert(Cond.size() == 2 &&((Cond.size() == 2 && "PPC branch conditions have two components!" ) ? static_cast<void> (0) : __assert_fail ("Cond.size() == 2 && \"PPC branch conditions have two components!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 796, __PRETTY_FUNCTION__))
796	"PPC branch conditions have two components!")((Cond.size() == 2 && "PPC branch conditions have two components!" ) ? static_cast<void> (0) : __assert_fail ("Cond.size() == 2 && \"PPC branch conditions have two components!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 796, __PRETTY_FUNCTION__));
797
798	// Get the register classes.
799	MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
800	const TargetRegisterClass *RC =
801	RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
802	assert(RC && "TrueReg and FalseReg must have overlapping register classes")((RC && "TrueReg and FalseReg must have overlapping register classes" ) ? static_cast<void> (0) : __assert_fail ("RC && \"TrueReg and FalseReg must have overlapping register classes\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 802, __PRETTY_FUNCTION__));
803
804	bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) \|\|
805	PPC::G8RC_NOX0RegClass.hasSubClassEq(RC);
806	assert((Is64Bit \|\|(((Is64Bit \|\| PPC::GPRCRegClass.hasSubClassEq(RC) \|\| PPC::GPRC_NOR0RegClass .hasSubClassEq(RC)) && "isel is for regular integer GPRs only" ) ? static_cast<void> (0) : __assert_fail ("(Is64Bit \|\| PPC::GPRCRegClass.hasSubClassEq(RC) \|\| PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 809, __PRETTY_FUNCTION__))
807	PPC::GPRCRegClass.hasSubClassEq(RC) \|\|(((Is64Bit \|\| PPC::GPRCRegClass.hasSubClassEq(RC) \|\| PPC::GPRC_NOR0RegClass .hasSubClassEq(RC)) && "isel is for regular integer GPRs only" ) ? static_cast<void> (0) : __assert_fail ("(Is64Bit \|\| PPC::GPRCRegClass.hasSubClassEq(RC) \|\| PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 809, __PRETTY_FUNCTION__))
808	PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) &&(((Is64Bit \|\| PPC::GPRCRegClass.hasSubClassEq(RC) \|\| PPC::GPRC_NOR0RegClass .hasSubClassEq(RC)) && "isel is for regular integer GPRs only" ) ? static_cast<void> (0) : __assert_fail ("(Is64Bit \|\| PPC::GPRCRegClass.hasSubClassEq(RC) \|\| PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 809, __PRETTY_FUNCTION__))
809	"isel is for regular integer GPRs only")(((Is64Bit \|\| PPC::GPRCRegClass.hasSubClassEq(RC) \|\| PPC::GPRC_NOR0RegClass .hasSubClassEq(RC)) && "isel is for regular integer GPRs only" ) ? static_cast<void> (0) : __assert_fail ("(Is64Bit \|\| PPC::GPRCRegClass.hasSubClassEq(RC) \|\| PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && \"isel is for regular integer GPRs only\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 809, __PRETTY_FUNCTION__));
810
811	unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL;
812	auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm());
813
814	unsigned SubIdx = 0;
815	bool SwapOps = false;
816	switch (SelectPred) {
817	case PPC::PRED_EQ:
818	case PPC::PRED_EQ_MINUS:
819	case PPC::PRED_EQ_PLUS:
820	SubIdx = PPC::sub_eq; SwapOps = false; break;
821	case PPC::PRED_NE:
822	case PPC::PRED_NE_MINUS:
823	case PPC::PRED_NE_PLUS:
824	SubIdx = PPC::sub_eq; SwapOps = true; break;
825	case PPC::PRED_LT:
826	case PPC::PRED_LT_MINUS:
827	case PPC::PRED_LT_PLUS:
828	SubIdx = PPC::sub_lt; SwapOps = false; break;
829	case PPC::PRED_GE:
830	case PPC::PRED_GE_MINUS:
831	case PPC::PRED_GE_PLUS:
832	SubIdx = PPC::sub_lt; SwapOps = true; break;
833	case PPC::PRED_GT:
834	case PPC::PRED_GT_MINUS:
835	case PPC::PRED_GT_PLUS:
836	SubIdx = PPC::sub_gt; SwapOps = false; break;
837	case PPC::PRED_LE:
838	case PPC::PRED_LE_MINUS:
839	case PPC::PRED_LE_PLUS:
840	SubIdx = PPC::sub_gt; SwapOps = true; break;
841	case PPC::PRED_UN:
842	case PPC::PRED_UN_MINUS:
843	case PPC::PRED_UN_PLUS:
844	SubIdx = PPC::sub_un; SwapOps = false; break;
845	case PPC::PRED_NU:
846	case PPC::PRED_NU_MINUS:
847	case PPC::PRED_NU_PLUS:
848	SubIdx = PPC::sub_un; SwapOps = true; break;
849	case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break;
850	case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break;
851	}
852
853	unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
854	SecondReg = SwapOps ? TrueReg : FalseReg;
855
856	// The first input register of isel cannot be r0. If it is a member
857	// of a register class that can be r0, then copy it first (the
858	// register allocator should eliminate the copy).
859	if (MRI.getRegClass(FirstReg)->contains(PPC::R0) \|\|
860	MRI.getRegClass(FirstReg)->contains(PPC::X0)) {
861	const TargetRegisterClass *FirstRC =
862	MRI.getRegClass(FirstReg)->contains(PPC::X0) ?
863	&PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass;
864	unsigned OldFirstReg = FirstReg;
865	FirstReg = MRI.createVirtualRegister(FirstRC);
866	BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
867	.addReg(OldFirstReg);
868	}
869
870	BuildMI(MBB, MI, dl, get(OpCode), DestReg)
871	.addReg(FirstReg).addReg(SecondReg)
872	.addReg(Cond[1].getReg(), 0, SubIdx);
873	}
874
875	static unsigned getCRBitValue(unsigned CRBit) {
876	unsigned Ret = 4;
877	if (CRBit == PPC::CR0LT \|\| CRBit == PPC::CR1LT \|\|
878	CRBit == PPC::CR2LT \|\| CRBit == PPC::CR3LT \|\|
879	CRBit == PPC::CR4LT \|\| CRBit == PPC::CR5LT \|\|
880	CRBit == PPC::CR6LT \|\| CRBit == PPC::CR7LT)
881	Ret = 3;
882	if (CRBit == PPC::CR0GT \|\| CRBit == PPC::CR1GT \|\|
883	CRBit == PPC::CR2GT \|\| CRBit == PPC::CR3GT \|\|
884	CRBit == PPC::CR4GT \|\| CRBit == PPC::CR5GT \|\|
885	CRBit == PPC::CR6GT \|\| CRBit == PPC::CR7GT)
886	Ret = 2;
887	if (CRBit == PPC::CR0EQ \|\| CRBit == PPC::CR1EQ \|\|
888	CRBit == PPC::CR2EQ \|\| CRBit == PPC::CR3EQ \|\|
889	CRBit == PPC::CR4EQ \|\| CRBit == PPC::CR5EQ \|\|
890	CRBit == PPC::CR6EQ \|\| CRBit == PPC::CR7EQ)
891	Ret = 1;
892	if (CRBit == PPC::CR0UN \|\| CRBit == PPC::CR1UN \|\|
893	CRBit == PPC::CR2UN \|\| CRBit == PPC::CR3UN \|\|
894	CRBit == PPC::CR4UN \|\| CRBit == PPC::CR5UN \|\|
895	CRBit == PPC::CR6UN \|\| CRBit == PPC::CR7UN)
896	Ret = 0;
897
898	assert(Ret != 4 && "Invalid CR bit register")((Ret != 4 && "Invalid CR bit register") ? static_cast <void> (0) : __assert_fail ("Ret != 4 && \"Invalid CR bit register\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 898, __PRETTY_FUNCTION__));
899	return Ret;
900	}
901
902	void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
903	MachineBasicBlock::iterator I,
904	const DebugLoc &DL, unsigned DestReg,
905	unsigned SrcReg, bool KillSrc) const {
906	// We can end up with self copies and similar things as a result of VSX copy
907	// legalization. Promote them here.
908	const TargetRegisterInfo *TRI = &getRegisterInfo();
909	if (PPC::F8RCRegClass.contains(DestReg) &&
910	PPC::VSRCRegClass.contains(SrcReg)) {
911	unsigned SuperReg =
912	TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
913
914	if (VSXSelfCopyCrash && SrcReg == SuperReg)
915	llvm_unreachable("nop VSX copy")::llvm::llvm_unreachable_internal("nop VSX copy", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 915);
916
917	DestReg = SuperReg;
918	} else if (PPC::F8RCRegClass.contains(SrcReg) &&
919	PPC::VSRCRegClass.contains(DestReg)) {
920	unsigned SuperReg =
921	TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
922
923	if (VSXSelfCopyCrash && DestReg == SuperReg)
924	llvm_unreachable("nop VSX copy")::llvm::llvm_unreachable_internal("nop VSX copy", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 924);
925
926	SrcReg = SuperReg;
927	}
928
929	// Different class register copy
930	if (PPC::CRBITRCRegClass.contains(SrcReg) &&
931	PPC::GPRCRegClass.contains(DestReg)) {
932	unsigned CRReg = getCRFromCRBit(SrcReg);
933	BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
934	getKillRegState(KillSrc);
935	// Rotate the CR bit in the CR fields to be the least significant bit and
936	// then mask with 0x1 (MB = ME = 31).
937	BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
938	.addReg(DestReg, RegState::Kill)
939	.addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
940	.addImm(31)
941	.addImm(31);
942	return;
943	} else if (PPC::CRRCRegClass.contains(SrcReg) &&
944	PPC::G8RCRegClass.contains(DestReg)) {
945	BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
946	getKillRegState(KillSrc);
947	return;
948	} else if (PPC::CRRCRegClass.contains(SrcReg) &&
949	PPC::GPRCRegClass.contains(DestReg)) {
950	BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
951	getKillRegState(KillSrc);
952	return;
953	} else if (PPC::G8RCRegClass.contains(SrcReg) &&
954	PPC::VSFRCRegClass.contains(DestReg)) {
955	assert(Subtarget.hasDirectMove() &&((Subtarget.hasDirectMove() && "Subtarget doesn't support directmove, don't know how to copy." ) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasDirectMove() && \"Subtarget doesn't support directmove, don't know how to copy.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 956, __PRETTY_FUNCTION__))
956	"Subtarget doesn't support directmove, don't know how to copy.")((Subtarget.hasDirectMove() && "Subtarget doesn't support directmove, don't know how to copy." ) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasDirectMove() && \"Subtarget doesn't support directmove, don't know how to copy.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 956, __PRETTY_FUNCTION__));
957	BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
958	NumGPRtoVSRSpill++;
959	getKillRegState(KillSrc);
960	return;
961	} else if (PPC::VSFRCRegClass.contains(SrcReg) &&
962	PPC::G8RCRegClass.contains(DestReg)) {
963	assert(Subtarget.hasDirectMove() &&((Subtarget.hasDirectMove() && "Subtarget doesn't support directmove, don't know how to copy." ) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasDirectMove() && \"Subtarget doesn't support directmove, don't know how to copy.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 964, __PRETTY_FUNCTION__))
964	"Subtarget doesn't support directmove, don't know how to copy.")((Subtarget.hasDirectMove() && "Subtarget doesn't support directmove, don't know how to copy." ) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasDirectMove() && \"Subtarget doesn't support directmove, don't know how to copy.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 964, __PRETTY_FUNCTION__));
965	BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
966	getKillRegState(KillSrc);
967	return;
968	} else if (PPC::SPERCRegClass.contains(SrcReg) &&
969	PPC::SPE4RCRegClass.contains(DestReg)) {
970	BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
971	getKillRegState(KillSrc);
972	return;
973	} else if (PPC::SPE4RCRegClass.contains(SrcReg) &&
974	PPC::SPERCRegClass.contains(DestReg)) {
975	BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
976	getKillRegState(KillSrc);
977	return;
978	}
979
980	unsigned Opc;
981	if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
982	Opc = PPC::OR;
983	else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
984	Opc = PPC::OR8;
985	else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
986	Opc = PPC::FMR;
987	else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
988	Opc = PPC::MCRF;
989	else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
990	Opc = PPC::VOR;
991	else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
992	// There are two different ways this can be done:
993	// 1. xxlor : This has lower latency (on the P7), 2 cycles, but can only
994	// issue in VSU pipeline 0.
995	// 2. xmovdp/xmovsp: This has higher latency (on the P7), 6 cycles, but
996	// can go to either pipeline.
997	// We'll always use xxlor here, because in practically all cases where
998	// copies are generated, they are close enough to some use that the
999	// lower-latency form is preferable.
1000	Opc = PPC::XXLOR;
1001	else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) \|\|
1002	PPC::VSSRCRegClass.contains(DestReg, SrcReg))
1003	Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf;
1004	else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
1005	Opc = PPC::QVFMR;
1006	else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
1007	Opc = PPC::QVFMRs;
1008	else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
1009	Opc = PPC::QVFMRb;
1010	else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
1011	Opc = PPC::CROR;
1012	else if (PPC::SPERCRegClass.contains(DestReg, SrcReg))
1013	Opc = PPC::EVOR;
1014	else
1015	llvm_unreachable("Impossible reg-to-reg copy")::llvm::llvm_unreachable_internal("Impossible reg-to-reg copy" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1015);
1016
1017	const MCInstrDesc &MCID = get(Opc);
1018	if (MCID.getNumOperands() == 3)
1019	BuildMI(MBB, I, DL, MCID, DestReg)
1020	.addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1021	else
1022	BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1023	}
1024
1025	unsigned PPCInstrInfo::getStoreOpcodeForSpill(unsigned Reg,
1026	const TargetRegisterClass *RC)
1027	const {
1028	const unsigned *OpcodesForSpill = getStoreOpcodesForSpillArray();
1029	int OpcodeIndex = 0;
1030
1031	if (RC != nullptr) {
1032	if (PPC::GPRCRegClass.hasSubClassEq(RC) \|\|
1033	PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1034	OpcodeIndex = SOK_Int4Spill;
1035	} else if (PPC::G8RCRegClass.hasSubClassEq(RC) \|\|
1036	PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1037	OpcodeIndex = SOK_Int8Spill;
1038	} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1039	OpcodeIndex = SOK_Float8Spill;
1040	} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1041	OpcodeIndex = SOK_Float4Spill;
1042	} else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1043	OpcodeIndex = SOK_SPESpill;
1044	} else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1045	OpcodeIndex = SOK_SPE4Spill;
1046	} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1047	OpcodeIndex = SOK_CRSpill;
1048	} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1049	OpcodeIndex = SOK_CRBitSpill;
1050	} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1051	OpcodeIndex = SOK_VRVectorSpill;
1052	} else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1053	OpcodeIndex = SOK_VSXVectorSpill;
1054	} else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1055	OpcodeIndex = SOK_VectorFloat8Spill;
1056	} else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1057	OpcodeIndex = SOK_VectorFloat4Spill;
1058	} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1059	OpcodeIndex = SOK_VRSaveSpill;
1060	} else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1061	OpcodeIndex = SOK_QuadFloat8Spill;
1062	} else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1063	OpcodeIndex = SOK_QuadFloat4Spill;
1064	} else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1065	OpcodeIndex = SOK_QuadBitSpill;
1066	} else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1067	OpcodeIndex = SOK_SpillToVSR;
1068	} else {
1069	llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1069);
1070	}
1071	} else {
1072	if (PPC::GPRCRegClass.contains(Reg) \|\|
1073	PPC::GPRC_NOR0RegClass.contains(Reg)) {
1074	OpcodeIndex = SOK_Int4Spill;
1075	} else if (PPC::G8RCRegClass.contains(Reg) \|\|
1076	PPC::G8RC_NOX0RegClass.contains(Reg)) {
1077	OpcodeIndex = SOK_Int8Spill;
1078	} else if (PPC::F8RCRegClass.contains(Reg)) {
1079	OpcodeIndex = SOK_Float8Spill;
1080	} else if (PPC::F4RCRegClass.contains(Reg)) {
1081	OpcodeIndex = SOK_Float4Spill;
1082	} else if (PPC::SPERCRegClass.contains(Reg)) {
1083	OpcodeIndex = SOK_SPESpill;
1084	} else if (PPC::SPE4RCRegClass.contains(Reg)) {
1085	OpcodeIndex = SOK_SPE4Spill;
1086	} else if (PPC::CRRCRegClass.contains(Reg)) {
1087	OpcodeIndex = SOK_CRSpill;
1088	} else if (PPC::CRBITRCRegClass.contains(Reg)) {
1089	OpcodeIndex = SOK_CRBitSpill;
1090	} else if (PPC::VRRCRegClass.contains(Reg)) {
1091	OpcodeIndex = SOK_VRVectorSpill;
1092	} else if (PPC::VSRCRegClass.contains(Reg)) {
1093	OpcodeIndex = SOK_VSXVectorSpill;
1094	} else if (PPC::VSFRCRegClass.contains(Reg)) {
1095	OpcodeIndex = SOK_VectorFloat8Spill;
1096	} else if (PPC::VSSRCRegClass.contains(Reg)) {
1097	OpcodeIndex = SOK_VectorFloat4Spill;
1098	} else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1099	OpcodeIndex = SOK_VRSaveSpill;
1100	} else if (PPC::QFRCRegClass.contains(Reg)) {
1101	OpcodeIndex = SOK_QuadFloat8Spill;
1102	} else if (PPC::QSRCRegClass.contains(Reg)) {
1103	OpcodeIndex = SOK_QuadFloat4Spill;
1104	} else if (PPC::QBRCRegClass.contains(Reg)) {
1105	OpcodeIndex = SOK_QuadBitSpill;
1106	} else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1107	OpcodeIndex = SOK_SpillToVSR;
1108	} else {
1109	llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1109);
1110	}
1111	}
1112	return OpcodesForSpill[OpcodeIndex];
1113	}
1114
1115	unsigned
1116	PPCInstrInfo::getLoadOpcodeForSpill(unsigned Reg,
1117	const TargetRegisterClass *RC) const {
1118	const unsigned *OpcodesForSpill = getLoadOpcodesForSpillArray();
1119	int OpcodeIndex = 0;
1120
1121	if (RC != nullptr) {
1122	if (PPC::GPRCRegClass.hasSubClassEq(RC) \|\|
1123	PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) {
1124	OpcodeIndex = SOK_Int4Spill;
1125	} else if (PPC::G8RCRegClass.hasSubClassEq(RC) \|\|
1126	PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) {
1127	OpcodeIndex = SOK_Int8Spill;
1128	} else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
1129	OpcodeIndex = SOK_Float8Spill;
1130	} else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
1131	OpcodeIndex = SOK_Float4Spill;
1132	} else if (PPC::SPERCRegClass.hasSubClassEq(RC)) {
1133	OpcodeIndex = SOK_SPESpill;
1134	} else if (PPC::SPE4RCRegClass.hasSubClassEq(RC)) {
1135	OpcodeIndex = SOK_SPE4Spill;
1136	} else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
1137	OpcodeIndex = SOK_CRSpill;
1138	} else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
1139	OpcodeIndex = SOK_CRBitSpill;
1140	} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
1141	OpcodeIndex = SOK_VRVectorSpill;
1142	} else if (PPC::VSRCRegClass.hasSubClassEq(RC)) {
1143	OpcodeIndex = SOK_VSXVectorSpill;
1144	} else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) {
1145	OpcodeIndex = SOK_VectorFloat8Spill;
1146	} else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) {
1147	OpcodeIndex = SOK_VectorFloat4Spill;
1148	} else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) {
1149	OpcodeIndex = SOK_VRSaveSpill;
1150	} else if (PPC::QFRCRegClass.hasSubClassEq(RC)) {
1151	OpcodeIndex = SOK_QuadFloat8Spill;
1152	} else if (PPC::QSRCRegClass.hasSubClassEq(RC)) {
1153	OpcodeIndex = SOK_QuadFloat4Spill;
1154	} else if (PPC::QBRCRegClass.hasSubClassEq(RC)) {
1155	OpcodeIndex = SOK_QuadBitSpill;
1156	} else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) {
1157	OpcodeIndex = SOK_SpillToVSR;
1158	} else {
1159	llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1159);
1160	}
1161	} else {
1162	if (PPC::GPRCRegClass.contains(Reg) \|\|
1163	PPC::GPRC_NOR0RegClass.contains(Reg)) {
1164	OpcodeIndex = SOK_Int4Spill;
1165	} else if (PPC::G8RCRegClass.contains(Reg) \|\|
1166	PPC::G8RC_NOX0RegClass.contains(Reg)) {
1167	OpcodeIndex = SOK_Int8Spill;
1168	} else if (PPC::F8RCRegClass.contains(Reg)) {
1169	OpcodeIndex = SOK_Float8Spill;
1170	} else if (PPC::F4RCRegClass.contains(Reg)) {
1171	OpcodeIndex = SOK_Float4Spill;
1172	} else if (PPC::SPERCRegClass.contains(Reg)) {
1173	OpcodeIndex = SOK_SPESpill;
1174	} else if (PPC::SPE4RCRegClass.contains(Reg)) {
1175	OpcodeIndex = SOK_SPE4Spill;
1176	} else if (PPC::CRRCRegClass.contains(Reg)) {
1177	OpcodeIndex = SOK_CRSpill;
1178	} else if (PPC::CRBITRCRegClass.contains(Reg)) {
1179	OpcodeIndex = SOK_CRBitSpill;
1180	} else if (PPC::VRRCRegClass.contains(Reg)) {
1181	OpcodeIndex = SOK_VRVectorSpill;
1182	} else if (PPC::VSRCRegClass.contains(Reg)) {
1183	OpcodeIndex = SOK_VSXVectorSpill;
1184	} else if (PPC::VSFRCRegClass.contains(Reg)) {
1185	OpcodeIndex = SOK_VectorFloat8Spill;
1186	} else if (PPC::VSSRCRegClass.contains(Reg)) {
1187	OpcodeIndex = SOK_VectorFloat4Spill;
1188	} else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1189	OpcodeIndex = SOK_VRSaveSpill;
1190	} else if (PPC::QFRCRegClass.contains(Reg)) {
1191	OpcodeIndex = SOK_QuadFloat8Spill;
1192	} else if (PPC::QSRCRegClass.contains(Reg)) {
1193	OpcodeIndex = SOK_QuadFloat4Spill;
1194	} else if (PPC::QBRCRegClass.contains(Reg)) {
1195	OpcodeIndex = SOK_QuadBitSpill;
1196	} else if (PPC::SPILLTOVSRRCRegClass.contains(Reg)) {
1197	OpcodeIndex = SOK_SpillToVSR;
1198	} else {
1199	llvm_unreachable("Unknown regclass!")::llvm::llvm_unreachable_internal("Unknown regclass!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1199);
1200	}
1201	}
1202	return OpcodesForSpill[OpcodeIndex];
1203	}
1204
1205	void PPCInstrInfo::StoreRegToStackSlot(
1206	MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx,
1207	const TargetRegisterClass *RC,
1208	SmallVectorImpl<MachineInstr *> &NewMIs) const {
1209	unsigned Opcode = getStoreOpcodeForSpill(PPC::NoRegister, RC);
1210	DebugLoc DL;
1211
1212	PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1213	FuncInfo->setHasSpills();
1214
1215	NewMIs.push_back(addFrameReference(
1216	BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1217	FrameIdx));
1218
1219	if (PPC::CRRCRegClass.hasSubClassEq(RC) \|\|
1220	PPC::CRBITRCRegClass.hasSubClassEq(RC))
1221	FuncInfo->setSpillsCR();
1222
1223	if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1224	FuncInfo->setSpillsVRSAVE();
1225
1226	if (isXFormMemOp(Opcode))
1227	FuncInfo->setHasNonRISpills();
1228	}
1229
1230	void PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1231	MachineBasicBlock::iterator MI,
1232	unsigned SrcReg, bool isKill,
1233	int FrameIdx,
1234	const TargetRegisterClass *RC,
1235	const TargetRegisterInfo *TRI) const {
1236	MachineFunction &MF = *MBB.getParent();
1237	SmallVector<MachineInstr *, 4> NewMIs;
1238
1239	// We need to avoid a situation in which the value from a VRRC register is
1240	// spilled using an Altivec instruction and reloaded into a VSRC register
1241	// using a VSX instruction. The issue with this is that the VSX
1242	// load/store instructions swap the doublewords in the vector and the Altivec
1243	// ones don't. The register classes on the spill/reload may be different if
1244	// the register is defined using an Altivec instruction and is then used by a
1245	// VSX instruction.
1246	RC = updatedRC(RC);
1247
1248	StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs);
1249
1250	for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1251	MBB.insert(MI, NewMIs[i]);
1252
1253	const MachineFrameInfo &MFI = MF.getFrameInfo();
1254	MachineMemOperand *MMO = MF.getMachineMemOperand(
1255	MachinePointerInfo::getFixedStack(MF, FrameIdx),
1256	MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx),
1257	MFI.getObjectAlignment(FrameIdx));
1258	NewMIs.back()->addMemOperand(MF, MMO);
1259	}
1260
1261	void PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL,
1262	unsigned DestReg, int FrameIdx,
1263	const TargetRegisterClass *RC,
1264	SmallVectorImpl<MachineInstr *> &NewMIs)
1265	const {
1266	unsigned Opcode = getLoadOpcodeForSpill(PPC::NoRegister, RC);
1267	NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(Opcode), DestReg),
1268	FrameIdx));
1269	PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1270
1271	if (PPC::CRRCRegClass.hasSubClassEq(RC) \|\|
1272	PPC::CRBITRCRegClass.hasSubClassEq(RC))
1273	FuncInfo->setSpillsCR();
1274
1275	if (PPC::VRSAVERCRegClass.hasSubClassEq(RC))
1276	FuncInfo->setSpillsVRSAVE();
1277
1278	if (isXFormMemOp(Opcode))
1279	FuncInfo->setHasNonRISpills();
1280	}
1281
1282	void
1283	PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1284	MachineBasicBlock::iterator MI,
1285	unsigned DestReg, int FrameIdx,
1286	const TargetRegisterClass *RC,
1287	const TargetRegisterInfo *TRI) const {
1288	MachineFunction &MF = *MBB.getParent();
1289	SmallVector<MachineInstr*, 4> NewMIs;
1290	DebugLoc DL;
1291	if (MI != MBB.end()) DL = MI->getDebugLoc();
1292
1293	PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1294	FuncInfo->setHasSpills();
1295
1296	// We need to avoid a situation in which the value from a VRRC register is
1297	// spilled using an Altivec instruction and reloaded into a VSRC register
1298	// using a VSX instruction. The issue with this is that the VSX
1299	// load/store instructions swap the doublewords in the vector and the Altivec
1300	// ones don't. The register classes on the spill/reload may be different if
1301	// the register is defined using an Altivec instruction and is then used by a
1302	// VSX instruction.
1303	if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
1304	RC = &PPC::VSRCRegClass;
1305
1306	LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
1307
1308	for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
1309	MBB.insert(MI, NewMIs[i]);
1310
1311	const MachineFrameInfo &MFI = MF.getFrameInfo();
1312	MachineMemOperand *MMO = MF.getMachineMemOperand(
1313	MachinePointerInfo::getFixedStack(MF, FrameIdx),
1314	MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx),
1315	MFI.getObjectAlignment(FrameIdx));
1316	NewMIs.back()->addMemOperand(MF, MMO);
1317	}
1318
1319	bool PPCInstrInfo::
1320	reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1321	assert(Cond.size() == 2 && "Invalid PPC branch opcode!")((Cond.size() == 2 && "Invalid PPC branch opcode!") ? static_cast<void> (0) : __assert_fail ("Cond.size() == 2 && \"Invalid PPC branch opcode!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1321, __PRETTY_FUNCTION__));
1322	if (Cond[1].getReg() == PPC::CTR8 \|\| Cond[1].getReg() == PPC::CTR)
1323	Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
1324	else
1325	// Leave the CR# the same, but invert the condition.
1326	Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
1327	return false;
1328	}
1329
1330	bool PPCInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1331	unsigned Reg, MachineRegisterInfo *MRI) const {
1332	// For some instructions, it is legal to fold ZERO into the RA register field.
1333	// A zero immediate should always be loaded with a single li.
1334	unsigned DefOpc = DefMI.getOpcode();
1335	if (DefOpc != PPC::LI && DefOpc != PPC::LI8)
1336	return false;
1337	if (!DefMI.getOperand(1).isImm())
1338	return false;
1339	if (DefMI.getOperand(1).getImm() != 0)
1340	return false;
1341
1342	// Note that we cannot here invert the arguments of an isel in order to fold
1343	// a ZERO into what is presented as the second argument. All we have here
1344	// is the condition bit, and that might come from a CR-logical bit operation.
1345
1346	const MCInstrDesc &UseMCID = UseMI.getDesc();
1347
1348	// Only fold into real machine instructions.
1349	if (UseMCID.isPseudo())
1350	return false;
1351
1352	unsigned UseIdx;
1353	for (UseIdx = 0; UseIdx < UseMI.getNumOperands(); ++UseIdx)
1354	if (UseMI.getOperand(UseIdx).isReg() &&
1355	UseMI.getOperand(UseIdx).getReg() == Reg)
1356	break;
1357
1358	assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI")((UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI" ) ? static_cast<void> (0) : __assert_fail ("UseIdx < UseMI.getNumOperands() && \"Cannot find Reg in UseMI\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1358, __PRETTY_FUNCTION__));
1359	assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg")((UseIdx < UseMCID.getNumOperands() && "No operand description for Reg" ) ? static_cast<void> (0) : __assert_fail ("UseIdx < UseMCID.getNumOperands() && \"No operand description for Reg\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1359, __PRETTY_FUNCTION__));
1360
1361	const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx];
1362
1363	// We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0
1364	// register (which might also be specified as a pointer class kind).
1365	if (UseInfo->isLookupPtrRegClass()) {
1366	if (UseInfo->RegClass /* Kind */ != 1)
1367	return false;
1368	} else {
1369	if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID &&
1370	UseInfo->RegClass != PPC::G8RC_NOX0RegClassID)
1371	return false;
1372	}
1373
1374	// Make sure this is not tied to an output register (or otherwise
1375	// constrained). This is true for ST?UX registers, for example, which
1376	// are tied to their output registers.
1377	if (UseInfo->Constraints != 0)
1378	return false;
1379
1380	unsigned ZeroReg;
1381	if (UseInfo->isLookupPtrRegClass()) {
1382	bool isPPC64 = Subtarget.isPPC64();
1383	ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;
1384	} else {
1385	ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ?
1386	PPC::ZERO8 : PPC::ZERO;
1387	}
1388
1389	bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
1390	UseMI.getOperand(UseIdx).setReg(ZeroReg);
1391
1392	if (DeleteDef)
1393	DefMI.eraseFromParent();
1394
1395	return true;
1396	}
1397
1398	static bool MBBDefinesCTR(MachineBasicBlock &MBB) {
1399	for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
1400	I != IE; ++I)
1401	if (I->definesRegister(PPC::CTR) \|\| I->definesRegister(PPC::CTR8))
1402	return true;
1403	return false;
1404	}
1405
1406	// We should make sure that, if we're going to predicate both sides of a
1407	// condition (a diamond), that both sides don't define the counter register. We
1408	// can predicate counter-decrement-based branches, but while that predicates
1409	// the branching, it does not predicate the counter decrement. If we tried to
1410	// merge the triangle into one predicated block, we'd decrement the counter
1411	// twice.
1412	bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
1413	unsigned NumT, unsigned ExtraT,
1414	MachineBasicBlock &FMBB,
1415	unsigned NumF, unsigned ExtraF,
1416	BranchProbability Probability) const {
1417	return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB));
1418	}
1419
1420
1421	bool PPCInstrInfo::isPredicated(const MachineInstr &MI) const {
1422	// The predicated branches are identified by their type, not really by the
1423	// explicit presence of a predicate. Furthermore, some of them can be
1424	// predicated more than once. Because if conversion won't try to predicate
1425	// any instruction which already claims to be predicated (by returning true
1426	// here), always return false. In doing so, we let isPredicable() be the
1427	// final word on whether not the instruction can be (further) predicated.
1428
1429	return false;
1430	}
1431
1432	bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
1433	if (!MI.isTerminator())
1434	return false;
1435
1436	// Conditional branch is a special case.
1437	if (MI.isBranch() && !MI.isBarrier())
1438	return true;
1439
1440	return !isPredicated(MI);
1441	}
1442
1443	bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI,
1444	ArrayRef<MachineOperand> Pred) const {
1445	unsigned OpC = MI.getOpcode();
1446	if (OpC == PPC::BLR \|\| OpC == PPC::BLR8) {
1447	if (Pred[1].getReg() == PPC::CTR8 \|\| Pred[1].getReg() == PPC::CTR) {
1448	bool isPPC64 = Subtarget.isPPC64();
1449	MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)
1450	: (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
1451	} else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1452	MI.setDesc(get(PPC::BCLR));
1453	MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1454	} else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1455	MI.setDesc(get(PPC::BCLRn));
1456	MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1457	} else {
1458	MI.setDesc(get(PPC::BCCLR));
1459	MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1460	.addImm(Pred[0].getImm())
1461	.add(Pred[1]);
1462	}
1463
1464	return true;
1465	} else if (OpC == PPC::B) {
1466	if (Pred[1].getReg() == PPC::CTR8 \|\| Pred[1].getReg() == PPC::CTR) {
1467	bool isPPC64 = Subtarget.isPPC64();
1468	MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)
1469	: (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
1470	} else if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1471	MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1472	MI.RemoveOperand(0);
1473
1474	MI.setDesc(get(PPC::BC));
1475	MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1476	.add(Pred[1])
1477	.addMBB(MBB);
1478	} else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1479	MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1480	MI.RemoveOperand(0);
1481
1482	MI.setDesc(get(PPC::BCn));
1483	MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1484	.add(Pred[1])
1485	.addMBB(MBB);
1486	} else {
1487	MachineBasicBlock *MBB = MI.getOperand(0).getMBB();
1488	MI.RemoveOperand(0);
1489
1490	MI.setDesc(get(PPC::BCC));
1491	MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1492	.addImm(Pred[0].getImm())
1493	.add(Pred[1])
1494	.addMBB(MBB);
1495	}
1496
1497	return true;
1498	} else if (OpC == PPC::BCTR \|\| OpC == PPC::BCTR8 \|\| OpC == PPC::BCTRL \|\|
1499	OpC == PPC::BCTRL8) {
1500	if (Pred[1].getReg() == PPC::CTR8 \|\| Pred[1].getReg() == PPC::CTR)
1501	llvm_unreachable("Cannot predicate bctr[l] on the ctr register")::llvm::llvm_unreachable_internal("Cannot predicate bctr[l] on the ctr register" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1501);
1502
1503	bool setLR = OpC == PPC::BCTRL \|\| OpC == PPC::BCTRL8;
1504	bool isPPC64 = Subtarget.isPPC64();
1505
1506	if (Pred[0].getImm() == PPC::PRED_BIT_SET) {
1507	MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)
1508	: (setLR ? PPC::BCCTRL : PPC::BCCTR)));
1509	MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1510	return true;
1511	} else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) {
1512	MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)
1513	: (setLR ? PPC::BCCTRLn : PPC::BCCTRn)));
1514	MachineInstrBuilder(*MI.getParent()->getParent(), MI).add(Pred[1]);
1515	return true;
1516	}
1517
1518	MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)
1519	: (setLR ? PPC::BCCCTRL : PPC::BCCCTR)));
1520	MachineInstrBuilder(*MI.getParent()->getParent(), MI)
1521	.addImm(Pred[0].getImm())
1522	.add(Pred[1]);
1523	return true;
1524	}
1525
1526	return false;
1527	}
1528
1529	bool PPCInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1530	ArrayRef<MachineOperand> Pred2) const {
1531	assert(Pred1.size() == 2 && "Invalid PPC first predicate")((Pred1.size() == 2 && "Invalid PPC first predicate") ? static_cast<void> (0) : __assert_fail ("Pred1.size() == 2 && \"Invalid PPC first predicate\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1531, __PRETTY_FUNCTION__));
1532	assert(Pred2.size() == 2 && "Invalid PPC second predicate")((Pred2.size() == 2 && "Invalid PPC second predicate" ) ? static_cast<void> (0) : __assert_fail ("Pred2.size() == 2 && \"Invalid PPC second predicate\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1532, __PRETTY_FUNCTION__));
1533
1534	if (Pred1[1].getReg() == PPC::CTR8 \|\| Pred1[1].getReg() == PPC::CTR)
1535	return false;
1536	if (Pred2[1].getReg() == PPC::CTR8 \|\| Pred2[1].getReg() == PPC::CTR)
1537	return false;
1538
1539	// P1 can only subsume P2 if they test the same condition register.
1540	if (Pred1[1].getReg() != Pred2[1].getReg())
1541	return false;
1542
1543	PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
1544	PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
1545
1546	if (P1 == P2)
1547	return true;
1548
1549	// Does P1 subsume P2, e.g. GE subsumes GT.
1550	if (P1 == PPC::PRED_LE &&
1551	(P2 == PPC::PRED_LT \|\| P2 == PPC::PRED_EQ))
1552	return true;
1553	if (P1 == PPC::PRED_GE &&
1554	(P2 == PPC::PRED_GT \|\| P2 == PPC::PRED_EQ))
1555	return true;
1556
1557	return false;
1558	}
1559
1560	bool PPCInstrInfo::DefinesPredicate(MachineInstr &MI,
1561	std::vector<MachineOperand> &Pred) const {
1562	// Note: At the present time, the contents of Pred from this function is
1563	// unused by IfConversion. This implementation follows ARM by pushing the
1564	// CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
1565	// predicate, instructions defining CTR or CTR8 are also included as
1566	// predicate-defining instructions.
1567
1568	const TargetRegisterClass *RCs[] =
1569	{ &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
1570	&PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
1571
1572	bool Found = false;
1573	for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1574	const MachineOperand &MO = MI.getOperand(i);
1575	for (unsigned c = 0; c < array_lengthof(RCs) && !Found; ++c) {
1576	const TargetRegisterClass *RC = RCs[c];
1577	if (MO.isReg()) {
1578	if (MO.isDef() && RC->contains(MO.getReg())) {
1579	Pred.push_back(MO);
1580	Found = true;
1581	}
1582	} else if (MO.isRegMask()) {
1583	for (TargetRegisterClass::iterator I = RC->begin(),
1584	IE = RC->end(); I != IE; ++I)
1585	if (MO.clobbersPhysReg(*I)) {
1586	Pred.push_back(MO);
1587	Found = true;
1588	}
1589	}
1590	}
1591	}
1592
1593	return Found;
1594	}
1595
1596	bool PPCInstrInfo::isPredicable(const MachineInstr &MI) const {
1597	unsigned OpC = MI.getOpcode();
1598	switch (OpC) {
1599	default:
1600	return false;
1601	case PPC::B:
1602	case PPC::BLR:
1603	case PPC::BLR8:
1604	case PPC::BCTR:
1605	case PPC::BCTR8:
1606	case PPC::BCTRL:
1607	case PPC::BCTRL8:
1608	return true;
1609	}
1610	}
1611
1612	bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1613	unsigned &SrcReg2, int &Mask,
1614	int &Value) const {
1615	unsigned Opc = MI.getOpcode();
1616
1617	switch (Opc) {
1618	default: return false;
1619	case PPC::CMPWI:
1620	case PPC::CMPLWI:
1621	case PPC::CMPDI:
1622	case PPC::CMPLDI:
1623	SrcReg = MI.getOperand(1).getReg();
1624	SrcReg2 = 0;
1625	Value = MI.getOperand(2).getImm();
1626	Mask = 0xFFFF;
1627	return true;
1628	case PPC::CMPW:
1629	case PPC::CMPLW:
1630	case PPC::CMPD:
1631	case PPC::CMPLD:
1632	case PPC::FCMPUS:
1633	case PPC::FCMPUD:
1634	SrcReg = MI.getOperand(1).getReg();
1635	SrcReg2 = MI.getOperand(2).getReg();
1636	Value = 0;
1637	Mask = 0;
1638	return true;
1639	}
1640	}
1641
1642	bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1643	unsigned SrcReg2, int Mask, int Value,
1644	const MachineRegisterInfo *MRI) const {
1645	if (DisableCmpOpt)
1646	return false;
1647
1648	int OpC = CmpInstr.getOpcode();
1649	unsigned CRReg = CmpInstr.getOperand(0).getReg();
1650
1651	// FP record forms set CR1 based on the exception status bits, not a
1652	// comparison with zero.
1653	if (OpC == PPC::FCMPUS \|\| OpC == PPC::FCMPUD)
1654	return false;
1655
1656	const TargetRegisterInfo *TRI = &getRegisterInfo();
1657	// The record forms set the condition register based on a signed comparison
1658	// with zero (so says the ISA manual). This is not as straightforward as it
1659	// seems, however, because this is always a 64-bit comparison on PPC64, even
1660	// for instructions that are 32-bit in nature (like slw for example).
1661	// So, on PPC32, for unsigned comparisons, we can use the record forms only
1662	// for equality checks (as those don't depend on the sign). On PPC64,
1663	// we are restricted to equality for unsigned 64-bit comparisons and for
1664	// signed 32-bit comparisons the applicability is more restricted.
1665	bool isPPC64 = Subtarget.isPPC64();
1666	bool is32BitSignedCompare = OpC == PPC::CMPWI \|\| OpC == PPC::CMPW;
1667	bool is32BitUnsignedCompare = OpC == PPC::CMPLWI \|\| OpC == PPC::CMPLW;
1668	bool is64BitUnsignedCompare = OpC == PPC::CMPLDI \|\| OpC == PPC::CMPLD;
1669
1670	// Look through copies unless that gets us to a physical register.
1671	unsigned ActualSrc = TRI->lookThruCopyLike(SrcReg, MRI);
1672	if (TargetRegisterInfo::isVirtualRegister(ActualSrc))
1673	SrcReg = ActualSrc;
1674
1675	// Get the unique definition of SrcReg.
1676	MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1677	if (!MI) return false;
1678
1679	bool equalityOnly = false;
1680	bool noSub = false;
1681	if (isPPC64) {
1682	if (is32BitSignedCompare) {
1683	// We can perform this optimization only if MI is sign-extending.
1684	if (isSignExtended(*MI))
1685	noSub = true;
1686	else
1687	return false;
1688	} else if (is32BitUnsignedCompare) {
1689	// We can perform this optimization, equality only, if MI is
1690	// zero-extending.
1691	if (isZeroExtended(*MI)) {
1692	noSub = true;
1693	equalityOnly = true;
1694	} else
1695	return false;
1696	} else
1697	equalityOnly = is64BitUnsignedCompare;
1698	} else
1699	equalityOnly = is32BitUnsignedCompare;
1700
1701	if (equalityOnly) {
1702	// We need to check the uses of the condition register in order to reject
1703	// non-equality comparisons.
1704	for (MachineRegisterInfo::use_instr_iterator
1705	I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1706	I != IE; ++I) {
1707	MachineInstr UseMI = &I;
1708	if (UseMI->getOpcode() == PPC::BCC) {
1709	PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1710	unsigned PredCond = PPC::getPredicateCondition(Pred);
1711	// We ignore hint bits when checking for non-equality comparisons.
1712	if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE)
1713	return false;
1714	} else if (UseMI->getOpcode() == PPC::ISEL \|\|
1715	UseMI->getOpcode() == PPC::ISEL8) {
1716	unsigned SubIdx = UseMI->getOperand(3).getSubReg();
1717	if (SubIdx != PPC::sub_eq)
1718	return false;
1719	} else
1720	return false;
1721	}
1722	}
1723
1724	MachineBasicBlock::iterator I = CmpInstr;
1725
1726	// Scan forward to find the first use of the compare.
1727	for (MachineBasicBlock::iterator EL = CmpInstr.getParent()->end(); I != EL;
1728	++I) {
1729	bool FoundUse = false;
1730	for (MachineRegisterInfo::use_instr_iterator
1731	J = MRI->use_instr_begin(CRReg), JE = MRI->use_instr_end();
1732	J != JE; ++J)
1733	if (&J == &I) {
1734	FoundUse = true;
1735	break;
1736	}
1737
1738	if (FoundUse)
1739	break;
1740	}
1741
1742	SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;
1743	SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;
1744
1745	// There are two possible candidates which can be changed to set CR[01].
1746	// One is MI, the other is a SUB instruction.
1747	// For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
1748	MachineInstr *Sub = nullptr;
1749	if (SrcReg2 != 0)
1750	// MI is not a candidate for CMPrr.
1751	MI = nullptr;
1752	// FIXME: Conservatively refuse to convert an instruction which isn't in the
1753	// same BB as the comparison. This is to allow the check below to avoid calls
1754	// (and other explicit clobbers); instead we should really check for these
1755	// more explicitly (in at least a few predecessors).
1756	else if (MI->getParent() != CmpInstr.getParent())
1757	return false;
1758	else if (Value != 0) {
1759	// The record-form instructions set CR bit based on signed comparison
1760	// against 0. We try to convert a compare against 1 or -1 into a compare
1761	// against 0 to exploit record-form instructions. For example, we change
1762	// the condition "greater than -1" into "greater than or equal to 0"
1763	// and "less than 1" into "less than or equal to 0".
1764
1765	// Since we optimize comparison based on a specific branch condition,
1766	// we don't optimize if condition code is used by more than once.
1767	if (equalityOnly \|\| !MRI->hasOneUse(CRReg))
1768	return false;
1769
1770	MachineInstr UseMI = &MRI->use_instr_begin(CRReg);
1771	if (UseMI->getOpcode() != PPC::BCC)
1772	return false;
1773
1774	PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();
1775	PPC::Predicate NewPred = Pred;
	Value stored to 'NewPred' during its initialization is never read
1776	unsigned PredCond = PPC::getPredicateCondition(Pred);
1777	unsigned PredHint = PPC::getPredicateHint(Pred);
1778	int16_t Immed = (int16_t)Value;
1779
1780	// When modifying the condition in the predicate, we propagate hint bits
1781	// from the original predicate to the new one.
1782	if (Immed == -1 && PredCond == PPC::PRED_GT)
1783	// We convert "greater than -1" into "greater than or equal to 0",
1784	// since we are assuming signed comparison by !equalityOnly
1785	NewPred = PPC::getPredicate(PPC::PRED_GE, PredHint);
1786	else if (Immed == -1 && PredCond == PPC::PRED_LE)
1787	// We convert "less than or equal to -1" into "less than 0".
1788	NewPred = PPC::getPredicate(PPC::PRED_LT, PredHint);
1789	else if (Immed == 1 && PredCond == PPC::PRED_LT)
1790	// We convert "less than 1" into "less than or equal to 0".
1791	NewPred = PPC::getPredicate(PPC::PRED_LE, PredHint);
1792	else if (Immed == 1 && PredCond == PPC::PRED_GE)
1793	// We convert "greater than or equal to 1" into "greater than 0".
1794	NewPred = PPC::getPredicate(PPC::PRED_GT, PredHint);
1795	else
1796	return false;
1797
1798	PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1799	NewPred));
1800	}
1801
1802	// Search for Sub.
1803	--I;
1804
1805	// Get ready to iterate backward from CmpInstr.
1806	MachineBasicBlock::iterator E = MI, B = CmpInstr.getParent()->begin();
1807
1808	for (; I != E && !noSub; --I) {
1809	const MachineInstr &Instr = *I;
1810	unsigned IOpC = Instr.getOpcode();
1811
1812	if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) \|\|
1813	Instr.readsRegister(PPC::CR0, TRI)))
1814	// This instruction modifies or uses the record condition register after
1815	// the one we want to change. While we could do this transformation, it
1816	// would likely not be profitable. This transformation removes one
1817	// instruction, and so even forcing RA to generate one move probably
1818	// makes it unprofitable.
1819	return false;
1820
1821	// Check whether CmpInstr can be made redundant by the current instruction.
1822	if ((OpC == PPC::CMPW \|\| OpC == PPC::CMPLW \|\|
1823	OpC == PPC::CMPD \|\| OpC == PPC::CMPLD) &&
1824	(IOpC == PPC::SUBF \|\| IOpC == PPC::SUBF8) &&
1825	((Instr.getOperand(1).getReg() == SrcReg &&
1826	Instr.getOperand(2).getReg() == SrcReg2) \|\|
1827	(Instr.getOperand(1).getReg() == SrcReg2 &&
1828	Instr.getOperand(2).getReg() == SrcReg))) {
1829	Sub = &*I;
1830	break;
1831	}
1832
1833	if (I == B)
1834	// The 'and' is below the comparison instruction.
1835	return false;
1836	}
1837
1838	// Return false if no candidates exist.
1839	if (!MI && !Sub)
1840	return false;
1841
1842	// The single candidate is called MI.
1843	if (!MI) MI = Sub;
1844
1845	int NewOpC = -1;
1846	int MIOpC = MI->getOpcode();
1847	if (MIOpC == PPC::ANDIo \|\| MIOpC == PPC::ANDIo8 \|\|
1848	MIOpC == PPC::ANDISo \|\| MIOpC == PPC::ANDISo8)
1849	NewOpC = MIOpC;
1850	else {
1851	NewOpC = PPC::getRecordFormOpcode(MIOpC);
1852	if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
1853	NewOpC = MIOpC;
1854	}
1855
1856	// FIXME: On the non-embedded POWER architectures, only some of the record
1857	// forms are fast, and we should use only the fast ones.
1858
1859	// The defining instruction has a record form (or is already a record
1860	// form). It is possible, however, that we'll need to reverse the condition
1861	// code of the users.
1862	if (NewOpC == -1)
1863	return false;
1864
1865	// If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
1866	// needs to be updated to be based on SUB. Push the condition code
1867	// operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
1868	// condition code of these operands will be modified.
1869	// Here, Value == 0 means we haven't converted comparison against 1 or -1 to
1870	// comparison against 0, which may modify predicate.
1871	bool ShouldSwap = false;
1872	if (Sub && Value == 0) {
1873	ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1874	Sub->getOperand(2).getReg() == SrcReg;
1875
1876	// The operands to subf are the opposite of sub, so only in the fixed-point
1877	// case, invert the order.
1878	ShouldSwap = !ShouldSwap;
1879	}
1880
1881	if (ShouldSwap)
1882	for (MachineRegisterInfo::use_instr_iterator
1883	I = MRI->use_instr_begin(CRReg), IE = MRI->use_instr_end();
1884	I != IE; ++I) {
1885	MachineInstr UseMI = &I;
1886	if (UseMI->getOpcode() == PPC::BCC) {
1887	PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
1888	unsigned PredCond = PPC::getPredicateCondition(Pred);
1889	assert((!equalityOnly \|\|(((!equalityOnly \|\| PredCond == PPC::PRED_EQ \|\| PredCond == PPC ::PRED_NE) && "Invalid predicate for equality-only optimization" ) ? static_cast<void> (0) : __assert_fail ("(!equalityOnly \|\| PredCond == PPC::PRED_EQ \|\| PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1891, __PRETTY_FUNCTION__))
1890	PredCond == PPC::PRED_EQ \|\| PredCond == PPC::PRED_NE) &&(((!equalityOnly \|\| PredCond == PPC::PRED_EQ \|\| PredCond == PPC ::PRED_NE) && "Invalid predicate for equality-only optimization" ) ? static_cast<void> (0) : __assert_fail ("(!equalityOnly \|\| PredCond == PPC::PRED_EQ \|\| PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1891, __PRETTY_FUNCTION__))
1891	"Invalid predicate for equality-only optimization")(((!equalityOnly \|\| PredCond == PPC::PRED_EQ \|\| PredCond == PPC ::PRED_NE) && "Invalid predicate for equality-only optimization" ) ? static_cast<void> (0) : __assert_fail ("(!equalityOnly \|\| PredCond == PPC::PRED_EQ \|\| PredCond == PPC::PRED_NE) && \"Invalid predicate for equality-only optimization\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1891, __PRETTY_FUNCTION__));
1892	(void)PredCond; // To suppress warning in release build.
1893	PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),
1894	PPC::getSwappedPredicate(Pred)));
1895	} else if (UseMI->getOpcode() == PPC::ISEL \|\|
1896	UseMI->getOpcode() == PPC::ISEL8) {
1897	unsigned NewSubReg = UseMI->getOperand(3).getSubReg();
1898	assert((!equalityOnly \|\| NewSubReg == PPC::sub_eq) &&(((!equalityOnly \|\| NewSubReg == PPC::sub_eq) && "Invalid CR bit for equality-only optimization" ) ? static_cast<void> (0) : __assert_fail ("(!equalityOnly \|\| NewSubReg == PPC::sub_eq) && \"Invalid CR bit for equality-only optimization\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1899, __PRETTY_FUNCTION__))
1899	"Invalid CR bit for equality-only optimization")(((!equalityOnly \|\| NewSubReg == PPC::sub_eq) && "Invalid CR bit for equality-only optimization" ) ? static_cast<void> (0) : __assert_fail ("(!equalityOnly \|\| NewSubReg == PPC::sub_eq) && \"Invalid CR bit for equality-only optimization\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1899, __PRETTY_FUNCTION__));
1900
1901	if (NewSubReg == PPC::sub_lt)
1902	NewSubReg = PPC::sub_gt;
1903	else if (NewSubReg == PPC::sub_gt)
1904	NewSubReg = PPC::sub_lt;
1905
1906	SubRegsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(3)),
1907	NewSubReg));
1908	} else // We need to abort on a user we don't understand.
1909	return false;
1910	}
1911	assert(!(Value != 0 && ShouldSwap) &&((!(Value != 0 && ShouldSwap) && "Non-zero immediate support and ShouldSwap" "may conflict in updating predicate") ? static_cast<void> (0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1913, __PRETTY_FUNCTION__))
1912	"Non-zero immediate support and ShouldSwap"((!(Value != 0 && ShouldSwap) && "Non-zero immediate support and ShouldSwap" "may conflict in updating predicate") ? static_cast<void> (0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1913, __PRETTY_FUNCTION__))
1913	"may conflict in updating predicate")((!(Value != 0 && ShouldSwap) && "Non-zero immediate support and ShouldSwap" "may conflict in updating predicate") ? static_cast<void> (0) : __assert_fail ("!(Value != 0 && ShouldSwap) && \"Non-zero immediate support and ShouldSwap\" \"may conflict in updating predicate\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 1913, __PRETTY_FUNCTION__));
1914
1915	// Create a new virtual register to hold the value of the CR set by the
1916	// record-form instruction. If the instruction was not previously in
1917	// record form, then set the kill flag on the CR.
1918	CmpInstr.eraseFromParent();
1919
1920	MachineBasicBlock::iterator MII = MI;
1921	BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
1922	get(TargetOpcode::COPY), CRReg)
1923	.addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
1924
1925	// Even if CR0 register were dead before, it is alive now since the
1926	// instruction we just built uses it.
1927	MI->clearRegisterDeads(PPC::CR0);
1928
1929	if (MIOpC != NewOpC) {
1930	// We need to be careful here: we're replacing one instruction with
1931	// another, and we need to make sure that we get all of the right
1932	// implicit uses and defs. On the other hand, the caller may be holding
1933	// an iterator to this instruction, and so we can't delete it (this is
1934	// specifically the case if this is the instruction directly after the
1935	// compare).
1936
1937	// Rotates are expensive instructions. If we're emitting a record-form
1938	// rotate that can just be an andi/andis, we should just emit that.
1939	if (MIOpC == PPC::RLWINM \|\| MIOpC == PPC::RLWINM8) {
1940	unsigned GPRRes = MI->getOperand(0).getReg();
1941	int64_t SH = MI->getOperand(2).getImm();
1942	int64_t MB = MI->getOperand(3).getImm();
1943	int64_t ME = MI->getOperand(4).getImm();
1944	// We can only do this if both the start and end of the mask are in the
1945	// same halfword.
1946	bool MBInLoHWord = MB >= 16;
1947	bool MEInLoHWord = ME >= 16;
1948	uint64_t Mask = ~0LLU;
1949
1950	if (MB <= ME && MBInLoHWord == MEInLoHWord && SH == 0) {
1951	Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
1952	// The mask value needs to shift right 16 if we're emitting andis.
1953	Mask >>= MBInLoHWord ? 0 : 16;
1954	NewOpC = MIOpC == PPC::RLWINM ?
1955	(MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) :
1956	(MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8);
1957	} else if (MRI->use_empty(GPRRes) && (ME == 31) &&
1958	(ME - MB + 1 == SH) && (MB >= 16)) {
1959	// If we are rotating by the exact number of bits as are in the mask
1960	// and the mask is in the least significant bits of the register,
1961	// that's just an andis. (as long as the GPR result has no uses).
1962	Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1);
1963	Mask >>= 16;
1964	NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8;
1965	}
1966	// If we've set the mask, we can transform.
1967	if (Mask != ~0LLU) {
1968	MI->RemoveOperand(4);
1969	MI->RemoveOperand(3);
1970	MI->getOperand(2).setImm(Mask);
1971	NumRcRotatesConvertedToRcAnd++;
1972	}
1973	} else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) {
1974	int64_t MB = MI->getOperand(3).getImm();
1975	if (MB >= 48) {
1976	uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
1977	NewOpC = PPC::ANDIo8;
1978	MI->RemoveOperand(3);
1979	MI->getOperand(2).setImm(Mask);
1980	NumRcRotatesConvertedToRcAnd++;
1981	}
1982	}
1983
1984	const MCInstrDesc &NewDesc = get(NewOpC);
1985	MI->setDesc(NewDesc);
1986
1987	if (NewDesc.ImplicitDefs)
1988	for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs();
1989	*ImpDefs; ++ImpDefs)
1990	if (!MI->definesRegister(*ImpDefs))
1991	MI->addOperand(*MI->getParent()->getParent(),
1992	MachineOperand::CreateReg(*ImpDefs, true, true));
1993	if (NewDesc.ImplicitUses)
1994	for (const MCPhysReg *ImpUses = NewDesc.getImplicitUses();
1995	*ImpUses; ++ImpUses)
1996	if (!MI->readsRegister(*ImpUses))
1997	MI->addOperand(*MI->getParent()->getParent(),
1998	MachineOperand::CreateReg(*ImpUses, false, true));
1999	}
2000	assert(MI->definesRegister(PPC::CR0) &&((MI->definesRegister(PPC::CR0) && "Record-form instruction does not define cr0?" ) ? static_cast<void> (0) : __assert_fail ("MI->definesRegister(PPC::CR0) && \"Record-form instruction does not define cr0?\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2001, __PRETTY_FUNCTION__))
2001	"Record-form instruction does not define cr0?")((MI->definesRegister(PPC::CR0) && "Record-form instruction does not define cr0?" ) ? static_cast<void> (0) : __assert_fail ("MI->definesRegister(PPC::CR0) && \"Record-form instruction does not define cr0?\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2001, __PRETTY_FUNCTION__));
2002
2003	// Modify the condition code of operands in OperandsToUpdate.
2004	// Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2005	// be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2006	for (unsigned i = 0, e = PredsToUpdate.size(); i < e; i++)
2007	PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
2008
2009	for (unsigned i = 0, e = SubRegsToUpdate.size(); i < e; i++)
2010	SubRegsToUpdate[i].first->setSubReg(SubRegsToUpdate[i].second);
2011
2012	return true;
2013	}
2014
2015	/// GetInstSize - Return the number of bytes of code the specified
2016	/// instruction may be. This returns the maximum number of bytes.
2017	///
2018	unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
2019	unsigned Opcode = MI.getOpcode();
2020
2021	if (Opcode == PPC::INLINEASM \|\| Opcode == PPC::INLINEASM_BR) {
2022	const MachineFunction *MF = MI.getParent()->getParent();
2023	const char *AsmStr = MI.getOperand(0).getSymbolName();
2024	return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
2025	} else if (Opcode == TargetOpcode::STACKMAP) {
2026	StackMapOpers Opers(&MI);
2027	return Opers.getNumPatchBytes();
2028	} else if (Opcode == TargetOpcode::PATCHPOINT) {
2029	PatchPointOpers Opers(&MI);
2030	return Opers.getNumPatchBytes();
2031	} else {
2032	return get(Opcode).getSize();
2033	}
2034	}
2035
2036	std::pair<unsigned, unsigned>
2037	PPCInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
2038	const unsigned Mask = PPCII::MO_ACCESS_MASK;
2039	return std::make_pair(TF & Mask, TF & ~Mask);
2040	}
2041
2042	ArrayRef<std::pair<unsigned, const char *>>
2043	PPCInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
2044	using namespace PPCII;
2045	static const std::pair<unsigned, const char *> TargetFlags[] = {
2046	{MO_LO, "ppc-lo"},
2047	{MO_HA, "ppc-ha"},
2048	{MO_TPREL_LO, "ppc-tprel-lo"},
2049	{MO_TPREL_HA, "ppc-tprel-ha"},
2050	{MO_DTPREL_LO, "ppc-dtprel-lo"},
2051	{MO_TLSLD_LO, "ppc-tlsld-lo"},
2052	{MO_TOC_LO, "ppc-toc-lo"},
2053	{MO_TLS, "ppc-tls"}};
2054	return makeArrayRef(TargetFlags);
2055	}
2056
2057	ArrayRef<std::pair<unsigned, const char *>>
2058	PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2059	using namespace PPCII;
2060	static const std::pair<unsigned, const char *> TargetFlags[] = {
2061	{MO_PLT, "ppc-plt"},
2062	{MO_PIC_FLAG, "ppc-pic"},
2063	{MO_NLP_FLAG, "ppc-nlp"},
2064	{MO_NLP_HIDDEN_FLAG, "ppc-nlp-hidden"}};
2065	return makeArrayRef(TargetFlags);
2066	}
2067
2068	// Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction.
2069	// The VSX versions have the advantage of a full 64-register target whereas
2070	// the FP ones have the advantage of lower latency and higher throughput. So
2071	// what we are after is using the faster instructions in low register pressure
2072	// situations and using the larger register file in high register pressure
2073	// situations.
2074	bool PPCInstrInfo::expandVSXMemPseudo(MachineInstr &MI) const {
2075	unsigned UpperOpcode, LowerOpcode;
2076	switch (MI.getOpcode()) {
2077	case PPC::DFLOADf32:
2078	UpperOpcode = PPC::LXSSP;
2079	LowerOpcode = PPC::LFS;
2080	break;
2081	case PPC::DFLOADf64:
2082	UpperOpcode = PPC::LXSD;
2083	LowerOpcode = PPC::LFD;
2084	break;
2085	case PPC::DFSTOREf32:
2086	UpperOpcode = PPC::STXSSP;
2087	LowerOpcode = PPC::STFS;
2088	break;
2089	case PPC::DFSTOREf64:
2090	UpperOpcode = PPC::STXSD;
2091	LowerOpcode = PPC::STFD;
2092	break;
2093	case PPC::XFLOADf32:
2094	UpperOpcode = PPC::LXSSPX;
2095	LowerOpcode = PPC::LFSX;
2096	break;
2097	case PPC::XFLOADf64:
2098	UpperOpcode = PPC::LXSDX;
2099	LowerOpcode = PPC::LFDX;
2100	break;
2101	case PPC::XFSTOREf32:
2102	UpperOpcode = PPC::STXSSPX;
2103	LowerOpcode = PPC::STFSX;
2104	break;
2105	case PPC::XFSTOREf64:
2106	UpperOpcode = PPC::STXSDX;
2107	LowerOpcode = PPC::STFDX;
2108	break;
2109	case PPC::LIWAX:
2110	UpperOpcode = PPC::LXSIWAX;
2111	LowerOpcode = PPC::LFIWAX;
2112	break;
2113	case PPC::LIWZX:
2114	UpperOpcode = PPC::LXSIWZX;
2115	LowerOpcode = PPC::LFIWZX;
2116	break;
2117	case PPC::STIWX:
2118	UpperOpcode = PPC::STXSIWX;
2119	LowerOpcode = PPC::STFIWX;
2120	break;
2121	default:
2122	llvm_unreachable("Unknown Operation!")::llvm::llvm_unreachable_internal("Unknown Operation!", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2122);
2123	}
2124
2125	unsigned TargetReg = MI.getOperand(0).getReg();
2126	unsigned Opcode;
2127	if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) \|\|
2128	(TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31))
2129	Opcode = LowerOpcode;
2130	else
2131	Opcode = UpperOpcode;
2132	MI.setDesc(get(Opcode));
2133	return true;
2134	}
2135
2136	static bool isAnImmediateOperand(const MachineOperand &MO) {
2137	return MO.isCPI() \|\| MO.isGlobal() \|\| MO.isImm();
2138	}
2139
2140	bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
2141	auto &MBB = *MI.getParent();
2142	auto DL = MI.getDebugLoc();
2143
2144	switch (MI.getOpcode()) {
2145	case TargetOpcode::LOAD_STACK_GUARD: {
2146	assert(Subtarget.isTargetLinux() &&((Subtarget.isTargetLinux() && "Only Linux target is expected to contain LOAD_STACK_GUARD" ) ? static_cast<void> (0) : __assert_fail ("Subtarget.isTargetLinux() && \"Only Linux target is expected to contain LOAD_STACK_GUARD\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2147, __PRETTY_FUNCTION__))
2147	"Only Linux target is expected to contain LOAD_STACK_GUARD")((Subtarget.isTargetLinux() && "Only Linux target is expected to contain LOAD_STACK_GUARD" ) ? static_cast<void> (0) : __assert_fail ("Subtarget.isTargetLinux() && \"Only Linux target is expected to contain LOAD_STACK_GUARD\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2147, __PRETTY_FUNCTION__));
2148	const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;
2149	const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;
2150	MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));
2151	MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2152	.addImm(Offset)
2153	.addReg(Reg);
2154	return true;
2155	}
2156	case PPC::DFLOADf32:
2157	case PPC::DFLOADf64:
2158	case PPC::DFSTOREf32:
2159	case PPC::DFSTOREf64: {
2160	assert(Subtarget.hasP9Vector() &&((Subtarget.hasP9Vector() && "Invalid D-Form Pseudo-ops on Pre-P9 target." ) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasP9Vector() && \"Invalid D-Form Pseudo-ops on Pre-P9 target.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2161, __PRETTY_FUNCTION__))
2161	"Invalid D-Form Pseudo-ops on Pre-P9 target.")((Subtarget.hasP9Vector() && "Invalid D-Form Pseudo-ops on Pre-P9 target." ) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasP9Vector() && \"Invalid D-Form Pseudo-ops on Pre-P9 target.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2161, __PRETTY_FUNCTION__));
2162	assert(MI.getOperand(2).isReg() &&((MI.getOperand(2).isReg() && isAnImmediateOperand(MI .getOperand(1)) && "D-form op must have register and immediate operands" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && isAnImmediateOperand(MI.getOperand(1)) && \"D-form op must have register and immediate operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2164, __PRETTY_FUNCTION__))
2163	isAnImmediateOperand(MI.getOperand(1)) &&((MI.getOperand(2).isReg() && isAnImmediateOperand(MI .getOperand(1)) && "D-form op must have register and immediate operands" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && isAnImmediateOperand(MI.getOperand(1)) && \"D-form op must have register and immediate operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2164, __PRETTY_FUNCTION__))
2164	"D-form op must have register and immediate operands")((MI.getOperand(2).isReg() && isAnImmediateOperand(MI .getOperand(1)) && "D-form op must have register and immediate operands" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && isAnImmediateOperand(MI.getOperand(1)) && \"D-form op must have register and immediate operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2164, __PRETTY_FUNCTION__));
2165	return expandVSXMemPseudo(MI);
2166	}
2167	case PPC::XFLOADf32:
2168	case PPC::XFSTOREf32:
2169	case PPC::LIWAX:
2170	case PPC::LIWZX:
2171	case PPC::STIWX: {
2172	assert(Subtarget.hasP8Vector() &&((Subtarget.hasP8Vector() && "Invalid X-Form Pseudo-ops on Pre-P8 target." ) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasP8Vector() && \"Invalid X-Form Pseudo-ops on Pre-P8 target.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2173, __PRETTY_FUNCTION__))
2173	"Invalid X-Form Pseudo-ops on Pre-P8 target.")((Subtarget.hasP8Vector() && "Invalid X-Form Pseudo-ops on Pre-P8 target." ) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasP8Vector() && \"Invalid X-Form Pseudo-ops on Pre-P8 target.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2173, __PRETTY_FUNCTION__));
2174	assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&((MI.getOperand(2).isReg() && MI.getOperand(1).isReg( ) && "X-form op must have register and register operands" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2175, __PRETTY_FUNCTION__))
2175	"X-form op must have register and register operands")((MI.getOperand(2).isReg() && MI.getOperand(1).isReg( ) && "X-form op must have register and register operands" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2175, __PRETTY_FUNCTION__));
2176	return expandVSXMemPseudo(MI);
2177	}
2178	case PPC::XFLOADf64:
2179	case PPC::XFSTOREf64: {
2180	assert(Subtarget.hasVSX() &&((Subtarget.hasVSX() && "Invalid X-Form Pseudo-ops on target that has no VSX." ) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasVSX() && \"Invalid X-Form Pseudo-ops on target that has no VSX.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2181, __PRETTY_FUNCTION__))
2181	"Invalid X-Form Pseudo-ops on target that has no VSX.")((Subtarget.hasVSX() && "Invalid X-Form Pseudo-ops on target that has no VSX." ) ? static_cast<void> (0) : __assert_fail ("Subtarget.hasVSX() && \"Invalid X-Form Pseudo-ops on target that has no VSX.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2181, __PRETTY_FUNCTION__));
2182	assert(MI.getOperand(2).isReg() && MI.getOperand(1).isReg() &&((MI.getOperand(2).isReg() && MI.getOperand(1).isReg( ) && "X-form op must have register and register operands" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2183, __PRETTY_FUNCTION__))
2183	"X-form op must have register and register operands")((MI.getOperand(2).isReg() && MI.getOperand(1).isReg( ) && "X-form op must have register and register operands" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(2).isReg() && MI.getOperand(1).isReg() && \"X-form op must have register and register operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2183, __PRETTY_FUNCTION__));
2184	return expandVSXMemPseudo(MI);
2185	}
2186	case PPC::SPILLTOVSR_LD: {
2187	unsigned TargetReg = MI.getOperand(0).getReg();
2188	if (PPC::VSFRCRegClass.contains(TargetReg)) {
2189	MI.setDesc(get(PPC::DFLOADf64));
2190	return expandPostRAPseudo(MI);
2191	}
2192	else
2193	MI.setDesc(get(PPC::LD));
2194	return true;
2195	}
2196	case PPC::SPILLTOVSR_ST: {
2197	unsigned SrcReg = MI.getOperand(0).getReg();
2198	if (PPC::VSFRCRegClass.contains(SrcReg)) {
2199	NumStoreSPILLVSRRCAsVec++;
2200	MI.setDesc(get(PPC::DFSTOREf64));
2201	return expandPostRAPseudo(MI);
2202	} else {
2203	NumStoreSPILLVSRRCAsGpr++;
2204	MI.setDesc(get(PPC::STD));
2205	}
2206	return true;
2207	}
2208	case PPC::SPILLTOVSR_LDX: {
2209	unsigned TargetReg = MI.getOperand(0).getReg();
2210	if (PPC::VSFRCRegClass.contains(TargetReg))
2211	MI.setDesc(get(PPC::LXSDX));
2212	else
2213	MI.setDesc(get(PPC::LDX));
2214	return true;
2215	}
2216	case PPC::SPILLTOVSR_STX: {
2217	unsigned SrcReg = MI.getOperand(0).getReg();
2218	if (PPC::VSFRCRegClass.contains(SrcReg)) {
2219	NumStoreSPILLVSRRCAsVec++;
2220	MI.setDesc(get(PPC::STXSDX));
2221	} else {
2222	NumStoreSPILLVSRRCAsGpr++;
2223	MI.setDesc(get(PPC::STDX));
2224	}
2225	return true;
2226	}
2227
2228	case PPC::CFENCE8: {
2229	auto Val = MI.getOperand(0).getReg();
2230	BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2231	BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP))
2232	.addImm(PPC::PRED_NE_MINUS)
2233	.addReg(PPC::CR7)
2234	.addImm(1);
2235	MI.setDesc(get(PPC::ISYNC));
2236	MI.RemoveOperand(0);
2237	return true;
2238	}
2239	}
2240	return false;
2241	}
2242
2243	// Essentially a compile-time implementation of a compare->isel sequence.
2244	// It takes two constants to compare, along with the true/false registers
2245	// and the comparison type (as a subreg to a CR field) and returns one
2246	// of the true/false registers, depending on the comparison results.
2247	static unsigned selectReg(int64_t Imm1, int64_t Imm2, unsigned CompareOpc,
2248	unsigned TrueReg, unsigned FalseReg,
2249	unsigned CRSubReg) {
2250	// Signed comparisons. The immediates are assumed to be sign-extended.
2251	if (CompareOpc == PPC::CMPWI \|\| CompareOpc == PPC::CMPDI) {
2252	switch (CRSubReg) {
2253	default: llvm_unreachable("Unknown integer comparison type.")::llvm::llvm_unreachable_internal("Unknown integer comparison type." , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2253);
2254	case PPC::sub_lt:
2255	return Imm1 < Imm2 ? TrueReg : FalseReg;
2256	case PPC::sub_gt:
2257	return Imm1 > Imm2 ? TrueReg : FalseReg;
2258	case PPC::sub_eq:
2259	return Imm1 == Imm2 ? TrueReg : FalseReg;
2260	}
2261	}
2262	// Unsigned comparisons.
2263	else if (CompareOpc == PPC::CMPLWI \|\| CompareOpc == PPC::CMPLDI) {
2264	switch (CRSubReg) {
2265	default: llvm_unreachable("Unknown integer comparison type.")::llvm::llvm_unreachable_internal("Unknown integer comparison type." , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2265);
2266	case PPC::sub_lt:
2267	return (uint64_t)Imm1 < (uint64_t)Imm2 ? TrueReg : FalseReg;
2268	case PPC::sub_gt:
2269	return (uint64_t)Imm1 > (uint64_t)Imm2 ? TrueReg : FalseReg;
2270	case PPC::sub_eq:
2271	return Imm1 == Imm2 ? TrueReg : FalseReg;
2272	}
2273	}
2274	return PPC::NoRegister;
2275	}
2276
2277	void PPCInstrInfo::replaceInstrOperandWithImm(MachineInstr &MI,
2278	unsigned OpNo,
2279	int64_t Imm) const {
2280	assert(MI.getOperand(OpNo).isReg() && "Operand must be a REG")((MI.getOperand(OpNo).isReg() && "Operand must be a REG" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(OpNo).isReg() && \"Operand must be a REG\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2280, __PRETTY_FUNCTION__));
2281	// Replace the REG with the Immediate.
2282	unsigned InUseReg = MI.getOperand(OpNo).getReg();
2283	MI.getOperand(OpNo).ChangeToImmediate(Imm);
2284
2285	if (empty(MI.implicit_operands()))
2286	return;
2287
2288	// We need to make sure that the MI didn't have any implicit use
2289	// of this REG any more.
2290	const TargetRegisterInfo *TRI = &getRegisterInfo();
2291	int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
2292	if (UseOpIdx >= 0) {
2293	MachineOperand &MO = MI.getOperand(UseOpIdx);
2294	if (MO.isImplicit())
2295	// The operands must always be in the following order:
2296	// - explicit reg defs,
2297	// - other explicit operands (reg uses, immediates, etc.),
2298	// - implicit reg defs
2299	// - implicit reg uses
2300	// Therefore, removing the implicit operand won't change the explicit
2301	// operands layout.
2302	MI.RemoveOperand(UseOpIdx);
2303	}
2304	}
2305
2306	// Replace an instruction with one that materializes a constant (and sets
2307	// CR0 if the original instruction was a record-form instruction).
2308	void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI,
2309	const LoadImmediateInfo &LII) const {
2310	// Remove existing operands.
2311	int OperandToKeep = LII.SetCR ? 1 : 0;
2312	for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--)
2313	MI.RemoveOperand(i);
2314
2315	// Replace the instruction.
2316	if (LII.SetCR) {
2317	MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo));
2318	// Set the immediate.
2319	MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2320	.addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
2321	return;
2322	}
2323	else
2324	MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI));
2325
2326	// Set the immediate.
2327	MachineInstrBuilder(*MI.getParent()->getParent(), MI)
2328	.addImm(LII.Imm);
2329	}
2330
2331	MachineInstr *PPCInstrInfo::getForwardingDefMI(
2332	MachineInstr &MI,
2333	unsigned &OpNoForForwarding,
2334	bool &SeenIntermediateUse) const {
2335	OpNoForForwarding = ~0U;
2336	MachineInstr *DefMI = nullptr;
2337	MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
2338	const TargetRegisterInfo *TRI = &getRegisterInfo();
2339	// If we're in SSA, get the defs through the MRI. Otherwise, only look
2340	// within the basic block to see if the register is defined using an LI/LI8.
2341	if (MRI->isSSA()) {
2342	for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2343	if (!MI.getOperand(i).isReg())
2344	continue;
2345	unsigned Reg = MI.getOperand(i).getReg();
2346	if (!TargetRegisterInfo::isVirtualRegister(Reg))
2347	continue;
2348	unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI);
2349	if (TargetRegisterInfo::isVirtualRegister(TrueReg)) {
2350	DefMI = MRI->getVRegDef(TrueReg);
2351	if (DefMI->getOpcode() == PPC::LI \|\| DefMI->getOpcode() == PPC::LI8) {
2352	OpNoForForwarding = i;
2353	break;
2354	}
2355	}
2356	}
2357	} else {
2358	// Looking back through the definition for each operand could be expensive,
2359	// so exit early if this isn't an instruction that either has an immediate
2360	// form or is already an immediate form that we can handle.
2361	ImmInstrInfo III;
2362	unsigned Opc = MI.getOpcode();
2363	bool ConvertibleImmForm =
2364	Opc == PPC::CMPWI \|\| Opc == PPC::CMPLWI \|\|
2365	Opc == PPC::CMPDI \|\| Opc == PPC::CMPLDI \|\|
2366	Opc == PPC::ADDI \|\| Opc == PPC::ADDI8 \|\|
2367	Opc == PPC::ORI \|\| Opc == PPC::ORI8 \|\|
2368	Opc == PPC::XORI \|\| Opc == PPC::XORI8 \|\|
2369	Opc == PPC::RLDICL \|\| Opc == PPC::RLDICLo \|\|
2370	Opc == PPC::RLDICL_32 \|\| Opc == PPC::RLDICL_32_64 \|\|
2371	Opc == PPC::RLWINM \|\| Opc == PPC::RLWINMo \|\|
2372	Opc == PPC::RLWINM8 \|\| Opc == PPC::RLWINM8o;
2373	if (!instrHasImmForm(MI, III, true) && !ConvertibleImmForm)
2374	return nullptr;
2375
2376	// Don't convert or %X, %Y, %Y since that's just a register move.
2377	if ((Opc == PPC::OR \|\| Opc == PPC::OR8) &&
2378	MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2379	return nullptr;
2380	for (int i = 1, e = MI.getNumOperands(); i < e; i++) {
2381	MachineOperand &MO = MI.getOperand(i);
2382	SeenIntermediateUse = false;
2383	if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2384	MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI;
2385	It++;
2386	unsigned Reg = MI.getOperand(i).getReg();
2387
2388	// Is this register defined by some form of add-immediate (including
2389	// load-immediate) within this basic block?
2390	for ( ; It != E; ++It) {
2391	if (It->modifiesRegister(Reg, &getRegisterInfo())) {
2392	switch (It->getOpcode()) {
2393	default: break;
2394	case PPC::LI:
2395	case PPC::LI8:
2396	case PPC::ADDItocL:
2397	case PPC::ADDI:
2398	case PPC::ADDI8:
2399	OpNoForForwarding = i;
2400	return &*It;
2401	}
2402	break;
2403	} else if (It->readsRegister(Reg, &getRegisterInfo()))
2404	// If we see another use of this reg between the def and the MI,
2405	// we want to flat it so the def isn't deleted.
2406	SeenIntermediateUse = true;
2407	}
2408	}
2409	}
2410	}
2411	return OpNoForForwarding == ~0U ? nullptr : DefMI;
2412	}
2413
2414	const unsigned *PPCInstrInfo::getStoreOpcodesForSpillArray() const {
2415	static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2416	// Power 8
2417	{PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2418	PPC::SPILL_CRBIT, PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX,
2419	PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2420	PPC::SPILLTOVSR_ST, PPC::EVSTDD, PPC::SPESTW},
2421	// Power 9
2422	{PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR,
2423	PPC::SPILL_CRBIT, PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32,
2424	PPC::SPILL_VRSAVE, PPC::QVSTFDX, PPC::QVSTFSXs, PPC::QVSTFDXb,
2425	PPC::SPILLTOVSR_ST}};
2426
2427	return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2428	}
2429
2430	const unsigned *PPCInstrInfo::getLoadOpcodesForSpillArray() const {
2431	static const unsigned OpcodesForSpill[2][SOK_LastOpcodeSpill] = {
2432	// Power 8
2433	{PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2434	PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX,
2435	PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2436	PPC::SPILLTOVSR_LD, PPC::EVLDD, PPC::SPELWZ},
2437	// Power 9
2438	{PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR,
2439	PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, PPC::DFLOADf32,
2440	PPC::RESTORE_VRSAVE, PPC::QVLFDX, PPC::QVLFSXs, PPC::QVLFDXb,
2441	PPC::SPILLTOVSR_LD}};
2442
2443	return OpcodesForSpill[(Subtarget.hasP9Vector()) ? 1 : 0];
2444	}
2445
2446	void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr &StartMI, MachineInstr &EndMI,
2447	unsigned RegNo) const {
2448	const MachineRegisterInfo &MRI =
2449	StartMI.getParent()->getParent()->getRegInfo();
2450	if (MRI.isSSA())
2451	return;
2452
2453	// Instructions between [StartMI, EndMI] should be in same basic block.
2454	assert((StartMI.getParent() == EndMI.getParent()) &&(((StartMI.getParent() == EndMI.getParent()) && "Instructions are not in same basic block" ) ? static_cast<void> (0) : __assert_fail ("(StartMI.getParent() == EndMI.getParent()) && \"Instructions are not in same basic block\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2455, __PRETTY_FUNCTION__))
2455	"Instructions are not in same basic block")(((StartMI.getParent() == EndMI.getParent()) && "Instructions are not in same basic block" ) ? static_cast<void> (0) : __assert_fail ("(StartMI.getParent() == EndMI.getParent()) && \"Instructions are not in same basic block\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2455, __PRETTY_FUNCTION__));
2456
2457	bool IsKillSet = false;
2458
2459	auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
2460	MachineOperand &MO = MI.getOperand(Index);
2461	if (MO.isReg() && MO.isUse() && MO.isKill() &&
2462	getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
2463	MO.setIsKill(false);
2464	};
2465
2466	// Set killed flag for EndMI.
2467	// No need to do anything if EndMI defines RegNo.
2468	int UseIndex =
2469	EndMI.findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
2470	if (UseIndex != -1) {
2471	EndMI.getOperand(UseIndex).setIsKill(true);
2472	IsKillSet = true;
2473	// Clear killed flag for other EndMI operands related to RegNo. In some
2474	// upexpected cases, killed may be set multiple times for same register
2475	// operand in same MI.
2476	for (int i = 0, e = EndMI.getNumOperands(); i != e; ++i)
2477	if (i != UseIndex)
2478	clearOperandKillInfo(EndMI, i);
2479	}
2480
2481	// Walking the inst in reverse order (EndMI -> StartMI].
2482	MachineBasicBlock::reverse_iterator It = EndMI;
2483	MachineBasicBlock::reverse_iterator E = EndMI.getParent()->rend();
2484	// EndMI has been handled above, skip it here.
2485	It++;
2486	MachineOperand *MO = nullptr;
2487	for (; It != E; ++It) {
2488	// Skip insturctions which could not be a def/use of RegNo.
2489	if (It->isDebugInstr() \|\| It->isPosition())
2490	continue;
2491
2492	// Clear killed flag for all It operands related to RegNo. In some
2493	// upexpected cases, killed may be set multiple times for same register
2494	// operand in same MI.
2495	for (int i = 0, e = It->getNumOperands(); i != e; ++i)
2496	clearOperandKillInfo(*It, i);
2497
2498	// If killed is not set, set killed for its last use or set dead for its def
2499	// if no use found.
2500	if (!IsKillSet) {
2501	if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
2502	// Use found, set it killed.
2503	IsKillSet = true;
2504	MO->setIsKill(true);
2505	continue;
2506	} else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
2507	&getRegisterInfo()))) {
2508	// No use found, set dead for its def.
2509	assert(&It == &StartMI && "No new def between StartMI and EndMI.")((&It == &StartMI && "No new def between StartMI and EndMI." ) ? static_cast<void> (0) : __assert_fail ("&*It == &StartMI && \"No new def between StartMI and EndMI.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2509, __PRETTY_FUNCTION__));
2510	MO->setIsDead(true);
2511	break;
2512	}
2513	}
2514
2515	if ((&*It) == &StartMI)
2516	break;
2517	}
2518	// Ensure RegMo liveness is killed after EndMI.
2519	assert((IsKillSet \|\| (MO && MO->isDead())) &&(((IsKillSet \|\| (MO && MO->isDead())) && "RegNo should be killed or dead" ) ? static_cast<void> (0) : __assert_fail ("(IsKillSet \|\| (MO && MO->isDead())) && \"RegNo should be killed or dead\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2520, __PRETTY_FUNCTION__))
2520	"RegNo should be killed or dead")(((IsKillSet \|\| (MO && MO->isDead())) && "RegNo should be killed or dead" ) ? static_cast<void> (0) : __assert_fail ("(IsKillSet \|\| (MO && MO->isDead())) && \"RegNo should be killed or dead\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2520, __PRETTY_FUNCTION__));
2521	}
2522
2523	// If this instruction has an immediate form and one of its operands is a
2524	// result of a load-immediate or an add-immediate, convert it to
2525	// the immediate form if the constant is in range.
2526	bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
2527	MachineInstr **KilledDef) const {
2528	MachineFunction *MF = MI.getParent()->getParent();
2529	MachineRegisterInfo *MRI = &MF->getRegInfo();
2530	bool PostRA = !MRI->isSSA();
2531	bool SeenIntermediateUse = true;
2532	unsigned ForwardingOperand = ~0U;
2533	MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
2534	SeenIntermediateUse);
2535	if (!DefMI)
2536	return false;
2537	assert(ForwardingOperand < MI.getNumOperands() &&((ForwardingOperand < MI.getNumOperands() && "The forwarding operand needs to be valid at this point" ) ? static_cast<void> (0) : __assert_fail ("ForwardingOperand < MI.getNumOperands() && \"The forwarding operand needs to be valid at this point\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2538, __PRETTY_FUNCTION__))
2538	"The forwarding operand needs to be valid at this point")((ForwardingOperand < MI.getNumOperands() && "The forwarding operand needs to be valid at this point" ) ? static_cast<void> (0) : __assert_fail ("ForwardingOperand < MI.getNumOperands() && \"The forwarding operand needs to be valid at this point\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2538, __PRETTY_FUNCTION__));
2539	bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
2540	bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
2541	unsigned ForwardingOperandReg = MI.getOperand(ForwardingOperand).getReg();
2542	if (KilledDef && KillFwdDefMI)
2543	*KilledDef = DefMI;
2544
2545	ImmInstrInfo III;
2546	bool HasImmForm = instrHasImmForm(MI, III, PostRA);
2547	// If this is a reg+reg instruction that has a reg+imm form,
2548	// and one of the operands is produced by an add-immediate,
2549	// try to convert it.
2550	if (HasImmForm &&
2551	transformToImmFormFedByAdd(MI, III, ForwardingOperand, *DefMI,
2552	KillFwdDefMI))
2553	return true;
2554
2555	if ((DefMI->getOpcode() != PPC::LI && DefMI->getOpcode() != PPC::LI8) \|\|
2556	!DefMI->getOperand(1).isImm())
2557	return false;
2558
2559	int64_t Immediate = DefMI->getOperand(1).getImm();
2560	// Sign-extend to 64-bits.
2561	int64_t SExtImm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
2562	(Immediate \| 0xFFFFFFFFFFFF0000) : Immediate;
2563
2564	// If this is a reg+reg instruction that has a reg+imm form,
2565	// and one of the operands is produced by LI, convert it now.
2566	if (HasImmForm)
2567	return transformToImmFormFedByLI(MI, III, ForwardingOperand, *DefMI, SExtImm);
2568
2569	bool ReplaceWithLI = false;
2570	bool Is64BitLI = false;
2571	int64_t NewImm = 0;
2572	bool SetCR = false;
2573	unsigned Opc = MI.getOpcode();
2574	switch (Opc) {
2575	default: return false;
2576
2577	// FIXME: Any branches conditional on such a comparison can be made
2578	// unconditional. At this time, this happens too infrequently to be worth
2579	// the implementation effort, but if that ever changes, we could convert
2580	// such a pattern here.
2581	case PPC::CMPWI:
2582	case PPC::CMPLWI:
2583	case PPC::CMPDI:
2584	case PPC::CMPLDI: {
2585	// Doing this post-RA would require dataflow analysis to reliably find uses
2586	// of the CR register set by the compare.
2587	// No need to fixup killed/dead flag since this transformation is only valid
2588	// before RA.
2589	if (PostRA)
2590	return false;
2591	// If a compare-immediate is fed by an immediate and is itself an input of
2592	// an ISEL (the most common case) into a COPY of the correct register.
2593	bool Changed = false;
2594	unsigned DefReg = MI.getOperand(0).getReg();
2595	int64_t Comparand = MI.getOperand(2).getImm();
2596	int64_t SExtComparand = ((uint64_t)Comparand & ~0x7FFFuLL) != 0 ?
2597	(Comparand \| 0xFFFFFFFFFFFF0000) : Comparand;
2598
2599	for (auto &CompareUseMI : MRI->use_instructions(DefReg)) {
2600	unsigned UseOpc = CompareUseMI.getOpcode();
2601	if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8)
2602	continue;
2603	unsigned CRSubReg = CompareUseMI.getOperand(3).getSubReg();
2604	unsigned TrueReg = CompareUseMI.getOperand(1).getReg();
2605	unsigned FalseReg = CompareUseMI.getOperand(2).getReg();
2606	unsigned RegToCopy = selectReg(SExtImm, SExtComparand, Opc, TrueReg,
2607	FalseReg, CRSubReg);
2608	if (RegToCopy == PPC::NoRegister)
2609	continue;
2610	// Can't use PPC::COPY to copy PPC::ZERO[8]. Convert it to LI[8] 0.
2611	if (RegToCopy == PPC::ZERO \|\| RegToCopy == PPC::ZERO8) {
2612	CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI));
2613	replaceInstrOperandWithImm(CompareUseMI, 1, 0);
2614	CompareUseMI.RemoveOperand(3);
2615	CompareUseMI.RemoveOperand(2);
2616	continue;
2617	}
2618	LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n" ; } } while (false)
2619	dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { dbgs() << "Found LI -> CMPI -> ISEL, replacing with a copy.\n" ; } } while (false);
2620	LLVM_DEBUG(DefMI->dump(); MI.dump(); CompareUseMI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { DefMI->dump(); MI.dump(); CompareUseMI .dump(); } } while (false);
2621	LLVM_DEBUG(dbgs() << "Is converted to:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { dbgs() << "Is converted to:\n"; } } while (false);
2622	// Convert to copy and remove unneeded operands.
2623	CompareUseMI.setDesc(get(PPC::COPY));
2624	CompareUseMI.RemoveOperand(3);
2625	CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1);
2626	CmpIselsConverted++;
2627	Changed = true;
2628	LLVM_DEBUG(CompareUseMI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { CompareUseMI.dump(); } } while (false);
2629	}
2630	if (Changed)
2631	return true;
2632	// This may end up incremented multiple times since this function is called
2633	// during a fixed-point transformation, but it is only meant to indicate the
2634	// presence of this opportunity.
2635	MissedConvertibleImmediateInstrs++;
2636	return false;
2637	}
2638
2639	// Immediate forms - may simply be convertable to an LI.
2640	case PPC::ADDI:
2641	case PPC::ADDI8: {
2642	// Does the sum fit in a 16-bit signed field?
2643	int64_t Addend = MI.getOperand(2).getImm();
2644	if (isInt<16>(Addend + SExtImm)) {
2645	ReplaceWithLI = true;
2646	Is64BitLI = Opc == PPC::ADDI8;
2647	NewImm = Addend + SExtImm;
2648	break;
2649	}
2650	return false;
2651	}
2652	case PPC::RLDICL:
2653	case PPC::RLDICLo:
2654	case PPC::RLDICL_32:
2655	case PPC::RLDICL_32_64: {
2656	// Use APInt's rotate function.
2657	int64_t SH = MI.getOperand(2).getImm();
2658	int64_t MB = MI.getOperand(3).getImm();
2659	APInt InVal((Opc == PPC::RLDICL \|\| Opc == PPC::RLDICLo) ?
2660	64 : 32, SExtImm, true);
2661	InVal = InVal.rotl(SH);
2662	uint64_t Mask = (1LLU << (63 - MB + 1)) - 1;
2663	InVal &= Mask;
2664	// Can't replace negative values with an LI as that will sign-extend
2665	// and not clear the left bits. If we're setting the CR bit, we will use
2666	// ANDIo which won't sign extend, so that's safe.
2667	if (isUInt<15>(InVal.getSExtValue()) \|\|
2668	(Opc == PPC::RLDICLo && isUInt<16>(InVal.getSExtValue()))) {
2669	ReplaceWithLI = true;
2670	Is64BitLI = Opc != PPC::RLDICL_32;
2671	NewImm = InVal.getSExtValue();
2672	SetCR = Opc == PPC::RLDICLo;
2673	break;
2674	}
2675	return false;
2676	}
2677	case PPC::RLWINM:
2678	case PPC::RLWINM8:
2679	case PPC::RLWINMo:
2680	case PPC::RLWINM8o: {
2681	int64_t SH = MI.getOperand(2).getImm();
2682	int64_t MB = MI.getOperand(3).getImm();
2683	int64_t ME = MI.getOperand(4).getImm();
2684	APInt InVal(32, SExtImm, true);
2685	InVal = InVal.rotl(SH);
2686	// Set the bits ( MB + 32 ) to ( ME + 32 ).
2687	uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
2688	InVal &= Mask;
2689	// Can't replace negative values with an LI as that will sign-extend
2690	// and not clear the left bits. If we're setting the CR bit, we will use
2691	// ANDIo which won't sign extend, so that's safe.
2692	bool ValueFits = isUInt<15>(InVal.getSExtValue());
2693	ValueFits \|= ((Opc == PPC::RLWINMo \|\| Opc == PPC::RLWINM8o) &&
2694	isUInt<16>(InVal.getSExtValue()));
2695	if (ValueFits) {
2696	ReplaceWithLI = true;
2697	Is64BitLI = Opc == PPC::RLWINM8 \|\| Opc == PPC::RLWINM8o;
2698	NewImm = InVal.getSExtValue();
2699	SetCR = Opc == PPC::RLWINMo \|\| Opc == PPC::RLWINM8o;
2700	break;
2701	}
2702	return false;
2703	}
2704	case PPC::ORI:
2705	case PPC::ORI8:
2706	case PPC::XORI:
2707	case PPC::XORI8: {
2708	int64_t LogicalImm = MI.getOperand(2).getImm();
2709	int64_t Result = 0;
2710	if (Opc == PPC::ORI \|\| Opc == PPC::ORI8)
2711	Result = LogicalImm \| SExtImm;
2712	else
2713	Result = LogicalImm ^ SExtImm;
2714	if (isInt<16>(Result)) {
2715	ReplaceWithLI = true;
2716	Is64BitLI = Opc == PPC::ORI8 \|\| Opc == PPC::XORI8;
2717	NewImm = Result;
2718	break;
2719	}
2720	return false;
2721	}
2722	}
2723
2724	if (ReplaceWithLI) {
2725	// We need to be careful with CR-setting instructions we're replacing.
2726	if (SetCR) {
2727	// We don't know anything about uses when we're out of SSA, so only
2728	// replace if the new immediate will be reproduced.
2729	bool ImmChanged = (SExtImm & NewImm) != NewImm;
2730	if (PostRA && ImmChanged)
2731	return false;
2732
2733	if (!PostRA) {
2734	// If the defining load-immediate has no other uses, we can just replace
2735	// the immediate with the new immediate.
2736	if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2737	DefMI->getOperand(1).setImm(NewImm);
2738
2739	// If we're not using the GPR result of the CR-setting instruction, we
2740	// just need to and with zero/non-zero depending on the new immediate.
2741	else if (MRI->use_empty(MI.getOperand(0).getReg())) {
2742	if (NewImm) {
2743	assert(Immediate && "Transformation converted zero to non-zero?")((Immediate && "Transformation converted zero to non-zero?" ) ? static_cast<void> (0) : __assert_fail ("Immediate && \"Transformation converted zero to non-zero?\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2743, __PRETTY_FUNCTION__));
2744	NewImm = Immediate;
2745	}
2746	}
2747	else if (ImmChanged)
2748	return false;
2749	}
2750	}
2751
2752	LLVM_DEBUG(dbgs() << "Replacing instruction:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { dbgs() << "Replacing instruction:\n" ; } } while (false);
2753	LLVM_DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { MI.dump(); } } while (false);
2754	LLVM_DEBUG(dbgs() << "Fed by:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { dbgs() << "Fed by:\n"; } } while ( false);
2755	LLVM_DEBUG(DefMI->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { DefMI->dump(); } } while (false);
2756	LoadImmediateInfo LII;
2757	LII.Imm = NewImm;
2758	LII.Is64Bit = Is64BitLI;
2759	LII.SetCR = SetCR;
2760	// If we're setting the CR, the original load-immediate must be kept (as an
2761	// operand to ANDIo/ANDI8o).
2762	if (KilledDef && SetCR)
2763	*KilledDef = nullptr;
2764	replaceInstrWithLI(MI, LII);
2765
2766	// Fixup killed/dead flag after transformation.
2767	// Pattern:
2768	// ForwardingOperandReg = LI imm1
2769	// y = op2 imm2, ForwardingOperandReg(killed)
2770	if (IsForwardingOperandKilled)
2771	fixupIsDeadOrKill(*DefMI, MI, ForwardingOperandReg);
2772
2773	LLVM_DEBUG(dbgs() << "With:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { dbgs() << "With:\n"; } } while (false );
2774	LLVM_DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { MI.dump(); } } while (false);
2775	return true;
2776	}
2777	return false;
2778	}
2779
2780	static bool isVFReg(unsigned Reg) {
2781	return PPC::VFRCRegClass.contains(Reg);
2782	}
2783
2784	bool PPCInstrInfo::instrHasImmForm(const MachineInstr &MI,
2785	ImmInstrInfo &III, bool PostRA) const {
2786	unsigned Opc = MI.getOpcode();
2787	// The vast majority of the instructions would need their operand 2 replaced
2788	// with an immediate when switching to the reg+imm form. A marked exception
2789	// are the update form loads/stores for which a constant operand 2 would need
2790	// to turn into a displacement and move operand 1 to the operand 2 position.
2791	III.ImmOpNo = 2;
2792	III.OpNoForForwarding = 2;
2793	III.ImmWidth = 16;
2794	III.ImmMustBeMultipleOf = 1;
2795	III.TruncateImmTo = 0;
2796	III.IsSummingOperands = false;
2797	switch (Opc) {
2798	default: return false;
2799	case PPC::ADD4:
2800	case PPC::ADD8:
2801	III.SignedImm = true;
2802	III.ZeroIsSpecialOrig = 0;
2803	III.ZeroIsSpecialNew = 1;
2804	III.IsCommutative = true;
2805	III.IsSummingOperands = true;
2806	III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8;
2807	break;
2808	case PPC::ADDC:
2809	case PPC::ADDC8:
2810	III.SignedImm = true;
2811	III.ZeroIsSpecialOrig = 0;
2812	III.ZeroIsSpecialNew = 0;
2813	III.IsCommutative = true;
2814	III.IsSummingOperands = true;
2815	III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8;
2816	break;
2817	case PPC::ADDCo:
2818	III.SignedImm = true;
2819	III.ZeroIsSpecialOrig = 0;
2820	III.ZeroIsSpecialNew = 0;
2821	III.IsCommutative = true;
2822	III.IsSummingOperands = true;
2823	III.ImmOpcode = PPC::ADDICo;
2824	break;
2825	case PPC::SUBFC:
2826	case PPC::SUBFC8:
2827	III.SignedImm = true;
2828	III.ZeroIsSpecialOrig = 0;
2829	III.ZeroIsSpecialNew = 0;
2830	III.IsCommutative = false;
2831	III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8;
2832	break;
2833	case PPC::CMPW:
2834	case PPC::CMPD:
2835	III.SignedImm = true;
2836	III.ZeroIsSpecialOrig = 0;
2837	III.ZeroIsSpecialNew = 0;
2838	III.IsCommutative = false;
2839	III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI;
2840	break;
2841	case PPC::CMPLW:
2842	case PPC::CMPLD:
2843	III.SignedImm = false;
2844	III.ZeroIsSpecialOrig = 0;
2845	III.ZeroIsSpecialNew = 0;
2846	III.IsCommutative = false;
2847	III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI;
2848	break;
2849	case PPC::ANDo:
2850	case PPC::AND8o:
2851	case PPC::OR:
2852	case PPC::OR8:
2853	case PPC::XOR:
2854	case PPC::XOR8:
2855	III.SignedImm = false;
2856	III.ZeroIsSpecialOrig = 0;
2857	III.ZeroIsSpecialNew = 0;
2858	III.IsCommutative = true;
2859	switch(Opc) {
2860	default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2860);
2861	case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break;
2862	case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break;
2863	case PPC::OR: III.ImmOpcode = PPC::ORI; break;
2864	case PPC::OR8: III.ImmOpcode = PPC::ORI8; break;
2865	case PPC::XOR: III.ImmOpcode = PPC::XORI; break;
2866	case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break;
2867	}
2868	break;
2869	case PPC::RLWNM:
2870	case PPC::RLWNM8:
2871	case PPC::RLWNMo:
2872	case PPC::RLWNM8o:
2873	case PPC::SLW:
2874	case PPC::SLW8:
2875	case PPC::SLWo:
2876	case PPC::SLW8o:
2877	case PPC::SRW:
2878	case PPC::SRW8:
2879	case PPC::SRWo:
2880	case PPC::SRW8o:
2881	case PPC::SRAW:
2882	case PPC::SRAWo:
2883	III.SignedImm = false;
2884	III.ZeroIsSpecialOrig = 0;
2885	III.ZeroIsSpecialNew = 0;
2886	III.IsCommutative = false;
2887	// This isn't actually true, but the instructions ignore any of the
2888	// upper bits, so any immediate loaded with an LI is acceptable.
2889	// This does not apply to shift right algebraic because a value
2890	// out of range will produce a -1/0.
2891	III.ImmWidth = 16;
2892	if (Opc == PPC::RLWNM \|\| Opc == PPC::RLWNM8 \|\|
2893	Opc == PPC::RLWNMo \|\| Opc == PPC::RLWNM8o)
2894	III.TruncateImmTo = 5;
2895	else
2896	III.TruncateImmTo = 6;
2897	switch(Opc) {
2898	default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2898);
2899	case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break;
2900	case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break;
2901	case PPC::RLWNMo: III.ImmOpcode = PPC::RLWINMo; break;
2902	case PPC::RLWNM8o: III.ImmOpcode = PPC::RLWINM8o; break;
2903	case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break;
2904	case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break;
2905	case PPC::SLWo: III.ImmOpcode = PPC::RLWINMo; break;
2906	case PPC::SLW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2907	case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break;
2908	case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break;
2909	case PPC::SRWo: III.ImmOpcode = PPC::RLWINMo; break;
2910	case PPC::SRW8o: III.ImmOpcode = PPC::RLWINM8o; break;
2911	case PPC::SRAW:
2912	III.ImmWidth = 5;
2913	III.TruncateImmTo = 0;
2914	III.ImmOpcode = PPC::SRAWI;
2915	break;
2916	case PPC::SRAWo:
2917	III.ImmWidth = 5;
2918	III.TruncateImmTo = 0;
2919	III.ImmOpcode = PPC::SRAWIo;
2920	break;
2921	}
2922	break;
2923	case PPC::RLDCL:
2924	case PPC::RLDCLo:
2925	case PPC::RLDCR:
2926	case PPC::RLDCRo:
2927	case PPC::SLD:
2928	case PPC::SLDo:
2929	case PPC::SRD:
2930	case PPC::SRDo:
2931	case PPC::SRAD:
2932	case PPC::SRADo:
2933	III.SignedImm = false;
2934	III.ZeroIsSpecialOrig = 0;
2935	III.ZeroIsSpecialNew = 0;
2936	III.IsCommutative = false;
2937	// This isn't actually true, but the instructions ignore any of the
2938	// upper bits, so any immediate loaded with an LI is acceptable.
2939	// This does not apply to shift right algebraic because a value
2940	// out of range will produce a -1/0.
2941	III.ImmWidth = 16;
2942	if (Opc == PPC::RLDCL \|\| Opc == PPC::RLDCLo \|\|
2943	Opc == PPC::RLDCR \|\| Opc == PPC::RLDCRo)
2944	III.TruncateImmTo = 6;
2945	else
2946	III.TruncateImmTo = 7;
2947	switch(Opc) {
2948	default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2948);
2949	case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break;
2950	case PPC::RLDCLo: III.ImmOpcode = PPC::RLDICLo; break;
2951	case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break;
2952	case PPC::RLDCRo: III.ImmOpcode = PPC::RLDICRo; break;
2953	case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break;
2954	case PPC::SLDo: III.ImmOpcode = PPC::RLDICRo; break;
2955	case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break;
2956	case PPC::SRDo: III.ImmOpcode = PPC::RLDICLo; break;
2957	case PPC::SRAD:
2958	III.ImmWidth = 6;
2959	III.TruncateImmTo = 0;
2960	III.ImmOpcode = PPC::SRADI;
2961	break;
2962	case PPC::SRADo:
2963	III.ImmWidth = 6;
2964	III.TruncateImmTo = 0;
2965	III.ImmOpcode = PPC::SRADIo;
2966	break;
2967	}
2968	break;
2969	// Loads and stores:
2970	case PPC::LBZX:
2971	case PPC::LBZX8:
2972	case PPC::LHZX:
2973	case PPC::LHZX8:
2974	case PPC::LHAX:
2975	case PPC::LHAX8:
2976	case PPC::LWZX:
2977	case PPC::LWZX8:
2978	case PPC::LWAX:
2979	case PPC::LDX:
2980	case PPC::LFSX:
2981	case PPC::LFDX:
2982	case PPC::STBX:
2983	case PPC::STBX8:
2984	case PPC::STHX:
2985	case PPC::STHX8:
2986	case PPC::STWX:
2987	case PPC::STWX8:
2988	case PPC::STDX:
2989	case PPC::STFSX:
2990	case PPC::STFDX:
2991	III.SignedImm = true;
2992	III.ZeroIsSpecialOrig = 1;
2993	III.ZeroIsSpecialNew = 2;
2994	III.IsCommutative = true;
2995	III.IsSummingOperands = true;
2996	III.ImmOpNo = 1;
2997	III.OpNoForForwarding = 2;
2998	switch(Opc) {
2999	default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 2999);
3000	case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break;
3001	case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break;
3002	case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break;
3003	case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break;
3004	case PPC::LHAX: III.ImmOpcode = PPC::LHA; break;
3005	case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break;
3006	case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break;
3007	case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break;
3008	case PPC::LWAX:
3009	III.ImmOpcode = PPC::LWA;
3010	III.ImmMustBeMultipleOf = 4;
3011	break;
3012	case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break;
3013	case PPC::LFSX: III.ImmOpcode = PPC::LFS; break;
3014	case PPC::LFDX: III.ImmOpcode = PPC::LFD; break;
3015	case PPC::STBX: III.ImmOpcode = PPC::STB; break;
3016	case PPC::STBX8: III.ImmOpcode = PPC::STB8; break;
3017	case PPC::STHX: III.ImmOpcode = PPC::STH; break;
3018	case PPC::STHX8: III.ImmOpcode = PPC::STH8; break;
3019	case PPC::STWX: III.ImmOpcode = PPC::STW; break;
3020	case PPC::STWX8: III.ImmOpcode = PPC::STW8; break;
3021	case PPC::STDX:
3022	III.ImmOpcode = PPC::STD;
3023	III.ImmMustBeMultipleOf = 4;
3024	break;
3025	case PPC::STFSX: III.ImmOpcode = PPC::STFS; break;
3026	case PPC::STFDX: III.ImmOpcode = PPC::STFD; break;
3027	}
3028	break;
3029	case PPC::LBZUX:
3030	case PPC::LBZUX8:
3031	case PPC::LHZUX:
3032	case PPC::LHZUX8:
3033	case PPC::LHAUX:
3034	case PPC::LHAUX8:
3035	case PPC::LWZUX:
3036	case PPC::LWZUX8:
3037	case PPC::LDUX:
3038	case PPC::LFSUX:
3039	case PPC::LFDUX:
3040	case PPC::STBUX:
3041	case PPC::STBUX8:
3042	case PPC::STHUX:
3043	case PPC::STHUX8:
3044	case PPC::STWUX:
3045	case PPC::STWUX8:
3046	case PPC::STDUX:
3047	case PPC::STFSUX:
3048	case PPC::STFDUX:
3049	III.SignedImm = true;
3050	III.ZeroIsSpecialOrig = 2;
3051	III.ZeroIsSpecialNew = 3;
3052	III.IsCommutative = false;
3053	III.IsSummingOperands = true;
3054	III.ImmOpNo = 2;
3055	III.OpNoForForwarding = 3;
3056	switch(Opc) {
3057	default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 3057);
3058	case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break;
3059	case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break;
3060	case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break;
3061	case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break;
3062	case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break;
3063	case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break;
3064	case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break;
3065	case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break;
3066	case PPC::LDUX:
3067	III.ImmOpcode = PPC::LDU;
3068	III.ImmMustBeMultipleOf = 4;
3069	break;
3070	case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break;
3071	case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break;
3072	case PPC::STBUX: III.ImmOpcode = PPC::STBU; break;
3073	case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break;
3074	case PPC::STHUX: III.ImmOpcode = PPC::STHU; break;
3075	case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break;
3076	case PPC::STWUX: III.ImmOpcode = PPC::STWU; break;
3077	case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break;
3078	case PPC::STDUX:
3079	III.ImmOpcode = PPC::STDU;
3080	III.ImmMustBeMultipleOf = 4;
3081	break;
3082	case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break;
3083	case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break;
3084	}
3085	break;
3086	// Power9 and up only. For some of these, the X-Form version has access to all
3087	// 64 VSR's whereas the D-Form only has access to the VR's. We replace those
3088	// with pseudo-ops pre-ra and for post-ra, we check that the register loaded
3089	// into or stored from is one of the VR registers.
3090	case PPC::LXVX:
3091	case PPC::LXSSPX:
3092	case PPC::LXSDX:
3093	case PPC::STXVX:
3094	case PPC::STXSSPX:
3095	case PPC::STXSDX:
3096	case PPC::XFLOADf32:
3097	case PPC::XFLOADf64:
3098	case PPC::XFSTOREf32:
3099	case PPC::XFSTOREf64:
3100	if (!Subtarget.hasP9Vector())
3101	return false;
3102	III.SignedImm = true;
3103	III.ZeroIsSpecialOrig = 1;
3104	III.ZeroIsSpecialNew = 2;
3105	III.IsCommutative = true;
3106	III.IsSummingOperands = true;
3107	III.ImmOpNo = 1;
3108	III.OpNoForForwarding = 2;
3109	III.ImmMustBeMultipleOf = 4;
3110	switch(Opc) {
3111	default: llvm_unreachable("Unknown opcode")::llvm::llvm_unreachable_internal("Unknown opcode", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 3111);
3112	case PPC::LXVX:
3113	III.ImmOpcode = PPC::LXV;
3114	III.ImmMustBeMultipleOf = 16;
3115	break;
3116	case PPC::LXSSPX:
3117	if (PostRA) {
3118	if (isVFReg(MI.getOperand(0).getReg()))
3119	III.ImmOpcode = PPC::LXSSP;
3120	else {
3121	III.ImmOpcode = PPC::LFS;
3122	III.ImmMustBeMultipleOf = 1;
3123	}
3124	break;
3125	}
3126	LLVM_FALLTHROUGH[[clang::fallthrough]];
3127	case PPC::XFLOADf32:
3128	III.ImmOpcode = PPC::DFLOADf32;
3129	break;
3130	case PPC::LXSDX:
3131	if (PostRA) {
3132	if (isVFReg(MI.getOperand(0).getReg()))
3133	III.ImmOpcode = PPC::LXSD;
3134	else {
3135	III.ImmOpcode = PPC::LFD;
3136	III.ImmMustBeMultipleOf = 1;
3137	}
3138	break;
3139	}
3140	LLVM_FALLTHROUGH[[clang::fallthrough]];
3141	case PPC::XFLOADf64:
3142	III.ImmOpcode = PPC::DFLOADf64;
3143	break;
3144	case PPC::STXVX:
3145	III.ImmOpcode = PPC::STXV;
3146	III.ImmMustBeMultipleOf = 16;
3147	break;
3148	case PPC::STXSSPX:
3149	if (PostRA) {
3150	if (isVFReg(MI.getOperand(0).getReg()))
3151	III.ImmOpcode = PPC::STXSSP;
3152	else {
3153	III.ImmOpcode = PPC::STFS;
3154	III.ImmMustBeMultipleOf = 1;
3155	}
3156	break;
3157	}
3158	LLVM_FALLTHROUGH[[clang::fallthrough]];
3159	case PPC::XFSTOREf32:
3160	III.ImmOpcode = PPC::DFSTOREf32;
3161	break;
3162	case PPC::STXSDX:
3163	if (PostRA) {
3164	if (isVFReg(MI.getOperand(0).getReg()))
3165	III.ImmOpcode = PPC::STXSD;
3166	else {
3167	III.ImmOpcode = PPC::STFD;
3168	III.ImmMustBeMultipleOf = 1;
3169	}
3170	break;
3171	}
3172	LLVM_FALLTHROUGH[[clang::fallthrough]];
3173	case PPC::XFSTOREf64:
3174	III.ImmOpcode = PPC::DFSTOREf64;
3175	break;
3176	}
3177	break;
3178	}
3179	return true;
3180	}
3181
3182	// Utility function for swaping two arbitrary operands of an instruction.
3183	static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) {
3184	assert(Op1 != Op2 && "Cannot swap operand with itself.")((Op1 != Op2 && "Cannot swap operand with itself.") ? static_cast<void> (0) : __assert_fail ("Op1 != Op2 && \"Cannot swap operand with itself.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 3184, __PRETTY_FUNCTION__));
3185
3186	unsigned MaxOp = std::max(Op1, Op2);
3187	unsigned MinOp = std::min(Op1, Op2);
3188	MachineOperand MOp1 = MI.getOperand(MinOp);
3189	MachineOperand MOp2 = MI.getOperand(MaxOp);
3190	MI.RemoveOperand(std::max(Op1, Op2));
3191	MI.RemoveOperand(std::min(Op1, Op2));
3192
3193	// If the operands we are swapping are the two at the end (the common case)
3194	// we can just remove both and add them in the opposite order.
3195	if (MaxOp - MinOp == 1 && MI.getNumOperands() == MinOp) {
3196	MI.addOperand(MOp2);
3197	MI.addOperand(MOp1);
3198	} else {
3199	// Store all operands in a temporary vector, remove them and re-add in the
3200	// right order.
3201	SmallVector<MachineOperand, 2> MOps;
3202	unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops.
3203	for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) {
3204	MOps.push_back(MI.getOperand(i));
3205	MI.RemoveOperand(i);
3206	}
3207	// MOp2 needs to be added next.
3208	MI.addOperand(MOp2);
3209	// Now add the rest.
3210	for (unsigned i = MI.getNumOperands(); i < TotalOps; i++) {
3211	if (i == MaxOp)
3212	MI.addOperand(MOp1);
3213	else {
3214	MI.addOperand(MOps.back());
3215	MOps.pop_back();
3216	}
3217	}
3218	}
3219	}
3220
3221	// Check if the 'MI' that has the index OpNoForForwarding
3222	// meets the requirement described in the ImmInstrInfo.
3223	bool PPCInstrInfo::isUseMIElgibleForForwarding(MachineInstr &MI,
3224	const ImmInstrInfo &III,
3225	unsigned OpNoForForwarding
3226	) const {
3227	// As the algorithm of checking for PPC::ZERO/PPC::ZERO8
3228	// would not work pre-RA, we can only do the check post RA.
3229	MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3230	if (MRI.isSSA())
3231	return false;
3232
3233	// Cannot do the transform if MI isn't summing the operands.
3234	if (!III.IsSummingOperands)
3235	return false;
3236
3237	// The instruction we are trying to replace must have the ZeroIsSpecialOrig set.
3238	if (!III.ZeroIsSpecialOrig)
3239	return false;
3240
3241	// We cannot do the transform if the operand we are trying to replace
3242	// isn't the same as the operand the instruction allows.
3243	if (OpNoForForwarding != III.OpNoForForwarding)
3244	return false;
3245
3246	// Check if the instruction we are trying to transform really has
3247	// the special zero register as its operand.
3248	if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3249	MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3250	return false;
3251
3252	// This machine instruction is convertible if it is,
3253	// 1. summing the operands.
3254	// 2. one of the operands is special zero register.
3255	// 3. the operand we are trying to replace is allowed by the MI.
3256	return true;
3257	}
3258
3259	// Check if the DefMI is the add inst and set the ImmMO and RegMO
3260	// accordingly.
3261	bool PPCInstrInfo::isDefMIElgibleForForwarding(MachineInstr &DefMI,
3262	const ImmInstrInfo &III,
3263	MachineOperand *&ImmMO,
3264	MachineOperand *&RegMO) const {
3265	unsigned Opc = DefMI.getOpcode();
3266	if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8)
3267	return false;
3268
3269	assert(DefMI.getNumOperands() >= 3 &&((DefMI.getNumOperands() >= 3 && "Add inst must have at least three operands" ) ? static_cast<void> (0) : __assert_fail ("DefMI.getNumOperands() >= 3 && \"Add inst must have at least three operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 3270, __PRETTY_FUNCTION__))
3270	"Add inst must have at least three operands")((DefMI.getNumOperands() >= 3 && "Add inst must have at least three operands" ) ? static_cast<void> (0) : __assert_fail ("DefMI.getNumOperands() >= 3 && \"Add inst must have at least three operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 3270, __PRETTY_FUNCTION__));
3271	RegMO = &DefMI.getOperand(1);
3272	ImmMO = &DefMI.getOperand(2);
3273
3274	// This DefMI is elgible for forwarding if it is:
3275	// 1. add inst
3276	// 2. one of the operands is Imm/CPI/Global.
3277	return isAnImmediateOperand(*ImmMO);
3278	}
3279
3280	bool PPCInstrInfo::isRegElgibleForForwarding(
3281	const MachineOperand &RegMO, const MachineInstr &DefMI,
3282	const MachineInstr &MI, bool KillDefMI,
3283	bool &IsFwdFeederRegKilled) const {
3284	// x = addi y, imm
3285	// ...
3286	// z = lfdx 0, x -> z = lfd imm(y)
3287	// The Reg "y" can be forwarded to the MI(z) only when there is no DEF
3288	// of "y" between the DEF of "x" and "z".
3289	// The query is only valid post RA.
3290	const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3291	if (MRI.isSSA())
3292	return false;
3293
3294	unsigned Reg = RegMO.getReg();
3295
3296	// Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg.
3297	MachineBasicBlock::const_reverse_iterator It = MI;
3298	MachineBasicBlock::const_reverse_iterator E = MI.getParent()->rend();
3299	It++;
3300	for (; It != E; ++It) {
3301	if (It->modifiesRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3302	return false;
3303	else if (It->killsRegister(Reg, &getRegisterInfo()) && (&*It) != &DefMI)
3304	IsFwdFeederRegKilled = true;
3305	// Made it to DefMI without encountering a clobber.
3306	if ((&*It) == &DefMI)
3307	break;
3308	}
3309	assert((&It) == &DefMI && "DefMI is missing")(((&It) == &DefMI && "DefMI is missing") ? static_cast <void> (0) : __assert_fail ("(&*It) == &DefMI && \"DefMI is missing\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 3309, __PRETTY_FUNCTION__));
3310
3311	// If DefMI also defines the register to be forwarded, we can only forward it
3312	// if DefMI is being erased.
3313	if (DefMI.modifiesRegister(Reg, &getRegisterInfo()))
3314	return KillDefMI;
3315
3316	return true;
3317	}
3318
3319	bool PPCInstrInfo::isImmElgibleForForwarding(const MachineOperand &ImmMO,
3320	const MachineInstr &DefMI,
3321	const ImmInstrInfo &III,
3322	int64_t &Imm) const {
3323	assert(isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate")((isAnImmediateOperand(ImmMO) && "ImmMO is NOT an immediate" ) ? static_cast<void> (0) : __assert_fail ("isAnImmediateOperand(ImmMO) && \"ImmMO is NOT an immediate\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 3323, __PRETTY_FUNCTION__));
3324	if (DefMI.getOpcode() == PPC::ADDItocL) {
3325	// The operand for ADDItocL is CPI, which isn't imm at compiling time,
3326	// However, we know that, it is 16-bit width, and has the alignment of 4.
3327	// Check if the instruction met the requirement.
3328	if (III.ImmMustBeMultipleOf > 4 \|\|
3329	III.TruncateImmTo \|\| III.ImmWidth != 16)
3330	return false;
3331
3332	// Going from XForm to DForm loads means that the displacement needs to be
3333	// not just an immediate but also a multiple of 4, or 16 depending on the
3334	// load. A DForm load cannot be represented if it is a multiple of say 2.
3335	// XForm loads do not have this restriction.
3336	if (ImmMO.isGlobal() &&
3337	ImmMO.getGlobal()->getAlignment() < III.ImmMustBeMultipleOf)
3338	return false;
3339
3340	return true;
3341	}
3342
3343	if (ImmMO.isImm()) {
3344	// It is Imm, we need to check if the Imm fit the range.
3345	int64_t Immediate = ImmMO.getImm();
3346	// Sign-extend to 64-bits.
3347	Imm = ((uint64_t)Immediate & ~0x7FFFuLL) != 0 ?
3348	(Immediate \| 0xFFFFFFFFFFFF0000) : Immediate;
3349
3350	if (Imm % III.ImmMustBeMultipleOf)
3351	return false;
3352	if (III.TruncateImmTo)
3353	Imm &= ((1 << III.TruncateImmTo) - 1);
3354	if (III.SignedImm) {
3355	APInt ActualValue(64, Imm, true);
3356	if (!ActualValue.isSignedIntN(III.ImmWidth))
3357	return false;
3358	} else {
3359	uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3360	if ((uint64_t)Imm > UnsignedMax)
3361	return false;
3362	}
3363	}
3364	else
3365	return false;
3366
3367	// This ImmMO is forwarded if it meets the requriement describle
3368	// in ImmInstrInfo
3369	return true;
3370	}
3371
3372	// If an X-Form instruction is fed by an add-immediate and one of its operands
3373	// is the literal zero, attempt to forward the source of the add-immediate to
3374	// the corresponding D-Form instruction with the displacement coming from
3375	// the immediate being added.
3376	bool PPCInstrInfo::transformToImmFormFedByAdd(
3377	MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding,
3378	MachineInstr &DefMI, bool KillDefMI) const {
3379	// RegMO ImmMO
3380	// \| \|
3381	// x = addi reg, imm <----- DefMI
3382	// y = op 0 , x <----- MI
3383	// \|
3384	// OpNoForForwarding
3385	// Check if the MI meet the requirement described in the III.
3386	if (!isUseMIElgibleForForwarding(MI, III, OpNoForForwarding))
3387	return false;
3388
3389	// Check if the DefMI meet the requirement
3390	// described in the III. If yes, set the ImmMO and RegMO accordingly.
3391	MachineOperand *ImmMO = nullptr;
3392	MachineOperand *RegMO = nullptr;
3393	if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO))
3394	return false;
3395	assert(ImmMO && RegMO && "Imm and Reg operand must have been set")((ImmMO && RegMO && "Imm and Reg operand must have been set" ) ? static_cast<void> (0) : __assert_fail ("ImmMO && RegMO && \"Imm and Reg operand must have been set\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 3395, __PRETTY_FUNCTION__));
3396
3397	// As we get the Imm operand now, we need to check if the ImmMO meet
3398	// the requirement described in the III. If yes set the Imm.
3399	int64_t Imm = 0;
3400	if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
3401	return false;
3402
3403	bool IsFwdFeederRegKilled = false;
3404	// Check if the RegMO can be forwarded to MI.
3405	if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI,
3406	IsFwdFeederRegKilled))
3407	return false;
3408
3409	// Get killed info in case fixup needed after transformation.
3410	unsigned ForwardKilledOperandReg = ~0U;
3411	MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3412	bool PostRA = !MRI.isSSA();
3413	if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
3414	ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
3415
3416	// We know that, the MI and DefMI both meet the pattern, and
3417	// the Imm also meet the requirement with the new Imm-form.
3418	// It is safe to do the transformation now.
3419	LLVM_DEBUG(dbgs() << "Replacing instruction:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { dbgs() << "Replacing instruction:\n" ; } } while (false);
3420	LLVM_DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { MI.dump(); } } while (false);
3421	LLVM_DEBUG(dbgs() << "Fed by:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { dbgs() << "Fed by:\n"; } } while ( false);
3422	LLVM_DEBUG(DefMI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { DefMI.dump(); } } while (false);
3423
3424	// Update the base reg first.
3425	MI.getOperand(III.OpNoForForwarding).ChangeToRegister(RegMO->getReg(),
3426	false, false,
3427	RegMO->isKill());
3428
3429	// Then, update the imm.
3430	if (ImmMO->isImm()) {
3431	// If the ImmMO is Imm, change the operand that has ZERO to that Imm
3432	// directly.
3433	replaceInstrOperandWithImm(MI, III.ZeroIsSpecialOrig, Imm);
3434	}
3435	else {
3436	// Otherwise, it is Constant Pool Index(CPI) or Global,
3437	// which is relocation in fact. We need to replace the special zero
3438	// register with ImmMO.
3439	// Before that, we need to fixup the target flags for imm.
3440	// For some reason, we miss to set the flag for the ImmMO if it is CPI.
3441	if (DefMI.getOpcode() == PPC::ADDItocL)
3442	ImmMO->setTargetFlags(PPCII::MO_TOC_LO);
3443
3444	// MI didn't have the interface such as MI.setOperand(i) though
3445	// it has MI.getOperand(i). To repalce the ZERO MachineOperand with
3446	// ImmMO, we need to remove ZERO operand and all the operands behind it,
3447	// and, add the ImmMO, then, move back all the operands behind ZERO.
3448	SmallVector<MachineOperand, 2> MOps;
3449	for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) {
3450	MOps.push_back(MI.getOperand(i));
3451	MI.RemoveOperand(i);
3452	}
3453
3454	// Remove the last MO in the list, which is ZERO operand in fact.
3455	MOps.pop_back();
3456	// Add the imm operand.
3457	MI.addOperand(*ImmMO);
3458	// Now add the rest back.
3459	for (auto &MO : MOps)
3460	MI.addOperand(MO);
3461	}
3462
3463	// Update the opcode.
3464	MI.setDesc(get(III.ImmOpcode));
3465
3466	// Fix up killed/dead flag after transformation.
3467	// Pattern 1:
3468	// x = ADD KilledFwdFeederReg, imm
3469	// n = opn KilledFwdFeederReg(killed), regn
3470	// y = XOP 0, x
3471	// Pattern 2:
3472	// x = ADD reg(killed), imm
3473	// y = XOP 0, x
3474	if (IsFwdFeederRegKilled \|\| RegMO->isKill())
3475	fixupIsDeadOrKill(DefMI, MI, RegMO->getReg());
3476	// Pattern 3:
3477	// ForwardKilledOperandReg = ADD reg, imm
3478	// y = XOP 0, ForwardKilledOperandReg(killed)
3479	if (ForwardKilledOperandReg != ~0U)
3480	fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3481
3482	LLVM_DEBUG(dbgs() << "With:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { dbgs() << "With:\n"; } } while (false );
3483	LLVM_DEBUG(MI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType ("ppc-instr-info")) { MI.dump(); } } while (false);
3484
3485	return true;
3486	}
3487
3488	bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
3489	const ImmInstrInfo &III,
3490	unsigned ConstantOpNo,
3491	MachineInstr &DefMI,
3492	int64_t Imm) const {
3493	MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3494	bool PostRA = !MRI.isSSA();
3495	// Exit early if we can't convert this.
3496	if ((ConstantOpNo != III.OpNoForForwarding) && !III.IsCommutative)
3497	return false;
3498	if (Imm % III.ImmMustBeMultipleOf)
3499	return false;
3500	if (III.TruncateImmTo)
3501	Imm &= ((1 << III.TruncateImmTo) - 1);
3502	if (III.SignedImm) {
3503	APInt ActualValue(64, Imm, true);
3504	if (!ActualValue.isSignedIntN(III.ImmWidth))
3505	return false;
3506	} else {
3507	uint64_t UnsignedMax = (1 << III.ImmWidth) - 1;
3508	if ((uint64_t)Imm > UnsignedMax)
3509	return false;
3510	}
3511
3512	// If we're post-RA, the instructions don't agree on whether register zero is
3513	// special, we can transform this as long as the register operand that will
3514	// end up in the location where zero is special isn't R0.
3515	if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3516	unsigned PosForOrigZero = III.ZeroIsSpecialOrig ? III.ZeroIsSpecialOrig :
3517	III.ZeroIsSpecialNew + 1;
3518	unsigned OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3519	unsigned NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3520	// If R0 is in the operand where zero is special for the new instruction,
3521	// it is unsafe to transform if the constant operand isn't that operand.
3522	if ((NewZeroReg == PPC::R0 \|\| NewZeroReg == PPC::X0) &&
3523	ConstantOpNo != III.ZeroIsSpecialNew)
3524	return false;
3525	if ((OrigZeroReg == PPC::R0 \|\| OrigZeroReg == PPC::X0) &&
3526	ConstantOpNo != PosForOrigZero)
3527	return false;
3528	}
3529
3530	// Get killed info in case fixup needed after transformation.
3531	unsigned ForwardKilledOperandReg = ~0U;
3532	if (PostRA && MI.getOperand(ConstantOpNo).isKill())
3533	ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
3534
3535	unsigned Opc = MI.getOpcode();
3536	bool SpecialShift32 =
3537	Opc == PPC::SLW \|\| Opc == PPC::SLWo \|\| Opc == PPC::SRW \|\| Opc == PPC::SRWo;
3538	bool SpecialShift64 =
3539	Opc == PPC::SLD \|\| Opc == PPC::SLDo \|\| Opc == PPC::SRD \|\| Opc == PPC::SRDo;
3540	bool SetCR = Opc == PPC::SLWo \|\| Opc == PPC::SRWo \|\|
3541	Opc == PPC::SLDo \|\| Opc == PPC::SRDo;
3542	bool RightShift =
3543	Opc == PPC::SRW \|\| Opc == PPC::SRWo \|\| Opc == PPC::SRD \|\| Opc == PPC::SRDo;
3544
3545	MI.setDesc(get(III.ImmOpcode));
3546	if (ConstantOpNo == III.OpNoForForwarding) {
3547	// Converting shifts to immediate form is a bit tricky since they may do
3548	// one of three things:
3549	// 1. If the shift amount is between OpSize and 2*OpSize, the result is zero
3550	// 2. If the shift amount is zero, the result is unchanged (save for maybe
3551	// setting CR0)
3552	// 3. If the shift amount is in [1, OpSize), it's just a shift
3553	if (SpecialShift32 \|\| SpecialShift64) {
3554	LoadImmediateInfo LII;
3555	LII.Imm = 0;
3556	LII.SetCR = SetCR;
3557	LII.Is64Bit = SpecialShift64;
3558	uint64_t ShAmt = Imm & (SpecialShift32 ? 0x1F : 0x3F);
3559	if (Imm & (SpecialShift32 ? 0x20 : 0x40))
3560	replaceInstrWithLI(MI, LII);
3561	// Shifts by zero don't change the value. If we don't need to set CR0,
3562	// just convert this to a COPY. Can't do this post-RA since we've already
3563	// cleaned up the copies.
3564	else if (!SetCR && ShAmt == 0 && !PostRA) {
3565	MI.RemoveOperand(2);
3566	MI.setDesc(get(PPC::COPY));
3567	} else {
3568	// The 32 bit and 64 bit instructions are quite different.
3569	if (SpecialShift32) {
3570	// Left shifts use (N, 0, 31-N), right shifts use (32-N, N, 31).
3571	uint64_t SH = RightShift ? 32 - ShAmt : ShAmt;
3572	uint64_t MB = RightShift ? ShAmt : 0;
3573	uint64_t ME = RightShift ? 31 : 31 - ShAmt;
3574	replaceInstrOperandWithImm(MI, III.OpNoForForwarding, SH);
3575	MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(MB)
3576	.addImm(ME);
3577	} else {
3578	// Left shifts use (N, 63-N), right shifts use (64-N, N).
3579	uint64_t SH = RightShift ? 64 - ShAmt : ShAmt;
3580	uint64_t ME = RightShift ? ShAmt : 63 - ShAmt;
3581	replaceInstrOperandWithImm(MI, III.OpNoForForwarding, SH);
3582	MachineInstrBuilder(*MI.getParent()->getParent(), MI).addImm(ME);
3583	}
3584	}
3585	} else
3586	replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3587	}
3588	// Convert commutative instructions (switch the operands and convert the
3589	// desired one to an immediate.
3590	else if (III.IsCommutative) {
3591	replaceInstrOperandWithImm(MI, ConstantOpNo, Imm);
3592	swapMIOperands(MI, ConstantOpNo, III.OpNoForForwarding);
3593	} else
3594	llvm_unreachable("Should have exited early!")::llvm::llvm_unreachable_internal("Should have exited early!" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 3594);
3595
3596	// For instructions for which the constant register replaces a different
3597	// operand than where the immediate goes, we need to swap them.
3598	if (III.OpNoForForwarding != III.ImmOpNo)
3599	swapMIOperands(MI, III.OpNoForForwarding, III.ImmOpNo);
3600
3601	// If the special R0/X0 register index are different for original instruction
3602	// and new instruction, we need to fix up the register class in new
3603	// instruction.
3604	if (!PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
3605	if (III.ZeroIsSpecialNew) {
3606	// If operand at III.ZeroIsSpecialNew is physical reg(eg: ZERO/ZERO8), no
3607	// need to fix up register class.
3608	unsigned RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3609	if (TargetRegisterInfo::isVirtualRegister(RegToModify)) {
3610	const TargetRegisterClass *NewRC =
3611	MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
3612	&PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
3613	MRI.setRegClass(RegToModify, NewRC);
3614	}
3615	}
3616	}
3617
3618	// Fix up killed/dead flag after transformation.
3619	// Pattern:
3620	// ForwardKilledOperandReg = LI imm
3621	// y = XOP reg, ForwardKilledOperandReg(killed)
3622	if (ForwardKilledOperandReg != ~0U)
3623	fixupIsDeadOrKill(DefMI, MI, ForwardKilledOperandReg);
3624	return true;
3625	}
3626
3627	const TargetRegisterClass *
3628	PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
3629	if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass)
3630	return &PPC::VSRCRegClass;
3631	return RC;
3632	}
3633
3634	int PPCInstrInfo::getRecordFormOpcode(unsigned Opcode) {
3635	return PPC::getRecordFormOpcode(Opcode);
3636	}
3637
3638	// This function returns true if the machine instruction
3639	// always outputs a value by sign-extending a 32 bit value,
3640	// i.e. 0 to 31-th bits are same as 32-th bit.
3641	static bool isSignExtendingOp(const MachineInstr &MI) {
3642	int Opcode = MI.getOpcode();
3643	if (Opcode == PPC::LI \|\| Opcode == PPC::LI8 \|\|
3644	Opcode == PPC::LIS \|\| Opcode == PPC::LIS8 \|\|
3645	Opcode == PPC::SRAW \|\| Opcode == PPC::SRAWo \|\|
3646	Opcode == PPC::SRAWI \|\| Opcode == PPC::SRAWIo \|\|
3647	Opcode == PPC::LWA \|\| Opcode == PPC::LWAX \|\|
3648	Opcode == PPC::LWA_32 \|\| Opcode == PPC::LWAX_32 \|\|
3649	Opcode == PPC::LHA \|\| Opcode == PPC::LHAX \|\|
3650	Opcode == PPC::LHA8 \|\| Opcode == PPC::LHAX8 \|\|
3651	Opcode == PPC::LBZ \|\| Opcode == PPC::LBZX \|\|
3652	Opcode == PPC::LBZ8 \|\| Opcode == PPC::LBZX8 \|\|
3653	Opcode == PPC::LBZU \|\| Opcode == PPC::LBZUX \|\|
3654	Opcode == PPC::LBZU8 \|\| Opcode == PPC::LBZUX8 \|\|
3655	Opcode == PPC::LHZ \|\| Opcode == PPC::LHZX \|\|
3656	Opcode == PPC::LHZ8 \|\| Opcode == PPC::LHZX8 \|\|
3657	Opcode == PPC::LHZU \|\| Opcode == PPC::LHZUX \|\|
3658	Opcode == PPC::LHZU8 \|\| Opcode == PPC::LHZUX8 \|\|
3659	Opcode == PPC::EXTSB \|\| Opcode == PPC::EXTSBo \|\|
3660	Opcode == PPC::EXTSH \|\| Opcode == PPC::EXTSHo \|\|
3661	Opcode == PPC::EXTSB8 \|\| Opcode == PPC::EXTSH8 \|\|
3662	Opcode == PPC::EXTSW \|\| Opcode == PPC::EXTSWo \|\|
3663	Opcode == PPC::SETB \|\| Opcode == PPC::SETB8 \|\|
3664	Opcode == PPC::EXTSH8_32_64 \|\| Opcode == PPC::EXTSW_32_64 \|\|
3665	Opcode == PPC::EXTSB8_32_64)
3666	return true;
3667
3668	if (Opcode == PPC::RLDICL && MI.getOperand(3).getImm() >= 33)
3669	return true;
3670
3671	if ((Opcode == PPC::RLWINM \|\| Opcode == PPC::RLWINMo \|\|
3672	Opcode == PPC::RLWNM \|\| Opcode == PPC::RLWNMo) &&
3673	MI.getOperand(3).getImm() > 0 &&
3674	MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3675	return true;
3676
3677	return false;
3678	}
3679
3680	// This function returns true if the machine instruction
3681	// always outputs zeros in higher 32 bits.
3682	static bool isZeroExtendingOp(const MachineInstr &MI) {
3683	int Opcode = MI.getOpcode();
3684	// The 16-bit immediate is sign-extended in li/lis.
3685	// If the most significant bit is zero, all higher bits are zero.
3686	if (Opcode == PPC::LI \|\| Opcode == PPC::LI8 \|\|
3687	Opcode == PPC::LIS \|\| Opcode == PPC::LIS8) {
3688	int64_t Imm = MI.getOperand(1).getImm();
3689	if (((uint64_t)Imm & ~0x7FFFuLL) == 0)
3690	return true;
3691	}
3692
3693	// We have some variations of rotate-and-mask instructions
3694	// that clear higher 32-bits.
3695	if ((Opcode == PPC::RLDICL \|\| Opcode == PPC::RLDICLo \|\|
3696	Opcode == PPC::RLDCL \|\| Opcode == PPC::RLDCLo \|\|
3697	Opcode == PPC::RLDICL_32_64) &&
3698	MI.getOperand(3).getImm() >= 32)
3699	return true;
3700
3701	if ((Opcode == PPC::RLDIC \|\| Opcode == PPC::RLDICo) &&
3702	MI.getOperand(3).getImm() >= 32 &&
3703	MI.getOperand(3).getImm() <= 63 - MI.getOperand(2).getImm())
3704	return true;
3705
3706	if ((Opcode == PPC::RLWINM \|\| Opcode == PPC::RLWINMo \|\|
3707	Opcode == PPC::RLWNM \|\| Opcode == PPC::RLWNMo \|\|
3708	Opcode == PPC::RLWINM8 \|\| Opcode == PPC::RLWNM8) &&
3709	MI.getOperand(3).getImm() <= MI.getOperand(4).getImm())
3710	return true;
3711
3712	// There are other instructions that clear higher 32-bits.
3713	if (Opcode == PPC::CNTLZW \|\| Opcode == PPC::CNTLZWo \|\|
3714	Opcode == PPC::CNTTZW \|\| Opcode == PPC::CNTTZWo \|\|
3715	Opcode == PPC::CNTLZW8 \|\| Opcode == PPC::CNTTZW8 \|\|
3716	Opcode == PPC::CNTLZD \|\| Opcode == PPC::CNTLZDo \|\|
3717	Opcode == PPC::CNTTZD \|\| Opcode == PPC::CNTTZDo \|\|
3718	Opcode == PPC::POPCNTD \|\| Opcode == PPC::POPCNTW \|\|
3719	Opcode == PPC::SLW \|\| Opcode == PPC::SLWo \|\|
3720	Opcode == PPC::SRW \|\| Opcode == PPC::SRWo \|\|
3721	Opcode == PPC::SLW8 \|\| Opcode == PPC::SRW8 \|\|
3722	Opcode == PPC::SLWI \|\| Opcode == PPC::SLWIo \|\|
3723	Opcode == PPC::SRWI \|\| Opcode == PPC::SRWIo \|\|
3724	Opcode == PPC::LWZ \|\| Opcode == PPC::LWZX \|\|
3725	Opcode == PPC::LWZU \|\| Opcode == PPC::LWZUX \|\|
3726	Opcode == PPC::LWBRX \|\| Opcode == PPC::LHBRX \|\|
3727	Opcode == PPC::LHZ \|\| Opcode == PPC::LHZX \|\|
3728	Opcode == PPC::LHZU \|\| Opcode == PPC::LHZUX \|\|
3729	Opcode == PPC::LBZ \|\| Opcode == PPC::LBZX \|\|
3730	Opcode == PPC::LBZU \|\| Opcode == PPC::LBZUX \|\|
3731	Opcode == PPC::LWZ8 \|\| Opcode == PPC::LWZX8 \|\|
3732	Opcode == PPC::LWZU8 \|\| Opcode == PPC::LWZUX8 \|\|
3733	Opcode == PPC::LWBRX8 \|\| Opcode == PPC::LHBRX8 \|\|
3734	Opcode == PPC::LHZ8 \|\| Opcode == PPC::LHZX8 \|\|
3735	Opcode == PPC::LHZU8 \|\| Opcode == PPC::LHZUX8 \|\|
3736	Opcode == PPC::LBZ8 \|\| Opcode == PPC::LBZX8 \|\|
3737	Opcode == PPC::LBZU8 \|\| Opcode == PPC::LBZUX8 \|\|
3738	Opcode == PPC::ANDIo \|\| Opcode == PPC::ANDISo \|\|
3739	Opcode == PPC::ROTRWI \|\| Opcode == PPC::ROTRWIo \|\|
3740	Opcode == PPC::EXTLWI \|\| Opcode == PPC::EXTLWIo \|\|
3741	Opcode == PPC::MFVSRWZ)
3742	return true;
3743
3744	return false;
3745	}
3746
3747	// This function returns true if the input MachineInstr is a TOC save
3748	// instruction.
3749	bool PPCInstrInfo::isTOCSaveMI(const MachineInstr &MI) const {
3750	if (!MI.getOperand(1).isImm() \|\| !MI.getOperand(2).isReg())
3751	return false;
3752	unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
3753	unsigned StackOffset = MI.getOperand(1).getImm();
3754	unsigned StackReg = MI.getOperand(2).getReg();
3755	if (StackReg == PPC::X1 && StackOffset == TOCSaveOffset)
3756	return true;
3757
3758	return false;
3759	}
3760
3761	// We limit the max depth to track incoming values of PHIs or binary ops
3762	// (e.g. AND) to avoid excessive cost.
3763	const unsigned MAX_DEPTH = 1;
3764
3765	bool
3766	PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt,
3767	const unsigned Depth) const {
3768	const MachineFunction *MF = MI.getParent()->getParent();
3769	const MachineRegisterInfo *MRI = &MF->getRegInfo();
3770
3771	// If we know this instruction returns sign- or zero-extended result,
3772	// return true.
3773	if (SignExt ? isSignExtendingOp(MI):
3774	isZeroExtendingOp(MI))
3775	return true;
3776
3777	switch (MI.getOpcode()) {
3778	case PPC::COPY: {
3779	unsigned SrcReg = MI.getOperand(1).getReg();
3780
3781	// In both ELFv1 and v2 ABI, method parameters and the return value
3782	// are sign- or zero-extended.
3783	if (MF->getSubtarget<PPCSubtarget>().isSVR4ABI()) {
3784	const PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
3785	// We check the ZExt/SExt flags for a method parameter.
3786	if (MI.getParent()->getBasicBlock() ==
3787	&MF->getFunction().getEntryBlock()) {
3788	unsigned VReg = MI.getOperand(0).getReg();
3789	if (MF->getRegInfo().isLiveIn(VReg))
3790	return SignExt ? FuncInfo->isLiveInSExt(VReg) :
3791	FuncInfo->isLiveInZExt(VReg);
3792	}
3793
3794	// For a method return value, we check the ZExt/SExt flags in attribute.
3795	// We assume the following code sequence for method call.
3796	// ADJCALLSTACKDOWN 32, implicit dead %r1, implicit %r1
3797	// BL8_NOP @func,...
3798	// ADJCALLSTACKUP 32, 0, implicit dead %r1, implicit %r1
3799	// %5 = COPY %x3; G8RC:%5
3800	if (SrcReg == PPC::X3) {
3801	const MachineBasicBlock *MBB = MI.getParent();
3802	MachineBasicBlock::const_instr_iterator II =
3803	MachineBasicBlock::const_instr_iterator(&MI);
3804	if (II != MBB->instr_begin() &&
3805	(--II)->getOpcode() == PPC::ADJCALLSTACKUP) {
3806	const MachineInstr &CallMI = *(--II);
3807	if (CallMI.isCall() && CallMI.getOperand(0).isGlobal()) {
3808	const Function *CalleeFn =
3809	dyn_cast<Function>(CallMI.getOperand(0).getGlobal());
3810	if (!CalleeFn)
3811	return false;
3812	const IntegerType *IntTy =
3813	dyn_cast<IntegerType>(CalleeFn->getReturnType());
3814	const AttributeSet &Attrs =
3815	CalleeFn->getAttributes().getRetAttributes();
3816	if (IntTy && IntTy->getBitWidth() <= 32)
3817	return Attrs.hasAttribute(SignExt ? Attribute::SExt :
3818	Attribute::ZExt);
3819	}
3820	}
3821	}
3822	}
3823
3824	// If this is a copy from another register, we recursively check source.
3825	if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3826	return false;
3827	const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3828	if (SrcMI != NULL__null)
3829	return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3830
3831	return false;
3832	}
3833
3834	case PPC::ANDIo:
3835	case PPC::ANDISo:
3836	case PPC::ORI:
3837	case PPC::ORIS:
3838	case PPC::XORI:
3839	case PPC::XORIS:
3840	case PPC::ANDIo8:
3841	case PPC::ANDISo8:
3842	case PPC::ORI8:
3843	case PPC::ORIS8:
3844	case PPC::XORI8:
3845	case PPC::XORIS8: {
3846	// logical operation with 16-bit immediate does not change the upper bits.
3847	// So, we track the operand register as we do for register copy.
3848	unsigned SrcReg = MI.getOperand(1).getReg();
3849	if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3850	return false;
3851	const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3852	if (SrcMI != NULL__null)
3853	return isSignOrZeroExtended(*SrcMI, SignExt, Depth);
3854
3855	return false;
3856	}
3857
3858	// If all incoming values are sign-/zero-extended,
3859	// the output of OR, ISEL or PHI is also sign-/zero-extended.
3860	case PPC::OR:
3861	case PPC::OR8:
3862	case PPC::ISEL:
3863	case PPC::PHI: {
3864	if (Depth >= MAX_DEPTH)
3865	return false;
3866
3867	// The input registers for PHI are operand 1, 3, ...
3868	// The input registers for others are operand 1 and 2.
3869	unsigned E = 3, D = 1;
3870	if (MI.getOpcode() == PPC::PHI) {
3871	E = MI.getNumOperands();
3872	D = 2;
3873	}
3874
3875	for (unsigned I = 1; I != E; I += D) {
3876	if (MI.getOperand(I).isReg()) {
3877	unsigned SrcReg = MI.getOperand(I).getReg();
3878	if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
3879	return false;
3880	const MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
3881	if (SrcMI == NULL__null \|\| !isSignOrZeroExtended(*SrcMI, SignExt, Depth+1))
3882	return false;
3883	}
3884	else
3885	return false;
3886	}
3887	return true;
3888	}
3889
3890	// If at least one of the incoming values of an AND is zero extended
3891	// then the output is also zero-extended. If both of the incoming values
3892	// are sign-extended then the output is also sign extended.
3893	case PPC::AND:
3894	case PPC::AND8: {
3895	if (Depth >= MAX_DEPTH)
3896	return false;
3897
3898	assert(MI.getOperand(1).isReg() && MI.getOperand(2).isReg())((MI.getOperand(1).isReg() && MI.getOperand(2).isReg( )) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(1).isReg() && MI.getOperand(2).isReg()" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/PowerPC/PPCInstrInfo.cpp" , 3898, __PRETTY_FUNCTION__));
3899
3900	unsigned SrcReg1 = MI.getOperand(1).getReg();
3901	unsigned SrcReg2 = MI.getOperand(2).getReg();
3902
3903	if (!TargetRegisterInfo::isVirtualRegister(SrcReg1) \|\|
3904	!TargetRegisterInfo::isVirtualRegister(SrcReg2))
3905	return false;
3906
3907	const MachineInstr *MISrc1 = MRI->getVRegDef(SrcReg1);
3908	const MachineInstr *MISrc2 = MRI->getVRegDef(SrcReg2);
3909	if (!MISrc1 \|\| !MISrc2)
3910	return false;
3911
3912	if(SignExt)
3913	return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) &&
3914	isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3915	else
3916	return isSignOrZeroExtended(*MISrc1, SignExt, Depth+1) \|\|
3917	isSignOrZeroExtended(*MISrc2, SignExt, Depth+1);
3918	}
3919
3920	default:
3921	break;
3922	}
3923	return false;
3924	}