Bug Summary

File:llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp
Warning:line 132, column 39
The result of the left shift is undefined due to shifting by '32', which is greater or equal to the width of type 'uint32_t'

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name PPCMachineFunctionInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4/build-llvm/lib/Target/PowerPC -resource-dir /usr/lib/llvm-13/lib/clang/13.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4/build-llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4/llvm/lib/Target/PowerPC -I /build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4/build-llvm/include -I /build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-13/lib/clang/13.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4/build-llvm/lib/Target/PowerPC -fdebug-prefix-map=/build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-07-23-023125-8721-1 -x c++ /build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

/build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp

1//===-- PPCMachineFunctionInfo.cpp - Private data used for PowerPC --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "PPCMachineFunctionInfo.h"
10#include "llvm/ADT/Twine.h"
11#include "llvm/BinaryFormat/XCOFF.h"
12#include "llvm/IR/DataLayout.h"
13#include "llvm/MC/MCContext.h"
14#include "llvm/Support/CommandLine.h"
15
16using namespace llvm;
17static cl::opt<bool> PPCDisableNonVolatileCR(
18 "ppc-disable-non-volatile-cr",
19 cl::desc("Disable the use of non-volatile CR register fields"),
20 cl::init(false), cl::Hidden);
21
22void PPCFunctionInfo::anchor() {}
23PPCFunctionInfo::PPCFunctionInfo(const MachineFunction &MF)
24 : DisableNonVolatileCR(PPCDisableNonVolatileCR) {}
25
26MCSymbol *PPCFunctionInfo::getPICOffsetSymbol(MachineFunction &MF) const {
27 const DataLayout &DL = MF.getDataLayout();
28 return MF.getContext().getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
29 Twine(MF.getFunctionNumber()) +
30 "$poff");
31}
32
33MCSymbol *PPCFunctionInfo::getGlobalEPSymbol(MachineFunction &MF) const {
34 const DataLayout &DL = MF.getDataLayout();
35 return MF.getContext().getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
36 "func_gep" +
37 Twine(MF.getFunctionNumber()));
38}
39
40MCSymbol *PPCFunctionInfo::getLocalEPSymbol(MachineFunction &MF) const {
41 const DataLayout &DL = MF.getDataLayout();
42 return MF.getContext().getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
43 "func_lep" +
44 Twine(MF.getFunctionNumber()));
45}
46
47MCSymbol *PPCFunctionInfo::getTOCOffsetSymbol(MachineFunction &MF) const {
48 const DataLayout &DL = MF.getDataLayout();
49 return MF.getContext().getOrCreateSymbol(Twine(DL.getPrivateGlobalPrefix()) +
50 "func_toc" +
51 Twine(MF.getFunctionNumber()));
52}
53
54bool PPCFunctionInfo::isLiveInSExt(Register VReg) const {
55 for (const std::pair<Register, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
56 if (LiveIn.first == VReg)
57 return LiveIn.second.isSExt();
58 return false;
59}
60
61bool PPCFunctionInfo::isLiveInZExt(Register VReg) const {
62 for (const std::pair<Register, ISD::ArgFlagsTy> &LiveIn : LiveInAttrs)
63 if (LiveIn.first == VReg)
64 return LiveIn.second.isZExt();
65 return false;
66}
67
68void PPCFunctionInfo::appendParameterType(ParamType Type) {
69
70 ParamtersType.push_back(Type);
71 switch (Type) {
72 case FixedType:
73 ++FixedParmsNum;
74 return;
75 case ShortFloatingPoint:
76 case LongFloatingPoint:
77 ++FloatingParmsNum;
78 return;
79 case VectorChar:
80 case VectorShort:
81 case VectorInt:
82 case VectorFloat:
83 ++VectorParmsNum;
84 return;
85 }
86 llvm_unreachable("Error ParamType type.")::llvm::llvm_unreachable_internal("Error ParamType type.", "/build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp"
, 86)
;
87}
88
89uint32_t PPCFunctionInfo::getVecExtParmsType() const {
90
91 uint32_t VectExtParamInfo = 0;
92 unsigned ShiftBits = 32 - XCOFF::TracebackTable::WidthOfParamType;
93 int Bits = 0;
94
95 if (!hasVectorParms())
1
Calling 'PPCFunctionInfo::hasVectorParms'
4
Returning from 'PPCFunctionInfo::hasVectorParms'
5
Taking false branch
96 return 0;
97
98 for (const auto &Elt : ParamtersType) {
6
Assuming '__begin1' is equal to '__end1'
99 switch (Elt) {
100 case VectorChar:
101 VectExtParamInfo <<= XCOFF::TracebackTable::WidthOfParamType;
102 VectExtParamInfo |=
103 XCOFF::TracebackTable::ParmTypeIsVectorCharBit >> ShiftBits;
104 Bits += XCOFF::TracebackTable::WidthOfParamType;
105 break;
106 case VectorShort:
107 VectExtParamInfo <<= XCOFF::TracebackTable::WidthOfParamType;
108 VectExtParamInfo |=
109 XCOFF::TracebackTable::ParmTypeIsVectorShortBit >> ShiftBits;
110 Bits += XCOFF::TracebackTable::WidthOfParamType;
111 break;
112 case VectorInt:
113 VectExtParamInfo <<= XCOFF::TracebackTable::WidthOfParamType;
114 VectExtParamInfo |=
115 XCOFF::TracebackTable::ParmTypeIsVectorIntBit >> ShiftBits;
116 Bits += XCOFF::TracebackTable::WidthOfParamType;
117 break;
118 case VectorFloat:
119 VectExtParamInfo <<= XCOFF::TracebackTable::WidthOfParamType;
120 VectExtParamInfo |=
121 XCOFF::TracebackTable::ParmTypeIsVectorFloatBit >> ShiftBits;
122 Bits += XCOFF::TracebackTable::WidthOfParamType;
123 break;
124 default:
125 break;
126 }
127
128 // There are only 32bits in the VectExtParamInfo.
129 if (Bits >= 32)
130 break;
131 }
132 return Bits
6.1
'Bits' is < 32
6.1
'Bits' is < 32
< 32 ? VectExtParamInfo << (32 - Bits) : VectExtParamInfo;
7
'?' condition is true
8
The result of the left shift is undefined due to shifting by '32', which is greater or equal to the width of type 'uint32_t'
133}
134
135uint32_t PPCFunctionInfo::getParmsType() const {
136 uint32_t ParamsTypeInfo = 0;
137 unsigned ShiftBits = 32 - XCOFF::TracebackTable::WidthOfParamType;
138
139 int Bits = 0;
140 for (const auto &Elt : ParamtersType) {
141
142 if (Bits > 31 || (Bits > 30 && (Elt != FixedType || hasVectorParms())))
143 break;
144
145 switch (Elt) {
146 case FixedType:
147 if (hasVectorParms()) {
148 //'00' ==> fixed parameter if HasVectorParms is true.
149 ParamsTypeInfo <<= XCOFF::TracebackTable::WidthOfParamType;
150 ParamsTypeInfo |=
151 XCOFF::TracebackTable::ParmTypeIsFixedBits >> ShiftBits;
152 Bits += XCOFF::TracebackTable::WidthOfParamType;
153 } else {
154 //'0' ==> fixed parameter if HasVectorParms is false.
155 ParamsTypeInfo <<= 1;
156 ++Bits;
157 }
158 break;
159 case ShortFloatingPoint:
160 // '10'b => floating point short parameter.
161 ParamsTypeInfo <<= XCOFF::TracebackTable::WidthOfParamType;
162 ParamsTypeInfo |=
163 XCOFF::TracebackTable::ParmTypeIsFloatingBits >> ShiftBits;
164 Bits += XCOFF::TracebackTable::WidthOfParamType;
165 break;
166 case LongFloatingPoint:
167 // '11'b => floating point long parameter.
168 ParamsTypeInfo <<= XCOFF::TracebackTable::WidthOfParamType;
169 ParamsTypeInfo |=
170 XCOFF::TracebackTable::ParmTypeIsDoubleBits >> ShiftBits;
171 Bits += XCOFF::TracebackTable::WidthOfParamType;
172 break;
173 case VectorChar:
174 case VectorShort:
175 case VectorInt:
176 case VectorFloat:
177 // '01' ==> vector parameter
178 ParamsTypeInfo <<= XCOFF::TracebackTable::WidthOfParamType;
179 ParamsTypeInfo |=
180 XCOFF::TracebackTable::ParmTypeIsVectorBits >> ShiftBits;
181 Bits += XCOFF::TracebackTable::WidthOfParamType;
182 break;
183 }
184 }
185
186 return Bits < 32 ? ParamsTypeInfo << (32 - Bits) : ParamsTypeInfo;
187}

/build/llvm-toolchain-snapshot-13~++20210722111111+b115c038d2d4/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h

1//===-- PPCMachineFunctionInfo.h - Private data used for PowerPC --*- C++ -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the PowerPC specific subclass of MachineFunctionInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H
15
16#include "llvm/ADT/SmallVector.h"
17#include "llvm/CodeGen/MachineFunction.h"
18#include "llvm/CodeGen/TargetCallingConv.h"
19
20namespace llvm {
21
22/// PPCFunctionInfo - This class is derived from MachineFunction private
23/// PowerPC target-specific information for each MachineFunction.
24class PPCFunctionInfo : public MachineFunctionInfo {
25public:
26 enum ParamType {
27 FixedType,
28 ShortFloatingPoint,
29 LongFloatingPoint,
30 VectorChar,
31 VectorShort,
32 VectorInt,
33 VectorFloat
34 };
35
36private:
37 virtual void anchor();
38
39 /// FramePointerSaveIndex - Frame index of where the old frame pointer is
40 /// stored. Also used as an anchor for instructions that need to be altered
41 /// when using frame pointers (dyna_add, dyna_sub.)
42 int FramePointerSaveIndex = 0;
43
44 /// ReturnAddrSaveIndex - Frame index of where the return address is stored.
45 ///
46 int ReturnAddrSaveIndex = 0;
47
48 /// Frame index where the old base pointer is stored.
49 int BasePointerSaveIndex = 0;
50
51 /// Frame index where the old PIC base pointer is stored.
52 int PICBasePointerSaveIndex = 0;
53
54 /// Frame index where the ROP Protection Hash is stored.
55 int ROPProtectionHashSaveIndex = 0;
56
57 /// MustSaveLR - Indicates whether LR is defined (or clobbered) in the current
58 /// function. This is only valid after the initial scan of the function by
59 /// PEI.
60 bool MustSaveLR = false;
61
62 /// MustSaveTOC - Indicates that the TOC save needs to be performed in the
63 /// prologue of the function. This is typically the case when there are
64 /// indirect calls in the function and it is more profitable to save the
65 /// TOC pointer in the prologue than in the block(s) containing the call(s).
66 bool MustSaveTOC = false;
67
68 /// Do we have to disable shrink-wrapping? This has to be set if we emit any
69 /// instructions that clobber LR in the entry block because discovering this
70 /// in PEI is too late (happens after shrink-wrapping);
71 bool ShrinkWrapDisabled = false;
72
73 /// Does this function have any stack spills.
74 bool HasSpills = false;
75
76 /// Does this function spill using instructions with only r+r (not r+i)
77 /// forms.
78 bool HasNonRISpills = false;
79
80 /// SpillsCR - Indicates whether CR is spilled in the current function.
81 bool SpillsCR = false;
82
83 /// DisableNonVolatileCR - Indicates whether non-volatile CR fields would be
84 /// disabled.
85 bool DisableNonVolatileCR = false;
86
87 /// LRStoreRequired - The bool indicates whether there is some explicit use of
88 /// the LR/LR8 stack slot that is not obvious from scanning the code. This
89 /// requires that the code generator produce a store of LR to the stack on
90 /// entry, even though LR may otherwise apparently not be used.
91 bool LRStoreRequired = false;
92
93 /// This function makes use of the PPC64 ELF TOC base pointer (register r2).
94 bool UsesTOCBasePtr = false;
95
96 /// MinReservedArea - This is the frame size that is at least reserved in a
97 /// potential caller (parameter+linkage area).
98 unsigned MinReservedArea = 0;
99
100 /// TailCallSPDelta - Stack pointer delta used when tail calling. Maximum
101 /// amount the stack pointer is adjusted to make the frame bigger for tail
102 /// calls. Used for creating an area before the register spill area.
103 int TailCallSPDelta = 0;
104
105 /// HasFastCall - Does this function contain a fast call. Used to determine
106 /// how the caller's stack pointer should be calculated (epilog/dynamicalloc).
107 bool HasFastCall = false;
108
109 /// VarArgsFrameIndex - FrameIndex for start of varargs area.
110 int VarArgsFrameIndex = 0;
111
112 /// VarArgsStackOffset - StackOffset for start of stack
113 /// arguments.
114
115 int VarArgsStackOffset = 0;
116
117 /// VarArgsNumGPR - Index of the first unused integer
118 /// register for parameter passing.
119 unsigned VarArgsNumGPR = 0;
120
121 /// VarArgsNumFPR - Index of the first unused double
122 /// register for parameter passing.
123 unsigned VarArgsNumFPR = 0;
124
125 /// FixedParmsNum - The number of fixed parameters.
126 unsigned FixedParmsNum = 0;
127
128 /// FloatingParmsNum - The number of floating parameters.
129 unsigned FloatingParmsNum = 0;
130
131 /// VectorParmsNum - The number of vector parameters.
132 unsigned VectorParmsNum = 0;
133
134 /// ParamtersType - Store all the parameter's type that are saved on
135 /// registers.
136 SmallVector<ParamType, 32> ParamtersType;
137
138 /// CRSpillFrameIndex - FrameIndex for CR spill slot for 32-bit SVR4.
139 int CRSpillFrameIndex = 0;
140
141 /// If any of CR[2-4] need to be saved in the prologue and restored in the
142 /// epilogue then they are added to this array. This is used for the
143 /// 64-bit SVR4 ABI.
144 SmallVector<Register, 3> MustSaveCRs;
145
146 /// Whether this uses the PIC Base register or not.
147 bool UsesPICBase = false;
148
149 /// We keep track attributes for each live-in virtual registers
150 /// to use SExt/ZExt flags in later optimization.
151 std::vector<std::pair<Register, ISD::ArgFlagsTy>> LiveInAttrs;
152
153public:
154 explicit PPCFunctionInfo(const MachineFunction &MF);
155
156 int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
157 void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
158
159 int getReturnAddrSaveIndex() const { return ReturnAddrSaveIndex; }
160 void setReturnAddrSaveIndex(int idx) { ReturnAddrSaveIndex = idx; }
161
162 int getBasePointerSaveIndex() const { return BasePointerSaveIndex; }
163 void setBasePointerSaveIndex(int Idx) { BasePointerSaveIndex = Idx; }
164
165 int getPICBasePointerSaveIndex() const { return PICBasePointerSaveIndex; }
166 void setPICBasePointerSaveIndex(int Idx) { PICBasePointerSaveIndex = Idx; }
167
168 int getROPProtectionHashSaveIndex() const {
169 return ROPProtectionHashSaveIndex;
170 }
171 void setROPProtectionHashSaveIndex(int Idx) {
172 ROPProtectionHashSaveIndex = Idx;
173 }
174
175 unsigned getMinReservedArea() const { return MinReservedArea; }
176 void setMinReservedArea(unsigned size) { MinReservedArea = size; }
177
178 int getTailCallSPDelta() const { return TailCallSPDelta; }
179 void setTailCallSPDelta(int size) { TailCallSPDelta = size; }
180
181 /// MustSaveLR - This is set when the prolog/epilog inserter does its initial
182 /// scan of the function. It is true if the LR/LR8 register is ever explicitly
183 /// defined/clobbered in the machine function (e.g. by calls and movpctolr,
184 /// which is used in PIC generation), or if the LR stack slot is explicitly
185 /// referenced by builtin_return_address.
186 void setMustSaveLR(bool U) { MustSaveLR = U; }
187 bool mustSaveLR() const { return MustSaveLR; }
188
189 void setMustSaveTOC(bool U) { MustSaveTOC = U; }
190 bool mustSaveTOC() const { return MustSaveTOC; }
191
192 /// We certainly don't want to shrink wrap functions if we've emitted a
193 /// MovePCtoLR8 as that has to go into the entry, so the prologue definitely
194 /// has to go into the entry block.
195 void setShrinkWrapDisabled(bool U) { ShrinkWrapDisabled = U; }
196 bool shrinkWrapDisabled() const { return ShrinkWrapDisabled; }
197
198 void setHasSpills() { HasSpills = true; }
199 bool hasSpills() const { return HasSpills; }
200
201 void setHasNonRISpills() { HasNonRISpills = true; }
202 bool hasNonRISpills() const { return HasNonRISpills; }
203
204 void setSpillsCR() { SpillsCR = true; }
205 bool isCRSpilled() const { return SpillsCR; }
206
207 void setDisableNonVolatileCR() { DisableNonVolatileCR = true; }
208 bool isNonVolatileCRDisabled() const { return DisableNonVolatileCR; }
209
210 void setLRStoreRequired() { LRStoreRequired = true; }
211 bool isLRStoreRequired() const { return LRStoreRequired; }
212
213 void setUsesTOCBasePtr() { UsesTOCBasePtr = true; }
214 bool usesTOCBasePtr() const { return UsesTOCBasePtr; }
215
216 void setHasFastCall() { HasFastCall = true; }
217 bool hasFastCall() const { return HasFastCall;}
218
219 int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
220 void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
221
222 int getVarArgsStackOffset() const { return VarArgsStackOffset; }
223 void setVarArgsStackOffset(int Offset) { VarArgsStackOffset = Offset; }
224
225 unsigned getVarArgsNumGPR() const { return VarArgsNumGPR; }
226 void setVarArgsNumGPR(unsigned Num) { VarArgsNumGPR = Num; }
227
228 unsigned getFixedParmsNum() const { return FixedParmsNum; }
229 unsigned getFloatingPointParmsNum() const { return FloatingParmsNum; }
230 unsigned getVectorParmsNum() const { return VectorParmsNum; }
231 bool hasVectorParms() const { return VectorParmsNum != 0; }
2
Assuming field 'VectorParmsNum' is not equal to 0
3
Returning the value 1, which participates in a condition later
232
233 uint32_t getParmsType() const;
234
235 uint32_t getVecExtParmsType() const;
236
237 void appendParameterType(ParamType Type);
238
239 unsigned getVarArgsNumFPR() const { return VarArgsNumFPR; }
240 void setVarArgsNumFPR(unsigned Num) { VarArgsNumFPR = Num; }
241
242 /// This function associates attributes for each live-in virtual register.
243 void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags) {
244 LiveInAttrs.push_back(std::make_pair(VReg, Flags));
245 }
246
247 /// This function returns true if the specified vreg is
248 /// a live-in register and sign-extended.
249 bool isLiveInSExt(Register VReg) const;
250
251 /// This function returns true if the specified vreg is
252 /// a live-in register and zero-extended.
253 bool isLiveInZExt(Register VReg) const;
254
255 int getCRSpillFrameIndex() const { return CRSpillFrameIndex; }
256 void setCRSpillFrameIndex(int idx) { CRSpillFrameIndex = idx; }
257
258 const SmallVectorImpl<Register> &
259 getMustSaveCRs() const { return MustSaveCRs; }
260 void addMustSaveCR(Register Reg) { MustSaveCRs.push_back(Reg); }
261
262 void setUsesPICBase(bool uses) { UsesPICBase = uses; }
263 bool usesPICBase() const { return UsesPICBase; }
264
265 MCSymbol *getPICOffsetSymbol(MachineFunction &MF) const;
266
267 MCSymbol *getGlobalEPSymbol(MachineFunction &MF) const;
268 MCSymbol *getLocalEPSymbol(MachineFunction &MF) const;
269 MCSymbol *getTOCOffsetSymbol(MachineFunction &MF) const;
270};
271
272} // end namespace llvm
273
274#endif // LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H