/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

Bug Summary

File:	llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
Warning:	line 569, column 10 3rd function call argument is an uninitialized value
Annotated Source Code

Press '?' to see keyboard shortcuts
Show analyzer invocation
clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name R600InstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/lib/Target/AMDGPU -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-09-17-195756-12974-1 -x c++ /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
1//===-- R600InstrInfo.cpp - R600 Instruction Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// R600 Implementation of TargetInstrInfo.
11//
12//===----------------------------------------------------------------------===//

14#include "R600InstrInfo.h"
15#include "AMDGPU.h"
16#include "AMDGPUInstrInfo.h"
17#include "AMDGPUSubtarget.h"
18#include "R600Defines.h"
19#include "R600FrameLowering.h"
20#include "R600RegisterInfo.h"
21#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22#include "Utils/AMDGPUBaseInfo.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/SmallSet.h"
25#include "llvm/ADT/SmallVector.h"
26#include "llvm/CodeGen/MachineBasicBlock.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstr.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineOperand.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/CodeGen/TargetRegisterInfo.h"
34#include "llvm/CodeGen/TargetSubtargetInfo.h"
35#include "llvm/Support/ErrorHandling.h"
36#include <algorithm>
37#include <cassert>
38#include <cstdint>
39#include <cstring>
40#include <iterator>
41#include <utility>
42#include <vector>

44using namespace llvm;

46#define GET_INSTRINFO_CTOR_DTOR
47#include "R600GenDFAPacketizer.inc"

49#define GET_INSTRINFO_CTOR_DTOR
50#define GET_INSTRMAP_INFO
51#define GET_INSTRINFO_NAMED_OPS
52#include "R600GenInstrInfo.inc"

54R600InstrInfo::R600InstrInfo(const R600Subtarget &ST)
: R600GenInstrInfo(-1, -1), RI(), ST(ST) {}

57bool R600InstrInfo::isVector(const MachineInstr &MI) const {
return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
59}

61void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                              MachineBasicBlock::iterator MI,
                              const DebugLoc &DL, MCRegister DestReg,
                              MCRegister SrcReg, bool KillSrc) const {
unsigned VectorComponents = 0;
if ((R600::R600_Reg128RegClass.contains(DestReg) ||
    R600::R600_Reg128VerticalRegClass.contains(DestReg)) &&
    (R600::R600_Reg128RegClass.contains(SrcReg) ||
     R600::R600_Reg128VerticalRegClass.contains(SrcReg))) {
  VectorComponents = 4;
} else if((R600::R600_Reg64RegClass.contains(DestReg) ||
          R600::R600_Reg64VerticalRegClass.contains(DestReg)) &&
          (R600::R600_Reg64RegClass.contains(SrcReg) ||
           R600::R600_Reg64VerticalRegClass.contains(SrcReg))) {
  VectorComponents = 2;
}

if (VectorComponents > 0) {
  for (unsigned I = 0; I < VectorComponents; I++) {
    unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(I);
    buildDefaultInstruction(MBB, MI, R600::MOV,
                            RI.getSubReg(DestReg, SubRegIndex),
                            RI.getSubReg(SrcReg, SubRegIndex))
                            .addReg(DestReg,
                                    RegState::Define | RegState::Implicit);
  }
} else {
  MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV,
                                                DestReg, SrcReg);
  NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0))
                                  .setIsKill(KillSrc);
}
93}

95/// \returns true if \p MBBI can be moved into a new basic.
96bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
                                     MachineBasicBlock::iterator MBBI) const {
for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(),
                                      E = MBBI->operands_end(); I != E; ++I) {
  if (I->isReg() && !I->getReg().isVirtual() && I->isUse() &&
      RI.isPhysRegLiveAcrossClauses(I->getReg()))
    return false;
}
return true;
105}

107bool R600InstrInfo::isMov(unsigned Opcode) const {
switch(Opcode) {
default:
  return false;
case R600::MOV:
case R600::MOV_IMM_F32:
case R600::MOV_IMM_I32:
  return true;
}
116}

118bool R600InstrInfo::isReductionOp(unsigned Opcode) const {
return false;
120}

122bool R600InstrInfo::isCubeOp(unsigned Opcode) const {
switch(Opcode) {
  default: return false;
  case R600::CUBE_r600_pseudo:
  case R600::CUBE_r600_real:
  case R600::CUBE_eg_pseudo:
  case R600::CUBE_eg_real:
    return true;
}
131}

133bool R600InstrInfo::isALUInstr(unsigned Opcode) const {
unsigned TargetFlags = get(Opcode).TSFlags;

return (TargetFlags & R600_InstFlag::ALU_INST);
137}

139bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const {
unsigned TargetFlags = get(Opcode).TSFlags;

return ((TargetFlags & R600_InstFlag::OP1) |
        (TargetFlags & R600_InstFlag::OP2) |
        (TargetFlags & R600_InstFlag::OP3));
145}

147bool R600InstrInfo::isLDSInstr(unsigned Opcode) const {
unsigned TargetFlags = get(Opcode).TSFlags;

return ((TargetFlags & R600_InstFlag::LDS_1A) |
        (TargetFlags & R600_InstFlag::LDS_1A1D) |
        (TargetFlags & R600_InstFlag::LDS_1A2D));
153}

155bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const {
return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1;
157}

159bool R600InstrInfo::canBeConsideredALU(const MachineInstr &MI) const {
if (isALUInstr(MI.getOpcode()))
  return true;
if (isVector(MI) || isCubeOp(MI.getOpcode()))
  return true;
switch (MI.getOpcode()) {
case R600::PRED_X:
case R600::INTERP_PAIR_XY:
case R600::INTERP_PAIR_ZW:
case R600::INTERP_VEC_LOAD:
case R600::COPY:
case R600::DOT_4:
  return true;
default:
  return false;
}
175}

177bool R600InstrInfo::isTransOnly(unsigned Opcode) const {
if (ST.hasCaymanISA())
  return false;
return (get(Opcode).getSchedClass() == R600::Sched::TransALU);
181}

183bool R600InstrInfo::isTransOnly(const MachineInstr &MI) const {
return isTransOnly(MI.getOpcode());
185}

187bool R600InstrInfo::isVectorOnly(unsigned Opcode) const {
return (get(Opcode).getSchedClass() == R600::Sched::VecALU);
189}

191bool R600InstrInfo::isVectorOnly(const MachineInstr &MI) const {
return isVectorOnly(MI.getOpcode());
193}

195bool R600InstrInfo::isExport(unsigned Opcode) const {
return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
197}

199bool R600InstrInfo::usesVertexCache(unsigned Opcode) const {
return ST.hasVertexCache() && IS_VTX(get(Opcode))((get(Opcode)).TSFlags & R600_InstFlag::VTX_INST);
201}

203bool R600InstrInfo::usesVertexCache(const MachineInstr &MI) const {
const MachineFunction *MF = MI.getParent()->getParent();
return !AMDGPU::isCompute(MF->getFunction().getCallingConv()) &&
       usesVertexCache(MI.getOpcode());
207}

209bool R600InstrInfo::usesTextureCache(unsigned Opcode) const {
return (!ST.hasVertexCache() && IS_VTX(get(Opcode))((get(Opcode)).TSFlags & R600_InstFlag::VTX_INST)) || IS_TEX(get(Opcode))((get(Opcode)).TSFlags & R600_InstFlag::TEX_INST);
211}

213bool R600InstrInfo::usesTextureCache(const MachineInstr &MI) const {
const MachineFunction *MF = MI.getParent()->getParent();
return (AMDGPU::isCompute(MF->getFunction().getCallingConv()) &&
        usesVertexCache(MI.getOpcode())) ||
        usesTextureCache(MI.getOpcode());
218}

220bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const {
switch (Opcode) {
case R600::KILLGT:
case R600::GROUP_BARRIER:
  return true;
default:
  return false;
}
228}

230bool R600InstrInfo::usesAddressRegister(MachineInstr &MI) const {
return MI.findRegisterUseOperandIdx(R600::AR_X, false, &RI) != -1;
232}

234bool R600InstrInfo::definesAddressRegister(MachineInstr &MI) const {
return MI.findRegisterDefOperandIdx(R600::AR_X, false, false, &RI) != -1;
236}

238bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const {
if (!isALUInstr(MI.getOpcode())) {
  return false;
}
for (MachineInstr::const_mop_iterator I = MI.operands_begin(),
                                      E = MI.operands_end();
     I != E; ++I) {
  if (!I->isReg() || !I->isUse() || I->getReg().isVirtual())
    continue;

  if (R600::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
    return true;
}
return false;
252}

254int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const {
static const unsigned SrcSelTable[][2] = {
  {R600::OpName::src0, R600::OpName::src0_sel},
  {R600::OpName::src1, R600::OpName::src1_sel},
  {R600::OpName::src2, R600::OpName::src2_sel},
  {R600::OpName::src0_X, R600::OpName::src0_sel_X},
  {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
  {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
  {R600::OpName::src0_W, R600::OpName::src0_sel_W},
  {R600::OpName::src1_X, R600::OpName::src1_sel_X},
  {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
  {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
  {R600::OpName::src1_W, R600::OpName::src1_sel_W}
};

for (const auto &Row : SrcSelTable) {
  if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) {
    return getOperandIdx(Opcode, Row[1]);
  }
}
return -1;
275}

277SmallVector<std::pair<MachineOperand *, int64_t>, 3>
278R600InstrInfo::getSrcs(MachineInstr &MI) const {
SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result;

if (MI.getOpcode() == R600::DOT_4) {
  static const unsigned OpTable[8][2] = {
    {R600::OpName::src0_X, R600::OpName::src0_sel_X},
    {R600::OpName::src0_Y, R600::OpName::src0_sel_Y},
    {R600::OpName::src0_Z, R600::OpName::src0_sel_Z},
    {R600::OpName::src0_W, R600::OpName::src0_sel_W},
    {R600::OpName::src1_X, R600::OpName::src1_sel_X},
    {R600::OpName::src1_Y, R600::OpName::src1_sel_Y},
    {R600::OpName::src1_Z, R600::OpName::src1_sel_Z},
    {R600::OpName::src1_W, R600::OpName::src1_sel_W},
  };

  for (unsigned j = 0; j < 8; j++) {
    MachineOperand &MO =
        MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0]));
    Register Reg = MO.getReg();
    if (Reg == R600::ALU_CONST) {
      MachineOperand &Sel =
          MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
      Result.push_back(std::make_pair(&MO, Sel.getImm()));
      continue;
    }

  }
  return Result;
}

static const unsigned OpTable[3][2] = {
  {R600::OpName::src0, R600::OpName::src0_sel},
  {R600::OpName::src1, R600::OpName::src1_sel},
  {R600::OpName::src2, R600::OpName::src2_sel},
};

for (unsigned j = 0; j < 3; j++) {
  int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]);
  if (SrcIdx < 0)
    break;
  MachineOperand &MO = MI.getOperand(SrcIdx);
  Register Reg = MO.getReg();
  if (Reg == R600::ALU_CONST) {
    MachineOperand &Sel =
        MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1]));
    Result.push_back(std::make_pair(&MO, Sel.getImm()));
    continue;
  }
  if (Reg == R600::ALU_LITERAL_X) {
    MachineOperand &Operand =
        MI.getOperand(getOperandIdx(MI.getOpcode(), R600::OpName::literal));
    if (Operand.isImm()) {
      Result.push_back(std::make_pair(&MO, Operand.getImm()));
      continue;
    }
    assert(Operand.isGlobal())((Operand.isGlobal()) ? static_cast<void> (0) : __assert_fail
 ("Operand.isGlobal()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 333, __PRETTY_FUNCTION__));
  }
  Result.push_back(std::make_pair(&MO, 0));
}
return Result;
338}

340std::vector<std::pair<int, unsigned>>
341R600InstrInfo::ExtractSrcs(MachineInstr &MI,
                         const DenseMap<unsigned, unsigned> &PV,
                         unsigned &ConstCount) const {
ConstCount = 0;
const std::pair<int, unsigned> DummyPair(-1, 0);
std::vector<std::pair<int, unsigned>> Result;
unsigned i = 0;
for (const auto &Src : getSrcs(MI)) {
  ++i;
  Register Reg = Src.first->getReg();
  int Index = RI.getEncodingValue(Reg) & 0xff;
  if (Reg == R600::OQAP) {
    Result.push_back(std::make_pair(Index, 0U));
  }
  if (PV.find(Reg) != PV.end()) {
    // 255 is used to tells its a PS/PV reg
    Result.push_back(std::make_pair(255, 0U));
    continue;
  }
  if (Index > 127) {
    ConstCount++;
    Result.push_back(DummyPair);
    continue;
  }
  unsigned Chan = RI.getHWRegChan(Reg);
  Result.push_back(std::make_pair(Index, Chan));
}
for (; i < 3; ++i)
  Result.push_back(DummyPair);
return Result;
371}

373static std::vector<std::pair<int, unsigned>>
374Swizzle(std::vector<std::pair<int, unsigned>> Src,
      R600InstrInfo::BankSwizzle Swz) {
if (Src[0] == Src[1])
  Src[1].first = -1;
switch (Swz) {
case R600InstrInfo::ALU_VEC_012_SCL_210:
  break;
case R600InstrInfo::ALU_VEC_021_SCL_122:
  std::swap(Src[1], Src[2]);
  break;
case R600InstrInfo::ALU_VEC_102_SCL_221:
  std::swap(Src[0], Src[1]);
  break;
case R600InstrInfo::ALU_VEC_120_SCL_212:
  std::swap(Src[0], Src[1]);
  std::swap(Src[0], Src[2]);
  break;
case R600InstrInfo::ALU_VEC_201:
  std::swap(Src[0], Src[2]);
  std::swap(Src[0], Src[1]);
  break;
case R600InstrInfo::ALU_VEC_210:
  std::swap(Src[0], Src[2]);
  break;
}
return Src;
400}

402static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
assert(Op < 3 && "Out of range swizzle index")((Op < 3 && "Out of range swizzle index") ? static_cast
<void> (0) : __assert_fail ("Op < 3 && \"Out of range swizzle index\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 403, __PRETTY_FUNCTION__));
switch (Swz) {
case R600InstrInfo::ALU_VEC_012_SCL_210: {
  unsigned Cycles[3] = { 2, 1, 0};
  return Cycles[Op];
}
case R600InstrInfo::ALU_VEC_021_SCL_122: {
  unsigned Cycles[3] = { 1, 2, 2};
  return Cycles[Op];
}
case R600InstrInfo::ALU_VEC_120_SCL_212: {
  unsigned Cycles[3] = { 2, 1, 2};
  return Cycles[Op];
}
case R600InstrInfo::ALU_VEC_102_SCL_221: {
  unsigned Cycles[3] = { 2, 2, 1};
  return Cycles[Op];
}
default:
  llvm_unreachable("Wrong Swizzle for Trans Slot")::llvm::llvm_unreachable_internal("Wrong Swizzle for Trans Slot"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 422);
}
424}

426/// returns how many MIs (whose inputs are represented by IGSrcs) can be packed
427/// in the same Instruction Group while meeting read port limitations given a
428/// Swz swizzle sequence.
429unsigned  R600InstrInfo::isLegalUpTo(
  const std::vector<std::vector<std::pair<int, unsigned>>> &IGSrcs,
  const std::vector<R600InstrInfo::BankSwizzle> &Swz,
  const std::vector<std::pair<int, unsigned>> &TransSrcs,
  R600InstrInfo::BankSwizzle TransSwz) const {
int Vector[4][3];
memset(Vector, -1, sizeof(Vector));
for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) {
  const std::vector<std::pair<int, unsigned>> &Srcs =
      Swizzle(IGSrcs[i], Swz[i]);
  for (unsigned j = 0; j < 3; j++) {
    const std::pair<int, unsigned> &Src = Srcs[j];
    if (Src.first < 0 || Src.first == 255)
      continue;
    if (Src.first == GET_REG_INDEX(RI.getEncodingValue(R600::OQAP))((RI.getEncodingValue(R600::OQAP)) & 0x1ff)) {
      if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
          Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
          // The value from output queue A (denoted by register OQAP) can
          // only be fetched during the first cycle.
          return false;
      }
      // OQAP does not count towards the normal read port restrictions
      continue;
    }
    if (Vector[Src.second][j] < 0)
      Vector[Src.second][j] = Src.first;
    if (Vector[Src.second][j] != Src.first)
      return i;
  }
}
// Now check Trans Alu
for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) {
  const std::pair<int, unsigned> &Src = TransSrcs[i];
  unsigned Cycle = getTransSwizzle(TransSwz, i);
  if (Src.first < 0)
    continue;
  if (Src.first == 255)
    continue;
  if (Vector[Src.second][Cycle] < 0)
    Vector[Src.second][Cycle] = Src.first;
  if (Vector[Src.second][Cycle] != Src.first)
    return IGSrcs.size() - 1;
}
return IGSrcs.size();
473}

475/// Given a swizzle sequence SwzCandidate and an index Idx, returns the next
476/// (in lexicographic term) swizzle sequence assuming that all swizzles after
477/// Idx can be skipped
478static bool
479NextPossibleSolution(
  std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
  unsigned Idx) {
assert(Idx < SwzCandidate.size())((Idx < SwzCandidate.size()) ? static_cast<void> (0)
 : __assert_fail ("Idx < SwzCandidate.size()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 482, __PRETTY_FUNCTION__));
int ResetIdx = Idx;
while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210)
  ResetIdx --;
for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) {
  SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210;
}
if (ResetIdx == -1)
  return false;
int NextSwizzle = SwzCandidate[ResetIdx] + 1;
SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
return true;
494}

496/// Enumerate all possible Swizzle sequence to find one that can meet all
497/// read port requirements.
498bool R600InstrInfo::FindSwizzleForVectorSlot(
  const std::vector<std::vector<std::pair<int, unsigned>>> &IGSrcs,
  std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
  const std::vector<std::pair<int, unsigned>> &TransSrcs,
  R600InstrInfo::BankSwizzle TransSwz) const {
unsigned ValidUpTo = 0;
do {
  ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz);
  if (ValidUpTo == IGSrcs.size())
    return true;
} while (NextPossibleSolution(SwzCandidate, ValidUpTo));
return false;
510}

512/// Instructions in Trans slot can't read gpr at cycle 0 if they also read
513/// a const, and can't read a gpr at cycle 1 if they read 2 const.
514static bool
515isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
                const std::vector<std::pair<int, unsigned>> &TransOps,
                unsigned ConstCount) {
// TransALU can't read 3 constants
if (ConstCount > 2)
  return false;
for (unsigned i = 0, e = TransOps.size(); i < e; ++i) {
  const std::pair<int, unsigned> &Src = TransOps[i];
  unsigned Cycle = getTransSwizzle(TransSwz, i);
  if (Src.first < 0)
    continue;
  if (ConstCount > 0 && Cycle == 0)
    return false;
  if (ConstCount > 1 && Cycle == 1)
    return false;
}
return true;
532}

534bool
535R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG,
                                     const DenseMap<unsigned, unsigned> &PV,
                                     std::vector<BankSwizzle> &ValidSwizzle,
                                     bool isLastAluTrans)
  const {
//Todo : support shared src0 - src1 operand

std::vector<std::vector<std::pair<int, unsigned>>> IGSrcs;
ValidSwizzle.clear();
unsigned ConstCount;
1
'ConstCount' declared without an initial value→
BankSwizzle TransBS = ALU_VEC_012_SCL_210;
for (unsigned i = 0, e = IG.size(); i < e; ++i) {
2
←
Assuming 'i' is >= 'e'→
3
←
Loop condition is false. Execution continues on line 553→
  IGSrcs.push_back(ExtractSrcs(*IG[i], PV, ConstCount));
  unsigned Op = getOperandIdx(IG[i]->getOpcode(),
      R600::OpName::bank_swizzle);
  ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle)
      IG[i]->getOperand(Op).getImm());
}
std::vector<std::pair<int, unsigned>> TransOps;
if (!isLastAluTrans)
4
←
Assuming 'isLastAluTrans' is true→
5
←
Taking false branch→
  return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS);

TransOps = std::move(IGSrcs.back());
IGSrcs.pop_back();
ValidSwizzle.pop_back();

static const R600InstrInfo::BankSwizzle TransSwz[] = {
  ALU_VEC_012_SCL_210,
  ALU_VEC_021_SCL_122,
  ALU_VEC_120_SCL_212,
  ALU_VEC_102_SCL_221
};
for (unsigned i = 0; i < 4; i++) {
6
←
Loop condition is true.  Entering loop body→
  TransBS = TransSwz[i];
  if (!isConstCompatible(TransBS, TransOps, ConstCount))
7
←
3rd function call argument is an uninitialized value
    continue;
  bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps,
      TransBS);
  if (Result) {
    ValidSwizzle.push_back(TransBS);
    return true;
  }
}

return false;
580}

582bool
583R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts)
  const {
assert (Consts.size() <= 12 && "Too many operands in instructions group")((Consts.size() <= 12 && "Too many operands in instructions group"
) ? static_cast<void> (0) : __assert_fail ("Consts.size() <= 12 && \"Too many operands in instructions group\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 585, __PRETTY_FUNCTION__));
unsigned Pair1 = 0, Pair2 = 0;
for (unsigned i = 0, n = Consts.size(); i < n; ++i) {
  unsigned ReadConstHalf = Consts[i] & 2;
  unsigned ReadConstIndex = Consts[i] & (~3);
  unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf;
  if (!Pair1) {
    Pair1 = ReadHalfConst;
    continue;
  }
  if (Pair1 == ReadHalfConst)
    continue;
  if (!Pair2) {
    Pair2 = ReadHalfConst;
    continue;
  }
  if (Pair2 != ReadHalfConst)
    return false;
}
return true;
605}

607bool
608R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs)
  const {
std::vector<unsigned> Consts;
SmallSet<int64_t, 4> Literals;
for (unsigned i = 0, n = MIs.size(); i < n; i++) {
  MachineInstr &MI = *MIs[i];
  if (!isALUInstr(MI.getOpcode()))
    continue;

  for (const auto &Src : getSrcs(MI)) {
    if (Src.first->getReg() == R600::ALU_LITERAL_X)
      Literals.insert(Src.second);
    if (Literals.size() > 4)
      return false;
    if (Src.first->getReg() == R600::ALU_CONST)
      Consts.push_back(Src.second);
    if (R600::R600_KC0RegClass.contains(Src.first->getReg()) ||
        R600::R600_KC1RegClass.contains(Src.first->getReg())) {
      unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
      unsigned Chan = RI.getHWRegChan(Src.first->getReg());
      Consts.push_back((Index << 2) | Chan);
    }
  }
}
return fitsConstReadLimitations(Consts);
633}

635DFAPacketizer *
636R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const {
const InstrItineraryData *II = STI.getInstrItineraryData();
return static_cast<const R600Subtarget &>(STI).createDFAPacketizer(II);
639}

641static bool
642isPredicateSetter(unsigned Opcode) {
switch (Opcode) {
case R600::PRED_X:
  return true;
default:
  return false;
}
649}

651static MachineInstr *
652findFirstPredicateSetterFrom(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator I) {
while (I != MBB.begin()) {
  --I;
  MachineInstr &MI = *I;
  if (isPredicateSetter(MI.getOpcode()))
    return &MI;
}

return nullptr;
662}

664static
665bool isJump(unsigned Opcode) {
return Opcode == R600::JUMP || Opcode == R600::JUMP_COND;
667}

669static bool isBranch(unsigned Opcode) {
return Opcode == R600::BRANCH || Opcode == R600::BRANCH_COND_i32 ||
    Opcode == R600::BRANCH_COND_f32;
672}

674bool R600InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                MachineBasicBlock *&TBB,
                                MachineBasicBlock *&FBB,
                                SmallVectorImpl<MachineOperand> &Cond,
                                bool AllowModify) const {
// Most of the following comes from the ARM implementation of analyzeBranch

// If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
if (I == MBB.end())
  return false;

// R600::BRANCH* instructions are only available after isel and are not
// handled
if (isBranch(I->getOpcode()))
  return true;
if (!isJump(I->getOpcode())) {
  return false;
}

// Remove successive JUMP
while (I != MBB.begin() && std::prev(I)->getOpcode() == R600::JUMP) {
    MachineBasicBlock::iterator PriorI = std::prev(I);
    if (AllowModify)
      I->removeFromParent();
    I = PriorI;
}
MachineInstr &LastInst = *I;

// If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst.getOpcode();
if (I == MBB.begin() || !isJump((--I)->getOpcode())) {
  if (LastOpc == R600::JUMP) {
    TBB = LastInst.getOperand(0).getMBB();
    return false;
  } else if (LastOpc == R600::JUMP_COND) {
    auto predSet = I;
    while (!isPredicateSetter(predSet->getOpcode())) {
      predSet = --I;
    }
    TBB = LastInst.getOperand(0).getMBB();
    Cond.push_back(predSet->getOperand(1));
    Cond.push_back(predSet->getOperand(2));
    Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false));
    return false;
  }
  return true;  // Can't handle indirect branch.
}

// Get the instruction before it if it is a terminator.
MachineInstr &SecondLastInst = *I;
unsigned SecondLastOpc = SecondLastInst.getOpcode();

// If the block ends with a B and a Bcc, handle it.
if (SecondLastOpc == R600::JUMP_COND && LastOpc == R600::JUMP) {
  auto predSet = --I;
  while (!isPredicateSetter(predSet->getOpcode())) {
    predSet = --I;
  }
  TBB = SecondLastInst.getOperand(0).getMBB();
  FBB = LastInst.getOperand(0).getMBB();
  Cond.push_back(predSet->getOperand(1));
  Cond.push_back(predSet->getOperand(2));
  Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false));
  return false;
}

// Otherwise, can't handle this.
return true;
743}

745static
746MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) {
for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
    It != E; ++It) {
  if (It->getOpcode() == R600::CF_ALU ||
      It->getOpcode() == R600::CF_ALU_PUSH_BEFORE)
    return It.getReverse();
}
return MBB.end();
754}

756unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB,
                                   MachineBasicBlock *TBB,
                                   MachineBasicBlock *FBB,
                                   ArrayRef<MachineOperand> Cond,
                                   const DebugLoc &DL,
                                   int *BytesAdded) const {
assert(TBB && "insertBranch must not be told to insert a fallthrough")((TBB && "insertBranch must not be told to insert a fallthrough"
) ? static_cast<void> (0) : __assert_fail ("TBB && \"insertBranch must not be told to insert a fallthrough\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 762, __PRETTY_FUNCTION__));
assert(!BytesAdded && "code size not handled")((!BytesAdded && "code size not handled") ? static_cast
<void> (0) : __assert_fail ("!BytesAdded && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 763, __PRETTY_FUNCTION__));

if (!FBB) {
  if (Cond.empty()) {
    BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB);
    return 1;
  } else {
    MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
    assert(PredSet && "No previous predicate !")((PredSet && "No previous predicate !") ? static_cast
<void> (0) : __assert_fail ("PredSet && \"No previous predicate !\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 771, __PRETTY_FUNCTION__));
    addFlag(*PredSet, 0, MO_FLAG_PUSH(1 << 4));
    PredSet->getOperand(2).setImm(Cond[1].getImm());

    BuildMI(&MBB, DL, get(R600::JUMP_COND))
           .addMBB(TBB)
           .addReg(R600::PREDICATE_BIT, RegState::Kill);
    MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
    if (CfAlu == MBB.end())
      return 1;
    assert (CfAlu->getOpcode() == R600::CF_ALU)((CfAlu->getOpcode() == R600::CF_ALU) ? static_cast<void
> (0) : __assert_fail ("CfAlu->getOpcode() == R600::CF_ALU"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 781, __PRETTY_FUNCTION__));
    CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
    return 1;
  }
} else {
  MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
  assert(PredSet && "No previous predicate !")((PredSet && "No previous predicate !") ? static_cast
<void> (0) : __assert_fail ("PredSet && \"No previous predicate !\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 787, __PRETTY_FUNCTION__));
  addFlag(*PredSet, 0, MO_FLAG_PUSH(1 << 4));
  PredSet->getOperand(2).setImm(Cond[1].getImm());
  BuildMI(&MBB, DL, get(R600::JUMP_COND))
          .addMBB(TBB)
          .addReg(R600::PREDICATE_BIT, RegState::Kill);
  BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB);
  MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
  if (CfAlu == MBB.end())
    return 2;
  assert (CfAlu->getOpcode() == R600::CF_ALU)((CfAlu->getOpcode() == R600::CF_ALU) ? static_cast<void
> (0) : __assert_fail ("CfAlu->getOpcode() == R600::CF_ALU"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 797, __PRETTY_FUNCTION__));
  CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE));
  return 2;
}
801}

803unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB,
                                   int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled")((!BytesRemoved && "code size not handled") ? static_cast
<void> (0) : __assert_fail ("!BytesRemoved && \"code size not handled\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 805, __PRETTY_FUNCTION__));

// Note : we leave PRED* instructions there.
// They may be needed when predicating instructions.

MachineBasicBlock::iterator I = MBB.end();

if (I == MBB.begin()) {
  return 0;
}
--I;
switch (I->getOpcode()) {
default:
  return 0;
case R600::JUMP_COND: {
  MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
  clearFlag(*predSet, 0, MO_FLAG_PUSH(1 << 4));
  I->eraseFromParent();
  MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
  if (CfAlu == MBB.end())
    break;
  assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE)((CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE) ? static_cast
<void> (0) : __assert_fail ("CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 826, __PRETTY_FUNCTION__));
  CfAlu->setDesc(get(R600::CF_ALU));
  break;
}
case R600::JUMP:
  I->eraseFromParent();
  break;
}
I = MBB.end();

if (I == MBB.begin()) {
  return 1;
}
--I;
switch (I->getOpcode()) {
  // FIXME: only one case??
default:
  return 1;
case R600::JUMP_COND: {
  MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
  clearFlag(*predSet, 0, MO_FLAG_PUSH(1 << 4));
  I->eraseFromParent();
  MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB);
  if (CfAlu == MBB.end())
    break;
  assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE)((CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE) ? static_cast
<void> (0) : __assert_fail ("CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 851, __PRETTY_FUNCTION__));
  CfAlu->setDesc(get(R600::CF_ALU));
  break;
}
case R600::JUMP:
  I->eraseFromParent();
  break;
}
return 2;
860}

862bool R600InstrInfo::isPredicated(const MachineInstr &MI) const {
int idx = MI.findFirstPredOperandIdx();
if (idx < 0)
  return false;

Register Reg = MI.getOperand(idx).getReg();
switch (Reg) {
default: return false;
case R600::PRED_SEL_ONE:
case R600::PRED_SEL_ZERO:
case R600::PREDICATE_BIT:
  return true;
}
875}

877bool R600InstrInfo::isPredicable(const MachineInstr &MI) const {
// XXX: KILL* instructions can be predicated, but they must be the last
// instruction in a clause, so this means any instructions after them cannot
// be predicated.  Until we have proper support for instruction clauses in the
// backend, we will mark KILL* instructions as unpredicable.

if (MI.getOpcode() == R600::KILLGT) {
  return false;
} else if (MI.getOpcode() == R600::CF_ALU) {
  // If the clause start in the middle of MBB then the MBB has more
  // than a single clause, unable to predicate several clauses.
  if (MI.getParent()->begin() != MachineBasicBlock::const_iterator(MI))
    return false;
  // TODO: We don't support KC merging atm
  return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0;
} else if (isVector(MI)) {
  return false;
} else {
  return TargetInstrInfo::isPredicable(MI);
}
897}

899bool
900R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
                                 unsigned NumCycles,
                                 unsigned ExtraPredCycles,
                                 BranchProbability Probability) const{
return true;
905}

907bool
908R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
                                 unsigned NumTCycles,
                                 unsigned ExtraTCycles,
                                 MachineBasicBlock &FMBB,
                                 unsigned NumFCycles,
                                 unsigned ExtraFCycles,
                                 BranchProbability Probability) const {
return true;
916}

918bool
919R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
                                       unsigned NumCycles,
                                       BranchProbability Probability)
                                       const {
return true;
924}

926bool
927R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
                                       MachineBasicBlock &FMBB) const {
return false;
930}

932bool
933R600InstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
MachineOperand &MO = Cond[1];
switch (MO.getImm()) {
case R600::PRED_SETE_INT:
  MO.setImm(R600::PRED_SETNE_INT);
  break;
case R600::PRED_SETNE_INT:
  MO.setImm(R600::PRED_SETE_INT);
  break;
case R600::PRED_SETE:
  MO.setImm(R600::PRED_SETNE);
  break;
case R600::PRED_SETNE:
  MO.setImm(R600::PRED_SETE);
  break;
default:
  return true;
}

MachineOperand &MO2 = Cond[2];
switch (MO2.getReg()) {
case R600::PRED_SEL_ZERO:
  MO2.setReg(R600::PRED_SEL_ONE);
  break;
case R600::PRED_SEL_ONE:
  MO2.setReg(R600::PRED_SEL_ZERO);
  break;
default:
  return true;
}
return false;
964}

966bool R600InstrInfo::DefinesPredicate(MachineInstr &MI,
                                   std::vector<MachineOperand> &Pred) const {
return isPredicateSetter(MI.getOpcode());
969}

971bool R600InstrInfo::PredicateInstruction(MachineInstr &MI,
                                       ArrayRef<MachineOperand> Pred) const {
int PIdx = MI.findFirstPredOperandIdx();

if (MI.getOpcode() == R600::CF_ALU) {
  MI.getOperand(8).setImm(0);
  return true;
}

if (MI.getOpcode() == R600::DOT_4) {
  MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_X))
      .setReg(Pred[2].getReg());
  MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_Y))
      .setReg(Pred[2].getReg());
  MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_Z))
      .setReg(Pred[2].getReg());
  MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_W))
      .setReg(Pred[2].getReg());
  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
  MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit);
  return true;
}

if (PIdx != -1) {
  MachineOperand &PMO = MI.getOperand(PIdx);
  PMO.setReg(Pred[2].getReg());
  MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
  MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit);
  return true;
}

return false;
1003}

1005unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const {
return 2;
1007}

1009unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
                                          const MachineInstr &,
                                          unsigned *PredCost) const {
if (PredCost)
  *PredCost = 2;
return 2;
1015}

1017unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex,
                                                 unsigned Channel) const {
assert(Channel == 0)((Channel == 0) ? static_cast<void> (0) : __assert_fail
 ("Channel == 0", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1019, __PRETTY_FUNCTION__));
return RegIndex;
1021}

1023bool R600InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
switch (MI.getOpcode()) {
default: {
  MachineBasicBlock *MBB = MI.getParent();
  int OffsetOpIdx =
      R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::addr);
  // addr is a custom operand with multiple MI operands, and only the
  // first MI operand is given a name.
  int RegOpIdx = OffsetOpIdx + 1;
  int ChanOpIdx =
      R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::chan);
  if (isRegisterLoad(MI)) {
    int DstOpIdx =
        R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::dst);
    unsigned RegIndex = MI.getOperand(RegOpIdx).getImm();
    unsigned Channel = MI.getOperand(ChanOpIdx).getImm();
    unsigned Address = calculateIndirectAddress(RegIndex, Channel);
    Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
    if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
      buildMovInstr(MBB, MI, MI.getOperand(DstOpIdx).getReg(),
                    getIndirectAddrRegClass()->getRegister(Address));
    } else {
      buildIndirectRead(MBB, MI, MI.getOperand(DstOpIdx).getReg(), Address,
                        OffsetReg);
    }
  } else if (isRegisterStore(MI)) {
    int ValOpIdx =
        R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::val);
    unsigned RegIndex = MI.getOperand(RegOpIdx).getImm();
    unsigned Channel = MI.getOperand(ChanOpIdx).getImm();
    unsigned Address = calculateIndirectAddress(RegIndex, Channel);
    Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
    if (OffsetReg == R600::INDIRECT_BASE_ADDR) {
      buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address),
                    MI.getOperand(ValOpIdx).getReg());
    } else {
      buildIndirectWrite(MBB, MI, MI.getOperand(ValOpIdx).getReg(),
                         calculateIndirectAddress(RegIndex, Channel),
                         OffsetReg);
    }
  } else {
    return false;
  }

  MBB->erase(MI);
  return true;
}
case R600::R600_EXTRACT_ELT_V2:
case R600::R600_EXTRACT_ELT_V4:
  buildIndirectRead(MI.getParent(), MI, MI.getOperand(0).getReg(),
                    RI.getHWRegIndex(MI.getOperand(1).getReg()), //  Address
                    MI.getOperand(2).getReg(),
                    RI.getHWRegChan(MI.getOperand(1).getReg()));
  break;
case R600::R600_INSERT_ELT_V2:
case R600::R600_INSERT_ELT_V4:
  buildIndirectWrite(MI.getParent(), MI, MI.getOperand(2).getReg(), // Value
                     RI.getHWRegIndex(MI.getOperand(1).getReg()),   // Address
                     MI.getOperand(3).getReg(),                     // Offset
                     RI.getHWRegChan(MI.getOperand(1).getReg()));   // Channel
  break;
}
MI.eraseFromParent();
return true;
1087}

1089void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
                                           const MachineFunction &MF,
                                           const R600RegisterInfo &TRI) const {
const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
const R600FrameLowering *TFL = ST.getFrameLowering();

unsigned StackWidth = TFL->getStackWidth(MF);
int End = getIndirectIndexEnd(MF);

if (End == -1)
  return;

for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
  for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
    unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
    TRI.reserveRegisterTuples(Reserved, Reg);
  }
}
1107}

1109const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
return &R600::R600_TReg32_XRegClass;
1111}

1113MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
                                     MachineBasicBlock::iterator I,
                                     unsigned ValueReg, unsigned Address,
                                     unsigned OffsetReg) const {
return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0);
1118}

1120MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
                                     MachineBasicBlock::iterator I,
                                     unsigned ValueReg, unsigned Address,
                                     unsigned OffsetReg,
                                     unsigned AddrChan) const {
unsigned AddrReg;
switch (AddrChan) {
  default: llvm_unreachable("Invalid Channel")::llvm::llvm_unreachable_internal("Invalid Channel", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1127);
  case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
  case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
  case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break;
  case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break;
}
MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, R600::MOVA_INT_eg,
                                             R600::AR_X, OffsetReg);
setImmOperand(*MOVA, R600::OpName::write, 0);

MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV,
                                    AddrReg, ValueReg)
                                    .addReg(R600::AR_X,
                                         RegState::Implicit | RegState::Kill);
setImmOperand(*Mov, R600::OpName::dst_rel, 1);
return Mov;
1143}

1145MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
                                     MachineBasicBlock::iterator I,
                                     unsigned ValueReg, unsigned Address,
                                     unsigned OffsetReg) const {
return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0);
1150}

1152MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
                                     MachineBasicBlock::iterator I,
                                     unsigned ValueReg, unsigned Address,
                                     unsigned OffsetReg,
                                     unsigned AddrChan) const {
unsigned AddrReg;
switch (AddrChan) {
  default: llvm_unreachable("Invalid Channel")::llvm::llvm_unreachable_internal("Invalid Channel", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1159);
  case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
  case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
  case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break;
  case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break;
}
MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, R600::MOVA_INT_eg,
                                                     R600::AR_X,
                                                     OffsetReg);
setImmOperand(*MOVA, R600::OpName::write, 0);
MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV,
                                    ValueReg,
                                    AddrReg)
                                    .addReg(R600::AR_X,
                                         RegState::Implicit | RegState::Kill);
setImmOperand(*Mov, R600::OpName::src0_rel, 1);

return Mov;
1177}

1179int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
const MachineRegisterInfo &MRI = MF.getRegInfo();
const MachineFrameInfo &MFI = MF.getFrameInfo();
int Offset = -1;

if (MFI.getNumObjects() == 0) {
  return -1;
}

if (MRI.livein_empty()) {
  return 0;
}

const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
for (std::pair<unsigned, unsigned> LI : MRI.liveins()) {
  Register Reg = LI.first;
  if (Reg.isVirtual() || !IndirectRC->contains(Reg))
    continue;

  unsigned RegIndex;
  unsigned RegEnd;
  for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd;
                                                        ++RegIndex) {
    if (IndirectRC->getRegister(RegIndex) == (unsigned)Reg)
      break;
  }
  Offset = std::max(Offset, (int)RegIndex);
}

return Offset + 1;
1209}

1211int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
int Offset = 0;
const MachineFrameInfo &MFI = MF.getFrameInfo();

// Variable sized objects are not supported
if (MFI.hasVarSizedObjects()) {
  return -1;
}

if (MFI.getNumObjects() == 0) {
  return -1;
}

const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
const R600FrameLowering *TFL = ST.getFrameLowering();

Register IgnoredFrameReg;
Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg);

return getIndirectIndexBegin(MF) + Offset;
1231}

1233unsigned R600InstrInfo::getMaxAlusPerClause() const {
return 115;
1235}

1237MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
                                                MachineBasicBlock::iterator I,
                                                unsigned Opcode,
                                                unsigned DstReg,
                                                unsigned Src0Reg,
                                                unsigned Src1Reg) const {
MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
  DstReg);           // $dst

if (Src1Reg) {
  MIB.addImm(0)     // $update_exec_mask
     .addImm(0);    // $update_predicate
}
MIB.addImm(1)        // $write
   .addImm(0)        // $omod
   .addImm(0)        // $dst_rel
   .addImm(0)        // $dst_clamp
   .addReg(Src0Reg)  // $src0
   .addImm(0)        // $src0_neg
   .addImm(0)        // $src0_rel
   .addImm(0)        // $src0_abs
   .addImm(-1);       // $src0_sel

if (Src1Reg) {
  MIB.addReg(Src1Reg) // $src1
     .addImm(0)       // $src1_neg
     .addImm(0)       // $src1_rel
     .addImm(0)       // $src1_abs
     .addImm(-1);      // $src1_sel
}

//XXX: The r600g finalizer expects this to be 1, once we've moved the
//scheduling to the backend, we can change the default to 0.
MIB.addImm(1)        // $last
    .addReg(R600::PRED_SEL_OFF) // $pred_sel
    .addImm(0)         // $literal
    .addImm(0);        // $bank_swizzle

return MIB;
1276}

1278#define OPERAND_CASE(Label) \
case Label: { \
  static const unsigned Ops[] = \
  { \
    Label##_X, \
    Label##_Y, \
    Label##_Z, \
    Label##_W \
  }; \
  return Ops[Slot]; \
}

1290static unsigned getSlotedOps(unsigned  Op, unsigned Slot) {
switch (Op) {
OPERAND_CASE(R600::OpName::update_exec_mask)
OPERAND_CASE(R600::OpName::update_pred)
OPERAND_CASE(R600::OpName::write)
OPERAND_CASE(R600::OpName::omod)
OPERAND_CASE(R600::OpName::dst_rel)
OPERAND_CASE(R600::OpName::clamp)
OPERAND_CASE(R600::OpName::src0)
OPERAND_CASE(R600::OpName::src0_neg)
OPERAND_CASE(R600::OpName::src0_rel)
OPERAND_CASE(R600::OpName::src0_abs)
OPERAND_CASE(R600::OpName::src0_sel)
OPERAND_CASE(R600::OpName::src1)
OPERAND_CASE(R600::OpName::src1_neg)
OPERAND_CASE(R600::OpName::src1_rel)
OPERAND_CASE(R600::OpName::src1_abs)
OPERAND_CASE(R600::OpName::src1_sel)
OPERAND_CASE(R600::OpName::pred_sel)
default:
  llvm_unreachable("Wrong Operand")::llvm::llvm_unreachable_internal("Wrong Operand", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1310);
}
1312}

1314#undef OPERAND_CASE

1316MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction(
  MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg)
  const {
assert (MI->getOpcode() == R600::DOT_4 && "Not Implemented")((MI->getOpcode() == R600::DOT_4 && "Not Implemented"
) ? static_cast<void> (0) : __assert_fail ("MI->getOpcode() == R600::DOT_4 && \"Not Implemented\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1319, __PRETTY_FUNCTION__));
unsigned Opcode;
if (ST.getGeneration() <= AMDGPUSubtarget::R700)
  Opcode = R600::DOT4_r600;
else
  Opcode = R600::DOT4_eg;
MachineBasicBlock::iterator I = MI;
MachineOperand &Src0 = MI->getOperand(
    getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src0, Slot)));
MachineOperand &Src1 = MI->getOperand(
    getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src1, Slot)));
MachineInstr *MIB = buildDefaultInstruction(
    MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
static const unsigned  Operands[14] = {
  R600::OpName::update_exec_mask,
  R600::OpName::update_pred,
  R600::OpName::write,
  R600::OpName::omod,
  R600::OpName::dst_rel,
  R600::OpName::clamp,
  R600::OpName::src0_neg,
  R600::OpName::src0_rel,
  R600::OpName::src0_abs,
  R600::OpName::src0_sel,
  R600::OpName::src1_neg,
  R600::OpName::src1_rel,
  R600::OpName::src1_abs,
  R600::OpName::src1_sel,
};

MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(),
    getSlotedOps(R600::OpName::pred_sel, Slot)));
MIB->getOperand(getOperandIdx(Opcode, R600::OpName::pred_sel))
    .setReg(MO.getReg());

for (unsigned i = 0; i < 14; i++) {
  MachineOperand &MO = MI->getOperand(
      getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot)));
  assert (MO.isImm())((MO.isImm()) ? static_cast<void> (0) : __assert_fail (
"MO.isImm()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1357, __PRETTY_FUNCTION__));
  setImmOperand(*MIB, Operands[i], MO.getImm());
}
MIB->getOperand(20).setImm(0);
return MIB;
1362}

1364MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB,
                                       MachineBasicBlock::iterator I,
                                       unsigned DstReg,
                                       uint64_t Imm) const {
MachineInstr *MovImm = buildDefaultInstruction(BB, I, R600::MOV, DstReg,
                                                R600::ALU_LITERAL_X);
setImmOperand(*MovImm, R600::OpName::literal, Imm);
return MovImm;
1372}

1374MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB,
                                     MachineBasicBlock::iterator I,
                                     unsigned DstReg, unsigned SrcReg) const {
return buildDefaultInstruction(*MBB, I, R600::MOV, DstReg, SrcReg);
1378}

1380int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const {
return getOperandIdx(MI.getOpcode(), Op);
1382}

1384int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const {
return R600::getNamedOperandIdx(Opcode, Op);
1386}

1388void R600InstrInfo::setImmOperand(MachineInstr &MI, unsigned Op,
                                int64_t Imm) const {
int Idx = getOperandIdx(MI, Op);
assert(Idx != -1 && "Operand not supported for this instruction.")((Idx != -1 && "Operand not supported for this instruction."
) ? static_cast<void> (0) : __assert_fail ("Idx != -1 && \"Operand not supported for this instruction.\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1391, __PRETTY_FUNCTION__));
assert(MI.getOperand(Idx).isImm())((MI.getOperand(Idx).isImm()) ? static_cast<void> (0) :
 __assert_fail ("MI.getOperand(Idx).isImm()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1392, __PRETTY_FUNCTION__));
MI.getOperand(Idx).setImm(Imm);
1394}

1396//===----------------------------------------------------------------------===//
1397// Instruction flag getters/setters
1398//===----------------------------------------------------------------------===//

1400MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx,
                                       unsigned Flag) const {
unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
int FlagIndex = 0;
if (Flag != 0) {
  // If we pass something other than the default value of Flag to this
  // function, it means we are want to set a flag on an instruction
  // that uses native encoding.
  assert(HAS_NATIVE_OPERANDS(TargetFlags))((((TargetFlags) & R600_InstFlag::NATIVE_OPERANDS)) ? static_cast
<void> (0) : __assert_fail ("HAS_NATIVE_OPERANDS(TargetFlags)"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1408, __PRETTY_FUNCTION__));
  bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3;
  switch (Flag) {
  case MO_FLAG_CLAMP(1 << 0):
    FlagIndex = getOperandIdx(MI, R600::OpName::clamp);
    break;
  case MO_FLAG_MASK(1 << 3):
    FlagIndex = getOperandIdx(MI, R600::OpName::write);
    break;
  case MO_FLAG_NOT_LAST(1 << 5):
  case MO_FLAG_LAST(1 << 6):
    FlagIndex = getOperandIdx(MI, R600::OpName::last);
    break;
  case MO_FLAG_NEG(1 << 1):
    switch (SrcIdx) {
    case 0:
      FlagIndex = getOperandIdx(MI, R600::OpName::src0_neg);
      break;
    case 1:
      FlagIndex = getOperandIdx(MI, R600::OpName::src1_neg);
      break;
    case 2:
      FlagIndex = getOperandIdx(MI, R600::OpName::src2_neg);
      break;
    }
    break;

  case MO_FLAG_ABS(1 << 2):
    assert(!IsOP3 && "Cannot set absolute value modifier for OP3 "((!IsOP3 && "Cannot set absolute value modifier for OP3 "
 "instructions.") ? static_cast<void> (0) : __assert_fail
 ("!IsOP3 && \"Cannot set absolute value modifier for OP3 \" \"instructions.\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1437, __PRETTY_FUNCTION__))
                     "instructions.")((!IsOP3 && "Cannot set absolute value modifier for OP3 "
 "instructions.") ? static_cast<void> (0) : __assert_fail
 ("!IsOP3 && \"Cannot set absolute value modifier for OP3 \" \"instructions.\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1437, __PRETTY_FUNCTION__));
    (void)IsOP3;
    switch (SrcIdx) {
    case 0:
      FlagIndex = getOperandIdx(MI, R600::OpName::src0_abs);
      break;
    case 1:
      FlagIndex = getOperandIdx(MI, R600::OpName::src1_abs);
      break;
    }
    break;

  default:
    FlagIndex = -1;
    break;
  }
  assert(FlagIndex != -1 && "Flag not supported for this instruction")((FlagIndex != -1 && "Flag not supported for this instruction"
) ? static_cast<void> (0) : __assert_fail ("FlagIndex != -1 && \"Flag not supported for this instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1453, __PRETTY_FUNCTION__));
} else {
    FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags)(((TargetFlags) >> 7) & 0x3);
    assert(FlagIndex != 0 &&((FlagIndex != 0 && "Instruction flags not supported for this instruction"
) ? static_cast<void> (0) : __assert_fail ("FlagIndex != 0 && \"Instruction flags not supported for this instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1457, __PRETTY_FUNCTION__))
       "Instruction flags not supported for this instruction")((FlagIndex != 0 && "Instruction flags not supported for this instruction"
) ? static_cast<void> (0) : __assert_fail ("FlagIndex != 0 && \"Instruction flags not supported for this instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1457, __PRETTY_FUNCTION__));
}

MachineOperand &FlagOp = MI.getOperand(FlagIndex);
assert(FlagOp.isImm())((FlagOp.isImm()) ? static_cast<void> (0) : __assert_fail
 ("FlagOp.isImm()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1461, __PRETTY_FUNCTION__));
return FlagOp;
1463}

1465void R600InstrInfo::addFlag(MachineInstr &MI, unsigned Operand,
                          unsigned Flag) const {
unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
if (Flag == 0) {
  return;
}
if (HAS_NATIVE_OPERANDS(TargetFlags)((TargetFlags) & R600_InstFlag::NATIVE_OPERANDS)) {
  MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
  if (Flag == MO_FLAG_NOT_LAST(1 << 5)) {
    clearFlag(MI, Operand, MO_FLAG_LAST(1 << 6));
  } else if (Flag == MO_FLAG_MASK(1 << 3)) {
    clearFlag(MI, Operand, Flag);
  } else {
    FlagOp.setImm(1);
  }
} else {
    MachineOperand &FlagOp = getFlagOp(MI, Operand);
    FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS7 * Operand)));
}
1484}

1486void R600InstrInfo::clearFlag(MachineInstr &MI, unsigned Operand,
                            unsigned Flag) const {
unsigned TargetFlags = get(MI.getOpcode()).TSFlags;
if (HAS_NATIVE_OPERANDS(TargetFlags)((TargetFlags) & R600_InstFlag::NATIVE_OPERANDS)) {
  MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag);
  FlagOp.setImm(0);
} else {
  MachineOperand &FlagOp = getFlagOp(MI);
  unsigned InstFlags = FlagOp.getImm();
  InstFlags &= ~(Flag << (NUM_MO_FLAGS7 * Operand));
  FlagOp.setImm(InstFlags);
}
1498}

1500unsigned R600InstrInfo::getAddressSpaceForPseudoSourceKind(
  unsigned Kind) const {
switch (Kind) {
case PseudoSourceValue::Stack:
case PseudoSourceValue::FixedStack:
  return AMDGPUAS::PRIVATE_ADDRESS;
case PseudoSourceValue::ConstantPool:
case PseudoSourceValue::GOT:
case PseudoSourceValue::JumpTable:
case PseudoSourceValue::GlobalValueCallEntry:
case PseudoSourceValue::ExternalSymbolCallEntry:
case PseudoSourceValue::TargetCustom:
  return AMDGPUAS::CONSTANT_ADDRESS;
}

llvm_unreachable("Invalid pseudo source kind")::llvm::llvm_unreachable_internal("Invalid pseudo source kind"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp"
, 1515);
1516}