/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp

Bug Summary

File:	lib/Target/Hexagon/RDFGraph.cpp
Warning:	line 1685, column 9 Called C++ object pointer is null

Annotated Source Code

Press '?' to see keyboard shortcuts

Show analyzer invocation

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name RDFGraph.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-9/lib/clang/9.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/include -I /build/llvm-toolchain-snapshot-9~svn362543/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/9.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-9/lib/clang/9.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-9~svn362543/build-llvm/lib/Target/Hexagon -fdebug-prefix-map=/build/llvm-toolchain-snapshot-9~svn362543=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2019-06-05-060531-1271-1 -x c++ /build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp -faddrsig

/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp

→

1//===- RDFGraph.cpp -------------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Target-independent, SSA-based data flow graph for register data flow (RDF).
10//
11#include "RDFGraph.h"
12#include "RDFRegisters.h"
13#include "llvm/ADT/BitVector.h"
14#include "llvm/ADT/STLExtras.h"
15#include "llvm/ADT/SetVector.h"
16#include "llvm/CodeGen/MachineBasicBlock.h"
17#include "llvm/CodeGen/MachineDominanceFrontier.h"
18#include "llvm/CodeGen/MachineDominators.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstr.h"
21#include "llvm/CodeGen/MachineOperand.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/CodeGen/TargetLowering.h"
25#include "llvm/CodeGen/TargetRegisterInfo.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/IR/Function.h"
28#include "llvm/MC/LaneBitmask.h"
29#include "llvm/MC/MCInstrDesc.h"
30#include "llvm/MC/MCRegisterInfo.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <cstring>
38#include <iterator>
39#include <set>
40#include <utility>
41#include <vector>

43using namespace llvm;
44using namespace rdf;

46// Printing functions. Have them here first, so that the rest of the code
47// can use them.
48namespace llvm {
49namespace rdf {

51raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P) {
if (!P.Mask.all())
  OS << ':' << PrintLaneMask(P.Mask);
return OS;
55}

57raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterRef> &P) {
auto &TRI = P.G.getTRI();
if (P.Obj.Reg > 0 && P.Obj.Reg < TRI.getNumRegs())
  OS << TRI.getName(P.Obj.Reg);
else
  OS << '#' << P.Obj.Reg;
OS << PrintLaneMaskOpt(P.Obj.Mask);
return OS;
65}

67raw_ostream &operator<< (raw_ostream &OS, const Print<NodeId> &P) {
auto NA = P.G.addr<NodeBase*>(P.Obj);
uint16_t Attrs = NA.Addr->getAttrs();
uint16_t Kind = NodeAttrs::kind(Attrs);
uint16_t Flags = NodeAttrs::flags(Attrs);
switch (NodeAttrs::type(Attrs)) {
  case NodeAttrs::Code:
    switch (Kind) {
      case NodeAttrs::Func:   OS << 'f'; break;
      case NodeAttrs::Block:  OS << 'b'; break;
      case NodeAttrs::Stmt:   OS << 's'; break;
      case NodeAttrs::Phi:    OS << 'p'; break;
      default:                OS << "c?"; break;
    }
    break;
  case NodeAttrs::Ref:
    if (Flags & NodeAttrs::Undef)
      OS << '/';
    if (Flags & NodeAttrs::Dead)
      OS << '\\';
    if (Flags & NodeAttrs::Preserving)
      OS << '+';
    if (Flags & NodeAttrs::Clobbering)
      OS << '~';
    switch (Kind) {
      case NodeAttrs::Use:    OS << 'u'; break;
      case NodeAttrs::Def:    OS << 'd'; break;
      case NodeAttrs::Block:  OS << 'b'; break;
      default:                OS << "r?"; break;
    }
    break;
  default:
    OS << '?';
    break;
}
OS << P.Obj;
if (Flags & NodeAttrs::Shadow)
  OS << '"';
return OS;
106}

108static void printRefHeader(raw_ostream &OS, const NodeAddr<RefNode*> RA,
              const DataFlowGraph &G) {
OS << Print<NodeId>(RA.Id, G) << '<'
   << Print<RegisterRef>(RA.Addr->getRegRef(G), G) << '>';
if (RA.Addr->getFlags() & NodeAttrs::Fixed)
  OS << '!';
114}

116raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<DefNode*>> &P) {
printRefHeader(OS, P.Obj, P.G);
OS << '(';
if (NodeId N = P.Obj.Addr->getReachingDef())
  OS << Print<NodeId>(N, P.G);
OS << ',';
if (NodeId N = P.Obj.Addr->getReachedDef())
  OS << Print<NodeId>(N, P.G);
OS << ',';
if (NodeId N = P.Obj.Addr->getReachedUse())
  OS << Print<NodeId>(N, P.G);
OS << "):";
if (NodeId N = P.Obj.Addr->getSibling())
  OS << Print<NodeId>(N, P.G);
return OS;
131}

133raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<UseNode*>> &P) {
printRefHeader(OS, P.Obj, P.G);
OS << '(';
if (NodeId N = P.Obj.Addr->getReachingDef())
  OS << Print<NodeId>(N, P.G);
OS << "):";
if (NodeId N = P.Obj.Addr->getSibling())
  OS << Print<NodeId>(N, P.G);
return OS;
142}

144raw_ostream &operator<< (raw_ostream &OS,
    const Print<NodeAddr<PhiUseNode*>> &P) {
printRefHeader(OS, P.Obj, P.G);
OS << '(';
if (NodeId N = P.Obj.Addr->getReachingDef())
  OS << Print<NodeId>(N, P.G);
OS << ',';
if (NodeId N = P.Obj.Addr->getPredecessor())
  OS << Print<NodeId>(N, P.G);
OS << "):";
if (NodeId N = P.Obj.Addr->getSibling())
  OS << Print<NodeId>(N, P.G);
return OS;
157}

159raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<RefNode*>> &P) {
switch (P.Obj.Addr->getKind()) {
  case NodeAttrs::Def:
    OS << PrintNode<DefNode*>(P.Obj, P.G);
    break;
  case NodeAttrs::Use:
    if (P.Obj.Addr->getFlags() & NodeAttrs::PhiRef)
      OS << PrintNode<PhiUseNode*>(P.Obj, P.G);
    else
      OS << PrintNode<UseNode*>(P.Obj, P.G);
    break;
}
return OS;
172}

174raw_ostream &operator<< (raw_ostream &OS, const Print<NodeList> &P) {
unsigned N = P.Obj.size();
for (auto I : P.Obj) {
  OS << Print<NodeId>(I.Id, P.G);
  if (--N)
    OS << ' ';
}
return OS;
182}

184raw_ostream &operator<< (raw_ostream &OS, const Print<NodeSet> &P) {
unsigned N = P.Obj.size();
for (auto I : P.Obj) {
  OS << Print<NodeId>(I, P.G);
  if (--N)
    OS << ' ';
}
return OS;
192}

194namespace {

template <typename T>
struct PrintListV {
  PrintListV(const NodeList &L, const DataFlowGraph &G) : List(L), G(G) {}

  using Type = T;
  const NodeList &List;
  const DataFlowGraph &G;
};

template <typename T>
raw_ostream &operator<< (raw_ostream &OS, const PrintListV<T> &P) {
  unsigned N = P.List.size();
  for (NodeAddr<T> A : P.List) {
    OS << PrintNode<T>(A, P.G);
    if (--N)
      OS << ", ";
  }
  return OS;
}

216} // end anonymous namespace

218raw_ostream &operator<< (raw_ostream &OS, const Print<NodeAddr<PhiNode*>> &P) {
OS << Print<NodeId>(P.Obj.Id, P.G) << ": phi ["
   << PrintListV<RefNode*>(P.Obj.Addr->members(P.G), P.G) << ']';
return OS;
222}

224raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<StmtNode *>> &P) {
const MachineInstr &MI = *P.Obj.Addr->getCode();
unsigned Opc = MI.getOpcode();
OS << Print<NodeId>(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc);
// Print the target for calls and branches (for readability).
if (MI.isCall() || MI.isBranch()) {
  MachineInstr::const_mop_iterator T =
        llvm::find_if(MI.operands(),
                      [] (const MachineOperand &Op) -> bool {
                        return Op.isMBB() || Op.isGlobal() || Op.isSymbol();
                      });
  if (T != MI.operands_end()) {
    OS << ' ';
    if (T->isMBB())
      OS << printMBBReference(*T->getMBB());
    else if (T->isGlobal())
      OS << T->getGlobal()->getName();
    else if (T->isSymbol())
      OS << T->getSymbolName();
  }
}
OS << " [" << PrintListV<RefNode*>(P.Obj.Addr->members(P.G), P.G) << ']';
return OS;
247}

249raw_ostream &operator<< (raw_ostream &OS,
    const Print<NodeAddr<InstrNode*>> &P) {
switch (P.Obj.Addr->getKind()) {
  case NodeAttrs::Phi:
    OS << PrintNode<PhiNode*>(P.Obj, P.G);
    break;
  case NodeAttrs::Stmt:
    OS << PrintNode<StmtNode*>(P.Obj, P.G);
    break;
  default:
    OS << "instr? " << Print<NodeId>(P.Obj.Id, P.G);
    break;
}
return OS;
263}

265raw_ostream &operator<< (raw_ostream &OS,
    const Print<NodeAddr<BlockNode*>> &P) {
MachineBasicBlock *BB = P.Obj.Addr->getCode();
unsigned NP = BB->pred_size();
std::vector<int> Ns;
auto PrintBBs = [&OS] (std::vector<int> Ns) -> void {
  unsigned N = Ns.size();
  for (int I : Ns) {
    OS << "%bb." << I;
    if (--N)
      OS << ", ";
  }
};

OS << Print<NodeId>(P.Obj.Id, P.G) << ": --- " << printMBBReference(*BB)
   << " --- preds(" << NP << "): ";
for (MachineBasicBlock *B : BB->predecessors())
  Ns.push_back(B->getNumber());
PrintBBs(Ns);

unsigned NS = BB->succ_size();
OS << "  succs(" << NS << "): ";
Ns.clear();
for (MachineBasicBlock *B : BB->successors())
  Ns.push_back(B->getNumber());
PrintBBs(Ns);
OS << '\n';

for (auto I : P.Obj.Addr->members(P.G))
  OS << PrintNode<InstrNode*>(I, P.G) << '\n';
return OS;
296}

298raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<FuncNode *>> &P) {
OS << "DFG dump:[\n" << Print<NodeId>(P.Obj.Id, P.G) << ": Function: "
   << P.Obj.Addr->getCode()->getName() << '\n';
for (auto I : P.Obj.Addr->members(P.G))
  OS << PrintNode<BlockNode*>(I, P.G) << '\n';
OS << "]\n";
return OS;
305}

307raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterSet> &P) {
OS << '{';
for (auto I : P.Obj)
  OS << ' ' << Print<RegisterRef>(I, P.G);
OS << " }";
return OS;
313}

315raw_ostream &operator<< (raw_ostream &OS, const Print<RegisterAggr> &P) {
P.Obj.print(OS);
return OS;
318}

320raw_ostream &operator<< (raw_ostream &OS,
    const Print<DataFlowGraph::DefStack> &P) {
for (auto I = P.Obj.top(), E = P.Obj.bottom(); I != E; ) {
  OS << Print<NodeId>(I->Id, P.G)
     << '<' << Print<RegisterRef>(I->Addr->getRegRef(P.G), P.G) << '>';
  I.down();
  if (I != E)
    OS << ' ';
}
return OS;
330}

332} // end namespace rdf
333} // end namespace llvm

335// Node allocation functions.
336//
337// Node allocator is like a slab memory allocator: it allocates blocks of
338// memory in sizes that are multiples of the size of a node. Each block has
339// the same size. Nodes are allocated from the currently active block, and
340// when it becomes full, a new one is created.
341// There is a mapping scheme between node id and its location in a block,
342// and within that block is described in the header file.
343//
344void NodeAllocator::startNewBlock() {
void *T = MemPool.Allocate(NodesPerBlock*NodeMemSize, NodeMemSize);
char *P = static_cast<char*>(T);
Blocks.push_back(P);
// Check if the block index is still within the allowed range, i.e. less
// than 2^N, where N is the number of bits in NodeId for the block index.
// BitsPerIndex is the number of bits per node index.
assert((Blocks.size() < ((size_t)1 << (8*sizeof(NodeId)-BitsPerIndex))) &&(((Blocks.size() < ((size_t)1 << (8*sizeof(NodeId)-BitsPerIndex
))) && "Out of bits for block index") ? static_cast<
void> (0) : __assert_fail ("(Blocks.size() < ((size_t)1 << (8*sizeof(NodeId)-BitsPerIndex))) && \"Out of bits for block index\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 352, __PRETTY_FUNCTION__))
       "Out of bits for block index")(((Blocks.size() < ((size_t)1 << (8*sizeof(NodeId)-BitsPerIndex
))) && "Out of bits for block index") ? static_cast<
void> (0) : __assert_fail ("(Blocks.size() < ((size_t)1 << (8*sizeof(NodeId)-BitsPerIndex))) && \"Out of bits for block index\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 352, __PRETTY_FUNCTION__));
ActiveEnd = P;
354}

356bool NodeAllocator::needNewBlock() {
if (Blocks.empty())
  return true;

char *ActiveBegin = Blocks.back();
uint32_t Index = (ActiveEnd-ActiveBegin)/NodeMemSize;
return Index >= NodesPerBlock;
363}

365NodeAddr<NodeBase*> NodeAllocator::New() {
if (needNewBlock())
  startNewBlock();

uint32_t ActiveB = Blocks.size()-1;
uint32_t Index = (ActiveEnd - Blocks[ActiveB])/NodeMemSize;
NodeAddr<NodeBase*> NA = { reinterpret_cast<NodeBase*>(ActiveEnd),
                           makeId(ActiveB, Index) };
ActiveEnd += NodeMemSize;
return NA;
375}

377NodeId NodeAllocator::id(const NodeBase *P) const {
uintptr_t A = reinterpret_cast<uintptr_t>(P);
for (unsigned i = 0, n = Blocks.size(); i != n; ++i) {
  uintptr_t B = reinterpret_cast<uintptr_t>(Blocks[i]);
  if (A < B || A >= B + NodesPerBlock*NodeMemSize)
    continue;
  uint32_t Idx = (A-B)/NodeMemSize;
  return makeId(i, Idx);
}
llvm_unreachable("Invalid node address")::llvm::llvm_unreachable_internal("Invalid node address", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 386);
387}

389void NodeAllocator::clear() {
MemPool.Reset();
Blocks.clear();
ActiveEnd = nullptr;
393}

395// Insert node NA after "this" in the circular chain.
396void NodeBase::append(NodeAddr<NodeBase*> NA) {
NodeId Nx = Next;
// If NA is already "next", do nothing.
if (Next != NA.Id) {
  Next = NA.Id;
  NA.Addr->Next = Nx;
}
403}

405// Fundamental node manipulator functions.

407// Obtain the register reference from a reference node.
408RegisterRef RefNode::getRegRef(const DataFlowGraph &G) const {
assert(NodeAttrs::type(Attrs) == NodeAttrs::Ref)((NodeAttrs::type(Attrs) == NodeAttrs::Ref) ? static_cast<
void> (0) : __assert_fail ("NodeAttrs::type(Attrs) == NodeAttrs::Ref"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 409, __PRETTY_FUNCTION__));
if (NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef)
  return G.unpack(Ref.PR);
assert(Ref.Op != nullptr)((Ref.Op != nullptr) ? static_cast<void> (0) : __assert_fail
 ("Ref.Op != nullptr", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 412, __PRETTY_FUNCTION__));
return G.makeRegRef(*Ref.Op);
414}

416// Set the register reference in the reference node directly (for references
417// in phi nodes).
418void RefNode::setRegRef(RegisterRef RR, DataFlowGraph &G) {
assert(NodeAttrs::type(Attrs) == NodeAttrs::Ref)((NodeAttrs::type(Attrs) == NodeAttrs::Ref) ? static_cast<
void> (0) : __assert_fail ("NodeAttrs::type(Attrs) == NodeAttrs::Ref"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 419, __PRETTY_FUNCTION__));
assert(NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef)((NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef) ? static_cast
<void> (0) : __assert_fail ("NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 420, __PRETTY_FUNCTION__));
Ref.PR = G.pack(RR);
422}

424// Set the register reference in the reference node based on a machine
425// operand (for references in statement nodes).
426void RefNode::setRegRef(MachineOperand *Op, DataFlowGraph &G) {
assert(NodeAttrs::type(Attrs) == NodeAttrs::Ref)((NodeAttrs::type(Attrs) == NodeAttrs::Ref) ? static_cast<
void> (0) : __assert_fail ("NodeAttrs::type(Attrs) == NodeAttrs::Ref"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 427, __PRETTY_FUNCTION__));
assert(!(NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef))((!(NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef)) ? static_cast
<void> (0) : __assert_fail ("!(NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef)"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 428, __PRETTY_FUNCTION__));
(void)G;
Ref.Op = Op;
431}

433// Get the owner of a given reference node.
434NodeAddr<NodeBase*> RefNode::getOwner(const DataFlowGraph &G) {
NodeAddr<NodeBase*> NA = G.addr<NodeBase*>(getNext());

while (NA.Addr != this) {
  if (NA.Addr->getType() == NodeAttrs::Code)
    return NA;
  NA = G.addr<NodeBase*>(NA.Addr->getNext());
}
llvm_unreachable("No owner in circular list")::llvm::llvm_unreachable_internal("No owner in circular list"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 442);
443}

445// Connect the def node to the reaching def node.
446void DefNode::linkToDef(NodeId Self, NodeAddr<DefNode*> DA) {
Ref.RD = DA.Id;
Ref.Sib = DA.Addr->getReachedDef();
DA.Addr->setReachedDef(Self);
450}

452// Connect the use node to the reaching def node.
453void UseNode::linkToDef(NodeId Self, NodeAddr<DefNode*> DA) {
Ref.RD = DA.Id;
Ref.Sib = DA.Addr->getReachedUse();
DA.Addr->setReachedUse(Self);
457}

459// Get the first member of the code node.
460NodeAddr<NodeBase*> CodeNode::getFirstMember(const DataFlowGraph &G) const {
if (Code.FirstM == 0)
  return NodeAddr<NodeBase*>();
return G.addr<NodeBase*>(Code.FirstM);
464}

466// Get the last member of the code node.
467NodeAddr<NodeBase*> CodeNode::getLastMember(const DataFlowGraph &G) const {
if (Code.LastM == 0)
  return NodeAddr<NodeBase*>();
return G.addr<NodeBase*>(Code.LastM);
471}

473// Add node NA at the end of the member list of the given code node.
474void CodeNode::addMember(NodeAddr<NodeBase*> NA, const DataFlowGraph &G) {
NodeAddr<NodeBase*> ML = getLastMember(G);
if (ML.Id != 0) {
  ML.Addr->append(NA);
} else {
  Code.FirstM = NA.Id;
  NodeId Self = G.id(this);
  NA.Addr->setNext(Self);
}
Code.LastM = NA.Id;
484}

486// Add node NA after member node MA in the given code node.
487void CodeNode::addMemberAfter(NodeAddr<NodeBase*> MA, NodeAddr<NodeBase*> NA,
    const DataFlowGraph &G) {
MA.Addr->append(NA);
if (Code.LastM == MA.Id)
  Code.LastM = NA.Id;
492}

494// Remove member node NA from the given code node.
495void CodeNode::removeMember(NodeAddr<NodeBase*> NA, const DataFlowGraph &G) {
NodeAddr<NodeBase*> MA = getFirstMember(G);
assert(MA.Id != 0)((MA.Id != 0) ? static_cast<void> (0) : __assert_fail (
"MA.Id != 0", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 497, __PRETTY_FUNCTION__));

// Special handling if the member to remove is the first member.
if (MA.Id == NA.Id) {
  if (Code.LastM == MA.Id) {
    // If it is the only member, set both first and last to 0.
    Code.FirstM = Code.LastM = 0;
  } else {
    // Otherwise, advance the first member.
    Code.FirstM = MA.Addr->getNext();
  }
  return;
}

while (MA.Addr != this) {
  NodeId MX = MA.Addr->getNext();
  if (MX == NA.Id) {
    MA.Addr->setNext(NA.Addr->getNext());
    // If the member to remove happens to be the last one, update the
    // LastM indicator.
    if (Code.LastM == NA.Id)
      Code.LastM = MA.Id;
    return;
  }
  MA = G.addr<NodeBase*>(MX);
}
llvm_unreachable("No such member")::llvm::llvm_unreachable_internal("No such member", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 523);
524}

526// Return the list of all members of the code node.
527NodeList CodeNode::members(const DataFlowGraph &G) const {
static auto True = [] (NodeAddr<NodeBase*>) -> bool { return true; };
return members_if(True, G);
530}

532// Return the owner of the given instr node.
533NodeAddr<NodeBase*> InstrNode::getOwner(const DataFlowGraph &G) {
NodeAddr<NodeBase*> NA = G.addr<NodeBase*>(getNext());

while (NA.Addr != this) {
  assert(NA.Addr->getType() == NodeAttrs::Code)((NA.Addr->getType() == NodeAttrs::Code) ? static_cast<
void> (0) : __assert_fail ("NA.Addr->getType() == NodeAttrs::Code"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 537, __PRETTY_FUNCTION__));
  if (NA.Addr->getKind() == NodeAttrs::Block)
    return NA;
  NA = G.addr<NodeBase*>(NA.Addr->getNext());
}
llvm_unreachable("No owner in circular list")::llvm::llvm_unreachable_internal("No owner in circular list"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 542);
543}

545// Add the phi node PA to the given block node.
546void BlockNode::addPhi(NodeAddr<PhiNode*> PA, const DataFlowGraph &G) {
NodeAddr<NodeBase*> M = getFirstMember(G);
if (M.Id == 0) {
  addMember(PA, G);
  return;
}

assert(M.Addr->getType() == NodeAttrs::Code)((M.Addr->getType() == NodeAttrs::Code) ? static_cast<void
> (0) : __assert_fail ("M.Addr->getType() == NodeAttrs::Code"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 553, __PRETTY_FUNCTION__));
if (M.Addr->getKind() == NodeAttrs::Stmt) {
  // If the first member of the block is a statement, insert the phi as
  // the first member.
  Code.FirstM = PA.Id;
  PA.Addr->setNext(M.Id);
} else {
  // If the first member is a phi, find the last phi, and append PA to it.
  assert(M.Addr->getKind() == NodeAttrs::Phi)((M.Addr->getKind() == NodeAttrs::Phi) ? static_cast<void
> (0) : __assert_fail ("M.Addr->getKind() == NodeAttrs::Phi"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 561, __PRETTY_FUNCTION__));
  NodeAddr<NodeBase*> MN = M;
  do {
    M = MN;
    MN = G.addr<NodeBase*>(M.Addr->getNext());
    assert(MN.Addr->getType() == NodeAttrs::Code)((MN.Addr->getType() == NodeAttrs::Code) ? static_cast<
void> (0) : __assert_fail ("MN.Addr->getType() == NodeAttrs::Code"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 566, __PRETTY_FUNCTION__));
  } while (MN.Addr->getKind() == NodeAttrs::Phi);

  // M is the last phi.
  addMemberAfter(M, PA, G);
}
572}

574// Find the block node corresponding to the machine basic block BB in the
575// given func node.
576NodeAddr<BlockNode*> FuncNode::findBlock(const MachineBasicBlock *BB,
    const DataFlowGraph &G) const {
auto EqBB = [BB] (NodeAddr<NodeBase*> NA) -> bool {
  return NodeAddr<BlockNode*>(NA).Addr->getCode() == BB;
};
NodeList Ms = members_if(EqBB, G);
if (!Ms.empty())
  return Ms[0];
return NodeAddr<BlockNode*>();
585}

587// Get the block node for the entry block in the given function.
588NodeAddr<BlockNode*> FuncNode::getEntryBlock(const DataFlowGraph &G) {
MachineBasicBlock *EntryB = &getCode()->front();
return findBlock(EntryB, G);
591}

593// Target operand information.
594//

596// For a given instruction, check if there are any bits of RR that can remain
597// unchanged across this def.
598bool TargetOperandInfo::isPreserving(const MachineInstr &In, unsigned OpNum)
    const {
return TII.isPredicated(In);
601}

603// Check if the definition of RR produces an unspecified value.
604bool TargetOperandInfo::isClobbering(const MachineInstr &In, unsigned OpNum)
    const {
const MachineOperand &Op = In.getOperand(OpNum);
if (Op.isRegMask())
  return true;
assert(Op.isReg())((Op.isReg()) ? static_cast<void> (0) : __assert_fail (
"Op.isReg()", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 609, __PRETTY_FUNCTION__));
if (In.isCall())
  if (Op.isDef() && Op.isDead())
    return true;
return false;
614}

616// Check if the given instruction specifically requires
617bool TargetOperandInfo::isFixedReg(const MachineInstr &In, unsigned OpNum)
    const {
if (In.isCall() || In.isReturn() || In.isInlineAsm())
  return true;
// Check for a tail call.
if (In.isBranch())
  for (const MachineOperand &O : In.operands())
    if (O.isGlobal() || O.isSymbol())
      return true;

const MCInstrDesc &D = In.getDesc();
if (!D.getImplicitDefs() && !D.getImplicitUses())
  return false;
const MachineOperand &Op = In.getOperand(OpNum);
// If there is a sub-register, treat the operand as non-fixed. Currently,
// fixed registers are those that are listed in the descriptor as implicit
// uses or defs, and those lists do not allow sub-registers.
if (Op.getSubReg() != 0)
  return false;
RegisterId Reg = Op.getReg();
const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs()
                                   : D.getImplicitUses();
if (!ImpR)
  return false;
while (*ImpR)
  if (*ImpR++ == Reg)
    return true;
return false;
645}

647//
648// The data flow graph construction.
649//

651DataFlowGraph::DataFlowGraph(MachineFunction &mf, const TargetInstrInfo &tii,
    const TargetRegisterInfo &tri, const MachineDominatorTree &mdt,
    const MachineDominanceFrontier &mdf, const TargetOperandInfo &toi)
  : MF(mf), TII(tii), TRI(tri), PRI(tri, mf), MDT(mdt), MDF(mdf), TOI(toi),
    LiveIns(PRI) {
656}

658// The implementation of the definition stack.
659// Each register reference has its own definition stack. In particular,
660// for a register references "Reg" and "Reg:subreg" will each have their
661// own definition stacks.

663// Construct a stack iterator.
664DataFlowGraph::DefStack::Iterator::Iterator(const DataFlowGraph::DefStack &S,
    bool Top) : DS(S) {
if (!Top) {
  // Initialize to bottom.
  Pos = 0;
  return;
}
// Initialize to the top, i.e. top-most non-delimiter (or 0, if empty).
Pos = DS.Stack.size();
while (Pos > 0 && DS.isDelimiter(DS.Stack[Pos-1]))
  Pos--;
675}

677// Return the size of the stack, including block delimiters.
678unsigned DataFlowGraph::DefStack::size() const {
unsigned S = 0;
for (auto I = top(), E = bottom(); I != E; I.down())
  S++;
return S;
683}

685// Remove the top entry from the stack. Remove all intervening delimiters
686// so that after this, the stack is either empty, or the top of the stack
687// is a non-delimiter.
688void DataFlowGraph::DefStack::pop() {
assert(!empty())((!empty()) ? static_cast<void> (0) : __assert_fail ("!empty()"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 689, __PRETTY_FUNCTION__));
unsigned P = nextDown(Stack.size());
Stack.resize(P);
692}

694// Push a delimiter for block node N on the stack.
695void DataFlowGraph::DefStack::start_block(NodeId N) {
assert(N != 0)((N != 0) ? static_cast<void> (0) : __assert_fail ("N != 0"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 696, __PRETTY_FUNCTION__));
Stack.push_back(NodeAddr<DefNode*>(nullptr, N));
698}

700// Remove all nodes from the top of the stack, until the delimited for
701// block node N is encountered. Remove the delimiter as well. In effect,
702// this will remove from the stack all definitions from block N.
703void DataFlowGraph::DefStack::clear_block(NodeId N) {
assert(N != 0)((N != 0) ? static_cast<void> (0) : __assert_fail ("N != 0"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 704, __PRETTY_FUNCTION__));
unsigned P = Stack.size();
while (P > 0) {
  bool Found = isDelimiter(Stack[P-1], N);
  P--;
  if (Found)
    break;
}
// This will also remove the delimiter, if found.
Stack.resize(P);
714}

716// Move the stack iterator up by one.
717unsigned DataFlowGraph::DefStack::nextUp(unsigned P) const {
// Get the next valid position after P (skipping all delimiters).
// The input position P does not have to point to a non-delimiter.
unsigned SS = Stack.size();
bool IsDelim;
assert(P < SS)((P < SS) ? static_cast<void> (0) : __assert_fail ("P < SS"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 722, __PRETTY_FUNCTION__));
do {
  P++;
  IsDelim = isDelimiter(Stack[P-1]);
} while (P < SS && IsDelim);
assert(!IsDelim)((!IsDelim) ? static_cast<void> (0) : __assert_fail ("!IsDelim"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 727, __PRETTY_FUNCTION__));
return P;
729}

731// Move the stack iterator down by one.
732unsigned DataFlowGraph::DefStack::nextDown(unsigned P) const {
// Get the preceding valid position before P (skipping all delimiters).
// The input position P does not have to point to a non-delimiter.
assert(P > 0 && P <= Stack.size())((P > 0 && P <= Stack.size()) ? static_cast<
void> (0) : __assert_fail ("P > 0 && P <= Stack.size()"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 735, __PRETTY_FUNCTION__));
bool IsDelim = isDelimiter(Stack[P-1]);
do {
  if (--P == 0)
    break;
  IsDelim = isDelimiter(Stack[P-1]);
} while (P > 0 && IsDelim);
assert(!IsDelim)((!IsDelim) ? static_cast<void> (0) : __assert_fail ("!IsDelim"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 742, __PRETTY_FUNCTION__));
return P;
744}

746// Register information.

748RegisterSet DataFlowGraph::getLandingPadLiveIns() const {
RegisterSet LR;
const Function &F = MF.getFunction();
const Constant *PF = F.hasPersonalityFn() ? F.getPersonalityFn()
                                          : nullptr;
const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
if (RegisterId R = TLI.getExceptionPointerRegister(PF))
  LR.insert(RegisterRef(R));
if (RegisterId R = TLI.getExceptionSelectorRegister(PF))
  LR.insert(RegisterRef(R));
return LR;
759}

761// Node management functions.

763// Get the pointer to the node with the id N.
764NodeBase *DataFlowGraph::ptr(NodeId N) const {
if (N == 0)
  return nullptr;
return Memory.ptr(N);
768}

770// Get the id of the node at the address P.
771NodeId DataFlowGraph::id(const NodeBase *P) const {
if (P == nullptr)
  return 0;
return Memory.id(P);
775}

777// Allocate a new node and set the attributes to Attrs.
778NodeAddr<NodeBase*> DataFlowGraph::newNode(uint16_t Attrs) {
NodeAddr<NodeBase*> P = Memory.New();
P.Addr->init();
P.Addr->setAttrs(Attrs);
return P;
783}

785// Make a copy of the given node B, except for the data-flow links, which
786// are set to 0.
787NodeAddr<NodeBase*> DataFlowGraph::cloneNode(const NodeAddr<NodeBase*> B) {
NodeAddr<NodeBase*> NA = newNode(0);
memcpy(NA.Addr, B.Addr, sizeof(NodeBase));
// Ref nodes need to have the data-flow links reset.
if (NA.Addr->getType() == NodeAttrs::Ref) {
  NodeAddr<RefNode*> RA = NA;
  RA.Addr->setReachingDef(0);
  RA.Addr->setSibling(0);
  if (NA.Addr->getKind() == NodeAttrs::Def) {
    NodeAddr<DefNode*> DA = NA;
    DA.Addr->setReachedDef(0);
    DA.Addr->setReachedUse(0);
  }
}
return NA;
802}

804// Allocation routines for specific node types/kinds.

806NodeAddr<UseNode*> DataFlowGraph::newUse(NodeAddr<InstrNode*> Owner,
    MachineOperand &Op, uint16_t Flags) {
NodeAddr<UseNode*> UA = newNode(NodeAttrs::Ref | NodeAttrs::Use | Flags);
UA.Addr->setRegRef(&Op, *this);
return UA;
811}

813NodeAddr<PhiUseNode*> DataFlowGraph::newPhiUse(NodeAddr<PhiNode*> Owner,
    RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) {
NodeAddr<PhiUseNode*> PUA = newNode(NodeAttrs::Ref | NodeAttrs::Use | Flags);
assert(Flags & NodeAttrs::PhiRef)((Flags & NodeAttrs::PhiRef) ? static_cast<void> (0
) : __assert_fail ("Flags & NodeAttrs::PhiRef", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 816, __PRETTY_FUNCTION__));
PUA.Addr->setRegRef(RR, *this);
PUA.Addr->setPredecessor(PredB.Id);
return PUA;
820}

822NodeAddr<DefNode*> DataFlowGraph::newDef(NodeAddr<InstrNode*> Owner,
    MachineOperand &Op, uint16_t Flags) {
NodeAddr<DefNode*> DA = newNode(NodeAttrs::Ref | NodeAttrs::Def | Flags);
DA.Addr->setRegRef(&Op, *this);
return DA;
827}

829NodeAddr<DefNode*> DataFlowGraph::newDef(NodeAddr<InstrNode*> Owner,
    RegisterRef RR, uint16_t Flags) {
NodeAddr<DefNode*> DA = newNode(NodeAttrs::Ref | NodeAttrs::Def | Flags);
assert(Flags & NodeAttrs::PhiRef)((Flags & NodeAttrs::PhiRef) ? static_cast<void> (0
) : __assert_fail ("Flags & NodeAttrs::PhiRef", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 832, __PRETTY_FUNCTION__));
DA.Addr->setRegRef(RR, *this);
return DA;
835}

837NodeAddr<PhiNode*> DataFlowGraph::newPhi(NodeAddr<BlockNode*> Owner) {
NodeAddr<PhiNode*> PA = newNode(NodeAttrs::Code | NodeAttrs::Phi);
Owner.Addr->addPhi(PA, *this);
return PA;
841}

843NodeAddr<StmtNode*> DataFlowGraph::newStmt(NodeAddr<BlockNode*> Owner,
    MachineInstr *MI) {
NodeAddr<StmtNode*> SA = newNode(NodeAttrs::Code | NodeAttrs::Stmt);
SA.Addr->setCode(MI);
Owner.Addr->addMember(SA, *this);
return SA;
849}

851NodeAddr<BlockNode*> DataFlowGraph::newBlock(NodeAddr<FuncNode*> Owner,
    MachineBasicBlock *BB) {
NodeAddr<BlockNode*> BA = newNode(NodeAttrs::Code | NodeAttrs::Block);
BA.Addr->setCode(BB);
Owner.Addr->addMember(BA, *this);
return BA;
857}

859NodeAddr<FuncNode*> DataFlowGraph::newFunc(MachineFunction *MF) {
NodeAddr<FuncNode*> FA = newNode(NodeAttrs::Code | NodeAttrs::Func);
FA.Addr->setCode(MF);
return FA;
863}

865// Build the data flow graph.
866void DataFlowGraph::build(unsigned Options) {
reset();
Func = newFunc(&MF);

if (MF.empty())
1
Assuming the condition is false→
2
←
Taking false branch→
  return;

for (MachineBasicBlock &B : MF) {
  NodeAddr<BlockNode*> BA = newBlock(Func, &B);
  BlockNodes.insert(std::make_pair(&B, BA));
  for (MachineInstr &I : B) {
    if (I.isDebugInstr())
      continue;
    buildStmt(BA, I);
  }
}

NodeAddr<BlockNode*> EA = Func.Addr->getEntryBlock(*this);
NodeList Blocks = Func.Addr->members(*this);

// Collect information about block references.
RegisterSet AllRefs;
for (NodeAddr<BlockNode*> BA : Blocks)
3
←
Assuming '__begin1' is equal to '__end1'→
  for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this))
    for (NodeAddr<RefNode*> RA : IA.Addr->members(*this))
      AllRefs.insert(RA.Addr->getRegRef(*this));

// Collect function live-ins and entry block live-ins.
MachineRegisterInfo &MRI = MF.getRegInfo();
MachineBasicBlock &EntryB = *EA.Addr->getCode();
assert(EntryB.pred_empty() && "Function entry block has predecessors")((EntryB.pred_empty() && "Function entry block has predecessors"
) ? static_cast<void> (0) : __assert_fail ("EntryB.pred_empty() && \"Function entry block has predecessors\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 896, __PRETTY_FUNCTION__));
4
←
Assuming the condition is true→
5
←
'?' condition is true→
for (std::pair<unsigned,unsigned> P : MRI.liveins())
6
←
Assuming '__begin1' is equal to '__end1'→
  LiveIns.insert(RegisterRef(P.first));
if (MRI.tracksLiveness()) {
7
←
Taking false branch→
  for (auto I : EntryB.liveins())
    LiveIns.insert(RegisterRef(I.PhysReg, I.LaneMask));
}

// Add function-entry phi nodes for the live-in registers.
//for (std::pair<RegisterId,LaneBitmask> P : LiveIns) {
for (auto I = LiveIns.rr_begin(), E = LiveIns.rr_end(); I != E; ++I) {
8
←
Loop condition is false. Execution continues on line 919→
  RegisterRef RR = *I;
  NodeAddr<PhiNode*> PA = newPhi(EA);
  uint16_t PhiFlags = NodeAttrs::PhiRef | NodeAttrs::Preserving;
  NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags);
  PA.Addr->addMember(DA, *this);
}

// Add phis for landing pads.
// Landing pads, unlike usual backs blocks, are not entered through
// branches in the program, or fall-throughs from other blocks. They
// are entered from the exception handling runtime and target's ABI
// may define certain registers as defined on entry to such a block.
RegisterSet EHRegs = getLandingPadLiveIns();
if (!EHRegs.empty()) {
9
←
Assuming the condition is false→
10
←
Taking false branch→
  for (NodeAddr<BlockNode*> BA : Blocks) {
    const MachineBasicBlock &B = *BA.Addr->getCode();
    if (!B.isEHPad())
      continue;

    // Prepare a list of NodeIds of the block's predecessors.
    NodeList Preds;
    for (MachineBasicBlock *PB : B.predecessors())
      Preds.push_back(findBlock(PB));

    // Build phi nodes for each live-in.
    for (RegisterRef RR : EHRegs) {
      NodeAddr<PhiNode*> PA = newPhi(BA);
      uint16_t PhiFlags = NodeAttrs::PhiRef | NodeAttrs::Preserving;
      // Add def:
      NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags);
      PA.Addr->addMember(DA, *this);
      // Add uses (no reaching defs for phi uses):
      for (NodeAddr<BlockNode*> PBA : Preds) {
        NodeAddr<PhiUseNode*> PUA = newPhiUse(PA, RR, PBA);
        PA.Addr->addMember(PUA, *this);
      }
    }
  }
}

// Build a map "PhiM" which will contain, for each block, the set
// of references that will require phi definitions in that block.
BlockRefsMap PhiM;
for (NodeAddr<BlockNode*> BA : Blocks)
11
←
Assuming '__begin1' is equal to '__end1'→
  recordDefsForDF(PhiM, BA);
for (NodeAddr<BlockNode*> BA : Blocks)
12
←
Assuming '__begin1' is equal to '__end1'→
  buildPhis(PhiM, AllRefs, BA);

// Link all the refs. This will recursively traverse the dominator tree.
DefStackMap DM;
linkBlockRefs(DM, EA);
13
←
Calling 'DataFlowGraph::linkBlockRefs'→

// Finally, remove all unused phi nodes.
if (!(Options & BuildOptions::KeepDeadPhis))
  removeUnusedPhis();
962}

964RegisterRef DataFlowGraph::makeRegRef(unsigned Reg, unsigned Sub) const {
assert(PhysicalRegisterInfo::isRegMaskId(Reg) ||((PhysicalRegisterInfo::isRegMaskId(Reg) || TargetRegisterInfo
::isPhysicalRegister(Reg)) ? static_cast<void> (0) : __assert_fail
 ("PhysicalRegisterInfo::isRegMaskId(Reg) || TargetRegisterInfo::isPhysicalRegister(Reg)"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 966, __PRETTY_FUNCTION__))
       TargetRegisterInfo::isPhysicalRegister(Reg))((PhysicalRegisterInfo::isRegMaskId(Reg) || TargetRegisterInfo
::isPhysicalRegister(Reg)) ? static_cast<void> (0) : __assert_fail
 ("PhysicalRegisterInfo::isRegMaskId(Reg) || TargetRegisterInfo::isPhysicalRegister(Reg)"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 966, __PRETTY_FUNCTION__));
assert(Reg != 0)((Reg != 0) ? static_cast<void> (0) : __assert_fail ("Reg != 0"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 967, __PRETTY_FUNCTION__));
if (Sub != 0)
  Reg = TRI.getSubReg(Reg, Sub);
return RegisterRef(Reg);
971}

973RegisterRef DataFlowGraph::makeRegRef(const MachineOperand &Op) const {
assert(Op.isReg() || Op.isRegMask())((Op.isReg() || Op.isRegMask()) ? static_cast<void> (0)
 : __assert_fail ("Op.isReg() || Op.isRegMask()", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 974, __PRETTY_FUNCTION__));
if (Op.isReg())
  return makeRegRef(Op.getReg(), Op.getSubReg());
return RegisterRef(PRI.getRegMaskId(Op.getRegMask()), LaneBitmask::getAll());
978}

980RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const {
if (AR.Reg == BR.Reg) {
  LaneBitmask M = AR.Mask & BR.Mask;
  return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef();
}
985#ifndef NDEBUG
986//  RegisterRef NAR = PRI.normalize(AR);
987//  RegisterRef NBR = PRI.normalize(BR);
988//  assert(NAR.Reg != NBR.Reg);
989#endif
// This isn't strictly correct, because the overlap may happen in the
// part masked out.
if (PRI.alias(AR, BR))
  return AR;
return RegisterRef();
995}

997// For each stack in the map DefM, push the delimiter for block B on it.
998void DataFlowGraph::markBlock(NodeId B, DefStackMap &DefM) {
// Push block delimiters.
for (auto I = DefM.begin(), E = DefM.end(); I != E; ++I)
  I->second.start_block(B);
1002}

1004// Remove all definitions coming from block B from each stack in DefM.
1005void DataFlowGraph::releaseBlock(NodeId B, DefStackMap &DefM) {
// Pop all defs from this block from the definition stack. Defs that were
// added to the map during the traversal of instructions will not have a
// delimiter, but for those, the whole stack will be emptied.
for (auto I = DefM.begin(), E = DefM.end(); I != E; ++I)
  I->second.clear_block(B);

// Finally, remove empty stacks from the map.
for (auto I = DefM.begin(), E = DefM.end(), NextI = I; I != E; I = NextI) {
  NextI = std::next(I);
  // This preserves the validity of iterators other than I.
  if (I->second.empty())
    DefM.erase(I);
}
1019}

1021// Push all definitions from the instruction node IA to an appropriate
1022// stack in DefM.
1023void DataFlowGraph::pushAllDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) {
pushClobbers(IA, DefM);
pushDefs(IA, DefM);
1026}

1028// Push all definitions from the instruction node IA to an appropriate
1029// stack in DefM.
1030void DataFlowGraph::pushClobbers(NodeAddr<InstrNode*> IA, DefStackMap &DefM) {
NodeSet Visited;
std::set<RegisterId> Defined;

// The important objectives of this function are:
// - to be able to handle instructions both while the graph is being
//   constructed, and after the graph has been constructed, and
// - maintain proper ordering of definitions on the stack for each
//   register reference:
//   - if there are two or more related defs in IA (i.e. coming from
//     the same machine operand), then only push one def on the stack,
//   - if there are multiple unrelated defs of non-overlapping
//     subregisters of S, then the stack for S will have both (in an
//     unspecified order), but the order does not matter from the data-
//     -flow perspective.

for (NodeAddr<DefNode*> DA : IA.Addr->members_if(IsDef, *this)) {
  if (Visited.count(DA.Id))
    continue;
  if (!(DA.Addr->getFlags() & NodeAttrs::Clobbering))
    continue;

  NodeList Rel = getRelatedRefs(IA, DA);
  NodeAddr<DefNode*> PDA = Rel.front();
  RegisterRef RR = PDA.Addr->getRegRef(*this);

  // Push the definition on the stack for the register and all aliases.
  // The def stack traversal in linkNodeUp will check the exact aliasing.
  DefM[RR.Reg].push(DA);
  Defined.insert(RR.Reg);
  for (RegisterId A : PRI.getAliasSet(RR.Reg)) {
    // Check that we don't push the same def twice.
    assert(A != RR.Reg)((A != RR.Reg) ? static_cast<void> (0) : __assert_fail (
"A != RR.Reg", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1062, __PRETTY_FUNCTION__));
    if (!Defined.count(A))
      DefM[A].push(DA);
  }
  // Mark all the related defs as visited.
  for (NodeAddr<NodeBase*> T : Rel)
    Visited.insert(T.Id);
}
1070}

1072// Push all definitions from the instruction node IA to an appropriate
1073// stack in DefM.
1074void DataFlowGraph::pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) {
NodeSet Visited;
1076#ifndef NDEBUG
std::set<RegisterId> Defined;
1078#endif

// The important objectives of this function are:
// - to be able to handle instructions both while the graph is being
//   constructed, and after the graph has been constructed, and
// - maintain proper ordering of definitions on the stack for each
//   register reference:
//   - if there are two or more related defs in IA (i.e. coming from
//     the same machine operand), then only push one def on the stack,
//   - if there are multiple unrelated defs of non-overlapping
//     subregisters of S, then the stack for S will have both (in an
//     unspecified order), but the order does not matter from the data-
//     -flow perspective.

for (NodeAddr<DefNode*> DA : IA.Addr->members_if(IsDef, *this)) {
  if (Visited.count(DA.Id))
    continue;
  if (DA.Addr->getFlags() & NodeAttrs::Clobbering)
    continue;

  NodeList Rel = getRelatedRefs(IA, DA);
  NodeAddr<DefNode*> PDA = Rel.front();
  RegisterRef RR = PDA.Addr->getRegRef(*this);
1101#ifndef NDEBUG
  // Assert if the register is defined in two or more unrelated defs.
  // This could happen if there are two or more def operands defining it.
  if (!Defined.insert(RR.Reg).second) {
    MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
    dbgs() << "Multiple definitions of register: "
           << Print<RegisterRef>(RR, *this) << " in\n  " << *MI << "in "
           << printMBBReference(*MI->getParent()) << '\n';
    llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1109);
  }
1111#endif
  // Push the definition on the stack for the register and all aliases.
  // The def stack traversal in linkNodeUp will check the exact aliasing.
  DefM[RR.Reg].push(DA);
  for (RegisterId A : PRI.getAliasSet(RR.Reg)) {
    // Check that we don't push the same def twice.
    assert(A != RR.Reg)((A != RR.Reg) ? static_cast<void> (0) : __assert_fail (
"A != RR.Reg", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1117, __PRETTY_FUNCTION__));
    DefM[A].push(DA);
  }
  // Mark all the related defs as visited.
  for (NodeAddr<NodeBase*> T : Rel)
    Visited.insert(T.Id);
}
1124}

1126// Return the list of all reference nodes related to RA, including RA itself.
1127// See "getNextRelated" for the meaning of a "related reference".
1128NodeList DataFlowGraph::getRelatedRefs(NodeAddr<InstrNode*> IA,
    NodeAddr<RefNode*> RA) const {
assert(IA.Id != 0 && RA.Id != 0)((IA.Id != 0 && RA.Id != 0) ? static_cast<void>
 (0) : __assert_fail ("IA.Id != 0 && RA.Id != 0", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1130, __PRETTY_FUNCTION__));

NodeList Refs;
NodeId Start = RA.Id;
do {
  Refs.push_back(RA);
  RA = getNextRelated(IA, RA);
} while (RA.Id != 0 && RA.Id != Start);
return Refs;
1139}

1141// Clear all information in the graph.
1142void DataFlowGraph::reset() {
Memory.clear();
BlockNodes.clear();
Func = NodeAddr<FuncNode*>();
1146}

1148// Return the next reference node in the instruction node IA that is related
1149// to RA. Conceptually, two reference nodes are related if they refer to the
1150// same instance of a register access, but differ in flags or other minor
1151// characteristics. Specific examples of related nodes are shadow reference
1152// nodes.
1153// Return the equivalent of nullptr if there are no more related references.
1154NodeAddr<RefNode*> DataFlowGraph::getNextRelated(NodeAddr<InstrNode*> IA,
    NodeAddr<RefNode*> RA) const {
assert(IA.Id != 0 && RA.Id != 0)((IA.Id != 0 && RA.Id != 0) ? static_cast<void>
 (0) : __assert_fail ("IA.Id != 0 && RA.Id != 0", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1156, __PRETTY_FUNCTION__));

auto Related = [this,RA](NodeAddr<RefNode*> TA) -> bool {
  if (TA.Addr->getKind() != RA.Addr->getKind())
    return false;
  if (TA.Addr->getRegRef(*this) != RA.Addr->getRegRef(*this))
    return false;
  return true;
};
auto RelatedStmt = [&Related,RA](NodeAddr<RefNode*> TA) -> bool {
  return Related(TA) &&
         &RA.Addr->getOp() == &TA.Addr->getOp();
};
auto RelatedPhi = [&Related,RA](NodeAddr<RefNode*> TA) -> bool {
  if (!Related(TA))
    return false;
  if (TA.Addr->getKind() != NodeAttrs::Use)
    return true;
  // For phi uses, compare predecessor blocks.
  const NodeAddr<const PhiUseNode*> TUA = TA;
  const NodeAddr<const PhiUseNode*> RUA = RA;
  return TUA.Addr->getPredecessor() == RUA.Addr->getPredecessor();
};

RegisterRef RR = RA.Addr->getRegRef(*this);
if (IA.Addr->getKind() == NodeAttrs::Stmt)
  return RA.Addr->getNextRef(RR, RelatedStmt, true, *this);
return RA.Addr->getNextRef(RR, RelatedPhi, true, *this);
1184}

1186// Find the next node related to RA in IA that satisfies condition P.
1187// If such a node was found, return a pair where the second element is the
1188// located node. If such a node does not exist, return a pair where the
1189// first element is the element after which such a node should be inserted,
1190// and the second element is a null-address.
1191template <typename Predicate>
1192std::pair<NodeAddr<RefNode*>,NodeAddr<RefNode*>>
1193DataFlowGraph::locateNextRef(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA,
    Predicate P) const {
assert(IA.Id != 0 && RA.Id != 0)((IA.Id != 0 && RA.Id != 0) ? static_cast<void>
 (0) : __assert_fail ("IA.Id != 0 && RA.Id != 0", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1195, __PRETTY_FUNCTION__));

NodeAddr<RefNode*> NA;
NodeId Start = RA.Id;
while (true) {
  NA = getNextRelated(IA, RA);
  if (NA.Id == 0 || NA.Id == Start)
    break;
  if (P(NA))
    break;
  RA = NA;
}

if (NA.Id != 0 && NA.Id != Start)
  return std::make_pair(RA, NA);
return std::make_pair(RA, NodeAddr<RefNode*>());
1211}

1213// Get the next shadow node in IA corresponding to RA, and optionally create
1214// such a node if it does not exist.
1215NodeAddr<RefNode*> DataFlowGraph::getNextShadow(NodeAddr<InstrNode*> IA,
    NodeAddr<RefNode*> RA, bool Create) {
assert(IA.Id != 0 && RA.Id != 0)((IA.Id != 0 && RA.Id != 0) ? static_cast<void>
 (0) : __assert_fail ("IA.Id != 0 && RA.Id != 0", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1217, __PRETTY_FUNCTION__));

uint16_t Flags = RA.Addr->getFlags() | NodeAttrs::Shadow;
auto IsShadow = [Flags] (NodeAddr<RefNode*> TA) -> bool {
  return TA.Addr->getFlags() == Flags;
};
auto Loc = locateNextRef(IA, RA, IsShadow);
if (Loc.second.Id != 0 || !Create)
  return Loc.second;

// Create a copy of RA and mark is as shadow.
NodeAddr<RefNode*> NA = cloneNode(RA);
NA.Addr->setFlags(Flags | NodeAttrs::Shadow);
IA.Addr->addMemberAfter(Loc.first, NA, *this);
return NA;
1232}

1234// Get the next shadow node in IA corresponding to RA. Return null-address
1235// if such a node does not exist.
1236NodeAddr<RefNode*> DataFlowGraph::getNextShadow(NodeAddr<InstrNode*> IA,
    NodeAddr<RefNode*> RA) const {
assert(IA.Id != 0 && RA.Id != 0)((IA.Id != 0 && RA.Id != 0) ? static_cast<void>
 (0) : __assert_fail ("IA.Id != 0 && RA.Id != 0", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1238, __PRETTY_FUNCTION__));
uint16_t Flags = RA.Addr->getFlags() | NodeAttrs::Shadow;
auto IsShadow = [Flags] (NodeAddr<RefNode*> TA) -> bool {
  return TA.Addr->getFlags() == Flags;
};
return locateNextRef(IA, RA, IsShadow).second;
1244}

1246// Create a new statement node in the block node BA that corresponds to
1247// the machine instruction MI.
1248void DataFlowGraph::buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In) {
NodeAddr<StmtNode*> SA = newStmt(BA, &In);

auto isCall = [] (const MachineInstr &In) -> bool {
  if (In.isCall())
    return true;
  // Is tail call?
  if (In.isBranch()) {
    for (const MachineOperand &Op : In.operands())
      if (Op.isGlobal() || Op.isSymbol())
        return true;
    // Assume indirect branches are calls. This is for the purpose of
    // keeping implicit operands, and so it won't hurt on intra-function
    // indirect branches.
    if (In.isIndirectBranch())
      return true;
  }
  return false;
};

auto isDefUndef = [this] (const MachineInstr &In, RegisterRef DR) -> bool {
  // This instruction defines DR. Check if there is a use operand that
  // would make DR live on entry to the instruction.
  for (const MachineOperand &Op : In.operands()) {
    if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
      continue;
    RegisterRef UR = makeRegRef(Op);
    if (PRI.alias(DR, UR))
      return false;
  }
  return true;
};

bool IsCall = isCall(In);
unsigned NumOps = In.getNumOperands();

// Avoid duplicate implicit defs. This will not detect cases of implicit
// defs that define registers that overlap, but it is not clear how to
// interpret that in the absence of explicit defs. Overlapping explicit
// defs are likely illegal already.
BitVector DoneDefs(TRI.getNumRegs());
// Process explicit defs first.
for (unsigned OpN = 0; OpN < NumOps; ++OpN) {
  MachineOperand &Op = In.getOperand(OpN);
  if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
    continue;
  unsigned R = Op.getReg();
  if (!R || !TargetRegisterInfo::isPhysicalRegister(R))
    continue;
  uint16_t Flags = NodeAttrs::None;
  if (TOI.isPreserving(In, OpN)) {
    Flags |= NodeAttrs::Preserving;
    // If the def is preserving, check if it is also undefined.
    if (isDefUndef(In, makeRegRef(Op)))
      Flags |= NodeAttrs::Undef;
  }
  if (TOI.isClobbering(In, OpN))
    Flags |= NodeAttrs::Clobbering;
  if (TOI.isFixedReg(In, OpN))
    Flags |= NodeAttrs::Fixed;
  if (IsCall && Op.isDead())
    Flags |= NodeAttrs::Dead;
  NodeAddr<DefNode*> DA = newDef(SA, Op, Flags);
  SA.Addr->addMember(DA, *this);
  assert(!DoneDefs.test(R))((!DoneDefs.test(R)) ? static_cast<void> (0) : __assert_fail
 ("!DoneDefs.test(R)", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1312, __PRETTY_FUNCTION__));
  DoneDefs.set(R);
}

// Process reg-masks (as clobbers).
BitVector DoneClobbers(TRI.getNumRegs());
for (unsigned OpN = 0; OpN < NumOps; ++OpN) {
  MachineOperand &Op = In.getOperand(OpN);
  if (!Op.isRegMask())
    continue;
  uint16_t Flags = NodeAttrs::Clobbering | NodeAttrs::Fixed |
                   NodeAttrs::Dead;
  NodeAddr<DefNode*> DA = newDef(SA, Op, Flags);
  SA.Addr->addMember(DA, *this);
  // Record all clobbered registers in DoneDefs.
  const uint32_t *RM = Op.getRegMask();
  for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i)
    if (!(RM[i/32] & (1u << (i%32))))
      DoneClobbers.set(i);
}

// Process implicit defs, skipping those that have already been added
// as explicit.
for (unsigned OpN = 0; OpN < NumOps; ++OpN) {
  MachineOperand &Op = In.getOperand(OpN);
  if (!Op.isReg() || !Op.isDef() || !Op.isImplicit())
    continue;
  unsigned R = Op.getReg();
  if (!R || !TargetRegisterInfo::isPhysicalRegister(R) || DoneDefs.test(R))
    continue;
  RegisterRef RR = makeRegRef(Op);
  uint16_t Flags = NodeAttrs::None;
  if (TOI.isPreserving(In, OpN)) {
    Flags |= NodeAttrs::Preserving;
    // If the def is preserving, check if it is also undefined.
    if (isDefUndef(In, RR))
      Flags |= NodeAttrs::Undef;
  }
  if (TOI.isClobbering(In, OpN))
    Flags |= NodeAttrs::Clobbering;
  if (TOI.isFixedReg(In, OpN))
    Flags |= NodeAttrs::Fixed;
  if (IsCall && Op.isDead()) {
    if (DoneClobbers.test(R))
      continue;
    Flags |= NodeAttrs::Dead;
  }
  NodeAddr<DefNode*> DA = newDef(SA, Op, Flags);
  SA.Addr->addMember(DA, *this);
  DoneDefs.set(R);
}

for (unsigned OpN = 0; OpN < NumOps; ++OpN) {
  MachineOperand &Op = In.getOperand(OpN);
  if (!Op.isReg() || !Op.isUse())
    continue;
  unsigned R = Op.getReg();
  if (!R || !TargetRegisterInfo::isPhysicalRegister(R))
    continue;
  uint16_t Flags = NodeAttrs::None;
  if (Op.isUndef())
    Flags |= NodeAttrs::Undef;
  if (TOI.isFixedReg(In, OpN))
    Flags |= NodeAttrs::Fixed;
  NodeAddr<UseNode*> UA = newUse(SA, Op, Flags);
  SA.Addr->addMember(UA, *this);
}
1379}

1381// Scan all defs in the block node BA and record in PhiM the locations of
1382// phi nodes corresponding to these defs.
1383void DataFlowGraph::recordDefsForDF(BlockRefsMap &PhiM,
    NodeAddr<BlockNode*> BA) {
// Check all defs from block BA and record them in each block in BA's
// iterated dominance frontier. This information will later be used to
// create phi nodes.
MachineBasicBlock *BB = BA.Addr->getCode();
assert(BB)((BB) ? static_cast<void> (0) : __assert_fail ("BB", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1389, __PRETTY_FUNCTION__));
auto DFLoc = MDF.find(BB);
if (DFLoc == MDF.end() || DFLoc->second.empty())
  return;

// Traverse all instructions in the block and collect the set of all
// defined references. For each reference there will be a phi created
// in the block's iterated dominance frontier.
// This is done to make sure that each defined reference gets only one
// phi node, even if it is defined multiple times.
RegisterSet Defs;
for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this))
  for (NodeAddr<RefNode*> RA : IA.Addr->members_if(IsDef, *this))
    Defs.insert(RA.Addr->getRegRef(*this));

// Calculate the iterated dominance frontier of BB.
const MachineDominanceFrontier::DomSetType &DF = DFLoc->second;
SetVector<MachineBasicBlock*> IDF(DF.begin(), DF.end());
for (unsigned i = 0; i < IDF.size(); ++i) {
  auto F = MDF.find(IDF[i]);
  if (F != MDF.end())
    IDF.insert(F->second.begin(), F->second.end());
}

// Finally, add the set of defs to each block in the iterated dominance
// frontier.
for (auto DB : IDF) {
  NodeAddr<BlockNode*> DBA = findBlock(DB);
  PhiM[DBA.Id].insert(Defs.begin(), Defs.end());
}
1419}

1421// Given the locations of phi nodes in the map PhiM, create the phi nodes
1422// that are located in the block node BA.
1423void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs,
    NodeAddr<BlockNode*> BA) {
// Check if this blocks has any DF defs, i.e. if there are any defs
// that this block is in the iterated dominance frontier of.
auto HasDF = PhiM.find(BA.Id);
if (HasDF == PhiM.end() || HasDF->second.empty())
  return;

// First, remove all R in Refs in such that there exists T in Refs
// such that T covers R. In other words, only leave those refs that
// are not covered by another ref (i.e. maximal with respect to covering).

auto MaxCoverIn = [this] (RegisterRef RR, RegisterSet &RRs) -> RegisterRef {
  for (RegisterRef I : RRs)
    if (I != RR && RegisterAggr::isCoverOf(I, RR, PRI))
      RR = I;
  return RR;
};

RegisterSet MaxDF;
for (RegisterRef I : HasDF->second)
  MaxDF.insert(MaxCoverIn(I, HasDF->second));

std::vector<RegisterRef> MaxRefs;
for (RegisterRef I : MaxDF)
  MaxRefs.push_back(MaxCoverIn(I, AllRefs));

// Now, for each R in MaxRefs, get the alias closure of R. If the closure
// only has R in it, create a phi a def for R. Otherwise, create a phi,
// and add a def for each S in the closure.

// Sort the refs so that the phis will be created in a deterministic order.
llvm::sort(MaxRefs);
// Remove duplicates.
auto NewEnd = std::unique(MaxRefs.begin(), MaxRefs.end());
MaxRefs.erase(NewEnd, MaxRefs.end());

auto Aliased = [this,&MaxRefs](RegisterRef RR,
                               std::vector<unsigned> &Closure) -> bool {
  for (unsigned I : Closure)
    if (PRI.alias(RR, MaxRefs[I]))
      return true;
  return false;
};

// Prepare a list of NodeIds of the block's predecessors.
NodeList Preds;
const MachineBasicBlock *MBB = BA.Addr->getCode();
for (MachineBasicBlock *PB : MBB->predecessors())
  Preds.push_back(findBlock(PB));

while (!MaxRefs.empty()) {
  // Put the first element in the closure, and then add all subsequent
  // elements from MaxRefs to it, if they alias at least one element
  // already in the closure.
  // ClosureIdx: vector of indices in MaxRefs of members of the closure.
  std::vector<unsigned> ClosureIdx = { 0 };
  for (unsigned i = 1; i != MaxRefs.size(); ++i)
    if (Aliased(MaxRefs[i], ClosureIdx))
      ClosureIdx.push_back(i);

  // Build a phi for the closure.
  unsigned CS = ClosureIdx.size();
  NodeAddr<PhiNode*> PA = newPhi(BA);

  // Add defs.
  for (unsigned X = 0; X != CS; ++X) {
    RegisterRef RR = MaxRefs[ClosureIdx[X]];
    uint16_t PhiFlags = NodeAttrs::PhiRef | NodeAttrs::Preserving;
    NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags);
    PA.Addr->addMember(DA, *this);
  }
  // Add phi uses.
  for (NodeAddr<BlockNode*> PBA : Preds) {
    for (unsigned X = 0; X != CS; ++X) {
      RegisterRef RR = MaxRefs[ClosureIdx[X]];
      NodeAddr<PhiUseNode*> PUA = newPhiUse(PA, RR, PBA);
      PA.Addr->addMember(PUA, *this);
    }
  }

  // Erase from MaxRefs all elements in the closure.
  auto Begin = MaxRefs.begin();
  for (unsigned i = ClosureIdx.size(); i != 0; --i)
    MaxRefs.erase(Begin + ClosureIdx[i-1]);
}
1509}

1511// Remove any unneeded phi nodes that were created during the build process.
1512void DataFlowGraph::removeUnusedPhis() {
// This will remove unused phis, i.e. phis where each def does not reach
// any uses or other defs. This will not detect or remove circular phi
// chains that are otherwise dead. Unused/dead phis are created during
// the build process and this function is intended to remove these cases
// that are easily determinable to be unnecessary.

SetVector<NodeId> PhiQ;
for (NodeAddr<BlockNode*> BA : Func.Addr->members(*this)) {
  for (auto P : BA.Addr->members_if(IsPhi, *this))
    PhiQ.insert(P.Id);
}

static auto HasUsedDef = [](NodeList &Ms) -> bool {
  for (NodeAddr<NodeBase*> M : Ms) {
    if (M.Addr->getKind() != NodeAttrs::Def)
      continue;
    NodeAddr<DefNode*> DA = M;
    if (DA.Addr->getReachedDef() != 0 || DA.Addr->getReachedUse() != 0)
      return true;
  }
  return false;
};

// Any phi, if it is removed, may affect other phis (make them dead).
// For each removed phi, collect the potentially affected phis and add
// them back to the queue.
while (!PhiQ.empty()) {
  auto PA = addr<PhiNode*>(PhiQ[0]);
  PhiQ.remove(PA.Id);
  NodeList Refs = PA.Addr->members(*this);
  if (HasUsedDef(Refs))
    continue;
  for (NodeAddr<RefNode*> RA : Refs) {
    if (NodeId RD = RA.Addr->getReachingDef()) {
      auto RDA = addr<DefNode*>(RD);
      NodeAddr<InstrNode*> OA = RDA.Addr->getOwner(*this);
      if (IsPhi(OA))
        PhiQ.insert(OA.Id);
    }
    if (RA.Addr->isDef())
      unlinkDef(RA, true);
    else
      unlinkUse(RA, true);
  }
  NodeAddr<BlockNode*> BA = PA.Addr->getOwner(*this);
  BA.Addr->removeMember(PA, *this);
}
1560}

1562// For a given reference node TA in an instruction node IA, connect the
1563// reaching def of TA to the appropriate def node. Create any shadow nodes
1564// as appropriate.
1565template <typename T>
1566void DataFlowGraph::linkRefUp(NodeAddr<InstrNode*> IA, NodeAddr<T> TA,
    DefStack &DS) {
if (DS.empty())
  return;
RegisterRef RR = TA.Addr->getRegRef(*this);
NodeAddr<T> TAP;

// References from the def stack that have been examined so far.
RegisterAggr Defs(PRI);

for (auto I = DS.top(), E = DS.bottom(); I != E; I.down()) {
  RegisterRef QR = I->Addr->getRegRef(*this);

  // Skip all defs that are aliased to any of the defs that we have already
  // seen. If this completes a cover of RR, stop the stack traversal.
  bool Alias = Defs.hasAliasOf(QR);
  bool Cover = Defs.insert(QR).hasCoverOf(RR);
  if (Alias) {
    if (Cover)
      break;
    continue;
  }

  // The reaching def.
  NodeAddr<DefNode*> RDA = *I;

  // Pick the reached node.
  if (TAP.Id == 0) {
    TAP = TA;
  } else {
    // Mark the existing ref as "shadow" and create a new shadow.
    TAP.Addr->setFlags(TAP.Addr->getFlags() | NodeAttrs::Shadow);
    TAP = getNextShadow(IA, TAP, true);
  }

  // Create the link.
  TAP.Addr->linkToDef(TAP.Id, RDA);

  if (Cover)
    break;
}
1607}

1609// Create data-flow links for all reference nodes in the statement node SA.
1610template <typename Predicate>
1611void DataFlowGraph::linkStmtRefs(DefStackMap &DefM, NodeAddr<StmtNode*> SA,
    Predicate P) {
1613#ifndef NDEBUG
RegisterSet Defs;
1615#endif

// Link all nodes (upwards in the data-flow) with their reaching defs.
for (NodeAddr<RefNode*> RA : SA.Addr->members_if(P, *this)) {
  uint16_t Kind = RA.Addr->getKind();
  assert(Kind == NodeAttrs::Def || Kind == NodeAttrs::Use)((Kind == NodeAttrs::Def || Kind == NodeAttrs::Use) ? static_cast
<void> (0) : __assert_fail ("Kind == NodeAttrs::Def || Kind == NodeAttrs::Use"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1620, __PRETTY_FUNCTION__));
  RegisterRef RR = RA.Addr->getRegRef(*this);
1622#ifndef NDEBUG
  // Do not expect multiple defs of the same reference.
  assert(Kind != NodeAttrs::Def || !Defs.count(RR))((Kind != NodeAttrs::Def || !Defs.count(RR)) ? static_cast<
void> (0) : __assert_fail ("Kind != NodeAttrs::Def || !Defs.count(RR)"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1624, __PRETTY_FUNCTION__));
  Defs.insert(RR);
1626#endif

  auto F = DefM.find(RR.Reg);
  if (F == DefM.end())
    continue;
  DefStack &DS = F->second;
  if (Kind == NodeAttrs::Use)
    linkRefUp<UseNode*>(SA, RA, DS);
  else if (Kind == NodeAttrs::Def)
    linkRefUp<DefNode*>(SA, RA, DS);
  else
    llvm_unreachable("Unexpected node in instruction")::llvm::llvm_unreachable_internal("Unexpected node in instruction"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1637);
}
1639}

1641// Create data-flow links for all instructions in the block node BA. This
1642// will include updating any phi nodes in BA.
1643void DataFlowGraph::linkBlockRefs(DefStackMap &DefM, NodeAddr<BlockNode*> BA) {
// Push block delimiters.
markBlock(BA.Id, DefM);

auto IsClobber = [] (NodeAddr<RefNode*> RA) -> bool {
  return IsDef(RA) && (RA.Addr->getFlags() & NodeAttrs::Clobbering);
};
auto IsNoClobber = [] (NodeAddr<RefNode*> RA) -> bool {
  return IsDef(RA) && !(RA.Addr->getFlags() & NodeAttrs::Clobbering);
};

assert(BA.Addr && "block node address is needed to create a data-flow link")((BA.Addr && "block node address is needed to create a data-flow link"
) ? static_cast<void> (0) : __assert_fail ("BA.Addr && \"block node address is needed to create a data-flow link\""
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1654, __PRETTY_FUNCTION__));
14
←
'?' condition is true→
// For each non-phi instruction in the block, link all the defs and uses
// to their reaching defs. For any member of the block (including phis),
// push the defs on the corresponding stacks.
for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this)) {
15
←
Assuming '__begin1' is equal to '__end1'→
  // Ignore phi nodes here. They will be linked part by part from the
  // predecessors.
  if (IA.Addr->getKind() == NodeAttrs::Stmt) {
    linkStmtRefs(DefM, IA, IsUse);
    linkStmtRefs(DefM, IA, IsClobber);
  }

  // Push the definitions on the stack.
  pushClobbers(IA, DefM);

  if (IA.Addr->getKind() == NodeAttrs::Stmt)
    linkStmtRefs(DefM, IA, IsNoClobber);

  pushDefs(IA, DefM);
}

// Recursively process all children in the dominator tree.
MachineDomTreeNode *N = MDT.getNode(BA.Addr->getCode());
for (auto I : *N) {
  MachineBasicBlock *SB = I->getBlock();
  NodeAddr<BlockNode*> SBA = findBlock(SB);
  linkBlockRefs(DefM, SBA);
}

// Link the phi uses from the successor blocks.
auto IsUseForBA = [BA](NodeAddr<NodeBase*> NA) -> bool {
  if (NA.Addr->getKind() != NodeAttrs::Use)
27
←
Called C++ object pointer is null
    return false;
  assert(NA.Addr->getFlags() & NodeAttrs::PhiRef)((NA.Addr->getFlags() & NodeAttrs::PhiRef) ? static_cast
<void> (0) : __assert_fail ("NA.Addr->getFlags() & NodeAttrs::PhiRef"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1687, __PRETTY_FUNCTION__));
  NodeAddr<PhiUseNode*> PUA = NA;
  return PUA.Addr->getPredecessor() == BA.Id;
};

RegisterSet EHLiveIns = getLandingPadLiveIns();
MachineBasicBlock *MBB = BA.Addr->getCode();

for (MachineBasicBlock *SB : MBB->successors()) {
  bool IsEHPad = SB->isEHPad();
  NodeAddr<BlockNode*> SBA = findBlock(SB);
  for (NodeAddr<InstrNode*> IA : SBA.Addr->members_if(IsPhi, *this)) {
16
←
Assuming '__begin2' is not equal to '__end2'→
    // Do not link phi uses for landing pad live-ins.
    if (IsEHPad) {
17
←
Assuming 'IsEHPad' is 0→
18
←
Taking false branch→
      // Find what register this phi is for.
      NodeAddr<RefNode*> RA = IA.Addr->getFirstMember(*this);
      assert(RA.Id != 0)((RA.Id != 0) ? static_cast<void> (0) : __assert_fail (
"RA.Id != 0", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1703, __PRETTY_FUNCTION__));
      if (EHLiveIns.count(RA.Addr->getRegRef(*this)))
        continue;
    }
    // Go over each phi use associated with MBB, and link it.
    for (auto U : IA.Addr->members_if(IsUseForBA, *this)) {
19
←
Calling 'CodeNode::members_if'→
      NodeAddr<PhiUseNode*> PUA = U;
      RegisterRef RR = PUA.Addr->getRegRef(*this);
      linkRefUp<UseNode*>(IA, PUA, DefM[RR.Reg]);
    }
  }
}

// Pop all defs from this block from the definition stacks.
releaseBlock(BA.Id, DefM);
1718}

1720// Remove the use node UA from any data-flow and structural links.
1721void DataFlowGraph::unlinkUseDF(NodeAddr<UseNode*> UA) {
NodeId RD = UA.Addr->getReachingDef();
NodeId Sib = UA.Addr->getSibling();

if (RD == 0) {
  assert(Sib == 0)((Sib == 0) ? static_cast<void> (0) : __assert_fail ("Sib == 0"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1726, __PRETTY_FUNCTION__));
  return;
}

auto RDA = addr<DefNode*>(RD);
auto TA = addr<UseNode*>(RDA.Addr->getReachedUse());
if (TA.Id == UA.Id) {
  RDA.Addr->setReachedUse(Sib);
  return;
}

while (TA.Id != 0) {
  NodeId S = TA.Addr->getSibling();
  if (S == UA.Id) {
    TA.Addr->setSibling(UA.Addr->getSibling());
    return;
  }
  TA = addr<UseNode*>(S);
}
1745}

1747// Remove the def node DA from any data-flow and structural links.
1748void DataFlowGraph::unlinkDefDF(NodeAddr<DefNode*> DA) {
//
//         RD
//         | reached
//         | def
//         :
//         .
//        +----+
// ... -- | DA | -- ... -- 0  : sibling chain of DA
//        +----+
//         |  | reached
//         |  : def
//         |  .
//         | ...  : Siblings (defs)
//         |
//         : reached
//         . use
//        ... : sibling chain of reached uses

NodeId RD = DA.Addr->getReachingDef();

// Visit all siblings of the reached def and reset their reaching defs.
// Also, defs reached by DA are now "promoted" to being reached by RD,
// so all of them will need to be spliced into the sibling chain where
// DA belongs.
auto getAllNodes = [this] (NodeId N) -> NodeList {
  NodeList Res;
  while (N) {
    auto RA = addr<RefNode*>(N);
    // Keep the nodes in the exact sibling order.
    Res.push_back(RA);
    N = RA.Addr->getSibling();
  }
  return Res;
};
NodeList ReachedDefs = getAllNodes(DA.Addr->getReachedDef());
NodeList ReachedUses = getAllNodes(DA.Addr->getReachedUse());

if (RD == 0) {
  for (NodeAddr<RefNode*> I : ReachedDefs)
    I.Addr->setSibling(0);
  for (NodeAddr<RefNode*> I : ReachedUses)
    I.Addr->setSibling(0);
}
for (NodeAddr<DefNode*> I : ReachedDefs)
  I.Addr->setReachingDef(RD);
for (NodeAddr<UseNode*> I : ReachedUses)
  I.Addr->setReachingDef(RD);

NodeId Sib = DA.Addr->getSibling();
if (RD == 0) {
  assert(Sib == 0)((Sib == 0) ? static_cast<void> (0) : __assert_fail ("Sib == 0"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.cpp"
, 1799, __PRETTY_FUNCTION__));
  return;
}

// Update the reaching def node and remove DA from the sibling list.
auto RDA = addr<DefNode*>(RD);
auto TA = addr<DefNode*>(RDA.Addr->getReachedDef());
if (TA.Id == DA.Id) {
  // If DA is the first reached def, just update the RD's reached def
  // to the DA's sibling.
  RDA.Addr->setReachedDef(Sib);
} else {
  // Otherwise, traverse the sibling list of the reached defs and remove
  // DA from it.
  while (TA.Id != 0) {
    NodeId S = TA.Addr->getSibling();
    if (S == DA.Id) {
      TA.Addr->setSibling(Sib);
      break;
    }
    TA = addr<DefNode*>(S);
  }
}

// Splice the DA's reached defs into the RDA's reached def chain.
if (!ReachedDefs.empty()) {
  auto Last = NodeAddr<DefNode*>(ReachedDefs.back());
  Last.Addr->setSibling(RDA.Addr->getReachedDef());
  RDA.Addr->setReachedDef(ReachedDefs.front().Id);
}
// Splice the DA's reached uses into the RDA's reached use chain.
if (!ReachedUses.empty()) {
  auto Last = NodeAddr<UseNode*>(ReachedUses.back());
  Last.Addr->setSibling(RDA.Addr->getReachedUse());
  RDA.Addr->setReachedUse(ReachedUses.front().Id);
}
1835}

←

/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h

1//===- RDFGraph.h -----------------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Target-independent, SSA-based data flow graph for register data flow (RDF)
10// for a non-SSA program representation (e.g. post-RA machine code).
11//
12//
13// *** Introduction
14//
15// The RDF graph is a collection of nodes, each of which denotes some element
16// of the program. There are two main types of such elements: code and refe-
17// rences. Conceptually, "code" is something that represents the structure
18// of the program, e.g. basic block or a statement, while "reference" is an
19// instance of accessing a register, e.g. a definition or a use. Nodes are
20// connected with each other based on the structure of the program (such as
21// blocks, instructions, etc.), and based on the data flow (e.g. reaching
22// definitions, reached uses, etc.). The single-reaching-definition principle
23// of SSA is generally observed, although, due to the non-SSA representation
24// of the program, there are some differences between the graph and a "pure"
25// SSA representation.
26//
27//
28// *** Implementation remarks
29//
30// Since the graph can contain a large number of nodes, memory consumption
31// was one of the major design considerations. As a result, there is a single
32// base class NodeBase which defines all members used by all possible derived
33// classes. The members are arranged in a union, and a derived class cannot
34// add any data members of its own. Each derived class only defines the
35// functional interface, i.e. member functions. NodeBase must be a POD,
36// which implies that all of its members must also be PODs.
37// Since nodes need to be connected with other nodes, pointers have been
38// replaced with 32-bit identifiers: each node has an id of type NodeId.
39// There are mapping functions in the graph that translate between actual
40// memory addresses and the corresponding identifiers.
41// A node id of 0 is equivalent to nullptr.
42//
43//
44// *** Structure of the graph
45//
46// A code node is always a collection of other nodes. For example, a code
47// node corresponding to a basic block will contain code nodes corresponding
48// to instructions. In turn, a code node corresponding to an instruction will
49// contain a list of reference nodes that correspond to the definitions and
50// uses of registers in that instruction. The members are arranged into a
51// circular list, which is yet another consequence of the effort to save
52// memory: for each member node it should be possible to obtain its owner,
53// and it should be possible to access all other members. There are other
54// ways to accomplish that, but the circular list seemed the most natural.
55//
56// +- CodeNode -+
57// |            | <---------------------------------------------------+
58// +-+--------+-+                                                     |
59//   |FirstM  |LastM                                                  |
60//   |        +-------------------------------------+                 |
61//   |                                              |                 |
62//   V                                              V                 |
63//  +----------+ Next +----------+ Next       Next +----------+ Next  |
64//  |          |----->|          |-----> ... ----->|          |----->-+
65//  +- Member -+      +- Member -+                 +- Member -+
66//
67// The order of members is such that related reference nodes (see below)
68// should be contiguous on the member list.
69//
70// A reference node is a node that encapsulates an access to a register,
71// in other words, data flowing into or out of a register. There are two
72// major kinds of reference nodes: defs and uses. A def node will contain
73// the id of the first reached use, and the id of the first reached def.
74// Each def and use will contain the id of the reaching def, and also the
75// id of the next reached def (for def nodes) or use (for use nodes).
76// The "next node sharing the same reaching def" is denoted as "sibling".
77// In summary:
78// - Def node contains: reaching def, sibling, first reached def, and first
79// reached use.
80// - Use node contains: reaching def and sibling.
81//
82// +-- DefNode --+
83// | R2 = ...    | <---+--------------------+
84// ++---------+--+     |                    |
85//  |Reached  |Reached |                    |
86//  |Def      |Use     |                    |
87//  |         |        |Reaching            |Reaching
88//  |         V        |Def                 |Def
89//  |      +-- UseNode --+ Sib  +-- UseNode --+ Sib       Sib
90//  |      | ... = R2    |----->| ... = R2    |----> ... ----> 0
91//  |      +-------------+      +-------------+
92//  V
93// +-- DefNode --+ Sib
94// | R2 = ...    |----> ...
95// ++---------+--+
96//  |         |
97//  |         |
98// ...       ...
99//
100// To get a full picture, the circular lists connecting blocks within a
101// function, instructions within a block, etc. should be superimposed with
102// the def-def, def-use links shown above.
103// To illustrate this, consider a small example in a pseudo-assembly:
104// foo:
105//   add r2, r0, r1   ; r2 = r0+r1
106//   addi r0, r2, 1   ; r0 = r2+1
107//   ret r0           ; return value in r0
108//
109// The graph (in a format used by the debugging functions) would look like:
110//
111//   DFG dump:[
112//   f1: Function foo
113//   b2: === %bb.0 === preds(0), succs(0):
114//   p3: phi [d4<r0>(,d12,u9):]
115//   p5: phi [d6<r1>(,,u10):]
116//   s7: add [d8<r2>(,,u13):, u9<r0>(d4):, u10<r1>(d6):]
117//   s11: addi [d12<r0>(d4,,u15):, u13<r2>(d8):]
118//   s14: ret [u15<r0>(d12):]
119//   ]
120//
121// The f1, b2, p3, etc. are node ids. The letter is prepended to indicate the
122// kind of the node (i.e. f - function, b - basic block, p - phi, s - state-
123// ment, d - def, u - use).
124// The format of a def node is:
125//   dN<R>(rd,d,u):sib,
126// where
127//   N   - numeric node id,
128//   R   - register being defined
129//   rd  - reaching def,
130//   d   - reached def,
131//   u   - reached use,
132//   sib - sibling.
133// The format of a use node is:
134//   uN<R>[!](rd):sib,
135// where
136//   N   - numeric node id,
137//   R   - register being used,
138//   rd  - reaching def,
139//   sib - sibling.
140// Possible annotations (usually preceding the node id):
141//   +   - preserving def,
142//   ~   - clobbering def,
143//   "   - shadow ref (follows the node id),
144//   !   - fixed register (appears after register name).
145//
146// The circular lists are not explicit in the dump.
147//
148//
149// *** Node attributes
150//
151// NodeBase has a member "Attrs", which is the primary way of determining
152// the node's characteristics. The fields in this member decide whether
153// the node is a code node or a reference node (i.e. node's "type"), then
154// within each type, the "kind" determines what specifically this node
155// represents. The remaining bits, "flags", contain additional information
156// that is even more detailed than the "kind".
157// CodeNode's kinds are:
158// - Phi:   Phi node, members are reference nodes.
159// - Stmt:  Statement, members are reference nodes.
160// - Block: Basic block, members are instruction nodes (i.e. Phi or Stmt).
161// - Func:  The whole function. The members are basic block nodes.
162// RefNode's kinds are:
163// - Use.
164// - Def.
165//
166// Meaning of flags:
167// - Preserving: applies only to defs. A preserving def is one that can
168//   preserve some of the original bits among those that are included in
169//   the register associated with that def. For example, if R0 is a 32-bit
170//   register, but a def can only change the lower 16 bits, then it will
171//   be marked as preserving.
172// - Shadow: a reference that has duplicates holding additional reaching
173//   defs (see more below).
174// - Clobbering: applied only to defs, indicates that the value generated
175//   by this def is unspecified. A typical example would be volatile registers
176//   after function calls.
177// - Fixed: the register in this def/use cannot be replaced with any other
178//   register. A typical case would be a parameter register to a call, or
179//   the register with the return value from a function.
180// - Undef: the register in this reference the register is assumed to have
181//   no pre-existing value, even if it appears to be reached by some def.
182//   This is typically used to prevent keeping registers artificially live
183//   in cases when they are defined via predicated instructions. For example:
184//     r0 = add-if-true cond, r10, r11                (1)
185//     r0 = add-if-false cond, r12, r13, implicit r0  (2)
186//     ... = r0                                       (3)
187//   Before (1), r0 is not intended to be live, and the use of r0 in (3) is
188//   not meant to be reached by any def preceding (1). However, since the
189//   defs in (1) and (2) are both preserving, these properties alone would
190//   imply that the use in (3) may indeed be reached by some prior def.
191//   Adding Undef flag to the def in (1) prevents that. The Undef flag
192//   may be applied to both defs and uses.
193// - Dead: applies only to defs. The value coming out of a "dead" def is
194//   assumed to be unused, even if the def appears to be reaching other defs
195//   or uses. The motivation for this flag comes from dead defs on function
196//   calls: there is no way to determine if such a def is dead without
197//   analyzing the target's ABI. Hence the graph should contain this info,
198//   as it is unavailable otherwise. On the other hand, a def without any
199//   uses on a typical instruction is not the intended target for this flag.
200//
201// *** Shadow references
202//
203// It may happen that a super-register can have two (or more) non-overlapping
204// sub-registers. When both of these sub-registers are defined and followed
205// by a use of the super-register, the use of the super-register will not
206// have a unique reaching def: both defs of the sub-registers need to be
207// accounted for. In such cases, a duplicate use of the super-register is
208// added and it points to the extra reaching def. Both uses are marked with
209// a flag "shadow". Example:
210// Assume t0 is a super-register of r0 and r1, r0 and r1 do not overlap:
211//   set r0, 1        ; r0 = 1
212//   set r1, 1        ; r1 = 1
213//   addi t1, t0, 1   ; t1 = t0+1
214//
215// The DFG:
216//   s1: set [d2<r0>(,,u9):]
217//   s3: set [d4<r1>(,,u10):]
218//   s5: addi [d6<t1>(,,):, u7"<t0>(d2):, u8"<t0>(d4):]
219//
220// The statement s5 has two use nodes for t0: u7" and u9". The quotation
221// mark " indicates that the node is a shadow.
222//

224#ifndef LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H
225#define LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H

227#include "RDFRegisters.h"
228#include "llvm/ADT/SmallVector.h"
229#include "llvm/MC/LaneBitmask.h"
230#include "llvm/Support/Allocator.h"
231#include "llvm/Support/MathExtras.h"
232#include <cassert>
233#include <cstdint>
234#include <cstring>
235#include <map>
236#include <set>
237#include <unordered_map>
238#include <utility>
239#include <vector>

241// RDF uses uint32_t to refer to registers. This is to ensure that the type
242// size remains specific. In other places, registers are often stored using
243// unsigned.
244static_assert(sizeof(uint32_t) == sizeof(unsigned), "Those should be equal");

246namespace llvm {

248class MachineBasicBlock;
249class MachineDominanceFrontier;
250class MachineDominatorTree;
251class MachineFunction;
252class MachineInstr;
253class MachineOperand;
254class raw_ostream;
255class TargetInstrInfo;
256class TargetRegisterInfo;

258namespace rdf {

using NodeId = uint32_t;

struct DataFlowGraph;

struct NodeAttrs {
  enum : uint16_t {
    None          = 0x0000,   // Nothing

    // Types: 2 bits
    TypeMask      = 0x0003,
    Code          = 0x0001,   // 01, Container
    Ref           = 0x0002,   // 10, Reference

    // Kind: 3 bits
    KindMask      = 0x0007 << 2,
    Def           = 0x0001 << 2,  // 001
    Use           = 0x0002 << 2,  // 010
    Phi           = 0x0003 << 2,  // 011
    Stmt          = 0x0004 << 2,  // 100
    Block         = 0x0005 << 2,  // 101
    Func          = 0x0006 << 2,  // 110

    // Flags: 7 bits for now
    FlagMask      = 0x007F << 5,
    Shadow        = 0x0001 << 5,  // 0000001, Has extra reaching defs.
    Clobbering    = 0x0002 << 5,  // 0000010, Produces unspecified values.
    PhiRef        = 0x0004 << 5,  // 0000100, Member of PhiNode.
    Preserving    = 0x0008 << 5,  // 0001000, Def can keep original bits.
    Fixed         = 0x0010 << 5,  // 0010000, Fixed register.
    Undef         = 0x0020 << 5,  // 0100000, Has no pre-existing value.
    Dead          = 0x0040 << 5,  // 1000000, Does not define a value.
  };

  static uint16_t type(uint16_t T)  { return T & TypeMask; }
  static uint16_t kind(uint16_t T)  { return T & KindMask; }
  static uint16_t flags(uint16_t T) { return T & FlagMask; }

  static uint16_t set_type(uint16_t A, uint16_t T) {
    return (A & ~TypeMask) | T;
  }

  static uint16_t set_kind(uint16_t A, uint16_t K) {
    return (A & ~KindMask) | K;
  }

  static uint16_t set_flags(uint16_t A, uint16_t F) {
    return (A & ~FlagMask) | F;
  }

  // Test if A contains B.
  static bool contains(uint16_t A, uint16_t B) {
    if (type(A) != Code)
      return false;
    uint16_t KB = kind(B);
    switch (kind(A)) {
      case Func:
        return KB == Block;
      case Block:
        return KB == Phi || KB == Stmt;
      case Phi:
      case Stmt:
        return type(B) == Ref;
    }
    return false;
  }
};

struct BuildOptions {
  enum : unsigned {
    None          = 0x00,
    KeepDeadPhis  = 0x01,   // Do not remove dead phis during build.
  };
};

template <typename T> struct NodeAddr {
  NodeAddr() = default;
  NodeAddr(T A, NodeId I) : Addr(A), Id(I) {}

  // Type cast (casting constructor). The reason for having this class
  // instead of std::pair.
  template <typename S> NodeAddr(const NodeAddr<S> &NA)
    : Addr(static_cast<T>(NA.Addr)), Id(NA.Id) {}

  bool operator== (const NodeAddr<T> &NA) const {
    assert((Addr == NA.Addr) == (Id == NA.Id))(((Addr == NA.Addr) == (Id == NA.Id)) ? static_cast<void>
 (0) : __assert_fail ("(Addr == NA.Addr) == (Id == NA.Id)", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 344, __PRETTY_FUNCTION__));
    return Addr == NA.Addr;
  }
  bool operator!= (const NodeAddr<T> &NA) const {
    return !operator==(NA);
  }

  T Addr = nullptr;
  NodeId Id = 0;
};

struct NodeBase;

// Fast memory allocation and translation between node id and node address.
// This is really the same idea as the one underlying the "bump pointer
// allocator", the difference being in the translation. A node id is
// composed of two components: the index of the block in which it was
// allocated, and the index within the block. With the default settings,
// where the number of nodes per block is 4096, the node id (minus 1) is:
//
// bit position:                11             0
// +----------------------------+--------------+
// | Index of the block         |Index in block|
// +----------------------------+--------------+
//
// The actual node id is the above plus 1, to avoid creating a node id of 0.
//
// This method significantly improved the build time, compared to using maps
// (std::unordered_map or DenseMap) to translate between pointers and ids.
struct NodeAllocator {
  // Amount of storage for a single node.
  enum { NodeMemSize = 32 };

  NodeAllocator(uint32_t NPB = 4096)
      : NodesPerBlock(NPB), BitsPerIndex(Log2_32(NPB)),
        IndexMask((1 << BitsPerIndex)-1) {
    assert(isPowerOf2_32(NPB))((isPowerOf2_32(NPB)) ? static_cast<void> (0) : __assert_fail
 ("isPowerOf2_32(NPB)", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 380, __PRETTY_FUNCTION__));
  }

  NodeBase *ptr(NodeId N) const {
    uint32_t N1 = N-1;
    uint32_t BlockN = N1 >> BitsPerIndex;
    uint32_t Offset = (N1 & IndexMask) * NodeMemSize;
    return reinterpret_cast<NodeBase*>(Blocks[BlockN]+Offset);
  }

  NodeId id(const NodeBase *P) const;
  NodeAddr<NodeBase*> New();
  void clear();

private:
  void startNewBlock();
  bool needNewBlock();

  uint32_t makeId(uint32_t Block, uint32_t Index) const {
    // Add 1 to the id, to avoid the id of 0, which is treated as "null".
    return ((Block << BitsPerIndex) | Index) + 1;
  }

  const uint32_t NodesPerBlock;
  const uint32_t BitsPerIndex;
  const uint32_t IndexMask;
  char *ActiveEnd = nullptr;
  std::vector<char*> Blocks;
  using AllocatorTy = BumpPtrAllocatorImpl<MallocAllocator, 65536>;
  AllocatorTy MemPool;
};

using RegisterSet = std::set<RegisterRef>;

struct TargetOperandInfo {
  TargetOperandInfo(const TargetInstrInfo &tii) : TII(tii) {}
  virtual ~TargetOperandInfo() = default;

  virtual bool isPreserving(const MachineInstr &In, unsigned OpNum) const;
  virtual bool isClobbering(const MachineInstr &In, unsigned OpNum) const;
  virtual bool isFixedReg(const MachineInstr &In, unsigned OpNum) const;

  const TargetInstrInfo &TII;
};

// Packed register reference. Only used for storage.
struct PackedRegisterRef {
  RegisterId Reg;
  uint32_t MaskId;
};

struct LaneMaskIndex : private IndexedSet<LaneBitmask> {
  LaneMaskIndex() = default;

  LaneBitmask getLaneMaskForIndex(uint32_t K) const {
    return K == 0 ? LaneBitmask::getAll() : get(K);
  }

  uint32_t getIndexForLaneMask(LaneBitmask LM) {
    assert(LM.any())((LM.any()) ? static_cast<void> (0) : __assert_fail ("LM.any()"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 439, __PRETTY_FUNCTION__));
    return LM.all() ? 0 : insert(LM);
  }

  uint32_t getIndexForLaneMask(LaneBitmask LM) const {
    assert(LM.any())((LM.any()) ? static_cast<void> (0) : __assert_fail ("LM.any()"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 444, __PRETTY_FUNCTION__));
    return LM.all() ? 0 : find(LM);
  }
};

struct NodeBase {
public:
  // Make sure this is a POD.
  NodeBase() = default;

  uint16_t getType()  const { return NodeAttrs::type(Attrs); }
  uint16_t getKind()  const { return NodeAttrs::kind(Attrs); }
  uint16_t getFlags() const { return NodeAttrs::flags(Attrs); }
  NodeId   getNext()  const { return Next; }

  uint16_t getAttrs() const { return Attrs; }
  void setAttrs(uint16_t A) { Attrs = A; }
  void setFlags(uint16_t F) { setAttrs(NodeAttrs::set_flags(getAttrs(), F)); }

  // Insert node NA after "this" in the circular chain.
  void append(NodeAddr<NodeBase*> NA);

  // Initialize all members to 0.
  void init() { memset(this, 0, sizeof *this); }

  void setNext(NodeId N) { Next = N; }

protected:
  uint16_t Attrs;
  uint16_t Reserved;
  NodeId Next;                // Id of the next node in the circular chain.
  // Definitions of nested types. Using anonymous nested structs would make
  // this class definition clearer, but unnamed structs are not a part of
  // the standard.
  struct Def_struct  {
    NodeId DD, DU;          // Ids of the first reached def and use.
  };
  struct PhiU_struct  {
    NodeId PredB;           // Id of the predecessor block for a phi use.
  };
  struct Code_struct {
    void *CP;               // Pointer to the actual code.
    NodeId FirstM, LastM;   // Id of the first member and last.
  };
  struct Ref_struct {
    NodeId RD, Sib;         // Ids of the reaching def and the sibling.
    union {
      Def_struct Def;
      PhiU_struct PhiU;
    };
    union {
      MachineOperand *Op;   // Non-phi refs point to a machine operand.
      PackedRegisterRef PR; // Phi refs store register info directly.
    };
  };

  // The actual payload.
  union {
    Ref_struct Ref;
    Code_struct Code;
  };
};
// The allocator allocates chunks of 32 bytes for each node. The fact that
// each node takes 32 bytes in memory is used for fast translation between
// the node id and the node address.
static_assert(sizeof(NodeBase) <= NodeAllocator::NodeMemSize,
      "NodeBase must be at most NodeAllocator::NodeMemSize bytes");

using NodeList = SmallVector<NodeAddr<NodeBase *>, 4>;
using NodeSet = std::set<NodeId>;

struct RefNode : public NodeBase {
  RefNode() = default;

  RegisterRef getRegRef(const DataFlowGraph &G) const;

  MachineOperand &getOp() {
    assert(!(getFlags() & NodeAttrs::PhiRef))((!(getFlags() & NodeAttrs::PhiRef)) ? static_cast<void
> (0) : __assert_fail ("!(getFlags() & NodeAttrs::PhiRef)"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 521, __PRETTY_FUNCTION__));
    return *Ref.Op;
  }

  void setRegRef(RegisterRef RR, DataFlowGraph &G);
  void setRegRef(MachineOperand *Op, DataFlowGraph &G);

  NodeId getReachingDef() const {
    return Ref.RD;
  }
  void setReachingDef(NodeId RD) {
    Ref.RD = RD;
  }

  NodeId getSibling() const {
    return Ref.Sib;
  }
  void setSibling(NodeId Sib) {
    Ref.Sib = Sib;
  }

  bool isUse() const {
    assert(getType() == NodeAttrs::Ref)((getType() == NodeAttrs::Ref) ? static_cast<void> (0) :
 __assert_fail ("getType() == NodeAttrs::Ref", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 543, __PRETTY_FUNCTION__));
    return getKind() == NodeAttrs::Use;
  }

  bool isDef() const {
    assert(getType() == NodeAttrs::Ref)((getType() == NodeAttrs::Ref) ? static_cast<void> (0) :
 __assert_fail ("getType() == NodeAttrs::Ref", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 548, __PRETTY_FUNCTION__));
    return getKind() == NodeAttrs::Def;
  }

  template <typename Predicate>
  NodeAddr<RefNode*> getNextRef(RegisterRef RR, Predicate P, bool NextOnly,
      const DataFlowGraph &G);
  NodeAddr<NodeBase*> getOwner(const DataFlowGraph &G);
};

struct DefNode : public RefNode {
  NodeId getReachedDef() const {
    return Ref.Def.DD;
  }
  void setReachedDef(NodeId D) {
    Ref.Def.DD = D;
  }
  NodeId getReachedUse() const {
    return Ref.Def.DU;
  }
  void setReachedUse(NodeId U) {
    Ref.Def.DU = U;
  }

  void linkToDef(NodeId Self, NodeAddr<DefNode*> DA);
};

struct UseNode : public RefNode {
  void linkToDef(NodeId Self, NodeAddr<DefNode*> DA);
};

struct PhiUseNode : public UseNode {
  NodeId getPredecessor() const {
    assert(getFlags() & NodeAttrs::PhiRef)((getFlags() & NodeAttrs::PhiRef) ? static_cast<void>
 (0) : __assert_fail ("getFlags() & NodeAttrs::PhiRef", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 581, __PRETTY_FUNCTION__));
    return Ref.PhiU.PredB;
  }
  void setPredecessor(NodeId B) {
    assert(getFlags() & NodeAttrs::PhiRef)((getFlags() & NodeAttrs::PhiRef) ? static_cast<void>
 (0) : __assert_fail ("getFlags() & NodeAttrs::PhiRef", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 585, __PRETTY_FUNCTION__));
    Ref.PhiU.PredB = B;
  }
};

struct CodeNode : public NodeBase {
  template <typename T> T getCode() const {
    return static_cast<T>(Code.CP);
  }
  void setCode(void *C) {
    Code.CP = C;
  }

  NodeAddr<NodeBase*> getFirstMember(const DataFlowGraph &G) const;
  NodeAddr<NodeBase*> getLastMember(const DataFlowGraph &G) const;
  void addMember(NodeAddr<NodeBase*> NA, const DataFlowGraph &G);
  void addMemberAfter(NodeAddr<NodeBase*> MA, NodeAddr<NodeBase*> NA,
      const DataFlowGraph &G);
  void removeMember(NodeAddr<NodeBase*> NA, const DataFlowGraph &G);

  NodeList members(const DataFlowGraph &G) const;
  template <typename Predicate>
  NodeList members_if(Predicate P, const DataFlowGraph &G) const;
};

struct InstrNode : public CodeNode {
  NodeAddr<NodeBase*> getOwner(const DataFlowGraph &G);
};

struct PhiNode : public InstrNode {
  MachineInstr *getCode() const {
    return nullptr;
  }
};

struct StmtNode : public InstrNode {
  MachineInstr *getCode() const {
    return CodeNode::getCode<MachineInstr*>();
  }
};

struct BlockNode : public CodeNode {
  MachineBasicBlock *getCode() const {
    return CodeNode::getCode<MachineBasicBlock*>();
  }

  void addPhi(NodeAddr<PhiNode*> PA, const DataFlowGraph &G);
};

struct FuncNode : public CodeNode {
  MachineFunction *getCode() const {
    return CodeNode::getCode<MachineFunction*>();
  }

  NodeAddr<BlockNode*> findBlock(const MachineBasicBlock *BB,
      const DataFlowGraph &G) const;
  NodeAddr<BlockNode*> getEntryBlock(const DataFlowGraph &G);
};

struct DataFlowGraph {
  DataFlowGraph(MachineFunction &mf, const TargetInstrInfo &tii,
      const TargetRegisterInfo &tri, const MachineDominatorTree &mdt,
      const MachineDominanceFrontier &mdf, const TargetOperandInfo &toi);

  NodeBase *ptr(NodeId N) const;
  template <typename T> T ptr(NodeId N) const {
    return static_cast<T>(ptr(N));
  }

  NodeId id(const NodeBase *P) const;

  template <typename T> NodeAddr<T> addr(NodeId N) const {
    return { ptr<T>(N), N };
  }

  NodeAddr<FuncNode*> getFunc() const { return Func; }
  MachineFunction &getMF() const { return MF; }
  const TargetInstrInfo &getTII() const { return TII; }
  const TargetRegisterInfo &getTRI() const { return TRI; }
  const PhysicalRegisterInfo &getPRI() const { return PRI; }
  const MachineDominatorTree &getDT() const { return MDT; }
  const MachineDominanceFrontier &getDF() const { return MDF; }
  const RegisterAggr &getLiveIns() const { return LiveIns; }

  struct DefStack {
    DefStack() = default;

    bool empty() const { return Stack.empty() || top() == bottom(); }

  private:
    using value_type = NodeAddr<DefNode *>;
    struct Iterator {
      using value_type = DefStack::value_type;

      Iterator &up() { Pos = DS.nextUp(Pos); return *this; }
      Iterator &down() { Pos = DS.nextDown(Pos); return *this; }

      value_type operator*() const {
        assert(Pos >= 1)((Pos >= 1) ? static_cast<void> (0) : __assert_fail (
"Pos >= 1", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 683, __PRETTY_FUNCTION__));
        return DS.Stack[Pos-1];
      }
      const value_type *operator->() const {
        assert(Pos >= 1)((Pos >= 1) ? static_cast<void> (0) : __assert_fail (
"Pos >= 1", "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 687, __PRETTY_FUNCTION__));
        return &DS.Stack[Pos-1];
      }
      bool operator==(const Iterator &It) const { return Pos == It.Pos; }
      bool operator!=(const Iterator &It) const { return Pos != It.Pos; }

    private:
      friend struct DefStack;

      Iterator(const DefStack &S, bool Top);

      // Pos-1 is the index in the StorageType object that corresponds to
      // the top of the DefStack.
      const DefStack &DS;
      unsigned Pos;
    };

  public:
    using iterator = Iterator;

    iterator top() const { return Iterator(*this, true); }
    iterator bottom() const { return Iterator(*this, false); }
    unsigned size() const;

    void push(NodeAddr<DefNode*> DA) { Stack.push_back(DA); }
    void pop();
    void start_block(NodeId N);
    void clear_block(NodeId N);

  private:
    friend struct Iterator;

    using StorageType = std::vector<value_type>;

    bool isDelimiter(const StorageType::value_type &P, NodeId N = 0) const {
      return (P.Addr == nullptr) && (N == 0 || P.Id == N);
    }

    unsigned nextUp(unsigned P) const;
    unsigned nextDown(unsigned P) const;

    StorageType Stack;
  };

  // Make this std::unordered_map for speed of accessing elements.
  // Map: Register (physical or virtual) -> DefStack
  using DefStackMap = std::unordered_map<RegisterId, DefStack>;

  void build(unsigned Options = BuildOptions::None);
  void pushAllDefs(NodeAddr<InstrNode*> IA, DefStackMap &DM);
  void markBlock(NodeId B, DefStackMap &DefM);
  void releaseBlock(NodeId B, DefStackMap &DefM);

  PackedRegisterRef pack(RegisterRef RR) {
    return { RR.Reg, LMI.getIndexForLaneMask(RR.Mask) };
  }
  PackedRegisterRef pack(RegisterRef RR) const {
    return { RR.Reg, LMI.getIndexForLaneMask(RR.Mask) };
  }
  RegisterRef unpack(PackedRegisterRef PR) const {
    return RegisterRef(PR.Reg, LMI.getLaneMaskForIndex(PR.MaskId));
  }

  RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const;
  RegisterRef makeRegRef(const MachineOperand &Op) const;
  RegisterRef restrictRef(RegisterRef AR, RegisterRef BR) const;

  NodeAddr<RefNode*> getNextRelated(NodeAddr<InstrNode*> IA,
      NodeAddr<RefNode*> RA) const;
  NodeAddr<RefNode*> getNextImp(NodeAddr<InstrNode*> IA,
      NodeAddr<RefNode*> RA, bool Create);
  NodeAddr<RefNode*> getNextImp(NodeAddr<InstrNode*> IA,
      NodeAddr<RefNode*> RA) const;
  NodeAddr<RefNode*> getNextShadow(NodeAddr<InstrNode*> IA,
      NodeAddr<RefNode*> RA, bool Create);
  NodeAddr<RefNode*> getNextShadow(NodeAddr<InstrNode*> IA,
      NodeAddr<RefNode*> RA) const;

  NodeList getRelatedRefs(NodeAddr<InstrNode*> IA,
      NodeAddr<RefNode*> RA) const;

  NodeAddr<BlockNode*> findBlock(MachineBasicBlock *BB) const {
    return BlockNodes.at(BB);
  }

  void unlinkUse(NodeAddr<UseNode*> UA, bool RemoveFromOwner) {
    unlinkUseDF(UA);
    if (RemoveFromOwner)
      removeFromOwner(UA);
  }

  void unlinkDef(NodeAddr<DefNode*> DA, bool RemoveFromOwner) {
    unlinkDefDF(DA);
    if (RemoveFromOwner)
      removeFromOwner(DA);
  }

  // Some useful filters.
  template <uint16_t Kind>
  static bool IsRef(const NodeAddr<NodeBase*> BA) {
    return BA.Addr->getType() == NodeAttrs::Ref &&
           BA.Addr->getKind() == Kind;
  }

  template <uint16_t Kind>
  static bool IsCode(const NodeAddr<NodeBase*> BA) {
    return BA.Addr->getType() == NodeAttrs::Code &&
           BA.Addr->getKind() == Kind;
  }

  static bool IsDef(const NodeAddr<NodeBase*> BA) {
    return BA.Addr->getType() == NodeAttrs::Ref &&
           BA.Addr->getKind() == NodeAttrs::Def;
  }

  static bool IsUse(const NodeAddr<NodeBase*> BA) {
    return BA.Addr->getType() == NodeAttrs::Ref &&
           BA.Addr->getKind() == NodeAttrs::Use;
  }

  static bool IsPhi(const NodeAddr<NodeBase*> BA) {
    return BA.Addr->getType() == NodeAttrs::Code &&
           BA.Addr->getKind() == NodeAttrs::Phi;
  }

  static bool IsPreservingDef(const NodeAddr<DefNode*> DA) {
    uint16_t Flags = DA.Addr->getFlags();
    return (Flags & NodeAttrs::Preserving) && !(Flags & NodeAttrs::Undef);
  }

private:
  void reset();

  RegisterSet getLandingPadLiveIns() const;

  NodeAddr<NodeBase*> newNode(uint16_t Attrs);
  NodeAddr<NodeBase*> cloneNode(const NodeAddr<NodeBase*> B);
  NodeAddr<UseNode*> newUse(NodeAddr<InstrNode*> Owner,
      MachineOperand &Op, uint16_t Flags = NodeAttrs::None);
  NodeAddr<PhiUseNode*> newPhiUse(NodeAddr<PhiNode*> Owner,
      RegisterRef RR, NodeAddr<BlockNode*> PredB,
      uint16_t Flags = NodeAttrs::PhiRef);
  NodeAddr<DefNode*> newDef(NodeAddr<InstrNode*> Owner,
      MachineOperand &Op, uint16_t Flags = NodeAttrs::None);
  NodeAddr<DefNode*> newDef(NodeAddr<InstrNode*> Owner,
      RegisterRef RR, uint16_t Flags = NodeAttrs::PhiRef);
  NodeAddr<PhiNode*> newPhi(NodeAddr<BlockNode*> Owner);
  NodeAddr<StmtNode*> newStmt(NodeAddr<BlockNode*> Owner,
      MachineInstr *MI);
  NodeAddr<BlockNode*> newBlock(NodeAddr<FuncNode*> Owner,
      MachineBasicBlock *BB);
  NodeAddr<FuncNode*> newFunc(MachineFunction *MF);

  template <typename Predicate>
  std::pair<NodeAddr<RefNode*>,NodeAddr<RefNode*>>
  locateNextRef(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA,
      Predicate P) const;

  using BlockRefsMap = std::map<NodeId, RegisterSet>;

  void buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In);
  void recordDefsForDF(BlockRefsMap &PhiM, NodeAddr<BlockNode*> BA);
  void buildPhis(BlockRefsMap &PhiM, RegisterSet &AllRefs,
      NodeAddr<BlockNode*> BA);
  void removeUnusedPhis();

  void pushClobbers(NodeAddr<InstrNode*> IA, DefStackMap &DM);
  void pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DM);
  template <typename T> void linkRefUp(NodeAddr<InstrNode*> IA,
      NodeAddr<T> TA, DefStack &DS);
  template <typename Predicate> void linkStmtRefs(DefStackMap &DefM,
      NodeAddr<StmtNode*> SA, Predicate P);
  void linkBlockRefs(DefStackMap &DefM, NodeAddr<BlockNode*> BA);

  void unlinkUseDF(NodeAddr<UseNode*> UA);
  void unlinkDefDF(NodeAddr<DefNode*> DA);

  void removeFromOwner(NodeAddr<RefNode*> RA) {
    NodeAddr<InstrNode*> IA = RA.Addr->getOwner(*this);
    IA.Addr->removeMember(RA, *this);
  }

  MachineFunction &MF;
  const TargetInstrInfo &TII;
  const TargetRegisterInfo &TRI;
  const PhysicalRegisterInfo PRI;
  const MachineDominatorTree &MDT;
  const MachineDominanceFrontier &MDF;
  const TargetOperandInfo &TOI;

  RegisterAggr LiveIns;
  NodeAddr<FuncNode*> Func;
  NodeAllocator Memory;
  // Local map:  MachineBasicBlock -> NodeAddr<BlockNode*>
  std::map<MachineBasicBlock*,NodeAddr<BlockNode*>> BlockNodes;
  // Lane mask map.
  LaneMaskIndex LMI;
};  // struct DataFlowGraph

template <typename Predicate>
NodeAddr<RefNode*> RefNode::getNextRef(RegisterRef RR, Predicate P,
      bool NextOnly, const DataFlowGraph &G) {
  // Get the "Next" reference in the circular list that references RR and
  // satisfies predicate "Pred".
  auto NA = G.addr<NodeBase*>(getNext());

  while (NA.Addr != this) {
    if (NA.Addr->getType() == NodeAttrs::Ref) {
      NodeAddr<RefNode*> RA = NA;
      if (RA.Addr->getRegRef(G) == RR && P(NA))
        return NA;
      if (NextOnly)
        break;
      NA = G.addr<NodeBase*>(NA.Addr->getNext());
    } else {
      // We've hit the beginning of the chain.
      assert(NA.Addr->getType() == NodeAttrs::Code)((NA.Addr->getType() == NodeAttrs::Code) ? static_cast<
void> (0) : __assert_fail ("NA.Addr->getType() == NodeAttrs::Code"
, "/build/llvm-toolchain-snapshot-9~svn362543/lib/Target/Hexagon/RDFGraph.h"
, 903, __PRETTY_FUNCTION__));
      NodeAddr<CodeNode*> CA = NA;
      NA = CA.Addr->getFirstMember(G);
    }
  }
  // Return the equivalent of "nullptr" if such a node was not found.
  return NodeAddr<RefNode*>();
}

template <typename Predicate>
NodeList CodeNode::members_if(Predicate P, const DataFlowGraph &G) const {
  NodeList MM;
  auto M = getFirstMember(G);
  if (M.Id == 0)
20
←
Taking false branch→
    return MM;

  while (M.Addr != this) {
21
←
Assuming the condition is true→
22
←
Loop condition is true.  Entering loop body→
24
←
Loop condition is true.  Entering loop body→
    if (P(M))
23
←
Taking false branch→
25
←
Null pointer value stored to 'NA.Addr'→
26
←
Calling 'operator()'→
      MM.push_back(M);
    M = G.addr<NodeBase*>(M.Addr->getNext());
  }
  return MM;
}

template <typename T>
struct Print {
  Print(const T &x, const DataFlowGraph &g) : Obj(x), G(g) {}

  const T &Obj;
  const DataFlowGraph &G;
};

template <typename T>
struct PrintNode : Print<NodeAddr<T>> {
  PrintNode(const NodeAddr<T> &x, const DataFlowGraph &g)
    : Print<NodeAddr<T>>(x, g) {}
};

raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterRef> &P);
raw_ostream &operator<<(raw_ostream &OS, const Print<NodeId> &P);
raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<DefNode *>> &P);
raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<UseNode *>> &P);
raw_ostream &operator<<(raw_ostream &OS,
                        const Print<NodeAddr<PhiUseNode *>> &P);
raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<RefNode *>> &P);
raw_ostream &operator<<(raw_ostream &OS, const Print<NodeList> &P);
raw_ostream &operator<<(raw_ostream &OS, const Print<NodeSet> &P);
raw_ostream &operator<<(raw_ostream &OS, const Print<NodeAddr<PhiNode *>> &P);
raw_ostream &operator<<(raw_ostream &OS,
                        const Print<NodeAddr<StmtNode *>> &P);
raw_ostream &operator<<(raw_ostream &OS,
                        const Print<NodeAddr<InstrNode *>> &P);
raw_ostream &operator<<(raw_ostream &OS,
                        const Print<NodeAddr<BlockNode *>> &P);
raw_ostream &operator<<(raw_ostream &OS,
                        const Print<NodeAddr<FuncNode *>> &P);
raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterSet> &P);
raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterAggr> &P);
raw_ostream &operator<<(raw_ostream &OS,
                        const Print<DataFlowGraph::DefStack> &P);

964} // end namespace rdf

966} // end namespace llvm

968#endif // LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H