Bug Summary

File:llvm/lib/CodeGen/RegisterClassInfo.cpp
Warning:line 190, column 24
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name RegisterClassInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/include -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-12-09-002921-48462-1 -x c++ /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/RegisterClassInfo.cpp
1//===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RegisterClassInfo class which provides dynamic
10// information about target register classes. Callee-saved vs. caller-saved and
11// reserved registers depend on calling conventions and other dynamic
12// information, so some things cannot be determined statically.
13//
14//===----------------------------------------------------------------------===//
15
16#include "llvm/CodeGen/RegisterClassInfo.h"
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/BitVector.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/TargetFrameLowering.h"
23#include "llvm/CodeGen/TargetRegisterInfo.h"
24#include "llvm/CodeGen/TargetSubtargetInfo.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/Support/CommandLine.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/raw_ostream.h"
29#include <algorithm>
30#include <cassert>
31#include <cstdint>
32
33using namespace llvm;
34
35#define DEBUG_TYPE"regalloc" "regalloc"
36
37static cl::opt<unsigned>
38StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
39 cl::desc("Limit all regclasses to N registers"));
40
41RegisterClassInfo::RegisterClassInfo() = default;
42
43void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
44 bool Update = false;
45 MF = &mf;
46
47 // Allocate new array the first time we see a new target.
48 if (MF->getSubtarget().getRegisterInfo() != TRI) {
49 TRI = MF->getSubtarget().getRegisterInfo();
50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
51 Update = true;
52 }
53
54 // Does this MF have different CSRs?
55 assert(TRI && "no register info set")((TRI && "no register info set") ? static_cast<void
> (0) : __assert_fail ("TRI && \"no register info set\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/RegisterClassInfo.cpp"
, 55, __PRETTY_FUNCTION__))
;
56
57 // Get the callee saved registers.
58 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
59 if (Update || CSR != CalleeSavedRegs) {
60 // Build a CSRAlias map. Every CSR alias saves the last
61 // overlapping CSR.
62 CalleeSavedAliases.resize(TRI->getNumRegs(), 0);
63 for (const MCPhysReg *I = CSR; *I; ++I)
64 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
65 CalleeSavedAliases[*AI] = *I;
66
67 Update = true;
68 }
69 CalleeSavedRegs = CSR;
70
71 // Different reserved registers?
72 const BitVector &RR = MF->getRegInfo().getReservedRegs();
73 if (Reserved.size() != RR.size() || RR != Reserved) {
74 Update = true;
75 Reserved = RR;
76 }
77
78 // Invalidate cached information from previous function.
79 if (Update) {
80 unsigned NumPSets = TRI->getNumRegPressureSets();
81 PSetLimits.reset(new unsigned[NumPSets]);
82 std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
83 ++Tag;
84 }
85}
86
87/// compute - Compute the preferred allocation order for RC with reserved
88/// registers filtered out. Volatile registers come first followed by CSR
89/// aliases ordered according to the CSR order specified by the target.
90void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
91 assert(RC && "no register class given")((RC && "no register class given") ? static_cast<void
> (0) : __assert_fail ("RC && \"no register class given\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/RegisterClassInfo.cpp"
, 91, __PRETTY_FUNCTION__))
;
92 RCInfo &RCI = RegClass[RC->getID()];
93 auto &STI = MF->getSubtarget();
94
95 // Raw register count, including all reserved regs.
96 unsigned NumRegs = RC->getNumRegs();
97
98 if (!RCI.Order)
99 RCI.Order.reset(new MCPhysReg[NumRegs]);
100
101 unsigned N = 0;
102 SmallVector<MCPhysReg, 16> CSRAlias;
103 unsigned MinCost = 0xff;
104 unsigned LastCost = ~0u;
105 unsigned LastCostChange = 0;
106
107 // FIXME: Once targets reserve registers instead of removing them from the
108 // allocation order, we can simply use begin/end here.
109 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
110 for (unsigned i = 0; i != RawOrder.size(); ++i) {
111 unsigned PhysReg = RawOrder[i];
112 // Remove reserved registers from the allocation order.
113 if (Reserved.test(PhysReg))
114 continue;
115 unsigned Cost = TRI->getCostPerUse(PhysReg);
116 MinCost = std::min(MinCost, Cost);
117
118 if (CalleeSavedAliases[PhysReg] &&
119 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg))
120 // PhysReg aliases a CSR, save it for later.
121 CSRAlias.push_back(PhysReg);
122 else {
123 if (Cost != LastCost)
124 LastCostChange = N;
125 RCI.Order[N++] = PhysReg;
126 LastCost = Cost;
127 }
128 }
129 RCI.NumRegs = N + CSRAlias.size();
130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass")((RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"
) ? static_cast<void> (0) : __assert_fail ("RCI.NumRegs <= NumRegs && \"Allocation order larger than regclass\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/CodeGen/RegisterClassInfo.cpp"
, 130, __PRETTY_FUNCTION__))
;
131
132 // CSR aliases go after the volatile registers, preserve the target's order.
133 for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
134 unsigned PhysReg = CSRAlias[i];
135 unsigned Cost = TRI->getCostPerUse(PhysReg);
136 if (Cost != LastCost)
137 LastCostChange = N;
138 RCI.Order[N++] = PhysReg;
139 LastCost = Cost;
140 }
141
142 // Register allocator stress test. Clip register class to N registers.
143 if (StressRA && RCI.NumRegs > StressRA)
144 RCI.NumRegs = StressRA;
145
146 // Check if RC is a proper sub-class.
147 if (const TargetRegisterClass *Super =
148 TRI->getLargestLegalSuperClass(RC, *MF))
149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
150 RCI.ProperSubClass = true;
151
152 RCI.MinCost = uint8_t(MinCost);
153 RCI.LastCostChange = LastCostChange;
154
155 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
156 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
157 for (unsigned I = 0; I != RCI.NumRegs; ++I)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
158 dbgs() << ' ' << printReg(RCI.Order[I], TRI);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
159 dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
160 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "AllocationOrder(" <<
TRI->getRegClassName(RC) << ") = ["; for (unsigned I
= 0; I != RCI.NumRegs; ++I) dbgs() << ' ' << printReg
(RCI.Order[I], TRI); dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n"
: " ]\n"); }; } } while (false)
;
161
162 // RCI is now up-to-date.
163 RCI.Tag = Tag;
164}
165
166/// This is not accurate because two overlapping register sets may have some
167/// nonoverlapping reserved registers. However, computing the allocation order
168/// for all register classes would be too expensive.
169unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
170 const TargetRegisterClass *RC = nullptr;
1
'RC' initialized to a null pointer value
171 unsigned NumRCUnits = 0;
172 for (const TargetRegisterClass *C : TRI->regclasses()) {
2
Assuming '__begin1' is not equal to '__end1'
173 const int *PSetID = TRI->getRegClassPressureSets(C);
174 for (; *PSetID != -1; ++PSetID) {
3
Assuming the condition is false
4
Loop condition is false. Execution continues on line 178
7
Assuming the condition is false
8
Loop condition is false. Execution continues on line 178
11
Assuming the condition is false
12
Loop condition is false. Execution continues on line 178
175 if ((unsigned)*PSetID == Idx)
176 break;
177 }
178 if (*PSetID == -1)
5
Taking true branch
9
Taking true branch
13
Taking true branch
179 continue;
6
Execution continues on line 172
10
Execution continues on line 172
14
Execution continues on line 172
180
181 // Found a register class that counts against this pressure set.
182 // For efficiency, only compute the set order for the largest set.
183 unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
184 if (!RC || NUnits > NumRCUnits) {
185 RC = C;
186 NumRCUnits = NUnits;
187 }
188 }
189 compute(RC);
190 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
15
Called C++ object pointer is null
191 return TRI->getRegPressureSetLimit(*MF, Idx) -
192 TRI->getRegClassWeight(RC).RegWeight * NReserved;
193}