Bug Summary

File:llvm/lib/CodeGen/RegisterCoalescer.cpp
Warning:line 2470, column 11
Called C++ object pointer is null

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name RegisterCoalescer.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb=. -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-09-26-161721-17566-1 -x c++ /build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp

/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp

1//===- RegisterCoalescer.cpp - Generic Register Coalescing Interface ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the generic RegisterCoalescer interface which
10// is used as the common interface used by all clients and
11// implementations of register coalescing.
12//
13//===----------------------------------------------------------------------===//
14
15#include "RegisterCoalescer.h"
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/BitVector.h"
18#include "llvm/ADT/DenseSet.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SmallPtrSet.h"
21#include "llvm/ADT/SmallVector.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/CodeGen/LiveInterval.h"
25#include "llvm/CodeGen/LiveIntervals.h"
26#include "llvm/CodeGen/LiveRangeEdit.h"
27#include "llvm/CodeGen/MachineBasicBlock.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
32#include "llvm/CodeGen/MachineLoopInfo.h"
33#include "llvm/CodeGen/MachineOperand.h"
34#include "llvm/CodeGen/MachineRegisterInfo.h"
35#include "llvm/CodeGen/Passes.h"
36#include "llvm/CodeGen/RegisterClassInfo.h"
37#include "llvm/CodeGen/SlotIndexes.h"
38#include "llvm/CodeGen/TargetInstrInfo.h"
39#include "llvm/CodeGen/TargetOpcodes.h"
40#include "llvm/CodeGen/TargetRegisterInfo.h"
41#include "llvm/CodeGen/TargetSubtargetInfo.h"
42#include "llvm/IR/DebugLoc.h"
43#include "llvm/InitializePasses.h"
44#include "llvm/MC/LaneBitmask.h"
45#include "llvm/MC/MCInstrDesc.h"
46#include "llvm/MC/MCRegisterInfo.h"
47#include "llvm/Pass.h"
48#include "llvm/Support/CommandLine.h"
49#include "llvm/Support/Compiler.h"
50#include "llvm/Support/Debug.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/raw_ostream.h"
53#include <algorithm>
54#include <cassert>
55#include <iterator>
56#include <limits>
57#include <tuple>
58#include <utility>
59#include <vector>
60
61using namespace llvm;
62
63#define DEBUG_TYPE"regalloc" "regalloc"
64
65STATISTIC(numJoins , "Number of interval joins performed")static llvm::Statistic numJoins = {"regalloc", "numJoins", "Number of interval joins performed"
}
;
66STATISTIC(numCrossRCs , "Number of cross class joins performed")static llvm::Statistic numCrossRCs = {"regalloc", "numCrossRCs"
, "Number of cross class joins performed"}
;
67STATISTIC(numCommutes , "Number of instruction commuting performed")static llvm::Statistic numCommutes = {"regalloc", "numCommutes"
, "Number of instruction commuting performed"}
;
68STATISTIC(numExtends , "Number of copies extended")static llvm::Statistic numExtends = {"regalloc", "numExtends"
, "Number of copies extended"}
;
69STATISTIC(NumReMats , "Number of instructions re-materialized")static llvm::Statistic NumReMats = {"regalloc", "NumReMats", "Number of instructions re-materialized"
}
;
70STATISTIC(NumInflated , "Number of register classes inflated")static llvm::Statistic NumInflated = {"regalloc", "NumInflated"
, "Number of register classes inflated"}
;
71STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested")static llvm::Statistic NumLaneConflicts = {"regalloc", "NumLaneConflicts"
, "Number of dead lane conflicts tested"}
;
72STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved")static llvm::Statistic NumLaneResolves = {"regalloc", "NumLaneResolves"
, "Number of dead lane conflicts resolved"}
;
73STATISTIC(NumShrinkToUses, "Number of shrinkToUses called")static llvm::Statistic NumShrinkToUses = {"regalloc", "NumShrinkToUses"
, "Number of shrinkToUses called"}
;
74
75static cl::opt<bool> EnableJoining("join-liveintervals",
76 cl::desc("Coalesce copies (default=true)"),
77 cl::init(true), cl::Hidden);
78
79static cl::opt<bool> UseTerminalRule("terminal-rule",
80 cl::desc("Apply the terminal rule"),
81 cl::init(false), cl::Hidden);
82
83/// Temporary flag to test critical edge unsplitting.
84static cl::opt<bool>
85EnableJoinSplits("join-splitedges",
86 cl::desc("Coalesce copies on split edges (default=subtarget)"), cl::Hidden);
87
88/// Temporary flag to test global copy optimization.
89static cl::opt<cl::boolOrDefault>
90EnableGlobalCopies("join-globalcopies",
91 cl::desc("Coalesce copies that span blocks (default=subtarget)"),
92 cl::init(cl::BOU_UNSET), cl::Hidden);
93
94static cl::opt<bool>
95VerifyCoalescing("verify-coalescing",
96 cl::desc("Verify machine instrs before and after register coalescing"),
97 cl::Hidden);
98
99static cl::opt<unsigned> LateRematUpdateThreshold(
100 "late-remat-update-threshold", cl::Hidden,
101 cl::desc("During rematerialization for a copy, if the def instruction has "
102 "many other copy uses to be rematerialized, delay the multiple "
103 "separate live interval update work and do them all at once after "
104 "all those rematerialization are done. It will save a lot of "
105 "repeated work. "),
106 cl::init(100));
107
108static cl::opt<unsigned> LargeIntervalSizeThreshold(
109 "large-interval-size-threshold", cl::Hidden,
110 cl::desc("If the valnos size of an interval is larger than the threshold, "
111 "it is regarded as a large interval. "),
112 cl::init(100));
113
114static cl::opt<unsigned> LargeIntervalFreqThreshold(
115 "large-interval-freq-threshold", cl::Hidden,
116 cl::desc("For a large interval, if it is coalesed with other live "
117 "intervals many times more than the threshold, stop its "
118 "coalescing to control the compile time. "),
119 cl::init(100));
120
121namespace {
122
123 class JoinVals;
124
125 class RegisterCoalescer : public MachineFunctionPass,
126 private LiveRangeEdit::Delegate {
127 MachineFunction* MF = nullptr;
128 MachineRegisterInfo* MRI = nullptr;
129 const TargetRegisterInfo* TRI = nullptr;
130 const TargetInstrInfo* TII = nullptr;
131 LiveIntervals *LIS = nullptr;
132 const MachineLoopInfo* Loops = nullptr;
133 AliasAnalysis *AA = nullptr;
134 RegisterClassInfo RegClassInfo;
135
136 /// Debug variable location tracking -- for each VReg, maintain an
137 /// ordered-by-slot-index set of DBG_VALUEs, to help quick
138 /// identification of whether coalescing may change location validity.
139 using DbgValueLoc = std::pair<SlotIndex, MachineInstr*>;
140 DenseMap<unsigned, std::vector<DbgValueLoc>> DbgVRegToValues;
141
142 /// VRegs may be repeatedly coalesced, and have many DBG_VALUEs attached.
143 /// To avoid repeatedly merging sets of DbgValueLocs, instead record
144 /// which vregs have been coalesced, and where to. This map is from
145 /// vreg => {set of vregs merged in}.
146 DenseMap<unsigned, SmallVector<unsigned, 4>> DbgMergedVRegNums;
147
148 /// A LaneMask to remember on which subregister live ranges we need to call
149 /// shrinkToUses() later.
150 LaneBitmask ShrinkMask;
151
152 /// True if the main range of the currently coalesced intervals should be
153 /// checked for smaller live intervals.
154 bool ShrinkMainRange = false;
155
156 /// True if the coalescer should aggressively coalesce global copies
157 /// in favor of keeping local copies.
158 bool JoinGlobalCopies = false;
159
160 /// True if the coalescer should aggressively coalesce fall-thru
161 /// blocks exclusively containing copies.
162 bool JoinSplitEdges = false;
163
164 /// Copy instructions yet to be coalesced.
165 SmallVector<MachineInstr*, 8> WorkList;
166 SmallVector<MachineInstr*, 8> LocalWorkList;
167
168 /// Set of instruction pointers that have been erased, and
169 /// that may be present in WorkList.
170 SmallPtrSet<MachineInstr*, 8> ErasedInstrs;
171
172 /// Dead instructions that are about to be deleted.
173 SmallVector<MachineInstr*, 8> DeadDefs;
174
175 /// Virtual registers to be considered for register class inflation.
176 SmallVector<unsigned, 8> InflateRegs;
177
178 /// The collection of live intervals which should have been updated
179 /// immediately after rematerialiation but delayed until
180 /// lateLiveIntervalUpdate is called.
181 DenseSet<unsigned> ToBeUpdated;
182
183 /// Record how many times the large live interval with many valnos
184 /// has been tried to join with other live interval.
185 DenseMap<unsigned, unsigned long> LargeLIVisitCounter;
186
187 /// Recursively eliminate dead defs in DeadDefs.
188 void eliminateDeadDefs();
189
190 /// LiveRangeEdit callback for eliminateDeadDefs().
191 void LRE_WillEraseInstruction(MachineInstr *MI) override;
192
193 /// Coalesce the LocalWorkList.
194 void coalesceLocals();
195
196 /// Join compatible live intervals
197 void joinAllIntervals();
198
199 /// Coalesce copies in the specified MBB, putting
200 /// copies that cannot yet be coalesced into WorkList.
201 void copyCoalesceInMBB(MachineBasicBlock *MBB);
202
203 /// Tries to coalesce all copies in CurrList. Returns true if any progress
204 /// was made.
205 bool copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList);
206
207 /// If one def has many copy like uses, and those copy uses are all
208 /// rematerialized, the live interval update needed for those
209 /// rematerializations will be delayed and done all at once instead
210 /// of being done multiple times. This is to save compile cost because
211 /// live interval update is costly.
212 void lateLiveIntervalUpdate();
213
214 /// Attempt to join intervals corresponding to SrcReg/DstReg, which are the
215 /// src/dst of the copy instruction CopyMI. This returns true if the copy
216 /// was successfully coalesced away. If it is not currently possible to
217 /// coalesce this interval, but it may be possible if other things get
218 /// coalesced, then it returns true by reference in 'Again'.
219 bool joinCopy(MachineInstr *CopyMI, bool &Again);
220
221 /// Attempt to join these two intervals. On failure, this
222 /// returns false. The output "SrcInt" will not have been modified, so we
223 /// can use this information below to update aliases.
224 bool joinIntervals(CoalescerPair &CP);
225
226 /// Attempt joining two virtual registers. Return true on success.
227 bool joinVirtRegs(CoalescerPair &CP);
228
229 /// If a live interval has many valnos and is coalesced with other
230 /// live intervals many times, we regard such live interval as having
231 /// high compile time cost.
232 bool isHighCostLiveInterval(LiveInterval &LI);
233
234 /// Attempt joining with a reserved physreg.
235 bool joinReservedPhysReg(CoalescerPair &CP);
236
237 /// Add the LiveRange @p ToMerge as a subregister liverange of @p LI.
238 /// Subranges in @p LI which only partially interfere with the desired
239 /// LaneMask are split as necessary. @p LaneMask are the lanes that
240 /// @p ToMerge will occupy in the coalescer register. @p LI has its subrange
241 /// lanemasks already adjusted to the coalesced register.
242 void mergeSubRangeInto(LiveInterval &LI, const LiveRange &ToMerge,
243 LaneBitmask LaneMask, CoalescerPair &CP,
244 unsigned DstIdx);
245
246 /// Join the liveranges of two subregisters. Joins @p RRange into
247 /// @p LRange, @p RRange may be invalid afterwards.
248 void joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
249 LaneBitmask LaneMask, const CoalescerPair &CP);
250
251 /// We found a non-trivially-coalescable copy. If the source value number is
252 /// defined by a copy from the destination reg see if we can merge these two
253 /// destination reg valno# into a single value number, eliminating a copy.
254 /// This returns true if an interval was modified.
255 bool adjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI);
256
257 /// Return true if there are definitions of IntB
258 /// other than BValNo val# that can reach uses of AValno val# of IntA.
259 bool hasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
260 VNInfo *AValNo, VNInfo *BValNo);
261
262 /// We found a non-trivially-coalescable copy.
263 /// If the source value number is defined by a commutable instruction and
264 /// its other operand is coalesced to the copy dest register, see if we
265 /// can transform the copy into a noop by commuting the definition.
266 /// This returns a pair of two flags:
267 /// - the first element is true if an interval was modified,
268 /// - the second element is true if the destination interval needs
269 /// to be shrunk after deleting the copy.
270 std::pair<bool,bool> removeCopyByCommutingDef(const CoalescerPair &CP,
271 MachineInstr *CopyMI);
272
273 /// We found a copy which can be moved to its less frequent predecessor.
274 bool removePartialRedundancy(const CoalescerPair &CP, MachineInstr &CopyMI);
275
276 /// If the source of a copy is defined by a
277 /// trivial computation, replace the copy by rematerialize the definition.
278 bool reMaterializeTrivialDef(const CoalescerPair &CP, MachineInstr *CopyMI,
279 bool &IsDefCopy);
280
281 /// Return true if a copy involving a physreg should be joined.
282 bool canJoinPhys(const CoalescerPair &CP);
283
284 /// Replace all defs and uses of SrcReg to DstReg and update the subregister
285 /// number if it is not zero. If DstReg is a physical register and the
286 /// existing subregister number of the def / use being updated is not zero,
287 /// make sure to set it to the correct physical subregister.
288 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
289
290 /// If the given machine operand reads only undefined lanes add an undef
291 /// flag.
292 /// This can happen when undef uses were previously concealed by a copy
293 /// which we coalesced. Example:
294 /// %0:sub0<def,read-undef> = ...
295 /// %1 = COPY %0 <-- Coalescing COPY reveals undef
296 /// = use %1:sub1 <-- hidden undef use
297 void addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
298 MachineOperand &MO, unsigned SubRegIdx);
299
300 /// Handle copies of undef values. If the undef value is an incoming
301 /// PHI value, it will convert @p CopyMI to an IMPLICIT_DEF.
302 /// Returns nullptr if @p CopyMI was not in any way eliminable. Otherwise,
303 /// it returns @p CopyMI (which could be an IMPLICIT_DEF at this point).
304 MachineInstr *eliminateUndefCopy(MachineInstr *CopyMI);
305
306 /// Check whether or not we should apply the terminal rule on the
307 /// destination (Dst) of \p Copy.
308 /// When the terminal rule applies, Copy is not profitable to
309 /// coalesce.
310 /// Dst is terminal if it has exactly one affinity (Dst, Src) and
311 /// at least one interference (Dst, Dst2). If Dst is terminal, the
312 /// terminal rule consists in checking that at least one of
313 /// interfering node, say Dst2, has an affinity of equal or greater
314 /// weight with Src.
315 /// In that case, Dst2 and Dst will not be able to be both coalesced
316 /// with Src. Since Dst2 exposes more coalescing opportunities than
317 /// Dst, we can drop \p Copy.
318 bool applyTerminalRule(const MachineInstr &Copy) const;
319
320 /// Wrapper method for \see LiveIntervals::shrinkToUses.
321 /// This method does the proper fixing of the live-ranges when the afore
322 /// mentioned method returns true.
323 void shrinkToUses(LiveInterval *LI,
324 SmallVectorImpl<MachineInstr * > *Dead = nullptr) {
325 NumShrinkToUses++;
326 if (LIS->shrinkToUses(LI, Dead)) {
327 /// Check whether or not \p LI is composed by multiple connected
328 /// components and if that is the case, fix that.
329 SmallVector<LiveInterval*, 8> SplitLIs;
330 LIS->splitSeparateComponents(*LI, SplitLIs);
331 }
332 }
333
334 /// Wrapper Method to do all the necessary work when an Instruction is
335 /// deleted.
336 /// Optimizations should use this to make sure that deleted instructions
337 /// are always accounted for.
338 void deleteInstr(MachineInstr* MI) {
339 ErasedInstrs.insert(MI);
340 LIS->RemoveMachineInstrFromMaps(*MI);
341 MI->eraseFromParent();
342 }
343
344 /// Walk over function and initialize the DbgVRegToValues map.
345 void buildVRegToDbgValueMap(MachineFunction &MF);
346
347 /// Test whether, after merging, any DBG_VALUEs would refer to a
348 /// different value number than before merging, and whether this can
349 /// be resolved. If not, mark the DBG_VALUE as being undef.
350 void checkMergingChangesDbgValues(CoalescerPair &CP, LiveRange &LHS,
351 JoinVals &LHSVals, LiveRange &RHS,
352 JoinVals &RHSVals);
353
354 void checkMergingChangesDbgValuesImpl(unsigned Reg, LiveRange &OtherRange,
355 LiveRange &RegRange, JoinVals &Vals2);
356
357 public:
358 static char ID; ///< Class identification, replacement for typeinfo
359
360 RegisterCoalescer() : MachineFunctionPass(ID) {
361 initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
362 }
363
364 void getAnalysisUsage(AnalysisUsage &AU) const override;
365
366 void releaseMemory() override;
367
368 /// This is the pass entry point.
369 bool runOnMachineFunction(MachineFunction&) override;
370
371 /// Implement the dump method.
372 void print(raw_ostream &O, const Module* = nullptr) const override;
373 };
374
375} // end anonymous namespace
376
377char RegisterCoalescer::ID = 0;
378
379char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
380
381INITIALIZE_PASS_BEGIN(RegisterCoalescer, "simple-register-coalescing",static void *initializeRegisterCoalescerPassOnce(PassRegistry
&Registry) {
382 "Simple Register Coalescing", false, false)static void *initializeRegisterCoalescerPassOnce(PassRegistry
&Registry) {
383INITIALIZE_PASS_DEPENDENCY(LiveIntervals)initializeLiveIntervalsPass(Registry);
384INITIALIZE_PASS_DEPENDENCY(SlotIndexes)initializeSlotIndexesPass(Registry);
385INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)initializeMachineLoopInfoPass(Registry);
386INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)initializeAAResultsWrapperPassPass(Registry);
387INITIALIZE_PASS_END(RegisterCoalescer, "simple-register-coalescing",PassInfo *PI = new PassInfo( "Simple Register Coalescing", "simple-register-coalescing"
, &RegisterCoalescer::ID, PassInfo::NormalCtor_t(callDefaultCtor
<RegisterCoalescer>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeRegisterCoalescerPassFlag
; void llvm::initializeRegisterCoalescerPass(PassRegistry &
Registry) { llvm::call_once(InitializeRegisterCoalescerPassFlag
, initializeRegisterCoalescerPassOnce, std::ref(Registry)); }
388 "Simple Register Coalescing", false, false)PassInfo *PI = new PassInfo( "Simple Register Coalescing", "simple-register-coalescing"
, &RegisterCoalescer::ID, PassInfo::NormalCtor_t(callDefaultCtor
<RegisterCoalescer>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeRegisterCoalescerPassFlag
; void llvm::initializeRegisterCoalescerPass(PassRegistry &
Registry) { llvm::call_once(InitializeRegisterCoalescerPassFlag
, initializeRegisterCoalescerPassOnce, std::ref(Registry)); }
389
390LLVM_NODISCARD[[clang::warn_unused_result]] static bool isMoveInstr(const TargetRegisterInfo &tri,
391 const MachineInstr *MI, unsigned &Src,
392 unsigned &Dst, unsigned &SrcSub,
393 unsigned &DstSub) {
394 if (MI->isCopy()) {
395 Dst = MI->getOperand(0).getReg();
396 DstSub = MI->getOperand(0).getSubReg();
397 Src = MI->getOperand(1).getReg();
398 SrcSub = MI->getOperand(1).getSubReg();
399 } else if (MI->isSubregToReg()) {
400 Dst = MI->getOperand(0).getReg();
401 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
402 MI->getOperand(3).getImm());
403 Src = MI->getOperand(2).getReg();
404 SrcSub = MI->getOperand(2).getSubReg();
405 } else
406 return false;
407 return true;
408}
409
410/// Return true if this block should be vacated by the coalescer to eliminate
411/// branches. The important cases to handle in the coalescer are critical edges
412/// split during phi elimination which contain only copies. Simple blocks that
413/// contain non-branches should also be vacated, but this can be handled by an
414/// earlier pass similar to early if-conversion.
415static bool isSplitEdge(const MachineBasicBlock *MBB) {
416 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
417 return false;
418
419 for (const auto &MI : *MBB) {
420 if (!MI.isCopyLike() && !MI.isUnconditionalBranch())
421 return false;
422 }
423 return true;
424}
425
426bool CoalescerPair::setRegisters(const MachineInstr *MI) {
427 SrcReg = DstReg = 0;
428 SrcIdx = DstIdx = 0;
429 NewRC = nullptr;
430 Flipped = CrossClass = false;
431
432 unsigned Src, Dst, SrcSub, DstSub;
433 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
434 return false;
435 Partial = SrcSub || DstSub;
436
437 // If one register is a physreg, it must be Dst.
438 if (Register::isPhysicalRegister(Src)) {
439 if (Register::isPhysicalRegister(Dst))
440 return false;
441 std::swap(Src, Dst);
442 std::swap(SrcSub, DstSub);
443 Flipped = true;
444 }
445
446 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
447
448 if (Register::isPhysicalRegister(Dst)) {
449 // Eliminate DstSub on a physreg.
450 if (DstSub) {
451 Dst = TRI.getSubReg(Dst, DstSub);
452 if (!Dst) return false;
453 DstSub = 0;
454 }
455
456 // Eliminate SrcSub by picking a corresponding Dst superregister.
457 if (SrcSub) {
458 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
459 if (!Dst) return false;
460 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
461 return false;
462 }
463 } else {
464 // Both registers are virtual.
465 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
466 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
467
468 // Both registers have subreg indices.
469 if (SrcSub && DstSub) {
470 // Copies between different sub-registers are never coalescable.
471 if (Src == Dst && SrcSub != DstSub)
472 return false;
473
474 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
475 SrcIdx, DstIdx);
476 if (!NewRC)
477 return false;
478 } else if (DstSub) {
479 // SrcReg will be merged with a sub-register of DstReg.
480 SrcIdx = DstSub;
481 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
482 } else if (SrcSub) {
483 // DstReg will be merged with a sub-register of SrcReg.
484 DstIdx = SrcSub;
485 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
486 } else {
487 // This is a straight copy without sub-registers.
488 NewRC = TRI.getCommonSubClass(DstRC, SrcRC);
489 }
490
491 // The combined constraint may be impossible to satisfy.
492 if (!NewRC)
493 return false;
494
495 // Prefer SrcReg to be a sub-register of DstReg.
496 // FIXME: Coalescer should support subregs symmetrically.
497 if (DstIdx && !SrcIdx) {
498 std::swap(Src, Dst);
499 std::swap(SrcIdx, DstIdx);
500 Flipped = !Flipped;
501 }
502
503 CrossClass = NewRC != DstRC || NewRC != SrcRC;
504 }
505 // Check our invariants
506 assert(Register::isVirtualRegister(Src) && "Src must be virtual")((Register::isVirtualRegister(Src) && "Src must be virtual"
) ? static_cast<void> (0) : __assert_fail ("Register::isVirtualRegister(Src) && \"Src must be virtual\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 506, __PRETTY_FUNCTION__))
;
507 assert(!(Register::isPhysicalRegister(Dst) && DstSub) &&((!(Register::isPhysicalRegister(Dst) && DstSub) &&
"Cannot have a physical SubIdx") ? static_cast<void> (
0) : __assert_fail ("!(Register::isPhysicalRegister(Dst) && DstSub) && \"Cannot have a physical SubIdx\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 508, __PRETTY_FUNCTION__))
508 "Cannot have a physical SubIdx")((!(Register::isPhysicalRegister(Dst) && DstSub) &&
"Cannot have a physical SubIdx") ? static_cast<void> (
0) : __assert_fail ("!(Register::isPhysicalRegister(Dst) && DstSub) && \"Cannot have a physical SubIdx\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 508, __PRETTY_FUNCTION__))
;
509 SrcReg = Src;
510 DstReg = Dst;
511 return true;
512}
513
514bool CoalescerPair::flip() {
515 if (Register::isPhysicalRegister(DstReg))
516 return false;
517 std::swap(SrcReg, DstReg);
518 std::swap(SrcIdx, DstIdx);
519 Flipped = !Flipped;
520 return true;
521}
522
523bool CoalescerPair::isCoalescable(const MachineInstr *MI) const {
524 if (!MI)
525 return false;
526 unsigned Src, Dst, SrcSub, DstSub;
527 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
528 return false;
529
530 // Find the virtual register that is SrcReg.
531 if (Dst == SrcReg) {
532 std::swap(Src, Dst);
533 std::swap(SrcSub, DstSub);
534 } else if (Src != SrcReg) {
535 return false;
536 }
537
538 // Now check that Dst matches DstReg.
539 if (Register::isPhysicalRegister(DstReg)) {
540 if (!Register::isPhysicalRegister(Dst))
541 return false;
542 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state.")((!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."
) ? static_cast<void> (0) : __assert_fail ("!DstIdx && !SrcIdx && \"Inconsistent CoalescerPair state.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 542, __PRETTY_FUNCTION__))
;
543 // DstSub could be set for a physreg from INSERT_SUBREG.
544 if (DstSub)
545 Dst = TRI.getSubReg(Dst, DstSub);
546 // Full copy of Src.
547 if (!SrcSub)
548 return DstReg == Dst;
549 // This is a partial register copy. Check that the parts match.
550 return TRI.getSubReg(DstReg, SrcSub) == Dst;
551 } else {
552 // DstReg is virtual.
553 if (DstReg != Dst)
554 return false;
555 // Registers match, do the subregisters line up?
556 return TRI.composeSubRegIndices(SrcIdx, SrcSub) ==
557 TRI.composeSubRegIndices(DstIdx, DstSub);
558 }
559}
560
561void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
562 AU.setPreservesCFG();
563 AU.addRequired<AAResultsWrapperPass>();
564 AU.addRequired<LiveIntervals>();
565 AU.addPreserved<LiveIntervals>();
566 AU.addPreserved<SlotIndexes>();
567 AU.addRequired<MachineLoopInfo>();
568 AU.addPreserved<MachineLoopInfo>();
569 AU.addPreservedID(MachineDominatorsID);
570 MachineFunctionPass::getAnalysisUsage(AU);
571}
572
573void RegisterCoalescer::eliminateDeadDefs() {
574 SmallVector<Register, 8> NewRegs;
575 LiveRangeEdit(nullptr, NewRegs, *MF, *LIS,
576 nullptr, this).eliminateDeadDefs(DeadDefs);
577}
578
579void RegisterCoalescer::LRE_WillEraseInstruction(MachineInstr *MI) {
580 // MI may be in WorkList. Make sure we don't visit it.
581 ErasedInstrs.insert(MI);
582}
583
584bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP,
585 MachineInstr *CopyMI) {
586 assert(!CP.isPartial() && "This doesn't work for partial copies.")((!CP.isPartial() && "This doesn't work for partial copies."
) ? static_cast<void> (0) : __assert_fail ("!CP.isPartial() && \"This doesn't work for partial copies.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 586, __PRETTY_FUNCTION__))
;
587 assert(!CP.isPhys() && "This doesn't work for physreg copies.")((!CP.isPhys() && "This doesn't work for physreg copies."
) ? static_cast<void> (0) : __assert_fail ("!CP.isPhys() && \"This doesn't work for physreg copies.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 587, __PRETTY_FUNCTION__))
;
588
589 LiveInterval &IntA =
590 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
591 LiveInterval &IntB =
592 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
593 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
594
595 // We have a non-trivially-coalescable copy with IntA being the source and
596 // IntB being the dest, thus this defines a value number in IntB. If the
597 // source value number (in IntA) is defined by a copy from B, see if we can
598 // merge these two pieces of B into a single value number, eliminating a copy.
599 // For example:
600 //
601 // A3 = B0
602 // ...
603 // B1 = A3 <- this copy
604 //
605 // In this case, B0 can be extended to where the B1 copy lives, allowing the
606 // B1 value number to be replaced with B0 (which simplifies the B
607 // liveinterval).
608
609 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
610 // the example above.
611 LiveInterval::iterator BS = IntB.FindSegmentContaining(CopyIdx);
612 if (BS == IntB.end()) return false;
613 VNInfo *BValNo = BS->valno;
614
615 // Get the location that B is defined at. Two options: either this value has
616 // an unknown definition point or it is defined at CopyIdx. If unknown, we
617 // can't process it.
618 if (BValNo->def != CopyIdx) return false;
619
620 // AValNo is the value number in A that defines the copy, A3 in the example.
621 SlotIndex CopyUseIdx = CopyIdx.getRegSlot(true);
622 LiveInterval::iterator AS = IntA.FindSegmentContaining(CopyUseIdx);
623 // The live segment might not exist after fun with physreg coalescing.
624 if (AS == IntA.end()) return false;
625 VNInfo *AValNo = AS->valno;
626
627 // If AValNo is defined as a copy from IntB, we can potentially process this.
628 // Get the instruction that defines this value number.
629 MachineInstr *ACopyMI = LIS->getInstructionFromIndex(AValNo->def);
630 // Don't allow any partial copies, even if isCoalescable() allows them.
631 if (!CP.isCoalescable(ACopyMI) || !ACopyMI->isFullCopy())
632 return false;
633
634 // Get the Segment in IntB that this value number starts with.
635 LiveInterval::iterator ValS =
636 IntB.FindSegmentContaining(AValNo->def.getPrevSlot());
637 if (ValS == IntB.end())
638 return false;
639
640 // Make sure that the end of the live segment is inside the same block as
641 // CopyMI.
642 MachineInstr *ValSEndInst =
643 LIS->getInstructionFromIndex(ValS->end.getPrevSlot());
644 if (!ValSEndInst || ValSEndInst->getParent() != CopyMI->getParent())
645 return false;
646
647 // Okay, we now know that ValS ends in the same block that the CopyMI
648 // live-range starts. If there are no intervening live segments between them
649 // in IntB, we can merge them.
650 if (ValS+1 != BS) return false;
651
652 LLVM_DEBUG(dbgs() << "Extending: " << printReg(IntB.reg(), TRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Extending: " << printReg
(IntB.reg(), TRI); } } while (false)
;
653
654 SlotIndex FillerStart = ValS->end, FillerEnd = BS->start;
655 // We are about to delete CopyMI, so need to remove it as the 'instruction
656 // that defines this value #'. Update the valnum with the new defining
657 // instruction #.
658 BValNo->def = FillerStart;
659
660 // Okay, we can merge them. We need to insert a new liverange:
661 // [ValS.end, BS.begin) of either value number, then we merge the
662 // two value numbers.
663 IntB.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, BValNo));
664
665 // Okay, merge "B1" into the same value number as "B0".
666 if (BValNo != ValS->valno)
667 IntB.MergeValueNumberInto(BValNo, ValS->valno);
668
669 // Do the same for the subregister segments.
670 for (LiveInterval::SubRange &S : IntB.subranges()) {
671 // Check for SubRange Segments of the form [1234r,1234d:0) which can be
672 // removed to prevent creating bogus SubRange Segments.
673 LiveInterval::iterator SS = S.FindSegmentContaining(CopyIdx);
674 if (SS != S.end() && SlotIndex::isSameInstr(SS->start, SS->end)) {
675 S.removeSegment(*SS, true);
676 continue;
677 }
678 // The subrange may have ended before FillerStart. If so, extend it.
679 if (!S.getVNInfoAt(FillerStart)) {
680 SlotIndex BBStart =
681 LIS->getMBBStartIdx(LIS->getMBBFromIndex(FillerStart));
682 S.extendInBlock(BBStart, FillerStart);
683 }
684 VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
685 S.addSegment(LiveInterval::Segment(FillerStart, FillerEnd, SubBValNo));
686 VNInfo *SubValSNo = S.getVNInfoAt(AValNo->def.getPrevSlot());
687 if (SubBValNo != SubValSNo)
688 S.MergeValueNumberInto(SubBValNo, SubValSNo);
689 }
690
691 LLVM_DEBUG(dbgs() << " result = " << IntB << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << " result = " << IntB <<
'\n'; } } while (false)
;
692
693 // If the source instruction was killing the source register before the
694 // merge, unset the isKill marker given the live range has been extended.
695 int UIdx = ValSEndInst->findRegisterUseOperandIdx(IntB.reg(), true);
696 if (UIdx != -1) {
697 ValSEndInst->getOperand(UIdx).setIsKill(false);
698 }
699
700 // Rewrite the copy.
701 CopyMI->substituteRegister(IntA.reg(), IntB.reg(), 0, *TRI);
702 // If the copy instruction was killing the destination register or any
703 // subrange before the merge trim the live range.
704 bool RecomputeLiveRange = AS->end == CopyIdx;
705 if (!RecomputeLiveRange) {
706 for (LiveInterval::SubRange &S : IntA.subranges()) {
707 LiveInterval::iterator SS = S.FindSegmentContaining(CopyUseIdx);
708 if (SS != S.end() && SS->end == CopyIdx) {
709 RecomputeLiveRange = true;
710 break;
711 }
712 }
713 }
714 if (RecomputeLiveRange)
715 shrinkToUses(&IntA);
716
717 ++numExtends;
718 return true;
719}
720
721bool RegisterCoalescer::hasOtherReachingDefs(LiveInterval &IntA,
722 LiveInterval &IntB,
723 VNInfo *AValNo,
724 VNInfo *BValNo) {
725 // If AValNo has PHI kills, conservatively assume that IntB defs can reach
726 // the PHI values.
727 if (LIS->hasPHIKill(IntA, AValNo))
728 return true;
729
730 for (LiveRange::Segment &ASeg : IntA.segments) {
731 if (ASeg.valno != AValNo) continue;
732 LiveInterval::iterator BI = llvm::upper_bound(IntB, ASeg.start);
733 if (BI != IntB.begin())
734 --BI;
735 for (; BI != IntB.end() && ASeg.end >= BI->start; ++BI) {
736 if (BI->valno == BValNo)
737 continue;
738 if (BI->start <= ASeg.start && BI->end > ASeg.start)
739 return true;
740 if (BI->start > ASeg.start && BI->start < ASeg.end)
741 return true;
742 }
743 }
744 return false;
745}
746
747/// Copy segments with value number @p SrcValNo from liverange @p Src to live
748/// range @Dst and use value number @p DstValNo there.
749static std::pair<bool,bool>
750addSegmentsWithValNo(LiveRange &Dst, VNInfo *DstValNo, const LiveRange &Src,
751 const VNInfo *SrcValNo) {
752 bool Changed = false;
753 bool MergedWithDead = false;
754 for (const LiveRange::Segment &S : Src.segments) {
755 if (S.valno != SrcValNo)
756 continue;
757 // This is adding a segment from Src that ends in a copy that is about
758 // to be removed. This segment is going to be merged with a pre-existing
759 // segment in Dst. This works, except in cases when the corresponding
760 // segment in Dst is dead. For example: adding [192r,208r:1) from Src
761 // to [208r,208d:1) in Dst would create [192r,208d:1) in Dst.
762 // Recognized such cases, so that the segments can be shrunk.
763 LiveRange::Segment Added = LiveRange::Segment(S.start, S.end, DstValNo);
764 LiveRange::Segment &Merged = *Dst.addSegment(Added);
765 if (Merged.end.isDead())
766 MergedWithDead = true;
767 Changed = true;
768 }
769 return std::make_pair(Changed, MergedWithDead);
770}
771
772std::pair<bool,bool>
773RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP,
774 MachineInstr *CopyMI) {
775 assert(!CP.isPhys())((!CP.isPhys()) ? static_cast<void> (0) : __assert_fail
("!CP.isPhys()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 775, __PRETTY_FUNCTION__))
;
776
777 LiveInterval &IntA =
778 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
779 LiveInterval &IntB =
780 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
781
782 // We found a non-trivially-coalescable copy with IntA being the source and
783 // IntB being the dest, thus this defines a value number in IntB. If the
784 // source value number (in IntA) is defined by a commutable instruction and
785 // its other operand is coalesced to the copy dest register, see if we can
786 // transform the copy into a noop by commuting the definition. For example,
787 //
788 // A3 = op A2 killed B0
789 // ...
790 // B1 = A3 <- this copy
791 // ...
792 // = op A3 <- more uses
793 //
794 // ==>
795 //
796 // B2 = op B0 killed A2
797 // ...
798 // B1 = B2 <- now an identity copy
799 // ...
800 // = op B2 <- more uses
801
802 // BValNo is a value number in B that is defined by a copy from A. 'B1' in
803 // the example above.
804 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
805 VNInfo *BValNo = IntB.getVNInfoAt(CopyIdx);
806 assert(BValNo != nullptr && BValNo->def == CopyIdx)((BValNo != nullptr && BValNo->def == CopyIdx) ? static_cast
<void> (0) : __assert_fail ("BValNo != nullptr && BValNo->def == CopyIdx"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 806, __PRETTY_FUNCTION__))
;
807
808 // AValNo is the value number in A that defines the copy, A3 in the example.
809 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx.getRegSlot(true));
810 assert(AValNo && !AValNo->isUnused() && "COPY source not live")((AValNo && !AValNo->isUnused() && "COPY source not live"
) ? static_cast<void> (0) : __assert_fail ("AValNo && !AValNo->isUnused() && \"COPY source not live\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 810, __PRETTY_FUNCTION__))
;
811 if (AValNo->isPHIDef())
812 return { false, false };
813 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def);
814 if (!DefMI)
815 return { false, false };
816 if (!DefMI->isCommutable())
817 return { false, false };
818 // If DefMI is a two-address instruction then commuting it will change the
819 // destination register.
820 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg());
821 assert(DefIdx != -1)((DefIdx != -1) ? static_cast<void> (0) : __assert_fail
("DefIdx != -1", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 821, __PRETTY_FUNCTION__))
;
822 unsigned UseOpIdx;
823 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
824 return { false, false };
825
826 // FIXME: The code below tries to commute 'UseOpIdx' operand with some other
827 // commutable operand which is expressed by 'CommuteAnyOperandIndex'value
828 // passed to the method. That _other_ operand is chosen by
829 // the findCommutedOpIndices() method.
830 //
831 // That is obviously an area for improvement in case of instructions having
832 // more than 2 operands. For example, if some instruction has 3 commutable
833 // operands then all possible variants (i.e. op#1<->op#2, op#1<->op#3,
834 // op#2<->op#3) of commute transformation should be considered/tried here.
835 unsigned NewDstIdx = TargetInstrInfo::CommuteAnyOperandIndex;
836 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx))
837 return { false, false };
838
839 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
840 Register NewReg = NewDstMO.getReg();
841 if (NewReg != IntB.reg() || !IntB.Query(AValNo->def).isKill())
842 return { false, false };
843
844 // Make sure there are no other definitions of IntB that would reach the
845 // uses which the new definition can reach.
846 if (hasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
847 return { false, false };
848
849 // If some of the uses of IntA.reg is already coalesced away, return false.
850 // It's not possible to determine whether it's safe to perform the coalescing.
851 for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg())) {
852 MachineInstr *UseMI = MO.getParent();
853 unsigned OpNo = &MO - &UseMI->getOperand(0);
854 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
855 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
856 if (US == IntA.end() || US->valno != AValNo)
857 continue;
858 // If this use is tied to a def, we can't rewrite the register.
859 if (UseMI->isRegTiedToDefOperand(OpNo))
860 return { false, false };
861 }
862
863 LLVM_DEBUG(dbgs() << "\tremoveCopyByCommutingDef: " << AValNo->def << '\t'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tremoveCopyByCommutingDef: "
<< AValNo->def << '\t' << *DefMI; } } while
(false)
864 << *DefMI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tremoveCopyByCommutingDef: "
<< AValNo->def << '\t' << *DefMI; } } while
(false)
;
865
866 // At this point we have decided that it is legal to do this
867 // transformation. Start by commuting the instruction.
868 MachineBasicBlock *MBB = DefMI->getParent();
869 MachineInstr *NewMI =
870 TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx);
871 if (!NewMI)
872 return { false, false };
873 if (Register::isVirtualRegister(IntA.reg()) &&
874 Register::isVirtualRegister(IntB.reg()) &&
875 !MRI->constrainRegClass(IntB.reg(), MRI->getRegClass(IntA.reg())))
876 return { false, false };
877 if (NewMI != DefMI) {
878 LIS->ReplaceMachineInstrInMaps(*DefMI, *NewMI);
879 MachineBasicBlock::iterator Pos = DefMI;
880 MBB->insert(Pos, NewMI);
881 MBB->erase(DefMI);
882 }
883
884 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
885 // A = or A, B
886 // ...
887 // B = A
888 // ...
889 // C = killed A
890 // ...
891 // = B
892
893 // Update uses of IntA of the specific Val# with IntB.
894 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg()),
895 UE = MRI->use_end();
896 UI != UE;
897 /* ++UI is below because of possible MI removal */) {
898 MachineOperand &UseMO = *UI;
899 ++UI;
900 if (UseMO.isUndef())
901 continue;
902 MachineInstr *UseMI = UseMO.getParent();
903 if (UseMI->isDebugValue()) {
904 // FIXME These don't have an instruction index. Not clear we have enough
905 // info to decide whether to do this replacement or not. For now do it.
906 UseMO.setReg(NewReg);
907 continue;
908 }
909 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
910 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
911 assert(US != IntA.end() && "Use must be live")((US != IntA.end() && "Use must be live") ? static_cast
<void> (0) : __assert_fail ("US != IntA.end() && \"Use must be live\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 911, __PRETTY_FUNCTION__))
;
912 if (US->valno != AValNo)
913 continue;
914 // Kill flags are no longer accurate. They are recomputed after RA.
915 UseMO.setIsKill(false);
916 if (Register::isPhysicalRegister(NewReg))
917 UseMO.substPhysReg(NewReg, *TRI);
918 else
919 UseMO.setReg(NewReg);
920 if (UseMI == CopyMI)
921 continue;
922 if (!UseMI->isCopy())
923 continue;
924 if (UseMI->getOperand(0).getReg() != IntB.reg() ||
925 UseMI->getOperand(0).getSubReg())
926 continue;
927
928 // This copy will become a noop. If it's defining a new val#, merge it into
929 // BValNo.
930 SlotIndex DefIdx = UseIdx.getRegSlot();
931 VNInfo *DVNI = IntB.getVNInfoAt(DefIdx);
932 if (!DVNI)
933 continue;
934 LLVM_DEBUG(dbgs() << "\t\tnoop: " << DefIdx << '\t' << *UseMI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tnoop: " << DefIdx <<
'\t' << *UseMI; } } while (false)
;
935 assert(DVNI->def == DefIdx)((DVNI->def == DefIdx) ? static_cast<void> (0) : __assert_fail
("DVNI->def == DefIdx", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 935, __PRETTY_FUNCTION__))
;
936 BValNo = IntB.MergeValueNumberInto(DVNI, BValNo);
937 for (LiveInterval::SubRange &S : IntB.subranges()) {
938 VNInfo *SubDVNI = S.getVNInfoAt(DefIdx);
939 if (!SubDVNI)
940 continue;
941 VNInfo *SubBValNo = S.getVNInfoAt(CopyIdx);
942 assert(SubBValNo->def == CopyIdx)((SubBValNo->def == CopyIdx) ? static_cast<void> (0)
: __assert_fail ("SubBValNo->def == CopyIdx", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 942, __PRETTY_FUNCTION__))
;
943 S.MergeValueNumberInto(SubDVNI, SubBValNo);
944 }
945
946 deleteInstr(UseMI);
947 }
948
949 // Extend BValNo by merging in IntA live segments of AValNo. Val# definition
950 // is updated.
951 bool ShrinkB = false;
952 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
953 if (IntA.hasSubRanges() || IntB.hasSubRanges()) {
954 if (!IntA.hasSubRanges()) {
955 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntA.reg());
956 IntA.createSubRangeFrom(Allocator, Mask, IntA);
957 } else if (!IntB.hasSubRanges()) {
958 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntB.reg());
959 IntB.createSubRangeFrom(Allocator, Mask, IntB);
960 }
961 SlotIndex AIdx = CopyIdx.getRegSlot(true);
962 LaneBitmask MaskA;
963 const SlotIndexes &Indexes = *LIS->getSlotIndexes();
964 for (LiveInterval::SubRange &SA : IntA.subranges()) {
965 VNInfo *ASubValNo = SA.getVNInfoAt(AIdx);
966 // Even if we are dealing with a full copy, some lanes can
967 // still be undefined.
968 // E.g.,
969 // undef A.subLow = ...
970 // B = COPY A <== A.subHigh is undefined here and does
971 // not have a value number.
972 if (!ASubValNo)
973 continue;
974 MaskA |= SA.LaneMask;
975
976 IntB.refineSubRanges(
977 Allocator, SA.LaneMask,
978 [&Allocator, &SA, CopyIdx, ASubValNo,
979 &ShrinkB](LiveInterval::SubRange &SR) {
980 VNInfo *BSubValNo = SR.empty() ? SR.getNextValue(CopyIdx, Allocator)
981 : SR.getVNInfoAt(CopyIdx);
982 assert(BSubValNo != nullptr)((BSubValNo != nullptr) ? static_cast<void> (0) : __assert_fail
("BSubValNo != nullptr", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 982, __PRETTY_FUNCTION__))
;
983 auto P = addSegmentsWithValNo(SR, BSubValNo, SA, ASubValNo);
984 ShrinkB |= P.second;
985 if (P.first)
986 BSubValNo->def = ASubValNo->def;
987 },
988 Indexes, *TRI);
989 }
990 // Go over all subranges of IntB that have not been covered by IntA,
991 // and delete the segments starting at CopyIdx. This can happen if
992 // IntA has undef lanes that are defined in IntB.
993 for (LiveInterval::SubRange &SB : IntB.subranges()) {
994 if ((SB.LaneMask & MaskA).any())
995 continue;
996 if (LiveRange::Segment *S = SB.getSegmentContaining(CopyIdx))
997 if (S->start.getBaseIndex() == CopyIdx.getBaseIndex())
998 SB.removeSegment(*S, true);
999 }
1000 }
1001
1002 BValNo->def = AValNo->def;
1003 auto P = addSegmentsWithValNo(IntB, BValNo, IntA, AValNo);
1004 ShrinkB |= P.second;
1005 LLVM_DEBUG(dbgs() << "\t\textended: " << IntB << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\textended: " << IntB
<< '\n'; } } while (false)
;
1006
1007 LIS->removeVRegDefAt(IntA, AValNo->def);
1008
1009 LLVM_DEBUG(dbgs() << "\t\ttrimmed: " << IntA << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\ttrimmed: " << IntA
<< '\n'; } } while (false)
;
1010 ++numCommutes;
1011 return { true, ShrinkB };
1012}
1013
1014/// For copy B = A in BB2, if A is defined by A = B in BB0 which is a
1015/// predecessor of BB2, and if B is not redefined on the way from A = B
1016/// in BB0 to B = A in BB2, B = A in BB2 is partially redundant if the
1017/// execution goes through the path from BB0 to BB2. We may move B = A
1018/// to the predecessor without such reversed copy.
1019/// So we will transform the program from:
1020/// BB0:
1021/// A = B; BB1:
1022/// ... ...
1023/// / \ /
1024/// BB2:
1025/// ...
1026/// B = A;
1027///
1028/// to:
1029///
1030/// BB0: BB1:
1031/// A = B; ...
1032/// ... B = A;
1033/// / \ /
1034/// BB2:
1035/// ...
1036///
1037/// A special case is when BB0 and BB2 are the same BB which is the only
1038/// BB in a loop:
1039/// BB1:
1040/// ...
1041/// BB0/BB2: ----
1042/// B = A; |
1043/// ... |
1044/// A = B; |
1045/// |-------
1046/// |
1047/// We may hoist B = A from BB0/BB2 to BB1.
1048///
1049/// The major preconditions for correctness to remove such partial
1050/// redundancy include:
1051/// 1. A in B = A in BB2 is defined by a PHI in BB2, and one operand of
1052/// the PHI is defined by the reversed copy A = B in BB0.
1053/// 2. No B is referenced from the start of BB2 to B = A.
1054/// 3. No B is defined from A = B to the end of BB0.
1055/// 4. BB1 has only one successor.
1056///
1057/// 2 and 4 implicitly ensure B is not live at the end of BB1.
1058/// 4 guarantees BB2 is hotter than BB1, so we can only move a copy to a
1059/// colder place, which not only prevent endless loop, but also make sure
1060/// the movement of copy is beneficial.
1061bool RegisterCoalescer::removePartialRedundancy(const CoalescerPair &CP,
1062 MachineInstr &CopyMI) {
1063 assert(!CP.isPhys())((!CP.isPhys()) ? static_cast<void> (0) : __assert_fail
("!CP.isPhys()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1063, __PRETTY_FUNCTION__))
;
1064 if (!CopyMI.isFullCopy())
1065 return false;
1066
1067 MachineBasicBlock &MBB = *CopyMI.getParent();
1068 // If this block is the target of an invoke/inlineasm_br, moving the copy into
1069 // the predecessor is tricker, and we don't handle it.
1070 if (MBB.isEHPad() || MBB.isInlineAsmBrIndirectTarget())
1071 return false;
1072
1073 if (MBB.pred_size() != 2)
1074 return false;
1075
1076 LiveInterval &IntA =
1077 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg());
1078 LiveInterval &IntB =
1079 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg());
1080
1081 // A is defined by PHI at the entry of MBB.
1082 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getRegSlot(true);
1083 VNInfo *AValNo = IntA.getVNInfoAt(CopyIdx);
1084 assert(AValNo && !AValNo->isUnused() && "COPY source not live")((AValNo && !AValNo->isUnused() && "COPY source not live"
) ? static_cast<void> (0) : __assert_fail ("AValNo && !AValNo->isUnused() && \"COPY source not live\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1084, __PRETTY_FUNCTION__))
;
1085 if (!AValNo->isPHIDef())
1086 return false;
1087
1088 // No B is referenced before CopyMI in MBB.
1089 if (IntB.overlaps(LIS->getMBBStartIdx(&MBB), CopyIdx))
1090 return false;
1091
1092 // MBB has two predecessors: one contains A = B so no copy will be inserted
1093 // for it. The other one will have a copy moved from MBB.
1094 bool FoundReverseCopy = false;
1095 MachineBasicBlock *CopyLeftBB = nullptr;
1096 for (MachineBasicBlock *Pred : MBB.predecessors()) {
1097 VNInfo *PVal = IntA.getVNInfoBefore(LIS->getMBBEndIdx(Pred));
1098 MachineInstr *DefMI = LIS->getInstructionFromIndex(PVal->def);
1099 if (!DefMI || !DefMI->isFullCopy()) {
1100 CopyLeftBB = Pred;
1101 continue;
1102 }
1103 // Check DefMI is a reverse copy and it is in BB Pred.
1104 if (DefMI->getOperand(0).getReg() != IntA.reg() ||
1105 DefMI->getOperand(1).getReg() != IntB.reg() ||
1106 DefMI->getParent() != Pred) {
1107 CopyLeftBB = Pred;
1108 continue;
1109 }
1110 // If there is any other def of B after DefMI and before the end of Pred,
1111 // we need to keep the copy of B = A at the end of Pred if we remove
1112 // B = A from MBB.
1113 bool ValB_Changed = false;
1114 for (auto VNI : IntB.valnos) {
1115 if (VNI->isUnused())
1116 continue;
1117 if (PVal->def < VNI->def && VNI->def < LIS->getMBBEndIdx(Pred)) {
1118 ValB_Changed = true;
1119 break;
1120 }
1121 }
1122 if (ValB_Changed) {
1123 CopyLeftBB = Pred;
1124 continue;
1125 }
1126 FoundReverseCopy = true;
1127 }
1128
1129 // If no reverse copy is found in predecessors, nothing to do.
1130 if (!FoundReverseCopy)
1131 return false;
1132
1133 // If CopyLeftBB is nullptr, it means every predecessor of MBB contains
1134 // reverse copy, CopyMI can be removed trivially if only IntA/IntB is updated.
1135 // If CopyLeftBB is not nullptr, move CopyMI from MBB to CopyLeftBB and
1136 // update IntA/IntB.
1137 //
1138 // If CopyLeftBB is not nullptr, ensure CopyLeftBB has a single succ so
1139 // MBB is hotter than CopyLeftBB.
1140 if (CopyLeftBB && CopyLeftBB->succ_size() > 1)
1141 return false;
1142
1143 // Now (almost sure it's) ok to move copy.
1144 if (CopyLeftBB) {
1145 // Position in CopyLeftBB where we should insert new copy.
1146 auto InsPos = CopyLeftBB->getFirstTerminator();
1147
1148 // Make sure that B isn't referenced in the terminators (if any) at the end
1149 // of the predecessor since we're about to insert a new definition of B
1150 // before them.
1151 if (InsPos != CopyLeftBB->end()) {
1152 SlotIndex InsPosIdx = LIS->getInstructionIndex(*InsPos).getRegSlot(true);
1153 if (IntB.overlaps(InsPosIdx, LIS->getMBBEndIdx(CopyLeftBB)))
1154 return false;
1155 }
1156
1157 LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Move the copy to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tremovePartialRedundancy: Move the copy to "
<< printMBBReference(*CopyLeftBB) << '\t' <<
CopyMI; } } while (false)
1158 << printMBBReference(*CopyLeftBB) << '\t' << CopyMI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tremovePartialRedundancy: Move the copy to "
<< printMBBReference(*CopyLeftBB) << '\t' <<
CopyMI; } } while (false)
;
1159
1160 // Insert new copy to CopyLeftBB.
1161 MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
1162 TII->get(TargetOpcode::COPY), IntB.reg())
1163 .addReg(IntA.reg());
1164 SlotIndex NewCopyIdx =
1165 LIS->InsertMachineInstrInMaps(*NewCopyMI).getRegSlot();
1166 IntB.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
1167 for (LiveInterval::SubRange &SR : IntB.subranges())
1168 SR.createDeadDef(NewCopyIdx, LIS->getVNInfoAllocator());
1169
1170 // If the newly created Instruction has an address of an instruction that was
1171 // deleted before (object recycled by the allocator) it needs to be removed from
1172 // the deleted list.
1173 ErasedInstrs.erase(NewCopyMI);
1174 } else {
1175 LLVM_DEBUG(dbgs() << "\tremovePartialRedundancy: Remove the copy from "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tremovePartialRedundancy: Remove the copy from "
<< printMBBReference(MBB) << '\t' << CopyMI
; } } while (false)
1176 << printMBBReference(MBB) << '\t' << CopyMI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tremovePartialRedundancy: Remove the copy from "
<< printMBBReference(MBB) << '\t' << CopyMI
; } } while (false)
;
1177 }
1178
1179 // Remove CopyMI.
1180 // Note: This is fine to remove the copy before updating the live-ranges.
1181 // While updating the live-ranges, we only look at slot indices and
1182 // never go back to the instruction.
1183 // Mark instructions as deleted.
1184 deleteInstr(&CopyMI);
1185
1186 // Update the liveness.
1187 SmallVector<SlotIndex, 8> EndPoints;
1188 VNInfo *BValNo = IntB.Query(CopyIdx).valueOutOrDead();
1189 LIS->pruneValue(*static_cast<LiveRange *>(&IntB), CopyIdx.getRegSlot(),
1190 &EndPoints);
1191 BValNo->markUnused();
1192 // Extend IntB to the EndPoints of its original live interval.
1193 LIS->extendToIndices(IntB, EndPoints);
1194
1195 // Now, do the same for its subranges.
1196 for (LiveInterval::SubRange &SR : IntB.subranges()) {
1197 EndPoints.clear();
1198 VNInfo *BValNo = SR.Query(CopyIdx).valueOutOrDead();
1199 assert(BValNo && "All sublanes should be live")((BValNo && "All sublanes should be live") ? static_cast
<void> (0) : __assert_fail ("BValNo && \"All sublanes should be live\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1199, __PRETTY_FUNCTION__))
;
1200 LIS->pruneValue(SR, CopyIdx.getRegSlot(), &EndPoints);
1201 BValNo->markUnused();
1202 // We can have a situation where the result of the original copy is live,
1203 // but is immediately dead in this subrange, e.g. [336r,336d:0). That makes
1204 // the copy appear as an endpoint from pruneValue(), but we don't want it
1205 // to because the copy has been removed. We can go ahead and remove that
1206 // endpoint; there is no other situation here that there could be a use at
1207 // the same place as we know that the copy is a full copy.
1208 for (unsigned I = 0; I != EndPoints.size(); ) {
1209 if (SlotIndex::isSameInstr(EndPoints[I], CopyIdx)) {
1210 EndPoints[I] = EndPoints.back();
1211 EndPoints.pop_back();
1212 continue;
1213 }
1214 ++I;
1215 }
1216 LIS->extendToIndices(SR, EndPoints);
1217 }
1218 // If any dead defs were extended, truncate them.
1219 shrinkToUses(&IntB);
1220
1221 // Finally, update the live-range of IntA.
1222 shrinkToUses(&IntA);
1223 return true;
1224}
1225
1226/// Returns true if @p MI defines the full vreg @p Reg, as opposed to just
1227/// defining a subregister.
1228static bool definesFullReg(const MachineInstr &MI, unsigned Reg) {
1229 assert(!Register::isPhysicalRegister(Reg) &&((!Register::isPhysicalRegister(Reg) && "This code cannot handle physreg aliasing"
) ? static_cast<void> (0) : __assert_fail ("!Register::isPhysicalRegister(Reg) && \"This code cannot handle physreg aliasing\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1230, __PRETTY_FUNCTION__))
1230 "This code cannot handle physreg aliasing")((!Register::isPhysicalRegister(Reg) && "This code cannot handle physreg aliasing"
) ? static_cast<void> (0) : __assert_fail ("!Register::isPhysicalRegister(Reg) && \"This code cannot handle physreg aliasing\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1230, __PRETTY_FUNCTION__))
;
1231 for (const MachineOperand &Op : MI.operands()) {
1232 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
1233 continue;
1234 // Return true if we define the full register or don't care about the value
1235 // inside other subregisters.
1236 if (Op.getSubReg() == 0 || Op.isUndef())
1237 return true;
1238 }
1239 return false;
1240}
1241
1242bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
1243 MachineInstr *CopyMI,
1244 bool &IsDefCopy) {
1245 IsDefCopy = false;
1246 unsigned SrcReg = CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg();
1247 unsigned SrcIdx = CP.isFlipped() ? CP.getDstIdx() : CP.getSrcIdx();
1248 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
1249 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx();
1250 if (Register::isPhysicalRegister(SrcReg))
1251 return false;
1252
1253 LiveInterval &SrcInt = LIS->getInterval(SrcReg);
1254 SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
1255 VNInfo *ValNo = SrcInt.Query(CopyIdx).valueIn();
1256 if (!ValNo)
1257 return false;
1258 if (ValNo->isPHIDef() || ValNo->isUnused())
1259 return false;
1260 MachineInstr *DefMI = LIS->getInstructionFromIndex(ValNo->def);
1261 if (!DefMI)
1262 return false;
1263 if (DefMI->isCopyLike()) {
1264 IsDefCopy = true;
1265 return false;
1266 }
1267 if (!TII->isAsCheapAsAMove(*DefMI))
1268 return false;
1269 if (!TII->isTriviallyReMaterializable(*DefMI, AA))
1270 return false;
1271 if (!definesFullReg(*DefMI, SrcReg))
1272 return false;
1273 bool SawStore = false;
1274 if (!DefMI->isSafeToMove(AA, SawStore))
1275 return false;
1276 const MCInstrDesc &MCID = DefMI->getDesc();
1277 if (MCID.getNumDefs() != 1)
1278 return false;
1279 // Only support subregister destinations when the def is read-undef.
1280 MachineOperand &DstOperand = CopyMI->getOperand(0);
1281 Register CopyDstReg = DstOperand.getReg();
1282 if (DstOperand.getSubReg() && !DstOperand.isUndef())
1283 return false;
1284
1285 // If both SrcIdx and DstIdx are set, correct rematerialization would widen
1286 // the register substantially (beyond both source and dest size). This is bad
1287 // for performance since it can cascade through a function, introducing many
1288 // extra spills and fills (e.g. ARM can easily end up copying QQQQPR registers
1289 // around after a few subreg copies).
1290 if (SrcIdx && DstIdx)
1291 return false;
1292
1293 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
1294 if (!DefMI->isImplicitDef()) {
1295 if (Register::isPhysicalRegister(DstReg)) {
1296 unsigned NewDstReg = DstReg;
1297
1298 unsigned NewDstIdx = TRI->composeSubRegIndices(CP.getSrcIdx(),
1299 DefMI->getOperand(0).getSubReg());
1300 if (NewDstIdx)
1301 NewDstReg = TRI->getSubReg(DstReg, NewDstIdx);
1302
1303 // Finally, make sure that the physical subregister that will be
1304 // constructed later is permitted for the instruction.
1305 if (!DefRC->contains(NewDstReg))
1306 return false;
1307 } else {
1308 // Theoretically, some stack frame reference could exist. Just make sure
1309 // it hasn't actually happened.
1310 assert(Register::isVirtualRegister(DstReg) &&((Register::isVirtualRegister(DstReg) && "Only expect to deal with virtual or physical registers"
) ? static_cast<void> (0) : __assert_fail ("Register::isVirtualRegister(DstReg) && \"Only expect to deal with virtual or physical registers\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1311, __PRETTY_FUNCTION__))
1311 "Only expect to deal with virtual or physical registers")((Register::isVirtualRegister(DstReg) && "Only expect to deal with virtual or physical registers"
) ? static_cast<void> (0) : __assert_fail ("Register::isVirtualRegister(DstReg) && \"Only expect to deal with virtual or physical registers\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1311, __PRETTY_FUNCTION__))
;
1312 }
1313 }
1314
1315 DebugLoc DL = CopyMI->getDebugLoc();
1316 MachineBasicBlock *MBB = CopyMI->getParent();
1317 MachineBasicBlock::iterator MII =
1318 std::next(MachineBasicBlock::iterator(CopyMI));
1319 TII->reMaterialize(*MBB, MII, DstReg, SrcIdx, *DefMI, *TRI);
1320 MachineInstr &NewMI = *std::prev(MII);
1321 NewMI.setDebugLoc(DL);
1322
1323 // In a situation like the following:
1324 // %0:subreg = instr ; DefMI, subreg = DstIdx
1325 // %1 = copy %0:subreg ; CopyMI, SrcIdx = 0
1326 // instead of widening %1 to the register class of %0 simply do:
1327 // %1 = instr
1328 const TargetRegisterClass *NewRC = CP.getNewRC();
1329 if (DstIdx != 0) {
1330 MachineOperand &DefMO = NewMI.getOperand(0);
1331 if (DefMO.getSubReg() == DstIdx) {
1332 assert(SrcIdx == 0 && CP.isFlipped()((SrcIdx == 0 && CP.isFlipped() && "Shouldn't have SrcIdx+DstIdx at this point"
) ? static_cast<void> (0) : __assert_fail ("SrcIdx == 0 && CP.isFlipped() && \"Shouldn't have SrcIdx+DstIdx at this point\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1333, __PRETTY_FUNCTION__))
1333 && "Shouldn't have SrcIdx+DstIdx at this point")((SrcIdx == 0 && CP.isFlipped() && "Shouldn't have SrcIdx+DstIdx at this point"
) ? static_cast<void> (0) : __assert_fail ("SrcIdx == 0 && CP.isFlipped() && \"Shouldn't have SrcIdx+DstIdx at this point\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1333, __PRETTY_FUNCTION__))
;
1334 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
1335 const TargetRegisterClass *CommonRC =
1336 TRI->getCommonSubClass(DefRC, DstRC);
1337 if (CommonRC != nullptr) {
1338 NewRC = CommonRC;
1339 DstIdx = 0;
1340 DefMO.setSubReg(0);
1341 DefMO.setIsUndef(false); // Only subregs can have def+undef.
1342 }
1343 }
1344 }
1345
1346 // CopyMI may have implicit operands, save them so that we can transfer them
1347 // over to the newly materialized instruction after CopyMI is removed.
1348 SmallVector<MachineOperand, 4> ImplicitOps;
1349 ImplicitOps.reserve(CopyMI->getNumOperands() -
1350 CopyMI->getDesc().getNumOperands());
1351 for (unsigned I = CopyMI->getDesc().getNumOperands(),
1352 E = CopyMI->getNumOperands();
1353 I != E; ++I) {
1354 MachineOperand &MO = CopyMI->getOperand(I);
1355 if (MO.isReg()) {
1356 assert(MO.isImplicit() && "No explicit operands after implicit operands.")((MO.isImplicit() && "No explicit operands after implicit operands."
) ? static_cast<void> (0) : __assert_fail ("MO.isImplicit() && \"No explicit operands after implicit operands.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1356, __PRETTY_FUNCTION__))
;
1357 // Discard VReg implicit defs.
1358 if (Register::isPhysicalRegister(MO.getReg()))
1359 ImplicitOps.push_back(MO);
1360 }
1361 }
1362
1363 LIS->ReplaceMachineInstrInMaps(*CopyMI, NewMI);
1364 CopyMI->eraseFromParent();
1365 ErasedInstrs.insert(CopyMI);
1366
1367 // NewMI may have dead implicit defs (E.g. EFLAGS for MOV<bits>r0 on X86).
1368 // We need to remember these so we can add intervals once we insert
1369 // NewMI into SlotIndexes.
1370 SmallVector<unsigned, 4> NewMIImplDefs;
1371 for (unsigned i = NewMI.getDesc().getNumOperands(),
1372 e = NewMI.getNumOperands();
1373 i != e; ++i) {
1374 MachineOperand &MO = NewMI.getOperand(i);
1375 if (MO.isReg() && MO.isDef()) {
1376 assert(MO.isImplicit() && MO.isDead() &&((MO.isImplicit() && MO.isDead() && Register::
isPhysicalRegister(MO.getReg())) ? static_cast<void> (0
) : __assert_fail ("MO.isImplicit() && MO.isDead() && Register::isPhysicalRegister(MO.getReg())"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1377, __PRETTY_FUNCTION__))
1377 Register::isPhysicalRegister(MO.getReg()))((MO.isImplicit() && MO.isDead() && Register::
isPhysicalRegister(MO.getReg())) ? static_cast<void> (0
) : __assert_fail ("MO.isImplicit() && MO.isDead() && Register::isPhysicalRegister(MO.getReg())"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1377, __PRETTY_FUNCTION__))
;
1378 NewMIImplDefs.push_back(MO.getReg());
1379 }
1380 }
1381
1382 if (Register::isVirtualRegister(DstReg)) {
1383 unsigned NewIdx = NewMI.getOperand(0).getSubReg();
1384
1385 if (DefRC != nullptr) {
1386 if (NewIdx)
1387 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx);
1388 else
1389 NewRC = TRI->getCommonSubClass(NewRC, DefRC);
1390 assert(NewRC && "subreg chosen for remat incompatible with instruction")((NewRC && "subreg chosen for remat incompatible with instruction"
) ? static_cast<void> (0) : __assert_fail ("NewRC && \"subreg chosen for remat incompatible with instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1390, __PRETTY_FUNCTION__))
;
1391 }
1392 // Remap subranges to new lanemask and change register class.
1393 LiveInterval &DstInt = LIS->getInterval(DstReg);
1394 for (LiveInterval::SubRange &SR : DstInt.subranges()) {
1395 SR.LaneMask = TRI->composeSubRegIndexLaneMask(DstIdx, SR.LaneMask);
1396 }
1397 MRI->setRegClass(DstReg, NewRC);
1398
1399 // Update machine operands and add flags.
1400 updateRegDefsUses(DstReg, DstReg, DstIdx);
1401 NewMI.getOperand(0).setSubReg(NewIdx);
1402 // updateRegDefUses can add an "undef" flag to the definition, since
1403 // it will replace DstReg with DstReg.DstIdx. If NewIdx is 0, make
1404 // sure that "undef" is not set.
1405 if (NewIdx == 0)
1406 NewMI.getOperand(0).setIsUndef(false);
1407 // Add dead subregister definitions if we are defining the whole register
1408 // but only part of it is live.
1409 // This could happen if the rematerialization instruction is rematerializing
1410 // more than actually is used in the register.
1411 // An example would be:
1412 // %1 = LOAD CONSTANTS 5, 8 ; Loading both 5 and 8 in different subregs
1413 // ; Copying only part of the register here, but the rest is undef.
1414 // %2:sub_16bit<def, read-undef> = COPY %1:sub_16bit
1415 // ==>
1416 // ; Materialize all the constants but only using one
1417 // %2 = LOAD_CONSTANTS 5, 8
1418 //
1419 // at this point for the part that wasn't defined before we could have
1420 // subranges missing the definition.
1421 if (NewIdx == 0 && DstInt.hasSubRanges()) {
1422 SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI);
1423 SlotIndex DefIndex =
1424 CurrIdx.getRegSlot(NewMI.getOperand(0).isEarlyClobber());
1425 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(DstReg);
1426 VNInfo::Allocator& Alloc = LIS->getVNInfoAllocator();
1427 for (LiveInterval::SubRange &SR : DstInt.subranges()) {
1428 if (!SR.liveAt(DefIndex))
1429 SR.createDeadDef(DefIndex, Alloc);
1430 MaxMask &= ~SR.LaneMask;
1431 }
1432 if (MaxMask.any()) {
1433 LiveInterval::SubRange *SR = DstInt.createSubRange(Alloc, MaxMask);
1434 SR->createDeadDef(DefIndex, Alloc);
1435 }
1436 }
1437
1438 // Make sure that the subrange for resultant undef is removed
1439 // For example:
1440 // %1:sub1<def,read-undef> = LOAD CONSTANT 1
1441 // %2 = COPY %1
1442 // ==>
1443 // %2:sub1<def, read-undef> = LOAD CONSTANT 1
1444 // ; Correct but need to remove the subrange for %2:sub0
1445 // ; as it is now undef
1446 if (NewIdx != 0 && DstInt.hasSubRanges()) {
1447 // The affected subregister segments can be removed.
1448 SlotIndex CurrIdx = LIS->getInstructionIndex(NewMI);
1449 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(NewIdx);
1450 bool UpdatedSubRanges = false;
1451 SlotIndex DefIndex =
1452 CurrIdx.getRegSlot(NewMI.getOperand(0).isEarlyClobber());
1453 VNInfo::Allocator &Alloc = LIS->getVNInfoAllocator();
1454 for (LiveInterval::SubRange &SR : DstInt.subranges()) {
1455 if ((SR.LaneMask & DstMask).none()) {
1456 LLVM_DEBUG(dbgs()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Removing undefined SubRange "
<< PrintLaneMask(SR.LaneMask) << " : " << SR
<< "\n"; } } while (false)
1457 << "Removing undefined SubRange "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Removing undefined SubRange "
<< PrintLaneMask(SR.LaneMask) << " : " << SR
<< "\n"; } } while (false)
1458 << PrintLaneMask(SR.LaneMask) << " : " << SR << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Removing undefined SubRange "
<< PrintLaneMask(SR.LaneMask) << " : " << SR
<< "\n"; } } while (false)
;
1459 // VNI is in ValNo - remove any segments in this SubRange that have this ValNo
1460 if (VNInfo *RmValNo = SR.getVNInfoAt(CurrIdx.getRegSlot())) {
1461 SR.removeValNo(RmValNo);
1462 UpdatedSubRanges = true;
1463 }
1464 } else {
1465 // We know that this lane is defined by this instruction,
1466 // but at this point it may be empty because it is not used by
1467 // anything. This happens when updateRegDefUses adds the missing
1468 // lanes. Assign that lane a dead def so that the interferences
1469 // are properly modeled.
1470 if (SR.empty())
1471 SR.createDeadDef(DefIndex, Alloc);
1472 }
1473 }
1474 if (UpdatedSubRanges)
1475 DstInt.removeEmptySubRanges();
1476 }
1477 } else if (NewMI.getOperand(0).getReg() != CopyDstReg) {
1478 // The New instruction may be defining a sub-register of what's actually
1479 // been asked for. If so it must implicitly define the whole thing.
1480 assert(Register::isPhysicalRegister(DstReg) &&((Register::isPhysicalRegister(DstReg) && "Only expect virtual or physical registers in remat"
) ? static_cast<void> (0) : __assert_fail ("Register::isPhysicalRegister(DstReg) && \"Only expect virtual or physical registers in remat\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1481, __PRETTY_FUNCTION__))
1481 "Only expect virtual or physical registers in remat")((Register::isPhysicalRegister(DstReg) && "Only expect virtual or physical registers in remat"
) ? static_cast<void> (0) : __assert_fail ("Register::isPhysicalRegister(DstReg) && \"Only expect virtual or physical registers in remat\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1481, __PRETTY_FUNCTION__))
;
1482 NewMI.getOperand(0).setIsDead(true);
1483 NewMI.addOperand(MachineOperand::CreateReg(
1484 CopyDstReg, true /*IsDef*/, true /*IsImp*/, false /*IsKill*/));
1485 // Record small dead def live-ranges for all the subregisters
1486 // of the destination register.
1487 // Otherwise, variables that live through may miss some
1488 // interferences, thus creating invalid allocation.
1489 // E.g., i386 code:
1490 // %1 = somedef ; %1 GR8
1491 // %2 = remat ; %2 GR32
1492 // CL = COPY %2.sub_8bit
1493 // = somedef %1 ; %1 GR8
1494 // =>
1495 // %1 = somedef ; %1 GR8
1496 // dead ECX = remat ; implicit-def CL
1497 // = somedef %1 ; %1 GR8
1498 // %1 will see the interferences with CL but not with CH since
1499 // no live-ranges would have been created for ECX.
1500 // Fix that!
1501 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
1502 for (MCRegUnitIterator Units(NewMI.getOperand(0).getReg(), TRI);
1503 Units.isValid(); ++Units)
1504 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
1505 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
1506 }
1507
1508 if (NewMI.getOperand(0).getSubReg())
1509 NewMI.getOperand(0).setIsUndef();
1510
1511 // Transfer over implicit operands to the rematerialized instruction.
1512 for (MachineOperand &MO : ImplicitOps)
1513 NewMI.addOperand(MO);
1514
1515 SlotIndex NewMIIdx = LIS->getInstructionIndex(NewMI);
1516 for (unsigned i = 0, e = NewMIImplDefs.size(); i != e; ++i) {
1517 unsigned Reg = NewMIImplDefs[i];
1518 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
1519 if (LiveRange *LR = LIS->getCachedRegUnit(*Units))
1520 LR->createDeadDef(NewMIIdx.getRegSlot(), LIS->getVNInfoAllocator());
1521 }
1522
1523 LLVM_DEBUG(dbgs() << "Remat: " << NewMI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Remat: " << NewMI; } }
while (false)
;
1524 ++NumReMats;
1525
1526 // If the virtual SrcReg is completely eliminated, update all DBG_VALUEs
1527 // to describe DstReg instead.
1528 if (MRI->use_nodbg_empty(SrcReg)) {
1529 for (MachineOperand &UseMO : MRI->use_operands(SrcReg)) {
1530 MachineInstr *UseMI = UseMO.getParent();
1531 if (UseMI->isDebugValue()) {
1532 if (Register::isPhysicalRegister(DstReg))
1533 UseMO.substPhysReg(DstReg, *TRI);
1534 else
1535 UseMO.setReg(DstReg);
1536 // Move the debug value directly after the def of the rematerialized
1537 // value in DstReg.
1538 MBB->splice(std::next(NewMI.getIterator()), UseMI->getParent(), UseMI);
1539 LLVM_DEBUG(dbgs() << "\t\tupdated: " << *UseMI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tupdated: " << *UseMI
; } } while (false)
;
1540 }
1541 }
1542 }
1543
1544 if (ToBeUpdated.count(SrcReg))
1545 return true;
1546
1547 unsigned NumCopyUses = 0;
1548 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
1549 if (UseMO.getParent()->isCopyLike())
1550 NumCopyUses++;
1551 }
1552 if (NumCopyUses < LateRematUpdateThreshold) {
1553 // The source interval can become smaller because we removed a use.
1554 shrinkToUses(&SrcInt, &DeadDefs);
1555 if (!DeadDefs.empty())
1556 eliminateDeadDefs();
1557 } else {
1558 ToBeUpdated.insert(SrcReg);
1559 }
1560 return true;
1561}
1562
1563MachineInstr *RegisterCoalescer::eliminateUndefCopy(MachineInstr *CopyMI) {
1564 // ProcessImplicitDefs may leave some copies of <undef> values, it only
1565 // removes local variables. When we have a copy like:
1566 //
1567 // %1 = COPY undef %2
1568 //
1569 // We delete the copy and remove the corresponding value number from %1.
1570 // Any uses of that value number are marked as <undef>.
1571
1572 // Note that we do not query CoalescerPair here but redo isMoveInstr as the
1573 // CoalescerPair may have a new register class with adjusted subreg indices
1574 // at this point.
1575 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1576 if(!isMoveInstr(*TRI, CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
1577 return nullptr;
1578
1579 SlotIndex Idx = LIS->getInstructionIndex(*CopyMI);
1580 const LiveInterval &SrcLI = LIS->getInterval(SrcReg);
1581 // CopyMI is undef iff SrcReg is not live before the instruction.
1582 if (SrcSubIdx != 0 && SrcLI.hasSubRanges()) {
1583 LaneBitmask SrcMask = TRI->getSubRegIndexLaneMask(SrcSubIdx);
1584 for (const LiveInterval::SubRange &SR : SrcLI.subranges()) {
1585 if ((SR.LaneMask & SrcMask).none())
1586 continue;
1587 if (SR.liveAt(Idx))
1588 return nullptr;
1589 }
1590 } else if (SrcLI.liveAt(Idx))
1591 return nullptr;
1592
1593 // If the undef copy defines a live-out value (i.e. an input to a PHI def),
1594 // then replace it with an IMPLICIT_DEF.
1595 LiveInterval &DstLI = LIS->getInterval(DstReg);
1596 SlotIndex RegIndex = Idx.getRegSlot();
1597 LiveRange::Segment *Seg = DstLI.getSegmentContaining(RegIndex);
1598 assert(Seg != nullptr && "No segment for defining instruction")((Seg != nullptr && "No segment for defining instruction"
) ? static_cast<void> (0) : __assert_fail ("Seg != nullptr && \"No segment for defining instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1598, __PRETTY_FUNCTION__))
;
1599 if (VNInfo *V = DstLI.getVNInfoAt(Seg->end)) {
1600 if (V->isPHIDef()) {
1601 CopyMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1602 for (unsigned i = CopyMI->getNumOperands(); i != 0; --i) {
1603 MachineOperand &MO = CopyMI->getOperand(i-1);
1604 if (MO.isReg() && MO.isUse())
1605 CopyMI->RemoveOperand(i-1);
1606 }
1607 LLVM_DEBUG(dbgs() << "\tReplaced copy of <undef> value with an "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tReplaced copy of <undef> value with an "
"implicit def\n"; } } while (false)
1608 "implicit def\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tReplaced copy of <undef> value with an "
"implicit def\n"; } } while (false)
;
1609 return CopyMI;
1610 }
1611 }
1612
1613 // Remove any DstReg segments starting at the instruction.
1614 LLVM_DEBUG(dbgs() << "\tEliminating copy of <undef> value\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tEliminating copy of <undef> value\n"
; } } while (false)
;
1615
1616 // Remove value or merge with previous one in case of a subregister def.
1617 if (VNInfo *PrevVNI = DstLI.getVNInfoAt(Idx)) {
1618 VNInfo *VNI = DstLI.getVNInfoAt(RegIndex);
1619 DstLI.MergeValueNumberInto(VNI, PrevVNI);
1620
1621 // The affected subregister segments can be removed.
1622 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx);
1623 for (LiveInterval::SubRange &SR : DstLI.subranges()) {
1624 if ((SR.LaneMask & DstMask).none())
1625 continue;
1626
1627 VNInfo *SVNI = SR.getVNInfoAt(RegIndex);
1628 assert(SVNI != nullptr && SlotIndex::isSameInstr(SVNI->def, RegIndex))((SVNI != nullptr && SlotIndex::isSameInstr(SVNI->
def, RegIndex)) ? static_cast<void> (0) : __assert_fail
("SVNI != nullptr && SlotIndex::isSameInstr(SVNI->def, RegIndex)"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1628, __PRETTY_FUNCTION__))
;
1629 SR.removeValNo(SVNI);
1630 }
1631 DstLI.removeEmptySubRanges();
1632 } else
1633 LIS->removeVRegDefAt(DstLI, RegIndex);
1634
1635 // Mark uses as undef.
1636 for (MachineOperand &MO : MRI->reg_nodbg_operands(DstReg)) {
1637 if (MO.isDef() /*|| MO.isUndef()*/)
1638 continue;
1639 const MachineInstr &MI = *MO.getParent();
1640 SlotIndex UseIdx = LIS->getInstructionIndex(MI);
1641 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
1642 bool isLive;
1643 if (!UseMask.all() && DstLI.hasSubRanges()) {
1644 isLive = false;
1645 for (const LiveInterval::SubRange &SR : DstLI.subranges()) {
1646 if ((SR.LaneMask & UseMask).none())
1647 continue;
1648 if (SR.liveAt(UseIdx)) {
1649 isLive = true;
1650 break;
1651 }
1652 }
1653 } else
1654 isLive = DstLI.liveAt(UseIdx);
1655 if (isLive)
1656 continue;
1657 MO.setIsUndef(true);
1658 LLVM_DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tnew undef: " << UseIdx
<< '\t' << MI; } } while (false)
;
1659 }
1660
1661 // A def of a subregister may be a use of the other subregisters, so
1662 // deleting a def of a subregister may also remove uses. Since CopyMI
1663 // is still part of the function (but about to be erased), mark all
1664 // defs of DstReg in it as <undef>, so that shrinkToUses would
1665 // ignore them.
1666 for (MachineOperand &MO : CopyMI->operands())
1667 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
1668 MO.setIsUndef(true);
1669 LIS->shrinkToUses(&DstLI);
1670
1671 return CopyMI;
1672}
1673
1674void RegisterCoalescer::addUndefFlag(const LiveInterval &Int, SlotIndex UseIdx,
1675 MachineOperand &MO, unsigned SubRegIdx) {
1676 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx);
1677 if (MO.isDef())
1678 Mask = ~Mask;
1679 bool IsUndef = true;
1680 for (const LiveInterval::SubRange &S : Int.subranges()) {
1681 if ((S.LaneMask & Mask).none())
1682 continue;
1683 if (S.liveAt(UseIdx)) {
1684 IsUndef = false;
1685 break;
1686 }
1687 }
1688 if (IsUndef) {
1689 MO.setIsUndef(true);
1690 // We found out some subregister use is actually reading an undefined
1691 // value. In some cases the whole vreg has become undefined at this
1692 // point so we have to potentially shrink the main range if the
1693 // use was ending a live segment there.
1694 LiveQueryResult Q = Int.Query(UseIdx);
1695 if (Q.valueOut() == nullptr)
1696 ShrinkMainRange = true;
1697 }
1698}
1699
1700void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg, unsigned DstReg,
1701 unsigned SubIdx) {
1702 bool DstIsPhys = Register::isPhysicalRegister(DstReg);
1703 LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg);
1704
1705 if (DstInt && DstInt->hasSubRanges() && DstReg != SrcReg) {
1706 for (MachineOperand &MO : MRI->reg_operands(DstReg)) {
1707 unsigned SubReg = MO.getSubReg();
1708 if (SubReg == 0 || MO.isUndef())
1709 continue;
1710 MachineInstr &MI = *MO.getParent();
1711 if (MI.isDebugValue())
1712 continue;
1713 SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot(true);
1714 addUndefFlag(*DstInt, UseIdx, MO, SubReg);
1715 }
1716 }
1717
1718 SmallPtrSet<MachineInstr*, 8> Visited;
1719 for (MachineRegisterInfo::reg_instr_iterator
1720 I = MRI->reg_instr_begin(SrcReg), E = MRI->reg_instr_end();
1721 I != E; ) {
1722 MachineInstr *UseMI = &*(I++);
1723
1724 // Each instruction can only be rewritten once because sub-register
1725 // composition is not always idempotent. When SrcReg != DstReg, rewriting
1726 // the UseMI operands removes them from the SrcReg use-def chain, but when
1727 // SrcReg is DstReg we could encounter UseMI twice if it has multiple
1728 // operands mentioning the virtual register.
1729 if (SrcReg == DstReg && !Visited.insert(UseMI).second)
1730 continue;
1731
1732 SmallVector<unsigned,8> Ops;
1733 bool Reads, Writes;
1734 std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
1735
1736 // If SrcReg wasn't read, it may still be the case that DstReg is live-in
1737 // because SrcReg is a sub-register.
1738 if (DstInt && !Reads && SubIdx && !UseMI->isDebugValue())
1739 Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
1740
1741 // Replace SrcReg with DstReg in all UseMI operands.
1742 for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
1743 MachineOperand &MO = UseMI->getOperand(Ops[i]);
1744
1745 // Adjust <undef> flags in case of sub-register joins. We don't want to
1746 // turn a full def into a read-modify-write sub-register def and vice
1747 // versa.
1748 if (SubIdx && MO.isDef())
1749 MO.setIsUndef(!Reads);
1750
1751 // A subreg use of a partially undef (super) register may be a complete
1752 // undef use now and then has to be marked that way.
1753 if (SubIdx != 0 && MO.isUse() && MRI->shouldTrackSubRegLiveness(DstReg)) {
1754 if (!DstInt->hasSubRanges()) {
1755 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
1756 LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg(DstInt->reg());
1757 LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask(SubIdx);
1758 LaneBitmask UnusedLanes = FullMask & ~UsedLanes;
1759 DstInt->createSubRangeFrom(Allocator, UsedLanes, *DstInt);
1760 // The unused lanes are just empty live-ranges at this point.
1761 // It is the caller responsibility to set the proper
1762 // dead segments if there is an actual dead def of the
1763 // unused lanes. This may happen with rematerialization.
1764 DstInt->createSubRange(Allocator, UnusedLanes);
1765 }
1766 SlotIndex MIIdx = UseMI->isDebugValue()
1767 ? LIS->getSlotIndexes()->getIndexBefore(*UseMI)
1768 : LIS->getInstructionIndex(*UseMI);
1769 SlotIndex UseIdx = MIIdx.getRegSlot(true);
1770 addUndefFlag(*DstInt, UseIdx, MO, SubIdx);
1771 }
1772
1773 if (DstIsPhys)
1774 MO.substPhysReg(DstReg, *TRI);
1775 else
1776 MO.substVirtReg(DstReg, SubIdx, *TRI);
1777 }
1778
1779 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tupdated: "; if (!UseMI
->isDebugValue()) dbgs() << LIS->getInstructionIndex
(*UseMI) << "\t"; dbgs() << *UseMI; }; } } while (
false)
1780 dbgs() << "\t\tupdated: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tupdated: "; if (!UseMI
->isDebugValue()) dbgs() << LIS->getInstructionIndex
(*UseMI) << "\t"; dbgs() << *UseMI; }; } } while (
false)
1781 if (!UseMI->isDebugValue())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tupdated: "; if (!UseMI
->isDebugValue()) dbgs() << LIS->getInstructionIndex
(*UseMI) << "\t"; dbgs() << *UseMI; }; } } while (
false)
1782 dbgs() << LIS->getInstructionIndex(*UseMI) << "\t";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tupdated: "; if (!UseMI
->isDebugValue()) dbgs() << LIS->getInstructionIndex
(*UseMI) << "\t"; dbgs() << *UseMI; }; } } while (
false)
1783 dbgs() << *UseMI;do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tupdated: "; if (!UseMI
->isDebugValue()) dbgs() << LIS->getInstructionIndex
(*UseMI) << "\t"; dbgs() << *UseMI; }; } } while (
false)
1784 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tupdated: "; if (!UseMI
->isDebugValue()) dbgs() << LIS->getInstructionIndex
(*UseMI) << "\t"; dbgs() << *UseMI; }; } } while (
false)
;
1785 }
1786}
1787
1788bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
1789 // Always join simple intervals that are defined by a single copy from a
1790 // reserved register. This doesn't increase register pressure, so it is
1791 // always beneficial.
1792 if (!MRI->isReserved(CP.getDstReg())) {
1793 LLVM_DEBUG(dbgs() << "\tCan only merge into reserved registers.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tCan only merge into reserved registers.\n"
; } } while (false)
;
1794 return false;
1795 }
1796
1797 LiveInterval &JoinVInt = LIS->getInterval(CP.getSrcReg());
1798 if (JoinVInt.containsOneValue())
1799 return true;
1800
1801 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tCannot join complex intervals into reserved register.\n"
; } } while (false)
1802 dbgs() << "\tCannot join complex intervals into reserved register.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tCannot join complex intervals into reserved register.\n"
; } } while (false)
;
1803 return false;
1804}
1805
1806bool RegisterCoalescer::joinCopy(MachineInstr *CopyMI, bool &Again) {
1807 Again = false;
1808 LLVM_DEBUG(dbgs() << LIS->getInstructionIndex(*CopyMI) << '\t' << *CopyMI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << LIS->getInstructionIndex(*
CopyMI) << '\t' << *CopyMI; } } while (false)
;
1809
1810 CoalescerPair CP(*TRI);
1811 if (!CP.setRegisters(CopyMI)) {
1812 LLVM_DEBUG(dbgs() << "\tNot coalescable.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tNot coalescable.\n"; } } while
(false)
;
1813 return false;
1814 }
1815
1816 if (CP.getNewRC()) {
1817 auto SrcRC = MRI->getRegClass(CP.getSrcReg());
1818 auto DstRC = MRI->getRegClass(CP.getDstReg());
1819 unsigned SrcIdx = CP.getSrcIdx();
1820 unsigned DstIdx = CP.getDstIdx();
1821 if (CP.isFlipped()) {
1822 std::swap(SrcIdx, DstIdx);
1823 std::swap(SrcRC, DstRC);
1824 }
1825 if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx,
1826 CP.getNewRC(), *LIS)) {
1827 LLVM_DEBUG(dbgs() << "\tSubtarget bailed on coalescing.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tSubtarget bailed on coalescing.\n"
; } } while (false)
;
1828 return false;
1829 }
1830 }
1831
1832 // Dead code elimination. This really should be handled by MachineDCE, but
1833 // sometimes dead copies slip through, and we can't generate invalid live
1834 // ranges.
1835 if (!CP.isPhys() && CopyMI->allDefsAreDead()) {
1836 LLVM_DEBUG(dbgs() << "\tCopy is dead.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tCopy is dead.\n"; } } while
(false)
;
1837 DeadDefs.push_back(CopyMI);
1838 eliminateDeadDefs();
1839 return true;
1840 }
1841
1842 // Eliminate undefs.
1843 if (!CP.isPhys()) {
1844 // If this is an IMPLICIT_DEF, leave it alone, but don't try to coalesce.
1845 if (MachineInstr *UndefMI = eliminateUndefCopy(CopyMI)) {
1846 if (UndefMI->isImplicitDef())
1847 return false;
1848 deleteInstr(CopyMI);
1849 return false; // Not coalescable.
1850 }
1851 }
1852
1853 // Coalesced copies are normally removed immediately, but transformations
1854 // like removeCopyByCommutingDef() can inadvertently create identity copies.
1855 // When that happens, just join the values and remove the copy.
1856 if (CP.getSrcReg() == CP.getDstReg()) {
1857 LiveInterval &LI = LIS->getInterval(CP.getSrcReg());
1858 LLVM_DEBUG(dbgs() << "\tCopy already coalesced: " << LI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tCopy already coalesced: " <<
LI << '\n'; } } while (false)
;
1859 const SlotIndex CopyIdx = LIS->getInstructionIndex(*CopyMI);
1860 LiveQueryResult LRQ = LI.Query(CopyIdx);
1861 if (VNInfo *DefVNI = LRQ.valueDefined()) {
1862 VNInfo *ReadVNI = LRQ.valueIn();
1863 assert(ReadVNI && "No value before copy and no <undef> flag.")((ReadVNI && "No value before copy and no <undef> flag."
) ? static_cast<void> (0) : __assert_fail ("ReadVNI && \"No value before copy and no <undef> flag.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1863, __PRETTY_FUNCTION__))
;
1864 assert(ReadVNI != DefVNI && "Cannot read and define the same value.")((ReadVNI != DefVNI && "Cannot read and define the same value."
) ? static_cast<void> (0) : __assert_fail ("ReadVNI != DefVNI && \"Cannot read and define the same value.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 1864, __PRETTY_FUNCTION__))
;
1865 LI.MergeValueNumberInto(DefVNI, ReadVNI);
1866
1867 // Process subregister liveranges.
1868 for (LiveInterval::SubRange &S : LI.subranges()) {
1869 LiveQueryResult SLRQ = S.Query(CopyIdx);
1870 if (VNInfo *SDefVNI = SLRQ.valueDefined()) {
1871 VNInfo *SReadVNI = SLRQ.valueIn();
1872 S.MergeValueNumberInto(SDefVNI, SReadVNI);
1873 }
1874 }
1875 LLVM_DEBUG(dbgs() << "\tMerged values: " << LI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tMerged values: " <<
LI << '\n'; } } while (false)
;
1876 }
1877 deleteInstr(CopyMI);
1878 return true;
1879 }
1880
1881 // Enforce policies.
1882 if (CP.isPhys()) {
1883 LLVM_DEBUG(dbgs() << "\tConsidering merging "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tConsidering merging " <<
printReg(CP.getSrcReg(), TRI) << " with " << printReg
(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; } } while
(false)
1884 << printReg(CP.getSrcReg(), TRI) << " with "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tConsidering merging " <<
printReg(CP.getSrcReg(), TRI) << " with " << printReg
(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; } } while
(false)
1885 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tConsidering merging " <<
printReg(CP.getSrcReg(), TRI) << " with " << printReg
(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; } } while
(false)
;
1886 if (!canJoinPhys(CP)) {
1887 // Before giving up coalescing, if definition of source is defined by
1888 // trivial computation, try rematerializing it.
1889 bool IsDefCopy;
1890 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
1891 return true;
1892 if (IsDefCopy)
1893 Again = true; // May be possible to coalesce later.
1894 return false;
1895 }
1896 } else {
1897 // When possible, let DstReg be the larger interval.
1898 if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).size() >
1899 LIS->getInterval(CP.getDstReg()).size())
1900 CP.flip();
1901
1902 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1903 dbgs() << "\tConsidering merging to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1904 << TRI->getRegClassName(CP.getNewRC()) << " with ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1905 if (CP.getDstIdx() && CP.getSrcIdx())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1906 dbgs() << printReg(CP.getDstReg()) << " in "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1907 << TRI->getSubRegIndexName(CP.getDstIdx()) << " and "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1908 << printReg(CP.getSrcReg()) << " in "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1909 << TRI->getSubRegIndexName(CP.getSrcIdx()) << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1910 elsedo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1911 dbgs() << printReg(CP.getSrcReg(), TRI) << " in "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1912 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
1913 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tConsidering merging to "
<< TRI->getRegClassName(CP.getNewRC()) << " with "
; if (CP.getDstIdx() && CP.getSrcIdx()) dbgs() <<
printReg(CP.getDstReg()) << " in " << TRI->getSubRegIndexName
(CP.getDstIdx()) << " and " << printReg(CP.getSrcReg
()) << " in " << TRI->getSubRegIndexName(CP.getSrcIdx
()) << '\n'; else dbgs() << printReg(CP.getSrcReg
(), TRI) << " in " << printReg(CP.getDstReg(), TRI
, CP.getSrcIdx()) << '\n'; }; } } while (false)
;
1914 }
1915
1916 ShrinkMask = LaneBitmask::getNone();
1917 ShrinkMainRange = false;
1918
1919 // Okay, attempt to join these two intervals. On failure, this returns false.
1920 // Otherwise, if one of the intervals being joined is a physreg, this method
1921 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1922 // been modified, so we can use this information below to update aliases.
1923 if (!joinIntervals(CP)) {
1924 // Coalescing failed.
1925
1926 // If definition of source is defined by trivial computation, try
1927 // rematerializing it.
1928 bool IsDefCopy;
1929 if (reMaterializeTrivialDef(CP, CopyMI, IsDefCopy))
1930 return true;
1931
1932 // If we can eliminate the copy without merging the live segments, do so
1933 // now.
1934 if (!CP.isPartial() && !CP.isPhys()) {
1935 bool Changed = adjustCopiesBackFrom(CP, CopyMI);
1936 bool Shrink = false;
1937 if (!Changed)
1938 std::tie(Changed, Shrink) = removeCopyByCommutingDef(CP, CopyMI);
1939 if (Changed) {
1940 deleteInstr(CopyMI);
1941 if (Shrink) {
1942 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg();
1943 LiveInterval &DstLI = LIS->getInterval(DstReg);
1944 shrinkToUses(&DstLI);
1945 LLVM_DEBUG(dbgs() << "\t\tshrunk: " << DstLI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tshrunk: " << DstLI
<< '\n'; } } while (false)
;
1946 }
1947 LLVM_DEBUG(dbgs() << "\tTrivial!\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tTrivial!\n"; } } while (false
)
;
1948 return true;
1949 }
1950 }
1951
1952 // Try and see if we can partially eliminate the copy by moving the copy to
1953 // its predecessor.
1954 if (!CP.isPartial() && !CP.isPhys())
1955 if (removePartialRedundancy(CP, *CopyMI))
1956 return true;
1957
1958 // Otherwise, we are unable to join the intervals.
1959 LLVM_DEBUG(dbgs() << "\tInterference!\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tInterference!\n"; } } while
(false)
;
1960 Again = true; // May be possible to coalesce later.
1961 return false;
1962 }
1963
1964 // Coalescing to a virtual register that is of a sub-register class of the
1965 // other. Make sure the resulting register is set to the right register class.
1966 if (CP.isCrossClass()) {
1967 ++numCrossRCs;
1968 MRI->setRegClass(CP.getDstReg(), CP.getNewRC());
1969 }
1970
1971 // Removing sub-register copies can ease the register class constraints.
1972 // Make sure we attempt to inflate the register class of DstReg.
1973 if (!CP.isPhys() && RegClassInfo.isProperSubClass(CP.getNewRC()))
1974 InflateRegs.push_back(CP.getDstReg());
1975
1976 // CopyMI has been erased by joinIntervals at this point. Remove it from
1977 // ErasedInstrs since copyCoalesceWorkList() won't add a successful join back
1978 // to the work list. This keeps ErasedInstrs from growing needlessly.
1979 ErasedInstrs.erase(CopyMI);
1980
1981 // Rewrite all SrcReg operands to DstReg.
1982 // Also update DstReg operands to include DstIdx if it is set.
1983 if (CP.getDstIdx())
1984 updateRegDefsUses(CP.getDstReg(), CP.getDstReg(), CP.getDstIdx());
1985 updateRegDefsUses(CP.getSrcReg(), CP.getDstReg(), CP.getSrcIdx());
1986
1987 // Shrink subregister ranges if necessary.
1988 if (ShrinkMask.any()) {
1989 LiveInterval &LI = LIS->getInterval(CP.getDstReg());
1990 for (LiveInterval::SubRange &S : LI.subranges()) {
1991 if ((S.LaneMask & ShrinkMask).none())
1992 continue;
1993 LLVM_DEBUG(dbgs() << "Shrink LaneUses (Lane " << PrintLaneMask(S.LaneMask)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Shrink LaneUses (Lane " <<
PrintLaneMask(S.LaneMask) << ")\n"; } } while (false)
1994 << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Shrink LaneUses (Lane " <<
PrintLaneMask(S.LaneMask) << ")\n"; } } while (false)
;
1995 LIS->shrinkToUses(S, LI.reg());
1996 }
1997 LI.removeEmptySubRanges();
1998 }
1999
2000 // CP.getSrcReg()'s live interval has been merged into CP.getDstReg's live
2001 // interval. Since CP.getSrcReg() is in ToBeUpdated set and its live interval
2002 // is not up-to-date, need to update the merged live interval here.
2003 if (ToBeUpdated.count(CP.getSrcReg()))
2004 ShrinkMainRange = true;
2005
2006 if (ShrinkMainRange) {
2007 LiveInterval &LI = LIS->getInterval(CP.getDstReg());
2008 shrinkToUses(&LI);
2009 }
2010
2011 // SrcReg is guaranteed to be the register whose live interval that is
2012 // being merged.
2013 LIS->removeInterval(CP.getSrcReg());
2014
2015 // Update regalloc hint.
2016 TRI->updateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *MF);
2017
2018 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tSuccess: " << printReg
(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " <<
printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; if (CP.isPhys()) dbgs() <<
printReg(CP.getDstReg(), TRI); else dbgs() << LIS->
getInterval(CP.getDstReg()); dbgs() << '\n'; }; } } while
(false)
2019 dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tSuccess: " << printReg
(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " <<
printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; if (CP.isPhys()) dbgs() <<
printReg(CP.getDstReg(), TRI); else dbgs() << LIS->
getInterval(CP.getDstReg()); dbgs() << '\n'; }; } } while
(false)
2020 << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tSuccess: " << printReg
(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " <<
printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; if (CP.isPhys()) dbgs() <<
printReg(CP.getDstReg(), TRI); else dbgs() << LIS->
getInterval(CP.getDstReg()); dbgs() << '\n'; }; } } while
(false)
2021 dbgs() << "\tResult = ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tSuccess: " << printReg
(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " <<
printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; if (CP.isPhys()) dbgs() <<
printReg(CP.getDstReg(), TRI); else dbgs() << LIS->
getInterval(CP.getDstReg()); dbgs() << '\n'; }; } } while
(false)
2022 if (CP.isPhys())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tSuccess: " << printReg
(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " <<
printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; if (CP.isPhys()) dbgs() <<
printReg(CP.getDstReg(), TRI); else dbgs() << LIS->
getInterval(CP.getDstReg()); dbgs() << '\n'; }; } } while
(false)
2023 dbgs() << printReg(CP.getDstReg(), TRI);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tSuccess: " << printReg
(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " <<
printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; if (CP.isPhys()) dbgs() <<
printReg(CP.getDstReg(), TRI); else dbgs() << LIS->
getInterval(CP.getDstReg()); dbgs() << '\n'; }; } } while
(false)
2024 elsedo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tSuccess: " << printReg
(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " <<
printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; if (CP.isPhys()) dbgs() <<
printReg(CP.getDstReg(), TRI); else dbgs() << LIS->
getInterval(CP.getDstReg()); dbgs() << '\n'; }; } } while
(false)
2025 dbgs() << LIS->getInterval(CP.getDstReg());do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tSuccess: " << printReg
(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " <<
printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; if (CP.isPhys()) dbgs() <<
printReg(CP.getDstReg(), TRI); else dbgs() << LIS->
getInterval(CP.getDstReg()); dbgs() << '\n'; }; } } while
(false)
2026 dbgs() << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tSuccess: " << printReg
(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " <<
printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; if (CP.isPhys()) dbgs() <<
printReg(CP.getDstReg(), TRI); else dbgs() << LIS->
getInterval(CP.getDstReg()); dbgs() << '\n'; }; } } while
(false)
2027 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\tSuccess: " << printReg
(CP.getSrcReg(), TRI, CP.getSrcIdx()) << " -> " <<
printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n';
dbgs() << "\tResult = "; if (CP.isPhys()) dbgs() <<
printReg(CP.getDstReg(), TRI); else dbgs() << LIS->
getInterval(CP.getDstReg()); dbgs() << '\n'; }; } } while
(false)
;
2028
2029 ++numJoins;
2030 return true;
2031}
2032
2033bool RegisterCoalescer::joinReservedPhysReg(CoalescerPair &CP) {
2034 unsigned DstReg = CP.getDstReg();
2035 unsigned SrcReg = CP.getSrcReg();
2036 assert(CP.isPhys() && "Must be a physreg copy")((CP.isPhys() && "Must be a physreg copy") ? static_cast
<void> (0) : __assert_fail ("CP.isPhys() && \"Must be a physreg copy\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2036, __PRETTY_FUNCTION__))
;
2037 assert(MRI->isReserved(DstReg) && "Not a reserved register")((MRI->isReserved(DstReg) && "Not a reserved register"
) ? static_cast<void> (0) : __assert_fail ("MRI->isReserved(DstReg) && \"Not a reserved register\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2037, __PRETTY_FUNCTION__))
;
2038 LiveInterval &RHS = LIS->getInterval(SrcReg);
2039 LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tRHS = " << RHS <<
'\n'; } } while (false)
;
2040
2041 assert(RHS.containsOneValue() && "Invalid join with reserved register")((RHS.containsOneValue() && "Invalid join with reserved register"
) ? static_cast<void> (0) : __assert_fail ("RHS.containsOneValue() && \"Invalid join with reserved register\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2041, __PRETTY_FUNCTION__))
;
2042
2043 // Optimization for reserved registers like ESP. We can only merge with a
2044 // reserved physreg if RHS has a single value that is a copy of DstReg.
2045 // The live range of the reserved register will look like a set of dead defs
2046 // - we don't properly track the live range of reserved registers.
2047
2048 // Deny any overlapping intervals. This depends on all the reserved
2049 // register live ranges to look like dead defs.
2050 if (!MRI->isConstantPhysReg(DstReg)) {
2051 for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
2052 // Abort if not all the regunits are reserved.
2053 for (MCRegUnitRootIterator RI(*UI, TRI); RI.isValid(); ++RI) {
2054 if (!MRI->isReserved(*RI))
2055 return false;
2056 }
2057 if (RHS.overlaps(LIS->getRegUnit(*UI))) {
2058 LLVM_DEBUG(dbgs() << "\t\tInterference: " << printRegUnit(*UI, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tInterference: " <<
printRegUnit(*UI, TRI) << '\n'; } } while (false)
2059 << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tInterference: " <<
printRegUnit(*UI, TRI) << '\n'; } } while (false)
;
2060 return false;
2061 }
2062 }
2063
2064 // We must also check for overlaps with regmask clobbers.
2065 BitVector RegMaskUsable;
2066 if (LIS->checkRegMaskInterference(RHS, RegMaskUsable) &&
2067 !RegMaskUsable.test(DstReg)) {
2068 LLVM_DEBUG(dbgs() << "\t\tRegMask interference\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tRegMask interference\n";
} } while (false)
;
2069 return false;
2070 }
2071 }
2072
2073 // Skip any value computations, we are not adding new values to the
2074 // reserved register. Also skip merging the live ranges, the reserved
2075 // register live range doesn't need to be accurate as long as all the
2076 // defs are there.
2077
2078 // Delete the identity copy.
2079 MachineInstr *CopyMI;
2080 if (CP.isFlipped()) {
2081 // Physreg is copied into vreg
2082 // %y = COPY %physreg_x
2083 // ... //< no other def of %physreg_x here
2084 // use %y
2085 // =>
2086 // ...
2087 // use %physreg_x
2088 CopyMI = MRI->getVRegDef(SrcReg);
2089 } else {
2090 // VReg is copied into physreg:
2091 // %y = def
2092 // ... //< no other def or use of %physreg_x here
2093 // %physreg_x = COPY %y
2094 // =>
2095 // %physreg_x = def
2096 // ...
2097 if (!MRI->hasOneNonDBGUse(SrcReg)) {
2098 LLVM_DEBUG(dbgs() << "\t\tMultiple vreg uses!\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tMultiple vreg uses!\n"; }
} while (false)
;
2099 return false;
2100 }
2101
2102 if (!LIS->intervalIsInOneMBB(RHS)) {
2103 LLVM_DEBUG(dbgs() << "\t\tComplex control flow!\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tComplex control flow!\n"
; } } while (false)
;
2104 return false;
2105 }
2106
2107 MachineInstr &DestMI = *MRI->getVRegDef(SrcReg);
2108 CopyMI = &*MRI->use_instr_nodbg_begin(SrcReg);
2109 SlotIndex CopyRegIdx = LIS->getInstructionIndex(*CopyMI).getRegSlot();
2110 SlotIndex DestRegIdx = LIS->getInstructionIndex(DestMI).getRegSlot();
2111
2112 if (!MRI->isConstantPhysReg(DstReg)) {
2113 // We checked above that there are no interfering defs of the physical
2114 // register. However, for this case, where we intend to move up the def of
2115 // the physical register, we also need to check for interfering uses.
2116 SlotIndexes *Indexes = LIS->getSlotIndexes();
2117 for (SlotIndex SI = Indexes->getNextNonNullIndex(DestRegIdx);
2118 SI != CopyRegIdx; SI = Indexes->getNextNonNullIndex(SI)) {
2119 MachineInstr *MI = LIS->getInstructionFromIndex(SI);
2120 if (MI->readsRegister(DstReg, TRI)) {
2121 LLVM_DEBUG(dbgs() << "\t\tInterference (read): " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tInterference (read): " <<
*MI; } } while (false)
;
2122 return false;
2123 }
2124 }
2125 }
2126
2127 // We're going to remove the copy which defines a physical reserved
2128 // register, so remove its valno, etc.
2129 LLVM_DEBUG(dbgs() << "\t\tRemoving phys reg def of "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tRemoving phys reg def of "
<< printReg(DstReg, TRI) << " at " << CopyRegIdx
<< "\n"; } } while (false)
2130 << printReg(DstReg, TRI) << " at " << CopyRegIdx << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tRemoving phys reg def of "
<< printReg(DstReg, TRI) << " at " << CopyRegIdx
<< "\n"; } } while (false)
;
2131
2132 LIS->removePhysRegDefAt(DstReg, CopyRegIdx);
2133 // Create a new dead def at the new def location.
2134 for (MCRegUnitIterator UI(DstReg, TRI); UI.isValid(); ++UI) {
2135 LiveRange &LR = LIS->getRegUnit(*UI);
2136 LR.createDeadDef(DestRegIdx, LIS->getVNInfoAllocator());
2137 }
2138 }
2139
2140 deleteInstr(CopyMI);
2141
2142 // We don't track kills for reserved registers.
2143 MRI->clearKillFlags(CP.getSrcReg());
2144
2145 return true;
2146}
2147
2148//===----------------------------------------------------------------------===//
2149// Interference checking and interval joining
2150//===----------------------------------------------------------------------===//
2151//
2152// In the easiest case, the two live ranges being joined are disjoint, and
2153// there is no interference to consider. It is quite common, though, to have
2154// overlapping live ranges, and we need to check if the interference can be
2155// resolved.
2156//
2157// The live range of a single SSA value forms a sub-tree of the dominator tree.
2158// This means that two SSA values overlap if and only if the def of one value
2159// is contained in the live range of the other value. As a special case, the
2160// overlapping values can be defined at the same index.
2161//
2162// The interference from an overlapping def can be resolved in these cases:
2163//
2164// 1. Coalescable copies. The value is defined by a copy that would become an
2165// identity copy after joining SrcReg and DstReg. The copy instruction will
2166// be removed, and the value will be merged with the source value.
2167//
2168// There can be several copies back and forth, causing many values to be
2169// merged into one. We compute a list of ultimate values in the joined live
2170// range as well as a mappings from the old value numbers.
2171//
2172// 2. IMPLICIT_DEF. This instruction is only inserted to ensure all PHI
2173// predecessors have a live out value. It doesn't cause real interference,
2174// and can be merged into the value it overlaps. Like a coalescable copy, it
2175// can be erased after joining.
2176//
2177// 3. Copy of external value. The overlapping def may be a copy of a value that
2178// is already in the other register. This is like a coalescable copy, but
2179// the live range of the source register must be trimmed after erasing the
2180// copy instruction:
2181//
2182// %src = COPY %ext
2183// %dst = COPY %ext <-- Remove this COPY, trim the live range of %ext.
2184//
2185// 4. Clobbering undefined lanes. Vector registers are sometimes built by
2186// defining one lane at a time:
2187//
2188// %dst:ssub0<def,read-undef> = FOO
2189// %src = BAR
2190// %dst:ssub1 = COPY %src
2191//
2192// The live range of %src overlaps the %dst value defined by FOO, but
2193// merging %src into %dst:ssub1 is only going to clobber the ssub1 lane
2194// which was undef anyway.
2195//
2196// The value mapping is more complicated in this case. The final live range
2197// will have different value numbers for both FOO and BAR, but there is no
2198// simple mapping from old to new values. It may even be necessary to add
2199// new PHI values.
2200//
2201// 5. Clobbering dead lanes. A def may clobber a lane of a vector register that
2202// is live, but never read. This can happen because we don't compute
2203// individual live ranges per lane.
2204//
2205// %dst = FOO
2206// %src = BAR
2207// %dst:ssub1 = COPY %src
2208//
2209// This kind of interference is only resolved locally. If the clobbered
2210// lane value escapes the block, the join is aborted.
2211
2212namespace {
2213
2214/// Track information about values in a single virtual register about to be
2215/// joined. Objects of this class are always created in pairs - one for each
2216/// side of the CoalescerPair (or one for each lane of a side of the coalescer
2217/// pair)
2218class JoinVals {
2219 /// Live range we work on.
2220 LiveRange &LR;
2221
2222 /// (Main) register we work on.
2223 const unsigned Reg;
2224
2225 /// Reg (and therefore the values in this liverange) will end up as
2226 /// subregister SubIdx in the coalesced register. Either CP.DstIdx or
2227 /// CP.SrcIdx.
2228 const unsigned SubIdx;
2229
2230 /// The LaneMask that this liverange will occupy the coalesced register. May
2231 /// be smaller than the lanemask produced by SubIdx when merging subranges.
2232 const LaneBitmask LaneMask;
2233
2234 /// This is true when joining sub register ranges, false when joining main
2235 /// ranges.
2236 const bool SubRangeJoin;
2237
2238 /// Whether the current LiveInterval tracks subregister liveness.
2239 const bool TrackSubRegLiveness;
2240
2241 /// Values that will be present in the final live range.
2242 SmallVectorImpl<VNInfo*> &NewVNInfo;
2243
2244 const CoalescerPair &CP;
2245 LiveIntervals *LIS;
2246 SlotIndexes *Indexes;
2247 const TargetRegisterInfo *TRI;
2248
2249 /// Value number assignments. Maps value numbers in LI to entries in
2250 /// NewVNInfo. This is suitable for passing to LiveInterval::join().
2251 SmallVector<int, 8> Assignments;
2252
2253 public:
2254 /// Conflict resolution for overlapping values.
2255 enum ConflictResolution {
2256 /// No overlap, simply keep this value.
2257 CR_Keep,
2258
2259 /// Merge this value into OtherVNI and erase the defining instruction.
2260 /// Used for IMPLICIT_DEF, coalescable copies, and copies from external
2261 /// values.
2262 CR_Erase,
2263
2264 /// Merge this value into OtherVNI but keep the defining instruction.
2265 /// This is for the special case where OtherVNI is defined by the same
2266 /// instruction.
2267 CR_Merge,
2268
2269 /// Keep this value, and have it replace OtherVNI where possible. This
2270 /// complicates value mapping since OtherVNI maps to two different values
2271 /// before and after this def.
2272 /// Used when clobbering undefined or dead lanes.
2273 CR_Replace,
2274
2275 /// Unresolved conflict. Visit later when all values have been mapped.
2276 CR_Unresolved,
2277
2278 /// Unresolvable conflict. Abort the join.
2279 CR_Impossible
2280 };
2281
2282 private:
2283 /// Per-value info for LI. The lane bit masks are all relative to the final
2284 /// joined register, so they can be compared directly between SrcReg and
2285 /// DstReg.
2286 struct Val {
2287 ConflictResolution Resolution = CR_Keep;
2288
2289 /// Lanes written by this def, 0 for unanalyzed values.
2290 LaneBitmask WriteLanes;
2291
2292 /// Lanes with defined values in this register. Other lanes are undef and
2293 /// safe to clobber.
2294 LaneBitmask ValidLanes;
2295
2296 /// Value in LI being redefined by this def.
2297 VNInfo *RedefVNI = nullptr;
2298
2299 /// Value in the other live range that overlaps this def, if any.
2300 VNInfo *OtherVNI = nullptr;
2301
2302 /// Is this value an IMPLICIT_DEF that can be erased?
2303 ///
2304 /// IMPLICIT_DEF values should only exist at the end of a basic block that
2305 /// is a predecessor to a phi-value. These IMPLICIT_DEF instructions can be
2306 /// safely erased if they are overlapping a live value in the other live
2307 /// interval.
2308 ///
2309 /// Weird control flow graphs and incomplete PHI handling in
2310 /// ProcessImplicitDefs can very rarely create IMPLICIT_DEF values with
2311 /// longer live ranges. Such IMPLICIT_DEF values should be treated like
2312 /// normal values.
2313 bool ErasableImplicitDef = false;
2314
2315 /// True when the live range of this value will be pruned because of an
2316 /// overlapping CR_Replace value in the other live range.
2317 bool Pruned = false;
2318
2319 /// True once Pruned above has been computed.
2320 bool PrunedComputed = false;
2321
2322 /// True if this value is determined to be identical to OtherVNI
2323 /// (in valuesIdentical). This is used with CR_Erase where the erased
2324 /// copy is redundant, i.e. the source value is already the same as
2325 /// the destination. In such cases the subranges need to be updated
2326 /// properly. See comment at pruneSubRegValues for more info.
2327 bool Identical = false;
2328
2329 Val() = default;
2330
2331 bool isAnalyzed() const { return WriteLanes.any(); }
2332 };
2333
2334 /// One entry per value number in LI.
2335 SmallVector<Val, 8> Vals;
2336
2337 /// Compute the bitmask of lanes actually written by DefMI.
2338 /// Set Redef if there are any partial register definitions that depend on the
2339 /// previous value of the register.
2340 LaneBitmask computeWriteLanes(const MachineInstr *DefMI, bool &Redef) const;
2341
2342 /// Find the ultimate value that VNI was copied from.
2343 std::pair<const VNInfo*,unsigned> followCopyChain(const VNInfo *VNI) const;
2344
2345 bool valuesIdentical(VNInfo *Value0, VNInfo *Value1, const JoinVals &Other) const;
2346
2347 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
2348 /// Return a conflict resolution when possible, but leave the hard cases as
2349 /// CR_Unresolved.
2350 /// Recursively calls computeAssignment() on this and Other, guaranteeing that
2351 /// both OtherVNI and RedefVNI have been analyzed and mapped before returning.
2352 /// The recursion always goes upwards in the dominator tree, making loops
2353 /// impossible.
2354 ConflictResolution analyzeValue(unsigned ValNo, JoinVals &Other);
2355
2356 /// Compute the value assignment for ValNo in RI.
2357 /// This may be called recursively by analyzeValue(), but never for a ValNo on
2358 /// the stack.
2359 void computeAssignment(unsigned ValNo, JoinVals &Other);
2360
2361 /// Assuming ValNo is going to clobber some valid lanes in Other.LR, compute
2362 /// the extent of the tainted lanes in the block.
2363 ///
2364 /// Multiple values in Other.LR can be affected since partial redefinitions
2365 /// can preserve previously tainted lanes.
2366 ///
2367 /// 1 %dst = VLOAD <-- Define all lanes in %dst
2368 /// 2 %src = FOO <-- ValNo to be joined with %dst:ssub0
2369 /// 3 %dst:ssub1 = BAR <-- Partial redef doesn't clear taint in ssub0
2370 /// 4 %dst:ssub0 = COPY %src <-- Conflict resolved, ssub0 wasn't read
2371 ///
2372 /// For each ValNo in Other that is affected, add an (EndIndex, TaintedLanes)
2373 /// entry to TaintedVals.
2374 ///
2375 /// Returns false if the tainted lanes extend beyond the basic block.
2376 bool
2377 taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
2378 SmallVectorImpl<std::pair<SlotIndex, LaneBitmask>> &TaintExtent);
2379
2380 /// Return true if MI uses any of the given Lanes from Reg.
2381 /// This does not include partial redefinitions of Reg.
2382 bool usesLanes(const MachineInstr &MI, unsigned, unsigned, LaneBitmask) const;
2383
2384 /// Determine if ValNo is a copy of a value number in LR or Other.LR that will
2385 /// be pruned:
2386 ///
2387 /// %dst = COPY %src
2388 /// %src = COPY %dst <-- This value to be pruned.
2389 /// %dst = COPY %src <-- This value is a copy of a pruned value.
2390 bool isPrunedValue(unsigned ValNo, JoinVals &Other);
2391
2392public:
2393 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask,
2394 SmallVectorImpl<VNInfo*> &newVNInfo, const CoalescerPair &cp,
2395 LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin,
2396 bool TrackSubRegLiveness)
2397 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask),
2398 SubRangeJoin(SubRangeJoin), TrackSubRegLiveness(TrackSubRegLiveness),
2399 NewVNInfo(newVNInfo), CP(cp), LIS(lis), Indexes(LIS->getSlotIndexes()),
2400 TRI(TRI), Assignments(LR.getNumValNums(), -1), Vals(LR.getNumValNums()) {}
2401
2402 /// Analyze defs in LR and compute a value mapping in NewVNInfo.
2403 /// Returns false if any conflicts were impossible to resolve.
2404 bool mapValues(JoinVals &Other);
2405
2406 /// Try to resolve conflicts that require all values to be mapped.
2407 /// Returns false if any conflicts were impossible to resolve.
2408 bool resolveConflicts(JoinVals &Other);
2409
2410 /// Prune the live range of values in Other.LR where they would conflict with
2411 /// CR_Replace values in LR. Collect end points for restoring the live range
2412 /// after joining.
2413 void pruneValues(JoinVals &Other, SmallVectorImpl<SlotIndex> &EndPoints,
2414 bool changeInstrs);
2415
2416 /// Removes subranges starting at copies that get removed. This sometimes
2417 /// happens when undefined subranges are copied around. These ranges contain
2418 /// no useful information and can be removed.
2419 void pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask);
2420
2421 /// Pruning values in subranges can lead to removing segments in these
2422 /// subranges started by IMPLICIT_DEFs. The corresponding segments in
2423 /// the main range also need to be removed. This function will mark
2424 /// the corresponding values in the main range as pruned, so that
2425 /// eraseInstrs can do the final cleanup.
2426 /// The parameter @p LI must be the interval whose main range is the
2427 /// live range LR.
2428 void pruneMainSegments(LiveInterval &LI, bool &ShrinkMainRange);
2429
2430 /// Erase any machine instructions that have been coalesced away.
2431 /// Add erased instructions to ErasedInstrs.
2432 /// Add foreign virtual registers to ShrinkRegs if their live range ended at
2433 /// the erased instrs.
2434 void eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
2435 SmallVectorImpl<Register> &ShrinkRegs,
2436 LiveInterval *LI = nullptr);
2437
2438 /// Remove liverange defs at places where implicit defs will be removed.
2439 void removeImplicitDefs();
2440
2441 /// Get the value assignments suitable for passing to LiveInterval::join.
2442 const int *getAssignments() const { return Assignments.data(); }
2443
2444 /// Get the conflict resolution for a value number.
2445 ConflictResolution getResolution(unsigned Num) const {
2446 return Vals[Num].Resolution;
2447 }
2448};
2449
2450} // end anonymous namespace
2451
2452LaneBitmask JoinVals::computeWriteLanes(const MachineInstr *DefMI, bool &Redef)
2453 const {
2454 LaneBitmask L;
2455 for (const MachineOperand &MO : DefMI->operands()) {
2456 if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
2457 continue;
2458 L |= TRI->getSubRegIndexLaneMask(
2459 TRI->composeSubRegIndices(SubIdx, MO.getSubReg()));
2460 if (MO.readsReg())
2461 Redef = true;
2462 }
2463 return L;
2464}
2465
2466std::pair<const VNInfo*, unsigned> JoinVals::followCopyChain(
2467 const VNInfo *VNI) const {
2468 unsigned TrackReg = Reg;
2469
2470 while (!VNI->isPHIDef()) {
2
Calling 'VNInfo::isPHIDef'
8
Returning from 'VNInfo::isPHIDef'
9
Loop condition is true. Entering loop body
23
Called C++ object pointer is null
2471 SlotIndex Def = VNI->def;
2472 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
2473 assert(MI && "No defining instruction")((MI && "No defining instruction") ? static_cast<void
> (0) : __assert_fail ("MI && \"No defining instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2473, __PRETTY_FUNCTION__))
;
10
Assuming 'MI' is non-null
11
'?' condition is true
2474 if (!MI->isFullCopy())
12
Taking false branch
2475 return std::make_pair(VNI, TrackReg);
2476 Register SrcReg = MI->getOperand(1).getReg();
2477 if (!Register::isVirtualRegister(SrcReg))
13
Taking false branch
2478 return std::make_pair(VNI, TrackReg);
2479
2480 const LiveInterval &LI = LIS->getInterval(SrcReg);
2481 const VNInfo *ValueIn;
2482 // No subrange involved.
2483 if (!SubRangeJoin || !LI.hasSubRanges()) {
14
Assuming field 'SubRangeJoin' is false
2484 LiveQueryResult LRQ = LI.Query(Def);
2485 ValueIn = LRQ.valueIn();
2486 } else {
2487 // Query subranges. Ensure that all matching ones take us to the same def
2488 // (allowing some of them to be undef).
2489 ValueIn = nullptr;
2490 for (const LiveInterval::SubRange &S : LI.subranges()) {
2491 // Transform lanemask to a mask in the joined live interval.
2492 LaneBitmask SMask = TRI->composeSubRegIndexLaneMask(SubIdx, S.LaneMask);
2493 if ((SMask & LaneMask).none())
2494 continue;
2495 LiveQueryResult LRQ = S.Query(Def);
2496 if (!ValueIn) {
2497 ValueIn = LRQ.valueIn();
2498 continue;
2499 }
2500 if (LRQ.valueIn() && ValueIn != LRQ.valueIn())
2501 return std::make_pair(VNI, TrackReg);
2502 }
2503 }
2504 if (ValueIn == nullptr) {
15
Assuming the condition is true
16
Taking true branch
2505 // Reaching an undefined value is legitimate, for example:
2506 //
2507 // 1 undef %0.sub1 = ... ;; %0.sub0 == undef
2508 // 2 %1 = COPY %0 ;; %1 is defined here.
2509 // 3 %0 = COPY %1 ;; Now %0.sub0 has a definition,
2510 // ;; but it's equivalent to "undef".
2511 return std::make_pair(nullptr, SrcReg);
2512 }
2513 VNI = ValueIn;
2514 TrackReg = SrcReg;
2515 }
2516 return std::make_pair(VNI, TrackReg);
2517}
2518
2519bool JoinVals::valuesIdentical(VNInfo *Value0, VNInfo *Value1,
2520 const JoinVals &Other) const {
2521 const VNInfo *Orig0;
2522 unsigned Reg0;
2523 std::tie(Orig0, Reg0) = followCopyChain(Value0);
1
Calling 'JoinVals::followCopyChain'
17
Returning from 'JoinVals::followCopyChain'
2524 if (Orig0 == Value1 && Reg0 == Other.Reg)
18
Assuming 'Orig0' is equal to 'Value1'
19
Assuming 'Reg0' is not equal to field 'Reg'
20
Taking false branch
2525 return true;
2526
2527 const VNInfo *Orig1;
2528 unsigned Reg1;
2529 std::tie(Orig1, Reg1) = Other.followCopyChain(Value1);
21
Passing null pointer value via 1st parameter 'VNI'
22
Calling 'JoinVals::followCopyChain'
2530 // If both values are undefined, and the source registers are the same
2531 // register, the values are identical. Filter out cases where only one
2532 // value is defined.
2533 if (Orig0 == nullptr || Orig1 == nullptr)
2534 return Orig0 == Orig1 && Reg0 == Reg1;
2535
2536 // The values are equal if they are defined at the same place and use the
2537 // same register. Note that we cannot compare VNInfos directly as some of
2538 // them might be from a copy created in mergeSubRangeInto() while the other
2539 // is from the original LiveInterval.
2540 return Orig0->def == Orig1->def && Reg0 == Reg1;
2541}
2542
2543JoinVals::ConflictResolution
2544JoinVals::analyzeValue(unsigned ValNo, JoinVals &Other) {
2545 Val &V = Vals[ValNo];
2546 assert(!V.isAnalyzed() && "Value has already been analyzed!")((!V.isAnalyzed() && "Value has already been analyzed!"
) ? static_cast<void> (0) : __assert_fail ("!V.isAnalyzed() && \"Value has already been analyzed!\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2546, __PRETTY_FUNCTION__))
;
2547 VNInfo *VNI = LR.getValNumInfo(ValNo);
2548 if (VNI->isUnused()) {
2549 V.WriteLanes = LaneBitmask::getAll();
2550 return CR_Keep;
2551 }
2552
2553 // Get the instruction defining this value, compute the lanes written.
2554 const MachineInstr *DefMI = nullptr;
2555 if (VNI->isPHIDef()) {
2556 // Conservatively assume that all lanes in a PHI are valid.
2557 LaneBitmask Lanes = SubRangeJoin ? LaneBitmask::getLane(0)
2558 : TRI->getSubRegIndexLaneMask(SubIdx);
2559 V.ValidLanes = V.WriteLanes = Lanes;
2560 } else {
2561 DefMI = Indexes->getInstructionFromIndex(VNI->def);
2562 assert(DefMI != nullptr)((DefMI != nullptr) ? static_cast<void> (0) : __assert_fail
("DefMI != nullptr", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2562, __PRETTY_FUNCTION__))
;
2563 if (SubRangeJoin) {
2564 // We don't care about the lanes when joining subregister ranges.
2565 V.WriteLanes = V.ValidLanes = LaneBitmask::getLane(0);
2566 if (DefMI->isImplicitDef()) {
2567 V.ValidLanes = LaneBitmask::getNone();
2568 V.ErasableImplicitDef = true;
2569 }
2570 } else {
2571 bool Redef = false;
2572 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef);
2573
2574 // If this is a read-modify-write instruction, there may be more valid
2575 // lanes than the ones written by this instruction.
2576 // This only covers partial redef operands. DefMI may have normal use
2577 // operands reading the register. They don't contribute valid lanes.
2578 //
2579 // This adds ssub1 to the set of valid lanes in %src:
2580 //
2581 // %src:ssub1 = FOO
2582 //
2583 // This leaves only ssub1 valid, making any other lanes undef:
2584 //
2585 // %src:ssub1<def,read-undef> = FOO %src:ssub2
2586 //
2587 // The <read-undef> flag on the def operand means that old lane values are
2588 // not important.
2589 if (Redef) {
2590 V.RedefVNI = LR.Query(VNI->def).valueIn();
2591 assert((TrackSubRegLiveness || V.RedefVNI) &&(((TrackSubRegLiveness || V.RedefVNI) && "Instruction is reading nonexistent value"
) ? static_cast<void> (0) : __assert_fail ("(TrackSubRegLiveness || V.RedefVNI) && \"Instruction is reading nonexistent value\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2592, __PRETTY_FUNCTION__))
2592 "Instruction is reading nonexistent value")(((TrackSubRegLiveness || V.RedefVNI) && "Instruction is reading nonexistent value"
) ? static_cast<void> (0) : __assert_fail ("(TrackSubRegLiveness || V.RedefVNI) && \"Instruction is reading nonexistent value\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2592, __PRETTY_FUNCTION__))
;
2593 if (V.RedefVNI != nullptr) {
2594 computeAssignment(V.RedefVNI->id, Other);
2595 V.ValidLanes |= Vals[V.RedefVNI->id].ValidLanes;
2596 }
2597 }
2598
2599 // An IMPLICIT_DEF writes undef values.
2600 if (DefMI->isImplicitDef()) {
2601 // We normally expect IMPLICIT_DEF values to be live only until the end
2602 // of their block. If the value is really live longer and gets pruned in
2603 // another block, this flag is cleared again.
2604 //
2605 // Clearing the valid lanes is deferred until it is sure this can be
2606 // erased.
2607 V.ErasableImplicitDef = true;
2608 }
2609 }
2610 }
2611
2612 // Find the value in Other that overlaps VNI->def, if any.
2613 LiveQueryResult OtherLRQ = Other.LR.Query(VNI->def);
2614
2615 // It is possible that both values are defined by the same instruction, or
2616 // the values are PHIs defined in the same block. When that happens, the two
2617 // values should be merged into one, but not into any preceding value.
2618 // The first value defined or visited gets CR_Keep, the other gets CR_Merge.
2619 if (VNInfo *OtherVNI = OtherLRQ.valueDefined()) {
2620 assert(SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && "Broken LRQ")((SlotIndex::isSameInstr(VNI->def, OtherVNI->def) &&
"Broken LRQ") ? static_cast<void> (0) : __assert_fail (
"SlotIndex::isSameInstr(VNI->def, OtherVNI->def) && \"Broken LRQ\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2620, __PRETTY_FUNCTION__))
;
2621
2622 // One value stays, the other is merged. Keep the earlier one, or the first
2623 // one we see.
2624 if (OtherVNI->def < VNI->def)
2625 Other.computeAssignment(OtherVNI->id, *this);
2626 else if (VNI->def < OtherVNI->def && OtherLRQ.valueIn()) {
2627 // This is an early-clobber def overlapping a live-in value in the other
2628 // register. Not mergeable.
2629 V.OtherVNI = OtherLRQ.valueIn();
2630 return CR_Impossible;
2631 }
2632 V.OtherVNI = OtherVNI;
2633 Val &OtherV = Other.Vals[OtherVNI->id];
2634 // Keep this value, check for conflicts when analyzing OtherVNI.
2635 if (!OtherV.isAnalyzed())
2636 return CR_Keep;
2637 // Both sides have been analyzed now.
2638 // Allow overlapping PHI values. Any real interference would show up in a
2639 // predecessor, the PHI itself can't introduce any conflicts.
2640 if (VNI->isPHIDef())
2641 return CR_Merge;
2642 if ((V.ValidLanes & OtherV.ValidLanes).any())
2643 // Overlapping lanes can't be resolved.
2644 return CR_Impossible;
2645 else
2646 return CR_Merge;
2647 }
2648
2649 // No simultaneous def. Is Other live at the def?
2650 V.OtherVNI = OtherLRQ.valueIn();
2651 if (!V.OtherVNI)
2652 // No overlap, no conflict.
2653 return CR_Keep;
2654
2655 assert(!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && "Broken LRQ")((!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) &&
"Broken LRQ") ? static_cast<void> (0) : __assert_fail (
"!SlotIndex::isSameInstr(VNI->def, V.OtherVNI->def) && \"Broken LRQ\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2655, __PRETTY_FUNCTION__))
;
2656
2657 // We have overlapping values, or possibly a kill of Other.
2658 // Recursively compute assignments up the dominator tree.
2659 Other.computeAssignment(V.OtherVNI->id, *this);
2660 Val &OtherV = Other.Vals[V.OtherVNI->id];
2661
2662 if (OtherV.ErasableImplicitDef) {
2663 // Check if OtherV is an IMPLICIT_DEF that extends beyond its basic block.
2664 // This shouldn't normally happen, but ProcessImplicitDefs can leave such
2665 // IMPLICIT_DEF instructions behind, and there is nothing wrong with it
2666 // technically.
2667 //
2668 // When it happens, treat that IMPLICIT_DEF as a normal value, and don't try
2669 // to erase the IMPLICIT_DEF instruction.
2670 if (DefMI &&
2671 DefMI->getParent() != Indexes->getMBBFromIndex(V.OtherVNI->def)) {
2672 LLVM_DEBUG(dbgs() << "IMPLICIT_DEF defined at " << V.OtherVNI->defdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "IMPLICIT_DEF defined at " <<
V.OtherVNI->def << " extends into " << printMBBReference
(*DefMI->getParent()) << ", keeping it.\n"; } } while
(false)
2673 << " extends into "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "IMPLICIT_DEF defined at " <<
V.OtherVNI->def << " extends into " << printMBBReference
(*DefMI->getParent()) << ", keeping it.\n"; } } while
(false)
2674 << printMBBReference(*DefMI->getParent())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "IMPLICIT_DEF defined at " <<
V.OtherVNI->def << " extends into " << printMBBReference
(*DefMI->getParent()) << ", keeping it.\n"; } } while
(false)
2675 << ", keeping it.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "IMPLICIT_DEF defined at " <<
V.OtherVNI->def << " extends into " << printMBBReference
(*DefMI->getParent()) << ", keeping it.\n"; } } while
(false)
;
2676 OtherV.ErasableImplicitDef = false;
2677 } else {
2678 // We deferred clearing these lanes in case we needed to save them
2679 OtherV.ValidLanes &= ~OtherV.WriteLanes;
2680 }
2681 }
2682
2683 // Allow overlapping PHI values. Any real interference would show up in a
2684 // predecessor, the PHI itself can't introduce any conflicts.
2685 if (VNI->isPHIDef())
2686 return CR_Replace;
2687
2688 // Check for simple erasable conflicts.
2689 if (DefMI->isImplicitDef())
2690 return CR_Erase;
2691
2692 // Include the non-conflict where DefMI is a coalescable copy that kills
2693 // OtherVNI. We still want the copy erased and value numbers merged.
2694 if (CP.isCoalescable(DefMI)) {
2695 // Some of the lanes copied from OtherVNI may be undef, making them undef
2696 // here too.
2697 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes;
2698 return CR_Erase;
2699 }
2700
2701 // This may not be a real conflict if DefMI simply kills Other and defines
2702 // VNI.
2703 if (OtherLRQ.isKill() && OtherLRQ.endPoint() <= VNI->def)
2704 return CR_Keep;
2705
2706 // Handle the case where VNI and OtherVNI can be proven to be identical:
2707 //
2708 // %other = COPY %ext
2709 // %this = COPY %ext <-- Erase this copy
2710 //
2711 if (DefMI->isFullCopy() && !CP.isPartial() &&
2712 valuesIdentical(VNI, V.OtherVNI, Other)) {
2713 V.Identical = true;
2714 return CR_Erase;
2715 }
2716
2717 // The remaining checks apply to the lanes, which aren't tracked here. This
2718 // was already decided to be OK via the following CR_Replace condition.
2719 // CR_Replace.
2720 if (SubRangeJoin)
2721 return CR_Replace;
2722
2723 // If the lanes written by this instruction were all undef in OtherVNI, it is
2724 // still safe to join the live ranges. This can't be done with a simple value
2725 // mapping, though - OtherVNI will map to multiple values:
2726 //
2727 // 1 %dst:ssub0 = FOO <-- OtherVNI
2728 // 2 %src = BAR <-- VNI
2729 // 3 %dst:ssub1 = COPY killed %src <-- Eliminate this copy.
2730 // 4 BAZ killed %dst
2731 // 5 QUUX killed %src
2732 //
2733 // Here OtherVNI will map to itself in [1;2), but to VNI in [2;5). CR_Replace
2734 // handles this complex value mapping.
2735 if ((V.WriteLanes & OtherV.ValidLanes).none())
2736 return CR_Replace;
2737
2738 // If the other live range is killed by DefMI and the live ranges are still
2739 // overlapping, it must be because we're looking at an early clobber def:
2740 //
2741 // %dst<def,early-clobber> = ASM killed %src
2742 //
2743 // In this case, it is illegal to merge the two live ranges since the early
2744 // clobber def would clobber %src before it was read.
2745 if (OtherLRQ.isKill()) {
2746 // This case where the def doesn't overlap the kill is handled above.
2747 assert(VNI->def.isEarlyClobber() &&((VNI->def.isEarlyClobber() && "Only early clobber defs can overlap a kill"
) ? static_cast<void> (0) : __assert_fail ("VNI->def.isEarlyClobber() && \"Only early clobber defs can overlap a kill\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2748, __PRETTY_FUNCTION__))
2748 "Only early clobber defs can overlap a kill")((VNI->def.isEarlyClobber() && "Only early clobber defs can overlap a kill"
) ? static_cast<void> (0) : __assert_fail ("VNI->def.isEarlyClobber() && \"Only early clobber defs can overlap a kill\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2748, __PRETTY_FUNCTION__))
;
2749 return CR_Impossible;
2750 }
2751
2752 // VNI is clobbering live lanes in OtherVNI, but there is still the
2753 // possibility that no instructions actually read the clobbered lanes.
2754 // If we're clobbering all the lanes in OtherVNI, at least one must be read.
2755 // Otherwise Other.RI wouldn't be live here.
2756 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes).none())
2757 return CR_Impossible;
2758
2759 // We need to verify that no instructions are reading the clobbered lanes. To
2760 // save compile time, we'll only check that locally. Don't allow the tainted
2761 // value to escape the basic block.
2762 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
2763 if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(MBB))
2764 return CR_Impossible;
2765
2766 // There are still some things that could go wrong besides clobbered lanes
2767 // being read, for example OtherVNI may be only partially redefined in MBB,
2768 // and some clobbered lanes could escape the block. Save this analysis for
2769 // resolveConflicts() when all values have been mapped. We need to know
2770 // RedefVNI and WriteLanes for any later defs in MBB, and we can't compute
2771 // that now - the recursive analyzeValue() calls must go upwards in the
2772 // dominator tree.
2773 return CR_Unresolved;
2774}
2775
2776void JoinVals::computeAssignment(unsigned ValNo, JoinVals &Other) {
2777 Val &V = Vals[ValNo];
2778 if (V.isAnalyzed()) {
2779 // Recursion should always move up the dominator tree, so ValNo is not
2780 // supposed to reappear before it has been assigned.
2781 assert(Assignments[ValNo] != -1 && "Bad recursion?")((Assignments[ValNo] != -1 && "Bad recursion?") ? static_cast
<void> (0) : __assert_fail ("Assignments[ValNo] != -1 && \"Bad recursion?\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2781, __PRETTY_FUNCTION__))
;
2782 return;
2783 }
2784 switch ((V.Resolution = analyzeValue(ValNo, Other))) {
2785 case CR_Erase:
2786 case CR_Merge:
2787 // Merge this ValNo into OtherVNI.
2788 assert(V.OtherVNI && "OtherVNI not assigned, can't merge.")((V.OtherVNI && "OtherVNI not assigned, can't merge."
) ? static_cast<void> (0) : __assert_fail ("V.OtherVNI && \"OtherVNI not assigned, can't merge.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2788, __PRETTY_FUNCTION__))
;
2789 assert(Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion")((Other.Vals[V.OtherVNI->id].isAnalyzed() && "Missing recursion"
) ? static_cast<void> (0) : __assert_fail ("Other.Vals[V.OtherVNI->id].isAnalyzed() && \"Missing recursion\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2789, __PRETTY_FUNCTION__))
;
2790 Assignments[ValNo] = Other.Assignments[V.OtherVNI->id];
2791 LLVM_DEBUG(dbgs() << "\t\tmerge " << printReg(Reg) << ':' << ValNo << '@'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tmerge " << printReg
(Reg) << ':' << ValNo << '@' << LR.getValNumInfo
(ValNo)->def << " into " << printReg(Other.Reg
) << ':' << V.OtherVNI->id << '@' <<
V.OtherVNI->def << " --> @" << NewVNInfo[Assignments
[ValNo]]->def << '\n'; } } while (false)
2792 << LR.getValNumInfo(ValNo)->def << " into "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tmerge " << printReg
(Reg) << ':' << ValNo << '@' << LR.getValNumInfo
(ValNo)->def << " into " << printReg(Other.Reg
) << ':' << V.OtherVNI->id << '@' <<
V.OtherVNI->def << " --> @" << NewVNInfo[Assignments
[ValNo]]->def << '\n'; } } while (false)
2793 << printReg(Other.Reg) << ':' << V.OtherVNI->id << '@'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tmerge " << printReg
(Reg) << ':' << ValNo << '@' << LR.getValNumInfo
(ValNo)->def << " into " << printReg(Other.Reg
) << ':' << V.OtherVNI->id << '@' <<
V.OtherVNI->def << " --> @" << NewVNInfo[Assignments
[ValNo]]->def << '\n'; } } while (false)
2794 << V.OtherVNI->def << " --> @"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tmerge " << printReg
(Reg) << ':' << ValNo << '@' << LR.getValNumInfo
(ValNo)->def << " into " << printReg(Other.Reg
) << ':' << V.OtherVNI->id << '@' <<
V.OtherVNI->def << " --> @" << NewVNInfo[Assignments
[ValNo]]->def << '\n'; } } while (false)
2795 << NewVNInfo[Assignments[ValNo]]->def << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tmerge " << printReg
(Reg) << ':' << ValNo << '@' << LR.getValNumInfo
(ValNo)->def << " into " << printReg(Other.Reg
) << ':' << V.OtherVNI->id << '@' <<
V.OtherVNI->def << " --> @" << NewVNInfo[Assignments
[ValNo]]->def << '\n'; } } while (false)
;
2796 break;
2797 case CR_Replace:
2798 case CR_Unresolved: {
2799 // The other value is going to be pruned if this join is successful.
2800 assert(V.OtherVNI && "OtherVNI not assigned, can't prune")((V.OtherVNI && "OtherVNI not assigned, can't prune")
? static_cast<void> (0) : __assert_fail ("V.OtherVNI && \"OtherVNI not assigned, can't prune\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2800, __PRETTY_FUNCTION__))
;
2801 Val &OtherV = Other.Vals[V.OtherVNI->id];
2802 // We cannot erase an IMPLICIT_DEF if we don't have valid values for all
2803 // its lanes.
2804 if (OtherV.ErasableImplicitDef &&
2805 TrackSubRegLiveness &&
2806 (OtherV.WriteLanes & ~V.ValidLanes).any()) {
2807 LLVM_DEBUG(dbgs() << "Cannot erase implicit_def with missing values\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Cannot erase implicit_def with missing values\n"
; } } while (false)
;
2808
2809 OtherV.ErasableImplicitDef = false;
2810 // The valid lanes written by the implicit_def were speculatively cleared
2811 // before, so make this more conservative. It may be better to track this,
2812 // I haven't found a testcase where it matters.
2813 OtherV.ValidLanes = LaneBitmask::getAll();
2814 }
2815
2816 OtherV.Pruned = true;
2817 LLVM_FALLTHROUGH[[gnu::fallthrough]];
2818 }
2819 default:
2820 // This value number needs to go in the final joined live range.
2821 Assignments[ValNo] = NewVNInfo.size();
2822 NewVNInfo.push_back(LR.getValNumInfo(ValNo));
2823 break;
2824 }
2825}
2826
2827bool JoinVals::mapValues(JoinVals &Other) {
2828 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2829 computeAssignment(i, Other);
2830 if (Vals[i].Resolution == CR_Impossible) {
2831 LLVM_DEBUG(dbgs() << "\t\tinterference at " << printReg(Reg) << ':' << ido { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tinterference at " <<
printReg(Reg) << ':' << i << '@' << LR
.getValNumInfo(i)->def << '\n'; } } while (false)
2832 << '@' << LR.getValNumInfo(i)->def << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tinterference at " <<
printReg(Reg) << ':' << i << '@' << LR
.getValNumInfo(i)->def << '\n'; } } while (false)
;
2833 return false;
2834 }
2835 }
2836 return true;
2837}
2838
2839bool JoinVals::
2840taintExtent(unsigned ValNo, LaneBitmask TaintedLanes, JoinVals &Other,
2841 SmallVectorImpl<std::pair<SlotIndex, LaneBitmask>> &TaintExtent) {
2842 VNInfo *VNI = LR.getValNumInfo(ValNo);
2843 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
2844 SlotIndex MBBEnd = Indexes->getMBBEndIdx(MBB);
2845
2846 // Scan Other.LR from VNI.def to MBBEnd.
2847 LiveInterval::iterator OtherI = Other.LR.find(VNI->def);
2848 assert(OtherI != Other.LR.end() && "No conflict?")((OtherI != Other.LR.end() && "No conflict?") ? static_cast
<void> (0) : __assert_fail ("OtherI != Other.LR.end() && \"No conflict?\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2848, __PRETTY_FUNCTION__))
;
2849 do {
2850 // OtherI is pointing to a tainted value. Abort the join if the tainted
2851 // lanes escape the block.
2852 SlotIndex End = OtherI->end;
2853 if (End >= MBBEnd) {
2854 LLVM_DEBUG(dbgs() << "\t\ttaints global " << printReg(Other.Reg) << ':'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\ttaints global " <<
printReg(Other.Reg) << ':' << OtherI->valno->
id << '@' << OtherI->start << '\n'; } } while
(false)
2855 << OtherI->valno->id << '@' << OtherI->start << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\ttaints global " <<
printReg(Other.Reg) << ':' << OtherI->valno->
id << '@' << OtherI->start << '\n'; } } while
(false)
;
2856 return false;
2857 }
2858 LLVM_DEBUG(dbgs() << "\t\ttaints local " << printReg(Other.Reg) << ':'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\ttaints local " << printReg
(Other.Reg) << ':' << OtherI->valno->id <<
'@' << OtherI->start << " to " << End <<
'\n'; } } while (false)
2859 << OtherI->valno->id << '@' << OtherI->start << " to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\ttaints local " << printReg
(Other.Reg) << ':' << OtherI->valno->id <<
'@' << OtherI->start << " to " << End <<
'\n'; } } while (false)
2860 << End << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\ttaints local " << printReg
(Other.Reg) << ':' << OtherI->valno->id <<
'@' << OtherI->start << " to " << End <<
'\n'; } } while (false)
;
2861 // A dead def is not a problem.
2862 if (End.isDead())
2863 break;
2864 TaintExtent.push_back(std::make_pair(End, TaintedLanes));
2865
2866 // Check for another def in the MBB.
2867 if (++OtherI == Other.LR.end() || OtherI->start >= MBBEnd)
2868 break;
2869
2870 // Lanes written by the new def are no longer tainted.
2871 const Val &OV = Other.Vals[OtherI->valno->id];
2872 TaintedLanes &= ~OV.WriteLanes;
2873 if (!OV.RedefVNI)
2874 break;
2875 } while (TaintedLanes.any());
2876 return true;
2877}
2878
2879bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx,
2880 LaneBitmask Lanes) const {
2881 if (MI.isDebugInstr())
2882 return false;
2883 for (const MachineOperand &MO : MI.operands()) {
2884 if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
2885 continue;
2886 if (!MO.readsReg())
2887 continue;
2888 unsigned S = TRI->composeSubRegIndices(SubIdx, MO.getSubReg());
2889 if ((Lanes & TRI->getSubRegIndexLaneMask(S)).any())
2890 return true;
2891 }
2892 return false;
2893}
2894
2895bool JoinVals::resolveConflicts(JoinVals &Other) {
2896 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2897 Val &V = Vals[i];
2898 assert(V.Resolution != CR_Impossible && "Unresolvable conflict")((V.Resolution != CR_Impossible && "Unresolvable conflict"
) ? static_cast<void> (0) : __assert_fail ("V.Resolution != CR_Impossible && \"Unresolvable conflict\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2898, __PRETTY_FUNCTION__))
;
2899 if (V.Resolution != CR_Unresolved)
2900 continue;
2901 LLVM_DEBUG(dbgs() << "\t\tconflict at " << printReg(Reg) << ':' << i << '@'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tconflict at " << printReg
(Reg) << ':' << i << '@' << LR.getValNumInfo
(i)->def << ' ' << PrintLaneMask(LaneMask) <<
'\n'; } } while (false)
2902 << LR.getValNumInfo(i)->defdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tconflict at " << printReg
(Reg) << ':' << i << '@' << LR.getValNumInfo
(i)->def << ' ' << PrintLaneMask(LaneMask) <<
'\n'; } } while (false)
2903 << ' ' << PrintLaneMask(LaneMask) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tconflict at " << printReg
(Reg) << ':' << i << '@' << LR.getValNumInfo
(i)->def << ' ' << PrintLaneMask(LaneMask) <<
'\n'; } } while (false)
;
2904 if (SubRangeJoin)
2905 return false;
2906
2907 ++NumLaneConflicts;
2908 assert(V.OtherVNI && "Inconsistent conflict resolution.")((V.OtherVNI && "Inconsistent conflict resolution.") ?
static_cast<void> (0) : __assert_fail ("V.OtherVNI && \"Inconsistent conflict resolution.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2908, __PRETTY_FUNCTION__))
;
2909 VNInfo *VNI = LR.getValNumInfo(i);
2910 const Val &OtherV = Other.Vals[V.OtherVNI->id];
2911
2912 // VNI is known to clobber some lanes in OtherVNI. If we go ahead with the
2913 // join, those lanes will be tainted with a wrong value. Get the extent of
2914 // the tainted lanes.
2915 LaneBitmask TaintedLanes = V.WriteLanes & OtherV.ValidLanes;
2916 SmallVector<std::pair<SlotIndex, LaneBitmask>, 8> TaintExtent;
2917 if (!taintExtent(i, TaintedLanes, Other, TaintExtent))
2918 // Tainted lanes would extend beyond the basic block.
2919 return false;
2920
2921 assert(!TaintExtent.empty() && "There should be at least one conflict.")((!TaintExtent.empty() && "There should be at least one conflict."
) ? static_cast<void> (0) : __assert_fail ("!TaintExtent.empty() && \"There should be at least one conflict.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2921, __PRETTY_FUNCTION__))
;
2922
2923 // Now look at the instructions from VNI->def to TaintExtent (inclusive).
2924 MachineBasicBlock *MBB = Indexes->getMBBFromIndex(VNI->def);
2925 MachineBasicBlock::iterator MI = MBB->begin();
2926 if (!VNI->isPHIDef()) {
2927 MI = Indexes->getInstructionFromIndex(VNI->def);
2928 // No need to check the instruction defining VNI for reads.
2929 ++MI;
2930 }
2931 assert(!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) &&((!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first
) && "Interference ends on VNI->def. Should have been handled earlier"
) ? static_cast<void> (0) : __assert_fail ("!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) && \"Interference ends on VNI->def. Should have been handled earlier\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2932, __PRETTY_FUNCTION__))
2932 "Interference ends on VNI->def. Should have been handled earlier")((!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first
) && "Interference ends on VNI->def. Should have been handled earlier"
) ? static_cast<void> (0) : __assert_fail ("!SlotIndex::isSameInstr(VNI->def, TaintExtent.front().first) && \"Interference ends on VNI->def. Should have been handled earlier\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2932, __PRETTY_FUNCTION__))
;
2933 MachineInstr *LastMI =
2934 Indexes->getInstructionFromIndex(TaintExtent.front().first);
2935 assert(LastMI && "Range must end at a proper instruction")((LastMI && "Range must end at a proper instruction")
? static_cast<void> (0) : __assert_fail ("LastMI && \"Range must end at a proper instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2935, __PRETTY_FUNCTION__))
;
2936 unsigned TaintNum = 0;
2937 while (true) {
2938 assert(MI != MBB->end() && "Bad LastMI")((MI != MBB->end() && "Bad LastMI") ? static_cast<
void> (0) : __assert_fail ("MI != MBB->end() && \"Bad LastMI\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2938, __PRETTY_FUNCTION__))
;
2939 if (usesLanes(*MI, Other.Reg, Other.SubIdx, TaintedLanes)) {
2940 LLVM_DEBUG(dbgs() << "\t\ttainted lanes used by: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\ttainted lanes used by: "
<< *MI; } } while (false)
;
2941 return false;
2942 }
2943 // LastMI is the last instruction to use the current value.
2944 if (&*MI == LastMI) {
2945 if (++TaintNum == TaintExtent.size())
2946 break;
2947 LastMI = Indexes->getInstructionFromIndex(TaintExtent[TaintNum].first);
2948 assert(LastMI && "Range must end at a proper instruction")((LastMI && "Range must end at a proper instruction")
? static_cast<void> (0) : __assert_fail ("LastMI && \"Range must end at a proper instruction\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 2948, __PRETTY_FUNCTION__))
;
2949 TaintedLanes = TaintExtent[TaintNum].second;
2950 }
2951 ++MI;
2952 }
2953
2954 // The tainted lanes are unused.
2955 V.Resolution = CR_Replace;
2956 ++NumLaneResolves;
2957 }
2958 return true;
2959}
2960
2961bool JoinVals::isPrunedValue(unsigned ValNo, JoinVals &Other) {
2962 Val &V = Vals[ValNo];
2963 if (V.Pruned || V.PrunedComputed)
2964 return V.Pruned;
2965
2966 if (V.Resolution != CR_Erase && V.Resolution != CR_Merge)
2967 return V.Pruned;
2968
2969 // Follow copies up the dominator tree and check if any intermediate value
2970 // has been pruned.
2971 V.PrunedComputed = true;
2972 V.Pruned = Other.isPrunedValue(V.OtherVNI->id, *this);
2973 return V.Pruned;
2974}
2975
2976void JoinVals::pruneValues(JoinVals &Other,
2977 SmallVectorImpl<SlotIndex> &EndPoints,
2978 bool changeInstrs) {
2979 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
2980 SlotIndex Def = LR.getValNumInfo(i)->def;
2981 switch (Vals[i].Resolution) {
2982 case CR_Keep:
2983 break;
2984 case CR_Replace: {
2985 // This value takes precedence over the value in Other.LR.
2986 LIS->pruneValue(Other.LR, Def, &EndPoints);
2987 // Check if we're replacing an IMPLICIT_DEF value. The IMPLICIT_DEF
2988 // instructions are only inserted to provide a live-out value for PHI
2989 // predecessors, so the instruction should simply go away once its value
2990 // has been replaced.
2991 Val &OtherV = Other.Vals[Vals[i].OtherVNI->id];
2992 bool EraseImpDef = OtherV.ErasableImplicitDef &&
2993 OtherV.Resolution == CR_Keep;
2994 if (!Def.isBlock()) {
2995 if (changeInstrs) {
2996 // Remove <def,read-undef> flags. This def is now a partial redef.
2997 // Also remove dead flags since the joined live range will
2998 // continue past this instruction.
2999 for (MachineOperand &MO :
3000 Indexes->getInstructionFromIndex(Def)->operands()) {
3001 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
3002 if (MO.getSubReg() != 0 && MO.isUndef() && !EraseImpDef)
3003 MO.setIsUndef(false);
3004 MO.setIsDead(false);
3005 }
3006 }
3007 }
3008 // This value will reach instructions below, but we need to make sure
3009 // the live range also reaches the instruction at Def.
3010 if (!EraseImpDef)
3011 EndPoints.push_back(Def);
3012 }
3013 LLVM_DEBUG(dbgs() << "\t\tpruned " << printReg(Other.Reg) << " at " << Defdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tpruned " << printReg
(Other.Reg) << " at " << Def << ": " <<
Other.LR << '\n'; } } while (false)
3014 << ": " << Other.LR << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tpruned " << printReg
(Other.Reg) << " at " << Def << ": " <<
Other.LR << '\n'; } } while (false)
;
3015 break;
3016 }
3017 case CR_Erase:
3018 case CR_Merge:
3019 if (isPrunedValue(i, Other)) {
3020 // This value is ultimately a copy of a pruned value in LR or Other.LR.
3021 // We can no longer trust the value mapping computed by
3022 // computeAssignment(), the value that was originally copied could have
3023 // been replaced.
3024 LIS->pruneValue(LR, Def, &EndPoints);
3025 LLVM_DEBUG(dbgs() << "\t\tpruned all of " << printReg(Reg) << " at "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tpruned all of " <<
printReg(Reg) << " at " << Def << ": " <<
LR << '\n'; } } while (false)
3026 << Def << ": " << LR << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tpruned all of " <<
printReg(Reg) << " at " << Def << ": " <<
LR << '\n'; } } while (false)
;
3027 }
3028 break;
3029 case CR_Unresolved:
3030 case CR_Impossible:
3031 llvm_unreachable("Unresolved conflicts")::llvm::llvm_unreachable_internal("Unresolved conflicts", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3031)
;
3032 }
3033 }
3034}
3035
3036/// Consider the following situation when coalescing the copy between
3037/// %31 and %45 at 800. (The vertical lines represent live range segments.)
3038///
3039/// Main range Subrange 0004 (sub2)
3040/// %31 %45 %31 %45
3041/// 544 %45 = COPY %28 + +
3042/// | v1 | v1
3043/// 560B bb.1: + +
3044/// 624 = %45.sub2 | v2 | v2
3045/// 800 %31 = COPY %45 + + + +
3046/// | v0 | v0
3047/// 816 %31.sub1 = ... + |
3048/// 880 %30 = COPY %31 | v1 +
3049/// 928 %45 = COPY %30 | + +
3050/// | | v0 | v0 <--+
3051/// 992B ; backedge -> bb.1 | + + |
3052/// 1040 = %31.sub0 + |
3053/// This value must remain
3054/// live-out!
3055///
3056/// Assuming that %31 is coalesced into %45, the copy at 928 becomes
3057/// redundant, since it copies the value from %45 back into it. The
3058/// conflict resolution for the main range determines that %45.v0 is
3059/// to be erased, which is ok since %31.v1 is identical to it.
3060/// The problem happens with the subrange for sub2: it has to be live
3061/// on exit from the block, but since 928 was actually a point of
3062/// definition of %45.sub2, %45.sub2 was not live immediately prior
3063/// to that definition. As a result, when 928 was erased, the value v0
3064/// for %45.sub2 was pruned in pruneSubRegValues. Consequently, an
3065/// IMPLICIT_DEF was inserted as a "backedge" definition for %45.sub2,
3066/// providing an incorrect value to the use at 624.
3067///
3068/// Since the main-range values %31.v1 and %45.v0 were proved to be
3069/// identical, the corresponding values in subranges must also be the
3070/// same. A redundant copy is removed because it's not needed, and not
3071/// because it copied an undefined value, so any liveness that originated
3072/// from that copy cannot disappear. When pruning a value that started
3073/// at the removed copy, the corresponding identical value must be
3074/// extended to replace it.
3075void JoinVals::pruneSubRegValues(LiveInterval &LI, LaneBitmask &ShrinkMask) {
3076 // Look for values being erased.
3077 bool DidPrune = false;
3078 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3079 Val &V = Vals[i];
3080 // We should trigger in all cases in which eraseInstrs() does something.
3081 // match what eraseInstrs() is doing, print a message so
3082 if (V.Resolution != CR_Erase &&
3083 (V.Resolution != CR_Keep || !V.ErasableImplicitDef || !V.Pruned))
3084 continue;
3085
3086 // Check subranges at the point where the copy will be removed.
3087 SlotIndex Def = LR.getValNumInfo(i)->def;
3088 SlotIndex OtherDef;
3089 if (V.Identical)
3090 OtherDef = V.OtherVNI->def;
3091
3092 // Print message so mismatches with eraseInstrs() can be diagnosed.
3093 LLVM_DEBUG(dbgs() << "\t\tExpecting instruction removal at " << Defdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tExpecting instruction removal at "
<< Def << '\n'; } } while (false)
3094 << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tExpecting instruction removal at "
<< Def << '\n'; } } while (false)
;
3095 for (LiveInterval::SubRange &S : LI.subranges()) {
3096 LiveQueryResult Q = S.Query(Def);
3097
3098 // If a subrange starts at the copy then an undefined value has been
3099 // copied and we must remove that subrange value as well.
3100 VNInfo *ValueOut = Q.valueOutOrDead();
3101 if (ValueOut != nullptr && (Q.valueIn() == nullptr ||
3102 (V.Identical && V.Resolution == CR_Erase &&
3103 ValueOut->def == Def))) {
3104 LLVM_DEBUG(dbgs() << "\t\tPrune sublane " << PrintLaneMask(S.LaneMask)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tPrune sublane " <<
PrintLaneMask(S.LaneMask) << " at " << Def <<
"\n"; } } while (false)
3105 << " at " << Def << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tPrune sublane " <<
PrintLaneMask(S.LaneMask) << " at " << Def <<
"\n"; } } while (false)
;
3106 SmallVector<SlotIndex,8> EndPoints;
3107 LIS->pruneValue(S, Def, &EndPoints);
3108 DidPrune = true;
3109 // Mark value number as unused.
3110 ValueOut->markUnused();
3111
3112 if (V.Identical && S.Query(OtherDef).valueOutOrDead()) {
3113 // If V is identical to V.OtherVNI (and S was live at OtherDef),
3114 // then we can't simply prune V from S. V needs to be replaced
3115 // with V.OtherVNI.
3116 LIS->extendToIndices(S, EndPoints);
3117 }
3118 continue;
3119 }
3120 // If a subrange ends at the copy, then a value was copied but only
3121 // partially used later. Shrink the subregister range appropriately.
3122 if (Q.valueIn() != nullptr && Q.valueOut() == nullptr) {
3123 LLVM_DEBUG(dbgs() << "\t\tDead uses at sublane "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tDead uses at sublane " <<
PrintLaneMask(S.LaneMask) << " at " << Def <<
"\n"; } } while (false)
3124 << PrintLaneMask(S.LaneMask) << " at " << Defdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tDead uses at sublane " <<
PrintLaneMask(S.LaneMask) << " at " << Def <<
"\n"; } } while (false)
3125 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tDead uses at sublane " <<
PrintLaneMask(S.LaneMask) << " at " << Def <<
"\n"; } } while (false)
;
3126 ShrinkMask |= S.LaneMask;
3127 }
3128 }
3129 }
3130 if (DidPrune)
3131 LI.removeEmptySubRanges();
3132}
3133
3134/// Check if any of the subranges of @p LI contain a definition at @p Def.
3135static bool isDefInSubRange(LiveInterval &LI, SlotIndex Def) {
3136 for (LiveInterval::SubRange &SR : LI.subranges()) {
3137 if (VNInfo *VNI = SR.Query(Def).valueOutOrDead())
3138 if (VNI->def == Def)
3139 return true;
3140 }
3141 return false;
3142}
3143
3144void JoinVals::pruneMainSegments(LiveInterval &LI, bool &ShrinkMainRange) {
3145 assert(&static_cast<LiveRange&>(LI) == &LR)((&static_cast<LiveRange&>(LI) == &LR) ? static_cast
<void> (0) : __assert_fail ("&static_cast<LiveRange&>(LI) == &LR"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3145, __PRETTY_FUNCTION__))
;
3146
3147 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3148 if (Vals[i].Resolution != CR_Keep)
3149 continue;
3150 VNInfo *VNI = LR.getValNumInfo(i);
3151 if (VNI->isUnused() || VNI->isPHIDef() || isDefInSubRange(LI, VNI->def))
3152 continue;
3153 Vals[i].Pruned = true;
3154 ShrinkMainRange = true;
3155 }
3156}
3157
3158void JoinVals::removeImplicitDefs() {
3159 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3160 Val &V = Vals[i];
3161 if (V.Resolution != CR_Keep || !V.ErasableImplicitDef || !V.Pruned)
3162 continue;
3163
3164 VNInfo *VNI = LR.getValNumInfo(i);
3165 VNI->markUnused();
3166 LR.removeValNo(VNI);
3167 }
3168}
3169
3170void JoinVals::eraseInstrs(SmallPtrSetImpl<MachineInstr*> &ErasedInstrs,
3171 SmallVectorImpl<Register> &ShrinkRegs,
3172 LiveInterval *LI) {
3173 for (unsigned i = 0, e = LR.getNumValNums(); i != e; ++i) {
3174 // Get the def location before markUnused() below invalidates it.
3175 VNInfo *VNI = LR.getValNumInfo(i);
3176 SlotIndex Def = VNI->def;
3177 switch (Vals[i].Resolution) {
3178 case CR_Keep: {
3179 // If an IMPLICIT_DEF value is pruned, it doesn't serve a purpose any
3180 // longer. The IMPLICIT_DEF instructions are only inserted by
3181 // PHIElimination to guarantee that all PHI predecessors have a value.
3182 if (!Vals[i].ErasableImplicitDef || !Vals[i].Pruned)
3183 break;
3184 // Remove value number i from LR.
3185 // For intervals with subranges, removing a segment from the main range
3186 // may require extending the previous segment: for each definition of
3187 // a subregister, there will be a corresponding def in the main range.
3188 // That def may fall in the middle of a segment from another subrange.
3189 // In such cases, removing this def from the main range must be
3190 // complemented by extending the main range to account for the liveness
3191 // of the other subrange.
3192 // The new end point of the main range segment to be extended.
3193 SlotIndex NewEnd;
3194 if (LI != nullptr) {
3195 LiveRange::iterator I = LR.FindSegmentContaining(Def);
3196 assert(I != LR.end())((I != LR.end()) ? static_cast<void> (0) : __assert_fail
("I != LR.end()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3196, __PRETTY_FUNCTION__))
;
3197 // Do not extend beyond the end of the segment being removed.
3198 // The segment may have been pruned in preparation for joining
3199 // live ranges.
3200 NewEnd = I->end;
3201 }
3202
3203 LR.removeValNo(VNI);
3204 // Note that this VNInfo is reused and still referenced in NewVNInfo,
3205 // make it appear like an unused value number.
3206 VNI->markUnused();
3207
3208 if (LI != nullptr && LI->hasSubRanges()) {
3209 assert(static_cast<LiveRange*>(LI) == &LR)((static_cast<LiveRange*>(LI) == &LR) ? static_cast
<void> (0) : __assert_fail ("static_cast<LiveRange*>(LI) == &LR"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3209, __PRETTY_FUNCTION__))
;
3210 // Determine the end point based on the subrange information:
3211 // minimum of (earliest def of next segment,
3212 // latest end point of containing segment)
3213 SlotIndex ED, LE;
3214 for (LiveInterval::SubRange &SR : LI->subranges()) {
3215 LiveRange::iterator I = SR.find(Def);
3216 if (I == SR.end())
3217 continue;
3218 if (I->start > Def)
3219 ED = ED.isValid() ? std::min(ED, I->start) : I->start;
3220 else
3221 LE = LE.isValid() ? std::max(LE, I->end) : I->end;
3222 }
3223 if (LE.isValid())
3224 NewEnd = std::min(NewEnd, LE);
3225 if (ED.isValid())
3226 NewEnd = std::min(NewEnd, ED);
3227
3228 // We only want to do the extension if there was a subrange that
3229 // was live across Def.
3230 if (LE.isValid()) {
3231 LiveRange::iterator S = LR.find(Def);
3232 if (S != LR.begin())
3233 std::prev(S)->end = NewEnd;
3234 }
3235 }
3236 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tremoved " << i <<
'@' << Def << ": " << LR << '\n'; if
(LI != nullptr) dbgs() << "\t\t LHS = " << *LI <<
'\n'; }; } } while (false)
3237 dbgs() << "\t\tremoved " << i << '@' << Def << ": " << LR << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tremoved " << i <<
'@' << Def << ": " << LR << '\n'; if
(LI != nullptr) dbgs() << "\t\t LHS = " << *LI <<
'\n'; }; } } while (false)
3238 if (LI != nullptr)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tremoved " << i <<
'@' << Def << ": " << LR << '\n'; if
(LI != nullptr) dbgs() << "\t\t LHS = " << *LI <<
'\n'; }; } } while (false)
3239 dbgs() << "\t\t LHS = " << *LI << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tremoved " << i <<
'@' << Def << ": " << LR << '\n'; if
(LI != nullptr) dbgs() << "\t\t LHS = " << *LI <<
'\n'; }; } } while (false)
3240 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\tremoved " << i <<
'@' << Def << ": " << LR << '\n'; if
(LI != nullptr) dbgs() << "\t\t LHS = " << *LI <<
'\n'; }; } } while (false)
;
3241 LLVM_FALLTHROUGH[[gnu::fallthrough]];
3242 }
3243
3244 case CR_Erase: {
3245 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
3246 assert(MI && "No instruction to erase")((MI && "No instruction to erase") ? static_cast<void
> (0) : __assert_fail ("MI && \"No instruction to erase\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3246, __PRETTY_FUNCTION__))
;
3247 if (MI->isCopy()) {
3248 Register Reg = MI->getOperand(1).getReg();
3249 if (Register::isVirtualRegister(Reg) && Reg != CP.getSrcReg() &&
3250 Reg != CP.getDstReg())
3251 ShrinkRegs.push_back(Reg);
3252 }
3253 ErasedInstrs.insert(MI);
3254 LLVM_DEBUG(dbgs() << "\t\terased:\t" << Def << '\t' << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\terased:\t" << Def <<
'\t' << *MI; } } while (false)
;
3255 LIS->RemoveMachineInstrFromMaps(*MI);
3256 MI->eraseFromParent();
3257 break;
3258 }
3259 default:
3260 break;
3261 }
3262 }
3263}
3264
3265void RegisterCoalescer::joinSubRegRanges(LiveRange &LRange, LiveRange &RRange,
3266 LaneBitmask LaneMask,
3267 const CoalescerPair &CP) {
3268 SmallVector<VNInfo*, 16> NewVNInfo;
3269 JoinVals RHSVals(RRange, CP.getSrcReg(), CP.getSrcIdx(), LaneMask,
3270 NewVNInfo, CP, LIS, TRI, true, true);
3271 JoinVals LHSVals(LRange, CP.getDstReg(), CP.getDstIdx(), LaneMask,
3272 NewVNInfo, CP, LIS, TRI, true, true);
3273
3274 // Compute NewVNInfo and resolve conflicts (see also joinVirtRegs())
3275 // We should be able to resolve all conflicts here as we could successfully do
3276 // it on the mainrange already. There is however a problem when multiple
3277 // ranges get mapped to the "overflow" lane mask bit which creates unexpected
3278 // interferences.
3279 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals)) {
3280 // We already determined that it is legal to merge the intervals, so this
3281 // should never fail.
3282 llvm_unreachable("*** Couldn't join subrange!\n")::llvm::llvm_unreachable_internal("*** Couldn't join subrange!\n"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3282)
;
3283 }
3284 if (!LHSVals.resolveConflicts(RHSVals) ||
3285 !RHSVals.resolveConflicts(LHSVals)) {
3286 // We already determined that it is legal to merge the intervals, so this
3287 // should never fail.
3288 llvm_unreachable("*** Couldn't join subrange!\n")::llvm::llvm_unreachable_internal("*** Couldn't join subrange!\n"
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3288)
;
3289 }
3290
3291 // The merging algorithm in LiveInterval::join() can't handle conflicting
3292 // value mappings, so we need to remove any live ranges that overlap a
3293 // CR_Replace resolution. Collect a set of end points that can be used to
3294 // restore the live range after joining.
3295 SmallVector<SlotIndex, 8> EndPoints;
3296 LHSVals.pruneValues(RHSVals, EndPoints, false);
3297 RHSVals.pruneValues(LHSVals, EndPoints, false);
3298
3299 LHSVals.removeImplicitDefs();
3300 RHSVals.removeImplicitDefs();
3301
3302 LRange.verify();
3303 RRange.verify();
3304
3305 // Join RRange into LHS.
3306 LRange.join(RRange, LHSVals.getAssignments(), RHSVals.getAssignments(),
3307 NewVNInfo);
3308
3309 LLVM_DEBUG(dbgs() << "\t\tjoined lanes: " << PrintLaneMask(LaneMask)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tjoined lanes: " <<
PrintLaneMask(LaneMask) << ' ' << LRange <<
"\n"; } } while (false)
3310 << ' ' << LRange << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tjoined lanes: " <<
PrintLaneMask(LaneMask) << ' ' << LRange <<
"\n"; } } while (false)
;
3311 if (EndPoints.empty())
3312 return;
3313
3314 // Recompute the parts of the live range we had to remove because of
3315 // CR_Replace conflicts.
3316 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LRange << '\n'; }; } } while (false)
3317 dbgs() << "\t\trestoring liveness to " << EndPoints.size() << " points: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LRange << '\n'; }; } } while (false)
3318 for (unsigned i = 0, n = EndPoints.size(); i != n; ++i) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LRange << '\n'; }; } } while (false)
3319 dbgs() << EndPoints[i];do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LRange << '\n'; }; } } while (false)
3320 if (i != n-1)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LRange << '\n'; }; } } while (false)
3321 dbgs() << ',';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LRange << '\n'; }; } } while (false)
3322 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LRange << '\n'; }; } } while (false)
3323 dbgs() << ": " << LRange << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LRange << '\n'; }; } } while (false)
3324 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LRange << '\n'; }; } } while (false)
;
3325 LIS->extendToIndices(LRange, EndPoints);
3326}
3327
3328void RegisterCoalescer::mergeSubRangeInto(LiveInterval &LI,
3329 const LiveRange &ToMerge,
3330 LaneBitmask LaneMask,
3331 CoalescerPair &CP,
3332 unsigned ComposeSubRegIdx) {
3333 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
3334 LI.refineSubRanges(
3335 Allocator, LaneMask,
3336 [this, &Allocator, &ToMerge, &CP](LiveInterval::SubRange &SR) {
3337 if (SR.empty()) {
3338 SR.assign(ToMerge, Allocator);
3339 } else {
3340 // joinSubRegRange() destroys the merged range, so we need a copy.
3341 LiveRange RangeCopy(ToMerge, Allocator);
3342 joinSubRegRanges(SR, RangeCopy, SR.LaneMask, CP);
3343 }
3344 },
3345 *LIS->getSlotIndexes(), *TRI, ComposeSubRegIdx);
3346}
3347
3348bool RegisterCoalescer::isHighCostLiveInterval(LiveInterval &LI) {
3349 if (LI.valnos.size() < LargeIntervalSizeThreshold)
3350 return false;
3351 auto &Counter = LargeLIVisitCounter[LI.reg()];
3352 if (Counter < LargeIntervalFreqThreshold) {
3353 Counter++;
3354 return false;
3355 }
3356 return true;
3357}
3358
3359bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
3360 SmallVector<VNInfo*, 16> NewVNInfo;
3361 LiveInterval &RHS = LIS->getInterval(CP.getSrcReg());
3362 LiveInterval &LHS = LIS->getInterval(CP.getDstReg());
3363 bool TrackSubRegLiveness = MRI->shouldTrackSubRegLiveness(*CP.getNewRC());
3364 JoinVals RHSVals(RHS, CP.getSrcReg(), CP.getSrcIdx(), LaneBitmask::getNone(),
3365 NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness);
3366 JoinVals LHSVals(LHS, CP.getDstReg(), CP.getDstIdx(), LaneBitmask::getNone(),
3367 NewVNInfo, CP, LIS, TRI, false, TrackSubRegLiveness);
3368
3369 LLVM_DEBUG(dbgs() << "\t\tRHS = " << RHS << "\n\t\tLHS = " << LHS << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tRHS = " << RHS <<
"\n\t\tLHS = " << LHS << '\n'; } } while (false)
;
3370
3371 if (isHighCostLiveInterval(LHS) || isHighCostLiveInterval(RHS))
3372 return false;
3373
3374 // First compute NewVNInfo and the simple value mappings.
3375 // Detect impossible conflicts early.
3376 if (!LHSVals.mapValues(RHSVals) || !RHSVals.mapValues(LHSVals))
3377 return false;
3378
3379 // Some conflicts can only be resolved after all values have been mapped.
3380 if (!LHSVals.resolveConflicts(RHSVals) || !RHSVals.resolveConflicts(LHSVals))
3381 return false;
3382
3383 // All clear, the live ranges can be merged.
3384 if (RHS.hasSubRanges() || LHS.hasSubRanges()) {
3385 BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator();
3386
3387 // Transform lanemasks from the LHS to masks in the coalesced register and
3388 // create initial subranges if necessary.
3389 unsigned DstIdx = CP.getDstIdx();
3390 if (!LHS.hasSubRanges()) {
3391 LaneBitmask Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask()
3392 : TRI->getSubRegIndexLaneMask(DstIdx);
3393 // LHS must support subregs or we wouldn't be in this codepath.
3394 assert(Mask.any())((Mask.any()) ? static_cast<void> (0) : __assert_fail (
"Mask.any()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3394, __PRETTY_FUNCTION__))
;
3395 LHS.createSubRangeFrom(Allocator, Mask, LHS);
3396 } else if (DstIdx != 0) {
3397 // Transform LHS lanemasks to new register class if necessary.
3398 for (LiveInterval::SubRange &R : LHS.subranges()) {
3399 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask);
3400 R.LaneMask = Mask;
3401 }
3402 }
3403 LLVM_DEBUG(dbgs() << "\t\tLHST = " << printReg(CP.getDstReg()) << ' ' << LHSdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tLHST = " << printReg
(CP.getDstReg()) << ' ' << LHS << '\n'; } }
while (false)
3404 << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t\tLHST = " << printReg
(CP.getDstReg()) << ' ' << LHS << '\n'; } }
while (false)
;
3405
3406 // Determine lanemasks of RHS in the coalesced register and merge subranges.
3407 unsigned SrcIdx = CP.getSrcIdx();
3408 if (!RHS.hasSubRanges()) {
3409 LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask()
3410 : TRI->getSubRegIndexLaneMask(SrcIdx);
3411 mergeSubRangeInto(LHS, RHS, Mask, CP, DstIdx);
3412 } else {
3413 // Pair up subranges and merge.
3414 for (LiveInterval::SubRange &R : RHS.subranges()) {
3415 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask);
3416 mergeSubRangeInto(LHS, R, Mask, CP, DstIdx);
3417 }
3418 }
3419 LLVM_DEBUG(dbgs() << "\tJoined SubRanges " << LHS << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tJoined SubRanges " <<
LHS << "\n"; } } while (false)
;
3420
3421 // Pruning implicit defs from subranges may result in the main range
3422 // having stale segments.
3423 LHSVals.pruneMainSegments(LHS, ShrinkMainRange);
3424
3425 LHSVals.pruneSubRegValues(LHS, ShrinkMask);
3426 RHSVals.pruneSubRegValues(LHS, ShrinkMask);
3427 }
3428
3429 // The merging algorithm in LiveInterval::join() can't handle conflicting
3430 // value mappings, so we need to remove any live ranges that overlap a
3431 // CR_Replace resolution. Collect a set of end points that can be used to
3432 // restore the live range after joining.
3433 SmallVector<SlotIndex, 8> EndPoints;
3434 LHSVals.pruneValues(RHSVals, EndPoints, true);
3435 RHSVals.pruneValues(LHSVals, EndPoints, true);
3436
3437 // Erase COPY and IMPLICIT_DEF instructions. This may cause some external
3438 // registers to require trimming.
3439 SmallVector<Register, 8> ShrinkRegs;
3440 LHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs, &LHS);
3441 RHSVals.eraseInstrs(ErasedInstrs, ShrinkRegs);
3442 while (!ShrinkRegs.empty())
3443 shrinkToUses(&LIS->getInterval(ShrinkRegs.pop_back_val()));
3444
3445 // Scan and mark undef any DBG_VALUEs that would refer to a different value.
3446 checkMergingChangesDbgValues(CP, LHS, LHSVals, RHS, RHSVals);
3447
3448 // Join RHS into LHS.
3449 LHS.join(RHS, LHSVals.getAssignments(), RHSVals.getAssignments(), NewVNInfo);
3450
3451 // Kill flags are going to be wrong if the live ranges were overlapping.
3452 // Eventually, we should simply clear all kill flags when computing live
3453 // ranges. They are reinserted after register allocation.
3454 MRI->clearKillFlags(LHS.reg());
3455 MRI->clearKillFlags(RHS.reg());
3456
3457 if (!EndPoints.empty()) {
3458 // Recompute the parts of the live range we had to remove because of
3459 // CR_Replace conflicts.
3460 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LHS << '\n'; }; } } while (false)
3461 dbgs() << "\t\trestoring liveness to " << EndPoints.size() << " points: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LHS << '\n'; }; } } while (false)
3462 for (unsigned i = 0, n = EndPoints.size(); i != n; ++i) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LHS << '\n'; }; } } while (false)
3463 dbgs() << EndPoints[i];do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LHS << '\n'; }; } } while (false)
3464 if (i != n-1)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LHS << '\n'; }; } } while (false)
3465 dbgs() << ',';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LHS << '\n'; }; } } while (false)
3466 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LHS << '\n'; }; } } while (false)
3467 dbgs() << ": " << LHS << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LHS << '\n'; }; } } while (false)
3468 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\t\trestoring liveness to "
<< EndPoints.size() << " points: "; for (unsigned
i = 0, n = EndPoints.size(); i != n; ++i) { dbgs() << EndPoints
[i]; if (i != n-1) dbgs() << ','; } dbgs() << ": "
<< LHS << '\n'; }; } } while (false)
;
3469 LIS->extendToIndices((LiveRange&)LHS, EndPoints);
3470 }
3471
3472 return true;
3473}
3474
3475bool RegisterCoalescer::joinIntervals(CoalescerPair &CP) {
3476 return CP.isPhys() ? joinReservedPhysReg(CP) : joinVirtRegs(CP);
3477}
3478
3479void RegisterCoalescer::buildVRegToDbgValueMap(MachineFunction &MF)
3480{
3481 const SlotIndexes &Slots = *LIS->getSlotIndexes();
3482 SmallVector<MachineInstr *, 8> ToInsert;
3483
3484 // After collecting a block of DBG_VALUEs into ToInsert, enter them into the
3485 // vreg => DbgValueLoc map.
3486 auto CloseNewDVRange = [this, &ToInsert](SlotIndex Slot) {
3487 for (auto *X : ToInsert)
3488 DbgVRegToValues[X->getDebugOperand(0).getReg()].push_back({Slot, X});
3489
3490 ToInsert.clear();
3491 };
3492
3493 // Iterate over all instructions, collecting them into the ToInsert vector.
3494 // Once a non-debug instruction is found, record the slot index of the
3495 // collected DBG_VALUEs.
3496 for (auto &MBB : MF) {
3497 SlotIndex CurrentSlot = Slots.getMBBStartIdx(&MBB);
3498
3499 for (auto &MI : MBB) {
3500 if (MI.isDebugValue() && MI.getDebugOperand(0).isReg() &&
3501 MI.getDebugOperand(0).getReg().isVirtual()) {
3502 ToInsert.push_back(&MI);
3503 } else if (!MI.isDebugInstr()) {
3504 CurrentSlot = Slots.getInstructionIndex(MI);
3505 CloseNewDVRange(CurrentSlot);
3506 }
3507 }
3508
3509 // Close range of DBG_VALUEs at the end of blocks.
3510 CloseNewDVRange(Slots.getMBBEndIdx(&MBB));
3511 }
3512
3513 // Sort all DBG_VALUEs we've seen by slot number.
3514 for (auto &Pair : DbgVRegToValues)
3515 llvm::sort(Pair.second);
3516}
3517
3518void RegisterCoalescer::checkMergingChangesDbgValues(CoalescerPair &CP,
3519 LiveRange &LHS,
3520 JoinVals &LHSVals,
3521 LiveRange &RHS,
3522 JoinVals &RHSVals) {
3523 auto ScanForDstReg = [&](unsigned Reg) {
3524 checkMergingChangesDbgValuesImpl(Reg, RHS, LHS, LHSVals);
3525 };
3526
3527 auto ScanForSrcReg = [&](unsigned Reg) {
3528 checkMergingChangesDbgValuesImpl(Reg, LHS, RHS, RHSVals);
3529 };
3530
3531 // Scan for potentially unsound DBG_VALUEs: examine first the register number
3532 // Reg, and then any other vregs that may have been merged into it.
3533 auto PerformScan = [this](unsigned Reg, std::function<void(unsigned)> Func) {
3534 Func(Reg);
3535 if (DbgMergedVRegNums.count(Reg))
3536 for (unsigned X : DbgMergedVRegNums[Reg])
3537 Func(X);
3538 };
3539
3540 // Scan for unsound updates of both the source and destination register.
3541 PerformScan(CP.getSrcReg(), ScanForSrcReg);
3542 PerformScan(CP.getDstReg(), ScanForDstReg);
3543}
3544
3545void RegisterCoalescer::checkMergingChangesDbgValuesImpl(unsigned Reg,
3546 LiveRange &OtherLR,
3547 LiveRange &RegLR,
3548 JoinVals &RegVals) {
3549 // Are there any DBG_VALUEs to examine?
3550 auto VRegMapIt = DbgVRegToValues.find(Reg);
3551 if (VRegMapIt == DbgVRegToValues.end())
3552 return;
3553
3554 auto &DbgValueSet = VRegMapIt->second;
3555 auto DbgValueSetIt = DbgValueSet.begin();
3556 auto SegmentIt = OtherLR.begin();
3557
3558 bool LastUndefResult = false;
3559 SlotIndex LastUndefIdx;
3560
3561 // If the "Other" register is live at a slot Idx, test whether Reg can
3562 // safely be merged with it, or should be marked undef.
3563 auto ShouldUndef = [&RegVals, &RegLR, &LastUndefResult,
3564 &LastUndefIdx](SlotIndex Idx) -> bool {
3565 // Our worst-case performance typically happens with asan, causing very
3566 // many DBG_VALUEs of the same location. Cache a copy of the most recent
3567 // result for this edge-case.
3568 if (LastUndefIdx == Idx)
3569 return LastUndefResult;
3570
3571 // If the other range was live, and Reg's was not, the register coalescer
3572 // will not have tried to resolve any conflicts. We don't know whether
3573 // the DBG_VALUE will refer to the same value number, so it must be made
3574 // undef.
3575 auto OtherIt = RegLR.find(Idx);
3576 if (OtherIt == RegLR.end())
3577 return true;
3578
3579 // Both the registers were live: examine the conflict resolution record for
3580 // the value number Reg refers to. CR_Keep meant that this value number
3581 // "won" and the merged register definitely refers to that value. CR_Erase
3582 // means the value number was a redundant copy of the other value, which
3583 // was coalesced and Reg deleted. It's safe to refer to the other register
3584 // (which will be the source of the copy).
3585 auto Resolution = RegVals.getResolution(OtherIt->valno->id);
3586 LastUndefResult = Resolution != JoinVals::CR_Keep &&
3587 Resolution != JoinVals::CR_Erase;
3588 LastUndefIdx = Idx;
3589 return LastUndefResult;
3590 };
3591
3592 // Iterate over both the live-range of the "Other" register, and the set of
3593 // DBG_VALUEs for Reg at the same time. Advance whichever one has the lowest
3594 // slot index. This relies on the DbgValueSet being ordered.
3595 while (DbgValueSetIt != DbgValueSet.end() && SegmentIt != OtherLR.end()) {
3596 if (DbgValueSetIt->first < SegmentIt->end) {
3597 // "Other" is live and there is a DBG_VALUE of Reg: test if we should
3598 // set it undef.
3599 if (DbgValueSetIt->first >= SegmentIt->start &&
3600 DbgValueSetIt->second->getDebugOperand(0).getReg() != 0 &&
3601 ShouldUndef(DbgValueSetIt->first)) {
3602 // Mark undef, erase record of this DBG_VALUE to avoid revisiting.
3603 DbgValueSetIt->second->setDebugValueUndef();
3604 continue;
3605 }
3606 ++DbgValueSetIt;
3607 } else {
3608 ++SegmentIt;
3609 }
3610 }
3611}
3612
3613namespace {
3614
3615/// Information concerning MBB coalescing priority.
3616struct MBBPriorityInfo {
3617 MachineBasicBlock *MBB;
3618 unsigned Depth;
3619 bool IsSplit;
3620
3621 MBBPriorityInfo(MachineBasicBlock *mbb, unsigned depth, bool issplit)
3622 : MBB(mbb), Depth(depth), IsSplit(issplit) {}
3623};
3624
3625} // end anonymous namespace
3626
3627/// C-style comparator that sorts first based on the loop depth of the basic
3628/// block (the unsigned), and then on the MBB number.
3629///
3630/// EnableGlobalCopies assumes that the primary sort key is loop depth.
3631static int compareMBBPriority(const MBBPriorityInfo *LHS,
3632 const MBBPriorityInfo *RHS) {
3633 // Deeper loops first
3634 if (LHS->Depth != RHS->Depth)
3635 return LHS->Depth > RHS->Depth ? -1 : 1;
3636
3637 // Try to unsplit critical edges next.
3638 if (LHS->IsSplit != RHS->IsSplit)
3639 return LHS->IsSplit ? -1 : 1;
3640
3641 // Prefer blocks that are more connected in the CFG. This takes care of
3642 // the most difficult copies first while intervals are short.
3643 unsigned cl = LHS->MBB->pred_size() + LHS->MBB->succ_size();
3644 unsigned cr = RHS->MBB->pred_size() + RHS->MBB->succ_size();
3645 if (cl != cr)
3646 return cl > cr ? -1 : 1;
3647
3648 // As a last resort, sort by block number.
3649 return LHS->MBB->getNumber() < RHS->MBB->getNumber() ? -1 : 1;
3650}
3651
3652/// \returns true if the given copy uses or defines a local live range.
3653static bool isLocalCopy(MachineInstr *Copy, const LiveIntervals *LIS) {
3654 if (!Copy->isCopy())
3655 return false;
3656
3657 if (Copy->getOperand(1).isUndef())
3658 return false;
3659
3660 Register SrcReg = Copy->getOperand(1).getReg();
3661 Register DstReg = Copy->getOperand(0).getReg();
3662 if (Register::isPhysicalRegister(SrcReg) ||
3663 Register::isPhysicalRegister(DstReg))
3664 return false;
3665
3666 return LIS->intervalIsInOneMBB(LIS->getInterval(SrcReg))
3667 || LIS->intervalIsInOneMBB(LIS->getInterval(DstReg));
3668}
3669
3670void RegisterCoalescer::lateLiveIntervalUpdate() {
3671 for (unsigned reg : ToBeUpdated) {
3672 if (!LIS->hasInterval(reg))
3673 continue;
3674 LiveInterval &LI = LIS->getInterval(reg);
3675 shrinkToUses(&LI, &DeadDefs);
3676 if (!DeadDefs.empty())
3677 eliminateDeadDefs();
3678 }
3679 ToBeUpdated.clear();
3680}
3681
3682bool RegisterCoalescer::
3683copyCoalesceWorkList(MutableArrayRef<MachineInstr*> CurrList) {
3684 bool Progress = false;
3685 for (unsigned i = 0, e = CurrList.size(); i != e; ++i) {
3686 if (!CurrList[i])
3687 continue;
3688 // Skip instruction pointers that have already been erased, for example by
3689 // dead code elimination.
3690 if (ErasedInstrs.count(CurrList[i])) {
3691 CurrList[i] = nullptr;
3692 continue;
3693 }
3694 bool Again = false;
3695 bool Success = joinCopy(CurrList[i], Again);
3696 Progress |= Success;
3697 if (Success || !Again)
3698 CurrList[i] = nullptr;
3699 }
3700 return Progress;
3701}
3702
3703/// Check if DstReg is a terminal node.
3704/// I.e., it does not have any affinity other than \p Copy.
3705static bool isTerminalReg(unsigned DstReg, const MachineInstr &Copy,
3706 const MachineRegisterInfo *MRI) {
3707 assert(Copy.isCopyLike())((Copy.isCopyLike()) ? static_cast<void> (0) : __assert_fail
("Copy.isCopyLike()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3707, __PRETTY_FUNCTION__))
;
3708 // Check if the destination of this copy as any other affinity.
3709 for (const MachineInstr &MI : MRI->reg_nodbg_instructions(DstReg))
3710 if (&MI != &Copy && MI.isCopyLike())
3711 return false;
3712 return true;
3713}
3714
3715bool RegisterCoalescer::applyTerminalRule(const MachineInstr &Copy) const {
3716 assert(Copy.isCopyLike())((Copy.isCopyLike()) ? static_cast<void> (0) : __assert_fail
("Copy.isCopyLike()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3716, __PRETTY_FUNCTION__))
;
3717 if (!UseTerminalRule)
3718 return false;
3719 unsigned DstReg, DstSubReg, SrcReg, SrcSubReg;
3720 if (!isMoveInstr(*TRI, &Copy, SrcReg, DstReg, SrcSubReg, DstSubReg))
3721 return false;
3722 // Check if the destination of this copy has any other affinity.
3723 if (Register::isPhysicalRegister(DstReg) ||
3724 // If SrcReg is a physical register, the copy won't be coalesced.
3725 // Ignoring it may have other side effect (like missing
3726 // rematerialization). So keep it.
3727 Register::isPhysicalRegister(SrcReg) || !isTerminalReg(DstReg, Copy, MRI))
3728 return false;
3729
3730 // DstReg is a terminal node. Check if it interferes with any other
3731 // copy involving SrcReg.
3732 const MachineBasicBlock *OrigBB = Copy.getParent();
3733 const LiveInterval &DstLI = LIS->getInterval(DstReg);
3734 for (const MachineInstr &MI : MRI->reg_nodbg_instructions(SrcReg)) {
3735 // Technically we should check if the weight of the new copy is
3736 // interesting compared to the other one and update the weight
3737 // of the copies accordingly. However, this would only work if
3738 // we would gather all the copies first then coalesce, whereas
3739 // right now we interleave both actions.
3740 // For now, just consider the copies that are in the same block.
3741 if (&MI == &Copy || !MI.isCopyLike() || MI.getParent() != OrigBB)
3742 continue;
3743 unsigned OtherReg, OtherSubReg, OtherSrcReg, OtherSrcSubReg;
3744 if (!isMoveInstr(*TRI, &Copy, OtherSrcReg, OtherReg, OtherSrcSubReg,
3745 OtherSubReg))
3746 return false;
3747 if (OtherReg == SrcReg)
3748 OtherReg = OtherSrcReg;
3749 // Check if OtherReg is a non-terminal.
3750 if (Register::isPhysicalRegister(OtherReg) ||
3751 isTerminalReg(OtherReg, MI, MRI))
3752 continue;
3753 // Check that OtherReg interfere with DstReg.
3754 if (LIS->getInterval(OtherReg).overlaps(DstLI)) {
3755 LLVM_DEBUG(dbgs() << "Apply terminal rule for: " << printReg(DstReg)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Apply terminal rule for: " <<
printReg(DstReg) << '\n'; } } while (false)
3756 << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Apply terminal rule for: " <<
printReg(DstReg) << '\n'; } } while (false)
;
3757 return true;
3758 }
3759 }
3760 return false;
3761}
3762
3763void
3764RegisterCoalescer::copyCoalesceInMBB(MachineBasicBlock *MBB) {
3765 LLVM_DEBUG(dbgs() << MBB->getName() << ":\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << MBB->getName() << ":\n"
; } } while (false)
;
3766
3767 // Collect all copy-like instructions in MBB. Don't start coalescing anything
3768 // yet, it might invalidate the iterator.
3769 const unsigned PrevSize = WorkList.size();
3770 if (JoinGlobalCopies) {
3771 SmallVector<MachineInstr*, 2> LocalTerminals;
3772 SmallVector<MachineInstr*, 2> GlobalTerminals;
3773 // Coalesce copies bottom-up to coalesce local defs before local uses. They
3774 // are not inherently easier to resolve, but slightly preferable until we
3775 // have local live range splitting. In particular this is required by
3776 // cmp+jmp macro fusion.
3777 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
3778 MII != E; ++MII) {
3779 if (!MII->isCopyLike())
3780 continue;
3781 bool ApplyTerminalRule = applyTerminalRule(*MII);
3782 if (isLocalCopy(&(*MII), LIS)) {
3783 if (ApplyTerminalRule)
3784 LocalTerminals.push_back(&(*MII));
3785 else
3786 LocalWorkList.push_back(&(*MII));
3787 } else {
3788 if (ApplyTerminalRule)
3789 GlobalTerminals.push_back(&(*MII));
3790 else
3791 WorkList.push_back(&(*MII));
3792 }
3793 }
3794 // Append the copies evicted by the terminal rule at the end of the list.
3795 LocalWorkList.append(LocalTerminals.begin(), LocalTerminals.end());
3796 WorkList.append(GlobalTerminals.begin(), GlobalTerminals.end());
3797 }
3798 else {
3799 SmallVector<MachineInstr*, 2> Terminals;
3800 for (MachineInstr &MII : *MBB)
3801 if (MII.isCopyLike()) {
3802 if (applyTerminalRule(MII))
3803 Terminals.push_back(&MII);
3804 else
3805 WorkList.push_back(&MII);
3806 }
3807 // Append the copies evicted by the terminal rule at the end of the list.
3808 WorkList.append(Terminals.begin(), Terminals.end());
3809 }
3810 // Try coalescing the collected copies immediately, and remove the nulls.
3811 // This prevents the WorkList from getting too large since most copies are
3812 // joinable on the first attempt.
3813 MutableArrayRef<MachineInstr*>
3814 CurrList(WorkList.begin() + PrevSize, WorkList.end());
3815 if (copyCoalesceWorkList(CurrList))
3816 WorkList.erase(std::remove(WorkList.begin() + PrevSize, WorkList.end(),
3817 nullptr), WorkList.end());
3818}
3819
3820void RegisterCoalescer::coalesceLocals() {
3821 copyCoalesceWorkList(LocalWorkList);
3822 for (unsigned j = 0, je = LocalWorkList.size(); j != je; ++j) {
3823 if (LocalWorkList[j])
3824 WorkList.push_back(LocalWorkList[j]);
3825 }
3826 LocalWorkList.clear();
3827}
3828
3829void RegisterCoalescer::joinAllIntervals() {
3830 LLVM_DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "********** JOINING INTERVALS ***********\n"
; } } while (false)
;
3831 assert(WorkList.empty() && LocalWorkList.empty() && "Old data still around.")((WorkList.empty() && LocalWorkList.empty() &&
"Old data still around.") ? static_cast<void> (0) : __assert_fail
("WorkList.empty() && LocalWorkList.empty() && \"Old data still around.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3831, __PRETTY_FUNCTION__))
;
3832
3833 std::vector<MBBPriorityInfo> MBBs;
3834 MBBs.reserve(MF->size());
3835 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
3836 MachineBasicBlock *MBB = &*I;
3837 MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
3838 JoinSplitEdges && isSplitEdge(MBB)));
3839 }
3840 array_pod_sort(MBBs.begin(), MBBs.end(), compareMBBPriority);
3841
3842 // Coalesce intervals in MBB priority order.
3843 unsigned CurrDepth = std::numeric_limits<unsigned>::max();
3844 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
3845 // Try coalescing the collected local copies for deeper loops.
3846 if (JoinGlobalCopies && MBBs[i].Depth < CurrDepth) {
3847 coalesceLocals();
3848 CurrDepth = MBBs[i].Depth;
3849 }
3850 copyCoalesceInMBB(MBBs[i].MBB);
3851 }
3852 lateLiveIntervalUpdate();
3853 coalesceLocals();
3854
3855 // Joining intervals can allow other intervals to be joined. Iteratively join
3856 // until we make no progress.
3857 while (copyCoalesceWorkList(WorkList))
3858 /* empty */ ;
3859 lateLiveIntervalUpdate();
3860}
3861
3862void RegisterCoalescer::releaseMemory() {
3863 ErasedInstrs.clear();
3864 WorkList.clear();
3865 DeadDefs.clear();
3866 InflateRegs.clear();
3867 LargeLIVisitCounter.clear();
3868}
3869
3870bool RegisterCoalescer::runOnMachineFunction(MachineFunction &fn) {
3871 LLVM_DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
<< "********** Function: " << fn.getName() <<
'\n'; } } while (false)
3872 << "********** Function: " << fn.getName() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
<< "********** Function: " << fn.getName() <<
'\n'; } } while (false)
;
3873
3874 // Variables changed between a setjmp and a longjump can have undefined value
3875 // after the longjmp. This behaviour can be observed if such a variable is
3876 // spilled, so longjmp won't restore the value in the spill slot.
3877 // RegisterCoalescer should not run in functions with a setjmp to avoid
3878 // merging such undefined variables with predictable ones.
3879 //
3880 // TODO: Could specifically disable coalescing registers live across setjmp
3881 // calls
3882 if (fn.exposesReturnsTwice()) {
3883 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "* Skipped as it exposes funcions that returns twice.\n"
; } } while (false)
3884 dbgs() << "* Skipped as it exposes funcions that returns twice.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "* Skipped as it exposes funcions that returns twice.\n"
; } } while (false)
;
3885 return false;
3886 }
3887
3888 MF = &fn;
3889 MRI = &fn.getRegInfo();
3890 const TargetSubtargetInfo &STI = fn.getSubtarget();
3891 TRI = STI.getRegisterInfo();
3892 TII = STI.getInstrInfo();
3893 LIS = &getAnalysis<LiveIntervals>();
3894 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
3895 Loops = &getAnalysis<MachineLoopInfo>();
3896 if (EnableGlobalCopies == cl::BOU_UNSET)
3897 JoinGlobalCopies = STI.enableJoinGlobalCopies();
3898 else
3899 JoinGlobalCopies = (EnableGlobalCopies == cl::BOU_TRUE);
3900
3901 // The MachineScheduler does not currently require JoinSplitEdges. This will
3902 // either be enabled unconditionally or replaced by a more general live range
3903 // splitting optimization.
3904 JoinSplitEdges = EnableJoinSplits;
3905
3906 if (VerifyCoalescing)
3907 MF->verify(this, "Before register coalescing");
3908
3909 DbgVRegToValues.clear();
3910 DbgMergedVRegNums.clear();
3911 buildVRegToDbgValueMap(fn);
3912
3913 RegClassInfo.runOnMachineFunction(fn);
3914
3915 // Join (coalesce) intervals if requested.
3916 if (EnableJoining)
3917 joinAllIntervals();
3918
3919 // After deleting a lot of copies, register classes may be less constrained.
3920 // Removing sub-register operands may allow GR32_ABCD -> GR32 and DPR_VFP2 ->
3921 // DPR inflation.
3922 array_pod_sort(InflateRegs.begin(), InflateRegs.end());
3923 InflateRegs.erase(std::unique(InflateRegs.begin(), InflateRegs.end()),
3924 InflateRegs.end());
3925 LLVM_DEBUG(dbgs() << "Trying to inflate " << InflateRegs.size()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Trying to inflate " <<
InflateRegs.size() << " regs.\n"; } } while (false)
3926 << " regs.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Trying to inflate " <<
InflateRegs.size() << " regs.\n"; } } while (false)
;
3927 for (unsigned i = 0, e = InflateRegs.size(); i != e; ++i) {
3928 unsigned Reg = InflateRegs[i];
3929 if (MRI->reg_nodbg_empty(Reg))
3930 continue;
3931 if (MRI->recomputeRegClass(Reg)) {
3932 LLVM_DEBUG(dbgs() << printReg(Reg) << " inflated to "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << printReg(Reg) << " inflated to "
<< TRI->getRegClassName(MRI->getRegClass(Reg)) <<
'\n'; } } while (false)
3933 << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << printReg(Reg) << " inflated to "
<< TRI->getRegClassName(MRI->getRegClass(Reg)) <<
'\n'; } } while (false)
;
3934 ++NumInflated;
3935
3936 LiveInterval &LI = LIS->getInterval(Reg);
3937 if (LI.hasSubRanges()) {
3938 // If the inflated register class does not support subregisters anymore
3939 // remove the subranges.
3940 if (!MRI->shouldTrackSubRegLiveness(Reg)) {
3941 LI.clearSubRanges();
3942 } else {
3943#ifndef NDEBUG
3944 LaneBitmask MaxMask = MRI->getMaxLaneMaskForVReg(Reg);
3945 // If subranges are still supported, then the same subregs
3946 // should still be supported.
3947 for (LiveInterval::SubRange &S : LI.subranges()) {
3948 assert((S.LaneMask & ~MaxMask).none())(((S.LaneMask & ~MaxMask).none()) ? static_cast<void>
(0) : __assert_fail ("(S.LaneMask & ~MaxMask).none()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/lib/CodeGen/RegisterCoalescer.cpp"
, 3948, __PRETTY_FUNCTION__))
;
3949 }
3950#endif
3951 }
3952 }
3953 }
3954 }
3955
3956 LLVM_DEBUG(dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dump(); } } while (false)
;
3957 if (VerifyCoalescing)
3958 MF->verify(this, "After register coalescing");
3959 return true;
3960}
3961
3962void RegisterCoalescer::print(raw_ostream &O, const Module* m) const {
3963 LIS->print(O, m);
3964}

/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h

1//===- llvm/CodeGen/LiveInterval.h - Interval representation ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the LiveRange and LiveInterval classes. Given some
10// numbering of each the machine instructions an interval [i, j) is said to be a
11// live range for register v if there is no instruction with number j' >= j
12// such that v is live at j' and there is no instruction with number i' < i such
13// that v is live at i'. In this implementation ranges can have holes,
14// i.e. a range might look like [1,20), [50,65), [1000,1001). Each
15// individual segment is represented as an instance of LiveRange::Segment,
16// and the whole range is represented as an instance of LiveRange.
17//
18//===----------------------------------------------------------------------===//
19
20#ifndef LLVM_CODEGEN_LIVEINTERVAL_H
21#define LLVM_CODEGEN_LIVEINTERVAL_H
22
23#include "llvm/ADT/ArrayRef.h"
24#include "llvm/ADT/IntEqClasses.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SmallVector.h"
27#include "llvm/ADT/iterator_range.h"
28#include "llvm/CodeGen/Register.h"
29#include "llvm/CodeGen/SlotIndexes.h"
30#include "llvm/MC/LaneBitmask.h"
31#include "llvm/Support/Allocator.h"
32#include "llvm/Support/MathExtras.h"
33#include <algorithm>
34#include <cassert>
35#include <cstddef>
36#include <functional>
37#include <memory>
38#include <set>
39#include <tuple>
40#include <utility>
41
42namespace llvm {
43
44 class CoalescerPair;
45 class LiveIntervals;
46 class MachineRegisterInfo;
47 class raw_ostream;
48
49 /// VNInfo - Value Number Information.
50 /// This class holds information about a machine level values, including
51 /// definition and use points.
52 ///
53 class VNInfo {
54 public:
55 using Allocator = BumpPtrAllocator;
56
57 /// The ID number of this value.
58 unsigned id;
59
60 /// The index of the defining instruction.
61 SlotIndex def;
62
63 /// VNInfo constructor.
64 VNInfo(unsigned i, SlotIndex d) : id(i), def(d) {}
65
66 /// VNInfo constructor, copies values from orig, except for the value number.
67 VNInfo(unsigned i, const VNInfo &orig) : id(i), def(orig.def) {}
68
69 /// Copy from the parameter into this VNInfo.
70 void copyFrom(VNInfo &src) {
71 def = src.def;
72 }
73
74 /// Returns true if this value is defined by a PHI instruction (or was,
75 /// PHI instructions may have been eliminated).
76 /// PHI-defs begin at a block boundary, all other defs begin at register or
77 /// EC slots.
78 bool isPHIDef() const { return def.isBlock(); }
3
Calling 'SlotIndex::isBlock'
6
Returning from 'SlotIndex::isBlock'
7
Returning zero, which participates in a condition later
79
80 /// Returns true if this value is unused.
81 bool isUnused() const { return !def.isValid(); }
82
83 /// Mark this value as unused.
84 void markUnused() { def = SlotIndex(); }
85 };
86
87 /// Result of a LiveRange query. This class hides the implementation details
88 /// of live ranges, and it should be used as the primary interface for
89 /// examining live ranges around instructions.
90 class LiveQueryResult {
91 VNInfo *const EarlyVal;
92 VNInfo *const LateVal;
93 const SlotIndex EndPoint;
94 const bool Kill;
95
96 public:
97 LiveQueryResult(VNInfo *EarlyVal, VNInfo *LateVal, SlotIndex EndPoint,
98 bool Kill)
99 : EarlyVal(EarlyVal), LateVal(LateVal), EndPoint(EndPoint), Kill(Kill)
100 {}
101
102 /// Return the value that is live-in to the instruction. This is the value
103 /// that will be read by the instruction's use operands. Return NULL if no
104 /// value is live-in.
105 VNInfo *valueIn() const {
106 return EarlyVal;
107 }
108
109 /// Return true if the live-in value is killed by this instruction. This
110 /// means that either the live range ends at the instruction, or it changes
111 /// value.
112 bool isKill() const {
113 return Kill;
114 }
115
116 /// Return true if this instruction has a dead def.
117 bool isDeadDef() const {
118 return EndPoint.isDead();
119 }
120
121 /// Return the value leaving the instruction, if any. This can be a
122 /// live-through value, or a live def. A dead def returns NULL.
123 VNInfo *valueOut() const {
124 return isDeadDef() ? nullptr : LateVal;
125 }
126
127 /// Returns the value alive at the end of the instruction, if any. This can
128 /// be a live-through value, a live def or a dead def.
129 VNInfo *valueOutOrDead() const {
130 return LateVal;
131 }
132
133 /// Return the value defined by this instruction, if any. This includes
134 /// dead defs, it is the value created by the instruction's def operands.
135 VNInfo *valueDefined() const {
136 return EarlyVal == LateVal ? nullptr : LateVal;
137 }
138
139 /// Return the end point of the last live range segment to interact with
140 /// the instruction, if any.
141 ///
142 /// The end point is an invalid SlotIndex only if the live range doesn't
143 /// intersect the instruction at all.
144 ///
145 /// The end point may be at or past the end of the instruction's basic
146 /// block. That means the value was live out of the block.
147 SlotIndex endPoint() const {
148 return EndPoint;
149 }
150 };
151
152 /// This class represents the liveness of a register, stack slot, etc.
153 /// It manages an ordered list of Segment objects.
154 /// The Segments are organized in a static single assignment form: At places
155 /// where a new value is defined or different values reach a CFG join a new
156 /// segment with a new value number is used.
157 class LiveRange {
158 public:
159 /// This represents a simple continuous liveness interval for a value.
160 /// The start point is inclusive, the end point exclusive. These intervals
161 /// are rendered as [start,end).
162 struct Segment {
163 SlotIndex start; // Start point of the interval (inclusive)
164 SlotIndex end; // End point of the interval (exclusive)
165 VNInfo *valno = nullptr; // identifier for the value contained in this
166 // segment.
167
168 Segment() = default;
169
170 Segment(SlotIndex S, SlotIndex E, VNInfo *V)
171 : start(S), end(E), valno(V) {
172 assert(S < E && "Cannot create empty or backwards segment")((S < E && "Cannot create empty or backwards segment"
) ? static_cast<void> (0) : __assert_fail ("S < E && \"Cannot create empty or backwards segment\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 172, __PRETTY_FUNCTION__))
;
173 }
174
175 /// Return true if the index is covered by this segment.
176 bool contains(SlotIndex I) const {
177 return start <= I && I < end;
178 }
179
180 /// Return true if the given interval, [S, E), is covered by this segment.
181 bool containsInterval(SlotIndex S, SlotIndex E) const {
182 assert((S < E) && "Backwards interval?")(((S < E) && "Backwards interval?") ? static_cast<
void> (0) : __assert_fail ("(S < E) && \"Backwards interval?\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 182, __PRETTY_FUNCTION__))
;
183 return (start <= S && S < end) && (start < E && E <= end);
184 }
185
186 bool operator<(const Segment &Other) const {
187 return std::tie(start, end) < std::tie(Other.start, Other.end);
188 }
189 bool operator==(const Segment &Other) const {
190 return start == Other.start && end == Other.end;
191 }
192
193 bool operator!=(const Segment &Other) const {
194 return !(*this == Other);
195 }
196
197 void dump() const;
198 };
199
200 using Segments = SmallVector<Segment, 2>;
201 using VNInfoList = SmallVector<VNInfo *, 2>;
202
203 Segments segments; // the liveness segments
204 VNInfoList valnos; // value#'s
205
206 // The segment set is used temporarily to accelerate initial computation
207 // of live ranges of physical registers in computeRegUnitRange.
208 // After that the set is flushed to the segment vector and deleted.
209 using SegmentSet = std::set<Segment>;
210 std::unique_ptr<SegmentSet> segmentSet;
211
212 using iterator = Segments::iterator;
213 using const_iterator = Segments::const_iterator;
214
215 iterator begin() { return segments.begin(); }
216 iterator end() { return segments.end(); }
217
218 const_iterator begin() const { return segments.begin(); }
219 const_iterator end() const { return segments.end(); }
220
221 using vni_iterator = VNInfoList::iterator;
222 using const_vni_iterator = VNInfoList::const_iterator;
223
224 vni_iterator vni_begin() { return valnos.begin(); }
225 vni_iterator vni_end() { return valnos.end(); }
226
227 const_vni_iterator vni_begin() const { return valnos.begin(); }
228 const_vni_iterator vni_end() const { return valnos.end(); }
229
230 /// Constructs a new LiveRange object.
231 LiveRange(bool UseSegmentSet = false)
232 : segmentSet(UseSegmentSet ? std::make_unique<SegmentSet>()
233 : nullptr) {}
234
235 /// Constructs a new LiveRange object by copying segments and valnos from
236 /// another LiveRange.
237 LiveRange(const LiveRange &Other, BumpPtrAllocator &Allocator) {
238 assert(Other.segmentSet == nullptr &&((Other.segmentSet == nullptr && "Copying of LiveRanges with active SegmentSets is not supported"
) ? static_cast<void> (0) : __assert_fail ("Other.segmentSet == nullptr && \"Copying of LiveRanges with active SegmentSets is not supported\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 239, __PRETTY_FUNCTION__))
239 "Copying of LiveRanges with active SegmentSets is not supported")((Other.segmentSet == nullptr && "Copying of LiveRanges with active SegmentSets is not supported"
) ? static_cast<void> (0) : __assert_fail ("Other.segmentSet == nullptr && \"Copying of LiveRanges with active SegmentSets is not supported\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 239, __PRETTY_FUNCTION__))
;
240 assign(Other, Allocator);
241 }
242
243 /// Copies values numbers and live segments from \p Other into this range.
244 void assign(const LiveRange &Other, BumpPtrAllocator &Allocator) {
245 if (this == &Other)
246 return;
247
248 assert(Other.segmentSet == nullptr &&((Other.segmentSet == nullptr && "Copying of LiveRanges with active SegmentSets is not supported"
) ? static_cast<void> (0) : __assert_fail ("Other.segmentSet == nullptr && \"Copying of LiveRanges with active SegmentSets is not supported\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 249, __PRETTY_FUNCTION__))
249 "Copying of LiveRanges with active SegmentSets is not supported")((Other.segmentSet == nullptr && "Copying of LiveRanges with active SegmentSets is not supported"
) ? static_cast<void> (0) : __assert_fail ("Other.segmentSet == nullptr && \"Copying of LiveRanges with active SegmentSets is not supported\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 249, __PRETTY_FUNCTION__))
;
250 // Duplicate valnos.
251 for (const VNInfo *VNI : Other.valnos)
252 createValueCopy(VNI, Allocator);
253 // Now we can copy segments and remap their valnos.
254 for (const Segment &S : Other.segments)
255 segments.push_back(Segment(S.start, S.end, valnos[S.valno->id]));
256 }
257
258 /// advanceTo - Advance the specified iterator to point to the Segment
259 /// containing the specified position, or end() if the position is past the
260 /// end of the range. If no Segment contains this position, but the
261 /// position is in a hole, this method returns an iterator pointing to the
262 /// Segment immediately after the hole.
263 iterator advanceTo(iterator I, SlotIndex Pos) {
264 assert(I != end())((I != end()) ? static_cast<void> (0) : __assert_fail (
"I != end()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 264, __PRETTY_FUNCTION__))
;
265 if (Pos >= endIndex())
266 return end();
267 while (I->end <= Pos) ++I;
268 return I;
269 }
270
271 const_iterator advanceTo(const_iterator I, SlotIndex Pos) const {
272 assert(I != end())((I != end()) ? static_cast<void> (0) : __assert_fail (
"I != end()", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 272, __PRETTY_FUNCTION__))
;
273 if (Pos >= endIndex())
274 return end();
275 while (I->end <= Pos) ++I;
276 return I;
277 }
278
279 /// find - Return an iterator pointing to the first segment that ends after
280 /// Pos, or end(). This is the same as advanceTo(begin(), Pos), but faster
281 /// when searching large ranges.
282 ///
283 /// If Pos is contained in a Segment, that segment is returned.
284 /// If Pos is in a hole, the following Segment is returned.
285 /// If Pos is beyond endIndex, end() is returned.
286 iterator find(SlotIndex Pos);
287
288 const_iterator find(SlotIndex Pos) const {
289 return const_cast<LiveRange*>(this)->find(Pos);
290 }
291
292 void clear() {
293 valnos.clear();
294 segments.clear();
295 }
296
297 size_t size() const {
298 return segments.size();
299 }
300
301 bool hasAtLeastOneValue() const { return !valnos.empty(); }
302
303 bool containsOneValue() const { return valnos.size() == 1; }
304
305 unsigned getNumValNums() const { return (unsigned)valnos.size(); }
306
307 /// getValNumInfo - Returns pointer to the specified val#.
308 ///
309 inline VNInfo *getValNumInfo(unsigned ValNo) {
310 return valnos[ValNo];
311 }
312 inline const VNInfo *getValNumInfo(unsigned ValNo) const {
313 return valnos[ValNo];
314 }
315
316 /// containsValue - Returns true if VNI belongs to this range.
317 bool containsValue(const VNInfo *VNI) const {
318 return VNI && VNI->id < getNumValNums() && VNI == getValNumInfo(VNI->id);
319 }
320
321 /// getNextValue - Create a new value number and return it. MIIdx specifies
322 /// the instruction that defines the value number.
323 VNInfo *getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator) {
324 VNInfo *VNI =
325 new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), def);
326 valnos.push_back(VNI);
327 return VNI;
328 }
329
330 /// createDeadDef - Make sure the range has a value defined at Def.
331 /// If one already exists, return it. Otherwise allocate a new value and
332 /// add liveness for a dead def.
333 VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc);
334
335 /// Create a def of value @p VNI. Return @p VNI. If there already exists
336 /// a definition at VNI->def, the value defined there must be @p VNI.
337 VNInfo *createDeadDef(VNInfo *VNI);
338
339 /// Create a copy of the given value. The new value will be identical except
340 /// for the Value number.
341 VNInfo *createValueCopy(const VNInfo *orig,
342 VNInfo::Allocator &VNInfoAllocator) {
343 VNInfo *VNI =
344 new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), *orig);
345 valnos.push_back(VNI);
346 return VNI;
347 }
348
349 /// RenumberValues - Renumber all values in order of appearance and remove
350 /// unused values.
351 void RenumberValues();
352
353 /// MergeValueNumberInto - This method is called when two value numbers
354 /// are found to be equivalent. This eliminates V1, replacing all
355 /// segments with the V1 value number with the V2 value number. This can
356 /// cause merging of V1/V2 values numbers and compaction of the value space.
357 VNInfo* MergeValueNumberInto(VNInfo *V1, VNInfo *V2);
358
359 /// Merge all of the live segments of a specific val# in RHS into this live
360 /// range as the specified value number. The segments in RHS are allowed
361 /// to overlap with segments in the current range, it will replace the
362 /// value numbers of the overlaped live segments with the specified value
363 /// number.
364 void MergeSegmentsInAsValue(const LiveRange &RHS, VNInfo *LHSValNo);
365
366 /// MergeValueInAsValue - Merge all of the segments of a specific val#
367 /// in RHS into this live range as the specified value number.
368 /// The segments in RHS are allowed to overlap with segments in the
369 /// current range, but only if the overlapping segments have the
370 /// specified value number.
371 void MergeValueInAsValue(const LiveRange &RHS,
372 const VNInfo *RHSValNo, VNInfo *LHSValNo);
373
374 bool empty() const { return segments.empty(); }
375
376 /// beginIndex - Return the lowest numbered slot covered.
377 SlotIndex beginIndex() const {
378 assert(!empty() && "Call to beginIndex() on empty range.")((!empty() && "Call to beginIndex() on empty range.")
? static_cast<void> (0) : __assert_fail ("!empty() && \"Call to beginIndex() on empty range.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 378, __PRETTY_FUNCTION__))
;
379 return segments.front().start;
380 }
381
382 /// endNumber - return the maximum point of the range of the whole,
383 /// exclusive.
384 SlotIndex endIndex() const {
385 assert(!empty() && "Call to endIndex() on empty range.")((!empty() && "Call to endIndex() on empty range.") ?
static_cast<void> (0) : __assert_fail ("!empty() && \"Call to endIndex() on empty range.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 385, __PRETTY_FUNCTION__))
;
386 return segments.back().end;
387 }
388
389 bool expiredAt(SlotIndex index) const {
390 return index >= endIndex();
391 }
392
393 bool liveAt(SlotIndex index) const {
394 const_iterator r = find(index);
395 return r != end() && r->start <= index;
396 }
397
398 /// Return the segment that contains the specified index, or null if there
399 /// is none.
400 const Segment *getSegmentContaining(SlotIndex Idx) const {
401 const_iterator I = FindSegmentContaining(Idx);
402 return I == end() ? nullptr : &*I;
403 }
404
405 /// Return the live segment that contains the specified index, or null if
406 /// there is none.
407 Segment *getSegmentContaining(SlotIndex Idx) {
408 iterator I = FindSegmentContaining(Idx);
409 return I == end() ? nullptr : &*I;
410 }
411
412 /// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
413 VNInfo *getVNInfoAt(SlotIndex Idx) const {
414 const_iterator I = FindSegmentContaining(Idx);
415 return I == end() ? nullptr : I->valno;
416 }
417
418 /// getVNInfoBefore - Return the VNInfo that is live up to but not
419 /// necessarilly including Idx, or NULL. Use this to find the reaching def
420 /// used by an instruction at this SlotIndex position.
421 VNInfo *getVNInfoBefore(SlotIndex Idx) const {
422 const_iterator I = FindSegmentContaining(Idx.getPrevSlot());
423 return I == end() ? nullptr : I->valno;
424 }
425
426 /// Return an iterator to the segment that contains the specified index, or
427 /// end() if there is none.
428 iterator FindSegmentContaining(SlotIndex Idx) {
429 iterator I = find(Idx);
430 return I != end() && I->start <= Idx ? I : end();
431 }
432
433 const_iterator FindSegmentContaining(SlotIndex Idx) const {
434 const_iterator I = find(Idx);
435 return I != end() && I->start <= Idx ? I : end();
436 }
437
438 /// overlaps - Return true if the intersection of the two live ranges is
439 /// not empty.
440 bool overlaps(const LiveRange &other) const {
441 if (other.empty())
442 return false;
443 return overlapsFrom(other, other.begin());
444 }
445
446 /// overlaps - Return true if the two ranges have overlapping segments
447 /// that are not coalescable according to CP.
448 ///
449 /// Overlapping segments where one range is defined by a coalescable
450 /// copy are allowed.
451 bool overlaps(const LiveRange &Other, const CoalescerPair &CP,
452 const SlotIndexes&) const;
453
454 /// overlaps - Return true if the live range overlaps an interval specified
455 /// by [Start, End).
456 bool overlaps(SlotIndex Start, SlotIndex End) const;
457
458 /// overlapsFrom - Return true if the intersection of the two live ranges
459 /// is not empty. The specified iterator is a hint that we can begin
460 /// scanning the Other range starting at I.
461 bool overlapsFrom(const LiveRange &Other, const_iterator StartPos) const;
462
463 /// Returns true if all segments of the @p Other live range are completely
464 /// covered by this live range.
465 /// Adjacent live ranges do not affect the covering:the liverange
466 /// [1,5](5,10] covers (3,7].
467 bool covers(const LiveRange &Other) const;
468
469 /// Add the specified Segment to this range, merging segments as
470 /// appropriate. This returns an iterator to the inserted segment (which
471 /// may have grown since it was inserted).
472 iterator addSegment(Segment S);
473
474 /// Attempt to extend a value defined after @p StartIdx to include @p Use.
475 /// Both @p StartIdx and @p Use should be in the same basic block. In case
476 /// of subranges, an extension could be prevented by an explicit "undef"
477 /// caused by a <def,read-undef> on a non-overlapping lane. The list of
478 /// location of such "undefs" should be provided in @p Undefs.
479 /// The return value is a pair: the first element is VNInfo of the value
480 /// that was extended (possibly nullptr), the second is a boolean value
481 /// indicating whether an "undef" was encountered.
482 /// If this range is live before @p Use in the basic block that starts at
483 /// @p StartIdx, and there is no intervening "undef", extend it to be live
484 /// up to @p Use, and return the pair {value, false}. If there is no
485 /// segment before @p Use and there is no "undef" between @p StartIdx and
486 /// @p Use, return {nullptr, false}. If there is an "undef" before @p Use,
487 /// return {nullptr, true}.
488 std::pair<VNInfo*,bool> extendInBlock(ArrayRef<SlotIndex> Undefs,
489 SlotIndex StartIdx, SlotIndex Kill);
490
491 /// Simplified version of the above "extendInBlock", which assumes that
492 /// no register lanes are undefined by <def,read-undef> operands.
493 /// If this range is live before @p Use in the basic block that starts
494 /// at @p StartIdx, extend it to be live up to @p Use, and return the
495 /// value. If there is no segment before @p Use, return nullptr.
496 VNInfo *extendInBlock(SlotIndex StartIdx, SlotIndex Kill);
497
498 /// join - Join two live ranges (this, and other) together. This applies
499 /// mappings to the value numbers in the LHS/RHS ranges as specified. If
500 /// the ranges are not joinable, this aborts.
501 void join(LiveRange &Other,
502 const int *ValNoAssignments,
503 const int *RHSValNoAssignments,
504 SmallVectorImpl<VNInfo *> &NewVNInfo);
505
506 /// True iff this segment is a single segment that lies between the
507 /// specified boundaries, exclusively. Vregs live across a backedge are not
508 /// considered local. The boundaries are expected to lie within an extended
509 /// basic block, so vregs that are not live out should contain no holes.
510 bool isLocal(SlotIndex Start, SlotIndex End) const {
511 return beginIndex() > Start.getBaseIndex() &&
512 endIndex() < End.getBoundaryIndex();
513 }
514
515 /// Remove the specified segment from this range. Note that the segment
516 /// must be a single Segment in its entirety.
517 void removeSegment(SlotIndex Start, SlotIndex End,
518 bool RemoveDeadValNo = false);
519
520 void removeSegment(Segment S, bool RemoveDeadValNo = false) {
521 removeSegment(S.start, S.end, RemoveDeadValNo);
522 }
523
524 /// Remove segment pointed to by iterator @p I from this range. This does
525 /// not remove dead value numbers.
526 iterator removeSegment(iterator I) {
527 return segments.erase(I);
528 }
529
530 /// Query Liveness at Idx.
531 /// The sub-instruction slot of Idx doesn't matter, only the instruction
532 /// it refers to is considered.
533 LiveQueryResult Query(SlotIndex Idx) const {
534 // Find the segment that enters the instruction.
535 const_iterator I = find(Idx.getBaseIndex());
536 const_iterator E = end();
537 if (I == E)
538 return LiveQueryResult(nullptr, nullptr, SlotIndex(), false);
539
540 // Is this an instruction live-in segment?
541 // If Idx is the start index of a basic block, include live-in segments
542 // that start at Idx.getBaseIndex().
543 VNInfo *EarlyVal = nullptr;
544 VNInfo *LateVal = nullptr;
545 SlotIndex EndPoint;
546 bool Kill = false;
547 if (I->start <= Idx.getBaseIndex()) {
548 EarlyVal = I->valno;
549 EndPoint = I->end;
550 // Move to the potentially live-out segment.
551 if (SlotIndex::isSameInstr(Idx, I->end)) {
552 Kill = true;
553 if (++I == E)
554 return LiveQueryResult(EarlyVal, LateVal, EndPoint, Kill);
555 }
556 // Special case: A PHIDef value can have its def in the middle of a
557 // segment if the value happens to be live out of the layout
558 // predecessor.
559 // Such a value is not live-in.
560 if (EarlyVal->def == Idx.getBaseIndex())
561 EarlyVal = nullptr;
562 }
563 // I now points to the segment that may be live-through, or defined by
564 // this instr. Ignore segments starting after the current instr.
565 if (!SlotIndex::isEarlierInstr(Idx, I->start)) {
566 LateVal = I->valno;
567 EndPoint = I->end;
568 }
569 return LiveQueryResult(EarlyVal, LateVal, EndPoint, Kill);
570 }
571
572 /// removeValNo - Remove all the segments defined by the specified value#.
573 /// Also remove the value# from value# list.
574 void removeValNo(VNInfo *ValNo);
575
576 /// Returns true if the live range is zero length, i.e. no live segments
577 /// span instructions. It doesn't pay to spill such a range.
578 bool isZeroLength(SlotIndexes *Indexes) const {
579 for (const Segment &S : segments)
580 if (Indexes->getNextNonNullIndex(S.start).getBaseIndex() <
581 S.end.getBaseIndex())
582 return false;
583 return true;
584 }
585
586 // Returns true if any segment in the live range contains any of the
587 // provided slot indexes. Slots which occur in holes between
588 // segments will not cause the function to return true.
589 bool isLiveAtIndexes(ArrayRef<SlotIndex> Slots) const;
590
591 bool operator<(const LiveRange& other) const {
592 const SlotIndex &thisIndex = beginIndex();
593 const SlotIndex &otherIndex = other.beginIndex();
594 return thisIndex < otherIndex;
595 }
596
597 /// Returns true if there is an explicit "undef" between @p Begin
598 /// @p End.
599 bool isUndefIn(ArrayRef<SlotIndex> Undefs, SlotIndex Begin,
600 SlotIndex End) const {
601 return std::any_of(Undefs.begin(), Undefs.end(),
602 [Begin,End] (SlotIndex Idx) -> bool {
603 return Begin <= Idx && Idx < End;
604 });
605 }
606
607 /// Flush segment set into the regular segment vector.
608 /// The method is to be called after the live range
609 /// has been created, if use of the segment set was
610 /// activated in the constructor of the live range.
611 void flushSegmentSet();
612
613 /// Stores indexes from the input index sequence R at which this LiveRange
614 /// is live to the output O iterator.
615 /// R is a range of _ascending sorted_ _random_ access iterators
616 /// to the input indexes. Indexes stored at O are ascending sorted so it
617 /// can be used directly in the subsequent search (for example for
618 /// subranges). Returns true if found at least one index.
619 template <typename Range, typename OutputIt>
620 bool findIndexesLiveAt(Range &&R, OutputIt O) const {
621 assert(llvm::is_sorted(R))((llvm::is_sorted(R)) ? static_cast<void> (0) : __assert_fail
("llvm::is_sorted(R)", "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/LiveInterval.h"
, 621, __PRETTY_FUNCTION__))
;
622 auto Idx = R.begin(), EndIdx = R.end();
623 auto Seg = segments.begin(), EndSeg = segments.end();
624 bool Found = false;
625 while (Idx != EndIdx && Seg != EndSeg) {
626 // if the Seg is lower find first segment that is above Idx using binary
627 // search
628 if (Seg->end <= *Idx) {
629 Seg = std::upper_bound(
630 ++Seg, EndSeg, *Idx,
631 [=](std::remove_reference_t<decltype(*Idx)> V,
632 const std::remove_reference_t<decltype(*Seg)> &S) {
633 return V < S.end;
634 });
635 if (Seg == EndSeg)
636 break;
637 }
638 auto NotLessStart = std::lower_bound(Idx, EndIdx, Seg->start);
639 if (NotLessStart == EndIdx)
640 break;
641 auto NotLessEnd = std::lower_bound(NotLessStart, EndIdx, Seg->end);
642 if (NotLessEnd != NotLessStart) {
643 Found = true;
644 O = std::copy(NotLessStart, NotLessEnd, O);
645 }
646 Idx = NotLessEnd;
647 ++Seg;
648 }
649 return Found;
650 }
651
652 void print(raw_ostream &OS) const;
653 void dump() const;
654
655 /// Walk the range and assert if any invariants fail to hold.
656 ///
657 /// Note that this is a no-op when asserts are disabled.
658#ifdef NDEBUG
659 void verify() const {}
660#else
661 void verify() const;
662#endif
663
664 protected:
665 /// Append a segment to the list of segments.
666 void append(const LiveRange::Segment S);
667
668 private:
669 friend class LiveRangeUpdater;
670 void addSegmentToSet(Segment S);
671 void markValNoForDeletion(VNInfo *V);
672 };
673
674 inline raw_ostream &operator<<(raw_ostream &OS, const LiveRange &LR) {
675 LR.print(OS);
676 return OS;
677 }
678
679 /// LiveInterval - This class represents the liveness of a register,
680 /// or stack slot.
681 class LiveInterval : public LiveRange {
682 public:
683 using super = LiveRange;
684
685 /// A live range for subregisters. The LaneMask specifies which parts of the
686 /// super register are covered by the interval.
687 /// (@sa TargetRegisterInfo::getSubRegIndexLaneMask()).
688 class SubRange : public LiveRange {
689 public:
690 SubRange *Next = nullptr;
691 LaneBitmask LaneMask;
692
693 /// Constructs a new SubRange object.
694 SubRange(LaneBitmask LaneMask) : LaneMask(LaneMask) {}
695
696 /// Constructs a new SubRange object by copying liveness from @p Other.
697 SubRange(LaneBitmask LaneMask, const LiveRange &Other,
698 BumpPtrAllocator &Allocator)
699 : LiveRange(Other, Allocator), LaneMask(LaneMask) {}
700
701 void print(raw_ostream &OS) const;
702 void dump() const;
703 };
704
705 private:
706 SubRange *SubRanges = nullptr; ///< Single linked list of subregister live
707 /// ranges.
708 const Register Reg; // the register or stack slot of this interval.
709 float Weight = 0.0; // weight of this interval
710
711 public:
712 Register reg() const { return Reg; }
713 float weight() const { return Weight; }
714 void incrementWeight(float Inc) { Weight += Inc; }
715 void setWeight(float Value) { Weight = Value; }
716
717 LiveInterval(unsigned Reg, float Weight) : Reg(Reg), Weight(Weight) {}
718
719 ~LiveInterval() {
720 clearSubRanges();
721 }
722
723 template<typename T>
724 class SingleLinkedListIterator {
725 T *P;
726
727 public:
728 SingleLinkedListIterator<T>(T *P) : P(P) {}
729
730 SingleLinkedListIterator<T> &operator++() {
731 P = P->Next;
732 return *this;
733 }
734 SingleLinkedListIterator<T> operator++(int) {
735 SingleLinkedListIterator res = *this;
736 ++*this;
737 return res;
738 }
739 bool operator!=(const SingleLinkedListIterator<T> &Other) {
740 return P != Other.operator->();
741 }
742 bool operator==(const SingleLinkedListIterator<T> &Other) {
743 return P == Other.operator->();
744 }
745 T &operator*() const {
746 return *P;
747 }
748 T *operator->() const {
749 return P;
750 }
751 };
752
753 using subrange_iterator = SingleLinkedListIterator<SubRange>;
754 using const_subrange_iterator = SingleLinkedListIterator<const SubRange>;
755
756 subrange_iterator subrange_begin() {
757 return subrange_iterator(SubRanges);
758 }
759 subrange_iterator subrange_end() {
760 return subrange_iterator(nullptr);
761 }
762
763 const_subrange_iterator subrange_begin() const {
764 return const_subrange_iterator(SubRanges);
765 }
766 const_subrange_iterator subrange_end() const {
767 return const_subrange_iterator(nullptr);
768 }
769
770 iterator_range<subrange_iterator> subranges() {
771 return make_range(subrange_begin(), subrange_end());
772 }
773
774 iterator_range<const_subrange_iterator> subranges() const {
775 return make_range(subrange_begin(), subrange_end());
776 }
777
778 /// Creates a new empty subregister live range. The range is added at the
779 /// beginning of the subrange list; subrange iterators stay valid.
780 SubRange *createSubRange(BumpPtrAllocator &Allocator,
781 LaneBitmask LaneMask) {
782 SubRange *Range = new (Allocator) SubRange(LaneMask);
783 appendSubRange(Range);
784 return Range;
785 }
786
787 /// Like createSubRange() but the new range is filled with a copy of the
788 /// liveness information in @p CopyFrom.
789 SubRange *createSubRangeFrom(BumpPtrAllocator &Allocator,
790 LaneBitmask LaneMask,
791 const LiveRange &CopyFrom) {
792 SubRange *Range = new (Allocator) SubRange(LaneMask, CopyFrom, Allocator);
793 appendSubRange(Range);
794 return Range;
795 }
796
797 /// Returns true if subregister liveness information is available.
798 bool hasSubRanges() const {
799 return SubRanges != nullptr;
800 }
801
802 /// Removes all subregister liveness information.
803 void clearSubRanges();
804
805 /// Removes all subranges without any segments (subranges without segments
806 /// are not considered valid and should only exist temporarily).
807 void removeEmptySubRanges();
808
809 /// getSize - Returns the sum of sizes of all the LiveRange's.
810 ///
811 unsigned getSize() const;
812
813 /// isSpillable - Can this interval be spilled?
814 bool isSpillable() const { return Weight != huge_valf; }
815
816 /// markNotSpillable - Mark interval as not spillable
817 void markNotSpillable() { Weight = huge_valf; }
818
819 /// For a given lane mask @p LaneMask, compute indexes at which the
820 /// lane is marked undefined by subregister <def,read-undef> definitions.
821 void computeSubRangeUndefs(SmallVectorImpl<SlotIndex> &Undefs,
822 LaneBitmask LaneMask,
823 const MachineRegisterInfo &MRI,
824 const SlotIndexes &Indexes) const;
825
826 /// Refines the subranges to support \p LaneMask. This may only be called
827 /// for LI.hasSubrange()==true. Subregister ranges are split or created
828 /// until \p LaneMask can be matched exactly. \p Mod is executed on the
829 /// matching subranges.
830 ///
831 /// Example:
832 /// Given an interval with subranges with lanemasks L0F00, L00F0 and
833 /// L000F, refining for mask L0018. Will split the L00F0 lane into
834 /// L00E0 and L0010 and the L000F lane into L0007 and L0008. The Mod
835 /// function will be applied to the L0010 and L0008 subranges.
836 ///
837 /// \p Indexes and \p TRI are required to clean up the VNIs that
838 /// don't defne the related lane masks after they get shrunk. E.g.,
839 /// when L000F gets split into L0007 and L0008 maybe only a subset
840 /// of the VNIs that defined L000F defines L0007.
841 ///
842 /// The clean up of the VNIs need to look at the actual instructions
843 /// to decide what is or is not live at a definition point. If the
844 /// update of the subranges occurs while the IR does not reflect these
845 /// changes, \p ComposeSubRegIdx can be used to specify how the
846 /// definition are going to be rewritten.
847 /// E.g., let say we want to merge:
848 /// V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32>
849 /// We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32>
850 /// overlap, i.e., by choosing a class where we can find "offset + 1 == 3".
851 /// Put differently we align V2's sub3 with V1's sub1:
852 /// V2: sub0 sub1 sub2 sub3
853 /// V1: <offset> sub0 sub1
854 ///
855 /// This offset will look like a composed subregidx in the the class:
856 /// V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
857 /// => V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
858 ///
859 /// Now if we didn't rewrite the uses and def of V1, all the checks for V1
860 /// need to account for this offset.
861 /// This happens during coalescing where we update the live-ranges while
862 /// still having the old IR around because updating the IR on-the-fly
863 /// would actually clobber some information on how the live-ranges that
864 /// are being updated look like.
865 void refineSubRanges(BumpPtrAllocator &Allocator, LaneBitmask LaneMask,
866 std::function<void(LiveInterval::SubRange &)> Apply,
867 const SlotIndexes &Indexes,
868 const TargetRegisterInfo &TRI,
869 unsigned ComposeSubRegIdx = 0);
870
871 bool operator<(const LiveInterval& other) const {
872 const SlotIndex &thisIndex = beginIndex();
873 const SlotIndex &otherIndex = other.beginIndex();
874 return std::tie(thisIndex, Reg) < std::tie(otherIndex, other.Reg);
875 }
876
877 void print(raw_ostream &OS) const;
878 void dump() const;
879
880 /// Walks the interval and assert if any invariants fail to hold.
881 ///
882 /// Note that this is a no-op when asserts are disabled.
883#ifdef NDEBUG
884 void verify(const MachineRegisterInfo *MRI = nullptr) const {}
885#else
886 void verify(const MachineRegisterInfo *MRI = nullptr) const;
887#endif
888
889 private:
890 /// Appends @p Range to SubRanges list.
891 void appendSubRange(SubRange *Range) {
892 Range->Next = SubRanges;
893 SubRanges = Range;
894 }
895
896 /// Free memory held by SubRange.
897 void freeSubRange(SubRange *S);
898 };
899
900 inline raw_ostream &operator<<(raw_ostream &OS,
901 const LiveInterval::SubRange &SR) {
902 SR.print(OS);
903 return OS;
904 }
905
906 inline raw_ostream &operator<<(raw_ostream &OS, const LiveInterval &LI) {
907 LI.print(OS);
908 return OS;
909 }
910
911 raw_ostream &operator<<(raw_ostream &OS, const LiveRange::Segment &S);
912
913 inline bool operator<(SlotIndex V, const LiveRange::Segment &S) {
914 return V < S.start;
915 }
916
917 inline bool operator<(const LiveRange::Segment &S, SlotIndex V) {
918 return S.start < V;
919 }
920
921 /// Helper class for performant LiveRange bulk updates.
922 ///
923 /// Calling LiveRange::addSegment() repeatedly can be expensive on large
924 /// live ranges because segments after the insertion point may need to be
925 /// shifted. The LiveRangeUpdater class can defer the shifting when adding
926 /// many segments in order.
927 ///
928 /// The LiveRange will be in an invalid state until flush() is called.
929 class LiveRangeUpdater {
930 LiveRange *LR;
931 SlotIndex LastStart;
932 LiveRange::iterator WriteI;
933 LiveRange::iterator ReadI;
934 SmallVector<LiveRange::Segment, 16> Spills;
935 void mergeSpills();
936
937 public:
938 /// Create a LiveRangeUpdater for adding segments to LR.
939 /// LR will temporarily be in an invalid state until flush() is called.
940 LiveRangeUpdater(LiveRange *lr = nullptr) : LR(lr) {}
941
942 ~LiveRangeUpdater() { flush(); }
943
944 /// Add a segment to LR and coalesce when possible, just like
945 /// LR.addSegment(). Segments should be added in increasing start order for
946 /// best performance.
947 void add(LiveRange::Segment);
948
949 void add(SlotIndex Start, SlotIndex End, VNInfo *VNI) {
950 add(LiveRange::Segment(Start, End, VNI));
951 }
952
953 /// Return true if the LR is currently in an invalid state, and flush()
954 /// needs to be called.
955 bool isDirty() const { return LastStart.isValid(); }
956
957 /// Flush the updater state to LR so it is valid and contains all added
958 /// segments.
959 void flush();
960
961 /// Select a different destination live range.
962 void setDest(LiveRange *lr) {
963 if (LR != lr && isDirty())
964 flush();
965 LR = lr;
966 }
967
968 /// Get the current destination live range.
969 LiveRange *getDest() const { return LR; }
970
971 void dump() const;
972 void print(raw_ostream&) const;
973 };
974
975 inline raw_ostream &operator<<(raw_ostream &OS, const LiveRangeUpdater &X) {
976 X.print(OS);
977 return OS;
978 }
979
980 /// ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a
981 /// LiveInterval into equivalence clases of connected components. A
982 /// LiveInterval that has multiple connected components can be broken into
983 /// multiple LiveIntervals.
984 ///
985 /// Given a LiveInterval that may have multiple connected components, run:
986 ///
987 /// unsigned numComps = ConEQ.Classify(LI);
988 /// if (numComps > 1) {
989 /// // allocate numComps-1 new LiveIntervals into LIS[1..]
990 /// ConEQ.Distribute(LIS);
991 /// }
992
993 class ConnectedVNInfoEqClasses {
994 LiveIntervals &LIS;
995 IntEqClasses EqClass;
996
997 public:
998 explicit ConnectedVNInfoEqClasses(LiveIntervals &lis) : LIS(lis) {}
999
1000 /// Classify the values in \p LR into connected components.
1001 /// Returns the number of connected components.
1002 unsigned Classify(const LiveRange &LR);
1003
1004 /// getEqClass - Classify creates equivalence classes numbered 0..N. Return
1005 /// the equivalence class assigned the VNI.
1006 unsigned getEqClass(const VNInfo *VNI) const { return EqClass[VNI->id]; }
1007
1008 /// Distribute values in \p LI into a separate LiveIntervals
1009 /// for each connected component. LIV must have an empty LiveInterval for
1010 /// each additional connected component. The first connected component is
1011 /// left in \p LI.
1012 void Distribute(LiveInterval &LI, LiveInterval *LIV[],
1013 MachineRegisterInfo &MRI);
1014 };
1015
1016} // end namespace llvm
1017
1018#endif // LLVM_CODEGEN_LIVEINTERVAL_H

/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h

1//===- llvm/CodeGen/SlotIndexes.h - Slot indexes representation -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements SlotIndex and related classes. The purpose of SlotIndex
10// is to describe a position at which a register can become live, or cease to
11// be live.
12//
13// SlotIndex is mostly a proxy for entries of the SlotIndexList, a class which
14// is held is LiveIntervals and provides the real numbering. This allows
15// LiveIntervals to perform largely transparent renumbering.
16//===----------------------------------------------------------------------===//
17
18#ifndef LLVM_CODEGEN_SLOTINDEXES_H
19#define LLVM_CODEGEN_SLOTINDEXES_H
20
21#include "llvm/ADT/DenseMap.h"
22#include "llvm/ADT/IntervalMap.h"
23#include "llvm/ADT/PointerIntPair.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/ADT/ilist.h"
26#include "llvm/CodeGen/MachineBasicBlock.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineInstr.h"
30#include "llvm/CodeGen/MachineInstrBundle.h"
31#include "llvm/Pass.h"
32#include "llvm/Support/Allocator.h"
33#include <algorithm>
34#include <cassert>
35#include <iterator>
36#include <utility>
37
38namespace llvm {
39
40class raw_ostream;
41
42 /// This class represents an entry in the slot index list held in the
43 /// SlotIndexes pass. It should not be used directly. See the
44 /// SlotIndex & SlotIndexes classes for the public interface to this
45 /// information.
46 class IndexListEntry : public ilist_node<IndexListEntry> {
47 MachineInstr *mi;
48 unsigned index;
49
50 public:
51 IndexListEntry(MachineInstr *mi, unsigned index) : mi(mi), index(index) {}
52
53 MachineInstr* getInstr() const { return mi; }
54 void setInstr(MachineInstr *mi) {
55 this->mi = mi;
56 }
57
58 unsigned getIndex() const { return index; }
59 void setIndex(unsigned index) {
60 this->index = index;
61 }
62
63#ifdef EXPENSIVE_CHECKS
64 // When EXPENSIVE_CHECKS is defined, "erased" index list entries will
65 // actually be moved to a "graveyard" list, and have their pointers
66 // poisoned, so that dangling SlotIndex access can be reliably detected.
67 void setPoison() {
68 intptr_t tmp = reinterpret_cast<intptr_t>(mi);
69 assert(((tmp & 0x1) == 0x0) && "Pointer already poisoned?")((((tmp & 0x1) == 0x0) && "Pointer already poisoned?"
) ? static_cast<void> (0) : __assert_fail ("((tmp & 0x1) == 0x0) && \"Pointer already poisoned?\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 69, __PRETTY_FUNCTION__))
;
70 tmp |= 0x1;
71 mi = reinterpret_cast<MachineInstr*>(tmp);
72 }
73
74 bool isPoisoned() const { return (reinterpret_cast<intptr_t>(mi) & 0x1) == 0x1; }
75#endif // EXPENSIVE_CHECKS
76 };
77
78 template <>
79 struct ilist_alloc_traits<IndexListEntry>
80 : public ilist_noalloc_traits<IndexListEntry> {};
81
82 /// SlotIndex - An opaque wrapper around machine indexes.
83 class SlotIndex {
84 friend class SlotIndexes;
85
86 enum Slot {
87 /// Basic block boundary. Used for live ranges entering and leaving a
88 /// block without being live in the layout neighbor. Also used as the
89 /// def slot of PHI-defs.
90 Slot_Block,
91
92 /// Early-clobber register use/def slot. A live range defined at
93 /// Slot_EarlyClobber interferes with normal live ranges killed at
94 /// Slot_Register. Also used as the kill slot for live ranges tied to an
95 /// early-clobber def.
96 Slot_EarlyClobber,
97
98 /// Normal register use/def slot. Normal instructions kill and define
99 /// register live ranges at this slot.
100 Slot_Register,
101
102 /// Dead def kill point. Kill slot for a live range that is defined by
103 /// the same instruction (Slot_Register or Slot_EarlyClobber), but isn't
104 /// used anywhere.
105 Slot_Dead,
106
107 Slot_Count
108 };
109
110 PointerIntPair<IndexListEntry*, 2, unsigned> lie;
111
112 SlotIndex(IndexListEntry *entry, unsigned slot)
113 : lie(entry, slot) {}
114
115 IndexListEntry* listEntry() const {
116 assert(isValid() && "Attempt to compare reserved index.")((isValid() && "Attempt to compare reserved index.") ?
static_cast<void> (0) : __assert_fail ("isValid() && \"Attempt to compare reserved index.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 116, __PRETTY_FUNCTION__))
;
117#ifdef EXPENSIVE_CHECKS
118 assert(!lie.getPointer()->isPoisoned() &&((!lie.getPointer()->isPoisoned() && "Attempt to access deleted list-entry."
) ? static_cast<void> (0) : __assert_fail ("!lie.getPointer()->isPoisoned() && \"Attempt to access deleted list-entry.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 119, __PRETTY_FUNCTION__))
119 "Attempt to access deleted list-entry.")((!lie.getPointer()->isPoisoned() && "Attempt to access deleted list-entry."
) ? static_cast<void> (0) : __assert_fail ("!lie.getPointer()->isPoisoned() && \"Attempt to access deleted list-entry.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 119, __PRETTY_FUNCTION__))
;
120#endif // EXPENSIVE_CHECKS
121 return lie.getPointer();
122 }
123
124 unsigned getIndex() const {
125 return listEntry()->getIndex() | getSlot();
126 }
127
128 /// Returns the slot for this SlotIndex.
129 Slot getSlot() const {
130 return static_cast<Slot>(lie.getInt());
131 }
132
133 public:
134 enum {
135 /// The default distance between instructions as returned by distance().
136 /// This may vary as instructions are inserted and removed.
137 InstrDist = 4 * Slot_Count
138 };
139
140 /// Construct an invalid index.
141 SlotIndex() = default;
142
143 // Construct a new slot index from the given one, and set the slot.
144 SlotIndex(const SlotIndex &li, Slot s) : lie(li.listEntry(), unsigned(s)) {
145 assert(lie.getPointer() != nullptr &&((lie.getPointer() != nullptr && "Attempt to construct index with 0 pointer."
) ? static_cast<void> (0) : __assert_fail ("lie.getPointer() != nullptr && \"Attempt to construct index with 0 pointer.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 146, __PRETTY_FUNCTION__))
146 "Attempt to construct index with 0 pointer.")((lie.getPointer() != nullptr && "Attempt to construct index with 0 pointer."
) ? static_cast<void> (0) : __assert_fail ("lie.getPointer() != nullptr && \"Attempt to construct index with 0 pointer.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 146, __PRETTY_FUNCTION__))
;
147 }
148
149 /// Returns true if this is a valid index. Invalid indices do
150 /// not point into an index table, and cannot be compared.
151 bool isValid() const {
152 return lie.getPointer();
153 }
154
155 /// Return true for a valid index.
156 explicit operator bool() const { return isValid(); }
157
158 /// Print this index to the given raw_ostream.
159 void print(raw_ostream &os) const;
160
161 /// Dump this index to stderr.
162 void dump() const;
163
164 /// Compare two SlotIndex objects for equality.
165 bool operator==(SlotIndex other) const {
166 return lie == other.lie;
167 }
168 /// Compare two SlotIndex objects for inequality.
169 bool operator!=(SlotIndex other) const {
170 return lie != other.lie;
171 }
172
173 /// Compare two SlotIndex objects. Return true if the first index
174 /// is strictly lower than the second.
175 bool operator<(SlotIndex other) const {
176 return getIndex() < other.getIndex();
177 }
178 /// Compare two SlotIndex objects. Return true if the first index
179 /// is lower than, or equal to, the second.
180 bool operator<=(SlotIndex other) const {
181 return getIndex() <= other.getIndex();
182 }
183
184 /// Compare two SlotIndex objects. Return true if the first index
185 /// is greater than the second.
186 bool operator>(SlotIndex other) const {
187 return getIndex() > other.getIndex();
188 }
189
190 /// Compare two SlotIndex objects. Return true if the first index
191 /// is greater than, or equal to, the second.
192 bool operator>=(SlotIndex other) const {
193 return getIndex() >= other.getIndex();
194 }
195
196 /// isSameInstr - Return true if A and B refer to the same instruction.
197 static bool isSameInstr(SlotIndex A, SlotIndex B) {
198 return A.lie.getPointer() == B.lie.getPointer();
199 }
200
201 /// isEarlierInstr - Return true if A refers to an instruction earlier than
202 /// B. This is equivalent to A < B && !isSameInstr(A, B).
203 static bool isEarlierInstr(SlotIndex A, SlotIndex B) {
204 return A.listEntry()->getIndex() < B.listEntry()->getIndex();
205 }
206
207 /// Return true if A refers to the same instruction as B or an earlier one.
208 /// This is equivalent to !isEarlierInstr(B, A).
209 static bool isEarlierEqualInstr(SlotIndex A, SlotIndex B) {
210 return !isEarlierInstr(B, A);
211 }
212
213 /// Return the distance from this index to the given one.
214 int distance(SlotIndex other) const {
215 return other.getIndex() - getIndex();
216 }
217
218 /// Return the scaled distance from this index to the given one, where all
219 /// slots on the same instruction have zero distance.
220 int getInstrDistance(SlotIndex other) const {
221 return (other.listEntry()->getIndex() - listEntry()->getIndex())
222 / Slot_Count;
223 }
224
225 /// isBlock - Returns true if this is a block boundary slot.
226 bool isBlock() const { return getSlot() == Slot_Block; }
4
Assuming the condition is false
5
Returning zero, which participates in a condition later
227
228 /// isEarlyClobber - Returns true if this is an early-clobber slot.
229 bool isEarlyClobber() const { return getSlot() == Slot_EarlyClobber; }
230
231 /// isRegister - Returns true if this is a normal register use/def slot.
232 /// Note that early-clobber slots may also be used for uses and defs.
233 bool isRegister() const { return getSlot() == Slot_Register; }
234
235 /// isDead - Returns true if this is a dead def kill slot.
236 bool isDead() const { return getSlot() == Slot_Dead; }
237
238 /// Returns the base index for associated with this index. The base index
239 /// is the one associated with the Slot_Block slot for the instruction
240 /// pointed to by this index.
241 SlotIndex getBaseIndex() const {
242 return SlotIndex(listEntry(), Slot_Block);
243 }
244
245 /// Returns the boundary index for associated with this index. The boundary
246 /// index is the one associated with the Slot_Block slot for the instruction
247 /// pointed to by this index.
248 SlotIndex getBoundaryIndex() const {
249 return SlotIndex(listEntry(), Slot_Dead);
250 }
251
252 /// Returns the register use/def slot in the current instruction for a
253 /// normal or early-clobber def.
254 SlotIndex getRegSlot(bool EC = false) const {
255 return SlotIndex(listEntry(), EC ? Slot_EarlyClobber : Slot_Register);
256 }
257
258 /// Returns the dead def kill slot for the current instruction.
259 SlotIndex getDeadSlot() const {
260 return SlotIndex(listEntry(), Slot_Dead);
261 }
262
263 /// Returns the next slot in the index list. This could be either the
264 /// next slot for the instruction pointed to by this index or, if this
265 /// index is a STORE, the first slot for the next instruction.
266 /// WARNING: This method is considerably more expensive than the methods
267 /// that return specific slots (getUseIndex(), etc). If you can - please
268 /// use one of those methods.
269 SlotIndex getNextSlot() const {
270 Slot s = getSlot();
271 if (s == Slot_Dead) {
272 return SlotIndex(&*++listEntry()->getIterator(), Slot_Block);
273 }
274 return SlotIndex(listEntry(), s + 1);
275 }
276
277 /// Returns the next index. This is the index corresponding to the this
278 /// index's slot, but for the next instruction.
279 SlotIndex getNextIndex() const {
280 return SlotIndex(&*++listEntry()->getIterator(), getSlot());
281 }
282
283 /// Returns the previous slot in the index list. This could be either the
284 /// previous slot for the instruction pointed to by this index or, if this
285 /// index is a Slot_Block, the last slot for the previous instruction.
286 /// WARNING: This method is considerably more expensive than the methods
287 /// that return specific slots (getUseIndex(), etc). If you can - please
288 /// use one of those methods.
289 SlotIndex getPrevSlot() const {
290 Slot s = getSlot();
291 if (s == Slot_Block) {
292 return SlotIndex(&*--listEntry()->getIterator(), Slot_Dead);
293 }
294 return SlotIndex(listEntry(), s - 1);
295 }
296
297 /// Returns the previous index. This is the index corresponding to this
298 /// index's slot, but for the previous instruction.
299 SlotIndex getPrevIndex() const {
300 return SlotIndex(&*--listEntry()->getIterator(), getSlot());
301 }
302 };
303
304 inline raw_ostream& operator<<(raw_ostream &os, SlotIndex li) {
305 li.print(os);
306 return os;
307 }
308
309 using IdxMBBPair = std::pair<SlotIndex, MachineBasicBlock *>;
310
311 /// SlotIndexes pass.
312 ///
313 /// This pass assigns indexes to each instruction.
314 class SlotIndexes : public MachineFunctionPass {
315 private:
316 // IndexListEntry allocator.
317 BumpPtrAllocator ileAllocator;
318
319 using IndexList = ilist<IndexListEntry>;
320 IndexList indexList;
321
322 MachineFunction *mf;
323
324 using Mi2IndexMap = DenseMap<const MachineInstr *, SlotIndex>;
325 Mi2IndexMap mi2iMap;
326
327 /// MBBRanges - Map MBB number to (start, stop) indexes.
328 SmallVector<std::pair<SlotIndex, SlotIndex>, 8> MBBRanges;
329
330 /// Idx2MBBMap - Sorted list of pairs of index of first instruction
331 /// and MBB id.
332 SmallVector<IdxMBBPair, 8> idx2MBBMap;
333
334 IndexListEntry* createEntry(MachineInstr *mi, unsigned index) {
335 IndexListEntry *entry =
336 static_cast<IndexListEntry *>(ileAllocator.Allocate(
337 sizeof(IndexListEntry), alignof(IndexListEntry)));
338
339 new (entry) IndexListEntry(mi, index);
340
341 return entry;
342 }
343
344 /// Renumber locally after inserting curItr.
345 void renumberIndexes(IndexList::iterator curItr);
346
347 public:
348 static char ID;
349
350 SlotIndexes();
351
352 ~SlotIndexes() override;
353
354 void getAnalysisUsage(AnalysisUsage &au) const override;
355 void releaseMemory() override;
356
357 bool runOnMachineFunction(MachineFunction &fn) override;
358
359 /// Dump the indexes.
360 void dump() const;
361
362 /// Repair indexes after adding and removing instructions.
363 void repairIndexesInRange(MachineBasicBlock *MBB,
364 MachineBasicBlock::iterator Begin,
365 MachineBasicBlock::iterator End);
366
367 /// Returns the zero index for this analysis.
368 SlotIndex getZeroIndex() {
369 assert(indexList.front().getIndex() == 0 && "First index is not 0?")((indexList.front().getIndex() == 0 && "First index is not 0?"
) ? static_cast<void> (0) : __assert_fail ("indexList.front().getIndex() == 0 && \"First index is not 0?\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 369, __PRETTY_FUNCTION__))
;
370 return SlotIndex(&indexList.front(), 0);
371 }
372
373 /// Returns the base index of the last slot in this analysis.
374 SlotIndex getLastIndex() {
375 return SlotIndex(&indexList.back(), 0);
376 }
377
378 /// Returns true if the given machine instr is mapped to an index,
379 /// otherwise returns false.
380 bool hasIndex(const MachineInstr &instr) const {
381 return mi2iMap.count(&instr);
382 }
383
384 /// Returns the base index for the given instruction.
385 SlotIndex getInstructionIndex(const MachineInstr &MI,
386 bool IgnoreBundle = false) const {
387 // Instructions inside a bundle have the same number as the bundle itself.
388 auto BundleStart = getBundleStart(MI.getIterator());
389 auto BundleEnd = getBundleEnd(MI.getIterator());
390 // Use the first non-debug instruction in the bundle to get SlotIndex.
391 const MachineInstr &BundleNonDebug =
392 IgnoreBundle ? MI
393 : *skipDebugInstructionsForward(BundleStart, BundleEnd);
394 assert(!BundleNonDebug.isDebugInstr() &&((!BundleNonDebug.isDebugInstr() && "Could not use a debug instruction to query mi2iMap."
) ? static_cast<void> (0) : __assert_fail ("!BundleNonDebug.isDebugInstr() && \"Could not use a debug instruction to query mi2iMap.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 395, __PRETTY_FUNCTION__))
395 "Could not use a debug instruction to query mi2iMap.")((!BundleNonDebug.isDebugInstr() && "Could not use a debug instruction to query mi2iMap."
) ? static_cast<void> (0) : __assert_fail ("!BundleNonDebug.isDebugInstr() && \"Could not use a debug instruction to query mi2iMap.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 395, __PRETTY_FUNCTION__))
;
396 Mi2IndexMap::const_iterator itr = mi2iMap.find(&BundleNonDebug);
397 assert(itr != mi2iMap.end() && "Instruction not found in maps.")((itr != mi2iMap.end() && "Instruction not found in maps."
) ? static_cast<void> (0) : __assert_fail ("itr != mi2iMap.end() && \"Instruction not found in maps.\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 397, __PRETTY_FUNCTION__))
;
398 return itr->second;
399 }
400
401 /// Returns the instruction for the given index, or null if the given
402 /// index has no instruction associated with it.
403 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
404 return index.isValid() ? index.listEntry()->getInstr() : nullptr;
405 }
406
407 /// Returns the next non-null index, if one exists.
408 /// Otherwise returns getLastIndex().
409 SlotIndex getNextNonNullIndex(SlotIndex Index) {
410 IndexList::iterator I = Index.listEntry()->getIterator();
411 IndexList::iterator E = indexList.end();
412 while (++I != E)
413 if (I->getInstr())
414 return SlotIndex(&*I, Index.getSlot());
415 // We reached the end of the function.
416 return getLastIndex();
417 }
418
419 /// getIndexBefore - Returns the index of the last indexed instruction
420 /// before MI, or the start index of its basic block.
421 /// MI is not required to have an index.
422 SlotIndex getIndexBefore(const MachineInstr &MI) const {
423 const MachineBasicBlock *MBB = MI.getParent();
424 assert(MBB && "MI must be inserted in a basic block")((MBB && "MI must be inserted in a basic block") ? static_cast
<void> (0) : __assert_fail ("MBB && \"MI must be inserted in a basic block\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 424, __PRETTY_FUNCTION__))
;
425 MachineBasicBlock::const_iterator I = MI, B = MBB->begin();
426 while (true) {
427 if (I == B)
428 return getMBBStartIdx(MBB);
429 --I;
430 Mi2IndexMap::const_iterator MapItr = mi2iMap.find(&*I);
431 if (MapItr != mi2iMap.end())
432 return MapItr->second;
433 }
434 }
435
436 /// getIndexAfter - Returns the index of the first indexed instruction
437 /// after MI, or the end index of its basic block.
438 /// MI is not required to have an index.
439 SlotIndex getIndexAfter(const MachineInstr &MI) const {
440 const MachineBasicBlock *MBB = MI.getParent();
441 assert(MBB && "MI must be inserted in a basic block")((MBB && "MI must be inserted in a basic block") ? static_cast
<void> (0) : __assert_fail ("MBB && \"MI must be inserted in a basic block\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 441, __PRETTY_FUNCTION__))
;
442 MachineBasicBlock::const_iterator I = MI, E = MBB->end();
443 while (true) {
444 ++I;
445 if (I == E)
446 return getMBBEndIdx(MBB);
447 Mi2IndexMap::const_iterator MapItr = mi2iMap.find(&*I);
448 if (MapItr != mi2iMap.end())
449 return MapItr->second;
450 }
451 }
452
453 /// Return the (start,end) range of the given basic block number.
454 const std::pair<SlotIndex, SlotIndex> &
455 getMBBRange(unsigned Num) const {
456 return MBBRanges[Num];
457 }
458
459 /// Return the (start,end) range of the given basic block.
460 const std::pair<SlotIndex, SlotIndex> &
461 getMBBRange(const MachineBasicBlock *MBB) const {
462 return getMBBRange(MBB->getNumber());
463 }
464
465 /// Returns the first index in the given basic block number.
466 SlotIndex getMBBStartIdx(unsigned Num) const {
467 return getMBBRange(Num).first;
468 }
469
470 /// Returns the first index in the given basic block.
471 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
472 return getMBBRange(mbb).first;
473 }
474
475 /// Returns the last index in the given basic block number.
476 SlotIndex getMBBEndIdx(unsigned Num) const {
477 return getMBBRange(Num).second;
478 }
479
480 /// Returns the last index in the given basic block.
481 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
482 return getMBBRange(mbb).second;
483 }
484
485 /// Iterator over the idx2MBBMap (sorted pairs of slot index of basic block
486 /// begin and basic block)
487 using MBBIndexIterator = SmallVectorImpl<IdxMBBPair>::const_iterator;
488
489 /// Move iterator to the next IdxMBBPair where the SlotIndex is greater or
490 /// equal to \p To.
491 MBBIndexIterator advanceMBBIndex(MBBIndexIterator I, SlotIndex To) const {
492 return std::partition_point(
493 I, idx2MBBMap.end(),
494 [=](const IdxMBBPair &IM) { return IM.first < To; });
495 }
496
497 /// Get an iterator pointing to the IdxMBBPair with the biggest SlotIndex
498 /// that is greater or equal to \p Idx.
499 MBBIndexIterator findMBBIndex(SlotIndex Idx) const {
500 return advanceMBBIndex(idx2MBBMap.begin(), Idx);
501 }
502
503 /// Returns an iterator for the begin of the idx2MBBMap.
504 MBBIndexIterator MBBIndexBegin() const {
505 return idx2MBBMap.begin();
506 }
507
508 /// Return an iterator for the end of the idx2MBBMap.
509 MBBIndexIterator MBBIndexEnd() const {
510 return idx2MBBMap.end();
511 }
512
513 /// Returns the basic block which the given index falls in.
514 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
515 if (MachineInstr *MI = getInstructionFromIndex(index))
516 return MI->getParent();
517
518 MBBIndexIterator I = findMBBIndex(index);
519 // Take the pair containing the index
520 MBBIndexIterator J =
521 ((I != MBBIndexEnd() && I->first > index) ||
522 (I == MBBIndexEnd() && !idx2MBBMap.empty())) ? std::prev(I) : I;
523
524 assert(J != MBBIndexEnd() && J->first <= index &&((J != MBBIndexEnd() && J->first <= index &&
index < getMBBEndIdx(J->second) && "index does not correspond to an MBB"
) ? static_cast<void> (0) : __assert_fail ("J != MBBIndexEnd() && J->first <= index && index < getMBBEndIdx(J->second) && \"index does not correspond to an MBB\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 526, __PRETTY_FUNCTION__))
525 index < getMBBEndIdx(J->second) &&((J != MBBIndexEnd() && J->first <= index &&
index < getMBBEndIdx(J->second) && "index does not correspond to an MBB"
) ? static_cast<void> (0) : __assert_fail ("J != MBBIndexEnd() && J->first <= index && index < getMBBEndIdx(J->second) && \"index does not correspond to an MBB\""
, "/build/llvm-toolchain-snapshot-12~++20200926111128+c6c5629f2fb/llvm/include/llvm/CodeGen/SlotIndexes.h"
, 526, __PRETTY_FUNCTION__))
526 "index does not correspond to an MBB")((J