Bug Summary

File:llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp
Warning:line 79, column 27
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SIAddIMGInit.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/build-llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/build-llvm/lib/Target/AMDGPU -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2021-01-16-002530-32805-1 -x c++ /build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp

/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp

1//===-- SIAddIMGInit.cpp - Add any required IMG inits ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Any MIMG instructions that use tfe or lwe require an initialization of the
11/// result register that will be written in the case of a memory access failure
12/// The required code is also added to tie this init code to the result of the
13/// img instruction
14///
15//===----------------------------------------------------------------------===//
16//
17
18#include "AMDGPU.h"
19#include "AMDGPUSubtarget.h"
20#include "llvm/CodeGen/MachineFunctionPass.h"
21
22#define DEBUG_TYPE"si-img-init" "si-img-init"
23
24using namespace llvm;
25
26namespace {
27
28class SIAddIMGInit : public MachineFunctionPass {
29public:
30 static char ID;
31
32public:
33 SIAddIMGInit() : MachineFunctionPass(ID) {
34 initializeSIAddIMGInitPass(*PassRegistry::getPassRegistry());
35 }
36
37 bool runOnMachineFunction(MachineFunction &MF) override;
38
39 void getAnalysisUsage(AnalysisUsage &AU) const override {
40 AU.setPreservesCFG();
41 MachineFunctionPass::getAnalysisUsage(AU);
42 }
43};
44
45} // End anonymous namespace.
46
47INITIALIZE_PASS(SIAddIMGInit, DEBUG_TYPE, "SI Add IMG Init", false, false)static void *initializeSIAddIMGInitPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "SI Add IMG Init", "si-img-init"
, &SIAddIMGInit::ID, PassInfo::NormalCtor_t(callDefaultCtor
<SIAddIMGInit>), false, false); Registry.registerPass(*
PI, true); return PI; } static llvm::once_flag InitializeSIAddIMGInitPassFlag
; void llvm::initializeSIAddIMGInitPass(PassRegistry &Registry
) { llvm::call_once(InitializeSIAddIMGInitPassFlag, initializeSIAddIMGInitPassOnce
, std::ref(Registry)); }
48
49char SIAddIMGInit::ID = 0;
50
51char &llvm::SIAddIMGInitID = SIAddIMGInit::ID;
52
53FunctionPass *llvm::createSIAddIMGInitPass() { return new SIAddIMGInit(); }
54
55bool SIAddIMGInit::runOnMachineFunction(MachineFunction &MF) {
56 MachineRegisterInfo &MRI = MF.getRegInfo();
57 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
58 const SIInstrInfo *TII = ST.getInstrInfo();
59 const SIRegisterInfo *RI = ST.getRegisterInfo();
60 bool Changed = false;
61
62 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
1
Calling 'operator!='
4
Returning from 'operator!='
5
Loop condition is true. Entering loop body
63 ++BI) {
64 MachineBasicBlock &MBB = *BI;
65 MachineBasicBlock::iterator I, Next;
66 for (I = MBB.begin(); I != MBB.end(); I = Next) {
6
Calling 'operator!='
15
Returning from 'operator!='
16
Loop condition is true. Entering loop body
67 Next = std::next(I);
68 MachineInstr &MI = *I;
69
70 auto Opcode = MI.getOpcode();
71 if (TII->isMIMG(Opcode) && !MI.mayStore()) {
17
Assuming the condition is true
18
Calling 'MachineInstr::mayStore'
31
Returning from 'MachineInstr::mayStore'
32
Assuming the condition is true
33
Taking true branch
72 MachineOperand *TFE = TII->getNamedOperand(MI, AMDGPU::OpName::tfe);
34
'TFE' initialized here
73 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe);
74 MachineOperand *D16 = TII->getNamedOperand(MI, AMDGPU::OpName::d16);
75
76 if (!TFE && !LWE) // intersect_ray
35
Assuming 'TFE' is null
36
Assuming 'LWE' is non-null
37
Taking false branch
77 continue;
78
79 unsigned TFEVal = TFE->getImm();
38
Called C++ object pointer is null
80 unsigned LWEVal = LWE->getImm();
81 unsigned D16Val = D16 ? D16->getImm() : 0;
82
83 if (TFEVal || LWEVal) {
84 // At least one of TFE or LWE are non-zero
85 // We have to insert a suitable initialization of the result value and
86 // tie this to the dest of the image instruction.
87
88 const DebugLoc &DL = MI.getDebugLoc();
89
90 int DstIdx =
91 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata);
92
93 // Calculate which dword we have to initialize to 0.
94 MachineOperand *MO_Dmask =
95 TII->getNamedOperand(MI, AMDGPU::OpName::dmask);
96
97 // check that dmask operand is found.
98 assert(MO_Dmask && "Expected dmask operand in instruction")((MO_Dmask && "Expected dmask operand in instruction"
) ? static_cast<void> (0) : __assert_fail ("MO_Dmask && \"Expected dmask operand in instruction\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/lib/Target/AMDGPU/SIAddIMGInit.cpp"
, 98, __PRETTY_FUNCTION__))
;
99
100 unsigned dmask = MO_Dmask->getImm();
101 // Determine the number of active lanes taking into account the
102 // Gather4 special case
103 unsigned ActiveLanes =
104 TII->isGather4(Opcode) ? 4 : countPopulation(dmask);
105
106 bool Packed = !ST.hasUnpackedD16VMem();
107
108 unsigned InitIdx =
109 D16Val && Packed ? ((ActiveLanes + 1) >> 1) + 1 : ActiveLanes + 1;
110
111 // Abandon attempt if the dst size isn't large enough
112 // - this is in fact an error but this is picked up elsewhere and
113 // reported correctly.
114 uint32_t DstSize =
115 RI->getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32;
116 if (DstSize < InitIdx)
117 continue;
118
119 // Create a register for the intialization value.
120 Register PrevDst =
121 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
122 unsigned NewDst = 0; // Final initialized value will be in here
123
124 // If PRTStrictNull feature is enabled (the default) then initialize
125 // all the result registers to 0, otherwise just the error indication
126 // register (VGPRn+1)
127 unsigned SizeLeft = ST.usePRTStrictNull() ? InitIdx : 1;
128 unsigned CurrIdx = ST.usePRTStrictNull() ? 0 : (InitIdx - 1);
129
130 if (DstSize == 1) {
131 // In this case we can just initialize the result directly
132 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), PrevDst)
133 .addImm(0);
134 NewDst = PrevDst;
135 } else {
136 BuildMI(MBB, MI, DL, TII->get(AMDGPU::IMPLICIT_DEF), PrevDst);
137 for (; SizeLeft; SizeLeft--, CurrIdx++) {
138 NewDst =
139 MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx));
140 // Initialize dword
141 Register SubReg =
142 MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
143 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), SubReg)
144 .addImm(0);
145 // Insert into the super-reg
146 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewDst)
147 .addReg(PrevDst)
148 .addReg(SubReg)
149 .addImm(SIRegisterInfo::getSubRegFromChannel(CurrIdx));
150
151 PrevDst = NewDst;
152 }
153 }
154
155 // Add as an implicit operand
156 MachineInstrBuilder(MF, MI).addReg(NewDst, RegState::Implicit);
157
158 // Tie the just added implicit operand to the dst
159 MI.tieOperands(DstIdx, MI.getNumOperands() - 1);
160
161 Changed = true;
162 }
163 }
164 }
165 }
166
167 return Changed;
168}

/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/ADT/ilist_iterator.h

1//===- llvm/ADT/ilist_iterator.h - Intrusive List Iterator ------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLVM_ADT_ILIST_ITERATOR_H
10#define LLVM_ADT_ILIST_ITERATOR_H
11
12#include "llvm/ADT/ilist_node.h"
13#include <cassert>
14#include <cstddef>
15#include <iterator>
16#include <type_traits>
17
18namespace llvm {
19
20namespace ilist_detail {
21
22/// Find const-correct node types.
23template <class OptionsT, bool IsConst> struct IteratorTraits;
24template <class OptionsT> struct IteratorTraits<OptionsT, false> {
25 using value_type = typename OptionsT::value_type;
26 using pointer = typename OptionsT::pointer;
27 using reference = typename OptionsT::reference;
28 using node_pointer = ilist_node_impl<OptionsT> *;
29 using node_reference = ilist_node_impl<OptionsT> &;
30};
31template <class OptionsT> struct IteratorTraits<OptionsT, true> {
32 using value_type = const typename OptionsT::value_type;
33 using pointer = typename OptionsT::const_pointer;
34 using reference = typename OptionsT::const_reference;
35 using node_pointer = const ilist_node_impl<OptionsT> *;
36 using node_reference = const ilist_node_impl<OptionsT> &;
37};
38
39template <bool IsReverse> struct IteratorHelper;
40template <> struct IteratorHelper<false> : ilist_detail::NodeAccess {
41 using Access = ilist_detail::NodeAccess;
42
43 template <class T> static void increment(T *&I) { I = Access::getNext(*I); }
44 template <class T> static void decrement(T *&I) { I = Access::getPrev(*I); }
45};
46template <> struct IteratorHelper<true> : ilist_detail::NodeAccess {
47 using Access = ilist_detail::NodeAccess;
48
49 template <class T> static void increment(T *&I) { I = Access::getPrev(*I); }
50 template <class T> static void decrement(T *&I) { I = Access::getNext(*I); }
51};
52
53} // end namespace ilist_detail
54
55/// Iterator for intrusive lists based on ilist_node.
56template <class OptionsT, bool IsReverse, bool IsConst>
57class ilist_iterator : ilist_detail::SpecificNodeAccess<OptionsT> {
58 friend ilist_iterator<OptionsT, IsReverse, !IsConst>;
59 friend ilist_iterator<OptionsT, !IsReverse, IsConst>;
60 friend ilist_iterator<OptionsT, !IsReverse, !IsConst>;
61
62 using Traits = ilist_detail::IteratorTraits<OptionsT, IsConst>;
63 using Access = ilist_detail::SpecificNodeAccess<OptionsT>;
64
65public:
66 using value_type = typename Traits::value_type;
67 using pointer = typename Traits::pointer;
68 using reference = typename Traits::reference;
69 using difference_type = ptrdiff_t;
70 using iterator_category = std::bidirectional_iterator_tag;
71 using const_pointer = typename OptionsT::const_pointer;
72 using const_reference = typename OptionsT::const_reference;
73
74private:
75 using node_pointer = typename Traits::node_pointer;
76 using node_reference = typename Traits::node_reference;
77
78 node_pointer NodePtr = nullptr;
79
80public:
81 /// Create from an ilist_node.
82 explicit ilist_iterator(node_reference N) : NodePtr(&N) {}
83
84 explicit ilist_iterator(pointer NP) : NodePtr(Access::getNodePtr(NP)) {}
85 explicit ilist_iterator(reference NR) : NodePtr(Access::getNodePtr(&NR)) {}
86 ilist_iterator() = default;
87
88 // This is templated so that we can allow constructing a const iterator from
89 // a nonconst iterator...
90 template <bool RHSIsConst>
91 ilist_iterator(const ilist_iterator<OptionsT, IsReverse, RHSIsConst> &RHS,
92 std::enable_if_t<IsConst || !RHSIsConst, void *> = nullptr)
93 : NodePtr(RHS.NodePtr) {}
94
95 // This is templated so that we can allow assigning to a const iterator from
96 // a nonconst iterator...
97 template <bool RHSIsConst>
98 std::enable_if_t<IsConst || !RHSIsConst, ilist_iterator &>
99 operator=(const ilist_iterator<OptionsT, IsReverse, RHSIsConst> &RHS) {
100 NodePtr = RHS.NodePtr;
101 return *this;
102 }
103
104 /// Explicit conversion between forward/reverse iterators.
105 ///
106 /// Translate between forward and reverse iterators without changing range
107 /// boundaries. The resulting iterator will dereference (and have a handle)
108 /// to the previous node, which is somewhat unexpected; but converting the
109 /// two endpoints in a range will give the same range in reverse.
110 ///
111 /// This matches std::reverse_iterator conversions.
112 explicit ilist_iterator(
113 const ilist_iterator<OptionsT, !IsReverse, IsConst> &RHS)
114 : ilist_iterator(++RHS.getReverse()) {}
115
116 /// Get a reverse iterator to the same node.
117 ///
118 /// Gives a reverse iterator that will dereference (and have a handle) to the
119 /// same node. Converting the endpoint iterators in a range will give a
120 /// different range; for range operations, use the explicit conversions.
121 ilist_iterator<OptionsT, !IsReverse, IsConst> getReverse() const {
122 if (NodePtr)
123 return ilist_iterator<OptionsT, !IsReverse, IsConst>(*NodePtr);
124 return ilist_iterator<OptionsT, !IsReverse, IsConst>();
125 }
126
127 /// Const-cast.
128 ilist_iterator<OptionsT, IsReverse, false> getNonConst() const {
129 if (NodePtr)
130 return ilist_iterator<OptionsT, IsReverse, false>(
131 const_cast<typename ilist_iterator<OptionsT, IsReverse,
132 false>::node_reference>(*NodePtr));
133 return ilist_iterator<OptionsT, IsReverse, false>();
134 }
135
136 // Accessors...
137 reference operator*() const {
138 assert(!NodePtr->isKnownSentinel())((!NodePtr->isKnownSentinel()) ? static_cast<void> (
0) : __assert_fail ("!NodePtr->isKnownSentinel()", "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/ADT/ilist_iterator.h"
, 138, __PRETTY_FUNCTION__))
;
139 return *Access::getValuePtr(NodePtr);
140 }
141 pointer operator->() const { return &operator*(); }
142
143 // Comparison operators
144 friend bool operator==(const ilist_iterator &LHS, const ilist_iterator &RHS) {
145 return LHS.NodePtr == RHS.NodePtr;
9
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'
10
Returning zero, which participates in a condition later
146 }
147 friend bool operator!=(const ilist_iterator &LHS, const ilist_iterator &RHS) {
148 return LHS.NodePtr != RHS.NodePtr;
2
Assuming 'LHS.NodePtr' is not equal to 'RHS.NodePtr'
3
Returning the value 1, which participates in a condition later
149 }
150
151 // Increment and decrement operators...
152 ilist_iterator &operator--() {
153 NodePtr = IsReverse ? NodePtr->getNext() : NodePtr->getPrev();
154 return *this;
155 }
156 ilist_iterator &operator++() {
157 NodePtr = IsReverse ? NodePtr->getPrev() : NodePtr->getNext();
158 return *this;
159 }
160 ilist_iterator operator--(int) {
161 ilist_iterator tmp = *this;
162 --*this;
163 return tmp;
164 }
165 ilist_iterator operator++(int) {
166 ilist_iterator tmp = *this;
167 ++*this;
168 return tmp;
169 }
170
171 /// Get the underlying ilist_node.
172 node_pointer getNodePtr() const { return static_cast<node_pointer>(NodePtr); }
173
174 /// Check for end. Only valid if ilist_sentinel_tracking<true>.
175 bool isEnd() const { return NodePtr ? NodePtr->isSentinel() : false; }
176};
177
178template <typename From> struct simplify_type;
179
180/// Allow ilist_iterators to convert into pointers to a node automatically when
181/// used by the dyn_cast, cast, isa mechanisms...
182///
183/// FIXME: remove this, since there is no implicit conversion to NodeTy.
184template <class OptionsT, bool IsConst>
185struct simplify_type<ilist_iterator<OptionsT, false, IsConst>> {
186 using iterator = ilist_iterator<OptionsT, false, IsConst>;
187 using SimpleType = typename iterator::pointer;
188
189 static SimpleType getSimplifiedValue(const iterator &Node) { return &*Node; }
190};
191template <class OptionsT, bool IsConst>
192struct simplify_type<const ilist_iterator<OptionsT, false, IsConst>>
193 : simplify_type<ilist_iterator<OptionsT, false, IsConst>> {};
194
195} // end namespace llvm
196
197#endif // LLVM_ADT_ILIST_ITERATOR_H

/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h

1//===- llvm/CodeGen/MachineInstrBundleIterator.h ----------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Defines an iterator class that bundles MachineInstr.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H
14#define LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H
15
16#include "llvm/ADT/ilist.h"
17#include "llvm/ADT/simple_ilist.h"
18#include <cassert>
19#include <iterator>
20#include <type_traits>
21
22namespace llvm {
23
24template <class T, bool IsReverse> struct MachineInstrBundleIteratorTraits;
25template <class T> struct MachineInstrBundleIteratorTraits<T, false> {
26 using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
27 using instr_iterator = typename list_type::iterator;
28 using nonconst_instr_iterator = typename list_type::iterator;
29 using const_instr_iterator = typename list_type::const_iterator;
30};
31template <class T> struct MachineInstrBundleIteratorTraits<T, true> {
32 using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
33 using instr_iterator = typename list_type::reverse_iterator;
34 using nonconst_instr_iterator = typename list_type::reverse_iterator;
35 using const_instr_iterator = typename list_type::const_reverse_iterator;
36};
37template <class T> struct MachineInstrBundleIteratorTraits<const T, false> {
38 using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
39 using instr_iterator = typename list_type::const_iterator;
40 using nonconst_instr_iterator = typename list_type::iterator;
41 using const_instr_iterator = typename list_type::const_iterator;
42};
43template <class T> struct MachineInstrBundleIteratorTraits<const T, true> {
44 using list_type = simple_ilist<T, ilist_sentinel_tracking<true>>;
45 using instr_iterator = typename list_type::const_reverse_iterator;
46 using nonconst_instr_iterator = typename list_type::reverse_iterator;
47 using const_instr_iterator = typename list_type::const_reverse_iterator;
48};
49
50template <bool IsReverse> struct MachineInstrBundleIteratorHelper;
51template <> struct MachineInstrBundleIteratorHelper<false> {
52 /// Get the beginning of the current bundle.
53 template <class Iterator> static Iterator getBundleBegin(Iterator I) {
54 if (!I.isEnd())
55 while (I->isBundledWithPred())
56 --I;
57 return I;
58 }
59
60 /// Get the final node of the current bundle.
61 template <class Iterator> static Iterator getBundleFinal(Iterator I) {
62 if (!I.isEnd())
63 while (I->isBundledWithSucc())
64 ++I;
65 return I;
66 }
67
68 /// Increment forward ilist iterator.
69 template <class Iterator> static void increment(Iterator &I) {
70 I = std::next(getBundleFinal(I));
71 }
72
73 /// Decrement forward ilist iterator.
74 template <class Iterator> static void decrement(Iterator &I) {
75 I = getBundleBegin(std::prev(I));
76 }
77};
78
79template <> struct MachineInstrBundleIteratorHelper<true> {
80 /// Get the beginning of the current bundle.
81 template <class Iterator> static Iterator getBundleBegin(Iterator I) {
82 return MachineInstrBundleIteratorHelper<false>::getBundleBegin(
83 I.getReverse())
84 .getReverse();
85 }
86
87 /// Get the final node of the current bundle.
88 template <class Iterator> static Iterator getBundleFinal(Iterator I) {
89 return MachineInstrBundleIteratorHelper<false>::getBundleFinal(
90 I.getReverse())
91 .getReverse();
92 }
93
94 /// Increment reverse ilist iterator.
95 template <class Iterator> static void increment(Iterator &I) {
96 I = getBundleBegin(std::next(I));
97 }
98
99 /// Decrement reverse ilist iterator.
100 template <class Iterator> static void decrement(Iterator &I) {
101 I = std::prev(getBundleFinal(I));
102 }
103};
104
105/// MachineBasicBlock iterator that automatically skips over MIs that are
106/// inside bundles (i.e. walk top level MIs only).
107template <typename Ty, bool IsReverse = false>
108class MachineInstrBundleIterator : MachineInstrBundleIteratorHelper<IsReverse> {
109 using Traits = MachineInstrBundleIteratorTraits<Ty, IsReverse>;
110 using instr_iterator = typename Traits::instr_iterator;
111
112 instr_iterator MII;
113
114public:
115 using value_type = typename instr_iterator::value_type;
116 using difference_type = typename instr_iterator::difference_type;
117 using pointer = typename instr_iterator::pointer;
118 using reference = typename instr_iterator::reference;
119 using const_pointer = typename instr_iterator::const_pointer;
120 using const_reference = typename instr_iterator::const_reference;
121 using iterator_category = std::bidirectional_iterator_tag;
122
123private:
124 using nonconst_instr_iterator = typename Traits::nonconst_instr_iterator;
125 using const_instr_iterator = typename Traits::const_instr_iterator;
126 using nonconst_iterator =
127 MachineInstrBundleIterator<typename nonconst_instr_iterator::value_type,
128 IsReverse>;
129 using reverse_iterator = MachineInstrBundleIterator<Ty, !IsReverse>;
130
131public:
132 MachineInstrBundleIterator(instr_iterator MI) : MII(MI) {
133 assert((!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) &&(((!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred
()) && "It's not legal to initialize MachineInstrBundleIterator with a "
"bundled MI") ? static_cast<void> (0) : __assert_fail (
"(!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) && \"It's not legal to initialize MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 135, __PRETTY_FUNCTION__))
134 "It's not legal to initialize MachineInstrBundleIterator with a "(((!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred
()) && "It's not legal to initialize MachineInstrBundleIterator with a "
"bundled MI") ? static_cast<void> (0) : __assert_fail (
"(!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) && \"It's not legal to initialize MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 135, __PRETTY_FUNCTION__))
135 "bundled MI")(((!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred
()) && "It's not legal to initialize MachineInstrBundleIterator with a "
"bundled MI") ? static_cast<void> (0) : __assert_fail (
"(!MI.getNodePtr() || MI.isEnd() || !MI->isBundledWithPred()) && \"It's not legal to initialize MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 135, __PRETTY_FUNCTION__))
;
136 }
137
138 MachineInstrBundleIterator(reference MI) : MII(MI) {
139 assert(!MI.isBundledWithPred() && "It's not legal to initialize "((!MI.isBundledWithPred() && "It's not legal to initialize "
"MachineInstrBundleIterator with a " "bundled MI") ? static_cast
<void> (0) : __assert_fail ("!MI.isBundledWithPred() && \"It's not legal to initialize \" \"MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 141, __PRETTY_FUNCTION__))
140 "MachineInstrBundleIterator with a "((!MI.isBundledWithPred() && "It's not legal to initialize "
"MachineInstrBundleIterator with a " "bundled MI") ? static_cast
<void> (0) : __assert_fail ("!MI.isBundledWithPred() && \"It's not legal to initialize \" \"MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 141, __PRETTY_FUNCTION__))
141 "bundled MI")((!MI.isBundledWithPred() && "It's not legal to initialize "
"MachineInstrBundleIterator with a " "bundled MI") ? static_cast
<void> (0) : __assert_fail ("!MI.isBundledWithPred() && \"It's not legal to initialize \" \"MachineInstrBundleIterator with a \" \"bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 141, __PRETTY_FUNCTION__))
;
142 }
143
144 MachineInstrBundleIterator(pointer MI) : MII(MI) {
145 // FIXME: This conversion should be explicit.
146 assert((!MI || !MI->isBundledWithPred()) && "It's not legal to initialize "(((!MI || !MI->isBundledWithPred()) && "It's not legal to initialize "
"MachineInstrBundleIterator " "with a bundled MI") ? static_cast
<void> (0) : __assert_fail ("(!MI || !MI->isBundledWithPred()) && \"It's not legal to initialize \" \"MachineInstrBundleIterator \" \"with a bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 148, __PRETTY_FUNCTION__))
147 "MachineInstrBundleIterator "(((!MI || !MI->isBundledWithPred()) && "It's not legal to initialize "
"MachineInstrBundleIterator " "with a bundled MI") ? static_cast
<void> (0) : __assert_fail ("(!MI || !MI->isBundledWithPred()) && \"It's not legal to initialize \" \"MachineInstrBundleIterator \" \"with a bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 148, __PRETTY_FUNCTION__))
148 "with a bundled MI")(((!MI || !MI->isBundledWithPred()) && "It's not legal to initialize "
"MachineInstrBundleIterator " "with a bundled MI") ? static_cast
<void> (0) : __assert_fail ("(!MI || !MI->isBundledWithPred()) && \"It's not legal to initialize \" \"MachineInstrBundleIterator \" \"with a bundled MI\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstrBundleIterator.h"
, 148, __PRETTY_FUNCTION__))
;
149 }
150
151 // Template allows conversion from const to nonconst.
152 template <class OtherTy>
153 MachineInstrBundleIterator(
154 const MachineInstrBundleIterator<OtherTy, IsReverse> &I,
155 std::enable_if_t<std::is_convertible<OtherTy *, Ty *>::value, void *> =
156 nullptr)
157 : MII(I.getInstrIterator()) {}
158
159 MachineInstrBundleIterator() : MII(nullptr) {}
160
161 /// Explicit conversion between forward/reverse iterators.
162 ///
163 /// Translate between forward and reverse iterators without changing range
164 /// boundaries. The resulting iterator will dereference (and have a handle)
165 /// to the previous node, which is somewhat unexpected; but converting the
166 /// two endpoints in a range will give the same range in reverse.
167 ///
168 /// This matches std::reverse_iterator conversions.
169 explicit MachineInstrBundleIterator(
170 const MachineInstrBundleIterator<Ty, !IsReverse> &I)
171 : MachineInstrBundleIterator(++I.getReverse()) {}
172
173 /// Get the bundle iterator for the given instruction's bundle.
174 static MachineInstrBundleIterator getAtBundleBegin(instr_iterator MI) {
175 return MachineInstrBundleIteratorHelper<IsReverse>::getBundleBegin(MI);
176 }
177
178 reference operator*() const { return *MII; }
179 pointer operator->() const { return &operator*(); }
180
181 /// Check for null.
182 bool isValid() const { return MII.getNodePtr(); }
183
184 friend bool operator==(const MachineInstrBundleIterator &L,
185 const MachineInstrBundleIterator &R) {
186 return L.MII == R.MII;
8
Calling 'operator=='
11
Returning from 'operator=='
12
Returning zero, which participates in a condition later
187 }
188 friend bool operator==(const MachineInstrBundleIterator &L,
189 const const_instr_iterator &R) {
190 return L.MII == R; // Avoid assertion about validity of R.
191 }
192 friend bool operator==(const const_instr_iterator &L,
193 const MachineInstrBundleIterator &R) {
194 return L == R.MII; // Avoid assertion about validity of L.
195 }
196 friend bool operator==(const MachineInstrBundleIterator &L,
197 const nonconst_instr_iterator &R) {
198 return L.MII == R; // Avoid assertion about validity of R.
199 }
200 friend bool operator==(const nonconst_instr_iterator &L,
201 const MachineInstrBundleIterator &R) {
202 return L == R.MII; // Avoid assertion about validity of L.
203 }
204 friend bool operator==(const MachineInstrBundleIterator &L, const_pointer R) {
205 return L == const_instr_iterator(R); // Avoid assertion about validity of R.
206 }
207 friend bool operator==(const_pointer L, const MachineInstrBundleIterator &R) {
208 return const_instr_iterator(L) == R; // Avoid assertion about validity of L.
209 }
210 friend bool operator==(const MachineInstrBundleIterator &L,
211 const_reference R) {
212 return L == &R; // Avoid assertion about validity of R.
213 }
214 friend bool operator==(const_reference L,
215 const MachineInstrBundleIterator &R) {
216 return &L == R; // Avoid assertion about validity of L.
217 }
218
219 friend bool operator!=(const MachineInstrBundleIterator &L,
220 const MachineInstrBundleIterator &R) {
221 return !(L == R);
7
Calling 'operator=='
13
Returning from 'operator=='
14
Returning the value 1, which participates in a condition later
222 }
223 friend bool operator!=(const MachineInstrBundleIterator &L,
224 const const_instr_iterator &R) {
225 return !(L == R);
226 }
227 friend bool operator!=(const const_instr_iterator &L,
228 const MachineInstrBundleIterator &R) {
229 return !(L == R);
230 }
231 friend bool operator!=(const MachineInstrBundleIterator &L,
232 const nonconst_instr_iterator &R) {
233 return !(L == R);
234 }
235 friend bool operator!=(const nonconst_instr_iterator &L,
236 const MachineInstrBundleIterator &R) {
237 return !(L == R);
238 }
239 friend bool operator!=(const MachineInstrBundleIterator &L, const_pointer R) {
240 return !(L == R);
241 }
242 friend bool operator!=(const_pointer L, const MachineInstrBundleIterator &R) {
243 return !(L == R);
244 }
245 friend bool operator!=(const MachineInstrBundleIterator &L,
246 const_reference R) {
247 return !(L == R);
248 }
249 friend bool operator!=(const_reference L,
250 const MachineInstrBundleIterator &R) {
251 return !(L == R);
252 }
253
254 // Increment and decrement operators...
255 MachineInstrBundleIterator &operator--() {
256 this->decrement(MII);
257 return *this;
258 }
259 MachineInstrBundleIterator &operator++() {
260 this->increment(MII);
261 return *this;
262 }
263 MachineInstrBundleIterator operator--(int) {
264 MachineInstrBundleIterator Temp = *this;
265 --*this;
266 return Temp;
267 }
268 MachineInstrBundleIterator operator++(int) {
269 MachineInstrBundleIterator Temp = *this;
270 ++*this;
271 return Temp;
272 }
273
274 instr_iterator getInstrIterator() const { return MII; }
275
276 nonconst_iterator getNonConstIterator() const { return MII.getNonConst(); }
277
278 /// Get a reverse iterator to the same node.
279 ///
280 /// Gives a reverse iterator that will dereference (and have a handle) to the
281 /// same node. Converting the endpoint iterators in a range will give a
282 /// different range; for range operations, use the explicit conversions.
283 reverse_iterator getReverse() const { return MII.getReverse(); }
284};
285
286} // end namespace llvm
287
288#endif // LLVM_CODEGEN_MACHINEINSTRBUNDLEITERATOR_H

/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h

1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
18#include "llvm/ADT/DenseMapInfo.h"
19#include "llvm/ADT/PointerSumType.h"
20#include "llvm/ADT/ilist.h"
21#include "llvm/ADT/ilist_node.h"
22#include "llvm/ADT/iterator_range.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineOperand.h"
25#include "llvm/CodeGen/TargetOpcodes.h"
26#include "llvm/IR/DebugLoc.h"
27#include "llvm/IR/InlineAsm.h"
28#include "llvm/MC/MCInstrDesc.h"
29#include "llvm/MC/MCSymbol.h"
30#include "llvm/Support/ArrayRecycler.h"
31#include "llvm/Support/TrailingObjects.h"
32#include <algorithm>
33#include <cassert>
34#include <cstdint>
35#include <utility>
36
37namespace llvm {
38
39class AAResults;
40template <typename T> class ArrayRef;
41class DIExpression;
42class DILocalVariable;
43class MachineBasicBlock;
44class MachineFunction;
45class MachineRegisterInfo;
46class ModuleSlotTracker;
47class raw_ostream;
48template <typename T> class SmallVectorImpl;
49class SmallBitVector;
50class StringRef;
51class TargetInstrInfo;
52class TargetRegisterClass;
53class TargetRegisterInfo;
54
55//===----------------------------------------------------------------------===//
56/// Representation of each machine instruction.
57///
58/// This class isn't a POD type, but it must have a trivial destructor. When a
59/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
60/// without having their destructor called.
61///
62class MachineInstr
63 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
64 ilist_sentinel_tracking<true>> {
65public:
66 using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
67
68 /// Flags to specify different kinds of comments to output in
69 /// assembly code. These flags carry semantic information not
70 /// otherwise easily derivable from the IR text.
71 ///
72 enum CommentFlag {
73 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
74 NoSchedComment = 0x2,
75 TAsmComments = 0x4 // Target Asm comments should start from this value.
76 };
77
78 enum MIFlag {
79 NoFlags = 0,
80 FrameSetup = 1 << 0, // Instruction is used as a part of
81 // function frame setup code.
82 FrameDestroy = 1 << 1, // Instruction is used as a part of
83 // function frame destruction code.
84 BundledPred = 1 << 2, // Instruction has bundled predecessors.
85 BundledSucc = 1 << 3, // Instruction has bundled successors.
86 FmNoNans = 1 << 4, // Instruction does not support Fast
87 // math nan values.
88 FmNoInfs = 1 << 5, // Instruction does not support Fast
89 // math infinity values.
90 FmNsz = 1 << 6, // Instruction is not required to retain
91 // signed zero values.
92 FmArcp = 1 << 7, // Instruction supports Fast math
93 // reciprocal approximations.
94 FmContract = 1 << 8, // Instruction supports Fast math
95 // contraction operations like fma.
96 FmAfn = 1 << 9, // Instruction may map to Fast math
97 // instrinsic approximation.
98 FmReassoc = 1 << 10, // Instruction supports Fast math
99 // reassociation of operand order.
100 NoUWrap = 1 << 11, // Instruction supports binary operator
101 // no unsigned wrap.
102 NoSWrap = 1 << 12, // Instruction supports binary operator
103 // no signed wrap.
104 IsExact = 1 << 13, // Instruction supports division is
105 // known to be exact.
106 NoFPExcept = 1 << 14, // Instruction does not raise
107 // floatint-point exceptions.
108 NoMerge = 1 << 15, // Passes that drop source location info
109 // (e.g. branch folding) should skip
110 // this instruction.
111 };
112
113private:
114 const MCInstrDesc *MCID; // Instruction descriptor.
115 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
116
117 // Operands are allocated by an ArrayRecycler.
118 MachineOperand *Operands = nullptr; // Pointer to the first operand.
119 unsigned NumOperands = 0; // Number of operands on instruction.
120
121 uint16_t Flags = 0; // Various bits of additional
122 // information about machine
123 // instruction.
124
125 uint8_t AsmPrinterFlags = 0; // Various bits of information used by
126 // the AsmPrinter to emit helpful
127 // comments. This is *not* semantic
128 // information. Do not use this for
129 // anything other than to convey comment
130 // information to AsmPrinter.
131
132 // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags
133 // to properly pack.
134 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
135 OperandCapacity CapOperands; // Capacity of the Operands array.
136
137 /// Internal implementation detail class that provides out-of-line storage for
138 /// extra info used by the machine instruction when this info cannot be stored
139 /// in-line within the instruction itself.
140 ///
141 /// This has to be defined eagerly due to the implementation constraints of
142 /// `PointerSumType` where it is used.
143 class ExtraInfo final
144 : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> {
145 public:
146 static ExtraInfo *create(BumpPtrAllocator &Allocator,
147 ArrayRef<MachineMemOperand *> MMOs,
148 MCSymbol *PreInstrSymbol = nullptr,
149 MCSymbol *PostInstrSymbol = nullptr,
150 MDNode *HeapAllocMarker = nullptr) {
151 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
152 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
153 bool HasHeapAllocMarker = HeapAllocMarker != nullptr;
154 auto *Result = new (Allocator.Allocate(
155 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>(
156 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol,
157 HasHeapAllocMarker),
158 alignof(ExtraInfo)))
159 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol,
160 HasHeapAllocMarker);
161
162 // Copy the actual data into the trailing objects.
163 std::copy(MMOs.begin(), MMOs.end(),
164 Result->getTrailingObjects<MachineMemOperand *>());
165
166 if (HasPreInstrSymbol)
167 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
168 if (HasPostInstrSymbol)
169 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
170 PostInstrSymbol;
171 if (HasHeapAllocMarker)
172 Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker;
173
174 return Result;
175 }
176
177 ArrayRef<MachineMemOperand *> getMMOs() const {
178 return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
179 }
180
181 MCSymbol *getPreInstrSymbol() const {
182 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
183 }
184
185 MCSymbol *getPostInstrSymbol() const {
186 return HasPostInstrSymbol
187 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
188 : nullptr;
189 }
190
191 MDNode *getHeapAllocMarker() const {
192 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr;
193 }
194
195 private:
196 friend TrailingObjects;
197
198 // Description of the extra info, used to interpret the actual optional
199 // data appended.
200 //
201 // Note that this is not terribly space optimized. This leaves a great deal
202 // of flexibility to fit more in here later.
203 const int NumMMOs;
204 const bool HasPreInstrSymbol;
205 const bool HasPostInstrSymbol;
206 const bool HasHeapAllocMarker;
207
208 // Implement the `TrailingObjects` internal API.
209 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
210 return NumMMOs;
211 }
212 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
213 return HasPreInstrSymbol + HasPostInstrSymbol;
214 }
215 size_t numTrailingObjects(OverloadToken<MDNode *>) const {
216 return HasHeapAllocMarker;
217 }
218
219 // Just a boring constructor to allow us to initialize the sizes. Always use
220 // the `create` routine above.
221 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol,
222 bool HasHeapAllocMarker)
223 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
224 HasPostInstrSymbol(HasPostInstrSymbol),
225 HasHeapAllocMarker(HasHeapAllocMarker) {}
226 };
227
228 /// Enumeration of the kinds of inline extra info available. It is important
229 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
230 /// it accessible as an `ArrayRef`.
231 enum ExtraInfoInlineKinds {
232 EIIK_MMO = 0,
233 EIIK_PreInstrSymbol,
234 EIIK_PostInstrSymbol,
235 EIIK_OutOfLine
236 };
237
238 // We store extra information about the instruction here. The common case is
239 // expected to be nothing or a single pointer (typically a MMO or a symbol).
240 // We work to optimize this common case by storing it inline here rather than
241 // requiring a separate allocation, but we fall back to an allocation when
242 // multiple pointers are needed.
243 PointerSumType<ExtraInfoInlineKinds,
244 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
245 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
246 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
247 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
248 Info;
249
250 DebugLoc debugLoc; // Source line information.
251
252 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values
253 /// defined by this instruction.
254 unsigned DebugInstrNum;
255
256 // Intrusive list support
257 friend struct ilist_traits<MachineInstr>;
258 friend struct ilist_callback_traits<MachineBasicBlock>;
259 void setParent(MachineBasicBlock *P) { Parent = P; }
260
261 /// This constructor creates a copy of the given
262 /// MachineInstr in the given MachineFunction.
263 MachineInstr(MachineFunction &, const MachineInstr &);
264
265 /// This constructor create a MachineInstr and add the implicit operands.
266 /// It reserves space for number of operands specified by
267 /// MCInstrDesc. An explicit DebugLoc is supplied.
268 MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
269 bool NoImp = false);
270
271 // MachineInstrs are pool-allocated and owned by MachineFunction.
272 friend class MachineFunction;
273
274 void
275 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth,
276 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const;
277
278public:
279 MachineInstr(const MachineInstr &) = delete;
280 MachineInstr &operator=(const MachineInstr &) = delete;
281 // Use MachineFunction::DeleteMachineInstr() instead.
282 ~MachineInstr() = delete;
283
284 const MachineBasicBlock* getParent() const { return Parent; }
285 MachineBasicBlock* getParent() { return Parent; }
286
287 /// Move the instruction before \p MovePos.
288 void moveBefore(MachineInstr *MovePos);
289
290 /// Return the function that contains the basic block that this instruction
291 /// belongs to.
292 ///
293 /// Note: this is undefined behaviour if the instruction does not have a
294 /// parent.
295 const MachineFunction *getMF() const;
296 MachineFunction *getMF() {
297 return const_cast<MachineFunction *>(
298 static_cast<const MachineInstr *>(this)->getMF());
299 }
300
301 /// Return the asm printer flags bitvector.
302 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
303
304 /// Clear the AsmPrinter bitvector.
305 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
306
307 /// Return whether an AsmPrinter flag is set.
308 bool getAsmPrinterFlag(CommentFlag Flag) const {
309 return AsmPrinterFlags & Flag;
310 }
311
312 /// Set a flag for the AsmPrinter.
313 void setAsmPrinterFlag(uint8_t Flag) {
314 AsmPrinterFlags |= Flag;
315 }
316
317 /// Clear specific AsmPrinter flags.
318 void clearAsmPrinterFlag(CommentFlag Flag) {
319 AsmPrinterFlags &= ~Flag;
320 }
321
322 /// Return the MI flags bitvector.
323 uint16_t getFlags() const {
324 return Flags;
325 }
326
327 /// Return whether an MI flag is set.
328 bool getFlag(MIFlag Flag) const {
329 return Flags & Flag;
330 }
331
332 /// Set a MI flag.
333 void setFlag(MIFlag Flag) {
334 Flags |= (uint16_t)Flag;
335 }
336
337 void setFlags(unsigned flags) {
338 // Filter out the automatically maintained flags.
339 unsigned Mask = BundledPred | BundledSucc;
340 Flags = (Flags & Mask) | (flags & ~Mask);
341 }
342
343 /// clearFlag - Clear a MI flag.
344 void clearFlag(MIFlag Flag) {
345 Flags &= ~((uint16_t)Flag);
346 }
347
348 /// Return true if MI is in a bundle (but not the first MI in a bundle).
349 ///
350 /// A bundle looks like this before it's finalized:
351 /// ----------------
352 /// | MI |
353 /// ----------------
354 /// |
355 /// ----------------
356 /// | MI * |
357 /// ----------------
358 /// |
359 /// ----------------
360 /// | MI * |
361 /// ----------------
362 /// In this case, the first MI starts a bundle but is not inside a bundle, the
363 /// next 2 MIs are considered "inside" the bundle.
364 ///
365 /// After a bundle is finalized, it looks like this:
366 /// ----------------
367 /// | Bundle |
368 /// ----------------
369 /// |
370 /// ----------------
371 /// | MI * |
372 /// ----------------
373 /// |
374 /// ----------------
375 /// | MI * |
376 /// ----------------
377 /// |
378 /// ----------------
379 /// | MI * |
380 /// ----------------
381 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
382 /// a bundle, but the next three MIs are.
383 bool isInsideBundle() const {
384 return getFlag(BundledPred);
385 }
386
387 /// Return true if this instruction part of a bundle. This is true
388 /// if either itself or its following instruction is marked "InsideBundle".
389 bool isBundled() const {
390 return isBundledWithPred() || isBundledWithSucc();
391 }
392
393 /// Return true if this instruction is part of a bundle, and it is not the
394 /// first instruction in the bundle.
395 bool isBundledWithPred() const { return getFlag(BundledPred); }
396
397 /// Return true if this instruction is part of a bundle, and it is not the
398 /// last instruction in the bundle.
399 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
400
401 /// Bundle this instruction with its predecessor. This can be an unbundled
402 /// instruction, or it can be the first instruction in a bundle.
403 void bundleWithPred();
404
405 /// Bundle this instruction with its successor. This can be an unbundled
406 /// instruction, or it can be the last instruction in a bundle.
407 void bundleWithSucc();
408
409 /// Break bundle above this instruction.
410 void unbundleFromPred();
411
412 /// Break bundle below this instruction.
413 void unbundleFromSucc();
414
415 /// Returns the debug location id of this MachineInstr.
416 const DebugLoc &getDebugLoc() const { return debugLoc; }
417
418 /// Return the operand containing the offset to be used if this DBG_VALUE
419 /// instruction is indirect; will be an invalid register if this value is
420 /// not indirect, and an immediate with value 0 otherwise.
421 const MachineOperand &getDebugOffset() const {
422 assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast<
void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 422, __PRETTY_FUNCTION__))
;
423 return getOperand(1);
424 }
425 MachineOperand &getDebugOffset() {
426 assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast<
void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 426, __PRETTY_FUNCTION__))
;
427 return getOperand(1);
428 }
429
430 /// Return the operand for the debug variable referenced by
431 /// this DBG_VALUE instruction.
432 const MachineOperand &getDebugVariableOp() const;
433 MachineOperand &getDebugVariableOp();
434
435 /// Return the debug variable referenced by
436 /// this DBG_VALUE instruction.
437 const DILocalVariable *getDebugVariable() const;
438
439 /// Return the operand for the complex address expression referenced by
440 /// this DBG_VALUE instruction.
441 MachineOperand &getDebugExpressionOp();
442
443 /// Return the complex address expression referenced by
444 /// this DBG_VALUE instruction.
445 const DIExpression *getDebugExpression() const;
446
447 /// Return the debug label referenced by
448 /// this DBG_LABEL instruction.
449 const DILabel *getDebugLabel() const;
450
451 /// Fetch the instruction number of this MachineInstr. If it does not have
452 /// one already, a new and unique number will be assigned.
453 unsigned getDebugInstrNum();
454
455 /// Examine the instruction number of this MachineInstr. May be zero if
456 /// it hasn't been assigned a number yet.
457 unsigned peekDebugInstrNum() const { return DebugInstrNum; }
458
459 /// Set instruction number of this MachineInstr. Avoid using unless you're
460 /// deserializing this information.
461 void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
462
463 /// Emit an error referring to the source location of this instruction.
464 /// This should only be used for inline assembly that is somehow
465 /// impossible to compile. Other errors should have been handled much
466 /// earlier.
467 ///
468 /// If this method returns, the caller should try to recover from the error.
469 void emitError(StringRef Msg) const;
470
471 /// Returns the target instruction descriptor of this MachineInstr.
472 const MCInstrDesc &getDesc() const { return *MCID; }
473
474 /// Returns the opcode of this MachineInstr.
475 unsigned getOpcode() const { return MCID->Opcode; }
476
477 /// Retuns the total number of operands.
478 unsigned getNumOperands() const { return NumOperands; }
479
480 /// Returns the total number of operands which are debug locations.
481 unsigned getNumDebugOperands() const {
482 return std::distance(debug_operands().begin(), debug_operands().end());
483 }
484
485 const MachineOperand& getOperand(unsigned i) const {
486 assert(i < getNumOperands() && "getOperand() out of range!")((i < getNumOperands() && "getOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 486, __PRETTY_FUNCTION__))
;
487 return Operands[i];
488 }
489 MachineOperand& getOperand(unsigned i) {
490 assert(i < getNumOperands() && "getOperand() out of range!")((i < getNumOperands() && "getOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 490, __PRETTY_FUNCTION__))
;
491 return Operands[i];
492 }
493
494 MachineOperand &getDebugOperand(unsigned Index) {
495 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!")((Index < getNumDebugOperands() && "getDebugOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("Index < getNumDebugOperands() && \"getDebugOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 495, __PRETTY_FUNCTION__))
;
496 return *(debug_operands().begin() + Index);
497 }
498 const MachineOperand &getDebugOperand(unsigned Index) const {
499 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!")((Index < getNumDebugOperands() && "getDebugOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("Index < getNumDebugOperands() && \"getDebugOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 499, __PRETTY_FUNCTION__))
;
500 return *(debug_operands().begin() + Index);
501 }
502
503 /// Returns a pointer to the operand corresponding to a debug use of Reg, or
504 /// nullptr if Reg is not used in any debug operand.
505 const MachineOperand *getDebugOperandForReg(Register Reg) const {
506 const MachineOperand *RegOp =
507 find_if(debug_operands(), [Reg](const MachineOperand &Op) {
508 return Op.isReg() && Op.getReg() == Reg;
509 });
510 return RegOp == adl_end(debug_operands()) ? nullptr : RegOp;
511 }
512 MachineOperand *getDebugOperandForReg(Register Reg) {
513 MachineOperand *RegOp =
514 find_if(debug_operands(), [Reg](const MachineOperand &Op) {
515 return Op.isReg() && Op.getReg() == Reg;
516 });
517 return RegOp == adl_end(debug_operands()) ? nullptr : RegOp;
518 }
519
520 unsigned getDebugOperandIndex(const MachineOperand *Op) const {
521 assert(Op >= adl_begin(debug_operands()) &&((Op >= adl_begin(debug_operands()) && Op <= adl_end
(debug_operands()) && "Expected a debug operand.") ? static_cast
<void> (0) : __assert_fail ("Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands()) && \"Expected a debug operand.\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 522, __PRETTY_FUNCTION__))
522 Op <= adl_end(debug_operands()) && "Expected a debug operand.")((Op >= adl_begin(debug_operands()) && Op <= adl_end
(debug_operands()) && "Expected a debug operand.") ? static_cast
<void> (0) : __assert_fail ("Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands()) && \"Expected a debug operand.\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 522, __PRETTY_FUNCTION__))
;
523 return std::distance(adl_begin(debug_operands()), Op);
524 }
525
526 /// Returns the total number of definitions.
527 unsigned getNumDefs() const {
528 return getNumExplicitDefs() + MCID->getNumImplicitDefs();
529 }
530
531 /// Returns true if the instruction has implicit definition.
532 bool hasImplicitDef() const {
533 for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
534 I != E; ++I) {
535 const MachineOperand &MO = getOperand(I);
536 if (MO.isDef() && MO.isImplicit())
537 return true;
538 }
539 return false;
540 }
541
542 /// Returns the implicit operands number.
543 unsigned getNumImplicitOperands() const {
544 return getNumOperands() - getNumExplicitOperands();
545 }
546
547 /// Return true if operand \p OpIdx is a subregister index.
548 bool isOperandSubregIdx(unsigned OpIdx) const {
549 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&((getOperand(OpIdx).getType() == MachineOperand::MO_Immediate
&& "Expected MO_Immediate operand type.") ? static_cast
<void> (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 550, __PRETTY_FUNCTION__))
550 "Expected MO_Immediate operand type.")((getOperand(OpIdx).getType() == MachineOperand::MO_Immediate
&& "Expected MO_Immediate operand type.") ? static_cast
<void> (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 550, __PRETTY_FUNCTION__))
;
551 if (isExtractSubreg() && OpIdx == 2)
552 return true;
553 if (isInsertSubreg() && OpIdx == 3)
554 return true;
555 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
556 return true;
557 if (isSubregToReg() && OpIdx == 3)
558 return true;
559 return false;
560 }
561
562 /// Returns the number of non-implicit operands.
563 unsigned getNumExplicitOperands() const;
564
565 /// Returns the number of non-implicit definitions.
566 unsigned getNumExplicitDefs() const;
567
568 /// iterator/begin/end - Iterate over all operands of a machine instruction.
569 using mop_iterator = MachineOperand *;
570 using const_mop_iterator = const MachineOperand *;
571
572 mop_iterator operands_begin() { return Operands; }
573 mop_iterator operands_end() { return Operands + NumOperands; }
574
575 const_mop_iterator operands_begin() const { return Operands; }
576 const_mop_iterator operands_end() const { return Operands + NumOperands; }
577
578 iterator_range<mop_iterator> operands() {
579 return make_range(operands_begin(), operands_end());
580 }
581 iterator_range<const_mop_iterator> operands() const {
582 return make_range(operands_begin(), operands_end());
583 }
584 iterator_range<mop_iterator> explicit_operands() {
585 return make_range(operands_begin(),
586 operands_begin() + getNumExplicitOperands());
587 }
588 iterator_range<const_mop_iterator> explicit_operands() const {
589 return make_range(operands_begin(),
590 operands_begin() + getNumExplicitOperands());
591 }
592 iterator_range<mop_iterator> implicit_operands() {
593 return make_range(explicit_operands().end(), operands_end());
594 }
595 iterator_range<const_mop_iterator> implicit_operands() const {
596 return make_range(explicit_operands().end(), operands_end());
597 }
598 /// Returns a range over all operands that are used to determine the variable
599 /// location for this DBG_VALUE instruction.
600 iterator_range<mop_iterator> debug_operands() {
601 assert(isDebugValue() && "Must be a debug value instruction.")((isDebugValue() && "Must be a debug value instruction."
) ? static_cast<void> (0) : __assert_fail ("isDebugValue() && \"Must be a debug value instruction.\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 601, __PRETTY_FUNCTION__))
;
602 return make_range(operands_begin(), operands_begin() + 1);
603 }
604 /// \copydoc debug_operands()
605 iterator_range<const_mop_iterator> debug_operands() const {
606 assert(isDebugValue() && "Must be a debug value instruction.")((isDebugValue() && "Must be a debug value instruction."
) ? static_cast<void> (0) : __assert_fail ("isDebugValue() && \"Must be a debug value instruction.\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 606, __PRETTY_FUNCTION__))
;
607 return make_range(operands_begin(), operands_begin() + 1);
608 }
609 /// Returns a range over all explicit operands that are register definitions.
610 /// Implicit definition are not included!
611 iterator_range<mop_iterator> defs() {
612 return make_range(operands_begin(),
613 operands_begin() + getNumExplicitDefs());
614 }
615 /// \copydoc defs()
616 iterator_range<const_mop_iterator> defs() const {
617 return make_range(operands_begin(),
618 operands_begin() + getNumExplicitDefs());
619 }
620 /// Returns a range that includes all operands that are register uses.
621 /// This may include unrelated operands which are not register uses.
622 iterator_range<mop_iterator> uses() {
623 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
624 }
625 /// \copydoc uses()
626 iterator_range<const_mop_iterator> uses() const {
627 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
628 }
629 iterator_range<mop_iterator> explicit_uses() {
630 return make_range(operands_begin() + getNumExplicitDefs(),
631 operands_begin() + getNumExplicitOperands());
632 }
633 iterator_range<const_mop_iterator> explicit_uses() const {
634 return make_range(operands_begin() + getNumExplicitDefs(),
635 operands_begin() + getNumExplicitOperands());
636 }
637
638 /// Returns the number of the operand iterator \p I points to.
639 unsigned getOperandNo(const_mop_iterator I) const {
640 return I - operands_begin();
641 }
642
643 /// Access to memory operands of the instruction. If there are none, that does
644 /// not imply anything about whether the function accesses memory. Instead,
645 /// the caller must behave conservatively.
646 ArrayRef<MachineMemOperand *> memoperands() const {
647 if (!Info)
648 return {};
649
650 if (Info.is<EIIK_MMO>())
651 return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
652
653 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
654 return EI->getMMOs();
655
656 return {};
657 }
658
659 /// Access to memory operands of the instruction.
660 ///
661 /// If `memoperands_begin() == memoperands_end()`, that does not imply
662 /// anything about whether the function accesses memory. Instead, the caller
663 /// must behave conservatively.
664 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
665
666 /// Access to memory operands of the instruction.
667 ///
668 /// If `memoperands_begin() == memoperands_end()`, that does not imply
669 /// anything about whether the function accesses memory. Instead, the caller
670 /// must behave conservatively.
671 mmo_iterator memoperands_end() const { return memoperands().end(); }
672
673 /// Return true if we don't have any memory operands which described the
674 /// memory access done by this instruction. If this is true, calling code
675 /// must be conservative.
676 bool memoperands_empty() const { return memoperands().empty(); }
677
678 /// Return true if this instruction has exactly one MachineMemOperand.
679 bool hasOneMemOperand() const { return memoperands().size() == 1; }
680
681 /// Return the number of memory operands.
682 unsigned getNumMemOperands() const { return memoperands().size(); }
683
684 /// Helper to extract a pre-instruction symbol if one has been added.
685 MCSymbol *getPreInstrSymbol() const {
686 if (!Info)
687 return nullptr;
688 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
689 return S;
690 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
691 return EI->getPreInstrSymbol();
692
693 return nullptr;
694 }
695
696 /// Helper to extract a post-instruction symbol if one has been added.
697 MCSymbol *getPostInstrSymbol() const {
698 if (!Info)
699 return nullptr;
700 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
701 return S;
702 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
703 return EI->getPostInstrSymbol();
704
705 return nullptr;
706 }
707
708 /// Helper to extract a heap alloc marker if one has been added.
709 MDNode *getHeapAllocMarker() const {
710 if (!Info)
711 return nullptr;
712 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
713 return EI->getHeapAllocMarker();
714
715 return nullptr;
716 }
717
718 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
719 /// queries but they are bundle aware.
720
721 enum QueryType {
722 IgnoreBundle, // Ignore bundles
723 AnyInBundle, // Return true if any instruction in bundle has property
724 AllInBundle // Return true if all instructions in bundle have property
725 };
726
727 /// Return true if the instruction (or in the case of a bundle,
728 /// the instructions inside the bundle) has the specified property.
729 /// The first argument is the property being queried.
730 /// The second argument indicates whether the query should look inside
731 /// instruction bundles.
732 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
733 assert(MCFlag < 64 &&((MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."
) ? static_cast<void> (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 734, __PRETTY_FUNCTION__))
26
'?' condition is true
734 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.")((MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."
) ? static_cast<void> (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 734, __PRETTY_FUNCTION__))
;
735 // Inline the fast path for unbundled or bundle-internal instructions.
736 if (Type
26.1
'Type' is not equal to IgnoreBundle
26.1
'Type' is not equal to IgnoreBundle
26.1
'Type' is not equal to IgnoreBundle
26.1
'Type' is not equal to IgnoreBundle
== IgnoreBundle || !isBundled() || isBundledWithPred())
27
Taking true branch
737 return getDesc().getFlags() & (1ULL << MCFlag);
28
Returning value, which participates in a condition later
738
739 // If this is the first instruction in a bundle, take the slow path.
740 return hasPropertyInBundle(1ULL << MCFlag, Type);
741 }
742
743 /// Return true if this is an instruction that should go through the usual
744 /// legalization steps.
745 bool isPreISelOpcode(QueryType Type = IgnoreBundle) const {
746 return hasProperty(MCID::PreISelOpcode, Type);
747 }
748
749 /// Return true if this instruction can have a variable number of operands.
750 /// In this case, the variable operands will be after the normal
751 /// operands but before the implicit definitions and uses (if any are
752 /// present).
753 bool isVariadic(QueryType Type = IgnoreBundle) const {
754 return hasProperty(MCID::Variadic, Type);
755 }
756
757 /// Set if this instruction has an optional definition, e.g.
758 /// ARM instructions which can set condition code if 's' bit is set.
759 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
760 return hasProperty(MCID::HasOptionalDef, Type);
761 }
762
763 /// Return true if this is a pseudo instruction that doesn't
764 /// correspond to a real machine instruction.
765 bool isPseudo(QueryType Type = IgnoreBundle) const {
766 return hasProperty(MCID::Pseudo, Type);
767 }
768
769 bool isReturn(QueryType Type = AnyInBundle) const {
770 return hasProperty(MCID::Return, Type);
771 }
772
773 /// Return true if this is an instruction that marks the end of an EH scope,
774 /// i.e., a catchpad or a cleanuppad instruction.
775 bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
776 return hasProperty(MCID::EHScopeReturn, Type);
777 }
778
779 bool isCall(QueryType Type = AnyInBundle) const {
780 return hasProperty(MCID::Call, Type);
781 }
782
783 /// Return true if this is a call instruction that may have an associated
784 /// call site entry in the debug info.
785 bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const;
786 /// Return true if copying, moving, or erasing this instruction requires
787 /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo,
788 /// \ref eraseCallSiteInfo).
789 bool shouldUpdateCallSiteInfo() const;
790
791 /// Returns true if the specified instruction stops control flow
792 /// from executing the instruction immediately following it. Examples include
793 /// unconditional branches and return instructions.
794 bool isBarrier(QueryType Type = AnyInBundle) const {
795 return hasProperty(MCID::Barrier, Type);
796 }
797
798 /// Returns true if this instruction part of the terminator for a basic block.
799 /// Typically this is things like return and branch instructions.
800 ///
801 /// Various passes use this to insert code into the bottom of a basic block,
802 /// but before control flow occurs.
803 bool isTerminator(QueryType Type = AnyInBundle) const {
804 return hasProperty(MCID::Terminator, Type);
805 }
806
807 /// Returns true if this is a conditional, unconditional, or indirect branch.
808 /// Predicates below can be used to discriminate between
809 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
810 /// get more information.
811 bool isBranch(QueryType Type = AnyInBundle) const {
812 return hasProperty(MCID::Branch, Type);
813 }
814
815 /// Return true if this is an indirect branch, such as a
816 /// branch through a register.
817 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
818 return hasProperty(MCID::IndirectBranch, Type);
819 }
820
821 /// Return true if this is a branch which may fall
822 /// through to the next instruction or may transfer control flow to some other
823 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
824 /// information about this branch.
825 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
826 return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
827 }
828
829 /// Return true if this is a branch which always
830 /// transfers control flow to some other block. The
831 /// TargetInstrInfo::analyzeBranch method can be used to get more information
832 /// about this branch.
833 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
834 return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
835 }
836
837 /// Return true if this instruction has a predicate operand that
838 /// controls execution. It may be set to 'always', or may be set to other
839 /// values. There are various methods in TargetInstrInfo that can be used to
840 /// control and modify the predicate in this instruction.
841 bool isPredicable(QueryType Type = AllInBundle) const {
842 // If it's a bundle than all bundled instructions must be predicable for this
843 // to return true.
844 return hasProperty(MCID::Predicable, Type);
845 }
846
847 /// Return true if this instruction is a comparison.
848 bool isCompare(QueryType Type = IgnoreBundle) const {
849 return hasProperty(MCID::Compare, Type);
850 }
851
852 /// Return true if this instruction is a move immediate
853 /// (including conditional moves) instruction.
854 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
855 return hasProperty(MCID::MoveImm, Type);
856 }
857
858 /// Return true if this instruction is a register move.
859 /// (including moving values from subreg to reg)
860 bool isMoveReg(QueryType Type = IgnoreBundle) const {
861 return hasProperty(MCID::MoveReg, Type);
862 }
863
864 /// Return true if this instruction is a bitcast instruction.
865 bool isBitcast(QueryType Type = IgnoreBundle) const {
866 return hasProperty(MCID::Bitcast, Type);
867 }
868
869 /// Return true if this instruction is a select instruction.
870 bool isSelect(QueryType Type = IgnoreBundle) const {
871 return hasProperty(MCID::Select, Type);
872 }
873
874 /// Return true if this instruction cannot be safely duplicated.
875 /// For example, if the instruction has a unique labels attached
876 /// to it, duplicating it would cause multiple definition errors.
877 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
878 return hasProperty(MCID::NotDuplicable, Type);
879 }
880
881 /// Return true if this instruction is convergent.
882 /// Convergent instructions can not be made control-dependent on any
883 /// additional values.
884 bool isConvergent(QueryType Type = AnyInBundle) const {
885 if (isInlineAsm()) {
886 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
887 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
888 return true;
889 }
890 return hasProperty(MCID::Convergent, Type);
891 }
892
893 /// Returns true if the specified instruction has a delay slot
894 /// which must be filled by the code generator.
895 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
896 return hasProperty(MCID::DelaySlot, Type);
897 }
898
899 /// Return true for instructions that can be folded as
900 /// memory operands in other instructions. The most common use for this
901 /// is instructions that are simple loads from memory that don't modify
902 /// the loaded value in any way, but it can also be used for instructions
903 /// that can be expressed as constant-pool loads, such as V_SETALLONES
904 /// on x86, to allow them to be folded when it is beneficial.
905 /// This should only be set on instructions that return a value in their
906 /// only virtual register definition.
907 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
908 return hasProperty(MCID::FoldableAsLoad, Type);
909 }
910
911 /// Return true if this instruction behaves
912 /// the same way as the generic REG_SEQUENCE instructions.
913 /// E.g., on ARM,
914 /// dX VMOVDRR rY, rZ
915 /// is equivalent to
916 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
917 ///
918 /// Note that for the optimizers to be able to take advantage of
919 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
920 /// override accordingly.
921 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
922 return hasProperty(MCID::RegSequence, Type);
923 }
924
925 /// Return true if this instruction behaves
926 /// the same way as the generic EXTRACT_SUBREG instructions.
927 /// E.g., on ARM,
928 /// rX, rY VMOVRRD dZ
929 /// is equivalent to two EXTRACT_SUBREG:
930 /// rX = EXTRACT_SUBREG dZ, ssub_0
931 /// rY = EXTRACT_SUBREG dZ, ssub_1
932 ///
933 /// Note that for the optimizers to be able to take advantage of
934 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
935 /// override accordingly.
936 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
937 return hasProperty(MCID::ExtractSubreg, Type);
938 }
939
940 /// Return true if this instruction behaves
941 /// the same way as the generic INSERT_SUBREG instructions.
942 /// E.g., on ARM,
943 /// dX = VSETLNi32 dY, rZ, Imm
944 /// is equivalent to a INSERT_SUBREG:
945 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
946 ///
947 /// Note that for the optimizers to be able to take advantage of
948 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
949 /// override accordingly.
950 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
951 return hasProperty(MCID::InsertSubreg, Type);
952 }
953
954 //===--------------------------------------------------------------------===//
955 // Side Effect Analysis
956 //===--------------------------------------------------------------------===//
957
958 /// Return true if this instruction could possibly read memory.
959 /// Instructions with this flag set are not necessarily simple load
960 /// instructions, they may load a value and modify it, for example.
961 bool mayLoad(QueryType Type = AnyInBundle) const {
962 if (isInlineAsm()) {
963 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
964 if (ExtraInfo & InlineAsm::Extra_MayLoad)
965 return true;
966 }
967 return hasProperty(MCID::MayLoad, Type);
968 }
969
970 /// Return true if this instruction could possibly modify memory.
971 /// Instructions with this flag set are not necessarily simple store
972 /// instructions, they may store a modified value based on their operands, or
973 /// may not actually modify anything, for example.
974 bool mayStore(QueryType Type = AnyInBundle) const {
975 if (isInlineAsm()) {
19
Calling 'MachineInstr::isInlineAsm'
23
Returning from 'MachineInstr::isInlineAsm'
24
Taking false branch
976 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
977 if (ExtraInfo & InlineAsm::Extra_MayStore)
978 return true;
979 }
980 return hasProperty(MCID::MayStore, Type);
25
Calling 'MachineInstr::hasProperty'
29
Returning from 'MachineInstr::hasProperty'
30
Returning value, which participates in a condition later
981 }
982
983 /// Return true if this instruction could possibly read or modify memory.
984 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
985 return mayLoad(Type) || mayStore(Type);
986 }
987
988 /// Return true if this instruction could possibly raise a floating-point
989 /// exception. This is the case if the instruction is a floating-point
990 /// instruction that can in principle raise an exception, as indicated
991 /// by the MCID::MayRaiseFPException property, *and* at the same time,
992 /// the instruction is used in a context where we expect floating-point
993 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag.
994 bool mayRaiseFPException() const {
995 return hasProperty(MCID::MayRaiseFPException) &&
996 !getFlag(MachineInstr::MIFlag::NoFPExcept);
997 }
998
999 //===--------------------------------------------------------------------===//
1000 // Flags that indicate whether an instruction can be modified by a method.
1001 //===--------------------------------------------------------------------===//
1002
1003 /// Return true if this may be a 2- or 3-address
1004 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
1005 /// result if Y and Z are exchanged. If this flag is set, then the
1006 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
1007 /// instruction.
1008 ///
1009 /// Note that this flag may be set on instructions that are only commutable
1010 /// sometimes. In these cases, the call to commuteInstruction will fail.
1011 /// Also note that some instructions require non-trivial modification to
1012 /// commute them.
1013 bool isCommutable(QueryType Type = IgnoreBundle) const {
1014 return hasProperty(MCID::Commutable, Type);
1015 }
1016
1017 /// Return true if this is a 2-address instruction
1018 /// which can be changed into a 3-address instruction if needed. Doing this
1019 /// transformation can be profitable in the register allocator, because it
1020 /// means that the instruction can use a 2-address form if possible, but
1021 /// degrade into a less efficient form if the source and dest register cannot
1022 /// be assigned to the same register. For example, this allows the x86
1023 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
1024 /// is the same speed as the shift but has bigger code size.
1025 ///
1026 /// If this returns true, then the target must implement the
1027 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
1028 /// is allowed to fail if the transformation isn't valid for this specific
1029 /// instruction (e.g. shl reg, 4 on x86).
1030 ///
1031 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
1032 return hasProperty(MCID::ConvertibleTo3Addr, Type);
1033 }
1034
1035 /// Return true if this instruction requires
1036 /// custom insertion support when the DAG scheduler is inserting it into a
1037 /// machine basic block. If this is true for the instruction, it basically
1038 /// means that it is a pseudo instruction used at SelectionDAG time that is
1039 /// expanded out into magic code by the target when MachineInstrs are formed.
1040 ///
1041 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
1042 /// is used to insert this into the MachineBasicBlock.
1043 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
1044 return hasProperty(MCID::UsesCustomInserter, Type);
1045 }
1046
1047 /// Return true if this instruction requires *adjustment*
1048 /// after instruction selection by calling a target hook. For example, this
1049 /// can be used to fill in ARM 's' optional operand depending on whether
1050 /// the conditional flag register is used.
1051 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
1052 return hasProperty(MCID::HasPostISelHook, Type);
1053 }
1054
1055 /// Returns true if this instruction is a candidate for remat.
1056 /// This flag is deprecated, please don't use it anymore. If this
1057 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
1058 /// verify the instruction is really rematable.
1059 bool isRematerializable(QueryType Type = AllInBundle) const {
1060 // It's only possible to re-mat a bundle if all bundled instructions are
1061 // re-materializable.
1062 return hasProperty(MCID::Rematerializable, Type);
1063 }
1064
1065 /// Returns true if this instruction has the same cost (or less) than a move
1066 /// instruction. This is useful during certain types of optimizations
1067 /// (e.g., remat during two-address conversion or machine licm)
1068 /// where we would like to remat or hoist the instruction, but not if it costs
1069 /// more than moving the instruction into the appropriate register. Note, we
1070 /// are not marking copies from and to the same register class with this flag.
1071 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
1072 // Only returns true for a bundle if all bundled instructions are cheap.
1073 return hasProperty(MCID::CheapAsAMove, Type);
1074 }
1075
1076 /// Returns true if this instruction source operands
1077 /// have special register allocation requirements that are not captured by the
1078 /// operand register classes. e.g. ARM::STRD's two source registers must be an
1079 /// even / odd pair, ARM::STM registers have to be in ascending order.
1080 /// Post-register allocation passes should not attempt to change allocations
1081 /// for sources of instructions with this flag.
1082 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
1083 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
1084 }
1085
1086 /// Returns true if this instruction def operands
1087 /// have special register allocation requirements that are not captured by the
1088 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
1089 /// even / odd pair, ARM::LDM registers have to be in ascending order.
1090 /// Post-register allocation passes should not attempt to change allocations
1091 /// for definitions of instructions with this flag.
1092 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
1093 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
1094 }
1095
1096 enum MICheckType {
1097 CheckDefs, // Check all operands for equality
1098 CheckKillDead, // Check all operands including kill / dead markers
1099 IgnoreDefs, // Ignore all definitions
1100 IgnoreVRegDefs // Ignore virtual register definitions
1101 };
1102
1103 /// Return true if this instruction is identical to \p Other.
1104 /// Two instructions are identical if they have the same opcode and all their
1105 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
1106 /// Note that this means liveness related flags (dead, undef, kill) do not
1107 /// affect the notion of identical.
1108 bool isIdenticalTo(const MachineInstr &Other,
1109 MICheckType Check = CheckDefs) const;
1110
1111 /// Unlink 'this' from the containing basic block, and return it without
1112 /// deleting it.
1113 ///
1114 /// This function can not be used on bundled instructions, use
1115 /// removeFromBundle() to remove individual instructions from a bundle.
1116 MachineInstr *removeFromParent();
1117
1118 /// Unlink this instruction from its basic block and return it without
1119 /// deleting it.
1120 ///
1121 /// If the instruction is part of a bundle, the other instructions in the
1122 /// bundle remain bundled.
1123 MachineInstr *removeFromBundle();
1124
1125 /// Unlink 'this' from the containing basic block and delete it.
1126 ///
1127 /// If this instruction is the header of a bundle, the whole bundle is erased.
1128 /// This function can not be used for instructions inside a bundle, use
1129 /// eraseFromBundle() to erase individual bundled instructions.
1130 void eraseFromParent();
1131
1132 /// Unlink 'this' from the containing basic block and delete it.
1133 ///
1134 /// For all definitions mark their uses in DBG_VALUE nodes
1135 /// as undefined. Otherwise like eraseFromParent().
1136 void eraseFromParentAndMarkDBGValuesForRemoval();
1137
1138 /// Unlink 'this' form its basic block and delete it.
1139 ///
1140 /// If the instruction is part of a bundle, the other instructions in the
1141 /// bundle remain bundled.
1142 void eraseFromBundle();
1143
1144 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1145 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1146 bool isAnnotationLabel() const {
1147 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1148 }
1149
1150 /// Returns true if the MachineInstr represents a label.
1151 bool isLabel() const {
1152 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1153 }
1154
1155 bool isCFIInstruction() const {
1156 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1157 }
1158
1159 // True if the instruction represents a position in the function.
1160 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1161
1162 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
1163 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1164 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
1165 bool isDebugInstr() const {
1166 return isDebugValue() || isDebugLabel() || isDebugRef();
1167 }
1168
1169 bool isDebugOffsetImm() const { return getDebugOffset().isImm(); }
1170
1171 /// A DBG_VALUE is indirect iff the location operand is a register and
1172 /// the offset operand is an immediate.
1173 bool isIndirectDebugValue() const {
1174 return isDebugValue() && getDebugOperand(0).isReg() && isDebugOffsetImm();
1175 }
1176
1177 /// A DBG_VALUE is an entry value iff its debug expression contains the
1178 /// DW_OP_LLVM_entry_value operation.
1179 bool isDebugEntryValue() const;
1180
1181 /// Return true if the instruction is a debug value which describes a part of
1182 /// a variable as unavailable.
1183 bool isUndefDebugValue() const {
1184 return isDebugValue() && getDebugOperand(0).isReg() &&
1185 !getDebugOperand(0).getReg().isValid();
1186 }
1187
1188 bool isPHI() const {
1189 return getOpcode() == TargetOpcode::PHI ||
1190 getOpcode() == TargetOpcode::G_PHI;
1191 }
1192 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1193 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1194 bool isInlineAsm() const {
1195 return getOpcode() == TargetOpcode::INLINEASM ||
20
Assuming the condition is false
22
Returning zero, which participates in a condition later
1196 getOpcode() == TargetOpcode::INLINEASM_BR;
21
Assuming the condition is false
1197 }
1198
1199 /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1200 /// specific, be attached to a generic MachineInstr.
1201 bool isMSInlineAsm() const {
1202 return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
1203 }
1204
1205 bool isStackAligningInlineAsm() const;
1206 InlineAsm::AsmDialect getInlineAsmDialect() const;
1207
1208 bool isInsertSubreg() const {
1209 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1210 }
1211
1212 bool isSubregToReg() const {
1213 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1214 }
1215
1216 bool isRegSequence() const {
1217 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1218 }
1219
1220 bool isBundle() const {
1221 return getOpcode() == TargetOpcode::BUNDLE;
1222 }
1223
1224 bool isCopy() const {
1225 return getOpcode() == TargetOpcode::COPY;
1226 }
1227
1228 bool isFullCopy() const {
1229 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1230 }
1231
1232 bool isExtractSubreg() const {
1233 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1234 }
1235
1236 /// Return true if the instruction behaves like a copy.
1237 /// This does not include native copy instructions.
1238 bool isCopyLike() const {
1239 return isCopy() || isSubregToReg();
1240 }
1241
1242 /// Return true is the instruction is an identity copy.
1243 bool isIdentityCopy() const {
1244 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1245 getOperand(0).getSubReg() == getOperand(1).getSubReg();
1246 }
1247
1248 /// Return true if this instruction doesn't produce any output in the form of
1249 /// executable instructions.
1250 bool isMetaInstruction() const {
1251 switch (getOpcode()) {
1252 default:
1253 return false;
1254 case TargetOpcode::IMPLICIT_DEF:
1255 case TargetOpcode::KILL:
1256 case TargetOpcode::CFI_INSTRUCTION:
1257 case TargetOpcode::EH_LABEL:
1258 case TargetOpcode::GC_LABEL:
1259 case TargetOpcode::DBG_VALUE:
1260 case TargetOpcode::DBG_INSTR_REF:
1261 case TargetOpcode::DBG_LABEL:
1262 case TargetOpcode::LIFETIME_START:
1263 case TargetOpcode::LIFETIME_END:
1264 case TargetOpcode::PSEUDO_PROBE:
1265 return true;
1266 }
1267 }
1268
1269 /// Return true if this is a transient instruction that is either very likely
1270 /// to be eliminated during register allocation (such as copy-like
1271 /// instructions), or if this instruction doesn't have an execution-time cost.
1272 bool isTransient() const {
1273 switch (getOpcode()) {
1274 default:
1275 return isMetaInstruction();
1276 // Copy-like instructions are usually eliminated during register allocation.
1277 case TargetOpcode::PHI:
1278 case TargetOpcode::G_PHI:
1279 case TargetOpcode::COPY:
1280 case TargetOpcode::INSERT_SUBREG:
1281 case TargetOpcode::SUBREG_TO_REG:
1282 case TargetOpcode::REG_SEQUENCE:
1283 return true;
1284 }
1285 }
1286
1287 /// Return the number of instructions inside the MI bundle, excluding the
1288 /// bundle header.
1289 ///
1290 /// This is the number of instructions that MachineBasicBlock::iterator
1291 /// skips, 0 for unbundled instructions.
1292 unsigned getBundleSize() const;
1293
1294 /// Return true if the MachineInstr reads the specified register.
1295 /// If TargetRegisterInfo is passed, then it also checks if there
1296 /// is a read of a super-register.
1297 /// This does not count partial redefines of virtual registers as reads:
1298 /// %reg1024:6 = OP.
1299 bool readsRegister(Register Reg,
1300 const TargetRegisterInfo *TRI = nullptr) const {
1301 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1302 }
1303
1304 /// Return true if the MachineInstr reads the specified virtual register.
1305 /// Take into account that a partial define is a
1306 /// read-modify-write operation.
1307 bool readsVirtualRegister(Register Reg) const {
1308 return readsWritesVirtualRegister(Reg).first;
1309 }
1310
1311 /// Return a pair of bools (reads, writes) indicating if this instruction
1312 /// reads or writes Reg. This also considers partial defines.
1313 /// If Ops is not null, all operand indices for Reg are added.
1314 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1315 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1316
1317 /// Return true if the MachineInstr kills the specified register.
1318 /// If TargetRegisterInfo is passed, then it also checks if there is
1319 /// a kill of a super-register.
1320 bool killsRegister(Register Reg,
1321 const TargetRegisterInfo *TRI = nullptr) const {
1322 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1323 }
1324
1325 /// Return true if the MachineInstr fully defines the specified register.
1326 /// If TargetRegisterInfo is passed, then it also checks
1327 /// if there is a def of a super-register.
1328 /// NOTE: It's ignoring subreg indices on virtual registers.
1329 bool definesRegister(Register Reg,
1330 const TargetRegisterInfo *TRI = nullptr) const {
1331 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1332 }
1333
1334 /// Return true if the MachineInstr modifies (fully define or partially
1335 /// define) the specified register.
1336 /// NOTE: It's ignoring subreg indices on virtual registers.
1337 bool modifiesRegister(Register Reg,
1338 const TargetRegisterInfo *TRI = nullptr) const {
1339 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1340 }
1341
1342 /// Returns true if the register is dead in this machine instruction.
1343 /// If TargetRegisterInfo is passed, then it also checks
1344 /// if there is a dead def of a super-register.
1345 bool registerDefIsDead(Register Reg,
1346 const TargetRegisterInfo *TRI = nullptr) const {
1347 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1348 }
1349
1350 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1351 /// the given register (not considering sub/super-registers).
1352 bool hasRegisterImplicitUseOperand(Register Reg) const;
1353
1354 /// Returns the operand index that is a use of the specific register or -1
1355 /// if it is not found. It further tightens the search criteria to a use
1356 /// that kills the register if isKill is true.
1357 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1358 const TargetRegisterInfo *TRI = nullptr) const;
1359
1360 /// Wrapper for findRegisterUseOperandIdx, it returns
1361 /// a pointer to the MachineOperand rather than an index.
1362 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
1363 const TargetRegisterInfo *TRI = nullptr) {
1364 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1365 return (Idx == -1) ? nullptr : &getOperand(Idx);
1366 }
1367
1368 const MachineOperand *findRegisterUseOperand(
1369 Register Reg, bool isKill = false,
1370 const TargetRegisterInfo *TRI = nullptr) const {
1371 return const_cast<MachineInstr *>(this)->
1372 findRegisterUseOperand(Reg, isKill, TRI);
1373 }
1374
1375 /// Returns the operand index that is a def of the specified register or
1376 /// -1 if it is not found. If isDead is true, defs that are not dead are
1377 /// skipped. If Overlap is true, then it also looks for defs that merely
1378 /// overlap the specified register. If TargetRegisterInfo is non-null,
1379 /// then it also checks if there is a def of a super-register.
1380 /// This may also return a register mask operand when Overlap is true.
1381 int findRegisterDefOperandIdx(Register Reg,
1382 bool isDead = false, bool Overlap = false,
1383 const TargetRegisterInfo *TRI = nullptr) const;
1384
1385 /// Wrapper for findRegisterDefOperandIdx, it returns
1386 /// a pointer to the MachineOperand rather than an index.
1387 MachineOperand *
1388 findRegisterDefOperand(Register Reg, bool isDead = false,
1389 bool Overlap = false,
1390 const TargetRegisterInfo *TRI = nullptr) {
1391 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1392 return (Idx == -1) ? nullptr : &getOperand(Idx);
1393 }
1394
1395 const MachineOperand *
1396 findRegisterDefOperand(Register Reg, bool isDead = false,
1397 bool Overlap = false,
1398 const TargetRegisterInfo *TRI = nullptr) const {
1399 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1400 Reg, isDead, Overlap, TRI);
1401 }
1402
1403 /// Find the index of the first operand in the
1404 /// operand list that is used to represent the predicate. It returns -1 if
1405 /// none is found.
1406 int findFirstPredOperandIdx() const;
1407
1408 /// Find the index of the flag word operand that
1409 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1410 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1411 ///
1412 /// If GroupNo is not NULL, it will receive the number of the operand group
1413 /// containing OpIdx.
1414 ///
1415 /// The flag operand is an immediate that can be decoded with methods like
1416 /// InlineAsm::hasRegClassConstraint().
1417 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1418
1419 /// Compute the static register class constraint for operand OpIdx.
1420 /// For normal instructions, this is derived from the MCInstrDesc.
1421 /// For inline assembly it is derived from the flag words.
1422 ///
1423 /// Returns NULL if the static register class constraint cannot be
1424 /// determined.
1425 const TargetRegisterClass*
1426 getRegClassConstraint(unsigned OpIdx,
1427 const TargetInstrInfo *TII,
1428 const TargetRegisterInfo *TRI) const;
1429
1430 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1431 /// the given \p CurRC.
1432 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1433 /// instructions inside the bundle will be taken into account. In other words,
1434 /// this method accumulates all the constraints of the operand of this MI and
1435 /// the related bundle if MI is a bundle or inside a bundle.
1436 ///
1437 /// Returns the register class that satisfies both \p CurRC and the
1438 /// constraints set by MI. Returns NULL if such a register class does not
1439 /// exist.
1440 ///
1441 /// \pre CurRC must not be NULL.
1442 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1443 Register Reg, const TargetRegisterClass *CurRC,
1444 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1445 bool ExploreBundle = false) const;
1446
1447 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1448 /// to the given \p CurRC.
1449 ///
1450 /// Returns the register class that satisfies both \p CurRC and the
1451 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1452 /// does not exist.
1453 ///
1454 /// \pre CurRC must not be NULL.
1455 /// \pre The operand at \p OpIdx must be a register.
1456 const TargetRegisterClass *
1457 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1458 const TargetInstrInfo *TII,
1459 const TargetRegisterInfo *TRI) const;
1460
1461 /// Add a tie between the register operands at DefIdx and UseIdx.
1462 /// The tie will cause the register allocator to ensure that the two
1463 /// operands are assigned the same physical register.
1464 ///
1465 /// Tied operands are managed automatically for explicit operands in the
1466 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1467 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1468
1469 /// Given the index of a tied register operand, find the
1470 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1471 /// index of the tied operand which must exist.
1472 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1473
1474 /// Given the index of a register def operand,
1475 /// check if the register def is tied to a source operand, due to either
1476 /// two-address elimination or inline assembly constraints. Returns the
1477 /// first tied use operand index by reference if UseOpIdx is not null.
1478 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1479 unsigned *UseOpIdx = nullptr) const {
1480 const MachineOperand &MO = getOperand(DefOpIdx);
1481 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1482 return false;
1483 if (UseOpIdx)
1484 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1485 return true;
1486 }
1487
1488 /// Return true if the use operand of the specified index is tied to a def
1489 /// operand. It also returns the def operand index by reference if DefOpIdx
1490 /// is not null.
1491 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1492 unsigned *DefOpIdx = nullptr) const {
1493 const MachineOperand &MO = getOperand(UseOpIdx);
1494 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1495 return false;
1496 if (DefOpIdx)
1497 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1498 return true;
1499 }
1500
1501 /// Clears kill flags on all operands.
1502 void clearKillInfo();
1503
1504 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1505 /// properly composing subreg indices where necessary.
1506 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1507 const TargetRegisterInfo &RegInfo);
1508
1509 /// We have determined MI kills a register. Look for the
1510 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1511 /// add a implicit operand if it's not found. Returns true if the operand
1512 /// exists / is added.
1513 bool addRegisterKilled(Register IncomingReg,
1514 const TargetRegisterInfo *RegInfo,
1515 bool AddIfNotFound = false);
1516
1517 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1518 /// all aliasing registers.
1519 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1520
1521 /// We have determined MI defined a register without a use.
1522 /// Look for the operand that defines it and mark it as IsDead. If
1523 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1524 /// true if the operand exists / is added.
1525 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1526 bool AddIfNotFound = false);
1527
1528 /// Clear all dead flags on operands defining register @p Reg.
1529 void clearRegisterDeads(Register Reg);
1530
1531 /// Mark all subregister defs of register @p Reg with the undef flag.
1532 /// This function is used when we determined to have a subregister def in an
1533 /// otherwise undefined super register.
1534 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1535
1536 /// We have determined MI defines a register. Make sure there is an operand
1537 /// defining Reg.
1538 void addRegisterDefined(Register Reg,
1539 const TargetRegisterInfo *RegInfo = nullptr);
1540
1541 /// Mark every physreg used by this instruction as
1542 /// dead except those in the UsedRegs list.
1543 ///
1544 /// On instructions with register mask operands, also add implicit-def
1545 /// operands for all registers in UsedRegs.
1546 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1547 const TargetRegisterInfo &TRI);
1548
1549 /// Return true if it is safe to move this instruction. If
1550 /// SawStore is set to true, it means that there is a store (or call) between
1551 /// the instruction's location and its intended destination.
1552 bool isSafeToMove(AAResults *AA, bool &SawStore) const;
1553
1554 /// Returns true if this instruction's memory access aliases the memory
1555 /// access of Other.
1556 //
1557 /// Assumes any physical registers used to compute addresses
1558 /// have the same value for both instructions. Returns false if neither
1559 /// instruction writes to memory.
1560 ///
1561 /// @param AA Optional alias analysis, used to compare memory operands.
1562 /// @param Other MachineInstr to check aliasing against.
1563 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1564 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
1565
1566 /// Return true if this instruction may have an ordered
1567 /// or volatile memory reference, or if the information describing the memory
1568 /// reference is not available. Return false if it is known to have no
1569 /// ordered or volatile memory references.
1570 bool hasOrderedMemoryRef() const;
1571
1572 /// Return true if this load instruction never traps and points to a memory
1573 /// location whose value doesn't change during the execution of this function.
1574 ///
1575 /// Examples include loading a value from the constant pool or from the
1576 /// argument area of a function (if it does not change). If the instruction
1577 /// does multiple loads, this returns true only if all of the loads are
1578 /// dereferenceable and invariant.
1579 bool isDereferenceableInvariantLoad(AAResults *AA) const;
1580
1581 /// If the specified instruction is a PHI that always merges together the
1582 /// same virtual register, return the register, otherwise return 0.
1583 unsigned isConstantValuePHI() const;
1584
1585 /// Return true if this instruction has side effects that are not modeled
1586 /// by mayLoad / mayStore, etc.
1587 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1588 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1589 /// INLINEASM instruction, in which case the side effect property is encoded
1590 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1591 ///
1592 bool hasUnmodeledSideEffects() const;
1593
1594 /// Returns true if it is illegal to fold a load across this instruction.
1595 bool isLoadFoldBarrier() const;
1596
1597 /// Return true if all the defs of this instruction are dead.
1598 bool allDefsAreDead() const;
1599
1600 /// Return a valid size if the instruction is a spill instruction.
1601 Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
1602
1603 /// Return a valid size if the instruction is a folded spill instruction.
1604 Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
1605
1606 /// Return a valid size if the instruction is a restore instruction.
1607 Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
1608
1609 /// Return a valid size if the instruction is a folded restore instruction.
1610 Optional<unsigned>
1611 getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1612
1613 /// Copy implicit register operands from specified
1614 /// instruction to this instruction.
1615 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1616
1617 /// Debugging support
1618 /// @{
1619 /// Determine the generic type to be printed (if needed) on uses and defs.
1620 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1621 const MachineRegisterInfo &MRI) const;
1622
1623 /// Return true when an instruction has tied register that can't be determined
1624 /// by the instruction's descriptor. This is useful for MIR printing, to
1625 /// determine whether we need to print the ties or not.
1626 bool hasComplexRegisterTies() const;
1627
1628 /// Print this MI to \p OS.
1629 /// Don't print information that can be inferred from other instructions if
1630 /// \p IsStandalone is false. It is usually true when only a fragment of the
1631 /// function is printed.
1632 /// Only print the defs and the opcode if \p SkipOpers is true.
1633 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1634 /// Otherwise, also print the debug loc, with a terminating newline.
1635 /// \p TII is used to print the opcode name. If it's not present, but the
1636 /// MI is in a function, the opcode will be printed using the function's TII.
1637 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1638 bool SkipDebugLoc = false, bool AddNewLine = true,
1639 const TargetInstrInfo *TII = nullptr) const;
1640 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1641 bool SkipOpers = false, bool SkipDebugLoc = false,
1642 bool AddNewLine = true,
1643 const TargetInstrInfo *TII = nullptr) const;
1644 void dump() const;
1645 /// Print on dbgs() the current instruction and the instructions defining its
1646 /// operands and so on until we reach \p MaxDepth.
1647 void dumpr(const MachineRegisterInfo &MRI,
1648 unsigned MaxDepth = UINT_MAX(2147483647 *2U +1U)) const;
1649 /// @}
1650
1651 //===--------------------------------------------------------------------===//
1652 // Accessors used to build up machine instructions.
1653
1654 /// Add the specified operand to the instruction. If it is an implicit
1655 /// operand, it is added to the end of the operand list. If it is an
1656 /// explicit operand it is added at the end of the explicit operand list
1657 /// (before the first implicit operand).
1658 ///
1659 /// MF must be the machine function that was used to allocate this
1660 /// instruction.
1661 ///
1662 /// MachineInstrBuilder provides a more convenient interface for creating
1663 /// instructions and adding operands.
1664 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1665
1666 /// Add an operand without providing an MF reference. This only works for
1667 /// instructions that are inserted in a basic block.
1668 ///
1669 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1670 /// preferred.
1671 void addOperand(const MachineOperand &Op);
1672
1673 /// Replace the instruction descriptor (thus opcode) of
1674 /// the current instruction with a new one.
1675 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1676
1677 /// Replace current source information with new such.
1678 /// Avoid using this, the constructor argument is preferable.
1679 void setDebugLoc(DebugLoc dl) {
1680 debugLoc = std::move(dl);
1681 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 1681, __PRETTY_FUNCTION__))
;
1682 }
1683
1684 /// Erase an operand from an instruction, leaving it with one
1685 /// fewer operand than it started with.
1686 void RemoveOperand(unsigned OpNo);
1687
1688 /// Clear this MachineInstr's memory reference descriptor list. This resets
1689 /// the memrefs to their most conservative state. This should be used only
1690 /// as a last resort since it greatly pessimizes our knowledge of the memory
1691 /// access performed by the instruction.
1692 void dropMemRefs(MachineFunction &MF);
1693
1694 /// Assign this MachineInstr's memory reference descriptor list.
1695 ///
1696 /// Unlike other methods, this *will* allocate them into a new array
1697 /// associated with the provided `MachineFunction`.
1698 void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);
1699
1700 /// Add a MachineMemOperand to the machine instruction.
1701 /// This function should be used only occasionally. The setMemRefs function
1702 /// is the primary method for setting up a MachineInstr's MemRefs list.
1703 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1704
1705 /// Clone another MachineInstr's memory reference descriptor list and replace
1706 /// ours with it.
1707 ///
1708 /// Note that `*this` may be the incoming MI!
1709 ///
1710 /// Prefer this API whenever possible as it can avoid allocations in common
1711 /// cases.
1712 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1713
1714 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1715 /// list and replace ours with it.
1716 ///
1717 /// Note that `*this` may be one of the incoming MIs!
1718 ///
1719 /// Prefer this API whenever possible as it can avoid allocations in common
1720 /// cases.
1721 void cloneMergedMemRefs(MachineFunction &MF,
1722 ArrayRef<const MachineInstr *> MIs);
1723
1724 /// Set a symbol that will be emitted just prior to the instruction itself.
1725 ///
1726 /// Setting this to a null pointer will remove any such symbol.
1727 ///
1728 /// FIXME: This is not fully implemented yet.
1729 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1730
1731 /// Set a symbol that will be emitted just after the instruction itself.
1732 ///
1733 /// Setting this to a null pointer will remove any such symbol.
1734 ///
1735 /// FIXME: This is not fully implemented yet.
1736 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1737
1738 /// Clone another MachineInstr's pre- and post- instruction symbols and
1739 /// replace ours with it.
1740 void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1741
1742 /// Set a marker on instructions that denotes where we should create and emit
1743 /// heap alloc site labels. This waits until after instruction selection and
1744 /// optimizations to create the label, so it should still work if the
1745 /// instruction is removed or duplicated.
1746 void setHeapAllocMarker(MachineFunction &MF, MDNode *MD);
1747
1748 /// Return the MIFlags which represent both MachineInstrs. This
1749 /// should be used when merging two MachineInstrs into one. This routine does
1750 /// not modify the MIFlags of this MachineInstr.
1751 uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1752
1753 static uint16_t copyFlagsFromInstruction(const Instruction &I);
1754
1755 /// Copy all flags to MachineInst MIFlags
1756 void copyIRFlags(const Instruction &I);
1757
1758 /// Break any tie involving OpIdx.
1759 void untieRegOperand(unsigned OpIdx) {
1760 MachineOperand &MO = getOperand(OpIdx);
1761 if (MO.isReg() && MO.isTied()) {
1762 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1763 MO.TiedTo = 0;
1764 }
1765 }
1766
1767 /// Add all implicit def and use operands to this instruction.
1768 void addImplicitDefUseOperands(MachineFunction &MF);
1769
1770 /// Scan instructions immediately following MI and collect any matching
1771 /// DBG_VALUEs.
1772 void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
1773
1774 /// Find all DBG_VALUEs that point to the register def in this instruction
1775 /// and point them to \p Reg instead.
1776 void changeDebugValuesDefReg(Register Reg);
1777
1778 /// Returns the Intrinsic::ID for this instruction.
1779 /// \pre Must have an intrinsic ID operand.
1780 unsigned getIntrinsicID() const {
1781 return getOperand(getNumExplicitDefs()).getIntrinsicID();
1782 }
1783
1784 /// Sets all register debug operands in this debug value instruction to be
1785 /// undef.
1786 void setDebugValueUndef() {
1787 assert(isDebugValue() && "Must be a debug value instruction.")((isDebugValue() && "Must be a debug value instruction."
) ? static_cast<void> (0) : __assert_fail ("isDebugValue() && \"Must be a debug value instruction.\""
, "/build/llvm-toolchain-snapshot-12~++20210115100614+a14c36fe27f5/llvm/include/llvm/CodeGen/MachineInstr.h"
, 1787, __PRETTY_FUNCTION__))
;
1788 for (MachineOperand &MO : debug_operands()) {
1789 if (MO.isReg()) {
1790 MO.setReg(0);
1791 MO.setSubReg(0);
1792 }
1793 }
1794 }
1795
1796private:
1797 /// If this instruction is embedded into a MachineFunction, return the
1798 /// MachineRegisterInfo object for the current function, otherwise
1799 /// return null.
1800 MachineRegisterInfo *getRegInfo();
1801
1802 /// Unlink all of the register operands in this instruction from their
1803 /// respective use lists. This requires that the operands already be on their
1804 /// use lists.
1805 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1806
1807 /// Add all of the register operands in this instruction from their
1808 /// respective use lists. This requires that the operands not be on their
1809 /// use lists yet.
1810 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1811
1812 /// Slow path for hasProperty when we're dealing with a bundle.
1813 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1814
1815 /// Implements the logic of getRegClassConstraintEffectForVReg for the
1816 /// this MI and the given operand index \p OpIdx.
1817 /// If the related operand does not constrained Reg, this returns CurRC.
1818 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1819 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1820 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1821
1822 /// Stores extra instruction information inline or allocates as ExtraInfo
1823 /// based on the number of pointers.
1824 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs,
1825 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol,
1826 MDNode *HeapAllocMarker);
1827};
1828
1829/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1830/// instruction rather than by pointer value.
1831/// The hashing and equality testing functions ignore definitions so this is
1832/// useful for CSE, etc.
1833struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1834 static inline MachineInstr *getEmptyKey() {
1835 return nullptr;
1836 }
1837
1838 static inline MachineInstr *getTombstoneKey() {
1839 return reinterpret_cast<MachineInstr*>(-1);
1840 }
1841
1842 static unsigned getHashValue(const MachineInstr* const &MI);
1843
1844 static bool isEqual(const MachineInstr* const &LHS,
1845 const MachineInstr* const &RHS) {
1846 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1847 LHS == getEmptyKey() || LHS == getTombstoneKey())
1848 return LHS == RHS;
1849 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1850 }
1851};
1852
1853//===----------------------------------------------------------------------===//
1854// Debugging Support
1855
1856inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1857 MI.print(OS);
1858 return OS;
1859}
1860
1861} // end namespace llvm
1862
1863#endif // LLVM_CODEGEN_MACHINEINSTR_H