Bug Summary

File:llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Warning:line 10255, column 52
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SIISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/include -I /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/build-llvm/lib/Target/AMDGPU -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-01-13-084841-49055-1 -x c++ /build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Custom DAG lowering for SI
11//
12//===----------------------------------------------------------------------===//
13
14#if defined(_MSC_VER) || defined(__MINGW32__)
15// Provide M_PI.
16#define _USE_MATH_DEFINES
17#endif
18
19#include "SIISelLowering.h"
20#include "AMDGPU.h"
21#include "AMDGPUSubtarget.h"
22#include "AMDGPUTargetMachine.h"
23#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24#include "SIDefines.h"
25#include "SIInstrInfo.h"
26#include "SIMachineFunctionInfo.h"
27#include "SIRegisterInfo.h"
28#include "Utils/AMDGPUBaseInfo.h"
29#include "llvm/ADT/APFloat.h"
30#include "llvm/ADT/APInt.h"
31#include "llvm/ADT/ArrayRef.h"
32#include "llvm/ADT/BitVector.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
36#include "llvm/ADT/StringSwitch.h"
37#include "llvm/ADT/Twine.h"
38#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
39#include "llvm/CodeGen/Analysis.h"
40#include "llvm/CodeGen/CallingConvLower.h"
41#include "llvm/CodeGen/DAGCombine.h"
42#include "llvm/CodeGen/ISDOpcodes.h"
43#include "llvm/CodeGen/MachineBasicBlock.h"
44#include "llvm/CodeGen/MachineFrameInfo.h"
45#include "llvm/CodeGen/MachineFunction.h"
46#include "llvm/CodeGen/MachineInstr.h"
47#include "llvm/CodeGen/MachineInstrBuilder.h"
48#include "llvm/CodeGen/MachineLoopInfo.h"
49#include "llvm/CodeGen/MachineMemOperand.h"
50#include "llvm/CodeGen/MachineModuleInfo.h"
51#include "llvm/CodeGen/MachineOperand.h"
52#include "llvm/CodeGen/MachineRegisterInfo.h"
53#include "llvm/CodeGen/SelectionDAG.h"
54#include "llvm/CodeGen/SelectionDAGNodes.h"
55#include "llvm/CodeGen/TargetCallingConv.h"
56#include "llvm/CodeGen/TargetRegisterInfo.h"
57#include "llvm/CodeGen/ValueTypes.h"
58#include "llvm/IR/Constants.h"
59#include "llvm/IR/DataLayout.h"
60#include "llvm/IR/DebugLoc.h"
61#include "llvm/IR/DerivedTypes.h"
62#include "llvm/IR/DiagnosticInfo.h"
63#include "llvm/IR/Function.h"
64#include "llvm/IR/GlobalValue.h"
65#include "llvm/IR/InstrTypes.h"
66#include "llvm/IR/Instruction.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/IntrinsicInst.h"
69#include "llvm/IR/Type.h"
70#include "llvm/Support/Casting.h"
71#include "llvm/Support/CodeGen.h"
72#include "llvm/Support/CommandLine.h"
73#include "llvm/Support/Compiler.h"
74#include "llvm/Support/ErrorHandling.h"
75#include "llvm/Support/KnownBits.h"
76#include "llvm/Support/MachineValueType.h"
77#include "llvm/Support/MathExtras.h"
78#include "llvm/Target/TargetOptions.h"
79#include <cassert>
80#include <cmath>
81#include <cstdint>
82#include <iterator>
83#include <tuple>
84#include <utility>
85#include <vector>
86
87using namespace llvm;
88
89#define DEBUG_TYPE"si-lower" "si-lower"
90
91STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"si-lower", "NumTailCalls"
, "Number of tail calls"}
;
92
93static cl::opt<bool> DisableLoopAlignment(
94 "amdgpu-disable-loop-alignment",
95 cl::desc("Do not align and prefetch loops"),
96 cl::init(false));
97
98static bool hasFP32Denormals(const MachineFunction &MF) {
99 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
100 return Info->getMode().FP32Denormals;
101}
102
103static bool hasFP64FP16Denormals(const MachineFunction &MF) {
104 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
105 return Info->getMode().FP64FP16Denormals;
106}
107
108static unsigned findFirstFreeSGPR(CCState &CCInfo) {
109 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
110 for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
111 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
112 return AMDGPU::SGPR0 + Reg;
113 }
114 }
115 llvm_unreachable("Cannot allocate sgpr")::llvm::llvm_unreachable_internal("Cannot allocate sgpr", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 115)
;
116}
117
118SITargetLowering::SITargetLowering(const TargetMachine &TM,
119 const GCNSubtarget &STI)
120 : AMDGPUTargetLowering(TM, STI),
121 Subtarget(&STI) {
122 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
123 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
124
125 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
126 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
127
128 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
129 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
130 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
131
132 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
133 addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
134
135 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
136 addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
137
138 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
139 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
140
141 addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
142 addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
143
144 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
145 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
146
147 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
148 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
149
150 if (Subtarget->has16BitInsts()) {
151 addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
152 addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
153
154 // Unless there are also VOP3P operations, not operations are really legal.
155 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
156 addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);
157 addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
158 addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
159 }
160
161 if (Subtarget->hasMAIInsts()) {
162 addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
163 addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
164 }
165
166 computeRegisterProperties(Subtarget->getRegisterInfo());
167
168 // The boolean content concept here is too inflexible. Compares only ever
169 // really produce a 1-bit result. Any copy/extend from these will turn into a
170 // select, and zext/1 or sext/-1 are equally cheap. Arbitrarily choose 0/1, as
171 // it's what most targets use.
172 setBooleanContents(ZeroOrOneBooleanContent);
173 setBooleanVectorContents(ZeroOrOneBooleanContent);
174
175 // We need to custom lower vector stores from local memory
176 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
177 setOperationAction(ISD::LOAD, MVT::v3i32, Custom);
178 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
179 setOperationAction(ISD::LOAD, MVT::v5i32, Custom);
180 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
181 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
182 setOperationAction(ISD::LOAD, MVT::i1, Custom);
183 setOperationAction(ISD::LOAD, MVT::v32i32, Custom);
184
185 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
186 setOperationAction(ISD::STORE, MVT::v3i32, Custom);
187 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
188 setOperationAction(ISD::STORE, MVT::v5i32, Custom);
189 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
190 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
191 setOperationAction(ISD::STORE, MVT::i1, Custom);
192 setOperationAction(ISD::STORE, MVT::v32i32, Custom);
193
194 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
195 setTruncStoreAction(MVT::v3i32, MVT::v3i16, Expand);
196 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
197 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
198 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
199 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand);
200 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Expand);
201 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
202 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Expand);
203 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
204 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Expand);
205
206 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
207 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
208
209 setOperationAction(ISD::SELECT, MVT::i1, Promote);
210 setOperationAction(ISD::SELECT, MVT::i64, Custom);
211 setOperationAction(ISD::SELECT, MVT::f64, Promote);
212 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
213
214 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
215 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
216 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
217 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
218 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
219
220 setOperationAction(ISD::SETCC, MVT::i1, Promote);
221 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
222 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
223 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
224
225 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
226 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
227
228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
232 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v3i16, Custom);
234 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
236
237 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
238 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
239 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
240 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
241 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
242 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
243
244 setOperationAction(ISD::UADDO, MVT::i32, Legal);
245 setOperationAction(ISD::USUBO, MVT::i32, Legal);
246
247 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
248 setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
249
250 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
251 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
252 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
253
254#if 0
255 setOperationAction(ISD::ADDCARRY, MVT::i64, Legal);
256 setOperationAction(ISD::SUBCARRY, MVT::i64, Legal);
257#endif
258
259 // We only support LOAD/STORE and vector manipulation ops for vectors
260 // with > 4 elements.
261 for (MVT VT : { MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32,
262 MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16,
263 MVT::v32i32, MVT::v32f32 }) {
264 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
265 switch (Op) {
266 case ISD::LOAD:
267 case ISD::STORE:
268 case ISD::BUILD_VECTOR:
269 case ISD::BITCAST:
270 case ISD::EXTRACT_VECTOR_ELT:
271 case ISD::INSERT_VECTOR_ELT:
272 case ISD::INSERT_SUBVECTOR:
273 case ISD::EXTRACT_SUBVECTOR:
274 case ISD::SCALAR_TO_VECTOR:
275 break;
276 case ISD::CONCAT_VECTORS:
277 setOperationAction(Op, VT, Custom);
278 break;
279 default:
280 setOperationAction(Op, VT, Expand);
281 break;
282 }
283 }
284 }
285
286 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand);
287
288 // TODO: For dynamic 64-bit vector inserts/extracts, should emit a pseudo that
289 // is expanded to avoid having two separate loops in case the index is a VGPR.
290
291 // Most operations are naturally 32-bit vector operations. We only support
292 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
293 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
294 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
295 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
296
297 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
298 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
299
300 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
301 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
302
303 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
304 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
305 }
306
307 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
308 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
309 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
310 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
311
312 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f16, Custom);
313 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
314
315 // Avoid stack access for these.
316 // TODO: Generalize to more vector types.
317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);
318 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);
319 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
320 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
321
322 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
324 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom);
325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom);
326 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom);
327
328 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
329 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
330 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
331
332 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom);
333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f16, Custom);
334 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
335 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
336
337 // Deal with vec3 vector operations when widened to vec4.
338 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom);
339 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom);
340 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom);
341 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom);
342
343 // Deal with vec5 vector operations when widened to vec8.
344 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom);
345 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom);
346 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom);
347 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom);
348
349 // BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
350 // and output demarshalling
351 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
352 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
353
354 // We can't return success/failure, only the old value,
355 // let LLVM add the comparison
356 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Expand);
358
359 if (Subtarget->hasFlatAddressSpace()) {
360 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
361 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
362 }
363
364 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
365 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
366
367 // On SI this is s_memtime and s_memrealtime on VI.
368 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
369 setOperationAction(ISD::TRAP, MVT::Other, Custom);
370 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Custom);
371
372 if (Subtarget->has16BitInsts()) {
373 setOperationAction(ISD::FPOW, MVT::f16, Promote);
374 setOperationAction(ISD::FLOG, MVT::f16, Custom);
375 setOperationAction(ISD::FEXP, MVT::f16, Custom);
376 setOperationAction(ISD::FLOG10, MVT::f16, Custom);
377 }
378
379 // v_mad_f32 does not support denormals. We report it as unconditionally
380 // legal, and the context where it is formed will disallow it when fp32
381 // denormals are enabled.
382 setOperationAction(ISD::FMAD, MVT::f32, Legal);
383
384 if (!Subtarget->hasBFI()) {
385 // fcopysign can be done in a single instruction with BFI.
386 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
387 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
388 }
389
390 if (!Subtarget->hasBCNT(32))
391 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
392
393 if (!Subtarget->hasBCNT(64))
394 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
395
396 if (Subtarget->hasFFBH())
397 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
398
399 if (Subtarget->hasFFBL())
400 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
401
402 // We only really have 32-bit BFE instructions (and 16-bit on VI).
403 //
404 // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
405 // effort to match them now. We want this to be false for i64 cases when the
406 // extraction isn't restricted to the upper or lower half. Ideally we would
407 // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
408 // span the midpoint are probably relatively rare, so don't worry about them
409 // for now.
410 if (Subtarget->hasBFE())
411 setHasExtractBitsInsn(true);
412
413 setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
414 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom);
415 setOperationAction(ISD::FMINNUM, MVT::f64, Custom);
416 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom);
417
418
419 // These are really only legal for ieee_mode functions. We should be avoiding
420 // them for functions that don't have ieee_mode enabled, so just say they are
421 // legal.
422 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
423 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
424 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
425 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
426
427
428 if (Subtarget->haveRoundOpsF64()) {
429 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
430 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
431 setOperationAction(ISD::FRINT, MVT::f64, Legal);
432 } else {
433 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
434 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
435 setOperationAction(ISD::FRINT, MVT::f64, Custom);
436 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
437 }
438
439 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
440
441 setOperationAction(ISD::FSIN, MVT::f32, Custom);
442 setOperationAction(ISD::FCOS, MVT::f32, Custom);
443 setOperationAction(ISD::FDIV, MVT::f32, Custom);
444 setOperationAction(ISD::FDIV, MVT::f64, Custom);
445
446 if (Subtarget->has16BitInsts()) {
447 setOperationAction(ISD::Constant, MVT::i16, Legal);
448
449 setOperationAction(ISD::SMIN, MVT::i16, Legal);
450 setOperationAction(ISD::SMAX, MVT::i16, Legal);
451
452 setOperationAction(ISD::UMIN, MVT::i16, Legal);
453 setOperationAction(ISD::UMAX, MVT::i16, Legal);
454
455 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
456 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
457
458 setOperationAction(ISD::ROTR, MVT::i16, Promote);
459 setOperationAction(ISD::ROTL, MVT::i16, Promote);
460
461 setOperationAction(ISD::SDIV, MVT::i16, Promote);
462 setOperationAction(ISD::UDIV, MVT::i16, Promote);
463 setOperationAction(ISD::SREM, MVT::i16, Promote);
464 setOperationAction(ISD::UREM, MVT::i16, Promote);
465
466 setOperationAction(ISD::BSWAP, MVT::i16, Promote);
467 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
468
469 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
470 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
471 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
472 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
473 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
474
475 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
476
477 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
478
479 setOperationAction(ISD::LOAD, MVT::i16, Custom);
480
481 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
482
483 setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote);
484 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
485 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
486 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
487
488 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
489 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
490
491 // F16 - Constant Actions.
492 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
493
494 // F16 - Load/Store Actions.
495 setOperationAction(ISD::LOAD, MVT::f16, Promote);
496 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
497 setOperationAction(ISD::STORE, MVT::f16, Promote);
498 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
499
500 // F16 - VOP1 Actions.
501 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
502 setOperationAction(ISD::FCOS, MVT::f16, Promote);
503 setOperationAction(ISD::FSIN, MVT::f16, Promote);
504
505 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
506 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Custom);
507
508 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
509 setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
510 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
511 setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
512 setOperationAction(ISD::FROUND, MVT::f16, Custom);
513
514 // F16 - VOP2 Actions.
515 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
516 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
517
518 setOperationAction(ISD::FDIV, MVT::f16, Custom);
519
520 // F16 - VOP3 Actions.
521 setOperationAction(ISD::FMA, MVT::f16, Legal);
522 if (STI.hasMadF16())
523 setOperationAction(ISD::FMAD, MVT::f16, Legal);
524
525 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) {
526 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
527 switch (Op) {
528 case ISD::LOAD:
529 case ISD::STORE:
530 case ISD::BUILD_VECTOR:
531 case ISD::BITCAST:
532 case ISD::EXTRACT_VECTOR_ELT:
533 case ISD::INSERT_VECTOR_ELT:
534 case ISD::INSERT_SUBVECTOR:
535 case ISD::EXTRACT_SUBVECTOR:
536 case ISD::SCALAR_TO_VECTOR:
537 break;
538 case ISD::CONCAT_VECTORS:
539 setOperationAction(Op, VT, Custom);
540 break;
541 default:
542 setOperationAction(Op, VT, Expand);
543 break;
544 }
545 }
546 }
547
548 // XXX - Do these do anything? Vector constants turn into build_vector.
549 setOperationAction(ISD::Constant, MVT::v2i16, Legal);
550 setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal);
551
552 setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);
553 setOperationAction(ISD::UNDEF, MVT::v2f16, Legal);
554
555 setOperationAction(ISD::STORE, MVT::v2i16, Promote);
556 AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
557 setOperationAction(ISD::STORE, MVT::v2f16, Promote);
558 AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32);
559
560 setOperationAction(ISD::LOAD, MVT::v2i16, Promote);
561 AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32);
562 setOperationAction(ISD::LOAD, MVT::v2f16, Promote);
563 AddPromotedToType(ISD::LOAD, MVT::v2f16, MVT::i32);
564
565 setOperationAction(ISD::AND, MVT::v2i16, Promote);
566 AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);
567 setOperationAction(ISD::OR, MVT::v2i16, Promote);
568 AddPromotedToType(ISD::OR, MVT::v2i16, MVT::i32);
569 setOperationAction(ISD::XOR, MVT::v2i16, Promote);
570 AddPromotedToType(ISD::XOR, MVT::v2i16, MVT::i32);
571
572 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
573 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::v2i32);
574 setOperationAction(ISD::LOAD, MVT::v4f16, Promote);
575 AddPromotedToType(ISD::LOAD, MVT::v4f16, MVT::v2i32);
576
577 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
578 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
579 setOperationAction(ISD::STORE, MVT::v4f16, Promote);
580 AddPromotedToType(ISD::STORE, MVT::v4f16, MVT::v2i32);
581
582 setOperationAction(ISD::ANY_EXTEND, MVT::v2i32, Expand);
583 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i32, Expand);
584 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i32, Expand);
585 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand);
586
587 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Expand);
588 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand);
589 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Expand);
590
591 if (!Subtarget->hasVOP3PInsts()) {
592 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
593 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
594 }
595
596 setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
597 // This isn't really legal, but this avoids the legalizer unrolling it (and
598 // allows matching fneg (fabs x) patterns)
599 setOperationAction(ISD::FABS, MVT::v2f16, Legal);
600
601 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom);
602 setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
603 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal);
604 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal);
605
606 setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom);
607 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v4f16, Custom);
608
609 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand);
610 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand);
611 }
612
613 if (Subtarget->hasVOP3PInsts()) {
614 setOperationAction(ISD::ADD, MVT::v2i16, Legal);
615 setOperationAction(ISD::SUB, MVT::v2i16, Legal);
616 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
617 setOperationAction(ISD::SHL, MVT::v2i16, Legal);
618 setOperationAction(ISD::SRL, MVT::v2i16, Legal);
619 setOperationAction(ISD::SRA, MVT::v2i16, Legal);
620 setOperationAction(ISD::SMIN, MVT::v2i16, Legal);
621 setOperationAction(ISD::UMIN, MVT::v2i16, Legal);
622 setOperationAction(ISD::SMAX, MVT::v2i16, Legal);
623 setOperationAction(ISD::UMAX, MVT::v2i16, Legal);
624
625 setOperationAction(ISD::FADD, MVT::v2f16, Legal);
626 setOperationAction(ISD::FMUL, MVT::v2f16, Legal);
627 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
628
629 setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal);
630 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v2f16, Legal);
631
632 setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal);
633
634 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
635 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
636
637 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom);
638 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
639
640 setOperationAction(ISD::SHL, MVT::v4i16, Custom);
641 setOperationAction(ISD::SRA, MVT::v4i16, Custom);
642 setOperationAction(ISD::SRL, MVT::v4i16, Custom);
643 setOperationAction(ISD::ADD, MVT::v4i16, Custom);
644 setOperationAction(ISD::SUB, MVT::v4i16, Custom);
645 setOperationAction(ISD::MUL, MVT::v4i16, Custom);
646
647 setOperationAction(ISD::SMIN, MVT::v4i16, Custom);
648 setOperationAction(ISD::SMAX, MVT::v4i16, Custom);
649 setOperationAction(ISD::UMIN, MVT::v4i16, Custom);
650 setOperationAction(ISD::UMAX, MVT::v4i16, Custom);
651
652 setOperationAction(ISD::FADD, MVT::v4f16, Custom);
653 setOperationAction(ISD::FMUL, MVT::v4f16, Custom);
654 setOperationAction(ISD::FMA, MVT::v4f16, Custom);
655
656 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom);
657 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom);
658
659 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
660 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom);
661 setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom);
662
663 setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
664 setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
665 setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
666 }
667
668 setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
669 setOperationAction(ISD::FABS, MVT::v4f16, Custom);
670
671 if (Subtarget->has16BitInsts()) {
672 setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
673 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
674 setOperationAction(ISD::SELECT, MVT::v2f16, Promote);
675 AddPromotedToType(ISD::SELECT, MVT::v2f16, MVT::i32);
676 } else {
677 // Legalization hack.
678 setOperationAction(ISD::SELECT, MVT::v2i16, Custom);
679 setOperationAction(ISD::SELECT, MVT::v2f16, Custom);
680
681 setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
682 setOperationAction(ISD::FABS, MVT::v2f16, Custom);
683 }
684
685 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
686 setOperationAction(ISD::SELECT, VT, Custom);
687 }
688
689 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
690 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
691 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
692 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
693 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f16, Custom);
694 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i16, Custom);
695 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
696
697 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2f16, Custom);
698 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2i16, Custom);
699 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4f16, Custom);
700 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4i16, Custom);
701 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v8f16, Custom);
702 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
703 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::f16, Custom);
704 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom);
705 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
706
707 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
708 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
709 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
710 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
711 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4i16, Custom);
712 setOperationAction(ISD::INTRINSIC_VOID, MVT::f16, Custom);
713 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
714 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
715
716 setTargetDAGCombine(ISD::ADD);
717 setTargetDAGCombine(ISD::ADDCARRY);
718 setTargetDAGCombine(ISD::SUB);
719 setTargetDAGCombine(ISD::SUBCARRY);
720 setTargetDAGCombine(ISD::FADD);
721 setTargetDAGCombine(ISD::FSUB);
722 setTargetDAGCombine(ISD::FMINNUM);
723 setTargetDAGCombine(ISD::FMAXNUM);
724 setTargetDAGCombine(ISD::FMINNUM_IEEE);
725 setTargetDAGCombine(ISD::FMAXNUM_IEEE);
726 setTargetDAGCombine(ISD::FMA);
727 setTargetDAGCombine(ISD::SMIN);
728 setTargetDAGCombine(ISD::SMAX);
729 setTargetDAGCombine(ISD::UMIN);
730 setTargetDAGCombine(ISD::UMAX);
731 setTargetDAGCombine(ISD::SETCC);
732 setTargetDAGCombine(ISD::AND);
733 setTargetDAGCombine(ISD::OR);
734 setTargetDAGCombine(ISD::XOR);
735 setTargetDAGCombine(ISD::SINT_TO_FP);
736 setTargetDAGCombine(ISD::UINT_TO_FP);
737 setTargetDAGCombine(ISD::FCANONICALIZE);
738 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
739 setTargetDAGCombine(ISD::ZERO_EXTEND);
740 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
741 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
742 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
743
744 // All memory operations. Some folding on the pointer operand is done to help
745 // matching the constant offsets in the addressing modes.
746 setTargetDAGCombine(ISD::LOAD);
747 setTargetDAGCombine(ISD::STORE);
748 setTargetDAGCombine(ISD::ATOMIC_LOAD);
749 setTargetDAGCombine(ISD::ATOMIC_STORE);
750 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
751 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
752 setTargetDAGCombine(ISD::ATOMIC_SWAP);
753 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
754 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
755 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
756 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
757 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
758 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
759 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
760 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
761 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
762 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
763 setTargetDAGCombine(ISD::ATOMIC_LOAD_FADD);
764
765 setSchedulingPreference(Sched::RegPressure);
766}
767
768const GCNSubtarget *SITargetLowering::getSubtarget() const {
769 return Subtarget;
770}
771
772//===----------------------------------------------------------------------===//
773// TargetLowering queries
774//===----------------------------------------------------------------------===//
775
776// v_mad_mix* support a conversion from f16 to f32.
777//
778// There is only one special case when denormals are enabled we don't currently,
779// where this is OK to use.
780bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
781 EVT DestVT, EVT SrcVT) const {
782 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||
783 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
784 DestVT.getScalarType() == MVT::f32 &&
785 SrcVT.getScalarType() == MVT::f16 &&
786 !hasFP32Denormals(DAG.getMachineFunction());
787}
788
789bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
790 // SI has some legal vector types, but no legal vector operations. Say no
791 // shuffles are legal in order to prefer scalarizing some vector operations.
792 return false;
793}
794
795MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
796 CallingConv::ID CC,
797 EVT VT) const {
798 if (CC == CallingConv::AMDGPU_KERNEL)
799 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
800
801 if (VT.isVector()) {
802 EVT ScalarVT = VT.getScalarType();
803 unsigned Size = ScalarVT.getSizeInBits();
804 if (Size == 32)
805 return ScalarVT.getSimpleVT();
806
807 if (Size > 32)
808 return MVT::i32;
809
810 if (Size == 16 && Subtarget->has16BitInsts())
811 return VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
812 } else if (VT.getSizeInBits() > 32)
813 return MVT::i32;
814
815 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
816}
817
818unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
819 CallingConv::ID CC,
820 EVT VT) const {
821 if (CC == CallingConv::AMDGPU_KERNEL)
822 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
823
824 if (VT.isVector()) {
825 unsigned NumElts = VT.getVectorNumElements();
826 EVT ScalarVT = VT.getScalarType();
827 unsigned Size = ScalarVT.getSizeInBits();
828
829 if (Size == 32)
830 return NumElts;
831
832 if (Size > 32)
833 return NumElts * ((Size + 31) / 32);
834
835 if (Size == 16 && Subtarget->has16BitInsts())
836 return (NumElts + 1) / 2;
837 } else if (VT.getSizeInBits() > 32)
838 return (VT.getSizeInBits() + 31) / 32;
839
840 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
841}
842
843unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
844 LLVMContext &Context, CallingConv::ID CC,
845 EVT VT, EVT &IntermediateVT,
846 unsigned &NumIntermediates, MVT &RegisterVT) const {
847 if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
848 unsigned NumElts = VT.getVectorNumElements();
849 EVT ScalarVT = VT.getScalarType();
850 unsigned Size = ScalarVT.getSizeInBits();
851 if (Size == 32) {
852 RegisterVT = ScalarVT.getSimpleVT();
853 IntermediateVT = RegisterVT;
854 NumIntermediates = NumElts;
855 return NumIntermediates;
856 }
857
858 if (Size > 32) {
859 RegisterVT = MVT::i32;
860 IntermediateVT = RegisterVT;
861 NumIntermediates = NumElts * ((Size + 31) / 32);
862 return NumIntermediates;
863 }
864
865 // FIXME: We should fix the ABI to be the same on targets without 16-bit
866 // support, but unless we can properly handle 3-vectors, it will be still be
867 // inconsistent.
868 if (Size == 16 && Subtarget->has16BitInsts()) {
869 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
870 IntermediateVT = RegisterVT;
871 NumIntermediates = (NumElts + 1) / 2;
872 return NumIntermediates;
873 }
874 }
875
876 return TargetLowering::getVectorTypeBreakdownForCallingConv(
877 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
878}
879
880static MVT memVTFromAggregate(Type *Ty) {
881 // Only limited forms of aggregate type currently expected.
882 assert(Ty->isStructTy() && "Expected struct type")((Ty->isStructTy() && "Expected struct type") ? static_cast
<void> (0) : __assert_fail ("Ty->isStructTy() && \"Expected struct type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 882, __PRETTY_FUNCTION__))
;
883
884
885 Type *ElementType = nullptr;
886 unsigned NumElts;
887 if (Ty->getContainedType(0)->isVectorTy()) {
888 VectorType *VecComponent = cast<VectorType>(Ty->getContainedType(0));
889 ElementType = VecComponent->getElementType();
890 NumElts = VecComponent->getNumElements();
891 } else {
892 ElementType = Ty->getContainedType(0);
893 NumElts = 1;
894 }
895
896 assert((Ty->getContainedType(1) && Ty->getContainedType(1)->isIntegerTy(32)) && "Expected int32 type")(((Ty->getContainedType(1) && Ty->getContainedType
(1)->isIntegerTy(32)) && "Expected int32 type") ? static_cast
<void> (0) : __assert_fail ("(Ty->getContainedType(1) && Ty->getContainedType(1)->isIntegerTy(32)) && \"Expected int32 type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 896, __PRETTY_FUNCTION__))
;
897
898 // Calculate the size of the memVT type from the aggregate
899 unsigned Pow2Elts = 0;
900 unsigned ElementSize;
901 switch (ElementType->getTypeID()) {
902 default:
903 llvm_unreachable("Unknown type!")::llvm::llvm_unreachable_internal("Unknown type!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 903)
;
904 case Type::IntegerTyID:
905 ElementSize = cast<IntegerType>(ElementType)->getBitWidth();
906 break;
907 case Type::HalfTyID:
908 ElementSize = 16;
909 break;
910 case Type::FloatTyID:
911 ElementSize = 32;
912 break;
913 }
914 unsigned AdditionalElts = ElementSize == 16 ? 2 : 1;
915 Pow2Elts = 1 << Log2_32_Ceil(NumElts + AdditionalElts);
916
917 return MVT::getVectorVT(MVT::getVT(ElementType, false),
918 Pow2Elts);
919}
920
921bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
922 const CallInst &CI,
923 MachineFunction &MF,
924 unsigned IntrID) const {
925 if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
926 AMDGPU::lookupRsrcIntrinsic(IntrID)) {
927 AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
928 (Intrinsic::ID)IntrID);
929 if (Attr.hasFnAttribute(Attribute::ReadNone))
930 return false;
931
932 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
933
934 if (RsrcIntr->IsImage) {
935 Info.ptrVal = MFI->getImagePSV(
936 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
937 CI.getArgOperand(RsrcIntr->RsrcArg));
938 Info.align.reset();
939 } else {
940 Info.ptrVal = MFI->getBufferPSV(
941 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
942 CI.getArgOperand(RsrcIntr->RsrcArg));
943 }
944
945 Info.flags = MachineMemOperand::MODereferenceable;
946 if (Attr.hasFnAttribute(Attribute::ReadOnly)) {
947 Info.opc = ISD::INTRINSIC_W_CHAIN;
948 Info.memVT = MVT::getVT(CI.getType(), true);
949 if (Info.memVT == MVT::Other) {
950 // Some intrinsics return an aggregate type - special case to work out
951 // the correct memVT
952 Info.memVT = memVTFromAggregate(CI.getType());
953 }
954 Info.flags |= MachineMemOperand::MOLoad;
955 } else if (Attr.hasFnAttribute(Attribute::WriteOnly)) {
956 Info.opc = ISD::INTRINSIC_VOID;
957 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
958 Info.flags |= MachineMemOperand::MOStore;
959 } else {
960 // Atomic
961 Info.opc = ISD::INTRINSIC_W_CHAIN;
962 Info.memVT = MVT::getVT(CI.getType());
963 Info.flags = MachineMemOperand::MOLoad |
964 MachineMemOperand::MOStore |
965 MachineMemOperand::MODereferenceable;
966
967 // XXX - Should this be volatile without known ordering?
968 Info.flags |= MachineMemOperand::MOVolatile;
969 }
970 return true;
971 }
972
973 switch (IntrID) {
974 case Intrinsic::amdgcn_atomic_inc:
975 case Intrinsic::amdgcn_atomic_dec:
976 case Intrinsic::amdgcn_ds_ordered_add:
977 case Intrinsic::amdgcn_ds_ordered_swap:
978 case Intrinsic::amdgcn_ds_fadd:
979 case Intrinsic::amdgcn_ds_fmin:
980 case Intrinsic::amdgcn_ds_fmax: {
981 Info.opc = ISD::INTRINSIC_W_CHAIN;
982 Info.memVT = MVT::getVT(CI.getType());
983 Info.ptrVal = CI.getOperand(0);
984 Info.align.reset();
985 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
986
987 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(4));
988 if (!Vol->isZero())
989 Info.flags |= MachineMemOperand::MOVolatile;
990
991 return true;
992 }
993 case Intrinsic::amdgcn_buffer_atomic_fadd: {
994 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
995
996 Info.opc = ISD::INTRINSIC_VOID;
997 Info.memVT = MVT::getVT(CI.getOperand(0)->getType());
998 Info.ptrVal = MFI->getBufferPSV(
999 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
1000 CI.getArgOperand(1));
1001 Info.align.reset();
1002 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1003
1004 const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
1005 if (!Vol || !Vol->isZero())
1006 Info.flags |= MachineMemOperand::MOVolatile;
1007
1008 return true;
1009 }
1010 case Intrinsic::amdgcn_global_atomic_fadd: {
1011 Info.opc = ISD::INTRINSIC_VOID;
1012 Info.memVT = MVT::getVT(CI.getOperand(0)->getType()
1013 ->getPointerElementType());
1014 Info.ptrVal = CI.getOperand(0);
1015 Info.align.reset();
1016 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1017
1018 return true;
1019 }
1020 case Intrinsic::amdgcn_ds_append:
1021 case Intrinsic::amdgcn_ds_consume: {
1022 Info.opc = ISD::INTRINSIC_W_CHAIN;
1023 Info.memVT = MVT::getVT(CI.getType());
1024 Info.ptrVal = CI.getOperand(0);
1025 Info.align.reset();
1026 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1027
1028 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(1));
1029 if (!Vol->isZero())
1030 Info.flags |= MachineMemOperand::MOVolatile;
1031
1032 return true;
1033 }
1034 case Intrinsic::amdgcn_ds_gws_init:
1035 case Intrinsic::amdgcn_ds_gws_barrier:
1036 case Intrinsic::amdgcn_ds_gws_sema_v:
1037 case Intrinsic::amdgcn_ds_gws_sema_br:
1038 case Intrinsic::amdgcn_ds_gws_sema_p:
1039 case Intrinsic::amdgcn_ds_gws_sema_release_all: {
1040 Info.opc = ISD::INTRINSIC_VOID;
1041
1042 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1043 Info.ptrVal =
1044 MFI->getGWSPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1045
1046 // This is an abstract access, but we need to specify a type and size.
1047 Info.memVT = MVT::i32;
1048 Info.size = 4;
1049 Info.align = Align(4);
1050
1051 Info.flags = MachineMemOperand::MOStore;
1052 if (IntrID == Intrinsic::amdgcn_ds_gws_barrier)
1053 Info.flags = MachineMemOperand::MOLoad;
1054 return true;
1055 }
1056 default:
1057 return false;
1058 }
1059}
1060
1061bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
1062 SmallVectorImpl<Value*> &Ops,
1063 Type *&AccessTy) const {
1064 switch (II->getIntrinsicID()) {
1065 case Intrinsic::amdgcn_atomic_inc:
1066 case Intrinsic::amdgcn_atomic_dec:
1067 case Intrinsic::amdgcn_ds_ordered_add:
1068 case Intrinsic::amdgcn_ds_ordered_swap:
1069 case Intrinsic::amdgcn_ds_fadd:
1070 case Intrinsic::amdgcn_ds_fmin:
1071 case Intrinsic::amdgcn_ds_fmax: {
1072 Value *Ptr = II->getArgOperand(0);
1073 AccessTy = II->getType();
1074 Ops.push_back(Ptr);
1075 return true;
1076 }
1077 default:
1078 return false;
1079 }
1080}
1081
1082bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
1083 if (!Subtarget->hasFlatInstOffsets()) {
1084 // Flat instructions do not have offsets, and only have the register
1085 // address.
1086 return AM.BaseOffs == 0 && AM.Scale == 0;
1087 }
1088
1089 return AM.Scale == 0 &&
1090 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset(
1091 AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS,
1092 /*Signed=*/false));
1093}
1094
1095bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const {
1096 if (Subtarget->hasFlatGlobalInsts())
1097 return AM.Scale == 0 &&
1098 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset(
1099 AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS,
1100 /*Signed=*/true));
1101
1102 if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) {
1103 // Assume the we will use FLAT for all global memory accesses
1104 // on VI.
1105 // FIXME: This assumption is currently wrong. On VI we still use
1106 // MUBUF instructions for the r + i addressing mode. As currently
1107 // implemented, the MUBUF instructions only work on buffer < 4GB.
1108 // It may be possible to support > 4GB buffers with MUBUF instructions,
1109 // by setting the stride value in the resource descriptor which would
1110 // increase the size limit to (stride * 4GB). However, this is risky,
1111 // because it has never been validated.
1112 return isLegalFlatAddressingMode(AM);
1113 }
1114
1115 return isLegalMUBUFAddressingMode(AM);
1116}
1117
1118bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
1119 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
1120 // additionally can do r + r + i with addr64. 32-bit has more addressing
1121 // mode options. Depending on the resource constant, it can also do
1122 // (i64 r0) + (i32 r1) * (i14 i).
1123 //
1124 // Private arrays end up using a scratch buffer most of the time, so also
1125 // assume those use MUBUF instructions. Scratch loads / stores are currently
1126 // implemented as mubuf instructions with offen bit set, so slightly
1127 // different than the normal addr64.
1128 if (!isUInt<12>(AM.BaseOffs))
1129 return false;
1130
1131 // FIXME: Since we can split immediate into soffset and immediate offset,
1132 // would it make sense to allow any immediate?
1133
1134 switch (AM.Scale) {
1135 case 0: // r + i or just i, depending on HasBaseReg.
1136 return true;
1137 case 1:
1138 return true; // We have r + r or r + i.
1139 case 2:
1140 if (AM.HasBaseReg) {
1141 // Reject 2 * r + r.
1142 return false;
1143 }
1144
1145 // Allow 2 * r as r + r
1146 // Or 2 * r + i is allowed as r + r + i.
1147 return true;
1148 default: // Don't allow n * r
1149 return false;
1150 }
1151}
1152
1153bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
1154 const AddrMode &AM, Type *Ty,
1155 unsigned AS, Instruction *I) const {
1156 // No global is ever allowed as a base.
1157 if (AM.BaseGV)
1158 return false;
1159
1160 if (AS == AMDGPUAS::GLOBAL_ADDRESS)
1161 return isLegalGlobalAddressingMode(AM);
1162
1163 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
1164 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
1165 AS == AMDGPUAS::BUFFER_FAT_POINTER) {
1166 // If the offset isn't a multiple of 4, it probably isn't going to be
1167 // correctly aligned.
1168 // FIXME: Can we get the real alignment here?
1169 if (AM.BaseOffs % 4 != 0)
1170 return isLegalMUBUFAddressingMode(AM);
1171
1172 // There are no SMRD extloads, so if we have to do a small type access we
1173 // will use a MUBUF load.
1174 // FIXME?: We also need to do this if unaligned, but we don't know the
1175 // alignment here.
1176 if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4)
1177 return isLegalGlobalAddressingMode(AM);
1178
1179 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1180 // SMRD instructions have an 8-bit, dword offset on SI.
1181 if (!isUInt<8>(AM.BaseOffs / 4))
1182 return false;
1183 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
1184 // On CI+, this can also be a 32-bit literal constant offset. If it fits
1185 // in 8-bits, it can use a smaller encoding.
1186 if (!isUInt<32>(AM.BaseOffs / 4))
1187 return false;
1188 } else if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
1189 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
1190 if (!isUInt<20>(AM.BaseOffs))
1191 return false;
1192 } else
1193 llvm_unreachable("unhandled generation")::llvm::llvm_unreachable_internal("unhandled generation", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1193)
;
1194
1195 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1196 return true;
1197
1198 if (AM.Scale == 1 && AM.HasBaseReg)
1199 return true;
1200
1201 return false;
1202
1203 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1204 return isLegalMUBUFAddressingMode(AM);
1205 } else if (AS == AMDGPUAS::LOCAL_ADDRESS ||
1206 AS == AMDGPUAS::REGION_ADDRESS) {
1207 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
1208 // field.
1209 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
1210 // an 8-bit dword offset but we don't know the alignment here.
1211 if (!isUInt<16>(AM.BaseOffs))
1212 return false;
1213
1214 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1215 return true;
1216
1217 if (AM.Scale == 1 && AM.HasBaseReg)
1218 return true;
1219
1220 return false;
1221 } else if (AS == AMDGPUAS::FLAT_ADDRESS ||
1222 AS == AMDGPUAS::UNKNOWN_ADDRESS_SPACE) {
1223 // For an unknown address space, this usually means that this is for some
1224 // reason being used for pure arithmetic, and not based on some addressing
1225 // computation. We don't have instructions that compute pointers with any
1226 // addressing modes, so treat them as having no offset like flat
1227 // instructions.
1228 return isLegalFlatAddressingMode(AM);
1229 } else {
1230 llvm_unreachable("unhandled address space")::llvm::llvm_unreachable_internal("unhandled address space", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1230)
;
1231 }
1232}
1233
1234bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1235 const SelectionDAG &DAG) const {
1236 if (AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS) {
1237 return (MemVT.getSizeInBits() <= 4 * 32);
1238 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1239 unsigned MaxPrivateBits = 8 * getSubtarget()->getMaxPrivateElementSize();
1240 return (MemVT.getSizeInBits() <= MaxPrivateBits);
1241 } else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
1242 return (MemVT.getSizeInBits() <= 2 * 32);
1243 }
1244 return true;
1245}
1246
1247bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
1248 unsigned Size, unsigned AddrSpace, unsigned Align,
1249 MachineMemOperand::Flags Flags, bool *IsFast) const {
1250 if (IsFast)
1251 *IsFast = false;
1252
1253 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1254 AddrSpace == AMDGPUAS::REGION_ADDRESS) {
1255 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
1256 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
1257 // with adjacent offsets.
1258 bool AlignedBy4 = (Align % 4 == 0);
1259 if (IsFast)
1260 *IsFast = AlignedBy4;
1261
1262 return AlignedBy4;
1263 }
1264
1265 // FIXME: We have to be conservative here and assume that flat operations
1266 // will access scratch. If we had access to the IR function, then we
1267 // could determine if any private memory was used in the function.
1268 if (!Subtarget->hasUnalignedScratchAccess() &&
1269 (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
1270 AddrSpace == AMDGPUAS::FLAT_ADDRESS)) {
1271 bool AlignedBy4 = Align >= 4;
1272 if (IsFast)
1273 *IsFast = AlignedBy4;
1274
1275 return AlignedBy4;
1276 }
1277
1278 if (Subtarget->hasUnalignedBufferAccess()) {
1279 // If we have an uniform constant load, it still requires using a slow
1280 // buffer instruction if unaligned.
1281 if (IsFast) {
1282 *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
1283 AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ?
1284 (Align % 4 == 0) : true;
1285 }
1286
1287 return true;
1288 }
1289
1290 // Smaller than dword value must be aligned.
1291 if (Size < 32)
1292 return false;
1293
1294 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
1295 // byte-address are ignored, thus forcing Dword alignment.
1296 // This applies to private, global, and constant memory.
1297 if (IsFast)
1298 *IsFast = true;
1299
1300 return Size >= 32 && Align >= 4;
1301}
1302
1303bool SITargetLowering::allowsMisalignedMemoryAccesses(
1304 EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags,
1305 bool *IsFast) const {
1306 if (IsFast)
1307 *IsFast = false;
1308
1309 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
1310 // which isn't a simple VT.
1311 // Until MVT is extended to handle this, simply check for the size and
1312 // rely on the condition below: allow accesses if the size is a multiple of 4.
1313 if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
1314 VT.getStoreSize() > 16)) {
1315 return false;
1316 }
1317
1318 return allowsMisalignedMemoryAccessesImpl(VT.getSizeInBits(), AddrSpace,
1319 Align, Flags, IsFast);
1320}
1321
1322EVT SITargetLowering::getOptimalMemOpType(
1323 uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset,
1324 bool ZeroMemset, bool MemcpyStrSrc,
1325 const AttributeList &FuncAttributes) const {
1326 // FIXME: Should account for address space here.
1327
1328 // The default fallback uses the private pointer size as a guess for a type to
1329 // use. Make sure we switch these to 64-bit accesses.
1330
1331 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
1332 return MVT::v4i32;
1333
1334 if (Size >= 8 && DstAlign >= 4)
1335 return MVT::v2i32;
1336
1337 // Use the default.
1338 return MVT::Other;
1339}
1340
1341bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1342 unsigned DestAS) const {
1343 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
1344}
1345
1346bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {
1347 const MemSDNode *MemNode = cast<MemSDNode>(N);
1348 const Value *Ptr = MemNode->getMemOperand()->getValue();
1349 const Instruction *I = dyn_cast_or_null<Instruction>(Ptr);
1350 return I && I->getMetadata("amdgpu.noclobber");
1351}
1352
1353bool SITargetLowering::isFreeAddrSpaceCast(unsigned SrcAS,
1354 unsigned DestAS) const {
1355 // Flat -> private/local is a simple truncate.
1356 // Flat -> global is no-op
1357 if (SrcAS == AMDGPUAS::FLAT_ADDRESS)
1358 return true;
1359
1360 return isNoopAddrSpaceCast(SrcAS, DestAS);
1361}
1362
1363bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
1364 const MemSDNode *MemNode = cast<MemSDNode>(N);
1365
1366 return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
1367}
1368
1369TargetLoweringBase::LegalizeTypeAction
1370SITargetLowering::getPreferredVectorAction(MVT VT) const {
1371 int NumElts = VT.getVectorNumElements();
1372 if (NumElts != 1 && VT.getScalarType().bitsLE(MVT::i16))
1373 return VT.isPow2VectorType() ? TypeSplitVector : TypeWidenVector;
1374 return TargetLoweringBase::getPreferredVectorAction(VT);
1375}
1376
1377bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
1378 Type *Ty) const {
1379 // FIXME: Could be smarter if called for vector constants.
1380 return true;
1381}
1382
1383bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
1384 if (Subtarget->has16BitInsts() && VT == MVT::i16) {
1385 switch (Op) {
1386 case ISD::LOAD:
1387 case ISD::STORE:
1388
1389 // These operations are done with 32-bit instructions anyway.
1390 case ISD::AND:
1391 case ISD::OR:
1392 case ISD::XOR:
1393 case ISD::SELECT:
1394 // TODO: Extensions?
1395 return true;
1396 default:
1397 return false;
1398 }
1399 }
1400
1401 // SimplifySetCC uses this function to determine whether or not it should
1402 // create setcc with i1 operands. We don't have instructions for i1 setcc.
1403 if (VT == MVT::i1 && Op == ISD::SETCC)
1404 return false;
1405
1406 return TargetLowering::isTypeDesirableForOp(Op, VT);
1407}
1408
1409SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
1410 const SDLoc &SL,
1411 SDValue Chain,
1412 uint64_t Offset) const {
1413 const DataLayout &DL = DAG.getDataLayout();
1414 MachineFunction &MF = DAG.getMachineFunction();
1415 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1416
1417 const ArgDescriptor *InputPtrReg;
1418 const TargetRegisterClass *RC;
1419
1420 std::tie(InputPtrReg, RC)
1421 = Info->getPreloadedValue(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
1422
1423 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1424 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
1425 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
1426 MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
1427
1428 return DAG.getObjectPtrOffset(SL, BasePtr, Offset);
1429}
1430
1431SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
1432 const SDLoc &SL) const {
1433 uint64_t Offset = getImplicitParameterOffset(DAG.getMachineFunction(),
1434 FIRST_IMPLICIT);
1435 return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset);
1436}
1437
1438SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
1439 const SDLoc &SL, SDValue Val,
1440 bool Signed,
1441 const ISD::InputArg *Arg) const {
1442 // First, if it is a widened vector, narrow it.
1443 if (VT.isVector() &&
1444 VT.getVectorNumElements() != MemVT.getVectorNumElements()) {
1445 EVT NarrowedVT =
1446 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(),
1447 VT.getVectorNumElements());
1448 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val,
1449 DAG.getConstant(0, SL, MVT::i32));
1450 }
1451
1452 // Then convert the vector elements or scalar value.
1453 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
1454 VT.bitsLT(MemVT)) {
1455 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
1456 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT));
1457 }
1458
1459 if (MemVT.isFloatingPoint())
1460 Val = getFPExtOrFPTrunc(DAG, Val, SL, VT);
1461 else if (Signed)
1462 Val = DAG.getSExtOrTrunc(Val, SL, VT);
1463 else
1464 Val = DAG.getZExtOrTrunc(Val, SL, VT);
1465
1466 return Val;
1467}
1468
1469SDValue SITargetLowering::lowerKernargMemParameter(
1470 SelectionDAG &DAG, EVT VT, EVT MemVT,
1471 const SDLoc &SL, SDValue Chain,
1472 uint64_t Offset, unsigned Align, bool Signed,
1473 const ISD::InputArg *Arg) const {
1474 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
1475
1476 // Try to avoid using an extload by loading earlier than the argument address,
1477 // and extracting the relevant bits. The load should hopefully be merged with
1478 // the previous argument.
1479 if (MemVT.getStoreSize() < 4 && Align < 4) {
1480 // TODO: Handle align < 4 and size >= 4 (can happen with packed structs).
1481 int64_t AlignDownOffset = alignDown(Offset, 4);
1482 int64_t OffsetDiff = Offset - AlignDownOffset;
1483
1484 EVT IntVT = MemVT.changeTypeToInteger();
1485
1486 // TODO: If we passed in the base kernel offset we could have a better
1487 // alignment than 4, but we don't really need it.
1488 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
1489 SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, 4,
1490 MachineMemOperand::MODereferenceable |
1491 MachineMemOperand::MOInvariant);
1492
1493 SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
1494 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
1495
1496 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract);
1497 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal);
1498 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg);
1499
1500
1501 return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
1502 }
1503
1504 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
1505 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Align,
1506 MachineMemOperand::MODereferenceable |
1507 MachineMemOperand::MOInvariant);
1508
1509 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg);
1510 return DAG.getMergeValues({ Val, Load.getValue(1) }, SL);
1511}
1512
1513SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
1514 const SDLoc &SL, SDValue Chain,
1515 const ISD::InputArg &Arg) const {
1516 MachineFunction &MF = DAG.getMachineFunction();
1517 MachineFrameInfo &MFI = MF.getFrameInfo();
1518
1519 if (Arg.Flags.isByVal()) {
1520 unsigned Size = Arg.Flags.getByValSize();
1521 int FrameIdx = MFI.CreateFixedObject(Size, VA.getLocMemOffset(), false);
1522 return DAG.getFrameIndex(FrameIdx, MVT::i32);
1523 }
1524
1525 unsigned ArgOffset = VA.getLocMemOffset();
1526 unsigned ArgSize = VA.getValVT().getStoreSize();
1527
1528 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, true);
1529
1530 // Create load nodes to retrieve arguments from the stack.
1531 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1532 SDValue ArgValue;
1533
1534 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1535 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1536 MVT MemVT = VA.getValVT();
1537
1538 switch (VA.getLocInfo()) {
1539 default:
1540 break;
1541 case CCValAssign::BCvt:
1542 MemVT = VA.getLocVT();
1543 break;
1544 case CCValAssign::SExt:
1545 ExtType = ISD::SEXTLOAD;
1546 break;
1547 case CCValAssign::ZExt:
1548 ExtType = ISD::ZEXTLOAD;
1549 break;
1550 case CCValAssign::AExt:
1551 ExtType = ISD::EXTLOAD;
1552 break;
1553 }
1554
1555 ArgValue = DAG.getExtLoad(
1556 ExtType, SL, VA.getLocVT(), Chain, FIN,
1557 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
1558 MemVT);
1559 return ArgValue;
1560}
1561
1562SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,
1563 const SIMachineFunctionInfo &MFI,
1564 EVT VT,
1565 AMDGPUFunctionArgInfo::PreloadedValue PVID) const {
1566 const ArgDescriptor *Reg;
1567 const TargetRegisterClass *RC;
1568
1569 std::tie(Reg, RC) = MFI.getPreloadedValue(PVID);
1570 return CreateLiveInRegister(DAG, RC, Reg->getRegister(), VT);
1571}
1572
1573static void processShaderInputArgs(SmallVectorImpl<ISD::InputArg> &Splits,
1574 CallingConv::ID CallConv,
1575 ArrayRef<ISD::InputArg> Ins,
1576 BitVector &Skipped,
1577 FunctionType *FType,
1578 SIMachineFunctionInfo *Info) {
1579 for (unsigned I = 0, E = Ins.size(), PSInputNum = 0; I != E; ++I) {
1580 const ISD::InputArg *Arg = &Ins[I];
1581
1582 assert((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) &&(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "vector type argument should have been split"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1583, __PRETTY_FUNCTION__))
1583 "vector type argument should have been split")(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "vector type argument should have been split"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1583, __PRETTY_FUNCTION__))
;
1584
1585 // First check if it's a PS input addr.
1586 if (CallConv == CallingConv::AMDGPU_PS &&
1587 !Arg->Flags.isInReg() && PSInputNum <= 15) {
1588 bool SkipArg = !Arg->Used && !Info->isPSInputAllocated(PSInputNum);
1589
1590 // Inconveniently only the first part of the split is marked as isSplit,
1591 // so skip to the end. We only want to increment PSInputNum once for the
1592 // entire split argument.
1593 if (Arg->Flags.isSplit()) {
1594 while (!Arg->Flags.isSplitEnd()) {
1595 assert((!Arg->VT.isVector() ||(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1597, __PRETTY_FUNCTION__))
1596 Arg->VT.getScalarSizeInBits() == 16) &&(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1597, __PRETTY_FUNCTION__))
1597 "unexpected vector split in ps argument type")(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1597, __PRETTY_FUNCTION__))
;
1598 if (!SkipArg)
1599 Splits.push_back(*Arg);
1600 Arg = &Ins[++I];
1601 }
1602 }
1603
1604 if (SkipArg) {
1605 // We can safely skip PS inputs.
1606 Skipped.set(Arg->getOrigArgIndex());
1607 ++PSInputNum;
1608 continue;
1609 }
1610
1611 Info->markPSInputAllocated(PSInputNum);
1612 if (Arg->Used)
1613 Info->markPSInputEnabled(PSInputNum);
1614
1615 ++PSInputNum;
1616 }
1617
1618 Splits.push_back(*Arg);
1619 }
1620}
1621
1622// Allocate special inputs passed in VGPRs.
1623void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,
1624 MachineFunction &MF,
1625 const SIRegisterInfo &TRI,
1626 SIMachineFunctionInfo &Info) const {
1627 const LLT S32 = LLT::scalar(32);
1628 MachineRegisterInfo &MRI = MF.getRegInfo();
1629
1630 if (Info.hasWorkItemIDX()) {
1631 Register Reg = AMDGPU::VGPR0;
1632 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1633
1634 CCInfo.AllocateReg(Reg);
1635 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg));
1636 }
1637
1638 if (Info.hasWorkItemIDY()) {
1639 Register Reg = AMDGPU::VGPR1;
1640 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1641
1642 CCInfo.AllocateReg(Reg);
1643 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg));
1644 }
1645
1646 if (Info.hasWorkItemIDZ()) {
1647 Register Reg = AMDGPU::VGPR2;
1648 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1649
1650 CCInfo.AllocateReg(Reg);
1651 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg));
1652 }
1653}
1654
1655// Try to allocate a VGPR at the end of the argument list, or if no argument
1656// VGPRs are left allocating a stack slot.
1657// If \p Mask is is given it indicates bitfield position in the register.
1658// If \p Arg is given use it with new ]p Mask instead of allocating new.
1659static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,
1660 ArgDescriptor Arg = ArgDescriptor()) {
1661 if (Arg.isSet())
1662 return ArgDescriptor::createArg(Arg, Mask);
1663
1664 ArrayRef<MCPhysReg> ArgVGPRs
1665 = makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), 32);
1666 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
1667 if (RegIdx == ArgVGPRs.size()) {
1668 // Spill to stack required.
1669 int64_t Offset = CCInfo.AllocateStack(4, 4);
1670
1671 return ArgDescriptor::createStack(Offset, Mask);
1672 }
1673
1674 unsigned Reg = ArgVGPRs[RegIdx];
1675 Reg = CCInfo.AllocateReg(Reg);
1676 assert(Reg != AMDGPU::NoRegister)((Reg != AMDGPU::NoRegister) ? static_cast<void> (0) : __assert_fail
("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1676, __PRETTY_FUNCTION__))
;
1677
1678 MachineFunction &MF = CCInfo.getMachineFunction();
1679 Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1680 MF.getRegInfo().setType(LiveInVReg, LLT::scalar(32));
1681 return ArgDescriptor::createRegister(Reg, Mask);
1682}
1683
1684static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,
1685 const TargetRegisterClass *RC,
1686 unsigned NumArgRegs) {
1687 ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
1688 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
1689 if (RegIdx == ArgSGPRs.size())
1690 report_fatal_error("ran out of SGPRs for arguments");
1691
1692 unsigned Reg = ArgSGPRs[RegIdx];
1693 Reg = CCInfo.AllocateReg(Reg);
1694 assert(Reg != AMDGPU::NoRegister)((Reg != AMDGPU::NoRegister) ? static_cast<void> (0) : __assert_fail
("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1694, __PRETTY_FUNCTION__))
;
1695
1696 MachineFunction &MF = CCInfo.getMachineFunction();
1697 MF.addLiveIn(Reg, RC);
1698 return ArgDescriptor::createRegister(Reg);
1699}
1700
1701static ArgDescriptor allocateSGPR32Input(CCState &CCInfo) {
1702 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
1703}
1704
1705static ArgDescriptor allocateSGPR64Input(CCState &CCInfo) {
1706 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);
1707}
1708
1709void SITargetLowering::allocateSpecialInputVGPRs(CCState &CCInfo,
1710 MachineFunction &MF,
1711 const SIRegisterInfo &TRI,
1712 SIMachineFunctionInfo &Info) const {
1713 const unsigned Mask = 0x3ff;
1714 ArgDescriptor Arg;
1715
1716 if (Info.hasWorkItemIDX()) {
1717 Arg = allocateVGPR32Input(CCInfo, Mask);
1718 Info.setWorkItemIDX(Arg);
1719 }
1720
1721 if (Info.hasWorkItemIDY()) {
1722 Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);
1723 Info.setWorkItemIDY(Arg);
1724 }
1725
1726 if (Info.hasWorkItemIDZ())
1727 Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));
1728}
1729
1730void SITargetLowering::allocateSpecialInputSGPRs(
1731 CCState &CCInfo,
1732 MachineFunction &MF,
1733 const SIRegisterInfo &TRI,
1734 SIMachineFunctionInfo &Info) const {
1735 auto &ArgInfo = Info.getArgInfo();
1736
1737 // TODO: Unify handling with private memory pointers.
1738
1739 if (Info.hasDispatchPtr())
1740 ArgInfo.DispatchPtr = allocateSGPR64Input(CCInfo);
1741
1742 if (Info.hasQueuePtr())
1743 ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo);
1744
1745 if (Info.hasKernargSegmentPtr())
1746 ArgInfo.KernargSegmentPtr = allocateSGPR64Input(CCInfo);
1747
1748 if (Info.hasDispatchID())
1749 ArgInfo.DispatchID = allocateSGPR64Input(CCInfo);
1750
1751 // flat_scratch_init is not applicable for non-kernel functions.
1752
1753 if (Info.hasWorkGroupIDX())
1754 ArgInfo.WorkGroupIDX = allocateSGPR32Input(CCInfo);
1755
1756 if (Info.hasWorkGroupIDY())
1757 ArgInfo.WorkGroupIDY = allocateSGPR32Input(CCInfo);
1758
1759 if (Info.hasWorkGroupIDZ())
1760 ArgInfo.WorkGroupIDZ = allocateSGPR32Input(CCInfo);
1761
1762 if (Info.hasImplicitArgPtr())
1763 ArgInfo.ImplicitArgPtr = allocateSGPR64Input(CCInfo);
1764}
1765
1766// Allocate special inputs passed in user SGPRs.
1767void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
1768 MachineFunction &MF,
1769 const SIRegisterInfo &TRI,
1770 SIMachineFunctionInfo &Info) const {
1771 if (Info.hasImplicitBufferPtr()) {
1772 unsigned ImplicitBufferPtrReg = Info.addImplicitBufferPtr(TRI);
1773 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
1774 CCInfo.AllocateReg(ImplicitBufferPtrReg);
1775 }
1776
1777 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
1778 if (Info.hasPrivateSegmentBuffer()) {
1779 unsigned PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
1780 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
1781 CCInfo.AllocateReg(PrivateSegmentBufferReg);
1782 }
1783
1784 if (Info.hasDispatchPtr()) {
1785 unsigned DispatchPtrReg = Info.addDispatchPtr(TRI);
1786 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
1787 CCInfo.AllocateReg(DispatchPtrReg);
1788 }
1789
1790 if (Info.hasQueuePtr()) {
1791 unsigned QueuePtrReg = Info.addQueuePtr(TRI);
1792 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
1793 CCInfo.AllocateReg(QueuePtrReg);
1794 }
1795
1796 if (Info.hasKernargSegmentPtr()) {
1797 MachineRegisterInfo &MRI = MF.getRegInfo();
1798 Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
1799 CCInfo.AllocateReg(InputPtrReg);
1800
1801 Register VReg = MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
1802 MRI.setType(VReg, LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
1803 }
1804
1805 if (Info.hasDispatchID()) {
1806 unsigned DispatchIDReg = Info.addDispatchID(TRI);
1807 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
1808 CCInfo.AllocateReg(DispatchIDReg);
1809 }
1810
1811 if (Info.hasFlatScratchInit()) {
1812 unsigned FlatScratchInitReg = Info.addFlatScratchInit(TRI);
1813 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
1814 CCInfo.AllocateReg(FlatScratchInitReg);
1815 }
1816
1817 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
1818 // these from the dispatch pointer.
1819}
1820
1821// Allocate special input registers that are initialized per-wave.
1822void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,
1823 MachineFunction &MF,
1824 SIMachineFunctionInfo &Info,
1825 CallingConv::ID CallConv,
1826 bool IsShader) const {
1827 if (Info.hasWorkGroupIDX()) {
1828 unsigned Reg = Info.addWorkGroupIDX();
1829 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1830 CCInfo.AllocateReg(Reg);
1831 }
1832
1833 if (Info.hasWorkGroupIDY()) {
1834 unsigned Reg = Info.addWorkGroupIDY();
1835 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1836 CCInfo.AllocateReg(Reg);
1837 }
1838
1839 if (Info.hasWorkGroupIDZ()) {
1840 unsigned Reg = Info.addWorkGroupIDZ();
1841 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1842 CCInfo.AllocateReg(Reg);
1843 }
1844
1845 if (Info.hasWorkGroupInfo()) {
1846 unsigned Reg = Info.addWorkGroupInfo();
1847 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1848 CCInfo.AllocateReg(Reg);
1849 }
1850
1851 if (Info.hasPrivateSegmentWaveByteOffset()) {
1852 // Scratch wave offset passed in system SGPR.
1853 unsigned PrivateSegmentWaveByteOffsetReg;
1854
1855 if (IsShader) {
1856 PrivateSegmentWaveByteOffsetReg =
1857 Info.getPrivateSegmentWaveByteOffsetSystemSGPR();
1858
1859 // This is true if the scratch wave byte offset doesn't have a fixed
1860 // location.
1861 if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) {
1862 PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
1863 Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
1864 }
1865 } else
1866 PrivateSegmentWaveByteOffsetReg = Info.addPrivateSegmentWaveByteOffset();
1867
1868 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
1869 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
1870 }
1871}
1872
1873static void reservePrivateMemoryRegs(const TargetMachine &TM,
1874 MachineFunction &MF,
1875 const SIRegisterInfo &TRI,
1876 SIMachineFunctionInfo &Info) {
1877 // Now that we've figured out where the scratch register inputs are, see if
1878 // should reserve the arguments and use them directly.
1879 MachineFrameInfo &MFI = MF.getFrameInfo();
1880 bool HasStackObjects = MFI.hasStackObjects();
1881 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1882
1883 // Record that we know we have non-spill stack objects so we don't need to
1884 // check all stack objects later.
1885 if (HasStackObjects)
1886 Info.setHasNonSpillStackObjects(true);
1887
1888 // Everything live out of a block is spilled with fast regalloc, so it's
1889 // almost certain that spilling will be required.
1890 if (TM.getOptLevel() == CodeGenOpt::None)
1891 HasStackObjects = true;
1892
1893 // For now assume stack access is needed in any callee functions, so we need
1894 // the scratch registers to pass in.
1895 bool RequiresStackAccess = HasStackObjects || MFI.hasCalls();
1896
1897 if (RequiresStackAccess && ST.isAmdHsaOrMesa(MF.getFunction())) {
1898 // If we have stack objects, we unquestionably need the private buffer
1899 // resource. For the Code Object V2 ABI, this will be the first 4 user
1900 // SGPR inputs. We can reserve those and use them directly.
1901
1902 Register PrivateSegmentBufferReg =
1903 Info.getPreloadedReg(AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER);
1904 Info.setScratchRSrcReg(PrivateSegmentBufferReg);
1905 } else {
1906 unsigned ReservedBufferReg = TRI.reservedPrivateSegmentBufferReg(MF);
1907 // We tentatively reserve the last registers (skipping the last registers
1908 // which may contain VCC, FLAT_SCR, and XNACK). After register allocation,
1909 // we'll replace these with the ones immediately after those which were
1910 // really allocated. In the prologue copies will be inserted from the
1911 // argument to these reserved registers.
1912
1913 // Without HSA, relocations are used for the scratch pointer and the
1914 // buffer resource setup is always inserted in the prologue. Scratch wave
1915 // offset is still in an input SGPR.
1916 Info.setScratchRSrcReg(ReservedBufferReg);
1917 }
1918
1919 // hasFP should be accurate for kernels even before the frame is finalized.
1920 if (ST.getFrameLowering()->hasFP(MF)) {
1921 MachineRegisterInfo &MRI = MF.getRegInfo();
1922
1923 // Try to use s32 as the SP, but move it if it would interfere with input
1924 // arguments. This won't work with calls though.
1925 //
1926 // FIXME: Move SP to avoid any possible inputs, or find a way to spill input
1927 // registers.
1928 if (!MRI.isLiveIn(AMDGPU::SGPR32)) {
1929 Info.setStackPtrOffsetReg(AMDGPU::SGPR32);
1930 } else {
1931 assert(AMDGPU::isShader(MF.getFunction().getCallingConv()))((AMDGPU::isShader(MF.getFunction().getCallingConv())) ? static_cast
<void> (0) : __assert_fail ("AMDGPU::isShader(MF.getFunction().getCallingConv())"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1931, __PRETTY_FUNCTION__))
;
1932
1933 if (MFI.hasCalls())
1934 report_fatal_error("call in graphics shader with too many input SGPRs");
1935
1936 for (unsigned Reg : AMDGPU::SGPR_32RegClass) {
1937 if (!MRI.isLiveIn(Reg)) {
1938 Info.setStackPtrOffsetReg(Reg);
1939 break;
1940 }
1941 }
1942
1943 if (Info.getStackPtrOffsetReg() == AMDGPU::SP_REG)
1944 report_fatal_error("failed to find register for SP");
1945 }
1946
1947 if (MFI.hasCalls()) {
1948 Info.setScratchWaveOffsetReg(AMDGPU::SGPR33);
1949 Info.setFrameOffsetReg(AMDGPU::SGPR33);
1950 } else {
1951 unsigned ReservedOffsetReg =
1952 TRI.reservedPrivateSegmentWaveByteOffsetReg(MF);
1953 Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1954 Info.setFrameOffsetReg(ReservedOffsetReg);
1955 }
1956 } else if (RequiresStackAccess) {
1957 assert(!MFI.hasCalls())((!MFI.hasCalls()) ? static_cast<void> (0) : __assert_fail
("!MFI.hasCalls()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1957, __PRETTY_FUNCTION__))
;
1958 // We know there are accesses and they will be done relative to SP, so just
1959 // pin it to the input.
1960 //
1961 // FIXME: Should not do this if inline asm is reading/writing these
1962 // registers.
1963 Register PreloadedSP = Info.getPreloadedReg(
1964 AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
1965
1966 Info.setStackPtrOffsetReg(PreloadedSP);
1967 Info.setScratchWaveOffsetReg(PreloadedSP);
1968 Info.setFrameOffsetReg(PreloadedSP);
1969 } else {
1970 assert(!MFI.hasCalls())((!MFI.hasCalls()) ? static_cast<void> (0) : __assert_fail
("!MFI.hasCalls()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1970, __PRETTY_FUNCTION__))
;
1971
1972 // There may not be stack access at all. There may still be spills, or
1973 // access of a constant pointer (in which cases an extra copy will be
1974 // emitted in the prolog).
1975 unsigned ReservedOffsetReg
1976 = TRI.reservedPrivateSegmentWaveByteOffsetReg(MF);
1977 Info.setStackPtrOffsetReg(ReservedOffsetReg);
1978 Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1979 Info.setFrameOffsetReg(ReservedOffsetReg);
1980 }
1981}
1982
1983bool SITargetLowering::supportSplitCSR(MachineFunction *MF) const {
1984 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
1985 return !Info->isEntryFunction();
1986}
1987
1988void SITargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
1989
1990}
1991
1992void SITargetLowering::insertCopiesSplitCSR(
1993 MachineBasicBlock *Entry,
1994 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
1995 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
1996
1997 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
1998 if (!IStart)
1999 return;
2000
2001 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2002 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
2003 MachineBasicBlock::iterator MBBI = Entry->begin();
2004 for (const MCPhysReg *I = IStart; *I; ++I) {
2005 const TargetRegisterClass *RC = nullptr;
2006 if (AMDGPU::SReg_64RegClass.contains(*I))
2007 RC = &AMDGPU::SGPR_64RegClass;
2008 else if (AMDGPU::SReg_32RegClass.contains(*I))
2009 RC = &AMDGPU::SGPR_32RegClass;
2010 else
2011 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2011)
;
2012
2013 Register NewVR = MRI->createVirtualRegister(RC);
2014 // Create copy from CSR to a virtual register.
2015 Entry->addLiveIn(*I);
2016 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
2017 .addReg(*I);
2018
2019 // Insert the copy-back instructions right before the terminator.
2020 for (auto *Exit : Exits)
2021 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
2022 TII->get(TargetOpcode::COPY), *I)
2023 .addReg(NewVR);
2024 }
2025}
2026
2027SDValue SITargetLowering::LowerFormalArguments(
2028 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2029 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2030 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2031 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2032
2033 MachineFunction &MF = DAG.getMachineFunction();
2034 const Function &Fn = MF.getFunction();
2035 FunctionType *FType = MF.getFunction().getFunctionType();
2036 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2037
2038 if (Subtarget->isAmdHsaOS() && AMDGPU::isShader(CallConv)) {
2039 DiagnosticInfoUnsupported NoGraphicsHSA(
2040 Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
2041 DAG.getContext()->diagnose(NoGraphicsHSA);
2042 return DAG.getEntryNode();
2043 }
2044
2045 SmallVector<ISD::InputArg, 16> Splits;
2046 SmallVector<CCValAssign, 16> ArgLocs;
2047 BitVector Skipped(Ins.size());
2048 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2049 *DAG.getContext());
2050
2051 bool IsShader = AMDGPU::isShader(CallConv);
2052 bool IsKernel = AMDGPU::isKernel(CallConv);
2053 bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CallConv);
2054
2055 if (IsShader) {
2056 processShaderInputArgs(Splits, CallConv, Ins, Skipped, FType, Info);
2057
2058 // At least one interpolation mode must be enabled or else the GPU will
2059 // hang.
2060 //
2061 // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
2062 // set PSInputAddr, the user wants to enable some bits after the compilation
2063 // based on run-time states. Since we can't know what the final PSInputEna
2064 // will look like, so we shouldn't do anything here and the user should take
2065 // responsibility for the correct programming.
2066 //
2067 // Otherwise, the following restrictions apply:
2068 // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
2069 // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
2070 // enabled too.
2071 if (CallConv == CallingConv::AMDGPU_PS) {
2072 if ((Info->getPSInputAddr() & 0x7F) == 0 ||
2073 ((Info->getPSInputAddr() & 0xF) == 0 &&
2074 Info->isPSInputAllocated(11))) {
2075 CCInfo.AllocateReg(AMDGPU::VGPR0);
2076 CCInfo.AllocateReg(AMDGPU::VGPR1);
2077 Info->markPSInputAllocated(0);
2078 Info->markPSInputEnabled(0);
2079 }
2080 if (Subtarget->isAmdPalOS()) {
2081 // For isAmdPalOS, the user does not enable some bits after compilation
2082 // based on run-time states; the register values being generated here are
2083 // the final ones set in hardware. Therefore we need to apply the
2084 // workaround to PSInputAddr and PSInputEnable together. (The case where
2085 // a bit is set in PSInputAddr but not PSInputEnable is where the
2086 // frontend set up an input arg for a particular interpolation mode, but
2087 // nothing uses that input arg. Really we should have an earlier pass
2088 // that removes such an arg.)
2089 unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
2090 if ((PsInputBits & 0x7F) == 0 ||
2091 ((PsInputBits & 0xF) == 0 &&
2092 (PsInputBits >> 11 & 1)))
2093 Info->markPSInputEnabled(
2094 countTrailingZeros(Info->getPSInputAddr(), ZB_Undefined));
2095 }
2096 }
2097
2098 assert(!Info->hasDispatchPtr() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2103, __PRETTY_FUNCTION__))
2099 !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2103, __PRETTY_FUNCTION__))
2100 !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2103, __PRETTY_FUNCTION__))
2101 !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2103, __PRETTY_FUNCTION__))
2102 !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2103, __PRETTY_FUNCTION__))
2103 !Info->hasWorkItemIDZ())((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2103, __PRETTY_FUNCTION__))
;
2104 } else if (IsKernel) {
2105 assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX())((Info->hasWorkGroupIDX() && Info->hasWorkItemIDX
()) ? static_cast<void> (0) : __assert_fail ("Info->hasWorkGroupIDX() && Info->hasWorkItemIDX()"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2105, __PRETTY_FUNCTION__))
;
2106 } else {
2107 Splits.append(Ins.begin(), Ins.end());
2108 }
2109
2110 if (IsEntryFunc) {
2111 allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
2112 allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
2113 }
2114
2115 if (IsKernel) {
2116 analyzeFormalArgumentsCompute(CCInfo, Ins);
2117 } else {
2118 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg);
2119 CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
2120 }
2121
2122 SmallVector<SDValue, 16> Chains;
2123
2124 // FIXME: This is the minimum kernel argument alignment. We should improve
2125 // this to the maximum alignment of the arguments.
2126 //
2127 // FIXME: Alignment of explicit arguments totally broken with non-0 explicit
2128 // kern arg offset.
2129 const unsigned KernelArgBaseAlign = 16;
2130
2131 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
2132 const ISD::InputArg &Arg = Ins[i];
2133 if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
2134 InVals.push_back(DAG.getUNDEF(Arg.VT));
2135 continue;
2136 }
2137
2138 CCValAssign &VA = ArgLocs[ArgIdx++];
2139 MVT VT = VA.getLocVT();
2140
2141 if (IsEntryFunc && VA.isMemLoc()) {
2142 VT = Ins[i].VT;
2143 EVT MemVT = VA.getLocVT();
2144
2145 const uint64_t Offset = VA.getLocMemOffset();
2146 unsigned Align = MinAlign(KernelArgBaseAlign, Offset);
2147
2148 SDValue Arg = lowerKernargMemParameter(
2149 DAG, VT, MemVT, DL, Chain, Offset, Align, Ins[i].Flags.isSExt(), &Ins[i]);
2150 Chains.push_back(Arg.getValue(1));
2151
2152 auto *ParamTy =
2153 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
2154 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
2155 ParamTy && (ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
2156 ParamTy->getAddressSpace() == AMDGPUAS::REGION_ADDRESS)) {
2157 // On SI local pointers are just offsets into LDS, so they are always
2158 // less than 16-bits. On CI and newer they could potentially be
2159 // real pointers, so we can't guarantee their size.
2160 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
2161 DAG.getValueType(MVT::i16));
2162 }
2163
2164 InVals.push_back(Arg);
2165 continue;
2166 } else if (!IsEntryFunc && VA.isMemLoc()) {
2167 SDValue Val = lowerStackParameter(DAG, VA, DL, Chain, Arg);
2168 InVals.push_back(Val);
2169 if (!Arg.Flags.isByVal())
2170 Chains.push_back(Val.getValue(1));
2171 continue;
2172 }
2173
2174 assert(VA.isRegLoc() && "Parameter must be in a register!")((VA.isRegLoc() && "Parameter must be in a register!"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Parameter must be in a register!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2174, __PRETTY_FUNCTION__))
;
2175
2176 Register Reg = VA.getLocReg();
2177 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2178 EVT ValVT = VA.getValVT();
2179
2180 Reg = MF.addLiveIn(Reg, RC);
2181 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
2182
2183 if (Arg.Flags.isSRet()) {
2184 // The return object should be reasonably addressable.
2185
2186 // FIXME: This helps when the return is a real sret. If it is a
2187 // automatically inserted sret (i.e. CanLowerReturn returns false), an
2188 // extra copy is inserted in SelectionDAGBuilder which obscures this.
2189 unsigned NumBits
2190 = 32 - getSubtarget()->getKnownHighZeroBitsForFrameIndex();
2191 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2192 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), NumBits)));
2193 }
2194
2195 // If this is an 8 or 16-bit value, it is really passed promoted
2196 // to 32 bits. Insert an assert[sz]ext to capture this, then
2197 // truncate to the right size.
2198 switch (VA.getLocInfo()) {
2199 case CCValAssign::Full:
2200 break;
2201 case CCValAssign::BCvt:
2202 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2203 break;
2204 case CCValAssign::SExt:
2205 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val,
2206 DAG.getValueType(ValVT));
2207 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2208 break;
2209 case CCValAssign::ZExt:
2210 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2211 DAG.getValueType(ValVT));
2212 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2213 break;
2214 case CCValAssign::AExt:
2215 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2216 break;
2217 default:
2218 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2218)
;
2219 }
2220
2221 InVals.push_back(Val);
2222 }
2223
2224 if (!IsEntryFunc) {
2225 // Special inputs come after user arguments.
2226 allocateSpecialInputVGPRs(CCInfo, MF, *TRI, *Info);
2227 }
2228
2229 // Start adding system SGPRs.
2230 if (IsEntryFunc) {
2231 allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsShader);
2232 } else {
2233 CCInfo.AllocateReg(Info->getScratchRSrcReg());
2234 CCInfo.AllocateReg(Info->getScratchWaveOffsetReg());
2235 CCInfo.AllocateReg(Info->getFrameOffsetReg());
2236 allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
2237 }
2238
2239 auto &ArgUsageInfo =
2240 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2241 ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
2242
2243 unsigned StackArgSize = CCInfo.getNextStackOffset();
2244 Info->setBytesInStackArgArea(StackArgSize);
2245
2246 return Chains.empty() ? Chain :
2247 DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
2248}
2249
2250// TODO: If return values can't fit in registers, we should return as many as
2251// possible in registers before passing on stack.
2252bool SITargetLowering::CanLowerReturn(
2253 CallingConv::ID CallConv,
2254 MachineFunction &MF, bool IsVarArg,
2255 const SmallVectorImpl<ISD::OutputArg> &Outs,
2256 LLVMContext &Context) const {
2257 // Replacing returns with sret/stack usage doesn't make sense for shaders.
2258 // FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
2259 // for shaders. Vector types should be explicitly handled by CC.
2260 if (AMDGPU::isEntryFunctionCC(CallConv))
2261 return true;
2262
2263 SmallVector<CCValAssign, 16> RVLocs;
2264 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2265 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
2266}
2267
2268SDValue
2269SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2270 bool isVarArg,
2271 const SmallVectorImpl<ISD::OutputArg> &Outs,
2272 const SmallVectorImpl<SDValue> &OutVals,
2273 const SDLoc &DL, SelectionDAG &DAG) const {
2274 MachineFunction &MF = DAG.getMachineFunction();
2275 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2276
2277 if (AMDGPU::isKernel(CallConv)) {
2278 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
2279 OutVals, DL, DAG);
2280 }
2281
2282 bool IsShader = AMDGPU::isShader(CallConv);
2283
2284 Info->setIfReturnsVoid(Outs.empty());
2285 bool IsWaveEnd = Info->returnsVoid() && IsShader;
2286
2287 // CCValAssign - represent the assignment of the return value to a location.
2288 SmallVector<CCValAssign, 48> RVLocs;
2289 SmallVector<ISD::OutputArg, 48> Splits;
2290
2291 // CCState - Info about the registers and stack slots.
2292 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2293 *DAG.getContext());
2294
2295 // Analyze outgoing return values.
2296 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2297
2298 SDValue Flag;
2299 SmallVector<SDValue, 48> RetOps;
2300 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2301
2302 // Add return address for callable functions.
2303 if (!Info->isEntryFunction()) {
2304 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2305 SDValue ReturnAddrReg = CreateLiveInRegister(
2306 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2307
2308 SDValue ReturnAddrVirtualReg = DAG.getRegister(
2309 MF.getRegInfo().createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass),
2310 MVT::i64);
2311 Chain =
2312 DAG.getCopyToReg(Chain, DL, ReturnAddrVirtualReg, ReturnAddrReg, Flag);
2313 Flag = Chain.getValue(1);
2314 RetOps.push_back(ReturnAddrVirtualReg);
2315 }
2316
2317 // Copy the result values into the output registers.
2318 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E;
2319 ++I, ++RealRVLocIdx) {
2320 CCValAssign &VA = RVLocs[I];
2321 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2321, __PRETTY_FUNCTION__))
;
2322 // TODO: Partially return in registers if return values don't fit.
2323 SDValue Arg = OutVals[RealRVLocIdx];
2324
2325 // Copied from other backends.
2326 switch (VA.getLocInfo()) {
2327 case CCValAssign::Full:
2328 break;
2329 case CCValAssign::BCvt:
2330 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2331 break;
2332 case CCValAssign::SExt:
2333 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2334 break;
2335 case CCValAssign::ZExt:
2336 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2337 break;
2338 case CCValAssign::AExt:
2339 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2340 break;
2341 default:
2342 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2342)
;
2343 }
2344
2345 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2346 Flag = Chain.getValue(1);
2347 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2348 }
2349
2350 // FIXME: Does sret work properly?
2351 if (!Info->isEntryFunction()) {
2352 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2353 const MCPhysReg *I =
2354 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2355 if (I) {
2356 for (; *I; ++I) {
2357 if (AMDGPU::SReg_64RegClass.contains(*I))
2358 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2359 else if (AMDGPU::SReg_32RegClass.contains(*I))
2360 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2361 else
2362 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2362)
;
2363 }
2364 }
2365 }
2366
2367 // Update chain and glue.
2368 RetOps[0] = Chain;
2369 if (Flag.getNode())
2370 RetOps.push_back(Flag);
2371
2372 unsigned Opc = AMDGPUISD::ENDPGM;
2373 if (!IsWaveEnd)
2374 Opc = IsShader ? AMDGPUISD::RETURN_TO_EPILOG : AMDGPUISD::RET_FLAG;
2375 return DAG.getNode(Opc, DL, MVT::Other, RetOps);
2376}
2377
2378SDValue SITargetLowering::LowerCallResult(
2379 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2380 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2381 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool IsThisReturn,
2382 SDValue ThisVal) const {
2383 CCAssignFn *RetCC = CCAssignFnForReturn(CallConv, IsVarArg);
2384
2385 // Assign locations to each value returned by this call.
2386 SmallVector<CCValAssign, 16> RVLocs;
2387 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2388 *DAG.getContext());
2389 CCInfo.AnalyzeCallResult(Ins, RetCC);
2390
2391 // Copy all of the result registers out of their specified physreg.
2392 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2393 CCValAssign VA = RVLocs[i];
2394 SDValue Val;
2395
2396 if (VA.isRegLoc()) {
2397 Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2398 Chain = Val.getValue(1);
2399 InFlag = Val.getValue(2);
2400 } else if (VA.isMemLoc()) {
2401 report_fatal_error("TODO: return values in memory");
2402 } else
2403 llvm_unreachable("unknown argument location type")::llvm::llvm_unreachable_internal("unknown argument location type"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2403)
;
2404
2405 switch (VA.getLocInfo()) {
2406 case CCValAssign::Full:
2407 break;
2408 case CCValAssign::BCvt:
2409 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2410 break;
2411 case CCValAssign::ZExt:
2412 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2413 DAG.getValueType(VA.getValVT()));
2414 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2415 break;
2416 case CCValAssign::SExt:
2417 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2418 DAG.getValueType(VA.getValVT()));
2419 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2420 break;
2421 case CCValAssign::AExt:
2422 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2423 break;
2424 default:
2425 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2425)
;
2426 }
2427
2428 InVals.push_back(Val);
2429 }
2430
2431 return Chain;
2432}
2433
2434// Add code to pass special inputs required depending on used features separate
2435// from the explicit user arguments present in the IR.
2436void SITargetLowering::passSpecialInputs(
2437 CallLoweringInfo &CLI,
2438 CCState &CCInfo,
2439 const SIMachineFunctionInfo &Info,
2440 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
2441 SmallVectorImpl<SDValue> &MemOpChains,
2442 SDValue Chain) const {
2443 // If we don't have a call site, this was a call inserted by
2444 // legalization. These can never use special inputs.
2445 if (!CLI.CS)
2446 return;
2447
2448 const Function *CalleeFunc = CLI.CS.getCalledFunction();
2449 assert(CalleeFunc)((CalleeFunc) ? static_cast<void> (0) : __assert_fail (
"CalleeFunc", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2449, __PRETTY_FUNCTION__))
;
2450
2451 SelectionDAG &DAG = CLI.DAG;
2452 const SDLoc &DL = CLI.DL;
2453
2454 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2455
2456 auto &ArgUsageInfo =
2457 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2458 const AMDGPUFunctionArgInfo &CalleeArgInfo
2459 = ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
2460
2461 const AMDGPUFunctionArgInfo &CallerArgInfo = Info.getArgInfo();
2462
2463 // TODO: Unify with private memory register handling. This is complicated by
2464 // the fact that at least in kernels, the input argument is not necessarily
2465 // in the same location as the input.
2466 AMDGPUFunctionArgInfo::PreloadedValue InputRegs[] = {
2467 AMDGPUFunctionArgInfo::DISPATCH_PTR,
2468 AMDGPUFunctionArgInfo::QUEUE_PTR,
2469 AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR,
2470 AMDGPUFunctionArgInfo::DISPATCH_ID,
2471 AMDGPUFunctionArgInfo::WORKGROUP_ID_X,
2472 AMDGPUFunctionArgInfo::WORKGROUP_ID_Y,
2473 AMDGPUFunctionArgInfo::WORKGROUP_ID_Z,
2474 AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR
2475 };
2476
2477 for (auto InputID : InputRegs) {
2478 const ArgDescriptor *OutgoingArg;
2479 const TargetRegisterClass *ArgRC;
2480
2481 std::tie(OutgoingArg, ArgRC) = CalleeArgInfo.getPreloadedValue(InputID);
2482 if (!OutgoingArg)
2483 continue;
2484
2485 const ArgDescriptor *IncomingArg;
2486 const TargetRegisterClass *IncomingArgRC;
2487 std::tie(IncomingArg, IncomingArgRC)
2488 = CallerArgInfo.getPreloadedValue(InputID);
2489 assert(IncomingArgRC == ArgRC)((IncomingArgRC == ArgRC) ? static_cast<void> (0) : __assert_fail
("IncomingArgRC == ArgRC", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2489, __PRETTY_FUNCTION__))
;
2490
2491 // All special arguments are ints for now.
2492 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;
2493 SDValue InputReg;
2494
2495 if (IncomingArg) {
2496 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg);
2497 } else {
2498 // The implicit arg ptr is special because it doesn't have a corresponding
2499 // input for kernels, and is computed from the kernarg segment pointer.
2500 assert(InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR)((InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR) ? static_cast
<void> (0) : __assert_fail ("InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2500, __PRETTY_FUNCTION__))
;
2501 InputReg = getImplicitArgPtr(DAG, DL);
2502 }
2503
2504 if (OutgoingArg->isRegister()) {
2505 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2506 } else {
2507 unsigned SpecialArgOffset = CCInfo.AllocateStack(ArgVT.getStoreSize(), 4);
2508 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2509 SpecialArgOffset);
2510 MemOpChains.push_back(ArgStore);
2511 }
2512 }
2513
2514 // Pack workitem IDs into a single register or pass it as is if already
2515 // packed.
2516 const ArgDescriptor *OutgoingArg;
2517 const TargetRegisterClass *ArgRC;
2518
2519 std::tie(OutgoingArg, ArgRC) =
2520 CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
2521 if (!OutgoingArg)
2522 std::tie(OutgoingArg, ArgRC) =
2523 CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
2524 if (!OutgoingArg)
2525 std::tie(OutgoingArg, ArgRC) =
2526 CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
2527 if (!OutgoingArg)
2528 return;
2529
2530 const ArgDescriptor *IncomingArgX
2531 = CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X).first;
2532 const ArgDescriptor *IncomingArgY
2533 = CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y).first;
2534 const ArgDescriptor *IncomingArgZ
2535 = CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z).first;
2536
2537 SDValue InputReg;
2538 SDLoc SL;
2539
2540 // If incoming ids are not packed we need to pack them.
2541 if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo.WorkItemIDX)
2542 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX);
2543
2544 if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo.WorkItemIDY) {
2545 SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY);
2546 Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y,
2547 DAG.getShiftAmountConstant(10, MVT::i32, SL));
2548 InputReg = InputReg.getNode() ?
2549 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y;
2550 }
2551
2552 if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo.WorkItemIDZ) {
2553 SDValue Z = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgZ);
2554 Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z,
2555 DAG.getShiftAmountConstant(20, MVT::i32, SL));
2556 InputReg = InputReg.getNode() ?
2557 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Z) : Z;
2558 }
2559
2560 if (!InputReg.getNode()) {
2561 // Workitem ids are already packed, any of present incoming arguments
2562 // will carry all required fields.
2563 ArgDescriptor IncomingArg = ArgDescriptor::createArg(
2564 IncomingArgX ? *IncomingArgX :
2565 IncomingArgY ? *IncomingArgY :
2566 *IncomingArgZ, ~0u);
2567 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, IncomingArg);
2568 }
2569
2570 if (OutgoingArg->isRegister()) {
2571 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2572 } else {
2573 unsigned SpecialArgOffset = CCInfo.AllocateStack(4, 4);
2574 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2575 SpecialArgOffset);
2576 MemOpChains.push_back(ArgStore);
2577 }
2578}
2579
2580static bool canGuaranteeTCO(CallingConv::ID CC) {
2581 return CC == CallingConv::Fast;
2582}
2583
2584/// Return true if we might ever do TCO for calls with this calling convention.
2585static bool mayTailCallThisCC(CallingConv::ID CC) {
2586 switch (CC) {
2587 case CallingConv::C:
2588 return true;
2589 default:
2590 return canGuaranteeTCO(CC);
2591 }
2592}
2593
2594bool SITargetLowering::isEligibleForTailCallOptimization(
2595 SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
2596 const SmallVectorImpl<ISD::OutputArg> &Outs,
2597 const SmallVectorImpl<SDValue> &OutVals,
2598 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2599 if (!mayTailCallThisCC(CalleeCC))
2600 return false;
2601
2602 MachineFunction &MF = DAG.getMachineFunction();
2603 const Function &CallerF = MF.getFunction();
2604 CallingConv::ID CallerCC = CallerF.getCallingConv();
2605 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2606 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2607
2608 // Kernels aren't callable, and don't have a live in return address so it
2609 // doesn't make sense to do a tail call with entry functions.
2610 if (!CallerPreserved)
2611 return false;
2612
2613 bool CCMatch = CallerCC == CalleeCC;
2614
2615 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
2616 if (canGuaranteeTCO(CalleeCC) && CCMatch)
2617 return true;
2618 return false;
2619 }
2620
2621 // TODO: Can we handle var args?
2622 if (IsVarArg)
2623 return false;
2624
2625 for (const Argument &Arg : CallerF.args()) {
2626 if (Arg.hasByValAttr())
2627 return false;
2628 }
2629
2630 LLVMContext &Ctx = *DAG.getContext();
2631
2632 // Check that the call results are passed in the same way.
2633 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, Ctx, Ins,
2634 CCAssignFnForCall(CalleeCC, IsVarArg),
2635 CCAssignFnForCall(CallerCC, IsVarArg)))
2636 return false;
2637
2638 // The callee has to preserve all registers the caller needs to preserve.
2639 if (!CCMatch) {
2640 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2641 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2642 return false;
2643 }
2644
2645 // Nothing more to check if the callee is taking no arguments.
2646 if (Outs.empty())
2647 return true;
2648
2649 SmallVector<CCValAssign, 16> ArgLocs;
2650 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
2651
2652 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
2653
2654 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
2655 // If the stack arguments for this call do not fit into our own save area then
2656 // the call cannot be made tail.
2657 // TODO: Is this really necessary?
2658 if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
2659 return false;
2660
2661 const MachineRegisterInfo &MRI = MF.getRegInfo();
2662 return parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals);
2663}
2664
2665bool SITargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2666 if (!CI->isTailCall())
2667 return false;
2668
2669 const Function *ParentFn = CI->getParent()->getParent();
2670 if (AMDGPU::isEntryFunctionCC(ParentFn->getCallingConv()))
2671 return false;
2672 return true;
2673}
2674
2675// The wave scratch offset register is used as the global base pointer.
2676SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
2677 SmallVectorImpl<SDValue> &InVals) const {
2678 SelectionDAG &DAG = CLI.DAG;
2679 const SDLoc &DL = CLI.DL;
2680 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2681 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2682 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2683 SDValue Chain = CLI.Chain;
2684 SDValue Callee = CLI.Callee;
2685 bool &IsTailCall = CLI.IsTailCall;
2686 CallingConv::ID CallConv = CLI.CallConv;
2687 bool IsVarArg = CLI.IsVarArg;
2688 bool IsSibCall = false;
2689 bool IsThisReturn = false;
2690 MachineFunction &MF = DAG.getMachineFunction();
2691
2692 if (Callee.isUndef() || isNullConstant(Callee)) {
2693 if (!CLI.IsTailCall) {
2694 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
2695 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
2696 }
2697
2698 return Chain;
2699 }
2700
2701 if (IsVarArg) {
2702 return lowerUnhandledCall(CLI, InVals,
2703 "unsupported call to variadic function ");
2704 }
2705
2706 if (!CLI.CS.getInstruction())
2707 report_fatal_error("unsupported libcall legalization");
2708
2709 if (!CLI.CS.getCalledFunction()) {
2710 return lowerUnhandledCall(CLI, InVals,
2711 "unsupported indirect call to function ");
2712 }
2713
2714 if (IsTailCall && MF.getTarget().Options.GuaranteedTailCallOpt) {
2715 return lowerUnhandledCall(CLI, InVals,
2716 "unsupported required tail call to function ");
2717 }
2718
2719 if (AMDGPU::isShader(MF.getFunction().getCallingConv())) {
2720 // Note the issue is with the CC of the calling function, not of the call
2721 // itself.
2722 return lowerUnhandledCall(CLI, InVals,
2723 "unsupported call from graphics shader of function ");
2724 }
2725
2726 if (IsTailCall) {
2727 IsTailCall = isEligibleForTailCallOptimization(
2728 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
2729 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) {
2730 report_fatal_error("failed to perform tail call elimination on a call "
2731 "site marked musttail");
2732 }
2733
2734 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2735
2736 // A sibling call is one where we're under the usual C ABI and not planning
2737 // to change that but can still do a tail call:
2738 if (!TailCallOpt && IsTailCall)
2739 IsSibCall = true;
2740
2741 if (IsTailCall)
2742 ++NumTailCalls;
2743 }
2744
2745 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2746
2747 // Analyze operands of the call, assigning locations to each operand.
2748 SmallVector<CCValAssign, 16> ArgLocs;
2749 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
2750 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, IsVarArg);
2751
2752 CCInfo.AnalyzeCallOperands(Outs, AssignFn);
2753
2754 // Get a count of how many bytes are to be pushed on the stack.
2755 unsigned NumBytes = CCInfo.getNextStackOffset();
2756
2757 if (IsSibCall) {
2758 // Since we're not changing the ABI to make this a tail call, the memory
2759 // operands are already available in the caller's incoming argument space.
2760 NumBytes = 0;
2761 }
2762
2763 // FPDiff is the byte offset of the call's argument area from the callee's.
2764 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2765 // by this amount for a tail call. In a sibling call it must be 0 because the
2766 // caller will deallocate the entire stack and the callee still expects its
2767 // arguments to begin at SP+0. Completely unused for non-tail calls.
2768 int32_t FPDiff = 0;
2769 MachineFrameInfo &MFI = MF.getFrameInfo();
2770 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2771
2772 // Adjust the stack pointer for the new arguments...
2773 // These operations are automatically eliminated by the prolog/epilog pass
2774 if (!IsSibCall) {
2775 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
2776
2777 SmallVector<SDValue, 4> CopyFromChains;
2778
2779 // In the HSA case, this should be an identity copy.
2780 SDValue ScratchRSrcReg
2781 = DAG.getCopyFromReg(Chain, DL, Info->getScratchRSrcReg(), MVT::v4i32);
2782 RegsToPass.emplace_back(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
2783 CopyFromChains.push_back(ScratchRSrcReg.getValue(1));
2784 Chain = DAG.getTokenFactor(DL, CopyFromChains);
2785 }
2786
2787 SmallVector<SDValue, 8> MemOpChains;
2788 MVT PtrVT = MVT::i32;
2789
2790 // Walk the register/memloc assignments, inserting copies/loads.
2791 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2792 CCValAssign &VA = ArgLocs[i];
2793 SDValue Arg = OutVals[i];
2794
2795 // Promote the value if needed.
2796 switch (VA.getLocInfo()) {
2797 case CCValAssign::Full:
2798 break;
2799 case CCValAssign::BCvt:
2800 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2801 break;
2802 case CCValAssign::ZExt:
2803 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2804 break;
2805 case CCValAssign::SExt:
2806 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2807 break;
2808 case CCValAssign::AExt:
2809 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2810 break;
2811 case CCValAssign::FPExt:
2812 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2813 break;
2814 default:
2815 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2815)
;
2816 }
2817
2818 if (VA.isRegLoc()) {
2819 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2820 } else {
2821 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2821, __PRETTY_FUNCTION__))
;
2822
2823 SDValue DstAddr;
2824 MachinePointerInfo DstInfo;
2825
2826 unsigned LocMemOffset = VA.getLocMemOffset();
2827 int32_t Offset = LocMemOffset;
2828
2829 SDValue PtrOff = DAG.getConstant(Offset, DL, PtrVT);
2830 MaybeAlign Alignment;
2831
2832 if (IsTailCall) {
2833 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2834 unsigned OpSize = Flags.isByVal() ?
2835 Flags.getByValSize() : VA.getValVT().getStoreSize();
2836
2837 // FIXME: We can have better than the minimum byval required alignment.
2838 Alignment =
2839 Flags.isByVal()
2840 ? MaybeAlign(Flags.getByValAlign())
2841 : commonAlignment(Subtarget->getStackAlignment(), Offset);
2842
2843 Offset = Offset + FPDiff;
2844 int FI = MFI.CreateFixedObject(OpSize, Offset, true);
2845
2846 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2847 DstInfo = MachinePointerInfo::getFixedStack(MF, FI);
2848
2849 // Make sure any stack arguments overlapping with where we're storing
2850 // are loaded before this eventual operation. Otherwise they'll be
2851 // clobbered.
2852
2853 // FIXME: Why is this really necessary? This seems to just result in a
2854 // lot of code to copy the stack and write them back to the same
2855 // locations, which are supposed to be immutable?
2856 Chain = addTokenForArgument(Chain, DAG, MFI, FI);
2857 } else {
2858 DstAddr = PtrOff;
2859 DstInfo = MachinePointerInfo::getStack(MF, LocMemOffset);
2860 Alignment =
2861 commonAlignment(Subtarget->getStackAlignment(), LocMemOffset);
2862 }
2863
2864 if (Outs[i].Flags.isByVal()) {
2865 SDValue SizeNode =
2866 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32);
2867 SDValue Cpy = DAG.getMemcpy(
2868 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2869 /*isVol = */ false, /*AlwaysInline = */ true,
2870 /*isTailCall = */ false, DstInfo,
2871 MachinePointerInfo(AMDGPUAS::PRIVATE_ADDRESS));
2872
2873 MemOpChains.push_back(Cpy);
2874 } else {
2875 SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo,
2876 Alignment ? Alignment->value() : 0);
2877 MemOpChains.push_back(Store);
2878 }
2879 }
2880 }
2881
2882 // Copy special input registers after user input arguments.
2883 passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
2884
2885 if (!MemOpChains.empty())
2886 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2887
2888 // Build a sequence of copy-to-reg nodes chained together with token chain
2889 // and flag operands which copy the outgoing args into the appropriate regs.
2890 SDValue InFlag;
2891 for (auto &RegToPass : RegsToPass) {
2892 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
2893 RegToPass.second, InFlag);
2894 InFlag = Chain.getValue(1);
2895 }
2896
2897
2898 SDValue PhysReturnAddrReg;
2899 if (IsTailCall) {
2900 // Since the return is being combined with the call, we need to pass on the
2901 // return address.
2902
2903 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2904 SDValue ReturnAddrReg = CreateLiveInRegister(
2905 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2906
2907 PhysReturnAddrReg = DAG.getRegister(TRI->getReturnAddressReg(MF),
2908 MVT::i64);
2909 Chain = DAG.getCopyToReg(Chain, DL, PhysReturnAddrReg, ReturnAddrReg, InFlag);
2910 InFlag = Chain.getValue(1);
2911 }
2912
2913 // We don't usually want to end the call-sequence here because we would tidy
2914 // the frame up *after* the call, however in the ABI-changing tail-call case
2915 // we've carefully laid out the parameters so that when sp is reset they'll be
2916 // in the correct location.
2917 if (IsTailCall && !IsSibCall) {
2918 Chain = DAG.getCALLSEQ_END(Chain,
2919 DAG.getTargetConstant(NumBytes, DL, MVT::i32),
2920 DAG.getTargetConstant(0, DL, MVT::i32),
2921 InFlag, DL);
2922 InFlag = Chain.getValue(1);
2923 }
2924
2925 std::vector<SDValue> Ops;
2926 Ops.push_back(Chain);
2927 Ops.push_back(Callee);
2928 // Add a redundant copy of the callee global which will not be legalized, as
2929 // we need direct access to the callee later.
2930 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Callee);
2931 const GlobalValue *GV = GSD->getGlobal();
2932 Ops.push_back(DAG.getTargetGlobalAddress(GV, DL, MVT::i64));
2933
2934 if (IsTailCall) {
2935 // Each tail call may have to adjust the stack by a different amount, so
2936 // this information must travel along with the operation for eventual
2937 // consumption by emitEpilogue.
2938 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
2939
2940 Ops.push_back(PhysReturnAddrReg);
2941 }
2942
2943 // Add argument registers to the end of the list so that they are known live
2944 // into the call.
2945 for (auto &RegToPass : RegsToPass) {
2946 Ops.push_back(DAG.getRegister(RegToPass.first,
2947 RegToPass.second.getValueType()));
2948 }
2949
2950 // Add a register mask operand representing the call-preserved registers.
2951
2952 auto *TRI = static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
2953 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
2954 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2954, __PRETTY_FUNCTION__))
;
2955 Ops.push_back(DAG.getRegisterMask(Mask));
2956
2957 if (InFlag.getNode())
2958 Ops.push_back(InFlag);
2959
2960 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2961
2962 // If we're doing a tall call, use a TC_RETURN here rather than an
2963 // actual call instruction.
2964 if (IsTailCall) {
2965 MFI.setHasTailCall();
2966 return DAG.getNode(AMDGPUISD::TC_RETURN, DL, NodeTys, Ops);
2967 }
2968
2969 // Returns a chain and a flag for retval copy to use.
2970 SDValue Call = DAG.getNode(AMDGPUISD::CALL, DL, NodeTys, Ops);
2971 Chain = Call.getValue(0);
2972 InFlag = Call.getValue(1);
2973
2974 uint64_t CalleePopBytes = NumBytes;
2975 Chain = DAG.getCALLSEQ_END(Chain, DAG.getTargetConstant(0, DL, MVT::i32),
2976 DAG.getTargetConstant(CalleePopBytes, DL, MVT::i32),
2977 InFlag, DL);
2978 if (!Ins.empty())
2979 InFlag = Chain.getValue(1);
2980
2981 // Handle result values, copying them out of physregs into vregs that we
2982 // return.
2983 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2984 InVals, IsThisReturn,
2985 IsThisReturn ? OutVals[0] : SDValue());
2986}
2987
2988Register SITargetLowering::getRegisterByName(const char* RegName, LLT VT,
2989 const MachineFunction &MF) const {
2990 Register Reg = StringSwitch<Register>(RegName)
2991 .Case("m0", AMDGPU::M0)
2992 .Case("exec", AMDGPU::EXEC)
2993 .Case("exec_lo", AMDGPU::EXEC_LO)
2994 .Case("exec_hi", AMDGPU::EXEC_HI)
2995 .Case("flat_scratch", AMDGPU::FLAT_SCR)
2996 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
2997 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
2998 .Default(Register());
2999
3000 if (Reg == AMDGPU::NoRegister) {
3001 report_fatal_error(Twine("invalid register name \""
3002 + StringRef(RegName) + "\"."));
3003
3004 }
3005
3006 if (!Subtarget->hasFlatScrRegister() &&
3007 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
3008 report_fatal_error(Twine("invalid register \""
3009 + StringRef(RegName) + "\" for subtarget."));
3010 }
3011
3012 switch (Reg) {
3013 case AMDGPU::M0:
3014 case AMDGPU::EXEC_LO:
3015 case AMDGPU::EXEC_HI:
3016 case AMDGPU::FLAT_SCR_LO:
3017 case AMDGPU::FLAT_SCR_HI:
3018 if (VT.getSizeInBits() == 32)
3019 return Reg;
3020 break;
3021 case AMDGPU::EXEC:
3022 case AMDGPU::FLAT_SCR:
3023 if (VT.getSizeInBits() == 64)
3024 return Reg;
3025 break;
3026 default:
3027 llvm_unreachable("missing register type checking")::llvm::llvm_unreachable_internal("missing register type checking"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3027)
;
3028 }
3029
3030 report_fatal_error(Twine("invalid type for register \""
3031 + StringRef(RegName) + "\"."));
3032}
3033
3034// If kill is not the last instruction, split the block so kill is always a
3035// proper terminator.
3036MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,
3037 MachineBasicBlock *BB) const {
3038 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3039
3040 MachineBasicBlock::iterator SplitPoint(&MI);
3041 ++SplitPoint;
3042
3043 if (SplitPoint == BB->end()) {
3044 // Don't bother with a new block.
3045 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
3046 return BB;
3047 }
3048
3049 MachineFunction *MF = BB->getParent();
3050 MachineBasicBlock *SplitBB
3051 = MF->CreateMachineBasicBlock(BB->getBasicBlock());
3052
3053 MF->insert(++MachineFunction::iterator(BB), SplitBB);
3054 SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
3055
3056 SplitBB->transferSuccessorsAndUpdatePHIs(BB);
3057 BB->addSuccessor(SplitBB);
3058
3059 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
3060 return SplitBB;
3061}
3062
3063// Split block \p MBB at \p MI, as to insert a loop. If \p InstInLoop is true,
3064// \p MI will be the only instruction in the loop body block. Otherwise, it will
3065// be the first instruction in the remainder block.
3066//
3067/// \returns { LoopBody, Remainder }
3068static std::pair<MachineBasicBlock *, MachineBasicBlock *>
3069splitBlockForLoop(MachineInstr &MI, MachineBasicBlock &MBB, bool InstInLoop) {
3070 MachineFunction *MF = MBB.getParent();
3071 MachineBasicBlock::iterator I(&MI);
3072
3073 // To insert the loop we need to split the block. Move everything after this
3074 // point to a new block, and insert a new empty block between the two.
3075 MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
3076 MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
3077 MachineFunction::iterator MBBI(MBB);
3078 ++MBBI;
3079
3080 MF->insert(MBBI, LoopBB);
3081 MF->insert(MBBI, RemainderBB);
3082
3083 LoopBB->addSuccessor(LoopBB);
3084 LoopBB->addSuccessor(RemainderBB);
3085
3086 // Move the rest of the block into a new block.
3087 RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
3088
3089 if (InstInLoop) {
3090 auto Next = std::next(I);
3091
3092 // Move instruction to loop body.
3093 LoopBB->splice(LoopBB->begin(), &MBB, I, Next);
3094
3095 // Move the rest of the block.
3096 RemainderBB->splice(RemainderBB->begin(), &MBB, Next, MBB.end());
3097 } else {
3098 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
3099 }
3100
3101 MBB.addSuccessor(LoopBB);
3102
3103 return std::make_pair(LoopBB, RemainderBB);
3104}
3105
3106/// Insert \p MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
3107void SITargetLowering::bundleInstWithWaitcnt(MachineInstr &MI) const {
3108 MachineBasicBlock *MBB = MI.getParent();
3109 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3110 auto I = MI.getIterator();
3111 auto E = std::next(I);
3112
3113 BuildMI(*MBB, E, MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
3114 .addImm(0);
3115
3116 MIBundleBuilder Bundler(*MBB, I, E);
3117 finalizeBundle(*MBB, Bundler.begin());
3118}
3119
3120MachineBasicBlock *
3121SITargetLowering::emitGWSMemViolTestLoop(MachineInstr &MI,
3122 MachineBasicBlock *BB) const {
3123 const DebugLoc &DL = MI.getDebugLoc();
3124
3125 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3126
3127 MachineBasicBlock *LoopBB;
3128 MachineBasicBlock *RemainderBB;
3129 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3130
3131 // Apparently kill flags are only valid if the def is in the same block?
3132 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0))
3133 Src->setIsKill(false);
3134
3135 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, *BB, true);
3136
3137 MachineBasicBlock::iterator I = LoopBB->end();
3138
3139 const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg(
3140 AMDGPU::Hwreg::ID_TRAPSTS, AMDGPU::Hwreg::OFFSET_MEM_VIOL, 1);
3141
3142 // Clear TRAP_STS.MEM_VIOL
3143 BuildMI(*LoopBB, LoopBB->begin(), DL, TII->get(AMDGPU::S_SETREG_IMM32_B32))
3144 .addImm(0)
3145 .addImm(EncodedReg);
3146
3147 bundleInstWithWaitcnt(MI);
3148
3149 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3150
3151 // Load and check TRAP_STS.MEM_VIOL
3152 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), Reg)
3153 .addImm(EncodedReg);
3154
3155 // FIXME: Do we need to use an isel pseudo that may clobber scc?
3156 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32))
3157 .addReg(Reg, RegState::Kill)
3158 .addImm(0);
3159 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3160 .addMBB(LoopBB);
3161
3162 return RemainderBB;
3163}
3164
3165// Do a v_movrels_b32 or v_movreld_b32 for each unique value of \p IdxReg in the
3166// wavefront. If the value is uniform and just happens to be in a VGPR, this
3167// will only do one iteration. In the worst case, this will loop 64 times.
3168//
3169// TODO: Just use v_readlane_b32 if we know the VGPR has a uniform value.
3170static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(
3171 const SIInstrInfo *TII,
3172 MachineRegisterInfo &MRI,
3173 MachineBasicBlock &OrigBB,
3174 MachineBasicBlock &LoopBB,
3175 const DebugLoc &DL,
3176 const MachineOperand &IdxReg,
3177 unsigned InitReg,
3178 unsigned ResultReg,
3179 unsigned PhiReg,
3180 unsigned InitSaveExecReg,
3181 int Offset,
3182 bool UseGPRIdxMode,
3183 bool IsIndirectSrc) {
3184 MachineFunction *MF = OrigBB.getParent();
3185 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3186 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3187 MachineBasicBlock::iterator I = LoopBB.begin();
3188
3189 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3190 Register PhiExec = MRI.createVirtualRegister(BoolRC);
3191 Register NewExec = MRI.createVirtualRegister(BoolRC);
3192 Register CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3193 Register CondReg = MRI.createVirtualRegister(BoolRC);
3194
3195 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
3196 .addReg(InitReg)
3197 .addMBB(&OrigBB)
3198 .addReg(ResultReg)
3199 .addMBB(&LoopBB);
3200
3201 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
3202 .addReg(InitSaveExecReg)
3203 .addMBB(&OrigBB)
3204 .addReg(NewExec)
3205 .addMBB(&LoopBB);
3206
3207 // Read the next variant <- also loop target.
3208 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
3209 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));
3210
3211 // Compare the just read M0 value to all possible Idx values.
3212 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
3213 .addReg(CurrentIdxReg)
3214 .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
3215
3216 // Update EXEC, save the original EXEC value to VCC.
3217 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
3218 : AMDGPU::S_AND_SAVEEXEC_B64),
3219 NewExec)
3220 .addReg(CondReg, RegState::Kill);
3221
3222 MRI.setSimpleHint(NewExec, CondReg);
3223
3224 if (UseGPRIdxMode) {
3225 unsigned IdxReg;
3226 if (Offset == 0) {
3227 IdxReg = CurrentIdxReg;
3228 } else {
3229 IdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3230 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), IdxReg)
3231 .addReg(CurrentIdxReg, RegState::Kill)
3232 .addImm(Offset);
3233 }
3234 unsigned IdxMode = IsIndirectSrc ?
3235 AMDGPU::VGPRIndexMode::SRC0_ENABLE : AMDGPU::VGPRIndexMode::DST_ENABLE;
3236 MachineInstr *SetOn =
3237 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3238 .addReg(IdxReg, RegState::Kill)
3239 .addImm(IdxMode);
3240 SetOn->getOperand(3).setIsUndef();
3241 } else {
3242 // Move index from VCC into M0
3243 if (Offset == 0) {
3244 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3245 .addReg(CurrentIdxReg, RegState::Kill);
3246 } else {
3247 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3248 .addReg(CurrentIdxReg, RegState::Kill)
3249 .addImm(Offset);
3250 }
3251 }
3252
3253 // Update EXEC, switch all done bits to 0 and all todo bits to 1.
3254 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3255 MachineInstr *InsertPt =
3256 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
3257 : AMDGPU::S_XOR_B64_term), Exec)
3258 .addReg(Exec)
3259 .addReg(NewExec);
3260
3261 // XXX - s_xor_b64 sets scc to 1 if the result is nonzero, so can we use
3262 // s_cbranch_scc0?
3263
3264 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover.
3265 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
3266 .addMBB(&LoopBB);
3267
3268 return InsertPt->getIterator();
3269}
3270
3271// This has slightly sub-optimal regalloc when the source vector is killed by
3272// the read. The register allocator does not understand that the kill is
3273// per-workitem, so is kept alive for the whole loop so we end up not re-using a
3274// subregister from it, using 1 more VGPR than necessary. This was saved when
3275// this was expanded after register allocation.
3276static MachineBasicBlock::iterator loadM0FromVGPR(const SIInstrInfo *TII,
3277 MachineBasicBlock &MBB,
3278 MachineInstr &MI,
3279 unsigned InitResultReg,
3280 unsigned PhiReg,
3281 int Offset,
3282 bool UseGPRIdxMode,
3283 bool IsIndirectSrc) {
3284 MachineFunction *MF = MBB.getParent();
3285 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3286 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3287 MachineRegisterInfo &MRI = MF->getRegInfo();
3288 const DebugLoc &DL = MI.getDebugLoc();
3289 MachineBasicBlock::iterator I(&MI);
3290
3291 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3292 Register DstReg = MI.getOperand(0).getReg();
3293 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
3294 Register TmpExec = MRI.createVirtualRegister(BoolXExecRC);
3295 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3296 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
3297
3298 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
3299
3300 // Save the EXEC mask
3301 BuildMI(MBB, I, DL, TII->get(MovExecOpc), SaveExec)
3302 .addReg(Exec);
3303
3304 MachineBasicBlock *LoopBB;
3305 MachineBasicBlock *RemainderBB;
3306 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, MBB, false);
3307
3308 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3309
3310 auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
3311 InitResultReg, DstReg, PhiReg, TmpExec,
3312 Offset, UseGPRIdxMode, IsIndirectSrc);
3313
3314 MachineBasicBlock::iterator First = RemainderBB->begin();
3315 BuildMI(*RemainderBB, First, DL, TII->get(MovExecOpc), Exec)
3316 .addReg(SaveExec);
3317
3318 return InsPt;
3319}
3320
3321// Returns subreg index, offset
3322static std::pair<unsigned, int>
3323computeIndirectRegAndOffset(const SIRegisterInfo &TRI,
3324 const TargetRegisterClass *SuperRC,
3325 unsigned VecReg,
3326 int Offset) {
3327 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
3328
3329 // Skip out of bounds offsets, or else we would end up using an undefined
3330 // register.
3331 if (Offset >= NumElts || Offset < 0)
3332 return std::make_pair(AMDGPU::sub0, Offset);
3333
3334 return std::make_pair(AMDGPU::sub0 + Offset, 0);
3335}
3336
3337// Return true if the index is an SGPR and was set.
3338static bool setM0ToIndexFromSGPR(const SIInstrInfo *TII,
3339 MachineRegisterInfo &MRI,
3340 MachineInstr &MI,
3341 int Offset,
3342 bool UseGPRIdxMode,
3343 bool IsIndirectSrc) {
3344 MachineBasicBlock *MBB = MI.getParent();
3345 const DebugLoc &DL = MI.getDebugLoc();
3346 MachineBasicBlock::iterator I(&MI);
3347
3348 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3349 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3350
3351 assert(Idx->getReg() != AMDGPU::NoRegister)((Idx->getReg() != AMDGPU::NoRegister) ? static_cast<void
> (0) : __assert_fail ("Idx->getReg() != AMDGPU::NoRegister"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3351, __PRETTY_FUNCTION__))
;
3352
3353 if (!TII->getRegisterInfo().isSGPRClass(IdxRC))
3354 return false;
3355
3356 if (UseGPRIdxMode) {
3357 unsigned IdxMode = IsIndirectSrc ?
3358 AMDGPU::VGPRIndexMode::SRC0_ENABLE : AMDGPU::VGPRIndexMode::DST_ENABLE;
3359 if (Offset == 0) {
3360 MachineInstr *SetOn =
3361 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3362 .add(*Idx)
3363 .addImm(IdxMode);
3364
3365 SetOn->getOperand(3).setIsUndef();
3366 } else {
3367 Register Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3368 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
3369 .add(*Idx)
3370 .addImm(Offset);
3371 MachineInstr *SetOn =
3372 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3373 .addReg(Tmp, RegState::Kill)
3374 .addImm(IdxMode);
3375
3376 SetOn->getOperand(3).setIsUndef();
3377 }
3378
3379 return true;
3380 }
3381
3382 if (Offset == 0) {
3383 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3384 .add(*Idx);
3385 } else {
3386 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3387 .add(*Idx)
3388 .addImm(Offset);
3389 }
3390
3391 return true;
3392}
3393
3394// Control flow needs to be inserted if indexing with a VGPR.
3395static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
3396 MachineBasicBlock &MBB,
3397 const GCNSubtarget &ST) {
3398 const SIInstrInfo *TII = ST.getInstrInfo();
3399 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3400 MachineFunction *MF = MBB.getParent();
3401 MachineRegisterInfo &MRI = MF->getRegInfo();
3402
3403 Register Dst = MI.getOperand(0).getReg();
3404 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
3405 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3406
3407 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3408
3409 unsigned SubReg;
3410 std::tie(SubReg, Offset)
3411 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
3412
3413 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3414
3415 if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, true)) {
3416 MachineBasicBlock::iterator I(&MI);
3417 const DebugLoc &DL = MI.getDebugLoc();
3418
3419 if (UseGPRIdxMode) {
3420 // TODO: Look at the uses to avoid the copy. This may require rescheduling
3421 // to avoid interfering with other uses, so probably requires a new
3422 // optimization pass.
3423 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3424 .addReg(SrcReg, RegState::Undef, SubReg)
3425 .addReg(SrcReg, RegState::Implicit)
3426 .addReg(AMDGPU::M0, RegState::Implicit);
3427 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3428 } else {
3429 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3430 .addReg(SrcReg, RegState::Undef, SubReg)
3431 .addReg(SrcReg, RegState::Implicit);
3432 }
3433
3434 MI.eraseFromParent();
3435
3436 return &MBB;
3437 }
3438
3439 const DebugLoc &DL = MI.getDebugLoc();
3440 MachineBasicBlock::iterator I(&MI);
3441
3442 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3443 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3444
3445 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3446
3447 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg,
3448 Offset, UseGPRIdxMode, true);
3449 MachineBasicBlock *LoopBB = InsPt->getParent();
3450
3451 if (UseGPRIdxMode) {
3452 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3453 .addReg(SrcReg, RegState::Undef, SubReg)
3454 .addReg(SrcReg, RegState::Implicit)
3455 .addReg(AMDGPU::M0, RegState::Implicit);
3456 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3457 } else {
3458 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3459 .addReg(SrcReg, RegState::Undef, SubReg)
3460 .addReg(SrcReg, RegState::Implicit);
3461 }
3462
3463 MI.eraseFromParent();
3464
3465 return LoopBB;
3466}
3467
3468static unsigned getMOVRELDPseudo(const SIRegisterInfo &TRI,
3469 const TargetRegisterClass *VecRC) {
3470 switch (TRI.getRegSizeInBits(*VecRC)) {
3471 case 32: // 4 bytes
3472 return AMDGPU::V_MOVRELD_B32_V1;
3473 case 64: // 8 bytes
3474 return AMDGPU::V_MOVRELD_B32_V2;
3475 case 128: // 16 bytes
3476 return AMDGPU::V_MOVRELD_B32_V4;
3477 case 256: // 32 bytes
3478 return AMDGPU::V_MOVRELD_B32_V8;
3479 case 512: // 64 bytes
3480 return AMDGPU::V_MOVRELD_B32_V16;
3481 default:
3482 llvm_unreachable("unsupported size for MOVRELD pseudos")::llvm::llvm_unreachable_internal("unsupported size for MOVRELD pseudos"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3482)
;
3483 }
3484}
3485
3486static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
3487 MachineBasicBlock &MBB,
3488 const GCNSubtarget &ST) {
3489 const SIInstrInfo *TII = ST.getInstrInfo();
3490 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3491 MachineFunction *MF = MBB.getParent();
3492 MachineRegisterInfo &MRI = MF->getRegInfo();
3493
3494 Register Dst = MI.getOperand(0).getReg();
3495 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
3496 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3497 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
3498 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3499 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3500
3501 // This can be an immediate, but will be folded later.
3502 assert(Val->getReg())((Val->getReg()) ? static_cast<void> (0) : __assert_fail
("Val->getReg()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3502, __PRETTY_FUNCTION__))
;
3503
3504 unsigned SubReg;
3505 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
3506 SrcVec->getReg(),
3507 Offset);
3508 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3509
3510 if (Idx->getReg() == AMDGPU::NoRegister) {
3511 MachineBasicBlock::iterator I(&MI);
3512 const DebugLoc &DL = MI.getDebugLoc();
3513
3514 assert(Offset == 0)((Offset == 0) ? static_cast<void> (0) : __assert_fail (
"Offset == 0", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3514, __PRETTY_FUNCTION__))
;
3515
3516 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
3517 .add(*SrcVec)
3518 .add(*Val)
3519 .addImm(SubReg);
3520
3521 MI.eraseFromParent();
3522 return &MBB;
3523 }
3524
3525 if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, false)) {
3526 MachineBasicBlock::iterator I(&MI);
3527 const DebugLoc &DL = MI.getDebugLoc();
3528
3529 if (UseGPRIdxMode) {
3530 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3531 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst
3532 .add(*Val)
3533 .addReg(Dst, RegState::ImplicitDefine)
3534 .addReg(SrcVec->getReg(), RegState::Implicit)
3535 .addReg(AMDGPU::M0, RegState::Implicit);
3536
3537 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3538 } else {
3539 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3540
3541 BuildMI(MBB, I, DL, MovRelDesc)
3542 .addReg(Dst, RegState::Define)
3543 .addReg(SrcVec->getReg())
3544 .add(*Val)
3545 .addImm(SubReg - AMDGPU::sub0);
3546 }
3547
3548 MI.eraseFromParent();
3549 return &MBB;
3550 }
3551
3552 if (Val->isReg())
3553 MRI.clearKillFlags(Val->getReg());
3554
3555 const DebugLoc &DL = MI.getDebugLoc();
3556
3557 Register PhiReg = MRI.createVirtualRegister(VecRC);
3558
3559 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
3560 Offset, UseGPRIdxMode, false);
3561 MachineBasicBlock *LoopBB = InsPt->getParent();
3562
3563 if (UseGPRIdxMode) {
3564 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
3565 .addReg(PhiReg, RegState::Undef, SubReg) // vdst
3566 .add(*Val) // src0
3567 .addReg(Dst, RegState::ImplicitDefine)
3568 .addReg(PhiReg, RegState::Implicit)
3569 .addReg(AMDGPU::M0, RegState::Implicit);
3570 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3571 } else {
3572 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC));
3573
3574 BuildMI(*LoopBB, InsPt, DL, MovRelDesc)
3575 .addReg(Dst, RegState::Define)
3576 .addReg(PhiReg)
3577 .add(*Val)
3578 .addImm(SubReg - AMDGPU::sub0);
3579 }
3580
3581 MI.eraseFromParent();
3582
3583 return LoopBB;
3584}
3585
3586MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
3587 MachineInstr &MI, MachineBasicBlock *BB) const {
3588
3589 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3590 MachineFunction *MF = BB->getParent();
3591 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
3592
3593 if (TII->isMIMG(MI)) {
3594 if (MI.memoperands_empty() && MI.mayLoadOrStore()) {
3595 report_fatal_error("missing mem operand from MIMG instruction");
3596 }
3597 // Add a memoperand for mimg instructions so that they aren't assumed to
3598 // be ordered memory instuctions.
3599
3600 return BB;
3601 }
3602
3603 switch (MI.getOpcode()) {
3604 case AMDGPU::S_ADD_U64_PSEUDO:
3605 case AMDGPU::S_SUB_U64_PSEUDO: {
3606 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3607 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3608 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3609 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3610 const DebugLoc &DL = MI.getDebugLoc();
3611
3612 MachineOperand &Dest = MI.getOperand(0);
3613 MachineOperand &Src0 = MI.getOperand(1);
3614 MachineOperand &Src1 = MI.getOperand(2);
3615
3616 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3617 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3618
3619 MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3620 Src0, BoolRC, AMDGPU::sub0,
3621 &AMDGPU::SReg_32RegClass);
3622 MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3623 Src0, BoolRC, AMDGPU::sub1,
3624 &AMDGPU::SReg_32RegClass);
3625
3626 MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3627 Src1, BoolRC, AMDGPU::sub0,
3628 &AMDGPU::SReg_32RegClass);
3629 MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3630 Src1, BoolRC, AMDGPU::sub1,
3631 &AMDGPU::SReg_32RegClass);
3632
3633 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
3634
3635 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
3636 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
3637 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3638 .add(Src0Sub0)
3639 .add(Src1Sub0);
3640 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
3641 .add(Src0Sub1)
3642 .add(Src1Sub1);
3643 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3644 .addReg(DestSub0)
3645 .addImm(AMDGPU::sub0)
3646 .addReg(DestSub1)
3647 .addImm(AMDGPU::sub1);
3648 MI.eraseFromParent();
3649 return BB;
3650 }
3651 case AMDGPU::SI_INIT_M0: {
3652 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
3653 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3654 .add(MI.getOperand(0));
3655 MI.eraseFromParent();
3656 return BB;
3657 }
3658 case AMDGPU::SI_INIT_EXEC:
3659 // This should be before all vector instructions.
3660 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B64),
3661 AMDGPU::EXEC)
3662 .addImm(MI.getOperand(0).getImm());
3663 MI.eraseFromParent();
3664 return BB;
3665
3666 case AMDGPU::SI_INIT_EXEC_LO:
3667 // This should be before all vector instructions.
3668 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
3669 AMDGPU::EXEC_LO)
3670 .addImm(MI.getOperand(0).getImm());
3671 MI.eraseFromParent();
3672 return BB;
3673
3674 case AMDGPU::SI_INIT_EXEC_FROM_INPUT: {
3675 // Extract the thread count from an SGPR input and set EXEC accordingly.
3676 // Since BFM can't shift by 64, handle that case with CMP + CMOV.
3677 //
3678 // S_BFE_U32 count, input, {shift, 7}
3679 // S_BFM_B64 exec, count, 0
3680 // S_CMP_EQ_U32 count, 64
3681 // S_CMOV_B64 exec, -1
3682 MachineInstr *FirstMI = &*BB->begin();
3683 MachineRegisterInfo &MRI = MF->getRegInfo();
3684 Register InputReg = MI.getOperand(0).getReg();
3685 Register CountReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3686 bool Found = false;
3687
3688 // Move the COPY of the input reg to the beginning, so that we can use it.
3689 for (auto I = BB->begin(); I != &MI; I++) {
3690 if (I->getOpcode() != TargetOpcode::COPY ||
3691 I->getOperand(0).getReg() != InputReg)
3692 continue;
3693
3694 if (I == FirstMI) {
3695 FirstMI = &*++BB->begin();
3696 } else {
3697 I->removeFromParent();
3698 BB->insert(FirstMI, &*I);
3699 }
3700 Found = true;
3701 break;
3702 }
3703 assert(Found)((Found) ? static_cast<void> (0) : __assert_fail ("Found"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3703, __PRETTY_FUNCTION__))
;
3704 (void)Found;
3705
3706 // This should be before all vector instructions.
3707 unsigned Mask = (getSubtarget()->getWavefrontSize() << 1) - 1;
3708 bool isWave32 = getSubtarget()->isWave32();
3709 unsigned Exec = isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3710 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_BFE_U32), CountReg)
3711 .addReg(InputReg)
3712 .addImm((MI.getOperand(1).getImm() & Mask) | 0x70000);
3713 BuildMI(*BB, FirstMI, DebugLoc(),
3714 TII->get(isWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64),
3715 Exec)
3716 .addReg(CountReg)
3717 .addImm(0);
3718 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_CMP_EQ_U32))
3719 .addReg(CountReg, RegState::Kill)
3720 .addImm(getSubtarget()->getWavefrontSize());
3721 BuildMI(*BB, FirstMI, DebugLoc(),
3722 TII->get(isWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
3723 Exec)
3724 .addImm(-1);
3725 MI.eraseFromParent();
3726 return BB;
3727 }
3728
3729 case AMDGPU::GET_GROUPSTATICSIZE: {
3730 assert(getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA ||((getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA
|| getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL
) ? static_cast<void> (0) : __assert_fail ("getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3731, __PRETTY_FUNCTION__))
3731 getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL)((getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA
|| getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL
) ? static_cast<void> (0) : __assert_fail ("getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3731, __PRETTY_FUNCTION__))
;
3732 DebugLoc DL = MI.getDebugLoc();
3733 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
3734 .add(MI.getOperand(0))
3735 .addImm(MFI->getLDSSize());
3736 MI.eraseFromParent();
3737 return BB;
3738 }
3739 case AMDGPU::SI_INDIRECT_SRC_V1:
3740 case AMDGPU::SI_INDIRECT_SRC_V2:
3741 case AMDGPU::SI_INDIRECT_SRC_V4:
3742 case AMDGPU::SI_INDIRECT_SRC_V8:
3743 case AMDGPU::SI_INDIRECT_SRC_V16:
3744 return emitIndirectSrc(MI, *BB, *getSubtarget());
3745 case AMDGPU::SI_INDIRECT_DST_V1:
3746 case AMDGPU::SI_INDIRECT_DST_V2:
3747 case AMDGPU::SI_INDIRECT_DST_V4:
3748 case AMDGPU::SI_INDIRECT_DST_V8:
3749 case AMDGPU::SI_INDIRECT_DST_V16:
3750 return emitIndirectDst(MI, *BB, *getSubtarget());
3751 case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
3752 case AMDGPU::SI_KILL_I1_PSEUDO:
3753 return splitKillBlock(MI, BB);
3754 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
3755 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3756 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3757 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3758
3759 Register Dst = MI.getOperand(0).getReg();
3760 Register Src0 = MI.getOperand(1).getReg();
3761 Register Src1 = MI.getOperand(2).getReg();
3762 const DebugLoc &DL = MI.getDebugLoc();
3763 Register SrcCond = MI.getOperand(3).getReg();
3764
3765 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3766 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3767 const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3768 Register SrcCondCopy = MRI.createVirtualRegister(CondRC);
3769
3770 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
3771 .addReg(SrcCond);
3772 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
3773 .addImm(0)
3774 .addReg(Src0, 0, AMDGPU::sub0)
3775 .addImm(0)
3776 .addReg(Src1, 0, AMDGPU::sub0)
3777 .addReg(SrcCondCopy);
3778 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
3779 .addImm(0)
3780 .addReg(Src0, 0, AMDGPU::sub1)
3781 .addImm(0)
3782 .addReg(Src1, 0, AMDGPU::sub1)
3783 .addReg(SrcCondCopy);
3784
3785 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
3786 .addReg(DstLo)
3787 .addImm(AMDGPU::sub0)
3788 .addReg(DstHi)
3789 .addImm(AMDGPU::sub1);
3790 MI.eraseFromParent();
3791 return BB;
3792 }
3793 case AMDGPU::SI_BR_UNDEF: {
3794 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3795 const DebugLoc &DL = MI.getDebugLoc();
3796 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3797 .add(MI.getOperand(0));
3798 Br->getOperand(1).setIsUndef(true); // read undef SCC
3799 MI.eraseFromParent();
3800 return BB;
3801 }
3802 case AMDGPU::ADJCALLSTACKUP:
3803 case AMDGPU::ADJCALLSTACKDOWN: {
3804 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
3805 MachineInstrBuilder MIB(*MF, &MI);
3806
3807 // Add an implicit use of the frame offset reg to prevent the restore copy
3808 // inserted after the call from being reorderd after stack operations in the
3809 // the caller's frame.
3810 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
3811 .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
3812 .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
3813 return BB;
3814 }
3815 case AMDGPU::SI_CALL_ISEL: {
3816 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3817 const DebugLoc &DL = MI.getDebugLoc();
3818
3819 unsigned ReturnAddrReg = TII->getRegisterInfo().getReturnAddressReg(*MF);
3820
3821 MachineInstrBuilder MIB;
3822 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg);
3823
3824 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I)
3825 MIB.add(MI.getOperand(I));
3826
3827 MIB.cloneMemRefs(MI);
3828 MI.eraseFromParent();
3829 return BB;
3830 }
3831 case AMDGPU::V_ADD_I32_e32:
3832 case AMDGPU::V_SUB_I32_e32:
3833 case AMDGPU::V_SUBREV_I32_e32: {
3834 // TODO: Define distinct V_*_I32_Pseudo instructions instead.
3835 const DebugLoc &DL = MI.getDebugLoc();
3836 unsigned Opc = MI.getOpcode();
3837
3838 bool NeedClampOperand = false;
3839 if (TII->pseudoToMCOpcode(Opc) == -1) {
3840 Opc = AMDGPU::getVOPe64(Opc);
3841 NeedClampOperand = true;
3842 }
3843
3844 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
3845 if (TII->isVOP3(*I)) {
3846 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3847 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3848 I.addReg(TRI->getVCC(), RegState::Define);
3849 }
3850 I.add(MI.getOperand(1))
3851 .add(MI.getOperand(2));
3852 if (NeedClampOperand)
3853 I.addImm(0); // clamp bit for e64 encoding
3854
3855 TII->legalizeOperands(*I);
3856
3857 MI.eraseFromParent();
3858 return BB;
3859 }
3860 case AMDGPU::DS_GWS_INIT:
3861 case AMDGPU::DS_GWS_SEMA_V:
3862 case AMDGPU::DS_GWS_SEMA_BR:
3863 case AMDGPU::DS_GWS_SEMA_P:
3864 case AMDGPU::DS_GWS_SEMA_RELEASE_ALL:
3865 case AMDGPU::DS_GWS_BARRIER:
3866 // A s_waitcnt 0 is required to be the instruction immediately following.
3867 if (getSubtarget()->hasGWSAutoReplay()) {
3868 bundleInstWithWaitcnt(MI);
3869 return BB;
3870 }
3871
3872 return emitGWSMemViolTestLoop(MI, BB);
3873 default:
3874 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
3875 }
3876}
3877
3878bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const {
3879 return isTypeLegal(VT.getScalarType());
3880}
3881
3882bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
3883 // This currently forces unfolding various combinations of fsub into fma with
3884 // free fneg'd operands. As long as we have fast FMA (controlled by
3885 // isFMAFasterThanFMulAndFAdd), we should perform these.
3886
3887 // When fma is quarter rate, for f64 where add / sub are at best half rate,
3888 // most of these combines appear to be cycle neutral but save on instruction
3889 // count / code size.
3890 return true;
3891}
3892
3893EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
3894 EVT VT) const {
3895 if (!VT.isVector()) {
3896 return MVT::i1;
3897 }
3898 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
3899}
3900
3901MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT VT) const {
3902 // TODO: Should i16 be used always if legal? For now it would force VALU
3903 // shifts.
3904 return (VT == MVT::i16) ? MVT::i16 : MVT::i32;
3905}
3906
3907// Answering this is somewhat tricky and depends on the specific device which
3908// have different rates for fma or all f64 operations.
3909//
3910// v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
3911// regardless of which device (although the number of cycles differs between
3912// devices), so it is always profitable for f64.
3913//
3914// v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
3915// only on full rate devices. Normally, we should prefer selecting v_mad_f32
3916// which we can always do even without fused FP ops since it returns the same
3917// result as the separate operations and since it is always full
3918// rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
3919// however does not support denormals, so we do report fma as faster if we have
3920// a fast fma device and require denormals.
3921//
3922bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
3923 EVT VT) const {
3924 VT = VT.getScalarType();
3925
3926 switch (VT.getSimpleVT().SimpleTy) {
3927 case MVT::f32: {
3928 // This is as fast on some subtargets. However, we always have full rate f32
3929 // mad available which returns the same result as the separate operations
3930 // which we should prefer over fma. We can't use this if we want to support
3931 // denormals, so only report this in these cases.
3932 if (hasFP32Denormals(MF))
3933 return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts();
3934
3935 // If the subtarget has v_fmac_f32, that's just as good as v_mac_f32.
3936 return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts();
3937 }
3938 case MVT::f64:
3939 return true;
3940 case MVT::f16:
3941 return Subtarget->has16BitInsts() && hasFP64FP16Denormals(MF);
3942 default:
3943 break;
3944 }
3945
3946 return false;
3947}
3948
3949bool SITargetLowering::isFMADLegalForFAddFSub(const SelectionDAG &DAG,
3950 const SDNode *N) const {
3951 // TODO: Check future ftz flag
3952 // v_mad_f32/v_mac_f32 do not support denormals.
3953 EVT VT = N->getValueType(0);
3954 if (VT == MVT::f32)
3955 return !hasFP32Denormals(DAG.getMachineFunction());
3956 if (VT == MVT::f16) {
3957 return Subtarget->hasMadF16() &&
3958 !hasFP64FP16Denormals(DAG.getMachineFunction());
3959 }
3960
3961 return false;
3962}
3963
3964//===----------------------------------------------------------------------===//
3965// Custom DAG Lowering Operations
3966//===----------------------------------------------------------------------===//
3967
3968// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
3969// wider vector type is legal.
3970SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
3971 SelectionDAG &DAG) const {
3972 unsigned Opc = Op.getOpcode();
3973 EVT VT = Op.getValueType();
3974 assert(VT == MVT::v4f16)((VT == MVT::v4f16) ? static_cast<void> (0) : __assert_fail
("VT == MVT::v4f16", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3974, __PRETTY_FUNCTION__))
;
3975
3976 SDValue Lo, Hi;
3977 std::tie(Lo, Hi) = DAG.SplitVectorOperand(Op.getNode(), 0);
3978
3979 SDLoc SL(Op);
3980 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo,
3981 Op->getFlags());
3982 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi,
3983 Op->getFlags());
3984
3985 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
3986}
3987
3988// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
3989// wider vector type is legal.
3990SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
3991 SelectionDAG &DAG) const {
3992 unsigned Opc = Op.getOpcode();
3993 EVT VT = Op.getValueType();
3994 assert(VT == MVT::v4i16 || VT == MVT::v4f16)((VT == MVT::v4i16 || VT == MVT::v4f16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3994, __PRETTY_FUNCTION__))
;
3995
3996 SDValue Lo0, Hi0;
3997 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
3998 SDValue Lo1, Hi1;
3999 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4000
4001 SDLoc SL(Op);
4002
4003 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1,
4004 Op->getFlags());
4005 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1,
4006 Op->getFlags());
4007
4008 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4009}
4010
4011SDValue SITargetLowering::splitTernaryVectorOp(SDValue Op,
4012 SelectionDAG &DAG) const {
4013 unsigned Opc = Op.getOpcode();
4014 EVT VT = Op.getValueType();
4015 assert(VT == MVT::v4i16 || VT == MVT::v4f16)((VT == MVT::v4i16 || VT == MVT::v4f16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4015, __PRETTY_FUNCTION__))
;
4016
4017 SDValue Lo0, Hi0;
4018 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
4019 SDValue Lo1, Hi1;
4020 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4021 SDValue Lo2, Hi2;
4022 std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2);
4023
4024 SDLoc SL(Op);
4025
4026 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2,
4027 Op->getFlags());
4028 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2,
4029 Op->getFlags());
4030
4031 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4032}
4033
4034
4035SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4036 switch (Op.getOpcode()) {
4037 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
4038 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4039 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4040 case ISD::LOAD: {
4041 SDValue Result = LowerLOAD(Op, DAG);
4042 assert((!Result.getNode() ||(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4044, __PRETTY_FUNCTION__))
4043 Result.getNode()->getNumValues() == 2) &&(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4044, __PRETTY_FUNCTION__))
4044 "Load should return a value and a chain")(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4044, __PRETTY_FUNCTION__))
;
4045 return Result;
4046 }
4047
4048 case ISD::FSIN:
4049 case ISD::FCOS:
4050 return LowerTrig(Op, DAG);
4051 case ISD::SELECT: return LowerSELECT(Op, DAG);
4052 case ISD::FDIV: return LowerFDIV(Op, DAG);
4053 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
4054 case ISD::STORE: return LowerSTORE(Op, DAG);
4055 case ISD::GlobalAddress: {
4056 MachineFunction &MF = DAG.getMachineFunction();
4057 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
4058 return LowerGlobalAddress(MFI, Op, DAG);
4059 }
4060 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4061 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
4062 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
4063 case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
4064 case ISD::INSERT_SUBVECTOR:
4065 return lowerINSERT_SUBVECTOR(Op, DAG);
4066 case ISD::INSERT_VECTOR_ELT:
4067 return lowerINSERT_VECTOR_ELT(Op, DAG);
4068 case ISD::EXTRACT_VECTOR_ELT:
4069 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4070 case ISD::VECTOR_SHUFFLE:
4071 return lowerVECTOR_SHUFFLE(Op, DAG);
4072 case ISD::BUILD_VECTOR:
4073 return lowerBUILD_VECTOR(Op, DAG);
4074 case ISD::FP_ROUND:
4075 return lowerFP_ROUND(Op, DAG);
4076 case ISD::TRAP:
4077 return lowerTRAP(Op, DAG);
4078 case ISD::DEBUGTRAP:
4079 return lowerDEBUGTRAP(Op, DAG);
4080 case ISD::FABS:
4081 case ISD::FNEG:
4082 case ISD::FCANONICALIZE:
4083 return splitUnaryVectorOp(Op, DAG);
4084 case ISD::FMINNUM:
4085 case ISD::FMAXNUM:
4086 return lowerFMINNUM_FMAXNUM(Op, DAG);
4087 case ISD::FMA:
4088 return splitTernaryVectorOp(Op, DAG);
4089 case ISD::SHL:
4090 case ISD::SRA:
4091 case ISD::SRL:
4092 case ISD::ADD:
4093 case ISD::SUB:
4094 case ISD::MUL:
4095 case ISD::SMIN:
4096 case ISD::SMAX:
4097 case ISD::UMIN:
4098 case ISD::UMAX:
4099 case ISD::FADD:
4100 case ISD::FMUL:
4101 case ISD::FMINNUM_IEEE:
4102 case ISD::FMAXNUM_IEEE:
4103 return splitBinaryVectorOp(Op, DAG);
4104 }
4105 return SDValue();
4106}
4107
4108static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT,
4109 const SDLoc &DL,
4110 SelectionDAG &DAG, bool Unpacked) {
4111 if (!LoadVT.isVector())
4112 return Result;
4113
4114 if (Unpacked) { // From v2i32/v4i32 back to v2f16/v4f16.
4115 // Truncate to v2i16/v4i16.
4116 EVT IntLoadVT = LoadVT.changeTypeToInteger();
4117
4118 // Workaround legalizer not scalarizing truncate after vector op
4119 // legalization byt not creating intermediate vector trunc.
4120 SmallVector<SDValue, 4> Elts;
4121 DAG.ExtractVectorElements(Result, Elts);
4122 for (SDValue &Elt : Elts)
4123 Elt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Elt);
4124
4125 Result = DAG.getBuildVector(IntLoadVT, DL, Elts);
4126
4127 // Bitcast to original type (v2f16/v4f16).
4128 return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
4129 }
4130
4131 // Cast back to the original packed type.
4132 return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
4133}
4134
4135SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
4136 MemSDNode *M,
4137 SelectionDAG &DAG,
4138 ArrayRef<SDValue> Ops,
4139 bool IsIntrinsic) const {
4140 SDLoc DL(M);
4141
4142 bool Unpacked = Subtarget->hasUnpackedD16VMem();
4143 EVT LoadVT = M->getValueType(0);
4144
4145 EVT EquivLoadVT = LoadVT;
4146 if (Unpacked && LoadVT.isVector()) {
4147 EquivLoadVT = LoadVT.isVector() ?
4148 EVT::getVectorVT(*DAG.getContext(), MVT::i32,
4149 LoadVT.getVectorNumElements()) : LoadVT;
4150 }
4151
4152 // Change from v4f16/v2f16 to EquivLoadVT.
4153 SDVTList VTList = DAG.getVTList(EquivLoadVT, MVT::Other);
4154
4155 SDValue Load
4156 = DAG.getMemIntrinsicNode(
4157 IsIntrinsic ? (unsigned)ISD::INTRINSIC_W_CHAIN : Opcode, DL,
4158 VTList, Ops, M->getMemoryVT(),
4159 M->getMemOperand());
4160 if (!Unpacked) // Just adjusted the opcode.
4161 return Load;
4162
4163 SDValue Adjusted = adjustLoadValueTypeImpl(Load, LoadVT, DL, DAG, Unpacked);
4164
4165 return DAG.getMergeValues({ Adjusted, Load.getValue(1) }, DL);
4166}
4167
4168SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
4169 SelectionDAG &DAG,
4170 ArrayRef<SDValue> Ops) const {
4171 SDLoc DL(M);
4172 EVT LoadVT = M->getValueType(0);
4173 EVT EltType = LoadVT.getScalarType();
4174 EVT IntVT = LoadVT.changeTypeToInteger();
4175
4176 bool IsD16 = IsFormat && (EltType.getSizeInBits() == 16);
4177
4178 unsigned Opc =
4179 IsFormat ? AMDGPUISD::BUFFER_LOAD_FORMAT : AMDGPUISD::BUFFER_LOAD;
4180
4181 if (IsD16) {
4182 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, M, DAG, Ops);
4183 }
4184
4185 // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
4186 if (!IsD16 && !LoadVT.isVector() && EltType.getSizeInBits() < 32)
4187 return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
4188
4189 if (isTypeLegal(LoadVT)) {
4190 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT,
4191 M->getMemOperand(), DAG);
4192 }
4193
4194 EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT);
4195 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other);
4196 SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT,
4197 M->getMemOperand(), DAG);
4198 return DAG.getMergeValues(
4199 {DAG.getNode(ISD::BITCAST, DL, LoadVT, MemNode), MemNode.getValue(1)},
4200 DL);
4201}
4202
4203static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
4204 SDNode *N, SelectionDAG &DAG) {
4205 EVT VT = N->getValueType(0);
4206 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4207 int CondCode = CD->getSExtValue();
4208 if (CondCode < ICmpInst::Predicate::FIRST_ICMP_PREDICATE ||
4209 CondCode > ICmpInst::Predicate::LAST_ICMP_PREDICATE)
4210 return DAG.getUNDEF(VT);
4211
4212 ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
4213
4214 SDValue LHS = N->getOperand(1);
4215 SDValue RHS = N->getOperand(2);
4216
4217 SDLoc DL(N);
4218
4219 EVT CmpVT = LHS.getValueType();
4220 if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) {
4221 unsigned PromoteOp = ICmpInst::isSigned(IcInput) ?
4222 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4223 LHS = DAG.getNode(PromoteOp, DL, MVT::i32, LHS);
4224 RHS = DAG.getNode(PromoteOp, DL, MVT::i32, RHS);
4225 }
4226
4227 ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
4228
4229 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4230 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4231
4232 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS,
4233 DAG.getCondCode(CCOpcode));
4234 if (VT.bitsEq(CCVT))
4235 return SetCC;
4236 return DAG.getZExtOrTrunc(SetCC, DL, VT);
4237}
4238
4239static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI,
4240 SDNode *N, SelectionDAG &DAG) {
4241 EVT VT = N->getValueType(0);
4242 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4243
4244 int CondCode = CD->getSExtValue();
4245 if (CondCode < FCmpInst::Predicate::FIRST_FCMP_PREDICATE ||
4246 CondCode > FCmpInst::Predicate::LAST_FCMP_PREDICATE) {
4247 return DAG.getUNDEF(VT);
4248 }
4249
4250 SDValue Src0 = N->getOperand(1);
4251 SDValue Src1 = N->getOperand(2);
4252 EVT CmpVT = Src0.getValueType();
4253 SDLoc SL(N);
4254
4255 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
4256 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4257 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
4258 }
4259
4260 FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
4261 ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
4262 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4263 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4264 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0,
4265 Src1, DAG.getCondCode(CCOpcode));
4266 if (VT.bitsEq(CCVT))
4267 return SetCC;
4268 return DAG.getZExtOrTrunc(SetCC, SL, VT);
4269}
4270
4271void SITargetLowering::ReplaceNodeResults(SDNode *N,
4272 SmallVectorImpl<SDValue> &Results,
4273 SelectionDAG &DAG) const {
4274 switch (N->getOpcode()) {
4275 case ISD::INSERT_VECTOR_ELT: {
4276 if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
4277 Results.push_back(Res);
4278 return;
4279 }
4280 case ISD::EXTRACT_VECTOR_ELT: {
4281 if (SDValue Res = lowerEXTRACT_VECTOR_ELT(SDValue(N, 0), DAG))
4282 Results.push_back(Res);
4283 return;
4284 }
4285 case ISD::INTRINSIC_WO_CHAIN: {
4286 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4287 switch (IID) {
4288 case Intrinsic::amdgcn_cvt_pkrtz: {
4289 SDValue Src0 = N->getOperand(1);
4290 SDValue Src1 = N->getOperand(2);
4291 SDLoc SL(N);
4292 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32,
4293 Src0, Src1);
4294 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt));
4295 return;
4296 }
4297 case Intrinsic::amdgcn_cvt_pknorm_i16:
4298 case Intrinsic::amdgcn_cvt_pknorm_u16:
4299 case Intrinsic::amdgcn_cvt_pk_i16:
4300 case Intrinsic::amdgcn_cvt_pk_u16: {
4301 SDValue Src0 = N->getOperand(1);
4302 SDValue Src1 = N->getOperand(2);
4303 SDLoc SL(N);
4304 unsigned Opcode;
4305
4306 if (IID == Intrinsic::amdgcn_cvt_pknorm_i16)
4307 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
4308 else if (IID == Intrinsic::amdgcn_cvt_pknorm_u16)
4309 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
4310 else if (IID == Intrinsic::amdgcn_cvt_pk_i16)
4311 Opcode = AMDGPUISD::CVT_PK_I16_I32;
4312 else
4313 Opcode = AMDGPUISD::CVT_PK_U16_U32;
4314
4315 EVT VT = N->getValueType(0);
4316 if (isTypeLegal(VT))
4317 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
4318 else {
4319 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
4320 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt));
4321 }
4322 return;
4323 }
4324 }
4325 break;
4326 }
4327 case ISD::INTRINSIC_W_CHAIN: {
4328 if (SDValue Res = LowerINTRINSIC_W_CHAIN(SDValue(N, 0), DAG)) {
4329 if (Res.getOpcode() == ISD::MERGE_VALUES) {
4330 // FIXME: Hacky
4331 Results.push_back(Res.getOperand(0));
4332 Results.push_back(Res.getOperand(1));
4333 } else {
4334 Results.push_back(Res);
4335 Results.push_back(Res.getValue(1));
4336 }
4337 return;
4338 }
4339
4340 break;
4341 }
4342 case ISD::SELECT: {
4343 SDLoc SL(N);
4344 EVT VT = N->getValueType(0);
4345 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
4346 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1));
4347 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2));
4348
4349 EVT SelectVT = NewVT;
4350 if (NewVT.bitsLT(MVT::i32)) {
4351 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS);
4352 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS);
4353 SelectVT = MVT::i32;
4354 }
4355
4356 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT,
4357 N->getOperand(0), LHS, RHS);
4358
4359 if (NewVT != SelectVT)
4360 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect);
4361 Results.push_back(DAG.getNode(ISD::BITCAST, SL, VT, NewSelect));
4362 return;
4363 }
4364 case ISD::FNEG: {
4365 if (N->getValueType(0) != MVT::v2f16)
4366 break;
4367
4368 SDLoc SL(N);
4369 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
4370
4371 SDValue Op = DAG.getNode(ISD::XOR, SL, MVT::i32,
4372 BC,
4373 DAG.getConstant(0x80008000, SL, MVT::i32));
4374 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
4375 return;
4376 }
4377 case ISD::FABS: {
4378 if (N->getValueType(0) != MVT::v2f16)
4379 break;
4380
4381 SDLoc SL(N);
4382 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
4383
4384 SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32,
4385 BC,
4386 DAG.getConstant(0x7fff7fff, SL, MVT::i32));
4387 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
4388 return;
4389 }
4390 default:
4391 break;
4392 }
4393}
4394
4395/// Helper function for LowerBRCOND
4396static SDNode *findUser(SDValue Value, unsigned Opcode) {
4397
4398 SDNode *Parent = Value.getNode();
4399 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
4400 I != E; ++I) {
4401
4402 if (I.getUse().get() != Value)
4403 continue;
4404
4405 if (I->getOpcode() == Opcode)
4406 return *I;
4407 }
4408 return nullptr;
4409}
4410
4411unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
4412 if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
4413 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
4414 case Intrinsic::amdgcn_if:
4415 return AMDGPUISD::IF;
4416 case Intrinsic::amdgcn_else:
4417 return AMDGPUISD::ELSE;
4418 case Intrinsic::amdgcn_loop:
4419 return AMDGPUISD::LOOP;
4420 case Intrinsic::amdgcn_end_cf:
4421 llvm_unreachable("should not occur")::llvm::llvm_unreachable_internal("should not occur", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4421)
;
4422 default:
4423 return 0;
4424 }
4425 }
4426
4427 // break, if_break, else_break are all only used as inputs to loop, not
4428 // directly as branch conditions.
4429 return 0;
4430}
4431
4432bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
4433 const Triple &TT = getTargetMachine().getTargetTriple();
4434 return (GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
4435 GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
4436 AMDGPU::shouldEmitConstantsToTextSection(TT);
4437}
4438
4439bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
4440 // FIXME: Either avoid relying on address space here or change the default
4441 // address space for functions to avoid the explicit check.
4442 return (GV->getValueType()->isFunctionTy() ||
4443 GV->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
4444 GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
4445 GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
4446 !shouldEmitFixup(GV) &&
4447 !getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
4448}
4449
4450bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
4451 return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
4452}
4453
4454/// This transforms the control flow intrinsics to get the branch destination as
4455/// last parameter, also switches branch target with BR if the need arise
4456SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
4457 SelectionDAG &DAG) const {
4458 SDLoc DL(BRCOND);
4459
4460 SDNode *Intr = BRCOND.getOperand(1).getNode();
4461 SDValue Target = BRCOND.getOperand(2);
4462 SDNode *BR = nullptr;
4463 SDNode *SetCC = nullptr;
4464
4465 if (Intr->getOpcode() == ISD::SETCC) {
4466 // As long as we negate the condition everything is fine
4467 SetCC = Intr;
4468 Intr = SetCC->getOperand(0).getNode();
4469
4470 } else {
4471 // Get the target from BR if we don't negate the condition
4472 BR = findUser(BRCOND, ISD::BR);
4473 Target = BR->getOperand(1);
4474 }
4475
4476 // FIXME: This changes the types of the intrinsics instead of introducing new
4477 // nodes with the correct types.
4478 // e.g. llvm.amdgcn.loop
4479
4480 // eg: i1,ch = llvm.amdgcn.loop t0, TargetConstant:i32<6271>, t3
4481 // => t9: ch = llvm.amdgcn.loop t0, TargetConstant:i32<6271>, t3, BasicBlock:ch<bb1 0x7fee5286d088>
4482
4483 unsigned CFNode = isCFIntrinsic(Intr);
4484 if (CFNode == 0) {
4485 // This is a uniform branch so we don't need to legalize.
4486 return BRCOND;
4487 }
4488
4489 bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||
4490 Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN;
4491
4492 assert(!SetCC ||((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4495, __PRETTY_FUNCTION__))
4493 (SetCC->getConstantOperandVal(1) == 1 &&((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4495, __PRETTY_FUNCTION__))
4494 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4495, __PRETTY_FUNCTION__))
4495 ISD::SETNE))((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4495, __PRETTY_FUNCTION__))
;
4496
4497 // operands of the new intrinsic call
4498 SmallVector<SDValue, 4> Ops;
4499 if (HaveChain)
4500 Ops.push_back(BRCOND.getOperand(0));
4501
4502 Ops.append(Intr->op_begin() + (HaveChain ? 2 : 1), Intr->op_end());
4503 Ops.push_back(Target);
4504
4505 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
4506
4507 // build the new intrinsic call
4508 SDNode *Result = DAG.getNode(CFNode, DL, DAG.getVTList(Res), Ops).getNode();
4509
4510 if (!HaveChain) {
4511 SDValue Ops[] = {
4512 SDValue(Result, 0),
4513 BRCOND.getOperand(0)
4514 };
4515
4516 Result = DAG.getMergeValues(Ops, DL).getNode();
4517 }
4518
4519 if (BR) {
4520 // Give the branch instruction our target
4521 SDValue Ops[] = {
4522 BR->getOperand(0),
4523 BRCOND.getOperand(2)
4524 };
4525 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
4526 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
4527 BR = NewBR.getNode();
4528 }
4529
4530 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
4531
4532 // Copy the intrinsic results to registers
4533 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
4534 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
4535 if (!CopyToReg)
4536 continue;
4537
4538 Chain = DAG.getCopyToReg(
4539 Chain, DL,
4540 CopyToReg->getOperand(1),
4541 SDValue(Result, i - 1),
4542 SDValue());
4543
4544 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
4545 }
4546
4547 // Remove the old intrinsic from the chain
4548 DAG.ReplaceAllUsesOfValueWith(
4549 SDValue(Intr, Intr->getNumValues() - 1),
4550 Intr->getOperand(0));
4551
4552 return Chain;
4553}
4554
4555SDValue SITargetLowering::LowerRETURNADDR(SDValue Op,
4556 SelectionDAG &DAG) const {
4557 MVT VT = Op.getSimpleValueType();
4558 SDLoc DL(Op);
4559 // Checking the depth
4560 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0)
4561 return DAG.getConstant(0, DL, VT);
4562
4563 MachineFunction &MF = DAG.getMachineFunction();
4564 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4565 // Check for kernel and shader functions
4566 if (Info->isEntryFunction())
4567 return DAG.getConstant(0, DL, VT);
4568
4569 MachineFrameInfo &MFI = MF.getFrameInfo();
4570 // There is a call to @llvm.returnaddress in this function
4571 MFI.setReturnAddressIsTaken(true);
4572
4573 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
4574 // Get the return address reg and mark it as an implicit live-in
4575 unsigned Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent()));
4576
4577 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4578}
4579
4580SDValue SITargetLowering::getFPExtOrFPTrunc(SelectionDAG &DAG,
4581 SDValue Op,
4582 const SDLoc &DL,
4583 EVT VT) const {
4584 return Op.getValueType().bitsLE(VT) ?
4585 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) :
4586 DAG.getNode(ISD::FTRUNC, DL, VT, Op);
4587}
4588
4589SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
4590 assert(Op.getValueType() == MVT::f16 &&((Op.getValueType() == MVT::f16 && "Do not know how to custom lower FP_ROUND for non-f16 type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4591, __PRETTY_FUNCTION__))
4591 "Do not know how to custom lower FP_ROUND for non-f16 type")((Op.getValueType() == MVT::f16 && "Do not know how to custom lower FP_ROUND for non-f16 type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4591, __PRETTY_FUNCTION__))
;
4592
4593 SDValue Src = Op.getOperand(0);
4594 EVT SrcVT = Src.getValueType();
4595 if (SrcVT != MVT::f64)
4596 return Op;
4597
4598 SDLoc DL(Op);
4599
4600 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);
4601 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToFp16);
4602 return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);
4603}
4604
4605SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
4606 SelectionDAG &DAG) const {
4607 EVT VT = Op.getValueType();
4608 const MachineFunction &MF = DAG.getMachineFunction();
4609 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4610 bool IsIEEEMode = Info->getMode().IEEE;
4611
4612 // FIXME: Assert during eslection that this is only selected for
4613 // ieee_mode. Currently a combine can produce the ieee version for non-ieee
4614 // mode functions, but this happens to be OK since it's only done in cases
4615 // where there is known no sNaN.
4616 if (IsIEEEMode)
4617 return expandFMINNUM_FMAXNUM(Op.getNode(), DAG);
4618
4619 if (VT == MVT::v4f16)
4620 return splitBinaryVectorOp(Op, DAG);
4621 return Op;
4622}
4623
4624SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
4625 SDLoc SL(Op);
4626 SDValue Chain = Op.getOperand(0);
4627
4628 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
4629 !Subtarget->isTrapHandlerEnabled())
4630 return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain);
4631
4632 MachineFunction &MF = DAG.getMachineFunction();
4633 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4634 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
4635 assert(UserSGPR != AMDGPU::NoRegister)((UserSGPR != AMDGPU::NoRegister) ? static_cast<void> (
0) : __assert_fail ("UserSGPR != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4635, __PRETTY_FUNCTION__))
;
4636 SDValue QueuePtr = CreateLiveInRegister(
4637 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
4638 SDValue SGPR01 = DAG.getRegister(AMDGPU::SGPR0_SGPR1, MVT::i64);
4639 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01,
4640 QueuePtr, SDValue());
4641 SDValue Ops[] = {
4642 ToReg,
4643 DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMTrap, SL, MVT::i16),
4644 SGPR01,
4645 ToReg.getValue(1)
4646 };
4647 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
4648}
4649
4650SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
4651 SDLoc SL(Op);
4652 SDValue Chain = Op.getOperand(0);
4653 MachineFunction &MF = DAG.getMachineFunction();
4654
4655 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
4656 !Subtarget->isTrapHandlerEnabled()) {
4657 DiagnosticInfoUnsupported NoTrap(MF.getFunction(),
4658 "debugtrap handler not supported",
4659 Op.getDebugLoc(),
4660 DS_Warning);
4661 LLVMContext &Ctx = MF.getFunction().getContext();
4662 Ctx.diagnose(NoTrap);
4663 return Chain;
4664 }
4665
4666 SDValue Ops[] = {
4667 Chain,
4668 DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMDebugTrap, SL, MVT::i16)
4669 };
4670 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
4671}
4672
4673SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
4674 SelectionDAG &DAG) const {
4675 // FIXME: Use inline constants (src_{shared, private}_base) instead.
4676 if (Subtarget->hasApertureRegs()) {
4677 unsigned Offset = AS == AMDGPUAS::LOCAL_ADDRESS ?
4678 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE :
4679 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE;
4680 unsigned WidthM1 = AS == AMDGPUAS::LOCAL_ADDRESS ?
4681 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
4682 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
4683 unsigned Encoding =
4684 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
4685 Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
4686 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
4687
4688 SDValue EncodingImm = DAG.getTargetConstant(Encoding, DL, MVT::i16);
4689 SDValue ApertureReg = SDValue(
4690 DAG.getMachineNode(AMDGPU::S_GETREG_B32, DL, MVT::i32, EncodingImm), 0);
4691 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32);
4692 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);
4693 }
4694
4695 MachineFunction &MF = DAG.getMachineFunction();
4696 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4697 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
4698 assert(UserSGPR != AMDGPU::NoRegister)((UserSGPR != AMDGPU::NoRegister) ? static_cast<void> (
0) : __assert_fail ("UserSGPR != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4698, __PRETTY_FUNCTION__))
;
4699
4700 SDValue QueuePtr = CreateLiveInRegister(
4701 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
4702
4703 // Offset into amd_queue_t for group_segment_aperture_base_hi /
4704 // private_segment_aperture_base_hi.
4705 uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
4706
4707 SDValue Ptr = DAG.getObjectPtrOffset(DL, QueuePtr, StructOffset);
4708
4709 // TODO: Use custom target PseudoSourceValue.
4710 // TODO: We should use the value from the IR intrinsic call, but it might not
4711 // be available and how do we get it?
4712 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
4713 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,
4714 MinAlign(64, StructOffset),
4715 MachineMemOperand::MODereferenceable |
4716 MachineMemOperand::MOInvariant);
4717}
4718
4719SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
4720 SelectionDAG &DAG) const {
4721 SDLoc SL(Op);
4722 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
4723
4724 SDValue Src = ASC->getOperand(0);
4725 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64);
4726
4727 const AMDGPUTargetMachine &TM =
4728 static_cast<const AMDGPUTargetMachine &>(getTargetMachine());
4729
4730 // flat -> local/private
4731 if (ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
4732 unsigned DestAS = ASC->getDestAddressSpace();
4733
4734 if (DestAS == AMDGPUAS::LOCAL_ADDRESS ||
4735 DestAS == AMDGPUAS::PRIVATE_ADDRESS) {
4736 unsigned NullVal = TM.getNullPointerValue(DestAS);
4737 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
4738 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE);
4739 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
4740
4741 return DAG.getNode(ISD::SELECT, SL, MVT::i32,
4742 NonNull, Ptr, SegmentNullPtr);
4743 }
4744 }
4745
4746 // local/private -> flat
4747 if (ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
4748 unsigned SrcAS = ASC->getSrcAddressSpace();
4749
4750 if (SrcAS == AMDGPUAS::LOCAL_ADDRESS ||
4751 SrcAS == AMDGPUAS::PRIVATE_ADDRESS) {
4752 unsigned NullVal = TM.getNullPointerValue(SrcAS);
4753 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
4754
4755 SDValue NonNull
4756 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE);
4757
4758 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), SL, DAG);
4759 SDValue CvtPtr
4760 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture);
4761
4762 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull,
4763 DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr),
4764 FlatNullPtr);
4765 }
4766 }
4767
4768 // global <-> flat are no-ops and never emitted.
4769
4770 const MachineFunction &MF = DAG.getMachineFunction();
4771 DiagnosticInfoUnsupported InvalidAddrSpaceCast(
4772 MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc());
4773 DAG.getContext()->diagnose(InvalidAddrSpaceCast);
4774
4775 return DAG.getUNDEF(ASC->getValueType(0));
4776}
4777
4778// This lowers an INSERT_SUBVECTOR by extracting the individual elements from
4779// the small vector and inserting them into the big vector. That is better than
4780// the default expansion of doing it via a stack slot. Even though the use of
4781// the stack slot would be optimized away afterwards, the stack slot itself
4782// remains.
4783SDValue SITargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
4784 SelectionDAG &DAG) const {
4785 SDValue Vec = Op.getOperand(0);
4786 SDValue Ins = Op.getOperand(1);
4787 SDValue Idx = Op.getOperand(2);
4788 EVT VecVT = Vec.getValueType();
4789 EVT InsVT = Ins.getValueType();
4790 EVT EltVT = VecVT.getVectorElementType();
4791 unsigned InsNumElts = InsVT.getVectorNumElements();
4792 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4793 SDLoc SL(Op);
4794
4795 for (unsigned I = 0; I != InsNumElts; ++I) {
4796 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Ins,
4797 DAG.getConstant(I, SL, MVT::i32));
4798 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt,
4799 DAG.getConstant(IdxVal + I, SL, MVT::i32));
4800 }
4801 return Vec;
4802}
4803
4804SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4805 SelectionDAG &DAG) const {
4806 SDValue Vec = Op.getOperand(0);
4807 SDValue InsVal = Op.getOperand(1);
4808 SDValue Idx = Op.getOperand(2);
4809 EVT VecVT = Vec.getValueType();
4810 EVT EltVT = VecVT.getVectorElementType();
4811 unsigned VecSize = VecVT.getSizeInBits();
4812 unsigned EltSize = EltVT.getSizeInBits();
4813
4814
4815 assert(VecSize <= 64)((VecSize <= 64) ? static_cast<void> (0) : __assert_fail
("VecSize <= 64", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4815, __PRETTY_FUNCTION__))
;
4816
4817 unsigned NumElts = VecVT.getVectorNumElements();
4818 SDLoc SL(Op);
4819 auto KIdx = dyn_cast<ConstantSDNode>(Idx);
4820
4821 if (NumElts == 4 && EltSize == 16 && KIdx) {
4822 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec);
4823
4824 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
4825 DAG.getConstant(0, SL, MVT::i32));
4826 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
4827 DAG.getConstant(1, SL, MVT::i32));
4828
4829 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf);
4830 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf);
4831
4832 unsigned Idx = KIdx->getZExtValue();
4833 bool InsertLo = Idx < 2;
4834 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16,
4835 InsertLo ? LoVec : HiVec,
4836 DAG.getNode(ISD::BITCAST, SL, MVT::i16, InsVal),
4837 DAG.getConstant(InsertLo ? Idx : (Idx - 2), SL, MVT::i32));
4838
4839 InsHalf = DAG.getNode(ISD::BITCAST, SL, MVT::i32, InsHalf);
4840
4841 SDValue Concat = InsertLo ?
4842 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) :
4843 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf });
4844
4845 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
4846 }
4847
4848 if (isa<ConstantSDNode>(Idx))
4849 return SDValue();
4850
4851 MVT IntVT = MVT::getIntegerVT(VecSize);
4852
4853 // Avoid stack access for dynamic indexing.
4854 // v_bfi_b32 (v_bfm_b32 16, (shl idx, 16)), val, vec
4855
4856 // Create a congruent vector with the target value in each element so that
4857 // the required element can be masked and ORed into the target vector.
4858 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT,
4859 DAG.getSplatBuildVector(VecVT, SL, InsVal));
4860
4861 assert(isPowerOf2_32(EltSize))((isPowerOf2_32(EltSize)) ? static_cast<void> (0) : __assert_fail
("isPowerOf2_32(EltSize)", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4861, __PRETTY_FUNCTION__))
;
4862 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
4863
4864 // Convert vector index to bit-index.
4865 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
4866
4867 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
4868 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT,
4869 DAG.getConstant(0xffff, SL, IntVT),
4870 ScaledIdx);
4871
4872 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal);
4873 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT,
4874 DAG.getNOT(SL, BFM, IntVT), BCVec);
4875
4876 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS);
4877 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI);
4878}
4879
4880SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4881 SelectionDAG &DAG) const {
4882 SDLoc SL(Op);
4883
4884 EVT ResultVT = Op.getValueType();
4885 SDValue Vec = Op.getOperand(0);
4886 SDValue Idx = Op.getOperand(1);
4887 EVT VecVT = Vec.getValueType();
4888 unsigned VecSize = VecVT.getSizeInBits();
4889 EVT EltVT = VecVT.getVectorElementType();
4890 assert(VecSize <= 64)((VecSize <= 64) ? static_cast<void> (0) : __assert_fail
("VecSize <= 64", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4890, __PRETTY_FUNCTION__))
;
4891
4892 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
4893
4894 // Make sure we do any optimizations that will make it easier to fold
4895 // source modifiers before obscuring it with bit operations.
4896
4897 // XXX - Why doesn't this get called when vector_shuffle is expanded?
4898 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
4899 return Combined;
4900
4901 unsigned EltSize = EltVT.getSizeInBits();
4902 assert(isPowerOf2_32(EltSize))((isPowerOf2_32(EltSize)) ? static_cast<void> (0) : __assert_fail
("isPowerOf2_32(EltSize)", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4902, __PRETTY_FUNCTION__))
;
4903
4904 MVT IntVT = MVT::getIntegerVT(VecSize);
4905 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
4906
4907 // Convert vector index to bit-index (* EltSize)
4908 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
4909
4910 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
4911 SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx);
4912
4913 if (ResultVT == MVT::f16) {
4914 SDValue Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Elt);
4915 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
4916 }
4917
4918 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT);
4919}
4920
4921static bool elementPairIsContiguous(ArrayRef<int> Mask, int Elt) {
4922 assert(Elt % 2 == 0)((Elt % 2 == 0) ? static_cast<void> (0) : __assert_fail
("Elt % 2 == 0", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4922, __PRETTY_FUNCTION__))
;
4923 return Mask[Elt + 1] == Mask[Elt] + 1 && (Mask[Elt] % 2 == 0);
4924}
4925
4926SDValue SITargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4927 SelectionDAG &DAG) const {
4928 SDLoc SL(Op);
4929 EVT ResultVT = Op.getValueType();
4930 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
4931
4932 EVT PackVT = ResultVT.isInteger() ? MVT::v2i16 : MVT::v2f16;
4933 EVT EltVT = PackVT.getVectorElementType();
4934 int SrcNumElts = Op.getOperand(0).getValueType().getVectorNumElements();
4935
4936 // vector_shuffle <0,1,6,7> lhs, rhs
4937 // -> concat_vectors (extract_subvector lhs, 0), (extract_subvector rhs, 2)
4938 //
4939 // vector_shuffle <6,7,2,3> lhs, rhs
4940 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 2)
4941 //
4942 // vector_shuffle <6,7,0,1> lhs, rhs
4943 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 0)
4944
4945 // Avoid scalarizing when both halves are reading from consecutive elements.
4946 SmallVector<SDValue, 4> Pieces;
4947 for (int I = 0, N = ResultVT.getVectorNumElements(); I != N; I += 2) {
4948 if (elementPairIsContiguous(SVN->getMask(), I)) {
4949 const int Idx = SVN->getMaskElt(I);
4950 int VecIdx = Idx < SrcNumElts ? 0 : 1;
4951 int EltIdx = Idx < SrcNumElts ? Idx : Idx - SrcNumElts;
4952 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL,
4953 PackVT, SVN->getOperand(VecIdx),
4954 DAG.getConstant(EltIdx, SL, MVT::i32));
4955 Pieces.push_back(SubVec);
4956 } else {
4957 const int Idx0 = SVN->getMaskElt(I);
4958 const int Idx1 = SVN->getMaskElt(I + 1);
4959 int VecIdx0 = Idx0 < SrcNumElts ? 0 : 1;
4960 int VecIdx1 = Idx1 < SrcNumElts ? 0 : 1;
4961 int EltIdx0 = Idx0 < SrcNumElts ? Idx0 : Idx0 - SrcNumElts;
4962 int EltIdx1 = Idx1 < SrcNumElts ? Idx1 : Idx1 - SrcNumElts;
4963
4964 SDValue Vec0 = SVN->getOperand(VecIdx0);
4965 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
4966 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32));
4967
4968 SDValue Vec1 = SVN->getOperand(VecIdx1);
4969 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
4970 Vec1, DAG.getConstant(EltIdx1, SL, MVT::i32));
4971 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 }));
4972 }
4973 }
4974
4975 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces);
4976}
4977
4978SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
4979 SelectionDAG &DAG) const {
4980 SDLoc SL(Op);
4981 EVT VT = Op.getValueType();
4982
4983 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
4984 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2);
4985
4986 // Turn into pair of packed build_vectors.
4987 // TODO: Special case for constants that can be materialized with s_mov_b64.
4988 SDValue Lo = DAG.getBuildVector(HalfVT, SL,
4989 { Op.getOperand(0), Op.getOperand(1) });
4990 SDValue Hi = DAG.getBuildVector(HalfVT, SL,
4991 { Op.getOperand(2), Op.getOperand(3) });
4992
4993 SDValue CastLo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Lo);
4994 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Hi);
4995
4996 SDValue Blend = DAG.getBuildVector(MVT::v2i32, SL, { CastLo, CastHi });
4997 return DAG.getNode(ISD::BITCAST, SL, VT, Blend);
4998 }
4999
5000 assert(VT == MVT::v2f16 || VT == MVT::v2i16)((VT == MVT::v2f16 || VT == MVT::v2i16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v2f16 || VT == MVT::v2i16"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5000, __PRETTY_FUNCTION__))
;
5001 assert(!Subtarget->hasVOP3PInsts() && "this should be legal")((!Subtarget->hasVOP3PInsts() && "this should be legal"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget->hasVOP3PInsts() && \"this should be legal\""
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5001, __PRETTY_FUNCTION__))
;
5002
5003 SDValue Lo = Op.getOperand(0);
5004 SDValue Hi = Op.getOperand(1);
5005
5006 // Avoid adding defined bits with the zero_extend.
5007 if (Hi.isUndef()) {
5008 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
5009 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo);
5010 return DAG.getNode(ISD::BITCAST, SL, VT, ExtLo);
5011 }
5012
5013 Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Hi);
5014 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi);
5015
5016 SDValue ShlHi = DAG.getNode(ISD::SHL, SL, MVT::i32, Hi,
5017 DAG.getConstant(16, SL, MVT::i32));
5018 if (Lo.isUndef())
5019 return DAG.getNode(ISD::BITCAST, SL, VT, ShlHi);
5020
5021 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
5022 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);
5023
5024 SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi);
5025 return DAG.getNode(ISD::BITCAST, SL, VT, Or);
5026}
5027
5028bool
5029SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5030 // We can fold offsets for anything that doesn't require a GOT relocation.
5031 return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
5032 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
5033 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
5034 !shouldEmitGOTReloc(GA->getGlobal());
5035}
5036
5037static SDValue
5038buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
5039 const SDLoc &DL, unsigned Offset, EVT PtrVT,
5040 unsigned GAFlags = SIInstrInfo::MO_NONE) {
5041 // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
5042 // lowered to the following code sequence:
5043 //
5044 // For constant address space:
5045 // s_getpc_b64 s[0:1]
5046 // s_add_u32 s0, s0, $symbol
5047 // s_addc_u32 s1, s1, 0
5048 //
5049 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5050 // a fixup or relocation is emitted to replace $symbol with a literal
5051 // constant, which is a pc-relative offset from the encoding of the $symbol
5052 // operand to the global variable.
5053 //
5054 // For global address space:
5055 // s_getpc_b64 s[0:1]
5056 // s_add_u32 s0, s0, $symbol@{gotpc}rel32@lo
5057 // s_addc_u32 s1, s1, $symbol@{gotpc}rel32@hi
5058 //
5059 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5060 // fixups or relocations are emitted to replace $symbol@*@lo and
5061 // $symbol@*@hi with lower 32 bits and higher 32 bits of a literal constant,
5062 // which is a 64-bit pc-relative offset from the encoding of the $symbol
5063 // operand to the global variable.
5064 //
5065 // What we want here is an offset from the value returned by s_getpc
5066 // (which is the address of the s_add_u32 instruction) to the global
5067 // variable, but since the encoding of $symbol starts 4 bytes after the start
5068 // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
5069 // small. This requires us to add 4 to the global variable offset in order to
5070 // compute the correct address.
5071 SDValue PtrLo =
5072 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags);
5073 SDValue PtrHi;
5074 if (GAFlags == SIInstrInfo::MO_NONE) {
5075 PtrHi = DAG.getTargetConstant(0, DL, MVT::i32);
5076 } else {
5077 PtrHi =
5078 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags + 1);
5079 }
5080 return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, PtrLo, PtrHi);
5081}
5082
5083SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
5084 SDValue Op,
5085 SelectionDAG &DAG) const {
5086 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
5087 const GlobalValue *GV = GSD->getGlobal();
5088 if ((GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
5089 (!GV->hasExternalLinkage() ||
5090 getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA ||
5091 getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL)) ||
5092 GSD->getAddressSpace() == AMDGPUAS::REGION_ADDRESS ||
5093 GSD->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS)
5094 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
5095
5096 SDLoc DL(GSD);
5097 EVT PtrVT = Op.getValueType();
5098
5099 if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
5100 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, GSD->getOffset(),
5101 SIInstrInfo::MO_ABS32_LO);
5102 return DAG.getNode(AMDGPUISD::LDS, DL, MVT::i32, GA);
5103 }
5104
5105 if (shouldEmitFixup(GV))
5106 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
5107 else if (shouldEmitPCReloc(GV))
5108 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
5109 SIInstrInfo::MO_REL32);
5110
5111 SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
5112 SIInstrInfo::MO_GOTPCREL32);
5113
5114 Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
5115 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
5116 const DataLayout &DataLayout = DAG.getDataLayout();
5117 unsigned Align = DataLayout.getABITypeAlignment(PtrTy);
5118 MachinePointerInfo PtrInfo
5119 = MachinePointerInfo::getGOT(DAG.getMachineFunction());
5120
5121 return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Align,
5122 MachineMemOperand::MODereferenceable |
5123 MachineMemOperand::MOInvariant);
5124}
5125
5126SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
5127 const SDLoc &DL, SDValue V) const {
5128 // We can't use S_MOV_B32 directly, because there is no way to specify m0 as
5129 // the destination register.
5130 //
5131 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
5132 // so we will end up with redundant moves to m0.
5133 //
5134 // We use a pseudo to ensure we emit s_mov_b32 with m0 as the direct result.
5135
5136 // A Null SDValue creates a glue result.
5137 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue,
5138 V, Chain);
5139 return SDValue(M0, 0);
5140}
5141
5142SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
5143 SDValue Op,
5144 MVT VT,
5145 unsigned Offset) const {
5146 SDLoc SL(Op);
5147 SDValue Param = lowerKernargMemParameter(DAG, MVT::i32, MVT::i32, SL,
5148 DAG.getEntryNode(), Offset, 4, false);
5149 // The local size values will have the hi 16-bits as zero.
5150 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
5151 DAG.getValueType(VT));
5152}
5153
5154static SDValue emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5155 EVT VT) {
5156 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5157 "non-hsa intrinsic with hsa target",
5158 DL.getDebugLoc());
5159 DAG.getContext()->diagnose(BadIntrin);
5160 return DAG.getUNDEF(VT);
5161}
5162
5163static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5164 EVT VT) {
5165 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5166 "intrinsic not supported on subtarget",
5167 DL.getDebugLoc());
5168 DAG.getContext()->diagnose(BadIntrin);
5169 return DAG.getUNDEF(VT);
5170}
5171
5172static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
5173 ArrayRef<SDValue> Elts) {
5174 assert(!Elts.empty())((!Elts.empty()) ? static_cast<void> (0) : __assert_fail
("!Elts.empty()", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5174, __PRETTY_FUNCTION__))
;
5175 MVT Type;
5176 unsigned NumElts;
5177
5178 if (Elts.size() == 1) {
5179 Type = MVT::f32;
5180 NumElts = 1;
5181 } else if (Elts.size() == 2) {
5182 Type = MVT::v2f32;
5183 NumElts = 2;
5184 } else if (Elts.size() <= 4) {
5185 Type = MVT::v4f32;
5186 NumElts = 4;
5187 } else if (Elts.size() <= 8) {
5188 Type = MVT::v8f32;
5189 NumElts = 8;
5190 } else {
5191 assert(Elts.size() <= 16)((Elts.size() <= 16) ? static_cast<void> (0) : __assert_fail
("Elts.size() <= 16", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5191, __PRETTY_FUNCTION__))
;
5192 Type = MVT::v16f32;
5193 NumElts = 16;
5194 }
5195
5196 SmallVector<SDValue, 16> VecElts(NumElts);
5197 for (unsigned i = 0; i < Elts.size(); ++i) {
5198 SDValue Elt = Elts[i];
5199 if (Elt.getValueType() != MVT::f32)
5200 Elt = DAG.getBitcast(MVT::f32, Elt);
5201 VecElts[i] = Elt;
5202 }
5203 for (unsigned i = Elts.size(); i < NumElts; ++i)
5204 VecElts[i] = DAG.getUNDEF(MVT::f32);
5205
5206 if (NumElts == 1)
5207 return VecElts[0];
5208 return DAG.getBuildVector(Type, DL, VecElts);
5209}
5210
5211static bool parseCachePolicy(SDValue CachePolicy, SelectionDAG &DAG,
5212 SDValue *GLC, SDValue *SLC, SDValue *DLC) {
5213 auto CachePolicyConst = cast<ConstantSDNode>(CachePolicy.getNode());
5214
5215 uint64_t Value = CachePolicyConst->getZExtValue();
5216 SDLoc DL(CachePolicy);
5217 if (GLC) {
5218 *GLC = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
5219 Value &= ~(uint64_t)0x1;
5220 }
5221 if (SLC) {
5222 *SLC = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
5223 Value &= ~(uint64_t)0x2;
5224 }
5225 if (DLC) {
5226 *DLC = DAG.getTargetConstant((Value & 0x4) ? 1 : 0, DL, MVT::i32);
5227 Value &= ~(uint64_t)0x4;
5228 }
5229
5230 return Value == 0;
5231}
5232
5233// Re-construct the required return value for a image load intrinsic.
5234// This is more complicated due to the optional use TexFailCtrl which means the required
5235// return type is an aggregate
5236static SDValue constructRetValue(SelectionDAG &DAG,
5237 MachineSDNode *Result,
5238 ArrayRef<EVT> ResultTypes,
5239 bool IsTexFail, bool Unpacked, bool IsD16,
5240 int DMaskPop, int NumVDataDwords,
5241 const SDLoc &DL, LLVMContext &Context) {
5242 // Determine the required return type. This is the same regardless of IsTexFail flag
5243 EVT ReqRetVT = ResultTypes[0];
5244 EVT ReqRetEltVT = ReqRetVT.isVector() ? ReqRetVT.getVectorElementType() : ReqRetVT;
5245 int ReqRetNumElts = ReqRetVT.isVector() ? ReqRetVT.getVectorNumElements() : 1;
5246 EVT AdjEltVT = Unpacked && IsD16 ? MVT::i32 : ReqRetEltVT;
5247 EVT AdjVT = Unpacked ? ReqRetNumElts > 1 ? EVT::getVectorVT(Context, AdjEltVT, ReqRetNumElts)
5248 : AdjEltVT
5249 : ReqRetVT;
5250
5251 // Extract data part of the result
5252 // Bitcast the result to the same type as the required return type
5253 int NumElts;
5254 if (IsD16 && !Unpacked)
5255 NumElts = NumVDataDwords << 1;
5256 else
5257 NumElts = NumVDataDwords;
5258
5259 EVT CastVT = NumElts > 1 ? EVT::getVectorVT(Context, AdjEltVT, NumElts)
5260 : AdjEltVT;
5261
5262 // Special case for v6f16. Rather than add support for this, use v3i32 to
5263 // extract the data elements
5264 bool V6F16Special = false;
5265 if (NumElts == 6) {
5266 CastVT = EVT::getVectorVT(Context, MVT::i32, NumElts / 2);
5267 DMaskPop >>= 1;
5268 ReqRetNumElts >>= 1;
5269 V6F16Special = true;
5270 AdjVT = MVT::v2i32;
5271 }
5272
5273 SDValue N = SDValue(Result, 0);
5274 SDValue CastRes = DAG.getNode(ISD::BITCAST, DL, CastVT, N);
5275
5276 // Iterate over the result
5277 SmallVector<SDValue, 4> BVElts;
5278
5279 if (CastVT.isVector()) {
5280 DAG.ExtractVectorElements(CastRes, BVElts, 0, DMaskPop);
5281 } else {
5282 BVElts.push_back(CastRes);
5283 }
5284 int ExtraElts = ReqRetNumElts - DMaskPop;
5285 while(ExtraElts--)
5286 BVElts.push_back(DAG.getUNDEF(AdjEltVT));
5287
5288 SDValue PreTFCRes;
5289 if (ReqRetNumElts > 1) {
5290 SDValue NewVec = DAG.getBuildVector(AdjVT, DL, BVElts);
5291 if (IsD16 && Unpacked)
5292 PreTFCRes = adjustLoadValueTypeImpl(NewVec, ReqRetVT, DL, DAG, Unpacked);
5293 else
5294 PreTFCRes = NewVec;
5295 } else {
5296 PreTFCRes = BVElts[0];
5297 }
5298
5299 if (V6F16Special)
5300 PreTFCRes = DAG.getNode(ISD::BITCAST, DL, MVT::v4f16, PreTFCRes);
5301
5302 if (!IsTexFail) {
5303 if (Result->getNumValues() > 1)
5304 return DAG.getMergeValues({PreTFCRes, SDValue(Result, 1)}, DL);
5305 else
5306 return PreTFCRes;
5307 }
5308
5309 // Extract the TexFail result and insert into aggregate return
5310 SmallVector<SDValue, 1> TFCElt;
5311 DAG.ExtractVectorElements(N, TFCElt, DMaskPop, 1);
5312 SDValue TFCRes = DAG.getNode(ISD::BITCAST, DL, ResultTypes[1], TFCElt[0]);
5313 return DAG.getMergeValues({PreTFCRes, TFCRes, SDValue(Result, 1)}, DL);
5314}
5315
5316static bool parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE,
5317 SDValue *LWE, bool &IsTexFail) {
5318 auto TexFailCtrlConst = cast<ConstantSDNode>(TexFailCtrl.getNode());
5319
5320 uint64_t Value = TexFailCtrlConst->getZExtValue();
5321 if (Value) {
5322 IsTexFail = true;
5323 }
5324
5325 SDLoc DL(TexFailCtrlConst);
5326 *TFE = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
5327 Value &= ~(uint64_t)0x1;
5328 *LWE = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
5329 Value &= ~(uint64_t)0x2;
5330
5331 return Value == 0;
5332}
5333
5334SDValue SITargetLowering::lowerImage(SDValue Op,
5335 const AMDGPU::ImageDimIntrinsicInfo *Intr,
5336 SelectionDAG &DAG) const {
5337 SDLoc DL(Op);
5338 MachineFunction &MF = DAG.getMachineFunction();
5339 const GCNSubtarget* ST = &MF.getSubtarget<GCNSubtarget>();
5340 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
5341 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
5342 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfo(Intr->Dim);
5343 const AMDGPU::MIMGLZMappingInfo *LZMappingInfo =
5344 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
5345 const AMDGPU::MIMGMIPMappingInfo *MIPMappingInfo =
5346 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
5347 unsigned IntrOpcode = Intr->BaseOpcode;
5348 bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10;
5349
5350 SmallVector<EVT, 3> ResultTypes(Op->value_begin(), Op->value_end());
5351 SmallVector<EVT, 3> OrigResultTypes(Op->value_begin(), Op->value_end());
5352 bool IsD16 = false;
5353 bool IsA16 = false;
5354 SDValue VData;
5355 int NumVDataDwords;
5356 bool AdjustRetType = false;
5357
5358 unsigned AddrIdx; // Index of first address argument
5359 unsigned DMask;
5360 unsigned DMaskLanes = 0;
5361
5362 if (BaseOpcode->Atomic) {
5363 VData = Op.getOperand(2);
5364
5365 bool Is64Bit = VData.getValueType() == MVT::i64;
5366 if (BaseOpcode->AtomicX2) {
5367 SDValue VData2 = Op.getOperand(3);
5368 VData = DAG.getBuildVector(Is64Bit ? MVT::v2i64 : MVT::v2i32, DL,
5369 {VData, VData2});
5370 if (Is64Bit)
5371 VData = DAG.getBitcast(MVT::v4i32, VData);
5372
5373 ResultTypes[0] = Is64Bit ? MVT::v2i64 : MVT::v2i32;
5374 DMask = Is64Bit ? 0xf : 0x3;
5375 NumVDataDwords = Is64Bit ? 4 : 2;
5376 AddrIdx = 4;
5377 } else {
5378 DMask = Is64Bit ? 0x3 : 0x1;
5379 NumVDataDwords = Is64Bit ? 2 : 1;
5380 AddrIdx = 3;
5381 }
5382 } else {
5383 unsigned DMaskIdx = BaseOpcode->Store ? 3 : isa<MemSDNode>(Op) ? 2 : 1;
5384 auto DMaskConst = cast<ConstantSDNode>(Op.getOperand(DMaskIdx));
5385 DMask = DMaskConst->getZExtValue();
5386 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask);
5387
5388 if (BaseOpcode->Store) {
5389 VData = Op.getOperand(2);
5390
5391 MVT StoreVT = VData.getSimpleValueType();
5392 if (StoreVT.getScalarType() == MVT::f16) {
5393 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
5394 return Op; // D16 is unsupported for this instruction
5395
5396 IsD16 = true;
5397 VData = handleD16VData(VData, DAG);
5398 }
5399
5400 NumVDataDwords = (VData.getValueType().getSizeInBits() + 31) / 32;
5401 } else {
5402 // Work out the num dwords based on the dmask popcount and underlying type
5403 // and whether packing is supported.
5404 MVT LoadVT = ResultTypes[0].getSimpleVT();
5405 if (LoadVT.getScalarType() == MVT::f16) {
5406 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
5407 return Op; // D16 is unsupported for this instruction
5408
5409 IsD16 = true;
5410 }
5411
5412 // Confirm that the return type is large enough for the dmask specified
5413 if ((LoadVT.isVector() && LoadVT.getVectorNumElements() < DMaskLanes) ||
5414 (!LoadVT.isVector() && DMaskLanes > 1))
5415 return Op;
5416
5417 if (IsD16 && !Subtarget->hasUnpackedD16VMem())
5418 NumVDataDwords = (DMaskLanes + 1) / 2;
5419 else
5420 NumVDataDwords = DMaskLanes;
5421
5422 AdjustRetType = true;
5423 }
5424
5425 AddrIdx = DMaskIdx + 1;
5426 }
5427
5428 unsigned NumGradients = BaseOpcode->Gradients ? DimInfo->NumGradients : 0;
5429 unsigned NumCoords = BaseOpcode->Coordinates ? DimInfo->NumCoords : 0;
5430 unsigned NumLCM = BaseOpcode->LodOrClampOrMip ? 1 : 0;
5431 unsigned NumVAddrs = BaseOpcode->NumExtraArgs + NumGradients +
5432 NumCoords + NumLCM;
5433 unsigned NumMIVAddrs = NumVAddrs;
5434
5435 SmallVector<SDValue, 4> VAddrs;
5436
5437 // Optimize _L to _LZ when _L is zero
5438 if (LZMappingInfo) {
5439 if (auto ConstantLod =
5440 dyn_cast<ConstantFPSDNode>(Op.getOperand(AddrIdx+NumVAddrs-1))) {
5441 if (ConstantLod->isZero() || ConstantLod->isNegative()) {
5442 IntrOpcode = LZMappingInfo->LZ; // set new opcode to _lz variant of _l
5443 NumMIVAddrs--; // remove 'lod'
5444 }
5445 }
5446 }
5447
5448 // Optimize _mip away, when 'lod' is zero
5449 if (MIPMappingInfo) {
5450 if (auto ConstantLod =
5451 dyn_cast<ConstantSDNode>(Op.getOperand(AddrIdx+NumVAddrs-1))) {
5452 if (ConstantLod->isNullValue()) {
5453 IntrOpcode = MIPMappingInfo->NONMIP; // set new opcode to variant without _mip
5454 NumMIVAddrs--; // remove 'lod'
5455 }
5456 }
5457 }
5458
5459 // Check for 16 bit addresses and pack if true.
5460 unsigned DimIdx = AddrIdx + BaseOpcode->NumExtraArgs;
5461 MVT VAddrVT = Op.getOperand(DimIdx).getSimpleValueType();
5462 const MVT VAddrScalarVT = VAddrVT.getScalarType();
5463 if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16)) &&
5464 ST->hasFeature(AMDGPU::FeatureR128A16)) {
5465 IsA16 = true;
5466 const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
5467 for (unsigned i = AddrIdx; i < (AddrIdx + NumMIVAddrs); ++i) {
5468 SDValue AddrLo, AddrHi;
5469 // Push back extra arguments.
5470 if (i < DimIdx) {
5471 AddrLo = Op.getOperand(i);
5472 } else {
5473 AddrLo = Op.getOperand(i);
5474 // Dz/dh, dz/dv and the last odd coord are packed with undef. Also,
5475 // in 1D, derivatives dx/dh and dx/dv are packed with undef.
5476 if (((i + 1) >= (AddrIdx + NumMIVAddrs)) ||
5477 ((NumGradients / 2) % 2 == 1 &&
5478 (i == DimIdx + (NumGradients / 2) - 1 ||
5479 i == DimIdx + NumGradients - 1))) {
5480 AddrHi = DAG.getUNDEF(MVT::f16);
5481 } else {
5482 AddrHi = Op.getOperand(i + 1);
5483 i++;
5484 }
5485 AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorVT,
5486 {AddrLo, AddrHi});
5487 AddrLo = DAG.getBitcast(MVT::i32, AddrLo);
5488 }
5489 VAddrs.push_back(AddrLo);
5490 }
5491 } else {
5492 for (unsigned i = 0; i < NumMIVAddrs; ++i)
5493 VAddrs.push_back(Op.getOperand(AddrIdx + i));
5494 }
5495
5496 // If the register allocator cannot place the address registers contiguously
5497 // without introducing moves, then using the non-sequential address encoding
5498 // is always preferable, since it saves VALU instructions and is usually a
5499 // wash in terms of code size or even better.
5500 //
5501 // However, we currently have no way of hinting to the register allocator that
5502 // MIMG addresses should be placed contiguously when it is possible to do so,
5503 // so force non-NSA for the common 2-address case as a heuristic.
5504 //
5505 // SIShrinkInstructions will convert NSA encodings to non-NSA after register
5506 // allocation when possible.
5507 bool UseNSA =
5508 ST->hasFeature(AMDGPU::FeatureNSAEncoding) && VAddrs.size() >= 3;
5509 SDValue VAddr;
5510 if (!UseNSA)
5511 VAddr = getBuildDwordsVector(DAG, DL, VAddrs);
5512
5513 SDValue True = DAG.getTargetConstant(1, DL, MVT::i1);
5514 SDValue False = DAG.getTargetConstant(0, DL, MVT::i1);
5515 unsigned CtrlIdx; // Index of texfailctrl argument
5516 SDValue Unorm;
5517 if (!BaseOpcode->Sampler) {
5518 Unorm = True;
5519 CtrlIdx = AddrIdx + NumVAddrs + 1;
5520 } else {
5521 auto UnormConst =
5522 cast<ConstantSDNode>(Op.getOperand(AddrIdx + NumVAddrs + 2));
5523
5524 Unorm = UnormConst->getZExtValue() ? True : False;
5525 CtrlIdx = AddrIdx + NumVAddrs + 3;
5526 }
5527
5528 SDValue TFE;
5529 SDValue LWE;
5530 SDValue TexFail = Op.getOperand(CtrlIdx);
5531 bool IsTexFail = false;
5532 if (!parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail))
5533 return Op;
5534
5535 if (IsTexFail) {
5536 if (!DMaskLanes) {
5537 // Expecting to get an error flag since TFC is on - and dmask is 0
5538 // Force dmask to be at least 1 otherwise the instruction will fail
5539 DMask = 0x1;
5540 DMaskLanes = 1;
5541 NumVDataDwords = 1;
5542 }
5543 NumVDataDwords += 1;
5544 AdjustRetType = true;
5545 }
5546
5547 // Has something earlier tagged that the return type needs adjusting
5548 // This happens if the instruction is a load or has set TexFailCtrl flags
5549 if (AdjustRetType) {
5550 // NumVDataDwords reflects the true number of dwords required in the return type
5551 if (DMaskLanes == 0 && !BaseOpcode->Store) {
5552 // This is a no-op load. This can be eliminated
5553 SDValue Undef = DAG.getUNDEF(Op.getValueType());
5554 if (isa<MemSDNode>(Op))
5555 return DAG.getMergeValues({Undef, Op.getOperand(0)}, DL);
5556 return Undef;
5557 }
5558
5559 EVT NewVT = NumVDataDwords > 1 ?
5560 EVT::getVectorVT(*DAG.getContext(), MVT::f32, NumVDataDwords)
5561 : MVT::f32;
5562
5563 ResultTypes[0] = NewVT;
5564 if (ResultTypes.size() == 3) {
5565 // Original result was aggregate type used for TexFailCtrl results
5566 // The actual instruction returns as a vector type which has now been
5567 // created. Remove the aggregate result.
5568 ResultTypes.erase(&ResultTypes[1]);
5569 }
5570 }
5571
5572 SDValue GLC;
5573 SDValue SLC;
5574 SDValue DLC;
5575 if (BaseOpcode->Atomic) {
5576 GLC = True; // TODO no-return optimization
5577 if (!parseCachePolicy(Op.getOperand(CtrlIdx + 1), DAG, nullptr, &SLC,
5578 IsGFX10 ? &DLC : nullptr))
5579 return Op;
5580 } else {
5581 if (!parseCachePolicy(Op.getOperand(CtrlIdx + 1), DAG, &GLC, &SLC,
5582 IsGFX10 ? &DLC : nullptr))
5583 return Op;
5584 }
5585
5586 SmallVector<SDValue, 26> Ops;
5587 if (BaseOpcode->Store || BaseOpcode->Atomic)
5588 Ops.push_back(VData); // vdata
5589 if (UseNSA) {
5590 for (const SDValue &Addr : VAddrs)
5591 Ops.push_back(Addr);
5592 } else {
5593 Ops.push_back(VAddr);
5594 }
5595 Ops.push_back(Op.getOperand(AddrIdx + NumVAddrs)); // rsrc
5596 if (BaseOpcode->Sampler)
5597 Ops.push_back(Op.getOperand(AddrIdx + NumVAddrs + 1)); // sampler
5598 Ops.push_back(DAG.getTargetConstant(DMask, DL, MVT::i32));
5599 if (IsGFX10)
5600 Ops.push_back(DAG.getTargetConstant(DimInfo->Encoding, DL, MVT::i32));
5601 Ops.push_back(Unorm);
5602 if (IsGFX10)
5603 Ops.push_back(DLC);
5604 Ops.push_back(GLC);
5605 Ops.push_back(SLC);
5606 Ops.push_back(IsA16 && // a16 or r128
5607 ST->hasFeature(AMDGPU::FeatureR128A16) ? True : False);
5608 Ops.push_back(TFE); // tfe
5609 Ops.push_back(LWE); // lwe
5610 if (!IsGFX10)
5611 Ops.push_back(DimInfo->DA ? True : False);
5612 if (BaseOpcode->HasD16)
5613 Ops.push_back(IsD16 ? True : False);
5614 if (isa<MemSDNode>(Op))
5615 Ops.push_back(Op.getOperand(0)); // chain
5616
5617 int NumVAddrDwords =
5618 UseNSA ? VAddrs.size() : VAddr.getValueType().getSizeInBits() / 32;
5619 int Opcode = -1;
5620
5621 if (IsGFX10) {
5622 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode,
5623 UseNSA ? AMDGPU::MIMGEncGfx10NSA
5624 : AMDGPU::MIMGEncGfx10Default,
5625 NumVDataDwords, NumVAddrDwords);
5626 } else {
5627 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5628 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx8,
5629 NumVDataDwords, NumVAddrDwords);
5630 if (Opcode == -1)
5631 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx6,
5632 NumVDataDwords, NumVAddrDwords);
5633 }
5634 assert(Opcode != -1)((Opcode != -1) ? static_cast<void> (0) : __assert_fail
("Opcode != -1", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5634, __PRETTY_FUNCTION__))
;
5635
5636 MachineSDNode *NewNode = DAG.getMachineNode(Opcode, DL, ResultTypes, Ops);
5637 if (auto MemOp = dyn_cast<MemSDNode>(Op)) {
5638 MachineMemOperand *MemRef = MemOp->getMemOperand();
5639 DAG.setNodeMemRefs(NewNode, {MemRef});
5640 }
5641
5642 if (BaseOpcode->AtomicX2) {
5643 SmallVector<SDValue, 1> Elt;
5644 DAG.ExtractVectorElements(SDValue(NewNode, 0), Elt, 0, 1);
5645 return DAG.getMergeValues({Elt[0], SDValue(NewNode, 1)}, DL);
5646 } else if (!BaseOpcode->Store) {
5647 return constructRetValue(DAG, NewNode,
5648 OrigResultTypes, IsTexFail,
5649 Subtarget->hasUnpackedD16VMem(), IsD16,
5650 DMaskLanes, NumVDataDwords, DL,
5651 *DAG.getContext());
5652 }
5653
5654 return SDValue(NewNode, 0);
5655}
5656
5657SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc,
5658 SDValue Offset, SDValue GLC, SDValue DLC,
5659 SelectionDAG &DAG) const {
5660 MachineFunction &MF = DAG.getMachineFunction();
5661
5662 const DataLayout &DataLayout = DAG.getDataLayout();
5663 unsigned Align =
5664 DataLayout.getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5665
5666 MachineMemOperand *MMO = MF.getMachineMemOperand(
5667 MachinePointerInfo(),
5668 MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
5669 MachineMemOperand::MOInvariant,
5670 VT.getStoreSize(), Align);
5671
5672 if (!Offset->isDivergent()) {
5673 SDValue Ops[] = {
5674 Rsrc,
5675 Offset, // Offset
5676 GLC,
5677 DLC,
5678 };
5679
5680 // Widen vec3 load to vec4.
5681 if (VT.isVector() && VT.getVectorNumElements() == 3) {
5682 EVT WidenedVT =
5683 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4);
5684 auto WidenedOp = DAG.getMemIntrinsicNode(
5685 AMDGPUISD::SBUFFER_LOAD, DL, DAG.getVTList(WidenedVT), Ops, WidenedVT,
5686 MF.getMachineMemOperand(MMO, 0, WidenedVT.getStoreSize()));
5687 auto Subvector = DAG.getNode(
5688 ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp,
5689 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout())));
5690 return Subvector;
5691 }
5692
5693 return DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD, DL,
5694 DAG.getVTList(VT), Ops, VT, MMO);
5695 }
5696
5697 // We have a divergent offset. Emit a MUBUF buffer load instead. We can
5698 // assume that the buffer is unswizzled.
5699 SmallVector<SDValue, 4> Loads;
5700 unsigned NumLoads = 1;
5701 MVT LoadVT = VT.getSimpleVT();
5702 unsigned NumElts = LoadVT.isVector() ? LoadVT.getVectorNumElements() : 1;
5703 assert((LoadVT.getScalarType() == MVT::i32 ||(((LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType
() == MVT::f32)) ? static_cast<void> (0) : __assert_fail
("(LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType() == MVT::f32)"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5704, __PRETTY_FUNCTION__))
5704 LoadVT.getScalarType() == MVT::f32))(((LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType
() == MVT::f32)) ? static_cast<void> (0) : __assert_fail
("(LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType() == MVT::f32)"
, "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5704, __PRETTY_FUNCTION__))
;
5705
5706 if (NumElts == 8 || NumElts == 16) {
5707 NumLoads = NumElts / 4;
5708 LoadVT = MVT::v4i32;
5709 }
5710
5711 SDVTList VTList = DAG.getVTList({LoadVT, MVT::Glue});
5712 unsigned CachePolicy = cast<ConstantSDNode>(GLC)->getZExtValue();
5713 SDValue Ops[] = {
5714 DAG.getEntryNode(), // Chain
5715 Rsrc, // rsrc
5716 DAG.getConstant(0, DL, MVT::i32), // vindex
5717 {}, // voffset
5718 {}, // soffset
5719 {}, // offset
5720 DAG.getTargetConstant(CachePolicy, DL, MVT::i32), // cachepolicy
5721 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
5722 };
5723
5724 // Use the alignment to ensure that the required offsets will fit into the
5725 // immediate offsets.
5726 setBufferOffsets(Offset, DAG, &Ops[3], NumLoads > 1 ? 16 * NumLoads : 4);
5727
5728 uint64_t InstOffset = cast<ConstantSDNode>(Ops[5])->getZExtValue();
5729 for (unsigned i = 0; i < NumLoads; ++i) {
5730 Ops[5] = DAG.getTargetConstant(InstOffset + 16 * i, DL, MVT::i32);
5731 Loads.push_back(getMemIntrinsicNode(AMDGPUISD::BUFFER_LOAD, DL, VTList, Ops,
5732 LoadVT, MMO, DAG));
5733 }
5734
5735 if (VT == MVT::v8i32 || VT == MVT::v16i32)
5736 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads);
5737
5738 return Loads[0];
5739}
5740
5741SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5742 SelectionDAG &DAG) const {
5743 MachineFunction &MF = DAG.getMachineFunction();
5744 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
5745
5746 EVT VT = Op.getValueType();
5747 SDLoc DL(Op);
5748 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5749
5750 // TODO: Should this propagate fast-math-flags?
5751
5752 switch (IntrinsicID) {
5753 case Intrinsic::amdgcn_implicit_buffer_ptr: {
5754 if (getSubtarget()->isAmdHsaOrMesa(MF.getFunction()))
5755 return emitNonHSAIntrinsicError(DAG, DL, VT);
5756 return getPreloadedValue(DAG, *MFI, VT,
5757 AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR);
5758 }
5759 case Intrinsic::amdgcn_dispatch_ptr:
5760 case Intrinsic::amdgcn_queue_ptr: {
5761 if (!Subtarget->isAmdHsaOrMesa(MF.getFunction())) {
5762 DiagnosticInfoUnsupported BadIntrin(
5763 MF.getFunction(), "unsupported hsa intrinsic without hsa target",
5764 DL.getDebugLoc());
5765 DAG.getContext()->diagnose(BadIntrin);
5766 return DAG.getUNDEF(VT);
5767 }
5768
5769 auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ?
5770 AMDGPUFunctionArgInfo::DISPATCH_PTR : AMDGPUFunctionArgInfo::QUEUE_PTR;
5771 return getPreloadedValue(DAG, *MFI, VT, RegID);
5772 }
5773 case Intrinsic::amdgcn_implicitarg_ptr: {
5774 if (MFI->isEntryFunction())
5775 return getImplicitArgPtr(DAG, DL);
5776 return getPreloadedValue(DAG, *MFI, VT,
5777 AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR);
5778 }
5779 case Intrinsic::amdgcn_kernarg_segment_ptr: {
5780 return getPreloadedValue(DAG, *MFI, VT,
5781 AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
5782 }
5783 case Intrinsic::amdgcn_dispatch_id: {
5784 return getPreloadedValue(DAG, *MFI, VT, AMDGPUFunctionArgInfo::DISPATCH_ID);
5785 }
5786 case Intrinsic::amdgcn_rcp:
5787 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
5788 case Intrinsic::amdgcn_rsq:
5789 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
5790 case Intrinsic::amdgcn_rsq_legacy:
5791 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5792 return emitRemovedIntrinsicError(DAG, DL, VT);
5793
5794 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
5795 case Intrinsic::amdgcn_rcp_legacy:
5796 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5797 return emitRemovedIntrinsicError(DAG, DL, VT);
5798 return DAG.getNode(AMDGPUISD::RCP_LEGACY, DL, VT, Op.getOperand(1));
5799 case Intrinsic::amdgcn_rsq_clamp: {
5800 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
5801 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
5802
5803 Type *Type = VT.getTypeForEVT(*DAG.getContext());
5804 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
5805 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
5806
5807 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
5808 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
5809 DAG.getConstantFP(Max, DL, VT));
5810 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
5811 DAG.getConstantFP(Min, DL, VT));
5812 }
5813 case Intrinsic::r600_read_ngroups_x:
5814 if (Subtarget->isAmdHsaOS())
5815 return emitNonHSAIntrinsicError(DAG, DL, VT);
5816
5817 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5818 SI::KernelInputOffsets::NGROUPS_X, 4, false);
5819 case Intrinsic::r600_read_ngroups_y:
5820 if (Subtarget->isAmdHsaOS())
5821 return emitNonHSAIntrinsicError(DAG, DL, VT);
5822
5823 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5824 SI::KernelInputOffsets::NGROUPS_Y, 4, false);
5825 case Intrinsic::r600_read_ngroups_z:
5826 if (Subtarget->isAmdHsaOS())
5827 return emitNonHSAIntrinsicError(DAG, DL, VT);
5828
5829 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5830 SI::KernelInputOffsets::NGROUPS_Z, 4, false);
5831 case Intrinsic::r600_read_global_size_x:
5832 if (Subtarget->isAmdHsaOS())
5833 return emitNonHSAIntrinsicError(DAG, DL, VT);
5834
5835 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5836 SI::KernelInputOffsets::GLOBAL_SIZE_X, 4, false);
5837 case Intrinsic::r600_read_global_size_y:
5838 if (Subtarget->isAmdHsaOS())
5839 return emitNonHSAIntrinsicError(DAG, DL, VT);
5840
5841 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5842 SI::KernelInputOffsets::GLOBAL_SIZE_Y, 4, false);
5843 case Intrinsic::r600_read_global_size_z:
5844 if (Subtarget->isAmdHsaOS())
5845 return emitNonHSAIntrinsicError(DAG, DL, VT);
5846
5847 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5848 SI::KernelInputOffsets::GLOBAL_SIZE_Z, 4, false);
5849 case Intrinsic::r600_read_local_size_x:
5850 if (Subtarget->isAmdHsaOS())
5851 return emitNonHSAIntrinsicError(DAG, DL, VT);
5852
5853 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5854 SI::KernelInputOffsets::LOCAL_SIZE_X);
5855 case Intrinsic::r600_read_local_size_y:
5856 if (Subtarget->isAmdHsaOS())
5857 return emitNonHSAIntrinsicError(DAG, DL, VT);
5858
5859 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5860 SI::KernelInputOffsets::LOCAL_SIZE_Y);
5861 case Intrinsic::r600_read_local_size_z:
5862 if (Subtarget->isAmdHsaOS())
5863 return emitNonHSAIntrinsicError(DAG, DL, VT);
5864
5865 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5866 SI::KernelInputOffsets::LOCAL_SIZE_Z);
5867 case Intrinsic::amdgcn_workgroup_id_x:
5868 case Intrinsic::r600_read_tgid_x:
5869 return getPreloadedValue(DAG, *MFI, VT,
5870 AMDGPUFunctionArgInfo::WORKGROUP_ID_X);
5871 case Intrinsic::amdgcn_workgroup_id_y:
5872 case Intrinsic::r600_read_tgid_y:
5873 return getPreloadedValue(DAG, *MFI, VT,
5874 AMDGPUFunctionArgInfo::WORKGROUP_ID_Y);
5875 case Intrinsic::amdgcn_workgroup_id_z:
5876 case Intrinsic::r600_read_tgid_z:
5877 return getPreloadedValue(DAG, *MFI, VT,
5878 AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
5879 case Intrinsic::amdgcn_workitem_id_x:
5880 case Intrinsic::r600_read_tidig_x:
5881 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5882 SDLoc(DAG.getEntryNode()),
5883 MFI->getArgInfo().WorkItemIDX);
5884 case Intrinsic::amdgcn_workitem_id_y:
5885 case Intrinsic::r600_read_tidig_y:
5886 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5887 SDLoc(DAG.getEntryNode()),
5888 MFI->getArgInfo().WorkItemIDY);
5889 case Intrinsic::amdgcn_workitem_id_z:
5890 case Intrinsic::r600_read_tidig_z:
5891 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5892 SDLoc(DAG.getEntryNode()),
5893 MFI->getArgInfo().WorkItemIDZ);
5894 case Intrinsic::amdgcn_wavefrontsize:
5895 return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(),
5896 SDLoc(Op), MVT::i32);
5897 case Intrinsic::amdgcn_s_buffer_load: {
5898 bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10;
5899 SDValue GLC;
5900 SDValue DLC = DAG.getTargetConstant(0, DL, MVT::i1);
5901 if (!parseCachePolicy(Op.getOperand(3), DAG, &GLC, nullptr,
5902 IsGFX10 ? &DLC : nullptr))
5903 return Op;
5904 return lowerSBuffer(VT, DL, Op.getOperand(1), Op.getOperand(2), GLC, DLC,
5905 DAG);
5906 }
5907 case Intrinsic::amdgcn_fdiv_fast:
5908 return lowerFDIV_FAST(Op, DAG);
5909 case Intrinsic::amdgcn_interp_p1_f16: {
5910 SDValue ToM0 = DAG.getCopyToReg(DAG.getEntryNode(), DL, AMDGPU::M0,
5911 Op.getOperand(5), SDValue());
5912 if (getSubtarget()->getLDSBankCount() == 16) {
5913 // 16 bank LDS
5914
5915 // FIXME: This implicitly will insert a second CopyToReg to M0.
5916 SDValue S = DAG.getNode(
5917 ISD::INTRINSIC_WO_CHAIN, DL, MVT::f32,
5918 DAG.getTargetConstant(Intrinsic::amdgcn_interp_mov, DL, MVT::i32),
5919 DAG.getConstant(2, DL, MVT::i32), // P0
5920 Op.getOperand(2), // Attrchan
5921 Op.getOperand(3), // Attr
5922 Op.getOperand(5)); // m0
5923
5924 SDValue Ops[] = {
5925 Op.getOperand(1), // Src0
5926 Op.getOperand(2), // Attrchan
5927 Op.getOperand(3), // Attr
5928 DAG.getTargetConstant(0, DL, MVT::i32), // $src0_modifiers
5929 S, // Src2 - holds two f16 values selected by high
5930 DAG.getTargetConstant(0, DL, MVT::i32), // $src2_modifiers
5931 Op.getOperand(4), // high
5932 DAG.getTargetConstant(0, DL, MVT::i1), // $clamp
5933 DAG.getTargetConstant(0, DL, MVT::i32) // $omod
5934 };
5935 return DAG.getNode(AMDGPUISD::INTERP_P1LV_F16, DL, MVT::f32, Ops);
5936 } else {
5937 // 32 bank LDS
5938 SDValue Ops[] = {
5939 Op.getOperand(1), // Src0
5940 Op.getOperand(2), // Attrchan
5941 Op.getOperand(3), // Attr
5942 DAG.getTargetConstant(0, DL, MVT::i32), // $src0_modifiers
5943 Op.getOperand(4), // high
5944 DAG.getTargetConstant(0, DL, MVT::i1), // $clamp
5945 DAG.getTargetConstant(0, DL, MVT::i32), // $omod
5946 ToM0.getValue(1)
5947 };
5948 return DAG.getNode(AMDGPUISD::INTERP_P1LL_F16, DL, MVT::f32, Ops);
5949 }
5950 }
5951 case Intrinsic::amdgcn_sin:
5952 return DAG.getNode(AMDGPUISD::SIN_HW, DL, VT, Op.getOperand(1));
5953
5954 case Intrinsic::amdgcn_cos:
5955 return DAG.getNode(AMDGPUISD::COS_HW, DL, VT, Op.getOperand(1));
5956
5957 case Intrinsic::amdgcn_mul_u24:
5958 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT, Op.getOperand(1), Op.getOperand(2));
5959 case Intrinsic::amdgcn_mul_i24:
5960 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT, Op.getOperand(1), Op.getOperand(2));
5961
5962 case Intrinsic::amdgcn_log_clamp: {
5963 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
5964 return SDValue();
5965
5966 DiagnosticInfoUnsupported BadIntrin(
5967 MF.getFunction(), "intrinsic not supported on subtarget",
5968 DL.getDebugLoc());
5969 DAG.getContext()->diagnose(BadIntrin);
5970 return DAG.getUNDEF(VT);
5971 }
5972 case Intrinsic::amdgcn_ldexp:
5973 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT,
5974 Op.getOperand(1), Op.getOperand(2));
5975
5976 case Intrinsic::amdgcn_fract:
5977 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
5978
5979 case Intrinsic::amdgcn_class:
5980 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
5981 Op.getOperand(1), Op.getOperand(2));
5982 case Intrinsic::amdgcn_div_fmas:
5983 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
5984 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
5985 Op.getOperand(4));
5986
5987 case Intrinsic::amdgcn_div_fixup:
5988 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
5989 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
5990
5991 case Intrinsic::amdgcn_trig_preop:
5992 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
5993 Op.getOperand(1), Op.getOperand(2));
5994 case Intrinsic::amdgcn_div_scale: {
5995 const ConstantSDNode *Param = cast<ConstantSDNode>(Op.getOperand(3));
5996
5997 // Translate to the operands expected by the machine instruction. The
5998 // first parameter must be the same as the first instruction.
5999 SDValue Numerator = Op.getOperand(1);
6000 SDValue Denominator = Op.getOperand(2);
6001
6002 // Note this order is opposite of the machine instruction's operations,
6003 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
6004 // intrinsic has the numerator as the first operand to match a normal
6005 // division operation.
6006
6007 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
6008
6009 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
6010 Denominator, Numerator);
6011 }
6012 case Intrinsic::amdgcn_icmp: {
6013 // There is a Pat that handles this variant, so return it as-is.
6014 if (Op.getOperand(1).getValueType() == MVT::i1 &&
6015 Op.getConstantOperandVal(2) == 0 &&
6016 Op.getConstantOperandVal(3) == ICmpInst::Predicate::ICMP_NE)
6017 return Op;
6018 return lowerICMPIntrinsic(*this, Op.getNode(), DAG);
6019 }
6020 case Intrinsic::amdgcn_fcmp: {
6021 return lowerFCMPIntrinsic(*this, Op.getNode(), DAG);
6022 }
6023 case Intrinsic::amdgcn_fmed3:
6024 return DAG.getNode(AMDGPUISD::FMED3, DL, VT,
6025 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
6026 case Intrinsic::amdgcn_fdot2:
6027 return DAG.getNode(AMDGPUISD::FDOT2, DL, VT,
6028 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
6029 Op.getOperand(4));
6030 case Intrinsic::amdgcn_fmul_legacy:
6031 return DAG.getNode(AMDGPUISD::FMUL_LEGACY, DL, VT,
6032 Op.getOperand(1), Op.getOperand(2));
6033 case Intrinsic::amdgcn_sffbh:
6034 return DAG.getNode(AMDGPUISD::FFBH_I32, DL, VT, Op.getOperand(1));
6035 case Intrinsic::amdgcn_sbfe:
6036 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
6037 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
6038 case Intrinsic::amdgcn_ubfe:
6039 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
6040 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
6041 case Intrinsic::amdgcn_cvt_pkrtz:
6042 case Intrinsic::amdgcn_cvt_pknorm_i16:
6043 case Intrinsic::amdgcn_cvt_pknorm_u16:
6044 case Intrinsic::amdgcn_cvt_pk_i16:
6045 case Intrinsic::amdgcn_cvt_pk_u16: {
6046 // FIXME: Stop adding cast if v2f16/v2i16 are legal.
6047 EVT VT = Op.getValueType();
6048 unsigned Opcode;
6049
6050 if (IntrinsicID == Intrinsic::amdgcn_cvt_pkrtz)
6051 Opcode = AMDGPUISD::CVT_PKRTZ_F16_F32;
6052 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_i16)
6053 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
6054 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_u16)
6055 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
6056 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pk_i16)
6057 Opcode = AMDGPUISD::CVT_PK_I16_I32;
6058 else
6059 Opcode = AMDGPUISD::CVT_PK_U16_U32;
6060
6061 if (isTypeLegal(VT))
6062 return DAG.getNode(Opcode, DL, VT, Op.getOperand(1), Op.getOperand(2));
6063
6064 SDValue Node = DAG.getNode(Opcode, DL, MVT::i32,
6065 Op.getOperand(1), Op.getOperand(2));
6066 return DAG.getNode(ISD::BITCAST, DL, VT, Node);
6067 }
6068 case Intrinsic::amdgcn_fmad_ftz:
6069 return DAG.getNode(AMDGPUISD::FMAD_FTZ, DL, VT, Op.getOperand(1),
6070 Op.getOperand(2), Op.getOperand(3));
6071
6072 case Intrinsic::amdgcn_if_break:
6073 return SDValue(DAG.getMachineNode(AMDGPU::SI_IF_BREAK, DL, VT,
6074 Op->getOperand(1), Op->getOperand(2)), 0);
6075
6076 case Intrinsic::amdgcn_groupstaticsize: {
6077 Triple::OSType OS = getTargetMachine().getTargetTriple().getOS();
6078 if (OS == Triple::AMDHSA || OS == Triple::AMDPAL)
6079 return Op;
6080
6081 const Module *M = MF.getFunction().getParent();
6082 const GlobalValue *GV =
6083 M->getNamedValue(Intrinsic::getName(Intrinsic::amdgcn_groupstaticsize));
6084 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
6085 SIInstrInfo::MO_ABS32_LO);
6086 return {DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, GA), 0};
6087 }
6088 case Intrinsic::amdgcn_is_shared:
6089 case Intrinsic::amdgcn_is_private: {
6090 SDLoc SL(Op);
6091 unsigned AS = (IntrinsicID == Intrinsic::amdgcn_is_shared) ?
6092 AMDGPUAS::LOCAL_ADDRESS : AMDGPUAS::PRIVATE_ADDRESS;
6093 SDValue Aperture = getSegmentAperture(AS, SL, DAG);
6094 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32,
6095 Op.getOperand(1));
6096
6097 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec,
6098 DAG.getConstant(1, SL, MVT::i32));
6099 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ);
6100 }
6101 default:
6102 if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
6103 AMDGPU::getImageDimIntrinsicInfo(IntrinsicID))
6104 return lowerImage(Op, ImageDimIntr, DAG);
6105
6106 return Op;
6107 }
6108}
6109
6110// This function computes an appropriate offset to pass to
6111// MachineMemOperand::setOffset() based on the offset inputs to
6112// an intrinsic. If any of the offsets are non-contstant or
6113// if VIndex is non-zero then this function returns 0. Otherwise,
6114// it returns the sum of VOffset, SOffset, and Offset.
6115static unsigned getBufferOffsetForMMO(SDValue VOffset,
6116 SDValue SOffset,
6117 SDValue Offset,
6118 SDValue VIndex = SDValue()) {
6119
6120 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) ||
6121 !isa<ConstantSDNode>(Offset))
6122 return 0;
6123
6124 if (VIndex) {
6125 if (!isa<ConstantSDNode>(VIndex) || !cast<ConstantSDNode>(VIndex)->isNullValue())
6126 return 0;
6127 }
6128
6129 return cast<ConstantSDNode>(VOffset)->getSExtValue() +
6130 cast<ConstantSDNode>(SOffset)->getSExtValue() +
6131 cast<ConstantSDNode>(Offset)->getSExtValue();
6132}
6133
6134SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
6135 SelectionDAG &DAG) const {
6136 unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6137 SDLoc DL(Op);
6138
6139 switch (IntrID) {
6140 case Intrinsic::amdgcn_ds_ordered_add:
6141 case Intrinsic::amdgcn_ds_ordered_swap: {
6142 MemSDNode *M = cast<MemSDNode>(Op);
6143 SDValue Chain = M->getOperand(0);
6144 SDValue M0 = M->getOperand(2);
6145 SDValue Value = M->getOperand(3);
6146 unsigned IndexOperand = M->getConstantOperandVal(7);
6147 unsigned WaveRelease = M->getConstantOperandVal(8);
6148 unsigned WaveDone = M->getConstantOperandVal(9);
6149 unsigned ShaderType;
6150 unsigned Instruction;
6151
6152 unsigned OrderedCountIndex = IndexOperand & 0x3f;
6153 IndexOperand &= ~0x3f;
6154 unsigned CountDw = 0;
6155
6156 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10) {
6157 CountDw = (IndexOperand >> 24) & 0xf;
6158 IndexOperand &= ~(0xf << 24);
6159
6160 if (CountDw < 1 || CountDw > 4) {
6161 report_fatal_error(
6162 "ds_ordered_count: dword count must be between 1 and 4");
6163 }
6164 }
6165
6166 if (IndexOperand)
6167 report_fatal_error("ds_ordered_count: bad index operand");
6168
6169 switch (IntrID) {
6170 case Intrinsic::amdgcn_ds_ordered_add:
6171 Instruction = 0;
6172 break;
6173 case Intrinsic::amdgcn_ds_ordered_swap:
6174 Instruction = 1;
6175 break;
6176 }
6177
6178 if (WaveDone && !WaveRelease)
6179 report_fatal_error("ds_ordered_count: wave_done requires wave_release");
6180
6181 switch (DAG.getMachineFunction().getFunction().getCallingConv()) {
6182 case CallingConv::AMDGPU_CS:
6183 case CallingConv::AMDGPU_KERNEL:
6184 ShaderType = 0;
6185 break;
6186 case CallingConv::AMDGPU_PS:
6187 ShaderType = 1;
6188 break;
6189 case CallingConv::AMDGPU_VS:
6190 ShaderType = 2;
6191 break;
6192 case CallingConv::AMDGPU_GS:
6193 ShaderType = 3;
6194 break;
6195 default:
6196 report_fatal_error("ds_ordered_count unsupported for this calling conv");
6197 }
6198
6199 unsigned Offset0 = OrderedCountIndex << 2;
6200 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) |
6201 (Instruction << 4);
6202
6203 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10)
6204 Offset1 |= (CountDw - 1) << 6;
6205
6206 unsigned Offset = Offset0 | (Offset1 << 8);
6207
6208 SDValue Ops[] = {
6209 Chain,
6210 Value,
6211 DAG.getTargetConstant(Offset, DL, MVT::i16),
6212 copyToM0(DAG, Chain, DL, M0).getValue(1), // Glue
6213 };
6214 return DAG.getMemIntrinsicNode(AMDGPUISD::DS_ORDERED_COUNT, DL,
6215 M->getVTList(), Ops, M->getMemoryVT(),
6216 M->getMemOperand());
6217 }
6218 case Intrinsic::amdgcn_ds_fadd: {
6219 MemSDNode *M = cast<MemSDNode>(Op);
6220 unsigned Opc;
6221 switch (IntrID) {
6222 case Intrinsic::amdgcn_ds_fadd:
6223 Opc = ISD::ATOMIC_LOAD_FADD;
6224 break;
6225 }
6226
6227 return DAG.getAtomic(Opc, SDLoc(Op), M->getMemoryVT(),
6228 M->getOperand(0), M->getOperand(2), M->getOperand(3),
6229 M->getMemOperand());
6230 }
6231 case Intrinsic::amdgcn_atomic_inc:
6232 case Intrinsic::amdgcn_atomic_dec:
6233 case Intrinsic::amdgcn_ds_fmin:
6234 case Intrinsic::amdgcn_ds_fmax: {
6235 MemSDNode *M = cast<MemSDNode>(Op);
6236 unsigned Opc;
6237 switch (IntrID) {
6238 case Intrinsic::amdgcn_atomic_inc:
6239 Opc = AMDGPUISD::ATOMIC_INC;
6240 break;
6241 case Intrinsic::amdgcn_atomic_dec:
6242 Opc = AMDGPUISD::ATOMIC_DEC;
6243 break;
6244 case Intrinsic::amdgcn_ds_fmin:
6245 Opc = AMDGPUISD::ATOMIC_LOAD_FMIN;
6246 break;
6247 case Intrinsic::amdgcn_ds_fmax:
6248 Opc = AMDGPUISD::ATOMIC_LOAD_FMAX;
6249 break;
6250 default:
6251 llvm_unreachable("Unknown intrinsic!")::llvm::llvm_unreachable_internal("Unknown intrinsic!", "/build/llvm-toolchain-snapshot-10~++20200112100611+7fa5290d5bd/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6251)
;
6252 }
6253 SDValue Ops[] = {
6254 M->getOperand(0), // Chain
6255 M->getOperand(2), // Ptr
6256 M->getOperand(3) // Value
6257 };
6258
6259 return DAG.getMemIntrinsicNode(Opc, SDLoc(Op), M->getVTList(), Ops,
6260 M->getMemoryVT(), M->getMemOperand());
6261 }
6262 case Intrinsic::amdgcn_buffer_load:
6263 case Intrinsic::amdgcn_buffer_load_format: {
6264 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
6265 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(6))->getZExtValue();
6266 unsigned IdxEn = 1;
6267 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
6268 IdxEn = Idx->getZExtValue() != 0;
6269 SDValue Ops[] = {
6270 Op.getOperand(0), // Chain
6271 Op.getOperand(2), // rsrc
6272 Op.getOperand(3), // vindex
6273 SDValue(), // voffset -- will be set by setBufferOffsets
6274 SDValue(), // soffset -- will be set by setBufferOffsets
6275 SDValue(), // offset -- will be set by setBufferOffsets
6276 DAG.getTargetConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
6277 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idxen
6278 };
6279