Bug Summary

File:llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Warning:line 10909, column 52
Called C++ object pointer is null

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SIISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -fhalf-no-semantic-interposition -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/build-llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/build-llvm/lib/Target/AMDGPU -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2021-01-26-035717-31997-1 -x c++ /build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Custom DAG lowering for SI
11//
12//===----------------------------------------------------------------------===//
13
14#include "SIISelLowering.h"
15#include "AMDGPU.h"
16#include "AMDGPUInstrInfo.h"
17#include "AMDGPUTargetMachine.h"
18#include "SIMachineFunctionInfo.h"
19#include "SIRegisterInfo.h"
20#include "llvm/ADT/Statistic.h"
21#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
22#include "llvm/CodeGen/Analysis.h"
23#include "llvm/CodeGen/FunctionLoweringInfo.h"
24#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
25#include "llvm/CodeGen/MachineLoopInfo.h"
26#include "llvm/IR/DiagnosticInfo.h"
27#include "llvm/IR/IntrinsicsAMDGPU.h"
28#include "llvm/IR/IntrinsicsR600.h"
29#include "llvm/Support/CommandLine.h"
30#include "llvm/Support/KnownBits.h"
31
32using namespace llvm;
33
34#define DEBUG_TYPE"si-lower" "si-lower"
35
36STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"si-lower", "NumTailCalls"
, "Number of tail calls"}
;
37
38static cl::opt<bool> DisableLoopAlignment(
39 "amdgpu-disable-loop-alignment",
40 cl::desc("Do not align and prefetch loops"),
41 cl::init(false));
42
43static cl::opt<bool> VGPRReserveforSGPRSpill(
44 "amdgpu-reserve-vgpr-for-sgpr-spill",
45 cl::desc("Allocates one VGPR for future SGPR Spill"), cl::init(true));
46
47static cl::opt<bool> UseDivergentRegisterIndexing(
48 "amdgpu-use-divergent-register-indexing",
49 cl::Hidden,
50 cl::desc("Use indirect register addressing for divergent indexes"),
51 cl::init(false));
52
53static bool hasFP32Denormals(const MachineFunction &MF) {
54 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
55 return Info->getMode().allFP32Denormals();
56}
57
58static bool hasFP64FP16Denormals(const MachineFunction &MF) {
59 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
60 return Info->getMode().allFP64FP16Denormals();
61}
62
63static unsigned findFirstFreeSGPR(CCState &CCInfo) {
64 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
65 for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
66 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
67 return AMDGPU::SGPR0 + Reg;
68 }
69 }
70 llvm_unreachable("Cannot allocate sgpr")::llvm::llvm_unreachable_internal("Cannot allocate sgpr", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 70)
;
71}
72
73SITargetLowering::SITargetLowering(const TargetMachine &TM,
74 const GCNSubtarget &STI)
75 : AMDGPUTargetLowering(TM, STI),
76 Subtarget(&STI) {
77 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
78 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
79
80 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
81 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
82
83 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
84 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
85 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
86
87 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
88 addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
89
90 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
91 addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
92
93 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
94 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
95
96 addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
97 addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
98
99 addRegisterClass(MVT::v8i32, &AMDGPU::SGPR_256RegClass);
100 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
101
102 addRegisterClass(MVT::v4i64, &AMDGPU::SGPR_256RegClass);
103 addRegisterClass(MVT::v4f64, &AMDGPU::VReg_256RegClass);
104
105 addRegisterClass(MVT::v16i32, &AMDGPU::SGPR_512RegClass);
106 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
107
108 addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);
109 addRegisterClass(MVT::v8f64, &AMDGPU::VReg_512RegClass);
110
111 addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);
112 addRegisterClass(MVT::v16f64, &AMDGPU::VReg_1024RegClass);
113
114 if (Subtarget->has16BitInsts()) {
115 addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
116 addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
117
118 // Unless there are also VOP3P operations, not operations are really legal.
119 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
120 addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);
121 addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
122 addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
123 }
124
125 addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
126 addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
127
128 computeRegisterProperties(Subtarget->getRegisterInfo());
129
130 // The boolean content concept here is too inflexible. Compares only ever
131 // really produce a 1-bit result. Any copy/extend from these will turn into a
132 // select, and zext/1 or sext/-1 are equally cheap. Arbitrarily choose 0/1, as
133 // it's what most targets use.
134 setBooleanContents(ZeroOrOneBooleanContent);
135 setBooleanVectorContents(ZeroOrOneBooleanContent);
136
137 // We need to custom lower vector stores from local memory
138 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
139 setOperationAction(ISD::LOAD, MVT::v3i32, Custom);
140 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
141 setOperationAction(ISD::LOAD, MVT::v5i32, Custom);
142 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
143 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
144 setOperationAction(ISD::LOAD, MVT::i1, Custom);
145 setOperationAction(ISD::LOAD, MVT::v32i32, Custom);
146
147 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
148 setOperationAction(ISD::STORE, MVT::v3i32, Custom);
149 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
150 setOperationAction(ISD::STORE, MVT::v5i32, Custom);
151 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
152 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
153 setOperationAction(ISD::STORE, MVT::i1, Custom);
154 setOperationAction(ISD::STORE, MVT::v32i32, Custom);
155
156 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
157 setTruncStoreAction(MVT::v3i32, MVT::v3i16, Expand);
158 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
159 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
160 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
161 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand);
162 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Expand);
163 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
164 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Expand);
165 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
166 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Expand);
167 setTruncStoreAction(MVT::v2i16, MVT::v2i8, Expand);
168 setTruncStoreAction(MVT::v4i16, MVT::v4i8, Expand);
169 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
170 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Expand);
171 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Expand);
172
173 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Expand);
174 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Expand);
175 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Expand);
176 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Expand);
177 setTruncStoreAction(MVT::v16i64, MVT::v16i32, Expand);
178
179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
180 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
181
182 setOperationAction(ISD::SELECT, MVT::i1, Promote);
183 setOperationAction(ISD::SELECT, MVT::i64, Custom);
184 setOperationAction(ISD::SELECT, MVT::f64, Promote);
185 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
186
187 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
188 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
189 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
190 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
191 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
192
193 setOperationAction(ISD::SETCC, MVT::i1, Promote);
194 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
195 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
196 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
197
198 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
199 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
200 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Expand);
201 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Expand);
202 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Expand);
203 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Expand);
204 setOperationAction(ISD::TRUNCATE, MVT::v16i32, Expand);
205 setOperationAction(ISD::FP_ROUND, MVT::v16f32, Expand);
206
207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
209 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
210 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v3i16, Custom);
213 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
215
216 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
217 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
218 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
219 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
220 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
221 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
222
223 setOperationAction(ISD::UADDO, MVT::i32, Legal);
224 setOperationAction(ISD::USUBO, MVT::i32, Legal);
225
226 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
227 setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
228
229 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
230 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
231 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
232
233#if 0
234 setOperationAction(ISD::ADDCARRY, MVT::i64, Legal);
235 setOperationAction(ISD::SUBCARRY, MVT::i64, Legal);
236#endif
237
238 // We only support LOAD/STORE and vector manipulation ops for vectors
239 // with > 4 elements.
240 for (MVT VT : { MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32,
241 MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16,
242 MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64,
243 MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32 }) {
244 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
245 switch (Op) {
246 case ISD::LOAD:
247 case ISD::STORE:
248 case ISD::BUILD_VECTOR:
249 case ISD::BITCAST:
250 case ISD::EXTRACT_VECTOR_ELT:
251 case ISD::INSERT_VECTOR_ELT:
252 case ISD::INSERT_SUBVECTOR:
253 case ISD::EXTRACT_SUBVECTOR:
254 case ISD::SCALAR_TO_VECTOR:
255 break;
256 case ISD::CONCAT_VECTORS:
257 setOperationAction(Op, VT, Custom);
258 break;
259 default:
260 setOperationAction(Op, VT, Expand);
261 break;
262 }
263 }
264 }
265
266 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand);
267
268 // TODO: For dynamic 64-bit vector inserts/extracts, should emit a pseudo that
269 // is expanded to avoid having two separate loops in case the index is a VGPR.
270
271 // Most operations are naturally 32-bit vector operations. We only support
272 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
273 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
274 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
275 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
276
277 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
278 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
279
280 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
281 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
282
283 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
284 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
285 }
286
287 for (MVT Vec64 : { MVT::v4i64, MVT::v4f64 }) {
288 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
289 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v8i32);
290
291 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
292 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v8i32);
293
294 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
295 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v8i32);
296
297 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
298 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v8i32);
299 }
300
301 for (MVT Vec64 : { MVT::v8i64, MVT::v8f64 }) {
302 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
303 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v16i32);
304
305 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
306 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v16i32);
307
308 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
309 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v16i32);
310
311 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
312 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v16i32);
313 }
314
315 for (MVT Vec64 : { MVT::v16i64, MVT::v16f64 }) {
316 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
317 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v32i32);
318
319 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
320 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v32i32);
321
322 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
323 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v32i32);
324
325 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
326 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v32i32);
327 }
328
329 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
330 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
331 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
332 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
333
334 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f16, Custom);
335 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
336
337 // Avoid stack access for these.
338 // TODO: Generalize to more vector types.
339 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);
340 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);
341 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
342 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
343
344 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
345 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
346 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom);
347 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom);
348 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom);
349
350 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
351 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
352 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
353
354 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom);
355 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f16, Custom);
356 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
357 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
358
359 // Deal with vec3 vector operations when widened to vec4.
360 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom);
361 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom);
362 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom);
363 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom);
364
365 // Deal with vec5 vector operations when widened to vec8.
366 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom);
367 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom);
368 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom);
369 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom);
370
371 // BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
372 // and output demarshalling
373 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
374 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
375
376 // We can't return success/failure, only the old value,
377 // let LLVM add the comparison
378 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
379 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Expand);
380
381 if (Subtarget->hasFlatAddressSpace()) {
382 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
383 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
384 }
385
386 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
387
388 // FIXME: This should be narrowed to i32, but that only happens if i64 is
389 // illegal.
390 // FIXME: Should lower sub-i32 bswaps to bit-ops without v_perm_b32.
391 setOperationAction(ISD::BSWAP, MVT::i64, Legal);
392 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
393
394 // On SI this is s_memtime and s_memrealtime on VI.
395 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
396 setOperationAction(ISD::TRAP, MVT::Other, Custom);
397 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Custom);
398
399 if (Subtarget->has16BitInsts()) {
400 setOperationAction(ISD::FPOW, MVT::f16, Promote);
401 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
402 setOperationAction(ISD::FLOG, MVT::f16, Custom);
403 setOperationAction(ISD::FEXP, MVT::f16, Custom);
404 setOperationAction(ISD::FLOG10, MVT::f16, Custom);
405 }
406
407 if (Subtarget->hasMadMacF32Insts())
408 setOperationAction(ISD::FMAD, MVT::f32, Legal);
409
410 if (!Subtarget->hasBFI()) {
411 // fcopysign can be done in a single instruction with BFI.
412 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
413 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
414 }
415
416 if (!Subtarget->hasBCNT(32))
417 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
418
419 if (!Subtarget->hasBCNT(64))
420 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
421
422 if (Subtarget->hasFFBH())
423 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
424
425 if (Subtarget->hasFFBL())
426 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
427
428 // We only really have 32-bit BFE instructions (and 16-bit on VI).
429 //
430 // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
431 // effort to match them now. We want this to be false for i64 cases when the
432 // extraction isn't restricted to the upper or lower half. Ideally we would
433 // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
434 // span the midpoint are probably relatively rare, so don't worry about them
435 // for now.
436 if (Subtarget->hasBFE())
437 setHasExtractBitsInsn(true);
438
439 // Clamp modifier on add/sub
440 if (Subtarget->hasIntClamp()) {
441 setOperationAction(ISD::UADDSAT, MVT::i32, Legal);
442 setOperationAction(ISD::USUBSAT, MVT::i32, Legal);
443 }
444
445 if (Subtarget->hasAddNoCarry()) {
446 setOperationAction(ISD::SADDSAT, MVT::i16, Legal);
447 setOperationAction(ISD::SSUBSAT, MVT::i16, Legal);
448 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
449 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
450 }
451
452 setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
453 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom);
454 setOperationAction(ISD::FMINNUM, MVT::f64, Custom);
455 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom);
456
457
458 // These are really only legal for ieee_mode functions. We should be avoiding
459 // them for functions that don't have ieee_mode enabled, so just say they are
460 // legal.
461 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
462 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
463 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
464 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
465
466
467 if (Subtarget->haveRoundOpsF64()) {
468 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
469 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
470 setOperationAction(ISD::FRINT, MVT::f64, Legal);
471 } else {
472 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
473 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
474 setOperationAction(ISD::FRINT, MVT::f64, Custom);
475 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
476 }
477
478 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
479
480 setOperationAction(ISD::FSIN, MVT::f32, Custom);
481 setOperationAction(ISD::FCOS, MVT::f32, Custom);
482 setOperationAction(ISD::FDIV, MVT::f32, Custom);
483 setOperationAction(ISD::FDIV, MVT::f64, Custom);
484
485 if (Subtarget->has16BitInsts()) {
486 setOperationAction(ISD::Constant, MVT::i16, Legal);
487
488 setOperationAction(ISD::SMIN, MVT::i16, Legal);
489 setOperationAction(ISD::SMAX, MVT::i16, Legal);
490
491 setOperationAction(ISD::UMIN, MVT::i16, Legal);
492 setOperationAction(ISD::UMAX, MVT::i16, Legal);
493
494 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
495 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
496
497 setOperationAction(ISD::ROTR, MVT::i16, Expand);
498 setOperationAction(ISD::ROTL, MVT::i16, Expand);
499
500 setOperationAction(ISD::SDIV, MVT::i16, Promote);
501 setOperationAction(ISD::UDIV, MVT::i16, Promote);
502 setOperationAction(ISD::SREM, MVT::i16, Promote);
503 setOperationAction(ISD::UREM, MVT::i16, Promote);
504 setOperationAction(ISD::UADDSAT, MVT::i16, Legal);
505 setOperationAction(ISD::USUBSAT, MVT::i16, Legal);
506
507 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
508
509 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
510 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
511 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
512 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
513 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
514
515 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
516
517 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
518
519 setOperationAction(ISD::LOAD, MVT::i16, Custom);
520
521 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
522
523 setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote);
524 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
525 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
526 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
527
528 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
529 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
530
531 // F16 - Constant Actions.
532 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
533
534 // F16 - Load/Store Actions.
535 setOperationAction(ISD::LOAD, MVT::f16, Promote);
536 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
537 setOperationAction(ISD::STORE, MVT::f16, Promote);
538 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
539
540 // F16 - VOP1 Actions.
541 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
542 setOperationAction(ISD::FCOS, MVT::f16, Custom);
543 setOperationAction(ISD::FSIN, MVT::f16, Custom);
544
545 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
546 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Custom);
547
548 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
549 setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
550 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
551 setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
552 setOperationAction(ISD::FROUND, MVT::f16, Custom);
553
554 // F16 - VOP2 Actions.
555 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
556 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
557
558 setOperationAction(ISD::FDIV, MVT::f16, Custom);
559
560 // F16 - VOP3 Actions.
561 setOperationAction(ISD::FMA, MVT::f16, Legal);
562 if (STI.hasMadF16())
563 setOperationAction(ISD::FMAD, MVT::f16, Legal);
564
565 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) {
566 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
567 switch (Op) {
568 case ISD::LOAD:
569 case ISD::STORE:
570 case ISD::BUILD_VECTOR:
571 case ISD::BITCAST:
572 case ISD::EXTRACT_VECTOR_ELT:
573 case ISD::INSERT_VECTOR_ELT:
574 case ISD::INSERT_SUBVECTOR:
575 case ISD::EXTRACT_SUBVECTOR:
576 case ISD::SCALAR_TO_VECTOR:
577 break;
578 case ISD::CONCAT_VECTORS:
579 setOperationAction(Op, VT, Custom);
580 break;
581 default:
582 setOperationAction(Op, VT, Expand);
583 break;
584 }
585 }
586 }
587
588 // v_perm_b32 can handle either of these.
589 setOperationAction(ISD::BSWAP, MVT::i16, Legal);
590 setOperationAction(ISD::BSWAP, MVT::v2i16, Legal);
591 setOperationAction(ISD::BSWAP, MVT::v4i16, Custom);
592
593 // XXX - Do these do anything? Vector constants turn into build_vector.
594 setOperationAction(ISD::Constant, MVT::v2i16, Legal);
595 setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal);
596
597 setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);
598 setOperationAction(ISD::UNDEF, MVT::v2f16, Legal);
599
600 setOperationAction(ISD::STORE, MVT::v2i16, Promote);
601 AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
602 setOperationAction(ISD::STORE, MVT::v2f16, Promote);
603 AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32);
604
605 setOperationAction(ISD::LOAD, MVT::v2i16, Promote);
606 AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32);
607 setOperationAction(ISD::LOAD, MVT::v2f16, Promote);
608 AddPromotedToType(ISD::LOAD, MVT::v2f16, MVT::i32);
609
610 setOperationAction(ISD::AND, MVT::v2i16, Promote);
611 AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);
612 setOperationAction(ISD::OR, MVT::v2i16, Promote);
613 AddPromotedToType(ISD::OR, MVT::v2i16, MVT::i32);
614 setOperationAction(ISD::XOR, MVT::v2i16, Promote);
615 AddPromotedToType(ISD::XOR, MVT::v2i16, MVT::i32);
616
617 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
618 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::v2i32);
619 setOperationAction(ISD::LOAD, MVT::v4f16, Promote);
620 AddPromotedToType(ISD::LOAD, MVT::v4f16, MVT::v2i32);
621
622 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
623 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
624 setOperationAction(ISD::STORE, MVT::v4f16, Promote);
625 AddPromotedToType(ISD::STORE, MVT::v4f16, MVT::v2i32);
626
627 setOperationAction(ISD::ANY_EXTEND, MVT::v2i32, Expand);
628 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i32, Expand);
629 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i32, Expand);
630 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand);
631
632 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Expand);
633 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand);
634 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Expand);
635
636 if (!Subtarget->hasVOP3PInsts()) {
637 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
638 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
639 }
640
641 setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
642 // This isn't really legal, but this avoids the legalizer unrolling it (and
643 // allows matching fneg (fabs x) patterns)
644 setOperationAction(ISD::FABS, MVT::v2f16, Legal);
645
646 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom);
647 setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
648 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal);
649 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal);
650
651 setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom);
652 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v4f16, Custom);
653
654 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand);
655 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand);
656 }
657
658 if (Subtarget->hasVOP3PInsts()) {
659 setOperationAction(ISD::ADD, MVT::v2i16, Legal);
660 setOperationAction(ISD::SUB, MVT::v2i16, Legal);
661 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
662 setOperationAction(ISD::SHL, MVT::v2i16, Legal);
663 setOperationAction(ISD::SRL, MVT::v2i16, Legal);
664 setOperationAction(ISD::SRA, MVT::v2i16, Legal);
665 setOperationAction(ISD::SMIN, MVT::v2i16, Legal);
666 setOperationAction(ISD::UMIN, MVT::v2i16, Legal);
667 setOperationAction(ISD::SMAX, MVT::v2i16, Legal);
668 setOperationAction(ISD::UMAX, MVT::v2i16, Legal);
669
670 setOperationAction(ISD::UADDSAT, MVT::v2i16, Legal);
671 setOperationAction(ISD::USUBSAT, MVT::v2i16, Legal);
672 setOperationAction(ISD::SADDSAT, MVT::v2i16, Legal);
673 setOperationAction(ISD::SSUBSAT, MVT::v2i16, Legal);
674
675 setOperationAction(ISD::FADD, MVT::v2f16, Legal);
676 setOperationAction(ISD::FMUL, MVT::v2f16, Legal);
677 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
678
679 setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal);
680 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v2f16, Legal);
681
682 setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal);
683
684 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
685 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
686
687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom);
688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
689
690 setOperationAction(ISD::SHL, MVT::v4i16, Custom);
691 setOperationAction(ISD::SRA, MVT::v4i16, Custom);
692 setOperationAction(ISD::SRL, MVT::v4i16, Custom);
693 setOperationAction(ISD::ADD, MVT::v4i16, Custom);
694 setOperationAction(ISD::SUB, MVT::v4i16, Custom);
695 setOperationAction(ISD::MUL, MVT::v4i16, Custom);
696
697 setOperationAction(ISD::SMIN, MVT::v4i16, Custom);
698 setOperationAction(ISD::SMAX, MVT::v4i16, Custom);
699 setOperationAction(ISD::UMIN, MVT::v4i16, Custom);
700 setOperationAction(ISD::UMAX, MVT::v4i16, Custom);
701
702 setOperationAction(ISD::UADDSAT, MVT::v4i16, Custom);
703 setOperationAction(ISD::SADDSAT, MVT::v4i16, Custom);
704 setOperationAction(ISD::USUBSAT, MVT::v4i16, Custom);
705 setOperationAction(ISD::SSUBSAT, MVT::v4i16, Custom);
706
707 setOperationAction(ISD::FADD, MVT::v4f16, Custom);
708 setOperationAction(ISD::FMUL, MVT::v4f16, Custom);
709 setOperationAction(ISD::FMA, MVT::v4f16, Custom);
710
711 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom);
712 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom);
713
714 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
715 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom);
716 setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom);
717
718 setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
719 setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
720 setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
721 }
722
723 setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
724 setOperationAction(ISD::FABS, MVT::v4f16, Custom);
725
726 if (Subtarget->has16BitInsts()) {
727 setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
728 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
729 setOperationAction(ISD::SELECT, MVT::v2f16, Promote);
730 AddPromotedToType(ISD::SELECT, MVT::v2f16, MVT::i32);
731 } else {
732 // Legalization hack.
733 setOperationAction(ISD::SELECT, MVT::v2i16, Custom);
734 setOperationAction(ISD::SELECT, MVT::v2f16, Custom);
735
736 setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
737 setOperationAction(ISD::FABS, MVT::v2f16, Custom);
738 }
739
740 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
741 setOperationAction(ISD::SELECT, VT, Custom);
742 }
743
744 setOperationAction(ISD::SMULO, MVT::i64, Custom);
745 setOperationAction(ISD::UMULO, MVT::i64, Custom);
746
747 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
748 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
749 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
750 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
751 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f16, Custom);
752 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i16, Custom);
753 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
754
755 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2f16, Custom);
756 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2i16, Custom);
757 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v3f16, Custom);
758 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v3i16, Custom);
759 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4f16, Custom);
760 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4i16, Custom);
761 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v8f16, Custom);
762 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
763 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::f16, Custom);
764 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom);
765 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
766
767 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
768 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
769 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
770 setOperationAction(ISD::INTRINSIC_VOID, MVT::v3i16, Custom);
771 setOperationAction(ISD::INTRINSIC_VOID, MVT::v3f16, Custom);
772 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
773 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4i16, Custom);
774 setOperationAction(ISD::INTRINSIC_VOID, MVT::f16, Custom);
775 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
776 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
777
778 setTargetDAGCombine(ISD::ADD);
779 setTargetDAGCombine(ISD::ADDCARRY);
780 setTargetDAGCombine(ISD::SUB);
781 setTargetDAGCombine(ISD::SUBCARRY);
782 setTargetDAGCombine(ISD::FADD);
783 setTargetDAGCombine(ISD::FSUB);
784 setTargetDAGCombine(ISD::FMINNUM);
785 setTargetDAGCombine(ISD::FMAXNUM);
786 setTargetDAGCombine(ISD::FMINNUM_IEEE);
787 setTargetDAGCombine(ISD::FMAXNUM_IEEE);
788 setTargetDAGCombine(ISD::FMA);
789 setTargetDAGCombine(ISD::SMIN);
790 setTargetDAGCombine(ISD::SMAX);
791 setTargetDAGCombine(ISD::UMIN);
792 setTargetDAGCombine(ISD::UMAX);
793 setTargetDAGCombine(ISD::SETCC);
794 setTargetDAGCombine(ISD::AND);
795 setTargetDAGCombine(ISD::OR);
796 setTargetDAGCombine(ISD::XOR);
797 setTargetDAGCombine(ISD::SINT_TO_FP);
798 setTargetDAGCombine(ISD::UINT_TO_FP);
799 setTargetDAGCombine(ISD::FCANONICALIZE);
800 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
801 setTargetDAGCombine(ISD::ZERO_EXTEND);
802 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
803 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
804 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
805
806 // All memory operations. Some folding on the pointer operand is done to help
807 // matching the constant offsets in the addressing modes.
808 setTargetDAGCombine(ISD::LOAD);
809 setTargetDAGCombine(ISD::STORE);
810 setTargetDAGCombine(ISD::ATOMIC_LOAD);
811 setTargetDAGCombine(ISD::ATOMIC_STORE);
812 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
813 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
814 setTargetDAGCombine(ISD::ATOMIC_SWAP);
815 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
816 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
817 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
818 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
819 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
820 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
821 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
822 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
823 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
824 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
825 setTargetDAGCombine(ISD::ATOMIC_LOAD_FADD);
826 setTargetDAGCombine(ISD::INTRINSIC_VOID);
827 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
828
829 // FIXME: In other contexts we pretend this is a per-function property.
830 setStackPointerRegisterToSaveRestore(AMDGPU::SGPR32);
831
832 setSchedulingPreference(Sched::RegPressure);
833}
834
835const GCNSubtarget *SITargetLowering::getSubtarget() const {
836 return Subtarget;
837}
838
839//===----------------------------------------------------------------------===//
840// TargetLowering queries
841//===----------------------------------------------------------------------===//
842
843// v_mad_mix* support a conversion from f16 to f32.
844//
845// There is only one special case when denormals are enabled we don't currently,
846// where this is OK to use.
847bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
848 EVT DestVT, EVT SrcVT) const {
849 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||
850 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
851 DestVT.getScalarType() == MVT::f32 &&
852 SrcVT.getScalarType() == MVT::f16 &&
853 // TODO: This probably only requires no input flushing?
854 !hasFP32Denormals(DAG.getMachineFunction());
855}
856
857bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
858 // SI has some legal vector types, but no legal vector operations. Say no
859 // shuffles are legal in order to prefer scalarizing some vector operations.
860 return false;
861}
862
863MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
864 CallingConv::ID CC,
865 EVT VT) const {
866 if (CC == CallingConv::AMDGPU_KERNEL)
867 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
868
869 if (VT.isVector()) {
870 EVT ScalarVT = VT.getScalarType();
871 unsigned Size = ScalarVT.getSizeInBits();
872 if (Size == 16) {
873 if (Subtarget->has16BitInsts())
874 return VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
875 return VT.isInteger() ? MVT::i32 : MVT::f32;
876 }
877
878 if (Size < 16)
879 return Subtarget->has16BitInsts() ? MVT::i16 : MVT::i32;
880 return Size == 32 ? ScalarVT.getSimpleVT() : MVT::i32;
881 }
882
883 if (VT.getSizeInBits() > 32)
884 return MVT::i32;
885
886 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
887}
888
889unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
890 CallingConv::ID CC,
891 EVT VT) const {
892 if (CC == CallingConv::AMDGPU_KERNEL)
893 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
894
895 if (VT.isVector()) {
896 unsigned NumElts = VT.getVectorNumElements();
897 EVT ScalarVT = VT.getScalarType();
898 unsigned Size = ScalarVT.getSizeInBits();
899
900 // FIXME: Should probably promote 8-bit vectors to i16.
901 if (Size == 16 && Subtarget->has16BitInsts())
902 return (NumElts + 1) / 2;
903
904 if (Size <= 32)
905 return NumElts;
906
907 if (Size > 32)
908 return NumElts * ((Size + 31) / 32);
909 } else if (VT.getSizeInBits() > 32)
910 return (VT.getSizeInBits() + 31) / 32;
911
912 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
913}
914
915unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
916 LLVMContext &Context, CallingConv::ID CC,
917 EVT VT, EVT &IntermediateVT,
918 unsigned &NumIntermediates, MVT &RegisterVT) const {
919 if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
920 unsigned NumElts = VT.getVectorNumElements();
921 EVT ScalarVT = VT.getScalarType();
922 unsigned Size = ScalarVT.getSizeInBits();
923 // FIXME: We should fix the ABI to be the same on targets without 16-bit
924 // support, but unless we can properly handle 3-vectors, it will be still be
925 // inconsistent.
926 if (Size == 16 && Subtarget->has16BitInsts()) {
927 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
928 IntermediateVT = RegisterVT;
929 NumIntermediates = (NumElts + 1) / 2;
930 return NumIntermediates;
931 }
932
933 if (Size == 32) {
934 RegisterVT = ScalarVT.getSimpleVT();
935 IntermediateVT = RegisterVT;
936 NumIntermediates = NumElts;
937 return NumIntermediates;
938 }
939
940 if (Size < 16 && Subtarget->has16BitInsts()) {
941 // FIXME: Should probably form v2i16 pieces
942 RegisterVT = MVT::i16;
943 IntermediateVT = ScalarVT;
944 NumIntermediates = NumElts;
945 return NumIntermediates;
946 }
947
948
949 if (Size != 16 && Size <= 32) {
950 RegisterVT = MVT::i32;
951 IntermediateVT = ScalarVT;
952 NumIntermediates = NumElts;
953 return NumIntermediates;
954 }
955
956 if (Size > 32) {
957 RegisterVT = MVT::i32;
958 IntermediateVT = RegisterVT;
959 NumIntermediates = NumElts * ((Size + 31) / 32);
960 return NumIntermediates;
961 }
962 }
963
964 return TargetLowering::getVectorTypeBreakdownForCallingConv(
965 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
966}
967
968static EVT memVTFromImageData(Type *Ty, unsigned DMaskLanes) {
969 assert(DMaskLanes != 0)((DMaskLanes != 0) ? static_cast<void> (0) : __assert_fail
("DMaskLanes != 0", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 969, __PRETTY_FUNCTION__))
;
970
971 if (auto *VT = dyn_cast<FixedVectorType>(Ty)) {
972 unsigned NumElts = std::min(DMaskLanes, VT->getNumElements());
973 return EVT::getVectorVT(Ty->getContext(),
974 EVT::getEVT(VT->getElementType()),
975 NumElts);
976 }
977
978 return EVT::getEVT(Ty);
979}
980
981// Peek through TFE struct returns to only use the data size.
982static EVT memVTFromImageReturn(Type *Ty, unsigned DMaskLanes) {
983 auto *ST = dyn_cast<StructType>(Ty);
984 if (!ST)
985 return memVTFromImageData(Ty, DMaskLanes);
986
987 // Some intrinsics return an aggregate type - special case to work out the
988 // correct memVT.
989 //
990 // Only limited forms of aggregate type currently expected.
991 if (ST->getNumContainedTypes() != 2 ||
992 !ST->getContainedType(1)->isIntegerTy(32))
993 return EVT();
994 return memVTFromImageData(ST->getContainedType(0), DMaskLanes);
995}
996
997bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
998 const CallInst &CI,
999 MachineFunction &MF,
1000 unsigned IntrID) const {
1001 if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
1002 AMDGPU::lookupRsrcIntrinsic(IntrID)) {
1003 AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
1004 (Intrinsic::ID)IntrID);
1005 if (Attr.hasFnAttribute(Attribute::ReadNone))
1006 return false;
1007
1008 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1009
1010 if (RsrcIntr->IsImage) {
1011 Info.ptrVal =
1012 MFI->getImagePSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1013 Info.align.reset();
1014 } else {
1015 Info.ptrVal =
1016 MFI->getBufferPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1017 }
1018
1019 Info.flags = MachineMemOperand::MODereferenceable;
1020 if (Attr.hasFnAttribute(Attribute::ReadOnly)) {
1021 unsigned DMaskLanes = 4;
1022
1023 if (RsrcIntr->IsImage) {
1024 const AMDGPU::ImageDimIntrinsicInfo *Intr
1025 = AMDGPU::getImageDimIntrinsicInfo(IntrID);
1026 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
1027 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
1028
1029 if (!BaseOpcode->Gather4) {
1030 // If this isn't a gather, we may have excess loaded elements in the
1031 // IR type. Check the dmask for the real number of elements loaded.
1032 unsigned DMask
1033 = cast<ConstantInt>(CI.getArgOperand(0))->getZExtValue();
1034 DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask);
1035 }
1036
1037 Info.memVT = memVTFromImageReturn(CI.getType(), DMaskLanes);
1038 } else
1039 Info.memVT = EVT::getEVT(CI.getType());
1040
1041 // FIXME: What does alignment mean for an image?
1042 Info.opc = ISD::INTRINSIC_W_CHAIN;
1043 Info.flags |= MachineMemOperand::MOLoad;
1044 } else if (Attr.hasFnAttribute(Attribute::WriteOnly)) {
1045 Info.opc = ISD::INTRINSIC_VOID;
1046
1047 Type *DataTy = CI.getArgOperand(0)->getType();
1048 if (RsrcIntr->IsImage) {
1049 unsigned DMask = cast<ConstantInt>(CI.getArgOperand(1))->getZExtValue();
1050 unsigned DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask);
1051 Info.memVT = memVTFromImageData(DataTy, DMaskLanes);
1052 } else
1053 Info.memVT = EVT::getEVT(DataTy);
1054
1055 Info.flags |= MachineMemOperand::MOStore;
1056 } else {
1057 // Atomic
1058 Info.opc = CI.getType()->isVoidTy() ? ISD::INTRINSIC_VOID :
1059 ISD::INTRINSIC_W_CHAIN;
1060 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
1061 Info.flags = MachineMemOperand::MOLoad |
1062 MachineMemOperand::MOStore |
1063 MachineMemOperand::MODereferenceable;
1064
1065 // XXX - Should this be volatile without known ordering?
1066 Info.flags |= MachineMemOperand::MOVolatile;
1067 }
1068 return true;
1069 }
1070
1071 switch (IntrID) {
1072 case Intrinsic::amdgcn_atomic_inc:
1073 case Intrinsic::amdgcn_atomic_dec:
1074 case Intrinsic::amdgcn_ds_ordered_add:
1075 case Intrinsic::amdgcn_ds_ordered_swap:
1076 case Intrinsic::amdgcn_ds_fadd:
1077 case Intrinsic::amdgcn_ds_fmin:
1078 case Intrinsic::amdgcn_ds_fmax: {
1079 Info.opc = ISD::INTRINSIC_W_CHAIN;
1080 Info.memVT = MVT::getVT(CI.getType());
1081 Info.ptrVal = CI.getOperand(0);
1082 Info.align.reset();
1083 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1084
1085 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(4));
1086 if (!Vol->isZero())
1087 Info.flags |= MachineMemOperand::MOVolatile;
1088
1089 return true;
1090 }
1091 case Intrinsic::amdgcn_buffer_atomic_fadd: {
1092 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1093
1094 Info.opc = ISD::INTRINSIC_W_CHAIN;
1095 Info.memVT = MVT::getVT(CI.getOperand(0)->getType());
1096 Info.ptrVal =
1097 MFI->getBufferPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1098 Info.align.reset();
1099 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1100
1101 const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
1102 if (!Vol || !Vol->isZero())
1103 Info.flags |= MachineMemOperand::MOVolatile;
1104
1105 return true;
1106 }
1107 case Intrinsic::amdgcn_ds_append:
1108 case Intrinsic::amdgcn_ds_consume: {
1109 Info.opc = ISD::INTRINSIC_W_CHAIN;
1110 Info.memVT = MVT::getVT(CI.getType());
1111 Info.ptrVal = CI.getOperand(0);
1112 Info.align.reset();
1113 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1114
1115 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(1));
1116 if (!Vol->isZero())
1117 Info.flags |= MachineMemOperand::MOVolatile;
1118
1119 return true;
1120 }
1121 case Intrinsic::amdgcn_global_atomic_csub: {
1122 Info.opc = ISD::INTRINSIC_W_CHAIN;
1123 Info.memVT = MVT::getVT(CI.getType());
1124 Info.ptrVal = CI.getOperand(0);
1125 Info.align.reset();
1126 Info.flags = MachineMemOperand::MOLoad |
1127 MachineMemOperand::MOStore |
1128 MachineMemOperand::MOVolatile;
1129 return true;
1130 }
1131 case Intrinsic::amdgcn_global_atomic_fadd: {
1132 Info.opc = ISD::INTRINSIC_W_CHAIN;
1133 Info.memVT = MVT::getVT(CI.getType());
1134 Info.ptrVal = CI.getOperand(0);
1135 Info.align.reset();
1136 Info.flags = MachineMemOperand::MOLoad |
1137 MachineMemOperand::MOStore |
1138 MachineMemOperand::MODereferenceable |
1139 MachineMemOperand::MOVolatile;
1140 return true;
1141 }
1142 case Intrinsic::amdgcn_image_bvh_intersect_ray: {
1143 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1144 Info.opc = ISD::INTRINSIC_W_CHAIN;
1145 Info.memVT = MVT::getVT(CI.getType()); // XXX: what is correct VT?
1146 Info.ptrVal =
1147 MFI->getImagePSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1148 Info.align.reset();
1149 Info.flags = MachineMemOperand::MOLoad |
1150 MachineMemOperand::MODereferenceable;
1151 return true;
1152 }
1153 case Intrinsic::amdgcn_ds_gws_init:
1154 case Intrinsic::amdgcn_ds_gws_barrier:
1155 case Intrinsic::amdgcn_ds_gws_sema_v:
1156 case Intrinsic::amdgcn_ds_gws_sema_br:
1157 case Intrinsic::amdgcn_ds_gws_sema_p:
1158 case Intrinsic::amdgcn_ds_gws_sema_release_all: {
1159 Info.opc = ISD::INTRINSIC_VOID;
1160
1161 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1162 Info.ptrVal =
1163 MFI->getGWSPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1164
1165 // This is an abstract access, but we need to specify a type and size.
1166 Info.memVT = MVT::i32;
1167 Info.size = 4;
1168 Info.align = Align(4);
1169
1170 Info.flags = MachineMemOperand::MOStore;
1171 if (IntrID == Intrinsic::amdgcn_ds_gws_barrier)
1172 Info.flags = MachineMemOperand::MOLoad;
1173 return true;
1174 }
1175 default:
1176 return false;
1177 }
1178}
1179
1180bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
1181 SmallVectorImpl<Value*> &Ops,
1182 Type *&AccessTy) const {
1183 switch (II->getIntrinsicID()) {
1184 case Intrinsic::amdgcn_atomic_inc:
1185 case Intrinsic::amdgcn_atomic_dec:
1186 case Intrinsic::amdgcn_ds_ordered_add:
1187 case Intrinsic::amdgcn_ds_ordered_swap:
1188 case Intrinsic::amdgcn_ds_append:
1189 case Intrinsic::amdgcn_ds_consume:
1190 case Intrinsic::amdgcn_ds_fadd:
1191 case Intrinsic::amdgcn_ds_fmin:
1192 case Intrinsic::amdgcn_ds_fmax:
1193 case Intrinsic::amdgcn_global_atomic_fadd:
1194 case Intrinsic::amdgcn_global_atomic_csub: {
1195 Value *Ptr = II->getArgOperand(0);
1196 AccessTy = II->getType();
1197 Ops.push_back(Ptr);
1198 return true;
1199 }
1200 default:
1201 return false;
1202 }
1203}
1204
1205bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
1206 if (!Subtarget->hasFlatInstOffsets()) {
1207 // Flat instructions do not have offsets, and only have the register
1208 // address.
1209 return AM.BaseOffs == 0 && AM.Scale == 0;
1210 }
1211
1212 return AM.Scale == 0 &&
1213 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset(
1214 AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS,
1215 /*Signed=*/false));
1216}
1217
1218bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const {
1219 if (Subtarget->hasFlatGlobalInsts())
1220 return AM.Scale == 0 &&
1221 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset(
1222 AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS,
1223 /*Signed=*/true));
1224
1225 if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) {
1226 // Assume the we will use FLAT for all global memory accesses
1227 // on VI.
1228 // FIXME: This assumption is currently wrong. On VI we still use
1229 // MUBUF instructions for the r + i addressing mode. As currently
1230 // implemented, the MUBUF instructions only work on buffer < 4GB.
1231 // It may be possible to support > 4GB buffers with MUBUF instructions,
1232 // by setting the stride value in the resource descriptor which would
1233 // increase the size limit to (stride * 4GB). However, this is risky,
1234 // because it has never been validated.
1235 return isLegalFlatAddressingMode(AM);
1236 }
1237
1238 return isLegalMUBUFAddressingMode(AM);
1239}
1240
1241bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
1242 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
1243 // additionally can do r + r + i with addr64. 32-bit has more addressing
1244 // mode options. Depending on the resource constant, it can also do
1245 // (i64 r0) + (i32 r1) * (i14 i).
1246 //
1247 // Private arrays end up using a scratch buffer most of the time, so also
1248 // assume those use MUBUF instructions. Scratch loads / stores are currently
1249 // implemented as mubuf instructions with offen bit set, so slightly
1250 // different than the normal addr64.
1251 if (!SIInstrInfo::isLegalMUBUFImmOffset(AM.BaseOffs))
1252 return false;
1253
1254 // FIXME: Since we can split immediate into soffset and immediate offset,
1255 // would it make sense to allow any immediate?
1256
1257 switch (AM.Scale) {
1258 case 0: // r + i or just i, depending on HasBaseReg.
1259 return true;
1260 case 1:
1261 return true; // We have r + r or r + i.
1262 case 2:
1263 if (AM.HasBaseReg) {
1264 // Reject 2 * r + r.
1265 return false;
1266 }
1267
1268 // Allow 2 * r as r + r
1269 // Or 2 * r + i is allowed as r + r + i.
1270 return true;
1271 default: // Don't allow n * r
1272 return false;
1273 }
1274}
1275
1276bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
1277 const AddrMode &AM, Type *Ty,
1278 unsigned AS, Instruction *I) const {
1279 // No global is ever allowed as a base.
1280 if (AM.BaseGV)
1281 return false;
1282
1283 if (AS == AMDGPUAS::GLOBAL_ADDRESS)
1284 return isLegalGlobalAddressingMode(AM);
1285
1286 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
1287 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
1288 AS == AMDGPUAS::BUFFER_FAT_POINTER) {
1289 // If the offset isn't a multiple of 4, it probably isn't going to be
1290 // correctly aligned.
1291 // FIXME: Can we get the real alignment here?
1292 if (AM.BaseOffs % 4 != 0)
1293 return isLegalMUBUFAddressingMode(AM);
1294
1295 // There are no SMRD extloads, so if we have to do a small type access we
1296 // will use a MUBUF load.
1297 // FIXME?: We also need to do this if unaligned, but we don't know the
1298 // alignment here.
1299 if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4)
1300 return isLegalGlobalAddressingMode(AM);
1301
1302 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1303 // SMRD instructions have an 8-bit, dword offset on SI.
1304 if (!isUInt<8>(AM.BaseOffs / 4))
1305 return false;
1306 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
1307 // On CI+, this can also be a 32-bit literal constant offset. If it fits
1308 // in 8-bits, it can use a smaller encoding.
1309 if (!isUInt<32>(AM.BaseOffs / 4))
1310 return false;
1311 } else if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
1312 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
1313 if (!isUInt<20>(AM.BaseOffs))
1314 return false;
1315 } else
1316 llvm_unreachable("unhandled generation")::llvm::llvm_unreachable_internal("unhandled generation", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1316)
;
1317
1318 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1319 return true;
1320
1321 if (AM.Scale == 1 && AM.HasBaseReg)
1322 return true;
1323
1324 return false;
1325
1326 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1327 return isLegalMUBUFAddressingMode(AM);
1328 } else if (AS == AMDGPUAS::LOCAL_ADDRESS ||
1329 AS == AMDGPUAS::REGION_ADDRESS) {
1330 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
1331 // field.
1332 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
1333 // an 8-bit dword offset but we don't know the alignment here.
1334 if (!isUInt<16>(AM.BaseOffs))
1335 return false;
1336
1337 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1338 return true;
1339
1340 if (AM.Scale == 1 && AM.HasBaseReg)
1341 return true;
1342
1343 return false;
1344 } else if (AS == AMDGPUAS::FLAT_ADDRESS ||
1345 AS == AMDGPUAS::UNKNOWN_ADDRESS_SPACE) {
1346 // For an unknown address space, this usually means that this is for some
1347 // reason being used for pure arithmetic, and not based on some addressing
1348 // computation. We don't have instructions that compute pointers with any
1349 // addressing modes, so treat them as having no offset like flat
1350 // instructions.
1351 return isLegalFlatAddressingMode(AM);
1352 }
1353
1354 // Assume a user alias of global for unknown address spaces.
1355 return isLegalGlobalAddressingMode(AM);
1356}
1357
1358bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1359 const SelectionDAG &DAG) const {
1360 if (AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS) {
1361 return (MemVT.getSizeInBits() <= 4 * 32);
1362 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1363 unsigned MaxPrivateBits = 8 * getSubtarget()->getMaxPrivateElementSize();
1364 return (MemVT.getSizeInBits() <= MaxPrivateBits);
1365 } else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
1366 return (MemVT.getSizeInBits() <= 2 * 32);
1367 }
1368 return true;
1369}
1370
1371bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
1372 unsigned Size, unsigned AddrSpace, Align Alignment,
1373 MachineMemOperand::Flags Flags, bool *IsFast) const {
1374 if (IsFast)
1375 *IsFast = false;
1376
1377 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1378 AddrSpace == AMDGPUAS::REGION_ADDRESS) {
1379 // Check if alignment requirements for ds_read/write instructions are
1380 // disabled.
1381 if (Subtarget->hasUnalignedDSAccessEnabled() &&
1382 !Subtarget->hasLDSMisalignedBug()) {
1383 if (IsFast)
1384 *IsFast = Alignment != Align(2);
1385 return true;
1386 }
1387
1388 if (Size == 64) {
1389 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
1390 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
1391 // with adjacent offsets.
1392 bool AlignedBy4 = Alignment >= Align(4);
1393 if (IsFast)
1394 *IsFast = AlignedBy4;
1395
1396 return AlignedBy4;
1397 }
1398 if (Size == 96) {
1399 // ds_read/write_b96 require 16-byte alignment on gfx8 and older.
1400 bool Aligned = Alignment >= Align(16);
1401 if (IsFast)
1402 *IsFast = Aligned;
1403
1404 return Aligned;
1405 }
1406 if (Size == 128) {
1407 // ds_read/write_b128 require 16-byte alignment on gfx8 and older, but we
1408 // can do a 8 byte aligned, 16 byte access in a single operation using
1409 // ds_read2/write2_b64.
1410 bool Aligned = Alignment >= Align(8);
1411 if (IsFast)
1412 *IsFast = Aligned;
1413
1414 return Aligned;
1415 }
1416 }
1417
1418 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
1419 bool AlignedBy4 = Alignment >= Align(4);
1420 if (IsFast)
1421 *IsFast = AlignedBy4;
1422
1423 return AlignedBy4 ||
1424 Subtarget->enableFlatScratch() ||
1425 Subtarget->hasUnalignedScratchAccess();
1426 }
1427
1428 // FIXME: We have to be conservative here and assume that flat operations
1429 // will access scratch. If we had access to the IR function, then we
1430 // could determine if any private memory was used in the function.
1431 if (AddrSpace == AMDGPUAS::FLAT_ADDRESS &&
1432 !Subtarget->hasUnalignedScratchAccess()) {
1433 bool AlignedBy4 = Alignment >= Align(4);
1434 if (IsFast)
1435 *IsFast = AlignedBy4;
1436
1437 return AlignedBy4;
1438 }
1439
1440 if (Subtarget->hasUnalignedBufferAccessEnabled() &&
1441 !(AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1442 AddrSpace == AMDGPUAS::REGION_ADDRESS)) {
1443 // If we have an uniform constant load, it still requires using a slow
1444 // buffer instruction if unaligned.
1445 if (IsFast) {
1446 // Accesses can really be issued as 1-byte aligned or 4-byte aligned, so
1447 // 2-byte alignment is worse than 1 unless doing a 2-byte accesss.
1448 *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
1449 AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ?
1450 Alignment >= Align(4) : Alignment != Align(2);
1451 }
1452
1453 return true;
1454 }
1455
1456 // Smaller than dword value must be aligned.
1457 if (Size < 32)
1458 return false;
1459
1460 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
1461 // byte-address are ignored, thus forcing Dword alignment.
1462 // This applies to private, global, and constant memory.
1463 if (IsFast)
1464 *IsFast = true;
1465
1466 return Size >= 32 && Alignment >= Align(4);
1467}
1468
1469bool SITargetLowering::allowsMisalignedMemoryAccesses(
1470 EVT VT, unsigned AddrSpace, unsigned Alignment,
1471 MachineMemOperand::Flags Flags, bool *IsFast) const {
1472 if (IsFast)
1473 *IsFast = false;
1474
1475 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
1476 // which isn't a simple VT.
1477 // Until MVT is extended to handle this, simply check for the size and
1478 // rely on the condition below: allow accesses if the size is a multiple of 4.
1479 if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
1480 VT.getStoreSize() > 16)) {
1481 return false;
1482 }
1483
1484 return allowsMisalignedMemoryAccessesImpl(VT.getSizeInBits(), AddrSpace,
1485 Align(Alignment), Flags, IsFast);
1486}
1487
1488EVT SITargetLowering::getOptimalMemOpType(
1489 const MemOp &Op, const AttributeList &FuncAttributes) const {
1490 // FIXME: Should account for address space here.
1491
1492 // The default fallback uses the private pointer size as a guess for a type to
1493 // use. Make sure we switch these to 64-bit accesses.
1494
1495 if (Op.size() >= 16 &&
1496 Op.isDstAligned(Align(4))) // XXX: Should only do for global
1497 return MVT::v4i32;
1498
1499 if (Op.size() >= 8 && Op.isDstAligned(Align(4)))
1500 return MVT::v2i32;
1501
1502 // Use the default.
1503 return MVT::Other;
1504}
1505
1506bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {
1507 const MemSDNode *MemNode = cast<MemSDNode>(N);
1508 const Value *Ptr = MemNode->getMemOperand()->getValue();
1509 const Instruction *I = dyn_cast_or_null<Instruction>(Ptr);
1510 return I && I->getMetadata("amdgpu.noclobber");
1511}
1512
1513bool SITargetLowering::isNonGlobalAddrSpace(unsigned AS) {
1514 return AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS ||
1515 AS == AMDGPUAS::PRIVATE_ADDRESS;
1516}
1517
1518bool SITargetLowering::isFreeAddrSpaceCast(unsigned SrcAS,
1519 unsigned DestAS) const {
1520 // Flat -> private/local is a simple truncate.
1521 // Flat -> global is no-op
1522 if (SrcAS == AMDGPUAS::FLAT_ADDRESS)
1523 return true;
1524
1525 const GCNTargetMachine &TM =
1526 static_cast<const GCNTargetMachine &>(getTargetMachine());
1527 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1528}
1529
1530bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
1531 const MemSDNode *MemNode = cast<MemSDNode>(N);
1532
1533 return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
1534}
1535
1536TargetLoweringBase::LegalizeTypeAction
1537SITargetLowering::getPreferredVectorAction(MVT VT) const {
1538 int NumElts = VT.getVectorNumElements();
1539 if (NumElts != 1 && VT.getScalarType().bitsLE(MVT::i16))
1540 return VT.isPow2VectorType() ? TypeSplitVector : TypeWidenVector;
1541 return TargetLoweringBase::getPreferredVectorAction(VT);
1542}
1543
1544bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
1545 Type *Ty) const {
1546 // FIXME: Could be smarter if called for vector constants.
1547 return true;
1548}
1549
1550bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
1551 if (Subtarget->has16BitInsts() && VT == MVT::i16) {
1552 switch (Op) {
1553 case ISD::LOAD:
1554 case ISD::STORE:
1555
1556 // These operations are done with 32-bit instructions anyway.
1557 case ISD::AND:
1558 case ISD::OR:
1559 case ISD::XOR:
1560 case ISD::SELECT:
1561 // TODO: Extensions?
1562 return true;
1563 default:
1564 return false;
1565 }
1566 }
1567
1568 // SimplifySetCC uses this function to determine whether or not it should
1569 // create setcc with i1 operands. We don't have instructions for i1 setcc.
1570 if (VT == MVT::i1 && Op == ISD::SETCC)
1571 return false;
1572
1573 return TargetLowering::isTypeDesirableForOp(Op, VT);
1574}
1575
1576SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
1577 const SDLoc &SL,
1578 SDValue Chain,
1579 uint64_t Offset) const {
1580 const DataLayout &DL = DAG.getDataLayout();
1581 MachineFunction &MF = DAG.getMachineFunction();
1582 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1583
1584 const ArgDescriptor *InputPtrReg;
1585 const TargetRegisterClass *RC;
1586 LLT ArgTy;
1587
1588 std::tie(InputPtrReg, RC, ArgTy) =
1589 Info->getPreloadedValue(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
1590
1591 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1592 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
1593 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
1594 MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
1595
1596 return DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Offset));
1597}
1598
1599SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
1600 const SDLoc &SL) const {
1601 uint64_t Offset = getImplicitParameterOffset(DAG.getMachineFunction(),
1602 FIRST_IMPLICIT);
1603 return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset);
1604}
1605
1606SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
1607 const SDLoc &SL, SDValue Val,
1608 bool Signed,
1609 const ISD::InputArg *Arg) const {
1610 // First, if it is a widened vector, narrow it.
1611 if (VT.isVector() &&
1612 VT.getVectorNumElements() != MemVT.getVectorNumElements()) {
1613 EVT NarrowedVT =
1614 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(),
1615 VT.getVectorNumElements());
1616 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val,
1617 DAG.getConstant(0, SL, MVT::i32));
1618 }
1619
1620 // Then convert the vector elements or scalar value.
1621 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
1622 VT.bitsLT(MemVT)) {
1623 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
1624 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT));
1625 }
1626
1627 if (MemVT.isFloatingPoint())
1628 Val = getFPExtOrFPRound(DAG, Val, SL, VT);
1629 else if (Signed)
1630 Val = DAG.getSExtOrTrunc(Val, SL, VT);
1631 else
1632 Val = DAG.getZExtOrTrunc(Val, SL, VT);
1633
1634 return Val;
1635}
1636
1637SDValue SITargetLowering::lowerKernargMemParameter(
1638 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain,
1639 uint64_t Offset, Align Alignment, bool Signed,
1640 const ISD::InputArg *Arg) const {
1641 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
1642
1643 // Try to avoid using an extload by loading earlier than the argument address,
1644 // and extracting the relevant bits. The load should hopefully be merged with
1645 // the previous argument.
1646 if (MemVT.getStoreSize() < 4 && Alignment < 4) {
1647 // TODO: Handle align < 4 and size >= 4 (can happen with packed structs).
1648 int64_t AlignDownOffset = alignDown(Offset, 4);
1649 int64_t OffsetDiff = Offset - AlignDownOffset;
1650
1651 EVT IntVT = MemVT.changeTypeToInteger();
1652
1653 // TODO: If we passed in the base kernel offset we could have a better
1654 // alignment than 4, but we don't really need it.
1655 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
1656 SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, Align(4),
1657 MachineMemOperand::MODereferenceable |
1658 MachineMemOperand::MOInvariant);
1659
1660 SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
1661 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
1662
1663 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract);
1664 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal);
1665 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg);
1666
1667
1668 return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
1669 }
1670
1671 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
1672 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Alignment,
1673 MachineMemOperand::MODereferenceable |
1674 MachineMemOperand::MOInvariant);
1675
1676 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg);
1677 return DAG.getMergeValues({ Val, Load.getValue(1) }, SL);
1678}
1679
1680SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
1681 const SDLoc &SL, SDValue Chain,
1682 const ISD::InputArg &Arg) const {
1683 MachineFunction &MF = DAG.getMachineFunction();
1684 MachineFrameInfo &MFI = MF.getFrameInfo();
1685
1686 if (Arg.Flags.isByVal()) {
1687 unsigned Size = Arg.Flags.getByValSize();
1688 int FrameIdx = MFI.CreateFixedObject(Size, VA.getLocMemOffset(), false);
1689 return DAG.getFrameIndex(FrameIdx, MVT::i32);
1690 }
1691
1692 unsigned ArgOffset = VA.getLocMemOffset();
1693 unsigned ArgSize = VA.getValVT().getStoreSize();
1694
1695 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, true);
1696
1697 // Create load nodes to retrieve arguments from the stack.
1698 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1699 SDValue ArgValue;
1700
1701 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1702 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1703 MVT MemVT = VA.getValVT();
1704
1705 switch (VA.getLocInfo()) {
1706 default:
1707 break;
1708 case CCValAssign::BCvt:
1709 MemVT = VA.getLocVT();
1710 break;
1711 case CCValAssign::SExt:
1712 ExtType = ISD::SEXTLOAD;
1713 break;
1714 case CCValAssign::ZExt:
1715 ExtType = ISD::ZEXTLOAD;
1716 break;
1717 case CCValAssign::AExt:
1718 ExtType = ISD::EXTLOAD;
1719 break;
1720 }
1721
1722 ArgValue = DAG.getExtLoad(
1723 ExtType, SL, VA.getLocVT(), Chain, FIN,
1724 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
1725 MemVT);
1726 return ArgValue;
1727}
1728
1729SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,
1730 const SIMachineFunctionInfo &MFI,
1731 EVT VT,
1732 AMDGPUFunctionArgInfo::PreloadedValue PVID) const {
1733 const ArgDescriptor *Reg;
1734 const TargetRegisterClass *RC;
1735 LLT Ty;
1736
1737 std::tie(Reg, RC, Ty) = MFI.getPreloadedValue(PVID);
1738 return CreateLiveInRegister(DAG, RC, Reg->getRegister(), VT);
1739}
1740
1741static void processPSInputArgs(SmallVectorImpl<ISD::InputArg> &Splits,
1742 CallingConv::ID CallConv,
1743 ArrayRef<ISD::InputArg> Ins, BitVector &Skipped,
1744 FunctionType *FType,
1745 SIMachineFunctionInfo *Info) {
1746 for (unsigned I = 0, E = Ins.size(), PSInputNum = 0; I != E; ++I) {
1747 const ISD::InputArg *Arg = &Ins[I];
1748
1749 assert((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) &&(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "vector type argument should have been split"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1750, __PRETTY_FUNCTION__))
1750 "vector type argument should have been split")(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "vector type argument should have been split"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1750, __PRETTY_FUNCTION__))
;
1751
1752 // First check if it's a PS input addr.
1753 if (CallConv == CallingConv::AMDGPU_PS &&
1754 !Arg->Flags.isInReg() && PSInputNum <= 15) {
1755 bool SkipArg = !Arg->Used && !Info->isPSInputAllocated(PSInputNum);
1756
1757 // Inconveniently only the first part of the split is marked as isSplit,
1758 // so skip to the end. We only want to increment PSInputNum once for the
1759 // entire split argument.
1760 if (Arg->Flags.isSplit()) {
1761 while (!Arg->Flags.isSplitEnd()) {
1762 assert((!Arg->VT.isVector() ||(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1764, __PRETTY_FUNCTION__))
1763 Arg->VT.getScalarSizeInBits() == 16) &&(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1764, __PRETTY_FUNCTION__))
1764 "unexpected vector split in ps argument type")(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1764, __PRETTY_FUNCTION__))
;
1765 if (!SkipArg)
1766 Splits.push_back(*Arg);
1767 Arg = &Ins[++I];
1768 }
1769 }
1770
1771 if (SkipArg) {
1772 // We can safely skip PS inputs.
1773 Skipped.set(Arg->getOrigArgIndex());
1774 ++PSInputNum;
1775 continue;
1776 }
1777
1778 Info->markPSInputAllocated(PSInputNum);
1779 if (Arg->Used)
1780 Info->markPSInputEnabled(PSInputNum);
1781
1782 ++PSInputNum;
1783 }
1784
1785 Splits.push_back(*Arg);
1786 }
1787}
1788
1789// Allocate special inputs passed in VGPRs.
1790void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,
1791 MachineFunction &MF,
1792 const SIRegisterInfo &TRI,
1793 SIMachineFunctionInfo &Info) const {
1794 const LLT S32 = LLT::scalar(32);
1795 MachineRegisterInfo &MRI = MF.getRegInfo();
1796
1797 if (Info.hasWorkItemIDX()) {
1798 Register Reg = AMDGPU::VGPR0;
1799 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1800
1801 CCInfo.AllocateReg(Reg);
1802 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg));
1803 }
1804
1805 if (Info.hasWorkItemIDY()) {
1806 Register Reg = AMDGPU::VGPR1;
1807 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1808
1809 CCInfo.AllocateReg(Reg);
1810 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg));
1811 }
1812
1813 if (Info.hasWorkItemIDZ()) {
1814 Register Reg = AMDGPU::VGPR2;
1815 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1816
1817 CCInfo.AllocateReg(Reg);
1818 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg));
1819 }
1820}
1821
1822// Try to allocate a VGPR at the end of the argument list, or if no argument
1823// VGPRs are left allocating a stack slot.
1824// If \p Mask is is given it indicates bitfield position in the register.
1825// If \p Arg is given use it with new ]p Mask instead of allocating new.
1826static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,
1827 ArgDescriptor Arg = ArgDescriptor()) {
1828 if (Arg.isSet())
1829 return ArgDescriptor::createArg(Arg, Mask);
1830
1831 ArrayRef<MCPhysReg> ArgVGPRs
1832 = makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), 32);
1833 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
1834 if (RegIdx == ArgVGPRs.size()) {
1835 // Spill to stack required.
1836 int64_t Offset = CCInfo.AllocateStack(4, Align(4));
1837
1838 return ArgDescriptor::createStack(Offset, Mask);
1839 }
1840
1841 unsigned Reg = ArgVGPRs[RegIdx];
1842 Reg = CCInfo.AllocateReg(Reg);
1843 assert(Reg != AMDGPU::NoRegister)((Reg != AMDGPU::NoRegister) ? static_cast<void> (0) : __assert_fail
("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1843, __PRETTY_FUNCTION__))
;
1844
1845 MachineFunction &MF = CCInfo.getMachineFunction();
1846 Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1847 MF.getRegInfo().setType(LiveInVReg, LLT::scalar(32));
1848 return ArgDescriptor::createRegister(Reg, Mask);
1849}
1850
1851static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,
1852 const TargetRegisterClass *RC,
1853 unsigned NumArgRegs) {
1854 ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
1855 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
1856 if (RegIdx == ArgSGPRs.size())
1857 report_fatal_error("ran out of SGPRs for arguments");
1858
1859 unsigned Reg = ArgSGPRs[RegIdx];
1860 Reg = CCInfo.AllocateReg(Reg);
1861 assert(Reg != AMDGPU::NoRegister)((Reg != AMDGPU::NoRegister) ? static_cast<void> (0) : __assert_fail
("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1861, __PRETTY_FUNCTION__))
;
1862
1863 MachineFunction &MF = CCInfo.getMachineFunction();
1864 MF.addLiveIn(Reg, RC);
1865 return ArgDescriptor::createRegister(Reg);
1866}
1867
1868static ArgDescriptor allocateSGPR32Input(CCState &CCInfo) {
1869 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
1870}
1871
1872static ArgDescriptor allocateSGPR64Input(CCState &CCInfo) {
1873 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);
1874}
1875
1876/// Allocate implicit function VGPR arguments at the end of allocated user
1877/// arguments.
1878void SITargetLowering::allocateSpecialInputVGPRs(
1879 CCState &CCInfo, MachineFunction &MF,
1880 const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const {
1881 const unsigned Mask = 0x3ff;
1882 ArgDescriptor Arg;
1883
1884 if (Info.hasWorkItemIDX()) {
1885 Arg = allocateVGPR32Input(CCInfo, Mask);
1886 Info.setWorkItemIDX(Arg);
1887 }
1888
1889 if (Info.hasWorkItemIDY()) {
1890 Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);
1891 Info.setWorkItemIDY(Arg);
1892 }
1893
1894 if (Info.hasWorkItemIDZ())
1895 Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));
1896}
1897
1898/// Allocate implicit function VGPR arguments in fixed registers.
1899void SITargetLowering::allocateSpecialInputVGPRsFixed(
1900 CCState &CCInfo, MachineFunction &MF,
1901 const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const {
1902 Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31);
1903 if (!Reg)
1904 report_fatal_error("failed to allocated VGPR for implicit arguments");
1905
1906 const unsigned Mask = 0x3ff;
1907 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask));
1908 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg, Mask << 10));
1909 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg, Mask << 20));
1910}
1911
1912void SITargetLowering::allocateSpecialInputSGPRs(
1913 CCState &CCInfo,
1914 MachineFunction &MF,
1915 const SIRegisterInfo &TRI,
1916 SIMachineFunctionInfo &Info) const {
1917 auto &ArgInfo = Info.getArgInfo();
1918
1919 // TODO: Unify handling with private memory pointers.
1920
1921 if (Info.hasDispatchPtr())
1922 ArgInfo.DispatchPtr = allocateSGPR64Input(CCInfo);
1923
1924 if (Info.hasQueuePtr())
1925 ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo);
1926
1927 // Implicit arg ptr takes the place of the kernarg segment pointer. This is a
1928 // constant offset from the kernarg segment.
1929 if (Info.hasImplicitArgPtr())
1930 ArgInfo.ImplicitArgPtr = allocateSGPR64Input(CCInfo);
1931
1932 if (Info.hasDispatchID())
1933 ArgInfo.DispatchID = allocateSGPR64Input(CCInfo);
1934
1935 // flat_scratch_init is not applicable for non-kernel functions.
1936
1937 if (Info.hasWorkGroupIDX())
1938 ArgInfo.WorkGroupIDX = allocateSGPR32Input(CCInfo);
1939
1940 if (Info.hasWorkGroupIDY())
1941 ArgInfo.WorkGroupIDY = allocateSGPR32Input(CCInfo);
1942
1943 if (Info.hasWorkGroupIDZ())
1944 ArgInfo.WorkGroupIDZ = allocateSGPR32Input(CCInfo);
1945}
1946
1947// Allocate special inputs passed in user SGPRs.
1948void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
1949 MachineFunction &MF,
1950 const SIRegisterInfo &TRI,
1951 SIMachineFunctionInfo &Info) const {
1952 if (Info.hasImplicitBufferPtr()) {
1953 Register ImplicitBufferPtrReg = Info.addImplicitBufferPtr(TRI);
1954 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
1955 CCInfo.AllocateReg(ImplicitBufferPtrReg);
1956 }
1957
1958 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
1959 if (Info.hasPrivateSegmentBuffer()) {
1960 Register PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
1961 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
1962 CCInfo.AllocateReg(PrivateSegmentBufferReg);
1963 }
1964
1965 if (Info.hasDispatchPtr()) {
1966 Register DispatchPtrReg = Info.addDispatchPtr(TRI);
1967 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
1968 CCInfo.AllocateReg(DispatchPtrReg);
1969 }
1970
1971 if (Info.hasQueuePtr()) {
1972 Register QueuePtrReg = Info.addQueuePtr(TRI);
1973 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
1974 CCInfo.AllocateReg(QueuePtrReg);
1975 }
1976
1977 if (Info.hasKernargSegmentPtr()) {
1978 MachineRegisterInfo &MRI = MF.getRegInfo();
1979 Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
1980 CCInfo.AllocateReg(InputPtrReg);
1981
1982 Register VReg = MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
1983 MRI.setType(VReg, LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
1984 }
1985
1986 if (Info.hasDispatchID()) {
1987 Register DispatchIDReg = Info.addDispatchID(TRI);
1988 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
1989 CCInfo.AllocateReg(DispatchIDReg);
1990 }
1991
1992 if (Info.hasFlatScratchInit() && !getSubtarget()->isAmdPalOS()) {
1993 Register FlatScratchInitReg = Info.addFlatScratchInit(TRI);
1994 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
1995 CCInfo.AllocateReg(FlatScratchInitReg);
1996 }
1997
1998 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
1999 // these from the dispatch pointer.
2000}
2001
2002// Allocate special input registers that are initialized per-wave.
2003void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,
2004 MachineFunction &MF,
2005 SIMachineFunctionInfo &Info,
2006 CallingConv::ID CallConv,
2007 bool IsShader) const {
2008 if (Info.hasWorkGroupIDX()) {
2009 Register Reg = Info.addWorkGroupIDX();
2010 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2011 CCInfo.AllocateReg(Reg);
2012 }
2013
2014 if (Info.hasWorkGroupIDY()) {
2015 Register Reg = Info.addWorkGroupIDY();
2016 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2017 CCInfo.AllocateReg(Reg);
2018 }
2019
2020 if (Info.hasWorkGroupIDZ()) {
2021 Register Reg = Info.addWorkGroupIDZ();
2022 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2023 CCInfo.AllocateReg(Reg);
2024 }
2025
2026 if (Info.hasWorkGroupInfo()) {
2027 Register Reg = Info.addWorkGroupInfo();
2028 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2029 CCInfo.AllocateReg(Reg);
2030 }
2031
2032 if (Info.hasPrivateSegmentWaveByteOffset()) {
2033 // Scratch wave offset passed in system SGPR.
2034 unsigned PrivateSegmentWaveByteOffsetReg;
2035
2036 if (IsShader) {
2037 PrivateSegmentWaveByteOffsetReg =
2038 Info.getPrivateSegmentWaveByteOffsetSystemSGPR();
2039
2040 // This is true if the scratch wave byte offset doesn't have a fixed
2041 // location.
2042 if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) {
2043 PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
2044 Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
2045 }
2046 } else
2047 PrivateSegmentWaveByteOffsetReg = Info.addPrivateSegmentWaveByteOffset();
2048
2049 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
2050 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
2051 }
2052}
2053
2054static void reservePrivateMemoryRegs(const TargetMachine &TM,
2055 MachineFunction &MF,
2056 const SIRegisterInfo &TRI,
2057 SIMachineFunctionInfo &Info) {
2058 // Now that we've figured out where the scratch register inputs are, see if
2059 // should reserve the arguments and use them directly.
2060 MachineFrameInfo &MFI = MF.getFrameInfo();
2061 bool HasStackObjects = MFI.hasStackObjects();
2062 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
2063
2064 // Record that we know we have non-spill stack objects so we don't need to
2065 // check all stack objects later.
2066 if (HasStackObjects)
2067 Info.setHasNonSpillStackObjects(true);
2068
2069 // Everything live out of a block is spilled with fast regalloc, so it's
2070 // almost certain that spilling will be required.
2071 if (TM.getOptLevel() == CodeGenOpt::None)
2072 HasStackObjects = true;
2073
2074 // For now assume stack access is needed in any callee functions, so we need
2075 // the scratch registers to pass in.
2076 bool RequiresStackAccess = HasStackObjects || MFI.hasCalls();
2077
2078 if (!ST.enableFlatScratch()) {
2079 if (RequiresStackAccess && ST.isAmdHsaOrMesa(MF.getFunction())) {
2080 // If we have stack objects, we unquestionably need the private buffer
2081 // resource. For the Code Object V2 ABI, this will be the first 4 user
2082 // SGPR inputs. We can reserve those and use them directly.
2083
2084 Register PrivateSegmentBufferReg =
2085 Info.getPreloadedReg(AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER);
2086 Info.setScratchRSrcReg(PrivateSegmentBufferReg);
2087 } else {
2088 unsigned ReservedBufferReg = TRI.reservedPrivateSegmentBufferReg(MF);
2089 // We tentatively reserve the last registers (skipping the last registers
2090 // which may contain VCC, FLAT_SCR, and XNACK). After register allocation,
2091 // we'll replace these with the ones immediately after those which were
2092 // really allocated. In the prologue copies will be inserted from the
2093 // argument to these reserved registers.
2094
2095 // Without HSA, relocations are used for the scratch pointer and the
2096 // buffer resource setup is always inserted in the prologue. Scratch wave
2097 // offset is still in an input SGPR.
2098 Info.setScratchRSrcReg(ReservedBufferReg);
2099 }
2100 }
2101
2102 MachineRegisterInfo &MRI = MF.getRegInfo();
2103
2104 // For entry functions we have to set up the stack pointer if we use it,
2105 // whereas non-entry functions get this "for free". This means there is no
2106 // intrinsic advantage to using S32 over S34 in cases where we do not have
2107 // calls but do need a frame pointer (i.e. if we are requested to have one
2108 // because frame pointer elimination is disabled). To keep things simple we
2109 // only ever use S32 as the call ABI stack pointer, and so using it does not
2110 // imply we need a separate frame pointer.
2111 //
2112 // Try to use s32 as the SP, but move it if it would interfere with input
2113 // arguments. This won't work with calls though.
2114 //
2115 // FIXME: Move SP to avoid any possible inputs, or find a way to spill input
2116 // registers.
2117 if (!MRI.isLiveIn(AMDGPU::SGPR32)) {
2118 Info.setStackPtrOffsetReg(AMDGPU::SGPR32);
2119 } else {
2120 assert(AMDGPU::isShader(MF.getFunction().getCallingConv()))((AMDGPU::isShader(MF.getFunction().getCallingConv())) ? static_cast
<void> (0) : __assert_fail ("AMDGPU::isShader(MF.getFunction().getCallingConv())"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2120, __PRETTY_FUNCTION__))
;
2121
2122 if (MFI.hasCalls())
2123 report_fatal_error("call in graphics shader with too many input SGPRs");
2124
2125 for (unsigned Reg : AMDGPU::SGPR_32RegClass) {
2126 if (!MRI.isLiveIn(Reg)) {
2127 Info.setStackPtrOffsetReg(Reg);
2128 break;
2129 }
2130 }
2131
2132 if (Info.getStackPtrOffsetReg() == AMDGPU::SP_REG)
2133 report_fatal_error("failed to find register for SP");
2134 }
2135
2136 // hasFP should be accurate for entry functions even before the frame is
2137 // finalized, because it does not rely on the known stack size, only
2138 // properties like whether variable sized objects are present.
2139 if (ST.getFrameLowering()->hasFP(MF)) {
2140 Info.setFrameOffsetReg(AMDGPU::SGPR33);
2141 }
2142}
2143
2144bool SITargetLowering::supportSplitCSR(MachineFunction *MF) const {
2145 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
2146 return !Info->isEntryFunction();
2147}
2148
2149void SITargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
2150
2151}
2152
2153void SITargetLowering::insertCopiesSplitCSR(
2154 MachineBasicBlock *Entry,
2155 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
2156 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2157
2158 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
2159 if (!IStart)
2160 return;
2161
2162 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2163 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
2164 MachineBasicBlock::iterator MBBI = Entry->begin();
2165 for (const MCPhysReg *I = IStart; *I; ++I) {
2166 const TargetRegisterClass *RC = nullptr;
2167 if (AMDGPU::SReg_64RegClass.contains(*I))
2168 RC = &AMDGPU::SGPR_64RegClass;
2169 else if (AMDGPU::SReg_32RegClass.contains(*I))
2170 RC = &AMDGPU::SGPR_32RegClass;
2171 else
2172 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2172)
;
2173
2174 Register NewVR = MRI->createVirtualRegister(RC);
2175 // Create copy from CSR to a virtual register.
2176 Entry->addLiveIn(*I);
2177 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
2178 .addReg(*I);
2179
2180 // Insert the copy-back instructions right before the terminator.
2181 for (auto *Exit : Exits)
2182 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
2183 TII->get(TargetOpcode::COPY), *I)
2184 .addReg(NewVR);
2185 }
2186}
2187
2188SDValue SITargetLowering::LowerFormalArguments(
2189 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2190 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2191 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2192 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2193
2194 MachineFunction &MF = DAG.getMachineFunction();
2195 const Function &Fn = MF.getFunction();
2196 FunctionType *FType = MF.getFunction().getFunctionType();
2197 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2198
2199 if (Subtarget->isAmdHsaOS() && AMDGPU::isGraphics(CallConv)) {
2200 DiagnosticInfoUnsupported NoGraphicsHSA(
2201 Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
2202 DAG.getContext()->diagnose(NoGraphicsHSA);
2203 return DAG.getEntryNode();
2204 }
2205
2206 SmallVector<ISD::InputArg, 16> Splits;
2207 SmallVector<CCValAssign, 16> ArgLocs;
2208 BitVector Skipped(Ins.size());
2209 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2210 *DAG.getContext());
2211
2212 bool IsGraphics = AMDGPU::isGraphics(CallConv);
2213 bool IsKernel = AMDGPU::isKernel(CallConv);
2214 bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CallConv);
2215
2216 if (IsGraphics) {
2217 assert(!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && (!Info->hasFlatScratchInit() || Subtarget->
enableFlatScratch()) && !Info->hasWorkGroupIDX() &&
!Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ
() && !Info->hasWorkGroupInfo() && !Info->
hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
!Info->hasWorkItemIDZ()) ? static_cast<void> (0) : __assert_fail
("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2222, __PRETTY_FUNCTION__))
2218 (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && (!Info->hasFlatScratchInit() || Subtarget->
enableFlatScratch()) && !Info->hasWorkGroupIDX() &&
!Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ
() && !Info->hasWorkGroupInfo() && !Info->
hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
!Info->hasWorkItemIDZ()) ? static_cast<void> (0) : __assert_fail
("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2222, __PRETTY_FUNCTION__))
2219 !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && (!Info->hasFlatScratchInit() || Subtarget->
enableFlatScratch()) && !Info->hasWorkGroupIDX() &&
!Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ
() && !Info->hasWorkGroupInfo() && !Info->
hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
!Info->hasWorkItemIDZ()) ? static_cast<void> (0) : __assert_fail
("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2222, __PRETTY_FUNCTION__))
2220 !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && (!Info->hasFlatScratchInit() || Subtarget->
enableFlatScratch()) && !Info->hasWorkGroupIDX() &&
!Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ
() && !Info->hasWorkGroupInfo() && !Info->
hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
!Info->hasWorkItemIDZ()) ? static_cast<void> (0) : __assert_fail
("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2222, __PRETTY_FUNCTION__))
2221 !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && (!Info->hasFlatScratchInit() || Subtarget->
enableFlatScratch()) && !Info->hasWorkGroupIDX() &&
!Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ
() && !Info->hasWorkGroupInfo() && !Info->
hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
!Info->hasWorkItemIDZ()) ? static_cast<void> (0) : __assert_fail
("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2222, __PRETTY_FUNCTION__))
2222 !Info->hasWorkItemIDZ())((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && (!Info->hasFlatScratchInit() || Subtarget->
enableFlatScratch()) && !Info->hasWorkGroupIDX() &&
!Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ
() && !Info->hasWorkGroupInfo() && !Info->
hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
!Info->hasWorkItemIDZ()) ? static_cast<void> (0) : __assert_fail
("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2222, __PRETTY_FUNCTION__))
;
2223 }
2224
2225 if (CallConv == CallingConv::AMDGPU_PS) {
2226 processPSInputArgs(Splits, CallConv, Ins, Skipped, FType, Info);
2227
2228 // At least one interpolation mode must be enabled or else the GPU will
2229 // hang.
2230 //
2231 // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
2232 // set PSInputAddr, the user wants to enable some bits after the compilation
2233 // based on run-time states. Since we can't know what the final PSInputEna
2234 // will look like, so we shouldn't do anything here and the user should take
2235 // responsibility for the correct programming.
2236 //
2237 // Otherwise, the following restrictions apply:
2238 // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
2239 // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
2240 // enabled too.
2241 if ((Info->getPSInputAddr() & 0x7F) == 0 ||
2242 ((Info->getPSInputAddr() & 0xF) == 0 && Info->isPSInputAllocated(11))) {
2243 CCInfo.AllocateReg(AMDGPU::VGPR0);
2244 CCInfo.AllocateReg(AMDGPU::VGPR1);
2245 Info->markPSInputAllocated(0);
2246 Info->markPSInputEnabled(0);
2247 }
2248 if (Subtarget->isAmdPalOS()) {
2249 // For isAmdPalOS, the user does not enable some bits after compilation
2250 // based on run-time states; the register values being generated here are
2251 // the final ones set in hardware. Therefore we need to apply the
2252 // workaround to PSInputAddr and PSInputEnable together. (The case where
2253 // a bit is set in PSInputAddr but not PSInputEnable is where the
2254 // frontend set up an input arg for a particular interpolation mode, but
2255 // nothing uses that input arg. Really we should have an earlier pass
2256 // that removes such an arg.)
2257 unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
2258 if ((PsInputBits & 0x7F) == 0 ||
2259 ((PsInputBits & 0xF) == 0 && (PsInputBits >> 11 & 1)))
2260 Info->markPSInputEnabled(
2261 countTrailingZeros(Info->getPSInputAddr(), ZB_Undefined));
2262 }
2263 } else if (IsKernel) {
2264 assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX())((Info->hasWorkGroupIDX() && Info->hasWorkItemIDX
()) ? static_cast<void> (0) : __assert_fail ("Info->hasWorkGroupIDX() && Info->hasWorkItemIDX()"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2264, __PRETTY_FUNCTION__))
;
2265 } else {
2266 Splits.append(Ins.begin(), Ins.end());
2267 }
2268
2269 if (IsEntryFunc) {
2270 allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
2271 allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
2272 } else {
2273 // For the fixed ABI, pass workitem IDs in the last argument register.
2274 if (AMDGPUTargetMachine::EnableFixedFunctionABI)
2275 allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
2276 }
2277
2278 if (IsKernel) {
2279 analyzeFormalArgumentsCompute(CCInfo, Ins);
2280 } else {
2281 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg);
2282 CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
2283 }
2284
2285 SmallVector<SDValue, 16> Chains;
2286
2287 // FIXME: This is the minimum kernel argument alignment. We should improve
2288 // this to the maximum alignment of the arguments.
2289 //
2290 // FIXME: Alignment of explicit arguments totally broken with non-0 explicit
2291 // kern arg offset.
2292 const Align KernelArgBaseAlign = Align(16);
2293
2294 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
2295 const ISD::InputArg &Arg = Ins[i];
2296 if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
2297 InVals.push_back(DAG.getUNDEF(Arg.VT));
2298 continue;
2299 }
2300
2301 CCValAssign &VA = ArgLocs[ArgIdx++];
2302 MVT VT = VA.getLocVT();
2303
2304 if (IsEntryFunc && VA.isMemLoc()) {
2305 VT = Ins[i].VT;
2306 EVT MemVT = VA.getLocVT();
2307
2308 const uint64_t Offset = VA.getLocMemOffset();
2309 Align Alignment = commonAlignment(KernelArgBaseAlign, Offset);
2310
2311 if (Arg.Flags.isByRef()) {
2312 SDValue Ptr = lowerKernArgParameterPtr(DAG, DL, Chain, Offset);
2313
2314 const GCNTargetMachine &TM =
2315 static_cast<const GCNTargetMachine &>(getTargetMachine());
2316 if (!TM.isNoopAddrSpaceCast(AMDGPUAS::CONSTANT_ADDRESS,
2317 Arg.Flags.getPointerAddrSpace())) {
2318 Ptr = DAG.getAddrSpaceCast(DL, VT, Ptr, AMDGPUAS::CONSTANT_ADDRESS,
2319 Arg.Flags.getPointerAddrSpace());
2320 }
2321
2322 InVals.push_back(Ptr);
2323 continue;
2324 }
2325
2326 SDValue Arg = lowerKernargMemParameter(
2327 DAG, VT, MemVT, DL, Chain, Offset, Alignment, Ins[i].Flags.isSExt(), &Ins[i]);
2328 Chains.push_back(Arg.getValue(1));
2329
2330 auto *ParamTy =
2331 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
2332 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
2333 ParamTy && (ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
2334 ParamTy->getAddressSpace() == AMDGPUAS::REGION_ADDRESS)) {
2335 // On SI local pointers are just offsets into LDS, so they are always
2336 // less than 16-bits. On CI and newer they could potentially be
2337 // real pointers, so we can't guarantee their size.
2338 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
2339 DAG.getValueType(MVT::i16));
2340 }
2341
2342 InVals.push_back(Arg);
2343 continue;
2344 } else if (!IsEntryFunc && VA.isMemLoc()) {
2345 SDValue Val = lowerStackParameter(DAG, VA, DL, Chain, Arg);
2346 InVals.push_back(Val);
2347 if (!Arg.Flags.isByVal())
2348 Chains.push_back(Val.getValue(1));
2349 continue;
2350 }
2351
2352 assert(VA.isRegLoc() && "Parameter must be in a register!")((VA.isRegLoc() && "Parameter must be in a register!"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Parameter must be in a register!\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2352, __PRETTY_FUNCTION__))
;
2353
2354 Register Reg = VA.getLocReg();
2355 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2356 EVT ValVT = VA.getValVT();
2357
2358 Reg = MF.addLiveIn(Reg, RC);
2359 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
2360
2361 if (Arg.Flags.isSRet()) {
2362 // The return object should be reasonably addressable.
2363
2364 // FIXME: This helps when the return is a real sret. If it is a
2365 // automatically inserted sret (i.e. CanLowerReturn returns false), an
2366 // extra copy is inserted in SelectionDAGBuilder which obscures this.
2367 unsigned NumBits
2368 = 32 - getSubtarget()->getKnownHighZeroBitsForFrameIndex();
2369 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2370 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), NumBits)));
2371 }
2372
2373 // If this is an 8 or 16-bit value, it is really passed promoted
2374 // to 32 bits. Insert an assert[sz]ext to capture this, then
2375 // truncate to the right size.
2376 switch (VA.getLocInfo()) {
2377 case CCValAssign::Full:
2378 break;
2379 case CCValAssign::BCvt:
2380 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2381 break;
2382 case CCValAssign::SExt:
2383 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val,
2384 DAG.getValueType(ValVT));
2385 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2386 break;
2387 case CCValAssign::ZExt:
2388 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2389 DAG.getValueType(ValVT));
2390 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2391 break;
2392 case CCValAssign::AExt:
2393 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2394 break;
2395 default:
2396 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2396)
;
2397 }
2398
2399 InVals.push_back(Val);
2400 }
2401
2402 if (!IsEntryFunc && !AMDGPUTargetMachine::EnableFixedFunctionABI) {
2403 // Special inputs come after user arguments.
2404 allocateSpecialInputVGPRs(CCInfo, MF, *TRI, *Info);
2405 }
2406
2407 // Start adding system SGPRs.
2408 if (IsEntryFunc) {
2409 allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics);
2410 } else {
2411 CCInfo.AllocateReg(Info->getScratchRSrcReg());
2412 allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
2413 }
2414
2415 auto &ArgUsageInfo =
2416 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2417 ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
2418
2419 unsigned StackArgSize = CCInfo.getNextStackOffset();
2420 Info->setBytesInStackArgArea(StackArgSize);
2421
2422 return Chains.empty() ? Chain :
2423 DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
2424}
2425
2426// TODO: If return values can't fit in registers, we should return as many as
2427// possible in registers before passing on stack.
2428bool SITargetLowering::CanLowerReturn(
2429 CallingConv::ID CallConv,
2430 MachineFunction &MF, bool IsVarArg,
2431 const SmallVectorImpl<ISD::OutputArg> &Outs,
2432 LLVMContext &Context) const {
2433 // Replacing returns with sret/stack usage doesn't make sense for shaders.
2434 // FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
2435 // for shaders. Vector types should be explicitly handled by CC.
2436 if (AMDGPU::isEntryFunctionCC(CallConv))
2437 return true;
2438
2439 SmallVector<CCValAssign, 16> RVLocs;
2440 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2441 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
2442}
2443
2444SDValue
2445SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2446 bool isVarArg,
2447 const SmallVectorImpl<ISD::OutputArg> &Outs,
2448 const SmallVectorImpl<SDValue> &OutVals,
2449 const SDLoc &DL, SelectionDAG &DAG) const {
2450 MachineFunction &MF = DAG.getMachineFunction();
2451 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2452
2453 if (AMDGPU::isKernel(CallConv)) {
2454 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
2455 OutVals, DL, DAG);
2456 }
2457
2458 bool IsShader = AMDGPU::isShader(CallConv);
2459
2460 Info->setIfReturnsVoid(Outs.empty());
2461 bool IsWaveEnd = Info->returnsVoid() && IsShader;
2462
2463 // CCValAssign - represent the assignment of the return value to a location.
2464 SmallVector<CCValAssign, 48> RVLocs;
2465 SmallVector<ISD::OutputArg, 48> Splits;
2466
2467 // CCState - Info about the registers and stack slots.
2468 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2469 *DAG.getContext());
2470
2471 // Analyze outgoing return values.
2472 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2473
2474 SDValue Flag;
2475 SmallVector<SDValue, 48> RetOps;
2476 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2477
2478 // Add return address for callable functions.
2479 if (!Info->isEntryFunction()) {
2480 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2481 SDValue ReturnAddrReg = CreateLiveInRegister(
2482 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2483
2484 SDValue ReturnAddrVirtualReg = DAG.getRegister(
2485 MF.getRegInfo().createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass),
2486 MVT::i64);
2487 Chain =
2488 DAG.getCopyToReg(Chain, DL, ReturnAddrVirtualReg, ReturnAddrReg, Flag);
2489 Flag = Chain.getValue(1);
2490 RetOps.push_back(ReturnAddrVirtualReg);
2491 }
2492
2493 // Copy the result values into the output registers.
2494 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E;
2495 ++I, ++RealRVLocIdx) {
2496 CCValAssign &VA = RVLocs[I];
2497 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2497, __PRETTY_FUNCTION__))
;
2498 // TODO: Partially return in registers if return values don't fit.
2499 SDValue Arg = OutVals[RealRVLocIdx];
2500
2501 // Copied from other backends.
2502 switch (VA.getLocInfo()) {
2503 case CCValAssign::Full:
2504 break;
2505 case CCValAssign::BCvt:
2506 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2507 break;
2508 case CCValAssign::SExt:
2509 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2510 break;
2511 case CCValAssign::ZExt:
2512 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2513 break;
2514 case CCValAssign::AExt:
2515 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2516 break;
2517 default:
2518 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2518)
;
2519 }
2520
2521 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2522 Flag = Chain.getValue(1);
2523 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2524 }
2525
2526 // FIXME: Does sret work properly?
2527 if (!Info->isEntryFunction()) {
2528 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2529 const MCPhysReg *I =
2530 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2531 if (I) {
2532 for (; *I; ++I) {
2533 if (AMDGPU::SReg_64RegClass.contains(*I))
2534 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2535 else if (AMDGPU::SReg_32RegClass.contains(*I))
2536 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2537 else
2538 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2538)
;
2539 }
2540 }
2541 }
2542
2543 // Update chain and glue.
2544 RetOps[0] = Chain;
2545 if (Flag.getNode())
2546 RetOps.push_back(Flag);
2547
2548 unsigned Opc = AMDGPUISD::ENDPGM;
2549 if (!IsWaveEnd)
2550 Opc = IsShader ? AMDGPUISD::RETURN_TO_EPILOG : AMDGPUISD::RET_FLAG;
2551 return DAG.getNode(Opc, DL, MVT::Other, RetOps);
2552}
2553
2554SDValue SITargetLowering::LowerCallResult(
2555 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2556 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2557 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool IsThisReturn,
2558 SDValue ThisVal) const {
2559 CCAssignFn *RetCC = CCAssignFnForReturn(CallConv, IsVarArg);
2560
2561 // Assign locations to each value returned by this call.
2562 SmallVector<CCValAssign, 16> RVLocs;
2563 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2564 *DAG.getContext());
2565 CCInfo.AnalyzeCallResult(Ins, RetCC);
2566
2567 // Copy all of the result registers out of their specified physreg.
2568 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2569 CCValAssign VA = RVLocs[i];
2570 SDValue Val;
2571
2572 if (VA.isRegLoc()) {
2573 Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2574 Chain = Val.getValue(1);
2575 InFlag = Val.getValue(2);
2576 } else if (VA.isMemLoc()) {
2577 report_fatal_error("TODO: return values in memory");
2578 } else
2579 llvm_unreachable("unknown argument location type")::llvm::llvm_unreachable_internal("unknown argument location type"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2579)
;
2580
2581 switch (VA.getLocInfo()) {
2582 case CCValAssign::Full:
2583 break;
2584 case CCValAssign::BCvt:
2585 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2586 break;
2587 case CCValAssign::ZExt:
2588 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2589 DAG.getValueType(VA.getValVT()));
2590 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2591 break;
2592 case CCValAssign::SExt:
2593 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2594 DAG.getValueType(VA.getValVT()));
2595 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2596 break;
2597 case CCValAssign::AExt:
2598 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2599 break;
2600 default:
2601 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2601)
;
2602 }
2603
2604 InVals.push_back(Val);
2605 }
2606
2607 return Chain;
2608}
2609
2610// Add code to pass special inputs required depending on used features separate
2611// from the explicit user arguments present in the IR.
2612void SITargetLowering::passSpecialInputs(
2613 CallLoweringInfo &CLI,
2614 CCState &CCInfo,
2615 const SIMachineFunctionInfo &Info,
2616 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
2617 SmallVectorImpl<SDValue> &MemOpChains,
2618 SDValue Chain) const {
2619 // If we don't have a call site, this was a call inserted by
2620 // legalization. These can never use special inputs.
2621 if (!CLI.CB)
2622 return;
2623
2624 SelectionDAG &DAG = CLI.DAG;
2625 const SDLoc &DL = CLI.DL;
2626
2627 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2628 const AMDGPUFunctionArgInfo &CallerArgInfo = Info.getArgInfo();
2629
2630 const AMDGPUFunctionArgInfo *CalleeArgInfo
2631 = &AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
2632 if (const Function *CalleeFunc = CLI.CB->getCalledFunction()) {
2633 auto &ArgUsageInfo =
2634 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2635 CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
2636 }
2637
2638 // TODO: Unify with private memory register handling. This is complicated by
2639 // the fact that at least in kernels, the input argument is not necessarily
2640 // in the same location as the input.
2641 AMDGPUFunctionArgInfo::PreloadedValue InputRegs[] = {
2642 AMDGPUFunctionArgInfo::DISPATCH_PTR,
2643 AMDGPUFunctionArgInfo::QUEUE_PTR,
2644 AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR,
2645 AMDGPUFunctionArgInfo::DISPATCH_ID,
2646 AMDGPUFunctionArgInfo::WORKGROUP_ID_X,
2647 AMDGPUFunctionArgInfo::WORKGROUP_ID_Y,
2648 AMDGPUFunctionArgInfo::WORKGROUP_ID_Z
2649 };
2650
2651 for (auto InputID : InputRegs) {
2652 const ArgDescriptor *OutgoingArg;
2653 const TargetRegisterClass *ArgRC;
2654 LLT ArgTy;
2655
2656 std::tie(OutgoingArg, ArgRC, ArgTy) =
2657 CalleeArgInfo->getPreloadedValue(InputID);
2658 if (!OutgoingArg)
2659 continue;
2660
2661 const ArgDescriptor *IncomingArg;
2662 const TargetRegisterClass *IncomingArgRC;
2663 LLT Ty;
2664 std::tie(IncomingArg, IncomingArgRC, Ty) =
2665 CallerArgInfo.getPreloadedValue(InputID);
2666 assert(IncomingArgRC == ArgRC)((IncomingArgRC == ArgRC) ? static_cast<void> (0) : __assert_fail
("IncomingArgRC == ArgRC", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2666, __PRETTY_FUNCTION__))
;
2667
2668 // All special arguments are ints for now.
2669 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;
2670 SDValue InputReg;
2671
2672 if (IncomingArg) {
2673 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg);
2674 } else {
2675 // The implicit arg ptr is special because it doesn't have a corresponding
2676 // input for kernels, and is computed from the kernarg segment pointer.
2677 assert(InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR)((InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR) ? static_cast
<void> (0) : __assert_fail ("InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2677, __PRETTY_FUNCTION__))
;
2678 InputReg = getImplicitArgPtr(DAG, DL);
2679 }
2680
2681 if (OutgoingArg->isRegister()) {
2682 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2683 if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
2684 report_fatal_error("failed to allocate implicit input argument");
2685 } else {
2686 unsigned SpecialArgOffset =
2687 CCInfo.AllocateStack(ArgVT.getStoreSize(), Align(4));
2688 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2689 SpecialArgOffset);
2690 MemOpChains.push_back(ArgStore);
2691 }
2692 }
2693
2694 // Pack workitem IDs into a single register or pass it as is if already
2695 // packed.
2696 const ArgDescriptor *OutgoingArg;
2697 const TargetRegisterClass *ArgRC;
2698 LLT Ty;
2699
2700 std::tie(OutgoingArg, ArgRC, Ty) =
2701 CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
2702 if (!OutgoingArg)
2703 std::tie(OutgoingArg, ArgRC, Ty) =
2704 CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
2705 if (!OutgoingArg)
2706 std::tie(OutgoingArg, ArgRC, Ty) =
2707 CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
2708 if (!OutgoingArg)
2709 return;
2710
2711 const ArgDescriptor *IncomingArgX = std::get<0>(
2712 CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X));
2713 const ArgDescriptor *IncomingArgY = std::get<0>(
2714 CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y));
2715 const ArgDescriptor *IncomingArgZ = std::get<0>(
2716 CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z));
2717
2718 SDValue InputReg;
2719 SDLoc SL;
2720
2721 // If incoming ids are not packed we need to pack them.
2722 if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo->WorkItemIDX)
2723 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX);
2724
2725 if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo->WorkItemIDY) {
2726 SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY);
2727 Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y,
2728 DAG.getShiftAmountConstant(10, MVT::i32, SL));
2729 InputReg = InputReg.getNode() ?
2730 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y;
2731 }
2732
2733 if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo->WorkItemIDZ) {
2734 SDValue Z = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgZ);
2735 Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z,
2736 DAG.getShiftAmountConstant(20, MVT::i32, SL));
2737 InputReg = InputReg.getNode() ?
2738 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Z) : Z;
2739 }
2740
2741 if (!InputReg.getNode()) {
2742 // Workitem ids are already packed, any of present incoming arguments
2743 // will carry all required fields.
2744 ArgDescriptor IncomingArg = ArgDescriptor::createArg(
2745 IncomingArgX ? *IncomingArgX :
2746 IncomingArgY ? *IncomingArgY :
2747 *IncomingArgZ, ~0u);
2748 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, IncomingArg);
2749 }
2750
2751 if (OutgoingArg->isRegister()) {
2752 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2753 CCInfo.AllocateReg(OutgoingArg->getRegister());
2754 } else {
2755 unsigned SpecialArgOffset = CCInfo.AllocateStack(4, Align(4));
2756 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2757 SpecialArgOffset);
2758 MemOpChains.push_back(ArgStore);
2759 }
2760}
2761
2762static bool canGuaranteeTCO(CallingConv::ID CC) {
2763 return CC == CallingConv::Fast;
2764}
2765
2766/// Return true if we might ever do TCO for calls with this calling convention.
2767static bool mayTailCallThisCC(CallingConv::ID CC) {
2768 switch (CC) {
2769 case CallingConv::C:
2770 return true;
2771 default:
2772 return canGuaranteeTCO(CC);
2773 }
2774}
2775
2776bool SITargetLowering::isEligibleForTailCallOptimization(
2777 SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
2778 const SmallVectorImpl<ISD::OutputArg> &Outs,
2779 const SmallVectorImpl<SDValue> &OutVals,
2780 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2781 if (!mayTailCallThisCC(CalleeCC))
2782 return false;
2783
2784 MachineFunction &MF = DAG.getMachineFunction();
2785 const Function &CallerF = MF.getFunction();
2786 CallingConv::ID CallerCC = CallerF.getCallingConv();
2787 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2788 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2789
2790 // Kernels aren't callable, and don't have a live in return address so it
2791 // doesn't make sense to do a tail call with entry functions.
2792 if (!CallerPreserved)
2793 return false;
2794
2795 bool CCMatch = CallerCC == CalleeCC;
2796
2797 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
2798 if (canGuaranteeTCO(CalleeCC) && CCMatch)
2799 return true;
2800 return false;
2801 }
2802
2803 // TODO: Can we handle var args?
2804 if (IsVarArg)
2805 return false;
2806
2807 for (const Argument &Arg : CallerF.args()) {
2808 if (Arg.hasByValAttr())
2809 return false;
2810 }
2811
2812 LLVMContext &Ctx = *DAG.getContext();
2813
2814 // Check that the call results are passed in the same way.
2815 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, Ctx, Ins,
2816 CCAssignFnForCall(CalleeCC, IsVarArg),
2817 CCAssignFnForCall(CallerCC, IsVarArg)))
2818 return false;
2819
2820 // The callee has to preserve all registers the caller needs to preserve.
2821 if (!CCMatch) {
2822 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2823 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2824 return false;
2825 }
2826
2827 // Nothing more to check if the callee is taking no arguments.
2828 if (Outs.empty())
2829 return true;
2830
2831 SmallVector<CCValAssign, 16> ArgLocs;
2832 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
2833
2834 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
2835
2836 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
2837 // If the stack arguments for this call do not fit into our own save area then
2838 // the call cannot be made tail.
2839 // TODO: Is this really necessary?
2840 if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
2841 return false;
2842
2843 const MachineRegisterInfo &MRI = MF.getRegInfo();
2844 return parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals);
2845}
2846
2847bool SITargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2848 if (!CI->isTailCall())
2849 return false;
2850
2851 const Function *ParentFn = CI->getParent()->getParent();
2852 if (AMDGPU::isEntryFunctionCC(ParentFn->getCallingConv()))
2853 return false;
2854 return true;
2855}
2856
2857// The wave scratch offset register is used as the global base pointer.
2858SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
2859 SmallVectorImpl<SDValue> &InVals) const {
2860 SelectionDAG &DAG = CLI.DAG;
2861 const SDLoc &DL = CLI.DL;
2862 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2863 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2864 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2865 SDValue Chain = CLI.Chain;
2866 SDValue Callee = CLI.Callee;
2867 bool &IsTailCall = CLI.IsTailCall;
2868 CallingConv::ID CallConv = CLI.CallConv;
2869 bool IsVarArg = CLI.IsVarArg;
2870 bool IsSibCall = false;
2871 bool IsThisReturn = false;
2872 MachineFunction &MF = DAG.getMachineFunction();
2873
2874 if (Callee.isUndef() || isNullConstant(Callee)) {
2875 if (!CLI.IsTailCall) {
2876 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
2877 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
2878 }
2879
2880 return Chain;
2881 }
2882
2883 if (IsVarArg) {
2884 return lowerUnhandledCall(CLI, InVals,
2885 "unsupported call to variadic function ");
2886 }
2887
2888 if (!CLI.CB)
2889 report_fatal_error("unsupported libcall legalization");
2890
2891 if (!AMDGPUTargetMachine::EnableFixedFunctionABI &&
2892 !CLI.CB->getCalledFunction() && CallConv != CallingConv::AMDGPU_Gfx) {
2893 return lowerUnhandledCall(CLI, InVals,
2894 "unsupported indirect call to function ");
2895 }
2896
2897 if (IsTailCall && MF.getTarget().Options.GuaranteedTailCallOpt) {
2898 return lowerUnhandledCall(CLI, InVals,
2899 "unsupported required tail call to function ");
2900 }
2901
2902 if (AMDGPU::isShader(CallConv)) {
2903 // Note the issue is with the CC of the called function, not of the call
2904 // itself.
2905 return lowerUnhandledCall(CLI, InVals,
2906 "unsupported call to a shader function ");
2907 }
2908
2909 if (AMDGPU::isShader(MF.getFunction().getCallingConv()) &&
2910 CallConv != CallingConv::AMDGPU_Gfx) {
2911 // Only allow calls with specific calling conventions.
2912 return lowerUnhandledCall(CLI, InVals,
2913 "unsupported calling convention for call from "
2914 "graphics shader of function ");
2915 }
2916
2917 if (IsTailCall) {
2918 IsTailCall = isEligibleForTailCallOptimization(
2919 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
2920 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) {
2921 report_fatal_error("failed to perform tail call elimination on a call "
2922 "site marked musttail");
2923 }
2924
2925 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2926
2927 // A sibling call is one where we're under the usual C ABI and not planning
2928 // to change that but can still do a tail call:
2929 if (!TailCallOpt && IsTailCall)
2930 IsSibCall = true;
2931
2932 if (IsTailCall)
2933 ++NumTailCalls;
2934 }
2935
2936 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2937 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2938 SmallVector<SDValue, 8> MemOpChains;
2939
2940 // Analyze operands of the call, assigning locations to each operand.
2941 SmallVector<CCValAssign, 16> ArgLocs;
2942 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
2943 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, IsVarArg);
2944
2945 if (AMDGPUTargetMachine::EnableFixedFunctionABI &&
2946 CallConv != CallingConv::AMDGPU_Gfx) {
2947 // With a fixed ABI, allocate fixed registers before user arguments.
2948 passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
2949 }
2950
2951 CCInfo.AnalyzeCallOperands(Outs, AssignFn);
2952
2953 // Get a count of how many bytes are to be pushed on the stack.
2954 unsigned NumBytes = CCInfo.getNextStackOffset();
2955
2956 if (IsSibCall) {
2957 // Since we're not changing the ABI to make this a tail call, the memory
2958 // operands are already available in the caller's incoming argument space.
2959 NumBytes = 0;
2960 }
2961
2962 // FPDiff is the byte offset of the call's argument area from the callee's.
2963 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2964 // by this amount for a tail call. In a sibling call it must be 0 because the
2965 // caller will deallocate the entire stack and the callee still expects its
2966 // arguments to begin at SP+0. Completely unused for non-tail calls.
2967 int32_t FPDiff = 0;
2968 MachineFrameInfo &MFI = MF.getFrameInfo();
2969
2970 // Adjust the stack pointer for the new arguments...
2971 // These operations are automatically eliminated by the prolog/epilog pass
2972 if (!IsSibCall) {
2973 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
2974
2975 if (!Subtarget->enableFlatScratch()) {
2976 SmallVector<SDValue, 4> CopyFromChains;
2977
2978 // In the HSA case, this should be an identity copy.
2979 SDValue ScratchRSrcReg
2980 = DAG.getCopyFromReg(Chain, DL, Info->getScratchRSrcReg(), MVT::v4i32);
2981 RegsToPass.emplace_back(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
2982 CopyFromChains.push_back(ScratchRSrcReg.getValue(1));
2983 Chain = DAG.getTokenFactor(DL, CopyFromChains);
2984 }
2985 }
2986
2987 MVT PtrVT = MVT::i32;
2988
2989 // Walk the register/memloc assignments, inserting copies/loads.
2990 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2991 CCValAssign &VA = ArgLocs[i];
2992 SDValue Arg = OutVals[i];
2993
2994 // Promote the value if needed.
2995 switch (VA.getLocInfo()) {
2996 case CCValAssign::Full:
2997 break;
2998 case CCValAssign::BCvt:
2999 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3000 break;
3001 case CCValAssign::ZExt:
3002 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3003 break;
3004 case CCValAssign::SExt:
3005 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
3006 break;
3007 case CCValAssign::AExt:
3008 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
3009 break;
3010 case CCValAssign::FPExt:
3011 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
3012 break;
3013 default:
3014 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3014)
;
3015 }
3016
3017 if (VA.isRegLoc()) {
3018 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3019 } else {
3020 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3020, __PRETTY_FUNCTION__))
;
3021
3022 SDValue DstAddr;
3023 MachinePointerInfo DstInfo;
3024
3025 unsigned LocMemOffset = VA.getLocMemOffset();
3026 int32_t Offset = LocMemOffset;
3027
3028 SDValue PtrOff = DAG.getConstant(Offset, DL, PtrVT);
3029 MaybeAlign Alignment;
3030
3031 if (IsTailCall) {
3032 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3033 unsigned OpSize = Flags.isByVal() ?
3034 Flags.getByValSize() : VA.getValVT().getStoreSize();
3035
3036 // FIXME: We can have better than the minimum byval required alignment.
3037 Alignment =
3038 Flags.isByVal()
3039 ? Flags.getNonZeroByValAlign()
3040 : commonAlignment(Subtarget->getStackAlignment(), Offset);
3041
3042 Offset = Offset + FPDiff;
3043 int FI = MFI.CreateFixedObject(OpSize, Offset, true);
3044
3045 DstAddr = DAG.getFrameIndex(FI, PtrVT);
3046 DstInfo = MachinePointerInfo::getFixedStack(MF, FI);
3047
3048 // Make sure any stack arguments overlapping with where we're storing
3049 // are loaded before this eventual operation. Otherwise they'll be
3050 // clobbered.
3051
3052 // FIXME: Why is this really necessary? This seems to just result in a
3053 // lot of code to copy the stack and write them back to the same
3054 // locations, which are supposed to be immutable?
3055 Chain = addTokenForArgument(Chain, DAG, MFI, FI);
3056 } else {
3057 DstAddr = PtrOff;
3058 DstInfo = MachinePointerInfo::getStack(MF, LocMemOffset);
3059 Alignment =
3060 commonAlignment(Subtarget->getStackAlignment(), LocMemOffset);
3061 }
3062
3063 if (Outs[i].Flags.isByVal()) {
3064 SDValue SizeNode =
3065 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32);
3066 SDValue Cpy =
3067 DAG.getMemcpy(Chain, DL, DstAddr, Arg, SizeNode,
3068 Outs[i].Flags.getNonZeroByValAlign(),
3069 /*isVol = */ false, /*AlwaysInline = */ true,
3070 /*isTailCall = */ false, DstInfo,
3071 MachinePointerInfo(AMDGPUAS::PRIVATE_ADDRESS));
3072
3073 MemOpChains.push_back(Cpy);
3074 } else {
3075 SDValue Store =
3076 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, Alignment);
3077 MemOpChains.push_back(Store);
3078 }
3079 }
3080 }
3081
3082 if (!AMDGPUTargetMachine::EnableFixedFunctionABI &&
3083 CallConv != CallingConv::AMDGPU_Gfx) {
3084 // Copy special input registers after user input arguments.
3085 passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
3086 }
3087
3088 if (!MemOpChains.empty())
3089 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3090
3091 // Build a sequence of copy-to-reg nodes chained together with token chain
3092 // and flag operands which copy the outgoing args into the appropriate regs.
3093 SDValue InFlag;
3094 for (auto &RegToPass : RegsToPass) {
3095 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
3096 RegToPass.second, InFlag);
3097 InFlag = Chain.getValue(1);
3098 }
3099
3100
3101 SDValue PhysReturnAddrReg;
3102 if (IsTailCall) {
3103 // Since the return is being combined with the call, we need to pass on the
3104 // return address.
3105
3106 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
3107 SDValue ReturnAddrReg = CreateLiveInRegister(
3108 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
3109
3110 PhysReturnAddrReg = DAG.getRegister(TRI->getReturnAddressReg(MF),
3111 MVT::i64);
3112 Chain = DAG.getCopyToReg(Chain, DL, PhysReturnAddrReg, ReturnAddrReg, InFlag);
3113 InFlag = Chain.getValue(1);
3114 }
3115
3116 // We don't usually want to end the call-sequence here because we would tidy
3117 // the frame up *after* the call, however in the ABI-changing tail-call case
3118 // we've carefully laid out the parameters so that when sp is reset they'll be
3119 // in the correct location.
3120 if (IsTailCall && !IsSibCall) {
3121 Chain = DAG.getCALLSEQ_END(Chain,
3122 DAG.getTargetConstant(NumBytes, DL, MVT::i32),
3123 DAG.getTargetConstant(0, DL, MVT::i32),
3124 InFlag, DL);
3125 InFlag = Chain.getValue(1);
3126 }
3127
3128 std::vector<SDValue> Ops;
3129 Ops.push_back(Chain);
3130 Ops.push_back(Callee);
3131 // Add a redundant copy of the callee global which will not be legalized, as
3132 // we need direct access to the callee later.
3133 if (GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(Callee)) {
3134 const GlobalValue *GV = GSD->getGlobal();
3135 Ops.push_back(DAG.getTargetGlobalAddress(GV, DL, MVT::i64));
3136 } else {
3137 Ops.push_back(DAG.getTargetConstant(0, DL, MVT::i64));
3138 }
3139
3140 if (IsTailCall) {
3141 // Each tail call may have to adjust the stack by a different amount, so
3142 // this information must travel along with the operation for eventual
3143 // consumption by emitEpilogue.
3144 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
3145
3146 Ops.push_back(PhysReturnAddrReg);
3147 }
3148
3149 // Add argument registers to the end of the list so that they are known live
3150 // into the call.
3151 for (auto &RegToPass : RegsToPass) {
3152 Ops.push_back(DAG.getRegister(RegToPass.first,
3153 RegToPass.second.getValueType()));
3154 }
3155
3156 // Add a register mask operand representing the call-preserved registers.
3157
3158 auto *TRI = static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
3159 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3160 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3160, __PRETTY_FUNCTION__))
;
3161 Ops.push_back(DAG.getRegisterMask(Mask));
3162
3163 if (InFlag.getNode())
3164 Ops.push_back(InFlag);
3165
3166 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3167
3168 // If we're doing a tall call, use a TC_RETURN here rather than an
3169 // actual call instruction.
3170 if (IsTailCall) {
3171 MFI.setHasTailCall();
3172 return DAG.getNode(AMDGPUISD::TC_RETURN, DL, NodeTys, Ops);
3173 }
3174
3175 // Returns a chain and a flag for retval copy to use.
3176 SDValue Call = DAG.getNode(AMDGPUISD::CALL, DL, NodeTys, Ops);
3177 Chain = Call.getValue(0);
3178 InFlag = Call.getValue(1);
3179
3180 uint64_t CalleePopBytes = NumBytes;
3181 Chain = DAG.getCALLSEQ_END(Chain, DAG.getTargetConstant(0, DL, MVT::i32),
3182 DAG.getTargetConstant(CalleePopBytes, DL, MVT::i32),
3183 InFlag, DL);
3184 if (!Ins.empty())
3185 InFlag = Chain.getValue(1);
3186
3187 // Handle result values, copying them out of physregs into vregs that we
3188 // return.
3189 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3190 InVals, IsThisReturn,
3191 IsThisReturn ? OutVals[0] : SDValue());
3192}
3193
3194// This is identical to the default implementation in ExpandDYNAMIC_STACKALLOC,
3195// except for applying the wave size scale to the increment amount.
3196SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(
3197 SDValue Op, SelectionDAG &DAG) const {
3198 const MachineFunction &MF = DAG.getMachineFunction();
3199 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
3200
3201 SDLoc dl(Op);
3202 EVT VT = Op.getValueType();
3203 SDValue Tmp1 = Op;
3204 SDValue Tmp2 = Op.getValue(1);
3205 SDValue Tmp3 = Op.getOperand(2);
3206 SDValue Chain = Tmp1.getOperand(0);
3207
3208 Register SPReg = Info->getStackPtrOffsetReg();
3209
3210 // Chain the dynamic stack allocation so that it doesn't modify the stack
3211 // pointer when other instructions are using the stack.
3212 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
3213
3214 SDValue Size = Tmp2.getOperand(1);
3215 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
3216 Chain = SP.getValue(1);
3217 MaybeAlign Alignment = cast<ConstantSDNode>(Tmp3)->getMaybeAlignValue();
3218 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
3219 const TargetFrameLowering *TFL = ST.getFrameLowering();
3220 unsigned Opc =
3221 TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp ?
3222 ISD::ADD : ISD::SUB;
3223
3224 SDValue ScaledSize = DAG.getNode(
3225 ISD::SHL, dl, VT, Size,
3226 DAG.getConstant(ST.getWavefrontSizeLog2(), dl, MVT::i32));
3227
3228 Align StackAlign = TFL->getStackAlign();
3229 Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value
3230 if (Alignment && *Alignment > StackAlign) {
3231 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
3232 DAG.getConstant(-(uint64_t)Alignment->value()
3233 << ST.getWavefrontSizeLog2(),
3234 dl, VT));
3235 }
3236
3237 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
3238 Tmp2 = DAG.getCALLSEQ_END(
3239 Chain, DAG.getIntPtrConstant(0, dl, true),
3240 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
3241
3242 return DAG.getMergeValues({Tmp1, Tmp2}, dl);
3243}
3244
3245SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3246 SelectionDAG &DAG) const {
3247 // We only handle constant sizes here to allow non-entry block, static sized
3248 // allocas. A truly dynamic value is more difficult to support because we
3249 // don't know if the size value is uniform or not. If the size isn't uniform,
3250 // we would need to do a wave reduction to get the maximum size to know how
3251 // much to increment the uniform stack pointer.
3252 SDValue Size = Op.getOperand(1);
3253 if (isa<ConstantSDNode>(Size))
3254 return lowerDYNAMIC_STACKALLOCImpl(Op, DAG); // Use "generic" expansion.
3255
3256 return AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(Op, DAG);
3257}
3258
3259Register SITargetLowering::getRegisterByName(const char* RegName, LLT VT,
3260 const MachineFunction &MF) const {
3261 Register Reg = StringSwitch<Register>(RegName)
3262 .Case("m0", AMDGPU::M0)
3263 .Case("exec", AMDGPU::EXEC)
3264 .Case("exec_lo", AMDGPU::EXEC_LO)
3265 .Case("exec_hi", AMDGPU::EXEC_HI)
3266 .Case("flat_scratch", AMDGPU::FLAT_SCR)
3267 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
3268 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
3269 .Default(Register());
3270
3271 if (Reg == AMDGPU::NoRegister) {
3272 report_fatal_error(Twine("invalid register name \""
3273 + StringRef(RegName) + "\"."));
3274
3275 }
3276
3277 if (!Subtarget->hasFlatScrRegister() &&
3278 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
3279 report_fatal_error(Twine("invalid register \""
3280 + StringRef(RegName) + "\" for subtarget."));
3281 }
3282
3283 switch (Reg) {
3284 case AMDGPU::M0:
3285 case AMDGPU::EXEC_LO:
3286 case AMDGPU::EXEC_HI:
3287 case AMDGPU::FLAT_SCR_LO:
3288 case AMDGPU::FLAT_SCR_HI:
3289 if (VT.getSizeInBits() == 32)
3290 return Reg;
3291 break;
3292 case AMDGPU::EXEC:
3293 case AMDGPU::FLAT_SCR:
3294 if (VT.getSizeInBits() == 64)
3295 return Reg;
3296 break;
3297 default:
3298 llvm_unreachable("missing register type checking")::llvm::llvm_unreachable_internal("missing register type checking"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3298)
;
3299 }
3300
3301 report_fatal_error(Twine("invalid type for register \""
3302 + StringRef(RegName) + "\"."));
3303}
3304
3305// If kill is not the last instruction, split the block so kill is always a
3306// proper terminator.
3307MachineBasicBlock *
3308SITargetLowering::splitKillBlock(MachineInstr &MI,
3309 MachineBasicBlock *BB) const {
3310 MachineBasicBlock *SplitBB = BB->splitAt(MI, false /*UpdateLiveIns*/);
3311 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3312 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
3313 return SplitBB;
3314}
3315
3316// Split block \p MBB at \p MI, as to insert a loop. If \p InstInLoop is true,
3317// \p MI will be the only instruction in the loop body block. Otherwise, it will
3318// be the first instruction in the remainder block.
3319//
3320/// \returns { LoopBody, Remainder }
3321static std::pair<MachineBasicBlock *, MachineBasicBlock *>
3322splitBlockForLoop(MachineInstr &MI, MachineBasicBlock &MBB, bool InstInLoop) {
3323 MachineFunction *MF = MBB.getParent();
3324 MachineBasicBlock::iterator I(&MI);
3325
3326 // To insert the loop we need to split the block. Move everything after this
3327 // point to a new block, and insert a new empty block between the two.
3328 MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
3329 MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
3330 MachineFunction::iterator MBBI(MBB);
3331 ++MBBI;
3332
3333 MF->insert(MBBI, LoopBB);
3334 MF->insert(MBBI, RemainderBB);
3335
3336 LoopBB->addSuccessor(LoopBB);
3337 LoopBB->addSuccessor(RemainderBB);
3338
3339 // Move the rest of the block into a new block.
3340 RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
3341
3342 if (InstInLoop) {
3343 auto Next = std::next(I);
3344
3345 // Move instruction to loop body.
3346 LoopBB->splice(LoopBB->begin(), &MBB, I, Next);
3347
3348 // Move the rest of the block.
3349 RemainderBB->splice(RemainderBB->begin(), &MBB, Next, MBB.end());
3350 } else {
3351 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
3352 }
3353
3354 MBB.addSuccessor(LoopBB);
3355
3356 return std::make_pair(LoopBB, RemainderBB);
3357}
3358
3359/// Insert \p MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
3360void SITargetLowering::bundleInstWithWaitcnt(MachineInstr &MI) const {
3361 MachineBasicBlock *MBB = MI.getParent();
3362 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3363 auto I = MI.getIterator();
3364 auto E = std::next(I);
3365
3366 BuildMI(*MBB, E, MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
3367 .addImm(0);
3368
3369 MIBundleBuilder Bundler(*MBB, I, E);
3370 finalizeBundle(*MBB, Bundler.begin());
3371}
3372
3373MachineBasicBlock *
3374SITargetLowering::emitGWSMemViolTestLoop(MachineInstr &MI,
3375 MachineBasicBlock *BB) const {
3376 const DebugLoc &DL = MI.getDebugLoc();
3377
3378 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3379
3380 MachineBasicBlock *LoopBB;
3381 MachineBasicBlock *RemainderBB;
3382 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3383
3384 // Apparently kill flags are only valid if the def is in the same block?
3385 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0))
3386 Src->setIsKill(false);
3387
3388 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, *BB, true);
3389
3390 MachineBasicBlock::iterator I = LoopBB->end();
3391
3392 const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg(
3393 AMDGPU::Hwreg::ID_TRAPSTS, AMDGPU::Hwreg::OFFSET_MEM_VIOL, 1);
3394
3395 // Clear TRAP_STS.MEM_VIOL
3396 BuildMI(*LoopBB, LoopBB->begin(), DL, TII->get(AMDGPU::S_SETREG_IMM32_B32))
3397 .addImm(0)
3398 .addImm(EncodedReg);
3399
3400 bundleInstWithWaitcnt(MI);
3401
3402 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3403
3404 // Load and check TRAP_STS.MEM_VIOL
3405 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), Reg)
3406 .addImm(EncodedReg);
3407
3408 // FIXME: Do we need to use an isel pseudo that may clobber scc?
3409 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32))
3410 .addReg(Reg, RegState::Kill)
3411 .addImm(0);
3412 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3413 .addMBB(LoopBB);
3414
3415 return RemainderBB;
3416}
3417
3418// Do a v_movrels_b32 or v_movreld_b32 for each unique value of \p IdxReg in the
3419// wavefront. If the value is uniform and just happens to be in a VGPR, this
3420// will only do one iteration. In the worst case, this will loop 64 times.
3421//
3422// TODO: Just use v_readlane_b32 if we know the VGPR has a uniform value.
3423static MachineBasicBlock::iterator
3424emitLoadM0FromVGPRLoop(const SIInstrInfo *TII, MachineRegisterInfo &MRI,
3425 MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB,
3426 const DebugLoc &DL, const MachineOperand &Idx,
3427 unsigned InitReg, unsigned ResultReg, unsigned PhiReg,
3428 unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode,
3429 Register &SGPRIdxReg) {
3430
3431 MachineFunction *MF = OrigBB.getParent();
3432 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3433 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3434 MachineBasicBlock::iterator I = LoopBB.begin();
3435
3436 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3437 Register PhiExec = MRI.createVirtualRegister(BoolRC);
3438 Register NewExec = MRI.createVirtualRegister(BoolRC);
3439 Register CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3440 Register CondReg = MRI.createVirtualRegister(BoolRC);
3441
3442 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
3443 .addReg(InitReg)
3444 .addMBB(&OrigBB)
3445 .addReg(ResultReg)
3446 .addMBB(&LoopBB);
3447
3448 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
3449 .addReg(InitSaveExecReg)
3450 .addMBB(&OrigBB)
3451 .addReg(NewExec)
3452 .addMBB(&LoopBB);
3453
3454 // Read the next variant <- also loop target.
3455 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
3456 .addReg(Idx.getReg(), getUndefRegState(Idx.isUndef()));
3457
3458 // Compare the just read M0 value to all possible Idx values.
3459 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
3460 .addReg(CurrentIdxReg)
3461 .addReg(Idx.getReg(), 0, Idx.getSubReg());
3462
3463 // Update EXEC, save the original EXEC value to VCC.
3464 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
3465 : AMDGPU::S_AND_SAVEEXEC_B64),
3466 NewExec)
3467 .addReg(CondReg, RegState::Kill);
3468
3469 MRI.setSimpleHint(NewExec, CondReg);
3470
3471 if (UseGPRIdxMode) {
3472 if (Offset == 0) {
3473 SGPRIdxReg = CurrentIdxReg;
3474 } else {
3475 SGPRIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3476 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), SGPRIdxReg)
3477 .addReg(CurrentIdxReg, RegState::Kill)
3478 .addImm(Offset);
3479 }
3480 } else {
3481 // Move index from VCC into M0
3482 if (Offset == 0) {
3483 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3484 .addReg(CurrentIdxReg, RegState::Kill);
3485 } else {
3486 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3487 .addReg(CurrentIdxReg, RegState::Kill)
3488 .addImm(Offset);
3489 }
3490 }
3491
3492 // Update EXEC, switch all done bits to 0 and all todo bits to 1.
3493 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3494 MachineInstr *InsertPt =
3495 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
3496 : AMDGPU::S_XOR_B64_term), Exec)
3497 .addReg(Exec)
3498 .addReg(NewExec);
3499
3500 // XXX - s_xor_b64 sets scc to 1 if the result is nonzero, so can we use
3501 // s_cbranch_scc0?
3502
3503 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover.
3504 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
3505 .addMBB(&LoopBB);
3506
3507 return InsertPt->getIterator();
3508}
3509
3510// This has slightly sub-optimal regalloc when the source vector is killed by
3511// the read. The register allocator does not understand that the kill is
3512// per-workitem, so is kept alive for the whole loop so we end up not re-using a
3513// subregister from it, using 1 more VGPR than necessary. This was saved when
3514// this was expanded after register allocation.
3515static MachineBasicBlock::iterator
3516loadM0FromVGPR(const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineInstr &MI,
3517 unsigned InitResultReg, unsigned PhiReg, int Offset,
3518 bool UseGPRIdxMode, Register &SGPRIdxReg) {
3519 MachineFunction *MF = MBB.getParent();
3520 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3521 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3522 MachineRegisterInfo &MRI = MF->getRegInfo();
3523 const DebugLoc &DL = MI.getDebugLoc();
3524 MachineBasicBlock::iterator I(&MI);
3525
3526 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3527 Register DstReg = MI.getOperand(0).getReg();
3528 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
3529 Register TmpExec = MRI.createVirtualRegister(BoolXExecRC);
3530 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3531 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
3532
3533 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
3534
3535 // Save the EXEC mask
3536 BuildMI(MBB, I, DL, TII->get(MovExecOpc), SaveExec)
3537 .addReg(Exec);
3538
3539 MachineBasicBlock *LoopBB;
3540 MachineBasicBlock *RemainderBB;
3541 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, MBB, false);
3542
3543 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3544
3545 auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
3546 InitResultReg, DstReg, PhiReg, TmpExec,
3547 Offset, UseGPRIdxMode, SGPRIdxReg);
3548
3549 MachineBasicBlock* LandingPad = MF->CreateMachineBasicBlock();
3550 MachineFunction::iterator MBBI(LoopBB);
3551 ++MBBI;
3552 MF->insert(MBBI, LandingPad);
3553 LoopBB->removeSuccessor(RemainderBB);
3554 LandingPad->addSuccessor(RemainderBB);
3555 LoopBB->addSuccessor(LandingPad);
3556 MachineBasicBlock::iterator First = LandingPad->begin();
3557 BuildMI(*LandingPad, First, DL, TII->get(MovExecOpc), Exec)
3558 .addReg(SaveExec);
3559
3560 return InsPt;
3561}
3562
3563// Returns subreg index, offset
3564static std::pair<unsigned, int>
3565computeIndirectRegAndOffset(const SIRegisterInfo &TRI,
3566 const TargetRegisterClass *SuperRC,
3567 unsigned VecReg,
3568 int Offset) {
3569 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
3570
3571 // Skip out of bounds offsets, or else we would end up using an undefined
3572 // register.
3573 if (Offset >= NumElts || Offset < 0)
3574 return std::make_pair(AMDGPU::sub0, Offset);
3575
3576 return std::make_pair(SIRegisterInfo::getSubRegFromChannel(Offset), 0);
3577}
3578
3579static void setM0ToIndexFromSGPR(const SIInstrInfo *TII,
3580 MachineRegisterInfo &MRI, MachineInstr &MI,
3581 int Offset) {
3582 MachineBasicBlock *MBB = MI.getParent();
3583 const DebugLoc &DL = MI.getDebugLoc();
3584 MachineBasicBlock::iterator I(&MI);
3585
3586 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3587
3588 assert(Idx->getReg() != AMDGPU::NoRegister)((Idx->getReg() != AMDGPU::NoRegister) ? static_cast<void
> (0) : __assert_fail ("Idx->getReg() != AMDGPU::NoRegister"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3588, __PRETTY_FUNCTION__))
;
3589
3590 if (Offset == 0) {
3591 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0).add(*Idx);
3592 } else {
3593 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3594 .add(*Idx)
3595 .addImm(Offset);
3596 }
3597}
3598
3599static Register getIndirectSGPRIdx(const SIInstrInfo *TII,
3600 MachineRegisterInfo &MRI, MachineInstr &MI,
3601 int Offset) {
3602 MachineBasicBlock *MBB = MI.getParent();
3603 const DebugLoc &DL = MI.getDebugLoc();
3604 MachineBasicBlock::iterator I(&MI);
3605
3606 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3607
3608 if (Offset == 0)
3609 return Idx->getReg();
3610
3611 Register Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3612 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
3613 .add(*Idx)
3614 .addImm(Offset);
3615 return Tmp;
3616}
3617
3618static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
3619 MachineBasicBlock &MBB,
3620 const GCNSubtarget &ST) {
3621 const SIInstrInfo *TII = ST.getInstrInfo();
3622 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3623 MachineFunction *MF = MBB.getParent();
3624 MachineRegisterInfo &MRI = MF->getRegInfo();
3625
3626 Register Dst = MI.getOperand(0).getReg();
3627 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3628 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
3629 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3630
3631 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3632 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3633
3634 unsigned SubReg;
3635 std::tie(SubReg, Offset)
3636 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
3637
3638 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3639
3640 // Check for a SGPR index.
3641 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) {
3642 MachineBasicBlock::iterator I(&MI);
3643 const DebugLoc &DL = MI.getDebugLoc();
3644
3645 if (UseGPRIdxMode) {
3646 // TODO: Look at the uses to avoid the copy. This may require rescheduling
3647 // to avoid interfering with other uses, so probably requires a new
3648 // optimization pass.
3649 Register Idx = getIndirectSGPRIdx(TII, MRI, MI, Offset);
3650
3651 const MCInstrDesc &GPRIDXDesc =
3652 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true);
3653 BuildMI(MBB, I, DL, GPRIDXDesc, Dst)
3654 .addReg(SrcReg)
3655 .addReg(Idx)
3656 .addImm(SubReg);
3657 } else {
3658 setM0ToIndexFromSGPR(TII, MRI, MI, Offset);
3659
3660 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3661 .addReg(SrcReg, 0, SubReg)
3662 .addReg(SrcReg, RegState::Implicit);
3663 }
3664
3665 MI.eraseFromParent();
3666
3667 return &MBB;
3668 }
3669
3670 // Control flow needs to be inserted if indexing with a VGPR.
3671 const DebugLoc &DL = MI.getDebugLoc();
3672 MachineBasicBlock::iterator I(&MI);
3673
3674 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3675 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3676
3677 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3678
3679 Register SGPRIdxReg;
3680 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset,
3681 UseGPRIdxMode, SGPRIdxReg);
3682
3683 MachineBasicBlock *LoopBB = InsPt->getParent();
3684
3685 if (UseGPRIdxMode) {
3686 const MCInstrDesc &GPRIDXDesc =
3687 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true);
3688
3689 BuildMI(*LoopBB, InsPt, DL, GPRIDXDesc, Dst)
3690 .addReg(SrcReg)
3691 .addReg(SGPRIdxReg)
3692 .addImm(SubReg);
3693 } else {
3694 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3695 .addReg(SrcReg, 0, SubReg)
3696 .addReg(SrcReg, RegState::Implicit);
3697 }
3698
3699 MI.eraseFromParent();
3700
3701 return LoopBB;
3702}
3703
3704static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
3705 MachineBasicBlock &MBB,
3706 const GCNSubtarget &ST) {
3707 const SIInstrInfo *TII = ST.getInstrInfo();
3708 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3709 MachineFunction *MF = MBB.getParent();
3710 MachineRegisterInfo &MRI = MF->getRegInfo();
3711
3712 Register Dst = MI.getOperand(0).getReg();
3713 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
3714 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3715 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
3716 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3717 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3718 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3719
3720 // This can be an immediate, but will be folded later.
3721 assert(Val->getReg())((Val->getReg()) ? static_cast<void> (0) : __assert_fail
("Val->getReg()", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3721, __PRETTY_FUNCTION__))
;
3722
3723 unsigned SubReg;
3724 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
3725 SrcVec->getReg(),
3726 Offset);
3727 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3728
3729 if (Idx->getReg() == AMDGPU::NoRegister) {
3730 MachineBasicBlock::iterator I(&MI);
3731 const DebugLoc &DL = MI.getDebugLoc();
3732
3733 assert(Offset == 0)((Offset == 0) ? static_cast<void> (0) : __assert_fail (
"Offset == 0", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3733, __PRETTY_FUNCTION__))
;
3734
3735 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
3736 .add(*SrcVec)
3737 .add(*Val)
3738 .addImm(SubReg);
3739
3740 MI.eraseFromParent();
3741 return &MBB;
3742 }
3743
3744 // Check for a SGPR index.
3745 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) {
3746 MachineBasicBlock::iterator I(&MI);
3747 const DebugLoc &DL = MI.getDebugLoc();
3748
3749 if (UseGPRIdxMode) {
3750 Register Idx = getIndirectSGPRIdx(TII, MRI, MI, Offset);
3751
3752 const MCInstrDesc &GPRIDXDesc =
3753 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false);
3754 BuildMI(MBB, I, DL, GPRIDXDesc, Dst)
3755 .addReg(SrcVec->getReg())
3756 .add(*Val)
3757 .addReg(Idx)
3758 .addImm(SubReg);
3759 } else {
3760 setM0ToIndexFromSGPR(TII, MRI, MI, Offset);
3761
3762 const MCInstrDesc &MovRelDesc = TII->getIndirectRegWriteMovRelPseudo(
3763 TRI.getRegSizeInBits(*VecRC), 32, false);
3764 BuildMI(MBB, I, DL, MovRelDesc, Dst)
3765 .addReg(SrcVec->getReg())
3766 .add(*Val)
3767 .addImm(SubReg);
3768 }
3769 MI.eraseFromParent();
3770 return &MBB;
3771 }
3772
3773 // Control flow needs to be inserted if indexing with a VGPR.
3774 if (Val->isReg())
3775 MRI.clearKillFlags(Val->getReg());
3776
3777 const DebugLoc &DL = MI.getDebugLoc();
3778
3779 Register PhiReg = MRI.createVirtualRegister(VecRC);
3780
3781 Register SGPRIdxReg;
3782 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset,
3783 UseGPRIdxMode, SGPRIdxReg);
3784 MachineBasicBlock *LoopBB = InsPt->getParent();
3785
3786 if (UseGPRIdxMode) {
3787 const MCInstrDesc &GPRIDXDesc =
3788 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false);
3789
3790 BuildMI(*LoopBB, InsPt, DL, GPRIDXDesc, Dst)
3791 .addReg(PhiReg)
3792 .add(*Val)
3793 .addReg(SGPRIdxReg)
3794 .addImm(AMDGPU::sub0);
3795 } else {
3796 const MCInstrDesc &MovRelDesc = TII->getIndirectRegWriteMovRelPseudo(
3797 TRI.getRegSizeInBits(*VecRC), 32, false);
3798 BuildMI(*LoopBB, InsPt, DL, MovRelDesc, Dst)
3799 .addReg(PhiReg)
3800 .add(*Val)
3801 .addImm(AMDGPU::sub0);
3802 }
3803
3804 MI.eraseFromParent();
3805 return LoopBB;
3806}
3807
3808MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
3809 MachineInstr &MI, MachineBasicBlock *BB) const {
3810
3811 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3812 MachineFunction *MF = BB->getParent();
3813 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
3814
3815 switch (MI.getOpcode()) {
3816 case AMDGPU::S_UADDO_PSEUDO:
3817 case AMDGPU::S_USUBO_PSEUDO: {
3818 const DebugLoc &DL = MI.getDebugLoc();
3819 MachineOperand &Dest0 = MI.getOperand(0);
3820 MachineOperand &Dest1 = MI.getOperand(1);
3821 MachineOperand &Src0 = MI.getOperand(2);
3822 MachineOperand &Src1 = MI.getOperand(3);
3823
3824 unsigned Opc = (MI.getOpcode() == AMDGPU::S_UADDO_PSEUDO)
3825 ? AMDGPU::S_ADD_I32
3826 : AMDGPU::S_SUB_I32;
3827 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1);
3828
3829 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CSELECT_B64), Dest1.getReg())
3830 .addImm(1)
3831 .addImm(0);
3832
3833 MI.eraseFromParent();
3834 return BB;
3835 }
3836 case AMDGPU::S_ADD_U64_PSEUDO:
3837 case AMDGPU::S_SUB_U64_PSEUDO: {
3838 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3839 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3840 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3841 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3842 const DebugLoc &DL = MI.getDebugLoc();
3843
3844 MachineOperand &Dest = MI.getOperand(0);
3845 MachineOperand &Src0 = MI.getOperand(1);
3846 MachineOperand &Src1 = MI.getOperand(2);
3847
3848 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3849 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3850
3851 MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(
3852 MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
3853 MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(
3854 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
3855
3856 MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(
3857 MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
3858 MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(
3859 MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
3860
3861 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
3862
3863 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
3864 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
3865 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0).add(Src0Sub0).add(Src1Sub0);
3866 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1).add(Src0Sub1).add(Src1Sub1);
3867 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3868 .addReg(DestSub0)
3869 .addImm(AMDGPU::sub0)
3870 .addReg(DestSub1)
3871 .addImm(AMDGPU::sub1);
3872 MI.eraseFromParent();
3873 return BB;
3874 }
3875 case AMDGPU::V_ADD_U64_PSEUDO:
3876 case AMDGPU::V_SUB_U64_PSEUDO: {
3877 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3878 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3879 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3880 const DebugLoc &DL = MI.getDebugLoc();
3881
3882 bool IsAdd = (MI.getOpcode() == AMDGPU::V_ADD_U64_PSEUDO);
3883
3884 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3885
3886 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3887 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3888
3889 Register CarryReg = MRI.createVirtualRegister(CarryRC);
3890 Register DeadCarryReg = MRI.createVirtualRegister(CarryRC);
3891
3892 MachineOperand &Dest = MI.getOperand(0);
3893 MachineOperand &Src0 = MI.getOperand(1);
3894 MachineOperand &Src1 = MI.getOperand(2);
3895
3896 const TargetRegisterClass *Src0RC = Src0.isReg()
3897 ? MRI.getRegClass(Src0.getReg())
3898 : &AMDGPU::VReg_64RegClass;
3899 const TargetRegisterClass *Src1RC = Src1.isReg()
3900 ? MRI.getRegClass(Src1.getReg())
3901 : &AMDGPU::VReg_64RegClass;
3902
3903 const TargetRegisterClass *Src0SubRC =
3904 TRI->getSubRegClass(Src0RC, AMDGPU::sub0);
3905 const TargetRegisterClass *Src1SubRC =
3906 TRI->getSubRegClass(Src1RC, AMDGPU::sub1);
3907
3908 MachineOperand SrcReg0Sub0 = TII->buildExtractSubRegOrImm(
3909 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
3910 MachineOperand SrcReg1Sub0 = TII->buildExtractSubRegOrImm(
3911 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
3912
3913 MachineOperand SrcReg0Sub1 = TII->buildExtractSubRegOrImm(
3914 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
3915 MachineOperand SrcReg1Sub1 = TII->buildExtractSubRegOrImm(
3916 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
3917
3918 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64;
3919 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3920 .addReg(CarryReg, RegState::Define)
3921 .add(SrcReg0Sub0)
3922 .add(SrcReg1Sub0)
3923 .addImm(0); // clamp bit
3924
3925 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
3926 MachineInstr *HiHalf =
3927 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
3928 .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
3929 .add(SrcReg0Sub1)
3930 .add(SrcReg1Sub1)
3931 .addReg(CarryReg, RegState::Kill)
3932 .addImm(0); // clamp bit
3933
3934 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3935 .addReg(DestSub0)
3936 .addImm(AMDGPU::sub0)
3937 .addReg(DestSub1)
3938 .addImm(AMDGPU::sub1);
3939 TII->legalizeOperands(*LoHalf);
3940 TII->legalizeOperands(*HiHalf);
3941 MI.eraseFromParent();
3942 return BB;
3943 }
3944 case AMDGPU::S_ADD_CO_PSEUDO:
3945 case AMDGPU::S_SUB_CO_PSEUDO: {
3946 // This pseudo has a chance to be selected
3947 // only from uniform add/subcarry node. All the VGPR operands
3948 // therefore assumed to be splat vectors.
3949 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3950 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3951 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3952 MachineBasicBlock::iterator MII = MI;
3953 const DebugLoc &DL = MI.getDebugLoc();
3954 MachineOperand &Dest = MI.getOperand(0);
3955 MachineOperand &CarryDest = MI.getOperand(1);
3956 MachineOperand &Src0 = MI.getOperand(2);
3957 MachineOperand &Src1 = MI.getOperand(3);
3958 MachineOperand &Src2 = MI.getOperand(4);
3959 unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO)
3960 ? AMDGPU::S_ADDC_U32
3961 : AMDGPU::S_SUBB_U32;
3962 if (Src0.isReg() && TRI->isVectorRegister(MRI, Src0.getReg())) {
3963 Register RegOp0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3964 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp0)
3965 .addReg(Src0.getReg());
3966 Src0.setReg(RegOp0);
3967 }
3968 if (Src1.isReg() && TRI->isVectorRegister(MRI, Src1.getReg())) {
3969 Register RegOp1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3970 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp1)
3971 .addReg(Src1.getReg());
3972 Src1.setReg(RegOp1);
3973 }
3974 Register RegOp2 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3975 if (TRI->isVectorRegister(MRI, Src2.getReg())) {
3976 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp2)
3977 .addReg(Src2.getReg());
3978 Src2.setReg(RegOp2);
3979 }
3980
3981 const TargetRegisterClass *Src2RC = MRI.getRegClass(Src2.getReg());
3982 if (TRI->getRegSizeInBits(*Src2RC) == 64) {
3983 if (ST.hasScalarCompareEq64()) {
3984 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMP_LG_U64))
3985 .addReg(Src2.getReg())
3986 .addImm(0);
3987 } else {
3988 const TargetRegisterClass *SubRC =
3989 TRI->getSubRegClass(Src2RC, AMDGPU::sub0);
3990 MachineOperand Src2Sub0 = TII->buildExtractSubRegOrImm(
3991 MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC);
3992 MachineOperand Src2Sub1 = TII->buildExtractSubRegOrImm(
3993 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC);
3994 Register Src2_32 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3995
3996 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_OR_B32), Src2_32)
3997 .add(Src2Sub0)
3998 .add(Src2Sub1);
3999
4000 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMP_LG_U32))
4001 .addReg(Src2_32, RegState::Kill)
4002 .addImm(0);
4003 }
4004 } else {
4005 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMPK_LG_U32))
4006 .addReg(Src2.getReg())
4007 .addImm(0);
4008 }
4009
4010 BuildMI(*BB, MII, DL, TII->get(Opc), Dest.getReg()).add(Src0).add(Src1);
4011
4012 BuildMI(*BB, MII, DL, TII->get(AMDGPU::COPY), CarryDest.getReg())
4013 .addReg(AMDGPU::SCC);
4014 MI.eraseFromParent();
4015 return BB;
4016 }
4017 case AMDGPU::SI_INIT_M0: {
4018 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
4019 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
4020 .add(MI.getOperand(0));
4021 MI.eraseFromParent();
4022 return BB;
4023 }
4024 case AMDGPU::GET_GROUPSTATICSIZE: {
4025 assert(getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA ||((getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA
|| getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL
) ? static_cast<void> (0) : __assert_fail ("getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4026, __PRETTY_FUNCTION__))
4026 getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL)((getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA
|| getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL
) ? static_cast<void> (0) : __assert_fail ("getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4026, __PRETTY_FUNCTION__))
;
4027 DebugLoc DL = MI.getDebugLoc();
4028 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
4029 .add(MI.getOperand(0))
4030 .addImm(MFI->getLDSSize());
4031 MI.eraseFromParent();
4032 return BB;
4033 }
4034 case AMDGPU::SI_INDIRECT_SRC_V1:
4035 case AMDGPU::SI_INDIRECT_SRC_V2:
4036 case AMDGPU::SI_INDIRECT_SRC_V4:
4037 case AMDGPU::SI_INDIRECT_SRC_V8:
4038 case AMDGPU::SI_INDIRECT_SRC_V16:
4039 case AMDGPU::SI_INDIRECT_SRC_V32:
4040 return emitIndirectSrc(MI, *BB, *getSubtarget());
4041 case AMDGPU::SI_INDIRECT_DST_V1:
4042 case AMDGPU::SI_INDIRECT_DST_V2:
4043 case AMDGPU::SI_INDIRECT_DST_V4:
4044 case AMDGPU::SI_INDIRECT_DST_V8:
4045 case AMDGPU::SI_INDIRECT_DST_V16:
4046 case AMDGPU::SI_INDIRECT_DST_V32:
4047 return emitIndirectDst(MI, *BB, *getSubtarget());
4048 case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
4049 case AMDGPU::SI_KILL_I1_PSEUDO:
4050 return splitKillBlock(MI, BB);
4051 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
4052 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4053 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4054 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4055
4056 Register Dst = MI.getOperand(0).getReg();
4057 Register Src0 = MI.getOperand(1).getReg();
4058 Register Src1 = MI.getOperand(2).getReg();
4059 const DebugLoc &DL = MI.getDebugLoc();
4060 Register SrcCond = MI.getOperand(3).getReg();
4061
4062 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4063 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4064 const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4065 Register SrcCondCopy = MRI.createVirtualRegister(CondRC);
4066
4067 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
4068 .addReg(SrcCond);
4069 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
4070 .addImm(0)
4071 .addReg(Src0, 0, AMDGPU::sub0)
4072 .addImm(0)
4073 .addReg(Src1, 0, AMDGPU::sub0)
4074 .addReg(SrcCondCopy);
4075 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
4076 .addImm(0)
4077 .addReg(Src0, 0, AMDGPU::sub1)
4078 .addImm(0)
4079 .addReg(Src1, 0, AMDGPU::sub1)
4080 .addReg(SrcCondCopy);
4081
4082 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
4083 .addReg(DstLo)
4084 .addImm(AMDGPU::sub0)
4085 .addReg(DstHi)
4086 .addImm(AMDGPU::sub1);
4087 MI.eraseFromParent();
4088 return BB;
4089 }
4090 case AMDGPU::SI_BR_UNDEF: {
4091 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4092 const DebugLoc &DL = MI.getDebugLoc();
4093 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
4094 .add(MI.getOperand(0));
4095 Br->getOperand(1).setIsUndef(true); // read undef SCC
4096 MI.eraseFromParent();
4097 return BB;
4098 }
4099 case AMDGPU::ADJCALLSTACKUP:
4100 case AMDGPU::ADJCALLSTACKDOWN: {
4101 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
4102 MachineInstrBuilder MIB(*MF, &MI);
4103 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
4104 .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit);
4105 return BB;
4106 }
4107 case AMDGPU::SI_CALL_ISEL: {
4108 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4109 const DebugLoc &DL = MI.getDebugLoc();
4110
4111 unsigned ReturnAddrReg = TII->getRegisterInfo().getReturnAddressReg(*MF);
4112
4113 MachineInstrBuilder MIB;
4114 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg);
4115
4116 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I)
4117 MIB.add(MI.getOperand(I));
4118
4119 MIB.cloneMemRefs(MI);
4120 MI.eraseFromParent();
4121 return BB;
4122 }
4123 case AMDGPU::V_ADD_CO_U32_e32:
4124 case AMDGPU::V_SUB_CO_U32_e32:
4125 case AMDGPU::V_SUBREV_CO_U32_e32: {
4126 // TODO: Define distinct V_*_I32_Pseudo instructions instead.
4127 const DebugLoc &DL = MI.getDebugLoc();
4128 unsigned Opc = MI.getOpcode();
4129
4130 bool NeedClampOperand = false;
4131 if (TII->pseudoToMCOpcode(Opc) == -1) {
4132 Opc = AMDGPU::getVOPe64(Opc);
4133 NeedClampOperand = true;
4134 }
4135
4136 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
4137 if (TII->isVOP3(*I)) {
4138 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4139 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4140 I.addReg(TRI->getVCC(), RegState::Define);
4141 }
4142 I.add(MI.getOperand(1))
4143 .add(MI.getOperand(2));
4144 if (NeedClampOperand)
4145 I.addImm(0); // clamp bit for e64 encoding
4146
4147 TII->legalizeOperands(*I);
4148
4149 MI.eraseFromParent();
4150 return BB;
4151 }
4152 case AMDGPU::DS_GWS_INIT:
4153 case AMDGPU::DS_GWS_SEMA_V:
4154 case AMDGPU::DS_GWS_SEMA_BR:
4155 case AMDGPU::DS_GWS_SEMA_P:
4156 case AMDGPU::DS_GWS_SEMA_RELEASE_ALL:
4157 case AMDGPU::DS_GWS_BARRIER:
4158 // A s_waitcnt 0 is required to be the instruction immediately following.
4159 if (getSubtarget()->hasGWSAutoReplay()) {
4160 bundleInstWithWaitcnt(MI);
4161 return BB;
4162 }
4163
4164 return emitGWSMemViolTestLoop(MI, BB);
4165 case AMDGPU::S_SETREG_B32: {
4166 // Try to optimize cases that only set the denormal mode or rounding mode.
4167 //
4168 // If the s_setreg_b32 fully sets all of the bits in the rounding mode or
4169 // denormal mode to a constant, we can use s_round_mode or s_denorm_mode
4170 // instead.
4171 //
4172 // FIXME: This could be predicates on the immediate, but tablegen doesn't
4173 // allow you to have a no side effect instruction in the output of a
4174 // sideeffecting pattern.
4175 unsigned ID, Offset, Width;
4176 AMDGPU::Hwreg::decodeHwreg(MI.getOperand(1).getImm(), ID, Offset, Width);
4177 if (ID != AMDGPU::Hwreg::ID_MODE)
4178 return BB;
4179
4180 const unsigned WidthMask = maskTrailingOnes<unsigned>(Width);
4181 const unsigned SetMask = WidthMask << Offset;
4182
4183 if (getSubtarget()->hasDenormModeInst()) {
4184 unsigned SetDenormOp = 0;
4185 unsigned SetRoundOp = 0;
4186
4187 // The dedicated instructions can only set the whole denorm or round mode
4188 // at once, not a subset of bits in either.
4189 if (SetMask ==
4190 (AMDGPU::Hwreg::FP_ROUND_MASK | AMDGPU::Hwreg::FP_DENORM_MASK)) {
4191 // If this fully sets both the round and denorm mode, emit the two
4192 // dedicated instructions for these.
4193 SetRoundOp = AMDGPU::S_ROUND_MODE;
4194 SetDenormOp = AMDGPU::S_DENORM_MODE;
4195 } else if (SetMask == AMDGPU::Hwreg::FP_ROUND_MASK) {
4196 SetRoundOp = AMDGPU::S_ROUND_MODE;
4197 } else if (SetMask == AMDGPU::Hwreg::FP_DENORM_MASK) {
4198 SetDenormOp = AMDGPU::S_DENORM_MODE;
4199 }
4200
4201 if (SetRoundOp || SetDenormOp) {
4202 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4203 MachineInstr *Def = MRI.getVRegDef(MI.getOperand(0).getReg());
4204 if (Def && Def->isMoveImmediate() && Def->getOperand(1).isImm()) {
4205 unsigned ImmVal = Def->getOperand(1).getImm();
4206 if (SetRoundOp) {
4207 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SetRoundOp))
4208 .addImm(ImmVal & 0xf);
4209
4210 // If we also have the denorm mode, get just the denorm mode bits.
4211 ImmVal >>= 4;
4212 }
4213
4214 if (SetDenormOp) {
4215 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SetDenormOp))
4216 .addImm(ImmVal & 0xf);
4217 }
4218
4219 MI.eraseFromParent();
4220 return BB;
4221 }
4222 }
4223 }
4224
4225 // If only FP bits are touched, used the no side effects pseudo.
4226 if ((SetMask & (AMDGPU::Hwreg::FP_ROUND_MASK |
4227 AMDGPU::Hwreg::FP_DENORM_MASK)) == SetMask)
4228 MI.setDesc(TII->get(AMDGPU::S_SETREG_B32_mode));
4229
4230 return BB;
4231 }
4232 default:
4233 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
4234 }
4235}
4236
4237bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const {
4238 return isTypeLegal(VT.getScalarType());
4239}
4240
4241bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
4242 // This currently forces unfolding various combinations of fsub into fma with
4243 // free fneg'd operands. As long as we have fast FMA (controlled by
4244 // isFMAFasterThanFMulAndFAdd), we should perform these.
4245
4246 // When fma is quarter rate, for f64 where add / sub are at best half rate,
4247 // most of these combines appear to be cycle neutral but save on instruction
4248 // count / code size.
4249 return true;
4250}
4251
4252EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
4253 EVT VT) const {
4254 if (!VT.isVector()) {
4255 return MVT::i1;
4256 }
4257 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
4258}
4259
4260MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT VT) const {
4261 // TODO: Should i16 be used always if legal? For now it would force VALU
4262 // shifts.
4263 return (VT == MVT::i16) ? MVT::i16 : MVT::i32;
4264}
4265
4266LLT SITargetLowering::getPreferredShiftAmountTy(LLT Ty) const {
4267 return (Ty.getScalarSizeInBits() <= 16 && Subtarget->has16BitInsts())
4268 ? Ty.changeElementSize(16)
4269 : Ty.changeElementSize(32);
4270}
4271
4272// Answering this is somewhat tricky and depends on the specific device which
4273// have different rates for fma or all f64 operations.
4274//
4275// v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
4276// regardless of which device (although the number of cycles differs between
4277// devices), so it is always profitable for f64.
4278//
4279// v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
4280// only on full rate devices. Normally, we should prefer selecting v_mad_f32
4281// which we can always do even without fused FP ops since it returns the same
4282// result as the separate operations and since it is always full
4283// rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
4284// however does not support denormals, so we do report fma as faster if we have
4285// a fast fma device and require denormals.
4286//
4287bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
4288 EVT VT) const {
4289 VT = VT.getScalarType();
4290
4291 switch (VT.getSimpleVT().SimpleTy) {
4292 case MVT::f32: {
4293 // If mad is not available this depends only on if f32 fma is full rate.
4294 if (!Subtarget->hasMadMacF32Insts())
4295 return Subtarget->hasFastFMAF32();
4296
4297 // Otherwise f32 mad is always full rate and returns the same result as
4298 // the separate operations so should be preferred over fma.
4299 // However does not support denomals.
4300 if (hasFP32Denormals(MF))
4301 return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts();
4302
4303 // If the subtarget has v_fmac_f32, that's just as good as v_mac_f32.
4304 return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts();
4305 }
4306 case MVT::f64:
4307 return true;
4308 case MVT::f16:
4309 return Subtarget->has16BitInsts() && hasFP64FP16Denormals(MF);
4310 default:
4311 break;
4312 }
4313
4314 return false;
4315}
4316
4317bool SITargetLowering::isFMADLegal(const SelectionDAG &DAG,
4318 const SDNode *N) const {
4319 // TODO: Check future ftz flag
4320 // v_mad_f32/v_mac_f32 do not support denormals.
4321 EVT VT = N->getValueType(0);
4322 if (VT == MVT::f32)
4323 return Subtarget->hasMadMacF32Insts() &&
4324 !hasFP32Denormals(DAG.getMachineFunction());
4325 if (VT == MVT::f16) {
4326 return Subtarget->hasMadF16() &&
4327 !hasFP64FP16Denormals(DAG.getMachineFunction());
4328 }
4329
4330 return false;
4331}
4332
4333//===----------------------------------------------------------------------===//
4334// Custom DAG Lowering Operations
4335//===----------------------------------------------------------------------===//
4336
4337// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
4338// wider vector type is legal.
4339SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
4340 SelectionDAG &DAG) const {
4341 unsigned Opc = Op.getOpcode();
4342 EVT VT = Op.getValueType();
4343 assert(VT == MVT::v4f16 || VT == MVT::v4i16)((VT == MVT::v4f16 || VT == MVT::v4i16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v4f16 || VT == MVT::v4i16"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4343, __PRETTY_FUNCTION__))
;
4344
4345 SDValue Lo, Hi;
4346 std::tie(Lo, Hi) = DAG.SplitVectorOperand(Op.getNode(), 0);
4347
4348 SDLoc SL(Op);
4349 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo,
4350 Op->getFlags());
4351 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi,
4352 Op->getFlags());
4353
4354 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4355}
4356
4357// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
4358// wider vector type is legal.
4359SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
4360 SelectionDAG &DAG) const {
4361 unsigned Opc = Op.getOpcode();
4362 EVT VT = Op.getValueType();
4363 assert(VT == MVT::v4i16 || VT == MVT::v4f16)((VT == MVT::v4i16 || VT == MVT::v4f16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4363, __PRETTY_FUNCTION__))
;
4364
4365 SDValue Lo0, Hi0;
4366 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
4367 SDValue Lo1, Hi1;
4368 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4369
4370 SDLoc SL(Op);
4371
4372 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1,
4373 Op->getFlags());
4374 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1,
4375 Op->getFlags());
4376
4377 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4378}
4379
4380SDValue SITargetLowering::splitTernaryVectorOp(SDValue Op,
4381 SelectionDAG &DAG) const {
4382 unsigned Opc = Op.getOpcode();
4383 EVT VT = Op.getValueType();
4384 assert(VT == MVT::v4i16 || VT == MVT::v4f16)((VT == MVT::v4i16 || VT == MVT::v4f16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4384, __PRETTY_FUNCTION__))
;
4385
4386 SDValue Lo0, Hi0;
4387 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
4388 SDValue Lo1, Hi1;
4389 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4390 SDValue Lo2, Hi2;
4391 std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2);
4392
4393 SDLoc SL(Op);
4394
4395 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2,
4396 Op->getFlags());
4397 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2,
4398 Op->getFlags());
4399
4400 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4401}
4402
4403
4404SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4405 switch (Op.getOpcode()) {
4406 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
4407 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4408 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4409 case ISD::LOAD: {
4410 SDValue Result = LowerLOAD(Op, DAG);
4411 assert((!Result.getNode() ||(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4413, __PRETTY_FUNCTION__))
4412 Result.getNode()->getNumValues() == 2) &&(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4413, __PRETTY_FUNCTION__))
4413 "Load should return a value and a chain")(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4413, __PRETTY_FUNCTION__))
;
4414 return Result;
4415 }
4416
4417 case ISD::FSIN:
4418 case ISD::FCOS:
4419 return LowerTrig(Op, DAG);
4420 case ISD::SELECT: return LowerSELECT(Op, DAG);
4421 case ISD::FDIV: return LowerFDIV(Op, DAG);
4422 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
4423 case ISD::STORE: return LowerSTORE(Op, DAG);
4424 case ISD::GlobalAddress: {
4425 MachineFunction &MF = DAG.getMachineFunction();
4426 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
4427 return LowerGlobalAddress(MFI, Op, DAG);
4428 }
4429 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4430 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
4431 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
4432 case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
4433 case ISD::INSERT_SUBVECTOR:
4434 return lowerINSERT_SUBVECTOR(Op, DAG);
4435 case ISD::INSERT_VECTOR_ELT:
4436 return lowerINSERT_VECTOR_ELT(Op, DAG);
4437 case ISD::EXTRACT_VECTOR_ELT:
4438 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4439 case ISD::VECTOR_SHUFFLE:
4440 return lowerVECTOR_SHUFFLE(Op, DAG);
4441 case ISD::BUILD_VECTOR:
4442 return lowerBUILD_VECTOR(Op, DAG);
4443 case ISD::FP_ROUND:
4444 return lowerFP_ROUND(Op, DAG);
4445 case ISD::TRAP:
4446 return lowerTRAP(Op, DAG);
4447 case ISD::DEBUGTRAP:
4448 return lowerDEBUGTRAP(Op, DAG);
4449 case ISD::FABS:
4450 case ISD::FNEG:
4451 case ISD::FCANONICALIZE:
4452 case ISD::BSWAP:
4453 return splitUnaryVectorOp(Op, DAG);
4454 case ISD::FMINNUM:
4455 case ISD::FMAXNUM:
4456 return lowerFMINNUM_FMAXNUM(Op, DAG);
4457 case ISD::FMA:
4458 return splitTernaryVectorOp(Op, DAG);
4459 case ISD::SHL:
4460 case ISD::SRA:
4461 case ISD::SRL:
4462 case ISD::ADD:
4463 case ISD::SUB:
4464 case ISD::MUL:
4465 case ISD::SMIN:
4466 case ISD::SMAX:
4467 case ISD::UMIN:
4468 case ISD::UMAX:
4469 case ISD::FADD:
4470 case ISD::FMUL:
4471 case ISD::FMINNUM_IEEE:
4472 case ISD::FMAXNUM_IEEE:
4473 case ISD::UADDSAT:
4474 case ISD::USUBSAT:
4475 case ISD::SADDSAT:
4476 case ISD::SSUBSAT:
4477 return splitBinaryVectorOp(Op, DAG);
4478 case ISD::SMULO:
4479 case ISD::UMULO:
4480 return lowerXMULO(Op, DAG);
4481 case ISD::DYNAMIC_STACKALLOC:
4482 return LowerDYNAMIC_STACKALLOC(Op, DAG);
4483 }
4484 return SDValue();
4485}
4486
4487// Used for D16: Casts the result of an instruction into the right vector,
4488// packs values if loads return unpacked values.
4489static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT,
4490 const SDLoc &DL,
4491 SelectionDAG &DAG, bool Unpacked) {
4492 if (!LoadVT.isVector())
4493 return Result;
4494
4495 // Cast back to the original packed type or to a larger type that is a
4496 // multiple of 32 bit for D16. Widening the return type is a required for
4497 // legalization.
4498 EVT FittingLoadVT = LoadVT;
4499 if ((LoadVT.getVectorNumElements() % 2) == 1) {
4500 FittingLoadVT =
4501 EVT::getVectorVT(*DAG.getContext(), LoadVT.getVectorElementType(),
4502 LoadVT.getVectorNumElements() + 1);
4503 }
4504
4505 if (Unpacked) { // From v2i32/v4i32 back to v2f16/v4f16.
4506 // Truncate to v2i16/v4i16.
4507 EVT IntLoadVT = FittingLoadVT.changeTypeToInteger();
4508
4509 // Workaround legalizer not scalarizing truncate after vector op
4510 // legalization but not creating intermediate vector trunc.
4511 SmallVector<SDValue, 4> Elts;
4512 DAG.ExtractVectorElements(Result, Elts);
4513 for (SDValue &Elt : Elts)
4514 Elt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Elt);
4515
4516 // Pad illegal v1i16/v3fi6 to v4i16
4517 if ((LoadVT.getVectorNumElements() % 2) == 1)
4518 Elts.push_back(DAG.getUNDEF(MVT::i16));
4519
4520 Result = DAG.getBuildVector(IntLoadVT, DL, Elts);
4521
4522 // Bitcast to original type (v2f16/v4f16).
4523 return DAG.getNode(ISD::BITCAST, DL, FittingLoadVT, Result);
4524 }
4525
4526 // Cast back to the original packed type.
4527 return DAG.getNode(ISD::BITCAST, DL, FittingLoadVT, Result);
4528}
4529
4530SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
4531 MemSDNode *M,
4532 SelectionDAG &DAG,
4533 ArrayRef<SDValue> Ops,
4534 bool IsIntrinsic) const {
4535 SDLoc DL(M);
4536
4537 bool Unpacked = Subtarget->hasUnpackedD16VMem();
4538 EVT LoadVT = M->getValueType(0);
4539
4540 EVT EquivLoadVT = LoadVT;
4541 if (LoadVT.isVector()) {
4542 if (Unpacked) {
4543 EquivLoadVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
4544 LoadVT.getVectorNumElements());
4545 } else if ((LoadVT.getVectorNumElements() % 2) == 1) {
4546 // Widen v3f16 to legal type
4547 EquivLoadVT =
4548 EVT::getVectorVT(*DAG.getContext(), LoadVT.getVectorElementType(),
4549 LoadVT.getVectorNumElements() + 1);
4550 }
4551 }
4552
4553 // Change from v4f16/v2f16 to EquivLoadVT.
4554 SDVTList VTList = DAG.getVTList(EquivLoadVT, MVT::Other);
4555
4556 SDValue Load
4557 = DAG.getMemIntrinsicNode(
4558 IsIntrinsic ? (unsigned)ISD::INTRINSIC_W_CHAIN : Opcode, DL,
4559 VTList, Ops, M->getMemoryVT(),
4560 M->getMemOperand());
4561
4562 SDValue Adjusted = adjustLoadValueTypeImpl(Load, LoadVT, DL, DAG, Unpacked);
4563
4564 return DAG.getMergeValues({ Adjusted, Load.getValue(1) }, DL);
4565}
4566
4567SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
4568 SelectionDAG &DAG,
4569 ArrayRef<SDValue> Ops) const {
4570 SDLoc DL(M);
4571 EVT LoadVT = M->getValueType(0);
4572 EVT EltType = LoadVT.getScalarType();
4573 EVT IntVT = LoadVT.changeTypeToInteger();
4574
4575 bool IsD16 = IsFormat && (EltType.getSizeInBits() == 16);
4576
4577 unsigned Opc =
4578 IsFormat ? AMDGPUISD::BUFFER_LOAD_FORMAT : AMDGPUISD::BUFFER_LOAD;
4579
4580 if (IsD16) {
4581 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, M, DAG, Ops);
4582 }
4583
4584 // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
4585 if (!IsD16 && !LoadVT.isVector() && EltType.getSizeInBits() < 32)
4586 return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
4587
4588 if (isTypeLegal(LoadVT)) {
4589 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT,
4590 M->getMemOperand(), DAG);
4591 }
4592
4593 EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT);
4594 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other);
4595 SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT,
4596 M->getMemOperand(), DAG);
4597 return DAG.getMergeValues(
4598 {DAG.getNode(ISD::BITCAST, DL, LoadVT, MemNode), MemNode.getValue(1)},
4599 DL);
4600}
4601
4602static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
4603 SDNode *N, SelectionDAG &DAG) {
4604 EVT VT = N->getValueType(0);
4605 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4606 unsigned CondCode = CD->getZExtValue();
4607 if (!ICmpInst::isIntPredicate(static_cast<ICmpInst::Predicate>(CondCode)))
4608 return DAG.getUNDEF(VT);
4609
4610 ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
4611
4612 SDValue LHS = N->getOperand(1);
4613 SDValue RHS = N->getOperand(2);
4614
4615 SDLoc DL(N);
4616
4617 EVT CmpVT = LHS.getValueType();
4618 if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) {
4619 unsigned PromoteOp = ICmpInst::isSigned(IcInput) ?
4620 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4621 LHS = DAG.getNode(PromoteOp, DL, MVT::i32, LHS);
4622 RHS = DAG.getNode(PromoteOp, DL, MVT::i32, RHS);
4623 }
4624
4625 ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
4626
4627 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4628 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4629
4630 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS,
4631 DAG.getCondCode(CCOpcode));
4632 if (VT.bitsEq(CCVT))
4633 return SetCC;
4634 return DAG.getZExtOrTrunc(SetCC, DL, VT);
4635}
4636
4637static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI,
4638 SDNode *N, SelectionDAG &DAG) {
4639 EVT VT = N->getValueType(0);
4640 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4641
4642 unsigned CondCode = CD->getZExtValue();
4643 if (!FCmpInst::isFPPredicate(static_cast<FCmpInst::Predicate>(CondCode)))
4644 return DAG.getUNDEF(VT);
4645
4646 SDValue Src0 = N->getOperand(1);
4647 SDValue Src1 = N->getOperand(2);
4648 EVT CmpVT = Src0.getValueType();
4649 SDLoc SL(N);
4650
4651 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
4652 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4653 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
4654 }
4655
4656 FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
4657 ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
4658 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4659 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4660 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0,
4661 Src1, DAG.getCondCode(CCOpcode));
4662 if (VT.bitsEq(CCVT))
4663 return SetCC;
4664 return DAG.getZExtOrTrunc(SetCC, SL, VT);
4665}
4666
4667static SDValue lowerBALLOTIntrinsic(const SITargetLowering &TLI, SDNode *N,
4668 SelectionDAG &DAG) {
4669 EVT VT = N->getValueType(0);
4670 SDValue Src = N->getOperand(1);
4671 SDLoc SL(N);
4672
4673 if (Src.getOpcode() == ISD::SETCC) {
4674 // (ballot (ISD::SETCC ...)) -> (AMDGPUISD::SETCC ...)
4675 return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Src.getOperand(0),
4676 Src.getOperand(1), Src.getOperand(2));
4677 }
4678 if (const ConstantSDNode *Arg = dyn_cast<ConstantSDNode>(Src)) {
4679 // (ballot 0) -> 0
4680 if (Arg->isNullValue())
4681 return DAG.getConstant(0, SL, VT);
4682
4683 // (ballot 1) -> EXEC/EXEC_LO
4684 if (Arg->isOne()) {
4685 Register Exec;
4686 if (VT.getScalarSizeInBits() == 32)
4687 Exec = AMDGPU::EXEC_LO;
4688 else if (VT.getScalarSizeInBits() == 64)
4689 Exec = AMDGPU::EXEC;
4690 else
4691 return SDValue();
4692
4693 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, Exec, VT);
4694 }
4695 }
4696
4697 // (ballot (i1 $src)) -> (AMDGPUISD::SETCC (i32 (zext $src)) (i32 0)
4698 // ISD::SETNE)
4699 return DAG.getNode(
4700 AMDGPUISD::SETCC, SL, VT, DAG.getZExtOrTrunc(Src, SL, MVT::i32),
4701 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE));
4702}
4703
4704void SITargetLowering::ReplaceNodeResults(SDNode *N,
4705 SmallVectorImpl<SDValue> &Results,
4706 SelectionDAG &DAG) const {
4707 switch (N->getOpcode()) {
4708 case ISD::INSERT_VECTOR_ELT: {
4709 if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
4710 Results.push_back(Res);
4711 return;
4712 }
4713 case ISD::EXTRACT_VECTOR_ELT: {
4714 if (SDValue Res = lowerEXTRACT_VECTOR_ELT(SDValue(N, 0), DAG))
4715 Results.push_back(Res);
4716 return;
4717 }
4718 case ISD::INTRINSIC_WO_CHAIN: {
4719 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4720 switch (IID) {
4721 case Intrinsic::amdgcn_cvt_pkrtz: {
4722 SDValue Src0 = N->getOperand(1);
4723 SDValue Src1 = N->getOperand(2);
4724 SDLoc SL(N);
4725 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32,
4726 Src0, Src1);
4727 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt));
4728 return;
4729 }
4730 case Intrinsic::amdgcn_cvt_pknorm_i16:
4731 case Intrinsic::amdgcn_cvt_pknorm_u16:
4732 case Intrinsic::amdgcn_cvt_pk_i16:
4733 case Intrinsic::amdgcn_cvt_pk_u16: {
4734 SDValue Src0 = N->getOperand(1);
4735 SDValue Src1 = N->getOperand(2);
4736 SDLoc SL(N);
4737 unsigned Opcode;
4738
4739 if (IID == Intrinsic::amdgcn_cvt_pknorm_i16)
4740 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
4741 else if (IID == Intrinsic::amdgcn_cvt_pknorm_u16)
4742 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
4743 else if (IID == Intrinsic::amdgcn_cvt_pk_i16)
4744 Opcode = AMDGPUISD::CVT_PK_I16_I32;
4745 else
4746 Opcode = AMDGPUISD::CVT_PK_U16_U32;
4747
4748 EVT VT = N->getValueType(0);
4749 if (isTypeLegal(VT))
4750 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
4751 else {
4752 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
4753 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt));
4754 }
4755 return;
4756 }
4757 }
4758 break;
4759 }
4760 case ISD::INTRINSIC_W_CHAIN: {
4761 if (SDValue Res = LowerINTRINSIC_W_CHAIN(SDValue(N, 0), DAG)) {
4762 if (Res.getOpcode() == ISD::MERGE_VALUES) {
4763 // FIXME: Hacky
4764 for (unsigned I = 0; I < Res.getNumOperands(); I++) {
4765 Results.push_back(Res.getOperand(I));
4766 }
4767 } else {
4768 Results.push_back(Res);
4769 Results.push_back(Res.getValue(1));
4770 }
4771 return;
4772 }
4773
4774 break;
4775 }
4776 case ISD::SELECT: {
4777 SDLoc SL(N);
4778 EVT VT = N->getValueType(0);
4779 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
4780 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1));
4781 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2));
4782
4783 EVT SelectVT = NewVT;
4784 if (NewVT.bitsLT(MVT::i32)) {
4785 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS);
4786 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS);
4787 SelectVT = MVT::i32;
4788 }
4789
4790 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT,
4791 N->getOperand(0), LHS, RHS);
4792
4793 if (NewVT != SelectVT)
4794 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect);
4795 Results.push_back(DAG.getNode(ISD::BITCAST, SL, VT, NewSelect));
4796 return;
4797 }
4798 case ISD::FNEG: {
4799 if (N->getValueType(0) != MVT::v2f16)
4800 break;
4801
4802 SDLoc SL(N);
4803 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
4804
4805 SDValue Op = DAG.getNode(ISD::XOR, SL, MVT::i32,
4806 BC,
4807 DAG.getConstant(0x80008000, SL, MVT::i32));
4808 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
4809 return;
4810 }
4811 case ISD::FABS: {
4812 if (N->getValueType(0) != MVT::v2f16)
4813 break;
4814
4815 SDLoc SL(N);
4816 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
4817
4818 SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32,
4819 BC,
4820 DAG.getConstant(0x7fff7fff, SL, MVT::i32));
4821 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
4822 return;
4823 }
4824 default:
4825 break;
4826 }
4827}
4828
4829/// Helper function for LowerBRCOND
4830static SDNode *findUser(SDValue Value, unsigned Opcode) {
4831
4832 SDNode *Parent = Value.getNode();
4833 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
4834 I != E; ++I) {
4835
4836 if (I.getUse().get() != Value)
4837 continue;
4838
4839 if (I->getOpcode() == Opcode)
4840 return *I;
4841 }
4842 return nullptr;
4843}
4844
4845unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
4846 if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
4847 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
4848 case Intrinsic::amdgcn_if:
4849 return AMDGPUISD::IF;
4850 case Intrinsic::amdgcn_else:
4851 return AMDGPUISD::ELSE;
4852 case Intrinsic::amdgcn_loop:
4853 return AMDGPUISD::LOOP;
4854 case Intrinsic::amdgcn_end_cf:
4855 llvm_unreachable("should not occur")::llvm::llvm_unreachable_internal("should not occur", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4855)
;
4856 default:
4857 return 0;
4858 }
4859 }
4860
4861 // break, if_break, else_break are all only used as inputs to loop, not
4862 // directly as branch conditions.
4863 return 0;
4864}
4865
4866bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
4867 const Triple &TT = getTargetMachine().getTargetTriple();
4868 return (GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
4869 GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
4870 AMDGPU::shouldEmitConstantsToTextSection(TT);
4871}
4872
4873bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
4874 // FIXME: Either avoid relying on address space here or change the default
4875 // address space for functions to avoid the explicit check.
4876 return (GV->getValueType()->isFunctionTy() ||
4877 !isNonGlobalAddrSpace(GV->getAddressSpace())) &&
4878 !shouldEmitFixup(GV) &&
4879 !getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
4880}
4881
4882bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
4883 return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
4884}
4885
4886bool SITargetLowering::shouldUseLDSConstAddress(const GlobalValue *GV) const {
4887 if (!GV->hasExternalLinkage())
4888 return true;
4889
4890 const auto OS = getTargetMachine().getTargetTriple().getOS();
4891 return OS == Triple::AMDHSA || OS == Triple::AMDPAL;
4892}
4893
4894/// This transforms the control flow intrinsics to get the branch destination as
4895/// last parameter, also switches branch target with BR if the need arise
4896SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
4897 SelectionDAG &DAG) const {
4898 SDLoc DL(BRCOND);
4899
4900 SDNode *Intr = BRCOND.getOperand(1).getNode();
4901 SDValue Target = BRCOND.getOperand(2);
4902 SDNode *BR = nullptr;
4903 SDNode *SetCC = nullptr;
4904
4905 if (Intr->getOpcode() == ISD::SETCC) {
4906 // As long as we negate the condition everything is fine
4907 SetCC = Intr;
4908 Intr = SetCC->getOperand(0).getNode();
4909
4910 } else {
4911 // Get the target from BR if we don't negate the condition
4912 BR = findUser(BRCOND, ISD::BR);
4913 assert(BR && "brcond missing unconditional branch user")((BR && "brcond missing unconditional branch user") ?
static_cast<void> (0) : __assert_fail ("BR && \"brcond missing unconditional branch user\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4913, __PRETTY_FUNCTION__))
;
4914 Target = BR->getOperand(1);
4915 }
4916
4917 unsigned CFNode = isCFIntrinsic(Intr);
4918 if (CFNode == 0) {
4919 // This is a uniform branch so we don't need to legalize.
4920 return BRCOND;
4921 }
4922
4923 bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||
4924 Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN;
4925
4926 assert(!SetCC ||((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4929, __PRETTY_FUNCTION__))
4927 (SetCC->getConstantOperandVal(1) == 1 &&((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4929, __PRETTY_FUNCTION__))
4928 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4929, __PRETTY_FUNCTION__))
4929 ISD::SETNE))((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4929, __PRETTY_FUNCTION__))
;
4930
4931 // operands of the new intrinsic call
4932 SmallVector<SDValue, 4> Ops;
4933 if (HaveChain)
4934 Ops.push_back(BRCOND.getOperand(0));
4935
4936 Ops.append(Intr->op_begin() + (HaveChain ? 2 : 1), Intr->op_end());
4937 Ops.push_back(Target);
4938
4939 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
4940
4941 // build the new intrinsic call
4942 SDNode *Result = DAG.getNode(CFNode, DL, DAG.getVTList(Res), Ops).getNode();
4943
4944 if (!HaveChain) {
4945 SDValue Ops[] = {
4946 SDValue(Result, 0),
4947 BRCOND.getOperand(0)
4948 };
4949
4950 Result = DAG.getMergeValues(Ops, DL).getNode();
4951 }
4952
4953 if (BR) {
4954 // Give the branch instruction our target
4955 SDValue Ops[] = {
4956 BR->getOperand(0),
4957 BRCOND.getOperand(2)
4958 };
4959 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
4960 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
4961 }
4962
4963 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
4964
4965 // Copy the intrinsic results to registers
4966 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
4967 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
4968 if (!CopyToReg)
4969 continue;
4970
4971 Chain = DAG.getCopyToReg(
4972 Chain, DL,
4973 CopyToReg->getOperand(1),
4974 SDValue(Result, i - 1),
4975 SDValue());
4976
4977 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
4978 }
4979
4980 // Remove the old intrinsic from the chain
4981 DAG.ReplaceAllUsesOfValueWith(
4982 SDValue(Intr, Intr->getNumValues() - 1),
4983 Intr->getOperand(0));
4984
4985 return Chain;
4986}
4987
4988SDValue SITargetLowering::LowerRETURNADDR(SDValue Op,
4989 SelectionDAG &DAG) const {
4990 MVT VT = Op.getSimpleValueType();
4991 SDLoc DL(Op);
4992 // Checking the depth
4993 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0)
4994 return DAG.getConstant(0, DL, VT);
4995
4996 MachineFunction &MF = DAG.getMachineFunction();
4997 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4998 // Check for kernel and shader functions
4999 if (Info->isEntryFunction())
5000 return DAG.getConstant(0, DL, VT);
5001
5002 MachineFrameInfo &MFI = MF.getFrameInfo();
5003 // There is a call to @llvm.returnaddress in this function
5004 MFI.setReturnAddressIsTaken(true);
5005
5006 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
5007 // Get the return address reg and mark it as an implicit live-in
5008 Register Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent()));
5009
5010 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
5011}
5012
5013SDValue SITargetLowering::getFPExtOrFPRound(SelectionDAG &DAG,
5014 SDValue Op,
5015 const SDLoc &DL,
5016 EVT VT) const {
5017 return Op.getValueType().bitsLE(VT) ?
5018 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) :
5019 DAG.getNode(ISD::FP_ROUND, DL, VT, Op,
5020 DAG.getTargetConstant(0, DL, MVT::i32));
5021}
5022
5023SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
5024 assert(Op.getValueType() == MVT::f16 &&((Op.getValueType() == MVT::f16 && "Do not know how to custom lower FP_ROUND for non-f16 type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5025, __PRETTY_FUNCTION__))
5025 "Do not know how to custom lower FP_ROUND for non-f16 type")((Op.getValueType() == MVT::f16 && "Do not know how to custom lower FP_ROUND for non-f16 type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5025, __PRETTY_FUNCTION__))
;
5026
5027 SDValue Src = Op.getOperand(0);
5028 EVT SrcVT = Src.getValueType();
5029 if (SrcVT != MVT::f64)
5030 return Op;
5031
5032 SDLoc DL(Op);
5033
5034 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);
5035 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToFp16);
5036 return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);
5037}
5038
5039SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
5040 SelectionDAG &DAG) const {
5041 EVT VT = Op.getValueType();
5042 const MachineFunction &MF = DAG.getMachineFunction();
5043 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5044 bool IsIEEEMode = Info->getMode().IEEE;
5045
5046 // FIXME: Assert during selection that this is only selected for
5047 // ieee_mode. Currently a combine can produce the ieee version for non-ieee
5048 // mode functions, but this happens to be OK since it's only done in cases
5049 // where there is known no sNaN.
5050 if (IsIEEEMode)
5051 return expandFMINNUM_FMAXNUM(Op.getNode(), DAG);
5052
5053 if (VT == MVT::v4f16)
5054 return splitBinaryVectorOp(Op, DAG);
5055 return Op;
5056}
5057
5058SDValue SITargetLowering::lowerXMULO(SDValue Op, SelectionDAG &DAG) const {
5059 EVT VT = Op.getValueType();
5060 SDLoc SL(Op);
5061 SDValue LHS = Op.getOperand(0);
5062 SDValue RHS = Op.getOperand(1);
5063 bool isSigned = Op.getOpcode() == ISD::SMULO;
5064
5065 if (ConstantSDNode *RHSC = isConstOrConstSplat(RHS)) {
5066 const APInt &C = RHSC->getAPIntValue();
5067 // mulo(X, 1 << S) -> { X << S, (X << S) >> S != X }
5068 if (C.isPowerOf2()) {
5069 // smulo(x, signed_min) is same as umulo(x, signed_min).
5070 bool UseArithShift = isSigned && !C.isMinSignedValue();
5071 SDValue ShiftAmt = DAG.getConstant(C.logBase2(), SL, MVT::i32);
5072 SDValue Result = DAG.getNode(ISD::SHL, SL, VT, LHS, ShiftAmt);
5073 SDValue Overflow = DAG.getSetCC(SL, MVT::i1,
5074 DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL,
5075 SL, VT, Result, ShiftAmt),
5076 LHS, ISD::SETNE);
5077 return DAG.getMergeValues({ Result, Overflow }, SL);
5078 }
5079 }
5080
5081 SDValue Result = DAG.getNode(ISD::MUL, SL, VT, LHS, RHS);
5082 SDValue Top = DAG.getNode(isSigned ? ISD::MULHS : ISD::MULHU,
5083 SL, VT, LHS, RHS);
5084
5085 SDValue Sign = isSigned
5086 ? DAG.getNode(ISD::SRA, SL, VT, Result,
5087 DAG.getConstant(VT.getScalarSizeInBits() - 1, SL, MVT::i32))
5088 : DAG.getConstant(0, SL, VT);
5089 SDValue Overflow = DAG.getSetCC(SL, MVT::i1, Top, Sign, ISD::SETNE);
5090
5091 return DAG.getMergeValues({ Result, Overflow }, SL);
5092}
5093
5094SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
5095 SDLoc SL(Op);
5096 SDValue Chain = Op.getOperand(0);
5097
5098 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
5099 !Subtarget->isTrapHandlerEnabled())
5100 return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain);
5101
5102 MachineFunction &MF = DAG.getMachineFunction();
5103 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5104 Register UserSGPR = Info->getQueuePtrUserSGPR();
5105 assert(UserSGPR != AMDGPU::NoRegister)((UserSGPR != AMDGPU::NoRegister) ? static_cast<void> (
0) : __assert_fail ("UserSGPR != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5105, __PRETTY_FUNCTION__))
;
5106 SDValue QueuePtr = CreateLiveInRegister(
5107 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
5108 SDValue SGPR01 = DAG.getRegister(AMDGPU::SGPR0_SGPR1, MVT::i64);
5109 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01,
5110 QueuePtr, SDValue());
5111 SDValue Ops[] = {
5112 ToReg,
5113 DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMTrap, SL, MVT::i16),
5114 SGPR01,
5115 ToReg.getValue(1)
5116 };
5117 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
5118}
5119
5120SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
5121 SDLoc SL(Op);
5122 SDValue Chain = Op.getOperand(0);
5123 MachineFunction &MF = DAG.getMachineFunction();
5124
5125 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
5126 !Subtarget->isTrapHandlerEnabled()) {
5127 DiagnosticInfoUnsupported NoTrap(MF.getFunction(),
5128 "debugtrap handler not supported",
5129 Op.getDebugLoc(),
5130 DS_Warning);
5131 LLVMContext &Ctx = MF.getFunction().getContext();
5132 Ctx.diagnose(NoTrap);
5133 return Chain;
5134 }
5135
5136 SDValue Ops[] = {
5137 Chain,
5138 DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMDebugTrap, SL, MVT::i16)
5139 };
5140 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
5141}
5142
5143SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
5144 SelectionDAG &DAG) const {
5145 // FIXME: Use inline constants (src_{shared, private}_base) instead.
5146 if (Subtarget->hasApertureRegs()) {
5147 unsigned Offset = AS == AMDGPUAS::LOCAL_ADDRESS ?
5148 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE :
5149 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE;
5150 unsigned WidthM1 = AS == AMDGPUAS::LOCAL_ADDRESS ?
5151 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
5152 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
5153 unsigned Encoding =
5154 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
5155 Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
5156 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
5157
5158 SDValue EncodingImm = DAG.getTargetConstant(Encoding, DL, MVT::i16);
5159 SDValue ApertureReg = SDValue(
5160 DAG.getMachineNode(AMDGPU::S_GETREG_B32, DL, MVT::i32, EncodingImm), 0);
5161 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32);
5162 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);
5163 }
5164
5165 MachineFunction &MF = DAG.getMachineFunction();
5166 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5167 Register UserSGPR = Info->getQueuePtrUserSGPR();
5168 assert(UserSGPR != AMDGPU::NoRegister)((UserSGPR != AMDGPU::NoRegister) ? static_cast<void> (
0) : __assert_fail ("UserSGPR != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5168, __PRETTY_FUNCTION__))
;
5169
5170 SDValue QueuePtr = CreateLiveInRegister(
5171 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
5172
5173 // Offset into amd_queue_t for group_segment_aperture_base_hi /
5174 // private_segment_aperture_base_hi.
5175 uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
5176
5177 SDValue Ptr =
5178 DAG.getObjectPtrOffset(DL, QueuePtr, TypeSize::Fixed(StructOffset));
5179
5180 // TODO: Use custom target PseudoSourceValue.
5181 // TODO: We should use the value from the IR intrinsic call, but it might not
5182 // be available and how do we get it?
5183 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
5184 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,
5185 commonAlignment(Align(64), StructOffset),
5186 MachineMemOperand::MODereferenceable |
5187 MachineMemOperand::MOInvariant);
5188}
5189
5190SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
5191 SelectionDAG &DAG) const {
5192 SDLoc SL(Op);
5193 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
5194
5195 SDValue Src = ASC->getOperand(0);
5196 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64);
5197
5198 const AMDGPUTargetMachine &TM =
5199 static_cast<const AMDGPUTargetMachine &>(getTargetMachine());
5200
5201 // flat -> local/private
5202 if (ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
5203 unsigned DestAS = ASC->getDestAddressSpace();
5204
5205 if (DestAS == AMDGPUAS::LOCAL_ADDRESS ||
5206 DestAS == AMDGPUAS::PRIVATE_ADDRESS) {
5207 unsigned NullVal = TM.getNullPointerValue(DestAS);
5208 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
5209 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE);
5210 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
5211
5212 return DAG.getNode(ISD::SELECT, SL, MVT::i32,
5213 NonNull, Ptr, SegmentNullPtr);
5214 }
5215 }
5216
5217 // local/private -> flat
5218 if (ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
5219 unsigned SrcAS = ASC->getSrcAddressSpace();
5220
5221 if (SrcAS == AMDGPUAS::LOCAL_ADDRESS ||
5222 SrcAS == AMDGPUAS::PRIVATE_ADDRESS) {
5223 unsigned NullVal = TM.getNullPointerValue(SrcAS);
5224 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
5225
5226 SDValue NonNull
5227 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE);
5228
5229 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), SL, DAG);
5230 SDValue CvtPtr
5231 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture);
5232
5233 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull,
5234 DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr),
5235 FlatNullPtr);
5236 }
5237 }
5238
5239 if (ASC->getDestAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT &&
5240 Src.getValueType() == MVT::i64)
5241 return DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
5242
5243 // global <-> flat are no-ops and never emitted.
5244
5245 const MachineFunction &MF = DAG.getMachineFunction();
5246 DiagnosticInfoUnsupported InvalidAddrSpaceCast(
5247 MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc());
5248 DAG.getContext()->diagnose(InvalidAddrSpaceCast);
5249
5250 return DAG.getUNDEF(ASC->getValueType(0));
5251}
5252
5253// This lowers an INSERT_SUBVECTOR by extracting the individual elements from
5254// the small vector and inserting them into the big vector. That is better than
5255// the default expansion of doing it via a stack slot. Even though the use of
5256// the stack slot would be optimized away afterwards, the stack slot itself
5257// remains.
5258SDValue SITargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
5259 SelectionDAG &DAG) const {
5260 SDValue Vec = Op.getOperand(0);
5261 SDValue Ins = Op.getOperand(1);
5262 SDValue Idx = Op.getOperand(2);
5263 EVT VecVT = Vec.getValueType();
5264 EVT InsVT = Ins.getValueType();
5265 EVT EltVT = VecVT.getVectorElementType();
5266 unsigned InsNumElts = InsVT.getVectorNumElements();
5267 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
5268 SDLoc SL(Op);
5269
5270 for (unsigned I = 0; I != InsNumElts; ++I) {
5271 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Ins,
5272 DAG.getConstant(I, SL, MVT::i32));
5273 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt,
5274 DAG.getConstant(IdxVal + I, SL, MVT::i32));
5275 }
5276 return Vec;
5277}
5278
5279SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
5280 SelectionDAG &DAG) const {
5281 SDValue Vec = Op.getOperand(0);
5282 SDValue InsVal = Op.getOperand(1);
5283 SDValue Idx = Op.getOperand(2);
5284 EVT VecVT = Vec.getValueType();
5285 EVT EltVT = VecVT.getVectorElementType();
5286 unsigned VecSize = VecVT.getSizeInBits();
5287 unsigned EltSize = EltVT.getSizeInBits();
5288
5289
5290 assert(VecSize <= 64)((VecSize <= 64) ? static_cast<void> (0) : __assert_fail
("VecSize <= 64", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5290, __PRETTY_FUNCTION__))
;
5291
5292 unsigned NumElts = VecVT.getVectorNumElements();
5293 SDLoc SL(Op);
5294 auto KIdx = dyn_cast<ConstantSDNode>(Idx);
5295
5296 if (NumElts == 4 && EltSize == 16 && KIdx) {
5297 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec);
5298
5299 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
5300 DAG.getConstant(0, SL, MVT::i32));
5301 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
5302 DAG.getConstant(1, SL, MVT::i32));
5303
5304 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf);
5305 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf);
5306
5307 unsigned Idx = KIdx->getZExtValue();
5308 bool InsertLo = Idx < 2;
5309 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16,
5310 InsertLo ? LoVec : HiVec,
5311 DAG.getNode(ISD::BITCAST, SL, MVT::i16, InsVal),
5312 DAG.getConstant(InsertLo ? Idx : (Idx - 2), SL, MVT::i32));
5313
5314 InsHalf = DAG.getNode(ISD::BITCAST, SL, MVT::i32, InsHalf);
5315
5316 SDValue Concat = InsertLo ?
5317 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) :
5318 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf });
5319
5320 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
5321 }
5322
5323 if (isa<ConstantSDNode>(Idx))
5324 return SDValue();
5325
5326 MVT IntVT = MVT::getIntegerVT(VecSize);
5327
5328 // Avoid stack access for dynamic indexing.
5329 // v_bfi_b32 (v_bfm_b32 16, (shl idx, 16)), val, vec
5330
5331 // Create a congruent vector with the target value in each element so that
5332 // the required element can be masked and ORed into the target vector.
5333 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT,
5334 DAG.getSplatBuildVector(VecVT, SL, InsVal));
5335
5336 assert(isPowerOf2_32(EltSize))((isPowerOf2_32(EltSize)) ? static_cast<void> (0) : __assert_fail
("isPowerOf2_32(EltSize)", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5336, __PRETTY_FUNCTION__))
;
5337 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
5338
5339 // Convert vector index to bit-index.
5340 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
5341
5342 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
5343 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT,
5344 DAG.getConstant(0xffff, SL, IntVT),
5345 ScaledIdx);
5346
5347 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal);
5348 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT,
5349 DAG.getNOT(SL, BFM, IntVT), BCVec);
5350
5351 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS);
5352 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI);
5353}
5354
5355SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
5356 SelectionDAG &DAG) const {
5357 SDLoc SL(Op);
5358
5359 EVT ResultVT = Op.getValueType();
5360 SDValue Vec = Op.getOperand(0);
5361 SDValue Idx = Op.getOperand(1);
5362 EVT VecVT = Vec.getValueType();
5363 unsigned VecSize = VecVT.getSizeInBits();
5364 EVT EltVT = VecVT.getVectorElementType();
5365 assert(VecSize <= 64)((VecSize <= 64) ? static_cast<void> (0) : __assert_fail
("VecSize <= 64", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5365, __PRETTY_FUNCTION__))
;
5366
5367 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
5368
5369 // Make sure we do any optimizations that will make it easier to fold
5370 // source modifiers before obscuring it with bit operations.
5371
5372 // XXX - Why doesn't this get called when vector_shuffle is expanded?
5373 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
5374 return Combined;
5375
5376 unsigned EltSize = EltVT.getSizeInBits();
5377 assert(isPowerOf2_32(EltSize))((isPowerOf2_32(EltSize)) ? static_cast<void> (0) : __assert_fail
("isPowerOf2_32(EltSize)", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5377, __PRETTY_FUNCTION__))
;
5378
5379 MVT IntVT = MVT::getIntegerVT(VecSize);
5380 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
5381
5382 // Convert vector index to bit-index (* EltSize)
5383 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
5384
5385 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
5386 SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx);
5387
5388 if (ResultVT == MVT::f16) {
5389 SDValue Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Elt);
5390 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
5391 }
5392
5393 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT);
5394}
5395
5396static bool elementPairIsContiguous(ArrayRef<int> Mask, int Elt) {
5397 assert(Elt % 2 == 0)((Elt % 2 == 0) ? static_cast<void> (0) : __assert_fail
("Elt % 2 == 0", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5397, __PRETTY_FUNCTION__))
;
5398 return Mask[Elt + 1] == Mask[Elt] + 1 && (Mask[Elt] % 2 == 0);
5399}
5400
5401SDValue SITargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
5402 SelectionDAG &DAG) const {
5403 SDLoc SL(Op);
5404 EVT ResultVT = Op.getValueType();
5405 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
5406
5407 EVT PackVT = ResultVT.isInteger() ? MVT::v2i16 : MVT::v2f16;
5408 EVT EltVT = PackVT.getVectorElementType();
5409 int SrcNumElts = Op.getOperand(0).getValueType().getVectorNumElements();
5410
5411 // vector_shuffle <0,1,6,7> lhs, rhs
5412 // -> concat_vectors (extract_subvector lhs, 0), (extract_subvector rhs, 2)
5413 //
5414 // vector_shuffle <6,7,2,3> lhs, rhs
5415 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 2)
5416 //
5417 // vector_shuffle <6,7,0,1> lhs, rhs
5418 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 0)
5419
5420 // Avoid scalarizing when both halves are reading from consecutive elements.
5421 SmallVector<SDValue, 4> Pieces;
5422 for (int I = 0, N = ResultVT.getVectorNumElements(); I != N; I += 2) {
5423 if (elementPairIsContiguous(SVN->getMask(), I)) {
5424 const int Idx = SVN->getMaskElt(I);
5425 int VecIdx = Idx < SrcNumElts ? 0 : 1;
5426 int EltIdx = Idx < SrcNumElts ? Idx : Idx - SrcNumElts;
5427 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL,
5428 PackVT, SVN->getOperand(VecIdx),
5429 DAG.getConstant(EltIdx, SL, MVT::i32));
5430 Pieces.push_back(SubVec);
5431 } else {
5432 const int Idx0 = SVN->getMaskElt(I);
5433 const int Idx1 = SVN->getMaskElt(I + 1);
5434 int VecIdx0 = Idx0 < SrcNumElts ? 0 : 1;
5435 int VecIdx1 = Idx1 < SrcNumElts ? 0 : 1;
5436 int EltIdx0 = Idx0 < SrcNumElts ? Idx0 : Idx0 - SrcNumElts;
5437 int EltIdx1 = Idx1 < SrcNumElts ? Idx1 : Idx1 - SrcNumElts;
5438
5439 SDValue Vec0 = SVN->getOperand(VecIdx0);
5440 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
5441 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32));
5442
5443 SDValue Vec1 = SVN->getOperand(VecIdx1);
5444 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
5445 Vec1, DAG.getConstant(EltIdx1, SL, MVT::i32));
5446 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 }));
5447 }
5448 }
5449
5450 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces);
5451}
5452
5453SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
5454 SelectionDAG &DAG) const {
5455 SDLoc SL(Op);
5456 EVT VT = Op.getValueType();
5457
5458 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
5459 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2);
5460
5461 // Turn into pair of packed build_vectors.
5462 // TODO: Special case for constants that can be materialized with s_mov_b64.
5463 SDValue Lo = DAG.getBuildVector(HalfVT, SL,
5464 { Op.getOperand(0), Op.getOperand(1) });
5465 SDValue Hi = DAG.getBuildVector(HalfVT, SL,
5466 { Op.getOperand(2), Op.getOperand(3) });
5467
5468 SDValue CastLo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Lo);
5469 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Hi);
5470
5471 SDValue Blend = DAG.getBuildVector(MVT::v2i32, SL, { CastLo, CastHi });
5472 return DAG.getNode(ISD::BITCAST, SL, VT, Blend);
5473 }
5474
5475 assert(VT == MVT::v2f16 || VT == MVT::v2i16)((VT == MVT::v2f16 || VT == MVT::v2i16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v2f16 || VT == MVT::v2i16"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5475, __PRETTY_FUNCTION__))
;
5476 assert(!Subtarget->hasVOP3PInsts() && "this should be legal")((!Subtarget->hasVOP3PInsts() && "this should be legal"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget->hasVOP3PInsts() && \"this should be legal\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5476, __PRETTY_FUNCTION__))
;
5477
5478 SDValue Lo = Op.getOperand(0);
5479 SDValue Hi = Op.getOperand(1);
5480
5481 // Avoid adding defined bits with the zero_extend.
5482 if (Hi.isUndef()) {
5483 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
5484 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo);
5485 return DAG.getNode(ISD::BITCAST, SL, VT, ExtLo);
5486 }
5487
5488 Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Hi);
5489 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi);
5490
5491 SDValue ShlHi = DAG.getNode(ISD::SHL, SL, MVT::i32, Hi,
5492 DAG.getConstant(16, SL, MVT::i32));
5493 if (Lo.isUndef())
5494 return DAG.getNode(ISD::BITCAST, SL, VT, ShlHi);
5495
5496 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
5497 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);
5498
5499 SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi);
5500 return DAG.getNode(ISD::BITCAST, SL, VT, Or);
5501}
5502
5503bool
5504SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5505 // We can fold offsets for anything that doesn't require a GOT relocation.
5506 return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
5507 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
5508 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
5509 !shouldEmitGOTReloc(GA->getGlobal());
5510}
5511
5512static SDValue
5513buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
5514 const SDLoc &DL, int64_t Offset, EVT PtrVT,
5515 unsigned GAFlags = SIInstrInfo::MO_NONE) {
5516 assert(isInt<32>(Offset + 4) && "32-bit offset is expected!")((isInt<32>(Offset + 4) && "32-bit offset is expected!"
) ? static_cast<void> (0) : __assert_fail ("isInt<32>(Offset + 4) && \"32-bit offset is expected!\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5516, __PRETTY_FUNCTION__))
;
5517 // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
5518 // lowered to the following code sequence:
5519 //
5520 // For constant address space:
5521 // s_getpc_b64 s[0:1]
5522 // s_add_u32 s0, s0, $symbol
5523 // s_addc_u32 s1, s1, 0
5524 //
5525 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5526 // a fixup or relocation is emitted to replace $symbol with a literal
5527 // constant, which is a pc-relative offset from the encoding of the $symbol
5528 // operand to the global variable.
5529 //
5530 // For global address space:
5531 // s_getpc_b64 s[0:1]
5532 // s_add_u32 s0, s0, $symbol@{gotpc}rel32@lo
5533 // s_addc_u32 s1, s1, $symbol@{gotpc}rel32@hi
5534 //
5535 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5536 // fixups or relocations are emitted to replace $symbol@*@lo and
5537 // $symbol@*@hi with lower 32 bits and higher 32 bits of a literal constant,
5538 // which is a 64-bit pc-relative offset from the encoding of the $symbol
5539 // operand to the global variable.
5540 //
5541 // What we want here is an offset from the value returned by s_getpc
5542 // (which is the address of the s_add_u32 instruction) to the global
5543 // variable, but since the encoding of $symbol starts 4 bytes after the start
5544 // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
5545 // small. This requires us to add 4 to the global variable offset in order to
5546 // compute the correct address. Similarly for the s_addc_u32 instruction, the
5547 // encoding of $symbol starts 12 bytes after the start of the s_add_u32
5548 // instruction.
5549 SDValue PtrLo =
5550 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags);
5551 SDValue PtrHi;
5552 if (GAFlags == SIInstrInfo::MO_NONE) {
5553 PtrHi = DAG.getTargetConstant(0, DL, MVT::i32);
5554 } else {
5555 PtrHi =
5556 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 12, GAFlags + 1);
5557 }
5558 return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, PtrLo, PtrHi);
5559}
5560
5561SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
5562 SDValue Op,
5563 SelectionDAG &DAG) const {
5564 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
5565 SDLoc DL(GSD);
5566 EVT PtrVT = Op.getValueType();
5567
5568 const GlobalValue *GV = GSD->getGlobal();
5569 if ((GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
5570 shouldUseLDSConstAddress(GV)) ||
5571 GSD->getAddressSpace() == AMDGPUAS::REGION_ADDRESS ||
5572 GSD->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
5573 if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
5574 GV->hasExternalLinkage()) {
5575 Type *Ty = GV->getValueType();
5576 // HIP uses an unsized array `extern __shared__ T s[]` or similar
5577 // zero-sized type in other languages to declare the dynamic shared
5578 // memory which size is not known at the compile time. They will be
5579 // allocated by the runtime and placed directly after the static
5580 // allocated ones. They all share the same offset.
5581 if (DAG.getDataLayout().getTypeAllocSize(Ty).isZero()) {
5582 assert(PtrVT == MVT::i32 && "32-bit pointer is expected.")((PtrVT == MVT::i32 && "32-bit pointer is expected.")
? static_cast<void> (0) : __assert_fail ("PtrVT == MVT::i32 && \"32-bit pointer is expected.\""
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5582, __PRETTY_FUNCTION__))
;
5583 // Adjust alignment for that dynamic shared memory array.
5584 MFI->setDynLDSAlign(DAG.getDataLayout(), *cast<GlobalVariable>(GV));
5585 return SDValue(
5586 DAG.getMachineNode(AMDGPU::GET_GROUPSTATICSIZE, DL, PtrVT), 0);
5587 }
5588 }
5589 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
5590 }
5591
5592 if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
5593 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, GSD->getOffset(),
5594 SIInstrInfo::MO_ABS32_LO);
5595 return DAG.getNode(AMDGPUISD::LDS, DL, MVT::i32, GA);
5596 }
5597
5598 if (shouldEmitFixup(GV))
5599 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
5600 else if (shouldEmitPCReloc(GV))
5601 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
5602 SIInstrInfo::MO_REL32);
5603
5604 SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
5605 SIInstrInfo::MO_GOTPCREL32);
5606
5607 Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
5608 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
5609 const DataLayout &DataLayout = DAG.getDataLayout();
5610 Align Alignment = DataLayout.getABITypeAlign(PtrTy);
5611 MachinePointerInfo PtrInfo
5612 = MachinePointerInfo::getGOT(DAG.getMachineFunction());
5613
5614 return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Alignment,
5615 MachineMemOperand::MODereferenceable |
5616 MachineMemOperand::MOInvariant);
5617}
5618
5619SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
5620 const SDLoc &DL, SDValue V) const {
5621 // We can't use S_MOV_B32 directly, because there is no way to specify m0 as
5622 // the destination register.
5623 //
5624 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
5625 // so we will end up with redundant moves to m0.
5626 //
5627 // We use a pseudo to ensure we emit s_mov_b32 with m0 as the direct result.
5628
5629 // A Null SDValue creates a glue result.
5630 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue,
5631 V, Chain);
5632 return SDValue(M0, 0);
5633}
5634
5635SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
5636 SDValue Op,
5637 MVT VT,
5638 unsigned Offset) const {
5639 SDLoc SL(Op);
5640 SDValue Param = lowerKernargMemParameter(
5641 DAG, MVT::i32, MVT::i32, SL, DAG.getEntryNode(), Offset, Align(4), false);
5642 // The local size values will have the hi 16-bits as zero.
5643 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
5644 DAG.getValueType(VT));
5645}
5646
5647static SDValue emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5648 EVT VT) {
5649 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5650 "non-hsa intrinsic with hsa target",
5651 DL.getDebugLoc());
5652 DAG.getContext()->diagnose(BadIntrin);
5653 return DAG.getUNDEF(VT);
5654}
5655
5656static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5657 EVT VT) {
5658 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5659 "intrinsic not supported on subtarget",
5660 DL.getDebugLoc());
5661 DAG.getContext()->diagnose(BadIntrin);
5662 return DAG.getUNDEF(VT);
5663}
5664
5665static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
5666 ArrayRef<SDValue> Elts) {
5667 assert(!Elts.empty())((!Elts.empty()) ? static_cast<void> (0) : __assert_fail
("!Elts.empty()", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5667, __PRETTY_FUNCTION__))
;
5668 MVT Type;
5669 unsigned NumElts;
5670
5671 if (Elts.size() == 1) {
5672 Type = MVT::f32;
5673 NumElts = 1;
5674 } else if (Elts.size() == 2) {
5675 Type = MVT::v2f32;
5676 NumElts = 2;
5677 } else if (Elts.size() == 3) {
5678 Type = MVT::v3f32;
5679 NumElts = 3;
5680 } else if (Elts.size() <= 4) {
5681 Type = MVT::v4f32;
5682 NumElts = 4;
5683 } else if (Elts.size() <= 8) {
5684 Type = MVT::v8f32;
5685 NumElts = 8;
5686 } else {
5687 assert(Elts.size() <= 16)((Elts.size() <= 16) ? static_cast<void> (0) : __assert_fail
("Elts.size() <= 16", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5687, __PRETTY_FUNCTION__))
;
5688 Type = MVT::v16f32;
5689 NumElts = 16;
5690 }
5691
5692 SmallVector<SDValue, 16> VecElts(NumElts);
5693 for (unsigned i = 0; i < Elts.size(); ++i) {
5694 SDValue Elt = Elts[i];
5695 if (Elt.getValueType() != MVT::f32)
5696 Elt = DAG.getBitcast(MVT::f32, Elt);
5697 VecElts[i] = Elt;
5698 }
5699 for (unsigned i = Elts.size(); i < NumElts; ++i)
5700 VecElts[i] = DAG.getUNDEF(MVT::f32);
5701
5702 if (NumElts == 1)
5703 return VecElts[0];
5704 return DAG.getBuildVector(Type, DL, VecElts);
5705}
5706
5707static bool parseCachePolicy(SDValue CachePolicy, SelectionDAG &DAG,
5708 SDValue *GLC, SDValue *SLC, SDValue *DLC) {
5709 auto CachePolicyConst = cast<ConstantSDNode>(CachePolicy.getNode());
5710
5711 uint64_t Value = CachePolicyConst->getZExtValue();
5712 SDLoc DL(CachePolicy);
5713 if (GLC) {
5714 *GLC = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
5715 Value &= ~(uint64_t)0x1;
5716 }
5717 if (SLC) {
5718 *SLC = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
5719 Value &= ~(uint64_t)0x2;
5720 }
5721 if (DLC) {
5722 *DLC = DAG.getTargetConstant((Value & 0x4) ? 1 : 0, DL, MVT::i32);
5723 Value &= ~(uint64_t)0x4;
5724 }
5725
5726 return Value == 0;
5727}
5728
5729static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT,
5730 SDValue Src, int ExtraElts) {
5731 EVT SrcVT = Src.getValueType();
5732
5733 SmallVector<SDValue, 8> Elts;
5734
5735 if (SrcVT.isVector())
5736 DAG.ExtractVectorElements(Src, Elts);
5737 else
5738 Elts.push_back(Src);
5739
5740 SDValue Undef = DAG.getUNDEF(SrcVT.getScalarType());
5741 while (ExtraElts--)
5742 Elts.push_back(Undef);
5743
5744 return DAG.getBuildVector(CastVT, DL, Elts);
5745}
5746
5747// Re-construct the required return value for a image load intrinsic.
5748// This is more complicated due to the optional use TexFailCtrl which means the required
5749// return type is an aggregate
5750static SDValue constructRetValue(SelectionDAG &DAG,
5751 MachineSDNode *Result,
5752 ArrayRef<EVT> ResultTypes,
5753 bool IsTexFail, bool Unpacked, bool IsD16,
5754 int DMaskPop, int NumVDataDwords,
5755 const SDLoc &DL, LLVMContext &Context) {
5756 // Determine the required return type. This is the same regardless of IsTexFail flag
5757 EVT ReqRetVT = ResultTypes[0];
5758 int ReqRetNumElts = ReqRetVT.isVector() ? ReqRetVT.getVectorNumElements() : 1;
5759 int NumDataDwords = (!IsD16 || (IsD16 && Unpacked)) ?
5760 ReqRetNumElts : (ReqRetNumElts + 1) / 2;
5761
5762 int MaskPopDwords = (!IsD16 || (IsD16 && Unpacked)) ?
5763 DMaskPop : (DMaskPop + 1) / 2;
5764
5765 MVT DataDwordVT = NumDataDwords == 1 ?
5766 MVT::i32 : MVT::getVectorVT(MVT::i32, NumDataDwords);
5767
5768 MVT MaskPopVT = MaskPopDwords == 1 ?
5769 MVT::i32 : MVT::getVectorVT(MVT::i32, MaskPopDwords);
5770
5771 SDValue Data(Result, 0);
5772 SDValue TexFail;
5773
5774 if (DMaskPop > 0 && Data.getValueType() != MaskPopVT) {
5775 SDValue ZeroIdx = DAG.getConstant(0, DL, MVT::i32);
5776 if (MaskPopVT.isVector()) {
5777 Data = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MaskPopVT,
5778 SDValue(Result, 0), ZeroIdx);
5779 } else {
5780 Data = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MaskPopVT,
5781 SDValue(Result, 0), ZeroIdx);
5782 }
5783 }
5784
5785 if (DataDwordVT.isVector())
5786 Data = padEltsToUndef(DAG, DL, DataDwordVT, Data,
5787 NumDataDwords - MaskPopDwords);
5788
5789 if (IsD16)
5790 Data = adjustLoadValueTypeImpl(Data, ReqRetVT, DL, DAG, Unpacked);
5791
5792 EVT LegalReqRetVT = ReqRetVT;
5793 if (!ReqRetVT.isVector()) {
5794 Data = DAG.getNode(ISD::TRUNCATE, DL, ReqRetVT.changeTypeToInteger(), Data);
5795 } else {
5796 // We need to widen the return vector to a legal type
5797 if ((ReqRetVT.getVectorNumElements() % 2) == 1 &&
5798 ReqRetVT.getVectorElementType().getSizeInBits() == 16) {
5799 LegalReqRetVT =
5800 EVT::getVectorVT(*DAG.getContext(), ReqRetVT.getVectorElementType(),
5801 ReqRetVT.getVectorNumElements() + 1);
5802 }
5803 }
5804 Data = DAG.getNode(ISD::BITCAST, DL, LegalReqRetVT, Data);
5805
5806 if (IsTexFail) {
5807 TexFail =
5808 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, SDValue(Result, 0),
5809 DAG.getConstant(MaskPopDwords, DL, MVT::i32));
5810
5811 return DAG.getMergeValues({Data, TexFail, SDValue(Result, 1)}, DL);
5812 }
5813
5814 if (Result->getNumValues() == 1)
5815 return Data;
5816
5817 return DAG.getMergeValues({Data, SDValue(Result, 1)}, DL);
5818}
5819
5820static bool parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE,
5821 SDValue *LWE, bool &IsTexFail) {
5822 auto TexFailCtrlConst = cast<ConstantSDNode>(TexFailCtrl.getNode());
5823
5824 uint64_t Value = TexFailCtrlConst->getZExtValue();
5825 if (Value) {
5826 IsTexFail = true;
5827 }
5828
5829 SDLoc DL(TexFailCtrlConst);
5830 *TFE = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
5831 Value &= ~(uint64_t)0x1;
5832 *LWE = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
5833 Value &= ~(uint64_t)0x2;
5834
5835 return Value == 0;
5836}
5837
5838static void packImageA16AddressToDwords(SelectionDAG &DAG, SDValue Op,
5839 MVT PackVectorVT,
5840 SmallVectorImpl<SDValue> &PackedAddrs,
5841 unsigned DimIdx, unsigned EndIdx,
5842 unsigned NumGradients) {
5843 SDLoc DL(Op);
5844 for (unsigned I = DimIdx; I < EndIdx; I++) {
5845 SDValue Addr = Op.getOperand(I);
5846
5847 // Gradients are packed with undef for each coordinate.
5848 // In <hi 16 bit>,<lo 16 bit> notation, the registers look like this:
5849 // 1D: undef,dx/dh; undef,dx/dv
5850 // 2D: dy/dh,dx/dh; dy/dv,dx/dv
5851 // 3D: dy/dh,dx/dh; undef,dz/dh; dy/dv,dx/dv; undef,dz/dv
5852 if (((I + 1) >= EndIdx) ||
5853 ((NumGradients / 2) % 2 == 1 && (I == DimIdx + (NumGradients / 2) - 1 ||
5854 I == DimIdx + NumGradients - 1))) {
5855 if (Addr.getValueType() != MVT::i16)
5856 Addr = DAG.getBitcast(MVT::i16, Addr);
5857 Addr = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Addr);
5858 } else {
5859 Addr = DAG.getBuildVector(PackVectorVT, DL, {Addr, Op.getOperand(I + 1)});
5860 I++;
5861 }
5862 Addr = DAG.getBitcast(MVT::f32, Addr);
5863 PackedAddrs.push_back(Addr);
5864 }
5865}
5866
5867SDValue SITargetLowering::lowerImage(SDValue Op,
5868 const AMDGPU::ImageDimIntrinsicInfo *Intr,
5869 SelectionDAG &DAG, bool WithChain) const {
5870 SDLoc DL(Op);
5871 MachineFunction &MF = DAG.getMachineFunction();
5872 const GCNSubtarget* ST = &MF.getSubtarget<GCNSubtarget>();
5873 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
5874 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
5875 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfo(Intr->Dim);
5876 const AMDGPU::MIMGLZMappingInfo *LZMappingInfo =
5877 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
5878 const AMDGPU::MIMGMIPMappingInfo *MIPMappingInfo =
5879 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
5880 unsigned IntrOpcode = Intr->BaseOpcode;
5881 bool IsGFX10Plus = AMDGPU::isGFX10Plus(*Subtarget);
5882
5883 SmallVector<EVT, 3> ResultTypes(Op->values());
5884 SmallVector<EVT, 3> OrigResultTypes(Op->values());
5885 bool IsD16 = false;
5886 bool IsG16 = false;
5887 bool IsA16 = false;
5888 SDValue VData;
5889 int NumVDataDwords;
5890 bool AdjustRetType = false;
5891
5892 // Offset of intrinsic arguments
5893 const unsigned ArgOffset = WithChain ? 2 : 1;
5894
5895 unsigned DMask;
5896 unsigned DMaskLanes = 0;
5897
5898 if (BaseOpcode->Atomic) {
5899 VData = Op.getOperand(2);
5900
5901 bool Is64Bit = VData.getValueType() == MVT::i64;
5902 if (BaseOpcode->AtomicX2) {
5903 SDValue VData2 = Op.getOperand(3);
5904 VData = DAG.getBuildVector(Is64Bit ? MVT::v2i64 : MVT::v2i32, DL,
5905 {VData, VData2});
5906 if (Is64Bit)
5907 VData = DAG.getBitcast(MVT::v4i32, VData);
5908
5909 ResultTypes[0] = Is64Bit ? MVT::v2i64 : MVT::v2i32;
5910 DMask = Is64Bit ? 0xf : 0x3;
5911 NumVDataDwords = Is64Bit ? 4 : 2;
5912 } else {
5913 DMask = Is64Bit ? 0x3 : 0x1;
5914 NumVDataDwords = Is64Bit ? 2 : 1;
5915 }
5916 } else {
5917 auto *DMaskConst =
5918 cast<ConstantSDNode>(Op.getOperand(ArgOffset + Intr->DMaskIndex));
5919 DMask = DMaskConst->getZExtValue();
5920 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask);
5921
5922 if (BaseOpcode->Store) {
5923 VData = Op.getOperand(2);
5924
5925 MVT StoreVT = VData.getSimpleValueType();
5926 if (StoreVT.getScalarType() == MVT::f16) {
5927 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
5928 return Op; // D16 is unsupported for this instruction
5929
5930 IsD16 = true;
5931 VData = handleD16VData(VData, DAG, true);
5932 }
5933
5934 NumVDataDwords = (VData.getValueType().getSizeInBits() + 31) / 32;
5935 } else {
5936 // Work out the num dwords based on the dmask popcount and underlying type
5937 // and whether packing is supported.
5938 MVT LoadVT = ResultTypes[0].getSimpleVT();
5939 if (LoadVT.getScalarType() == MVT::f16) {
5940 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
5941 return Op; // D16 is unsupported for this instruction
5942
5943 IsD16 = true;
5944 }
5945
5946 // Confirm that the return type is large enough for the dmask specified
5947 if ((LoadVT.isVector() && LoadVT.getVectorNumElements() < DMaskLanes) ||
5948 (!LoadVT.isVector() && DMaskLanes > 1))
5949 return Op;
5950
5951 // The sq block of gfx8 and gfx9 do not estimate register use correctly
5952 // for d16 image_gather4, image_gather4_l, and image_gather4_lz
5953 // instructions.
5954 if (IsD16 && !Subtarget->hasUnpackedD16VMem() &&
5955 !(BaseOpcode->Gather4 && Subtarget->hasImageGather4D16Bug()))
5956 NumVDataDwords = (DMaskLanes + 1) / 2;
5957 else
5958 NumVDataDwords = DMaskLanes;
5959
5960 AdjustRetType = true;
5961 }
5962 }
5963
5964 unsigned VAddrEnd = ArgOffset + Intr->VAddrEnd;
5965 SmallVector<SDValue, 4> VAddrs;
5966
5967 // Optimize _L to _LZ when _L is zero
5968 if (LZMappingInfo) {
5969 if (auto *ConstantLod = dyn_cast<ConstantFPSDNode>(
5970 Op.getOperand(ArgOffset + Intr->LodIndex))) {
5971 if (ConstantLod->isZero() || ConstantLod->isNegative()) {
5972 IntrOpcode = LZMappingInfo->LZ; // set new opcode to _lz variant of _l
5973 VAddrEnd--; // remove 'lod'
5974 }
5975 }
5976 }
5977
5978 // Optimize _mip away, when 'lod' is zero
5979 if (MIPMappingInfo) {
5980 if (auto *ConstantLod = dyn_cast<ConstantSDNode>(
5981 Op.getOperand(ArgOffset + Intr->MipIndex))) {
5982 if (ConstantLod->isNullValue()) {
5983 IntrOpcode = MIPMappingInfo->NONMIP; // set new opcode to variant without _mip
5984 VAddrEnd--; // remove 'mip'
5985 }
5986 }
5987 }
5988
5989 // Push back extra arguments.
5990 for (unsigned I = Intr->VAddrStart; I < Intr->GradientStart; I++)
5991 VAddrs.push_back(Op.getOperand(ArgOffset + I));
5992
5993 // Check for 16 bit addresses or derivatives and pack if true.
5994 MVT VAddrVT =
5995 Op.getOperand(ArgOffset + Intr->GradientStart).getSimpleValueType();
5996 MVT VAddrScalarVT = VAddrVT.getScalarType();
5997 MVT PackVectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
5998 IsG16 = VAddrScalarVT == MVT::f16 || VAddrScalarVT == MVT::i16;
5999
6000 VAddrVT = Op.getOperand(ArgOffset + Intr->CoordStart).getSimpleValueType();
6001 VAddrScalarVT = VAddrVT.getScalarType();
6002 IsA16 = VAddrScalarVT == MVT::f16 || VAddrScalarVT == MVT::i16;
6003 if (IsA16 || IsG16) {
6004 if (IsA16) {
6005 if (!ST->hasA16()) {
6006 LLVM_DEBUG(dbgs() << "Failed to lower image intrinsic: Target does not "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("si-lower")) { dbgs() << "Failed to lower image intrinsic: Target does not "
"support 16 bit addresses\n"; } } while (false)
6007 "support 16 bit addresses\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("si-lower")) { dbgs() << "Failed to lower image intrinsic: Target does not "
"support 16 bit addresses\n"; } } while (false)
;
6008 return Op;
6009 }
6010 if (!IsG16) {
6011 LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("si-lower")) { dbgs() << "Failed to lower image intrinsic: 16 bit addresses "
"need 16 bit derivatives but got 32 bit derivatives\n"; } } while
(false)
6012 dbgs() << "Failed to lower image intrinsic: 16 bit addresses "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("si-lower")) { dbgs() << "Failed to lower image intrinsic: 16 bit addresses "
"need 16 bit derivatives but got 32 bit derivatives\n"; } } while
(false)
6013 "need 16 bit derivatives but got 32 bit derivatives\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("si-lower")) { dbgs() << "Failed to lower image intrinsic: 16 bit addresses "
"need 16 bit derivatives but got 32 bit derivatives\n"; } } while
(false)
;
6014 return Op;
6015 }
6016 } else if (!ST->hasG16()) {
6017 LLVM_DEBUG(dbgs() << "Failed to lower image intrinsic: Target does not "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("si-lower")) { dbgs() << "Failed to lower image intrinsic: Target does not "
"support 16 bit derivatives\n"; } } while (false)
6018 "support 16 bit derivatives\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("si-lower")) { dbgs() << "Failed to lower image intrinsic: Target does not "
"support 16 bit derivatives\n"; } } while (false)
;
6019 return Op;
6020 }
6021
6022 if (BaseOpcode->Gradients && !IsA16) {
6023 if (!ST->hasG16()) {
6024 LLVM_DEBUG(dbgs() << "Failed to lower image intrinsic: Target does not "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("si-lower")) { dbgs() << "Failed to lower image intrinsic: Target does not "
"support 16 bit derivatives\n"; } } while (false)
6025 "support 16 bit derivatives\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("si-lower")) { dbgs() << "Failed to lower image intrinsic: Target does not "
"support 16 bit derivatives\n"; } } while (false)
;
6026 return Op;
6027 }
6028 // Activate g16
6029 const AMDGPU::MIMGG16MappingInfo *G16MappingInfo =
6030 AMDGPU::getMIMGG16MappingInfo(Intr->BaseOpcode);
6031 IntrOpcode = G16MappingInfo->G16; // set new opcode to variant with _g16
6032 }
6033
6034 // Don't compress addresses for G16
6035 const int PackEndIdx = IsA16 ? VAddrEnd : (ArgOffset + Intr->CoordStart);
6036 packImageA16AddressToDwords(DAG, Op, PackVectorVT, VAddrs,
6037 ArgOffset + Intr->GradientStart, PackEndIdx,
6038 Intr->NumGradients);
6039
6040 if (!IsA16) {
6041 // Add uncompressed address
6042 for (unsigned I = ArgOffset + Intr->CoordStart; I < VAddrEnd; I++)
6043 VAddrs.push_back(Op.getOperand(I));
6044 }
6045 } else {
6046 for (unsigned I = ArgOffset + Intr->GradientStart; I < VAddrEnd; I++)
6047 VAddrs.push_back(Op.getOperand(I));
6048 }
6049
6050 // If the register allocator cannot place the address registers contiguously
6051 // without introducing moves, then using the non-sequential address encoding
6052 // is always preferable, since it saves VALU instructions and is usually a
6053 // wash in terms of code size or even better.
6054 //
6055 // However, we currently have no way of hinting to the register allocator that
6056 // MIMG addresses should be placed contiguously when it is possible to do so,
6057 // so force non-NSA for the common 2-address case as a heuristic.
6058 //
6059 // SIShrinkInstructions will convert NSA encodings to non-NSA after register
6060 // allocation when possible.
6061 bool UseNSA =
6062 ST->hasFeature(AMDGPU::FeatureNSAEncoding) && VAddrs.size() >= 3;
6063 SDValue VAddr;
6064 if (!UseNSA)
6065 VAddr = getBuildDwordsVector(DAG, DL, VAddrs);
6066
6067 SDValue True = DAG.getTargetConstant(1, DL, MVT::i1);
6068 SDValue False = DAG.getTargetConstant(0, DL, MVT::i1);
6069 SDValue Unorm;
6070 if (!BaseOpcode->Sampler) {
6071 Unorm = True;
6072 } else {
6073 auto UnormConst =
6074 cast<ConstantSDNode>(Op.getOperand(ArgOffset + Intr->UnormIndex));
6075
6076 Unorm = UnormConst->getZExtValue() ? True : False;
6077 }
6078
6079 SDValue TFE;
6080 SDValue LWE;
6081 SDValue TexFail = Op.getOperand(ArgOffset + Intr->TexFailCtrlIndex);
6082 bool IsTexFail = false;
6083 if (!parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail))
6084 return Op;
6085
6086 if (IsTexFail) {
6087 if (!DMaskLanes) {
6088 // Expecting to get an error flag since TFC is on - and dmask is 0
6089 // Force dmask to be at least 1 otherwise the instruction will fail
6090 DMask = 0x1;
6091 DMaskLanes = 1;
6092 NumVDataDwords = 1;
6093 }
6094 NumVDataDwords += 1;
6095 AdjustRetType = true;
6096 }
6097
6098 // Has something earlier tagged that the return type needs adjusting
6099 // This happens if the instruction is a load or has set TexFailCtrl flags
6100 if (AdjustRetType) {
6101 // NumVDataDwords reflects the true number of dwords required in the return type
6102 if (DMaskLanes == 0 && !BaseOpcode->Store) {
6103 // This is a no-op load. This can be eliminated
6104 SDValue Undef = DAG.getUNDEF(Op.getValueType());
6105 if (isa<MemSDNode>(Op))
6106 return DAG.getMergeValues({Undef, Op.getOperand(0)}, DL);
6107 return Undef;
6108 }
6109
6110 EVT NewVT = NumVDataDwords > 1 ?
6111 EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumVDataDwords)
6112 : MVT::i32;
6113
6114 ResultTypes[0] = NewVT;
6115 if (ResultTypes.size() == 3) {
6116 // Original result was aggregate type used for TexFailCtrl results
6117 // The actual instruction returns as a vector type which has now been
6118 // created. Remove the aggregate result.
6119 ResultTypes.erase(&ResultTypes[1]);
6120 }
6121 }
6122
6123 SDValue GLC;
6124 SDValue SLC;
6125 SDValue DLC;
6126 if (BaseOpcode->Atomic) {
6127 GLC = True; // TODO no-return optimization
6128 if (!parseCachePolicy(Op.getOperand(ArgOffset + Intr->CachePolicyIndex),
6129 DAG, nullptr, &SLC, IsGFX10Plus ? &DLC : nullptr))
6130 return Op;
6131 } else {
6132 if (!parseCachePolicy(Op.getOperand(ArgOffset + Intr->CachePolicyIndex),
6133 DAG, &GLC, &SLC, IsGFX10Plus ? &DLC : nullptr))
6134 return Op;
6135 }
6136
6137 SmallVector<SDValue, 26> Ops;
6138 if (BaseOpcode->Store || BaseOpcode->Atomic)
6139 Ops.push_back(VData); // vdata
6140 if (UseNSA)
6141 append_range(Ops, VAddrs);
6142 else
6143 Ops.push_back(VAddr);
6144 Ops.push_back(Op.getOperand(ArgOffset + Intr->RsrcIndex));
6145 if (BaseOpcode->Sampler)
6146 Ops.push_back(Op.getOperand(ArgOffset + Intr->SampIndex));
6147 Ops.push_back(DAG.getTargetConstant(DMask, DL, MVT::i32));
6148 if (IsGFX10Plus)
6149 Ops.push_back(DAG.getTargetConstant(DimInfo->Encoding, DL, MVT::i32));
6150 Ops.push_back(Unorm);
6151 if (IsGFX10Plus)
6152 Ops.push_back(DLC);
6153 Ops.push_back(GLC);
6154 Ops.push_back(SLC);
6155 Ops.push_back(IsA16 && // r128, a16 for gfx9
6156 ST->hasFeature(AMDGPU::FeatureR128A16) ? True : False);
6157 if (IsGFX10Plus)
6158 Ops.push_back(IsA16 ? True : False);
6159 Ops.push_back(TFE);
6160 Ops.push_back(LWE);
6161 if (!IsGFX10Plus)
6162 Ops.push_back(DimInfo->DA ? True : False);
6163 if (BaseOpcode->HasD16)
6164 Ops.push_back(IsD16 ? True : False);
6165 if (isa<MemSDNode>(Op))
6166 Ops.push_back(Op.getOperand(0)); // chain
6167
6168 int NumVAddrDwords =
6169 UseNSA ? VAddrs.size() : VAddr.getValueType().getSizeInBits() / 32;
6170 int Opcode = -1;
6171
6172 if (IsGFX10Plus) {
6173 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode,
6174 UseNSA ? AMDGPU::MIMGEncGfx10NSA
6175 : AMDGPU::MIMGEncGfx10Default,
6176 NumVDataDwords, NumVAddrDwords);
6177 } else {
6178 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
6179 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx8,
6180 NumVDataDwords, NumVAddrDwords);
6181 if (Opcode == -1)
6182 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx6,
6183 NumVDataDwords, NumVAddrDwords);
6184 }
6185 assert(Opcode != -1)((Opcode != -1) ? static_cast<void> (0) : __assert_fail
("Opcode != -1", "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6185, __PRETTY_FUNCTION__))
;
6186
6187 MachineSDNode *NewNode = DAG.getMachineNode(Opcode, DL, ResultTypes, Ops);
6188 if (auto MemOp = dyn_cast<MemSDNode>(Op)) {
6189 MachineMemOperand *MemRef = MemOp->getMemOperand();
6190 DAG.setNodeMemRefs(NewNode, {MemRef});
6191 }
6192
6193 if (BaseOpcode->AtomicX2) {
6194 SmallVector<SDValue, 1> Elt;
6195 DAG.ExtractVectorElements(SDValue(NewNode, 0), Elt, 0, 1);
6196 return DAG.getMergeValues({Elt[0], SDValue(NewNode, 1)}, DL);
6197 } else if (!BaseOpcode->Store) {
6198 return constructRetValue(DAG, NewNode,
6199 OrigResultTypes, IsTexFail,
6200 Subtarget->hasUnpackedD16VMem(), IsD16,
6201 DMaskLanes, NumVDataDwords, DL,
6202 *DAG.getContext());
6203 }
6204
6205 return SDValue(NewNode, 0);
6206}
6207
6208SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc,
6209 SDValue Offset, SDValue CachePolicy,
6210 SelectionDAG &DAG) const {
6211 MachineFunction &MF = DAG.getMachineFunction();
6212
6213 const DataLayout &DataLayout = DAG.getDataLayout();
6214 Align Alignment =
6215 DataLayout.getABITypeAlign(VT.getTypeForEVT(*DAG.getContext()));
6216
6217 MachineMemOperand *MMO = MF.getMachineMemOperand(
6218 MachinePointerInfo(),
6219 MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
6220 MachineMemOperand::MOInvariant,
6221 VT.getStoreSize(), Alignment);
6222
6223 if (!Offset->isDivergent()) {
6224 SDValue Ops[] = {
6225 Rsrc,
6226 Offset, // Offset
6227 CachePolicy
6228 };
6229
6230 // Widen vec3 load to vec4.
6231 if (VT.isVector() && VT.getVectorNumElements() == 3) {
6232 EVT WidenedVT =
6233 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4);
6234 auto WidenedOp = DAG.getMemIntrinsicNode(
6235 AMDGPUISD::SBUFFER_LOAD, DL, DAG.getVTList(WidenedVT), Ops, WidenedVT,
6236 MF.getMachineMemOperand(MMO, 0, WidenedVT.getStoreSize()));
6237 auto Subvector = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp,
6238 DAG.getVectorIdxConstant(0, DL));
6239 return Subvector;
6240 }
6241
6242 return DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD, DL,
6243 DAG.getVTList(VT), Ops, VT, MMO);
6244 }
6245
6246 // We have a divergent offset. Emit a MUBUF buffer load instead. We can
6247 // assume that the buffer is unswizzled.
6248 SmallVector<SDValue, 4> Loads;
6249 unsigned NumLoads = 1;
6250 MVT LoadVT = VT.getSimpleVT();
6251 unsigned NumElts = LoadVT.isVector() ? LoadVT.getVectorNumElements() : 1;
6252 assert((LoadVT.getScalarType() == MVT::i32 ||(((LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType
() == MVT::f32)) ? static_cast<void> (0) : __assert_fail
("(LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType() == MVT::f32)"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6253, __PRETTY_FUNCTION__))
6253 LoadVT.getScalarType() == MVT::f32))(((LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType
() == MVT::f32)) ? static_cast<void> (0) : __assert_fail
("(LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType() == MVT::f32)"
, "/build/llvm-toolchain-snapshot-12~++20210125100614+2cdb34efdac5/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6253, __PRETTY_FUNCTION__))
;
6254
6255 if (NumElts == 8 || NumElts == 16) {
6256 NumLoads = NumElts / 4;
6257 LoadVT = MVT::getVectorVT(LoadVT.getScalarType(), 4);
6258 }
6259
6260 SDVTList VTList = DAG.getVTList({LoadVT, MVT::Glue});
6261 SDValue Ops[] = {
6262 DAG.getEntryNode(), // Chain
6263 Rsrc, // rsrc
6264 DAG.getConstant(0, DL, MVT::i32), // vindex
6265 {}, // voffset
6266 {}, // soffset
6267 {}, // offset
6268 CachePolicy, // cachepolicy
6269 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
6270 };
6271
6272 // Use the alignment to ensure that the required offsets will fit into the
6273 // immediate offsets.
6274 setBufferOffsets(Offset, DAG, &Ops[3],
6275 NumLoads > 1 ? Align(16 * NumLoads) : Align(4));
6276
6277 uint64_t InstOffset = cast<ConstantSDNode>(Ops[5])->getZExtValue();
6278 for (unsigned i = 0; i < NumLoads; ++i) {
6279 Ops[5] = DAG.getTargetConstant(InstOffset + 16 * i, DL, MVT::i32);
6280 Loads.push_back(getMemIntrinsicNode(AMDGPUISD::BUFFER_LOAD, DL, VTList, Ops,
6281 LoadVT, MMO, DAG));
6282 }
6283
6284 if (NumElts == 8 || NumElts == 16)
6285 return DAG.getNode(ISD::CONCAT_VECTORS, D