Bug Summary

File:llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Warning:line 11189, column 52
Called C++ object pointer is null

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name SIISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/build-llvm -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU -I include -I /build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/include -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-command-line-argument -Wno-unknown-warning-option -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/build-llvm -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2021-11-10-160236-22541-1 -x c++ /build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Custom DAG lowering for SI
11//
12//===----------------------------------------------------------------------===//
13
14#include "SIISelLowering.h"
15#include "AMDGPU.h"
16#include "AMDGPUInstrInfo.h"
17#include "AMDGPUTargetMachine.h"
18#include "SIMachineFunctionInfo.h"
19#include "SIRegisterInfo.h"
20#include "llvm/ADT/Statistic.h"
21#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
22#include "llvm/Analysis/OptimizationRemarkEmitter.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/CodeGen/Analysis.h"
25#include "llvm/CodeGen/FunctionLoweringInfo.h"
26#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineLoopInfo.h"
29#include "llvm/IR/DiagnosticInfo.h"
30#include "llvm/IR/IntrinsicInst.h"
31#include "llvm/IR/IntrinsicsAMDGPU.h"
32#include "llvm/IR/IntrinsicsR600.h"
33#include "llvm/Support/CommandLine.h"
34#include "llvm/Support/KnownBits.h"
35
36using namespace llvm;
37
38#define DEBUG_TYPE"si-lower" "si-lower"
39
40STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"si-lower", "NumTailCalls"
, "Number of tail calls"}
;
41
42static cl::opt<bool> DisableLoopAlignment(
43 "amdgpu-disable-loop-alignment",
44 cl::desc("Do not align and prefetch loops"),
45 cl::init(false));
46
47static cl::opt<bool> VGPRReserveforSGPRSpill(
48 "amdgpu-reserve-vgpr-for-sgpr-spill",
49 cl::desc("Allocates one VGPR for future SGPR Spill"), cl::init(true));
50
51static cl::opt<bool> UseDivergentRegisterIndexing(
52 "amdgpu-use-divergent-register-indexing",
53 cl::Hidden,
54 cl::desc("Use indirect register addressing for divergent indexes"),
55 cl::init(false));
56
57static bool hasFP32Denormals(const MachineFunction &MF) {
58 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
59 return Info->getMode().allFP32Denormals();
60}
61
62static bool hasFP64FP16Denormals(const MachineFunction &MF) {
63 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
64 return Info->getMode().allFP64FP16Denormals();
65}
66
67static unsigned findFirstFreeSGPR(CCState &CCInfo) {
68 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
69 for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
70 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
71 return AMDGPU::SGPR0 + Reg;
72 }
73 }
74 llvm_unreachable("Cannot allocate sgpr")::llvm::llvm_unreachable_internal("Cannot allocate sgpr", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 74)
;
75}
76
77SITargetLowering::SITargetLowering(const TargetMachine &TM,
78 const GCNSubtarget &STI)
79 : AMDGPUTargetLowering(TM, STI),
80 Subtarget(&STI) {
81 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
82 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
83
84 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
85 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
86
87 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
88
89 const SIRegisterInfo *TRI = STI.getRegisterInfo();
90 const TargetRegisterClass *V64RegClass = TRI->getVGPR64Class();
91
92 addRegisterClass(MVT::f64, V64RegClass);
93 addRegisterClass(MVT::v2f32, V64RegClass);
94
95 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
96 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));
97
98 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
99 addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
100
101 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
102 addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128));
103
104 addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
105 addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160));
106
107 addRegisterClass(MVT::v6i32, &AMDGPU::SGPR_192RegClass);
108 addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192));
109
110 addRegisterClass(MVT::v3i64, &AMDGPU::SGPR_192RegClass);
111 addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192));
112
113 addRegisterClass(MVT::v7i32, &AMDGPU::SGPR_224RegClass);
114 addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224));
115
116 addRegisterClass(MVT::v8i32, &AMDGPU::SGPR_256RegClass);
117 addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256));
118
119 addRegisterClass(MVT::v4i64, &AMDGPU::SGPR_256RegClass);
120 addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256));
121
122 addRegisterClass(MVT::v16i32, &AMDGPU::SGPR_512RegClass);
123 addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512));
124
125 addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);
126 addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));
127
128 addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);
129 addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));
130
131 if (Subtarget->has16BitInsts()) {
132 addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
133 addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
134
135 // Unless there are also VOP3P operations, not operations are really legal.
136 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
137 addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);
138 addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
139 addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
140 }
141
142 addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
143 addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024));
144
145 computeRegisterProperties(Subtarget->getRegisterInfo());
146
147 // The boolean content concept here is too inflexible. Compares only ever
148 // really produce a 1-bit result. Any copy/extend from these will turn into a
149 // select, and zext/1 or sext/-1 are equally cheap. Arbitrarily choose 0/1, as
150 // it's what most targets use.
151 setBooleanContents(ZeroOrOneBooleanContent);
152 setBooleanVectorContents(ZeroOrOneBooleanContent);
153
154 // We need to custom lower vector stores from local memory
155 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
156 setOperationAction(ISD::LOAD, MVT::v3i32, Custom);
157 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
158 setOperationAction(ISD::LOAD, MVT::v5i32, Custom);
159 setOperationAction(ISD::LOAD, MVT::v6i32, Custom);
160 setOperationAction(ISD::LOAD, MVT::v7i32, Custom);
161 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
162 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
163 setOperationAction(ISD::LOAD, MVT::i1, Custom);
164 setOperationAction(ISD::LOAD, MVT::v32i32, Custom);
165
166 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
167 setOperationAction(ISD::STORE, MVT::v3i32, Custom);
168 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
169 setOperationAction(ISD::STORE, MVT::v5i32, Custom);
170 setOperationAction(ISD::STORE, MVT::v6i32, Custom);
171 setOperationAction(ISD::STORE, MVT::v7i32, Custom);
172 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
173 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
174 setOperationAction(ISD::STORE, MVT::i1, Custom);
175 setOperationAction(ISD::STORE, MVT::v32i32, Custom);
176
177 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
178 setTruncStoreAction(MVT::v3i32, MVT::v3i16, Expand);
179 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
180 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
181 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
182 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand);
183 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Expand);
184 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
185 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Expand);
186 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
187 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Expand);
188 setTruncStoreAction(MVT::v2i16, MVT::v2i8, Expand);
189 setTruncStoreAction(MVT::v4i16, MVT::v4i8, Expand);
190 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
191 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Expand);
192 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Expand);
193
194 setTruncStoreAction(MVT::v3i64, MVT::v3i16, Expand);
195 setTruncStoreAction(MVT::v3i64, MVT::v3i32, Expand);
196 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Expand);
197 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Expand);
198 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Expand);
199 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Expand);
200 setTruncStoreAction(MVT::v16i64, MVT::v16i32, Expand);
201
202 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
203 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
204
205 setOperationAction(ISD::SELECT, MVT::i1, Promote);
206 setOperationAction(ISD::SELECT, MVT::i64, Custom);
207 setOperationAction(ISD::SELECT, MVT::f64, Promote);
208 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
209
210 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
211 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
212 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
213 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
214 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
215
216 setOperationAction(ISD::SETCC, MVT::i1, Promote);
217 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
218 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
219 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
220
221 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
222 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
223 setOperationAction(ISD::TRUNCATE, MVT::v3i32, Expand);
224 setOperationAction(ISD::FP_ROUND, MVT::v3f32, Expand);
225 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Expand);
226 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Expand);
227 setOperationAction(ISD::TRUNCATE, MVT::v5i32, Expand);
228 setOperationAction(ISD::FP_ROUND, MVT::v5f32, Expand);
229 setOperationAction(ISD::TRUNCATE, MVT::v6i32, Expand);
230 setOperationAction(ISD::FP_ROUND, MVT::v6f32, Expand);
231 setOperationAction(ISD::TRUNCATE, MVT::v7i32, Expand);
232 setOperationAction(ISD::FP_ROUND, MVT::v7f32, Expand);
233 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Expand);
234 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Expand);
235 setOperationAction(ISD::TRUNCATE, MVT::v16i32, Expand);
236 setOperationAction(ISD::FP_ROUND, MVT::v16f32, Expand);
237
238 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
239 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
240 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
241 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
242 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
243 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v3i16, Custom);
244 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
245 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
246
247 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
248 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
249 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
250 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
251 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
252 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
253
254 setOperationAction(ISD::UADDO, MVT::i32, Legal);
255 setOperationAction(ISD::USUBO, MVT::i32, Legal);
256
257 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
258 setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
259
260 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
261 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
262 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
263
264#if 0
265 setOperationAction(ISD::ADDCARRY, MVT::i64, Legal);
266 setOperationAction(ISD::SUBCARRY, MVT::i64, Legal);
267#endif
268
269 // We only support LOAD/STORE and vector manipulation ops for vectors
270 // with > 4 elements.
271 for (MVT VT : { MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32,
272 MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16,
273 MVT::v3i64, MVT::v3f64, MVT::v6i32, MVT::v6f32,
274 MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64,
275 MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32 }) {
276 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
277 switch (Op) {
278 case ISD::LOAD:
279 case ISD::STORE:
280 case ISD::BUILD_VECTOR:
281 case ISD::BITCAST:
282 case ISD::EXTRACT_VECTOR_ELT:
283 case ISD::INSERT_VECTOR_ELT:
284 case ISD::EXTRACT_SUBVECTOR:
285 case ISD::SCALAR_TO_VECTOR:
286 break;
287 case ISD::INSERT_SUBVECTOR:
288 case ISD::CONCAT_VECTORS:
289 setOperationAction(Op, VT, Custom);
290 break;
291 default:
292 setOperationAction(Op, VT, Expand);
293 break;
294 }
295 }
296 }
297
298 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand);
299
300 // TODO: For dynamic 64-bit vector inserts/extracts, should emit a pseudo that
301 // is expanded to avoid having two separate loops in case the index is a VGPR.
302
303 // Most operations are naturally 32-bit vector operations. We only support
304 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
305 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
306 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
307 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
308
309 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
310 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
311
312 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
313 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
314
315 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
316 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
317 }
318
319 for (MVT Vec64 : { MVT::v3i64, MVT::v3f64 }) {
320 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
321 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v6i32);
322
323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
324 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v6i32);
325
326 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
327 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v6i32);
328
329 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
330 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v6i32);
331 }
332
333 for (MVT Vec64 : { MVT::v4i64, MVT::v4f64 }) {
334 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
335 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v8i32);
336
337 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
338 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v8i32);
339
340 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
341 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v8i32);
342
343 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
344 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v8i32);
345 }
346
347 for (MVT Vec64 : { MVT::v8i64, MVT::v8f64 }) {
348 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
349 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v16i32);
350
351 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
352 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v16i32);
353
354 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
355 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v16i32);
356
357 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
358 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v16i32);
359 }
360
361 for (MVT Vec64 : { MVT::v16i64, MVT::v16f64 }) {
362 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
363 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v32i32);
364
365 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
366 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v32i32);
367
368 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
369 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v32i32);
370
371 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
372 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v32i32);
373 }
374
375 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
376 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
377 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
378 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
379
380 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f16, Custom);
381 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
382
383 // Avoid stack access for these.
384 // TODO: Generalize to more vector types.
385 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
386 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
387 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);
388 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);
389
390 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom);
391 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom);
392 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom);
393 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
394 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
395 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
396
397 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom);
398 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f16, Custom);
399 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
400 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
401
402 // Deal with vec3 vector operations when widened to vec4.
403 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom);
404 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom);
405 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom);
406 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom);
407
408 // Deal with vec5/6/7 vector operations when widened to vec8.
409 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom);
410 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom);
411 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v6i32, Custom);
412 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v6f32, Custom);
413 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v7i32, Custom);
414 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v7f32, Custom);
415 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom);
416 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom);
417
418 // BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
419 // and output demarshalling
420 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
421 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
422
423 // We can't return success/failure, only the old value,
424 // let LLVM add the comparison
425 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
426 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Expand);
427
428 if (Subtarget->hasFlatAddressSpace()) {
429 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
430 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
431 }
432
433 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
434 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
435
436 // FIXME: This should be narrowed to i32, but that only happens if i64 is
437 // illegal.
438 // FIXME: Should lower sub-i32 bswaps to bit-ops without v_perm_b32.
439 setOperationAction(ISD::BSWAP, MVT::i64, Legal);
440 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
441
442 // On SI this is s_memtime and s_memrealtime on VI.
443 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
444 setOperationAction(ISD::TRAP, MVT::Other, Custom);
445 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Custom);
446
447 if (Subtarget->has16BitInsts()) {
448 setOperationAction(ISD::FPOW, MVT::f16, Promote);
449 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
450 setOperationAction(ISD::FLOG, MVT::f16, Custom);
451 setOperationAction(ISD::FEXP, MVT::f16, Custom);
452 setOperationAction(ISD::FLOG10, MVT::f16, Custom);
453 }
454
455 if (Subtarget->hasMadMacF32Insts())
456 setOperationAction(ISD::FMAD, MVT::f32, Legal);
457
458 if (!Subtarget->hasBFI()) {
459 // fcopysign can be done in a single instruction with BFI.
460 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
461 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
462 }
463
464 if (!Subtarget->hasBCNT(32))
465 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
466
467 if (!Subtarget->hasBCNT(64))
468 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
469
470 if (Subtarget->hasFFBH()) {
471 setOperationAction(ISD::CTLZ, MVT::i32, Custom);
472 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
473 }
474
475 if (Subtarget->hasFFBL()) {
476 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
478 }
479
480 // We only really have 32-bit BFE instructions (and 16-bit on VI).
481 //
482 // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
483 // effort to match them now. We want this to be false for i64 cases when the
484 // extraction isn't restricted to the upper or lower half. Ideally we would
485 // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
486 // span the midpoint are probably relatively rare, so don't worry about them
487 // for now.
488 if (Subtarget->hasBFE())
489 setHasExtractBitsInsn(true);
490
491 // Clamp modifier on add/sub
492 if (Subtarget->hasIntClamp()) {
493 setOperationAction(ISD::UADDSAT, MVT::i32, Legal);
494 setOperationAction(ISD::USUBSAT, MVT::i32, Legal);
495 }
496
497 if (Subtarget->hasAddNoCarry()) {
498 setOperationAction(ISD::SADDSAT, MVT::i16, Legal);
499 setOperationAction(ISD::SSUBSAT, MVT::i16, Legal);
500 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
501 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
502 }
503
504 setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
505 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom);
506 setOperationAction(ISD::FMINNUM, MVT::f64, Custom);
507 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom);
508
509
510 // These are really only legal for ieee_mode functions. We should be avoiding
511 // them for functions that don't have ieee_mode enabled, so just say they are
512 // legal.
513 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
514 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
515 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
516 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
517
518
519 if (Subtarget->haveRoundOpsF64()) {
520 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
521 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
522 setOperationAction(ISD::FRINT, MVT::f64, Legal);
523 } else {
524 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
525 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
526 setOperationAction(ISD::FRINT, MVT::f64, Custom);
527 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
528 }
529
530 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
531
532 setOperationAction(ISD::FSIN, MVT::f32, Custom);
533 setOperationAction(ISD::FCOS, MVT::f32, Custom);
534 setOperationAction(ISD::FDIV, MVT::f32, Custom);
535 setOperationAction(ISD::FDIV, MVT::f64, Custom);
536
537 if (Subtarget->has16BitInsts()) {
538 setOperationAction(ISD::Constant, MVT::i16, Legal);
539
540 setOperationAction(ISD::SMIN, MVT::i16, Legal);
541 setOperationAction(ISD::SMAX, MVT::i16, Legal);
542
543 setOperationAction(ISD::UMIN, MVT::i16, Legal);
544 setOperationAction(ISD::UMAX, MVT::i16, Legal);
545
546 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
547 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
548
549 setOperationAction(ISD::ROTR, MVT::i16, Expand);
550 setOperationAction(ISD::ROTL, MVT::i16, Expand);
551
552 setOperationAction(ISD::SDIV, MVT::i16, Promote);
553 setOperationAction(ISD::UDIV, MVT::i16, Promote);
554 setOperationAction(ISD::SREM, MVT::i16, Promote);
555 setOperationAction(ISD::UREM, MVT::i16, Promote);
556 setOperationAction(ISD::UADDSAT, MVT::i16, Legal);
557 setOperationAction(ISD::USUBSAT, MVT::i16, Legal);
558
559 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
560
561 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
562 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
563 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
564 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
565 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
566
567 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
568
569 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
570
571 setOperationAction(ISD::LOAD, MVT::i16, Custom);
572
573 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
574
575 setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote);
576 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
577 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
578 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
579
580 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom);
581 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Custom);
582
583 // F16 - Constant Actions.
584 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
585
586 // F16 - Load/Store Actions.
587 setOperationAction(ISD::LOAD, MVT::f16, Promote);
588 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
589 setOperationAction(ISD::STORE, MVT::f16, Promote);
590 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
591
592 // F16 - VOP1 Actions.
593 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
594 setOperationAction(ISD::FCOS, MVT::f16, Custom);
595 setOperationAction(ISD::FSIN, MVT::f16, Custom);
596
597 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
598 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Custom);
599
600 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
601 setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
602 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
603 setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
604 setOperationAction(ISD::FROUND, MVT::f16, Custom);
605
606 // F16 - VOP2 Actions.
607 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
608 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
609
610 setOperationAction(ISD::FDIV, MVT::f16, Custom);
611
612 // F16 - VOP3 Actions.
613 setOperationAction(ISD::FMA, MVT::f16, Legal);
614 if (STI.hasMadF16())
615 setOperationAction(ISD::FMAD, MVT::f16, Legal);
616
617 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) {
618 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
619 switch (Op) {
620 case ISD::LOAD:
621 case ISD::STORE:
622 case ISD::BUILD_VECTOR:
623 case ISD::BITCAST:
624 case ISD::EXTRACT_VECTOR_ELT:
625 case ISD::INSERT_VECTOR_ELT:
626 case ISD::INSERT_SUBVECTOR:
627 case ISD::EXTRACT_SUBVECTOR:
628 case ISD::SCALAR_TO_VECTOR:
629 break;
630 case ISD::CONCAT_VECTORS:
631 setOperationAction(Op, VT, Custom);
632 break;
633 default:
634 setOperationAction(Op, VT, Expand);
635 break;
636 }
637 }
638 }
639
640 // v_perm_b32 can handle either of these.
641 setOperationAction(ISD::BSWAP, MVT::i16, Legal);
642 setOperationAction(ISD::BSWAP, MVT::v2i16, Legal);
643 setOperationAction(ISD::BSWAP, MVT::v4i16, Custom);
644
645 // XXX - Do these do anything? Vector constants turn into build_vector.
646 setOperationAction(ISD::Constant, MVT::v2i16, Legal);
647 setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal);
648
649 setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);
650 setOperationAction(ISD::UNDEF, MVT::v2f16, Legal);
651
652 setOperationAction(ISD::STORE, MVT::v2i16, Promote);
653 AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
654 setOperationAction(ISD::STORE, MVT::v2f16, Promote);
655 AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32);
656
657 setOperationAction(ISD::LOAD, MVT::v2i16, Promote);
658 AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32);
659 setOperationAction(ISD::LOAD, MVT::v2f16, Promote);
660 AddPromotedToType(ISD::LOAD, MVT::v2f16, MVT::i32);
661
662 setOperationAction(ISD::AND, MVT::v2i16, Promote);
663 AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);
664 setOperationAction(ISD::OR, MVT::v2i16, Promote);
665 AddPromotedToType(ISD::OR, MVT::v2i16, MVT::i32);
666 setOperationAction(ISD::XOR, MVT::v2i16, Promote);
667 AddPromotedToType(ISD::XOR, MVT::v2i16, MVT::i32);
668
669 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
670 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::v2i32);
671 setOperationAction(ISD::LOAD, MVT::v4f16, Promote);
672 AddPromotedToType(ISD::LOAD, MVT::v4f16, MVT::v2i32);
673
674 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
675 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
676 setOperationAction(ISD::STORE, MVT::v4f16, Promote);
677 AddPromotedToType(ISD::STORE, MVT::v4f16, MVT::v2i32);
678
679 setOperationAction(ISD::ANY_EXTEND, MVT::v2i32, Expand);
680 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i32, Expand);
681 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i32, Expand);
682 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand);
683
684 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Expand);
685 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand);
686 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Expand);
687
688 if (!Subtarget->hasVOP3PInsts()) {
689 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
690 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
691 }
692
693 setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
694 // This isn't really legal, but this avoids the legalizer unrolling it (and
695 // allows matching fneg (fabs x) patterns)
696 setOperationAction(ISD::FABS, MVT::v2f16, Legal);
697
698 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom);
699 setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
700 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal);
701 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal);
702
703 setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom);
704 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v4f16, Custom);
705
706 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand);
707 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand);
708 }
709
710 if (Subtarget->hasVOP3PInsts()) {
711 setOperationAction(ISD::ADD, MVT::v2i16, Legal);
712 setOperationAction(ISD::SUB, MVT::v2i16, Legal);
713 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
714 setOperationAction(ISD::SHL, MVT::v2i16, Legal);
715 setOperationAction(ISD::SRL, MVT::v2i16, Legal);
716 setOperationAction(ISD::SRA, MVT::v2i16, Legal);
717 setOperationAction(ISD::SMIN, MVT::v2i16, Legal);
718 setOperationAction(ISD::UMIN, MVT::v2i16, Legal);
719 setOperationAction(ISD::SMAX, MVT::v2i16, Legal);
720 setOperationAction(ISD::UMAX, MVT::v2i16, Legal);
721
722 setOperationAction(ISD::UADDSAT, MVT::v2i16, Legal);
723 setOperationAction(ISD::USUBSAT, MVT::v2i16, Legal);
724 setOperationAction(ISD::SADDSAT, MVT::v2i16, Legal);
725 setOperationAction(ISD::SSUBSAT, MVT::v2i16, Legal);
726
727 setOperationAction(ISD::FADD, MVT::v2f16, Legal);
728 setOperationAction(ISD::FMUL, MVT::v2f16, Legal);
729 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
730
731 setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal);
732 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v2f16, Legal);
733
734 setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal);
735
736 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
737 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
738
739 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom);
740 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
741
742 setOperationAction(ISD::SHL, MVT::v4i16, Custom);
743 setOperationAction(ISD::SRA, MVT::v4i16, Custom);
744 setOperationAction(ISD::SRL, MVT::v4i16, Custom);
745 setOperationAction(ISD::ADD, MVT::v4i16, Custom);
746 setOperationAction(ISD::SUB, MVT::v4i16, Custom);
747 setOperationAction(ISD::MUL, MVT::v4i16, Custom);
748
749 setOperationAction(ISD::SMIN, MVT::v4i16, Custom);
750 setOperationAction(ISD::SMAX, MVT::v4i16, Custom);
751 setOperationAction(ISD::UMIN, MVT::v4i16, Custom);
752 setOperationAction(ISD::UMAX, MVT::v4i16, Custom);
753
754 setOperationAction(ISD::UADDSAT, MVT::v4i16, Custom);
755 setOperationAction(ISD::SADDSAT, MVT::v4i16, Custom);
756 setOperationAction(ISD::USUBSAT, MVT::v4i16, Custom);
757 setOperationAction(ISD::SSUBSAT, MVT::v4i16, Custom);
758
759 setOperationAction(ISD::FADD, MVT::v4f16, Custom);
760 setOperationAction(ISD::FMUL, MVT::v4f16, Custom);
761 setOperationAction(ISD::FMA, MVT::v4f16, Custom);
762
763 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom);
764 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom);
765
766 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
767 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom);
768 setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom);
769
770 setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
771 setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
772 setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
773
774 if (Subtarget->hasPackedFP32Ops()) {
775 setOperationAction(ISD::FADD, MVT::v2f32, Legal);
776 setOperationAction(ISD::FMUL, MVT::v2f32, Legal);
777 setOperationAction(ISD::FMA, MVT::v2f32, Legal);
778 setOperationAction(ISD::FNEG, MVT::v2f32, Legal);
779
780 for (MVT VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32, MVT::v32f32 }) {
781 setOperationAction(ISD::FADD, VT, Custom);
782 setOperationAction(ISD::FMUL, VT, Custom);
783 setOperationAction(ISD::FMA, VT, Custom);
784 }
785 }
786 }
787
788 setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f16, Custom);
790
791 if (Subtarget->has16BitInsts()) {
792 setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
793 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
794 setOperationAction(ISD::SELECT, MVT::v2f16, Promote);
795 AddPromotedToType(ISD::SELECT, MVT::v2f16, MVT::i32);
796 } else {
797 // Legalization hack.
798 setOperationAction(ISD::SELECT, MVT::v2i16, Custom);
799 setOperationAction(ISD::SELECT, MVT::v2f16, Custom);
800
801 setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
802 setOperationAction(ISD::FABS, MVT::v2f16, Custom);
803 }
804
805 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
806 setOperationAction(ISD::SELECT, VT, Custom);
807 }
808
809 setOperationAction(ISD::SMULO, MVT::i64, Custom);
810 setOperationAction(ISD::UMULO, MVT::i64, Custom);
811
812 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
813 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
814 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
815 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
816 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f16, Custom);
817 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i16, Custom);
818 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
819
820 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2f16, Custom);
821 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2i16, Custom);
822 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v3f16, Custom);
823 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v3i16, Custom);
824 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4f16, Custom);
825 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4i16, Custom);
826 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v8f16, Custom);
827 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
828 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::f16, Custom);
829 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom);
830 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
831
832 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
833 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
834 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
835 setOperationAction(ISD::INTRINSIC_VOID, MVT::v3i16, Custom);
836 setOperationAction(ISD::INTRINSIC_VOID, MVT::v3f16, Custom);
837 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
838 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4i16, Custom);
839 setOperationAction(ISD::INTRINSIC_VOID, MVT::f16, Custom);
840 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
841 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
842
843 setTargetDAGCombine(ISD::ADD);
844 setTargetDAGCombine(ISD::ADDCARRY);
845 setTargetDAGCombine(ISD::SUB);
846 setTargetDAGCombine(ISD::SUBCARRY);
847 setTargetDAGCombine(ISD::FADD);
848 setTargetDAGCombine(ISD::FSUB);
849 setTargetDAGCombine(ISD::FMINNUM);
850 setTargetDAGCombine(ISD::FMAXNUM);
851 setTargetDAGCombine(ISD::FMINNUM_IEEE);
852 setTargetDAGCombine(ISD::FMAXNUM_IEEE);
853 setTargetDAGCombine(ISD::FMA);
854 setTargetDAGCombine(ISD::SMIN);
855 setTargetDAGCombine(ISD::SMAX);
856 setTargetDAGCombine(ISD::UMIN);
857 setTargetDAGCombine(ISD::UMAX);
858 setTargetDAGCombine(ISD::SETCC);
859 setTargetDAGCombine(ISD::AND);
860 setTargetDAGCombine(ISD::OR);
861 setTargetDAGCombine(ISD::XOR);
862 setTargetDAGCombine(ISD::SINT_TO_FP);
863 setTargetDAGCombine(ISD::UINT_TO_FP);
864 setTargetDAGCombine(ISD::FCANONICALIZE);
865 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
866 setTargetDAGCombine(ISD::ZERO_EXTEND);
867 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
868 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
869 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
870
871 // All memory operations. Some folding on the pointer operand is done to help
872 // matching the constant offsets in the addressing modes.
873 setTargetDAGCombine(ISD::LOAD);
874 setTargetDAGCombine(ISD::STORE);
875 setTargetDAGCombine(ISD::ATOMIC_LOAD);
876 setTargetDAGCombine(ISD::ATOMIC_STORE);
877 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
878 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
879 setTargetDAGCombine(ISD::ATOMIC_SWAP);
880 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
881 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
882 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
883 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
884 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
885 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
886 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
887 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
888 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
889 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
890 setTargetDAGCombine(ISD::ATOMIC_LOAD_FADD);
891 setTargetDAGCombine(ISD::INTRINSIC_VOID);
892 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
893
894 // FIXME: In other contexts we pretend this is a per-function property.
895 setStackPointerRegisterToSaveRestore(AMDGPU::SGPR32);
896
897 setSchedulingPreference(Sched::RegPressure);
898}
899
900const GCNSubtarget *SITargetLowering::getSubtarget() const {
901 return Subtarget;
902}
903
904//===----------------------------------------------------------------------===//
905// TargetLowering queries
906//===----------------------------------------------------------------------===//
907
908// v_mad_mix* support a conversion from f16 to f32.
909//
910// There is only one special case when denormals are enabled we don't currently,
911// where this is OK to use.
912bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
913 EVT DestVT, EVT SrcVT) const {
914 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||
915 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
916 DestVT.getScalarType() == MVT::f32 &&
917 SrcVT.getScalarType() == MVT::f16 &&
918 // TODO: This probably only requires no input flushing?
919 !hasFP32Denormals(DAG.getMachineFunction());
920}
921
922bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
923 // SI has some legal vector types, but no legal vector operations. Say no
924 // shuffles are legal in order to prefer scalarizing some vector operations.
925 return false;
926}
927
928MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
929 CallingConv::ID CC,
930 EVT VT) const {
931 if (CC == CallingConv::AMDGPU_KERNEL)
932 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
933
934 if (VT.isVector()) {
935 EVT ScalarVT = VT.getScalarType();
936 unsigned Size = ScalarVT.getSizeInBits();
937 if (Size == 16) {
938 if (Subtarget->has16BitInsts())
939 return VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
940 return VT.isInteger() ? MVT::i32 : MVT::f32;
941 }
942
943 if (Size < 16)
944 return Subtarget->has16BitInsts() ? MVT::i16 : MVT::i32;
945 return Size == 32 ? ScalarVT.getSimpleVT() : MVT::i32;
946 }
947
948 if (VT.getSizeInBits() > 32)
949 return MVT::i32;
950
951 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
952}
953
954unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
955 CallingConv::ID CC,
956 EVT VT) const {
957 if (CC == CallingConv::AMDGPU_KERNEL)
958 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
959
960 if (VT.isVector()) {
961 unsigned NumElts = VT.getVectorNumElements();
962 EVT ScalarVT = VT.getScalarType();
963 unsigned Size = ScalarVT.getSizeInBits();
964
965 // FIXME: Should probably promote 8-bit vectors to i16.
966 if (Size == 16 && Subtarget->has16BitInsts())
967 return (NumElts + 1) / 2;
968
969 if (Size <= 32)
970 return NumElts;
971
972 if (Size > 32)
973 return NumElts * ((Size + 31) / 32);
974 } else if (VT.getSizeInBits() > 32)
975 return (VT.getSizeInBits() + 31) / 32;
976
977 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
978}
979
980unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
981 LLVMContext &Context, CallingConv::ID CC,
982 EVT VT, EVT &IntermediateVT,
983 unsigned &NumIntermediates, MVT &RegisterVT) const {
984 if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
985 unsigned NumElts = VT.getVectorNumElements();
986 EVT ScalarVT = VT.getScalarType();
987 unsigned Size = ScalarVT.getSizeInBits();
988 // FIXME: We should fix the ABI to be the same on targets without 16-bit
989 // support, but unless we can properly handle 3-vectors, it will be still be
990 // inconsistent.
991 if (Size == 16 && Subtarget->has16BitInsts()) {
992 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
993 IntermediateVT = RegisterVT;
994 NumIntermediates = (NumElts + 1) / 2;
995 return NumIntermediates;
996 }
997
998 if (Size == 32) {
999 RegisterVT = ScalarVT.getSimpleVT();
1000 IntermediateVT = RegisterVT;
1001 NumIntermediates = NumElts;
1002 return NumIntermediates;
1003 }
1004
1005 if (Size < 16 && Subtarget->has16BitInsts()) {
1006 // FIXME: Should probably form v2i16 pieces
1007 RegisterVT = MVT::i16;
1008 IntermediateVT = ScalarVT;
1009 NumIntermediates = NumElts;
1010 return NumIntermediates;
1011 }
1012
1013
1014 if (Size != 16 && Size <= 32) {
1015 RegisterVT = MVT::i32;
1016 IntermediateVT = ScalarVT;
1017 NumIntermediates = NumElts;
1018 return NumIntermediates;
1019 }
1020
1021 if (Size > 32) {
1022 RegisterVT = MVT::i32;
1023 IntermediateVT = RegisterVT;
1024 NumIntermediates = NumElts * ((Size + 31) / 32);
1025 return NumIntermediates;
1026 }
1027 }
1028
1029 return TargetLowering::getVectorTypeBreakdownForCallingConv(
1030 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
1031}
1032
1033static EVT memVTFromImageData(Type *Ty, unsigned DMaskLanes) {
1034 assert(DMaskLanes != 0)(static_cast <bool> (DMaskLanes != 0) ? void (0) : __assert_fail
("DMaskLanes != 0", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1034, __extension__ __PRETTY_FUNCTION__))
;
1035
1036 if (auto *VT = dyn_cast<FixedVectorType>(Ty)) {
1037 unsigned NumElts = std::min(DMaskLanes, VT->getNumElements());
1038 return EVT::getVectorVT(Ty->getContext(),
1039 EVT::getEVT(VT->getElementType()),
1040 NumElts);
1041 }
1042
1043 return EVT::getEVT(Ty);
1044}
1045
1046// Peek through TFE struct returns to only use the data size.
1047static EVT memVTFromImageReturn(Type *Ty, unsigned DMaskLanes) {
1048 auto *ST = dyn_cast<StructType>(Ty);
1049 if (!ST)
1050 return memVTFromImageData(Ty, DMaskLanes);
1051
1052 // Some intrinsics return an aggregate type - special case to work out the
1053 // correct memVT.
1054 //
1055 // Only limited forms of aggregate type currently expected.
1056 if (ST->getNumContainedTypes() != 2 ||
1057 !ST->getContainedType(1)->isIntegerTy(32))
1058 return EVT();
1059 return memVTFromImageData(ST->getContainedType(0), DMaskLanes);
1060}
1061
1062bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1063 const CallInst &CI,
1064 MachineFunction &MF,
1065 unsigned IntrID) const {
1066 if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
1067 AMDGPU::lookupRsrcIntrinsic(IntrID)) {
1068 AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
1069 (Intrinsic::ID)IntrID);
1070 if (Attr.hasFnAttr(Attribute::ReadNone))
1071 return false;
1072
1073 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1074
1075 if (RsrcIntr->IsImage) {
1076 Info.ptrVal =
1077 MFI->getImagePSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1078 Info.align.reset();
1079 } else {
1080 Info.ptrVal =
1081 MFI->getBufferPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1082 }
1083
1084 Info.flags = MachineMemOperand::MODereferenceable;
1085 if (Attr.hasFnAttr(Attribute::ReadOnly)) {
1086 unsigned DMaskLanes = 4;
1087
1088 if (RsrcIntr->IsImage) {
1089 const AMDGPU::ImageDimIntrinsicInfo *Intr
1090 = AMDGPU::getImageDimIntrinsicInfo(IntrID);
1091 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
1092 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
1093
1094 if (!BaseOpcode->Gather4) {
1095 // If this isn't a gather, we may have excess loaded elements in the
1096 // IR type. Check the dmask for the real number of elements loaded.
1097 unsigned DMask
1098 = cast<ConstantInt>(CI.getArgOperand(0))->getZExtValue();
1099 DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask);
1100 }
1101
1102 Info.memVT = memVTFromImageReturn(CI.getType(), DMaskLanes);
1103 } else
1104 Info.memVT = EVT::getEVT(CI.getType());
1105
1106 // FIXME: What does alignment mean for an image?
1107 Info.opc = ISD::INTRINSIC_W_CHAIN;
1108 Info.flags |= MachineMemOperand::MOLoad;
1109 } else if (Attr.hasFnAttr(Attribute::WriteOnly)) {
1110 Info.opc = ISD::INTRINSIC_VOID;
1111
1112 Type *DataTy = CI.getArgOperand(0)->getType();
1113 if (RsrcIntr->IsImage) {
1114 unsigned DMask = cast<ConstantInt>(CI.getArgOperand(1))->getZExtValue();
1115 unsigned DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask);
1116 Info.memVT = memVTFromImageData(DataTy, DMaskLanes);
1117 } else
1118 Info.memVT = EVT::getEVT(DataTy);
1119
1120 Info.flags |= MachineMemOperand::MOStore;
1121 } else {
1122 // Atomic
1123 Info.opc = CI.getType()->isVoidTy() ? ISD::INTRINSIC_VOID :
1124 ISD::INTRINSIC_W_CHAIN;
1125 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
1126 Info.flags = MachineMemOperand::MOLoad |
1127 MachineMemOperand::MOStore |
1128 MachineMemOperand::MODereferenceable;
1129
1130 // XXX - Should this be volatile without known ordering?
1131 Info.flags |= MachineMemOperand::MOVolatile;
1132 }
1133 return true;
1134 }
1135
1136 switch (IntrID) {
1137 case Intrinsic::amdgcn_atomic_inc:
1138 case Intrinsic::amdgcn_atomic_dec:
1139 case Intrinsic::amdgcn_ds_ordered_add:
1140 case Intrinsic::amdgcn_ds_ordered_swap:
1141 case Intrinsic::amdgcn_ds_fadd:
1142 case Intrinsic::amdgcn_ds_fmin:
1143 case Intrinsic::amdgcn_ds_fmax: {
1144 Info.opc = ISD::INTRINSIC_W_CHAIN;
1145 Info.memVT = MVT::getVT(CI.getType());
1146 Info.ptrVal = CI.getOperand(0);
1147 Info.align.reset();
1148 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1149
1150 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(4));
1151 if (!Vol->isZero())
1152 Info.flags |= MachineMemOperand::MOVolatile;
1153
1154 return true;
1155 }
1156 case Intrinsic::amdgcn_buffer_atomic_fadd: {
1157 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1158
1159 Info.opc = ISD::INTRINSIC_W_CHAIN;
1160 Info.memVT = MVT::getVT(CI.getOperand(0)->getType());
1161 Info.ptrVal =
1162 MFI->getBufferPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1163 Info.align.reset();
1164 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1165
1166 const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
1167 if (!Vol || !Vol->isZero())
1168 Info.flags |= MachineMemOperand::MOVolatile;
1169
1170 return true;
1171 }
1172 case Intrinsic::amdgcn_ds_append:
1173 case Intrinsic::amdgcn_ds_consume: {
1174 Info.opc = ISD::INTRINSIC_W_CHAIN;
1175 Info.memVT = MVT::getVT(CI.getType());
1176 Info.ptrVal = CI.getOperand(0);
1177 Info.align.reset();
1178 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1179
1180 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(1));
1181 if (!Vol->isZero())
1182 Info.flags |= MachineMemOperand::MOVolatile;
1183
1184 return true;
1185 }
1186 case Intrinsic::amdgcn_global_atomic_csub: {
1187 Info.opc = ISD::INTRINSIC_W_CHAIN;
1188 Info.memVT = MVT::getVT(CI.getType());
1189 Info.ptrVal = CI.getOperand(0);
1190 Info.align.reset();
1191 Info.flags = MachineMemOperand::MOLoad |
1192 MachineMemOperand::MOStore |
1193 MachineMemOperand::MOVolatile;
1194 return true;
1195 }
1196 case Intrinsic::amdgcn_image_bvh_intersect_ray: {
1197 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1198 Info.opc = ISD::INTRINSIC_W_CHAIN;
1199 Info.memVT = MVT::getVT(CI.getType()); // XXX: what is correct VT?
1200 Info.ptrVal =
1201 MFI->getImagePSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1202 Info.align.reset();
1203 Info.flags = MachineMemOperand::MOLoad |
1204 MachineMemOperand::MODereferenceable;
1205 return true;
1206 }
1207 case Intrinsic::amdgcn_global_atomic_fadd:
1208 case Intrinsic::amdgcn_global_atomic_fmin:
1209 case Intrinsic::amdgcn_global_atomic_fmax:
1210 case Intrinsic::amdgcn_flat_atomic_fadd:
1211 case Intrinsic::amdgcn_flat_atomic_fmin:
1212 case Intrinsic::amdgcn_flat_atomic_fmax: {
1213 Info.opc = ISD::INTRINSIC_W_CHAIN;
1214 Info.memVT = MVT::getVT(CI.getType());
1215 Info.ptrVal = CI.getOperand(0);
1216 Info.align.reset();
1217 Info.flags = MachineMemOperand::MOLoad |
1218 MachineMemOperand::MOStore |
1219 MachineMemOperand::MODereferenceable |
1220 MachineMemOperand::MOVolatile;
1221 return true;
1222 }
1223 case Intrinsic::amdgcn_ds_gws_init:
1224 case Intrinsic::amdgcn_ds_gws_barrier:
1225 case Intrinsic::amdgcn_ds_gws_sema_v:
1226 case Intrinsic::amdgcn_ds_gws_sema_br:
1227 case Intrinsic::amdgcn_ds_gws_sema_p:
1228 case Intrinsic::amdgcn_ds_gws_sema_release_all: {
1229 Info.opc = ISD::INTRINSIC_VOID;
1230
1231 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1232 Info.ptrVal =
1233 MFI->getGWSPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1234
1235 // This is an abstract access, but we need to specify a type and size.
1236 Info.memVT = MVT::i32;
1237 Info.size = 4;
1238 Info.align = Align(4);
1239
1240 Info.flags = MachineMemOperand::MOStore;
1241 if (IntrID == Intrinsic::amdgcn_ds_gws_barrier)
1242 Info.flags = MachineMemOperand::MOLoad;
1243 return true;
1244 }
1245 default:
1246 return false;
1247 }
1248}
1249
1250bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
1251 SmallVectorImpl<Value*> &Ops,
1252 Type *&AccessTy) const {
1253 switch (II->getIntrinsicID()) {
1254 case Intrinsic::amdgcn_atomic_inc:
1255 case Intrinsic::amdgcn_atomic_dec:
1256 case Intrinsic::amdgcn_ds_ordered_add:
1257 case Intrinsic::amdgcn_ds_ordered_swap:
1258 case Intrinsic::amdgcn_ds_append:
1259 case Intrinsic::amdgcn_ds_consume:
1260 case Intrinsic::amdgcn_ds_fadd:
1261 case Intrinsic::amdgcn_ds_fmin:
1262 case Intrinsic::amdgcn_ds_fmax:
1263 case Intrinsic::amdgcn_global_atomic_fadd:
1264 case Intrinsic::amdgcn_flat_atomic_fadd:
1265 case Intrinsic::amdgcn_flat_atomic_fmin:
1266 case Intrinsic::amdgcn_flat_atomic_fmax:
1267 case Intrinsic::amdgcn_global_atomic_csub: {
1268 Value *Ptr = II->getArgOperand(0);
1269 AccessTy = II->getType();
1270 Ops.push_back(Ptr);
1271 return true;
1272 }
1273 default:
1274 return false;
1275 }
1276}
1277
1278bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
1279 if (!Subtarget->hasFlatInstOffsets()) {
1280 // Flat instructions do not have offsets, and only have the register
1281 // address.
1282 return AM.BaseOffs == 0 && AM.Scale == 0;
1283 }
1284
1285 return AM.Scale == 0 &&
1286 (AM.BaseOffs == 0 ||
1287 Subtarget->getInstrInfo()->isLegalFLATOffset(
1288 AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS, SIInstrFlags::FLAT));
1289}
1290
1291bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const {
1292 if (Subtarget->hasFlatGlobalInsts())
1293 return AM.Scale == 0 &&
1294 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset(
1295 AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS,
1296 SIInstrFlags::FlatGlobal));
1297
1298 if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) {
1299 // Assume the we will use FLAT for all global memory accesses
1300 // on VI.
1301 // FIXME: This assumption is currently wrong. On VI we still use
1302 // MUBUF instructions for the r + i addressing mode. As currently
1303 // implemented, the MUBUF instructions only work on buffer < 4GB.
1304 // It may be possible to support > 4GB buffers with MUBUF instructions,
1305 // by setting the stride value in the resource descriptor which would
1306 // increase the size limit to (stride * 4GB). However, this is risky,
1307 // because it has never been validated.
1308 return isLegalFlatAddressingMode(AM);
1309 }
1310
1311 return isLegalMUBUFAddressingMode(AM);
1312}
1313
1314bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
1315 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
1316 // additionally can do r + r + i with addr64. 32-bit has more addressing
1317 // mode options. Depending on the resource constant, it can also do
1318 // (i64 r0) + (i32 r1) * (i14 i).
1319 //
1320 // Private arrays end up using a scratch buffer most of the time, so also
1321 // assume those use MUBUF instructions. Scratch loads / stores are currently
1322 // implemented as mubuf instructions with offen bit set, so slightly
1323 // different than the normal addr64.
1324 if (!SIInstrInfo::isLegalMUBUFImmOffset(AM.BaseOffs))
1325 return false;
1326
1327 // FIXME: Since we can split immediate into soffset and immediate offset,
1328 // would it make sense to allow any immediate?
1329
1330 switch (AM.Scale) {
1331 case 0: // r + i or just i, depending on HasBaseReg.
1332 return true;
1333 case 1:
1334 return true; // We have r + r or r + i.
1335 case 2:
1336 if (AM.HasBaseReg) {
1337 // Reject 2 * r + r.
1338 return false;
1339 }
1340
1341 // Allow 2 * r as r + r
1342 // Or 2 * r + i is allowed as r + r + i.
1343 return true;
1344 default: // Don't allow n * r
1345 return false;
1346 }
1347}
1348
1349bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
1350 const AddrMode &AM, Type *Ty,
1351 unsigned AS, Instruction *I) const {
1352 // No global is ever allowed as a base.
1353 if (AM.BaseGV)
1354 return false;
1355
1356 if (AS == AMDGPUAS::GLOBAL_ADDRESS)
1357 return isLegalGlobalAddressingMode(AM);
1358
1359 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
1360 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
1361 AS == AMDGPUAS::BUFFER_FAT_POINTER) {
1362 // If the offset isn't a multiple of 4, it probably isn't going to be
1363 // correctly aligned.
1364 // FIXME: Can we get the real alignment here?
1365 if (AM.BaseOffs % 4 != 0)
1366 return isLegalMUBUFAddressingMode(AM);
1367
1368 // There are no SMRD extloads, so if we have to do a small type access we
1369 // will use a MUBUF load.
1370 // FIXME?: We also need to do this if unaligned, but we don't know the
1371 // alignment here.
1372 if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4)
1373 return isLegalGlobalAddressingMode(AM);
1374
1375 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1376 // SMRD instructions have an 8-bit, dword offset on SI.
1377 if (!isUInt<8>(AM.BaseOffs / 4))
1378 return false;
1379 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
1380 // On CI+, this can also be a 32-bit literal constant offset. If it fits
1381 // in 8-bits, it can use a smaller encoding.
1382 if (!isUInt<32>(AM.BaseOffs / 4))
1383 return false;
1384 } else if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
1385 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
1386 if (!isUInt<20>(AM.BaseOffs))
1387 return false;
1388 } else
1389 llvm_unreachable("unhandled generation")::llvm::llvm_unreachable_internal("unhandled generation", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1389)
;
1390
1391 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1392 return true;
1393
1394 if (AM.Scale == 1 && AM.HasBaseReg)
1395 return true;
1396
1397 return false;
1398
1399 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1400 return isLegalMUBUFAddressingMode(AM);
1401 } else if (AS == AMDGPUAS::LOCAL_ADDRESS ||
1402 AS == AMDGPUAS::REGION_ADDRESS) {
1403 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
1404 // field.
1405 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
1406 // an 8-bit dword offset but we don't know the alignment here.
1407 if (!isUInt<16>(AM.BaseOffs))
1408 return false;
1409
1410 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1411 return true;
1412
1413 if (AM.Scale == 1 && AM.HasBaseReg)
1414 return true;
1415
1416 return false;
1417 } else if (AS == AMDGPUAS::FLAT_ADDRESS ||
1418 AS == AMDGPUAS::UNKNOWN_ADDRESS_SPACE) {
1419 // For an unknown address space, this usually means that this is for some
1420 // reason being used for pure arithmetic, and not based on some addressing
1421 // computation. We don't have instructions that compute pointers with any
1422 // addressing modes, so treat them as having no offset like flat
1423 // instructions.
1424 return isLegalFlatAddressingMode(AM);
1425 }
1426
1427 // Assume a user alias of global for unknown address spaces.
1428 return isLegalGlobalAddressingMode(AM);
1429}
1430
1431bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1432 const MachineFunction &MF) const {
1433 if (AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS) {
1434 return (MemVT.getSizeInBits() <= 4 * 32);
1435 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1436 unsigned MaxPrivateBits = 8 * getSubtarget()->getMaxPrivateElementSize();
1437 return (MemVT.getSizeInBits() <= MaxPrivateBits);
1438 } else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
1439 return (MemVT.getSizeInBits() <= 2 * 32);
1440 }
1441 return true;
1442}
1443
1444bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
1445 unsigned Size, unsigned AddrSpace, Align Alignment,
1446 MachineMemOperand::Flags Flags, bool *IsFast) const {
1447 if (IsFast)
1448 *IsFast = false;
1449
1450 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1451 AddrSpace == AMDGPUAS::REGION_ADDRESS) {
1452 // Check if alignment requirements for ds_read/write instructions are
1453 // disabled.
1454 if (Subtarget->hasUnalignedDSAccessEnabled() &&
1455 !Subtarget->hasLDSMisalignedBug()) {
1456 if (IsFast)
1457 *IsFast = Alignment != Align(2);
1458 return true;
1459 }
1460
1461 // Either, the alignment requirements are "enabled", or there is an
1462 // unaligned LDS access related hardware bug though alignment requirements
1463 // are "disabled". In either case, we need to check for proper alignment
1464 // requirements.
1465 //
1466 if (Size == 64) {
1467 // 8 byte accessing via ds_read/write_b64 require 8-byte alignment, but we
1468 // can do a 4 byte aligned, 8 byte access in a single operation using
1469 // ds_read2/write2_b32 with adjacent offsets.
1470 bool AlignedBy4 = Alignment >= Align(4);
1471 if (IsFast)
1472 *IsFast = AlignedBy4;
1473
1474 return AlignedBy4;
1475 }
1476 if (Size == 96) {
1477 // 12 byte accessing via ds_read/write_b96 require 16-byte alignment on
1478 // gfx8 and older.
1479 bool AlignedBy16 = Alignment >= Align(16);
1480 if (IsFast)
1481 *IsFast = AlignedBy16;
1482
1483 return AlignedBy16;
1484 }
1485 if (Size == 128) {
1486 // 16 byte accessing via ds_read/write_b128 require 16-byte alignment on
1487 // gfx8 and older, but we can do a 8 byte aligned, 16 byte access in a
1488 // single operation using ds_read2/write2_b64.
1489 bool AlignedBy8 = Alignment >= Align(8);
1490 if (IsFast)
1491 *IsFast = AlignedBy8;
1492
1493 return AlignedBy8;
1494 }
1495 }
1496
1497 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
1498 bool AlignedBy4 = Alignment >= Align(4);
1499 if (IsFast)
1500 *IsFast = AlignedBy4;
1501
1502 return AlignedBy4 ||
1503 Subtarget->enableFlatScratch() ||
1504 Subtarget->hasUnalignedScratchAccess();
1505 }
1506
1507 // FIXME: We have to be conservative here and assume that flat operations
1508 // will access scratch. If we had access to the IR function, then we
1509 // could determine if any private memory was used in the function.
1510 if (AddrSpace == AMDGPUAS::FLAT_ADDRESS &&
1511 !Subtarget->hasUnalignedScratchAccess()) {
1512 bool AlignedBy4 = Alignment >= Align(4);
1513 if (IsFast)
1514 *IsFast = AlignedBy4;
1515
1516 return AlignedBy4;
1517 }
1518
1519 if (Subtarget->hasUnalignedBufferAccessEnabled() &&
1520 !(AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1521 AddrSpace == AMDGPUAS::REGION_ADDRESS)) {
1522 // If we have an uniform constant load, it still requires using a slow
1523 // buffer instruction if unaligned.
1524 if (IsFast) {
1525 // Accesses can really be issued as 1-byte aligned or 4-byte aligned, so
1526 // 2-byte alignment is worse than 1 unless doing a 2-byte accesss.
1527 *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
1528 AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ?
1529 Alignment >= Align(4) : Alignment != Align(2);
1530 }
1531
1532 return true;
1533 }
1534
1535 // Smaller than dword value must be aligned.
1536 if (Size < 32)
1537 return false;
1538
1539 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
1540 // byte-address are ignored, thus forcing Dword alignment.
1541 // This applies to private, global, and constant memory.
1542 if (IsFast)
1543 *IsFast = true;
1544
1545 return Size >= 32 && Alignment >= Align(4);
1546}
1547
1548bool SITargetLowering::allowsMisalignedMemoryAccesses(
1549 EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
1550 bool *IsFast) const {
1551 if (IsFast)
1552 *IsFast = false;
1553
1554 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
1555 // which isn't a simple VT.
1556 // Until MVT is extended to handle this, simply check for the size and
1557 // rely on the condition below: allow accesses if the size is a multiple of 4.
1558 if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
1559 VT.getStoreSize() > 16)) {
1560 return false;
1561 }
1562
1563 return allowsMisalignedMemoryAccessesImpl(VT.getSizeInBits(), AddrSpace,
1564 Alignment, Flags, IsFast);
1565}
1566
1567EVT SITargetLowering::getOptimalMemOpType(
1568 const MemOp &Op, const AttributeList &FuncAttributes) const {
1569 // FIXME: Should account for address space here.
1570
1571 // The default fallback uses the private pointer size as a guess for a type to
1572 // use. Make sure we switch these to 64-bit accesses.
1573
1574 if (Op.size() >= 16 &&
1575 Op.isDstAligned(Align(4))) // XXX: Should only do for global
1576 return MVT::v4i32;
1577
1578 if (Op.size() >= 8 && Op.isDstAligned(Align(4)))
1579 return MVT::v2i32;
1580
1581 // Use the default.
1582 return MVT::Other;
1583}
1584
1585bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {
1586 const MemSDNode *MemNode = cast<MemSDNode>(N);
1587 const Value *Ptr = MemNode->getMemOperand()->getValue();
1588 const Instruction *I = dyn_cast_or_null<Instruction>(Ptr);
1589 return I && I->getMetadata("amdgpu.noclobber");
1590}
1591
1592bool SITargetLowering::isNonGlobalAddrSpace(unsigned AS) {
1593 return AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS ||
1594 AS == AMDGPUAS::PRIVATE_ADDRESS;
1595}
1596
1597bool SITargetLowering::isFreeAddrSpaceCast(unsigned SrcAS,
1598 unsigned DestAS) const {
1599 // Flat -> private/local is a simple truncate.
1600 // Flat -> global is no-op
1601 if (SrcAS == AMDGPUAS::FLAT_ADDRESS)
1602 return true;
1603
1604 const GCNTargetMachine &TM =
1605 static_cast<const GCNTargetMachine &>(getTargetMachine());
1606 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1607}
1608
1609bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
1610 const MemSDNode *MemNode = cast<MemSDNode>(N);
1611
1612 return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
1613}
1614
1615TargetLoweringBase::LegalizeTypeAction
1616SITargetLowering::getPreferredVectorAction(MVT VT) const {
1617 if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
1618 VT.getScalarType().bitsLE(MVT::i16))
1619 return VT.isPow2VectorType() ? TypeSplitVector : TypeWidenVector;
1620 return TargetLoweringBase::getPreferredVectorAction(VT);
1621}
1622
1623bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
1624 Type *Ty) const {
1625 // FIXME: Could be smarter if called for vector constants.
1626 return true;
1627}
1628
1629bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
1630 if (Subtarget->has16BitInsts() && VT == MVT::i16) {
1631 switch (Op) {
1632 case ISD::LOAD:
1633 case ISD::STORE:
1634
1635 // These operations are done with 32-bit instructions anyway.
1636 case ISD::AND:
1637 case ISD::OR:
1638 case ISD::XOR:
1639 case ISD::SELECT:
1640 // TODO: Extensions?
1641 return true;
1642 default:
1643 return false;
1644 }
1645 }
1646
1647 // SimplifySetCC uses this function to determine whether or not it should
1648 // create setcc with i1 operands. We don't have instructions for i1 setcc.
1649 if (VT == MVT::i1 && Op == ISD::SETCC)
1650 return false;
1651
1652 return TargetLowering::isTypeDesirableForOp(Op, VT);
1653}
1654
1655SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
1656 const SDLoc &SL,
1657 SDValue Chain,
1658 uint64_t Offset) const {
1659 const DataLayout &DL = DAG.getDataLayout();
1660 MachineFunction &MF = DAG.getMachineFunction();
1661 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1662
1663 const ArgDescriptor *InputPtrReg;
1664 const TargetRegisterClass *RC;
1665 LLT ArgTy;
1666 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
1667
1668 std::tie(InputPtrReg, RC, ArgTy) =
1669 Info->getPreloadedValue(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
1670
1671 // We may not have the kernarg segment argument if we have no kernel
1672 // arguments.
1673 if (!InputPtrReg)
1674 return DAG.getConstant(0, SL, PtrVT);
1675
1676 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1677 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
1678 MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
1679
1680 return DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Offset));
1681}
1682
1683SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
1684 const SDLoc &SL) const {
1685 uint64_t Offset = getImplicitParameterOffset(DAG.getMachineFunction(),
1686 FIRST_IMPLICIT);
1687 return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset);
1688}
1689
1690SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
1691 const SDLoc &SL, SDValue Val,
1692 bool Signed,
1693 const ISD::InputArg *Arg) const {
1694 // First, if it is a widened vector, narrow it.
1695 if (VT.isVector() &&
1696 VT.getVectorNumElements() != MemVT.getVectorNumElements()) {
1697 EVT NarrowedVT =
1698 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(),
1699 VT.getVectorNumElements());
1700 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val,
1701 DAG.getConstant(0, SL, MVT::i32));
1702 }
1703
1704 // Then convert the vector elements or scalar value.
1705 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
1706 VT.bitsLT(MemVT)) {
1707 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
1708 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT));
1709 }
1710
1711 if (MemVT.isFloatingPoint())
1712 Val = getFPExtOrFPRound(DAG, Val, SL, VT);
1713 else if (Signed)
1714 Val = DAG.getSExtOrTrunc(Val, SL, VT);
1715 else
1716 Val = DAG.getZExtOrTrunc(Val, SL, VT);
1717
1718 return Val;
1719}
1720
1721SDValue SITargetLowering::lowerKernargMemParameter(
1722 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain,
1723 uint64_t Offset, Align Alignment, bool Signed,
1724 const ISD::InputArg *Arg) const {
1725 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
1726
1727 // Try to avoid using an extload by loading earlier than the argument address,
1728 // and extracting the relevant bits. The load should hopefully be merged with
1729 // the previous argument.
1730 if (MemVT.getStoreSize() < 4 && Alignment < 4) {
1731 // TODO: Handle align < 4 and size >= 4 (can happen with packed structs).
1732 int64_t AlignDownOffset = alignDown(Offset, 4);
1733 int64_t OffsetDiff = Offset - AlignDownOffset;
1734
1735 EVT IntVT = MemVT.changeTypeToInteger();
1736
1737 // TODO: If we passed in the base kernel offset we could have a better
1738 // alignment than 4, but we don't really need it.
1739 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
1740 SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, Align(4),
1741 MachineMemOperand::MODereferenceable |
1742 MachineMemOperand::MOInvariant);
1743
1744 SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
1745 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
1746
1747 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract);
1748 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal);
1749 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg);
1750
1751
1752 return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
1753 }
1754
1755 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
1756 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Alignment,
1757 MachineMemOperand::MODereferenceable |
1758 MachineMemOperand::MOInvariant);
1759
1760 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg);
1761 return DAG.getMergeValues({ Val, Load.getValue(1) }, SL);
1762}
1763
1764SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
1765 const SDLoc &SL, SDValue Chain,
1766 const ISD::InputArg &Arg) const {
1767 MachineFunction &MF = DAG.getMachineFunction();
1768 MachineFrameInfo &MFI = MF.getFrameInfo();
1769
1770 if (Arg.Flags.isByVal()) {
1771 unsigned Size = Arg.Flags.getByValSize();
1772 int FrameIdx = MFI.CreateFixedObject(Size, VA.getLocMemOffset(), false);
1773 return DAG.getFrameIndex(FrameIdx, MVT::i32);
1774 }
1775
1776 unsigned ArgOffset = VA.getLocMemOffset();
1777 unsigned ArgSize = VA.getValVT().getStoreSize();
1778
1779 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, true);
1780
1781 // Create load nodes to retrieve arguments from the stack.
1782 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1783 SDValue ArgValue;
1784
1785 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1786 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1787 MVT MemVT = VA.getValVT();
1788
1789 switch (VA.getLocInfo()) {
1790 default:
1791 break;
1792 case CCValAssign::BCvt:
1793 MemVT = VA.getLocVT();
1794 break;
1795 case CCValAssign::SExt:
1796 ExtType = ISD::SEXTLOAD;
1797 break;
1798 case CCValAssign::ZExt:
1799 ExtType = ISD::ZEXTLOAD;
1800 break;
1801 case CCValAssign::AExt:
1802 ExtType = ISD::EXTLOAD;
1803 break;
1804 }
1805
1806 ArgValue = DAG.getExtLoad(
1807 ExtType, SL, VA.getLocVT(), Chain, FIN,
1808 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
1809 MemVT);
1810 return ArgValue;
1811}
1812
1813SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,
1814 const SIMachineFunctionInfo &MFI,
1815 EVT VT,
1816 AMDGPUFunctionArgInfo::PreloadedValue PVID) const {
1817 const ArgDescriptor *Reg;
1818 const TargetRegisterClass *RC;
1819 LLT Ty;
1820
1821 std::tie(Reg, RC, Ty) = MFI.getPreloadedValue(PVID);
1822 if (!Reg) {
1823 if (PVID == AMDGPUFunctionArgInfo::PreloadedValue::KERNARG_SEGMENT_PTR) {
1824 // It's possible for a kernarg intrinsic call to appear in a kernel with
1825 // no allocated segment, in which case we do not add the user sgpr
1826 // argument, so just return null.
1827 return DAG.getConstant(0, SDLoc(), VT);
1828 }
1829
1830 // It's undefined behavior if a function marked with the amdgpu-no-*
1831 // attributes uses the corresponding intrinsic.
1832 return DAG.getUNDEF(VT);
1833 }
1834
1835 return CreateLiveInRegister(DAG, RC, Reg->getRegister(), VT);
1836}
1837
1838static void processPSInputArgs(SmallVectorImpl<ISD::InputArg> &Splits,
1839 CallingConv::ID CallConv,
1840 ArrayRef<ISD::InputArg> Ins, BitVector &Skipped,
1841 FunctionType *FType,
1842 SIMachineFunctionInfo *Info) {
1843 for (unsigned I = 0, E = Ins.size(), PSInputNum = 0; I != E; ++I) {
1844 const ISD::InputArg *Arg = &Ins[I];
1845
1846 assert((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) &&(static_cast <bool> ((!Arg->VT.isVector() || Arg->
VT.getScalarSizeInBits() == 16) && "vector type argument should have been split"
) ? void (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1847, __extension__ __PRETTY_FUNCTION__))
1847 "vector type argument should have been split")(static_cast <bool> ((!Arg->VT.isVector() || Arg->
VT.getScalarSizeInBits() == 16) && "vector type argument should have been split"
) ? void (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1847, __extension__ __PRETTY_FUNCTION__))
;
1848
1849 // First check if it's a PS input addr.
1850 if (CallConv == CallingConv::AMDGPU_PS &&
1851 !Arg->Flags.isInReg() && PSInputNum <= 15) {
1852 bool SkipArg = !Arg->Used && !Info->isPSInputAllocated(PSInputNum);
1853
1854 // Inconveniently only the first part of the split is marked as isSplit,
1855 // so skip to the end. We only want to increment PSInputNum once for the
1856 // entire split argument.
1857 if (Arg->Flags.isSplit()) {
1858 while (!Arg->Flags.isSplitEnd()) {
1859 assert((!Arg->VT.isVector() ||(static_cast <bool> ((!Arg->VT.isVector() || Arg->
VT.getScalarSizeInBits() == 16) && "unexpected vector split in ps argument type"
) ? void (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1861, __extension__ __PRETTY_FUNCTION__))
1860 Arg->VT.getScalarSizeInBits() == 16) &&(static_cast <bool> ((!Arg->VT.isVector() || Arg->
VT.getScalarSizeInBits() == 16) && "unexpected vector split in ps argument type"
) ? void (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1861, __extension__ __PRETTY_FUNCTION__))
1861 "unexpected vector split in ps argument type")(static_cast <bool> ((!Arg->VT.isVector() || Arg->
VT.getScalarSizeInBits() == 16) && "unexpected vector split in ps argument type"
) ? void (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1861, __extension__ __PRETTY_FUNCTION__))
;
1862 if (!SkipArg)
1863 Splits.push_back(*Arg);
1864 Arg = &Ins[++I];
1865 }
1866 }
1867
1868 if (SkipArg) {
1869 // We can safely skip PS inputs.
1870 Skipped.set(Arg->getOrigArgIndex());
1871 ++PSInputNum;
1872 continue;
1873 }
1874
1875 Info->markPSInputAllocated(PSInputNum);
1876 if (Arg->Used)
1877 Info->markPSInputEnabled(PSInputNum);
1878
1879 ++PSInputNum;
1880 }
1881
1882 Splits.push_back(*Arg);
1883 }
1884}
1885
1886// Allocate special inputs passed in VGPRs.
1887void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,
1888 MachineFunction &MF,
1889 const SIRegisterInfo &TRI,
1890 SIMachineFunctionInfo &Info) const {
1891 const LLT S32 = LLT::scalar(32);
1892 MachineRegisterInfo &MRI = MF.getRegInfo();
1893
1894 if (Info.hasWorkItemIDX()) {
1895 Register Reg = AMDGPU::VGPR0;
1896 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1897
1898 CCInfo.AllocateReg(Reg);
1899 unsigned Mask = (Subtarget->hasPackedTID() &&
1900 Info.hasWorkItemIDY()) ? 0x3ff : ~0u;
1901 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask));
1902 }
1903
1904 if (Info.hasWorkItemIDY()) {
1905 assert(Info.hasWorkItemIDX())(static_cast <bool> (Info.hasWorkItemIDX()) ? void (0) :
__assert_fail ("Info.hasWorkItemIDX()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1905, __extension__ __PRETTY_FUNCTION__))
;
1906 if (Subtarget->hasPackedTID()) {
1907 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0,
1908 0x3ff << 10));
1909 } else {
1910 unsigned Reg = AMDGPU::VGPR1;
1911 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1912
1913 CCInfo.AllocateReg(Reg);
1914 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg));
1915 }
1916 }
1917
1918 if (Info.hasWorkItemIDZ()) {
1919 assert(Info.hasWorkItemIDX() && Info.hasWorkItemIDY())(static_cast <bool> (Info.hasWorkItemIDX() && Info
.hasWorkItemIDY()) ? void (0) : __assert_fail ("Info.hasWorkItemIDX() && Info.hasWorkItemIDY()"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1919, __extension__ __PRETTY_FUNCTION__))
;
1920 if (Subtarget->hasPackedTID()) {
1921 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0,
1922 0x3ff << 20));
1923 } else {
1924 unsigned Reg = AMDGPU::VGPR2;
1925 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1926
1927 CCInfo.AllocateReg(Reg);
1928 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg));
1929 }
1930 }
1931}
1932
1933// Try to allocate a VGPR at the end of the argument list, or if no argument
1934// VGPRs are left allocating a stack slot.
1935// If \p Mask is is given it indicates bitfield position in the register.
1936// If \p Arg is given use it with new ]p Mask instead of allocating new.
1937static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,
1938 ArgDescriptor Arg = ArgDescriptor()) {
1939 if (Arg.isSet())
1940 return ArgDescriptor::createArg(Arg, Mask);
1941
1942 ArrayRef<MCPhysReg> ArgVGPRs
1943 = makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), 32);
1944 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
1945 if (RegIdx == ArgVGPRs.size()) {
1946 // Spill to stack required.
1947 int64_t Offset = CCInfo.AllocateStack(4, Align(4));
1948
1949 return ArgDescriptor::createStack(Offset, Mask);
1950 }
1951
1952 unsigned Reg = ArgVGPRs[RegIdx];
1953 Reg = CCInfo.AllocateReg(Reg);
1954 assert(Reg != AMDGPU::NoRegister)(static_cast <bool> (Reg != AMDGPU::NoRegister) ? void (
0) : __assert_fail ("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1954, __extension__ __PRETTY_FUNCTION__))
;
1955
1956 MachineFunction &MF = CCInfo.getMachineFunction();
1957 Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1958 MF.getRegInfo().setType(LiveInVReg, LLT::scalar(32));
1959 return ArgDescriptor::createRegister(Reg, Mask);
1960}
1961
1962static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,
1963 const TargetRegisterClass *RC,
1964 unsigned NumArgRegs) {
1965 ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
1966 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
1967 if (RegIdx == ArgSGPRs.size())
1968 report_fatal_error("ran out of SGPRs for arguments");
1969
1970 unsigned Reg = ArgSGPRs[RegIdx];
1971 Reg = CCInfo.AllocateReg(Reg);
1972 assert(Reg != AMDGPU::NoRegister)(static_cast <bool> (Reg != AMDGPU::NoRegister) ? void (
0) : __assert_fail ("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1972, __extension__ __PRETTY_FUNCTION__))
;
1973
1974 MachineFunction &MF = CCInfo.getMachineFunction();
1975 MF.addLiveIn(Reg, RC);
1976 return ArgDescriptor::createRegister(Reg);
1977}
1978
1979// If this has a fixed position, we still should allocate the register in the
1980// CCInfo state. Technically we could get away with this for values passed
1981// outside of the normal argument range.
1982static void allocateFixedSGPRInputImpl(CCState &CCInfo,
1983 const TargetRegisterClass *RC,
1984 MCRegister Reg) {
1985 Reg = CCInfo.AllocateReg(Reg);
1986 assert(Reg != AMDGPU::NoRegister)(static_cast <bool> (Reg != AMDGPU::NoRegister) ? void (
0) : __assert_fail ("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1986, __extension__ __PRETTY_FUNCTION__))
;
1987 MachineFunction &MF = CCInfo.getMachineFunction();
1988 MF.addLiveIn(Reg, RC);
1989}
1990
1991static void allocateSGPR32Input(CCState &CCInfo, ArgDescriptor &Arg) {
1992 if (Arg) {
1993 allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_32RegClass,
1994 Arg.getRegister());
1995 } else
1996 Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
1997}
1998
1999static void allocateSGPR64Input(CCState &CCInfo, ArgDescriptor &Arg) {
2000 if (Arg) {
2001 allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_64RegClass,
2002 Arg.getRegister());
2003 } else
2004 Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);
2005}
2006
2007/// Allocate implicit function VGPR arguments at the end of allocated user
2008/// arguments.
2009void SITargetLowering::allocateSpecialInputVGPRs(
2010 CCState &CCInfo, MachineFunction &MF,
2011 const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const {
2012 const unsigned Mask = 0x3ff;
2013 ArgDescriptor Arg;
2014
2015 if (Info.hasWorkItemIDX()) {
2016 Arg = allocateVGPR32Input(CCInfo, Mask);
2017 Info.setWorkItemIDX(Arg);
2018 }
2019
2020 if (Info.hasWorkItemIDY()) {
2021 Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);
2022 Info.setWorkItemIDY(Arg);
2023 }
2024
2025 if (Info.hasWorkItemIDZ())
2026 Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));
2027}
2028
2029/// Allocate implicit function VGPR arguments in fixed registers.
2030void SITargetLowering::allocateSpecialInputVGPRsFixed(
2031 CCState &CCInfo, MachineFunction &MF,
2032 const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const {
2033 Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31);
2034 if (!Reg)
2035 report_fatal_error("failed to allocated VGPR for implicit arguments");
2036
2037 const unsigned Mask = 0x3ff;
2038 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask));
2039 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg, Mask << 10));
2040 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg, Mask << 20));
2041}
2042
2043void SITargetLowering::allocateSpecialInputSGPRs(
2044 CCState &CCInfo,
2045 MachineFunction &MF,
2046 const SIRegisterInfo &TRI,
2047 SIMachineFunctionInfo &Info) const {
2048 auto &ArgInfo = Info.getArgInfo();
2049
2050 // We need to allocate these in place regardless of their use.
2051 const bool IsFixed = AMDGPUTargetMachine::EnableFixedFunctionABI;
2052
2053 // TODO: Unify handling with private memory pointers.
2054 if (IsFixed || Info.hasDispatchPtr())
2055 allocateSGPR64Input(CCInfo, ArgInfo.DispatchPtr);
2056
2057 if (IsFixed || Info.hasQueuePtr())
2058 allocateSGPR64Input(CCInfo, ArgInfo.QueuePtr);
2059
2060 // Implicit arg ptr takes the place of the kernarg segment pointer. This is a
2061 // constant offset from the kernarg segment.
2062 if (IsFixed || Info.hasImplicitArgPtr())
2063 allocateSGPR64Input(CCInfo, ArgInfo.ImplicitArgPtr);
2064
2065 if (IsFixed || Info.hasDispatchID())
2066 allocateSGPR64Input(CCInfo, ArgInfo.DispatchID);
2067
2068 // flat_scratch_init is not applicable for non-kernel functions.
2069
2070 if (IsFixed || Info.hasWorkGroupIDX())
2071 allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDX);
2072
2073 if (IsFixed || Info.hasWorkGroupIDY())
2074 allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDY);
2075
2076 if (IsFixed || Info.hasWorkGroupIDZ())
2077 allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDZ);
2078}
2079
2080// Allocate special inputs passed in user SGPRs.
2081void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
2082 MachineFunction &MF,
2083 const SIRegisterInfo &TRI,
2084 SIMachineFunctionInfo &Info) const {
2085 if (Info.hasImplicitBufferPtr()) {
2086 Register ImplicitBufferPtrReg = Info.addImplicitBufferPtr(TRI);
2087 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
2088 CCInfo.AllocateReg(ImplicitBufferPtrReg);
2089 }
2090
2091 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
2092 if (Info.hasPrivateSegmentBuffer()) {
2093 Register PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
2094 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
2095 CCInfo.AllocateReg(PrivateSegmentBufferReg);
2096 }
2097
2098 if (Info.hasDispatchPtr()) {
2099 Register DispatchPtrReg = Info.addDispatchPtr(TRI);
2100 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
2101 CCInfo.AllocateReg(DispatchPtrReg);
2102 }
2103
2104 if (Info.hasQueuePtr()) {
2105 Register QueuePtrReg = Info.addQueuePtr(TRI);
2106 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
2107 CCInfo.AllocateReg(QueuePtrReg);
2108 }
2109
2110 if (Info.hasKernargSegmentPtr()) {
2111 MachineRegisterInfo &MRI = MF.getRegInfo();
2112 Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
2113 CCInfo.AllocateReg(InputPtrReg);
2114
2115 Register VReg = MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
2116 MRI.setType(VReg, LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
2117 }
2118
2119 if (Info.hasDispatchID()) {
2120 Register DispatchIDReg = Info.addDispatchID(TRI);
2121 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
2122 CCInfo.AllocateReg(DispatchIDReg);
2123 }
2124
2125 if (Info.hasFlatScratchInit() && !getSubtarget()->isAmdPalOS()) {
2126 Register FlatScratchInitReg = Info.addFlatScratchInit(TRI);
2127 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
2128 CCInfo.AllocateReg(FlatScratchInitReg);
2129 }
2130
2131 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
2132 // these from the dispatch pointer.
2133}
2134
2135// Allocate special input registers that are initialized per-wave.
2136void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,
2137 MachineFunction &MF,
2138 SIMachineFunctionInfo &Info,
2139 CallingConv::ID CallConv,
2140 bool IsShader) const {
2141 if (Info.hasWorkGroupIDX()) {
2142 Register Reg = Info.addWorkGroupIDX();
2143 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2144 CCInfo.AllocateReg(Reg);
2145 }
2146
2147 if (Info.hasWorkGroupIDY()) {
2148 Register Reg = Info.addWorkGroupIDY();
2149 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2150 CCInfo.AllocateReg(Reg);
2151 }
2152
2153 if (Info.hasWorkGroupIDZ()) {
2154 Register Reg = Info.addWorkGroupIDZ();
2155 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2156 CCInfo.AllocateReg(Reg);
2157 }
2158
2159 if (Info.hasWorkGroupInfo()) {
2160 Register Reg = Info.addWorkGroupInfo();
2161 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2162 CCInfo.AllocateReg(Reg);
2163 }
2164
2165 if (Info.hasPrivateSegmentWaveByteOffset()) {
2166 // Scratch wave offset passed in system SGPR.
2167 unsigned PrivateSegmentWaveByteOffsetReg;
2168
2169 if (IsShader) {
2170 PrivateSegmentWaveByteOffsetReg =
2171 Info.getPrivateSegmentWaveByteOffsetSystemSGPR();
2172
2173 // This is true if the scratch wave byte offset doesn't have a fixed
2174 // location.
2175 if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) {
2176 PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
2177 Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
2178 }
2179 } else
2180 PrivateSegmentWaveByteOffsetReg = Info.addPrivateSegmentWaveByteOffset();
2181
2182 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
2183 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
2184 }
2185}
2186
2187static void reservePrivateMemoryRegs(const TargetMachine &TM,
2188 MachineFunction &MF,
2189 const SIRegisterInfo &TRI,
2190 SIMachineFunctionInfo &Info) {
2191 // Now that we've figured out where the scratch register inputs are, see if
2192 // should reserve the arguments and use them directly.
2193 MachineFrameInfo &MFI = MF.getFrameInfo();
2194 bool HasStackObjects = MFI.hasStackObjects();
2195 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
2196
2197 // Record that we know we have non-spill stack objects so we don't need to
2198 // check all stack objects later.
2199 if (HasStackObjects)
2200 Info.setHasNonSpillStackObjects(true);
2201
2202 // Everything live out of a block is spilled with fast regalloc, so it's
2203 // almost certain that spilling will be required.
2204 if (TM.getOptLevel() == CodeGenOpt::None)
2205 HasStackObjects = true;
2206
2207 // For now assume stack access is needed in any callee functions, so we need
2208 // the scratch registers to pass in.
2209 bool RequiresStackAccess = HasStackObjects || MFI.hasCalls();
2210
2211 if (!ST.enableFlatScratch()) {
2212 if (RequiresStackAccess && ST.isAmdHsaOrMesa(MF.getFunction())) {
2213 // If we have stack objects, we unquestionably need the private buffer
2214 // resource. For the Code Object V2 ABI, this will be the first 4 user
2215 // SGPR inputs. We can reserve those and use them directly.
2216
2217 Register PrivateSegmentBufferReg =
2218 Info.getPreloadedReg(AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER);
2219 Info.setScratchRSrcReg(PrivateSegmentBufferReg);
2220 } else {
2221 unsigned ReservedBufferReg = TRI.reservedPrivateSegmentBufferReg(MF);
2222 // We tentatively reserve the last registers (skipping the last registers
2223 // which may contain VCC, FLAT_SCR, and XNACK). After register allocation,
2224 // we'll replace these with the ones immediately after those which were
2225 // really allocated. In the prologue copies will be inserted from the
2226 // argument to these reserved registers.
2227
2228 // Without HSA, relocations are used for the scratch pointer and the
2229 // buffer resource setup is always inserted in the prologue. Scratch wave
2230 // offset is still in an input SGPR.
2231 Info.setScratchRSrcReg(ReservedBufferReg);
2232 }
2233 }
2234
2235 MachineRegisterInfo &MRI = MF.getRegInfo();
2236
2237 // For entry functions we have to set up the stack pointer if we use it,
2238 // whereas non-entry functions get this "for free". This means there is no
2239 // intrinsic advantage to using S32 over S34 in cases where we do not have
2240 // calls but do need a frame pointer (i.e. if we are requested to have one
2241 // because frame pointer elimination is disabled). To keep things simple we
2242 // only ever use S32 as the call ABI stack pointer, and so using it does not
2243 // imply we need a separate frame pointer.
2244 //
2245 // Try to use s32 as the SP, but move it if it would interfere with input
2246 // arguments. This won't work with calls though.
2247 //
2248 // FIXME: Move SP to avoid any possible inputs, or find a way to spill input
2249 // registers.
2250 if (!MRI.isLiveIn(AMDGPU::SGPR32)) {
2251 Info.setStackPtrOffsetReg(AMDGPU::SGPR32);
2252 } else {
2253 assert(AMDGPU::isShader(MF.getFunction().getCallingConv()))(static_cast <bool> (AMDGPU::isShader(MF.getFunction().
getCallingConv())) ? void (0) : __assert_fail ("AMDGPU::isShader(MF.getFunction().getCallingConv())"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2253, __extension__ __PRETTY_FUNCTION__))
;
2254
2255 if (MFI.hasCalls())
2256 report_fatal_error("call in graphics shader with too many input SGPRs");
2257
2258 for (unsigned Reg : AMDGPU::SGPR_32RegClass) {
2259 if (!MRI.isLiveIn(Reg)) {
2260 Info.setStackPtrOffsetReg(Reg);
2261 break;
2262 }
2263 }
2264
2265 if (Info.getStackPtrOffsetReg() == AMDGPU::SP_REG)
2266 report_fatal_error("failed to find register for SP");
2267 }
2268
2269 // hasFP should be accurate for entry functions even before the frame is
2270 // finalized, because it does not rely on the known stack size, only
2271 // properties like whether variable sized objects are present.
2272 if (ST.getFrameLowering()->hasFP(MF)) {
2273 Info.setFrameOffsetReg(AMDGPU::SGPR33);
2274 }
2275}
2276
2277bool SITargetLowering::supportSplitCSR(MachineFunction *MF) const {
2278 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
2279 return !Info->isEntryFunction();
2280}
2281
2282void SITargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
2283
2284}
2285
2286void SITargetLowering::insertCopiesSplitCSR(
2287 MachineBasicBlock *Entry,
2288 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
2289 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2290
2291 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
2292 if (!IStart)
2293 return;
2294
2295 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2296 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
2297 MachineBasicBlock::iterator MBBI = Entry->begin();
2298 for (const MCPhysReg *I = IStart; *I; ++I) {
2299 const TargetRegisterClass *RC = nullptr;
2300 if (AMDGPU::SReg_64RegClass.contains(*I))
2301 RC = &AMDGPU::SGPR_64RegClass;
2302 else if (AMDGPU::SReg_32RegClass.contains(*I))
2303 RC = &AMDGPU::SGPR_32RegClass;
2304 else
2305 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2305)
;
2306
2307 Register NewVR = MRI->createVirtualRegister(RC);
2308 // Create copy from CSR to a virtual register.
2309 Entry->addLiveIn(*I);
2310 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
2311 .addReg(*I);
2312
2313 // Insert the copy-back instructions right before the terminator.
2314 for (auto *Exit : Exits)
2315 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
2316 TII->get(TargetOpcode::COPY), *I)
2317 .addReg(NewVR);
2318 }
2319}
2320
2321SDValue SITargetLowering::LowerFormalArguments(
2322 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2323 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2324 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2325 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2326
2327 MachineFunction &MF = DAG.getMachineFunction();
2328 const Function &Fn = MF.getFunction();
2329 FunctionType *FType = MF.getFunction().getFunctionType();
2330 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2331
2332 if (Subtarget->isAmdHsaOS() && AMDGPU::isGraphics(CallConv)) {
2333 DiagnosticInfoUnsupported NoGraphicsHSA(
2334 Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
2335 DAG.getContext()->diagnose(NoGraphicsHSA);
2336 return DAG.getEntryNode();
2337 }
2338
2339 Info->allocateModuleLDSGlobal(Fn.getParent());
2340
2341 SmallVector<ISD::InputArg, 16> Splits;
2342 SmallVector<CCValAssign, 16> ArgLocs;
2343 BitVector Skipped(Ins.size());
2344 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2345 *DAG.getContext());
2346
2347 bool IsGraphics = AMDGPU::isGraphics(CallConv);
2348 bool IsKernel = AMDGPU::isKernel(CallConv);
2349 bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CallConv);
2350
2351 if (IsGraphics) {
2352 assert(!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() &&(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2357, __extension__ __PRETTY_FUNCTION__))
2353 (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) &&(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2357, __extension__ __PRETTY_FUNCTION__))
2354 !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2357, __extension__ __PRETTY_FUNCTION__))
2355 !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2357, __extension__ __PRETTY_FUNCTION__))
2356 !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2357, __extension__ __PRETTY_FUNCTION__))
2357 !Info->hasWorkItemIDZ())(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2357, __extension__ __PRETTY_FUNCTION__))
;
2358 }
2359
2360 if (CallConv == CallingConv::AMDGPU_PS) {
2361 processPSInputArgs(Splits, CallConv, Ins, Skipped, FType, Info);
2362
2363 // At least one interpolation mode must be enabled or else the GPU will
2364 // hang.
2365 //
2366 // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
2367 // set PSInputAddr, the user wants to enable some bits after the compilation
2368 // based on run-time states. Since we can't know what the final PSInputEna
2369 // will look like, so we shouldn't do anything here and the user should take
2370 // responsibility for the correct programming.
2371 //
2372 // Otherwise, the following restrictions apply:
2373 // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
2374 // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
2375 // enabled too.
2376 if ((Info->getPSInputAddr() & 0x7F) == 0 ||
2377 ((Info->getPSInputAddr() & 0xF) == 0 && Info->isPSInputAllocated(11))) {
2378 CCInfo.AllocateReg(AMDGPU::VGPR0);
2379 CCInfo.AllocateReg(AMDGPU::VGPR1);
2380 Info->markPSInputAllocated(0);
2381 Info->markPSInputEnabled(0);
2382 }
2383 if (Subtarget->isAmdPalOS()) {
2384 // For isAmdPalOS, the user does not enable some bits after compilation
2385 // based on run-time states; the register values being generated here are
2386 // the final ones set in hardware. Therefore we need to apply the
2387 // workaround to PSInputAddr and PSInputEnable together. (The case where
2388 // a bit is set in PSInputAddr but not PSInputEnable is where the
2389 // frontend set up an input arg for a particular interpolation mode, but
2390 // nothing uses that input arg. Really we should have an earlier pass
2391 // that removes such an arg.)
2392 unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
2393 if ((PsInputBits & 0x7F) == 0 ||
2394 ((PsInputBits & 0xF) == 0 && (PsInputBits >> 11 & 1)))
2395 Info->markPSInputEnabled(
2396 countTrailingZeros(Info->getPSInputAddr(), ZB_Undefined));
2397 }
2398 } else if (IsKernel) {
2399 assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX())(static_cast <bool> (Info->hasWorkGroupIDX() &&
Info->hasWorkItemIDX()) ? void (0) : __assert_fail ("Info->hasWorkGroupIDX() && Info->hasWorkItemIDX()"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2399, __extension__ __PRETTY_FUNCTION__))
;
2400 } else {
2401 Splits.append(Ins.begin(), Ins.end());
2402 }
2403
2404 if (IsEntryFunc) {
2405 allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
2406 allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
2407 } else {
2408 // For the fixed ABI, pass workitem IDs in the last argument register.
2409 if (AMDGPUTargetMachine::EnableFixedFunctionABI)
2410 allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
2411 }
2412
2413 if (IsKernel) {
2414 analyzeFormalArgumentsCompute(CCInfo, Ins);
2415 } else {
2416 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg);
2417 CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
2418 }
2419
2420 SmallVector<SDValue, 16> Chains;
2421
2422 // FIXME: This is the minimum kernel argument alignment. We should improve
2423 // this to the maximum alignment of the arguments.
2424 //
2425 // FIXME: Alignment of explicit arguments totally broken with non-0 explicit
2426 // kern arg offset.
2427 const Align KernelArgBaseAlign = Align(16);
2428
2429 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
2430 const ISD::InputArg &Arg = Ins[i];
2431 if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
2432 InVals.push_back(DAG.getUNDEF(Arg.VT));
2433 continue;
2434 }
2435
2436 CCValAssign &VA = ArgLocs[ArgIdx++];
2437 MVT VT = VA.getLocVT();
2438
2439 if (IsEntryFunc && VA.isMemLoc()) {
2440 VT = Ins[i].VT;
2441 EVT MemVT = VA.getLocVT();
2442
2443 const uint64_t Offset = VA.getLocMemOffset();
2444 Align Alignment = commonAlignment(KernelArgBaseAlign, Offset);
2445
2446 if (Arg.Flags.isByRef()) {
2447 SDValue Ptr = lowerKernArgParameterPtr(DAG, DL, Chain, Offset);
2448
2449 const GCNTargetMachine &TM =
2450 static_cast<const GCNTargetMachine &>(getTargetMachine());
2451 if (!TM.isNoopAddrSpaceCast(AMDGPUAS::CONSTANT_ADDRESS,
2452 Arg.Flags.getPointerAddrSpace())) {
2453 Ptr = DAG.getAddrSpaceCast(DL, VT, Ptr, AMDGPUAS::CONSTANT_ADDRESS,
2454 Arg.Flags.getPointerAddrSpace());
2455 }
2456
2457 InVals.push_back(Ptr);
2458 continue;
2459 }
2460
2461 SDValue Arg = lowerKernargMemParameter(
2462 DAG, VT, MemVT, DL, Chain, Offset, Alignment, Ins[i].Flags.isSExt(), &Ins[i]);
2463 Chains.push_back(Arg.getValue(1));
2464
2465 auto *ParamTy =
2466 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
2467 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
2468 ParamTy && (ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
2469 ParamTy->getAddressSpace() == AMDGPUAS::REGION_ADDRESS)) {
2470 // On SI local pointers are just offsets into LDS, so they are always
2471 // less than 16-bits. On CI and newer they could potentially be
2472 // real pointers, so we can't guarantee their size.
2473 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
2474 DAG.getValueType(MVT::i16));
2475 }
2476
2477 InVals.push_back(Arg);
2478 continue;
2479 } else if (!IsEntryFunc && VA.isMemLoc()) {
2480 SDValue Val = lowerStackParameter(DAG, VA, DL, Chain, Arg);
2481 InVals.push_back(Val);
2482 if (!Arg.Flags.isByVal())
2483 Chains.push_back(Val.getValue(1));
2484 continue;
2485 }
2486
2487 assert(VA.isRegLoc() && "Parameter must be in a register!")(static_cast <bool> (VA.isRegLoc() && "Parameter must be in a register!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Parameter must be in a register!\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2487, __extension__ __PRETTY_FUNCTION__))
;
2488
2489 Register Reg = VA.getLocReg();
2490 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2491 EVT ValVT = VA.getValVT();
2492
2493 Reg = MF.addLiveIn(Reg, RC);
2494 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
2495
2496 if (Arg.Flags.isSRet()) {
2497 // The return object should be reasonably addressable.
2498
2499 // FIXME: This helps when the return is a real sret. If it is a
2500 // automatically inserted sret (i.e. CanLowerReturn returns false), an
2501 // extra copy is inserted in SelectionDAGBuilder which obscures this.
2502 unsigned NumBits
2503 = 32 - getSubtarget()->getKnownHighZeroBitsForFrameIndex();
2504 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2505 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), NumBits)));
2506 }
2507
2508 // If this is an 8 or 16-bit value, it is really passed promoted
2509 // to 32 bits. Insert an assert[sz]ext to capture this, then
2510 // truncate to the right size.
2511 switch (VA.getLocInfo()) {
2512 case CCValAssign::Full:
2513 break;
2514 case CCValAssign::BCvt:
2515 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2516 break;
2517 case CCValAssign::SExt:
2518 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val,
2519 DAG.getValueType(ValVT));
2520 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2521 break;
2522 case CCValAssign::ZExt:
2523 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2524 DAG.getValueType(ValVT));
2525 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2526 break;
2527 case CCValAssign::AExt:
2528 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2529 break;
2530 default:
2531 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2531)
;
2532 }
2533
2534 InVals.push_back(Val);
2535 }
2536
2537 if (!IsEntryFunc && !AMDGPUTargetMachine::EnableFixedFunctionABI) {
2538 // Special inputs come after user arguments.
2539 allocateSpecialInputVGPRs(CCInfo, MF, *TRI, *Info);
2540 }
2541
2542 // Start adding system SGPRs.
2543 if (IsEntryFunc) {
2544 allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics);
2545 } else {
2546 CCInfo.AllocateReg(Info->getScratchRSrcReg());
2547 allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
2548 }
2549
2550 auto &ArgUsageInfo =
2551 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2552 ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
2553
2554 unsigned StackArgSize = CCInfo.getNextStackOffset();
2555 Info->setBytesInStackArgArea(StackArgSize);
2556
2557 return Chains.empty() ? Chain :
2558 DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
2559}
2560
2561// TODO: If return values can't fit in registers, we should return as many as
2562// possible in registers before passing on stack.
2563bool SITargetLowering::CanLowerReturn(
2564 CallingConv::ID CallConv,
2565 MachineFunction &MF, bool IsVarArg,
2566 const SmallVectorImpl<ISD::OutputArg> &Outs,
2567 LLVMContext &Context) const {
2568 // Replacing returns with sret/stack usage doesn't make sense for shaders.
2569 // FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
2570 // for shaders. Vector types should be explicitly handled by CC.
2571 if (AMDGPU::isEntryFunctionCC(CallConv))
2572 return true;
2573
2574 SmallVector<CCValAssign, 16> RVLocs;
2575 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2576 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
2577}
2578
2579SDValue
2580SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2581 bool isVarArg,
2582 const SmallVectorImpl<ISD::OutputArg> &Outs,
2583 const SmallVectorImpl<SDValue> &OutVals,
2584 const SDLoc &DL, SelectionDAG &DAG) const {
2585 MachineFunction &MF = DAG.getMachineFunction();
2586 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2587
2588 if (AMDGPU::isKernel(CallConv)) {
2589 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
2590 OutVals, DL, DAG);
2591 }
2592
2593 bool IsShader = AMDGPU::isShader(CallConv);
2594
2595 Info->setIfReturnsVoid(Outs.empty());
2596 bool IsWaveEnd = Info->returnsVoid() && IsShader;
2597
2598 // CCValAssign - represent the assignment of the return value to a location.
2599 SmallVector<CCValAssign, 48> RVLocs;
2600 SmallVector<ISD::OutputArg, 48> Splits;
2601
2602 // CCState - Info about the registers and stack slots.
2603 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2604 *DAG.getContext());
2605
2606 // Analyze outgoing return values.
2607 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2608
2609 SDValue Flag;
2610 SmallVector<SDValue, 48> RetOps;
2611 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2612
2613 // Add return address for callable functions.
2614 if (!Info->isEntryFunction()) {
2615 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2616 SDValue ReturnAddrReg = CreateLiveInRegister(
2617 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2618
2619 SDValue ReturnAddrVirtualReg =
2620 DAG.getRegister(MF.getRegInfo().createVirtualRegister(
2621 CallConv != CallingConv::AMDGPU_Gfx
2622 ? &AMDGPU::CCR_SGPR_64RegClass
2623 : &AMDGPU::Gfx_CCR_SGPR_64RegClass),
2624 MVT::i64);
2625 Chain =
2626 DAG.getCopyToReg(Chain, DL, ReturnAddrVirtualReg, ReturnAddrReg, Flag);
2627 Flag = Chain.getValue(1);
2628 RetOps.push_back(ReturnAddrVirtualReg);
2629 }
2630
2631 // Copy the result values into the output registers.
2632 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E;
2633 ++I, ++RealRVLocIdx) {
2634 CCValAssign &VA = RVLocs[I];
2635 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2635, __extension__ __PRETTY_FUNCTION__))
;
2636 // TODO: Partially return in registers if return values don't fit.
2637 SDValue Arg = OutVals[RealRVLocIdx];
2638
2639 // Copied from other backends.
2640 switch (VA.getLocInfo()) {
2641 case CCValAssign::Full:
2642 break;
2643 case CCValAssign::BCvt:
2644 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2645 break;
2646 case CCValAssign::SExt:
2647 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2648 break;
2649 case CCValAssign::ZExt:
2650 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2651 break;
2652 case CCValAssign::AExt:
2653 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2654 break;
2655 default:
2656 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2656)
;
2657 }
2658
2659 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2660 Flag = Chain.getValue(1);
2661 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2662 }
2663
2664 // FIXME: Does sret work properly?
2665 if (!Info->isEntryFunction()) {
2666 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2667 const MCPhysReg *I =
2668 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2669 if (I) {
2670 for (; *I; ++I) {
2671 if (AMDGPU::SReg_64RegClass.contains(*I))
2672 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2673 else if (AMDGPU::SReg_32RegClass.contains(*I))
2674 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2675 else
2676 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2676)
;
2677 }
2678 }
2679 }
2680
2681 // Update chain and glue.
2682 RetOps[0] = Chain;
2683 if (Flag.getNode())
2684 RetOps.push_back(Flag);
2685
2686 unsigned Opc = AMDGPUISD::ENDPGM;
2687 if (!IsWaveEnd) {
2688 if (IsShader)
2689 Opc = AMDGPUISD::RETURN_TO_EPILOG;
2690 else if (CallConv == CallingConv::AMDGPU_Gfx)
2691 Opc = AMDGPUISD::RET_GFX_FLAG;
2692 else
2693 Opc = AMDGPUISD::RET_FLAG;
2694 }
2695
2696 return DAG.getNode(Opc, DL, MVT::Other, RetOps);
2697}
2698
2699SDValue SITargetLowering::LowerCallResult(
2700 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2701 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2702 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool IsThisReturn,
2703 SDValue ThisVal) const {
2704 CCAssignFn *RetCC = CCAssignFnForReturn(CallConv, IsVarArg);
2705
2706 // Assign locations to each value returned by this call.
2707 SmallVector<CCValAssign, 16> RVLocs;
2708 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2709 *DAG.getContext());
2710 CCInfo.AnalyzeCallResult(Ins, RetCC);
2711
2712 // Copy all of the result registers out of their specified physreg.
2713 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2714 CCValAssign VA = RVLocs[i];
2715 SDValue Val;
2716
2717 if (VA.isRegLoc()) {
2718 Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2719 Chain = Val.getValue(1);
2720 InFlag = Val.getValue(2);
2721 } else if (VA.isMemLoc()) {
2722 report_fatal_error("TODO: return values in memory");
2723 } else
2724 llvm_unreachable("unknown argument location type")::llvm::llvm_unreachable_internal("unknown argument location type"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2724)
;
2725
2726 switch (VA.getLocInfo()) {
2727 case CCValAssign::Full:
2728 break;
2729 case CCValAssign::BCvt:
2730 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2731 break;
2732 case CCValAssign::ZExt:
2733 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2734 DAG.getValueType(VA.getValVT()));
2735 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2736 break;
2737 case CCValAssign::SExt:
2738 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2739 DAG.getValueType(VA.getValVT()));
2740 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2741 break;
2742 case CCValAssign::AExt:
2743 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2744 break;
2745 default:
2746 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2746)
;
2747 }
2748
2749 InVals.push_back(Val);
2750 }
2751
2752 return Chain;
2753}
2754
2755// Add code to pass special inputs required depending on used features separate
2756// from the explicit user arguments present in the IR.
2757void SITargetLowering::passSpecialInputs(
2758 CallLoweringInfo &CLI,
2759 CCState &CCInfo,
2760 const SIMachineFunctionInfo &Info,
2761 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
2762 SmallVectorImpl<SDValue> &MemOpChains,
2763 SDValue Chain) const {
2764 // If we don't have a call site, this was a call inserted by
2765 // legalization. These can never use special inputs.
2766 if (!CLI.CB)
2767 return;
2768
2769 SelectionDAG &DAG = CLI.DAG;
2770 const SDLoc &DL = CLI.DL;
2771
2772 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2773 const AMDGPUFunctionArgInfo &CallerArgInfo = Info.getArgInfo();
2774
2775 const AMDGPUFunctionArgInfo *CalleeArgInfo
2776 = &AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
2777 if (const Function *CalleeFunc = CLI.CB->getCalledFunction()) {
2778 auto &ArgUsageInfo =
2779 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2780 CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
2781 }
2782
2783 // TODO: Unify with private memory register handling. This is complicated by
2784 // the fact that at least in kernels, the input argument is not necessarily
2785 // in the same location as the input.
2786 static constexpr std::pair<AMDGPUFunctionArgInfo::PreloadedValue,
2787 StringLiteral> ImplicitAttrs[] = {
2788 {AMDGPUFunctionArgInfo::DISPATCH_PTR, "amdgpu-no-dispatch-ptr"},
2789 {AMDGPUFunctionArgInfo::QUEUE_PTR, "amdgpu-no-queue-ptr" },
2790 {AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR, "amdgpu-no-implicitarg-ptr"},
2791 {AMDGPUFunctionArgInfo::DISPATCH_ID, "amdgpu-no-dispatch-id"},
2792 {AMDGPUFunctionArgInfo::WORKGROUP_ID_X, "amdgpu-no-workgroup-id-x"},
2793 {AMDGPUFunctionArgInfo::WORKGROUP_ID_Y,"amdgpu-no-workgroup-id-y"},
2794 {AMDGPUFunctionArgInfo::WORKGROUP_ID_Z,"amdgpu-no-workgroup-id-z"}
2795 };
2796
2797 for (auto Attr : ImplicitAttrs) {
2798 const ArgDescriptor *OutgoingArg;
2799 const TargetRegisterClass *ArgRC;
2800 LLT ArgTy;
2801
2802 AMDGPUFunctionArgInfo::PreloadedValue InputID = Attr.first;
2803
2804 // If the callee does not use the attribute value, skip copying the value.
2805 if (CLI.CB->hasFnAttr(Attr.second))
2806 continue;
2807
2808 std::tie(OutgoingArg, ArgRC, ArgTy) =
2809 CalleeArgInfo->getPreloadedValue(InputID);
2810 if (!OutgoingArg)
2811 continue;
2812
2813 const ArgDescriptor *IncomingArg;
2814 const TargetRegisterClass *IncomingArgRC;
2815 LLT Ty;
2816 std::tie(IncomingArg, IncomingArgRC, Ty) =
2817 CallerArgInfo.getPreloadedValue(InputID);
2818 assert(IncomingArgRC == ArgRC)(static_cast <bool> (IncomingArgRC == ArgRC) ? void (0)
: __assert_fail ("IncomingArgRC == ArgRC", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2818, __extension__ __PRETTY_FUNCTION__))
;
2819
2820 // All special arguments are ints for now.
2821 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;
2822 SDValue InputReg;
2823
2824 if (IncomingArg) {
2825 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg);
2826 } else if (InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR) {
2827 // The implicit arg ptr is special because it doesn't have a corresponding
2828 // input for kernels, and is computed from the kernarg segment pointer.
2829 InputReg = getImplicitArgPtr(DAG, DL);
2830 } else {
2831 // We may have proven the input wasn't needed, although the ABI is
2832 // requiring it. We just need to allocate the register appropriately.
2833 InputReg = DAG.getUNDEF(ArgVT);
2834 }
2835
2836 if (OutgoingArg->isRegister()) {
2837 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2838 if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
2839 report_fatal_error("failed to allocate implicit input argument");
2840 } else {
2841 unsigned SpecialArgOffset =
2842 CCInfo.AllocateStack(ArgVT.getStoreSize(), Align(4));
2843 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2844 SpecialArgOffset);
2845 MemOpChains.push_back(ArgStore);
2846 }
2847 }
2848
2849 // Pack workitem IDs into a single register or pass it as is if already
2850 // packed.
2851 const ArgDescriptor *OutgoingArg;
2852 const TargetRegisterClass *ArgRC;
2853 LLT Ty;
2854
2855 std::tie(OutgoingArg, ArgRC, Ty) =
2856 CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
2857 if (!OutgoingArg)
2858 std::tie(OutgoingArg, ArgRC, Ty) =
2859 CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
2860 if (!OutgoingArg)
2861 std::tie(OutgoingArg, ArgRC, Ty) =
2862 CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
2863 if (!OutgoingArg)
2864 return;
2865
2866 const ArgDescriptor *IncomingArgX = std::get<0>(
2867 CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X));
2868 const ArgDescriptor *IncomingArgY = std::get<0>(
2869 CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y));
2870 const ArgDescriptor *IncomingArgZ = std::get<0>(
2871 CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z));
2872
2873 SDValue InputReg;
2874 SDLoc SL;
2875
2876 const bool NeedWorkItemIDX = !CLI.CB->hasFnAttr("amdgpu-no-workitem-id-x");
2877 const bool NeedWorkItemIDY = !CLI.CB->hasFnAttr("amdgpu-no-workitem-id-y");
2878 const bool NeedWorkItemIDZ = !CLI.CB->hasFnAttr("amdgpu-no-workitem-id-z");
2879
2880 // If incoming ids are not packed we need to pack them.
2881 if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo->WorkItemIDX &&
2882 NeedWorkItemIDX)
2883 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX);
2884
2885 if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo->WorkItemIDY &&
2886 NeedWorkItemIDY) {
2887 SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY);
2888 Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y,
2889 DAG.getShiftAmountConstant(10, MVT::i32, SL));
2890 InputReg = InputReg.getNode() ?
2891 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y;
2892 }
2893
2894 if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo->WorkItemIDZ &&
2895 NeedWorkItemIDZ) {
2896 SDValue Z = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgZ);
2897 Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z,
2898 DAG.getShiftAmountConstant(20, MVT::i32, SL));
2899 InputReg = InputReg.getNode() ?
2900 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Z) : Z;
2901 }
2902
2903 if (!InputReg && (NeedWorkItemIDX || NeedWorkItemIDY || NeedWorkItemIDZ)) {
2904 // Workitem ids are already packed, any of present incoming arguments
2905 // will carry all required fields.
2906 ArgDescriptor IncomingArg = ArgDescriptor::createArg(
2907 IncomingArgX ? *IncomingArgX :
2908 IncomingArgY ? *IncomingArgY :
2909 *IncomingArgZ, ~0u);
2910 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, IncomingArg);
2911 }
2912
2913 if (OutgoingArg->isRegister()) {
2914 if (InputReg)
2915 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2916
2917 CCInfo.AllocateReg(OutgoingArg->getRegister());
2918 } else {
2919 unsigned SpecialArgOffset = CCInfo.AllocateStack(4, Align(4));
2920 if (InputReg) {
2921 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2922 SpecialArgOffset);
2923 MemOpChains.push_back(ArgStore);
2924 }
2925 }
2926}
2927
2928static bool canGuaranteeTCO(CallingConv::ID CC) {
2929 return CC == CallingConv::Fast;
2930}
2931
2932/// Return true if we might ever do TCO for calls with this calling convention.
2933static bool mayTailCallThisCC(CallingConv::ID CC) {
2934 switch (CC) {
2935 case CallingConv::C:
2936 case CallingConv::AMDGPU_Gfx:
2937 return true;
2938 default:
2939 return canGuaranteeTCO(CC);
2940 }
2941}
2942
2943bool SITargetLowering::isEligibleForTailCallOptimization(
2944 SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
2945 const SmallVectorImpl<ISD::OutputArg> &Outs,
2946 const SmallVectorImpl<SDValue> &OutVals,
2947 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2948 if (!mayTailCallThisCC(CalleeCC))
2949 return false;
2950
2951 // For a divergent call target, we need to do a waterfall loop over the
2952 // possible callees which precludes us from using a simple jump.
2953 if (Callee->isDivergent())
2954 return false;
2955
2956 MachineFunction &MF = DAG.getMachineFunction();
2957 const Function &CallerF = MF.getFunction();
2958 CallingConv::ID CallerCC = CallerF.getCallingConv();
2959 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2960 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2961
2962 // Kernels aren't callable, and don't have a live in return address so it
2963 // doesn't make sense to do a tail call with entry functions.
2964 if (!CallerPreserved)
2965 return false;
2966
2967 bool CCMatch = CallerCC == CalleeCC;
2968
2969 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
2970 if (canGuaranteeTCO(CalleeCC) && CCMatch)
2971 return true;
2972 return false;
2973 }
2974
2975 // TODO: Can we handle var args?
2976 if (IsVarArg)
2977 return false;
2978
2979 for (const Argument &Arg : CallerF.args()) {
2980 if (Arg.hasByValAttr())
2981 return false;
2982 }
2983
2984 LLVMContext &Ctx = *DAG.getContext();
2985
2986 // Check that the call results are passed in the same way.
2987 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, Ctx, Ins,
2988 CCAssignFnForCall(CalleeCC, IsVarArg),
2989 CCAssignFnForCall(CallerCC, IsVarArg)))
2990 return false;
2991
2992 // The callee has to preserve all registers the caller needs to preserve.
2993 if (!CCMatch) {
2994 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2995 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2996 return false;
2997 }
2998
2999 // Nothing more to check if the callee is taking no arguments.
3000 if (Outs.empty())
3001 return true;
3002
3003 SmallVector<CCValAssign, 16> ArgLocs;
3004 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
3005
3006 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
3007
3008 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
3009 // If the stack arguments for this call do not fit into our own save area then
3010 // the call cannot be made tail.
3011 // TODO: Is this really necessary?
3012 if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
3013 return false;
3014
3015 const MachineRegisterInfo &MRI = MF.getRegInfo();
3016 return parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals);
3017}
3018
3019bool SITargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3020 if (!CI->isTailCall())
3021 return false;
3022
3023 const Function *ParentFn = CI->getParent()->getParent();
3024 if (AMDGPU::isEntryFunctionCC(ParentFn->getCallingConv()))
3025 return false;
3026 return true;
3027}
3028
3029// The wave scratch offset register is used as the global base pointer.
3030SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
3031 SmallVectorImpl<SDValue> &InVals) const {
3032 SelectionDAG &DAG = CLI.DAG;
3033 const SDLoc &DL = CLI.DL;
3034 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3035 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3036 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3037 SDValue Chain = CLI.Chain;
3038 SDValue Callee = CLI.Callee;
3039 bool &IsTailCall = CLI.IsTailCall;
3040 CallingConv::ID CallConv = CLI.CallConv;
3041 bool IsVarArg = CLI.IsVarArg;
3042 bool IsSibCall = false;
3043 bool IsThisReturn = false;
3044 MachineFunction &MF = DAG.getMachineFunction();
3045
3046 if (Callee.isUndef() || isNullConstant(Callee)) {
3047 if (!CLI.IsTailCall) {
3048 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
3049 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
3050 }
3051
3052 return Chain;
3053 }
3054
3055 if (IsVarArg) {
3056 return lowerUnhandledCall(CLI, InVals,
3057 "unsupported call to variadic function ");
3058 }
3059
3060 if (!CLI.CB)
3061 report_fatal_error("unsupported libcall legalization");
3062
3063 if (IsTailCall && MF.getTarget().Options.GuaranteedTailCallOpt) {
3064 return lowerUnhandledCall(CLI, InVals,
3065 "unsupported required tail call to function ");
3066 }
3067
3068 if (AMDGPU::isShader(CallConv)) {
3069 // Note the issue is with the CC of the called function, not of the call
3070 // itself.
3071 return lowerUnhandledCall(CLI, InVals,
3072 "unsupported call to a shader function ");
3073 }
3074
3075 if (AMDGPU::isShader(MF.getFunction().getCallingConv()) &&
3076 CallConv != CallingConv::AMDGPU_Gfx) {
3077 // Only allow calls with specific calling conventions.
3078 return lowerUnhandledCall(CLI, InVals,
3079 "unsupported calling convention for call from "
3080 "graphics shader of function ");
3081 }
3082
3083 if (IsTailCall) {
3084 IsTailCall = isEligibleForTailCallOptimization(
3085 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
3086 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) {
3087 report_fatal_error("failed to perform tail call elimination on a call "
3088 "site marked musttail");
3089 }
3090
3091 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
3092
3093 // A sibling call is one where we're under the usual C ABI and not planning
3094 // to change that but can still do a tail call:
3095 if (!TailCallOpt && IsTailCall)
3096 IsSibCall = true;
3097
3098 if (IsTailCall)
3099 ++NumTailCalls;
3100 }
3101
3102 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
3103 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3104 SmallVector<SDValue, 8> MemOpChains;
3105
3106 // Analyze operands of the call, assigning locations to each operand.
3107 SmallVector<CCValAssign, 16> ArgLocs;
3108 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
3109 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, IsVarArg);
3110
3111 if (AMDGPUTargetMachine::EnableFixedFunctionABI &&
3112 CallConv != CallingConv::AMDGPU_Gfx) {
3113 // With a fixed ABI, allocate fixed registers before user arguments.
3114 passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
3115 }
3116
3117 CCInfo.AnalyzeCallOperands(Outs, AssignFn);
3118
3119 // Get a count of how many bytes are to be pushed on the stack.
3120 unsigned NumBytes = CCInfo.getNextStackOffset();
3121
3122 if (IsSibCall) {
3123 // Since we're not changing the ABI to make this a tail call, the memory
3124 // operands are already available in the caller's incoming argument space.
3125 NumBytes = 0;
3126 }
3127
3128 // FPDiff is the byte offset of the call's argument area from the callee's.
3129 // Stores to callee stack arguments will be placed in FixedStackSlots offset
3130 // by this amount for a tail call. In a sibling call it must be 0 because the
3131 // caller will deallocate the entire stack and the callee still expects its
3132 // arguments to begin at SP+0. Completely unused for non-tail calls.
3133 int32_t FPDiff = 0;
3134 MachineFrameInfo &MFI = MF.getFrameInfo();
3135
3136 // Adjust the stack pointer for the new arguments...
3137 // These operations are automatically eliminated by the prolog/epilog pass
3138 if (!IsSibCall) {
3139 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
3140
3141 if (!Subtarget->enableFlatScratch()) {
3142 SmallVector<SDValue, 4> CopyFromChains;
3143
3144 // In the HSA case, this should be an identity copy.
3145 SDValue ScratchRSrcReg
3146 = DAG.getCopyFromReg(Chain, DL, Info->getScratchRSrcReg(), MVT::v4i32);
3147 RegsToPass.emplace_back(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
3148 CopyFromChains.push_back(ScratchRSrcReg.getValue(1));
3149 Chain = DAG.getTokenFactor(DL, CopyFromChains);
3150 }
3151 }
3152
3153 MVT PtrVT = MVT::i32;
3154
3155 // Walk the register/memloc assignments, inserting copies/loads.
3156 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3157 CCValAssign &VA = ArgLocs[i];
3158 SDValue Arg = OutVals[i];
3159
3160 // Promote the value if needed.
3161 switch (VA.getLocInfo()) {
3162 case CCValAssign::Full:
3163 break;
3164 case CCValAssign::BCvt:
3165 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3166 break;
3167 case CCValAssign::ZExt:
3168 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3169 break;
3170 case CCValAssign::SExt:
3171 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
3172 break;
3173 case CCValAssign::AExt:
3174 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
3175 break;
3176 case CCValAssign::FPExt:
3177 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
3178 break;
3179 default:
3180 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3180)
;
3181 }
3182
3183 if (VA.isRegLoc()) {
3184 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3185 } else {
3186 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3186, __extension__ __PRETTY_FUNCTION__))
;
3187
3188 SDValue DstAddr;
3189 MachinePointerInfo DstInfo;
3190
3191 unsigned LocMemOffset = VA.getLocMemOffset();
3192 int32_t Offset = LocMemOffset;
3193
3194 SDValue PtrOff = DAG.getConstant(Offset, DL, PtrVT);
3195 MaybeAlign Alignment;
3196
3197 if (IsTailCall) {
3198 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3199 unsigned OpSize = Flags.isByVal() ?
3200 Flags.getByValSize() : VA.getValVT().getStoreSize();
3201
3202 // FIXME: We can have better than the minimum byval required alignment.
3203 Alignment =
3204 Flags.isByVal()
3205 ? Flags.getNonZeroByValAlign()
3206 : commonAlignment(Subtarget->getStackAlignment(), Offset);
3207
3208 Offset = Offset + FPDiff;
3209 int FI = MFI.CreateFixedObject(OpSize, Offset, true);
3210
3211 DstAddr = DAG.getFrameIndex(FI, PtrVT);
3212 DstInfo = MachinePointerInfo::getFixedStack(MF, FI);
3213
3214 // Make sure any stack arguments overlapping with where we're storing
3215 // are loaded before this eventual operation. Otherwise they'll be
3216 // clobbered.
3217
3218 // FIXME: Why is this really necessary? This seems to just result in a
3219 // lot of code to copy the stack and write them back to the same
3220 // locations, which are supposed to be immutable?
3221 Chain = addTokenForArgument(Chain, DAG, MFI, FI);
3222 } else {
3223 // Stores to the argument stack area are relative to the stack pointer.
3224 SDValue SP = DAG.getCopyFromReg(Chain, DL, Info->getStackPtrOffsetReg(),
3225 MVT::i32);
3226 DstAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, SP, PtrOff);
3227 DstInfo = MachinePointerInfo::getStack(MF, LocMemOffset);
3228 Alignment =
3229 commonAlignment(Subtarget->getStackAlignment(), LocMemOffset);
3230 }
3231
3232 if (Outs[i].Flags.isByVal()) {
3233 SDValue SizeNode =
3234 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32);
3235 SDValue Cpy =
3236 DAG.getMemcpy(Chain, DL, DstAddr, Arg, SizeNode,
3237 Outs[i].Flags.getNonZeroByValAlign(),
3238 /*isVol = */ false, /*AlwaysInline = */ true,
3239 /*isTailCall = */ false, DstInfo,
3240 MachinePointerInfo(AMDGPUAS::PRIVATE_ADDRESS));
3241
3242 MemOpChains.push_back(Cpy);
3243 } else {
3244 SDValue Store =
3245 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, Alignment);
3246 MemOpChains.push_back(Store);
3247 }
3248 }
3249 }
3250
3251 if (!AMDGPUTargetMachine::EnableFixedFunctionABI &&
3252 CallConv != CallingConv::AMDGPU_Gfx) {
3253 // Copy special input registers after user input arguments.
3254 passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
3255 }
3256
3257 if (!MemOpChains.empty())
3258 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3259
3260 // Build a sequence of copy-to-reg nodes chained together with token chain
3261 // and flag operands which copy the outgoing args into the appropriate regs.
3262 SDValue InFlag;
3263 for (auto &RegToPass : RegsToPass) {
3264 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
3265 RegToPass.second, InFlag);
3266 InFlag = Chain.getValue(1);
3267 }
3268
3269
3270 SDValue PhysReturnAddrReg;
3271 if (IsTailCall) {
3272 // Since the return is being combined with the call, we need to pass on the
3273 // return address.
3274
3275 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
3276 SDValue ReturnAddrReg = CreateLiveInRegister(
3277 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
3278
3279 PhysReturnAddrReg = DAG.getRegister(TRI->getReturnAddressReg(MF),
3280 MVT::i64);
3281 Chain = DAG.getCopyToReg(Chain, DL, PhysReturnAddrReg, ReturnAddrReg, InFlag);
3282 InFlag = Chain.getValue(1);
3283 }
3284
3285 // We don't usually want to end the call-sequence here because we would tidy
3286 // the frame up *after* the call, however in the ABI-changing tail-call case
3287 // we've carefully laid out the parameters so that when sp is reset they'll be
3288 // in the correct location.
3289 if (IsTailCall && !IsSibCall) {
3290 Chain = DAG.getCALLSEQ_END(Chain,
3291 DAG.getTargetConstant(NumBytes, DL, MVT::i32),
3292 DAG.getTargetConstant(0, DL, MVT::i32),
3293 InFlag, DL);
3294 InFlag = Chain.getValue(1);
3295 }
3296
3297 std::vector<SDValue> Ops;
3298 Ops.push_back(Chain);
3299 Ops.push_back(Callee);
3300 // Add a redundant copy of the callee global which will not be legalized, as
3301 // we need direct access to the callee later.
3302 if (GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(Callee)) {
3303 const GlobalValue *GV = GSD->getGlobal();
3304 Ops.push_back(DAG.getTargetGlobalAddress(GV, DL, MVT::i64));
3305 } else {
3306 Ops.push_back(DAG.getTargetConstant(0, DL, MVT::i64));
3307 }
3308
3309 if (IsTailCall) {
3310 // Each tail call may have to adjust the stack by a different amount, so
3311 // this information must travel along with the operation for eventual
3312 // consumption by emitEpilogue.
3313 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
3314
3315 Ops.push_back(PhysReturnAddrReg);
3316 }
3317
3318 // Add argument registers to the end of the list so that they are known live
3319 // into the call.
3320 for (auto &RegToPass : RegsToPass) {
3321 Ops.push_back(DAG.getRegister(RegToPass.first,
3322 RegToPass.second.getValueType()));
3323 }
3324
3325 // Add a register mask operand representing the call-preserved registers.
3326
3327 auto *TRI = static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
3328 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3329 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3329, __extension__ __PRETTY_FUNCTION__))
;
3330 Ops.push_back(DAG.getRegisterMask(Mask));
3331
3332 if (InFlag.getNode())
3333 Ops.push_back(InFlag);
3334
3335 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3336
3337 // If we're doing a tall call, use a TC_RETURN here rather than an
3338 // actual call instruction.
3339 if (IsTailCall) {
3340 MFI.setHasTailCall();
3341 return DAG.getNode(AMDGPUISD::TC_RETURN, DL, NodeTys, Ops);
3342 }
3343
3344 // Returns a chain and a flag for retval copy to use.
3345 SDValue Call = DAG.getNode(AMDGPUISD::CALL, DL, NodeTys, Ops);
3346 Chain = Call.getValue(0);
3347 InFlag = Call.getValue(1);
3348
3349 uint64_t CalleePopBytes = NumBytes;
3350 Chain = DAG.getCALLSEQ_END(Chain, DAG.getTargetConstant(0, DL, MVT::i32),
3351 DAG.getTargetConstant(CalleePopBytes, DL, MVT::i32),
3352 InFlag, DL);
3353 if (!Ins.empty())
3354 InFlag = Chain.getValue(1);
3355
3356 // Handle result values, copying them out of physregs into vregs that we
3357 // return.
3358 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3359 InVals, IsThisReturn,
3360 IsThisReturn ? OutVals[0] : SDValue());
3361}
3362
3363// This is identical to the default implementation in ExpandDYNAMIC_STACKALLOC,
3364// except for applying the wave size scale to the increment amount.
3365SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(
3366 SDValue Op, SelectionDAG &DAG) const {
3367 const MachineFunction &MF = DAG.getMachineFunction();
3368 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
3369
3370 SDLoc dl(Op);
3371 EVT VT = Op.getValueType();
3372 SDValue Tmp1 = Op;
3373 SDValue Tmp2 = Op.getValue(1);
3374 SDValue Tmp3 = Op.getOperand(2);
3375 SDValue Chain = Tmp1.getOperand(0);
3376
3377 Register SPReg = Info->getStackPtrOffsetReg();
3378
3379 // Chain the dynamic stack allocation so that it doesn't modify the stack
3380 // pointer when other instructions are using the stack.
3381 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
3382
3383 SDValue Size = Tmp2.getOperand(1);
3384 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
3385 Chain = SP.getValue(1);
3386 MaybeAlign Alignment = cast<ConstantSDNode>(Tmp3)->getMaybeAlignValue();
3387 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
3388 const TargetFrameLowering *TFL = ST.getFrameLowering();
3389 unsigned Opc =
3390 TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp ?
3391 ISD::ADD : ISD::SUB;
3392
3393 SDValue ScaledSize = DAG.getNode(
3394 ISD::SHL, dl, VT, Size,
3395 DAG.getConstant(ST.getWavefrontSizeLog2(), dl, MVT::i32));
3396
3397 Align StackAlign = TFL->getStackAlign();
3398 Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value
3399 if (Alignment && *Alignment > StackAlign) {
3400 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
3401 DAG.getConstant(-(uint64_t)Alignment->value()
3402 << ST.getWavefrontSizeLog2(),
3403 dl, VT));
3404 }
3405
3406 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
3407 Tmp2 = DAG.getCALLSEQ_END(
3408 Chain, DAG.getIntPtrConstant(0, dl, true),
3409 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
3410
3411 return DAG.getMergeValues({Tmp1, Tmp2}, dl);
3412}
3413
3414SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3415 SelectionDAG &DAG) const {
3416 // We only handle constant sizes here to allow non-entry block, static sized
3417 // allocas. A truly dynamic value is more difficult to support because we
3418 // don't know if the size value is uniform or not. If the size isn't uniform,
3419 // we would need to do a wave reduction to get the maximum size to know how
3420 // much to increment the uniform stack pointer.
3421 SDValue Size = Op.getOperand(1);
3422 if (isa<ConstantSDNode>(Size))
3423 return lowerDYNAMIC_STACKALLOCImpl(Op, DAG); // Use "generic" expansion.
3424
3425 return AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(Op, DAG);
3426}
3427
3428Register SITargetLowering::getRegisterByName(const char* RegName, LLT VT,
3429 const MachineFunction &MF) const {
3430 Register Reg = StringSwitch<Register>(RegName)
3431 .Case("m0", AMDGPU::M0)
3432 .Case("exec", AMDGPU::EXEC)
3433 .Case("exec_lo", AMDGPU::EXEC_LO)
3434 .Case("exec_hi", AMDGPU::EXEC_HI)
3435 .Case("flat_scratch", AMDGPU::FLAT_SCR)
3436 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
3437 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
3438 .Default(Register());
3439
3440 if (Reg == AMDGPU::NoRegister) {
3441 report_fatal_error(Twine("invalid register name \""
3442 + StringRef(RegName) + "\"."));
3443
3444 }
3445
3446 if (!Subtarget->hasFlatScrRegister() &&
3447 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
3448 report_fatal_error(Twine("invalid register \""
3449 + StringRef(RegName) + "\" for subtarget."));
3450 }
3451
3452 switch (Reg) {
3453 case AMDGPU::M0:
3454 case AMDGPU::EXEC_LO:
3455 case AMDGPU::EXEC_HI:
3456 case AMDGPU::FLAT_SCR_LO:
3457 case AMDGPU::FLAT_SCR_HI:
3458 if (VT.getSizeInBits() == 32)
3459 return Reg;
3460 break;
3461 case AMDGPU::EXEC:
3462 case AMDGPU::FLAT_SCR:
3463 if (VT.getSizeInBits() == 64)
3464 return Reg;
3465 break;
3466 default:
3467 llvm_unreachable("missing register type checking")::llvm::llvm_unreachable_internal("missing register type checking"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3467)
;
3468 }
3469
3470 report_fatal_error(Twine("invalid type for register \""
3471 + StringRef(RegName) + "\"."));
3472}
3473
3474// If kill is not the last instruction, split the block so kill is always a
3475// proper terminator.
3476MachineBasicBlock *
3477SITargetLowering::splitKillBlock(MachineInstr &MI,
3478 MachineBasicBlock *BB) const {
3479 MachineBasicBlock *SplitBB = BB->splitAt(MI, false /*UpdateLiveIns*/);
3480 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3481 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
3482 return SplitBB;
3483}
3484
3485// Split block \p MBB at \p MI, as to insert a loop. If \p InstInLoop is true,
3486// \p MI will be the only instruction in the loop body block. Otherwise, it will
3487// be the first instruction in the remainder block.
3488//
3489/// \returns { LoopBody, Remainder }
3490static std::pair<MachineBasicBlock *, MachineBasicBlock *>
3491splitBlockForLoop(MachineInstr &MI, MachineBasicBlock &MBB, bool InstInLoop) {
3492 MachineFunction *MF = MBB.getParent();
3493 MachineBasicBlock::iterator I(&MI);
3494
3495 // To insert the loop we need to split the block. Move everything after this
3496 // point to a new block, and insert a new empty block between the two.
3497 MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
3498 MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
3499 MachineFunction::iterator MBBI(MBB);
3500 ++MBBI;
3501
3502 MF->insert(MBBI, LoopBB);
3503 MF->insert(MBBI, RemainderBB);
3504
3505 LoopBB->addSuccessor(LoopBB);
3506 LoopBB->addSuccessor(RemainderBB);
3507
3508 // Move the rest of the block into a new block.
3509 RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
3510
3511 if (InstInLoop) {
3512 auto Next = std::next(I);
3513
3514 // Move instruction to loop body.
3515 LoopBB->splice(LoopBB->begin(), &MBB, I, Next);
3516
3517 // Move the rest of the block.
3518 RemainderBB->splice(RemainderBB->begin(), &MBB, Next, MBB.end());
3519 } else {
3520 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
3521 }
3522
3523 MBB.addSuccessor(LoopBB);
3524
3525 return std::make_pair(LoopBB, RemainderBB);
3526}
3527
3528/// Insert \p MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
3529void SITargetLowering::bundleInstWithWaitcnt(MachineInstr &MI) const {
3530 MachineBasicBlock *MBB = MI.getParent();
3531 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3532 auto I = MI.getIterator();
3533 auto E = std::next(I);
3534
3535 BuildMI(*MBB, E, MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
3536 .addImm(0);
3537
3538 MIBundleBuilder Bundler(*MBB, I, E);
3539 finalizeBundle(*MBB, Bundler.begin());
3540}
3541
3542MachineBasicBlock *
3543SITargetLowering::emitGWSMemViolTestLoop(MachineInstr &MI,
3544 MachineBasicBlock *BB) const {
3545 const DebugLoc &DL = MI.getDebugLoc();
3546
3547 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3548
3549 MachineBasicBlock *LoopBB;
3550 MachineBasicBlock *RemainderBB;
3551 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3552
3553 // Apparently kill flags are only valid if the def is in the same block?
3554 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0))
3555 Src->setIsKill(false);
3556
3557 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, *BB, true);
3558
3559 MachineBasicBlock::iterator I = LoopBB->end();
3560
3561 const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg(
3562 AMDGPU::Hwreg::ID_TRAPSTS, AMDGPU::Hwreg::OFFSET_MEM_VIOL, 1);
3563
3564 // Clear TRAP_STS.MEM_VIOL
3565 BuildMI(*LoopBB, LoopBB->begin(), DL, TII->get(AMDGPU::S_SETREG_IMM32_B32))
3566 .addImm(0)
3567 .addImm(EncodedReg);
3568
3569 bundleInstWithWaitcnt(MI);
3570
3571 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3572
3573 // Load and check TRAP_STS.MEM_VIOL
3574 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), Reg)
3575 .addImm(EncodedReg);
3576
3577 // FIXME: Do we need to use an isel pseudo that may clobber scc?
3578 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32))
3579 .addReg(Reg, RegState::Kill)
3580 .addImm(0);
3581 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3582 .addMBB(LoopBB);
3583
3584 return RemainderBB;
3585}
3586
3587// Do a v_movrels_b32 or v_movreld_b32 for each unique value of \p IdxReg in the
3588// wavefront. If the value is uniform and just happens to be in a VGPR, this
3589// will only do one iteration. In the worst case, this will loop 64 times.
3590//
3591// TODO: Just use v_readlane_b32 if we know the VGPR has a uniform value.
3592static MachineBasicBlock::iterator
3593emitLoadM0FromVGPRLoop(const SIInstrInfo *TII, MachineRegisterInfo &MRI,
3594 MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB,
3595 const DebugLoc &DL, const MachineOperand &Idx,
3596 unsigned InitReg, unsigned ResultReg, unsigned PhiReg,
3597 unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode,
3598 Register &SGPRIdxReg) {
3599
3600 MachineFunction *MF = OrigBB.getParent();
3601 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3602 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3603 MachineBasicBlock::iterator I = LoopBB.begin();
3604
3605 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3606 Register PhiExec = MRI.createVirtualRegister(BoolRC);
3607 Register NewExec = MRI.createVirtualRegister(BoolRC);
3608 Register CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3609 Register CondReg = MRI.createVirtualRegister(BoolRC);
3610
3611 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
3612 .addReg(InitReg)
3613 .addMBB(&OrigBB)
3614 .addReg(ResultReg)
3615 .addMBB(&LoopBB);
3616
3617 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
3618 .addReg(InitSaveExecReg)
3619 .addMBB(&OrigBB)
3620 .addReg(NewExec)
3621 .addMBB(&LoopBB);
3622
3623 // Read the next variant <- also loop target.
3624 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
3625 .addReg(Idx.getReg(), getUndefRegState(Idx.isUndef()));
3626
3627 // Compare the just read M0 value to all possible Idx values.
3628 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
3629 .addReg(CurrentIdxReg)
3630 .addReg(Idx.getReg(), 0, Idx.getSubReg());
3631
3632 // Update EXEC, save the original EXEC value to VCC.
3633 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
3634 : AMDGPU::S_AND_SAVEEXEC_B64),
3635 NewExec)
3636 .addReg(CondReg, RegState::Kill);
3637
3638 MRI.setSimpleHint(NewExec, CondReg);
3639
3640 if (UseGPRIdxMode) {
3641 if (Offset == 0) {
3642 SGPRIdxReg = CurrentIdxReg;
3643 } else {
3644 SGPRIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3645 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), SGPRIdxReg)
3646 .addReg(CurrentIdxReg, RegState::Kill)
3647 .addImm(Offset);
3648 }
3649 } else {
3650 // Move index from VCC into M0
3651 if (Offset == 0) {
3652 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3653 .addReg(CurrentIdxReg, RegState::Kill);
3654 } else {
3655 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3656 .addReg(CurrentIdxReg, RegState::Kill)
3657 .addImm(Offset);
3658 }
3659 }
3660
3661 // Update EXEC, switch all done bits to 0 and all todo bits to 1.
3662 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3663 MachineInstr *InsertPt =
3664 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
3665 : AMDGPU::S_XOR_B64_term), Exec)
3666 .addReg(Exec)
3667 .addReg(NewExec);
3668
3669 // XXX - s_xor_b64 sets scc to 1 if the result is nonzero, so can we use
3670 // s_cbranch_scc0?
3671
3672 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover.
3673 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
3674 .addMBB(&LoopBB);
3675
3676 return InsertPt->getIterator();
3677}
3678
3679// This has slightly sub-optimal regalloc when the source vector is killed by
3680// the read. The register allocator does not understand that the kill is
3681// per-workitem, so is kept alive for the whole loop so we end up not re-using a
3682// subregister from it, using 1 more VGPR than necessary. This was saved when
3683// this was expanded after register allocation.
3684static MachineBasicBlock::iterator
3685loadM0FromVGPR(const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineInstr &MI,
3686 unsigned InitResultReg, unsigned PhiReg, int Offset,
3687 bool UseGPRIdxMode, Register &SGPRIdxReg) {
3688 MachineFunction *MF = MBB.getParent();
3689 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3690 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3691 MachineRegisterInfo &MRI = MF->getRegInfo();
3692 const DebugLoc &DL = MI.getDebugLoc();
3693 MachineBasicBlock::iterator I(&MI);
3694
3695 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3696 Register DstReg = MI.getOperand(0).getReg();
3697 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
3698 Register TmpExec = MRI.createVirtualRegister(BoolXExecRC);
3699 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3700 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
3701
3702 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
3703
3704 // Save the EXEC mask
3705 BuildMI(MBB, I, DL, TII->get(MovExecOpc), SaveExec)
3706 .addReg(Exec);
3707
3708 MachineBasicBlock *LoopBB;
3709 MachineBasicBlock *RemainderBB;
3710 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, MBB, false);
3711
3712 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3713
3714 auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
3715 InitResultReg, DstReg, PhiReg, TmpExec,
3716 Offset, UseGPRIdxMode, SGPRIdxReg);
3717
3718 MachineBasicBlock* LandingPad = MF->CreateMachineBasicBlock();
3719 MachineFunction::iterator MBBI(LoopBB);
3720 ++MBBI;
3721 MF->insert(MBBI, LandingPad);
3722 LoopBB->removeSuccessor(RemainderBB);
3723 LandingPad->addSuccessor(RemainderBB);
3724 LoopBB->addSuccessor(LandingPad);
3725 MachineBasicBlock::iterator First = LandingPad->begin();
3726 BuildMI(*LandingPad, First, DL, TII->get(MovExecOpc), Exec)
3727 .addReg(SaveExec);
3728
3729 return InsPt;
3730}
3731
3732// Returns subreg index, offset
3733static std::pair<unsigned, int>
3734computeIndirectRegAndOffset(const SIRegisterInfo &TRI,
3735 const TargetRegisterClass *SuperRC,
3736 unsigned VecReg,
3737 int Offset) {
3738 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
3739
3740 // Skip out of bounds offsets, or else we would end up using an undefined
3741 // register.
3742 if (Offset >= NumElts || Offset < 0)
3743 return std::make_pair(AMDGPU::sub0, Offset);
3744
3745 return std::make_pair(SIRegisterInfo::getSubRegFromChannel(Offset), 0);
3746}
3747
3748static void setM0ToIndexFromSGPR(const SIInstrInfo *TII,
3749 MachineRegisterInfo &MRI, MachineInstr &MI,
3750 int Offset) {
3751 MachineBasicBlock *MBB = MI.getParent();
3752 const DebugLoc &DL = MI.getDebugLoc();
3753 MachineBasicBlock::iterator I(&MI);
3754
3755 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3756
3757 assert(Idx->getReg() != AMDGPU::NoRegister)(static_cast <bool> (Idx->getReg() != AMDGPU::NoRegister
) ? void (0) : __assert_fail ("Idx->getReg() != AMDGPU::NoRegister"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3757, __extension__ __PRETTY_FUNCTION__))
;
3758
3759 if (Offset == 0) {
3760 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0).add(*Idx);
3761 } else {
3762 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3763 .add(*Idx)
3764 .addImm(Offset);
3765 }
3766}
3767
3768static Register getIndirectSGPRIdx(const SIInstrInfo *TII,
3769 MachineRegisterInfo &MRI, MachineInstr &MI,
3770 int Offset) {
3771 MachineBasicBlock *MBB = MI.getParent();
3772 const DebugLoc &DL = MI.getDebugLoc();
3773 MachineBasicBlock::iterator I(&MI);
3774
3775 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3776
3777 if (Offset == 0)
3778 return Idx->getReg();
3779
3780 Register Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3781 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
3782 .add(*Idx)
3783 .addImm(Offset);
3784 return Tmp;
3785}
3786
3787static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
3788 MachineBasicBlock &MBB,
3789 const GCNSubtarget &ST) {
3790 const SIInstrInfo *TII = ST.getInstrInfo();
3791 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3792 MachineFunction *MF = MBB.getParent();
3793 MachineRegisterInfo &MRI = MF->getRegInfo();
3794
3795 Register Dst = MI.getOperand(0).getReg();
3796 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3797 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
3798 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3799
3800 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3801 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3802
3803 unsigned SubReg;
3804 std::tie(SubReg, Offset)
3805 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
3806
3807 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3808
3809 // Check for a SGPR index.
3810 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) {
3811 MachineBasicBlock::iterator I(&MI);
3812 const DebugLoc &DL = MI.getDebugLoc();
3813
3814 if (UseGPRIdxMode) {
3815 // TODO: Look at the uses to avoid the copy. This may require rescheduling
3816 // to avoid interfering with other uses, so probably requires a new
3817 // optimization pass.
3818 Register Idx = getIndirectSGPRIdx(TII, MRI, MI, Offset);
3819
3820 const MCInstrDesc &GPRIDXDesc =
3821 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true);
3822 BuildMI(MBB, I, DL, GPRIDXDesc, Dst)
3823 .addReg(SrcReg)
3824 .addReg(Idx)
3825 .addImm(SubReg);
3826 } else {
3827 setM0ToIndexFromSGPR(TII, MRI, MI, Offset);
3828
3829 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3830 .addReg(SrcReg, 0, SubReg)
3831 .addReg(SrcReg, RegState::Implicit);
3832 }
3833
3834 MI.eraseFromParent();
3835
3836 return &MBB;
3837 }
3838
3839 // Control flow needs to be inserted if indexing with a VGPR.
3840 const DebugLoc &DL = MI.getDebugLoc();
3841 MachineBasicBlock::iterator I(&MI);
3842
3843 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3844 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3845
3846 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3847
3848 Register SGPRIdxReg;
3849 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset,
3850 UseGPRIdxMode, SGPRIdxReg);
3851
3852 MachineBasicBlock *LoopBB = InsPt->getParent();
3853
3854 if (UseGPRIdxMode) {
3855 const MCInstrDesc &GPRIDXDesc =
3856 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true);
3857
3858 BuildMI(*LoopBB, InsPt, DL, GPRIDXDesc, Dst)
3859 .addReg(SrcReg)
3860 .addReg(SGPRIdxReg)
3861 .addImm(SubReg);
3862 } else {
3863 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3864 .addReg(SrcReg, 0, SubReg)
3865 .addReg(SrcReg, RegState::Implicit);
3866 }
3867
3868 MI.eraseFromParent();
3869
3870 return LoopBB;
3871}
3872
3873static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
3874 MachineBasicBlock &MBB,
3875 const GCNSubtarget &ST) {
3876 const SIInstrInfo *TII = ST.getInstrInfo();
3877 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3878 MachineFunction *MF = MBB.getParent();
3879 MachineRegisterInfo &MRI = MF->getRegInfo();
3880
3881 Register Dst = MI.getOperand(0).getReg();
3882 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
3883 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3884 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
3885 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3886 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3887 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3888
3889 // This can be an immediate, but will be folded later.
3890 assert(Val->getReg())(static_cast <bool> (Val->getReg()) ? void (0) : __assert_fail
("Val->getReg()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3890, __extension__ __PRETTY_FUNCTION__))
;
3891
3892 unsigned SubReg;
3893 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
3894 SrcVec->getReg(),
3895 Offset);
3896 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3897
3898 if (Idx->getReg() == AMDGPU::NoRegister) {
3899 MachineBasicBlock::iterator I(&MI);
3900 const DebugLoc &DL = MI.getDebugLoc();
3901
3902 assert(Offset == 0)(static_cast <bool> (Offset == 0) ? void (0) : __assert_fail
("Offset == 0", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3902, __extension__ __PRETTY_FUNCTION__))
;
3903
3904 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
3905 .add(*SrcVec)
3906 .add(*Val)
3907 .addImm(SubReg);
3908
3909 MI.eraseFromParent();
3910 return &MBB;
3911 }
3912
3913 // Check for a SGPR index.
3914 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) {
3915 MachineBasicBlock::iterator I(&MI);
3916 const DebugLoc &DL = MI.getDebugLoc();
3917
3918 if (UseGPRIdxMode) {
3919 Register Idx = getIndirectSGPRIdx(TII, MRI, MI, Offset);
3920
3921 const MCInstrDesc &GPRIDXDesc =
3922 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false);
3923 BuildMI(MBB, I, DL, GPRIDXDesc, Dst)
3924 .addReg(SrcVec->getReg())
3925 .add(*Val)
3926 .addReg(Idx)
3927 .addImm(SubReg);
3928 } else {
3929 setM0ToIndexFromSGPR(TII, MRI, MI, Offset);
3930
3931 const MCInstrDesc &MovRelDesc = TII->getIndirectRegWriteMovRelPseudo(
3932 TRI.getRegSizeInBits(*VecRC), 32, false);
3933 BuildMI(MBB, I, DL, MovRelDesc, Dst)
3934 .addReg(SrcVec->getReg())
3935 .add(*Val)
3936 .addImm(SubReg);
3937 }
3938 MI.eraseFromParent();
3939 return &MBB;
3940 }
3941
3942 // Control flow needs to be inserted if indexing with a VGPR.
3943 if (Val->isReg())
3944 MRI.clearKillFlags(Val->getReg());
3945
3946 const DebugLoc &DL = MI.getDebugLoc();
3947
3948 Register PhiReg = MRI.createVirtualRegister(VecRC);
3949
3950 Register SGPRIdxReg;
3951 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset,
3952 UseGPRIdxMode, SGPRIdxReg);
3953 MachineBasicBlock *LoopBB = InsPt->getParent();
3954
3955 if (UseGPRIdxMode) {
3956 const MCInstrDesc &GPRIDXDesc =
3957 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false);
3958
3959 BuildMI(*LoopBB, InsPt, DL, GPRIDXDesc, Dst)
3960 .addReg(PhiReg)
3961 .add(*Val)
3962 .addReg(SGPRIdxReg)
3963 .addImm(AMDGPU::sub0);
3964 } else {
3965 const MCInstrDesc &MovRelDesc = TII->getIndirectRegWriteMovRelPseudo(
3966 TRI.getRegSizeInBits(*VecRC), 32, false);
3967 BuildMI(*LoopBB, InsPt, DL, MovRelDesc, Dst)
3968 .addReg(PhiReg)
3969 .add(*Val)
3970 .addImm(AMDGPU::sub0);
3971 }
3972
3973 MI.eraseFromParent();
3974 return LoopBB;
3975}
3976
3977MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
3978 MachineInstr &MI, MachineBasicBlock *BB) const {
3979
3980 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3981 MachineFunction *MF = BB->getParent();
3982 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
3983
3984 switch (MI.getOpcode()) {
3985 case AMDGPU::S_UADDO_PSEUDO:
3986 case AMDGPU::S_USUBO_PSEUDO: {
3987 const DebugLoc &DL = MI.getDebugLoc();
3988 MachineOperand &Dest0 = MI.getOperand(0);
3989 MachineOperand &Dest1 = MI.getOperand(1);
3990 MachineOperand &Src0 = MI.getOperand(2);
3991 MachineOperand &Src1 = MI.getOperand(3);
3992
3993 unsigned Opc = (MI.getOpcode() == AMDGPU::S_UADDO_PSEUDO)
3994 ? AMDGPU::S_ADD_I32
3995 : AMDGPU::S_SUB_I32;
3996 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1);
3997
3998 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CSELECT_B64), Dest1.getReg())
3999 .addImm(1)
4000 .addImm(0);
4001
4002 MI.eraseFromParent();
4003 return BB;
4004 }
4005 case AMDGPU::S_ADD_U64_PSEUDO:
4006 case AMDGPU::S_SUB_U64_PSEUDO: {
4007 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4008 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4009 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4010 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
4011 const DebugLoc &DL = MI.getDebugLoc();
4012
4013 MachineOperand &Dest = MI.getOperand(0);
4014 MachineOperand &Src0 = MI.getOperand(1);
4015 MachineOperand &Src1 = MI.getOperand(2);
4016
4017 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4018 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4019
4020 MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(
4021 MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
4022 MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(
4023 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
4024
4025 MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(
4026 MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
4027 MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(
4028 MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
4029
4030 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
4031
4032 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
4033 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
4034 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0).add(Src0Sub0).add(Src1Sub0);
4035 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1).add(Src0Sub1).add(Src1Sub1);
4036 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
4037 .addReg(DestSub0)
4038 .addImm(AMDGPU::sub0)
4039 .addReg(DestSub1)
4040 .addImm(AMDGPU::sub1);
4041 MI.eraseFromParent();
4042 return BB;
4043 }
4044 case AMDGPU::V_ADD_U64_PSEUDO:
4045 case AMDGPU::V_SUB_U64_PSEUDO: {
4046 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4047 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4048 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4049 const DebugLoc &DL = MI.getDebugLoc();
4050
4051 bool IsAdd = (MI.getOpcode() == AMDGPU::V_ADD_U64_PSEUDO);
4052
4053 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4054
4055 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4056 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4057
4058 Register CarryReg = MRI.createVirtualRegister(CarryRC);
4059 Register DeadCarryReg = MRI.createVirtualRegister(CarryRC);
4060
4061 MachineOperand &Dest = MI.getOperand(0);
4062 MachineOperand &Src0 = MI.getOperand(1);
4063 MachineOperand &Src1 = MI.getOperand(2);
4064
4065 const TargetRegisterClass *Src0RC = Src0.isReg()
4066 ? MRI.getRegClass(Src0.getReg())
4067 : &AMDGPU::VReg_64RegClass;
4068 const TargetRegisterClass *Src1RC = Src1.isReg()
4069 ? MRI.getRegClass(Src1.getReg())
4070 : &AMDGPU::VReg_64RegClass;
4071
4072 const TargetRegisterClass *Src0SubRC =
4073 TRI->getSubRegClass(Src0RC, AMDGPU::sub0);
4074 const TargetRegisterClass *Src1SubRC =
4075 TRI->getSubRegClass(Src1RC, AMDGPU::sub1);
4076
4077 MachineOperand SrcReg0Sub0 = TII->buildExtractSubRegOrImm(
4078 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
4079 MachineOperand SrcReg1Sub0 = TII->buildExtractSubRegOrImm(
4080 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
4081
4082 MachineOperand SrcReg0Sub1 = TII->buildExtractSubRegOrImm(
4083 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
4084 MachineOperand SrcReg1Sub1 = TII->buildExtractSubRegOrImm(
4085 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
4086
4087 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64;
4088 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
4089 .addReg(CarryReg, RegState::Define)
4090 .add(SrcReg0Sub0)
4091 .add(SrcReg1Sub0)
4092 .addImm(0); // clamp bit
4093
4094 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
4095 MachineInstr *HiHalf =
4096 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
4097 .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
4098 .add(SrcReg0Sub1)
4099 .add(SrcReg1Sub1)
4100 .addReg(CarryReg, RegState::Kill)
4101 .addImm(0); // clamp bit
4102
4103 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
4104 .addReg(DestSub0)
4105 .addImm(AMDGPU::sub0)
4106 .addReg(DestSub1)
4107 .addImm(AMDGPU::sub1);
4108 TII->legalizeOperands(*LoHalf);
4109 TII->legalizeOperands(*HiHalf);
4110 MI.eraseFromParent();
4111 return BB;
4112 }
4113 case AMDGPU::S_ADD_CO_PSEUDO:
4114 case AMDGPU::S_SUB_CO_PSEUDO: {
4115 // This pseudo has a chance to be selected
4116 // only from uniform add/subcarry node. All the VGPR operands
4117 // therefore assumed to be splat vectors.
4118 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4119 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4120 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4121 MachineBasicBlock::iterator MII = MI;
4122 const DebugLoc &DL = MI.getDebugLoc();
4123 MachineOperand &Dest = MI.getOperand(0);
4124 MachineOperand &CarryDest = MI.getOperand(1);
4125 MachineOperand &Src0 = MI.getOperand(2);
4126 MachineOperand &Src1 = MI.getOperand(3);
4127 MachineOperand &Src2 = MI.getOperand(4);
4128 unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO)
4129 ? AMDGPU::S_ADDC_U32
4130 : AMDGPU::S_SUBB_U32;
4131 if (Src0.isReg() && TRI->isVectorRegister(MRI, Src0.getReg())) {
4132 Register RegOp0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4133 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp0)
4134 .addReg(Src0.getReg());
4135 Src0.setReg(RegOp0);
4136 }
4137 if (Src1.isReg() && TRI->isVectorRegister(MRI, Src1.getReg())) {
4138 Register RegOp1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4139 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp1)
4140 .addReg(Src1.getReg());
4141 Src1.setReg(RegOp1);
4142 }
4143 Register RegOp2 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4144 if (TRI->isVectorRegister(MRI, Src2.getReg())) {
4145 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp2)
4146 .addReg(Src2.getReg());
4147 Src2.setReg(RegOp2);
4148 }
4149
4150 const TargetRegisterClass *Src2RC = MRI.getRegClass(Src2.getReg());
4151 unsigned WaveSize = TRI->getRegSizeInBits(*Src2RC);
4152 assert(WaveSize == 64 || WaveSize == 32)(static_cast <bool> (WaveSize == 64 || WaveSize == 32) ?
void (0) : __assert_fail ("WaveSize == 64 || WaveSize == 32"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4152, __extension__ __PRETTY_FUNCTION__))
;
4153
4154 if (WaveSize == 64) {
4155 if (ST.hasScalarCompareEq64()) {
4156 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMP_LG_U64))
4157 .addReg(Src2.getReg())
4158 .addImm(0);
4159 } else {
4160 const TargetRegisterClass *SubRC =
4161 TRI->getSubRegClass(Src2RC, AMDGPU::sub0);
4162 MachineOperand Src2Sub0 = TII->buildExtractSubRegOrImm(
4163 MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC);
4164 MachineOperand Src2Sub1 = TII->buildExtractSubRegOrImm(
4165 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC);
4166 Register Src2_32 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4167
4168 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_OR_B32), Src2_32)
4169 .add(Src2Sub0)
4170 .add(Src2Sub1);
4171
4172 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMP_LG_U32))
4173 .addReg(Src2_32, RegState::Kill)
4174 .addImm(0);
4175 }
4176 } else {
4177 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMPK_LG_U32))
4178 .addReg(Src2.getReg())
4179 .addImm(0);
4180 }
4181
4182 BuildMI(*BB, MII, DL, TII->get(Opc), Dest.getReg()).add(Src0).add(Src1);
4183
4184 unsigned SelOpc =
4185 (WaveSize == 64) ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
4186
4187 BuildMI(*BB, MII, DL, TII->get(SelOpc), CarryDest.getReg())
4188 .addImm(-1)
4189 .addImm(0);
4190
4191 MI.eraseFromParent();
4192 return BB;
4193 }
4194 case AMDGPU::SI_INIT_M0: {
4195 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
4196 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
4197 .add(MI.getOperand(0));
4198 MI.eraseFromParent();
4199 return BB;
4200 }
4201 case AMDGPU::GET_GROUPSTATICSIZE: {
4202 assert(getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA ||(static_cast <bool> (getTargetMachine().getTargetTriple
().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple
().getOS() == Triple::AMDPAL) ? void (0) : __assert_fail ("getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4203, __extension__ __PRETTY_FUNCTION__))
4203 getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL)(static_cast <bool> (getTargetMachine().getTargetTriple
().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple
().getOS() == Triple::AMDPAL) ? void (0) : __assert_fail ("getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4203, __extension__ __PRETTY_FUNCTION__))
;
4204 DebugLoc DL = MI.getDebugLoc();
4205 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
4206 .add(MI.getOperand(0))
4207 .addImm(MFI->getLDSSize());
4208 MI.eraseFromParent();
4209 return BB;
4210 }
4211 case AMDGPU::SI_INDIRECT_SRC_V1:
4212 case AMDGPU::SI_INDIRECT_SRC_V2:
4213 case AMDGPU::SI_INDIRECT_SRC_V4:
4214 case AMDGPU::SI_INDIRECT_SRC_V8:
4215 case AMDGPU::SI_INDIRECT_SRC_V16:
4216 case AMDGPU::SI_INDIRECT_SRC_V32:
4217 return emitIndirectSrc(MI, *BB, *getSubtarget());
4218 case AMDGPU::SI_INDIRECT_DST_V1:
4219 case AMDGPU::SI_INDIRECT_DST_V2:
4220 case AMDGPU::SI_INDIRECT_DST_V4:
4221 case AMDGPU::SI_INDIRECT_DST_V8:
4222 case AMDGPU::SI_INDIRECT_DST_V16:
4223 case AMDGPU::SI_INDIRECT_DST_V32:
4224 return emitIndirectDst(MI, *BB, *getSubtarget());
4225 case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
4226 case AMDGPU::SI_KILL_I1_PSEUDO:
4227 return splitKillBlock(MI, BB);
4228 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
4229 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4230 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4231 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4232
4233 Register Dst = MI.getOperand(0).getReg();
4234 Register Src0 = MI.getOperand(1).getReg();
4235 Register Src1 = MI.getOperand(2).getReg();
4236 const DebugLoc &DL = MI.getDebugLoc();
4237 Register SrcCond = MI.getOperand(3).getReg();
4238
4239 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4240 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4241 const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4242 Register SrcCondCopy = MRI.createVirtualRegister(CondRC);
4243
4244 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
4245 .addReg(SrcCond);
4246 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
4247 .addImm(0)
4248 .addReg(Src0, 0, AMDGPU::sub0)
4249 .addImm(0)
4250 .addReg(Src1, 0, AMDGPU::sub0)
4251 .addReg(SrcCondCopy);
4252 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
4253 .addImm(0)
4254 .addReg(Src0, 0, AMDGPU::sub1)
4255 .addImm(0)
4256 .addReg(Src1, 0, AMDGPU::sub1)
4257 .addReg(SrcCondCopy);
4258
4259 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
4260 .addReg(DstLo)
4261 .addImm(AMDGPU::sub0)
4262 .addReg(DstHi)
4263 .addImm(AMDGPU::sub1);
4264 MI.eraseFromParent();
4265 return BB;
4266 }
4267 case AMDGPU::SI_BR_UNDEF: {
4268 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4269 const DebugLoc &DL = MI.getDebugLoc();
4270 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
4271 .add(MI.getOperand(0));
4272 Br->getOperand(1).setIsUndef(true); // read undef SCC
4273 MI.eraseFromParent();
4274 return BB;
4275 }
4276 case AMDGPU::ADJCALLSTACKUP:
4277 case AMDGPU::ADJCALLSTACKDOWN: {
4278 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
4279 MachineInstrBuilder MIB(*MF, &MI);
4280 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
4281 .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit);
4282 return BB;
4283 }
4284 case AMDGPU::SI_CALL_ISEL: {
4285 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4286 const DebugLoc &DL = MI.getDebugLoc();
4287
4288 unsigned ReturnAddrReg = TII->getRegisterInfo().getReturnAddressReg(*MF);
4289
4290 MachineInstrBuilder MIB;
4291 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg);
4292
4293 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I)
4294 MIB.add(MI.getOperand(I));
4295
4296 MIB.cloneMemRefs(MI);
4297 MI.eraseFromParent();
4298 return BB;
4299 }
4300 case AMDGPU::V_ADD_CO_U32_e32:
4301 case AMDGPU::V_SUB_CO_U32_e32:
4302 case AMDGPU::V_SUBREV_CO_U32_e32: {
4303 // TODO: Define distinct V_*_I32_Pseudo instructions instead.
4304 const DebugLoc &DL = MI.getDebugLoc();
4305 unsigned Opc = MI.getOpcode();
4306
4307 bool NeedClampOperand = false;
4308 if (TII->pseudoToMCOpcode(Opc) == -1) {
4309 Opc = AMDGPU::getVOPe64(Opc);
4310 NeedClampOperand = true;
4311 }
4312
4313 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
4314 if (TII->isVOP3(*I)) {
4315 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4316 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4317 I.addReg(TRI->getVCC(), RegState::Define);
4318 }
4319 I.add(MI.getOperand(1))
4320 .add(MI.getOperand(2));
4321 if (NeedClampOperand)
4322 I.addImm(0); // clamp bit for e64 encoding
4323
4324 TII->legalizeOperands(*I);
4325
4326 MI.eraseFromParent();
4327 return BB;
4328 }
4329 case AMDGPU::V_ADDC_U32_e32:
4330 case AMDGPU::V_SUBB_U32_e32:
4331 case AMDGPU::V_SUBBREV_U32_e32:
4332 // These instructions have an implicit use of vcc which counts towards the
4333 // constant bus limit.
4334 TII->legalizeOperands(MI);
4335 return BB;
4336 case AMDGPU::DS_GWS_INIT:
4337 case AMDGPU::DS_GWS_SEMA_BR:
4338 case AMDGPU::DS_GWS_BARRIER:
4339 if (Subtarget->needsAlignedVGPRs()) {
4340 // Add implicit aligned super-reg to force alignment on the data operand.
4341 const DebugLoc &DL = MI.getDebugLoc();
4342 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4343 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
4344 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::data0);
4345 Register DataReg = Op->getReg();
4346 bool IsAGPR = TRI->isAGPR(MRI, DataReg);
4347 Register Undef = MRI.createVirtualRegister(
4348 IsAGPR ? &AMDGPU::AGPR_32RegClass : &AMDGPU::VGPR_32RegClass);
4349 BuildMI(*BB, MI, DL, TII->get(AMDGPU::IMPLICIT_DEF), Undef);
4350 Register NewVR =
4351 MRI.createVirtualRegister(IsAGPR ? &AMDGPU::AReg_64_Align2RegClass
4352 : &AMDGPU::VReg_64_Align2RegClass);
4353 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), NewVR)
4354 .addReg(DataReg, 0, Op->getSubReg())
4355 .addImm(AMDGPU::sub0)
4356 .addReg(Undef)
4357 .addImm(AMDGPU::sub1);
4358 Op->setReg(NewVR);
4359 Op->setSubReg(AMDGPU::sub0);
4360 MI.addOperand(MachineOperand::CreateReg(NewVR, false, true));
4361 }
4362 LLVM_FALLTHROUGH[[gnu::fallthrough]];
4363 case AMDGPU::DS_GWS_SEMA_V:
4364 case AMDGPU::DS_GWS_SEMA_P:
4365 case AMDGPU::DS_GWS_SEMA_RELEASE_ALL:
4366 // A s_waitcnt 0 is required to be the instruction immediately following.
4367 if (getSubtarget()->hasGWSAutoReplay()) {
4368 bundleInstWithWaitcnt(MI);
4369 return BB;
4370 }
4371
4372 return emitGWSMemViolTestLoop(MI, BB);
4373 case AMDGPU::S_SETREG_B32: {
4374 // Try to optimize cases that only set the denormal mode or rounding mode.
4375 //
4376 // If the s_setreg_b32 fully sets all of the bits in the rounding mode or
4377 // denormal mode to a constant, we can use s_round_mode or s_denorm_mode
4378 // instead.
4379 //
4380 // FIXME: This could be predicates on the immediate, but tablegen doesn't
4381 // allow you to have a no side effect instruction in the output of a
4382 // sideeffecting pattern.
4383 unsigned ID, Offset, Width;
4384 AMDGPU::Hwreg::decodeHwreg(MI.getOperand(1).getImm(), ID, Offset, Width);
4385 if (ID != AMDGPU::Hwreg::ID_MODE)
4386 return BB;
4387
4388 const unsigned WidthMask = maskTrailingOnes<unsigned>(Width);
4389 const unsigned SetMask = WidthMask << Offset;
4390
4391 if (getSubtarget()->hasDenormModeInst()) {
4392 unsigned SetDenormOp = 0;
4393 unsigned SetRoundOp = 0;
4394
4395 // The dedicated instructions can only set the whole denorm or round mode
4396 // at once, not a subset of bits in either.
4397 if (SetMask ==
4398 (AMDGPU::Hwreg::FP_ROUND_MASK | AMDGPU::Hwreg::FP_DENORM_MASK)) {
4399 // If this fully sets both the round and denorm mode, emit the two
4400 // dedicated instructions for these.
4401 SetRoundOp = AMDGPU::S_ROUND_MODE;
4402 SetDenormOp = AMDGPU::S_DENORM_MODE;
4403 } else if (SetMask == AMDGPU::Hwreg::FP_ROUND_MASK) {
4404 SetRoundOp = AMDGPU::S_ROUND_MODE;
4405 } else if (SetMask == AMDGPU::Hwreg::FP_DENORM_MASK) {
4406 SetDenormOp = AMDGPU::S_DENORM_MODE;
4407 }
4408
4409 if (SetRoundOp || SetDenormOp) {
4410 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4411 MachineInstr *Def = MRI.getVRegDef(MI.getOperand(0).getReg());
4412 if (Def && Def->isMoveImmediate() && Def->getOperand(1).isImm()) {
4413 unsigned ImmVal = Def->getOperand(1).getImm();
4414 if (SetRoundOp) {
4415 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SetRoundOp))
4416 .addImm(ImmVal & 0xf);
4417
4418 // If we also have the denorm mode, get just the denorm mode bits.
4419 ImmVal >>= 4;
4420 }
4421
4422 if (SetDenormOp) {
4423 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SetDenormOp))
4424 .addImm(ImmVal & 0xf);
4425 }
4426
4427 MI.eraseFromParent();
4428 return BB;
4429 }
4430 }
4431 }
4432
4433 // If only FP bits are touched, used the no side effects pseudo.
4434 if ((SetMask & (AMDGPU::Hwreg::FP_ROUND_MASK |
4435 AMDGPU::Hwreg::FP_DENORM_MASK)) == SetMask)
4436 MI.setDesc(TII->get(AMDGPU::S_SETREG_B32_mode));
4437
4438 return BB;
4439 }
4440 default:
4441 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
4442 }
4443}
4444
4445bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const {
4446 return isTypeLegal(VT.getScalarType());
4447}
4448
4449bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
4450 // This currently forces unfolding various combinations of fsub into fma with
4451 // free fneg'd operands. As long as we have fast FMA (controlled by
4452 // isFMAFasterThanFMulAndFAdd), we should perform these.
4453
4454 // When fma is quarter rate, for f64 where add / sub are at best half rate,
4455 // most of these combines appear to be cycle neutral but save on instruction
4456 // count / code size.
4457 return true;
4458}
4459
4460EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
4461 EVT VT) const {
4462 if (!VT.isVector()) {
4463 return MVT::i1;
4464 }
4465 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
4466}
4467
4468MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT VT) const {
4469 // TODO: Should i16 be used always if legal? For now it would force VALU
4470 // shifts.
4471 return (VT == MVT::i16) ? MVT::i16 : MVT::i32;
4472}
4473
4474LLT SITargetLowering::getPreferredShiftAmountTy(LLT Ty) const {
4475 return (Ty.getScalarSizeInBits() <= 16 && Subtarget->has16BitInsts())
4476 ? Ty.changeElementSize(16)
4477 : Ty.changeElementSize(32);
4478}
4479
4480// Answering this is somewhat tricky and depends on the specific device which
4481// have different rates for fma or all f64 operations.
4482//
4483// v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
4484// regardless of which device (although the number of cycles differs between
4485// devices), so it is always profitable for f64.
4486//
4487// v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
4488// only on full rate devices. Normally, we should prefer selecting v_mad_f32
4489// which we can always do even without fused FP ops since it returns the same
4490// result as the separate operations and since it is always full
4491// rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
4492// however does not support denormals, so we do report fma as faster if we have
4493// a fast fma device and require denormals.
4494//
4495bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
4496 EVT VT) const {
4497 VT = VT.getScalarType();
4498
4499 switch (VT.getSimpleVT().SimpleTy) {
4500 case MVT::f32: {
4501 // If mad is not available this depends only on if f32 fma is full rate.
4502 if (!Subtarget->hasMadMacF32Insts())
4503 return Subtarget->hasFastFMAF32();
4504
4505 // Otherwise f32 mad is always full rate and returns the same result as
4506 // the separate operations so should be preferred over fma.
4507 // However does not support denomals.
4508 if (hasFP32Denormals(MF))
4509 return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts();
4510
4511 // If the subtarget has v_fmac_f32, that's just as good as v_mac_f32.
4512 return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts();
4513 }
4514 case MVT::f64:
4515 return true;
4516 case MVT::f16:
4517 return Subtarget->has16BitInsts() && hasFP64FP16Denormals(MF);
4518 default:
4519 break;
4520 }
4521
4522 return false;
4523}
4524
4525bool SITargetLowering::isFMADLegal(const SelectionDAG &DAG,
4526 const SDNode *N) const {
4527 // TODO: Check future ftz flag
4528 // v_mad_f32/v_mac_f32 do not support denormals.
4529 EVT VT = N->getValueType(0);
4530 if (VT == MVT::f32)
4531 return Subtarget->hasMadMacF32Insts() &&
4532 !hasFP32Denormals(DAG.getMachineFunction());
4533 if (VT == MVT::f16) {
4534 return Subtarget->hasMadF16() &&
4535 !hasFP64FP16Denormals(DAG.getMachineFunction());
4536 }
4537
4538 return false;
4539}
4540
4541//===----------------------------------------------------------------------===//
4542// Custom DAG Lowering Operations
4543//===----------------------------------------------------------------------===//
4544
4545// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
4546// wider vector type is legal.
4547SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
4548 SelectionDAG &DAG) const {
4549 unsigned Opc = Op.getOpcode();
4550 EVT VT = Op.getValueType();
4551 assert(VT == MVT::v4f16 || VT == MVT::v4i16)(static_cast <bool> (VT == MVT::v4f16 || VT == MVT::v4i16
) ? void (0) : __assert_fail ("VT == MVT::v4f16 || VT == MVT::v4i16"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4551, __extension__ __PRETTY_FUNCTION__))
;
4552
4553 SDValue Lo, Hi;
4554 std::tie(Lo, Hi) = DAG.SplitVectorOperand(Op.getNode(), 0);
4555
4556 SDLoc SL(Op);
4557 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo,
4558 Op->getFlags());
4559 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi,
4560 Op->getFlags());
4561
4562 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4563}
4564
4565// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
4566// wider vector type is legal.
4567SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
4568 SelectionDAG &DAG) const {
4569 unsigned Opc = Op.getOpcode();
4570 EVT VT = Op.getValueType();
4571 assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 ||(static_cast <bool> (VT == MVT::v4i16 || VT == MVT::v4f16
|| VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32
|| VT == MVT::v32f32) ? void (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4572, __extension__ __PRETTY_FUNCTION__))
4572 VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32)(static_cast <bool> (VT == MVT::v4i16 || VT == MVT::v4f16
|| VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32
|| VT == MVT::v32f32) ? void (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4572, __extension__ __PRETTY_FUNCTION__))
;
4573
4574 SDValue Lo0, Hi0;
4575 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
4576 SDValue Lo1, Hi1;
4577 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4578
4579 SDLoc SL(Op);
4580
4581 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1,
4582 Op->getFlags());
4583 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1,
4584 Op->getFlags());
4585
4586 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4587}
4588
4589SDValue SITargetLowering::splitTernaryVectorOp(SDValue Op,
4590 SelectionDAG &DAG) const {
4591 unsigned Opc = Op.getOpcode();
4592 EVT VT = Op.getValueType();
4593 assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 ||(static_cast <bool> (VT == MVT::v4i16 || VT == MVT::v4f16
|| VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32
|| VT == MVT::v32f32) ? void (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4594, __extension__ __PRETTY_FUNCTION__))
4594 VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32)(static_cast <bool> (VT == MVT::v4i16 || VT == MVT::v4f16
|| VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32
|| VT == MVT::v32f32) ? void (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4594, __extension__ __PRETTY_FUNCTION__))
;
4595
4596 SDValue Lo0, Hi0;
4597 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
4598 SDValue Lo1, Hi1;
4599 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4600 SDValue Lo2, Hi2;
4601 std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2);
4602
4603 SDLoc SL(Op);
4604
4605 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2,
4606 Op->getFlags());
4607 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2,
4608 Op->getFlags());
4609
4610 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4611}
4612
4613
4614SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4615 switch (Op.getOpcode()) {
4616 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
4617 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4618 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4619 case ISD::LOAD: {
4620 SDValue Result = LowerLOAD(Op, DAG);
4621 assert((!Result.getNode() ||(static_cast <bool> ((!Result.getNode() || Result.getNode
()->getNumValues() == 2) && "Load should return a value and a chain"
) ? void (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4623, __extension__ __PRETTY_FUNCTION__))
4622 Result.getNode()->getNumValues() == 2) &&(static_cast <bool> ((!Result.getNode() || Result.getNode
()->getNumValues() == 2) && "Load should return a value and a chain"
) ? void (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4623, __extension__ __PRETTY_FUNCTION__))
4623 "Load should return a value and a chain")(static_cast <bool> ((!Result.getNode() || Result.getNode
()->getNumValues() == 2) && "Load should return a value and a chain"
) ? void (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4623, __extension__ __PRETTY_FUNCTION__))
;
4624 return Result;
4625 }
4626
4627 case ISD::FSIN:
4628 case ISD::FCOS:
4629 return LowerTrig(Op, DAG);
4630 case ISD::SELECT: return LowerSELECT(Op, DAG);
4631 case ISD::FDIV: return LowerFDIV(Op, DAG);
4632 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
4633 case ISD::STORE: return LowerSTORE(Op, DAG);
4634 case ISD::GlobalAddress: {
4635 MachineFunction &MF = DAG.getMachineFunction();
4636 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
4637 return LowerGlobalAddress(MFI, Op, DAG);
4638 }
4639 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4640 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
4641 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
4642 case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
4643 case ISD::INSERT_SUBVECTOR:
4644 return lowerINSERT_SUBVECTOR(Op, DAG);
4645 case ISD::INSERT_VECTOR_ELT:
4646 return lowerINSERT_VECTOR_ELT(Op, DAG);
4647 case ISD::EXTRACT_VECTOR_ELT:
4648 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4649 case ISD::VECTOR_SHUFFLE:
4650 return lowerVECTOR_SHUFFLE(Op, DAG);
4651 case ISD::BUILD_VECTOR:
4652 return lowerBUILD_VECTOR(Op, DAG);
4653 case ISD::FP_ROUND:
4654 return lowerFP_ROUND(Op, DAG);
4655 case ISD::TRAP:
4656 return lowerTRAP(Op, DAG);
4657 case ISD::DEBUGTRAP:
4658 return lowerDEBUGTRAP(Op, DAG);
4659 case ISD::FABS:
4660 case ISD::FNEG:
4661 case ISD::FCANONICALIZE:
4662 case ISD::BSWAP:
4663 return splitUnaryVectorOp(Op, DAG);
4664 case ISD::FMINNUM:
4665 case ISD::FMAXNUM:
4666 return lowerFMINNUM_FMAXNUM(Op, DAG);
4667 case ISD::FMA:
4668 return splitTernaryVectorOp(Op, DAG);
4669 case ISD::FP_TO_SINT:
4670 case ISD::FP_TO_UINT:
4671 return LowerFP_TO_INT(Op, DAG);
4672 case ISD::SHL:
4673 case ISD::SRA:
4674 case ISD::SRL:
4675 case ISD::ADD:
4676 case ISD::SUB:
4677 case ISD::MUL:
4678 case ISD::SMIN:
4679 case ISD::SMAX:
4680 case ISD::UMIN:
4681 case ISD::UMAX:
4682 case ISD::FADD:
4683 case ISD::FMUL:
4684 case ISD::FMINNUM_IEEE:
4685 case ISD::FMAXNUM_IEEE:
4686 case ISD::UADDSAT:
4687 case ISD::USUBSAT:
4688 case ISD::SADDSAT:
4689 case ISD::SSUBSAT:
4690 return splitBinaryVectorOp(Op, DAG);
4691 case ISD::SMULO:
4692 case ISD::UMULO:
4693 return lowerXMULO(Op, DAG);
4694 case ISD::DYNAMIC_STACKALLOC:
4695 return LowerDYNAMIC_STACKALLOC(Op, DAG);
4696 }
4697 return SDValue();
4698}
4699
4700// Used for D16: Casts the result of an instruction into the right vector,
4701// packs values if loads return unpacked values.
4702static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT,
4703 const SDLoc &DL,
4704 SelectionDAG &DAG, bool Unpacked) {
4705 if (!LoadVT.isVector())
4706 return Result;
4707
4708 // Cast back to the original packed type or to a larger type that is a
4709 // multiple of 32 bit for D16. Widening the return type is a required for
4710 // legalization.
4711 EVT FittingLoadVT = LoadVT;
4712 if ((LoadVT.getVectorNumElements() % 2) == 1) {
4713 FittingLoadVT =
4714 EVT::getVectorVT(*DAG.getContext(), LoadVT.getVectorElementType(),
4715 LoadVT.getVectorNumElements() + 1);
4716 }
4717
4718 if (Unpacked) { // From v2i32/v4i32 back to v2f16/v4f16.
4719 // Truncate to v2i16/v4i16.
4720 EVT IntLoadVT = FittingLoadVT.changeTypeToInteger();
4721
4722 // Workaround legalizer not scalarizing truncate after vector op
4723 // legalization but not creating intermediate vector trunc.
4724 SmallVector<SDValue, 4> Elts;
4725 DAG.ExtractVectorElements(Result, Elts);
4726 for (SDValue &Elt : Elts)
4727 Elt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Elt);
4728
4729 // Pad illegal v1i16/v3fi6 to v4i16
4730 if ((LoadVT.getVectorNumElements() % 2) == 1)
4731 Elts.push_back(DAG.getUNDEF(MVT::i16));
4732
4733 Result = DAG.getBuildVector(IntLoadVT, DL, Elts);
4734
4735 // Bitcast to original type (v2f16/v4f16).
4736 return DAG.getNode(ISD::BITCAST, DL, FittingLoadVT, Result);
4737 }
4738
4739 // Cast back to the original packed type.
4740 return DAG.getNode(ISD::BITCAST, DL, FittingLoadVT, Result);
4741}
4742
4743SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
4744 MemSDNode *M,
4745 SelectionDAG &DAG,
4746 ArrayRef<SDValue> Ops,
4747 bool IsIntrinsic) const {
4748 SDLoc DL(M);
4749
4750 bool Unpacked = Subtarget->hasUnpackedD16VMem();
4751 EVT LoadVT = M->getValueType(0);
4752
4753 EVT EquivLoadVT = LoadVT;
4754 if (LoadVT.isVector()) {
4755 if (Unpacked) {
4756 EquivLoadVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
4757 LoadVT.getVectorNumElements());
4758 } else if ((LoadVT.getVectorNumElements() % 2) == 1) {
4759 // Widen v3f16 to legal type
4760 EquivLoadVT =
4761 EVT::getVectorVT(*DAG.getContext(), LoadVT.getVectorElementType(),
4762 LoadVT.getVectorNumElements() + 1);
4763 }
4764 }
4765
4766 // Change from v4f16/v2f16 to EquivLoadVT.
4767 SDVTList VTList = DAG.getVTList(EquivLoadVT, MVT::Other);
4768
4769 SDValue Load
4770 = DAG.getMemIntrinsicNode(
4771 IsIntrinsic ? (unsigned)ISD::INTRINSIC_W_CHAIN : Opcode, DL,
4772 VTList, Ops, M->getMemoryVT(),
4773 M->getMemOperand());
4774
4775 SDValue Adjusted = adjustLoadValueTypeImpl(Load, LoadVT, DL, DAG, Unpacked);
4776
4777 return DAG.getMergeValues({ Adjusted, Load.getValue(1) }, DL);
4778}
4779
4780SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
4781 SelectionDAG &DAG,
4782 ArrayRef<SDValue> Ops) const {
4783 SDLoc DL(M);
4784 EVT LoadVT = M->getValueType(0);
4785 EVT EltType = LoadVT.getScalarType();
4786 EVT IntVT = LoadVT.changeTypeToInteger();
4787
4788 bool IsD16 = IsFormat && (EltType.getSizeInBits() == 16);
4789
4790 unsigned Opc =
4791 IsFormat ? AMDGPUISD::BUFFER_LOAD_FORMAT : AMDGPUISD::BUFFER_LOAD;
4792
4793 if (IsD16) {
4794 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, M, DAG, Ops);
4795 }
4796
4797 // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
4798 if (!IsD16 && !LoadVT.isVector() && EltType.getSizeInBits() < 32)
4799 return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
4800
4801 if (isTypeLegal(LoadVT)) {
4802 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT,
4803 M->getMemOperand(), DAG);
4804 }
4805
4806 EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT);
4807 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other);
4808 SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT,
4809 M->getMemOperand(), DAG);
4810 return DAG.getMergeValues(
4811 {DAG.getNode(ISD::BITCAST, DL, LoadVT, MemNode), MemNode.getValue(1)},
4812 DL);
4813}
4814
4815static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
4816 SDNode *N, SelectionDAG &DAG) {
4817 EVT VT = N->getValueType(0);
4818 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4819 unsigned CondCode = CD->getZExtValue();
4820 if (!ICmpInst::isIntPredicate(static_cast<ICmpInst::Predicate>(CondCode)))
4821 return DAG.getUNDEF(VT);
4822
4823 ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
4824
4825 SDValue LHS = N->getOperand(1);
4826 SDValue RHS = N->getOperand(2);
4827
4828 SDLoc DL(N);
4829
4830 EVT CmpVT = LHS.getValueType();
4831 if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) {
4832 unsigned PromoteOp = ICmpInst::isSigned(IcInput) ?
4833 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4834 LHS = DAG.getNode(PromoteOp, DL, MVT::i32, LHS);
4835 RHS = DAG.getNode(PromoteOp, DL, MVT::i32, RHS);
4836 }
4837
4838 ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
4839
4840 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4841 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4842
4843 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS,
4844 DAG.getCondCode(CCOpcode));
4845 if (VT.bitsEq(CCVT))
4846 return SetCC;
4847 return DAG.getZExtOrTrunc(SetCC, DL, VT);
4848}
4849
4850static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI,
4851 SDNode *N, SelectionDAG &DAG) {
4852 EVT VT = N->getValueType(0);
4853 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4854
4855 unsigned CondCode = CD->getZExtValue();
4856 if (!FCmpInst::isFPPredicate(static_cast<FCmpInst::Predicate>(CondCode)))
4857 return DAG.getUNDEF(VT);
4858
4859 SDValue Src0 = N->getOperand(1);
4860 SDValue Src1 = N->getOperand(2);
4861 EVT CmpVT = Src0.getValueType();
4862 SDLoc SL(N);
4863
4864 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
4865 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4866 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
4867 }
4868
4869 FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
4870 ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
4871 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4872 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4873 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0,
4874 Src1, DAG.getCondCode(CCOpcode));
4875 if (VT.bitsEq(CCVT))
4876 return SetCC;
4877 return DAG.getZExtOrTrunc(SetCC, SL, VT);
4878}
4879
4880static SDValue lowerBALLOTIntrinsic(const SITargetLowering &TLI, SDNode *N,
4881 SelectionDAG &DAG) {
4882 EVT VT = N->getValueType(0);
4883 SDValue Src = N->getOperand(1);
4884 SDLoc SL(N);
4885
4886 if (Src.getOpcode() == ISD::SETCC) {
4887 // (ballot (ISD::SETCC ...)) -> (AMDGPUISD::SETCC ...)
4888 return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Src.getOperand(0),
4889 Src.getOperand(1), Src.getOperand(2));
4890 }
4891 if (const ConstantSDNode *Arg = dyn_cast<ConstantSDNode>(Src)) {
4892 // (ballot 0) -> 0
4893 if (Arg->isZero())
4894 return DAG.getConstant(0, SL, VT);
4895
4896 // (ballot 1) -> EXEC/EXEC_LO
4897 if (Arg->isOne()) {
4898 Register Exec;
4899 if (VT.getScalarSizeInBits() == 32)
4900 Exec = AMDGPU::EXEC_LO;
4901 else if (VT.getScalarSizeInBits() == 64)
4902 Exec = AMDGPU::EXEC;
4903 else
4904 return SDValue();
4905
4906 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, Exec, VT);
4907 }
4908 }
4909
4910 // (ballot (i1 $src)) -> (AMDGPUISD::SETCC (i32 (zext $src)) (i32 0)
4911 // ISD::SETNE)
4912 return DAG.getNode(
4913 AMDGPUISD::SETCC, SL, VT, DAG.getZExtOrTrunc(Src, SL, MVT::i32),
4914 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE));
4915}
4916
4917void SITargetLowering::ReplaceNodeResults(SDNode *N,
4918 SmallVectorImpl<SDValue> &Results,
4919 SelectionDAG &DAG) const {
4920 switch (N->getOpcode()) {
4921 case ISD::INSERT_VECTOR_ELT: {
4922 if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
4923 Results.push_back(Res);
4924 return;
4925 }
4926 case ISD::EXTRACT_VECTOR_ELT: {
4927 if (SDValue Res = lowerEXTRACT_VECTOR_ELT(SDValue(N, 0), DAG))
4928 Results.push_back(Res);
4929 return;
4930 }
4931 case ISD::INTRINSIC_WO_CHAIN: {
4932 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4933 switch (IID) {
4934 case Intrinsic::amdgcn_cvt_pkrtz: {
4935 SDValue Src0 = N->getOperand(1);
4936 SDValue Src1 = N->getOperand(2);
4937 SDLoc SL(N);
4938 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32,
4939 Src0, Src1);
4940 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt));
4941 return;
4942 }
4943 case Intrinsic::amdgcn_cvt_pknorm_i16:
4944 case Intrinsic::amdgcn_cvt_pknorm_u16:
4945 case Intrinsic::amdgcn_cvt_pk_i16:
4946 case Intrinsic::amdgcn_cvt_pk_u16: {
4947 SDValue Src0 = N->getOperand(1);
4948 SDValue Src1 = N->getOperand(2);
4949 SDLoc SL(N);
4950 unsigned Opcode;
4951
4952 if (IID == Intrinsic::amdgcn_cvt_pknorm_i16)
4953 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
4954 else if (IID == Intrinsic::amdgcn_cvt_pknorm_u16)
4955 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
4956 else if (IID == Intrinsic::amdgcn_cvt_pk_i16)
4957 Opcode = AMDGPUISD::CVT_PK_I16_I32;
4958 else
4959 Opcode = AMDGPUISD::CVT_PK_U16_U32;
4960
4961 EVT VT = N->getValueType(0);
4962 if (isTypeLegal(VT))
4963 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
4964 else {
4965 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
4966 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt));
4967 }
4968 return;
4969 }
4970 }
4971 break;
4972 }
4973 case ISD::INTRINSIC_W_CHAIN: {
4974 if (SDValue Res = LowerINTRINSIC_W_CHAIN(SDValue(N, 0), DAG)) {
4975 if (Res.getOpcode() == ISD::MERGE_VALUES) {
4976 // FIXME: Hacky
4977 for (unsigned I = 0; I < Res.getNumOperands(); I++) {
4978 Results.push_back(Res.getOperand(I));
4979 }
4980 } else {
4981 Results.push_back(Res);
4982 Results.push_back(Res.getValue(1));
4983 }
4984 return;
4985 }
4986
4987 break;
4988 }
4989 case ISD::SELECT: {
4990 SDLoc SL(N);
4991 EVT VT = N->getValueType(0);
4992 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
4993 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1));
4994 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2));
4995
4996 EVT SelectVT = NewVT;
4997 if (NewVT.bitsLT(MVT::i32)) {
4998 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS);
4999 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS);
5000 SelectVT = MVT::i32;
5001 }
5002
5003 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT,
5004 N->getOperand(0), LHS, RHS);
5005
5006 if (NewVT != SelectVT)
5007 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect);
5008 Results.push_back(DAG.getNode(ISD::BITCAST, SL, VT, NewSelect));
5009 return;
5010 }
5011 case ISD::FNEG: {
5012 if (N->getValueType(0) != MVT::v2f16)
5013 break;
5014
5015 SDLoc SL(N);
5016 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
5017
5018 SDValue Op = DAG.getNode(ISD::XOR, SL, MVT::i32,
5019 BC,
5020 DAG.getConstant(0x80008000, SL, MVT::i32));
5021 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
5022 return;
5023 }
5024 case ISD::FABS: {
5025 if (N->getValueType(0) != MVT::v2f16)
5026 break;
5027
5028 SDLoc SL(N);
5029 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
5030
5031 SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32,
5032 BC,
5033 DAG.getConstant(0x7fff7fff, SL, MVT::i32));
5034 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
5035 return;
5036 }
5037 default:
5038 break;
5039 }
5040}
5041
5042/// Helper function for LowerBRCOND
5043static SDNode *findUser(SDValue Value, unsigned Opcode) {
5044
5045 SDNode *Parent = Value.getNode();
5046 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
5047 I != E; ++I) {
5048
5049 if (I.getUse().get() != Value)
5050 continue;
5051
5052 if (I->getOpcode() == Opcode)
5053 return *I;
5054 }
5055 return nullptr;
5056}
5057
5058unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
5059 if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
5060 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
5061 case Intrinsic::amdgcn_if:
5062 return AMDGPUISD::IF;
5063 case Intrinsic::amdgcn_else:
5064 return AMDGPUISD::ELSE;
5065 case Intrinsic::amdgcn_loop:
5066 return AMDGPUISD::LOOP;
5067 case Intrinsic::amdgcn_end_cf:
5068 llvm_unreachable("should not occur")::llvm::llvm_unreachable_internal("should not occur", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5068)
;
5069 default:
5070 return 0;
5071 }
5072 }
5073
5074 // break, if_break, else_break are all only used as inputs to loop, not
5075 // directly as branch conditions.
5076 return 0;
5077}
5078
5079bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
5080 const Triple &TT = getTargetMachine().getTargetTriple();
5081 return (GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
5082 GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
5083 AMDGPU::shouldEmitConstantsToTextSection(TT);
5084}
5085
5086bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
5087 // FIXME: Either avoid relying on address space here or change the default
5088 // address space for functions to avoid the explicit check.
5089 return (GV->getValueType()->isFunctionTy() ||
5090 !isNonGlobalAddrSpace(GV->getAddressSpace())) &&
5091 !shouldEmitFixup(GV) &&
5092 !getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
5093}
5094
5095bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
5096 return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
5097}
5098
5099bool SITargetLowering::shouldUseLDSConstAddress(const GlobalValue *GV) const {
5100 if (!GV->hasExternalLinkage())
5101 return true;
5102
5103 const auto OS = getTargetMachine().getTargetTriple().getOS();
5104 return OS == Triple::AMDHSA || OS == Triple::AMDPAL;
5105}
5106
5107/// This transforms the control flow intrinsics to get the branch destination as
5108/// last parameter, also switches branch target with BR if the need arise
5109SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
5110 SelectionDAG &DAG) const {
5111 SDLoc DL(BRCOND);
5112
5113 SDNode *Intr = BRCOND.getOperand(1).getNode();
5114 SDValue Target = BRCOND.getOperand(2);
5115 SDNode *BR = nullptr;
5116 SDNode *SetCC = nullptr;
5117
5118 if (Intr->getOpcode() == ISD::SETCC) {
5119 // As long as we negate the condition everything is fine
5120 SetCC = Intr;
5121 Intr = SetCC->getOperand(0).getNode();
5122
5123 } else {
5124 // Get the target from BR if we don't negate the condition
5125 BR = findUser(BRCOND, ISD::BR);
5126 assert(BR && "brcond missing unconditional branch user")(static_cast <bool> (BR && "brcond missing unconditional branch user"
) ? void (0) : __assert_fail ("BR && \"brcond missing unconditional branch user\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5126, __extension__ __PRETTY_FUNCTION__))
;
5127 Target = BR->getOperand(1);
5128 }
5129
5130 unsigned CFNode = isCFIntrinsic(Intr);
5131 if (CFNode == 0) {
5132 // This is a uniform branch so we don't need to legalize.
5133 return BRCOND;
5134 }
5135
5136 bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||
5137 Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN;
5138
5139 assert(!SetCC ||(static_cast <bool> (!SetCC || (SetCC->getConstantOperandVal
(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand
(2).getNode())->get() == ISD::SETNE)) ? void (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5142, __extension__ __PRETTY_FUNCTION__))
5140 (SetCC->getConstantOperandVal(1) == 1 &&(static_cast <bool> (!SetCC || (SetCC->getConstantOperandVal
(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand
(2).getNode())->get() == ISD::SETNE)) ? void (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5142, __extension__ __PRETTY_FUNCTION__))
5141 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==(static_cast <bool> (!SetCC || (SetCC->getConstantOperandVal
(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand
(2).getNode())->get() == ISD::SETNE)) ? void (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5142, __extension__ __PRETTY_FUNCTION__))
5142 ISD::SETNE))(static_cast <bool> (!SetCC || (SetCC->getConstantOperandVal
(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand
(2).getNode())->get() == ISD::SETNE)) ? void (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5142, __extension__ __PRETTY_FUNCTION__))
;
5143
5144 // operands of the new intrinsic call
5145 SmallVector<SDValue, 4> Ops;
5146 if (HaveChain)
5147 Ops.push_back(BRCOND.getOperand(0));
5148
5149 Ops.append(Intr->op_begin() + (HaveChain ? 2 : 1), Intr->op_end());
5150 Ops.push_back(Target);
5151
5152 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
5153
5154 // build the new intrinsic call
5155 SDNode *Result = DAG.getNode(CFNode, DL, DAG.getVTList(Res), Ops).getNode();
5156
5157 if (!HaveChain) {
5158 SDValue Ops[] = {
5159 SDValue(Result, 0),
5160 BRCOND.getOperand(0)
5161 };
5162
5163 Result = DAG.getMergeValues(Ops, DL).getNode();
5164 }
5165
5166 if (BR) {
5167 // Give the branch instruction our target
5168 SDValue Ops[] = {
5169 BR->getOperand(0),
5170 BRCOND.getOperand(2)
5171 };
5172 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
5173 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
5174 }
5175
5176 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
5177
5178 // Copy the intrinsic results to registers
5179 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
5180 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
5181 if (!CopyToReg)
5182 continue;
5183
5184 Chain = DAG.getCopyToReg(
5185 Chain, DL,
5186 CopyToReg->getOperand(1),
5187 SDValue(Result, i - 1),
5188 SDValue());
5189
5190 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
5191 }
5192
5193 // Remove the old intrinsic from the chain
5194 DAG.ReplaceAllUsesOfValueWith(
5195 SDValue(Intr, Intr->getNumValues() - 1),
5196 Intr->getOperand(0));
5197
5198 return Chain;
5199}
5200
5201SDValue SITargetLowering::LowerRETURNADDR(SDValue Op,
5202 SelectionDAG &DAG) const {
5203 MVT VT = Op.getSimpleValueType();
5204 SDLoc DL(Op);
5205 // Checking the depth
5206 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0)
5207 return DAG.getConstant(0, DL, VT);
5208
5209 MachineFunction &MF = DAG.getMachineFunction();
5210 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5211 // Check for kernel and shader functions
5212 if (Info->isEntryFunction())
5213 return DAG.getConstant(0, DL, VT);
5214
5215 MachineFrameInfo &MFI = MF.getFrameInfo();
5216 // There is a call to @llvm.returnaddress in this function
5217 MFI.setReturnAddressIsTaken(true);
5218
5219 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
5220 // Get the return address reg and mark it as an implicit live-in
5221 Register Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent()));
5222
5223 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
5224}
5225
5226SDValue SITargetLowering::getFPExtOrFPRound(SelectionDAG &DAG,
5227 SDValue Op,
5228 const SDLoc &DL,
5229 EVT VT) const {
5230 return Op.getValueType().bitsLE(VT) ?
5231 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) :
5232 DAG.getNode(ISD::FP_ROUND, DL, VT, Op,
5233 DAG.getTargetConstant(0, DL, MVT::i32));
5234}
5235
5236SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
5237 assert(Op.getValueType() == MVT::f16 &&(static_cast <bool> (Op.getValueType() == MVT::f16 &&
"Do not know how to custom lower FP_ROUND for non-f16 type")
? void (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5238, __extension__ __PRETTY_FUNCTION__))
5238 "Do not know how to custom lower FP_ROUND for non-f16 type")(static_cast <bool> (Op.getValueType() == MVT::f16 &&
"Do not know how to custom lower FP_ROUND for non-f16 type")
? void (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5238, __extension__ __PRETTY_FUNCTION__))
;
5239
5240 SDValue Src = Op.getOperand(0);
5241 EVT SrcVT = Src.getValueType();
5242 if (SrcVT != MVT::f64)
5243 return Op;
5244
5245 SDLoc DL(Op);
5246
5247 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);
5248 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToFp16);
5249 return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);
5250}
5251
5252SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
5253 SelectionDAG &DAG) const {
5254 EVT VT = Op.getValueType();
5255 const MachineFunction &MF = DAG.getMachineFunction();
5256 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5257 bool IsIEEEMode = Info->getMode().IEEE;
5258
5259 // FIXME: Assert during selection that this is only selected for
5260 // ieee_mode. Currently a combine can produce the ieee version for non-ieee
5261 // mode functions, but this happens to be OK since it's only done in cases
5262 // where there is known no sNaN.
5263 if (IsIEEEMode)
5264 return expandFMINNUM_FMAXNUM(Op.getNode(), DAG);
5265
5266 if (VT == MVT::v4f16)
5267 return splitBinaryVectorOp(Op, DAG);
5268 return Op;
5269}
5270
5271SDValue SITargetLowering::lowerXMULO(SDValue Op, SelectionDAG &DAG) const {
5272 EVT VT = Op.getValueType();
5273 SDLoc SL(Op);
5274 SDValue LHS = Op.getOperand(0);
5275 SDValue RHS = Op.getOperand(1);
5276 bool isSigned = Op.getOpcode() == ISD::SMULO;
5277
5278 if (ConstantSDNode *RHSC = isConstOrConstSplat(RHS)) {
5279 const APInt &C = RHSC->getAPIntValue();
5280 // mulo(X, 1 << S) -> { X << S, (X << S) >> S != X }
5281 if (C.isPowerOf2()) {
5282 // smulo(x, signed_min) is same as umulo(x, signed_min).
5283 bool UseArithShift = isSigned && !C.isMinSignedValue();
5284 SDValue ShiftAmt = DAG.getConstant(C.logBase2(), SL, MVT::i32);
5285 SDValue Result = DAG.getNode(ISD::SHL, SL, VT, LHS, ShiftAmt);
5286 SDValue Overflow = DAG.getSetCC(SL, MVT::i1,
5287 DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL,
5288 SL, VT, Result, ShiftAmt),
5289 LHS, ISD::SETNE);
5290 return DAG.getMergeValues({ Result, Overflow }, SL);
5291 }
5292 }
5293
5294 SDValue Result = DAG.getNode(ISD::MUL, SL, VT, LHS, RHS);
5295 SDValue Top = DAG.getNode(isSigned ? ISD::MULHS : ISD::MULHU,
5296 SL, VT, LHS, RHS);
5297
5298 SDValue Sign = isSigned
5299 ? DAG.getNode(ISD::SRA, SL, VT, Result,
5300 DAG.getConstant(VT.getScalarSizeInBits() - 1, SL, MVT::i32))
5301 : DAG.getConstant(0, SL, VT);
5302 SDValue Overflow = DAG.getSetCC(SL, MVT::i1, Top, Sign, ISD::SETNE);
5303
5304 return DAG.getMergeValues({ Result, Overflow }, SL);
5305}
5306
5307SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
5308 if (!Subtarget->isTrapHandlerEnabled() ||
5309 Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA)
5310 return lowerTrapEndpgm(Op, DAG);
5311
5312 if (Optional<uint8_t> HsaAbiVer = AMDGPU::getHsaAbiVersion(Subtarget)) {
5313 switch (*HsaAbiVer) {
5314 case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
5315 case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
5316 return lowerTrapHsaQueuePtr(Op, DAG);
5317 case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
5318 return Subtarget->supportsGetDoorbellID() ?
5319 lowerTrapHsa(Op, DAG) : lowerTrapHsaQueuePtr(Op, DAG);
5320 }
5321 }
5322
5323 llvm_unreachable("Unknown trap handler")::llvm::llvm_unreachable_internal("Unknown trap handler", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5323)
;
5324}
5325
5326SDValue SITargetLowering::lowerTrapEndpgm(
5327 SDValue Op, SelectionDAG &DAG) const {
5328 SDLoc SL(Op);
5329 SDValue Chain = Op.getOperand(0);
5330 return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain);
5331}
5332
5333SDValue SITargetLowering::lowerTrapHsaQueuePtr(
5334 SDValue Op, SelectionDAG &DAG) const {
5335 SDLoc SL(Op);
5336 SDValue Chain = Op.getOperand(0);
5337
5338 MachineFunction &MF = DAG.getMachineFunction();
5339 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5340 Register UserSGPR = Info->getQueuePtrUserSGPR();
5341
5342 SDValue QueuePtr;
5343 if (UserSGPR == AMDGPU::NoRegister) {
5344 // We probably are in a function incorrectly marked with
5345 // amdgpu-no-queue-ptr. This is undefined. We don't want to delete the trap,
5346 // so just use a null pointer.
5347 QueuePtr = DAG.getConstant(0, SL, MVT::i64);
5348 } else {
5349 QueuePtr = CreateLiveInRegister(
5350 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
5351 }
5352
5353 SDValue SGPR01 = DAG.getRegister(AMDGPU::SGPR0_SGPR1, MVT::i64);
5354 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01,
5355 QueuePtr, SDValue());
5356
5357 uint64_t TrapID = static_cast<uint64_t>(GCNSubtarget::TrapID::LLVMAMDHSATrap);
5358 SDValue Ops[] = {
5359 ToReg,
5360 DAG.getTargetConstant(TrapID, SL, MVT::i16),
5361 SGPR01,
5362 ToReg.getValue(1)
5363 };
5364 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
5365}
5366
5367SDValue SITargetLowering::lowerTrapHsa(
5368 SDValue Op, SelectionDAG &DAG) const {
5369 SDLoc SL(Op);
5370 SDValue Chain = Op.getOperand(0);
5371
5372 uint64_t TrapID = static_cast<uint64_t>(GCNSubtarget::TrapID::LLVMAMDHSATrap);
5373 SDValue Ops[] = {
5374 Chain,
5375 DAG.getTargetConstant(TrapID, SL, MVT::i16)
5376 };
5377 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
5378}
5379
5380SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
5381 SDLoc SL(Op);
5382 SDValue Chain = Op.getOperand(0);
5383 MachineFunction &MF = DAG.getMachineFunction();
5384
5385 if (!Subtarget->isTrapHandlerEnabled() ||
5386 Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) {
5387 DiagnosticInfoUnsupported NoTrap(MF.getFunction(),
5388 "debugtrap handler not supported",
5389 Op.getDebugLoc(),
5390 DS_Warning);
5391 LLVMContext &Ctx = MF.getFunction().getContext();
5392 Ctx.diagnose(NoTrap);
5393 return Chain;
5394 }
5395
5396 uint64_t TrapID = static_cast<uint64_t>(GCNSubtarget::TrapID::LLVMAMDHSADebugTrap);
5397 SDValue Ops[] = {
5398 Chain,
5399 DAG.getTargetConstant(TrapID, SL, MVT::i16)
5400 };
5401 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
5402}
5403
5404SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
5405 SelectionDAG &DAG) const {
5406 // FIXME: Use inline constants (src_{shared, private}_base) instead.
5407 if (Subtarget->hasApertureRegs()) {
5408 unsigned Offset = AS == AMDGPUAS::LOCAL_ADDRESS ?
5409 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE :
5410 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE;
5411 unsigned WidthM1 = AS == AMDGPUAS::LOCAL_ADDRESS ?
5412 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
5413 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
5414 unsigned Encoding =
5415 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
5416 Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
5417 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
5418
5419 SDValue EncodingImm = DAG.getTargetConstant(Encoding, DL, MVT::i16);
5420 SDValue ApertureReg = SDValue(
5421 DAG.getMachineNode(AMDGPU::S_GETREG_B32, DL, MVT::i32, EncodingImm), 0);
5422 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32);
5423 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);
5424 }
5425
5426 MachineFunction &MF = DAG.getMachineFunction();
5427 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5428 Register UserSGPR = Info->getQueuePtrUserSGPR();
5429 if (UserSGPR == AMDGPU::NoRegister) {
5430 // We probably are in a function incorrectly marked with
5431 // amdgpu-no-queue-ptr. This is undefined.
5432 return DAG.getUNDEF(MVT::i32);
5433 }
5434
5435 SDValue QueuePtr = CreateLiveInRegister(
5436 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
5437
5438 // Offset into amd_queue_t for group_segment_aperture_base_hi /
5439 // private_segment_aperture_base_hi.
5440 uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
5441
5442 SDValue Ptr =
5443 DAG.getObjectPtrOffset(DL, QueuePtr, TypeSize::Fixed(StructOffset));
5444
5445 // TODO: Use custom target PseudoSourceValue.
5446 // TODO: We should use the value from the IR intrinsic call, but it might not
5447 // be available and how do we get it?
5448 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
5449 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,
5450 commonAlignment(Align(64), StructOffset),
5451 MachineMemOperand::MODereferenceable |
5452 MachineMemOperand::MOInvariant);
5453}
5454
5455SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
5456 SelectionDAG &DAG) const {
5457 SDLoc SL(Op);
5458 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
5459
5460 SDValue Src = ASC->getOperand(0);
5461 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64);
5462
5463 const AMDGPUTargetMachine &TM =
5464 static_cast<const AMDGPUTargetMachine &>(getTargetMachine());
5465
5466 // flat -> local/private
5467 if (ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
5468 unsigned DestAS = ASC->getDestAddressSpace();
5469
5470 if (DestAS == AMDGPUAS::LOCAL_ADDRESS ||
5471 DestAS == AMDGPUAS::PRIVATE_ADDRESS) {
5472 unsigned NullVal = TM.getNullPointerValue(DestAS);
5473 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
5474 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE);
5475 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
5476
5477 return DAG.getNode(ISD::SELECT, SL, MVT::i32,
5478 NonNull, Ptr, SegmentNullPtr);
5479 }
5480 }
5481
5482 // local/private -> flat
5483 if (ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
5484 unsigned SrcAS = ASC->getSrcAddressSpace();
5485
5486 if (SrcAS == AMDGPUAS::LOCAL_ADDRESS ||
5487 SrcAS == AMDGPUAS::PRIVATE_ADDRESS) {
5488 unsigned NullVal = TM.getNullPointerValue(SrcAS);
5489 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
5490
5491 SDValue NonNull
5492 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE);
5493
5494 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), SL, DAG);
5495 SDValue CvtPtr
5496 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture);
5497
5498 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull,
5499 DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr),
5500 FlatNullPtr);
5501 }
5502 }
5503
5504 if (ASC->getDestAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT &&
5505 Src.getValueType() == MVT::i64)
5506 return DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
5507
5508 // global <-> flat are no-ops and never emitted.
5509
5510 const MachineFunction &MF = DAG.getMachineFunction();
5511 DiagnosticInfoUnsupported InvalidAddrSpaceCast(
5512 MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc());
5513 DAG.getContext()->diagnose(InvalidAddrSpaceCast);
5514
5515 return DAG.getUNDEF(ASC->getValueType(0));
5516}
5517
5518// This lowers an INSERT_SUBVECTOR by extracting the individual elements from
5519// the small vector and inserting them into the big vector. That is better than
5520// the default expansion of doing it via a stack slot. Even though the use of
5521// the stack slot would be optimized away afterwards, the stack slot itself
5522// remains.
5523SDValue SITargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
5524 SelectionDAG &DAG) const {
5525 SDValue Vec = Op.getOperand(0);
5526 SDValue Ins = Op.getOperand(1);
5527 SDValue Idx = Op.getOperand(2);
5528 EVT VecVT = Vec.getValueType();
5529 EVT InsVT = Ins.getValueType();
5530 EVT EltVT = VecVT.getVectorElementType();
5531 unsigned InsNumElts = InsVT.getVectorNumElements();
5532 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
5533 SDLoc SL(Op);
5534
5535 for (unsigned I = 0; I != InsNumElts; ++I) {
5536 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Ins,
5537 DAG.getConstant(I, SL, MVT::i32));
5538 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt,
5539 DAG.getConstant(IdxVal + I, SL, MVT::i32));
5540 }
5541 return Vec;
5542}
5543
5544SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
5545 SelectionDAG &DAG) const {
5546 SDValue Vec = Op.getOperand(0);
5547 SDValue InsVal = Op.getOperand(1);
5548 SDValue Idx = Op.getOperand(2);
5549 EVT VecVT = Vec.getValueType();
5550 EVT EltVT = VecVT.getVectorElementType();
5551 unsigned VecSize = VecVT.getSizeInBits();
5552 unsigned EltSize = EltVT.getSizeInBits();
5553
5554
5555 assert(VecSize <= 64)(static_cast <bool> (VecSize <= 64) ? void (0) : __assert_fail
("VecSize <= 64", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5555, __extension__ __PRETTY_FUNCTION__))
;
5556
5557 unsigned NumElts = VecVT.getVectorNumElements();
5558 SDLoc SL(Op);
5559 auto KIdx = dyn_cast<ConstantSDNode>(Idx);
5560
5561 if (NumElts == 4 && EltSize == 16 && KIdx) {
5562 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec);
5563
5564 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
5565 DAG.getConstant(0, SL, MVT::i32));
5566 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
5567 DAG.getConstant(1, SL, MVT::i32));
5568
5569 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf);
5570 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf);
5571
5572 unsigned Idx = KIdx->getZExtValue();
5573 bool InsertLo = Idx < 2;
5574 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16,
5575 InsertLo ? LoVec : HiVec,
5576 DAG.getNode(ISD::BITCAST, SL, MVT::i16, InsVal),
5577 DAG.getConstant(InsertLo ? Idx : (Idx - 2), SL, MVT::i32));
5578
5579 InsHalf = DAG.getNode(ISD::BITCAST, SL, MVT::i32, InsHalf);
5580
5581 SDValue Concat = InsertLo ?
5582 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) :
5583 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf });
5584
5585 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
5586 }
5587
5588 if (isa<ConstantSDNode>(Idx))
5589 return SDValue();
5590
5591 MVT IntVT = MVT::getIntegerVT(VecSize);
5592
5593 // Avoid stack access for dynamic indexing.
5594 // v_bfi_b32 (v_bfm_b32 16, (shl idx, 16)), val, vec
5595
5596 // Create a congruent vector with the target value in each element so that
5597 // the required element can be masked and ORed into the target vector.
5598 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT,
5599 DAG.getSplatBuildVector(VecVT, SL, InsVal));
5600
5601 assert(isPowerOf2_32(EltSize))(static_cast <bool> (isPowerOf2_32(EltSize)) ? void (0)
: __assert_fail ("isPowerOf2_32(EltSize)", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5601, __extension__ __PRETTY_FUNCTION__))
;
5602 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
5603
5604 // Convert vector index to bit-index.
5605 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
5606
5607 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
5608 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT,
5609 DAG.getConstant(0xffff, SL, IntVT),
5610 ScaledIdx);
5611
5612 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal);
5613 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT,
5614 DAG.getNOT(SL, BFM, IntVT), BCVec);
5615
5616 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS);
5617 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI);
5618}
5619
5620SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
5621 SelectionDAG &DAG) const {
5622 SDLoc SL(Op);
5623
5624 EVT ResultVT = Op.getValueType();
5625 SDValue Vec = Op.getOperand(0);
5626 SDValue Idx = Op.getOperand(1);
5627 EVT VecVT = Vec.getValueType();
5628 unsigned VecSize = VecVT.getSizeInBits();
5629 EVT EltVT = VecVT.getVectorElementType();
5630 assert(VecSize <= 64)(static_cast <bool> (VecSize <= 64) ? void (0) : __assert_fail
("VecSize <= 64", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5630, __extension__ __PRETTY_FUNCTION__))
;
5631
5632 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
5633
5634 // Make sure we do any optimizations that will make it easier to fold
5635 // source modifiers before obscuring it with bit operations.
5636
5637 // XXX - Why doesn't this get called when vector_shuffle is expanded?
5638 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
5639 return Combined;
5640
5641 unsigned EltSize = EltVT.getSizeInBits();
5642 assert(isPowerOf2_32(EltSize))(static_cast <bool> (isPowerOf2_32(EltSize)) ? void (0)
: __assert_fail ("isPowerOf2_32(EltSize)", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5642, __extension__ __PRETTY_FUNCTION__))
;
5643
5644 MVT IntVT = MVT::getIntegerVT(VecSize);
5645 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
5646
5647 // Convert vector index to bit-index (* EltSize)
5648 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
5649
5650 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
5651 SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx);
5652
5653 if (ResultVT == MVT::f16) {
5654 SDValue Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Elt);
5655 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
5656 }
5657
5658 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT);
5659}
5660
5661static bool elementPairIsContiguous(ArrayRef<int> Mask, int Elt) {
5662 assert(Elt % 2 == 0)(static_cast <bool> (Elt % 2 == 0) ? void (0) : __assert_fail
("Elt % 2 == 0", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5662, __extension__ __PRETTY_FUNCTION__))
;
5663 return Mask[Elt + 1] == Mask[Elt] + 1 && (Mask[Elt] % 2 == 0);
5664}
5665
5666SDValue SITargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
5667 SelectionDAG &DAG) const {
5668 SDLoc SL(Op);
5669 EVT ResultVT = Op.getValueType();
5670 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
5671
5672 EVT PackVT = ResultVT.isInteger() ? MVT::v2i16 : MVT::v2f16;
5673 EVT EltVT = PackVT.getVectorElementType();
5674 int SrcNumElts = Op.getOperand(0).getValueType().getVectorNumElements();
5675
5676 // vector_shuffle <0,1,6,7> lhs, rhs
5677 // -> concat_vectors (extract_subvector lhs, 0), (extract_subvector rhs, 2)
5678 //
5679 // vector_shuffle <6,7,2,3> lhs, rhs
5680 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 2)
5681 //
5682 // vector_shuffle <6,7,0,1> lhs, rhs
5683 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 0)
5684
5685 // Avoid scalarizing when both halves are reading from consecutive elements.
5686 SmallVector<SDValue, 4> Pieces;
5687 for (int I = 0, N = ResultVT.getVectorNumElements(); I != N; I += 2) {
5688 if (elementPairIsContiguous(SVN->getMask(), I)) {
5689 const int Idx = SVN->getMaskElt(I);
5690 int VecIdx = Idx < SrcNumElts ? 0 : 1;
5691 int EltIdx = Idx < SrcNumElts ? Idx : Idx - SrcNumElts;
5692 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL,
5693 PackVT, SVN->getOperand(VecIdx),
5694 DAG.getConstant(EltIdx, SL, MVT::i32));
5695 Pieces.push_back(SubVec);
5696 } else {
5697 const int Idx0 = SVN->getMaskElt(I);
5698 const int Idx1 = SVN->getMaskElt(I + 1);
5699 int VecIdx0 = Idx0 < SrcNumElts ? 0 : 1;
5700 int VecIdx1 = Idx1 < SrcNumElts ? 0 : 1;
5701 int EltIdx0 = Idx0 < SrcNumElts ? Idx0 : Idx0 - SrcNumElts;
5702 int EltIdx1 = Idx1 < SrcNumElts ? Idx1 : Idx1 - SrcNumElts;
5703
5704 SDValue Vec0 = SVN->getOperand(VecIdx0);
5705 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
5706 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32));
5707
5708 SDValue Vec1 = SVN->getOperand(VecIdx1);
5709 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
5710 Vec1, DAG.getConstant(EltIdx1, SL, MVT::i32));
5711 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 }));
5712 }
5713 }
5714
5715 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces);
5716}
5717
5718SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
5719 SelectionDAG &DAG) const {
5720 SDLoc SL(Op);
5721 EVT VT = Op.getValueType();
5722
5723 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
5724 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2);
5725
5726 // Turn into pair of packed build_vectors.
5727 // TODO: Special case for constants that can be materialized with s_mov_b64.
5728 SDValue Lo = DAG.getBuildVector(HalfVT, SL,
5729 { Op.getOperand(0), Op.getOperand(1) });
5730 SDValue Hi = DAG.getBuildVector(HalfVT, SL,
5731 { Op.getOperand(2), Op.getOperand(3) });
5732
5733 SDValue CastLo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Lo);
5734 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Hi);
5735
5736 SDValue Blend = DAG.getBuildVector(MVT::v2i32, SL, { CastLo, CastHi });
5737 return DAG.getNode(ISD::BITCAST, SL, VT, Blend);
5738 }
5739
5740 assert(VT == MVT::v2f16 || VT == MVT::v2i16)(static_cast <bool> (VT == MVT::v2f16 || VT == MVT::v2i16
) ? void (0) : __assert_fail ("VT == MVT::v2f16 || VT == MVT::v2i16"
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5740, __extension__ __PRETTY_FUNCTION__))
;
5741 assert(!Subtarget->hasVOP3PInsts() && "this should be legal")(static_cast <bool> (!Subtarget->hasVOP3PInsts() &&
"this should be legal") ? void (0) : __assert_fail ("!Subtarget->hasVOP3PInsts() && \"this should be legal\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5741, __extension__ __PRETTY_FUNCTION__))
;
5742
5743 SDValue Lo = Op.getOperand(0);
5744 SDValue Hi = Op.getOperand(1);
5745
5746 // Avoid adding defined bits with the zero_extend.
5747 if (Hi.isUndef()) {
5748 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
5749 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo);
5750 return DAG.getNode(ISD::BITCAST, SL, VT, ExtLo);
5751 }
5752
5753 Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Hi);
5754 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi);
5755
5756 SDValue ShlHi = DAG.getNode(ISD::SHL, SL, MVT::i32, Hi,
5757 DAG.getConstant(16, SL, MVT::i32));
5758 if (Lo.isUndef())
5759 return DAG.getNode(ISD::BITCAST, SL, VT, ShlHi);
5760
5761 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
5762 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);
5763
5764 SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi);
5765 return DAG.getNode(ISD::BITCAST, SL, VT, Or);
5766}
5767
5768bool
5769SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5770 // We can fold offsets for anything that doesn't require a GOT relocation.
5771 return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
5772 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
5773 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
5774 !shouldEmitGOTReloc(GA->getGlobal());
5775}
5776
5777static SDValue
5778buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
5779 const SDLoc &DL, int64_t Offset, EVT PtrVT,
5780 unsigned GAFlags = SIInstrInfo::MO_NONE) {
5781 assert(isInt<32>(Offset + 4) && "32-bit offset is expected!")(static_cast <bool> (isInt<32>(Offset + 4) &&
"32-bit offset is expected!") ? void (0) : __assert_fail ("isInt<32>(Offset + 4) && \"32-bit offset is expected!\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5781, __extension__ __PRETTY_FUNCTION__))
;
5782 // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
5783 // lowered to the following code sequence:
5784 //
5785 // For constant address space:
5786 // s_getpc_b64 s[0:1]
5787 // s_add_u32 s0, s0, $symbol
5788 // s_addc_u32 s1, s1, 0
5789 //
5790 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5791 // a fixup or relocation is emitted to replace $symbol with a literal
5792 // constant, which is a pc-relative offset from the encoding of the $symbol
5793 // operand to the global variable.
5794 //
5795 // For global address space:
5796 // s_getpc_b64 s[0:1]
5797 // s_add_u32 s0, s0, $symbol@{gotpc}rel32@lo
5798 // s_addc_u32 s1, s1, $symbol@{gotpc}rel32@hi
5799 //
5800 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5801 // fixups or relocations are emitted to replace $symbol@*@lo and
5802 // $symbol@*@hi with lower 32 bits and higher 32 bits of a literal constant,
5803 // which is a 64-bit pc-relative offset from the encoding of the $symbol
5804 // operand to the global variable.
5805 //
5806 // What we want here is an offset from the value returned by s_getpc
5807 // (which is the address of the s_add_u32 instruction) to the global
5808 // variable, but since the encoding of $symbol starts 4 bytes after the start
5809 // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
5810 // small. This requires us to add 4 to the global variable offset in order to
5811 // compute the correct address. Similarly for the s_addc_u32 instruction, the
5812 // encoding of $symbol starts 12 bytes after the start of the s_add_u32
5813 // instruction.
5814 SDValue PtrLo =
5815 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags);
5816 SDValue PtrHi;
5817 if (GAFlags == SIInstrInfo::MO_NONE) {
5818 PtrHi = DAG.getTargetConstant(0, DL, MVT::i32);
5819 } else {
5820 PtrHi =
5821 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 12, GAFlags + 1);
5822 }
5823 return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, PtrLo, PtrHi);
5824}
5825
5826SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
5827 SDValue Op,
5828 SelectionDAG &DAG) const {
5829 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
5830 SDLoc DL(GSD);
5831 EVT PtrVT = Op.getValueType();
5832
5833 const GlobalValue *GV = GSD->getGlobal();
5834 if ((GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
5835 shouldUseLDSConstAddress(GV)) ||
5836 GSD->getAddressSpace() == AMDGPUAS::REGION_ADDRESS ||
5837 GSD->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
5838 if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
5839 GV->hasExternalLinkage()) {
5840 Type *Ty = GV->getValueType();
5841 // HIP uses an unsized array `extern __shared__ T s[]` or similar
5842 // zero-sized type in other languages to declare the dynamic shared
5843 // memory which size is not known at the compile time. They will be
5844 // allocated by the runtime and placed directly after the static
5845 // allocated ones. They all share the same offset.
5846 if (DAG.getDataLayout().getTypeAllocSize(Ty).isZero()) {
5847 assert(PtrVT == MVT::i32 && "32-bit pointer is expected.")(static_cast <bool> (PtrVT == MVT::i32 && "32-bit pointer is expected."
) ? void (0) : __assert_fail ("PtrVT == MVT::i32 && \"32-bit pointer is expected.\""
, "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5847, __extension__ __PRETTY_FUNCTION__))
;
5848 // Adjust alignment for that dynamic shared memory array.
5849 MFI->setDynLDSAlign(DAG.getDataLayout(), *cast<GlobalVariable>(GV));
5850 return SDValue(
5851 DAG.getMachineNode(AMDGPU::GET_GROUPSTATICSIZE, DL, PtrVT), 0);
5852 }
5853 }
5854 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
5855 }
5856
5857 if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
5858 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, GSD->getOffset(),
5859 SIInstrInfo::MO_ABS32_LO);
5860 return DAG.getNode(AMDGPUISD::LDS, DL, MVT::i32, GA);
5861 }
5862
5863 if (shouldEmitFixup(GV))
5864 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
5865 else if (shouldEmitPCReloc(GV))
5866 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
5867 SIInstrInfo::MO_REL32);
5868
5869 SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
5870 SIInstrInfo::MO_GOTPCREL32);
5871
5872 Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
5873 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
5874 const DataLayout &DataLayout = DAG.getDataLayout();
5875 Align Alignment = DataLayout.getABITypeAlign(PtrTy);
5876 MachinePointerInfo PtrInfo
5877 = MachinePointerInfo::getGOT(DAG.getMachineFunction());
5878
5879 return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Alignment,
5880 MachineMemOperand::MODereferenceable |
5881 MachineMemOperand::MOInvariant);
5882}
5883
5884SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
5885 const SDLoc &DL, SDValue V) const {
5886 // We can't use S_MOV_B32 directly, because there is no way to specify m0 as
5887 // the destination register.
5888 //
5889 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
5890 // so we will end up with redundant moves to m0.
5891 //
5892 // We use a pseudo to ensure we emit s_mov_b32 with m0 as the direct result.
5893
5894 // A Null SDValue creates a glue result.
5895 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue,
5896 V, Chain);
5897 return SDValue(M0, 0);
5898}
5899
5900SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
5901 SDValue Op,
5902 MVT VT,
5903 unsigned Offset) const {
5904 SDLoc SL(Op);
5905 SDValue Param = lowerKernargMemParameter(
5906 DAG, MVT::i32, MVT::i32, SL, DAG.getEntryNode(), Offset, Align(4), false);
5907 // The local size values will have the hi 16-bits as zero.
5908 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
5909 DAG.getValueType(VT));
5910}
5911
5912static SDValue emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5913 EVT VT) {
5914 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5915 "non-hsa intrinsic with hsa target",
5916 DL.getDebugLoc());
5917 DAG.getContext()->diagnose(BadIntrin);
5918 return DAG.getUNDEF(VT);
5919}
5920
5921static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5922 EVT VT) {
5923 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5924 "intrinsic not supported on subtarget",
5925 DL.getDebugLoc());
5926 DAG.getContext()->diagnose(BadIntrin);
5927 return DAG.getUNDEF(VT);
5928}
5929
5930static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
5931 ArrayRef<SDValue> Elts) {
5932 assert(!Elts.empty())(static_cast <bool> (!Elts.empty()) ? void (0) : __assert_fail
("!Elts.empty()", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5932, __extension__ __PRETTY_FUNCTION__))
;
5933 MVT Type;
5934 unsigned NumElts = Elts.size();
5935
5936 if (NumElts <= 8) {
5937 Type = MVT::getVectorVT(MVT::f32, NumElts);
5938 } else {
5939 assert(Elts.size() <= 16)(static_cast <bool> (Elts.size() <= 16) ? void (0) :
__assert_fail ("Elts.size() <= 16", "/build/llvm-toolchain-snapshot-14~++20211110111138+cffbfd01e37b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5939, __extension__ __PRETTY_FUNCTION__))
;
5940 Type = MVT::v16f32;
5941 NumElts = 16;
5942 }
5943
5944 SmallVector<SDValue, 16> VecElts(NumElts);
5945 for (unsigned i = 0; i < Elts.size(); ++i) {
5946 SDValue Elt = Elts[i];
5947 if (Elt.getValueType() != MVT::f32)
5948 Elt = DAG.getBitcast(MVT::f32, Elt);
5949 VecElts[i] = Elt;
5950 }
5951 for (unsigned i = Elts.size(); i < NumElts; ++i)
5952 VecElts[i] = DAG.getUNDEF(MVT::f32);
5953
5954 if (NumElts == 1)
5955 return VecElts[0];
5956 return DAG.getBuildVector(Type, DL, VecElts);
5957}
5958
5959static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT,
5960 SDValue Src, int ExtraElts) {
5961 EVT SrcVT = Src.getValueType();
5962
5963 SmallVector<SDValue, 8> Elts;
5964
5965 if (SrcVT.isVector())
5966 DAG.ExtractVectorElements(Src, Elts);
5967 else
5968 Elts.push_back(Src);
5969
5970 SDValue Undef = DAG.getUNDEF(SrcVT.getScalarType());
5971 while (ExtraElts--)
5972 Elts.push_back(Undef);
5973
5974 return DAG.getBuildVector(CastVT, DL, Elts);
5975}
5976
5977// Re-construct the required return value for a image load intrinsic.
5978// This is more complicated due to the optional use TexFailCtrl which means the required
5979// return type is an aggregate
5980static SDValue constructRetValue(SelectionDAG &DAG,
5981 MachineSDNode *Result,
5982 ArrayRef<EVT> ResultTypes,
5983 bool IsTexFail, bool Unpacked, bool IsD16,
5984 int DMaskPop, int NumVDataDwords,
5985 const SDLoc &DL) {
5986 // Determine the required return type. This is the same regardless of IsTexFail flag
5987 EVT ReqRetVT = ResultTypes[0];
5988 int ReqRetNumElts = ReqRetVT.isVector() ? ReqRetVT.getVectorNumElements() : 1;
5989 int NumDataDwords = (!IsD16 || (IsD16 && Unpacked)) ?
5990 ReqRetNumElts : (ReqRetNumElts + 1) / 2;
5991
5992 int MaskPopDwords = (!IsD16 || (IsD16 && Unpacked)) ?
5993 DMaskPop : (DMaskPop + 1) / 2;
5994
5995 MVT DataDwordVT = NumDataDwords == 1 ?
5996 MVT::i32 : MVT::getVectorVT(MVT::i32, NumDataDwords);
5997
5998 MVT MaskPopVT = MaskPopDwords == 1 ?
5999 MVT::i32 : MVT::getVectorVT(MVT::i32, MaskPopDwords);
6000
6001 SDValue Data(Result, 0);
6002 SDValue TexFail;
6003
6004 if (DMaskPop > 0 && Data.getValueType() != MaskPopVT) {
6005 SDValue ZeroIdx = DAG.getConstant(0, DL, MVT::i32);
6006 if (MaskPopVT.isVector()) {
6007 Data = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MaskPopVT,
6008 SDValue(Result, 0), ZeroIdx);
6009 } else {
6010 Data = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MaskPopVT,
6011 SDValue(Result, 0), ZeroIdx);
6012 }
6013 }
6014
6015 if (DataDwordVT.isVector())
6016 Data = padEltsToUndef(DAG, DL, DataDwordVT, Data,
6017 NumDataDwords - MaskPopDwords);
6018
6019 if (IsD16)
6020 Data = adjustLoadValueTypeImpl(Data, ReqRetVT, DL, DAG, Unpacked);
6021
6022 EVT LegalReqRetVT = ReqRetVT;
6023 if (!ReqRetVT.isVector()) {
6024 if (!Data.getValueType().isInteger())
6025 Data = DAG.getNode(ISD::BITCAST, DL,
6026 Data.getValueType().changeTypeToInteger(), Data);
6027 Data = DAG.getNode(ISD::TRUNCATE, DL, ReqRetVT.changeTypeToInteger(), Data);
6028 } else {
6029 // We need to widen the return vector to a legal type
6030 if ((ReqRetVT.getVectorNumElements() % 2) == 1 &&
6031 ReqRetVT.getVectorElementType().getSizeInBits() == 16) {
6032 LegalReqRetVT =
6033 EVT::getVectorVT(*DAG.getContext(), ReqRetVT.getVectorElementType(),
6034 ReqRetVT.getVectorNumElements() + 1);
6035 }
6036 }
6037 Data = DAG.getNode(ISD::BITCAST, DL, LegalReqRetVT, Data);
6038
6039 if (IsTexFail) {
6040 TexFail =
6041 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, SDValue(Result, 0),
6042 DAG.getConstant(MaskPopDwords, DL, MVT::i32));
6043
6044 return DAG.getMergeValues({Data, TexFail, SDValue(Result, 1)}, DL);
6045 }
6046
6047 if (Result->getNumValues() == 1)
6048 return Data;
6049
6050 return DAG.getMergeValues({Data, SDValue(Result, 1)}, DL);
6051}
6052
6053static bool parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE,
6054 SDValue *LWE, bool &IsTexFail) {
6055 auto TexFailCtrlConst = cast<ConstantSDNode>(TexFailCtrl.getNode());
6056
6057 uint64_t Value = TexFailCtrlConst->getZExtValue();
6058 if (Value) {
6059 IsTexFail = true;
6060 }
6061
6062 SDLoc DL(TexFailCtrlConst);
6063 *TFE = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
6064 Value &= ~(uint64_t)0x1;
6065 *LWE = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
6066 Value &= ~(uint64_t)0x2;
6067
6068 return Value == 0;
6069}
6070
6071static void packImage16bitOpsToDwords(SelectionDAG &DAG, SDValue Op,
6072 MVT PackVectorVT,
6073 SmallVectorImpl<SDValue> &PackedAddrs,
6074 unsigned DimIdx, unsigned EndIdx,
6075 unsigned NumGradients) {
6076 SDLoc DL(Op);
6077 for (unsigned I = DimIdx; I < EndIdx; I++) {
6078 SDValue Addr = Op.getOperand(I);
6079
6080 // Gradients are packed with undef for each coordinate.
6081 // In <hi 16 bit>,<lo 16 bit> notation, the registers look like this:
6082 // 1D: undef,dx/dh; undef,dx/dv
6083 // 2D: dy/dh,dx/dh; dy/dv,dx/dv
6084 // 3D: dy/dh,dx/dh; undef,dz/dh; dy/dv,dx/dv; undef,dz/dv
6085 if (((I + 1) >= EndIdx) ||
6086 ((NumGradients / 2) % 2 == 1 && (I == DimIdx + (NumGradients / 2) - 1 ||
6087 I == DimIdx + NumGradients - 1))) {
6088 if (Addr.getValueType() != MVT::i16)
6089 Addr = DAG.getBitcast(MVT::i16, Addr);
6090 Addr = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Addr);
6091 } else {
6092 Addr = DAG.getBuildVector(PackVectorVT, DL, {Addr, Op.getOperand(I + 1)});
6093 I++;
6094 }
6095 Addr = DAG.getBitcast(MVT::f32, Addr);
6096 PackedAddrs.push_back(Addr);
6097 }
6098}
6099
6100SDValue SITargetLowering::lowerImage(SDValue Op,
6101 const AMDGPU::ImageDimIntrinsicInfo *Intr,
6102 SelectionDAG &DAG, bool WithChain) const {
6103 SDLoc DL(Op);
6104 MachineFunction &MF = DAG.getMachineFunction();
6105 const GCNSubtarget* ST = &MF.getSubtarget<GCNSubtarget>();
6106 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
6107 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
6108 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfo(Intr->Dim);
6109 const AMDGPU::MIMGLZMappingInfo *LZMappingInfo =
6110 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
6111 const AMDGPU::MIMGMIPMappingInfo *MIPMappingInfo =
6112 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
6113 unsigned IntrOpcode = Intr->BaseOpcode;
6114 bool IsGFX10Plus = AMDGPU::isGFX10Plus(*Subtarget);
6115
6116 SmallVector<EVT, 3> ResultTypes(Op->values());
6117 SmallVector<EVT, 3> OrigResultTypes(Op->values());
6118 bool IsD16 = false;
6119 bool IsG16 = false;
6120 bool IsA16 = false;
6121 SDValue VData;
6122 int NumVDataDwords;
6123 bool AdjustRetType = false;
6124
6125 // Offset of intrinsic arguments
6126 const unsigned ArgOffset = WithChain ? 2 : 1;
6127
6128 unsigned DMask;
6129 unsigned DMaskLanes = 0;
6130
6131 if (BaseOpcode->Atomic) {
6132 VData = Op.getOperand(2);
6133
6134 bool Is64Bit = VData.getValueType() == MVT::i64;
6135 if (BaseOpcode->AtomicX2) {
6136 SDValue VData2 = Op.getOperand(3);
6137 VData = DAG.getBuildVector(Is64Bit ? MVT::v2i64 : MVT::v2i32, DL,
6138 {VData, VData2});
6139 if (Is64Bit)
6140 VData = DAG.getBitcast(MVT::v4i32, VData);
6141
6142 ResultTypes[0] = Is64Bit ? MVT::v2i64 : MVT::v2i32;
6143 DMask = Is64Bit ? 0xf : 0x3;
6144 NumVDataDwords = Is64Bit ? 4 : 2;
6145 } else {
6146 DMask = Is64Bit ? 0x3 : 0x1;
6147 NumVDataDwords = Is64Bit ? 2 : 1;
6148 }
6149 } else {
6150 auto *DMaskConst =
6151 cast<ConstantSDNode>(Op.getOperand(ArgOffset + Intr->DMaskIndex));
6152 DMask = DMaskConst->getZExtValue();
6153 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask);
6154
6155 if (BaseOpcode->Store) {
6156 VData = Op.getOperand(2);
6157
6158 MVT StoreVT = VData.getSimpleValueType();
6159 if (StoreVT.getScalarType() == MVT::f16) {
6160 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
6161 return Op; // D16 is unsupported for this instruction
6162
6163 IsD16 = true;
6164 VData = handleD16VData(VData, DAG, true);
6165 }
6166
6167 NumVDataDwords = (VData.getValueType().getSizeInBits() + 31) / 32;
6168 } else {
6169 // Work out the num dwords based on the dmask popcount and underlying type
6170 // and whether packing is supported.
6171 MVT LoadVT = ResultTypes[0].getSimpleVT();
6172 if (LoadVT.getScalarType() == MVT::f16) {
6173 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
6174 return Op; // D16 is unsupported for this instruction
6175
6176 IsD16 = true;
6177 }
6178
6179 // Confirm that the return type is large enough for the dmask specified
6180 if ((LoadVT.isVector() && LoadVT.getVectorNumElements() < DMaskLanes) ||
6181 (!LoadVT.isVector() && DMaskLanes > 1))
6182 return Op;
6183
6184 // The sq block of gfx8 and gfx9 do not estimate register use correctly
6185 // for d16 image_gather4, image_gather4_l, and image_gather4_lz
6186 // instructions.
6187 if (IsD16 && !Subtarget->hasUnpackedD16VMem() &&
6188 !(BaseOpcode->Gather4 && Subtarget->hasImageGather4D16Bug()))
6189 NumVDataDwords = (DMaskLanes + 1) / 2;
6190 else
6191 NumVDataDwords = DMaskLanes;
6192
6193 AdjustRetType = true;
6194 }
6195 }
6196
6197 unsigned VAddrEnd = ArgOffset + Intr->VAddrEnd;
6198 SmallVector<SDValue, 4> VAddrs;
6199
6200