Bug Summary

File:llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Warning:line 11278, column 52
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name SIISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -funwind-tables=2 -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -ffunction-sections -fdata-sections -fcoverage-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm/tools/clang/stage2-bins -resource-dir /usr/lib/llvm-14/lib/clang/14.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/lib/Target/AMDGPU -I include -I /build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/include -D _FORTIFY_SOURCE=2 -D NDEBUG -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/x86_64-linux-gnu/c++/10 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../include/c++/10/backward -internal-isystem /usr/lib/llvm-14/lib/clang/14.0.0/include -internal-isystem /usr/local/include -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/10/../../../../x86_64-linux-gnu/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fmacro-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/= -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fcoverage-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/= -O3 -Wno-unused-command-line-argument -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-redundant-move -Wno-pessimizing-move -Wno-noexcept-type -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/build-llvm/tools/clang/stage2-bins=build-llvm/tools/clang/stage2-bins -fdebug-prefix-map=/build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/= -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fcolor-diagnostics -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /tmp/scan-build-2022-01-19-134126-35450-1 -x c++ /build/llvm-toolchain-snapshot-14~++20220119111520+da61cb019eb2/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
<
1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Custom DAG lowering for SI
11//
12//===----------------------------------------------------------------------===//
13
14#include "SIISelLowering.h"
15#include "AMDGPU.h"
16#include "AMDGPUInstrInfo.h"
17#include "AMDGPUTargetMachine.h"
18#include "SIMachineFunctionInfo.h"
19#include "SIRegisterInfo.h"
20#include "llvm/ADT/Statistic.h"
21#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
22#include "llvm/Analysis/OptimizationRemarkEmitter.h"
23#include "llvm/BinaryFormat/ELF.h"
24#include "llvm/CodeGen/Analysis.h"
25#include "llvm/CodeGen/FunctionLoweringInfo.h"
26#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
27#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineLoopInfo.h"
30#include "llvm/IR/DiagnosticInfo.h"
31#include "llvm/IR/IntrinsicInst.h"
32#include "llvm/IR/IntrinsicsAMDGPU.h"
33#include "llvm/IR/IntrinsicsR600.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/KnownBits.h"
36
37using namespace llvm;
38
39#define DEBUG_TYPE"si-lower" "si-lower"
40
41STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"si-lower", "NumTailCalls"
, "Number of tail calls"}
;
42
43static cl::opt<bool> DisableLoopAlignment(
44 "amdgpu-disable-loop-alignment",
45 cl::desc("Do not align and prefetch loops"),
46 cl::init(false));
47
48static cl::opt<bool> UseDivergentRegisterIndexing(
49 "amdgpu-use-divergent-register-indexing",
50 cl::Hidden,
51 cl::desc("Use indirect register addressing for divergent indexes"),
52 cl::init(false));
53
54static bool hasFP32Denormals(const MachineFunction &MF) {
55 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
56 return Info->getMode().allFP32Denormals();
57}
58
59static bool hasFP64FP16Denormals(const MachineFunction &MF) {
60 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
61 return Info->getMode().allFP64FP16Denormals();
62}
63
64static unsigned findFirstFreeSGPR(CCState &CCInfo) {
65 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
66 for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
67 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
68 return AMDGPU::SGPR0 + Reg;
69 }
70 }
71 llvm_unreachable("Cannot allocate sgpr")::llvm::llvm_unreachable_internal("Cannot allocate sgpr", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 71)
;
72}
73
74SITargetLowering::SITargetLowering(const TargetMachine &TM,
75 const GCNSubtarget &STI)
76 : AMDGPUTargetLowering(TM, STI),
77 Subtarget(&STI) {
78 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
79 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
80
81 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
82 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
83
84 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
85
86 const SIRegisterInfo *TRI = STI.getRegisterInfo();
87 const TargetRegisterClass *V64RegClass = TRI->getVGPR64Class();
88
89 addRegisterClass(MVT::f64, V64RegClass);
90 addRegisterClass(MVT::v2f32, V64RegClass);
91
92 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
93 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96));
94
95 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
96 addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
97
98 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
99 addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128));
100
101 addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
102 addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160));
103
104 addRegisterClass(MVT::v6i32, &AMDGPU::SGPR_192RegClass);
105 addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192));
106
107 addRegisterClass(MVT::v3i64, &AMDGPU::SGPR_192RegClass);
108 addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192));
109
110 addRegisterClass(MVT::v7i32, &AMDGPU::SGPR_224RegClass);
111 addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224));
112
113 addRegisterClass(MVT::v8i32, &AMDGPU::SGPR_256RegClass);
114 addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256));
115
116 addRegisterClass(MVT::v4i64, &AMDGPU::SGPR_256RegClass);
117 addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256));
118
119 addRegisterClass(MVT::v16i32, &AMDGPU::SGPR_512RegClass);
120 addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512));
121
122 addRegisterClass(MVT::v8i64, &AMDGPU::SGPR_512RegClass);
123 addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512));
124
125 addRegisterClass(MVT::v16i64, &AMDGPU::SGPR_1024RegClass);
126 addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024));
127
128 if (Subtarget->has16BitInsts()) {
129 addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
130 addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
131
132 // Unless there are also VOP3P operations, not operations are really legal.
133 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
134 addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);
135 addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
136 addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
137 }
138
139 addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
140 addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024));
141
142 computeRegisterProperties(Subtarget->getRegisterInfo());
143
144 // The boolean content concept here is too inflexible. Compares only ever
145 // really produce a 1-bit result. Any copy/extend from these will turn into a
146 // select, and zext/1 or sext/-1 are equally cheap. Arbitrarily choose 0/1, as
147 // it's what most targets use.
148 setBooleanContents(ZeroOrOneBooleanContent);
149 setBooleanVectorContents(ZeroOrOneBooleanContent);
150
151 // We need to custom lower vector stores from local memory
152 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
153 setOperationAction(ISD::LOAD, MVT::v3i32, Custom);
154 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
155 setOperationAction(ISD::LOAD, MVT::v5i32, Custom);
156 setOperationAction(ISD::LOAD, MVT::v6i32, Custom);
157 setOperationAction(ISD::LOAD, MVT::v7i32, Custom);
158 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
159 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
160 setOperationAction(ISD::LOAD, MVT::i1, Custom);
161 setOperationAction(ISD::LOAD, MVT::v32i32, Custom);
162
163 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
164 setOperationAction(ISD::STORE, MVT::v3i32, Custom);
165 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
166 setOperationAction(ISD::STORE, MVT::v5i32, Custom);
167 setOperationAction(ISD::STORE, MVT::v6i32, Custom);
168 setOperationAction(ISD::STORE, MVT::v7i32, Custom);
169 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
170 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
171 setOperationAction(ISD::STORE, MVT::i1, Custom);
172 setOperationAction(ISD::STORE, MVT::v32i32, Custom);
173
174 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
175 setTruncStoreAction(MVT::v3i32, MVT::v3i16, Expand);
176 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
177 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
178 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
179 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand);
180 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Expand);
181 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
182 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Expand);
183 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
184 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Expand);
185 setTruncStoreAction(MVT::v2i16, MVT::v2i8, Expand);
186 setTruncStoreAction(MVT::v4i16, MVT::v4i8, Expand);
187 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
188 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Expand);
189 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Expand);
190
191 setTruncStoreAction(MVT::v3i64, MVT::v3i16, Expand);
192 setTruncStoreAction(MVT::v3i64, MVT::v3i32, Expand);
193 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Expand);
194 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Expand);
195 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Expand);
196 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Expand);
197 setTruncStoreAction(MVT::v16i64, MVT::v16i32, Expand);
198
199 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
200 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
201
202 setOperationAction(ISD::SELECT, MVT::i1, Promote);
203 setOperationAction(ISD::SELECT, MVT::i64, Custom);
204 setOperationAction(ISD::SELECT, MVT::f64, Promote);
205 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
206
207 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
208 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
209 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
210 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
211 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
212
213 setOperationAction(ISD::SETCC, MVT::i1, Promote);
214 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
215 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
216 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
217
218 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
219 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
220 setOperationAction(ISD::TRUNCATE, MVT::v3i32, Expand);
221 setOperationAction(ISD::FP_ROUND, MVT::v3f32, Expand);
222 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Expand);
223 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Expand);
224 setOperationAction(ISD::TRUNCATE, MVT::v5i32, Expand);
225 setOperationAction(ISD::FP_ROUND, MVT::v5f32, Expand);
226 setOperationAction(ISD::TRUNCATE, MVT::v6i32, Expand);
227 setOperationAction(ISD::FP_ROUND, MVT::v6f32, Expand);
228 setOperationAction(ISD::TRUNCATE, MVT::v7i32, Expand);
229 setOperationAction(ISD::FP_ROUND, MVT::v7f32, Expand);
230 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Expand);
231 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Expand);
232 setOperationAction(ISD::TRUNCATE, MVT::v16i32, Expand);
233 setOperationAction(ISD::FP_ROUND, MVT::v16f32, Expand);
234
235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
236 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
237 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
238 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
239 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
240 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v3i16, Custom);
241 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
242 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
243
244 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
245 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
246 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
247 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
248 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
249 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
250
251 setOperationAction(ISD::UADDO, MVT::i32, Legal);
252 setOperationAction(ISD::USUBO, MVT::i32, Legal);
253
254 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
255 setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
256
257 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
258 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
259 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
260
261#if 0
262 setOperationAction(ISD::ADDCARRY, MVT::i64, Legal);
263 setOperationAction(ISD::SUBCARRY, MVT::i64, Legal);
264#endif
265
266 // We only support LOAD/STORE and vector manipulation ops for vectors
267 // with > 4 elements.
268 for (MVT VT : { MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32,
269 MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16,
270 MVT::v3i64, MVT::v3f64, MVT::v6i32, MVT::v6f32,
271 MVT::v4i64, MVT::v4f64, MVT::v8i64, MVT::v8f64,
272 MVT::v16i64, MVT::v16f64, MVT::v32i32, MVT::v32f32 }) {
273 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
274 switch (Op) {
275 case ISD::LOAD:
276 case ISD::STORE:
277 case ISD::BUILD_VECTOR:
278 case ISD::BITCAST:
279 case ISD::EXTRACT_VECTOR_ELT:
280 case ISD::INSERT_VECTOR_ELT:
281 case ISD::EXTRACT_SUBVECTOR:
282 case ISD::SCALAR_TO_VECTOR:
283 break;
284 case ISD::INSERT_SUBVECTOR:
285 case ISD::CONCAT_VECTORS:
286 setOperationAction(Op, VT, Custom);
287 break;
288 default:
289 setOperationAction(Op, VT, Expand);
290 break;
291 }
292 }
293 }
294
295 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand);
296
297 // TODO: For dynamic 64-bit vector inserts/extracts, should emit a pseudo that
298 // is expanded to avoid having two separate loops in case the index is a VGPR.
299
300 // Most operations are naturally 32-bit vector operations. We only support
301 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
302 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
303 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
304 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
305
306 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
307 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
308
309 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
310 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
311
312 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
313 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
314 }
315
316 for (MVT Vec64 : { MVT::v3i64, MVT::v3f64 }) {
317 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
318 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v6i32);
319
320 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
321 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v6i32);
322
323 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
324 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v6i32);
325
326 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
327 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v6i32);
328 }
329
330 for (MVT Vec64 : { MVT::v4i64, MVT::v4f64 }) {
331 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
332 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v8i32);
333
334 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
335 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v8i32);
336
337 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
338 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v8i32);
339
340 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
341 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v8i32);
342 }
343
344 for (MVT Vec64 : { MVT::v8i64, MVT::v8f64 }) {
345 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
346 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v16i32);
347
348 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
349 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v16i32);
350
351 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
352 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v16i32);
353
354 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
355 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v16i32);
356 }
357
358 for (MVT Vec64 : { MVT::v16i64, MVT::v16f64 }) {
359 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
360 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v32i32);
361
362 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
363 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v32i32);
364
365 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
366 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v32i32);
367
368 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
369 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v32i32);
370 }
371
372 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
373 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
374 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
375 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
376
377 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f16, Custom);
378 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
379
380 // Avoid stack access for these.
381 // TODO: Generalize to more vector types.
382 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
383 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
384 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);
385 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);
386
387 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom);
388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom);
389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom);
390 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
391 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
392 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
393
394 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom);
395 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f16, Custom);
396 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
397 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
398
399 // Deal with vec3 vector operations when widened to vec4.
400 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom);
401 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom);
402 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom);
403 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom);
404
405 // Deal with vec5/6/7 vector operations when widened to vec8.
406 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom);
407 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom);
408 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v6i32, Custom);
409 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v6f32, Custom);
410 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v7i32, Custom);
411 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v7f32, Custom);
412 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom);
413 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom);
414
415 // BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
416 // and output demarshalling
417 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
418 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
419
420 // We can't return success/failure, only the old value,
421 // let LLVM add the comparison
422 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
423 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Expand);
424
425 if (Subtarget->hasFlatAddressSpace()) {
426 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
427 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
428 }
429
430 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
431 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
432
433 // FIXME: This should be narrowed to i32, but that only happens if i64 is
434 // illegal.
435 // FIXME: Should lower sub-i32 bswaps to bit-ops without v_perm_b32.
436 setOperationAction(ISD::BSWAP, MVT::i64, Legal);
437 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
438
439 // On SI this is s_memtime and s_memrealtime on VI.
440 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
441 setOperationAction(ISD::TRAP, MVT::Other, Custom);
442 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Custom);
443
444 if (Subtarget->has16BitInsts()) {
445 setOperationAction(ISD::FPOW, MVT::f16, Promote);
446 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
447 setOperationAction(ISD::FLOG, MVT::f16, Custom);
448 setOperationAction(ISD::FEXP, MVT::f16, Custom);
449 setOperationAction(ISD::FLOG10, MVT::f16, Custom);
450 }
451
452 if (Subtarget->hasMadMacF32Insts())
453 setOperationAction(ISD::FMAD, MVT::f32, Legal);
454
455 if (!Subtarget->hasBFI()) {
456 // fcopysign can be done in a single instruction with BFI.
457 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
458 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
459 }
460
461 if (!Subtarget->hasBCNT(32))
462 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
463
464 if (!Subtarget->hasBCNT(64))
465 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
466
467 if (Subtarget->hasFFBH()) {
468 setOperationAction(ISD::CTLZ, MVT::i32, Custom);
469 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
470 }
471
472 if (Subtarget->hasFFBL()) {
473 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
475 }
476
477 // We only really have 32-bit BFE instructions (and 16-bit on VI).
478 //
479 // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
480 // effort to match them now. We want this to be false for i64 cases when the
481 // extraction isn't restricted to the upper or lower half. Ideally we would
482 // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
483 // span the midpoint are probably relatively rare, so don't worry about them
484 // for now.
485 if (Subtarget->hasBFE())
486 setHasExtractBitsInsn(true);
487
488 // Clamp modifier on add/sub
489 if (Subtarget->hasIntClamp()) {
490 setOperationAction(ISD::UADDSAT, MVT::i32, Legal);
491 setOperationAction(ISD::USUBSAT, MVT::i32, Legal);
492 }
493
494 if (Subtarget->hasAddNoCarry()) {
495 setOperationAction(ISD::SADDSAT, MVT::i16, Legal);
496 setOperationAction(ISD::SSUBSAT, MVT::i16, Legal);
497 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
498 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
499 }
500
501 setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
502 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom);
503 setOperationAction(ISD::FMINNUM, MVT::f64, Custom);
504 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom);
505
506
507 // These are really only legal for ieee_mode functions. We should be avoiding
508 // them for functions that don't have ieee_mode enabled, so just say they are
509 // legal.
510 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
511 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
512 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
513 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
514
515
516 if (Subtarget->haveRoundOpsF64()) {
517 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
518 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
519 setOperationAction(ISD::FRINT, MVT::f64, Legal);
520 } else {
521 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
522 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
523 setOperationAction(ISD::FRINT, MVT::f64, Custom);
524 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
525 }
526
527 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
528
529 setOperationAction(ISD::FSIN, MVT::f32, Custom);
530 setOperationAction(ISD::FCOS, MVT::f32, Custom);
531 setOperationAction(ISD::FDIV, MVT::f32, Custom);
532 setOperationAction(ISD::FDIV, MVT::f64, Custom);
533
534 if (Subtarget->has16BitInsts()) {
535 setOperationAction(ISD::Constant, MVT::i16, Legal);
536
537 setOperationAction(ISD::SMIN, MVT::i16, Legal);
538 setOperationAction(ISD::SMAX, MVT::i16, Legal);
539
540 setOperationAction(ISD::UMIN, MVT::i16, Legal);
541 setOperationAction(ISD::UMAX, MVT::i16, Legal);
542
543 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
544 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
545
546 setOperationAction(ISD::ROTR, MVT::i16, Expand);
547 setOperationAction(ISD::ROTL, MVT::i16, Expand);
548
549 setOperationAction(ISD::SDIV, MVT::i16, Promote);
550 setOperationAction(ISD::UDIV, MVT::i16, Promote);
551 setOperationAction(ISD::SREM, MVT::i16, Promote);
552 setOperationAction(ISD::UREM, MVT::i16, Promote);
553 setOperationAction(ISD::UADDSAT, MVT::i16, Legal);
554 setOperationAction(ISD::USUBSAT, MVT::i16, Legal);
555
556 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
557
558 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
559 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
560 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
561 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
562 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
563
564 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
565
566 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
567
568 setOperationAction(ISD::LOAD, MVT::i16, Custom);
569
570 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
571
572 setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote);
573 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
574 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
575 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
576
577 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Custom);
578 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Custom);
579
580 // F16 - Constant Actions.
581 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
582
583 // F16 - Load/Store Actions.
584 setOperationAction(ISD::LOAD, MVT::f16, Promote);
585 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
586 setOperationAction(ISD::STORE, MVT::f16, Promote);
587 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
588
589 // F16 - VOP1 Actions.
590 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
591 setOperationAction(ISD::FCOS, MVT::f16, Custom);
592 setOperationAction(ISD::FSIN, MVT::f16, Custom);
593
594 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
595 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Custom);
596
597 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
598 setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
599 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
600 setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
601 setOperationAction(ISD::FROUND, MVT::f16, Custom);
602
603 // F16 - VOP2 Actions.
604 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
605 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
606
607 setOperationAction(ISD::FDIV, MVT::f16, Custom);
608
609 // F16 - VOP3 Actions.
610 setOperationAction(ISD::FMA, MVT::f16, Legal);
611 if (STI.hasMadF16())
612 setOperationAction(ISD::FMAD, MVT::f16, Legal);
613
614 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) {
615 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
616 switch (Op) {
617 case ISD::LOAD:
618 case ISD::STORE:
619 case ISD::BUILD_VECTOR:
620 case ISD::BITCAST:
621 case ISD::EXTRACT_VECTOR_ELT:
622 case ISD::INSERT_VECTOR_ELT:
623 case ISD::INSERT_SUBVECTOR:
624 case ISD::EXTRACT_SUBVECTOR:
625 case ISD::SCALAR_TO_VECTOR:
626 break;
627 case ISD::CONCAT_VECTORS:
628 setOperationAction(Op, VT, Custom);
629 break;
630 default:
631 setOperationAction(Op, VT, Expand);
632 break;
633 }
634 }
635 }
636
637 // v_perm_b32 can handle either of these.
638 setOperationAction(ISD::BSWAP, MVT::i16, Legal);
639 setOperationAction(ISD::BSWAP, MVT::v2i16, Legal);
640 setOperationAction(ISD::BSWAP, MVT::v4i16, Custom);
641
642 // XXX - Do these do anything? Vector constants turn into build_vector.
643 setOperationAction(ISD::Constant, MVT::v2i16, Legal);
644 setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal);
645
646 setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);
647 setOperationAction(ISD::UNDEF, MVT::v2f16, Legal);
648
649 setOperationAction(ISD::STORE, MVT::v2i16, Promote);
650 AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
651 setOperationAction(ISD::STORE, MVT::v2f16, Promote);
652 AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32);
653
654 setOperationAction(ISD::LOAD, MVT::v2i16, Promote);
655 AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32);
656 setOperationAction(ISD::LOAD, MVT::v2f16, Promote);
657 AddPromotedToType(ISD::LOAD, MVT::v2f16, MVT::i32);
658
659 setOperationAction(ISD::AND, MVT::v2i16, Promote);
660 AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);
661 setOperationAction(ISD::OR, MVT::v2i16, Promote);
662 AddPromotedToType(ISD::OR, MVT::v2i16, MVT::i32);
663 setOperationAction(ISD::XOR, MVT::v2i16, Promote);
664 AddPromotedToType(ISD::XOR, MVT::v2i16, MVT::i32);
665
666 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
667 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::v2i32);
668 setOperationAction(ISD::LOAD, MVT::v4f16, Promote);
669 AddPromotedToType(ISD::LOAD, MVT::v4f16, MVT::v2i32);
670
671 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
672 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
673 setOperationAction(ISD::STORE, MVT::v4f16, Promote);
674 AddPromotedToType(ISD::STORE, MVT::v4f16, MVT::v2i32);
675
676 setOperationAction(ISD::ANY_EXTEND, MVT::v2i32, Expand);
677 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i32, Expand);
678 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i32, Expand);
679 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand);
680
681 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Expand);
682 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand);
683 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Expand);
684
685 if (!Subtarget->hasVOP3PInsts()) {
686 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
687 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
688 }
689
690 setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
691 // This isn't really legal, but this avoids the legalizer unrolling it (and
692 // allows matching fneg (fabs x) patterns)
693 setOperationAction(ISD::FABS, MVT::v2f16, Legal);
694
695 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom);
696 setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
697 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal);
698 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal);
699
700 setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom);
701 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v4f16, Custom);
702
703 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand);
704 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand);
705 }
706
707 if (Subtarget->hasVOP3PInsts()) {
708 setOperationAction(ISD::ADD, MVT::v2i16, Legal);
709 setOperationAction(ISD::SUB, MVT::v2i16, Legal);
710 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
711 setOperationAction(ISD::SHL, MVT::v2i16, Legal);
712 setOperationAction(ISD::SRL, MVT::v2i16, Legal);
713 setOperationAction(ISD::SRA, MVT::v2i16, Legal);
714 setOperationAction(ISD::SMIN, MVT::v2i16, Legal);
715 setOperationAction(ISD::UMIN, MVT::v2i16, Legal);
716 setOperationAction(ISD::SMAX, MVT::v2i16, Legal);
717 setOperationAction(ISD::UMAX, MVT::v2i16, Legal);
718
719 setOperationAction(ISD::UADDSAT, MVT::v2i16, Legal);
720 setOperationAction(ISD::USUBSAT, MVT::v2i16, Legal);
721 setOperationAction(ISD::SADDSAT, MVT::v2i16, Legal);
722 setOperationAction(ISD::SSUBSAT, MVT::v2i16, Legal);
723
724 setOperationAction(ISD::FADD, MVT::v2f16, Legal);
725 setOperationAction(ISD::FMUL, MVT::v2f16, Legal);
726 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
727
728 setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal);
729 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v2f16, Legal);
730
731 setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal);
732
733 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
734 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
735
736 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom);
737 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
738
739 setOperationAction(ISD::SHL, MVT::v4i16, Custom);
740 setOperationAction(ISD::SRA, MVT::v4i16, Custom);
741 setOperationAction(ISD::SRL, MVT::v4i16, Custom);
742 setOperationAction(ISD::ADD, MVT::v4i16, Custom);
743 setOperationAction(ISD::SUB, MVT::v4i16, Custom);
744 setOperationAction(ISD::MUL, MVT::v4i16, Custom);
745
746 setOperationAction(ISD::SMIN, MVT::v4i16, Custom);
747 setOperationAction(ISD::SMAX, MVT::v4i16, Custom);
748 setOperationAction(ISD::UMIN, MVT::v4i16, Custom);
749 setOperationAction(ISD::UMAX, MVT::v4i16, Custom);
750
751 setOperationAction(ISD::UADDSAT, MVT::v4i16, Custom);
752 setOperationAction(ISD::SADDSAT, MVT::v4i16, Custom);
753 setOperationAction(ISD::USUBSAT, MVT::v4i16, Custom);
754 setOperationAction(ISD::SSUBSAT, MVT::v4i16, Custom);
755
756 setOperationAction(ISD::FADD, MVT::v4f16, Custom);
757 setOperationAction(ISD::FMUL, MVT::v4f16, Custom);
758 setOperationAction(ISD::FMA, MVT::v4f16, Custom);
759
760 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom);
761 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom);
762
763 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
764 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom);
765 setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom);
766
767 setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
768 setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
769 setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
770
771 if (Subtarget->hasPackedFP32Ops()) {
772 setOperationAction(ISD::FADD, MVT::v2f32, Legal);
773 setOperationAction(ISD::FMUL, MVT::v2f32, Legal);
774 setOperationAction(ISD::FMA, MVT::v2f32, Legal);
775 setOperationAction(ISD::FNEG, MVT::v2f32, Legal);
776
777 for (MVT VT : { MVT::v4f32, MVT::v8f32, MVT::v16f32, MVT::v32f32 }) {
778 setOperationAction(ISD::FADD, VT, Custom);
779 setOperationAction(ISD::FMUL, VT, Custom);
780 setOperationAction(ISD::FMA, VT, Custom);
781 }
782 }
783 }
784
785 setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
786 setOperationAction(ISD::FABS, MVT::v4f16, Custom);
787
788 if (Subtarget->has16BitInsts()) {
789 setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
790 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
791 setOperationAction(ISD::SELECT, MVT::v2f16, Promote);
792 AddPromotedToType(ISD::SELECT, MVT::v2f16, MVT::i32);
793 } else {
794 // Legalization hack.
795 setOperationAction(ISD::SELECT, MVT::v2i16, Custom);
796 setOperationAction(ISD::SELECT, MVT::v2f16, Custom);
797
798 setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
799 setOperationAction(ISD::FABS, MVT::v2f16, Custom);
800 }
801
802 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
803 setOperationAction(ISD::SELECT, VT, Custom);
804 }
805
806 setOperationAction(ISD::SMULO, MVT::i64, Custom);
807 setOperationAction(ISD::UMULO, MVT::i64, Custom);
808
809 if (Subtarget->hasMad64_32()) {
810 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
811 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
812 }
813
814 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
815 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
816 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
817 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
818 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f16, Custom);
819 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i16, Custom);
820 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
821
822 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2f16, Custom);
823 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2i16, Custom);
824 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v3f16, Custom);
825 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v3i16, Custom);
826 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4f16, Custom);
827 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4i16, Custom);
828 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v8f16, Custom);
829 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
830 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::f16, Custom);
831 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom);
832 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
833
834 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
835 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
836 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
837 setOperationAction(ISD::INTRINSIC_VOID, MVT::v3i16, Custom);
838 setOperationAction(ISD::INTRINSIC_VOID, MVT::v3f16, Custom);
839 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
840 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4i16, Custom);
841 setOperationAction(ISD::INTRINSIC_VOID, MVT::f16, Custom);
842 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
843 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
844
845 setTargetDAGCombine(ISD::ADD);
846 setTargetDAGCombine(ISD::ADDCARRY);
847 setTargetDAGCombine(ISD::SUB);
848 setTargetDAGCombine(ISD::SUBCARRY);
849 setTargetDAGCombine(ISD::FADD);
850 setTargetDAGCombine(ISD::FSUB);
851 setTargetDAGCombine(ISD::FMINNUM);
852 setTargetDAGCombine(ISD::FMAXNUM);
853 setTargetDAGCombine(ISD::FMINNUM_IEEE);
854 setTargetDAGCombine(ISD::FMAXNUM_IEEE);
855 setTargetDAGCombine(ISD::FMA);
856 setTargetDAGCombine(ISD::SMIN);
857 setTargetDAGCombine(ISD::SMAX);
858 setTargetDAGCombine(ISD::UMIN);
859 setTargetDAGCombine(ISD::UMAX);
860 setTargetDAGCombine(ISD::SETCC);
861 setTargetDAGCombine(ISD::AND);
862 setTargetDAGCombine(ISD::OR);
863 setTargetDAGCombine(ISD::XOR);
864 setTargetDAGCombine(ISD::SINT_TO_FP);
865 setTargetDAGCombine(ISD::UINT_TO_FP);
866 setTargetDAGCombine(ISD::FCANONICALIZE);
867 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
868 setTargetDAGCombine(ISD::ZERO_EXTEND);
869 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
870 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
871 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
872
873 // All memory operations. Some folding on the pointer operand is done to help
874 // matching the constant offsets in the addressing modes.
875 setTargetDAGCombine(ISD::LOAD);
876 setTargetDAGCombine(ISD::STORE);
877 setTargetDAGCombine(ISD::ATOMIC_LOAD);
878 setTargetDAGCombine(ISD::ATOMIC_STORE);
879 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
880 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
881 setTargetDAGCombine(ISD::ATOMIC_SWAP);
882 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
883 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
884 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
885 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
886 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
887 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
888 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
889 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
890 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
891 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
892 setTargetDAGCombine(ISD::ATOMIC_LOAD_FADD);
893 setTargetDAGCombine(ISD::INTRINSIC_VOID);
894 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
895
896 // FIXME: In other contexts we pretend this is a per-function property.
897 setStackPointerRegisterToSaveRestore(AMDGPU::SGPR32);
898
899 setSchedulingPreference(Sched::RegPressure);
900}
901
902const GCNSubtarget *SITargetLowering::getSubtarget() const {
903 return Subtarget;
904}
905
906//===----------------------------------------------------------------------===//
907// TargetLowering queries
908//===----------------------------------------------------------------------===//
909
910// v_mad_mix* support a conversion from f16 to f32.
911//
912// There is only one special case when denormals are enabled we don't currently,
913// where this is OK to use.
914bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
915 EVT DestVT, EVT SrcVT) const {
916 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||
917 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
918 DestVT.getScalarType() == MVT::f32 &&
919 SrcVT.getScalarType() == MVT::f16 &&
920 // TODO: This probably only requires no input flushing?
921 !hasFP32Denormals(DAG.getMachineFunction());
922}
923
924bool SITargetLowering::isFPExtFoldable(const MachineInstr &MI, unsigned Opcode,
925 LLT DestTy, LLT SrcTy) const {
926 return ((Opcode == TargetOpcode::G_FMAD && Subtarget->hasMadMixInsts()) ||
927 (Opcode == TargetOpcode::G_FMA && Subtarget->hasFmaMixInsts())) &&
928 DestTy.getScalarSizeInBits() == 32 &&
929 SrcTy.getScalarSizeInBits() == 16 &&
930 // TODO: This probably only requires no input flushing?
931 !hasFP32Denormals(*MI.getMF());
932}
933
934bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
935 // SI has some legal vector types, but no legal vector operations. Say no
936 // shuffles are legal in order to prefer scalarizing some vector operations.
937 return false;
938}
939
940MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
941 CallingConv::ID CC,
942 EVT VT) const {
943 if (CC == CallingConv::AMDGPU_KERNEL)
944 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
945
946 if (VT.isVector()) {
947 EVT ScalarVT = VT.getScalarType();
948 unsigned Size = ScalarVT.getSizeInBits();
949 if (Size == 16) {
950 if (Subtarget->has16BitInsts())
951 return VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
952 return VT.isInteger() ? MVT::i32 : MVT::f32;
953 }
954
955 if (Size < 16)
956 return Subtarget->has16BitInsts() ? MVT::i16 : MVT::i32;
957 return Size == 32 ? ScalarVT.getSimpleVT() : MVT::i32;
958 }
959
960 if (VT.getSizeInBits() > 32)
961 return MVT::i32;
962
963 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
964}
965
966unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
967 CallingConv::ID CC,
968 EVT VT) const {
969 if (CC == CallingConv::AMDGPU_KERNEL)
970 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
971
972 if (VT.isVector()) {
973 unsigned NumElts = VT.getVectorNumElements();
974 EVT ScalarVT = VT.getScalarType();
975 unsigned Size = ScalarVT.getSizeInBits();
976
977 // FIXME: Should probably promote 8-bit vectors to i16.
978 if (Size == 16 && Subtarget->has16BitInsts())
979 return (NumElts + 1) / 2;
980
981 if (Size <= 32)
982 return NumElts;
983
984 if (Size > 32)
985 return NumElts * ((Size + 31) / 32);
986 } else if (VT.getSizeInBits() > 32)
987 return (VT.getSizeInBits() + 31) / 32;
988
989 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
990}
991
992unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
993 LLVMContext &Context, CallingConv::ID CC,
994 EVT VT, EVT &IntermediateVT,
995 unsigned &NumIntermediates, MVT &RegisterVT) const {
996 if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
997 unsigned NumElts = VT.getVectorNumElements();
998 EVT ScalarVT = VT.getScalarType();
999 unsigned Size = ScalarVT.getSizeInBits();
1000 // FIXME: We should fix the ABI to be the same on targets without 16-bit
1001 // support, but unless we can properly handle 3-vectors, it will be still be
1002 // inconsistent.
1003 if (Size == 16 && Subtarget->has16BitInsts()) {
1004 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
1005 IntermediateVT = RegisterVT;
1006 NumIntermediates = (NumElts + 1) / 2;
1007 return NumIntermediates;
1008 }
1009
1010 if (Size == 32) {
1011 RegisterVT = ScalarVT.getSimpleVT();
1012 IntermediateVT = RegisterVT;
1013 NumIntermediates = NumElts;
1014 return NumIntermediates;
1015 }
1016
1017 if (Size < 16 && Subtarget->has16BitInsts()) {
1018 // FIXME: Should probably form v2i16 pieces
1019 RegisterVT = MVT::i16;
1020 IntermediateVT = ScalarVT;
1021 NumIntermediates = NumElts;
1022 return NumIntermediates;
1023 }
1024
1025
1026 if (Size != 16 && Size <= 32) {
1027 RegisterVT = MVT::i32;
1028 IntermediateVT = ScalarVT;
1029 NumIntermediates = NumElts;
1030 return NumIntermediates;
1031 }
1032
1033 if (Size > 32) {
1034 RegisterVT = MVT::i32;
1035 IntermediateVT = RegisterVT;
1036 NumIntermediates = NumElts * ((Size + 31) / 32);
1037 return NumIntermediates;
1038 }
1039 }
1040
1041 return TargetLowering::getVectorTypeBreakdownForCallingConv(
1042 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
1043}
1044
1045static EVT memVTFromImageData(Type *Ty, unsigned DMaskLanes) {
1046 assert(DMaskLanes != 0)(static_cast <bool> (DMaskLanes != 0) ? void (0) : __assert_fail
("DMaskLanes != 0", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1046, __extension__ __PRETTY_FUNCTION__))
;
1047
1048 if (auto *VT = dyn_cast<FixedVectorType>(Ty)) {
1049 unsigned NumElts = std::min(DMaskLanes, VT->getNumElements());
1050 return EVT::getVectorVT(Ty->getContext(),
1051 EVT::getEVT(VT->getElementType()),
1052 NumElts);
1053 }
1054
1055 return EVT::getEVT(Ty);
1056}
1057
1058// Peek through TFE struct returns to only use the data size.
1059static EVT memVTFromImageReturn(Type *Ty, unsigned DMaskLanes) {
1060 auto *ST = dyn_cast<StructType>(Ty);
1061 if (!ST)
1062 return memVTFromImageData(Ty, DMaskLanes);
1063
1064 // Some intrinsics return an aggregate type - special case to work out the
1065 // correct memVT.
1066 //
1067 // Only limited forms of aggregate type currently expected.
1068 if (ST->getNumContainedTypes() != 2 ||
1069 !ST->getContainedType(1)->isIntegerTy(32))
1070 return EVT();
1071 return memVTFromImageData(ST->getContainedType(0), DMaskLanes);
1072}
1073
1074bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1075 const CallInst &CI,
1076 MachineFunction &MF,
1077 unsigned IntrID) const {
1078 if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
1079 AMDGPU::lookupRsrcIntrinsic(IntrID)) {
1080 AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
1081 (Intrinsic::ID)IntrID);
1082 if (Attr.hasFnAttr(Attribute::ReadNone))
1083 return false;
1084
1085 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1086
1087 if (RsrcIntr->IsImage) {
1088 Info.ptrVal =
1089 MFI->getImagePSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1090 Info.align.reset();
1091 } else {
1092 Info.ptrVal =
1093 MFI->getBufferPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1094 }
1095
1096 Info.flags = MachineMemOperand::MODereferenceable;
1097 if (Attr.hasFnAttr(Attribute::ReadOnly)) {
1098 unsigned DMaskLanes = 4;
1099
1100 if (RsrcIntr->IsImage) {
1101 const AMDGPU::ImageDimIntrinsicInfo *Intr
1102 = AMDGPU::getImageDimIntrinsicInfo(IntrID);
1103 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
1104 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
1105
1106 if (!BaseOpcode->Gather4) {
1107 // If this isn't a gather, we may have excess loaded elements in the
1108 // IR type. Check the dmask for the real number of elements loaded.
1109 unsigned DMask
1110 = cast<ConstantInt>(CI.getArgOperand(0))->getZExtValue();
1111 DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask);
1112 }
1113
1114 Info.memVT = memVTFromImageReturn(CI.getType(), DMaskLanes);
1115 } else
1116 Info.memVT = EVT::getEVT(CI.getType());
1117
1118 // FIXME: What does alignment mean for an image?
1119 Info.opc = ISD::INTRINSIC_W_CHAIN;
1120 Info.flags |= MachineMemOperand::MOLoad;
1121 } else if (Attr.hasFnAttr(Attribute::WriteOnly)) {
1122 Info.opc = ISD::INTRINSIC_VOID;
1123
1124 Type *DataTy = CI.getArgOperand(0)->getType();
1125 if (RsrcIntr->IsImage) {
1126 unsigned DMask = cast<ConstantInt>(CI.getArgOperand(1))->getZExtValue();
1127 unsigned DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask);
1128 Info.memVT = memVTFromImageData(DataTy, DMaskLanes);
1129 } else
1130 Info.memVT = EVT::getEVT(DataTy);
1131
1132 Info.flags |= MachineMemOperand::MOStore;
1133 } else {
1134 // Atomic
1135 Info.opc = CI.getType()->isVoidTy() ? ISD::INTRINSIC_VOID :
1136 ISD::INTRINSIC_W_CHAIN;
1137 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
1138 Info.flags = MachineMemOperand::MOLoad |
1139 MachineMemOperand::MOStore |
1140 MachineMemOperand::MODereferenceable;
1141
1142 // XXX - Should this be volatile without known ordering?
1143 Info.flags |= MachineMemOperand::MOVolatile;
1144 }
1145 return true;
1146 }
1147
1148 switch (IntrID) {
1149 case Intrinsic::amdgcn_atomic_inc:
1150 case Intrinsic::amdgcn_atomic_dec:
1151 case Intrinsic::amdgcn_ds_ordered_add:
1152 case Intrinsic::amdgcn_ds_ordered_swap:
1153 case Intrinsic::amdgcn_ds_fadd:
1154 case Intrinsic::amdgcn_ds_fmin:
1155 case Intrinsic::amdgcn_ds_fmax: {
1156 Info.opc = ISD::INTRINSIC_W_CHAIN;
1157 Info.memVT = MVT::getVT(CI.getType());
1158 Info.ptrVal = CI.getOperand(0);
1159 Info.align.reset();
1160 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1161
1162 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(4));
1163 if (!Vol->isZero())
1164 Info.flags |= MachineMemOperand::MOVolatile;
1165
1166 return true;
1167 }
1168 case Intrinsic::amdgcn_buffer_atomic_fadd: {
1169 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1170
1171 Info.opc = ISD::INTRINSIC_W_CHAIN;
1172 Info.memVT = MVT::getVT(CI.getOperand(0)->getType());
1173 Info.ptrVal =
1174 MFI->getBufferPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1175 Info.align.reset();
1176 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1177
1178 const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
1179 if (!Vol || !Vol->isZero())
1180 Info.flags |= MachineMemOperand::MOVolatile;
1181
1182 return true;
1183 }
1184 case Intrinsic::amdgcn_ds_append:
1185 case Intrinsic::amdgcn_ds_consume: {
1186 Info.opc = ISD::INTRINSIC_W_CHAIN;
1187 Info.memVT = MVT::getVT(CI.getType());
1188 Info.ptrVal = CI.getOperand(0);
1189 Info.align.reset();
1190 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1191
1192 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(1));
1193 if (!Vol->isZero())
1194 Info.flags |= MachineMemOperand::MOVolatile;
1195
1196 return true;
1197 }
1198 case Intrinsic::amdgcn_global_atomic_csub: {
1199 Info.opc = ISD::INTRINSIC_W_CHAIN;
1200 Info.memVT = MVT::getVT(CI.getType());
1201 Info.ptrVal = CI.getOperand(0);
1202 Info.align.reset();
1203 Info.flags = MachineMemOperand::MOLoad |
1204 MachineMemOperand::MOStore |
1205 MachineMemOperand::MOVolatile;
1206 return true;
1207 }
1208 case Intrinsic::amdgcn_image_bvh_intersect_ray: {
1209 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1210 Info.opc = ISD::INTRINSIC_W_CHAIN;
1211 Info.memVT = MVT::getVT(CI.getType()); // XXX: what is correct VT?
1212 Info.ptrVal =
1213 MFI->getImagePSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1214 Info.align.reset();
1215 Info.flags = MachineMemOperand::MOLoad |
1216 MachineMemOperand::MODereferenceable;
1217 return true;
1218 }
1219 case Intrinsic::amdgcn_global_atomic_fadd:
1220 case Intrinsic::amdgcn_global_atomic_fmin:
1221 case Intrinsic::amdgcn_global_atomic_fmax:
1222 case Intrinsic::amdgcn_flat_atomic_fadd:
1223 case Intrinsic::amdgcn_flat_atomic_fmin:
1224 case Intrinsic::amdgcn_flat_atomic_fmax: {
1225 Info.opc = ISD::INTRINSIC_W_CHAIN;
1226 Info.memVT = MVT::getVT(CI.getType());
1227 Info.ptrVal = CI.getOperand(0);
1228 Info.align.reset();
1229 Info.flags = MachineMemOperand::MOLoad |
1230 MachineMemOperand::MOStore |
1231 MachineMemOperand::MODereferenceable |
1232 MachineMemOperand::MOVolatile;
1233 return true;
1234 }
1235 case Intrinsic::amdgcn_ds_gws_init:
1236 case Intrinsic::amdgcn_ds_gws_barrier:
1237 case Intrinsic::amdgcn_ds_gws_sema_v:
1238 case Intrinsic::amdgcn_ds_gws_sema_br:
1239 case Intrinsic::amdgcn_ds_gws_sema_p:
1240 case Intrinsic::amdgcn_ds_gws_sema_release_all: {
1241 Info.opc = ISD::INTRINSIC_VOID;
1242
1243 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1244 Info.ptrVal =
1245 MFI->getGWSPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1246
1247 // This is an abstract access, but we need to specify a type and size.
1248 Info.memVT = MVT::i32;
1249 Info.size = 4;
1250 Info.align = Align(4);
1251
1252 Info.flags = MachineMemOperand::MOStore;
1253 if (IntrID == Intrinsic::amdgcn_ds_gws_barrier)
1254 Info.flags = MachineMemOperand::MOLoad;
1255 return true;
1256 }
1257 default:
1258 return false;
1259 }
1260}
1261
1262bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
1263 SmallVectorImpl<Value*> &Ops,
1264 Type *&AccessTy) const {
1265 switch (II->getIntrinsicID()) {
1266 case Intrinsic::amdgcn_atomic_inc:
1267 case Intrinsic::amdgcn_atomic_dec:
1268 case Intrinsic::amdgcn_ds_ordered_add:
1269 case Intrinsic::amdgcn_ds_ordered_swap:
1270 case Intrinsic::amdgcn_ds_append:
1271 case Intrinsic::amdgcn_ds_consume:
1272 case Intrinsic::amdgcn_ds_fadd:
1273 case Intrinsic::amdgcn_ds_fmin:
1274 case Intrinsic::amdgcn_ds_fmax:
1275 case Intrinsic::amdgcn_global_atomic_fadd:
1276 case Intrinsic::amdgcn_flat_atomic_fadd:
1277 case Intrinsic::amdgcn_flat_atomic_fmin:
1278 case Intrinsic::amdgcn_flat_atomic_fmax:
1279 case Intrinsic::amdgcn_global_atomic_csub: {
1280 Value *Ptr = II->getArgOperand(0);
1281 AccessTy = II->getType();
1282 Ops.push_back(Ptr);
1283 return true;
1284 }
1285 default:
1286 return false;
1287 }
1288}
1289
1290bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
1291 if (!Subtarget->hasFlatInstOffsets()) {
1292 // Flat instructions do not have offsets, and only have the register
1293 // address.
1294 return AM.BaseOffs == 0 && AM.Scale == 0;
1295 }
1296
1297 return AM.Scale == 0 &&
1298 (AM.BaseOffs == 0 ||
1299 Subtarget->getInstrInfo()->isLegalFLATOffset(
1300 AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS, SIInstrFlags::FLAT));
1301}
1302
1303bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const {
1304 if (Subtarget->hasFlatGlobalInsts())
1305 return AM.Scale == 0 &&
1306 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset(
1307 AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS,
1308 SIInstrFlags::FlatGlobal));
1309
1310 if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) {
1311 // Assume the we will use FLAT for all global memory accesses
1312 // on VI.
1313 // FIXME: This assumption is currently wrong. On VI we still use
1314 // MUBUF instructions for the r + i addressing mode. As currently
1315 // implemented, the MUBUF instructions only work on buffer < 4GB.
1316 // It may be possible to support > 4GB buffers with MUBUF instructions,
1317 // by setting the stride value in the resource descriptor which would
1318 // increase the size limit to (stride * 4GB). However, this is risky,
1319 // because it has never been validated.
1320 return isLegalFlatAddressingMode(AM);
1321 }
1322
1323 return isLegalMUBUFAddressingMode(AM);
1324}
1325
1326bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
1327 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
1328 // additionally can do r + r + i with addr64. 32-bit has more addressing
1329 // mode options. Depending on the resource constant, it can also do
1330 // (i64 r0) + (i32 r1) * (i14 i).
1331 //
1332 // Private arrays end up using a scratch buffer most of the time, so also
1333 // assume those use MUBUF instructions. Scratch loads / stores are currently
1334 // implemented as mubuf instructions with offen bit set, so slightly
1335 // different than the normal addr64.
1336 if (!SIInstrInfo::isLegalMUBUFImmOffset(AM.BaseOffs))
1337 return false;
1338
1339 // FIXME: Since we can split immediate into soffset and immediate offset,
1340 // would it make sense to allow any immediate?
1341
1342 switch (AM.Scale) {
1343 case 0: // r + i or just i, depending on HasBaseReg.
1344 return true;
1345 case 1:
1346 return true; // We have r + r or r + i.
1347 case 2:
1348 if (AM.HasBaseReg) {
1349 // Reject 2 * r + r.
1350 return false;
1351 }
1352
1353 // Allow 2 * r as r + r
1354 // Or 2 * r + i is allowed as r + r + i.
1355 return true;
1356 default: // Don't allow n * r
1357 return false;
1358 }
1359}
1360
1361bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
1362 const AddrMode &AM, Type *Ty,
1363 unsigned AS, Instruction *I) const {
1364 // No global is ever allowed as a base.
1365 if (AM.BaseGV)
1366 return false;
1367
1368 if (AS == AMDGPUAS::GLOBAL_ADDRESS)
1369 return isLegalGlobalAddressingMode(AM);
1370
1371 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
1372 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
1373 AS == AMDGPUAS::BUFFER_FAT_POINTER) {
1374 // If the offset isn't a multiple of 4, it probably isn't going to be
1375 // correctly aligned.
1376 // FIXME: Can we get the real alignment here?
1377 if (AM.BaseOffs % 4 != 0)
1378 return isLegalMUBUFAddressingMode(AM);
1379
1380 // There are no SMRD extloads, so if we have to do a small type access we
1381 // will use a MUBUF load.
1382 // FIXME?: We also need to do this if unaligned, but we don't know the
1383 // alignment here.
1384 if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4)
1385 return isLegalGlobalAddressingMode(AM);
1386
1387 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1388 // SMRD instructions have an 8-bit, dword offset on SI.
1389 if (!isUInt<8>(AM.BaseOffs / 4))
1390 return false;
1391 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
1392 // On CI+, this can also be a 32-bit literal constant offset. If it fits
1393 // in 8-bits, it can use a smaller encoding.
1394 if (!isUInt<32>(AM.BaseOffs / 4))
1395 return false;
1396 } else if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
1397 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
1398 if (!isUInt<20>(AM.BaseOffs))
1399 return false;
1400 } else
1401 llvm_unreachable("unhandled generation")::llvm::llvm_unreachable_internal("unhandled generation", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1401)
;
1402
1403 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1404 return true;
1405
1406 if (AM.Scale == 1 && AM.HasBaseReg)
1407 return true;
1408
1409 return false;
1410
1411 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1412 return isLegalMUBUFAddressingMode(AM);
1413 } else if (AS == AMDGPUAS::LOCAL_ADDRESS ||
1414 AS == AMDGPUAS::REGION_ADDRESS) {
1415 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
1416 // field.
1417 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
1418 // an 8-bit dword offset but we don't know the alignment here.
1419 if (!isUInt<16>(AM.BaseOffs))
1420 return false;
1421
1422 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1423 return true;
1424
1425 if (AM.Scale == 1 && AM.HasBaseReg)
1426 return true;
1427
1428 return false;
1429 } else if (AS == AMDGPUAS::FLAT_ADDRESS ||
1430 AS == AMDGPUAS::UNKNOWN_ADDRESS_SPACE) {
1431 // For an unknown address space, this usually means that this is for some
1432 // reason being used for pure arithmetic, and not based on some addressing
1433 // computation. We don't have instructions that compute pointers with any
1434 // addressing modes, so treat them as having no offset like flat
1435 // instructions.
1436 return isLegalFlatAddressingMode(AM);
1437 }
1438
1439 // Assume a user alias of global for unknown address spaces.
1440 return isLegalGlobalAddressingMode(AM);
1441}
1442
1443bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1444 const MachineFunction &MF) const {
1445 if (AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS) {
1446 return (MemVT.getSizeInBits() <= 4 * 32);
1447 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1448 unsigned MaxPrivateBits = 8 * getSubtarget()->getMaxPrivateElementSize();
1449 return (MemVT.getSizeInBits() <= MaxPrivateBits);
1450 } else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
1451 return (MemVT.getSizeInBits() <= 2 * 32);
1452 }
1453 return true;
1454}
1455
1456bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
1457 unsigned Size, unsigned AddrSpace, Align Alignment,
1458 MachineMemOperand::Flags Flags, bool *IsFast) const {
1459 if (IsFast)
1460 *IsFast = false;
1461
1462 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1463 AddrSpace == AMDGPUAS::REGION_ADDRESS) {
1464 // Check if alignment requirements for ds_read/write instructions are
1465 // disabled.
1466 if (Subtarget->hasUnalignedDSAccessEnabled() &&
1467 !Subtarget->hasLDSMisalignedBug()) {
1468 if (IsFast)
1469 *IsFast = Alignment != Align(2);
1470 return true;
1471 }
1472
1473 // Either, the alignment requirements are "enabled", or there is an
1474 // unaligned LDS access related hardware bug though alignment requirements
1475 // are "disabled". In either case, we need to check for proper alignment
1476 // requirements.
1477 //
1478 if (Size == 64) {
1479 // 8 byte accessing via ds_read/write_b64 require 8-byte alignment, but we
1480 // can do a 4 byte aligned, 8 byte access in a single operation using
1481 // ds_read2/write2_b32 with adjacent offsets.
1482 bool AlignedBy4 = Alignment >= Align(4);
1483 if (IsFast)
1484 *IsFast = AlignedBy4;
1485
1486 return AlignedBy4;
1487 }
1488 if (Size == 96) {
1489 // 12 byte accessing via ds_read/write_b96 require 16-byte alignment on
1490 // gfx8 and older.
1491 bool AlignedBy16 = Alignment >= Align(16);
1492 if (IsFast)
1493 *IsFast = AlignedBy16;
1494
1495 return AlignedBy16;
1496 }
1497 if (Size == 128) {
1498 // 16 byte accessing via ds_read/write_b128 require 16-byte alignment on
1499 // gfx8 and older, but we can do a 8 byte aligned, 16 byte access in a
1500 // single operation using ds_read2/write2_b64.
1501 bool AlignedBy8 = Alignment >= Align(8);
1502 if (IsFast)
1503 *IsFast = AlignedBy8;
1504
1505 return AlignedBy8;
1506 }
1507 }
1508
1509 if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
1510 bool AlignedBy4 = Alignment >= Align(4);
1511 if (IsFast)
1512 *IsFast = AlignedBy4;
1513
1514 return AlignedBy4 ||
1515 Subtarget->enableFlatScratch() ||
1516 Subtarget->hasUnalignedScratchAccess();
1517 }
1518
1519 // FIXME: We have to be conservative here and assume that flat operations
1520 // will access scratch. If we had access to the IR function, then we
1521 // could determine if any private memory was used in the function.
1522 if (AddrSpace == AMDGPUAS::FLAT_ADDRESS &&
1523 !Subtarget->hasUnalignedScratchAccess()) {
1524 bool AlignedBy4 = Alignment >= Align(4);
1525 if (IsFast)
1526 *IsFast = AlignedBy4;
1527
1528 return AlignedBy4;
1529 }
1530
1531 if (Subtarget->hasUnalignedBufferAccessEnabled() &&
1532 !(AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1533 AddrSpace == AMDGPUAS::REGION_ADDRESS)) {
1534 // If we have an uniform constant load, it still requires using a slow
1535 // buffer instruction if unaligned.
1536 if (IsFast) {
1537 // Accesses can really be issued as 1-byte aligned or 4-byte aligned, so
1538 // 2-byte alignment is worse than 1 unless doing a 2-byte accesss.
1539 *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
1540 AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ?
1541 Alignment >= Align(4) : Alignment != Align(2);
1542 }
1543
1544 return true;
1545 }
1546
1547 // Smaller than dword value must be aligned.
1548 if (Size < 32)
1549 return false;
1550
1551 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
1552 // byte-address are ignored, thus forcing Dword alignment.
1553 // This applies to private, global, and constant memory.
1554 if (IsFast)
1555 *IsFast = true;
1556
1557 return Size >= 32 && Alignment >= Align(4);
1558}
1559
1560bool SITargetLowering::allowsMisalignedMemoryAccesses(
1561 EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
1562 bool *IsFast) const {
1563 if (IsFast)
1564 *IsFast = false;
1565
1566 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
1567 // which isn't a simple VT.
1568 // Until MVT is extended to handle this, simply check for the size and
1569 // rely on the condition below: allow accesses if the size is a multiple of 4.
1570 if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
1571 VT.getStoreSize() > 16)) {
1572 return false;
1573 }
1574
1575 return allowsMisalignedMemoryAccessesImpl(VT.getSizeInBits(), AddrSpace,
1576 Alignment, Flags, IsFast);
1577}
1578
1579EVT SITargetLowering::getOptimalMemOpType(
1580 const MemOp &Op, const AttributeList &FuncAttributes) const {
1581 // FIXME: Should account for address space here.
1582
1583 // The default fallback uses the private pointer size as a guess for a type to
1584 // use. Make sure we switch these to 64-bit accesses.
1585
1586 if (Op.size() >= 16 &&
1587 Op.isDstAligned(Align(4))) // XXX: Should only do for global
1588 return MVT::v4i32;
1589
1590 if (Op.size() >= 8 && Op.isDstAligned(Align(4)))
1591 return MVT::v2i32;
1592
1593 // Use the default.
1594 return MVT::Other;
1595}
1596
1597bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {
1598 const MemSDNode *MemNode = cast<MemSDNode>(N);
1599 const Value *Ptr = MemNode->getMemOperand()->getValue();
1600 const Instruction *I = dyn_cast_or_null<Instruction>(Ptr);
1601 return I && I->getMetadata("amdgpu.noclobber");
1602}
1603
1604bool SITargetLowering::isNonGlobalAddrSpace(unsigned AS) {
1605 return AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS ||
1606 AS == AMDGPUAS::PRIVATE_ADDRESS;
1607}
1608
1609bool SITargetLowering::isFreeAddrSpaceCast(unsigned SrcAS,
1610 unsigned DestAS) const {
1611 // Flat -> private/local is a simple truncate.
1612 // Flat -> global is no-op
1613 if (SrcAS == AMDGPUAS::FLAT_ADDRESS)
1614 return true;
1615
1616 const GCNTargetMachine &TM =
1617 static_cast<const GCNTargetMachine &>(getTargetMachine());
1618 return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
1619}
1620
1621bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
1622 const MemSDNode *MemNode = cast<MemSDNode>(N);
1623
1624 return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
1625}
1626
1627TargetLoweringBase::LegalizeTypeAction
1628SITargetLowering::getPreferredVectorAction(MVT VT) const {
1629 if (!VT.isScalableVector() && VT.getVectorNumElements() != 1 &&
1630 VT.getScalarType().bitsLE(MVT::i16))
1631 return VT.isPow2VectorType() ? TypeSplitVector : TypeWidenVector;
1632 return TargetLoweringBase::getPreferredVectorAction(VT);
1633}
1634
1635bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
1636 Type *Ty) const {
1637 // FIXME: Could be smarter if called for vector constants.
1638 return true;
1639}
1640
1641bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
1642 if (Subtarget->has16BitInsts() && VT == MVT::i16) {
1643 switch (Op) {
1644 case ISD::LOAD:
1645 case ISD::STORE:
1646
1647 // These operations are done with 32-bit instructions anyway.
1648 case ISD::AND:
1649 case ISD::OR:
1650 case ISD::XOR:
1651 case ISD::SELECT:
1652 // TODO: Extensions?
1653 return true;
1654 default:
1655 return false;
1656 }
1657 }
1658
1659 // SimplifySetCC uses this function to determine whether or not it should
1660 // create setcc with i1 operands. We don't have instructions for i1 setcc.
1661 if (VT == MVT::i1 && Op == ISD::SETCC)
1662 return false;
1663
1664 return TargetLowering::isTypeDesirableForOp(Op, VT);
1665}
1666
1667SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
1668 const SDLoc &SL,
1669 SDValue Chain,
1670 uint64_t Offset) const {
1671 const DataLayout &DL = DAG.getDataLayout();
1672 MachineFunction &MF = DAG.getMachineFunction();
1673 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1674
1675 const ArgDescriptor *InputPtrReg;
1676 const TargetRegisterClass *RC;
1677 LLT ArgTy;
1678 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
1679
1680 std::tie(InputPtrReg, RC, ArgTy) =
1681 Info->getPreloadedValue(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
1682
1683 // We may not have the kernarg segment argument if we have no kernel
1684 // arguments.
1685 if (!InputPtrReg)
1686 return DAG.getConstant(0, SL, PtrVT);
1687
1688 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1689 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
1690 MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
1691
1692 return DAG.getObjectPtrOffset(SL, BasePtr, TypeSize::Fixed(Offset));
1693}
1694
1695SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
1696 const SDLoc &SL) const {
1697 uint64_t Offset = getImplicitParameterOffset(DAG.getMachineFunction(),
1698 FIRST_IMPLICIT);
1699 return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset);
1700}
1701
1702SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
1703 const SDLoc &SL, SDValue Val,
1704 bool Signed,
1705 const ISD::InputArg *Arg) const {
1706 // First, if it is a widened vector, narrow it.
1707 if (VT.isVector() &&
1708 VT.getVectorNumElements() != MemVT.getVectorNumElements()) {
1709 EVT NarrowedVT =
1710 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(),
1711 VT.getVectorNumElements());
1712 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val,
1713 DAG.getConstant(0, SL, MVT::i32));
1714 }
1715
1716 // Then convert the vector elements or scalar value.
1717 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
1718 VT.bitsLT(MemVT)) {
1719 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
1720 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT));
1721 }
1722
1723 if (MemVT.isFloatingPoint())
1724 Val = getFPExtOrFPRound(DAG, Val, SL, VT);
1725 else if (Signed)
1726 Val = DAG.getSExtOrTrunc(Val, SL, VT);
1727 else
1728 Val = DAG.getZExtOrTrunc(Val, SL, VT);
1729
1730 return Val;
1731}
1732
1733SDValue SITargetLowering::lowerKernargMemParameter(
1734 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain,
1735 uint64_t Offset, Align Alignment, bool Signed,
1736 const ISD::InputArg *Arg) const {
1737 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
1738
1739 // Try to avoid using an extload by loading earlier than the argument address,
1740 // and extracting the relevant bits. The load should hopefully be merged with
1741 // the previous argument.
1742 if (MemVT.getStoreSize() < 4 && Alignment < 4) {
1743 // TODO: Handle align < 4 and size >= 4 (can happen with packed structs).
1744 int64_t AlignDownOffset = alignDown(Offset, 4);
1745 int64_t OffsetDiff = Offset - AlignDownOffset;
1746
1747 EVT IntVT = MemVT.changeTypeToInteger();
1748
1749 // TODO: If we passed in the base kernel offset we could have a better
1750 // alignment than 4, but we don't really need it.
1751 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
1752 SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, Align(4),
1753 MachineMemOperand::MODereferenceable |
1754 MachineMemOperand::MOInvariant);
1755
1756 SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
1757 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
1758
1759 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract);
1760 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal);
1761 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg);
1762
1763
1764 return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
1765 }
1766
1767 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
1768 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Alignment,
1769 MachineMemOperand::MODereferenceable |
1770 MachineMemOperand::MOInvariant);
1771
1772 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg);
1773 return DAG.getMergeValues({ Val, Load.getValue(1) }, SL);
1774}
1775
1776SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
1777 const SDLoc &SL, SDValue Chain,
1778 const ISD::InputArg &Arg) const {
1779 MachineFunction &MF = DAG.getMachineFunction();
1780 MachineFrameInfo &MFI = MF.getFrameInfo();
1781
1782 if (Arg.Flags.isByVal()) {
1783 unsigned Size = Arg.Flags.getByValSize();
1784 int FrameIdx = MFI.CreateFixedObject(Size, VA.getLocMemOffset(), false);
1785 return DAG.getFrameIndex(FrameIdx, MVT::i32);
1786 }
1787
1788 unsigned ArgOffset = VA.getLocMemOffset();
1789 unsigned ArgSize = VA.getValVT().getStoreSize();
1790
1791 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, true);
1792
1793 // Create load nodes to retrieve arguments from the stack.
1794 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1795 SDValue ArgValue;
1796
1797 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1798 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1799 MVT MemVT = VA.getValVT();
1800
1801 switch (VA.getLocInfo()) {
1802 default:
1803 break;
1804 case CCValAssign::BCvt:
1805 MemVT = VA.getLocVT();
1806 break;
1807 case CCValAssign::SExt:
1808 ExtType = ISD::SEXTLOAD;
1809 break;
1810 case CCValAssign::ZExt:
1811 ExtType = ISD::ZEXTLOAD;
1812 break;
1813 case CCValAssign::AExt:
1814 ExtType = ISD::EXTLOAD;
1815 break;
1816 }
1817
1818 ArgValue = DAG.getExtLoad(
1819 ExtType, SL, VA.getLocVT(), Chain, FIN,
1820 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
1821 MemVT);
1822 return ArgValue;
1823}
1824
1825SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,
1826 const SIMachineFunctionInfo &MFI,
1827 EVT VT,
1828 AMDGPUFunctionArgInfo::PreloadedValue PVID) const {
1829 const ArgDescriptor *Reg;
1830 const TargetRegisterClass *RC;
1831 LLT Ty;
1832
1833 std::tie(Reg, RC, Ty) = MFI.getPreloadedValue(PVID);
1834 if (!Reg) {
1835 if (PVID == AMDGPUFunctionArgInfo::PreloadedValue::KERNARG_SEGMENT_PTR) {
1836 // It's possible for a kernarg intrinsic call to appear in a kernel with
1837 // no allocated segment, in which case we do not add the user sgpr
1838 // argument, so just return null.
1839 return DAG.getConstant(0, SDLoc(), VT);
1840 }
1841
1842 // It's undefined behavior if a function marked with the amdgpu-no-*
1843 // attributes uses the corresponding intrinsic.
1844 return DAG.getUNDEF(VT);
1845 }
1846
1847 return CreateLiveInRegister(DAG, RC, Reg->getRegister(), VT);
1848}
1849
1850static void processPSInputArgs(SmallVectorImpl<ISD::InputArg> &Splits,
1851 CallingConv::ID CallConv,
1852 ArrayRef<ISD::InputArg> Ins, BitVector &Skipped,
1853 FunctionType *FType,
1854 SIMachineFunctionInfo *Info) {
1855 for (unsigned I = 0, E = Ins.size(), PSInputNum = 0; I != E; ++I) {
1856 const ISD::InputArg *Arg = &Ins[I];
1857
1858 assert((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) &&(static_cast <bool> ((!Arg->VT.isVector() || Arg->
VT.getScalarSizeInBits() == 16) && "vector type argument should have been split"
) ? void (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 1859, __extension__
__PRETTY_FUNCTION__))
1859 "vector type argument should have been split")(static_cast <bool> ((!Arg->VT.isVector() || Arg->
VT.getScalarSizeInBits() == 16) && "vector type argument should have been split"
) ? void (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 1859, __extension__
__PRETTY_FUNCTION__))
;
1860
1861 // First check if it's a PS input addr.
1862 if (CallConv == CallingConv::AMDGPU_PS &&
1863 !Arg->Flags.isInReg() && PSInputNum <= 15) {
1864 bool SkipArg = !Arg->Used && !Info->isPSInputAllocated(PSInputNum);
1865
1866 // Inconveniently only the first part of the split is marked as isSplit,
1867 // so skip to the end. We only want to increment PSInputNum once for the
1868 // entire split argument.
1869 if (Arg->Flags.isSplit()) {
1870 while (!Arg->Flags.isSplitEnd()) {
1871 assert((!Arg->VT.isVector() ||(static_cast <bool> ((!Arg->VT.isVector() || Arg->
VT.getScalarSizeInBits() == 16) && "unexpected vector split in ps argument type"
) ? void (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 1873, __extension__
__PRETTY_FUNCTION__))
1872 Arg->VT.getScalarSizeInBits() == 16) &&(static_cast <bool> ((!Arg->VT.isVector() || Arg->
VT.getScalarSizeInBits() == 16) && "unexpected vector split in ps argument type"
) ? void (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 1873, __extension__
__PRETTY_FUNCTION__))
1873 "unexpected vector split in ps argument type")(static_cast <bool> ((!Arg->VT.isVector() || Arg->
VT.getScalarSizeInBits() == 16) && "unexpected vector split in ps argument type"
) ? void (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 1873, __extension__
__PRETTY_FUNCTION__))
;
1874 if (!SkipArg)
1875 Splits.push_back(*Arg);
1876 Arg = &Ins[++I];
1877 }
1878 }
1879
1880 if (SkipArg) {
1881 // We can safely skip PS inputs.
1882 Skipped.set(Arg->getOrigArgIndex());
1883 ++PSInputNum;
1884 continue;
1885 }
1886
1887 Info->markPSInputAllocated(PSInputNum);
1888 if (Arg->Used)
1889 Info->markPSInputEnabled(PSInputNum);
1890
1891 ++PSInputNum;
1892 }
1893
1894 Splits.push_back(*Arg);
1895 }
1896}
1897
1898// Allocate special inputs passed in VGPRs.
1899void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,
1900 MachineFunction &MF,
1901 const SIRegisterInfo &TRI,
1902 SIMachineFunctionInfo &Info) const {
1903 const LLT S32 = LLT::scalar(32);
1904 MachineRegisterInfo &MRI = MF.getRegInfo();
1905
1906 if (Info.hasWorkItemIDX()) {
1907 Register Reg = AMDGPU::VGPR0;
1908 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1909
1910 CCInfo.AllocateReg(Reg);
1911 unsigned Mask = (Subtarget->hasPackedTID() &&
1912 Info.hasWorkItemIDY()) ? 0x3ff : ~0u;
1913 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask));
1914 }
1915
1916 if (Info.hasWorkItemIDY()) {
1917 assert(Info.hasWorkItemIDX())(static_cast <bool> (Info.hasWorkItemIDX()) ? void (0) :
__assert_fail ("Info.hasWorkItemIDX()", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1917, __extension__ __PRETTY_FUNCTION__))
;
1918 if (Subtarget->hasPackedTID()) {
1919 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0,
1920 0x3ff << 10));
1921 } else {
1922 unsigned Reg = AMDGPU::VGPR1;
1923 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1924
1925 CCInfo.AllocateReg(Reg);
1926 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg));
1927 }
1928 }
1929
1930 if (Info.hasWorkItemIDZ()) {
1931 assert(Info.hasWorkItemIDX() && Info.hasWorkItemIDY())(static_cast <bool> (Info.hasWorkItemIDX() && Info
.hasWorkItemIDY()) ? void (0) : __assert_fail ("Info.hasWorkItemIDX() && Info.hasWorkItemIDY()"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 1931, __extension__
__PRETTY_FUNCTION__))
;
1932 if (Subtarget->hasPackedTID()) {
1933 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0,
1934 0x3ff << 20));
1935 } else {
1936 unsigned Reg = AMDGPU::VGPR2;
1937 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1938
1939 CCInfo.AllocateReg(Reg);
1940 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg));
1941 }
1942 }
1943}
1944
1945// Try to allocate a VGPR at the end of the argument list, or if no argument
1946// VGPRs are left allocating a stack slot.
1947// If \p Mask is is given it indicates bitfield position in the register.
1948// If \p Arg is given use it with new ]p Mask instead of allocating new.
1949static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,
1950 ArgDescriptor Arg = ArgDescriptor()) {
1951 if (Arg.isSet())
1952 return ArgDescriptor::createArg(Arg, Mask);
1953
1954 ArrayRef<MCPhysReg> ArgVGPRs
1955 = makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), 32);
1956 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
1957 if (RegIdx == ArgVGPRs.size()) {
1958 // Spill to stack required.
1959 int64_t Offset = CCInfo.AllocateStack(4, Align(4));
1960
1961 return ArgDescriptor::createStack(Offset, Mask);
1962 }
1963
1964 unsigned Reg = ArgVGPRs[RegIdx];
1965 Reg = CCInfo.AllocateReg(Reg);
1966 assert(Reg != AMDGPU::NoRegister)(static_cast <bool> (Reg != AMDGPU::NoRegister) ? void (
0) : __assert_fail ("Reg != AMDGPU::NoRegister", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1966, __extension__ __PRETTY_FUNCTION__))
;
1967
1968 MachineFunction &MF = CCInfo.getMachineFunction();
1969 Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1970 MF.getRegInfo().setType(LiveInVReg, LLT::scalar(32));
1971 return ArgDescriptor::createRegister(Reg, Mask);
1972}
1973
1974static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,
1975 const TargetRegisterClass *RC,
1976 unsigned NumArgRegs) {
1977 ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
1978 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
1979 if (RegIdx == ArgSGPRs.size())
1980 report_fatal_error("ran out of SGPRs for arguments");
1981
1982 unsigned Reg = ArgSGPRs[RegIdx];
1983 Reg = CCInfo.AllocateReg(Reg);
1984 assert(Reg != AMDGPU::NoRegister)(static_cast <bool> (Reg != AMDGPU::NoRegister) ? void (
0) : __assert_fail ("Reg != AMDGPU::NoRegister", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1984, __extension__ __PRETTY_FUNCTION__))
;
1985
1986 MachineFunction &MF = CCInfo.getMachineFunction();
1987 MF.addLiveIn(Reg, RC);
1988 return ArgDescriptor::createRegister(Reg);
1989}
1990
1991// If this has a fixed position, we still should allocate the register in the
1992// CCInfo state. Technically we could get away with this for values passed
1993// outside of the normal argument range.
1994static void allocateFixedSGPRInputImpl(CCState &CCInfo,
1995 const TargetRegisterClass *RC,
1996 MCRegister Reg) {
1997 Reg = CCInfo.AllocateReg(Reg);
1998 assert(Reg != AMDGPU::NoRegister)(static_cast <bool> (Reg != AMDGPU::NoRegister) ? void (
0) : __assert_fail ("Reg != AMDGPU::NoRegister", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1998, __extension__ __PRETTY_FUNCTION__))
;
1999 MachineFunction &MF = CCInfo.getMachineFunction();
2000 MF.addLiveIn(Reg, RC);
2001}
2002
2003static void allocateSGPR32Input(CCState &CCInfo, ArgDescriptor &Arg) {
2004 if (Arg) {
2005 allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_32RegClass,
2006 Arg.getRegister());
2007 } else
2008 Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
2009}
2010
2011static void allocateSGPR64Input(CCState &CCInfo, ArgDescriptor &Arg) {
2012 if (Arg) {
2013 allocateFixedSGPRInputImpl(CCInfo, &AMDGPU::SGPR_64RegClass,
2014 Arg.getRegister());
2015 } else
2016 Arg = allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);
2017}
2018
2019/// Allocate implicit function VGPR arguments at the end of allocated user
2020/// arguments.
2021void SITargetLowering::allocateSpecialInputVGPRs(
2022 CCState &CCInfo, MachineFunction &MF,
2023 const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const {
2024 const unsigned Mask = 0x3ff;
2025 ArgDescriptor Arg;
2026
2027 if (Info.hasWorkItemIDX()) {
2028 Arg = allocateVGPR32Input(CCInfo, Mask);
2029 Info.setWorkItemIDX(Arg);
2030 }
2031
2032 if (Info.hasWorkItemIDY()) {
2033 Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);
2034 Info.setWorkItemIDY(Arg);
2035 }
2036
2037 if (Info.hasWorkItemIDZ())
2038 Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));
2039}
2040
2041/// Allocate implicit function VGPR arguments in fixed registers.
2042void SITargetLowering::allocateSpecialInputVGPRsFixed(
2043 CCState &CCInfo, MachineFunction &MF,
2044 const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const {
2045 Register Reg = CCInfo.AllocateReg(AMDGPU::VGPR31);
2046 if (!Reg)
2047 report_fatal_error("failed to allocated VGPR for implicit arguments");
2048
2049 const unsigned Mask = 0x3ff;
2050 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask));
2051 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg, Mask << 10));
2052 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg, Mask << 20));
2053}
2054
2055void SITargetLowering::allocateSpecialInputSGPRs(
2056 CCState &CCInfo,
2057 MachineFunction &MF,
2058 const SIRegisterInfo &TRI,
2059 SIMachineFunctionInfo &Info) const {
2060 auto &ArgInfo = Info.getArgInfo();
2061
2062 // TODO: Unify handling with private memory pointers.
2063 if (Info.hasDispatchPtr())
2064 allocateSGPR64Input(CCInfo, ArgInfo.DispatchPtr);
2065
2066 if (Info.hasQueuePtr())
2067 allocateSGPR64Input(CCInfo, ArgInfo.QueuePtr);
2068
2069 // Implicit arg ptr takes the place of the kernarg segment pointer. This is a
2070 // constant offset from the kernarg segment.
2071 if (Info.hasImplicitArgPtr())
2072 allocateSGPR64Input(CCInfo, ArgInfo.ImplicitArgPtr);
2073
2074 if (Info.hasDispatchID())
2075 allocateSGPR64Input(CCInfo, ArgInfo.DispatchID);
2076
2077 // flat_scratch_init is not applicable for non-kernel functions.
2078
2079 if (Info.hasWorkGroupIDX())
2080 allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDX);
2081
2082 if (Info.hasWorkGroupIDY())
2083 allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDY);
2084
2085 if (Info.hasWorkGroupIDZ())
2086 allocateSGPR32Input(CCInfo, ArgInfo.WorkGroupIDZ);
2087}
2088
2089// Allocate special inputs passed in user SGPRs.
2090void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
2091 MachineFunction &MF,
2092 const SIRegisterInfo &TRI,
2093 SIMachineFunctionInfo &Info) const {
2094 if (Info.hasImplicitBufferPtr()) {
2095 Register ImplicitBufferPtrReg = Info.addImplicitBufferPtr(TRI);
2096 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
2097 CCInfo.AllocateReg(ImplicitBufferPtrReg);
2098 }
2099
2100 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
2101 if (Info.hasPrivateSegmentBuffer()) {
2102 Register PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
2103 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
2104 CCInfo.AllocateReg(PrivateSegmentBufferReg);
2105 }
2106
2107 if (Info.hasDispatchPtr()) {
2108 Register DispatchPtrReg = Info.addDispatchPtr(TRI);
2109 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
2110 CCInfo.AllocateReg(DispatchPtrReg);
2111 }
2112
2113 if (Info.hasQueuePtr()) {
2114 Register QueuePtrReg = Info.addQueuePtr(TRI);
2115 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
2116 CCInfo.AllocateReg(QueuePtrReg);
2117 }
2118
2119 if (Info.hasKernargSegmentPtr()) {
2120 MachineRegisterInfo &MRI = MF.getRegInfo();
2121 Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
2122 CCInfo.AllocateReg(InputPtrReg);
2123
2124 Register VReg = MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
2125 MRI.setType(VReg, LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
2126 }
2127
2128 if (Info.hasDispatchID()) {
2129 Register DispatchIDReg = Info.addDispatchID(TRI);
2130 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
2131 CCInfo.AllocateReg(DispatchIDReg);
2132 }
2133
2134 if (Info.hasFlatScratchInit() && !getSubtarget()->isAmdPalOS()) {
2135 Register FlatScratchInitReg = Info.addFlatScratchInit(TRI);
2136 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
2137 CCInfo.AllocateReg(FlatScratchInitReg);
2138 }
2139
2140 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
2141 // these from the dispatch pointer.
2142}
2143
2144// Allocate special input registers that are initialized per-wave.
2145void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,
2146 MachineFunction &MF,
2147 SIMachineFunctionInfo &Info,
2148 CallingConv::ID CallConv,
2149 bool IsShader) const {
2150 if (Info.hasWorkGroupIDX()) {
2151 Register Reg = Info.addWorkGroupIDX();
2152 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2153 CCInfo.AllocateReg(Reg);
2154 }
2155
2156 if (Info.hasWorkGroupIDY()) {
2157 Register Reg = Info.addWorkGroupIDY();
2158 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2159 CCInfo.AllocateReg(Reg);
2160 }
2161
2162 if (Info.hasWorkGroupIDZ()) {
2163 Register Reg = Info.addWorkGroupIDZ();
2164 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2165 CCInfo.AllocateReg(Reg);
2166 }
2167
2168 if (Info.hasWorkGroupInfo()) {
2169 Register Reg = Info.addWorkGroupInfo();
2170 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
2171 CCInfo.AllocateReg(Reg);
2172 }
2173
2174 if (Info.hasPrivateSegmentWaveByteOffset()) {
2175 // Scratch wave offset passed in system SGPR.
2176 unsigned PrivateSegmentWaveByteOffsetReg;
2177
2178 if (IsShader) {
2179 PrivateSegmentWaveByteOffsetReg =
2180 Info.getPrivateSegmentWaveByteOffsetSystemSGPR();
2181
2182 // This is true if the scratch wave byte offset doesn't have a fixed
2183 // location.
2184 if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) {
2185 PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
2186 Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
2187 }
2188 } else
2189 PrivateSegmentWaveByteOffsetReg = Info.addPrivateSegmentWaveByteOffset();
2190
2191 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
2192 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
2193 }
2194}
2195
2196static void reservePrivateMemoryRegs(const TargetMachine &TM,
2197 MachineFunction &MF,
2198 const SIRegisterInfo &TRI,
2199 SIMachineFunctionInfo &Info) {
2200 // Now that we've figured out where the scratch register inputs are, see if
2201 // should reserve the arguments and use them directly.
2202 MachineFrameInfo &MFI = MF.getFrameInfo();
2203 bool HasStackObjects = MFI.hasStackObjects();
2204 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
2205
2206 // Record that we know we have non-spill stack objects so we don't need to
2207 // check all stack objects later.
2208 if (HasStackObjects)
2209 Info.setHasNonSpillStackObjects(true);
2210
2211 // Everything live out of a block is spilled with fast regalloc, so it's
2212 // almost certain that spilling will be required.
2213 if (TM.getOptLevel() == CodeGenOpt::None)
2214 HasStackObjects = true;
2215
2216 // For now assume stack access is needed in any callee functions, so we need
2217 // the scratch registers to pass in.
2218 bool RequiresStackAccess = HasStackObjects || MFI.hasCalls();
2219
2220 if (!ST.enableFlatScratch()) {
2221 if (RequiresStackAccess && ST.isAmdHsaOrMesa(MF.getFunction())) {
2222 // If we have stack objects, we unquestionably need the private buffer
2223 // resource. For the Code Object V2 ABI, this will be the first 4 user
2224 // SGPR inputs. We can reserve those and use them directly.
2225
2226 Register PrivateSegmentBufferReg =
2227 Info.getPreloadedReg(AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER);
2228 Info.setScratchRSrcReg(PrivateSegmentBufferReg);
2229 } else {
2230 unsigned ReservedBufferReg = TRI.reservedPrivateSegmentBufferReg(MF);
2231 // We tentatively reserve the last registers (skipping the last registers
2232 // which may contain VCC, FLAT_SCR, and XNACK). After register allocation,
2233 // we'll replace these with the ones immediately after those which were
2234 // really allocated. In the prologue copies will be inserted from the
2235 // argument to these reserved registers.
2236
2237 // Without HSA, relocations are used for the scratch pointer and the
2238 // buffer resource setup is always inserted in the prologue. Scratch wave
2239 // offset is still in an input SGPR.
2240 Info.setScratchRSrcReg(ReservedBufferReg);
2241 }
2242 }
2243
2244 MachineRegisterInfo &MRI = MF.getRegInfo();
2245
2246 // For entry functions we have to set up the stack pointer if we use it,
2247 // whereas non-entry functions get this "for free". This means there is no
2248 // intrinsic advantage to using S32 over S34 in cases where we do not have
2249 // calls but do need a frame pointer (i.e. if we are requested to have one
2250 // because frame pointer elimination is disabled). To keep things simple we
2251 // only ever use S32 as the call ABI stack pointer, and so using it does not
2252 // imply we need a separate frame pointer.
2253 //
2254 // Try to use s32 as the SP, but move it if it would interfere with input
2255 // arguments. This won't work with calls though.
2256 //
2257 // FIXME: Move SP to avoid any possible inputs, or find a way to spill input
2258 // registers.
2259 if (!MRI.isLiveIn(AMDGPU::SGPR32)) {
2260 Info.setStackPtrOffsetReg(AMDGPU::SGPR32);
2261 } else {
2262 assert(AMDGPU::isShader(MF.getFunction().getCallingConv()))(static_cast <bool> (AMDGPU::isShader(MF.getFunction().
getCallingConv())) ? void (0) : __assert_fail ("AMDGPU::isShader(MF.getFunction().getCallingConv())"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2262, __extension__
__PRETTY_FUNCTION__))
;
2263
2264 if (MFI.hasCalls())
2265 report_fatal_error("call in graphics shader with too many input SGPRs");
2266
2267 for (unsigned Reg : AMDGPU::SGPR_32RegClass) {
2268 if (!MRI.isLiveIn(Reg)) {
2269 Info.setStackPtrOffsetReg(Reg);
2270 break;
2271 }
2272 }
2273
2274 if (Info.getStackPtrOffsetReg() == AMDGPU::SP_REG)
2275 report_fatal_error("failed to find register for SP");
2276 }
2277
2278 // hasFP should be accurate for entry functions even before the frame is
2279 // finalized, because it does not rely on the known stack size, only
2280 // properties like whether variable sized objects are present.
2281 if (ST.getFrameLowering()->hasFP(MF)) {
2282 Info.setFrameOffsetReg(AMDGPU::SGPR33);
2283 }
2284}
2285
2286bool SITargetLowering::supportSplitCSR(MachineFunction *MF) const {
2287 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
2288 return !Info->isEntryFunction();
2289}
2290
2291void SITargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
2292
2293}
2294
2295void SITargetLowering::insertCopiesSplitCSR(
2296 MachineBasicBlock *Entry,
2297 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
2298 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2299
2300 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
2301 if (!IStart)
2302 return;
2303
2304 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2305 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
2306 MachineBasicBlock::iterator MBBI = Entry->begin();
2307 for (const MCPhysReg *I = IStart; *I; ++I) {
2308 const TargetRegisterClass *RC = nullptr;
2309 if (AMDGPU::SReg_64RegClass.contains(*I))
2310 RC = &AMDGPU::SGPR_64RegClass;
2311 else if (AMDGPU::SReg_32RegClass.contains(*I))
2312 RC = &AMDGPU::SGPR_32RegClass;
2313 else
2314 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2314)
;
2315
2316 Register NewVR = MRI->createVirtualRegister(RC);
2317 // Create copy from CSR to a virtual register.
2318 Entry->addLiveIn(*I);
2319 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
2320 .addReg(*I);
2321
2322 // Insert the copy-back instructions right before the terminator.
2323 for (auto *Exit : Exits)
2324 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
2325 TII->get(TargetOpcode::COPY), *I)
2326 .addReg(NewVR);
2327 }
2328}
2329
2330SDValue SITargetLowering::LowerFormalArguments(
2331 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2332 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2333 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2334 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2335
2336 MachineFunction &MF = DAG.getMachineFunction();
2337 const Function &Fn = MF.getFunction();
2338 FunctionType *FType = MF.getFunction().getFunctionType();
2339 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2340
2341 if (Subtarget->isAmdHsaOS() && AMDGPU::isGraphics(CallConv)) {
2342 DiagnosticInfoUnsupported NoGraphicsHSA(
2343 Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
2344 DAG.getContext()->diagnose(NoGraphicsHSA);
2345 return DAG.getEntryNode();
2346 }
2347
2348 Info->allocateModuleLDSGlobal(Fn.getParent());
2349
2350 SmallVector<ISD::InputArg, 16> Splits;
2351 SmallVector<CCValAssign, 16> ArgLocs;
2352 BitVector Skipped(Ins.size());
2353 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2354 *DAG.getContext());
2355
2356 bool IsGraphics = AMDGPU::isGraphics(CallConv);
2357 bool IsKernel = AMDGPU::isKernel(CallConv);
2358 bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CallConv);
2359
2360 if (IsGraphics) {
2361 assert(!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() &&(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2366, __extension__
__PRETTY_FUNCTION__))
2362 (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) &&(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2366, __extension__
__PRETTY_FUNCTION__))
2363 !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2366, __extension__
__PRETTY_FUNCTION__))
2364 !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2366, __extension__
__PRETTY_FUNCTION__))
2365 !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2366, __extension__
__PRETTY_FUNCTION__))
2366 !Info->hasWorkItemIDZ())(static_cast <bool> (!Info->hasDispatchPtr() &&
!Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit
() || Subtarget->enableFlatScratch()) && !Info->
hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
!Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo
() && !Info->hasWorkItemIDX() && !Info->
hasWorkItemIDY() && !Info->hasWorkItemIDZ()) ? void
(0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && (!Info->hasFlatScratchInit() || Subtarget->enableFlatScratch()) && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2366, __extension__
__PRETTY_FUNCTION__))
;
2367 }
2368
2369 if (CallConv == CallingConv::AMDGPU_PS) {
2370 processPSInputArgs(Splits, CallConv, Ins, Skipped, FType, Info);
2371
2372 // At least one interpolation mode must be enabled or else the GPU will
2373 // hang.
2374 //
2375 // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
2376 // set PSInputAddr, the user wants to enable some bits after the compilation
2377 // based on run-time states. Since we can't know what the final PSInputEna
2378 // will look like, so we shouldn't do anything here and the user should take
2379 // responsibility for the correct programming.
2380 //
2381 // Otherwise, the following restrictions apply:
2382 // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
2383 // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
2384 // enabled too.
2385 if ((Info->getPSInputAddr() & 0x7F) == 0 ||
2386 ((Info->getPSInputAddr() & 0xF) == 0 && Info->isPSInputAllocated(11))) {
2387 CCInfo.AllocateReg(AMDGPU::VGPR0);
2388 CCInfo.AllocateReg(AMDGPU::VGPR1);
2389 Info->markPSInputAllocated(0);
2390 Info->markPSInputEnabled(0);
2391 }
2392 if (Subtarget->isAmdPalOS()) {
2393 // For isAmdPalOS, the user does not enable some bits after compilation
2394 // based on run-time states; the register values being generated here are
2395 // the final ones set in hardware. Therefore we need to apply the
2396 // workaround to PSInputAddr and PSInputEnable together. (The case where
2397 // a bit is set in PSInputAddr but not PSInputEnable is where the
2398 // frontend set up an input arg for a particular interpolation mode, but
2399 // nothing uses that input arg. Really we should have an earlier pass
2400 // that removes such an arg.)
2401 unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
2402 if ((PsInputBits & 0x7F) == 0 ||
2403 ((PsInputBits & 0xF) == 0 && (PsInputBits >> 11 & 1)))
2404 Info->markPSInputEnabled(
2405 countTrailingZeros(Info->getPSInputAddr(), ZB_Undefined));
2406 }
2407 } else if (IsKernel) {
2408 assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX())(static_cast <bool> (Info->hasWorkGroupIDX() &&
Info->hasWorkItemIDX()) ? void (0) : __assert_fail ("Info->hasWorkGroupIDX() && Info->hasWorkItemIDX()"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2408, __extension__
__PRETTY_FUNCTION__))
;
2409 } else {
2410 Splits.append(Ins.begin(), Ins.end());
2411 }
2412
2413 if (IsEntryFunc) {
2414 allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
2415 allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
2416 } else if (!IsGraphics) {
2417 // For the fixed ABI, pass workitem IDs in the last argument register.
2418 allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
2419 }
2420
2421 if (IsKernel) {
2422 analyzeFormalArgumentsCompute(CCInfo, Ins);
2423 } else {
2424 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg);
2425 CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
2426 }
2427
2428 SmallVector<SDValue, 16> Chains;
2429
2430 // FIXME: This is the minimum kernel argument alignment. We should improve
2431 // this to the maximum alignment of the arguments.
2432 //
2433 // FIXME: Alignment of explicit arguments totally broken with non-0 explicit
2434 // kern arg offset.
2435 const Align KernelArgBaseAlign = Align(16);
2436
2437 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
2438 const ISD::InputArg &Arg = Ins[i];
2439 if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
2440 InVals.push_back(DAG.getUNDEF(Arg.VT));
2441 continue;
2442 }
2443
2444 CCValAssign &VA = ArgLocs[ArgIdx++];
2445 MVT VT = VA.getLocVT();
2446
2447 if (IsEntryFunc && VA.isMemLoc()) {
2448 VT = Ins[i].VT;
2449 EVT MemVT = VA.getLocVT();
2450
2451 const uint64_t Offset = VA.getLocMemOffset();
2452 Align Alignment = commonAlignment(KernelArgBaseAlign, Offset);
2453
2454 if (Arg.Flags.isByRef()) {
2455 SDValue Ptr = lowerKernArgParameterPtr(DAG, DL, Chain, Offset);
2456
2457 const GCNTargetMachine &TM =
2458 static_cast<const GCNTargetMachine &>(getTargetMachine());
2459 if (!TM.isNoopAddrSpaceCast(AMDGPUAS::CONSTANT_ADDRESS,
2460 Arg.Flags.getPointerAddrSpace())) {
2461 Ptr = DAG.getAddrSpaceCast(DL, VT, Ptr, AMDGPUAS::CONSTANT_ADDRESS,
2462 Arg.Flags.getPointerAddrSpace());
2463 }
2464
2465 InVals.push_back(Ptr);
2466 continue;
2467 }
2468
2469 SDValue Arg = lowerKernargMemParameter(
2470 DAG, VT, MemVT, DL, Chain, Offset, Alignment, Ins[i].Flags.isSExt(), &Ins[i]);
2471 Chains.push_back(Arg.getValue(1));
2472
2473 auto *ParamTy =
2474 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
2475 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
2476 ParamTy && (ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
2477 ParamTy->getAddressSpace() == AMDGPUAS::REGION_ADDRESS)) {
2478 // On SI local pointers are just offsets into LDS, so they are always
2479 // less than 16-bits. On CI and newer they could potentially be
2480 // real pointers, so we can't guarantee their size.
2481 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
2482 DAG.getValueType(MVT::i16));
2483 }
2484
2485 InVals.push_back(Arg);
2486 continue;
2487 } else if (!IsEntryFunc && VA.isMemLoc()) {
2488 SDValue Val = lowerStackParameter(DAG, VA, DL, Chain, Arg);
2489 InVals.push_back(Val);
2490 if (!Arg.Flags.isByVal())
2491 Chains.push_back(Val.getValue(1));
2492 continue;
2493 }
2494
2495 assert(VA.isRegLoc() && "Parameter must be in a register!")(static_cast <bool> (VA.isRegLoc() && "Parameter must be in a register!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Parameter must be in a register!\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2495, __extension__
__PRETTY_FUNCTION__))
;
2496
2497 Register Reg = VA.getLocReg();
2498 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2499 EVT ValVT = VA.getValVT();
2500
2501 Reg = MF.addLiveIn(Reg, RC);
2502 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
2503
2504 if (Arg.Flags.isSRet()) {
2505 // The return object should be reasonably addressable.
2506
2507 // FIXME: This helps when the return is a real sret. If it is a
2508 // automatically inserted sret (i.e. CanLowerReturn returns false), an
2509 // extra copy is inserted in SelectionDAGBuilder which obscures this.
2510 unsigned NumBits
2511 = 32 - getSubtarget()->getKnownHighZeroBitsForFrameIndex();
2512 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2513 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), NumBits)));
2514 }
2515
2516 // If this is an 8 or 16-bit value, it is really passed promoted
2517 // to 32 bits. Insert an assert[sz]ext to capture this, then
2518 // truncate to the right size.
2519 switch (VA.getLocInfo()) {
2520 case CCValAssign::Full:
2521 break;
2522 case CCValAssign::BCvt:
2523 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2524 break;
2525 case CCValAssign::SExt:
2526 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val,
2527 DAG.getValueType(ValVT));
2528 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2529 break;
2530 case CCValAssign::ZExt:
2531 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2532 DAG.getValueType(ValVT));
2533 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2534 break;
2535 case CCValAssign::AExt:
2536 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2537 break;
2538 default:
2539 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2539)
;
2540 }
2541
2542 InVals.push_back(Val);
2543 }
2544
2545 // Start adding system SGPRs.
2546 if (IsEntryFunc) {
2547 allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsGraphics);
2548 } else {
2549 CCInfo.AllocateReg(Info->getScratchRSrcReg());
2550 if (!IsGraphics)
2551 allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
2552 }
2553
2554 auto &ArgUsageInfo =
2555 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2556 ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
2557
2558 unsigned StackArgSize = CCInfo.getNextStackOffset();
2559 Info->setBytesInStackArgArea(StackArgSize);
2560
2561 return Chains.empty() ? Chain :
2562 DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
2563}
2564
2565// TODO: If return values can't fit in registers, we should return as many as
2566// possible in registers before passing on stack.
2567bool SITargetLowering::CanLowerReturn(
2568 CallingConv::ID CallConv,
2569 MachineFunction &MF, bool IsVarArg,
2570 const SmallVectorImpl<ISD::OutputArg> &Outs,
2571 LLVMContext &Context) const {
2572 // Replacing returns with sret/stack usage doesn't make sense for shaders.
2573 // FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
2574 // for shaders. Vector types should be explicitly handled by CC.
2575 if (AMDGPU::isEntryFunctionCC(CallConv))
2576 return true;
2577
2578 SmallVector<CCValAssign, 16> RVLocs;
2579 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2580 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
2581}
2582
2583SDValue
2584SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2585 bool isVarArg,
2586 const SmallVectorImpl<ISD::OutputArg> &Outs,
2587 const SmallVectorImpl<SDValue> &OutVals,
2588 const SDLoc &DL, SelectionDAG &DAG) const {
2589 MachineFunction &MF = DAG.getMachineFunction();
2590 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2591
2592 if (AMDGPU::isKernel(CallConv)) {
2593 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
2594 OutVals, DL, DAG);
2595 }
2596
2597 bool IsShader = AMDGPU::isShader(CallConv);
2598
2599 Info->setIfReturnsVoid(Outs.empty());
2600 bool IsWaveEnd = Info->returnsVoid() && IsShader;
2601
2602 // CCValAssign - represent the assignment of the return value to a location.
2603 SmallVector<CCValAssign, 48> RVLocs;
2604 SmallVector<ISD::OutputArg, 48> Splits;
2605
2606 // CCState - Info about the registers and stack slots.
2607 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2608 *DAG.getContext());
2609
2610 // Analyze outgoing return values.
2611 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2612
2613 SDValue Flag;
2614 SmallVector<SDValue, 48> RetOps;
2615 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2616
2617 // Add return address for callable functions.
2618 if (!Info->isEntryFunction()) {
2619 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2620 SDValue ReturnAddrReg = CreateLiveInRegister(
2621 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2622
2623 SDValue ReturnAddrVirtualReg =
2624 DAG.getRegister(MF.getRegInfo().createVirtualRegister(
2625 CallConv != CallingConv::AMDGPU_Gfx
2626 ? &AMDGPU::CCR_SGPR_64RegClass
2627 : &AMDGPU::Gfx_CCR_SGPR_64RegClass),
2628 MVT::i64);
2629 Chain =
2630 DAG.getCopyToReg(Chain, DL, ReturnAddrVirtualReg, ReturnAddrReg, Flag);
2631 Flag = Chain.getValue(1);
2632 RetOps.push_back(ReturnAddrVirtualReg);
2633 }
2634
2635 // Copy the result values into the output registers.
2636 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E;
2637 ++I, ++RealRVLocIdx) {
2638 CCValAssign &VA = RVLocs[I];
2639 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2639, __extension__
__PRETTY_FUNCTION__))
;
2640 // TODO: Partially return in registers if return values don't fit.
2641 SDValue Arg = OutVals[RealRVLocIdx];
2642
2643 // Copied from other backends.
2644 switch (VA.getLocInfo()) {
2645 case CCValAssign::Full:
2646 break;
2647 case CCValAssign::BCvt:
2648 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2649 break;
2650 case CCValAssign::SExt:
2651 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2652 break;
2653 case CCValAssign::ZExt:
2654 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2655 break;
2656 case CCValAssign::AExt:
2657 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2658 break;
2659 default:
2660 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2660)
;
2661 }
2662
2663 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2664 Flag = Chain.getValue(1);
2665 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2666 }
2667
2668 // FIXME: Does sret work properly?
2669 if (!Info->isEntryFunction()) {
2670 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2671 const MCPhysReg *I =
2672 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2673 if (I) {
2674 for (; *I; ++I) {
2675 if (AMDGPU::SReg_64RegClass.contains(*I))
2676 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2677 else if (AMDGPU::SReg_32RegClass.contains(*I))
2678 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2679 else
2680 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2680)
;
2681 }
2682 }
2683 }
2684
2685 // Update chain and glue.
2686 RetOps[0] = Chain;
2687 if (Flag.getNode())
2688 RetOps.push_back(Flag);
2689
2690 unsigned Opc = AMDGPUISD::ENDPGM;
2691 if (!IsWaveEnd) {
2692 if (IsShader)
2693 Opc = AMDGPUISD::RETURN_TO_EPILOG;
2694 else if (CallConv == CallingConv::AMDGPU_Gfx)
2695 Opc = AMDGPUISD::RET_GFX_FLAG;
2696 else
2697 Opc = AMDGPUISD::RET_FLAG;
2698 }
2699
2700 return DAG.getNode(Opc, DL, MVT::Other, RetOps);
2701}
2702
2703SDValue SITargetLowering::LowerCallResult(
2704 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2705 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2706 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool IsThisReturn,
2707 SDValue ThisVal) const {
2708 CCAssignFn *RetCC = CCAssignFnForReturn(CallConv, IsVarArg);
2709
2710 // Assign locations to each value returned by this call.
2711 SmallVector<CCValAssign, 16> RVLocs;
2712 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2713 *DAG.getContext());
2714 CCInfo.AnalyzeCallResult(Ins, RetCC);
2715
2716 // Copy all of the result registers out of their specified physreg.
2717 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2718 CCValAssign VA = RVLocs[i];
2719 SDValue Val;
2720
2721 if (VA.isRegLoc()) {
2722 Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2723 Chain = Val.getValue(1);
2724 InFlag = Val.getValue(2);
2725 } else if (VA.isMemLoc()) {
2726 report_fatal_error("TODO: return values in memory");
2727 } else
2728 llvm_unreachable("unknown argument location type")::llvm::llvm_unreachable_internal("unknown argument location type"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 2728)
;
2729
2730 switch (VA.getLocInfo()) {
2731 case CCValAssign::Full:
2732 break;
2733 case CCValAssign::BCvt:
2734 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2735 break;
2736 case CCValAssign::ZExt:
2737 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2738 DAG.getValueType(VA.getValVT()));
2739 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2740 break;
2741 case CCValAssign::SExt:
2742 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2743 DAG.getValueType(VA.getValVT()));
2744 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2745 break;
2746 case CCValAssign::AExt:
2747 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2748 break;
2749 default:
2750 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2750)
;
2751 }
2752
2753 InVals.push_back(Val);
2754 }
2755
2756 return Chain;
2757}
2758
2759// Add code to pass special inputs required depending on used features separate
2760// from the explicit user arguments present in the IR.
2761void SITargetLowering::passSpecialInputs(
2762 CallLoweringInfo &CLI,
2763 CCState &CCInfo,
2764 const SIMachineFunctionInfo &Info,
2765 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
2766 SmallVectorImpl<SDValue> &MemOpChains,
2767 SDValue Chain) const {
2768 // If we don't have a call site, this was a call inserted by
2769 // legalization. These can never use special inputs.
2770 if (!CLI.CB)
2771 return;
2772
2773 SelectionDAG &DAG = CLI.DAG;
2774 const SDLoc &DL = CLI.DL;
2775 const Function &F = DAG.getMachineFunction().getFunction();
2776
2777 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2778 const AMDGPUFunctionArgInfo &CallerArgInfo = Info.getArgInfo();
2779
2780 const AMDGPUFunctionArgInfo *CalleeArgInfo
2781 = &AMDGPUArgumentUsageInfo::FixedABIFunctionInfo;
2782 if (const Function *CalleeFunc = CLI.CB->getCalledFunction()) {
2783 auto &ArgUsageInfo =
2784 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2785 CalleeArgInfo = &ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
2786 }
2787
2788 // TODO: Unify with private memory register handling. This is complicated by
2789 // the fact that at least in kernels, the input argument is not necessarily
2790 // in the same location as the input.
2791 static constexpr std::pair<AMDGPUFunctionArgInfo::PreloadedValue,
2792 StringLiteral> ImplicitAttrs[] = {
2793 {AMDGPUFunctionArgInfo::DISPATCH_PTR, "amdgpu-no-dispatch-ptr"},
2794 {AMDGPUFunctionArgInfo::QUEUE_PTR, "amdgpu-no-queue-ptr" },
2795 {AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR, "amdgpu-no-implicitarg-ptr"},
2796 {AMDGPUFunctionArgInfo::DISPATCH_ID, "amdgpu-no-dispatch-id"},
2797 {AMDGPUFunctionArgInfo::WORKGROUP_ID_X, "amdgpu-no-workgroup-id-x"},
2798 {AMDGPUFunctionArgInfo::WORKGROUP_ID_Y,"amdgpu-no-workgroup-id-y"},
2799 {AMDGPUFunctionArgInfo::WORKGROUP_ID_Z,"amdgpu-no-workgroup-id-z"}
2800 };
2801
2802 for (auto Attr : ImplicitAttrs) {
2803 const ArgDescriptor *OutgoingArg;
2804 const TargetRegisterClass *ArgRC;
2805 LLT ArgTy;
2806
2807 AMDGPUFunctionArgInfo::PreloadedValue InputID = Attr.first;
2808
2809 // If the callee does not use the attribute value, skip copying the value.
2810 if (CLI.CB->hasFnAttr(Attr.second))
2811 continue;
2812
2813 std::tie(OutgoingArg, ArgRC, ArgTy) =
2814 CalleeArgInfo->getPreloadedValue(InputID);
2815 if (!OutgoingArg)
2816 continue;
2817
2818 const ArgDescriptor *IncomingArg;
2819 const TargetRegisterClass *IncomingArgRC;
2820 LLT Ty;
2821 std::tie(IncomingArg, IncomingArgRC, Ty) =
2822 CallerArgInfo.getPreloadedValue(InputID);
2823 assert(IncomingArgRC == ArgRC)(static_cast <bool> (IncomingArgRC == ArgRC) ? void (0)
: __assert_fail ("IncomingArgRC == ArgRC", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2823, __extension__ __PRETTY_FUNCTION__))
;
2824
2825 // All special arguments are ints for now.
2826 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;
2827 SDValue InputReg;
2828
2829 if (IncomingArg) {
2830 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg);
2831 } else if (InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR) {
2832 // The implicit arg ptr is special because it doesn't have a corresponding
2833 // input for kernels, and is computed from the kernarg segment pointer.
2834 InputReg = getImplicitArgPtr(DAG, DL);
2835 } else {
2836 // We may have proven the input wasn't needed, although the ABI is
2837 // requiring it. We just need to allocate the register appropriately.
2838 InputReg = DAG.getUNDEF(ArgVT);
2839 }
2840
2841 if (OutgoingArg->isRegister()) {
2842 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2843 if (!CCInfo.AllocateReg(OutgoingArg->getRegister()))
2844 report_fatal_error("failed to allocate implicit input argument");
2845 } else {
2846 unsigned SpecialArgOffset =
2847 CCInfo.AllocateStack(ArgVT.getStoreSize(), Align(4));
2848 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2849 SpecialArgOffset);
2850 MemOpChains.push_back(ArgStore);
2851 }
2852 }
2853
2854 // Pack workitem IDs into a single register or pass it as is if already
2855 // packed.
2856 const ArgDescriptor *OutgoingArg;
2857 const TargetRegisterClass *ArgRC;
2858 LLT Ty;
2859
2860 std::tie(OutgoingArg, ArgRC, Ty) =
2861 CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
2862 if (!OutgoingArg)
2863 std::tie(OutgoingArg, ArgRC, Ty) =
2864 CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
2865 if (!OutgoingArg)
2866 std::tie(OutgoingArg, ArgRC, Ty) =
2867 CalleeArgInfo->getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
2868 if (!OutgoingArg)
2869 return;
2870
2871 const ArgDescriptor *IncomingArgX = std::get<0>(
2872 CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X));
2873 const ArgDescriptor *IncomingArgY = std::get<0>(
2874 CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y));
2875 const ArgDescriptor *IncomingArgZ = std::get<0>(
2876 CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z));
2877
2878 SDValue InputReg;
2879 SDLoc SL;
2880
2881 const bool NeedWorkItemIDX = !CLI.CB->hasFnAttr("amdgpu-no-workitem-id-x");
2882 const bool NeedWorkItemIDY = !CLI.CB->hasFnAttr("amdgpu-no-workitem-id-y");
2883 const bool NeedWorkItemIDZ = !CLI.CB->hasFnAttr("amdgpu-no-workitem-id-z");
2884
2885 // If incoming ids are not packed we need to pack them.
2886 if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo->WorkItemIDX &&
2887 NeedWorkItemIDX) {
2888 if (Subtarget->getMaxWorkitemID(F, 0) != 0) {
2889 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX);
2890 } else {
2891 InputReg = DAG.getConstant(0, DL, MVT::i32);
2892 }
2893 }
2894
2895 if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo->WorkItemIDY &&
2896 NeedWorkItemIDY && Subtarget->getMaxWorkitemID(F, 1) != 0) {
2897 SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY);
2898 Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y,
2899 DAG.getShiftAmountConstant(10, MVT::i32, SL));
2900 InputReg = InputReg.getNode() ?
2901 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y;
2902 }
2903
2904 if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo->WorkItemIDZ &&
2905 NeedWorkItemIDZ && Subtarget->getMaxWorkitemID(F, 2) != 0) {
2906 SDValue Z = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgZ);
2907 Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z,
2908 DAG.getShiftAmountConstant(20, MVT::i32, SL));
2909 InputReg = InputReg.getNode() ?
2910 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Z) : Z;
2911 }
2912
2913 if (!InputReg && (NeedWorkItemIDX || NeedWorkItemIDY || NeedWorkItemIDZ)) {
2914 if (!IncomingArgX && !IncomingArgY && !IncomingArgZ) {
2915 // We're in a situation where the outgoing function requires the workitem
2916 // ID, but the calling function does not have it (e.g a graphics function
2917 // calling a C calling convention function). This is illegal, but we need
2918 // to produce something.
2919 InputReg = DAG.getUNDEF(MVT::i32);
2920 } else {
2921 // Workitem ids are already packed, any of present incoming arguments
2922 // will carry all required fields.
2923 ArgDescriptor IncomingArg = ArgDescriptor::createArg(
2924 IncomingArgX ? *IncomingArgX :
2925 IncomingArgY ? *IncomingArgY :
2926 *IncomingArgZ, ~0u);
2927 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, IncomingArg);
2928 }
2929 }
2930
2931 if (OutgoingArg->isRegister()) {
2932 if (InputReg)
2933 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2934
2935 CCInfo.AllocateReg(OutgoingArg->getRegister());
2936 } else {
2937 unsigned SpecialArgOffset = CCInfo.AllocateStack(4, Align(4));
2938 if (InputReg) {
2939 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2940 SpecialArgOffset);
2941 MemOpChains.push_back(ArgStore);
2942 }
2943 }
2944}
2945
2946static bool canGuaranteeTCO(CallingConv::ID CC) {
2947 return CC == CallingConv::Fast;
2948}
2949
2950/// Return true if we might ever do TCO for calls with this calling convention.
2951static bool mayTailCallThisCC(CallingConv::ID CC) {
2952 switch (CC) {
2953 case CallingConv::C:
2954 case CallingConv::AMDGPU_Gfx:
2955 return true;
2956 default:
2957 return canGuaranteeTCO(CC);
2958 }
2959}
2960
2961bool SITargetLowering::isEligibleForTailCallOptimization(
2962 SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
2963 const SmallVectorImpl<ISD::OutputArg> &Outs,
2964 const SmallVectorImpl<SDValue> &OutVals,
2965 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2966 if (!mayTailCallThisCC(CalleeCC))
2967 return false;
2968
2969 // For a divergent call target, we need to do a waterfall loop over the
2970 // possible callees which precludes us from using a simple jump.
2971 if (Callee->isDivergent())
2972 return false;
2973
2974 MachineFunction &MF = DAG.getMachineFunction();
2975 const Function &CallerF = MF.getFunction();
2976 CallingConv::ID CallerCC = CallerF.getCallingConv();
2977 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2978 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2979
2980 // Kernels aren't callable, and don't have a live in return address so it
2981 // doesn't make sense to do a tail call with entry functions.
2982 if (!CallerPreserved)
2983 return false;
2984
2985 bool CCMatch = CallerCC == CalleeCC;
2986
2987 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
2988 if (canGuaranteeTCO(CalleeCC) && CCMatch)
2989 return true;
2990 return false;
2991 }
2992
2993 // TODO: Can we handle var args?
2994 if (IsVarArg)
2995 return false;
2996
2997 for (const Argument &Arg : CallerF.args()) {
2998 if (Arg.hasByValAttr())
2999 return false;
3000 }
3001
3002 LLVMContext &Ctx = *DAG.getContext();
3003
3004 // Check that the call results are passed in the same way.
3005 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, Ctx, Ins,
3006 CCAssignFnForCall(CalleeCC, IsVarArg),
3007 CCAssignFnForCall(CallerCC, IsVarArg)))
3008 return false;
3009
3010 // The callee has to preserve all registers the caller needs to preserve.
3011 if (!CCMatch) {
3012 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
3013 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
3014 return false;
3015 }
3016
3017 // Nothing more to check if the callee is taking no arguments.
3018 if (Outs.empty())
3019 return true;
3020
3021 SmallVector<CCValAssign, 16> ArgLocs;
3022 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
3023
3024 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
3025
3026 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
3027 // If the stack arguments for this call do not fit into our own save area then
3028 // the call cannot be made tail.
3029 // TODO: Is this really necessary?
3030 if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
3031 return false;
3032
3033 const MachineRegisterInfo &MRI = MF.getRegInfo();
3034 return parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals);
3035}
3036
3037bool SITargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3038 if (!CI->isTailCall())
3039 return false;
3040
3041 const Function *ParentFn = CI->getParent()->getParent();
3042 if (AMDGPU::isEntryFunctionCC(ParentFn->getCallingConv()))
3043 return false;
3044 return true;
3045}
3046
3047// The wave scratch offset register is used as the global base pointer.
3048SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
3049 SmallVectorImpl<SDValue> &InVals) const {
3050 SelectionDAG &DAG = CLI.DAG;
3051 const SDLoc &DL = CLI.DL;
3052 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3053 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3054 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3055 SDValue Chain = CLI.Chain;
3056 SDValue Callee = CLI.Callee;
3057 bool &IsTailCall = CLI.IsTailCall;
3058 CallingConv::ID CallConv = CLI.CallConv;
3059 bool IsVarArg = CLI.IsVarArg;
3060 bool IsSibCall = false;
3061 bool IsThisReturn = false;
3062 MachineFunction &MF = DAG.getMachineFunction();
3063
3064 if (Callee.isUndef() || isNullConstant(Callee)) {
3065 if (!CLI.IsTailCall) {
3066 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
3067 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
3068 }
3069
3070 return Chain;
3071 }
3072
3073 if (IsVarArg) {
3074 return lowerUnhandledCall(CLI, InVals,
3075 "unsupported call to variadic function ");
3076 }
3077
3078 if (!CLI.CB)
3079 report_fatal_error("unsupported libcall legalization");
3080
3081 if (IsTailCall && MF.getTarget().Options.GuaranteedTailCallOpt) {
3082 return lowerUnhandledCall(CLI, InVals,
3083 "unsupported required tail call to function ");
3084 }
3085
3086 if (AMDGPU::isShader(CallConv)) {
3087 // Note the issue is with the CC of the called function, not of the call
3088 // itself.
3089 return lowerUnhandledCall(CLI, InVals,
3090 "unsupported call to a shader function ");
3091 }
3092
3093 if (AMDGPU::isShader(MF.getFunction().getCallingConv()) &&
3094 CallConv != CallingConv::AMDGPU_Gfx) {
3095 // Only allow calls with specific calling conventions.
3096 return lowerUnhandledCall(CLI, InVals,
3097 "unsupported calling convention for call from "
3098 "graphics shader of function ");
3099 }
3100
3101 if (IsTailCall) {
3102 IsTailCall = isEligibleForTailCallOptimization(
3103 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
3104 if (!IsTailCall && CLI.CB && CLI.CB->isMustTailCall()) {
3105 report_fatal_error("failed to perform tail call elimination on a call "
3106 "site marked musttail");
3107 }
3108
3109 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
3110
3111 // A sibling call is one where we're under the usual C ABI and not planning
3112 // to change that but can still do a tail call:
3113 if (!TailCallOpt && IsTailCall)
3114 IsSibCall = true;
3115
3116 if (IsTailCall)
3117 ++NumTailCalls;
3118 }
3119
3120 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
3121 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3122 SmallVector<SDValue, 8> MemOpChains;
3123
3124 // Analyze operands of the call, assigning locations to each operand.
3125 SmallVector<CCValAssign, 16> ArgLocs;
3126 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
3127 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, IsVarArg);
3128
3129 if (CallConv != CallingConv::AMDGPU_Gfx) {
3130 // With a fixed ABI, allocate fixed registers before user arguments.
3131 passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
3132 }
3133
3134 CCInfo.AnalyzeCallOperands(Outs, AssignFn);
3135
3136 // Get a count of how many bytes are to be pushed on the stack.
3137 unsigned NumBytes = CCInfo.getNextStackOffset();
3138
3139 if (IsSibCall) {
3140 // Since we're not changing the ABI to make this a tail call, the memory
3141 // operands are already available in the caller's incoming argument space.
3142 NumBytes = 0;
3143 }
3144
3145 // FPDiff is the byte offset of the call's argument area from the callee's.
3146 // Stores to callee stack arguments will be placed in FixedStackSlots offset
3147 // by this amount for a tail call. In a sibling call it must be 0 because the
3148 // caller will deallocate the entire stack and the callee still expects its
3149 // arguments to begin at SP+0. Completely unused for non-tail calls.
3150 int32_t FPDiff = 0;
3151 MachineFrameInfo &MFI = MF.getFrameInfo();
3152
3153 // Adjust the stack pointer for the new arguments...
3154 // These operations are automatically eliminated by the prolog/epilog pass
3155 if (!IsSibCall) {
3156 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
3157
3158 if (!Subtarget->enableFlatScratch()) {
3159 SmallVector<SDValue, 4> CopyFromChains;
3160
3161 // In the HSA case, this should be an identity copy.
3162 SDValue ScratchRSrcReg
3163 = DAG.getCopyFromReg(Chain, DL, Info->getScratchRSrcReg(), MVT::v4i32);
3164 RegsToPass.emplace_back(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
3165 CopyFromChains.push_back(ScratchRSrcReg.getValue(1));
3166 Chain = DAG.getTokenFactor(DL, CopyFromChains);
3167 }
3168 }
3169
3170 MVT PtrVT = MVT::i32;
3171
3172 // Walk the register/memloc assignments, inserting copies/loads.
3173 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3174 CCValAssign &VA = ArgLocs[i];
3175 SDValue Arg = OutVals[i];
3176
3177 // Promote the value if needed.
3178 switch (VA.getLocInfo()) {
3179 case CCValAssign::Full:
3180 break;
3181 case CCValAssign::BCvt:
3182 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3183 break;
3184 case CCValAssign::ZExt:
3185 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3186 break;
3187 case CCValAssign::SExt:
3188 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
3189 break;
3190 case CCValAssign::AExt:
3191 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
3192 break;
3193 case CCValAssign::FPExt:
3194 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
3195 break;
3196 default:
3197 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3197)
;
3198 }
3199
3200 if (VA.isRegLoc()) {
3201 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3202 } else {
3203 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3203, __extension__ __PRETTY_FUNCTION__))
;
3204
3205 SDValue DstAddr;
3206 MachinePointerInfo DstInfo;
3207
3208 unsigned LocMemOffset = VA.getLocMemOffset();
3209 int32_t Offset = LocMemOffset;
3210
3211 SDValue PtrOff = DAG.getConstant(Offset, DL, PtrVT);
3212 MaybeAlign Alignment;
3213
3214 if (IsTailCall) {
3215 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3216 unsigned OpSize = Flags.isByVal() ?
3217 Flags.getByValSize() : VA.getValVT().getStoreSize();
3218
3219 // FIXME: We can have better than the minimum byval required alignment.
3220 Alignment =
3221 Flags.isByVal()
3222 ? Flags.getNonZeroByValAlign()
3223 : commonAlignment(Subtarget->getStackAlignment(), Offset);
3224
3225 Offset = Offset + FPDiff;
3226 int FI = MFI.CreateFixedObject(OpSize, Offset, true);
3227
3228 DstAddr = DAG.getFrameIndex(FI, PtrVT);
3229 DstInfo = MachinePointerInfo::getFixedStack(MF, FI);
3230
3231 // Make sure any stack arguments overlapping with where we're storing
3232 // are loaded before this eventual operation. Otherwise they'll be
3233 // clobbered.
3234
3235 // FIXME: Why is this really necessary? This seems to just result in a
3236 // lot of code to copy the stack and write them back to the same
3237 // locations, which are supposed to be immutable?
3238 Chain = addTokenForArgument(Chain, DAG, MFI, FI);
3239 } else {
3240 // Stores to the argument stack area are relative to the stack pointer.
3241 SDValue SP = DAG.getCopyFromReg(Chain, DL, Info->getStackPtrOffsetReg(),
3242 MVT::i32);
3243 DstAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, SP, PtrOff);
3244 DstInfo = MachinePointerInfo::getStack(MF, LocMemOffset);
3245 Alignment =
3246 commonAlignment(Subtarget->getStackAlignment(), LocMemOffset);
3247 }
3248
3249 if (Outs[i].Flags.isByVal()) {
3250 SDValue SizeNode =
3251 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32);
3252 SDValue Cpy =
3253 DAG.getMemcpy(Chain, DL, DstAddr, Arg, SizeNode,
3254 Outs[i].Flags.getNonZeroByValAlign(),
3255 /*isVol = */ false, /*AlwaysInline = */ true,
3256 /*isTailCall = */ false, DstInfo,
3257 MachinePointerInfo(AMDGPUAS::PRIVATE_ADDRESS));
3258
3259 MemOpChains.push_back(Cpy);
3260 } else {
3261 SDValue Store =
3262 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, Alignment);
3263 MemOpChains.push_back(Store);
3264 }
3265 }
3266 }
3267
3268 if (!MemOpChains.empty())
3269 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3270
3271 // Build a sequence of copy-to-reg nodes chained together with token chain
3272 // and flag operands which copy the outgoing args into the appropriate regs.
3273 SDValue InFlag;
3274 for (auto &RegToPass : RegsToPass) {
3275 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
3276 RegToPass.second, InFlag);
3277 InFlag = Chain.getValue(1);
3278 }
3279
3280
3281 SDValue PhysReturnAddrReg;
3282 if (IsTailCall) {
3283 // Since the return is being combined with the call, we need to pass on the
3284 // return address.
3285
3286 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
3287 SDValue ReturnAddrReg = CreateLiveInRegister(
3288 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
3289
3290 PhysReturnAddrReg = DAG.getRegister(TRI->getReturnAddressReg(MF),
3291 MVT::i64);
3292 Chain = DAG.getCopyToReg(Chain, DL, PhysReturnAddrReg, ReturnAddrReg, InFlag);
3293 InFlag = Chain.getValue(1);
3294 }
3295
3296 // We don't usually want to end the call-sequence here because we would tidy
3297 // the frame up *after* the call, however in the ABI-changing tail-call case
3298 // we've carefully laid out the parameters so that when sp is reset they'll be
3299 // in the correct location.
3300 if (IsTailCall && !IsSibCall) {
3301 Chain = DAG.getCALLSEQ_END(Chain,
3302 DAG.getTargetConstant(NumBytes, DL, MVT::i32),
3303 DAG.getTargetConstant(0, DL, MVT::i32),
3304 InFlag, DL);
3305 InFlag = Chain.getValue(1);
3306 }
3307
3308 std::vector<SDValue> Ops;
3309 Ops.push_back(Chain);
3310 Ops.push_back(Callee);
3311 // Add a redundant copy of the callee global which will not be legalized, as
3312 // we need direct access to the callee later.
3313 if (GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(Callee)) {
3314 const GlobalValue *GV = GSD->getGlobal();
3315 Ops.push_back(DAG.getTargetGlobalAddress(GV, DL, MVT::i64));
3316 } else {
3317 Ops.push_back(DAG.getTargetConstant(0, DL, MVT::i64));
3318 }
3319
3320 if (IsTailCall) {
3321 // Each tail call may have to adjust the stack by a different amount, so
3322 // this information must travel along with the operation for eventual
3323 // consumption by emitEpilogue.
3324 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
3325
3326 Ops.push_back(PhysReturnAddrReg);
3327 }
3328
3329 // Add argument registers to the end of the list so that they are known live
3330 // into the call.
3331 for (auto &RegToPass : RegsToPass) {
3332 Ops.push_back(DAG.getRegister(RegToPass.first,
3333 RegToPass.second.getValueType()));
3334 }
3335
3336 // Add a register mask operand representing the call-preserved registers.
3337
3338 auto *TRI = static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
3339 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3340 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 3340, __extension__
__PRETTY_FUNCTION__))
;
3341 Ops.push_back(DAG.getRegisterMask(Mask));
3342
3343 if (InFlag.getNode())
3344 Ops.push_back(InFlag);
3345
3346 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3347
3348 // If we're doing a tall call, use a TC_RETURN here rather than an
3349 // actual call instruction.
3350 if (IsTailCall) {
3351 MFI.setHasTailCall();
3352 return DAG.getNode(AMDGPUISD::TC_RETURN, DL, NodeTys, Ops);
3353 }
3354
3355 // Returns a chain and a flag for retval copy to use.
3356 SDValue Call = DAG.getNode(AMDGPUISD::CALL, DL, NodeTys, Ops);
3357 Chain = Call.getValue(0);
3358 InFlag = Call.getValue(1);
3359
3360 uint64_t CalleePopBytes = NumBytes;
3361 Chain = DAG.getCALLSEQ_END(Chain, DAG.getTargetConstant(0, DL, MVT::i32),
3362 DAG.getTargetConstant(CalleePopBytes, DL, MVT::i32),
3363 InFlag, DL);
3364 if (!Ins.empty())
3365 InFlag = Chain.getValue(1);
3366
3367 // Handle result values, copying them out of physregs into vregs that we
3368 // return.
3369 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3370 InVals, IsThisReturn,
3371 IsThisReturn ? OutVals[0] : SDValue());
3372}
3373
3374// This is identical to the default implementation in ExpandDYNAMIC_STACKALLOC,
3375// except for applying the wave size scale to the increment amount.
3376SDValue SITargetLowering::lowerDYNAMIC_STACKALLOCImpl(
3377 SDValue Op, SelectionDAG &DAG) const {
3378 const MachineFunction &MF = DAG.getMachineFunction();
3379 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
3380
3381 SDLoc dl(Op);
3382 EVT VT = Op.getValueType();
3383 SDValue Tmp1 = Op;
3384 SDValue Tmp2 = Op.getValue(1);
3385 SDValue Tmp3 = Op.getOperand(2);
3386 SDValue Chain = Tmp1.getOperand(0);
3387
3388 Register SPReg = Info->getStackPtrOffsetReg();
3389
3390 // Chain the dynamic stack allocation so that it doesn't modify the stack
3391 // pointer when other instructions are using the stack.
3392 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
3393
3394 SDValue Size = Tmp2.getOperand(1);
3395 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
3396 Chain = SP.getValue(1);
3397 MaybeAlign Alignment = cast<ConstantSDNode>(Tmp3)->getMaybeAlignValue();
3398 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
3399 const TargetFrameLowering *TFL = ST.getFrameLowering();
3400 unsigned Opc =
3401 TFL->getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp ?
3402 ISD::ADD : ISD::SUB;
3403
3404 SDValue ScaledSize = DAG.getNode(
3405 ISD::SHL, dl, VT, Size,
3406 DAG.getConstant(ST.getWavefrontSizeLog2(), dl, MVT::i32));
3407
3408 Align StackAlign = TFL->getStackAlign();
3409 Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value
3410 if (Alignment && *Alignment > StackAlign) {
3411 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
3412 DAG.getConstant(-(uint64_t)Alignment->value()
3413 << ST.getWavefrontSizeLog2(),
3414 dl, VT));
3415 }
3416
3417 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
3418 Tmp2 = DAG.getCALLSEQ_END(
3419 Chain, DAG.getIntPtrConstant(0, dl, true),
3420 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
3421
3422 return DAG.getMergeValues({Tmp1, Tmp2}, dl);
3423}
3424
3425SDValue SITargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3426 SelectionDAG &DAG) const {
3427 // We only handle constant sizes here to allow non-entry block, static sized
3428 // allocas. A truly dynamic value is more difficult to support because we
3429 // don't know if the size value is uniform or not. If the size isn't uniform,
3430 // we would need to do a wave reduction to get the maximum size to know how
3431 // much to increment the uniform stack pointer.
3432 SDValue Size = Op.getOperand(1);
3433 if (isa<ConstantSDNode>(Size))
3434 return lowerDYNAMIC_STACKALLOCImpl(Op, DAG); // Use "generic" expansion.
3435
3436 return AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(Op, DAG);
3437}
3438
3439Register SITargetLowering::getRegisterByName(const char* RegName, LLT VT,
3440 const MachineFunction &MF) const {
3441 Register Reg = StringSwitch<Register>(RegName)
3442 .Case("m0", AMDGPU::M0)
3443 .Case("exec", AMDGPU::EXEC)
3444 .Case("exec_lo", AMDGPU::EXEC_LO)
3445 .Case("exec_hi", AMDGPU::EXEC_HI)
3446 .Case("flat_scratch", AMDGPU::FLAT_SCR)
3447 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
3448 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
3449 .Default(Register());
3450
3451 if (Reg == AMDGPU::NoRegister) {
3452 report_fatal_error(Twine("invalid register name \""
3453 + StringRef(RegName) + "\"."));
3454
3455 }
3456
3457 if (!Subtarget->hasFlatScrRegister() &&
3458 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
3459 report_fatal_error(Twine("invalid register \""
3460 + StringRef(RegName) + "\" for subtarget."));
3461 }
3462
3463 switch (Reg) {
3464 case AMDGPU::M0:
3465 case AMDGPU::EXEC_LO:
3466 case AMDGPU::EXEC_HI:
3467 case AMDGPU::FLAT_SCR_LO:
3468 case AMDGPU::FLAT_SCR_HI:
3469 if (VT.getSizeInBits() == 32)
3470 return Reg;
3471 break;
3472 case AMDGPU::EXEC:
3473 case AMDGPU::FLAT_SCR:
3474 if (VT.getSizeInBits() == 64)
3475 return Reg;
3476 break;
3477 default:
3478 llvm_unreachable("missing register type checking")::llvm::llvm_unreachable_internal("missing register type checking"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 3478)
;
3479 }
3480
3481 report_fatal_error(Twine("invalid type for register \""
3482 + StringRef(RegName) + "\"."));
3483}
3484
3485// If kill is not the last instruction, split the block so kill is always a
3486// proper terminator.
3487MachineBasicBlock *
3488SITargetLowering::splitKillBlock(MachineInstr &MI,
3489 MachineBasicBlock *BB) const {
3490 MachineBasicBlock *SplitBB = BB->splitAt(MI, false /*UpdateLiveIns*/);
3491 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3492 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
3493 return SplitBB;
3494}
3495
3496// Split block \p MBB at \p MI, as to insert a loop. If \p InstInLoop is true,
3497// \p MI will be the only instruction in the loop body block. Otherwise, it will
3498// be the first instruction in the remainder block.
3499//
3500/// \returns { LoopBody, Remainder }
3501static std::pair<MachineBasicBlock *, MachineBasicBlock *>
3502splitBlockForLoop(MachineInstr &MI, MachineBasicBlock &MBB, bool InstInLoop) {
3503 MachineFunction *MF = MBB.getParent();
3504 MachineBasicBlock::iterator I(&MI);
3505
3506 // To insert the loop we need to split the block. Move everything after this
3507 // point to a new block, and insert a new empty block between the two.
3508 MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
3509 MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
3510 MachineFunction::iterator MBBI(MBB);
3511 ++MBBI;
3512
3513 MF->insert(MBBI, LoopBB);
3514 MF->insert(MBBI, RemainderBB);
3515
3516 LoopBB->addSuccessor(LoopBB);
3517 LoopBB->addSuccessor(RemainderBB);
3518
3519 // Move the rest of the block into a new block.
3520 RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
3521
3522 if (InstInLoop) {
3523 auto Next = std::next(I);
3524
3525 // Move instruction to loop body.
3526 LoopBB->splice(LoopBB->begin(), &MBB, I, Next);
3527
3528 // Move the rest of the block.
3529 RemainderBB->splice(RemainderBB->begin(), &MBB, Next, MBB.end());
3530 } else {
3531 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
3532 }
3533
3534 MBB.addSuccessor(LoopBB);
3535
3536 return std::make_pair(LoopBB, RemainderBB);
3537}
3538
3539/// Insert \p MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
3540void SITargetLowering::bundleInstWithWaitcnt(MachineInstr &MI) const {
3541 MachineBasicBlock *MBB = MI.getParent();
3542 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3543 auto I = MI.getIterator();
3544 auto E = std::next(I);
3545
3546 BuildMI(*MBB, E, MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
3547 .addImm(0);
3548
3549 MIBundleBuilder Bundler(*MBB, I, E);
3550 finalizeBundle(*MBB, Bundler.begin());
3551}
3552
3553MachineBasicBlock *
3554SITargetLowering::emitGWSMemViolTestLoop(MachineInstr &MI,
3555 MachineBasicBlock *BB) const {
3556 const DebugLoc &DL = MI.getDebugLoc();
3557
3558 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3559
3560 MachineBasicBlock *LoopBB;
3561 MachineBasicBlock *RemainderBB;
3562 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3563
3564 // Apparently kill flags are only valid if the def is in the same block?
3565 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0))
3566 Src->setIsKill(false);
3567
3568 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, *BB, true);
3569
3570 MachineBasicBlock::iterator I = LoopBB->end();
3571
3572 const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg(
3573 AMDGPU::Hwreg::ID_TRAPSTS, AMDGPU::Hwreg::OFFSET_MEM_VIOL, 1);
3574
3575 // Clear TRAP_STS.MEM_VIOL
3576 BuildMI(*LoopBB, LoopBB->begin(), DL, TII->get(AMDGPU::S_SETREG_IMM32_B32))
3577 .addImm(0)
3578 .addImm(EncodedReg);
3579
3580 bundleInstWithWaitcnt(MI);
3581
3582 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3583
3584 // Load and check TRAP_STS.MEM_VIOL
3585 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), Reg)
3586 .addImm(EncodedReg);
3587
3588 // FIXME: Do we need to use an isel pseudo that may clobber scc?
3589 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32))
3590 .addReg(Reg, RegState::Kill)
3591 .addImm(0);
3592 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3593 .addMBB(LoopBB);
3594
3595 return RemainderBB;
3596}
3597
3598// Do a v_movrels_b32 or v_movreld_b32 for each unique value of \p IdxReg in the
3599// wavefront. If the value is uniform and just happens to be in a VGPR, this
3600// will only do one iteration. In the worst case, this will loop 64 times.
3601//
3602// TODO: Just use v_readlane_b32 if we know the VGPR has a uniform value.
3603static MachineBasicBlock::iterator
3604emitLoadM0FromVGPRLoop(const SIInstrInfo *TII, MachineRegisterInfo &MRI,
3605 MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB,
3606 const DebugLoc &DL, const MachineOperand &Idx,
3607 unsigned InitReg, unsigned ResultReg, unsigned PhiReg,
3608 unsigned InitSaveExecReg, int Offset, bool UseGPRIdxMode,
3609 Register &SGPRIdxReg) {
3610
3611 MachineFunction *MF = OrigBB.getParent();
3612 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3613 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3614 MachineBasicBlock::iterator I = LoopBB.begin();
3615
3616 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3617 Register PhiExec = MRI.createVirtualRegister(BoolRC);
3618 Register NewExec = MRI.createVirtualRegister(BoolRC);
3619 Register CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3620 Register CondReg = MRI.createVirtualRegister(BoolRC);
3621
3622 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
3623 .addReg(InitReg)
3624 .addMBB(&OrigBB)
3625 .addReg(ResultReg)
3626 .addMBB(&LoopBB);
3627
3628 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
3629 .addReg(InitSaveExecReg)
3630 .addMBB(&OrigBB)
3631 .addReg(NewExec)
3632 .addMBB(&LoopBB);
3633
3634 // Read the next variant <- also loop target.
3635 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
3636 .addReg(Idx.getReg(), getUndefRegState(Idx.isUndef()));
3637
3638 // Compare the just read M0 value to all possible Idx values.
3639 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
3640 .addReg(CurrentIdxReg)
3641 .addReg(Idx.getReg(), 0, Idx.getSubReg());
3642
3643 // Update EXEC, save the original EXEC value to VCC.
3644 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
3645 : AMDGPU::S_AND_SAVEEXEC_B64),
3646 NewExec)
3647 .addReg(CondReg, RegState::Kill);
3648
3649 MRI.setSimpleHint(NewExec, CondReg);
3650
3651 if (UseGPRIdxMode) {
3652 if (Offset == 0) {
3653 SGPRIdxReg = CurrentIdxReg;
3654 } else {
3655 SGPRIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3656 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), SGPRIdxReg)
3657 .addReg(CurrentIdxReg, RegState::Kill)
3658 .addImm(Offset);
3659 }
3660 } else {
3661 // Move index from VCC into M0
3662 if (Offset == 0) {
3663 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3664 .addReg(CurrentIdxReg, RegState::Kill);
3665 } else {
3666 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3667 .addReg(CurrentIdxReg, RegState::Kill)
3668 .addImm(Offset);
3669 }
3670 }
3671
3672 // Update EXEC, switch all done bits to 0 and all todo bits to 1.
3673 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3674 MachineInstr *InsertPt =
3675 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
3676 : AMDGPU::S_XOR_B64_term), Exec)
3677 .addReg(Exec)
3678 .addReg(NewExec);
3679
3680 // XXX - s_xor_b64 sets scc to 1 if the result is nonzero, so can we use
3681 // s_cbranch_scc0?
3682
3683 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover.
3684 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
3685 .addMBB(&LoopBB);
3686
3687 return InsertPt->getIterator();
3688}
3689
3690// This has slightly sub-optimal regalloc when the source vector is killed by
3691// the read. The register allocator does not understand that the kill is
3692// per-workitem, so is kept alive for the whole loop so we end up not re-using a
3693// subregister from it, using 1 more VGPR than necessary. This was saved when
3694// this was expanded after register allocation.
3695static MachineBasicBlock::iterator
3696loadM0FromVGPR(const SIInstrInfo *TII, MachineBasicBlock &MBB, MachineInstr &MI,
3697 unsigned InitResultReg, unsigned PhiReg, int Offset,
3698 bool UseGPRIdxMode, Register &SGPRIdxReg) {
3699 MachineFunction *MF = MBB.getParent();
3700 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3701 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3702 MachineRegisterInfo &MRI = MF->getRegInfo();
3703 const DebugLoc &DL = MI.getDebugLoc();
3704 MachineBasicBlock::iterator I(&MI);
3705
3706 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3707 Register DstReg = MI.getOperand(0).getReg();
3708 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
3709 Register TmpExec = MRI.createVirtualRegister(BoolXExecRC);
3710 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3711 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
3712
3713 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
3714
3715 // Save the EXEC mask
3716 BuildMI(MBB, I, DL, TII->get(MovExecOpc), SaveExec)
3717 .addReg(Exec);
3718
3719 MachineBasicBlock *LoopBB;
3720 MachineBasicBlock *RemainderBB;
3721 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, MBB, false);
3722
3723 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3724
3725 auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
3726 InitResultReg, DstReg, PhiReg, TmpExec,
3727 Offset, UseGPRIdxMode, SGPRIdxReg);
3728
3729 MachineBasicBlock* LandingPad = MF->CreateMachineBasicBlock();
3730 MachineFunction::iterator MBBI(LoopBB);
3731 ++MBBI;
3732 MF->insert(MBBI, LandingPad);
3733 LoopBB->removeSuccessor(RemainderBB);
3734 LandingPad->addSuccessor(RemainderBB);
3735 LoopBB->addSuccessor(LandingPad);
3736 MachineBasicBlock::iterator First = LandingPad->begin();
3737 BuildMI(*LandingPad, First, DL, TII->get(MovExecOpc), Exec)
3738 .addReg(SaveExec);
3739
3740 return InsPt;
3741}
3742
3743// Returns subreg index, offset
3744static std::pair<unsigned, int>
3745computeIndirectRegAndOffset(const SIRegisterInfo &TRI,
3746 const TargetRegisterClass *SuperRC,
3747 unsigned VecReg,
3748 int Offset) {
3749 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
3750
3751 // Skip out of bounds offsets, or else we would end up using an undefined
3752 // register.
3753 if (Offset >= NumElts || Offset < 0)
3754 return std::make_pair(AMDGPU::sub0, Offset);
3755
3756 return std::make_pair(SIRegisterInfo::getSubRegFromChannel(Offset), 0);
3757}
3758
3759static void setM0ToIndexFromSGPR(const SIInstrInfo *TII,
3760 MachineRegisterInfo &MRI, MachineInstr &MI,
3761 int Offset) {
3762 MachineBasicBlock *MBB = MI.getParent();
3763 const DebugLoc &DL = MI.getDebugLoc();
3764 MachineBasicBlock::iterator I(&MI);
3765
3766 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3767
3768 assert(Idx->getReg() != AMDGPU::NoRegister)(static_cast <bool> (Idx->getReg() != AMDGPU::NoRegister
) ? void (0) : __assert_fail ("Idx->getReg() != AMDGPU::NoRegister"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 3768, __extension__
__PRETTY_FUNCTION__))
;
3769
3770 if (Offset == 0) {
3771 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0).add(*Idx);
3772 } else {
3773 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3774 .add(*Idx)
3775 .addImm(Offset);
3776 }
3777}
3778
3779static Register getIndirectSGPRIdx(const SIInstrInfo *TII,
3780 MachineRegisterInfo &MRI, MachineInstr &MI,
3781 int Offset) {
3782 MachineBasicBlock *MBB = MI.getParent();
3783 const DebugLoc &DL = MI.getDebugLoc();
3784 MachineBasicBlock::iterator I(&MI);
3785
3786 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3787
3788 if (Offset == 0)
3789 return Idx->getReg();
3790
3791 Register Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3792 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
3793 .add(*Idx)
3794 .addImm(Offset);
3795 return Tmp;
3796}
3797
3798static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
3799 MachineBasicBlock &MBB,
3800 const GCNSubtarget &ST) {
3801 const SIInstrInfo *TII = ST.getInstrInfo();
3802 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3803 MachineFunction *MF = MBB.getParent();
3804 MachineRegisterInfo &MRI = MF->getRegInfo();
3805
3806 Register Dst = MI.getOperand(0).getReg();
3807 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3808 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
3809 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3810
3811 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3812 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3813
3814 unsigned SubReg;
3815 std::tie(SubReg, Offset)
3816 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
3817
3818 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3819
3820 // Check for a SGPR index.
3821 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) {
3822 MachineBasicBlock::iterator I(&MI);
3823 const DebugLoc &DL = MI.getDebugLoc();
3824
3825 if (UseGPRIdxMode) {
3826 // TODO: Look at the uses to avoid the copy. This may require rescheduling
3827 // to avoid interfering with other uses, so probably requires a new
3828 // optimization pass.
3829 Register Idx = getIndirectSGPRIdx(TII, MRI, MI, Offset);
3830
3831 const MCInstrDesc &GPRIDXDesc =
3832 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true);
3833 BuildMI(MBB, I, DL, GPRIDXDesc, Dst)
3834 .addReg(SrcReg)
3835 .addReg(Idx)
3836 .addImm(SubReg);
3837 } else {
3838 setM0ToIndexFromSGPR(TII, MRI, MI, Offset);
3839
3840 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3841 .addReg(SrcReg, 0, SubReg)
3842 .addReg(SrcReg, RegState::Implicit);
3843 }
3844
3845 MI.eraseFromParent();
3846
3847 return &MBB;
3848 }
3849
3850 // Control flow needs to be inserted if indexing with a VGPR.
3851 const DebugLoc &DL = MI.getDebugLoc();
3852 MachineBasicBlock::iterator I(&MI);
3853
3854 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3855 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3856
3857 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3858
3859 Register SGPRIdxReg;
3860 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset,
3861 UseGPRIdxMode, SGPRIdxReg);
3862
3863 MachineBasicBlock *LoopBB = InsPt->getParent();
3864
3865 if (UseGPRIdxMode) {
3866 const MCInstrDesc &GPRIDXDesc =
3867 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), true);
3868
3869 BuildMI(*LoopBB, InsPt, DL, GPRIDXDesc, Dst)
3870 .addReg(SrcReg)
3871 .addReg(SGPRIdxReg)
3872 .addImm(SubReg);
3873 } else {
3874 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3875 .addReg(SrcReg, 0, SubReg)
3876 .addReg(SrcReg, RegState::Implicit);
3877 }
3878
3879 MI.eraseFromParent();
3880
3881 return LoopBB;
3882}
3883
3884static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
3885 MachineBasicBlock &MBB,
3886 const GCNSubtarget &ST) {
3887 const SIInstrInfo *TII = ST.getInstrInfo();
3888 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3889 MachineFunction *MF = MBB.getParent();
3890 MachineRegisterInfo &MRI = MF->getRegInfo();
3891
3892 Register Dst = MI.getOperand(0).getReg();
3893 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
3894 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3895 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
3896 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3897 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3898 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3899
3900 // This can be an immediate, but will be folded later.
3901 assert(Val->getReg())(static_cast <bool> (Val->getReg()) ? void (0) : __assert_fail
("Val->getReg()", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3901, __extension__ __PRETTY_FUNCTION__))
;
3902
3903 unsigned SubReg;
3904 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
3905 SrcVec->getReg(),
3906 Offset);
3907 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3908
3909 if (Idx->getReg() == AMDGPU::NoRegister) {
3910 MachineBasicBlock::iterator I(&MI);
3911 const DebugLoc &DL = MI.getDebugLoc();
3912
3913 assert(Offset == 0)(static_cast <bool> (Offset == 0) ? void (0) : __assert_fail
("Offset == 0", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp",
3913, __extension__ __PRETTY_FUNCTION__))
;
3914
3915 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
3916 .add(*SrcVec)
3917 .add(*Val)
3918 .addImm(SubReg);
3919
3920 MI.eraseFromParent();
3921 return &MBB;
3922 }
3923
3924 // Check for a SGPR index.
3925 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) {
3926 MachineBasicBlock::iterator I(&MI);
3927 const DebugLoc &DL = MI.getDebugLoc();
3928
3929 if (UseGPRIdxMode) {
3930 Register Idx = getIndirectSGPRIdx(TII, MRI, MI, Offset);
3931
3932 const MCInstrDesc &GPRIDXDesc =
3933 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false);
3934 BuildMI(MBB, I, DL, GPRIDXDesc, Dst)
3935 .addReg(SrcVec->getReg())
3936 .add(*Val)
3937 .addReg(Idx)
3938 .addImm(SubReg);
3939 } else {
3940 setM0ToIndexFromSGPR(TII, MRI, MI, Offset);
3941
3942 const MCInstrDesc &MovRelDesc = TII->getIndirectRegWriteMovRelPseudo(
3943 TRI.getRegSizeInBits(*VecRC), 32, false);
3944 BuildMI(MBB, I, DL, MovRelDesc, Dst)
3945 .addReg(SrcVec->getReg())
3946 .add(*Val)
3947 .addImm(SubReg);
3948 }
3949 MI.eraseFromParent();
3950 return &MBB;
3951 }
3952
3953 // Control flow needs to be inserted if indexing with a VGPR.
3954 if (Val->isReg())
3955 MRI.clearKillFlags(Val->getReg());
3956
3957 const DebugLoc &DL = MI.getDebugLoc();
3958
3959 Register PhiReg = MRI.createVirtualRegister(VecRC);
3960
3961 Register SGPRIdxReg;
3962 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset,
3963 UseGPRIdxMode, SGPRIdxReg);
3964 MachineBasicBlock *LoopBB = InsPt->getParent();
3965
3966 if (UseGPRIdxMode) {
3967 const MCInstrDesc &GPRIDXDesc =
3968 TII->getIndirectGPRIDXPseudo(TRI.getRegSizeInBits(*VecRC), false);
3969
3970 BuildMI(*LoopBB, InsPt, DL, GPRIDXDesc, Dst)
3971 .addReg(PhiReg)
3972 .add(*Val)
3973 .addReg(SGPRIdxReg)
3974 .addImm(AMDGPU::sub0);
3975 } else {
3976 const MCInstrDesc &MovRelDesc = TII->getIndirectRegWriteMovRelPseudo(
3977 TRI.getRegSizeInBits(*VecRC), 32, false);
3978 BuildMI(*LoopBB, InsPt, DL, MovRelDesc, Dst)
3979 .addReg(PhiReg)
3980 .add(*Val)
3981 .addImm(AMDGPU::sub0);
3982 }
3983
3984 MI.eraseFromParent();
3985 return LoopBB;
3986}
3987
3988MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
3989 MachineInstr &MI, MachineBasicBlock *BB) const {
3990
3991 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3992 MachineFunction *MF = BB->getParent();
3993 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
3994
3995 switch (MI.getOpcode()) {
3996 case AMDGPU::S_UADDO_PSEUDO:
3997 case AMDGPU::S_USUBO_PSEUDO: {
3998 const DebugLoc &DL = MI.getDebugLoc();
3999 MachineOperand &Dest0 = MI.getOperand(0);
4000 MachineOperand &Dest1 = MI.getOperand(1);
4001 MachineOperand &Src0 = MI.getOperand(2);
4002 MachineOperand &Src1 = MI.getOperand(3);
4003
4004 unsigned Opc = (MI.getOpcode() == AMDGPU::S_UADDO_PSEUDO)
4005 ? AMDGPU::S_ADD_I32
4006 : AMDGPU::S_SUB_I32;
4007 BuildMI(*BB, MI, DL, TII->get(Opc), Dest0.getReg()).add(Src0).add(Src1);
4008
4009 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CSELECT_B64), Dest1.getReg())
4010 .addImm(1)
4011 .addImm(0);
4012
4013 MI.eraseFromParent();
4014 return BB;
4015 }
4016 case AMDGPU::S_ADD_U64_PSEUDO:
4017 case AMDGPU::S_SUB_U64_PSEUDO: {
4018 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4019 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4020 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4021 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
4022 const DebugLoc &DL = MI.getDebugLoc();
4023
4024 MachineOperand &Dest = MI.getOperand(0);
4025 MachineOperand &Src0 = MI.getOperand(1);
4026 MachineOperand &Src1 = MI.getOperand(2);
4027
4028 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4029 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4030
4031 MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(
4032 MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
4033 MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(
4034 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
4035
4036 MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(
4037 MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass);
4038 MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(
4039 MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass);
4040
4041 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
4042
4043 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
4044 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
4045 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0).add(Src0Sub0).add(Src1Sub0);
4046 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1).add(Src0Sub1).add(Src1Sub1);
4047 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
4048 .addReg(DestSub0)
4049 .addImm(AMDGPU::sub0)
4050 .addReg(DestSub1)
4051 .addImm(AMDGPU::sub1);
4052 MI.eraseFromParent();
4053 return BB;
4054 }
4055 case AMDGPU::V_ADD_U64_PSEUDO:
4056 case AMDGPU::V_SUB_U64_PSEUDO: {
4057 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4058 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4059 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4060 const DebugLoc &DL = MI.getDebugLoc();
4061
4062 bool IsAdd = (MI.getOpcode() == AMDGPU::V_ADD_U64_PSEUDO);
4063
4064 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4065
4066 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4067 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4068
4069 Register CarryReg = MRI.createVirtualRegister(CarryRC);
4070 Register DeadCarryReg = MRI.createVirtualRegister(CarryRC);
4071
4072 MachineOperand &Dest = MI.getOperand(0);
4073 MachineOperand &Src0 = MI.getOperand(1);
4074 MachineOperand &Src1 = MI.getOperand(2);
4075
4076 const TargetRegisterClass *Src0RC = Src0.isReg()
4077 ? MRI.getRegClass(Src0.getReg())
4078 : &AMDGPU::VReg_64RegClass;
4079 const TargetRegisterClass *Src1RC = Src1.isReg()
4080 ? MRI.getRegClass(Src1.getReg())
4081 : &AMDGPU::VReg_64RegClass;
4082
4083 const TargetRegisterClass *Src0SubRC =
4084 TRI->getSubRegClass(Src0RC, AMDGPU::sub0);
4085 const TargetRegisterClass *Src1SubRC =
4086 TRI->getSubRegClass(Src1RC, AMDGPU::sub1);
4087
4088 MachineOperand SrcReg0Sub0 = TII->buildExtractSubRegOrImm(
4089 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC);
4090 MachineOperand SrcReg1Sub0 = TII->buildExtractSubRegOrImm(
4091 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC);
4092
4093 MachineOperand SrcReg0Sub1 = TII->buildExtractSubRegOrImm(
4094 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC);
4095 MachineOperand SrcReg1Sub1 = TII->buildExtractSubRegOrImm(
4096 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC);
4097
4098 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_CO_U32_e64 : AMDGPU::V_SUB_CO_U32_e64;
4099 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
4100 .addReg(CarryReg, RegState::Define)
4101 .add(SrcReg0Sub0)
4102 .add(SrcReg1Sub0)
4103 .addImm(0); // clamp bit
4104
4105 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
4106 MachineInstr *HiHalf =
4107 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
4108 .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
4109 .add(SrcReg0Sub1)
4110 .add(SrcReg1Sub1)
4111 .addReg(CarryReg, RegState::Kill)
4112 .addImm(0); // clamp bit
4113
4114 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
4115 .addReg(DestSub0)
4116 .addImm(AMDGPU::sub0)
4117 .addReg(DestSub1)
4118 .addImm(AMDGPU::sub1);
4119 TII->legalizeOperands(*LoHalf);
4120 TII->legalizeOperands(*HiHalf);
4121 MI.eraseFromParent();
4122 return BB;
4123 }
4124 case AMDGPU::S_ADD_CO_PSEUDO:
4125 case AMDGPU::S_SUB_CO_PSEUDO: {
4126 // This pseudo has a chance to be selected
4127 // only from uniform add/subcarry node. All the VGPR operands
4128 // therefore assumed to be splat vectors.
4129 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4130 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4131 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4132 MachineBasicBlock::iterator MII = MI;
4133 const DebugLoc &DL = MI.getDebugLoc();
4134 MachineOperand &Dest = MI.getOperand(0);
4135 MachineOperand &CarryDest = MI.getOperand(1);
4136 MachineOperand &Src0 = MI.getOperand(2);
4137 MachineOperand &Src1 = MI.getOperand(3);
4138 MachineOperand &Src2 = MI.getOperand(4);
4139 unsigned Opc = (MI.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO)
4140 ? AMDGPU::S_ADDC_U32
4141 : AMDGPU::S_SUBB_U32;
4142 if (Src0.isReg() && TRI->isVectorRegister(MRI, Src0.getReg())) {
4143 Register RegOp0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4144 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp0)
4145 .addReg(Src0.getReg());
4146 Src0.setReg(RegOp0);
4147 }
4148 if (Src1.isReg() && TRI->isVectorRegister(MRI, Src1.getReg())) {
4149 Register RegOp1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4150 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp1)
4151 .addReg(Src1.getReg());
4152 Src1.setReg(RegOp1);
4153 }
4154 Register RegOp2 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4155 if (TRI->isVectorRegister(MRI, Src2.getReg())) {
4156 BuildMI(*BB, MII, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), RegOp2)
4157 .addReg(Src2.getReg());
4158 Src2.setReg(RegOp2);
4159 }
4160
4161 const TargetRegisterClass *Src2RC = MRI.getRegClass(Src2.getReg());
4162 unsigned WaveSize = TRI->getRegSizeInBits(*Src2RC);
4163 assert(WaveSize == 64 || WaveSize == 32)(static_cast <bool> (WaveSize == 64 || WaveSize == 32) ?
void (0) : __assert_fail ("WaveSize == 64 || WaveSize == 32"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4163, __extension__
__PRETTY_FUNCTION__))
;
4164
4165 if (WaveSize == 64) {
4166 if (ST.hasScalarCompareEq64()) {
4167 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMP_LG_U64))
4168 .addReg(Src2.getReg())
4169 .addImm(0);
4170 } else {
4171 const TargetRegisterClass *SubRC =
4172 TRI->getSubRegClass(Src2RC, AMDGPU::sub0);
4173 MachineOperand Src2Sub0 = TII->buildExtractSubRegOrImm(
4174 MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC);
4175 MachineOperand Src2Sub1 = TII->buildExtractSubRegOrImm(
4176 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC);
4177 Register Src2_32 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
4178
4179 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_OR_B32), Src2_32)
4180 .add(Src2Sub0)
4181 .add(Src2Sub1);
4182
4183 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMP_LG_U32))
4184 .addReg(Src2_32, RegState::Kill)
4185 .addImm(0);
4186 }
4187 } else {
4188 BuildMI(*BB, MII, DL, TII->get(AMDGPU::S_CMPK_LG_U32))
4189 .addReg(Src2.getReg())
4190 .addImm(0);
4191 }
4192
4193 BuildMI(*BB, MII, DL, TII->get(Opc), Dest.getReg()).add(Src0).add(Src1);
4194
4195 unsigned SelOpc =
4196 (WaveSize == 64) ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32;
4197
4198 BuildMI(*BB, MII, DL, TII->get(SelOpc), CarryDest.getReg())
4199 .addImm(-1)
4200 .addImm(0);
4201
4202 MI.eraseFromParent();
4203 return BB;
4204 }
4205 case AMDGPU::SI_INIT_M0: {
4206 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
4207 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
4208 .add(MI.getOperand(0));
4209 MI.eraseFromParent();
4210 return BB;
4211 }
4212 case AMDGPU::GET_GROUPSTATICSIZE: {
4213 assert(getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA ||(static_cast <bool> (getTargetMachine().getTargetTriple
().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple
().getOS() == Triple::AMDPAL) ? void (0) : __assert_fail ("getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4214, __extension__
__PRETTY_FUNCTION__))
4214 getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL)(static_cast <bool> (getTargetMachine().getTargetTriple
().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple
().getOS() == Triple::AMDPAL) ? void (0) : __assert_fail ("getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4214, __extension__
__PRETTY_FUNCTION__))
;
4215 DebugLoc DL = MI.getDebugLoc();
4216 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
4217 .add(MI.getOperand(0))
4218 .addImm(MFI->getLDSSize());
4219 MI.eraseFromParent();
4220 return BB;
4221 }
4222 case AMDGPU::SI_INDIRECT_SRC_V1:
4223 case AMDGPU::SI_INDIRECT_SRC_V2:
4224 case AMDGPU::SI_INDIRECT_SRC_V4:
4225 case AMDGPU::SI_INDIRECT_SRC_V8:
4226 case AMDGPU::SI_INDIRECT_SRC_V16:
4227 case AMDGPU::SI_INDIRECT_SRC_V32:
4228 return emitIndirectSrc(MI, *BB, *getSubtarget());
4229 case AMDGPU::SI_INDIRECT_DST_V1:
4230 case AMDGPU::SI_INDIRECT_DST_V2:
4231 case AMDGPU::SI_INDIRECT_DST_V4:
4232 case AMDGPU::SI_INDIRECT_DST_V8:
4233 case AMDGPU::SI_INDIRECT_DST_V16:
4234 case AMDGPU::SI_INDIRECT_DST_V32:
4235 return emitIndirectDst(MI, *BB, *getSubtarget());
4236 case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
4237 case AMDGPU::SI_KILL_I1_PSEUDO:
4238 return splitKillBlock(MI, BB);
4239 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
4240 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4241 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4242 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4243
4244 Register Dst = MI.getOperand(0).getReg();
4245 Register Src0 = MI.getOperand(1).getReg();
4246 Register Src1 = MI.getOperand(2).getReg();
4247 const DebugLoc &DL = MI.getDebugLoc();
4248 Register SrcCond = MI.getOperand(3).getReg();
4249
4250 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4251 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4252 const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4253 Register SrcCondCopy = MRI.createVirtualRegister(CondRC);
4254
4255 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
4256 .addReg(SrcCond);
4257 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
4258 .addImm(0)
4259 .addReg(Src0, 0, AMDGPU::sub0)
4260 .addImm(0)
4261 .addReg(Src1, 0, AMDGPU::sub0)
4262 .addReg(SrcCondCopy);
4263 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
4264 .addImm(0)
4265 .addReg(Src0, 0, AMDGPU::sub1)
4266 .addImm(0)
4267 .addReg(Src1, 0, AMDGPU::sub1)
4268 .addReg(SrcCondCopy);
4269
4270 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
4271 .addReg(DstLo)
4272 .addImm(AMDGPU::sub0)
4273 .addReg(DstHi)
4274 .addImm(AMDGPU::sub1);
4275 MI.eraseFromParent();
4276 return BB;
4277 }
4278 case AMDGPU::SI_BR_UNDEF: {
4279 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4280 const DebugLoc &DL = MI.getDebugLoc();
4281 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
4282 .add(MI.getOperand(0));
4283 Br->getOperand(1).setIsUndef(true); // read undef SCC
4284 MI.eraseFromParent();
4285 return BB;
4286 }
4287 case AMDGPU::ADJCALLSTACKUP:
4288 case AMDGPU::ADJCALLSTACKDOWN: {
4289 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
4290 MachineInstrBuilder MIB(*MF, &MI);
4291 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
4292 .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit);
4293 return BB;
4294 }
4295 case AMDGPU::SI_CALL_ISEL: {
4296 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
4297 const DebugLoc &DL = MI.getDebugLoc();
4298
4299 unsigned ReturnAddrReg = TII->getRegisterInfo().getReturnAddressReg(*MF);
4300
4301 MachineInstrBuilder MIB;
4302 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg);
4303
4304 for (const MachineOperand &MO : MI.operands())
4305 MIB.add(MO);
4306
4307 MIB.cloneMemRefs(MI);
4308 MI.eraseFromParent();
4309 return BB;
4310 }
4311 case AMDGPU::V_ADD_CO_U32_e32:
4312 case AMDGPU::V_SUB_CO_U32_e32:
4313 case AMDGPU::V_SUBREV_CO_U32_e32: {
4314 // TODO: Define distinct V_*_I32_Pseudo instructions instead.
4315 const DebugLoc &DL = MI.getDebugLoc();
4316 unsigned Opc = MI.getOpcode();
4317
4318 bool NeedClampOperand = false;
4319 if (TII->pseudoToMCOpcode(Opc) == -1) {
4320 Opc = AMDGPU::getVOPe64(Opc);
4321 NeedClampOperand = true;
4322 }
4323
4324 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
4325 if (TII->isVOP3(*I)) {
4326 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
4327 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4328 I.addReg(TRI->getVCC(), RegState::Define);
4329 }
4330 I.add(MI.getOperand(1))
4331 .add(MI.getOperand(2));
4332 if (NeedClampOperand)
4333 I.addImm(0); // clamp bit for e64 encoding
4334
4335 TII->legalizeOperands(*I);
4336
4337 MI.eraseFromParent();
4338 return BB;
4339 }
4340 case AMDGPU::V_ADDC_U32_e32:
4341 case AMDGPU::V_SUBB_U32_e32:
4342 case AMDGPU::V_SUBBREV_U32_e32:
4343 // These instructions have an implicit use of vcc which counts towards the
4344 // constant bus limit.
4345 TII->legalizeOperands(MI);
4346 return BB;
4347 case AMDGPU::DS_GWS_INIT:
4348 case AMDGPU::DS_GWS_SEMA_BR:
4349 case AMDGPU::DS_GWS_BARRIER:
4350 if (Subtarget->needsAlignedVGPRs()) {
4351 // Add implicit aligned super-reg to force alignment on the data operand.
4352 const DebugLoc &DL = MI.getDebugLoc();
4353 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4354 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
4355 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::data0);
4356 Register DataReg = Op->getReg();
4357 bool IsAGPR = TRI->isAGPR(MRI, DataReg);
4358 Register Undef = MRI.createVirtualRegister(
4359 IsAGPR ? &AMDGPU::AGPR_32RegClass : &AMDGPU::VGPR_32RegClass);
4360 BuildMI(*BB, MI, DL, TII->get(AMDGPU::IMPLICIT_DEF), Undef);
4361 Register NewVR =
4362 MRI.createVirtualRegister(IsAGPR ? &AMDGPU::AReg_64_Align2RegClass
4363 : &AMDGPU::VReg_64_Align2RegClass);
4364 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), NewVR)
4365 .addReg(DataReg, 0, Op->getSubReg())
4366 .addImm(AMDGPU::sub0)
4367 .addReg(Undef)
4368 .addImm(AMDGPU::sub1);
4369 Op->setReg(NewVR);
4370 Op->setSubReg(AMDGPU::sub0);
4371 MI.addOperand(MachineOperand::CreateReg(NewVR, false, true));
4372 }
4373 LLVM_FALLTHROUGH[[gnu::fallthrough]];
4374 case AMDGPU::DS_GWS_SEMA_V:
4375 case AMDGPU::DS_GWS_SEMA_P:
4376 case AMDGPU::DS_GWS_SEMA_RELEASE_ALL:
4377 // A s_waitcnt 0 is required to be the instruction immediately following.
4378 if (getSubtarget()->hasGWSAutoReplay()) {
4379 bundleInstWithWaitcnt(MI);
4380 return BB;
4381 }
4382
4383 return emitGWSMemViolTestLoop(MI, BB);
4384 case AMDGPU::S_SETREG_B32: {
4385 // Try to optimize cases that only set the denormal mode or rounding mode.
4386 //
4387 // If the s_setreg_b32 fully sets all of the bits in the rounding mode or
4388 // denormal mode to a constant, we can use s_round_mode or s_denorm_mode
4389 // instead.
4390 //
4391 // FIXME: This could be predicates on the immediate, but tablegen doesn't
4392 // allow you to have a no side effect instruction in the output of a
4393 // sideeffecting pattern.
4394 unsigned ID, Offset, Width;
4395 AMDGPU::Hwreg::decodeHwreg(MI.getOperand(1).getImm(), ID, Offset, Width);
4396 if (ID != AMDGPU::Hwreg::ID_MODE)
4397 return BB;
4398
4399 const unsigned WidthMask = maskTrailingOnes<unsigned>(Width);
4400 const unsigned SetMask = WidthMask << Offset;
4401
4402 if (getSubtarget()->hasDenormModeInst()) {
4403 unsigned SetDenormOp = 0;
4404 unsigned SetRoundOp = 0;
4405
4406 // The dedicated instructions can only set the whole denorm or round mode
4407 // at once, not a subset of bits in either.
4408 if (SetMask ==
4409 (AMDGPU::Hwreg::FP_ROUND_MASK | AMDGPU::Hwreg::FP_DENORM_MASK)) {
4410 // If this fully sets both the round and denorm mode, emit the two
4411 // dedicated instructions for these.
4412 SetRoundOp = AMDGPU::S_ROUND_MODE;
4413 SetDenormOp = AMDGPU::S_DENORM_MODE;
4414 } else if (SetMask == AMDGPU::Hwreg::FP_ROUND_MASK) {
4415 SetRoundOp = AMDGPU::S_ROUND_MODE;
4416 } else if (SetMask == AMDGPU::Hwreg::FP_DENORM_MASK) {
4417 SetDenormOp = AMDGPU::S_DENORM_MODE;
4418 }
4419
4420 if (SetRoundOp || SetDenormOp) {
4421 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4422 MachineInstr *Def = MRI.getVRegDef(MI.getOperand(0).getReg());
4423 if (Def && Def->isMoveImmediate() && Def->getOperand(1).isImm()) {
4424 unsigned ImmVal = Def->getOperand(1).getImm();
4425 if (SetRoundOp) {
4426 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SetRoundOp))
4427 .addImm(ImmVal & 0xf);
4428
4429 // If we also have the denorm mode, get just the denorm mode bits.
4430 ImmVal >>= 4;
4431 }
4432
4433 if (SetDenormOp) {
4434 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SetDenormOp))
4435 .addImm(ImmVal & 0xf);
4436 }
4437
4438 MI.eraseFromParent();
4439 return BB;
4440 }
4441 }
4442 }
4443
4444 // If only FP bits are touched, used the no side effects pseudo.
4445 if ((SetMask & (AMDGPU::Hwreg::FP_ROUND_MASK |
4446 AMDGPU::Hwreg::FP_DENORM_MASK)) == SetMask)
4447 MI.setDesc(TII->get(AMDGPU::S_SETREG_B32_mode));
4448
4449 return BB;
4450 }
4451 default:
4452 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
4453 }
4454}
4455
4456bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const {
4457 return isTypeLegal(VT.getScalarType());
4458}
4459
4460bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
4461 // This currently forces unfolding various combinations of fsub into fma with
4462 // free fneg'd operands. As long as we have fast FMA (controlled by
4463 // isFMAFasterThanFMulAndFAdd), we should perform these.
4464
4465 // When fma is quarter rate, for f64 where add / sub are at best half rate,
4466 // most of these combines appear to be cycle neutral but save on instruction
4467 // count / code size.
4468 return true;
4469}
4470
4471bool SITargetLowering::enableAggressiveFMAFusion(LLT Ty) const { return true; }
4472
4473EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
4474 EVT VT) const {
4475 if (!VT.isVector()) {
4476 return MVT::i1;
4477 }
4478 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
4479}
4480
4481MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT VT) const {
4482 // TODO: Should i16 be used always if legal? For now it would force VALU
4483 // shifts.
4484 return (VT == MVT::i16) ? MVT::i16 : MVT::i32;
4485}
4486
4487LLT SITargetLowering::getPreferredShiftAmountTy(LLT Ty) const {
4488 return (Ty.getScalarSizeInBits() <= 16 && Subtarget->has16BitInsts())
4489 ? Ty.changeElementSize(16)
4490 : Ty.changeElementSize(32);
4491}
4492
4493// Answering this is somewhat tricky and depends on the specific device which
4494// have different rates for fma or all f64 operations.
4495//
4496// v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
4497// regardless of which device (although the number of cycles differs between
4498// devices), so it is always profitable for f64.
4499//
4500// v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
4501// only on full rate devices. Normally, we should prefer selecting v_mad_f32
4502// which we can always do even without fused FP ops since it returns the same
4503// result as the separate operations and since it is always full
4504// rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
4505// however does not support denormals, so we do report fma as faster if we have
4506// a fast fma device and require denormals.
4507//
4508bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
4509 EVT VT) const {
4510 VT = VT.getScalarType();
4511
4512 switch (VT.getSimpleVT().SimpleTy) {
4513 case MVT::f32: {
4514 // If mad is not available this depends only on if f32 fma is full rate.
4515 if (!Subtarget->hasMadMacF32Insts())
4516 return Subtarget->hasFastFMAF32();
4517
4518 // Otherwise f32 mad is always full rate and returns the same result as
4519 // the separate operations so should be preferred over fma.
4520 // However does not support denomals.
4521 if (hasFP32Denormals(MF))
4522 return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts();
4523
4524 // If the subtarget has v_fmac_f32, that's just as good as v_mac_f32.
4525 return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts();
4526 }
4527 case MVT::f64:
4528 return true;
4529 case MVT::f16:
4530 return Subtarget->has16BitInsts() && hasFP64FP16Denormals(MF);
4531 default:
4532 break;
4533 }
4534
4535 return false;
4536}
4537
4538bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
4539 LLT Ty) const {
4540 switch (Ty.getScalarSizeInBits()) {
4541 case 16:
4542 return isFMAFasterThanFMulAndFAdd(MF, MVT::f16);
4543 case 32:
4544 return isFMAFasterThanFMulAndFAdd(MF, MVT::f32);
4545 case 64:
4546 return isFMAFasterThanFMulAndFAdd(MF, MVT::f64);
4547 default:
4548 break;
4549 }
4550
4551 return false;
4552}
4553
4554bool SITargetLowering::isFMADLegal(const MachineInstr &MI, LLT Ty) const {
4555 if (!Ty.isScalar())
4556 return false;
4557
4558 if (Ty.getScalarSizeInBits() == 16)
4559 return Subtarget->hasMadF16() && !hasFP64FP16Denormals(*MI.getMF());
4560 if (Ty.getScalarSizeInBits() == 32)
4561 return Subtarget->hasMadMacF32Insts() && !hasFP32Denormals(*MI.getMF());
4562
4563 return false;
4564}
4565
4566bool SITargetLowering::isFMADLegal(const SelectionDAG &DAG,
4567 const SDNode *N) const {
4568 // TODO: Check future ftz flag
4569 // v_mad_f32/v_mac_f32 do not support denormals.
4570 EVT VT = N->getValueType(0);
4571 if (VT == MVT::f32)
4572 return Subtarget->hasMadMacF32Insts() &&
4573 !hasFP32Denormals(DAG.getMachineFunction());
4574 if (VT == MVT::f16) {
4575 return Subtarget->hasMadF16() &&
4576 !hasFP64FP16Denormals(DAG.getMachineFunction());
4577 }
4578
4579 return false;
4580}
4581
4582//===----------------------------------------------------------------------===//
4583// Custom DAG Lowering Operations
4584//===----------------------------------------------------------------------===//
4585
4586// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
4587// wider vector type is legal.
4588SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
4589 SelectionDAG &DAG) const {
4590 unsigned Opc = Op.getOpcode();
4591 EVT VT = Op.getValueType();
4592 assert(VT == MVT::v4f16 || VT == MVT::v4i16)(static_cast <bool> (VT == MVT::v4f16 || VT == MVT::v4i16
) ? void (0) : __assert_fail ("VT == MVT::v4f16 || VT == MVT::v4i16"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4592, __extension__
__PRETTY_FUNCTION__))
;
4593
4594 SDValue Lo, Hi;
4595 std::tie(Lo, Hi) = DAG.SplitVectorOperand(Op.getNode(), 0);
4596
4597 SDLoc SL(Op);
4598 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo,
4599 Op->getFlags());
4600 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi,
4601 Op->getFlags());
4602
4603 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4604}
4605
4606// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
4607// wider vector type is legal.
4608SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
4609 SelectionDAG &DAG) const {
4610 unsigned Opc = Op.getOpcode();
4611 EVT VT = Op.getValueType();
4612 assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 ||(static_cast <bool> (VT == MVT::v4i16 || VT == MVT::v4f16
|| VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32
|| VT == MVT::v32f32) ? void (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4613, __extension__
__PRETTY_FUNCTION__))
4613 VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32)(static_cast <bool> (VT == MVT::v4i16 || VT == MVT::v4f16
|| VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32
|| VT == MVT::v32f32) ? void (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4613, __extension__
__PRETTY_FUNCTION__))
;
4614
4615 SDValue Lo0, Hi0;
4616 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
4617 SDValue Lo1, Hi1;
4618 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4619
4620 SDLoc SL(Op);
4621
4622 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1,
4623 Op->getFlags());
4624 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1,
4625 Op->getFlags());
4626
4627 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4628}
4629
4630SDValue SITargetLowering::splitTernaryVectorOp(SDValue Op,
4631 SelectionDAG &DAG) const {
4632 unsigned Opc = Op.getOpcode();
4633 EVT VT = Op.getValueType();
4634 assert(VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 ||(static_cast <bool> (VT == MVT::v4i16 || VT == MVT::v4f16
|| VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32
|| VT == MVT::v32f32) ? void (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4635, __extension__
__PRETTY_FUNCTION__))
4635 VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32)(static_cast <bool> (VT == MVT::v4i16 || VT == MVT::v4f16
|| VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32
|| VT == MVT::v32f32) ? void (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4f32 || VT == MVT::v8f32 || VT == MVT::v16f32 || VT == MVT::v32f32"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4635, __extension__
__PRETTY_FUNCTION__))
;
4636
4637 SDValue Lo0, Hi0;
4638 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
4639 SDValue Lo1, Hi1;
4640 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
4641 SDValue Lo2, Hi2;
4642 std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2);
4643
4644 SDLoc SL(Op);
4645
4646 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2,
4647 Op->getFlags());
4648 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2,
4649 Op->getFlags());
4650
4651 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
4652}
4653
4654
4655SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4656 switch (Op.getOpcode()) {
4657 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
4658 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4659 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4660 case ISD::LOAD: {
4661 SDValue Result = LowerLOAD(Op, DAG);
4662 assert((!Result.getNode() ||(static_cast <bool> ((!Result.getNode() || Result.getNode
()->getNumValues() == 2) && "Load should return a value and a chain"
) ? void (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4664, __extension__
__PRETTY_FUNCTION__))
4663 Result.getNode()->getNumValues() == 2) &&(static_cast <bool> ((!Result.getNode() || Result.getNode
()->getNumValues() == 2) && "Load should return a value and a chain"
) ? void (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4664, __extension__
__PRETTY_FUNCTION__))
4664 "Load should return a value and a chain")(static_cast <bool> ((!Result.getNode() || Result.getNode
()->getNumValues() == 2) && "Load should return a value and a chain"
) ? void (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 4664, __extension__
__PRETTY_FUNCTION__))
;
4665 return Result;
4666 }
4667
4668 case ISD::FSIN:
4669 case ISD::FCOS:
4670 return LowerTrig(Op, DAG);
4671 case ISD::SELECT: return LowerSELECT(Op, DAG);
4672 case ISD::FDIV: return LowerFDIV(Op, DAG);
4673 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
4674 case ISD::STORE: return LowerSTORE(Op, DAG);
4675 case ISD::GlobalAddress: {
4676 MachineFunction &MF = DAG.getMachineFunction();
4677 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
4678 return LowerGlobalAddress(MFI, Op, DAG);
4679 }
4680 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4681 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
4682 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
4683 case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
4684 case ISD::INSERT_SUBVECTOR:
4685 return lowerINSERT_SUBVECTOR(Op, DAG);
4686 case ISD::INSERT_VECTOR_ELT:
4687 return lowerINSERT_VECTOR_ELT(Op, DAG);
4688 case ISD::EXTRACT_VECTOR_ELT:
4689 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4690 case ISD::VECTOR_SHUFFLE:
4691 return lowerVECTOR_SHUFFLE(Op, DAG);
4692 case ISD::BUILD_VECTOR:
4693 return lowerBUILD_VECTOR(Op, DAG);
4694 case ISD::FP_ROUND:
4695 return lowerFP_ROUND(Op, DAG);
4696 case ISD::TRAP:
4697 return lowerTRAP(Op, DAG);
4698 case ISD::DEBUGTRAP:
4699 return lowerDEBUGTRAP(Op, DAG);
4700 case ISD::FABS:
4701 case ISD::FNEG:
4702 case ISD::FCANONICALIZE:
4703 case ISD::BSWAP:
4704 return splitUnaryVectorOp(Op, DAG);
4705 case ISD::FMINNUM:
4706 case ISD::FMAXNUM:
4707 return lowerFMINNUM_FMAXNUM(Op, DAG);
4708 case ISD::FMA:
4709 return splitTernaryVectorOp(Op, DAG);
4710 case ISD::FP_TO_SINT:
4711 case ISD::FP_TO_UINT:
4712 return LowerFP_TO_INT(Op, DAG);
4713 case ISD::SHL:
4714 case ISD::SRA:
4715 case ISD::SRL:
4716 case ISD::ADD:
4717 case ISD::SUB:
4718 case ISD::MUL:
4719 case ISD::SMIN:
4720 case ISD::SMAX:
4721 case ISD::UMIN:
4722 case ISD::UMAX:
4723 case ISD::FADD:
4724 case ISD::FMUL:
4725 case ISD::FMINNUM_IEEE:
4726 case ISD::FMAXNUM_IEEE:
4727 case ISD::UADDSAT:
4728 case ISD::USUBSAT:
4729 case ISD::SADDSAT:
4730 case ISD::SSUBSAT:
4731 return splitBinaryVectorOp(Op, DAG);
4732 case ISD::SMULO:
4733 case ISD::UMULO:
4734 return lowerXMULO(Op, DAG);
4735 case ISD::SMUL_LOHI:
4736 case ISD::UMUL_LOHI:
4737 return lowerXMUL_LOHI(Op, DAG);
4738 case ISD::DYNAMIC_STACKALLOC:
4739 return LowerDYNAMIC_STACKALLOC(Op, DAG);
4740 }
4741 return SDValue();
4742}
4743
4744// Used for D16: Casts the result of an instruction into the right vector,
4745// packs values if loads return unpacked values.
4746static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT,
4747 const SDLoc &DL,
4748 SelectionDAG &DAG, bool Unpacked) {
4749 if (!LoadVT.isVector())
4750 return Result;
4751
4752 // Cast back to the original packed type or to a larger type that is a
4753 // multiple of 32 bit for D16. Widening the return type is a required for
4754 // legalization.
4755 EVT FittingLoadVT = LoadVT;
4756 if ((LoadVT.getVectorNumElements() % 2) == 1) {
4757 FittingLoadVT =
4758 EVT::getVectorVT(*DAG.getContext(), LoadVT.getVectorElementType(),
4759 LoadVT.getVectorNumElements() + 1);
4760 }
4761
4762 if (Unpacked) { // From v2i32/v4i32 back to v2f16/v4f16.
4763 // Truncate to v2i16/v4i16.
4764 EVT IntLoadVT = FittingLoadVT.changeTypeToInteger();
4765
4766 // Workaround legalizer not scalarizing truncate after vector op
4767 // legalization but not creating intermediate vector trunc.
4768 SmallVector<SDValue, 4> Elts;
4769 DAG.ExtractVectorElements(Result, Elts);
4770 for (SDValue &Elt : Elts)
4771 Elt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Elt);
4772
4773 // Pad illegal v1i16/v3fi6 to v4i16
4774 if ((LoadVT.getVectorNumElements() % 2) == 1)
4775 Elts.push_back(DAG.getUNDEF(MVT::i16));
4776
4777 Result = DAG.getBuildVector(IntLoadVT, DL, Elts);
4778
4779 // Bitcast to original type (v2f16/v4f16).
4780 return DAG.getNode(ISD::BITCAST, DL, FittingLoadVT, Result);
4781 }
4782
4783 // Cast back to the original packed type.
4784 return DAG.getNode(ISD::BITCAST, DL, FittingLoadVT, Result);
4785}
4786
4787SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
4788 MemSDNode *M,
4789 SelectionDAG &DAG,
4790 ArrayRef<SDValue> Ops,
4791 bool IsIntrinsic) const {
4792 SDLoc DL(M);
4793
4794 bool Unpacked = Subtarget->hasUnpackedD16VMem();
4795 EVT LoadVT = M->getValueType(0);
4796
4797 EVT EquivLoadVT = LoadVT;
4798 if (LoadVT.isVector()) {
4799 if (Unpacked) {
4800 EquivLoadVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
4801 LoadVT.getVectorNumElements());
4802 } else if ((LoadVT.getVectorNumElements() % 2) == 1) {
4803 // Widen v3f16 to legal type
4804 EquivLoadVT =
4805 EVT::getVectorVT(*DAG.getContext(), LoadVT.getVectorElementType(),
4806 LoadVT.getVectorNumElements() + 1);
4807 }
4808 }
4809
4810 // Change from v4f16/v2f16 to EquivLoadVT.
4811 SDVTList VTList = DAG.getVTList(EquivLoadVT, MVT::Other);
4812
4813 SDValue Load
4814 = DAG.getMemIntrinsicNode(
4815 IsIntrinsic ? (unsigned)ISD::INTRINSIC_W_CHAIN : Opcode, DL,
4816 VTList, Ops, M->getMemoryVT(),
4817 M->getMemOperand());
4818
4819 SDValue Adjusted = adjustLoadValueTypeImpl(Load, LoadVT, DL, DAG, Unpacked);
4820
4821 return DAG.getMergeValues({ Adjusted, Load.getValue(1) }, DL);
4822}
4823
4824SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
4825 SelectionDAG &DAG,
4826 ArrayRef<SDValue> Ops) const {
4827 SDLoc DL(M);
4828 EVT LoadVT = M->getValueType(0);
4829 EVT EltType = LoadVT.getScalarType();
4830 EVT IntVT = LoadVT.changeTypeToInteger();
4831
4832 bool IsD16 = IsFormat && (EltType.getSizeInBits() == 16);
4833
4834 unsigned Opc =
4835 IsFormat ? AMDGPUISD::BUFFER_LOAD_FORMAT : AMDGPUISD::BUFFER_LOAD;
4836
4837 if (IsD16) {
4838 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, M, DAG, Ops);
4839 }
4840
4841 // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
4842 if (!IsD16 && !LoadVT.isVector() && EltType.getSizeInBits() < 32)
4843 return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
4844
4845 if (isTypeLegal(LoadVT)) {
4846 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT,
4847 M->getMemOperand(), DAG);
4848 }
4849
4850 EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT);
4851 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other);
4852 SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT,
4853 M->getMemOperand(), DAG);
4854 return DAG.getMergeValues(
4855 {DAG.getNode(ISD::BITCAST, DL, LoadVT, MemNode), MemNode.getValue(1)},
4856 DL);
4857}
4858
4859static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
4860 SDNode *N, SelectionDAG &DAG) {
4861 EVT VT = N->getValueType(0);
4862 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4863 unsigned CondCode = CD->getZExtValue();
4864 if (!ICmpInst::isIntPredicate(static_cast<ICmpInst::Predicate>(CondCode)))
4865 return DAG.getUNDEF(VT);
4866
4867 ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
4868
4869 SDValue LHS = N->getOperand(1);
4870 SDValue RHS = N->getOperand(2);
4871
4872 SDLoc DL(N);
4873
4874 EVT CmpVT = LHS.getValueType();
4875 if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) {
4876 unsigned PromoteOp = ICmpInst::isSigned(IcInput) ?
4877 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4878 LHS = DAG.getNode(PromoteOp, DL, MVT::i32, LHS);
4879 RHS = DAG.getNode(PromoteOp, DL, MVT::i32, RHS);
4880 }
4881
4882 ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
4883
4884 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4885 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4886
4887 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS,
4888 DAG.getCondCode(CCOpcode));
4889 if (VT.bitsEq(CCVT))
4890 return SetCC;
4891 return DAG.getZExtOrTrunc(SetCC, DL, VT);
4892}
4893
4894static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI,
4895 SDNode *N, SelectionDAG &DAG) {
4896 EVT VT = N->getValueType(0);
4897 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4898
4899 unsigned CondCode = CD->getZExtValue();
4900 if (!FCmpInst::isFPPredicate(static_cast<FCmpInst::Predicate>(CondCode)))
4901 return DAG.getUNDEF(VT);
4902
4903 SDValue Src0 = N->getOperand(1);
4904 SDValue Src1 = N->getOperand(2);
4905 EVT CmpVT = Src0.getValueType();
4906 SDLoc SL(N);
4907
4908 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
4909 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4910 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
4911 }
4912
4913 FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
4914 ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
4915 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4916 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4917 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0,
4918 Src1, DAG.getCondCode(CCOpcode));
4919 if (VT.bitsEq(CCVT))
4920 return SetCC;
4921 return DAG.getZExtOrTrunc(SetCC, SL, VT);
4922}
4923
4924static SDValue lowerBALLOTIntrinsic(const SITargetLowering &TLI, SDNode *N,
4925 SelectionDAG &DAG) {
4926 EVT VT = N->getValueType(0);
4927 SDValue Src = N->getOperand(1);
4928 SDLoc SL(N);
4929
4930 if (Src.getOpcode() == ISD::SETCC) {
4931 // (ballot (ISD::SETCC ...)) -> (AMDGPUISD::SETCC ...)
4932 return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Src.getOperand(0),
4933 Src.getOperand(1), Src.getOperand(2));
4934 }
4935 if (const ConstantSDNode *Arg = dyn_cast<ConstantSDNode>(Src)) {
4936 // (ballot 0) -> 0
4937 if (Arg->isZero())
4938 return DAG.getConstant(0, SL, VT);
4939
4940 // (ballot 1) -> EXEC/EXEC_LO
4941 if (Arg->isOne()) {
4942 Register Exec;
4943 if (VT.getScalarSizeInBits() == 32)
4944 Exec = AMDGPU::EXEC_LO;
4945 else if (VT.getScalarSizeInBits() == 64)
4946 Exec = AMDGPU::EXEC;
4947 else
4948 return SDValue();
4949
4950 return DAG.getCopyFromReg(DAG.getEntryNode(), SL, Exec, VT);
4951 }
4952 }
4953
4954 // (ballot (i1 $src)) -> (AMDGPUISD::SETCC (i32 (zext $src)) (i32 0)
4955 // ISD::SETNE)
4956 return DAG.getNode(
4957 AMDGPUISD::SETCC, SL, VT, DAG.getZExtOrTrunc(Src, SL, MVT::i32),
4958 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE));
4959}
4960
4961void SITargetLowering::ReplaceNodeResults(SDNode *N,
4962 SmallVectorImpl<SDValue> &Results,
4963 SelectionDAG &DAG) const {
4964 switch (N->getOpcode()) {
4965 case ISD::INSERT_VECTOR_ELT: {
4966 if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
4967 Results.push_back(Res);
4968 return;
4969 }
4970 case ISD::EXTRACT_VECTOR_ELT: {
4971 if (SDValue Res = lowerEXTRACT_VECTOR_ELT(SDValue(N, 0), DAG))
4972 Results.push_back(Res);
4973 return;
4974 }
4975 case ISD::INTRINSIC_WO_CHAIN: {
4976 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4977 switch (IID) {
4978 case Intrinsic::amdgcn_cvt_pkrtz: {
4979 SDValue Src0 = N->getOperand(1);
4980 SDValue Src1 = N->getOperand(2);
4981 SDLoc SL(N);
4982 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32,
4983 Src0, Src1);
4984 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt));
4985 return;
4986 }
4987 case Intrinsic::amdgcn_cvt_pknorm_i16:
4988 case Intrinsic::amdgcn_cvt_pknorm_u16:
4989 case Intrinsic::amdgcn_cvt_pk_i16:
4990 case Intrinsic::amdgcn_cvt_pk_u16: {
4991 SDValue Src0 = N->getOperand(1);
4992 SDValue Src1 = N->getOperand(2);
4993 SDLoc SL(N);
4994 unsigned Opcode;
4995
4996 if (IID == Intrinsic::amdgcn_cvt_pknorm_i16)
4997 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
4998 else if (IID == Intrinsic::amdgcn_cvt_pknorm_u16)
4999 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
5000 else if (IID == Intrinsic::amdgcn_cvt_pk_i16)
5001 Opcode = AMDGPUISD::CVT_PK_I16_I32;
5002 else
5003 Opcode = AMDGPUISD::CVT_PK_U16_U32;
5004
5005 EVT VT = N->getValueType(0);
5006 if (isTypeLegal(VT))
5007 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
5008 else {
5009 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
5010 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt));
5011 }
5012 return;
5013 }
5014 }
5015 break;
5016 }
5017 case ISD::INTRINSIC_W_CHAIN: {
5018 if (SDValue Res = LowerINTRINSIC_W_CHAIN(SDValue(N, 0), DAG)) {
5019 if (Res.getOpcode() == ISD::MERGE_VALUES) {
5020 // FIXME: Hacky
5021 for (unsigned I = 0; I < Res.getNumOperands(); I++) {
5022 Results.push_back(Res.getOperand(I));
5023 }
5024 } else {
5025 Results.push_back(Res);
5026 Results.push_back(Res.getValue(1));
5027 }
5028 return;
5029 }
5030
5031 break;
5032 }
5033 case ISD::SELECT: {
5034 SDLoc SL(N);
5035 EVT VT = N->getValueType(0);
5036 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
5037 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1));
5038 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2));
5039
5040 EVT SelectVT = NewVT;
5041 if (NewVT.bitsLT(MVT::i32)) {
5042 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS);
5043 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS);
5044 SelectVT = MVT::i32;
5045 }
5046
5047 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT,
5048 N->getOperand(0), LHS, RHS);
5049
5050 if (NewVT != SelectVT)
5051 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect);
5052 Results.push_back(DAG.getNode(ISD::BITCAST, SL, VT, NewSelect));
5053 return;
5054 }
5055 case ISD::FNEG: {
5056 if (N->getValueType(0) != MVT::v2f16)
5057 break;
5058
5059 SDLoc SL(N);
5060 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
5061
5062 SDValue Op = DAG.getNode(ISD::XOR, SL, MVT::i32,
5063 BC,
5064 DAG.getConstant(0x80008000, SL, MVT::i32));
5065 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
5066 return;
5067 }
5068 case ISD::FABS: {
5069 if (N->getValueType(0) != MVT::v2f16)
5070 break;
5071
5072 SDLoc SL(N);
5073 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
5074
5075 SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32,
5076 BC,
5077 DAG.getConstant(0x7fff7fff, SL, MVT::i32));
5078 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
5079 return;
5080 }
5081 default:
5082 break;
5083 }
5084}
5085
5086/// Helper function for LowerBRCOND
5087static SDNode *findUser(SDValue Value, unsigned Opcode) {
5088
5089 SDNode *Parent = Value.getNode();
5090 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
5091 I != E; ++I) {
5092
5093 if (I.getUse().get() != Value)
5094 continue;
5095
5096 if (I->getOpcode() == Opcode)
5097 return *I;
5098 }
5099 return nullptr;
5100}
5101
5102unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
5103 if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
5104 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
5105 case Intrinsic::amdgcn_if:
5106 return AMDGPUISD::IF;
5107 case Intrinsic::amdgcn_else:
5108 return AMDGPUISD::ELSE;
5109 case Intrinsic::amdgcn_loop:
5110 return AMDGPUISD::LOOP;
5111 case Intrinsic::amdgcn_end_cf:
5112 llvm_unreachable("should not occur")::llvm::llvm_unreachable_internal("should not occur", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5112)
;
5113 default:
5114 return 0;
5115 }
5116 }
5117
5118 // break, if_break, else_break are all only used as inputs to loop, not
5119 // directly as branch conditions.
5120 return 0;
5121}
5122
5123bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
5124 const Triple &TT = getTargetMachine().getTargetTriple();
5125 return (GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
5126 GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
5127 AMDGPU::shouldEmitConstantsToTextSection(TT);
5128}
5129
5130bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
5131 // FIXME: Either avoid relying on address space here or change the default
5132 // address space for functions to avoid the explicit check.
5133 return (GV->getValueType()->isFunctionTy() ||
5134 !isNonGlobalAddrSpace(GV->getAddressSpace())) &&
5135 !shouldEmitFixup(GV) &&
5136 !getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
5137}
5138
5139bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
5140 return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
5141}
5142
5143bool SITargetLowering::shouldUseLDSConstAddress(const GlobalValue *GV) const {
5144 if (!GV->hasExternalLinkage())
5145 return true;
5146
5147 const auto OS = getTargetMachine().getTargetTriple().getOS();
5148 return OS == Triple::AMDHSA || OS == Triple::AMDPAL;
5149}
5150
5151/// This transforms the control flow intrinsics to get the branch destination as
5152/// last parameter, also switches branch target with BR if the need arise
5153SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
5154 SelectionDAG &DAG) const {
5155 SDLoc DL(BRCOND);
5156
5157 SDNode *Intr = BRCOND.getOperand(1).getNode();
5158 SDValue Target = BRCOND.getOperand(2);
5159 SDNode *BR = nullptr;
5160 SDNode *SetCC = nullptr;
5161
5162 if (Intr->getOpcode() == ISD::SETCC) {
5163 // As long as we negate the condition everything is fine
5164 SetCC = Intr;
5165 Intr = SetCC->getOperand(0).getNode();
5166
5167 } else {
5168 // Get the target from BR if we don't negate the condition
5169 BR = findUser(BRCOND, ISD::BR);
5170 assert(BR && "brcond missing unconditional branch user")(static_cast <bool> (BR && "brcond missing unconditional branch user"
) ? void (0) : __assert_fail ("BR && \"brcond missing unconditional branch user\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5170, __extension__
__PRETTY_FUNCTION__))
;
5171 Target = BR->getOperand(1);
5172 }
5173
5174 unsigned CFNode = isCFIntrinsic(Intr);
5175 if (CFNode == 0) {
5176 // This is a uniform branch so we don't need to legalize.
5177 return BRCOND;
5178 }
5179
5180 bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||
5181 Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN;
5182
5183 assert(!SetCC ||(static_cast <bool> (!SetCC || (SetCC->getConstantOperandVal
(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand
(2).getNode())->get() == ISD::SETNE)) ? void (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5186, __extension__
__PRETTY_FUNCTION__))
5184 (SetCC->getConstantOperandVal(1) == 1 &&(static_cast <bool> (!SetCC || (SetCC->getConstantOperandVal
(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand
(2).getNode())->get() == ISD::SETNE)) ? void (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5186, __extension__
__PRETTY_FUNCTION__))
5185 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==(static_cast <bool> (!SetCC || (SetCC->getConstantOperandVal
(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand
(2).getNode())->get() == ISD::SETNE)) ? void (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5186, __extension__
__PRETTY_FUNCTION__))
5186 ISD::SETNE))(static_cast <bool> (!SetCC || (SetCC->getConstantOperandVal
(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand
(2).getNode())->get() == ISD::SETNE)) ? void (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5186, __extension__
__PRETTY_FUNCTION__))
;
5187
5188 // operands of the new intrinsic call
5189 SmallVector<SDValue, 4> Ops;
5190 if (HaveChain)
5191 Ops.push_back(BRCOND.getOperand(0));
5192
5193 Ops.append(Intr->op_begin() + (HaveChain ? 2 : 1), Intr->op_end());
5194 Ops.push_back(Target);
5195
5196 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
5197
5198 // build the new intrinsic call
5199 SDNode *Result = DAG.getNode(CFNode, DL, DAG.getVTList(Res), Ops).getNode();
5200
5201 if (!HaveChain) {
5202 SDValue Ops[] = {
5203 SDValue(Result, 0),
5204 BRCOND.getOperand(0)
5205 };
5206
5207 Result = DAG.getMergeValues(Ops, DL).getNode();
5208 }
5209
5210 if (BR) {
5211 // Give the branch instruction our target
5212 SDValue Ops[] = {
5213 BR->getOperand(0),
5214 BRCOND.getOperand(2)
5215 };
5216 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
5217 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
5218 }
5219
5220 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
5221
5222 // Copy the intrinsic results to registers
5223 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
5224 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
5225 if (!CopyToReg)
5226 continue;
5227
5228 Chain = DAG.getCopyToReg(
5229 Chain, DL,
5230 CopyToReg->getOperand(1),
5231 SDValue(Result, i - 1),
5232 SDValue());
5233
5234 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
5235 }
5236
5237 // Remove the old intrinsic from the chain
5238 DAG.ReplaceAllUsesOfValueWith(
5239 SDValue(Intr, Intr->getNumValues() - 1),
5240 Intr->getOperand(0));
5241
5242 return Chain;
5243}
5244
5245SDValue SITargetLowering::LowerRETURNADDR(SDValue Op,
5246 SelectionDAG &DAG) const {
5247 MVT VT = Op.getSimpleValueType();
5248 SDLoc DL(Op);
5249 // Checking the depth
5250 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0)
5251 return DAG.getConstant(0, DL, VT);
5252
5253 MachineFunction &MF = DAG.getMachineFunction();
5254 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5255 // Check for kernel and shader functions
5256 if (Info->isEntryFunction())
5257 return DAG.getConstant(0, DL, VT);
5258
5259 MachineFrameInfo &MFI = MF.getFrameInfo();
5260 // There is a call to @llvm.returnaddress in this function
5261 MFI.setReturnAddressIsTaken(true);
5262
5263 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
5264 // Get the return address reg and mark it as an implicit live-in
5265 Register Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent()));
5266
5267 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
5268}
5269
5270SDValue SITargetLowering::getFPExtOrFPRound(SelectionDAG &DAG,
5271 SDValue Op,
5272 const SDLoc &DL,
5273 EVT VT) const {
5274 return Op.getValueType().bitsLE(VT) ?
5275 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) :
5276 DAG.getNode(ISD::FP_ROUND, DL, VT, Op,
5277 DAG.getTargetConstant(0, DL, MVT::i32));
5278}
5279
5280SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
5281 assert(Op.getValueType() == MVT::f16 &&(static_cast <bool> (Op.getValueType() == MVT::f16 &&
"Do not know how to custom lower FP_ROUND for non-f16 type")
? void (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5282, __extension__
__PRETTY_FUNCTION__))
5282 "Do not know how to custom lower FP_ROUND for non-f16 type")(static_cast <bool> (Op.getValueType() == MVT::f16 &&
"Do not know how to custom lower FP_ROUND for non-f16 type")
? void (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5282, __extension__
__PRETTY_FUNCTION__))
;
5283
5284 SDValue Src = Op.getOperand(0);
5285 EVT SrcVT = Src.getValueType();
5286 if (SrcVT != MVT::f64)
5287 return Op;
5288
5289 SDLoc DL(Op);
5290
5291 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);
5292 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToFp16);
5293 return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);
5294}
5295
5296SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
5297 SelectionDAG &DAG) const {
5298 EVT VT = Op.getValueType();
5299 const MachineFunction &MF = DAG.getMachineFunction();
5300 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5301 bool IsIEEEMode = Info->getMode().IEEE;
5302
5303 // FIXME: Assert during selection that this is only selected for
5304 // ieee_mode. Currently a combine can produce the ieee version for non-ieee
5305 // mode functions, but this happens to be OK since it's only done in cases
5306 // where there is known no sNaN.
5307 if (IsIEEEMode)
5308 return expandFMINNUM_FMAXNUM(Op.getNode(), DAG);
5309
5310 if (VT == MVT::v4f16)
5311 return splitBinaryVectorOp(Op, DAG);
5312 return Op;
5313}
5314
5315SDValue SITargetLowering::lowerXMULO(SDValue Op, SelectionDAG &DAG) const {
5316 EVT VT = Op.getValueType();
5317 SDLoc SL(Op);
5318 SDValue LHS = Op.getOperand(0);
5319 SDValue RHS = Op.getOperand(1);
5320 bool isSigned = Op.getOpcode() == ISD::SMULO;
5321
5322 if (ConstantSDNode *RHSC = isConstOrConstSplat(RHS)) {
5323 const APInt &C = RHSC->getAPIntValue();
5324 // mulo(X, 1 << S) -> { X << S, (X << S) >> S != X }
5325 if (C.isPowerOf2()) {
5326 // smulo(x, signed_min) is same as umulo(x, signed_min).
5327 bool UseArithShift = isSigned && !C.isMinSignedValue();
5328 SDValue ShiftAmt = DAG.getConstant(C.logBase2(), SL, MVT::i32);
5329 SDValue Result = DAG.getNode(ISD::SHL, SL, VT, LHS, ShiftAmt);
5330 SDValue Overflow = DAG.getSetCC(SL, MVT::i1,
5331 DAG.getNode(UseArithShift ? ISD::SRA : ISD::SRL,
5332 SL, VT, Result, ShiftAmt),
5333 LHS, ISD::SETNE);
5334 return DAG.getMergeValues({ Result, Overflow }, SL);
5335 }
5336 }
5337
5338 SDValue Result = DAG.getNode(ISD::MUL, SL, VT, LHS, RHS);
5339 SDValue Top = DAG.getNode(isSigned ? ISD::MULHS : ISD::MULHU,
5340 SL, VT, LHS, RHS);
5341
5342 SDValue Sign = isSigned
5343 ? DAG.getNode(ISD::SRA, SL, VT, Result,
5344 DAG.getConstant(VT.getScalarSizeInBits() - 1, SL, MVT::i32))
5345 : DAG.getConstant(0, SL, VT);
5346 SDValue Overflow = DAG.getSetCC(SL, MVT::i1, Top, Sign, ISD::SETNE);
5347
5348 return DAG.getMergeValues({ Result, Overflow }, SL);
5349}
5350
5351SDValue SITargetLowering::lowerXMUL_LOHI(SDValue Op, SelectionDAG &DAG) const {
5352 if (Op->isDivergent()) {
5353 // Select to V_MAD_[IU]64_[IU]32.
5354 return Op;
5355 }
5356 if (Subtarget->hasSMulHi()) {
5357 // Expand to S_MUL_I32 + S_MUL_HI_[IU]32.
5358 return SDValue();
5359 }
5360 // The multiply is uniform but we would have to use V_MUL_HI_[IU]32 to
5361 // calculate the high part, so we might as well do the whole thing with
5362 // V_MAD_[IU]64_[IU]32.
5363 return Op;
5364}
5365
5366SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
5367 if (!Subtarget->isTrapHandlerEnabled() ||
5368 Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA)
5369 return lowerTrapEndpgm(Op, DAG);
5370
5371 if (Optional<uint8_t> HsaAbiVer = AMDGPU::getHsaAbiVersion(Subtarget)) {
5372 switch (*HsaAbiVer) {
5373 case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
5374 case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
5375 return lowerTrapHsaQueuePtr(Op, DAG);
5376 case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
5377 return Subtarget->supportsGetDoorbellID() ?
5378 lowerTrapHsa(Op, DAG) : lowerTrapHsaQueuePtr(Op, DAG);
5379 }
5380 }
5381
5382 llvm_unreachable("Unknown trap handler")::llvm::llvm_unreachable_internal("Unknown trap handler", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5382)
;
5383}
5384
5385SDValue SITargetLowering::lowerTrapEndpgm(
5386 SDValue Op, SelectionDAG &DAG) const {
5387 SDLoc SL(Op);
5388 SDValue Chain = Op.getOperand(0);
5389 return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain);
5390}
5391
5392SDValue SITargetLowering::lowerTrapHsaQueuePtr(
5393 SDValue Op, SelectionDAG &DAG) const {
5394 SDLoc SL(Op);
5395 SDValue Chain = Op.getOperand(0);
5396
5397 MachineFunction &MF = DAG.getMachineFunction();
5398 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5399 Register UserSGPR = Info->getQueuePtrUserSGPR();
5400
5401 SDValue QueuePtr;
5402 if (UserSGPR == AMDGPU::NoRegister) {
5403 // We probably are in a function incorrectly marked with
5404 // amdgpu-no-queue-ptr. This is undefined. We don't want to delete the trap,
5405 // so just use a null pointer.
5406 QueuePtr = DAG.getConstant(0, SL, MVT::i64);
5407 } else {
5408 QueuePtr = CreateLiveInRegister(
5409 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
5410 }
5411
5412 SDValue SGPR01 = DAG.getRegister(AMDGPU::SGPR0_SGPR1, MVT::i64);
5413 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01,
5414 QueuePtr, SDValue());
5415
5416 uint64_t TrapID = static_cast<uint64_t>(GCNSubtarget::TrapID::LLVMAMDHSATrap);
5417 SDValue Ops[] = {
5418 ToReg,
5419 DAG.getTargetConstant(TrapID, SL, MVT::i16),
5420 SGPR01,
5421 ToReg.getValue(1)
5422 };
5423 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
5424}
5425
5426SDValue SITargetLowering::lowerTrapHsa(
5427 SDValue Op, SelectionDAG &DAG) const {
5428 SDLoc SL(Op);
5429 SDValue Chain = Op.getOperand(0);
5430
5431 uint64_t TrapID = static_cast<uint64_t>(GCNSubtarget::TrapID::LLVMAMDHSATrap);
5432 SDValue Ops[] = {
5433 Chain,
5434 DAG.getTargetConstant(TrapID, SL, MVT::i16)
5435 };
5436 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
5437}
5438
5439SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
5440 SDLoc SL(Op);
5441 SDValue Chain = Op.getOperand(0);
5442 MachineFunction &MF = DAG.getMachineFunction();
5443
5444 if (!Subtarget->isTrapHandlerEnabled() ||
5445 Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) {
5446 DiagnosticInfoUnsupported NoTrap(MF.getFunction(),
5447 "debugtrap handler not supported",
5448 Op.getDebugLoc(),
5449 DS_Warning);
5450 LLVMContext &Ctx = MF.getFunction().getContext();
5451 Ctx.diagnose(NoTrap);
5452 return Chain;
5453 }
5454
5455 uint64_t TrapID = static_cast<uint64_t>(GCNSubtarget::TrapID::LLVMAMDHSADebugTrap);
5456 SDValue Ops[] = {
5457 Chain,
5458 DAG.getTargetConstant(TrapID, SL, MVT::i16)
5459 };
5460 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
5461}
5462
5463SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
5464 SelectionDAG &DAG) const {
5465 // FIXME: Use inline constants (src_{shared, private}_base) instead.
5466 if (Subtarget->hasApertureRegs()) {
5467 unsigned Offset = AS == AMDGPUAS::LOCAL_ADDRESS ?
5468 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE :
5469 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE;
5470 unsigned WidthM1 = AS == AMDGPUAS::LOCAL_ADDRESS ?
5471 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
5472 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
5473 unsigned Encoding =
5474 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
5475 Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
5476 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
5477
5478 SDValue EncodingImm = DAG.getTargetConstant(Encoding, DL, MVT::i16);
5479 SDValue ApertureReg = SDValue(
5480 DAG.getMachineNode(AMDGPU::S_GETREG_B32, DL, MVT::i32, EncodingImm), 0);
5481 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32);
5482 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);
5483 }
5484
5485 MachineFunction &MF = DAG.getMachineFunction();
5486 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
5487 Register UserSGPR = Info->getQueuePtrUserSGPR();
5488 if (UserSGPR == AMDGPU::NoRegister) {
5489 // We probably are in a function incorrectly marked with
5490 // amdgpu-no-queue-ptr. This is undefined.
5491 return DAG.getUNDEF(MVT::i32);
5492 }
5493
5494 SDValue QueuePtr = CreateLiveInRegister(
5495 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
5496
5497 // Offset into amd_queue_t for group_segment_aperture_base_hi /
5498 // private_segment_aperture_base_hi.
5499 uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
5500
5501 SDValue Ptr =
5502 DAG.getObjectPtrOffset(DL, QueuePtr, TypeSize::Fixed(StructOffset));
5503
5504 // TODO: Use custom target PseudoSourceValue.
5505 // TODO: We should use the value from the IR intrinsic call, but it might not
5506 // be available and how do we get it?
5507 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
5508 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,
5509 commonAlignment(Align(64), StructOffset),
5510 MachineMemOperand::MODereferenceable |
5511 MachineMemOperand::MOInvariant);
5512}
5513
5514/// Return true if the value is a known valid address, such that a null check is
5515/// not necessary.
5516static bool isKnownNonNull(SDValue Val, SelectionDAG &DAG,
5517 const AMDGPUTargetMachine &TM, unsigned AddrSpace) {
5518 if (isa<FrameIndexSDNode>(Val) || isa<GlobalAddressSDNode>(Val) ||
5519 isa<BasicBlockSDNode>(Val))
5520 return true;
5521
5522 if (auto *ConstVal = dyn_cast<ConstantSDNode>(Val))
5523 return ConstVal->getSExtValue() != TM.getNullPointerValue(AddrSpace);
5524
5525 // TODO: Search through arithmetic, handle arguments and loads
5526 // marked nonnull.
5527 return false;
5528}
5529
5530SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
5531 SelectionDAG &DAG) const {
5532 SDLoc SL(Op);
5533 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
5534
5535 SDValue Src = ASC->getOperand(0);
5536 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64);
5537 unsigned SrcAS = ASC->getSrcAddressSpace();
5538
5539 const AMDGPUTargetMachine &TM =
5540 static_cast<const AMDGPUTargetMachine &>(getTargetMachine());
5541
5542 // flat -> local/private
5543 if (SrcAS == AMDGPUAS::FLAT_ADDRESS) {
5544 unsigned DestAS = ASC->getDestAddressSpace();
5545
5546 if (DestAS == AMDGPUAS::LOCAL_ADDRESS ||
5547 DestAS == AMDGPUAS::PRIVATE_ADDRESS) {
5548 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
5549
5550 if (isKnownNonNull(Src, DAG, TM, SrcAS))
5551 return Ptr;
5552
5553 unsigned NullVal = TM.getNullPointerValue(DestAS);
5554 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
5555 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE);
5556
5557 return DAG.getNode(ISD::SELECT, SL, MVT::i32, NonNull, Ptr,
5558 SegmentNullPtr);
5559 }
5560 }
5561
5562 // local/private -> flat
5563 if (ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
5564 if (SrcAS == AMDGPUAS::LOCAL_ADDRESS ||
5565 SrcAS == AMDGPUAS::PRIVATE_ADDRESS) {
5566
5567 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), SL, DAG);
5568 SDValue CvtPtr =
5569 DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture);
5570 CvtPtr = DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr);
5571
5572 if (isKnownNonNull(Src, DAG, TM, SrcAS))
5573 return CvtPtr;
5574
5575 unsigned NullVal = TM.getNullPointerValue(SrcAS);
5576 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
5577
5578 SDValue NonNull
5579 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE);
5580
5581 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull, CvtPtr,
5582 FlatNullPtr);
5583 }
5584 }
5585
5586 if (ASC->getDestAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT &&
5587 Src.getValueType() == MVT::i64)
5588 return DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
5589
5590 // global <-> flat are no-ops and never emitted.
5591
5592 const MachineFunction &MF = DAG.getMachineFunction();
5593 DiagnosticInfoUnsupported InvalidAddrSpaceCast(
5594 MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc());
5595 DAG.getContext()->diagnose(InvalidAddrSpaceCast);
5596
5597 return DAG.getUNDEF(ASC->getValueType(0));
5598}
5599
5600// This lowers an INSERT_SUBVECTOR by extracting the individual elements from
5601// the small vector and inserting them into the big vector. That is better than
5602// the default expansion of doing it via a stack slot. Even though the use of
5603// the stack slot would be optimized away afterwards, the stack slot itself
5604// remains.
5605SDValue SITargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
5606 SelectionDAG &DAG) const {
5607 SDValue Vec = Op.getOperand(0);
5608 SDValue Ins = Op.getOperand(1);
5609 SDValue Idx = Op.getOperand(2);
5610 EVT VecVT = Vec.getValueType();
5611 EVT InsVT = Ins.getValueType();
5612 EVT EltVT = VecVT.getVectorElementType();
5613 unsigned InsNumElts = InsVT.getVectorNumElements();
5614 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
5615 SDLoc SL(Op);
5616
5617 for (unsigned I = 0; I != InsNumElts; ++I) {
5618 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Ins,
5619 DAG.getConstant(I, SL, MVT::i32));
5620 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt,
5621 DAG.getConstant(IdxVal + I, SL, MVT::i32));
5622 }
5623 return Vec;
5624}
5625
5626SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
5627 SelectionDAG &DAG) const {
5628 SDValue Vec = Op.getOperand(0);
5629 SDValue InsVal = Op.getOperand(1);
5630 SDValue Idx = Op.getOperand(2);
5631 EVT VecVT = Vec.getValueType();
5632 EVT EltVT = VecVT.getVectorElementType();
5633 unsigned VecSize = VecVT.getSizeInBits();
5634 unsigned EltSize = EltVT.getSizeInBits();
5635
5636
5637 assert(VecSize <= 64)(static_cast <bool> (VecSize <= 64) ? void (0) : __assert_fail
("VecSize <= 64", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5637, __extension__ __PRETTY_FUNCTION__))
;
5638
5639 unsigned NumElts = VecVT.getVectorNumElements();
5640 SDLoc SL(Op);
5641 auto KIdx = dyn_cast<ConstantSDNode>(Idx);
5642
5643 if (NumElts == 4 && EltSize == 16 && KIdx) {
5644 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec);
5645
5646 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
5647 DAG.getConstant(0, SL, MVT::i32));
5648 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
5649 DAG.getConstant(1, SL, MVT::i32));
5650
5651 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf);
5652 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf);
5653
5654 unsigned Idx = KIdx->getZExtValue();
5655 bool InsertLo = Idx < 2;
5656 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16,
5657 InsertLo ? LoVec : HiVec,
5658 DAG.getNode(ISD::BITCAST, SL, MVT::i16, InsVal),
5659 DAG.getConstant(InsertLo ? Idx : (Idx - 2), SL, MVT::i32));
5660
5661 InsHalf = DAG.getNode(ISD::BITCAST, SL, MVT::i32, InsHalf);
5662
5663 SDValue Concat = InsertLo ?
5664 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) :
5665 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf });
5666
5667 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
5668 }
5669
5670 if (isa<ConstantSDNode>(Idx))
5671 return SDValue();
5672
5673 MVT IntVT = MVT::getIntegerVT(VecSize);
5674
5675 // Avoid stack access for dynamic indexing.
5676 // v_bfi_b32 (v_bfm_b32 16, (shl idx, 16)), val, vec
5677
5678 // Create a congruent vector with the target value in each element so that
5679 // the required element can be masked and ORed into the target vector.
5680 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT,
5681 DAG.getSplatBuildVector(VecVT, SL, InsVal));
5682
5683 assert(isPowerOf2_32(EltSize))(static_cast <bool> (isPowerOf2_32(EltSize)) ? void (0)
: __assert_fail ("isPowerOf2_32(EltSize)", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5683, __extension__ __PRETTY_FUNCTION__))
;
5684 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
5685
5686 // Convert vector index to bit-index.
5687 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
5688
5689 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
5690 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT,
5691 DAG.getConstant(0xffff, SL, IntVT),
5692 ScaledIdx);
5693
5694 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal);
5695 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT,
5696 DAG.getNOT(SL, BFM, IntVT), BCVec);
5697
5698 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS);
5699 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI);
5700}
5701
5702SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
5703 SelectionDAG &DAG) const {
5704 SDLoc SL(Op);
5705
5706 EVT ResultVT = Op.getValueType();
5707 SDValue Vec = Op.getOperand(0);
5708 SDValue Idx = Op.getOperand(1);
5709 EVT VecVT = Vec.getValueType();
5710 unsigned VecSize = VecVT.getSizeInBits();
5711 EVT EltVT = VecVT.getVectorElementType();
5712 assert(VecSize <= 64)(static_cast <bool> (VecSize <= 64) ? void (0) : __assert_fail
("VecSize <= 64", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5712, __extension__ __PRETTY_FUNCTION__))
;
5713
5714 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
5715
5716 // Make sure we do any optimizations that will make it easier to fold
5717 // source modifiers before obscuring it with bit operations.
5718
5719 // XXX - Why doesn't this get called when vector_shuffle is expanded?
5720 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
5721 return Combined;
5722
5723 unsigned EltSize = EltVT.getSizeInBits();
5724 assert(isPowerOf2_32(EltSize))(static_cast <bool> (isPowerOf2_32(EltSize)) ? void (0)
: __assert_fail ("isPowerOf2_32(EltSize)", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5724, __extension__ __PRETTY_FUNCTION__))
;
5725
5726 MVT IntVT = MVT::getIntegerVT(VecSize);
5727 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
5728
5729 // Convert vector index to bit-index (* EltSize)
5730 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
5731
5732 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
5733 SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx);
5734
5735 if (ResultVT == MVT::f16) {
5736 SDValue Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Elt);
5737 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
5738 }
5739
5740 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT);
5741}
5742
5743static bool elementPairIsContiguous(ArrayRef<int> Mask, int Elt) {
5744 assert(Elt % 2 == 0)(static_cast <bool> (Elt % 2 == 0) ? void (0) : __assert_fail
("Elt % 2 == 0", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5744, __extension__ __PRETTY_FUNCTION__))
;
5745 return Mask[Elt + 1] == Mask[Elt] + 1 && (Mask[Elt] % 2 == 0);
5746}
5747
5748SDValue SITargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
5749 SelectionDAG &DAG) const {
5750 SDLoc SL(Op);
5751 EVT ResultVT = Op.getValueType();
5752 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
5753
5754 EVT PackVT = ResultVT.isInteger() ? MVT::v2i16 : MVT::v2f16;
5755 EVT EltVT = PackVT.getVectorElementType();
5756 int SrcNumElts = Op.getOperand(0).getValueType().getVectorNumElements();
5757
5758 // vector_shuffle <0,1,6,7> lhs, rhs
5759 // -> concat_vectors (extract_subvector lhs, 0), (extract_subvector rhs, 2)
5760 //
5761 // vector_shuffle <6,7,2,3> lhs, rhs
5762 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 2)
5763 //
5764 // vector_shuffle <6,7,0,1> lhs, rhs
5765 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 0)
5766
5767 // Avoid scalarizing when both halves are reading from consecutive elements.
5768 SmallVector<SDValue, 4> Pieces;
5769 for (int I = 0, N = ResultVT.getVectorNumElements(); I != N; I += 2) {
5770 if (elementPairIsContiguous(SVN->getMask(), I)) {
5771 const int Idx = SVN->getMaskElt(I);
5772 int VecIdx = Idx < SrcNumElts ? 0 : 1;
5773 int EltIdx = Idx < SrcNumElts ? Idx : Idx - SrcNumElts;
5774 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL,
5775 PackVT, SVN->getOperand(VecIdx),
5776 DAG.getConstant(EltIdx, SL, MVT::i32));
5777 Pieces.push_back(SubVec);
5778 } else {
5779 const int Idx0 = SVN->getMaskElt(I);
5780 const int Idx1 = SVN->getMaskElt(I + 1);
5781 int VecIdx0 = Idx0 < SrcNumElts ? 0 : 1;
5782 int VecIdx1 = Idx1 < SrcNumElts ? 0 : 1;
5783 int EltIdx0 = Idx0 < SrcNumElts ? Idx0 : Idx0 - SrcNumElts;
5784 int EltIdx1 = Idx1 < SrcNumElts ? Idx1 : Idx1 - SrcNumElts;
5785
5786 SDValue Vec0 = SVN->getOperand(VecIdx0);
5787 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
5788 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32));
5789
5790 SDValue Vec1 = SVN->getOperand(VecIdx1);
5791 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
5792 Vec1, DAG.getConstant(EltIdx1, SL, MVT::i32));
5793 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 }));
5794 }
5795 }
5796
5797 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces);
5798}
5799
5800SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
5801 SelectionDAG &DAG) const {
5802 SDLoc SL(Op);
5803 EVT VT = Op.getValueType();
5804
5805 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
5806 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2);
5807
5808 // Turn into pair of packed build_vectors.
5809 // TODO: Special case for constants that can be materialized with s_mov_b64.
5810 SDValue Lo = DAG.getBuildVector(HalfVT, SL,
5811 { Op.getOperand(0), Op.getOperand(1) });
5812 SDValue Hi = DAG.getBuildVector(HalfVT, SL,
5813 { Op.getOperand(2), Op.getOperand(3) });
5814
5815 SDValue CastLo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Lo);
5816 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Hi);
5817
5818 SDValue Blend = DAG.getBuildVector(MVT::v2i32, SL, { CastLo, CastHi });
5819 return DAG.getNode(ISD::BITCAST, SL, VT, Blend);
5820 }
5821
5822 assert(VT == MVT::v2f16 || VT == MVT::v2i16)(static_cast <bool> (VT == MVT::v2f16 || VT == MVT::v2i16
) ? void (0) : __assert_fail ("VT == MVT::v2f16 || VT == MVT::v2i16"
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5822, __extension__
__PRETTY_FUNCTION__))
;
5823 assert(!Subtarget->hasVOP3PInsts() && "this should be legal")(static_cast <bool> (!Subtarget->hasVOP3PInsts() &&
"this should be legal") ? void (0) : __assert_fail ("!Subtarget->hasVOP3PInsts() && \"this should be legal\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5823, __extension__
__PRETTY_FUNCTION__))
;
5824
5825 SDValue Lo = Op.getOperand(0);
5826 SDValue Hi = Op.getOperand(1);
5827
5828 // Avoid adding defined bits with the zero_extend.
5829 if (Hi.isUndef()) {
5830 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
5831 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo);
5832 return DAG.getNode(ISD::BITCAST, SL, VT, ExtLo);
5833 }
5834
5835 Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Hi);
5836 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi);
5837
5838 SDValue ShlHi = DAG.getNode(ISD::SHL, SL, MVT::i32, Hi,
5839 DAG.getConstant(16, SL, MVT::i32));
5840 if (Lo.isUndef())
5841 return DAG.getNode(ISD::BITCAST, SL, VT, ShlHi);
5842
5843 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
5844 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);
5845
5846 SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi);
5847 return DAG.getNode(ISD::BITCAST, SL, VT, Or);
5848}
5849
5850bool
5851SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5852 // We can fold offsets for anything that doesn't require a GOT relocation.
5853 return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
5854 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
5855 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
5856 !shouldEmitGOTReloc(GA->getGlobal());
5857}
5858
5859static SDValue
5860buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
5861 const SDLoc &DL, int64_t Offset, EVT PtrVT,
5862 unsigned GAFlags = SIInstrInfo::MO_NONE) {
5863 assert(isInt<32>(Offset + 4) && "32-bit offset is expected!")(static_cast <bool> (isInt<32>(Offset + 4) &&
"32-bit offset is expected!") ? void (0) : __assert_fail ("isInt<32>(Offset + 4) && \"32-bit offset is expected!\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5863, __extension__
__PRETTY_FUNCTION__))
;
5864 // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
5865 // lowered to the following code sequence:
5866 //
5867 // For constant address space:
5868 // s_getpc_b64 s[0:1]
5869 // s_add_u32 s0, s0, $symbol
5870 // s_addc_u32 s1, s1, 0
5871 //
5872 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5873 // a fixup or relocation is emitted to replace $symbol with a literal
5874 // constant, which is a pc-relative offset from the encoding of the $symbol
5875 // operand to the global variable.
5876 //
5877 // For global address space:
5878 // s_getpc_b64 s[0:1]
5879 // s_add_u32 s0, s0, $symbol@{gotpc}rel32@lo
5880 // s_addc_u32 s1, s1, $symbol@{gotpc}rel32@hi
5881 //
5882 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5883 // fixups or relocations are emitted to replace $symbol@*@lo and
5884 // $symbol@*@hi with lower 32 bits and higher 32 bits of a literal constant,
5885 // which is a 64-bit pc-relative offset from the encoding of the $symbol
5886 // operand to the global variable.
5887 //
5888 // What we want here is an offset from the value returned by s_getpc
5889 // (which is the address of the s_add_u32 instruction) to the global
5890 // variable, but since the encoding of $symbol starts 4 bytes after the start
5891 // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
5892 // small. This requires us to add 4 to the global variable offset in order to
5893 // compute the correct address. Similarly for the s_addc_u32 instruction, the
5894 // encoding of $symbol starts 12 bytes after the start of the s_add_u32
5895 // instruction.
5896 SDValue PtrLo =
5897 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags);
5898 SDValue PtrHi;
5899 if (GAFlags == SIInstrInfo::MO_NONE) {
5900 PtrHi = DAG.getTargetConstant(0, DL, MVT::i32);
5901 } else {
5902 PtrHi =
5903 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 12, GAFlags + 1);
5904 }
5905 return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, PtrLo, PtrHi);
5906}
5907
5908SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
5909 SDValue Op,
5910 SelectionDAG &DAG) const {
5911 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
5912 SDLoc DL(GSD);
5913 EVT PtrVT = Op.getValueType();
5914
5915 const GlobalValue *GV = GSD->getGlobal();
5916 if ((GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
5917 shouldUseLDSConstAddress(GV)) ||
5918 GSD->getAddressSpace() == AMDGPUAS::REGION_ADDRESS ||
5919 GSD->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
5920 if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
5921 GV->hasExternalLinkage()) {
5922 Type *Ty = GV->getValueType();
5923 // HIP uses an unsized array `extern __shared__ T s[]` or similar
5924 // zero-sized type in other languages to declare the dynamic shared
5925 // memory which size is not known at the compile time. They will be
5926 // allocated by the runtime and placed directly after the static
5927 // allocated ones. They all share the same offset.
5928 if (DAG.getDataLayout().getTypeAllocSize(Ty).isZero()) {
5929 assert(PtrVT == MVT::i32 && "32-bit pointer is expected.")(static_cast <bool> (PtrVT == MVT::i32 && "32-bit pointer is expected."
) ? void (0) : __assert_fail ("PtrVT == MVT::i32 && \"32-bit pointer is expected.\""
, "llvm/lib/Target/AMDGPU/SIISelLowering.cpp", 5929, __extension__
__PRETTY_FUNCTION__))
;
5930 // Adjust alignment for that dynamic shared memory array.
5931 MFI->setDynLDSAlign(DAG.getDataLayout(), *cast<GlobalVariable>(GV));
5932 return SDValue(
5933 DAG.getMachineNode(AMDGPU::GET_GROUPSTATICSIZE, DL, PtrVT), 0);
5934 }
5935 }
5936 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
5937 }
5938
5939 if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
5940 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, GSD->getOffset(),
5941 SIInstrInfo::MO_ABS32_LO);
5942 return DAG.getNode(AMDGPUISD::LDS, DL, MVT::i32, GA);
5943 }
5944
5945 if (shouldEmitFixup(GV))
5946 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
5947 else if (shouldEmitPCReloc(GV))
5948 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
5949 SIInstrInfo::MO_REL32);
5950
5951 SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
5952 SIInstrInfo::MO_GOTPCREL32);
5953
5954 Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
5955 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
5956 const DataLayout &DataLayout = DAG.getDataLayout();
5957 Align Alignment = DataLayout.getABITypeAlign(PtrTy);
5958 MachinePointerInfo PtrInfo
5959 = MachinePointerInfo::getGOT(DAG.getMachineFunction());
5960
5961 return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Alignment,
5962 MachineMemOperand::MODereferenceable |
5963 MachineMemOperand::MOInvariant);
5964}
5965
5966SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
5967 const SDLoc &DL, SDValue V) const {
5968 // We can't use S_MOV_B32 directly, because there is no way to specify m0 as
5969 // the destination register.
5970 //
5971 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
5972 // so we will end up with redundant moves to m0.
5973 //
5974 // We use a pseudo to ensure we emit s_mov_b32 with m0 as the direct result.
5975
5976 // A Null SDValue creates a glue result.
5977 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue,
5978 V, Chain);
5979 return SDValue(M0, 0);
5980}
5981
5982SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
5983 SDValue Op,
5984 MVT VT,
5985 unsigned Offset) const {
5986 SDLoc SL(Op);
5987 SDValue Param = lowerKernargMemParameter(
5988 DAG, MVT::i32, MVT::i32, SL, DAG.getEntryNode(), Offset, Align(4), false);
5989 // The local size values will have the hi 16-bits as zero.
5990 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
5991 DAG.getValueType(VT));
5992}
5993
5994static SDValue emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5995 EVT VT) {
5996 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5997 "non-hsa intrinsic with hsa target",
5998 DL.getDebugLoc());
5999 DAG.getContext()->diagnose(BadIntrin);
6000 return DAG.getUNDEF(VT);
6001}
6002
6003static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
6004 EVT VT) {
6005 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
6006 "intrinsic not supported on subtarget",
6007 DL.getDebugLoc());
6008 DAG.getContext()->diagnose(BadIntrin);
6009 return DAG.getUNDEF(VT);
6010}
6011
6012static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
6013 ArrayRef<SDValue> Elts) {
6014 assert(!Elts.empty())(static_cast <bool> (!Elts.empty()) ? void (0) : __assert_fail
("!Elts.empty()", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6014, __extension__ __PRETTY_FUNCTION__))
;
6015 MVT Type;
6016 unsigned NumElts = Elts.size();
6017
6018 if (NumElts <= 8) {
6019 Type = MVT::getVectorVT(MVT::f32, NumElts);
6020 } else {
6021 assert(Elts.size() <= 16)(static_cast <bool> (Elts.size() <= 16) ? void (0) :
__assert_fail ("Elts.size() <= 16", "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6021, __extension__ __PRETTY_FUNCTION__))
;
6022 Type = MVT::v16f32;
6023 NumElts = 16;
6024 }
6025
6026 SmallVector<SDValue, 16> VecElts(NumElts);
6027 for (unsigned i = 0; i < Elts.size(); ++i) {
6028 SDValue Elt = Elts[i];
6029 if (Elt.getValueType() != MVT::f32)
6030 Elt = DAG.getBitcast(MVT::f32, Elt);
6031 VecElts[i] = Elt;
6032 }
6033 for (unsigned i = Elts.size(); i < NumElts; ++i)
6034 VecElts[i] = DAG.getUNDEF(MVT::f32);
6035
6036 if (NumElts == 1)
6037 return VecElts[0];
6038 return DAG.getBuildVector(Type, DL, VecElts);
6039}
6040
6041static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT,
6042 SDValue Src, int ExtraElts) {
6043 EVT SrcVT = Src.getValueType();
6044
6045 SmallVector<SDValue, 8> Elts;
6046
6047 if (SrcVT.isVector())
6048 DAG.ExtractVectorElements(Src, Elts);
6049 else
6050 Elts.push_back(Src);
6051
6052 SDValue Undef = DAG.getUNDEF(SrcVT.getScalarType());
6053 while (ExtraElts--)
6054 Elts.push_back(Undef);
6055
6056 return DAG.getBuildVector(CastVT, DL, Elts);
6057}
6058
6059// Re-construct the required return value for a image load intrinsic.
6060// This is more complicated due to the optional use TexFailCtrl which means the required
6061// return type is an aggregate
6062static SDValue constructRetValue(SelectionDAG &DAG,
6063 MachineSDNode *Result,
6064 ArrayRef<EVT> ResultTypes,
6065 bool IsTexFail, bool Unpacked, bool IsD16,
6066 int DMaskPop, int NumVDataDwords,
6067 const SDLoc &DL) {
6068 // Determine the required return type. This is the same regardless of IsTexFail flag
6069 EVT ReqRetVT = ResultTypes[0];
6070 int ReqRetNumElts = ReqRetVT.isVector() ? ReqRetVT.getVectorNumElements() : 1;
6071 int NumDataDwords = (!IsD16 || (IsD16 && Unpacked)) ?
6072 ReqRetNumElts : (ReqRetNumElts + 1) / 2;
6073
6074 int MaskPopDwords = (!IsD16 || (IsD16 && Unpacked)) ?
6075 DMaskPop : (DMaskPop + 1) / 2;
6076
6077 MVT DataDwordVT = NumDataDwords == 1 ?
6078 MVT::i32 : MVT::getVectorVT(MVT::i32, NumDataDwords);
6079
6080 MVT MaskPopVT = MaskPopDwords == 1 ?
6081 MVT::i32 : MVT::getVectorVT(MVT::i32, MaskPopDwords);
6082
6083 SDValue Data(Result, 0);
6084 SDValue TexFail;
6085
6086 if (DMaskPop > 0 && Data.getValueType() != MaskPopVT) {
6087 SDValue ZeroIdx = DAG.getConstant(0, DL, MVT::i32);
6088 if (MaskPopVT.isVector()) {
6089 Data = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MaskPopVT,
6090 SDValue(Result, 0), ZeroIdx);
6091 } else {
6092 Data = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MaskPopVT,
6093 SDValue(Result, 0), ZeroIdx);
6094 }
6095 }
6096
6097 if (DataDwordVT.isVector())
6098 Data = padEltsToUndef(DAG, DL, DataDwordVT, Data,
6099 NumDataDwords - MaskPopDwords);
6100
6101 if (IsD16)
6102 Data = adjustLoadValueTypeImpl(Data, ReqRetVT, DL, DAG, Unpacked);
6103
6104 EVT LegalReqRetVT = ReqRetVT;
6105 if (!ReqRetVT.isVector()) {
6106 if (!Data.getValueType().isInteger())
6107 Data = DAG.getNode(ISD::BITCAST, DL,
6108 Data.getValueType().changeTypeToInteger(), Data);
6109 Data = DAG.getNode(ISD::TRUNCATE, DL, ReqRetVT.changeTypeToInteger(), Data);
6110 } else {
6111 // We need to widen the return vector to a legal type
6112 if ((ReqRetVT.getVectorNumElements() % 2) == 1 &&
6113 ReqRetVT.getVectorElementType().getSizeInBits() == 16) {
6114 LegalReqRetVT =
6115 EVT::getVectorVT(*DAG.getContext(), ReqRetVT.getVectorElementType(),
6116 ReqRetVT.getVectorNumElements() + 1);
6117 }
6118 }
6119 Data = DAG.getNode(ISD::BITCAST, DL, LegalReqRetVT, Data);
6120
6121 if (IsTexFail) {
6122 TexFail =
6123 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, SDValue(Result, 0),
6124 DAG.getConstant(MaskPopDwords, DL, MVT::i32));
6125
6126 return DAG.getMergeValues({Data, TexFail, SDValue(Result, 1)}, DL);
6127 }
6128
6129 if (Result->getNumValues() == 1)
6130 return Data;
6131
6132 return DAG.getMergeValues({Data, SDValue(Result, 1)}, DL);
6133}
6134
6135static bool parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE,
6136 SDValue *LWE, bool &IsTexFail) {
6137 auto TexFailCtrlConst = cast<ConstantSDNode>(TexFailCtrl.getNode());
6138
6139 uint64_t Value = TexFailCtrlConst->getZExtValue();
6140 if (Value) {
6141 IsTexFail = true;
6142 }
6143
6144 SDLoc DL(TexFailCtrlConst);
6145 *TFE = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
6146 Value &= ~(uint64_t)0x1;
6147 *LWE = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
6148 Value &= ~(uint64_t)0x2;
6149
6150 return Value == 0;
6151}
6152
6153static void packImage16bitOpsToDwords(SelectionDAG &DAG, SDValue Op,
6154 MVT PackVectorVT,
6155 SmallVectorImpl<SDValue> &PackedAddrs,
6156 unsigned DimIdx, unsigned EndIdx,
6157 unsigned NumGradients) {
6158 SDLoc DL(Op);
6159 for (unsigned I = DimIdx; I < EndIdx; I++) {
6160 SDValue Addr = Op.getOperand(I);
6161
6162 // Gradients are packed with undef for each coordinate.
6163 // In <hi 16 bit>,<lo 16 bit> notation, the registers look like this:
6164 // 1D: undef,dx/dh; undef,dx/dv
6165 // 2D: dy/dh,dx/dh; dy/dv,dx/dv
6166 // 3D: dy/dh,dx/dh; undef,dz/dh; dy/dv,dx/dv; undef,dz/dv
6167 if (((I + 1) >= EndIdx) ||
6168 ((NumGradients / 2) % 2 == 1 && (I == DimIdx + (NumGradients / 2) - 1 ||
6169 I == DimIdx + NumGradients - 1))) {
6170 if (Addr.getValueType() != MVT::i16)
6171 Addr = DAG.getBitcast(MVT::i16, Addr);
6172 Addr = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Addr);
6173 } else {
6174 Addr = DAG.getBuildVector(PackVectorVT, DL, {Addr, Op.getOperand(I + 1)});
6175 I++;
6176 }
6177 Addr = DAG.getBitcast(MVT::f32, Addr);
6178 PackedAddrs.push_back(Addr);
6179 }
6180}
6181
6182SDValue SITargetLowering::lowerImage(SDValue Op,
6183 const AMDGPU::ImageDimIntrinsicInfo *Intr,
6184 SelectionDAG &DAG, bool WithChain) const {
6185 SDLoc DL(Op);
6186 MachineFunction &MF = DAG.getMachineFunction();
6187 const GCNSubtarget* ST = &MF.getSubtarget<GCNSubtarget>();
6188 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
6189 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
6190 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfo(Intr->Dim);
6191 const AMDGPU::MIMGLZMappingInfo *LZMappingInfo =
6192 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
6193 const AMDGPU::MIMGMIPMappingInfo *MIPMappingInfo =
6194 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
6195 unsigned IntrOpcode = Intr->BaseOpcode;
6196 bool IsGFX10Plus = AMDGPU::isGFX10Plus(*Subtarget);
6197
6198 SmallVector<EVT, 3> ResultTypes(Op->values());
6199 SmallVector<EVT, 3> OrigResultTypes(Op->values());
6200 bool IsD16 = false;
6201 bool IsG16 = false;
6202 bool IsA16 = false;
6203 SDValue VData;
6204 int NumVDataDwords;
6205 bool AdjustRetType = false;
6206
6207 // Offset of intrinsic arguments
6208 const unsigned ArgOffset = WithChain ? 2 : 1;
6209
6210 unsigned DMask;
6211 unsigned DMaskLanes = 0;
6212
6213 if (BaseOpcode->Atomic) {
6214 VData = Op.getOperand(2);
6215
6216 bool Is64Bit = VData.getValueType() == MVT::i64;
6217 if (BaseOpcode->AtomicX2) {
6218 SDValue VData2 = Op.getOperand(3);