Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1189, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SIISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -dwarf-column-info -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-11/lib/clang/11.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/include -I /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-11/lib/clang/11.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/build-llvm/lib/Target/AMDGPU -fdebug-prefix-map=/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347=. -ferror-limit 19 -fmessage-length 0 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-03-09-184146-41876-1 -x c++ /build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp

/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp

1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Custom DAG lowering for SI
11//
12//===----------------------------------------------------------------------===//
13
14#if defined(_MSC_VER) || defined(__MINGW32__)
15// Provide M_PI.
16#define _USE_MATH_DEFINES
17#endif
18
19#include "SIISelLowering.h"
20#include "AMDGPU.h"
21#include "AMDGPUSubtarget.h"
22#include "AMDGPUTargetMachine.h"
23#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24#include "SIDefines.h"
25#include "SIInstrInfo.h"
26#include "SIMachineFunctionInfo.h"
27#include "SIRegisterInfo.h"
28#include "Utils/AMDGPUBaseInfo.h"
29#include "llvm/ADT/APFloat.h"
30#include "llvm/ADT/APInt.h"
31#include "llvm/ADT/ArrayRef.h"
32#include "llvm/ADT/BitVector.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/ADT/StringRef.h"
36#include "llvm/ADT/StringSwitch.h"
37#include "llvm/ADT/Twine.h"
38#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
39#include "llvm/CodeGen/Analysis.h"
40#include "llvm/CodeGen/CallingConvLower.h"
41#include "llvm/CodeGen/DAGCombine.h"
42#include "llvm/CodeGen/ISDOpcodes.h"
43#include "llvm/CodeGen/MachineBasicBlock.h"
44#include "llvm/CodeGen/MachineFrameInfo.h"
45#include "llvm/CodeGen/MachineFunction.h"
46#include "llvm/CodeGen/MachineInstr.h"
47#include "llvm/CodeGen/MachineInstrBuilder.h"
48#include "llvm/CodeGen/MachineLoopInfo.h"
49#include "llvm/CodeGen/MachineMemOperand.h"
50#include "llvm/CodeGen/MachineModuleInfo.h"
51#include "llvm/CodeGen/MachineOperand.h"
52#include "llvm/CodeGen/MachineRegisterInfo.h"
53#include "llvm/CodeGen/SelectionDAG.h"
54#include "llvm/CodeGen/SelectionDAGNodes.h"
55#include "llvm/CodeGen/TargetCallingConv.h"
56#include "llvm/CodeGen/TargetRegisterInfo.h"
57#include "llvm/CodeGen/ValueTypes.h"
58#include "llvm/IR/Constants.h"
59#include "llvm/IR/DataLayout.h"
60#include "llvm/IR/DebugLoc.h"
61#include "llvm/IR/DerivedTypes.h"
62#include "llvm/IR/DiagnosticInfo.h"
63#include "llvm/IR/Function.h"
64#include "llvm/IR/GlobalValue.h"
65#include "llvm/IR/InstrTypes.h"
66#include "llvm/IR/Instruction.h"
67#include "llvm/IR/Instructions.h"
68#include "llvm/IR/IntrinsicInst.h"
69#include "llvm/IR/Type.h"
70#include "llvm/Support/Casting.h"
71#include "llvm/Support/CodeGen.h"
72#include "llvm/Support/CommandLine.h"
73#include "llvm/Support/Compiler.h"
74#include "llvm/Support/ErrorHandling.h"
75#include "llvm/Support/KnownBits.h"
76#include "llvm/Support/MachineValueType.h"
77#include "llvm/Support/MathExtras.h"
78#include "llvm/Target/TargetOptions.h"
79#include <cassert>
80#include <cmath>
81#include <cstdint>
82#include <iterator>
83#include <tuple>
84#include <utility>
85#include <vector>
86
87using namespace llvm;
88
89#define DEBUG_TYPE"si-lower" "si-lower"
90
91STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"si-lower", "NumTailCalls"
, "Number of tail calls"}
;
92
93static cl::opt<bool> DisableLoopAlignment(
94 "amdgpu-disable-loop-alignment",
95 cl::desc("Do not align and prefetch loops"),
96 cl::init(false));
97
98static bool hasFP32Denormals(const MachineFunction &MF) {
99 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
100 return Info->getMode().allFP32Denormals();
101}
102
103static bool hasFP64FP16Denormals(const MachineFunction &MF) {
104 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
105 return Info->getMode().allFP64FP16Denormals();
106}
107
108static unsigned findFirstFreeSGPR(CCState &CCInfo) {
109 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
110 for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
111 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
112 return AMDGPU::SGPR0 + Reg;
113 }
114 }
115 llvm_unreachable("Cannot allocate sgpr")::llvm::llvm_unreachable_internal("Cannot allocate sgpr", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 115)
;
116}
117
118SITargetLowering::SITargetLowering(const TargetMachine &TM,
119 const GCNSubtarget &STI)
120 : AMDGPUTargetLowering(TM, STI),
121 Subtarget(&STI) {
122 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
123 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
124
125 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
126 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
127
128 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
129 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
130 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
131
132 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass);
133 addRegisterClass(MVT::v3f32, &AMDGPU::VReg_96RegClass);
134
135 addRegisterClass(MVT::v2i64, &AMDGPU::SGPR_128RegClass);
136 addRegisterClass(MVT::v2f64, &AMDGPU::SGPR_128RegClass);
137
138 addRegisterClass(MVT::v4i32, &AMDGPU::SGPR_128RegClass);
139 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
140
141 addRegisterClass(MVT::v5i32, &AMDGPU::SGPR_160RegClass);
142 addRegisterClass(MVT::v5f32, &AMDGPU::VReg_160RegClass);
143
144 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
145 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
146
147 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
148 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
149
150 if (Subtarget->has16BitInsts()) {
151 addRegisterClass(MVT::i16, &AMDGPU::SReg_32RegClass);
152 addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass);
153
154 // Unless there are also VOP3P operations, not operations are really legal.
155 addRegisterClass(MVT::v2i16, &AMDGPU::SReg_32RegClass);
156 addRegisterClass(MVT::v2f16, &AMDGPU::SReg_32RegClass);
157 addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass);
158 addRegisterClass(MVT::v4f16, &AMDGPU::SReg_64RegClass);
159 }
160
161 if (Subtarget->hasMAIInsts()) {
162 addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
163 addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
164 }
165
166 computeRegisterProperties(Subtarget->getRegisterInfo());
167
168 // The boolean content concept here is too inflexible. Compares only ever
169 // really produce a 1-bit result. Any copy/extend from these will turn into a
170 // select, and zext/1 or sext/-1 are equally cheap. Arbitrarily choose 0/1, as
171 // it's what most targets use.
172 setBooleanContents(ZeroOrOneBooleanContent);
173 setBooleanVectorContents(ZeroOrOneBooleanContent);
174
175 // We need to custom lower vector stores from local memory
176 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
177 setOperationAction(ISD::LOAD, MVT::v3i32, Custom);
178 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
179 setOperationAction(ISD::LOAD, MVT::v5i32, Custom);
180 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
181 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
182 setOperationAction(ISD::LOAD, MVT::i1, Custom);
183 setOperationAction(ISD::LOAD, MVT::v32i32, Custom);
184
185 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
186 setOperationAction(ISD::STORE, MVT::v3i32, Custom);
187 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
188 setOperationAction(ISD::STORE, MVT::v5i32, Custom);
189 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
190 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
191 setOperationAction(ISD::STORE, MVT::i1, Custom);
192 setOperationAction(ISD::STORE, MVT::v32i32, Custom);
193
194 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
195 setTruncStoreAction(MVT::v3i32, MVT::v3i16, Expand);
196 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
197 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
198 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
199 setTruncStoreAction(MVT::v32i32, MVT::v32i16, Expand);
200 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Expand);
201 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Expand);
202 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Expand);
203 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
204 setTruncStoreAction(MVT::v32i32, MVT::v32i8, Expand);
205
206 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
207 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
208
209 setOperationAction(ISD::SELECT, MVT::i1, Promote);
210 setOperationAction(ISD::SELECT, MVT::i64, Custom);
211 setOperationAction(ISD::SELECT, MVT::f64, Promote);
212 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
213
214 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
215 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
216 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
217 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
218 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
219
220 setOperationAction(ISD::SETCC, MVT::i1, Promote);
221 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
222 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
223 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
224
225 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
226 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
227
228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
232 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
233 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v3i16, Custom);
234 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
236
237 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
238 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
239 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
240 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
241 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
242 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
243
244 setOperationAction(ISD::UADDO, MVT::i32, Legal);
245 setOperationAction(ISD::USUBO, MVT::i32, Legal);
246
247 setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
248 setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
249
250 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
251 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
252 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
253
254#if 0
255 setOperationAction(ISD::ADDCARRY, MVT::i64, Legal);
256 setOperationAction(ISD::SUBCARRY, MVT::i64, Legal);
257#endif
258
259 // We only support LOAD/STORE and vector manipulation ops for vectors
260 // with > 4 elements.
261 for (MVT VT : { MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32,
262 MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16,
263 MVT::v32i32, MVT::v32f32 }) {
264 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
265 switch (Op) {
266 case ISD::LOAD:
267 case ISD::STORE:
268 case ISD::BUILD_VECTOR:
269 case ISD::BITCAST:
270 case ISD::EXTRACT_VECTOR_ELT:
271 case ISD::INSERT_VECTOR_ELT:
272 case ISD::INSERT_SUBVECTOR:
273 case ISD::EXTRACT_SUBVECTOR:
274 case ISD::SCALAR_TO_VECTOR:
275 break;
276 case ISD::CONCAT_VECTORS:
277 setOperationAction(Op, VT, Custom);
278 break;
279 default:
280 setOperationAction(Op, VT, Expand);
281 break;
282 }
283 }
284 }
285
286 setOperationAction(ISD::FP_EXTEND, MVT::v4f32, Expand);
287
288 // TODO: For dynamic 64-bit vector inserts/extracts, should emit a pseudo that
289 // is expanded to avoid having two separate loops in case the index is a VGPR.
290
291 // Most operations are naturally 32-bit vector operations. We only support
292 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
293 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
294 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
295 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
296
297 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
298 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
299
300 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
301 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
302
303 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
304 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
305 }
306
307 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
308 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
309 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
310 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
311
312 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f16, Custom);
313 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
314
315 // Avoid stack access for these.
316 // TODO: Generalize to more vector types.
317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom);
318 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom);
319 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
320 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
321
322 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
323 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
324 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i8, Custom);
325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i8, Custom);
326 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i8, Custom);
327
328 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom);
329 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom);
330 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom);
331
332 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom);
333 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f16, Custom);
334 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
335 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom);
336
337 // Deal with vec3 vector operations when widened to vec4.
338 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3i32, Custom);
339 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v3f32, Custom);
340 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i32, Custom);
341 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4f32, Custom);
342
343 // Deal with vec5 vector operations when widened to vec8.
344 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5i32, Custom);
345 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v5f32, Custom);
346 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i32, Custom);
347 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8f32, Custom);
348
349 // BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
350 // and output demarshalling
351 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
352 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
353
354 // We can't return success/failure, only the old value,
355 // let LLVM add the comparison
356 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
357 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Expand);
358
359 if (Subtarget->hasFlatAddressSpace()) {
360 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
361 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
362 }
363
364 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
365
366 // FIXME: This should be narrowed to i32, but that only happens if i64 is
367 // illegal.
368 // FIXME: Should lower sub-i32 bswaps to bit-ops without v_perm_b32.
369 setOperationAction(ISD::BSWAP, MVT::i64, Legal);
370 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
371
372 // On SI this is s_memtime and s_memrealtime on VI.
373 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
374 setOperationAction(ISD::TRAP, MVT::Other, Custom);
375 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Custom);
376
377 if (Subtarget->has16BitInsts()) {
378 setOperationAction(ISD::FPOW, MVT::f16, Promote);
379 setOperationAction(ISD::FLOG, MVT::f16, Custom);
380 setOperationAction(ISD::FEXP, MVT::f16, Custom);
381 setOperationAction(ISD::FLOG10, MVT::f16, Custom);
382 }
383
384 // v_mad_f32 does not support denormals. We report it as unconditionally
385 // legal, and the context where it is formed will disallow it when fp32
386 // denormals are enabled.
387 setOperationAction(ISD::FMAD, MVT::f32, Legal);
388
389 if (!Subtarget->hasBFI()) {
390 // fcopysign can be done in a single instruction with BFI.
391 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
392 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
393 }
394
395 if (!Subtarget->hasBCNT(32))
396 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
397
398 if (!Subtarget->hasBCNT(64))
399 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
400
401 if (Subtarget->hasFFBH())
402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
403
404 if (Subtarget->hasFFBL())
405 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Custom);
406
407 // We only really have 32-bit BFE instructions (and 16-bit on VI).
408 //
409 // On SI+ there are 64-bit BFEs, but they are scalar only and there isn't any
410 // effort to match them now. We want this to be false for i64 cases when the
411 // extraction isn't restricted to the upper or lower half. Ideally we would
412 // have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
413 // span the midpoint are probably relatively rare, so don't worry about them
414 // for now.
415 if (Subtarget->hasBFE())
416 setHasExtractBitsInsn(true);
417
418 setOperationAction(ISD::FMINNUM, MVT::f32, Custom);
419 setOperationAction(ISD::FMAXNUM, MVT::f32, Custom);
420 setOperationAction(ISD::FMINNUM, MVT::f64, Custom);
421 setOperationAction(ISD::FMAXNUM, MVT::f64, Custom);
422
423
424 // These are really only legal for ieee_mode functions. We should be avoiding
425 // them for functions that don't have ieee_mode enabled, so just say they are
426 // legal.
427 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal);
428 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal);
429 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal);
430 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal);
431
432
433 if (Subtarget->haveRoundOpsF64()) {
434 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
435 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
436 setOperationAction(ISD::FRINT, MVT::f64, Legal);
437 } else {
438 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
439 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
440 setOperationAction(ISD::FRINT, MVT::f64, Custom);
441 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
442 }
443
444 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
445
446 setOperationAction(ISD::FSIN, MVT::f32, Custom);
447 setOperationAction(ISD::FCOS, MVT::f32, Custom);
448 setOperationAction(ISD::FDIV, MVT::f32, Custom);
449 setOperationAction(ISD::FDIV, MVT::f64, Custom);
450
451 if (Subtarget->has16BitInsts()) {
452 setOperationAction(ISD::Constant, MVT::i16, Legal);
453
454 setOperationAction(ISD::SMIN, MVT::i16, Legal);
455 setOperationAction(ISD::SMAX, MVT::i16, Legal);
456
457 setOperationAction(ISD::UMIN, MVT::i16, Legal);
458 setOperationAction(ISD::UMAX, MVT::i16, Legal);
459
460 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
461 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
462
463 setOperationAction(ISD::ROTR, MVT::i16, Promote);
464 setOperationAction(ISD::ROTL, MVT::i16, Promote);
465
466 setOperationAction(ISD::SDIV, MVT::i16, Promote);
467 setOperationAction(ISD::UDIV, MVT::i16, Promote);
468 setOperationAction(ISD::SREM, MVT::i16, Promote);
469 setOperationAction(ISD::UREM, MVT::i16, Promote);
470
471 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
472
473 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
475 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
477 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
478
479 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
480
481 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
482
483 setOperationAction(ISD::LOAD, MVT::i16, Custom);
484
485 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
486
487 setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote);
488 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
489 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
490 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
491
492 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
493 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
494
495 // F16 - Constant Actions.
496 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
497
498 // F16 - Load/Store Actions.
499 setOperationAction(ISD::LOAD, MVT::f16, Promote);
500 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
501 setOperationAction(ISD::STORE, MVT::f16, Promote);
502 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
503
504 // F16 - VOP1 Actions.
505 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
506 setOperationAction(ISD::FCOS, MVT::f16, Custom);
507 setOperationAction(ISD::FSIN, MVT::f16, Custom);
508
509 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
510 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Custom);
511
512 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
513 setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
514 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
515 setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
516 setOperationAction(ISD::FROUND, MVT::f16, Custom);
517
518 // F16 - VOP2 Actions.
519 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
520 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
521
522 setOperationAction(ISD::FDIV, MVT::f16, Custom);
523
524 // F16 - VOP3 Actions.
525 setOperationAction(ISD::FMA, MVT::f16, Legal);
526 if (STI.hasMadF16())
527 setOperationAction(ISD::FMAD, MVT::f16, Legal);
528
529 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) {
530 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
531 switch (Op) {
532 case ISD::LOAD:
533 case ISD::STORE:
534 case ISD::BUILD_VECTOR:
535 case ISD::BITCAST:
536 case ISD::EXTRACT_VECTOR_ELT:
537 case ISD::INSERT_VECTOR_ELT:
538 case ISD::INSERT_SUBVECTOR:
539 case ISD::EXTRACT_SUBVECTOR:
540 case ISD::SCALAR_TO_VECTOR:
541 break;
542 case ISD::CONCAT_VECTORS:
543 setOperationAction(Op, VT, Custom);
544 break;
545 default:
546 setOperationAction(Op, VT, Expand);
547 break;
548 }
549 }
550 }
551
552 // v_perm_b32 can handle either of these.
553 setOperationAction(ISD::BSWAP, MVT::i16, Legal);
554 setOperationAction(ISD::BSWAP, MVT::v2i16, Legal);
555 setOperationAction(ISD::BSWAP, MVT::v4i16, Custom);
556
557 // XXX - Do these do anything? Vector constants turn into build_vector.
558 setOperationAction(ISD::Constant, MVT::v2i16, Legal);
559 setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal);
560
561 setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);
562 setOperationAction(ISD::UNDEF, MVT::v2f16, Legal);
563
564 setOperationAction(ISD::STORE, MVT::v2i16, Promote);
565 AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
566 setOperationAction(ISD::STORE, MVT::v2f16, Promote);
567 AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32);
568
569 setOperationAction(ISD::LOAD, MVT::v2i16, Promote);
570 AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32);
571 setOperationAction(ISD::LOAD, MVT::v2f16, Promote);
572 AddPromotedToType(ISD::LOAD, MVT::v2f16, MVT::i32);
573
574 setOperationAction(ISD::AND, MVT::v2i16, Promote);
575 AddPromotedToType(ISD::AND, MVT::v2i16, MVT::i32);
576 setOperationAction(ISD::OR, MVT::v2i16, Promote);
577 AddPromotedToType(ISD::OR, MVT::v2i16, MVT::i32);
578 setOperationAction(ISD::XOR, MVT::v2i16, Promote);
579 AddPromotedToType(ISD::XOR, MVT::v2i16, MVT::i32);
580
581 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
582 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::v2i32);
583 setOperationAction(ISD::LOAD, MVT::v4f16, Promote);
584 AddPromotedToType(ISD::LOAD, MVT::v4f16, MVT::v2i32);
585
586 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
587 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
588 setOperationAction(ISD::STORE, MVT::v4f16, Promote);
589 AddPromotedToType(ISD::STORE, MVT::v4f16, MVT::v2i32);
590
591 setOperationAction(ISD::ANY_EXTEND, MVT::v2i32, Expand);
592 setOperationAction(ISD::ZERO_EXTEND, MVT::v2i32, Expand);
593 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i32, Expand);
594 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Expand);
595
596 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Expand);
597 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i32, Expand);
598 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Expand);
599
600 if (!Subtarget->hasVOP3PInsts()) {
601 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
602 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f16, Custom);
603 }
604
605 setOperationAction(ISD::FNEG, MVT::v2f16, Legal);
606 // This isn't really legal, but this avoids the legalizer unrolling it (and
607 // allows matching fneg (fabs x) patterns)
608 setOperationAction(ISD::FABS, MVT::v2f16, Legal);
609
610 setOperationAction(ISD::FMAXNUM, MVT::f16, Custom);
611 setOperationAction(ISD::FMINNUM, MVT::f16, Custom);
612 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f16, Legal);
613 setOperationAction(ISD::FMINNUM_IEEE, MVT::f16, Legal);
614
615 setOperationAction(ISD::FMINNUM_IEEE, MVT::v4f16, Custom);
616 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v4f16, Custom);
617
618 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand);
619 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Expand);
620 }
621
622 if (Subtarget->hasVOP3PInsts()) {
623 setOperationAction(ISD::ADD, MVT::v2i16, Legal);
624 setOperationAction(ISD::SUB, MVT::v2i16, Legal);
625 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
626 setOperationAction(ISD::SHL, MVT::v2i16, Legal);
627 setOperationAction(ISD::SRL, MVT::v2i16, Legal);
628 setOperationAction(ISD::SRA, MVT::v2i16, Legal);
629 setOperationAction(ISD::SMIN, MVT::v2i16, Legal);
630 setOperationAction(ISD::UMIN, MVT::v2i16, Legal);
631 setOperationAction(ISD::SMAX, MVT::v2i16, Legal);
632 setOperationAction(ISD::UMAX, MVT::v2i16, Legal);
633
634 setOperationAction(ISD::FADD, MVT::v2f16, Legal);
635 setOperationAction(ISD::FMUL, MVT::v2f16, Legal);
636 setOperationAction(ISD::FMA, MVT::v2f16, Legal);
637
638 setOperationAction(ISD::FMINNUM_IEEE, MVT::v2f16, Legal);
639 setOperationAction(ISD::FMAXNUM_IEEE, MVT::v2f16, Legal);
640
641 setOperationAction(ISD::FCANONICALIZE, MVT::v2f16, Legal);
642
643 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i16, Custom);
644 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom);
645
646 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom);
647 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
648
649 setOperationAction(ISD::SHL, MVT::v4i16, Custom);
650 setOperationAction(ISD::SRA, MVT::v4i16, Custom);
651 setOperationAction(ISD::SRL, MVT::v4i16, Custom);
652 setOperationAction(ISD::ADD, MVT::v4i16, Custom);
653 setOperationAction(ISD::SUB, MVT::v4i16, Custom);
654 setOperationAction(ISD::MUL, MVT::v4i16, Custom);
655
656 setOperationAction(ISD::SMIN, MVT::v4i16, Custom);
657 setOperationAction(ISD::SMAX, MVT::v4i16, Custom);
658 setOperationAction(ISD::UMIN, MVT::v4i16, Custom);
659 setOperationAction(ISD::UMAX, MVT::v4i16, Custom);
660
661 setOperationAction(ISD::FADD, MVT::v4f16, Custom);
662 setOperationAction(ISD::FMUL, MVT::v4f16, Custom);
663 setOperationAction(ISD::FMA, MVT::v4f16, Custom);
664
665 setOperationAction(ISD::FMAXNUM, MVT::v2f16, Custom);
666 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom);
667
668 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom);
669 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Custom);
670 setOperationAction(ISD::FCANONICALIZE, MVT::v4f16, Custom);
671
672 setOperationAction(ISD::FEXP, MVT::v2f16, Custom);
673 setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
674 setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
675 }
676
677 setOperationAction(ISD::FNEG, MVT::v4f16, Custom);
678 setOperationAction(ISD::FABS, MVT::v4f16, Custom);
679
680 if (Subtarget->has16BitInsts()) {
681 setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
682 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
683 setOperationAction(ISD::SELECT, MVT::v2f16, Promote);
684 AddPromotedToType(ISD::SELECT, MVT::v2f16, MVT::i32);
685 } else {
686 // Legalization hack.
687 setOperationAction(ISD::SELECT, MVT::v2i16, Custom);
688 setOperationAction(ISD::SELECT, MVT::v2f16, Custom);
689
690 setOperationAction(ISD::FNEG, MVT::v2f16, Custom);
691 setOperationAction(ISD::FABS, MVT::v2f16, Custom);
692 }
693
694 for (MVT VT : { MVT::v4i16, MVT::v4f16, MVT::v2i8, MVT::v4i8, MVT::v8i8 }) {
695 setOperationAction(ISD::SELECT, VT, Custom);
696 }
697
698 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
699 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
700 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
701 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
702 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f16, Custom);
703 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2i16, Custom);
704 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f16, Custom);
705
706 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2f16, Custom);
707 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v2i16, Custom);
708 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4f16, Custom);
709 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v4i16, Custom);
710 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::v8f16, Custom);
711 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
712 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::f16, Custom);
713 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i16, Custom);
714 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
715
716 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
717 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom);
718 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom);
719 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom);
720 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4i16, Custom);
721 setOperationAction(ISD::INTRINSIC_VOID, MVT::f16, Custom);
722 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
723 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
724
725 setTargetDAGCombine(ISD::ADD);
726 setTargetDAGCombine(ISD::ADDCARRY);
727 setTargetDAGCombine(ISD::SUB);
728 setTargetDAGCombine(ISD::SUBCARRY);
729 setTargetDAGCombine(ISD::FADD);
730 setTargetDAGCombine(ISD::FSUB);
731 setTargetDAGCombine(ISD::FMINNUM);
732 setTargetDAGCombine(ISD::FMAXNUM);
733 setTargetDAGCombine(ISD::FMINNUM_IEEE);
734 setTargetDAGCombine(ISD::FMAXNUM_IEEE);
735 setTargetDAGCombine(ISD::FMA);
736 setTargetDAGCombine(ISD::SMIN);
737 setTargetDAGCombine(ISD::SMAX);
738 setTargetDAGCombine(ISD::UMIN);
739 setTargetDAGCombine(ISD::UMAX);
740 setTargetDAGCombine(ISD::SETCC);
741 setTargetDAGCombine(ISD::AND);
742 setTargetDAGCombine(ISD::OR);
743 setTargetDAGCombine(ISD::XOR);
744 setTargetDAGCombine(ISD::SINT_TO_FP);
745 setTargetDAGCombine(ISD::UINT_TO_FP);
746 setTargetDAGCombine(ISD::FCANONICALIZE);
747 setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
748 setTargetDAGCombine(ISD::ZERO_EXTEND);
749 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
750 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
751 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
752
753 // All memory operations. Some folding on the pointer operand is done to help
754 // matching the constant offsets in the addressing modes.
755 setTargetDAGCombine(ISD::LOAD);
756 setTargetDAGCombine(ISD::STORE);
757 setTargetDAGCombine(ISD::ATOMIC_LOAD);
758 setTargetDAGCombine(ISD::ATOMIC_STORE);
759 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
760 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
761 setTargetDAGCombine(ISD::ATOMIC_SWAP);
762 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
763 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
764 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
765 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
766 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
767 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
768 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
769 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
770 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
771 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
772 setTargetDAGCombine(ISD::ATOMIC_LOAD_FADD);
773
774 setSchedulingPreference(Sched::RegPressure);
775}
776
777const GCNSubtarget *SITargetLowering::getSubtarget() const {
778 return Subtarget;
779}
780
781//===----------------------------------------------------------------------===//
782// TargetLowering queries
783//===----------------------------------------------------------------------===//
784
785// v_mad_mix* support a conversion from f16 to f32.
786//
787// There is only one special case when denormals are enabled we don't currently,
788// where this is OK to use.
789bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode,
790 EVT DestVT, EVT SrcVT) const {
791 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) ||
792 (Opcode == ISD::FMA && Subtarget->hasFmaMixInsts())) &&
793 DestVT.getScalarType() == MVT::f32 &&
794 SrcVT.getScalarType() == MVT::f16 &&
795 // TODO: This probably only requires no input flushing?
796 !hasFP32Denormals(DAG.getMachineFunction());
797}
798
799bool SITargetLowering::isShuffleMaskLegal(ArrayRef<int>, EVT) const {
800 // SI has some legal vector types, but no legal vector operations. Say no
801 // shuffles are legal in order to prefer scalarizing some vector operations.
802 return false;
803}
804
805MVT SITargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
806 CallingConv::ID CC,
807 EVT VT) const {
808 if (CC == CallingConv::AMDGPU_KERNEL)
809 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
810
811 if (VT.isVector()) {
812 EVT ScalarVT = VT.getScalarType();
813 unsigned Size = ScalarVT.getSizeInBits();
814 if (Size == 32)
815 return ScalarVT.getSimpleVT();
816
817 if (Size > 32)
818 return MVT::i32;
819
820 if (Size == 16 && Subtarget->has16BitInsts())
821 return VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
822 } else if (VT.getSizeInBits() > 32)
823 return MVT::i32;
824
825 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
826}
827
828unsigned SITargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
829 CallingConv::ID CC,
830 EVT VT) const {
831 if (CC == CallingConv::AMDGPU_KERNEL)
832 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
833
834 if (VT.isVector()) {
835 unsigned NumElts = VT.getVectorNumElements();
836 EVT ScalarVT = VT.getScalarType();
837 unsigned Size = ScalarVT.getSizeInBits();
838
839 if (Size == 32)
840 return NumElts;
841
842 if (Size > 32)
843 return NumElts * ((Size + 31) / 32);
844
845 if (Size == 16 && Subtarget->has16BitInsts())
846 return (NumElts + 1) / 2;
847 } else if (VT.getSizeInBits() > 32)
848 return (VT.getSizeInBits() + 31) / 32;
849
850 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
851}
852
853unsigned SITargetLowering::getVectorTypeBreakdownForCallingConv(
854 LLVMContext &Context, CallingConv::ID CC,
855 EVT VT, EVT &IntermediateVT,
856 unsigned &NumIntermediates, MVT &RegisterVT) const {
857 if (CC != CallingConv::AMDGPU_KERNEL && VT.isVector()) {
858 unsigned NumElts = VT.getVectorNumElements();
859 EVT ScalarVT = VT.getScalarType();
860 unsigned Size = ScalarVT.getSizeInBits();
861 if (Size == 32) {
862 RegisterVT = ScalarVT.getSimpleVT();
863 IntermediateVT = RegisterVT;
864 NumIntermediates = NumElts;
865 return NumIntermediates;
866 }
867
868 if (Size > 32) {
869 RegisterVT = MVT::i32;
870 IntermediateVT = RegisterVT;
871 NumIntermediates = NumElts * ((Size + 31) / 32);
872 return NumIntermediates;
873 }
874
875 // FIXME: We should fix the ABI to be the same on targets without 16-bit
876 // support, but unless we can properly handle 3-vectors, it will be still be
877 // inconsistent.
878 if (Size == 16 && Subtarget->has16BitInsts()) {
879 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16;
880 IntermediateVT = RegisterVT;
881 NumIntermediates = (NumElts + 1) / 2;
882 return NumIntermediates;
883 }
884 }
885
886 return TargetLowering::getVectorTypeBreakdownForCallingConv(
887 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
888}
889
890// Peek through TFE struct returns to only use the data size.
891static EVT memVTFromImageReturn(Type *Ty) {
892 auto *ST = dyn_cast<StructType>(Ty);
893 if (!ST)
894 return EVT::getEVT(Ty, true);
895
896 // Some intrinsics return an aggregate type - special case to work out the
897 // correct memVT.
898 //
899 // Only limited forms of aggregate type currently expected.
900 if (ST->getNumContainedTypes() != 2 ||
901 !ST->getContainedType(1)->isIntegerTy(32))
902 return EVT();
903 return EVT::getEVT(ST->getContainedType(0));
904}
905
906bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
907 const CallInst &CI,
908 MachineFunction &MF,
909 unsigned IntrID) const {
910 if (const AMDGPU::RsrcIntrinsic *RsrcIntr =
911 AMDGPU::lookupRsrcIntrinsic(IntrID)) {
912 AttributeList Attr = Intrinsic::getAttributes(CI.getContext(),
913 (Intrinsic::ID)IntrID);
914 if (Attr.hasFnAttribute(Attribute::ReadNone))
915 return false;
916
917 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
918
919 if (RsrcIntr->IsImage) {
920 Info.ptrVal = MFI->getImagePSV(
921 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
922 CI.getArgOperand(RsrcIntr->RsrcArg));
923 Info.align.reset();
924 } else {
925 Info.ptrVal = MFI->getBufferPSV(
926 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
927 CI.getArgOperand(RsrcIntr->RsrcArg));
928 }
929
930 Info.flags = MachineMemOperand::MODereferenceable;
931 if (Attr.hasFnAttribute(Attribute::ReadOnly)) {
932 Info.opc = ISD::INTRINSIC_W_CHAIN;
933 // TODO: Account for dmask reducing loaded size.
934 Info.memVT = memVTFromImageReturn(CI.getType());
935 Info.flags |= MachineMemOperand::MOLoad;
936 } else if (Attr.hasFnAttribute(Attribute::WriteOnly)) {
937 Info.opc = ISD::INTRINSIC_VOID;
938 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType());
939 Info.flags |= MachineMemOperand::MOStore;
940 } else {
941 // Atomic
942 Info.opc = ISD::INTRINSIC_W_CHAIN;
943 Info.memVT = MVT::getVT(CI.getType());
944 Info.flags = MachineMemOperand::MOLoad |
945 MachineMemOperand::MOStore |
946 MachineMemOperand::MODereferenceable;
947
948 // XXX - Should this be volatile without known ordering?
949 Info.flags |= MachineMemOperand::MOVolatile;
950 }
951 return true;
952 }
953
954 switch (IntrID) {
955 case Intrinsic::amdgcn_atomic_inc:
956 case Intrinsic::amdgcn_atomic_dec:
957 case Intrinsic::amdgcn_ds_ordered_add:
958 case Intrinsic::amdgcn_ds_ordered_swap:
959 case Intrinsic::amdgcn_ds_fadd:
960 case Intrinsic::amdgcn_ds_fmin:
961 case Intrinsic::amdgcn_ds_fmax: {
962 Info.opc = ISD::INTRINSIC_W_CHAIN;
963 Info.memVT = MVT::getVT(CI.getType());
964 Info.ptrVal = CI.getOperand(0);
965 Info.align.reset();
966 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
967
968 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(4));
969 if (!Vol->isZero())
970 Info.flags |= MachineMemOperand::MOVolatile;
971
972 return true;
973 }
974 case Intrinsic::amdgcn_buffer_atomic_fadd: {
975 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
976
977 Info.opc = ISD::INTRINSIC_VOID;
978 Info.memVT = MVT::getVT(CI.getOperand(0)->getType());
979 Info.ptrVal = MFI->getBufferPSV(
980 *MF.getSubtarget<GCNSubtarget>().getInstrInfo(),
981 CI.getArgOperand(1));
982 Info.align.reset();
983 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
984
985 const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
986 if (!Vol || !Vol->isZero())
987 Info.flags |= MachineMemOperand::MOVolatile;
988
989 return true;
990 }
991 case Intrinsic::amdgcn_global_atomic_fadd: {
992 Info.opc = ISD::INTRINSIC_VOID;
993 Info.memVT = MVT::getVT(CI.getOperand(0)->getType()
994 ->getPointerElementType());
995 Info.ptrVal = CI.getOperand(0);
996 Info.align.reset();
997 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
998
999 return true;
1000 }
1001 case Intrinsic::amdgcn_ds_append:
1002 case Intrinsic::amdgcn_ds_consume: {
1003 Info.opc = ISD::INTRINSIC_W_CHAIN;
1004 Info.memVT = MVT::getVT(CI.getType());
1005 Info.ptrVal = CI.getOperand(0);
1006 Info.align.reset();
1007 Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1008
1009 const ConstantInt *Vol = cast<ConstantInt>(CI.getOperand(1));
1010 if (!Vol->isZero())
1011 Info.flags |= MachineMemOperand::MOVolatile;
1012
1013 return true;
1014 }
1015 case Intrinsic::amdgcn_ds_gws_init:
1016 case Intrinsic::amdgcn_ds_gws_barrier:
1017 case Intrinsic::amdgcn_ds_gws_sema_v:
1018 case Intrinsic::amdgcn_ds_gws_sema_br:
1019 case Intrinsic::amdgcn_ds_gws_sema_p:
1020 case Intrinsic::amdgcn_ds_gws_sema_release_all: {
1021 Info.opc = ISD::INTRINSIC_VOID;
1022
1023 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1024 Info.ptrVal =
1025 MFI->getGWSPSV(*MF.getSubtarget<GCNSubtarget>().getInstrInfo());
1026
1027 // This is an abstract access, but we need to specify a type and size.
1028 Info.memVT = MVT::i32;
1029 Info.size = 4;
1030 Info.align = Align(4);
1031
1032 Info.flags = MachineMemOperand::MOStore;
1033 if (IntrID == Intrinsic::amdgcn_ds_gws_barrier)
1034 Info.flags = MachineMemOperand::MOLoad;
1035 return true;
1036 }
1037 default:
1038 return false;
1039 }
1040}
1041
1042bool SITargetLowering::getAddrModeArguments(IntrinsicInst *II,
1043 SmallVectorImpl<Value*> &Ops,
1044 Type *&AccessTy) const {
1045 switch (II->getIntrinsicID()) {
1046 case Intrinsic::amdgcn_atomic_inc:
1047 case Intrinsic::amdgcn_atomic_dec:
1048 case Intrinsic::amdgcn_ds_ordered_add:
1049 case Intrinsic::amdgcn_ds_ordered_swap:
1050 case Intrinsic::amdgcn_ds_fadd:
1051 case Intrinsic::amdgcn_ds_fmin:
1052 case Intrinsic::amdgcn_ds_fmax: {
1053 Value *Ptr = II->getArgOperand(0);
1054 AccessTy = II->getType();
1055 Ops.push_back(Ptr);
1056 return true;
1057 }
1058 default:
1059 return false;
1060 }
1061}
1062
1063bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
1064 if (!Subtarget->hasFlatInstOffsets()) {
1065 // Flat instructions do not have offsets, and only have the register
1066 // address.
1067 return AM.BaseOffs == 0 && AM.Scale == 0;
1068 }
1069
1070 return AM.Scale == 0 &&
1071 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset(
1072 AM.BaseOffs, AMDGPUAS::FLAT_ADDRESS,
1073 /*Signed=*/false));
1074}
1075
1076bool SITargetLowering::isLegalGlobalAddressingMode(const AddrMode &AM) const {
1077 if (Subtarget->hasFlatGlobalInsts())
1078 return AM.Scale == 0 &&
1079 (AM.BaseOffs == 0 || Subtarget->getInstrInfo()->isLegalFLATOffset(
1080 AM.BaseOffs, AMDGPUAS::GLOBAL_ADDRESS,
1081 /*Signed=*/true));
1082
1083 if (!Subtarget->hasAddr64() || Subtarget->useFlatForGlobal()) {
1084 // Assume the we will use FLAT for all global memory accesses
1085 // on VI.
1086 // FIXME: This assumption is currently wrong. On VI we still use
1087 // MUBUF instructions for the r + i addressing mode. As currently
1088 // implemented, the MUBUF instructions only work on buffer < 4GB.
1089 // It may be possible to support > 4GB buffers with MUBUF instructions,
1090 // by setting the stride value in the resource descriptor which would
1091 // increase the size limit to (stride * 4GB). However, this is risky,
1092 // because it has never been validated.
1093 return isLegalFlatAddressingMode(AM);
1094 }
1095
1096 return isLegalMUBUFAddressingMode(AM);
1097}
1098
1099bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
1100 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
1101 // additionally can do r + r + i with addr64. 32-bit has more addressing
1102 // mode options. Depending on the resource constant, it can also do
1103 // (i64 r0) + (i32 r1) * (i14 i).
1104 //
1105 // Private arrays end up using a scratch buffer most of the time, so also
1106 // assume those use MUBUF instructions. Scratch loads / stores are currently
1107 // implemented as mubuf instructions with offen bit set, so slightly
1108 // different than the normal addr64.
1109 if (!isUInt<12>(AM.BaseOffs))
1110 return false;
1111
1112 // FIXME: Since we can split immediate into soffset and immediate offset,
1113 // would it make sense to allow any immediate?
1114
1115 switch (AM.Scale) {
1116 case 0: // r + i or just i, depending on HasBaseReg.
1117 return true;
1118 case 1:
1119 return true; // We have r + r or r + i.
1120 case 2:
1121 if (AM.HasBaseReg) {
1122 // Reject 2 * r + r.
1123 return false;
1124 }
1125
1126 // Allow 2 * r as r + r
1127 // Or 2 * r + i is allowed as r + r + i.
1128 return true;
1129 default: // Don't allow n * r
1130 return false;
1131 }
1132}
1133
1134bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
1135 const AddrMode &AM, Type *Ty,
1136 unsigned AS, Instruction *I) const {
1137 // No global is ever allowed as a base.
1138 if (AM.BaseGV)
1139 return false;
1140
1141 if (AS == AMDGPUAS::GLOBAL_ADDRESS)
1142 return isLegalGlobalAddressingMode(AM);
1143
1144 if (AS == AMDGPUAS::CONSTANT_ADDRESS ||
1145 AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT ||
1146 AS == AMDGPUAS::BUFFER_FAT_POINTER) {
1147 // If the offset isn't a multiple of 4, it probably isn't going to be
1148 // correctly aligned.
1149 // FIXME: Can we get the real alignment here?
1150 if (AM.BaseOffs % 4 != 0)
1151 return isLegalMUBUFAddressingMode(AM);
1152
1153 // There are no SMRD extloads, so if we have to do a small type access we
1154 // will use a MUBUF load.
1155 // FIXME?: We also need to do this if unaligned, but we don't know the
1156 // alignment here.
1157 if (Ty->isSized() && DL.getTypeStoreSize(Ty) < 4)
1158 return isLegalGlobalAddressingMode(AM);
1159
1160 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) {
1161 // SMRD instructions have an 8-bit, dword offset on SI.
1162 if (!isUInt<8>(AM.BaseOffs / 4))
1163 return false;
1164 } else if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) {
1165 // On CI+, this can also be a 32-bit literal constant offset. If it fits
1166 // in 8-bits, it can use a smaller encoding.
1167 if (!isUInt<32>(AM.BaseOffs / 4))
1168 return false;
1169 } else if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
1170 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
1171 if (!isUInt<20>(AM.BaseOffs))
1172 return false;
1173 } else
1174 llvm_unreachable("unhandled generation")::llvm::llvm_unreachable_internal("unhandled generation", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1174)
;
1175
1176 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1177 return true;
1178
1179 if (AM.Scale == 1 && AM.HasBaseReg)
1180 return true;
1181
1182 return false;
1183
1184 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1185 return isLegalMUBUFAddressingMode(AM);
1186 } else if (AS == AMDGPUAS::LOCAL_ADDRESS ||
1187 AS == AMDGPUAS::REGION_ADDRESS) {
1188 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
1189 // field.
1190 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
1191 // an 8-bit dword offset but we don't know the alignment here.
1192 if (!isUInt<16>(AM.BaseOffs))
1193 return false;
1194
1195 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
1196 return true;
1197
1198 if (AM.Scale == 1 && AM.HasBaseReg)
1199 return true;
1200
1201 return false;
1202 } else if (AS == AMDGPUAS::FLAT_ADDRESS ||
1203 AS == AMDGPUAS::UNKNOWN_ADDRESS_SPACE) {
1204 // For an unknown address space, this usually means that this is for some
1205 // reason being used for pure arithmetic, and not based on some addressing
1206 // computation. We don't have instructions that compute pointers with any
1207 // addressing modes, so treat them as having no offset like flat
1208 // instructions.
1209 return isLegalFlatAddressingMode(AM);
1210 } else {
1211 llvm_unreachable("unhandled address space")::llvm::llvm_unreachable_internal("unhandled address space", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1211)
;
1212 }
1213}
1214
1215bool SITargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1216 const SelectionDAG &DAG) const {
1217 if (AS == AMDGPUAS::GLOBAL_ADDRESS || AS == AMDGPUAS::FLAT_ADDRESS) {
1218 return (MemVT.getSizeInBits() <= 4 * 32);
1219 } else if (AS == AMDGPUAS::PRIVATE_ADDRESS) {
1220 unsigned MaxPrivateBits = 8 * getSubtarget()->getMaxPrivateElementSize();
1221 return (MemVT.getSizeInBits() <= MaxPrivateBits);
1222 } else if (AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::REGION_ADDRESS) {
1223 return (MemVT.getSizeInBits() <= 2 * 32);
1224 }
1225 return true;
1226}
1227
1228bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
1229 unsigned Size, unsigned AddrSpace, unsigned Align,
1230 MachineMemOperand::Flags Flags, bool *IsFast) const {
1231 if (IsFast)
1232 *IsFast = false;
1233
1234 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
1235 AddrSpace == AMDGPUAS::REGION_ADDRESS) {
1236 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
1237 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
1238 // with adjacent offsets.
1239 bool AlignedBy4 = (Align % 4 == 0);
1240 if (IsFast)
1241 *IsFast = AlignedBy4;
1242
1243 return AlignedBy4;
1244 }
1245
1246 // FIXME: We have to be conservative here and assume that flat operations
1247 // will access scratch. If we had access to the IR function, then we
1248 // could determine if any private memory was used in the function.
1249 if (!Subtarget->hasUnalignedScratchAccess() &&
1250 (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
1251 AddrSpace == AMDGPUAS::FLAT_ADDRESS)) {
1252 bool AlignedBy4 = Align >= 4;
1253 if (IsFast)
1254 *IsFast = AlignedBy4;
1255
1256 return AlignedBy4;
1257 }
1258
1259 if (Subtarget->hasUnalignedBufferAccess()) {
1260 // If we have an uniform constant load, it still requires using a slow
1261 // buffer instruction if unaligned.
1262 if (IsFast) {
1263 // Accesses can really be issued as 1-byte aligned or 4-byte aligned, so
1264 // 2-byte alignment is worse than 1 unless doing a 2-byte accesss.
1265 *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS ||
1266 AddrSpace == AMDGPUAS::CONSTANT_ADDRESS_32BIT) ?
1267 Align >= 4 : Align != 2;
1268 }
1269
1270 return true;
1271 }
1272
1273 // Smaller than dword value must be aligned.
1274 if (Size < 32)
1275 return false;
1276
1277 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
1278 // byte-address are ignored, thus forcing Dword alignment.
1279 // This applies to private, global, and constant memory.
1280 if (IsFast)
1281 *IsFast = true;
1282
1283 return Size >= 32 && Align >= 4;
1284}
1285
1286bool SITargetLowering::allowsMisalignedMemoryAccesses(
1287 EVT VT, unsigned AddrSpace, unsigned Align, MachineMemOperand::Flags Flags,
1288 bool *IsFast) const {
1289 if (IsFast)
1290 *IsFast = false;
1291
1292 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
1293 // which isn't a simple VT.
1294 // Until MVT is extended to handle this, simply check for the size and
1295 // rely on the condition below: allow accesses if the size is a multiple of 4.
1296 if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
1297 VT.getStoreSize() > 16)) {
1298 return false;
1299 }
1300
1301 return allowsMisalignedMemoryAccessesImpl(VT.getSizeInBits(), AddrSpace,
1302 Align, Flags, IsFast);
1303}
1304
1305EVT SITargetLowering::getOptimalMemOpType(
1306 const MemOp &Op, const AttributeList &FuncAttributes) const {
1307 // FIXME: Should account for address space here.
1308
1309 // The default fallback uses the private pointer size as a guess for a type to
1310 // use. Make sure we switch these to 64-bit accesses.
1311
1312 if (Op.size() >= 16 &&
1313 Op.isDstAligned(Align(4))) // XXX: Should only do for global
1314 return MVT::v4i32;
1315
1316 if (Op.size() >= 8 && Op.isDstAligned(Align(4)))
1317 return MVT::v2i32;
1318
1319 // Use the default.
1320 return MVT::Other;
1321}
1322
1323bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1324 unsigned DestAS) const {
1325 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
1326}
1327
1328bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {
1329 const MemSDNode *MemNode = cast<MemSDNode>(N);
1330 const Value *Ptr = MemNode->getMemOperand()->getValue();
1331 const Instruction *I = dyn_cast_or_null<Instruction>(Ptr);
1332 return I && I->getMetadata("amdgpu.noclobber");
1333}
1334
1335bool SITargetLowering::isFreeAddrSpaceCast(unsigned SrcAS,
1336 unsigned DestAS) const {
1337 // Flat -> private/local is a simple truncate.
1338 // Flat -> global is no-op
1339 if (SrcAS == AMDGPUAS::FLAT_ADDRESS)
1340 return true;
1341
1342 return isNoopAddrSpaceCast(SrcAS, DestAS);
1343}
1344
1345bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
1346 const MemSDNode *MemNode = cast<MemSDNode>(N);
1347
1348 return AMDGPUInstrInfo::isUniformMMO(MemNode->getMemOperand());
1349}
1350
1351TargetLoweringBase::LegalizeTypeAction
1352SITargetLowering::getPreferredVectorAction(MVT VT) const {
1353 int NumElts = VT.getVectorNumElements();
1354 if (NumElts != 1 && VT.getScalarType().bitsLE(MVT::i16))
1355 return VT.isPow2VectorType() ? TypeSplitVector : TypeWidenVector;
1356 return TargetLoweringBase::getPreferredVectorAction(VT);
1357}
1358
1359bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
1360 Type *Ty) const {
1361 // FIXME: Could be smarter if called for vector constants.
1362 return true;
1363}
1364
1365bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
1366 if (Subtarget->has16BitInsts() && VT == MVT::i16) {
1367 switch (Op) {
1368 case ISD::LOAD:
1369 case ISD::STORE:
1370
1371 // These operations are done with 32-bit instructions anyway.
1372 case ISD::AND:
1373 case ISD::OR:
1374 case ISD::XOR:
1375 case ISD::SELECT:
1376 // TODO: Extensions?
1377 return true;
1378 default:
1379 return false;
1380 }
1381 }
1382
1383 // SimplifySetCC uses this function to determine whether or not it should
1384 // create setcc with i1 operands. We don't have instructions for i1 setcc.
1385 if (VT == MVT::i1 && Op == ISD::SETCC)
1386 return false;
1387
1388 return TargetLowering::isTypeDesirableForOp(Op, VT);
1389}
1390
1391SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG,
1392 const SDLoc &SL,
1393 SDValue Chain,
1394 uint64_t Offset) const {
1395 const DataLayout &DL = DAG.getDataLayout();
1396 MachineFunction &MF = DAG.getMachineFunction();
1397 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1398
1399 const ArgDescriptor *InputPtrReg;
1400 const TargetRegisterClass *RC;
1401
1402 std::tie(InputPtrReg, RC)
1403 = Info->getPreloadedValue(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
1404
1405 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1406 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
1407 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
1408 MRI.getLiveInVirtReg(InputPtrReg->getRegister()), PtrVT);
1409
1410 return DAG.getObjectPtrOffset(SL, BasePtr, Offset);
1411}
1412
1413SDValue SITargetLowering::getImplicitArgPtr(SelectionDAG &DAG,
1414 const SDLoc &SL) const {
1415 uint64_t Offset = getImplicitParameterOffset(DAG.getMachineFunction(),
1416 FIRST_IMPLICIT);
1417 return lowerKernArgParameterPtr(DAG, SL, DAG.getEntryNode(), Offset);
1418}
1419
1420SDValue SITargetLowering::convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT,
1421 const SDLoc &SL, SDValue Val,
1422 bool Signed,
1423 const ISD::InputArg *Arg) const {
1424 // First, if it is a widened vector, narrow it.
1425 if (VT.isVector() &&
1426 VT.getVectorNumElements() != MemVT.getVectorNumElements()) {
1427 EVT NarrowedVT =
1428 EVT::getVectorVT(*DAG.getContext(), MemVT.getVectorElementType(),
1429 VT.getVectorNumElements());
1430 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val,
1431 DAG.getConstant(0, SL, MVT::i32));
1432 }
1433
1434 // Then convert the vector elements or scalar value.
1435 if (Arg && (Arg->Flags.isSExt() || Arg->Flags.isZExt()) &&
1436 VT.bitsLT(MemVT)) {
1437 unsigned Opc = Arg->Flags.isZExt() ? ISD::AssertZext : ISD::AssertSext;
1438 Val = DAG.getNode(Opc, SL, MemVT, Val, DAG.getValueType(VT));
1439 }
1440
1441 if (MemVT.isFloatingPoint())
1442 Val = getFPExtOrFPTrunc(DAG, Val, SL, VT);
1443 else if (Signed)
1444 Val = DAG.getSExtOrTrunc(Val, SL, VT);
1445 else
1446 Val = DAG.getZExtOrTrunc(Val, SL, VT);
1447
1448 return Val;
1449}
1450
1451SDValue SITargetLowering::lowerKernargMemParameter(
1452 SelectionDAG &DAG, EVT VT, EVT MemVT,
1453 const SDLoc &SL, SDValue Chain,
1454 uint64_t Offset, unsigned Align, bool Signed,
1455 const ISD::InputArg *Arg) const {
1456 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
1457
1458 // Try to avoid using an extload by loading earlier than the argument address,
1459 // and extracting the relevant bits. The load should hopefully be merged with
1460 // the previous argument.
1461 if (MemVT.getStoreSize() < 4 && Align < 4) {
1462 // TODO: Handle align < 4 and size >= 4 (can happen with packed structs).
1463 int64_t AlignDownOffset = alignDown(Offset, 4);
1464 int64_t OffsetDiff = Offset - AlignDownOffset;
1465
1466 EVT IntVT = MemVT.changeTypeToInteger();
1467
1468 // TODO: If we passed in the base kernel offset we could have a better
1469 // alignment than 4, but we don't really need it.
1470 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, AlignDownOffset);
1471 SDValue Load = DAG.getLoad(MVT::i32, SL, Chain, Ptr, PtrInfo, 4,
1472 MachineMemOperand::MODereferenceable |
1473 MachineMemOperand::MOInvariant);
1474
1475 SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
1476 SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
1477
1478 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract);
1479 ArgVal = DAG.getNode(ISD::BITCAST, SL, MemVT, ArgVal);
1480 ArgVal = convertArgType(DAG, VT, MemVT, SL, ArgVal, Signed, Arg);
1481
1482
1483 return DAG.getMergeValues({ ArgVal, Load.getValue(1) }, SL);
1484 }
1485
1486 SDValue Ptr = lowerKernArgParameterPtr(DAG, SL, Chain, Offset);
1487 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Align,
1488 MachineMemOperand::MODereferenceable |
1489 MachineMemOperand::MOInvariant);
1490
1491 SDValue Val = convertArgType(DAG, VT, MemVT, SL, Load, Signed, Arg);
1492 return DAG.getMergeValues({ Val, Load.getValue(1) }, SL);
1493}
1494
1495SDValue SITargetLowering::lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
1496 const SDLoc &SL, SDValue Chain,
1497 const ISD::InputArg &Arg) const {
1498 MachineFunction &MF = DAG.getMachineFunction();
1499 MachineFrameInfo &MFI = MF.getFrameInfo();
1500
1501 if (Arg.Flags.isByVal()) {
1502 unsigned Size = Arg.Flags.getByValSize();
1503 int FrameIdx = MFI.CreateFixedObject(Size, VA.getLocMemOffset(), false);
1504 return DAG.getFrameIndex(FrameIdx, MVT::i32);
1505 }
1506
1507 unsigned ArgOffset = VA.getLocMemOffset();
1508 unsigned ArgSize = VA.getValVT().getStoreSize();
1509
1510 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset, true);
1511
1512 // Create load nodes to retrieve arguments from the stack.
1513 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1514 SDValue ArgValue;
1515
1516 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1517 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1518 MVT MemVT = VA.getValVT();
1519
1520 switch (VA.getLocInfo()) {
1521 default:
1522 break;
1523 case CCValAssign::BCvt:
1524 MemVT = VA.getLocVT();
1525 break;
1526 case CCValAssign::SExt:
1527 ExtType = ISD::SEXTLOAD;
1528 break;
1529 case CCValAssign::ZExt:
1530 ExtType = ISD::ZEXTLOAD;
1531 break;
1532 case CCValAssign::AExt:
1533 ExtType = ISD::EXTLOAD;
1534 break;
1535 }
1536
1537 ArgValue = DAG.getExtLoad(
1538 ExtType, SL, VA.getLocVT(), Chain, FIN,
1539 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
1540 MemVT);
1541 return ArgValue;
1542}
1543
1544SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG,
1545 const SIMachineFunctionInfo &MFI,
1546 EVT VT,
1547 AMDGPUFunctionArgInfo::PreloadedValue PVID) const {
1548 const ArgDescriptor *Reg;
1549 const TargetRegisterClass *RC;
1550
1551 std::tie(Reg, RC) = MFI.getPreloadedValue(PVID);
1552 return CreateLiveInRegister(DAG, RC, Reg->getRegister(), VT);
1553}
1554
1555static void processShaderInputArgs(SmallVectorImpl<ISD::InputArg> &Splits,
1556 CallingConv::ID CallConv,
1557 ArrayRef<ISD::InputArg> Ins,
1558 BitVector &Skipped,
1559 FunctionType *FType,
1560 SIMachineFunctionInfo *Info) {
1561 for (unsigned I = 0, E = Ins.size(), PSInputNum = 0; I != E; ++I) {
1562 const ISD::InputArg *Arg = &Ins[I];
1563
1564 assert((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) &&(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "vector type argument should have been split"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1565, __PRETTY_FUNCTION__))
1565 "vector type argument should have been split")(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "vector type argument should have been split"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"vector type argument should have been split\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1565, __PRETTY_FUNCTION__))
;
1566
1567 // First check if it's a PS input addr.
1568 if (CallConv == CallingConv::AMDGPU_PS &&
1569 !Arg->Flags.isInReg() && PSInputNum <= 15) {
1570 bool SkipArg = !Arg->Used && !Info->isPSInputAllocated(PSInputNum);
1571
1572 // Inconveniently only the first part of the split is marked as isSplit,
1573 // so skip to the end. We only want to increment PSInputNum once for the
1574 // entire split argument.
1575 if (Arg->Flags.isSplit()) {
1576 while (!Arg->Flags.isSplitEnd()) {
1577 assert((!Arg->VT.isVector() ||(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1579, __PRETTY_FUNCTION__))
1578 Arg->VT.getScalarSizeInBits() == 16) &&(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1579, __PRETTY_FUNCTION__))
1579 "unexpected vector split in ps argument type")(((!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits()
== 16) && "unexpected vector split in ps argument type"
) ? static_cast<void> (0) : __assert_fail ("(!Arg->VT.isVector() || Arg->VT.getScalarSizeInBits() == 16) && \"unexpected vector split in ps argument type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1579, __PRETTY_FUNCTION__))
;
1580 if (!SkipArg)
1581 Splits.push_back(*Arg);
1582 Arg = &Ins[++I];
1583 }
1584 }
1585
1586 if (SkipArg) {
1587 // We can safely skip PS inputs.
1588 Skipped.set(Arg->getOrigArgIndex());
1589 ++PSInputNum;
1590 continue;
1591 }
1592
1593 Info->markPSInputAllocated(PSInputNum);
1594 if (Arg->Used)
1595 Info->markPSInputEnabled(PSInputNum);
1596
1597 ++PSInputNum;
1598 }
1599
1600 Splits.push_back(*Arg);
1601 }
1602}
1603
1604// Allocate special inputs passed in VGPRs.
1605void SITargetLowering::allocateSpecialEntryInputVGPRs(CCState &CCInfo,
1606 MachineFunction &MF,
1607 const SIRegisterInfo &TRI,
1608 SIMachineFunctionInfo &Info) const {
1609 const LLT S32 = LLT::scalar(32);
1610 MachineRegisterInfo &MRI = MF.getRegInfo();
1611
1612 if (Info.hasWorkItemIDX()) {
1613 Register Reg = AMDGPU::VGPR0;
1614 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1615
1616 CCInfo.AllocateReg(Reg);
1617 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg));
1618 }
1619
1620 if (Info.hasWorkItemIDY()) {
1621 Register Reg = AMDGPU::VGPR1;
1622 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1623
1624 CCInfo.AllocateReg(Reg);
1625 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg));
1626 }
1627
1628 if (Info.hasWorkItemIDZ()) {
1629 Register Reg = AMDGPU::VGPR2;
1630 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32);
1631
1632 CCInfo.AllocateReg(Reg);
1633 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg));
1634 }
1635}
1636
1637// Try to allocate a VGPR at the end of the argument list, or if no argument
1638// VGPRs are left allocating a stack slot.
1639// If \p Mask is is given it indicates bitfield position in the register.
1640// If \p Arg is given use it with new ]p Mask instead of allocating new.
1641static ArgDescriptor allocateVGPR32Input(CCState &CCInfo, unsigned Mask = ~0u,
1642 ArgDescriptor Arg = ArgDescriptor()) {
1643 if (Arg.isSet())
1644 return ArgDescriptor::createArg(Arg, Mask);
1645
1646 ArrayRef<MCPhysReg> ArgVGPRs
1647 = makeArrayRef(AMDGPU::VGPR_32RegClass.begin(), 32);
1648 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs);
1649 if (RegIdx == ArgVGPRs.size()) {
1650 // Spill to stack required.
1651 int64_t Offset = CCInfo.AllocateStack(4, 4);
1652
1653 return ArgDescriptor::createStack(Offset, Mask);
1654 }
1655
1656 unsigned Reg = ArgVGPRs[RegIdx];
1657 Reg = CCInfo.AllocateReg(Reg);
1658 assert(Reg != AMDGPU::NoRegister)((Reg != AMDGPU::NoRegister) ? static_cast<void> (0) : __assert_fail
("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1658, __PRETTY_FUNCTION__))
;
1659
1660 MachineFunction &MF = CCInfo.getMachineFunction();
1661 Register LiveInVReg = MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1662 MF.getRegInfo().setType(LiveInVReg, LLT::scalar(32));
1663 return ArgDescriptor::createRegister(Reg, Mask);
1664}
1665
1666static ArgDescriptor allocateSGPR32InputImpl(CCState &CCInfo,
1667 const TargetRegisterClass *RC,
1668 unsigned NumArgRegs) {
1669 ArrayRef<MCPhysReg> ArgSGPRs = makeArrayRef(RC->begin(), 32);
1670 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs);
1671 if (RegIdx == ArgSGPRs.size())
1672 report_fatal_error("ran out of SGPRs for arguments");
1673
1674 unsigned Reg = ArgSGPRs[RegIdx];
1675 Reg = CCInfo.AllocateReg(Reg);
1676 assert(Reg != AMDGPU::NoRegister)((Reg != AMDGPU::NoRegister) ? static_cast<void> (0) : __assert_fail
("Reg != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1676, __PRETTY_FUNCTION__))
;
1677
1678 MachineFunction &MF = CCInfo.getMachineFunction();
1679 MF.addLiveIn(Reg, RC);
1680 return ArgDescriptor::createRegister(Reg);
1681}
1682
1683static ArgDescriptor allocateSGPR32Input(CCState &CCInfo) {
1684 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_32RegClass, 32);
1685}
1686
1687static ArgDescriptor allocateSGPR64Input(CCState &CCInfo) {
1688 return allocateSGPR32InputImpl(CCInfo, &AMDGPU::SGPR_64RegClass, 16);
1689}
1690
1691void SITargetLowering::allocateSpecialInputVGPRs(CCState &CCInfo,
1692 MachineFunction &MF,
1693 const SIRegisterInfo &TRI,
1694 SIMachineFunctionInfo &Info) const {
1695 const unsigned Mask = 0x3ff;
1696 ArgDescriptor Arg;
1697
1698 if (Info.hasWorkItemIDX()) {
1699 Arg = allocateVGPR32Input(CCInfo, Mask);
1700 Info.setWorkItemIDX(Arg);
1701 }
1702
1703 if (Info.hasWorkItemIDY()) {
1704 Arg = allocateVGPR32Input(CCInfo, Mask << 10, Arg);
1705 Info.setWorkItemIDY(Arg);
1706 }
1707
1708 if (Info.hasWorkItemIDZ())
1709 Info.setWorkItemIDZ(allocateVGPR32Input(CCInfo, Mask << 20, Arg));
1710}
1711
1712void SITargetLowering::allocateSpecialInputSGPRs(
1713 CCState &CCInfo,
1714 MachineFunction &MF,
1715 const SIRegisterInfo &TRI,
1716 SIMachineFunctionInfo &Info) const {
1717 auto &ArgInfo = Info.getArgInfo();
1718
1719 // TODO: Unify handling with private memory pointers.
1720
1721 if (Info.hasDispatchPtr())
1722 ArgInfo.DispatchPtr = allocateSGPR64Input(CCInfo);
1723
1724 if (Info.hasQueuePtr())
1725 ArgInfo.QueuePtr = allocateSGPR64Input(CCInfo);
1726
1727 if (Info.hasKernargSegmentPtr())
1728 ArgInfo.KernargSegmentPtr = allocateSGPR64Input(CCInfo);
1729
1730 if (Info.hasDispatchID())
1731 ArgInfo.DispatchID = allocateSGPR64Input(CCInfo);
1732
1733 // flat_scratch_init is not applicable for non-kernel functions.
1734
1735 if (Info.hasWorkGroupIDX())
1736 ArgInfo.WorkGroupIDX = allocateSGPR32Input(CCInfo);
1737
1738 if (Info.hasWorkGroupIDY())
1739 ArgInfo.WorkGroupIDY = allocateSGPR32Input(CCInfo);
1740
1741 if (Info.hasWorkGroupIDZ())
1742 ArgInfo.WorkGroupIDZ = allocateSGPR32Input(CCInfo);
1743
1744 if (Info.hasImplicitArgPtr())
1745 ArgInfo.ImplicitArgPtr = allocateSGPR64Input(CCInfo);
1746}
1747
1748// Allocate special inputs passed in user SGPRs.
1749void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
1750 MachineFunction &MF,
1751 const SIRegisterInfo &TRI,
1752 SIMachineFunctionInfo &Info) const {
1753 if (Info.hasImplicitBufferPtr()) {
1754 unsigned ImplicitBufferPtrReg = Info.addImplicitBufferPtr(TRI);
1755 MF.addLiveIn(ImplicitBufferPtrReg, &AMDGPU::SGPR_64RegClass);
1756 CCInfo.AllocateReg(ImplicitBufferPtrReg);
1757 }
1758
1759 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
1760 if (Info.hasPrivateSegmentBuffer()) {
1761 unsigned PrivateSegmentBufferReg = Info.addPrivateSegmentBuffer(TRI);
1762 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SGPR_128RegClass);
1763 CCInfo.AllocateReg(PrivateSegmentBufferReg);
1764 }
1765
1766 if (Info.hasDispatchPtr()) {
1767 unsigned DispatchPtrReg = Info.addDispatchPtr(TRI);
1768 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
1769 CCInfo.AllocateReg(DispatchPtrReg);
1770 }
1771
1772 if (Info.hasQueuePtr()) {
1773 unsigned QueuePtrReg = Info.addQueuePtr(TRI);
1774 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
1775 CCInfo.AllocateReg(QueuePtrReg);
1776 }
1777
1778 if (Info.hasKernargSegmentPtr()) {
1779 MachineRegisterInfo &MRI = MF.getRegInfo();
1780 Register InputPtrReg = Info.addKernargSegmentPtr(TRI);
1781 CCInfo.AllocateReg(InputPtrReg);
1782
1783 Register VReg = MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
1784 MRI.setType(VReg, LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
1785 }
1786
1787 if (Info.hasDispatchID()) {
1788 unsigned DispatchIDReg = Info.addDispatchID(TRI);
1789 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
1790 CCInfo.AllocateReg(DispatchIDReg);
1791 }
1792
1793 if (Info.hasFlatScratchInit()) {
1794 unsigned FlatScratchInitReg = Info.addFlatScratchInit(TRI);
1795 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
1796 CCInfo.AllocateReg(FlatScratchInitReg);
1797 }
1798
1799 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
1800 // these from the dispatch pointer.
1801}
1802
1803// Allocate special input registers that are initialized per-wave.
1804void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,
1805 MachineFunction &MF,
1806 SIMachineFunctionInfo &Info,
1807 CallingConv::ID CallConv,
1808 bool IsShader) const {
1809 if (Info.hasWorkGroupIDX()) {
1810 unsigned Reg = Info.addWorkGroupIDX();
1811 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1812 CCInfo.AllocateReg(Reg);
1813 }
1814
1815 if (Info.hasWorkGroupIDY()) {
1816 unsigned Reg = Info.addWorkGroupIDY();
1817 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1818 CCInfo.AllocateReg(Reg);
1819 }
1820
1821 if (Info.hasWorkGroupIDZ()) {
1822 unsigned Reg = Info.addWorkGroupIDZ();
1823 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1824 CCInfo.AllocateReg(Reg);
1825 }
1826
1827 if (Info.hasWorkGroupInfo()) {
1828 unsigned Reg = Info.addWorkGroupInfo();
1829 MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
1830 CCInfo.AllocateReg(Reg);
1831 }
1832
1833 if (Info.hasPrivateSegmentWaveByteOffset()) {
1834 // Scratch wave offset passed in system SGPR.
1835 unsigned PrivateSegmentWaveByteOffsetReg;
1836
1837 if (IsShader) {
1838 PrivateSegmentWaveByteOffsetReg =
1839 Info.getPrivateSegmentWaveByteOffsetSystemSGPR();
1840
1841 // This is true if the scratch wave byte offset doesn't have a fixed
1842 // location.
1843 if (PrivateSegmentWaveByteOffsetReg == AMDGPU::NoRegister) {
1844 PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
1845 Info.setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
1846 }
1847 } else
1848 PrivateSegmentWaveByteOffsetReg = Info.addPrivateSegmentWaveByteOffset();
1849
1850 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
1851 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
1852 }
1853}
1854
1855static void reservePrivateMemoryRegs(const TargetMachine &TM,
1856 MachineFunction &MF,
1857 const SIRegisterInfo &TRI,
1858 SIMachineFunctionInfo &Info) {
1859 // Now that we've figured out where the scratch register inputs are, see if
1860 // should reserve the arguments and use them directly.
1861 MachineFrameInfo &MFI = MF.getFrameInfo();
1862 bool HasStackObjects = MFI.hasStackObjects();
1863 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
1864
1865 // Record that we know we have non-spill stack objects so we don't need to
1866 // check all stack objects later.
1867 if (HasStackObjects)
1868 Info.setHasNonSpillStackObjects(true);
1869
1870 // Everything live out of a block is spilled with fast regalloc, so it's
1871 // almost certain that spilling will be required.
1872 if (TM.getOptLevel() == CodeGenOpt::None)
1873 HasStackObjects = true;
1874
1875 // For now assume stack access is needed in any callee functions, so we need
1876 // the scratch registers to pass in.
1877 bool RequiresStackAccess = HasStackObjects || MFI.hasCalls();
1878
1879 if (RequiresStackAccess && ST.isAmdHsaOrMesa(MF.getFunction())) {
1880 // If we have stack objects, we unquestionably need the private buffer
1881 // resource. For the Code Object V2 ABI, this will be the first 4 user
1882 // SGPR inputs. We can reserve those and use them directly.
1883
1884 Register PrivateSegmentBufferReg =
1885 Info.getPreloadedReg(AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER);
1886 Info.setScratchRSrcReg(PrivateSegmentBufferReg);
1887 } else {
1888 unsigned ReservedBufferReg = TRI.reservedPrivateSegmentBufferReg(MF);
1889 // We tentatively reserve the last registers (skipping the last registers
1890 // which may contain VCC, FLAT_SCR, and XNACK). After register allocation,
1891 // we'll replace these with the ones immediately after those which were
1892 // really allocated. In the prologue copies will be inserted from the
1893 // argument to these reserved registers.
1894
1895 // Without HSA, relocations are used for the scratch pointer and the
1896 // buffer resource setup is always inserted in the prologue. Scratch wave
1897 // offset is still in an input SGPR.
1898 Info.setScratchRSrcReg(ReservedBufferReg);
1899 }
1900
1901 // hasFP should be accurate for kernels even before the frame is finalized.
1902 if (ST.getFrameLowering()->hasFP(MF)) {
1903 MachineRegisterInfo &MRI = MF.getRegInfo();
1904
1905 // Try to use s32 as the SP, but move it if it would interfere with input
1906 // arguments. This won't work with calls though.
1907 //
1908 // FIXME: Move SP to avoid any possible inputs, or find a way to spill input
1909 // registers.
1910 if (!MRI.isLiveIn(AMDGPU::SGPR32)) {
1911 Info.setStackPtrOffsetReg(AMDGPU::SGPR32);
1912 } else {
1913 assert(AMDGPU::isShader(MF.getFunction().getCallingConv()))((AMDGPU::isShader(MF.getFunction().getCallingConv())) ? static_cast
<void> (0) : __assert_fail ("AMDGPU::isShader(MF.getFunction().getCallingConv())"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1913, __PRETTY_FUNCTION__))
;
1914
1915 if (MFI.hasCalls())
1916 report_fatal_error("call in graphics shader with too many input SGPRs");
1917
1918 for (unsigned Reg : AMDGPU::SGPR_32RegClass) {
1919 if (!MRI.isLiveIn(Reg)) {
1920 Info.setStackPtrOffsetReg(Reg);
1921 break;
1922 }
1923 }
1924
1925 if (Info.getStackPtrOffsetReg() == AMDGPU::SP_REG)
1926 report_fatal_error("failed to find register for SP");
1927 }
1928
1929 if (MFI.hasCalls()) {
1930 Info.setScratchWaveOffsetReg(AMDGPU::SGPR33);
1931 Info.setFrameOffsetReg(AMDGPU::SGPR33);
1932 } else {
1933 unsigned ReservedOffsetReg =
1934 TRI.reservedPrivateSegmentWaveByteOffsetReg(MF);
1935 Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1936 Info.setFrameOffsetReg(ReservedOffsetReg);
1937 }
1938 } else if (RequiresStackAccess) {
1939 assert(!MFI.hasCalls())((!MFI.hasCalls()) ? static_cast<void> (0) : __assert_fail
("!MFI.hasCalls()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1939, __PRETTY_FUNCTION__))
;
1940 // We know there are accesses and they will be done relative to SP, so just
1941 // pin it to the input.
1942 //
1943 // FIXME: Should not do this if inline asm is reading/writing these
1944 // registers.
1945 Register PreloadedSP = Info.getPreloadedReg(
1946 AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
1947
1948 Info.setStackPtrOffsetReg(PreloadedSP);
1949 Info.setScratchWaveOffsetReg(PreloadedSP);
1950 Info.setFrameOffsetReg(PreloadedSP);
1951 } else {
1952 assert(!MFI.hasCalls())((!MFI.hasCalls()) ? static_cast<void> (0) : __assert_fail
("!MFI.hasCalls()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1952, __PRETTY_FUNCTION__))
;
1953
1954 // There may not be stack access at all. There may still be spills, or
1955 // access of a constant pointer (in which cases an extra copy will be
1956 // emitted in the prolog).
1957 unsigned ReservedOffsetReg
1958 = TRI.reservedPrivateSegmentWaveByteOffsetReg(MF);
1959 Info.setStackPtrOffsetReg(ReservedOffsetReg);
1960 Info.setScratchWaveOffsetReg(ReservedOffsetReg);
1961 Info.setFrameOffsetReg(ReservedOffsetReg);
1962 }
1963}
1964
1965bool SITargetLowering::supportSplitCSR(MachineFunction *MF) const {
1966 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
1967 return !Info->isEntryFunction();
1968}
1969
1970void SITargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
1971
1972}
1973
1974void SITargetLowering::insertCopiesSplitCSR(
1975 MachineBasicBlock *Entry,
1976 const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
1977 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
1978
1979 const MCPhysReg *IStart = TRI->getCalleeSavedRegsViaCopy(Entry->getParent());
1980 if (!IStart)
1981 return;
1982
1983 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1984 MachineRegisterInfo *MRI = &Entry->getParent()->getRegInfo();
1985 MachineBasicBlock::iterator MBBI = Entry->begin();
1986 for (const MCPhysReg *I = IStart; *I; ++I) {
1987 const TargetRegisterClass *RC = nullptr;
1988 if (AMDGPU::SReg_64RegClass.contains(*I))
1989 RC = &AMDGPU::SGPR_64RegClass;
1990 else if (AMDGPU::SReg_32RegClass.contains(*I))
1991 RC = &AMDGPU::SGPR_32RegClass;
1992 else
1993 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 1993)
;
1994
1995 Register NewVR = MRI->createVirtualRegister(RC);
1996 // Create copy from CSR to a virtual register.
1997 Entry->addLiveIn(*I);
1998 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
1999 .addReg(*I);
2000
2001 // Insert the copy-back instructions right before the terminator.
2002 for (auto *Exit : Exits)
2003 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
2004 TII->get(TargetOpcode::COPY), *I)
2005 .addReg(NewVR);
2006 }
2007}
2008
2009SDValue SITargetLowering::LowerFormalArguments(
2010 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2011 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2012 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2013 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2014
2015 MachineFunction &MF = DAG.getMachineFunction();
2016 const Function &Fn = MF.getFunction();
2017 FunctionType *FType = MF.getFunction().getFunctionType();
2018 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2019
2020 if (Subtarget->isAmdHsaOS() && AMDGPU::isShader(CallConv)) {
2021 DiagnosticInfoUnsupported NoGraphicsHSA(
2022 Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
2023 DAG.getContext()->diagnose(NoGraphicsHSA);
2024 return DAG.getEntryNode();
2025 }
2026
2027 SmallVector<ISD::InputArg, 16> Splits;
2028 SmallVector<CCValAssign, 16> ArgLocs;
2029 BitVector Skipped(Ins.size());
2030 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2031 *DAG.getContext());
2032
2033 bool IsShader = AMDGPU::isShader(CallConv);
2034 bool IsKernel = AMDGPU::isKernel(CallConv);
2035 bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CallConv);
2036
2037 if (IsShader) {
2038 processShaderInputArgs(Splits, CallConv, Ins, Skipped, FType, Info);
2039
2040 // At least one interpolation mode must be enabled or else the GPU will
2041 // hang.
2042 //
2043 // Check PSInputAddr instead of PSInputEnable. The idea is that if the user
2044 // set PSInputAddr, the user wants to enable some bits after the compilation
2045 // based on run-time states. Since we can't know what the final PSInputEna
2046 // will look like, so we shouldn't do anything here and the user should take
2047 // responsibility for the correct programming.
2048 //
2049 // Otherwise, the following restrictions apply:
2050 // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
2051 // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
2052 // enabled too.
2053 if (CallConv == CallingConv::AMDGPU_PS) {
2054 if ((Info->getPSInputAddr() & 0x7F) == 0 ||
2055 ((Info->getPSInputAddr() & 0xF) == 0 &&
2056 Info->isPSInputAllocated(11))) {
2057 CCInfo.AllocateReg(AMDGPU::VGPR0);
2058 CCInfo.AllocateReg(AMDGPU::VGPR1);
2059 Info->markPSInputAllocated(0);
2060 Info->markPSInputEnabled(0);
2061 }
2062 if (Subtarget->isAmdPalOS()) {
2063 // For isAmdPalOS, the user does not enable some bits after compilation
2064 // based on run-time states; the register values being generated here are
2065 // the final ones set in hardware. Therefore we need to apply the
2066 // workaround to PSInputAddr and PSInputEnable together. (The case where
2067 // a bit is set in PSInputAddr but not PSInputEnable is where the
2068 // frontend set up an input arg for a particular interpolation mode, but
2069 // nothing uses that input arg. Really we should have an earlier pass
2070 // that removes such an arg.)
2071 unsigned PsInputBits = Info->getPSInputAddr() & Info->getPSInputEnable();
2072 if ((PsInputBits & 0x7F) == 0 ||
2073 ((PsInputBits & 0xF) == 0 &&
2074 (PsInputBits >> 11 & 1)))
2075 Info->markPSInputEnabled(
2076 countTrailingZeros(Info->getPSInputAddr(), ZB_Undefined));
2077 }
2078 }
2079
2080 assert(!Info->hasDispatchPtr() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2085, __PRETTY_FUNCTION__))
2081 !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2085, __PRETTY_FUNCTION__))
2082 !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2085, __PRETTY_FUNCTION__))
2083 !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2085, __PRETTY_FUNCTION__))
2084 !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2085, __PRETTY_FUNCTION__))
2085 !Info->hasWorkItemIDZ())((!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr
() && !Info->hasFlatScratchInit() && !Info
->hasWorkGroupIDX() && !Info->hasWorkGroupIDY()
&& !Info->hasWorkGroupIDZ() && !Info->
hasWorkGroupInfo() && !Info->hasWorkItemIDX() &&
!Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ
()) ? static_cast<void> (0) : __assert_fail ("!Info->hasDispatchPtr() && !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() && !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() && !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() && !Info->hasWorkItemIDZ()"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2085, __PRETTY_FUNCTION__))
;
2086 } else if (IsKernel) {
2087 assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX())((Info->hasWorkGroupIDX() && Info->hasWorkItemIDX
()) ? static_cast<void> (0) : __assert_fail ("Info->hasWorkGroupIDX() && Info->hasWorkItemIDX()"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2087, __PRETTY_FUNCTION__))
;
2088 } else {
2089 Splits.append(Ins.begin(), Ins.end());
2090 }
2091
2092 if (IsEntryFunc) {
2093 allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
2094 allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
2095 }
2096
2097 if (IsKernel) {
2098 analyzeFormalArgumentsCompute(CCInfo, Ins);
2099 } else {
2100 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg);
2101 CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
2102 }
2103
2104 SmallVector<SDValue, 16> Chains;
2105
2106 // FIXME: This is the minimum kernel argument alignment. We should improve
2107 // this to the maximum alignment of the arguments.
2108 //
2109 // FIXME: Alignment of explicit arguments totally broken with non-0 explicit
2110 // kern arg offset.
2111 const unsigned KernelArgBaseAlign = 16;
2112
2113 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
2114 const ISD::InputArg &Arg = Ins[i];
2115 if (Arg.isOrigArg() && Skipped[Arg.getOrigArgIndex()]) {
2116 InVals.push_back(DAG.getUNDEF(Arg.VT));
2117 continue;
2118 }
2119
2120 CCValAssign &VA = ArgLocs[ArgIdx++];
2121 MVT VT = VA.getLocVT();
2122
2123 if (IsEntryFunc && VA.isMemLoc()) {
2124 VT = Ins[i].VT;
2125 EVT MemVT = VA.getLocVT();
2126
2127 const uint64_t Offset = VA.getLocMemOffset();
2128 unsigned Align = MinAlign(KernelArgBaseAlign, Offset);
2129
2130 SDValue Arg = lowerKernargMemParameter(
2131 DAG, VT, MemVT, DL, Chain, Offset, Align, Ins[i].Flags.isSExt(), &Ins[i]);
2132 Chains.push_back(Arg.getValue(1));
2133
2134 auto *ParamTy =
2135 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
2136 if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
2137 ParamTy && (ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
2138 ParamTy->getAddressSpace() == AMDGPUAS::REGION_ADDRESS)) {
2139 // On SI local pointers are just offsets into LDS, so they are always
2140 // less than 16-bits. On CI and newer they could potentially be
2141 // real pointers, so we can't guarantee their size.
2142 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
2143 DAG.getValueType(MVT::i16));
2144 }
2145
2146 InVals.push_back(Arg);
2147 continue;
2148 } else if (!IsEntryFunc && VA.isMemLoc()) {
2149 SDValue Val = lowerStackParameter(DAG, VA, DL, Chain, Arg);
2150 InVals.push_back(Val);
2151 if (!Arg.Flags.isByVal())
2152 Chains.push_back(Val.getValue(1));
2153 continue;
2154 }
2155
2156 assert(VA.isRegLoc() && "Parameter must be in a register!")((VA.isRegLoc() && "Parameter must be in a register!"
) ? static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Parameter must be in a register!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2156, __PRETTY_FUNCTION__))
;
2157
2158 Register Reg = VA.getLocReg();
2159 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2160 EVT ValVT = VA.getValVT();
2161
2162 Reg = MF.addLiveIn(Reg, RC);
2163 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
2164
2165 if (Arg.Flags.isSRet()) {
2166 // The return object should be reasonably addressable.
2167
2168 // FIXME: This helps when the return is a real sret. If it is a
2169 // automatically inserted sret (i.e. CanLowerReturn returns false), an
2170 // extra copy is inserted in SelectionDAGBuilder which obscures this.
2171 unsigned NumBits
2172 = 32 - getSubtarget()->getKnownHighZeroBitsForFrameIndex();
2173 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2174 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), NumBits)));
2175 }
2176
2177 // If this is an 8 or 16-bit value, it is really passed promoted
2178 // to 32 bits. Insert an assert[sz]ext to capture this, then
2179 // truncate to the right size.
2180 switch (VA.getLocInfo()) {
2181 case CCValAssign::Full:
2182 break;
2183 case CCValAssign::BCvt:
2184 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2185 break;
2186 case CCValAssign::SExt:
2187 Val = DAG.getNode(ISD::AssertSext, DL, VT, Val,
2188 DAG.getValueType(ValVT));
2189 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2190 break;
2191 case CCValAssign::ZExt:
2192 Val = DAG.getNode(ISD::AssertZext, DL, VT, Val,
2193 DAG.getValueType(ValVT));
2194 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2195 break;
2196 case CCValAssign::AExt:
2197 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2198 break;
2199 default:
2200 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2200)
;
2201 }
2202
2203 InVals.push_back(Val);
2204 }
2205
2206 if (!IsEntryFunc) {
2207 // Special inputs come after user arguments.
2208 allocateSpecialInputVGPRs(CCInfo, MF, *TRI, *Info);
2209 }
2210
2211 // Start adding system SGPRs.
2212 if (IsEntryFunc) {
2213 allocateSystemSGPRs(CCInfo, MF, *Info, CallConv, IsShader);
2214 } else {
2215 CCInfo.AllocateReg(Info->getScratchRSrcReg());
2216 CCInfo.AllocateReg(Info->getScratchWaveOffsetReg());
2217 CCInfo.AllocateReg(Info->getFrameOffsetReg());
2218 allocateSpecialInputSGPRs(CCInfo, MF, *TRI, *Info);
2219 }
2220
2221 auto &ArgUsageInfo =
2222 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2223 ArgUsageInfo.setFuncArgInfo(Fn, Info->getArgInfo());
2224
2225 unsigned StackArgSize = CCInfo.getNextStackOffset();
2226 Info->setBytesInStackArgArea(StackArgSize);
2227
2228 return Chains.empty() ? Chain :
2229 DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
2230}
2231
2232// TODO: If return values can't fit in registers, we should return as many as
2233// possible in registers before passing on stack.
2234bool SITargetLowering::CanLowerReturn(
2235 CallingConv::ID CallConv,
2236 MachineFunction &MF, bool IsVarArg,
2237 const SmallVectorImpl<ISD::OutputArg> &Outs,
2238 LLVMContext &Context) const {
2239 // Replacing returns with sret/stack usage doesn't make sense for shaders.
2240 // FIXME: Also sort of a workaround for custom vector splitting in LowerReturn
2241 // for shaders. Vector types should be explicitly handled by CC.
2242 if (AMDGPU::isEntryFunctionCC(CallConv))
2243 return true;
2244
2245 SmallVector<CCValAssign, 16> RVLocs;
2246 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
2247 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, IsVarArg));
2248}
2249
2250SDValue
2251SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2252 bool isVarArg,
2253 const SmallVectorImpl<ISD::OutputArg> &Outs,
2254 const SmallVectorImpl<SDValue> &OutVals,
2255 const SDLoc &DL, SelectionDAG &DAG) const {
2256 MachineFunction &MF = DAG.getMachineFunction();
2257 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2258
2259 if (AMDGPU::isKernel(CallConv)) {
2260 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
2261 OutVals, DL, DAG);
2262 }
2263
2264 bool IsShader = AMDGPU::isShader(CallConv);
2265
2266 Info->setIfReturnsVoid(Outs.empty());
2267 bool IsWaveEnd = Info->returnsVoid() && IsShader;
2268
2269 // CCValAssign - represent the assignment of the return value to a location.
2270 SmallVector<CCValAssign, 48> RVLocs;
2271 SmallVector<ISD::OutputArg, 48> Splits;
2272
2273 // CCState - Info about the registers and stack slots.
2274 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2275 *DAG.getContext());
2276
2277 // Analyze outgoing return values.
2278 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2279
2280 SDValue Flag;
2281 SmallVector<SDValue, 48> RetOps;
2282 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2283
2284 // Add return address for callable functions.
2285 if (!Info->isEntryFunction()) {
2286 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2287 SDValue ReturnAddrReg = CreateLiveInRegister(
2288 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2289
2290 SDValue ReturnAddrVirtualReg = DAG.getRegister(
2291 MF.getRegInfo().createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass),
2292 MVT::i64);
2293 Chain =
2294 DAG.getCopyToReg(Chain, DL, ReturnAddrVirtualReg, ReturnAddrReg, Flag);
2295 Flag = Chain.getValue(1);
2296 RetOps.push_back(ReturnAddrVirtualReg);
2297 }
2298
2299 // Copy the result values into the output registers.
2300 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E;
2301 ++I, ++RealRVLocIdx) {
2302 CCValAssign &VA = RVLocs[I];
2303 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2303, __PRETTY_FUNCTION__))
;
2304 // TODO: Partially return in registers if return values don't fit.
2305 SDValue Arg = OutVals[RealRVLocIdx];
2306
2307 // Copied from other backends.
2308 switch (VA.getLocInfo()) {
2309 case CCValAssign::Full:
2310 break;
2311 case CCValAssign::BCvt:
2312 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2313 break;
2314 case CCValAssign::SExt:
2315 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2316 break;
2317 case CCValAssign::ZExt:
2318 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2319 break;
2320 case CCValAssign::AExt:
2321 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2322 break;
2323 default:
2324 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2324)
;
2325 }
2326
2327 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2328 Flag = Chain.getValue(1);
2329 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2330 }
2331
2332 // FIXME: Does sret work properly?
2333 if (!Info->isEntryFunction()) {
2334 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2335 const MCPhysReg *I =
2336 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2337 if (I) {
2338 for (; *I; ++I) {
2339 if (AMDGPU::SReg_64RegClass.contains(*I))
2340 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
2341 else if (AMDGPU::SReg_32RegClass.contains(*I))
2342 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2343 else
2344 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2344)
;
2345 }
2346 }
2347 }
2348
2349 // Update chain and glue.
2350 RetOps[0] = Chain;
2351 if (Flag.getNode())
2352 RetOps.push_back(Flag);
2353
2354 unsigned Opc = AMDGPUISD::ENDPGM;
2355 if (!IsWaveEnd)
2356 Opc = IsShader ? AMDGPUISD::RETURN_TO_EPILOG : AMDGPUISD::RET_FLAG;
2357 return DAG.getNode(Opc, DL, MVT::Other, RetOps);
2358}
2359
2360SDValue SITargetLowering::LowerCallResult(
2361 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2362 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2363 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool IsThisReturn,
2364 SDValue ThisVal) const {
2365 CCAssignFn *RetCC = CCAssignFnForReturn(CallConv, IsVarArg);
2366
2367 // Assign locations to each value returned by this call.
2368 SmallVector<CCValAssign, 16> RVLocs;
2369 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2370 *DAG.getContext());
2371 CCInfo.AnalyzeCallResult(Ins, RetCC);
2372
2373 // Copy all of the result registers out of their specified physreg.
2374 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2375 CCValAssign VA = RVLocs[i];
2376 SDValue Val;
2377
2378 if (VA.isRegLoc()) {
2379 Val = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2380 Chain = Val.getValue(1);
2381 InFlag = Val.getValue(2);
2382 } else if (VA.isMemLoc()) {
2383 report_fatal_error("TODO: return values in memory");
2384 } else
2385 llvm_unreachable("unknown argument location type")::llvm::llvm_unreachable_internal("unknown argument location type"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2385)
;
2386
2387 switch (VA.getLocInfo()) {
2388 case CCValAssign::Full:
2389 break;
2390 case CCValAssign::BCvt:
2391 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2392 break;
2393 case CCValAssign::ZExt:
2394 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2395 DAG.getValueType(VA.getValVT()));
2396 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2397 break;
2398 case CCValAssign::SExt:
2399 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2400 DAG.getValueType(VA.getValVT()));
2401 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2402 break;
2403 case CCValAssign::AExt:
2404 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2405 break;
2406 default:
2407 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2407)
;
2408 }
2409
2410 InVals.push_back(Val);
2411 }
2412
2413 return Chain;
2414}
2415
2416// Add code to pass special inputs required depending on used features separate
2417// from the explicit user arguments present in the IR.
2418void SITargetLowering::passSpecialInputs(
2419 CallLoweringInfo &CLI,
2420 CCState &CCInfo,
2421 const SIMachineFunctionInfo &Info,
2422 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
2423 SmallVectorImpl<SDValue> &MemOpChains,
2424 SDValue Chain) const {
2425 // If we don't have a call site, this was a call inserted by
2426 // legalization. These can never use special inputs.
2427 if (!CLI.CS)
2428 return;
2429
2430 const Function *CalleeFunc = CLI.CS.getCalledFunction();
2431 assert(CalleeFunc)((CalleeFunc) ? static_cast<void> (0) : __assert_fail (
"CalleeFunc", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2431, __PRETTY_FUNCTION__))
;
2432
2433 SelectionDAG &DAG = CLI.DAG;
2434 const SDLoc &DL = CLI.DL;
2435
2436 const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
2437
2438 auto &ArgUsageInfo =
2439 DAG.getPass()->getAnalysis<AMDGPUArgumentUsageInfo>();
2440 const AMDGPUFunctionArgInfo &CalleeArgInfo
2441 = ArgUsageInfo.lookupFuncArgInfo(*CalleeFunc);
2442
2443 const AMDGPUFunctionArgInfo &CallerArgInfo = Info.getArgInfo();
2444
2445 // TODO: Unify with private memory register handling. This is complicated by
2446 // the fact that at least in kernels, the input argument is not necessarily
2447 // in the same location as the input.
2448 AMDGPUFunctionArgInfo::PreloadedValue InputRegs[] = {
2449 AMDGPUFunctionArgInfo::DISPATCH_PTR,
2450 AMDGPUFunctionArgInfo::QUEUE_PTR,
2451 AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR,
2452 AMDGPUFunctionArgInfo::DISPATCH_ID,
2453 AMDGPUFunctionArgInfo::WORKGROUP_ID_X,
2454 AMDGPUFunctionArgInfo::WORKGROUP_ID_Y,
2455 AMDGPUFunctionArgInfo::WORKGROUP_ID_Z,
2456 AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR
2457 };
2458
2459 for (auto InputID : InputRegs) {
2460 const ArgDescriptor *OutgoingArg;
2461 const TargetRegisterClass *ArgRC;
2462
2463 std::tie(OutgoingArg, ArgRC) = CalleeArgInfo.getPreloadedValue(InputID);
2464 if (!OutgoingArg)
2465 continue;
2466
2467 const ArgDescriptor *IncomingArg;
2468 const TargetRegisterClass *IncomingArgRC;
2469 std::tie(IncomingArg, IncomingArgRC)
2470 = CallerArgInfo.getPreloadedValue(InputID);
2471 assert(IncomingArgRC == ArgRC)((IncomingArgRC == ArgRC) ? static_cast<void> (0) : __assert_fail
("IncomingArgRC == ArgRC", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2471, __PRETTY_FUNCTION__))
;
2472
2473 // All special arguments are ints for now.
2474 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32;
2475 SDValue InputReg;
2476
2477 if (IncomingArg) {
2478 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg);
2479 } else {
2480 // The implicit arg ptr is special because it doesn't have a corresponding
2481 // input for kernels, and is computed from the kernarg segment pointer.
2482 assert(InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR)((InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR) ? static_cast
<void> (0) : __assert_fail ("InputID == AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2482, __PRETTY_FUNCTION__))
;
2483 InputReg = getImplicitArgPtr(DAG, DL);
2484 }
2485
2486 if (OutgoingArg->isRegister()) {
2487 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2488 } else {
2489 unsigned SpecialArgOffset = CCInfo.AllocateStack(ArgVT.getStoreSize(), 4);
2490 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2491 SpecialArgOffset);
2492 MemOpChains.push_back(ArgStore);
2493 }
2494 }
2495
2496 // Pack workitem IDs into a single register or pass it as is if already
2497 // packed.
2498 const ArgDescriptor *OutgoingArg;
2499 const TargetRegisterClass *ArgRC;
2500
2501 std::tie(OutgoingArg, ArgRC) =
2502 CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X);
2503 if (!OutgoingArg)
2504 std::tie(OutgoingArg, ArgRC) =
2505 CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y);
2506 if (!OutgoingArg)
2507 std::tie(OutgoingArg, ArgRC) =
2508 CalleeArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
2509 if (!OutgoingArg)
2510 return;
2511
2512 const ArgDescriptor *IncomingArgX
2513 = CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_X).first;
2514 const ArgDescriptor *IncomingArgY
2515 = CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Y).first;
2516 const ArgDescriptor *IncomingArgZ
2517 = CallerArgInfo.getPreloadedValue(AMDGPUFunctionArgInfo::WORKITEM_ID_Z).first;
2518
2519 SDValue InputReg;
2520 SDLoc SL;
2521
2522 // If incoming ids are not packed we need to pack them.
2523 if (IncomingArgX && !IncomingArgX->isMasked() && CalleeArgInfo.WorkItemIDX)
2524 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX);
2525
2526 if (IncomingArgY && !IncomingArgY->isMasked() && CalleeArgInfo.WorkItemIDY) {
2527 SDValue Y = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgY);
2528 Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y,
2529 DAG.getShiftAmountConstant(10, MVT::i32, SL));
2530 InputReg = InputReg.getNode() ?
2531 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Y) : Y;
2532 }
2533
2534 if (IncomingArgZ && !IncomingArgZ->isMasked() && CalleeArgInfo.WorkItemIDZ) {
2535 SDValue Z = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgZ);
2536 Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z,
2537 DAG.getShiftAmountConstant(20, MVT::i32, SL));
2538 InputReg = InputReg.getNode() ?
2539 DAG.getNode(ISD::OR, SL, MVT::i32, InputReg, Z) : Z;
2540 }
2541
2542 if (!InputReg.getNode()) {
2543 // Workitem ids are already packed, any of present incoming arguments
2544 // will carry all required fields.
2545 ArgDescriptor IncomingArg = ArgDescriptor::createArg(
2546 IncomingArgX ? *IncomingArgX :
2547 IncomingArgY ? *IncomingArgY :
2548 *IncomingArgZ, ~0u);
2549 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, IncomingArg);
2550 }
2551
2552 if (OutgoingArg->isRegister()) {
2553 RegsToPass.emplace_back(OutgoingArg->getRegister(), InputReg);
2554 } else {
2555 unsigned SpecialArgOffset = CCInfo.AllocateStack(4, 4);
2556 SDValue ArgStore = storeStackInputValue(DAG, DL, Chain, InputReg,
2557 SpecialArgOffset);
2558 MemOpChains.push_back(ArgStore);
2559 }
2560}
2561
2562static bool canGuaranteeTCO(CallingConv::ID CC) {
2563 return CC == CallingConv::Fast;
2564}
2565
2566/// Return true if we might ever do TCO for calls with this calling convention.
2567static bool mayTailCallThisCC(CallingConv::ID CC) {
2568 switch (CC) {
2569 case CallingConv::C:
2570 return true;
2571 default:
2572 return canGuaranteeTCO(CC);
2573 }
2574}
2575
2576bool SITargetLowering::isEligibleForTailCallOptimization(
2577 SDValue Callee, CallingConv::ID CalleeCC, bool IsVarArg,
2578 const SmallVectorImpl<ISD::OutputArg> &Outs,
2579 const SmallVectorImpl<SDValue> &OutVals,
2580 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2581 if (!mayTailCallThisCC(CalleeCC))
2582 return false;
2583
2584 MachineFunction &MF = DAG.getMachineFunction();
2585 const Function &CallerF = MF.getFunction();
2586 CallingConv::ID CallerCC = CallerF.getCallingConv();
2587 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2588 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2589
2590 // Kernels aren't callable, and don't have a live in return address so it
2591 // doesn't make sense to do a tail call with entry functions.
2592 if (!CallerPreserved)
2593 return false;
2594
2595 bool CCMatch = CallerCC == CalleeCC;
2596
2597 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
2598 if (canGuaranteeTCO(CalleeCC) && CCMatch)
2599 return true;
2600 return false;
2601 }
2602
2603 // TODO: Can we handle var args?
2604 if (IsVarArg)
2605 return false;
2606
2607 for (const Argument &Arg : CallerF.args()) {
2608 if (Arg.hasByValAttr())
2609 return false;
2610 }
2611
2612 LLVMContext &Ctx = *DAG.getContext();
2613
2614 // Check that the call results are passed in the same way.
2615 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, Ctx, Ins,
2616 CCAssignFnForCall(CalleeCC, IsVarArg),
2617 CCAssignFnForCall(CallerCC, IsVarArg)))
2618 return false;
2619
2620 // The callee has to preserve all registers the caller needs to preserve.
2621 if (!CCMatch) {
2622 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2623 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2624 return false;
2625 }
2626
2627 // Nothing more to check if the callee is taking no arguments.
2628 if (Outs.empty())
2629 return true;
2630
2631 SmallVector<CCValAssign, 16> ArgLocs;
2632 CCState CCInfo(CalleeCC, IsVarArg, MF, ArgLocs, Ctx);
2633
2634 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, IsVarArg));
2635
2636 const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
2637 // If the stack arguments for this call do not fit into our own save area then
2638 // the call cannot be made tail.
2639 // TODO: Is this really necessary?
2640 if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
2641 return false;
2642
2643 const MachineRegisterInfo &MRI = MF.getRegInfo();
2644 return parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals);
2645}
2646
2647bool SITargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2648 if (!CI->isTailCall())
2649 return false;
2650
2651 const Function *ParentFn = CI->getParent()->getParent();
2652 if (AMDGPU::isEntryFunctionCC(ParentFn->getCallingConv()))
2653 return false;
2654 return true;
2655}
2656
2657// The wave scratch offset register is used as the global base pointer.
2658SDValue SITargetLowering::LowerCall(CallLoweringInfo &CLI,
2659 SmallVectorImpl<SDValue> &InVals) const {
2660 SelectionDAG &DAG = CLI.DAG;
2661 const SDLoc &DL = CLI.DL;
2662 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2663 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2664 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2665 SDValue Chain = CLI.Chain;
2666 SDValue Callee = CLI.Callee;
2667 bool &IsTailCall = CLI.IsTailCall;
2668 CallingConv::ID CallConv = CLI.CallConv;
2669 bool IsVarArg = CLI.IsVarArg;
2670 bool IsSibCall = false;
2671 bool IsThisReturn = false;
2672 MachineFunction &MF = DAG.getMachineFunction();
2673
2674 if (Callee.isUndef() || isNullConstant(Callee)) {
2675 if (!CLI.IsTailCall) {
2676 for (unsigned I = 0, E = CLI.Ins.size(); I != E; ++I)
2677 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT));
2678 }
2679
2680 return Chain;
2681 }
2682
2683 if (IsVarArg) {
2684 return lowerUnhandledCall(CLI, InVals,
2685 "unsupported call to variadic function ");
2686 }
2687
2688 if (!CLI.CS.getInstruction())
2689 report_fatal_error("unsupported libcall legalization");
2690
2691 if (!CLI.CS.getCalledFunction()) {
2692 return lowerUnhandledCall(CLI, InVals,
2693 "unsupported indirect call to function ");
2694 }
2695
2696 if (IsTailCall && MF.getTarget().Options.GuaranteedTailCallOpt) {
2697 return lowerUnhandledCall(CLI, InVals,
2698 "unsupported required tail call to function ");
2699 }
2700
2701 if (AMDGPU::isShader(MF.getFunction().getCallingConv())) {
2702 // Note the issue is with the CC of the calling function, not of the call
2703 // itself.
2704 return lowerUnhandledCall(CLI, InVals,
2705 "unsupported call from graphics shader of function ");
2706 }
2707
2708 if (IsTailCall) {
2709 IsTailCall = isEligibleForTailCallOptimization(
2710 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
2711 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall()) {
2712 report_fatal_error("failed to perform tail call elimination on a call "
2713 "site marked musttail");
2714 }
2715
2716 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2717
2718 // A sibling call is one where we're under the usual C ABI and not planning
2719 // to change that but can still do a tail call:
2720 if (!TailCallOpt && IsTailCall)
2721 IsSibCall = true;
2722
2723 if (IsTailCall)
2724 ++NumTailCalls;
2725 }
2726
2727 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
2728
2729 // Analyze operands of the call, assigning locations to each operand.
2730 SmallVector<CCValAssign, 16> ArgLocs;
2731 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
2732 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, IsVarArg);
2733
2734 CCInfo.AnalyzeCallOperands(Outs, AssignFn);
2735
2736 // Get a count of how many bytes are to be pushed on the stack.
2737 unsigned NumBytes = CCInfo.getNextStackOffset();
2738
2739 if (IsSibCall) {
2740 // Since we're not changing the ABI to make this a tail call, the memory
2741 // operands are already available in the caller's incoming argument space.
2742 NumBytes = 0;
2743 }
2744
2745 // FPDiff is the byte offset of the call's argument area from the callee's.
2746 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2747 // by this amount for a tail call. In a sibling call it must be 0 because the
2748 // caller will deallocate the entire stack and the callee still expects its
2749 // arguments to begin at SP+0. Completely unused for non-tail calls.
2750 int32_t FPDiff = 0;
2751 MachineFrameInfo &MFI = MF.getFrameInfo();
2752 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2753
2754 // Adjust the stack pointer for the new arguments...
2755 // These operations are automatically eliminated by the prolog/epilog pass
2756 if (!IsSibCall) {
2757 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
2758
2759 SmallVector<SDValue, 4> CopyFromChains;
2760
2761 // In the HSA case, this should be an identity copy.
2762 SDValue ScratchRSrcReg
2763 = DAG.getCopyFromReg(Chain, DL, Info->getScratchRSrcReg(), MVT::v4i32);
2764 RegsToPass.emplace_back(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
2765 CopyFromChains.push_back(ScratchRSrcReg.getValue(1));
2766 Chain = DAG.getTokenFactor(DL, CopyFromChains);
2767 }
2768
2769 SmallVector<SDValue, 8> MemOpChains;
2770 MVT PtrVT = MVT::i32;
2771
2772 // Walk the register/memloc assignments, inserting copies/loads.
2773 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2774 CCValAssign &VA = ArgLocs[i];
2775 SDValue Arg = OutVals[i];
2776
2777 // Promote the value if needed.
2778 switch (VA.getLocInfo()) {
2779 case CCValAssign::Full:
2780 break;
2781 case CCValAssign::BCvt:
2782 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2783 break;
2784 case CCValAssign::ZExt:
2785 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2786 break;
2787 case CCValAssign::SExt:
2788 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2789 break;
2790 case CCValAssign::AExt:
2791 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2792 break;
2793 case CCValAssign::FPExt:
2794 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2795 break;
2796 default:
2797 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2797)
;
2798 }
2799
2800 if (VA.isRegLoc()) {
2801 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2802 } else {
2803 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2803, __PRETTY_FUNCTION__))
;
2804
2805 SDValue DstAddr;
2806 MachinePointerInfo DstInfo;
2807
2808 unsigned LocMemOffset = VA.getLocMemOffset();
2809 int32_t Offset = LocMemOffset;
2810
2811 SDValue PtrOff = DAG.getConstant(Offset, DL, PtrVT);
2812 MaybeAlign Alignment;
2813
2814 if (IsTailCall) {
2815 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2816 unsigned OpSize = Flags.isByVal() ?
2817 Flags.getByValSize() : VA.getValVT().getStoreSize();
2818
2819 // FIXME: We can have better than the minimum byval required alignment.
2820 Alignment =
2821 Flags.isByVal()
2822 ? Flags.getNonZeroByValAlign()
2823 : commonAlignment(Subtarget->getStackAlignment(), Offset);
2824
2825 Offset = Offset + FPDiff;
2826 int FI = MFI.CreateFixedObject(OpSize, Offset, true);
2827
2828 DstAddr = DAG.getFrameIndex(FI, PtrVT);
2829 DstInfo = MachinePointerInfo::getFixedStack(MF, FI);
2830
2831 // Make sure any stack arguments overlapping with where we're storing
2832 // are loaded before this eventual operation. Otherwise they'll be
2833 // clobbered.
2834
2835 // FIXME: Why is this really necessary? This seems to just result in a
2836 // lot of code to copy the stack and write them back to the same
2837 // locations, which are supposed to be immutable?
2838 Chain = addTokenForArgument(Chain, DAG, MFI, FI);
2839 } else {
2840 DstAddr = PtrOff;
2841 DstInfo = MachinePointerInfo::getStack(MF, LocMemOffset);
2842 Alignment =
2843 commonAlignment(Subtarget->getStackAlignment(), LocMemOffset);
2844 }
2845
2846 if (Outs[i].Flags.isByVal()) {
2847 SDValue SizeNode =
2848 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i32);
2849 SDValue Cpy =
2850 DAG.getMemcpy(Chain, DL, DstAddr, Arg, SizeNode,
2851 Outs[i].Flags.getNonZeroByValAlign(),
2852 /*isVol = */ false, /*AlwaysInline = */ true,
2853 /*isTailCall = */ false, DstInfo,
2854 MachinePointerInfo(AMDGPUAS::PRIVATE_ADDRESS));
2855
2856 MemOpChains.push_back(Cpy);
2857 } else {
2858 SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo,
2859 Alignment ? Alignment->value() : 0);
2860 MemOpChains.push_back(Store);
2861 }
2862 }
2863 }
2864
2865 // Copy special input registers after user input arguments.
2866 passSpecialInputs(CLI, CCInfo, *Info, RegsToPass, MemOpChains, Chain);
2867
2868 if (!MemOpChains.empty())
2869 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2870
2871 // Build a sequence of copy-to-reg nodes chained together with token chain
2872 // and flag operands which copy the outgoing args into the appropriate regs.
2873 SDValue InFlag;
2874 for (auto &RegToPass : RegsToPass) {
2875 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
2876 RegToPass.second, InFlag);
2877 InFlag = Chain.getValue(1);
2878 }
2879
2880
2881 SDValue PhysReturnAddrReg;
2882 if (IsTailCall) {
2883 // Since the return is being combined with the call, we need to pass on the
2884 // return address.
2885
2886 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
2887 SDValue ReturnAddrReg = CreateLiveInRegister(
2888 DAG, &AMDGPU::SReg_64RegClass, TRI->getReturnAddressReg(MF), MVT::i64);
2889
2890 PhysReturnAddrReg = DAG.getRegister(TRI->getReturnAddressReg(MF),
2891 MVT::i64);
2892 Chain = DAG.getCopyToReg(Chain, DL, PhysReturnAddrReg, ReturnAddrReg, InFlag);
2893 InFlag = Chain.getValue(1);
2894 }
2895
2896 // We don't usually want to end the call-sequence here because we would tidy
2897 // the frame up *after* the call, however in the ABI-changing tail-call case
2898 // we've carefully laid out the parameters so that when sp is reset they'll be
2899 // in the correct location.
2900 if (IsTailCall && !IsSibCall) {
2901 Chain = DAG.getCALLSEQ_END(Chain,
2902 DAG.getTargetConstant(NumBytes, DL, MVT::i32),
2903 DAG.getTargetConstant(0, DL, MVT::i32),
2904 InFlag, DL);
2905 InFlag = Chain.getValue(1);
2906 }
2907
2908 std::vector<SDValue> Ops;
2909 Ops.push_back(Chain);
2910 Ops.push_back(Callee);
2911 // Add a redundant copy of the callee global which will not be legalized, as
2912 // we need direct access to the callee later.
2913 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Callee);
2914 const GlobalValue *GV = GSD->getGlobal();
2915 Ops.push_back(DAG.getTargetGlobalAddress(GV, DL, MVT::i64));
2916
2917 if (IsTailCall) {
2918 // Each tail call may have to adjust the stack by a different amount, so
2919 // this information must travel along with the operation for eventual
2920 // consumption by emitEpilogue.
2921 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
2922
2923 Ops.push_back(PhysReturnAddrReg);
2924 }
2925
2926 // Add argument registers to the end of the list so that they are known live
2927 // into the call.
2928 for (auto &RegToPass : RegsToPass) {
2929 Ops.push_back(DAG.getRegister(RegToPass.first,
2930 RegToPass.second.getValueType()));
2931 }
2932
2933 // Add a register mask operand representing the call-preserved registers.
2934
2935 auto *TRI = static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
2936 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
2937 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 2937, __PRETTY_FUNCTION__))
;
2938 Ops.push_back(DAG.getRegisterMask(Mask));
2939
2940 if (InFlag.getNode())
2941 Ops.push_back(InFlag);
2942
2943 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2944
2945 // If we're doing a tall call, use a TC_RETURN here rather than an
2946 // actual call instruction.
2947 if (IsTailCall) {
2948 MFI.setHasTailCall();
2949 return DAG.getNode(AMDGPUISD::TC_RETURN, DL, NodeTys, Ops);
2950 }
2951
2952 // Returns a chain and a flag for retval copy to use.
2953 SDValue Call = DAG.getNode(AMDGPUISD::CALL, DL, NodeTys, Ops);
2954 Chain = Call.getValue(0);
2955 InFlag = Call.getValue(1);
2956
2957 uint64_t CalleePopBytes = NumBytes;
2958 Chain = DAG.getCALLSEQ_END(Chain, DAG.getTargetConstant(0, DL, MVT::i32),
2959 DAG.getTargetConstant(CalleePopBytes, DL, MVT::i32),
2960 InFlag, DL);
2961 if (!Ins.empty())
2962 InFlag = Chain.getValue(1);
2963
2964 // Handle result values, copying them out of physregs into vregs that we
2965 // return.
2966 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2967 InVals, IsThisReturn,
2968 IsThisReturn ? OutVals[0] : SDValue());
2969}
2970
2971Register SITargetLowering::getRegisterByName(const char* RegName, LLT VT,
2972 const MachineFunction &MF) const {
2973 Register Reg = StringSwitch<Register>(RegName)
2974 .Case("m0", AMDGPU::M0)
2975 .Case("exec", AMDGPU::EXEC)
2976 .Case("exec_lo", AMDGPU::EXEC_LO)
2977 .Case("exec_hi", AMDGPU::EXEC_HI)
2978 .Case("flat_scratch", AMDGPU::FLAT_SCR)
2979 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
2980 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
2981 .Default(Register());
2982
2983 if (Reg == AMDGPU::NoRegister) {
2984 report_fatal_error(Twine("invalid register name \""
2985 + StringRef(RegName) + "\"."));
2986
2987 }
2988
2989 if (!Subtarget->hasFlatScrRegister() &&
2990 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
2991 report_fatal_error(Twine("invalid register \""
2992 + StringRef(RegName) + "\" for subtarget."));
2993 }
2994
2995 switch (Reg) {
2996 case AMDGPU::M0:
2997 case AMDGPU::EXEC_LO:
2998 case AMDGPU::EXEC_HI:
2999 case AMDGPU::FLAT_SCR_LO:
3000 case AMDGPU::FLAT_SCR_HI:
3001 if (VT.getSizeInBits() == 32)
3002 return Reg;
3003 break;
3004 case AMDGPU::EXEC:
3005 case AMDGPU::FLAT_SCR:
3006 if (VT.getSizeInBits() == 64)
3007 return Reg;
3008 break;
3009 default:
3010 llvm_unreachable("missing register type checking")::llvm::llvm_unreachable_internal("missing register type checking"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3010)
;
3011 }
3012
3013 report_fatal_error(Twine("invalid type for register \""
3014 + StringRef(RegName) + "\"."));
3015}
3016
3017// If kill is not the last instruction, split the block so kill is always a
3018// proper terminator.
3019MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,
3020 MachineBasicBlock *BB) const {
3021 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3022
3023 MachineBasicBlock::iterator SplitPoint(&MI);
3024 ++SplitPoint;
3025
3026 if (SplitPoint == BB->end()) {
3027 // Don't bother with a new block.
3028 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
3029 return BB;
3030 }
3031
3032 MachineFunction *MF = BB->getParent();
3033 MachineBasicBlock *SplitBB
3034 = MF->CreateMachineBasicBlock(BB->getBasicBlock());
3035
3036 MF->insert(++MachineFunction::iterator(BB), SplitBB);
3037 SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
3038
3039 SplitBB->transferSuccessorsAndUpdatePHIs(BB);
3040 BB->addSuccessor(SplitBB);
3041
3042 MI.setDesc(TII->getKillTerminatorFromPseudo(MI.getOpcode()));
3043 return SplitBB;
3044}
3045
3046// Split block \p MBB at \p MI, as to insert a loop. If \p InstInLoop is true,
3047// \p MI will be the only instruction in the loop body block. Otherwise, it will
3048// be the first instruction in the remainder block.
3049//
3050/// \returns { LoopBody, Remainder }
3051static std::pair<MachineBasicBlock *, MachineBasicBlock *>
3052splitBlockForLoop(MachineInstr &MI, MachineBasicBlock &MBB, bool InstInLoop) {
3053 MachineFunction *MF = MBB.getParent();
3054 MachineBasicBlock::iterator I(&MI);
3055
3056 // To insert the loop we need to split the block. Move everything after this
3057 // point to a new block, and insert a new empty block between the two.
3058 MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
3059 MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
3060 MachineFunction::iterator MBBI(MBB);
3061 ++MBBI;
3062
3063 MF->insert(MBBI, LoopBB);
3064 MF->insert(MBBI, RemainderBB);
3065
3066 LoopBB->addSuccessor(LoopBB);
3067 LoopBB->addSuccessor(RemainderBB);
3068
3069 // Move the rest of the block into a new block.
3070 RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
3071
3072 if (InstInLoop) {
3073 auto Next = std::next(I);
3074
3075 // Move instruction to loop body.
3076 LoopBB->splice(LoopBB->begin(), &MBB, I, Next);
3077
3078 // Move the rest of the block.
3079 RemainderBB->splice(RemainderBB->begin(), &MBB, Next, MBB.end());
3080 } else {
3081 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
3082 }
3083
3084 MBB.addSuccessor(LoopBB);
3085
3086 return std::make_pair(LoopBB, RemainderBB);
3087}
3088
3089/// Insert \p MI into a BUNDLE with an S_WAITCNT 0 immediately following it.
3090void SITargetLowering::bundleInstWithWaitcnt(MachineInstr &MI) const {
3091 MachineBasicBlock *MBB = MI.getParent();
3092 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3093 auto I = MI.getIterator();
3094 auto E = std::next(I);
3095
3096 BuildMI(*MBB, E, MI.getDebugLoc(), TII->get(AMDGPU::S_WAITCNT))
3097 .addImm(0);
3098
3099 MIBundleBuilder Bundler(*MBB, I, E);
3100 finalizeBundle(*MBB, Bundler.begin());
3101}
3102
3103MachineBasicBlock *
3104SITargetLowering::emitGWSMemViolTestLoop(MachineInstr &MI,
3105 MachineBasicBlock *BB) const {
3106 const DebugLoc &DL = MI.getDebugLoc();
3107
3108 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3109
3110 MachineBasicBlock *LoopBB;
3111 MachineBasicBlock *RemainderBB;
3112 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3113
3114 // Apparently kill flags are only valid if the def is in the same block?
3115 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0))
3116 Src->setIsKill(false);
3117
3118 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, *BB, true);
3119
3120 MachineBasicBlock::iterator I = LoopBB->end();
3121
3122 const unsigned EncodedReg = AMDGPU::Hwreg::encodeHwreg(
3123 AMDGPU::Hwreg::ID_TRAPSTS, AMDGPU::Hwreg::OFFSET_MEM_VIOL, 1);
3124
3125 // Clear TRAP_STS.MEM_VIOL
3126 BuildMI(*LoopBB, LoopBB->begin(), DL, TII->get(AMDGPU::S_SETREG_IMM32_B32))
3127 .addImm(0)
3128 .addImm(EncodedReg);
3129
3130 bundleInstWithWaitcnt(MI);
3131
3132 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3133
3134 // Load and check TRAP_STS.MEM_VIOL
3135 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), Reg)
3136 .addImm(EncodedReg);
3137
3138 // FIXME: Do we need to use an isel pseudo that may clobber scc?
3139 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CMP_LG_U32))
3140 .addReg(Reg, RegState::Kill)
3141 .addImm(0);
3142 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3143 .addMBB(LoopBB);
3144
3145 return RemainderBB;
3146}
3147
3148// Do a v_movrels_b32 or v_movreld_b32 for each unique value of \p IdxReg in the
3149// wavefront. If the value is uniform and just happens to be in a VGPR, this
3150// will only do one iteration. In the worst case, this will loop 64 times.
3151//
3152// TODO: Just use v_readlane_b32 if we know the VGPR has a uniform value.
3153static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(
3154 const SIInstrInfo *TII,
3155 MachineRegisterInfo &MRI,
3156 MachineBasicBlock &OrigBB,
3157 MachineBasicBlock &LoopBB,
3158 const DebugLoc &DL,
3159 const MachineOperand &IdxReg,
3160 unsigned InitReg,
3161 unsigned ResultReg,
3162 unsigned PhiReg,
3163 unsigned InitSaveExecReg,
3164 int Offset,
3165 bool UseGPRIdxMode,
3166 bool IsIndirectSrc) {
3167 MachineFunction *MF = OrigBB.getParent();
3168 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3169 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3170 MachineBasicBlock::iterator I = LoopBB.begin();
3171
3172 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3173 Register PhiExec = MRI.createVirtualRegister(BoolRC);
3174 Register NewExec = MRI.createVirtualRegister(BoolRC);
3175 Register CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3176 Register CondReg = MRI.createVirtualRegister(BoolRC);
3177
3178 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
3179 .addReg(InitReg)
3180 .addMBB(&OrigBB)
3181 .addReg(ResultReg)
3182 .addMBB(&LoopBB);
3183
3184 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
3185 .addReg(InitSaveExecReg)
3186 .addMBB(&OrigBB)
3187 .addReg(NewExec)
3188 .addMBB(&LoopBB);
3189
3190 // Read the next variant <- also loop target.
3191 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
3192 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));
3193
3194 // Compare the just read M0 value to all possible Idx values.
3195 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
3196 .addReg(CurrentIdxReg)
3197 .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
3198
3199 // Update EXEC, save the original EXEC value to VCC.
3200 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
3201 : AMDGPU::S_AND_SAVEEXEC_B64),
3202 NewExec)
3203 .addReg(CondReg, RegState::Kill);
3204
3205 MRI.setSimpleHint(NewExec, CondReg);
3206
3207 if (UseGPRIdxMode) {
3208 unsigned IdxReg;
3209 if (Offset == 0) {
3210 IdxReg = CurrentIdxReg;
3211 } else {
3212 IdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3213 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), IdxReg)
3214 .addReg(CurrentIdxReg, RegState::Kill)
3215 .addImm(Offset);
3216 }
3217 unsigned IdxMode = IsIndirectSrc ?
3218 AMDGPU::VGPRIndexMode::SRC0_ENABLE : AMDGPU::VGPRIndexMode::DST_ENABLE;
3219 MachineInstr *SetOn =
3220 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3221 .addReg(IdxReg, RegState::Kill)
3222 .addImm(IdxMode);
3223 SetOn->getOperand(3).setIsUndef();
3224 } else {
3225 // Move index from VCC into M0
3226 if (Offset == 0) {
3227 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3228 .addReg(CurrentIdxReg, RegState::Kill);
3229 } else {
3230 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3231 .addReg(CurrentIdxReg, RegState::Kill)
3232 .addImm(Offset);
3233 }
3234 }
3235
3236 // Update EXEC, switch all done bits to 0 and all todo bits to 1.
3237 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3238 MachineInstr *InsertPt =
3239 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
3240 : AMDGPU::S_XOR_B64_term), Exec)
3241 .addReg(Exec)
3242 .addReg(NewExec);
3243
3244 // XXX - s_xor_b64 sets scc to 1 if the result is nonzero, so can we use
3245 // s_cbranch_scc0?
3246
3247 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover.
3248 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
3249 .addMBB(&LoopBB);
3250
3251 return InsertPt->getIterator();
3252}
3253
3254// This has slightly sub-optimal regalloc when the source vector is killed by
3255// the read. The register allocator does not understand that the kill is
3256// per-workitem, so is kept alive for the whole loop so we end up not re-using a
3257// subregister from it, using 1 more VGPR than necessary. This was saved when
3258// this was expanded after register allocation.
3259static MachineBasicBlock::iterator loadM0FromVGPR(const SIInstrInfo *TII,
3260 MachineBasicBlock &MBB,
3261 MachineInstr &MI,
3262 unsigned InitResultReg,
3263 unsigned PhiReg,
3264 int Offset,
3265 bool UseGPRIdxMode,
3266 bool IsIndirectSrc) {
3267 MachineFunction *MF = MBB.getParent();
3268 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3269 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3270 MachineRegisterInfo &MRI = MF->getRegInfo();
3271 const DebugLoc &DL = MI.getDebugLoc();
3272 MachineBasicBlock::iterator I(&MI);
3273
3274 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3275 Register DstReg = MI.getOperand(0).getReg();
3276 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
3277 Register TmpExec = MRI.createVirtualRegister(BoolXExecRC);
3278 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3279 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
3280
3281 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
3282
3283 // Save the EXEC mask
3284 BuildMI(MBB, I, DL, TII->get(MovExecOpc), SaveExec)
3285 .addReg(Exec);
3286
3287 MachineBasicBlock *LoopBB;
3288 MachineBasicBlock *RemainderBB;
3289 std::tie(LoopBB, RemainderBB) = splitBlockForLoop(MI, MBB, false);
3290
3291 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3292
3293 auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
3294 InitResultReg, DstReg, PhiReg, TmpExec,
3295 Offset, UseGPRIdxMode, IsIndirectSrc);
3296
3297 MachineBasicBlock::iterator First = RemainderBB->begin();
3298 BuildMI(*RemainderBB, First, DL, TII->get(MovExecOpc), Exec)
3299 .addReg(SaveExec);
3300
3301 return InsPt;
3302}
3303
3304// Returns subreg index, offset
3305static std::pair<unsigned, int>
3306computeIndirectRegAndOffset(const SIRegisterInfo &TRI,
3307 const TargetRegisterClass *SuperRC,
3308 unsigned VecReg,
3309 int Offset) {
3310 int NumElts = TRI.getRegSizeInBits(*SuperRC) / 32;
3311
3312 // Skip out of bounds offsets, or else we would end up using an undefined
3313 // register.
3314 if (Offset >= NumElts || Offset < 0)
3315 return std::make_pair(AMDGPU::sub0, Offset);
3316
3317 return std::make_pair(SIRegisterInfo::getSubRegFromChannel(Offset), 0);
3318}
3319
3320// Return true if the index is an SGPR and was set.
3321static bool setM0ToIndexFromSGPR(const SIInstrInfo *TII,
3322 MachineRegisterInfo &MRI,
3323 MachineInstr &MI,
3324 int Offset,
3325 bool UseGPRIdxMode,
3326 bool IsIndirectSrc) {
3327 MachineBasicBlock *MBB = MI.getParent();
3328 const DebugLoc &DL = MI.getDebugLoc();
3329 MachineBasicBlock::iterator I(&MI);
3330
3331 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3332 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3333
3334 assert(Idx->getReg() != AMDGPU::NoRegister)((Idx->getReg() != AMDGPU::NoRegister) ? static_cast<void
> (0) : __assert_fail ("Idx->getReg() != AMDGPU::NoRegister"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3334, __PRETTY_FUNCTION__))
;
3335
3336 if (!TII->getRegisterInfo().isSGPRClass(IdxRC))
3337 return false;
3338
3339 if (UseGPRIdxMode) {
3340 unsigned IdxMode = IsIndirectSrc ?
3341 AMDGPU::VGPRIndexMode::SRC0_ENABLE : AMDGPU::VGPRIndexMode::DST_ENABLE;
3342 if (Offset == 0) {
3343 MachineInstr *SetOn =
3344 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3345 .add(*Idx)
3346 .addImm(IdxMode);
3347
3348 SetOn->getOperand(3).setIsUndef();
3349 } else {
3350 Register Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
3351 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
3352 .add(*Idx)
3353 .addImm(Offset);
3354 MachineInstr *SetOn =
3355 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
3356 .addReg(Tmp, RegState::Kill)
3357 .addImm(IdxMode);
3358
3359 SetOn->getOperand(3).setIsUndef();
3360 }
3361
3362 return true;
3363 }
3364
3365 if (Offset == 0) {
3366 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3367 .add(*Idx);
3368 } else {
3369 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3370 .add(*Idx)
3371 .addImm(Offset);
3372 }
3373
3374 return true;
3375}
3376
3377// Control flow needs to be inserted if indexing with a VGPR.
3378static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
3379 MachineBasicBlock &MBB,
3380 const GCNSubtarget &ST) {
3381 const SIInstrInfo *TII = ST.getInstrInfo();
3382 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3383 MachineFunction *MF = MBB.getParent();
3384 MachineRegisterInfo &MRI = MF->getRegInfo();
3385
3386 Register Dst = MI.getOperand(0).getReg();
3387 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
3388 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3389
3390 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3391
3392 unsigned SubReg;
3393 std::tie(SubReg, Offset)
3394 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
3395
3396 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3397
3398 if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, true)) {
3399 MachineBasicBlock::iterator I(&MI);
3400 const DebugLoc &DL = MI.getDebugLoc();
3401
3402 if (UseGPRIdxMode) {
3403 // TODO: Look at the uses to avoid the copy. This may require rescheduling
3404 // to avoid interfering with other uses, so probably requires a new
3405 // optimization pass.
3406 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3407 .addReg(SrcReg, RegState::Undef, SubReg)
3408 .addReg(SrcReg, RegState::Implicit)
3409 .addReg(AMDGPU::M0, RegState::Implicit);
3410 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3411 } else {
3412 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3413 .addReg(SrcReg, RegState::Undef, SubReg)
3414 .addReg(SrcReg, RegState::Implicit);
3415 }
3416
3417 MI.eraseFromParent();
3418
3419 return &MBB;
3420 }
3421
3422 const DebugLoc &DL = MI.getDebugLoc();
3423 MachineBasicBlock::iterator I(&MI);
3424
3425 Register PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3426 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3427
3428 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3429
3430 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg,
3431 Offset, UseGPRIdxMode, true);
3432 MachineBasicBlock *LoopBB = InsPt->getParent();
3433
3434 if (UseGPRIdxMode) {
3435 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3436 .addReg(SrcReg, RegState::Undef, SubReg)
3437 .addReg(SrcReg, RegState::Implicit)
3438 .addReg(AMDGPU::M0, RegState::Implicit);
3439 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3440 } else {
3441 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3442 .addReg(SrcReg, RegState::Undef, SubReg)
3443 .addReg(SrcReg, RegState::Implicit);
3444 }
3445
3446 MI.eraseFromParent();
3447
3448 return LoopBB;
3449}
3450
3451static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
3452 MachineBasicBlock &MBB,
3453 const GCNSubtarget &ST) {
3454 const SIInstrInfo *TII = ST.getInstrInfo();
3455 const SIRegisterInfo &TRI = TII->getRegisterInfo();
3456 MachineFunction *MF = MBB.getParent();
3457 MachineRegisterInfo &MRI = MF->getRegInfo();
3458
3459 Register Dst = MI.getOperand(0).getReg();
3460 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
3461 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
3462 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
3463 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
3464 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3465
3466 // This can be an immediate, but will be folded later.
3467 assert(Val->getReg())((Val->getReg()) ? static_cast<void> (0) : __assert_fail
("Val->getReg()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3467, __PRETTY_FUNCTION__))
;
3468
3469 unsigned SubReg;
3470 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
3471 SrcVec->getReg(),
3472 Offset);
3473 const bool UseGPRIdxMode = ST.useVGPRIndexMode();
3474
3475 if (Idx->getReg() == AMDGPU::NoRegister) {
3476 MachineBasicBlock::iterator I(&MI);
3477 const DebugLoc &DL = MI.getDebugLoc();
3478
3479 assert(Offset == 0)((Offset == 0) ? static_cast<void> (0) : __assert_fail (
"Offset == 0", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3479, __PRETTY_FUNCTION__))
;
3480
3481 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
3482 .add(*SrcVec)
3483 .add(*Val)
3484 .addImm(SubReg);
3485
3486 MI.eraseFromParent();
3487 return &MBB;
3488 }
3489
3490 const MCInstrDesc &MovRelDesc
3491 = TII->getIndirectRegWritePseudo(TRI.getRegSizeInBits(*VecRC), 32, false);
3492
3493 if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, false)) {
3494 MachineBasicBlock::iterator I(&MI);
3495 const DebugLoc &DL = MI.getDebugLoc();
3496 BuildMI(MBB, I, DL, MovRelDesc, Dst)
3497 .addReg(SrcVec->getReg())
3498 .add(*Val)
3499 .addImm(SubReg);
3500 if (UseGPRIdxMode)
3501 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3502
3503 MI.eraseFromParent();
3504 return &MBB;
3505 }
3506
3507 if (Val->isReg())
3508 MRI.clearKillFlags(Val->getReg());
3509
3510 const DebugLoc &DL = MI.getDebugLoc();
3511
3512 Register PhiReg = MRI.createVirtualRegister(VecRC);
3513
3514 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
3515 Offset, UseGPRIdxMode, false);
3516 MachineBasicBlock *LoopBB = InsPt->getParent();
3517
3518 BuildMI(*LoopBB, InsPt, DL, MovRelDesc, Dst)
3519 .addReg(PhiReg)
3520 .add(*Val)
3521 .addImm(AMDGPU::sub0);
3522 if (UseGPRIdxMode)
3523 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
3524
3525 MI.eraseFromParent();
3526 return LoopBB;
3527}
3528
3529MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
3530 MachineInstr &MI, MachineBasicBlock *BB) const {
3531
3532 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3533 MachineFunction *MF = BB->getParent();
3534 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
3535
3536 if (TII->isMIMG(MI)) {
3537 if (MI.memoperands_empty() && MI.mayLoadOrStore()) {
3538 report_fatal_error("missing mem operand from MIMG instruction");
3539 }
3540 // Add a memoperand for mimg instructions so that they aren't assumed to
3541 // be ordered memory instuctions.
3542
3543 return BB;
3544 }
3545
3546 switch (MI.getOpcode()) {
3547 case AMDGPU::S_ADD_U64_PSEUDO:
3548 case AMDGPU::S_SUB_U64_PSEUDO: {
3549 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3550 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3551 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3552 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3553 const DebugLoc &DL = MI.getDebugLoc();
3554
3555 MachineOperand &Dest = MI.getOperand(0);
3556 MachineOperand &Src0 = MI.getOperand(1);
3557 MachineOperand &Src1 = MI.getOperand(2);
3558
3559 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3560 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
3561
3562 MachineOperand Src0Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3563 Src0, BoolRC, AMDGPU::sub0,
3564 &AMDGPU::SReg_32RegClass);
3565 MachineOperand Src0Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3566 Src0, BoolRC, AMDGPU::sub1,
3567 &AMDGPU::SReg_32RegClass);
3568
3569 MachineOperand Src1Sub0 = TII->buildExtractSubRegOrImm(MI, MRI,
3570 Src1, BoolRC, AMDGPU::sub0,
3571 &AMDGPU::SReg_32RegClass);
3572 MachineOperand Src1Sub1 = TII->buildExtractSubRegOrImm(MI, MRI,
3573 Src1, BoolRC, AMDGPU::sub1,
3574 &AMDGPU::SReg_32RegClass);
3575
3576 bool IsAdd = (MI.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
3577
3578 unsigned LoOpc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
3579 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
3580 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3581 .add(Src0Sub0)
3582 .add(Src1Sub0);
3583 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
3584 .add(Src0Sub1)
3585 .add(Src1Sub1);
3586 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3587 .addReg(DestSub0)
3588 .addImm(AMDGPU::sub0)
3589 .addReg(DestSub1)
3590 .addImm(AMDGPU::sub1);
3591 MI.eraseFromParent();
3592 return BB;
3593 }
3594 case AMDGPU::SI_INIT_M0: {
3595 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
3596 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3597 .add(MI.getOperand(0));
3598 MI.eraseFromParent();
3599 return BB;
3600 }
3601 case AMDGPU::SI_INIT_EXEC:
3602 // This should be before all vector instructions.
3603 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B64),
3604 AMDGPU::EXEC)
3605 .addImm(MI.getOperand(0).getImm());
3606 MI.eraseFromParent();
3607 return BB;
3608
3609 case AMDGPU::SI_INIT_EXEC_LO:
3610 // This should be before all vector instructions.
3611 BuildMI(*BB, &*BB->begin(), MI.getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),
3612 AMDGPU::EXEC_LO)
3613 .addImm(MI.getOperand(0).getImm());
3614 MI.eraseFromParent();
3615 return BB;
3616
3617 case AMDGPU::SI_INIT_EXEC_FROM_INPUT: {
3618 // Extract the thread count from an SGPR input and set EXEC accordingly.
3619 // Since BFM can't shift by 64, handle that case with CMP + CMOV.
3620 //
3621 // S_BFE_U32 count, input, {shift, 7}
3622 // S_BFM_B64 exec, count, 0
3623 // S_CMP_EQ_U32 count, 64
3624 // S_CMOV_B64 exec, -1
3625 MachineInstr *FirstMI = &*BB->begin();
3626 MachineRegisterInfo &MRI = MF->getRegInfo();
3627 Register InputReg = MI.getOperand(0).getReg();
3628 Register CountReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
3629 bool Found = false;
3630
3631 // Move the COPY of the input reg to the beginning, so that we can use it.
3632 for (auto I = BB->begin(); I != &MI; I++) {
3633 if (I->getOpcode() != TargetOpcode::COPY ||
3634 I->getOperand(0).getReg() != InputReg)
3635 continue;
3636
3637 if (I == FirstMI) {
3638 FirstMI = &*++BB->begin();
3639 } else {
3640 I->removeFromParent();
3641 BB->insert(FirstMI, &*I);
3642 }
3643 Found = true;
3644 break;
3645 }
3646 assert(Found)((Found) ? static_cast<void> (0) : __assert_fail ("Found"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3646, __PRETTY_FUNCTION__))
;
3647 (void)Found;
3648
3649 // This should be before all vector instructions.
3650 unsigned Mask = (getSubtarget()->getWavefrontSize() << 1) - 1;
3651 bool isWave32 = getSubtarget()->isWave32();
3652 unsigned Exec = isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3653 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_BFE_U32), CountReg)
3654 .addReg(InputReg)
3655 .addImm((MI.getOperand(1).getImm() & Mask) | 0x70000);
3656 BuildMI(*BB, FirstMI, DebugLoc(),
3657 TII->get(isWave32 ? AMDGPU::S_BFM_B32 : AMDGPU::S_BFM_B64),
3658 Exec)
3659 .addReg(CountReg)
3660 .addImm(0);
3661 BuildMI(*BB, FirstMI, DebugLoc(), TII->get(AMDGPU::S_CMP_EQ_U32))
3662 .addReg(CountReg, RegState::Kill)
3663 .addImm(getSubtarget()->getWavefrontSize());
3664 BuildMI(*BB, FirstMI, DebugLoc(),
3665 TII->get(isWave32 ? AMDGPU::S_CMOV_B32 : AMDGPU::S_CMOV_B64),
3666 Exec)
3667 .addImm(-1);
3668 MI.eraseFromParent();
3669 return BB;
3670 }
3671
3672 case AMDGPU::GET_GROUPSTATICSIZE: {
3673 assert(getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA ||((getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA
|| getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL
) ? static_cast<void> (0) : __assert_fail ("getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3674, __PRETTY_FUNCTION__))
3674 getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL)((getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA
|| getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL
) ? static_cast<void> (0) : __assert_fail ("getTargetMachine().getTargetTriple().getOS() == Triple::AMDHSA || getTargetMachine().getTargetTriple().getOS() == Triple::AMDPAL"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3674, __PRETTY_FUNCTION__))
;
3675 DebugLoc DL = MI.getDebugLoc();
3676 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
3677 .add(MI.getOperand(0))
3678 .addImm(MFI->getLDSSize());
3679 MI.eraseFromParent();
3680 return BB;
3681 }
3682 case AMDGPU::SI_INDIRECT_SRC_V1:
3683 case AMDGPU::SI_INDIRECT_SRC_V2:
3684 case AMDGPU::SI_INDIRECT_SRC_V4:
3685 case AMDGPU::SI_INDIRECT_SRC_V8:
3686 case AMDGPU::SI_INDIRECT_SRC_V16:
3687 return emitIndirectSrc(MI, *BB, *getSubtarget());
3688 case AMDGPU::SI_INDIRECT_DST_V1:
3689 case AMDGPU::SI_INDIRECT_DST_V2:
3690 case AMDGPU::SI_INDIRECT_DST_V4:
3691 case AMDGPU::SI_INDIRECT_DST_V8:
3692 case AMDGPU::SI_INDIRECT_DST_V16:
3693 return emitIndirectDst(MI, *BB, *getSubtarget());
3694 case AMDGPU::SI_KILL_F32_COND_IMM_PSEUDO:
3695 case AMDGPU::SI_KILL_I1_PSEUDO:
3696 return splitKillBlock(MI, BB);
3697 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
3698 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
3699 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3700 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3701
3702 Register Dst = MI.getOperand(0).getReg();
3703 Register Src0 = MI.getOperand(1).getReg();
3704 Register Src1 = MI.getOperand(2).getReg();
3705 const DebugLoc &DL = MI.getDebugLoc();
3706 Register SrcCond = MI.getOperand(3).getReg();
3707
3708 Register DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3709 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
3710 const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3711 Register SrcCondCopy = MRI.createVirtualRegister(CondRC);
3712
3713 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
3714 .addReg(SrcCond);
3715 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
3716 .addImm(0)
3717 .addReg(Src0, 0, AMDGPU::sub0)
3718 .addImm(0)
3719 .addReg(Src1, 0, AMDGPU::sub0)
3720 .addReg(SrcCondCopy);
3721 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
3722 .addImm(0)
3723 .addReg(Src0, 0, AMDGPU::sub1)
3724 .addImm(0)
3725 .addReg(Src1, 0, AMDGPU::sub1)
3726 .addReg(SrcCondCopy);
3727
3728 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
3729 .addReg(DstLo)
3730 .addImm(AMDGPU::sub0)
3731 .addReg(DstHi)
3732 .addImm(AMDGPU::sub1);
3733 MI.eraseFromParent();
3734 return BB;
3735 }
3736 case AMDGPU::SI_BR_UNDEF: {
3737 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3738 const DebugLoc &DL = MI.getDebugLoc();
3739 MachineInstr *Br = BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CBRANCH_SCC1))
3740 .add(MI.getOperand(0));
3741 Br->getOperand(1).setIsUndef(true); // read undef SCC
3742 MI.eraseFromParent();
3743 return BB;
3744 }
3745 case AMDGPU::ADJCALLSTACKUP:
3746 case AMDGPU::ADJCALLSTACKDOWN: {
3747 const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
3748 MachineInstrBuilder MIB(*MF, &MI);
3749
3750 // Add an implicit use of the frame offset reg to prevent the restore copy
3751 // inserted after the call from being reorderd after stack operations in the
3752 // the caller's frame.
3753 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
3754 .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
3755 .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
3756 return BB;
3757 }
3758 case AMDGPU::SI_CALL_ISEL: {
3759 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3760 const DebugLoc &DL = MI.getDebugLoc();
3761
3762 unsigned ReturnAddrReg = TII->getRegisterInfo().getReturnAddressReg(*MF);
3763
3764 MachineInstrBuilder MIB;
3765 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg);
3766
3767 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I)
3768 MIB.add(MI.getOperand(I));
3769
3770 MIB.cloneMemRefs(MI);
3771 MI.eraseFromParent();
3772 return BB;
3773 }
3774 case AMDGPU::V_ADD_I32_e32:
3775 case AMDGPU::V_SUB_I32_e32:
3776 case AMDGPU::V_SUBREV_I32_e32: {
3777 // TODO: Define distinct V_*_I32_Pseudo instructions instead.
3778 const DebugLoc &DL = MI.getDebugLoc();
3779 unsigned Opc = MI.getOpcode();
3780
3781 bool NeedClampOperand = false;
3782 if (TII->pseudoToMCOpcode(Opc) == -1) {
3783 Opc = AMDGPU::getVOPe64(Opc);
3784 NeedClampOperand = true;
3785 }
3786
3787 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
3788 if (TII->isVOP3(*I)) {
3789 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3790 const SIRegisterInfo *TRI = ST.getRegisterInfo();
3791 I.addReg(TRI->getVCC(), RegState::Define);
3792 }
3793 I.add(MI.getOperand(1))
3794 .add(MI.getOperand(2));
3795 if (NeedClampOperand)
3796 I.addImm(0); // clamp bit for e64 encoding
3797
3798 TII->legalizeOperands(*I);
3799
3800 MI.eraseFromParent();
3801 return BB;
3802 }
3803 case AMDGPU::DS_GWS_INIT:
3804 case AMDGPU::DS_GWS_SEMA_V:
3805 case AMDGPU::DS_GWS_SEMA_BR:
3806 case AMDGPU::DS_GWS_SEMA_P:
3807 case AMDGPU::DS_GWS_SEMA_RELEASE_ALL:
3808 case AMDGPU::DS_GWS_BARRIER:
3809 // A s_waitcnt 0 is required to be the instruction immediately following.
3810 if (getSubtarget()->hasGWSAutoReplay()) {
3811 bundleInstWithWaitcnt(MI);
3812 return BB;
3813 }
3814
3815 return emitGWSMemViolTestLoop(MI, BB);
3816 default:
3817 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
3818 }
3819}
3820
3821bool SITargetLowering::hasBitPreservingFPLogic(EVT VT) const {
3822 return isTypeLegal(VT.getScalarType());
3823}
3824
3825bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
3826 // This currently forces unfolding various combinations of fsub into fma with
3827 // free fneg'd operands. As long as we have fast FMA (controlled by
3828 // isFMAFasterThanFMulAndFAdd), we should perform these.
3829
3830 // When fma is quarter rate, for f64 where add / sub are at best half rate,
3831 // most of these combines appear to be cycle neutral but save on instruction
3832 // count / code size.
3833 return true;
3834}
3835
3836EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
3837 EVT VT) const {
3838 if (!VT.isVector()) {
3839 return MVT::i1;
3840 }
3841 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
3842}
3843
3844MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT VT) const {
3845 // TODO: Should i16 be used always if legal? For now it would force VALU
3846 // shifts.
3847 return (VT == MVT::i16) ? MVT::i16 : MVT::i32;
3848}
3849
3850// Answering this is somewhat tricky and depends on the specific device which
3851// have different rates for fma or all f64 operations.
3852//
3853// v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
3854// regardless of which device (although the number of cycles differs between
3855// devices), so it is always profitable for f64.
3856//
3857// v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
3858// only on full rate devices. Normally, we should prefer selecting v_mad_f32
3859// which we can always do even without fused FP ops since it returns the same
3860// result as the separate operations and since it is always full
3861// rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
3862// however does not support denormals, so we do report fma as faster if we have
3863// a fast fma device and require denormals.
3864//
3865bool SITargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
3866 EVT VT) const {
3867 VT = VT.getScalarType();
3868
3869 switch (VT.getSimpleVT().SimpleTy) {
3870 case MVT::f32: {
3871 // This is as fast on some subtargets. However, we always have full rate f32
3872 // mad available which returns the same result as the separate operations
3873 // which we should prefer over fma. We can't use this if we want to support
3874 // denormals, so only report this in these cases.
3875 if (hasFP32Denormals(MF))
3876 return Subtarget->hasFastFMAF32() || Subtarget->hasDLInsts();
3877
3878 // If the subtarget has v_fmac_f32, that's just as good as v_mac_f32.
3879 return Subtarget->hasFastFMAF32() && Subtarget->hasDLInsts();
3880 }
3881 case MVT::f64:
3882 return true;
3883 case MVT::f16:
3884 return Subtarget->has16BitInsts() && hasFP64FP16Denormals(MF);
3885 default:
3886 break;
3887 }
3888
3889 return false;
3890}
3891
3892bool SITargetLowering::isFMADLegalForFAddFSub(const SelectionDAG &DAG,
3893 const SDNode *N) const {
3894 // TODO: Check future ftz flag
3895 // v_mad_f32/v_mac_f32 do not support denormals.
3896 EVT VT = N->getValueType(0);
3897 if (VT == MVT::f32)
3898 return !hasFP32Denormals(DAG.getMachineFunction());
3899 if (VT == MVT::f16) {
3900 return Subtarget->hasMadF16() &&
3901 !hasFP64FP16Denormals(DAG.getMachineFunction());
3902 }
3903
3904 return false;
3905}
3906
3907//===----------------------------------------------------------------------===//
3908// Custom DAG Lowering Operations
3909//===----------------------------------------------------------------------===//
3910
3911// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
3912// wider vector type is legal.
3913SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
3914 SelectionDAG &DAG) const {
3915 unsigned Opc = Op.getOpcode();
3916 EVT VT = Op.getValueType();
3917 assert(VT == MVT::v4f16 || VT == MVT::v4i16)((VT == MVT::v4f16 || VT == MVT::v4i16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v4f16 || VT == MVT::v4i16"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3917, __PRETTY_FUNCTION__))
;
3918
3919 SDValue Lo, Hi;
3920 std::tie(Lo, Hi) = DAG.SplitVectorOperand(Op.getNode(), 0);
3921
3922 SDLoc SL(Op);
3923 SDValue OpLo = DAG.getNode(Opc, SL, Lo.getValueType(), Lo,
3924 Op->getFlags());
3925 SDValue OpHi = DAG.getNode(Opc, SL, Hi.getValueType(), Hi,
3926 Op->getFlags());
3927
3928 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
3929}
3930
3931// Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
3932// wider vector type is legal.
3933SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
3934 SelectionDAG &DAG) const {
3935 unsigned Opc = Op.getOpcode();
3936 EVT VT = Op.getValueType();
3937 assert(VT == MVT::v4i16 || VT == MVT::v4f16)((VT == MVT::v4i16 || VT == MVT::v4f16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3937, __PRETTY_FUNCTION__))
;
3938
3939 SDValue Lo0, Hi0;
3940 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
3941 SDValue Lo1, Hi1;
3942 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
3943
3944 SDLoc SL(Op);
3945
3946 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1,
3947 Op->getFlags());
3948 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1,
3949 Op->getFlags());
3950
3951 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
3952}
3953
3954SDValue SITargetLowering::splitTernaryVectorOp(SDValue Op,
3955 SelectionDAG &DAG) const {
3956 unsigned Opc = Op.getOpcode();
3957 EVT VT = Op.getValueType();
3958 assert(VT == MVT::v4i16 || VT == MVT::v4f16)((VT == MVT::v4i16 || VT == MVT::v4f16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v4i16 || VT == MVT::v4f16"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3958, __PRETTY_FUNCTION__))
;
3959
3960 SDValue Lo0, Hi0;
3961 std::tie(Lo0, Hi0) = DAG.SplitVectorOperand(Op.getNode(), 0);
3962 SDValue Lo1, Hi1;
3963 std::tie(Lo1, Hi1) = DAG.SplitVectorOperand(Op.getNode(), 1);
3964 SDValue Lo2, Hi2;
3965 std::tie(Lo2, Hi2) = DAG.SplitVectorOperand(Op.getNode(), 2);
3966
3967 SDLoc SL(Op);
3968
3969 SDValue OpLo = DAG.getNode(Opc, SL, Lo0.getValueType(), Lo0, Lo1, Lo2,
3970 Op->getFlags());
3971 SDValue OpHi = DAG.getNode(Opc, SL, Hi0.getValueType(), Hi0, Hi1, Hi2,
3972 Op->getFlags());
3973
3974 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
3975}
3976
3977
3978SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3979 switch (Op.getOpcode()) {
3980 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
3981 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
3982 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3983 case ISD::LOAD: {
3984 SDValue Result = LowerLOAD(Op, DAG);
3985 assert((!Result.getNode() ||(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3987, __PRETTY_FUNCTION__))
3986 Result.getNode()->getNumValues() == 2) &&(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3987, __PRETTY_FUNCTION__))
3987 "Load should return a value and a chain")(((!Result.getNode() || Result.getNode()->getNumValues() ==
2) && "Load should return a value and a chain") ? static_cast
<void> (0) : __assert_fail ("(!Result.getNode() || Result.getNode()->getNumValues() == 2) && \"Load should return a value and a chain\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 3987, __PRETTY_FUNCTION__))
;
3988 return Result;
3989 }
3990
3991 case ISD::FSIN:
3992 case ISD::FCOS:
3993 return LowerTrig(Op, DAG);
3994 case ISD::SELECT: return LowerSELECT(Op, DAG);
3995 case ISD::FDIV: return LowerFDIV(Op, DAG);
3996 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
3997 case ISD::STORE: return LowerSTORE(Op, DAG);
3998 case ISD::GlobalAddress: {
3999 MachineFunction &MF = DAG.getMachineFunction();
4000 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
4001 return LowerGlobalAddress(MFI, Op, DAG);
4002 }
4003 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4004 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
4005 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
4006 case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
4007 case ISD::INSERT_SUBVECTOR:
4008 return lowerINSERT_SUBVECTOR(Op, DAG);
4009 case ISD::INSERT_VECTOR_ELT:
4010 return lowerINSERT_VECTOR_ELT(Op, DAG);
4011 case ISD::EXTRACT_VECTOR_ELT:
4012 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4013 case ISD::VECTOR_SHUFFLE:
4014 return lowerVECTOR_SHUFFLE(Op, DAG);
4015 case ISD::BUILD_VECTOR:
4016 return lowerBUILD_VECTOR(Op, DAG);
4017 case ISD::FP_ROUND:
4018 return lowerFP_ROUND(Op, DAG);
4019 case ISD::TRAP:
4020 return lowerTRAP(Op, DAG);
4021 case ISD::DEBUGTRAP:
4022 return lowerDEBUGTRAP(Op, DAG);
4023 case ISD::FABS:
4024 case ISD::FNEG:
4025 case ISD::FCANONICALIZE:
4026 case ISD::BSWAP:
4027 return splitUnaryVectorOp(Op, DAG);
4028 case ISD::FMINNUM:
4029 case ISD::FMAXNUM:
4030 return lowerFMINNUM_FMAXNUM(Op, DAG);
4031 case ISD::FMA:
4032 return splitTernaryVectorOp(Op, DAG);
4033 case ISD::SHL:
4034 case ISD::SRA:
4035 case ISD::SRL:
4036 case ISD::ADD:
4037 case ISD::SUB:
4038 case ISD::MUL:
4039 case ISD::SMIN:
4040 case ISD::SMAX:
4041 case ISD::UMIN:
4042 case ISD::UMAX:
4043 case ISD::FADD:
4044 case ISD::FMUL:
4045 case ISD::FMINNUM_IEEE:
4046 case ISD::FMAXNUM_IEEE:
4047 return splitBinaryVectorOp(Op, DAG);
4048 }
4049 return SDValue();
4050}
4051
4052static SDValue adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT,
4053 const SDLoc &DL,
4054 SelectionDAG &DAG, bool Unpacked) {
4055 if (!LoadVT.isVector())
4056 return Result;
4057
4058 if (Unpacked) { // From v2i32/v4i32 back to v2f16/v4f16.
4059 // Truncate to v2i16/v4i16.
4060 EVT IntLoadVT = LoadVT.changeTypeToInteger();
4061
4062 // Workaround legalizer not scalarizing truncate after vector op
4063 // legalization byt not creating intermediate vector trunc.
4064 SmallVector<SDValue, 4> Elts;
4065 DAG.ExtractVectorElements(Result, Elts);
4066 for (SDValue &Elt : Elts)
4067 Elt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Elt);
4068
4069 Result = DAG.getBuildVector(IntLoadVT, DL, Elts);
4070
4071 // Bitcast to original type (v2f16/v4f16).
4072 return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
4073 }
4074
4075 // Cast back to the original packed type.
4076 return DAG.getNode(ISD::BITCAST, DL, LoadVT, Result);
4077}
4078
4079SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
4080 MemSDNode *M,
4081 SelectionDAG &DAG,
4082 ArrayRef<SDValue> Ops,
4083 bool IsIntrinsic) const {
4084 SDLoc DL(M);
4085
4086 bool Unpacked = Subtarget->hasUnpackedD16VMem();
4087 EVT LoadVT = M->getValueType(0);
4088
4089 EVT EquivLoadVT = LoadVT;
4090 if (Unpacked && LoadVT.isVector()) {
4091 EquivLoadVT = LoadVT.isVector() ?
4092 EVT::getVectorVT(*DAG.getContext(), MVT::i32,
4093 LoadVT.getVectorNumElements()) : LoadVT;
4094 }
4095
4096 // Change from v4f16/v2f16 to EquivLoadVT.
4097 SDVTList VTList = DAG.getVTList(EquivLoadVT, MVT::Other);
4098
4099 SDValue Load
4100 = DAG.getMemIntrinsicNode(
4101 IsIntrinsic ? (unsigned)ISD::INTRINSIC_W_CHAIN : Opcode, DL,
4102 VTList, Ops, M->getMemoryVT(),
4103 M->getMemOperand());
4104 if (!Unpacked) // Just adjusted the opcode.
4105 return Load;
4106
4107 SDValue Adjusted = adjustLoadValueTypeImpl(Load, LoadVT, DL, DAG, Unpacked);
4108
4109 return DAG.getMergeValues({ Adjusted, Load.getValue(1) }, DL);
4110}
4111
4112SDValue SITargetLowering::lowerIntrinsicLoad(MemSDNode *M, bool IsFormat,
4113 SelectionDAG &DAG,
4114 ArrayRef<SDValue> Ops) const {
4115 SDLoc DL(M);
4116 EVT LoadVT = M->getValueType(0);
4117 EVT EltType = LoadVT.getScalarType();
4118 EVT IntVT = LoadVT.changeTypeToInteger();
4119
4120 bool IsD16 = IsFormat && (EltType.getSizeInBits() == 16);
4121
4122 unsigned Opc =
4123 IsFormat ? AMDGPUISD::BUFFER_LOAD_FORMAT : AMDGPUISD::BUFFER_LOAD;
4124
4125 if (IsD16) {
4126 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, M, DAG, Ops);
4127 }
4128
4129 // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
4130 if (!IsD16 && !LoadVT.isVector() && EltType.getSizeInBits() < 32)
4131 return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
4132
4133 if (isTypeLegal(LoadVT)) {
4134 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT,
4135 M->getMemOperand(), DAG);
4136 }
4137
4138 EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT);
4139 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other);
4140 SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT,
4141 M->getMemOperand(), DAG);
4142 return DAG.getMergeValues(
4143 {DAG.getNode(ISD::BITCAST, DL, LoadVT, MemNode), MemNode.getValue(1)},
4144 DL);
4145}
4146
4147static SDValue lowerICMPIntrinsic(const SITargetLowering &TLI,
4148 SDNode *N, SelectionDAG &DAG) {
4149 EVT VT = N->getValueType(0);
4150 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4151 int CondCode = CD->getSExtValue();
4152 if (CondCode < ICmpInst::Predicate::FIRST_ICMP_PREDICATE ||
4153 CondCode > ICmpInst::Predicate::LAST_ICMP_PREDICATE)
4154 return DAG.getUNDEF(VT);
4155
4156 ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
4157
4158 SDValue LHS = N->getOperand(1);
4159 SDValue RHS = N->getOperand(2);
4160
4161 SDLoc DL(N);
4162
4163 EVT CmpVT = LHS.getValueType();
4164 if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) {
4165 unsigned PromoteOp = ICmpInst::isSigned(IcInput) ?
4166 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4167 LHS = DAG.getNode(PromoteOp, DL, MVT::i32, LHS);
4168 RHS = DAG.getNode(PromoteOp, DL, MVT::i32, RHS);
4169 }
4170
4171 ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
4172
4173 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4174 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4175
4176 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS,
4177 DAG.getCondCode(CCOpcode));
4178 if (VT.bitsEq(CCVT))
4179 return SetCC;
4180 return DAG.getZExtOrTrunc(SetCC, DL, VT);
4181}
4182
4183static SDValue lowerFCMPIntrinsic(const SITargetLowering &TLI,
4184 SDNode *N, SelectionDAG &DAG) {
4185 EVT VT = N->getValueType(0);
4186 const auto *CD = cast<ConstantSDNode>(N->getOperand(3));
4187
4188 int CondCode = CD->getSExtValue();
4189 if (CondCode < FCmpInst::Predicate::FIRST_FCMP_PREDICATE ||
4190 CondCode > FCmpInst::Predicate::LAST_FCMP_PREDICATE) {
4191 return DAG.getUNDEF(VT);
4192 }
4193
4194 SDValue Src0 = N->getOperand(1);
4195 SDValue Src1 = N->getOperand(2);
4196 EVT CmpVT = Src0.getValueType();
4197 SDLoc SL(N);
4198
4199 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) {
4200 Src0 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src0);
4201 Src1 = DAG.getNode(ISD::FP_EXTEND, SL, MVT::f32, Src1);
4202 }
4203
4204 FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
4205 ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
4206 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize();
4207 EVT CCVT = EVT::getIntegerVT(*DAG.getContext(), WavefrontSize);
4208 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0,
4209 Src1, DAG.getCondCode(CCOpcode));
4210 if (VT.bitsEq(CCVT))
4211 return SetCC;
4212 return DAG.getZExtOrTrunc(SetCC, SL, VT);
4213}
4214
4215void SITargetLowering::ReplaceNodeResults(SDNode *N,
4216 SmallVectorImpl<SDValue> &Results,
4217 SelectionDAG &DAG) const {
4218 switch (N->getOpcode()) {
4219 case ISD::INSERT_VECTOR_ELT: {
4220 if (SDValue Res = lowerINSERT_VECTOR_ELT(SDValue(N, 0), DAG))
4221 Results.push_back(Res);
4222 return;
4223 }
4224 case ISD::EXTRACT_VECTOR_ELT: {
4225 if (SDValue Res = lowerEXTRACT_VECTOR_ELT(SDValue(N, 0), DAG))
4226 Results.push_back(Res);
4227 return;
4228 }
4229 case ISD::INTRINSIC_WO_CHAIN: {
4230 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4231 switch (IID) {
4232 case Intrinsic::amdgcn_cvt_pkrtz: {
4233 SDValue Src0 = N->getOperand(1);
4234 SDValue Src1 = N->getOperand(2);
4235 SDLoc SL(N);
4236 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, SL, MVT::i32,
4237 Src0, Src1);
4238 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Cvt));
4239 return;
4240 }
4241 case Intrinsic::amdgcn_cvt_pknorm_i16:
4242 case Intrinsic::amdgcn_cvt_pknorm_u16:
4243 case Intrinsic::amdgcn_cvt_pk_i16:
4244 case Intrinsic::amdgcn_cvt_pk_u16: {
4245 SDValue Src0 = N->getOperand(1);
4246 SDValue Src1 = N->getOperand(2);
4247 SDLoc SL(N);
4248 unsigned Opcode;
4249
4250 if (IID == Intrinsic::amdgcn_cvt_pknorm_i16)
4251 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
4252 else if (IID == Intrinsic::amdgcn_cvt_pknorm_u16)
4253 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
4254 else if (IID == Intrinsic::amdgcn_cvt_pk_i16)
4255 Opcode = AMDGPUISD::CVT_PK_I16_I32;
4256 else
4257 Opcode = AMDGPUISD::CVT_PK_U16_U32;
4258
4259 EVT VT = N->getValueType(0);
4260 if (isTypeLegal(VT))
4261 Results.push_back(DAG.getNode(Opcode, SL, VT, Src0, Src1));
4262 else {
4263 SDValue Cvt = DAG.getNode(Opcode, SL, MVT::i32, Src0, Src1);
4264 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, Cvt));
4265 }
4266 return;
4267 }
4268 }
4269 break;
4270 }
4271 case ISD::INTRINSIC_W_CHAIN: {
4272 if (SDValue Res = LowerINTRINSIC_W_CHAIN(SDValue(N, 0), DAG)) {
4273 if (Res.getOpcode() == ISD::MERGE_VALUES) {
4274 // FIXME: Hacky
4275 Results.push_back(Res.getOperand(0));
4276 Results.push_back(Res.getOperand(1));
4277 } else {
4278 Results.push_back(Res);
4279 Results.push_back(Res.getValue(1));
4280 }
4281 return;
4282 }
4283
4284 break;
4285 }
4286 case ISD::SELECT: {
4287 SDLoc SL(N);
4288 EVT VT = N->getValueType(0);
4289 EVT NewVT = getEquivalentMemType(*DAG.getContext(), VT);
4290 SDValue LHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(1));
4291 SDValue RHS = DAG.getNode(ISD::BITCAST, SL, NewVT, N->getOperand(2));
4292
4293 EVT SelectVT = NewVT;
4294 if (NewVT.bitsLT(MVT::i32)) {
4295 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS);
4296 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS);
4297 SelectVT = MVT::i32;
4298 }
4299
4300 SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, SelectVT,
4301 N->getOperand(0), LHS, RHS);
4302
4303 if (NewVT != SelectVT)
4304 NewSelect = DAG.getNode(ISD::TRUNCATE, SL, NewVT, NewSelect);
4305 Results.push_back(DAG.getNode(ISD::BITCAST, SL, VT, NewSelect));
4306 return;
4307 }
4308 case ISD::FNEG: {
4309 if (N->getValueType(0) != MVT::v2f16)
4310 break;
4311
4312 SDLoc SL(N);
4313 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
4314
4315 SDValue Op = DAG.getNode(ISD::XOR, SL, MVT::i32,
4316 BC,
4317 DAG.getConstant(0x80008000, SL, MVT::i32));
4318 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
4319 return;
4320 }
4321 case ISD::FABS: {
4322 if (N->getValueType(0) != MVT::v2f16)
4323 break;
4324
4325 SDLoc SL(N);
4326 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::i32, N->getOperand(0));
4327
4328 SDValue Op = DAG.getNode(ISD::AND, SL, MVT::i32,
4329 BC,
4330 DAG.getConstant(0x7fff7fff, SL, MVT::i32));
4331 Results.push_back(DAG.getNode(ISD::BITCAST, SL, MVT::v2f16, Op));
4332 return;
4333 }
4334 default:
4335 break;
4336 }
4337}
4338
4339/// Helper function for LowerBRCOND
4340static SDNode *findUser(SDValue Value, unsigned Opcode) {
4341
4342 SDNode *Parent = Value.getNode();
4343 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
4344 I != E; ++I) {
4345
4346 if (I.getUse().get() != Value)
4347 continue;
4348
4349 if (I->getOpcode() == Opcode)
4350 return *I;
4351 }
4352 return nullptr;
4353}
4354
4355unsigned SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
4356 if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
4357 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
4358 case Intrinsic::amdgcn_if:
4359 return AMDGPUISD::IF;
4360 case Intrinsic::amdgcn_else:
4361 return AMDGPUISD::ELSE;
4362 case Intrinsic::amdgcn_loop:
4363 return AMDGPUISD::LOOP;
4364 case Intrinsic::amdgcn_end_cf:
4365 llvm_unreachable("should not occur")::llvm::llvm_unreachable_internal("should not occur", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4365)
;
4366 default:
4367 return 0;
4368 }
4369 }
4370
4371 // break, if_break, else_break are all only used as inputs to loop, not
4372 // directly as branch conditions.
4373 return 0;
4374}
4375
4376bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
4377 const Triple &TT = getTargetMachine().getTargetTriple();
4378 return (GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
4379 GV->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
4380 AMDGPU::shouldEmitConstantsToTextSection(TT);
4381}
4382
4383bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
4384 // FIXME: Either avoid relying on address space here or change the default
4385 // address space for functions to avoid the explicit check.
4386 return (GV->getValueType()->isFunctionTy() ||
4387 !isNonGlobalAddrSpace(GV->getAddressSpace())) &&
4388 !shouldEmitFixup(GV) &&
4389 !getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
4390}
4391
4392bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
4393 return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
4394}
4395
4396bool SITargetLowering::shouldUseLDSConstAddress(const GlobalValue *GV) const {
4397 if (!GV->hasExternalLinkage())
4398 return true;
4399
4400 const auto OS = getTargetMachine().getTargetTriple().getOS();
4401 return OS == Triple::AMDHSA || OS == Triple::AMDPAL;
4402}
4403
4404/// This transforms the control flow intrinsics to get the branch destination as
4405/// last parameter, also switches branch target with BR if the need arise
4406SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
4407 SelectionDAG &DAG) const {
4408 SDLoc DL(BRCOND);
4409
4410 SDNode *Intr = BRCOND.getOperand(1).getNode();
4411 SDValue Target = BRCOND.getOperand(2);
4412 SDNode *BR = nullptr;
4413 SDNode *SetCC = nullptr;
4414
4415 if (Intr->getOpcode() == ISD::SETCC) {
4416 // As long as we negate the condition everything is fine
4417 SetCC = Intr;
4418 Intr = SetCC->getOperand(0).getNode();
4419
4420 } else {
4421 // Get the target from BR if we don't negate the condition
4422 BR = findUser(BRCOND, ISD::BR);
4423 Target = BR->getOperand(1);
4424 }
4425
4426 // FIXME: This changes the types of the intrinsics instead of introducing new
4427 // nodes with the correct types.
4428 // e.g. llvm.amdgcn.loop
4429
4430 // eg: i1,ch = llvm.amdgcn.loop t0, TargetConstant:i32<6271>, t3
4431 // => t9: ch = llvm.amdgcn.loop t0, TargetConstant:i32<6271>, t3, BasicBlock:ch<bb1 0x7fee5286d088>
4432
4433 unsigned CFNode = isCFIntrinsic(Intr);
4434 if (CFNode == 0) {
4435 // This is a uniform branch so we don't need to legalize.
4436 return BRCOND;
4437 }
4438
4439 bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||
4440 Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN;
4441
4442 assert(!SetCC ||((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4445, __PRETTY_FUNCTION__))
4443 (SetCC->getConstantOperandVal(1) == 1 &&((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4445, __PRETTY_FUNCTION__))
4444 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4445, __PRETTY_FUNCTION__))
4445 ISD::SETNE))((!SetCC || (SetCC->getConstantOperandVal(1) == 1 &&
cast<CondCodeSDNode>(SetCC->getOperand(2).getNode()
)->get() == ISD::SETNE)) ? static_cast<void> (0) : __assert_fail
("!SetCC || (SetCC->getConstantOperandVal(1) == 1 && cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == ISD::SETNE)"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4445, __PRETTY_FUNCTION__))
;
4446
4447 // operands of the new intrinsic call
4448 SmallVector<SDValue, 4> Ops;
4449 if (HaveChain)
4450 Ops.push_back(BRCOND.getOperand(0));
4451
4452 Ops.append(Intr->op_begin() + (HaveChain ? 2 : 1), Intr->op_end());
4453 Ops.push_back(Target);
4454
4455 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
4456
4457 // build the new intrinsic call
4458 SDNode *Result = DAG.getNode(CFNode, DL, DAG.getVTList(Res), Ops).getNode();
4459
4460 if (!HaveChain) {
4461 SDValue Ops[] = {
4462 SDValue(Result, 0),
4463 BRCOND.getOperand(0)
4464 };
4465
4466 Result = DAG.getMergeValues(Ops, DL).getNode();
4467 }
4468
4469 if (BR) {
4470 // Give the branch instruction our target
4471 SDValue Ops[] = {
4472 BR->getOperand(0),
4473 BRCOND.getOperand(2)
4474 };
4475 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
4476 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
4477 BR = NewBR.getNode();
4478 }
4479
4480 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
4481
4482 // Copy the intrinsic results to registers
4483 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
4484 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
4485 if (!CopyToReg)
4486 continue;
4487
4488 Chain = DAG.getCopyToReg(
4489 Chain, DL,
4490 CopyToReg->getOperand(1),
4491 SDValue(Result, i - 1),
4492 SDValue());
4493
4494 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
4495 }
4496
4497 // Remove the old intrinsic from the chain
4498 DAG.ReplaceAllUsesOfValueWith(
4499 SDValue(Intr, Intr->getNumValues() - 1),
4500 Intr->getOperand(0));
4501
4502 return Chain;
4503}
4504
4505SDValue SITargetLowering::LowerRETURNADDR(SDValue Op,
4506 SelectionDAG &DAG) const {
4507 MVT VT = Op.getSimpleValueType();
4508 SDLoc DL(Op);
4509 // Checking the depth
4510 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0)
4511 return DAG.getConstant(0, DL, VT);
4512
4513 MachineFunction &MF = DAG.getMachineFunction();
4514 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4515 // Check for kernel and shader functions
4516 if (Info->isEntryFunction())
4517 return DAG.getConstant(0, DL, VT);
4518
4519 MachineFrameInfo &MFI = MF.getFrameInfo();
4520 // There is a call to @llvm.returnaddress in this function
4521 MFI.setReturnAddressIsTaken(true);
4522
4523 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
4524 // Get the return address reg and mark it as an implicit live-in
4525 unsigned Reg = MF.addLiveIn(TRI->getReturnAddressReg(MF), getRegClassFor(VT, Op.getNode()->isDivergent()));
4526
4527 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4528}
4529
4530SDValue SITargetLowering::getFPExtOrFPTrunc(SelectionDAG &DAG,
4531 SDValue Op,
4532 const SDLoc &DL,
4533 EVT VT) const {
4534 return Op.getValueType().bitsLE(VT) ?
4535 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) :
4536 DAG.getNode(ISD::FTRUNC, DL, VT, Op);
4537}
4538
4539SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
4540 assert(Op.getValueType() == MVT::f16 &&((Op.getValueType() == MVT::f16 && "Do not know how to custom lower FP_ROUND for non-f16 type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4541, __PRETTY_FUNCTION__))
4541 "Do not know how to custom lower FP_ROUND for non-f16 type")((Op.getValueType() == MVT::f16 && "Do not know how to custom lower FP_ROUND for non-f16 type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::f16 && \"Do not know how to custom lower FP_ROUND for non-f16 type\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4541, __PRETTY_FUNCTION__))
;
4542
4543 SDValue Src = Op.getOperand(0);
4544 EVT SrcVT = Src.getValueType();
4545 if (SrcVT != MVT::f64)
4546 return Op;
4547
4548 SDLoc DL(Op);
4549
4550 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);
4551 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToFp16);
4552 return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);
4553}
4554
4555SDValue SITargetLowering::lowerFMINNUM_FMAXNUM(SDValue Op,
4556 SelectionDAG &DAG) const {
4557 EVT VT = Op.getValueType();
4558 const MachineFunction &MF = DAG.getMachineFunction();
4559 const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4560 bool IsIEEEMode = Info->getMode().IEEE;
4561
4562 // FIXME: Assert during eslection that this is only selected for
4563 // ieee_mode. Currently a combine can produce the ieee version for non-ieee
4564 // mode functions, but this happens to be OK since it's only done in cases
4565 // where there is known no sNaN.
4566 if (IsIEEEMode)
4567 return expandFMINNUM_FMAXNUM(Op.getNode(), DAG);
4568
4569 if (VT == MVT::v4f16)
4570 return splitBinaryVectorOp(Op, DAG);
4571 return Op;
4572}
4573
4574SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
4575 SDLoc SL(Op);
4576 SDValue Chain = Op.getOperand(0);
4577
4578 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
4579 !Subtarget->isTrapHandlerEnabled())
4580 return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain);
4581
4582 MachineFunction &MF = DAG.getMachineFunction();
4583 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4584 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
4585 assert(UserSGPR != AMDGPU::NoRegister)((UserSGPR != AMDGPU::NoRegister) ? static_cast<void> (
0) : __assert_fail ("UserSGPR != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4585, __PRETTY_FUNCTION__))
;
4586 SDValue QueuePtr = CreateLiveInRegister(
4587 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
4588 SDValue SGPR01 = DAG.getRegister(AMDGPU::SGPR0_SGPR1, MVT::i64);
4589 SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01,
4590 QueuePtr, SDValue());
4591 SDValue Ops[] = {
4592 ToReg,
4593 DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMTrap, SL, MVT::i16),
4594 SGPR01,
4595 ToReg.getValue(1)
4596 };
4597 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
4598}
4599
4600SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
4601 SDLoc SL(Op);
4602 SDValue Chain = Op.getOperand(0);
4603 MachineFunction &MF = DAG.getMachineFunction();
4604
4605 if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
4606 !Subtarget->isTrapHandlerEnabled()) {
4607 DiagnosticInfoUnsupported NoTrap(MF.getFunction(),
4608 "debugtrap handler not supported",
4609 Op.getDebugLoc(),
4610 DS_Warning);
4611 LLVMContext &Ctx = MF.getFunction().getContext();
4612 Ctx.diagnose(NoTrap);
4613 return Chain;
4614 }
4615
4616 SDValue Ops[] = {
4617 Chain,
4618 DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMDebugTrap, SL, MVT::i16)
4619 };
4620 return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
4621}
4622
4623SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
4624 SelectionDAG &DAG) const {
4625 // FIXME: Use inline constants (src_{shared, private}_base) instead.
4626 if (Subtarget->hasApertureRegs()) {
4627 unsigned Offset = AS == AMDGPUAS::LOCAL_ADDRESS ?
4628 AMDGPU::Hwreg::OFFSET_SRC_SHARED_BASE :
4629 AMDGPU::Hwreg::OFFSET_SRC_PRIVATE_BASE;
4630 unsigned WidthM1 = AS == AMDGPUAS::LOCAL_ADDRESS ?
4631 AMDGPU::Hwreg::WIDTH_M1_SRC_SHARED_BASE :
4632 AMDGPU::Hwreg::WIDTH_M1_SRC_PRIVATE_BASE;
4633 unsigned Encoding =
4634 AMDGPU::Hwreg::ID_MEM_BASES << AMDGPU::Hwreg::ID_SHIFT_ |
4635 Offset << AMDGPU::Hwreg::OFFSET_SHIFT_ |
4636 WidthM1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_;
4637
4638 SDValue EncodingImm = DAG.getTargetConstant(Encoding, DL, MVT::i16);
4639 SDValue ApertureReg = SDValue(
4640 DAG.getMachineNode(AMDGPU::S_GETREG_B32, DL, MVT::i32, EncodingImm), 0);
4641 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32);
4642 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);
4643 }
4644
4645 MachineFunction &MF = DAG.getMachineFunction();
4646 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
4647 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
4648 assert(UserSGPR != AMDGPU::NoRegister)((UserSGPR != AMDGPU::NoRegister) ? static_cast<void> (
0) : __assert_fail ("UserSGPR != AMDGPU::NoRegister", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4648, __PRETTY_FUNCTION__))
;
4649
4650 SDValue QueuePtr = CreateLiveInRegister(
4651 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
4652
4653 // Offset into amd_queue_t for group_segment_aperture_base_hi /
4654 // private_segment_aperture_base_hi.
4655 uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
4656
4657 SDValue Ptr = DAG.getObjectPtrOffset(DL, QueuePtr, StructOffset);
4658
4659 // TODO: Use custom target PseudoSourceValue.
4660 // TODO: We should use the value from the IR intrinsic call, but it might not
4661 // be available and how do we get it?
4662 MachinePointerInfo PtrInfo(AMDGPUAS::CONSTANT_ADDRESS);
4663 return DAG.getLoad(MVT::i32, DL, QueuePtr.getValue(1), Ptr, PtrInfo,
4664 MinAlign(64, StructOffset),
4665 MachineMemOperand::MODereferenceable |
4666 MachineMemOperand::MOInvariant);
4667}
4668
4669SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
4670 SelectionDAG &DAG) const {
4671 SDLoc SL(Op);
4672 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
4673
4674 SDValue Src = ASC->getOperand(0);
4675 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64);
4676
4677 const AMDGPUTargetMachine &TM =
4678 static_cast<const AMDGPUTargetMachine &>(getTargetMachine());
4679
4680 // flat -> local/private
4681 if (ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
4682 unsigned DestAS = ASC->getDestAddressSpace();
4683
4684 if (DestAS == AMDGPUAS::LOCAL_ADDRESS ||
4685 DestAS == AMDGPUAS::PRIVATE_ADDRESS) {
4686 unsigned NullVal = TM.getNullPointerValue(DestAS);
4687 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
4688 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE);
4689 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
4690
4691 return DAG.getNode(ISD::SELECT, SL, MVT::i32,
4692 NonNull, Ptr, SegmentNullPtr);
4693 }
4694 }
4695
4696 // local/private -> flat
4697 if (ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
4698 unsigned SrcAS = ASC->getSrcAddressSpace();
4699
4700 if (SrcAS == AMDGPUAS::LOCAL_ADDRESS ||
4701 SrcAS == AMDGPUAS::PRIVATE_ADDRESS) {
4702 unsigned NullVal = TM.getNullPointerValue(SrcAS);
4703 SDValue SegmentNullPtr = DAG.getConstant(NullVal, SL, MVT::i32);
4704
4705 SDValue NonNull
4706 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE);
4707
4708 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), SL, DAG);
4709 SDValue CvtPtr
4710 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture);
4711
4712 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull,
4713 DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr),
4714 FlatNullPtr);
4715 }
4716 }
4717
4718 // global <-> flat are no-ops and never emitted.
4719
4720 const MachineFunction &MF = DAG.getMachineFunction();
4721 DiagnosticInfoUnsupported InvalidAddrSpaceCast(
4722 MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc());
4723 DAG.getContext()->diagnose(InvalidAddrSpaceCast);
4724
4725 return DAG.getUNDEF(ASC->getValueType(0));
4726}
4727
4728// This lowers an INSERT_SUBVECTOR by extracting the individual elements from
4729// the small vector and inserting them into the big vector. That is better than
4730// the default expansion of doing it via a stack slot. Even though the use of
4731// the stack slot would be optimized away afterwards, the stack slot itself
4732// remains.
4733SDValue SITargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
4734 SelectionDAG &DAG) const {
4735 SDValue Vec = Op.getOperand(0);
4736 SDValue Ins = Op.getOperand(1);
4737 SDValue Idx = Op.getOperand(2);
4738 EVT VecVT = Vec.getValueType();
4739 EVT InsVT = Ins.getValueType();
4740 EVT EltVT = VecVT.getVectorElementType();
4741 unsigned InsNumElts = InsVT.getVectorNumElements();
4742 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4743 SDLoc SL(Op);
4744
4745 for (unsigned I = 0; I != InsNumElts; ++I) {
4746 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT, Ins,
4747 DAG.getConstant(I, SL, MVT::i32));
4748 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, VecVT, Vec, Elt,
4749 DAG.getConstant(IdxVal + I, SL, MVT::i32));
4750 }
4751 return Vec;
4752}
4753
4754SDValue SITargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4755 SelectionDAG &DAG) const {
4756 SDValue Vec = Op.getOperand(0);
4757 SDValue InsVal = Op.getOperand(1);
4758 SDValue Idx = Op.getOperand(2);
4759 EVT VecVT = Vec.getValueType();
4760 EVT EltVT = VecVT.getVectorElementType();
4761 unsigned VecSize = VecVT.getSizeInBits();
4762 unsigned EltSize = EltVT.getSizeInBits();
4763
4764
4765 assert(VecSize <= 64)((VecSize <= 64) ? static_cast<void> (0) : __assert_fail
("VecSize <= 64", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4765, __PRETTY_FUNCTION__))
;
4766
4767 unsigned NumElts = VecVT.getVectorNumElements();
4768 SDLoc SL(Op);
4769 auto KIdx = dyn_cast<ConstantSDNode>(Idx);
4770
4771 if (NumElts == 4 && EltSize == 16 && KIdx) {
4772 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Vec);
4773
4774 SDValue LoHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
4775 DAG.getConstant(0, SL, MVT::i32));
4776 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec,
4777 DAG.getConstant(1, SL, MVT::i32));
4778
4779 SDValue LoVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, LoHalf);
4780 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf);
4781
4782 unsigned Idx = KIdx->getZExtValue();
4783 bool InsertLo = Idx < 2;
4784 SDValue InsHalf = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, MVT::v2i16,
4785 InsertLo ? LoVec : HiVec,
4786 DAG.getNode(ISD::BITCAST, SL, MVT::i16, InsVal),
4787 DAG.getConstant(InsertLo ? Idx : (Idx - 2), SL, MVT::i32));
4788
4789 InsHalf = DAG.getNode(ISD::BITCAST, SL, MVT::i32, InsHalf);
4790
4791 SDValue Concat = InsertLo ?
4792 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) :
4793 DAG.getBuildVector(MVT::v2i32, SL, { LoHalf, InsHalf });
4794
4795 return DAG.getNode(ISD::BITCAST, SL, VecVT, Concat);
4796 }
4797
4798 if (isa<ConstantSDNode>(Idx))
4799 return SDValue();
4800
4801 MVT IntVT = MVT::getIntegerVT(VecSize);
4802
4803 // Avoid stack access for dynamic indexing.
4804 // v_bfi_b32 (v_bfm_b32 16, (shl idx, 16)), val, vec
4805
4806 // Create a congruent vector with the target value in each element so that
4807 // the required element can be masked and ORed into the target vector.
4808 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT,
4809 DAG.getSplatBuildVector(VecVT, SL, InsVal));
4810
4811 assert(isPowerOf2_32(EltSize))((isPowerOf2_32(EltSize)) ? static_cast<void> (0) : __assert_fail
("isPowerOf2_32(EltSize)", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4811, __PRETTY_FUNCTION__))
;
4812 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
4813
4814 // Convert vector index to bit-index.
4815 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
4816
4817 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
4818 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT,
4819 DAG.getConstant(0xffff, SL, IntVT),
4820 ScaledIdx);
4821
4822 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal);
4823 SDValue RHS = DAG.getNode(ISD::AND, SL, IntVT,
4824 DAG.getNOT(SL, BFM, IntVT), BCVec);
4825
4826 SDValue BFI = DAG.getNode(ISD::OR, SL, IntVT, LHS, RHS);
4827 return DAG.getNode(ISD::BITCAST, SL, VecVT, BFI);
4828}
4829
4830SDValue SITargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4831 SelectionDAG &DAG) const {
4832 SDLoc SL(Op);
4833
4834 EVT ResultVT = Op.getValueType();
4835 SDValue Vec = Op.getOperand(0);
4836 SDValue Idx = Op.getOperand(1);
4837 EVT VecVT = Vec.getValueType();
4838 unsigned VecSize = VecVT.getSizeInBits();
4839 EVT EltVT = VecVT.getVectorElementType();
4840 assert(VecSize <= 64)((VecSize <= 64) ? static_cast<void> (0) : __assert_fail
("VecSize <= 64", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4840, __PRETTY_FUNCTION__))
;
4841
4842 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
4843
4844 // Make sure we do any optimizations that will make it easier to fold
4845 // source modifiers before obscuring it with bit operations.
4846
4847 // XXX - Why doesn't this get called when vector_shuffle is expanded?
4848 if (SDValue Combined = performExtractVectorEltCombine(Op.getNode(), DCI))
4849 return Combined;
4850
4851 unsigned EltSize = EltVT.getSizeInBits();
4852 assert(isPowerOf2_32(EltSize))((isPowerOf2_32(EltSize)) ? static_cast<void> (0) : __assert_fail
("isPowerOf2_32(EltSize)", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4852, __PRETTY_FUNCTION__))
;
4853
4854 MVT IntVT = MVT::getIntegerVT(VecSize);
4855 SDValue ScaleFactor = DAG.getConstant(Log2_32(EltSize), SL, MVT::i32);
4856
4857 // Convert vector index to bit-index (* EltSize)
4858 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor);
4859
4860 SDValue BC = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec);
4861 SDValue Elt = DAG.getNode(ISD::SRL, SL, IntVT, BC, ScaledIdx);
4862
4863 if (ResultVT == MVT::f16) {
4864 SDValue Result = DAG.getNode(ISD::TRUNCATE, SL, MVT::i16, Elt);
4865 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result);
4866 }
4867
4868 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT);
4869}
4870
4871static bool elementPairIsContiguous(ArrayRef<int> Mask, int Elt) {
4872 assert(Elt % 2 == 0)((Elt % 2 == 0) ? static_cast<void> (0) : __assert_fail
("Elt % 2 == 0", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4872, __PRETTY_FUNCTION__))
;
4873 return Mask[Elt + 1] == Mask[Elt] + 1 && (Mask[Elt] % 2 == 0);
4874}
4875
4876SDValue SITargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4877 SelectionDAG &DAG) const {
4878 SDLoc SL(Op);
4879 EVT ResultVT = Op.getValueType();
4880 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
4881
4882 EVT PackVT = ResultVT.isInteger() ? MVT::v2i16 : MVT::v2f16;
4883 EVT EltVT = PackVT.getVectorElementType();
4884 int SrcNumElts = Op.getOperand(0).getValueType().getVectorNumElements();
4885
4886 // vector_shuffle <0,1,6,7> lhs, rhs
4887 // -> concat_vectors (extract_subvector lhs, 0), (extract_subvector rhs, 2)
4888 //
4889 // vector_shuffle <6,7,2,3> lhs, rhs
4890 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 2)
4891 //
4892 // vector_shuffle <6,7,0,1> lhs, rhs
4893 // -> concat_vectors (extract_subvector rhs, 2), (extract_subvector lhs, 0)
4894
4895 // Avoid scalarizing when both halves are reading from consecutive elements.
4896 SmallVector<SDValue, 4> Pieces;
4897 for (int I = 0, N = ResultVT.getVectorNumElements(); I != N; I += 2) {
4898 if (elementPairIsContiguous(SVN->getMask(), I)) {
4899 const int Idx = SVN->getMaskElt(I);
4900 int VecIdx = Idx < SrcNumElts ? 0 : 1;
4901 int EltIdx = Idx < SrcNumElts ? Idx : Idx - SrcNumElts;
4902 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL,
4903 PackVT, SVN->getOperand(VecIdx),
4904 DAG.getConstant(EltIdx, SL, MVT::i32));
4905 Pieces.push_back(SubVec);
4906 } else {
4907 const int Idx0 = SVN->getMaskElt(I);
4908 const int Idx1 = SVN->getMaskElt(I + 1);
4909 int VecIdx0 = Idx0 < SrcNumElts ? 0 : 1;
4910 int VecIdx1 = Idx1 < SrcNumElts ? 0 : 1;
4911 int EltIdx0 = Idx0 < SrcNumElts ? Idx0 : Idx0 - SrcNumElts;
4912 int EltIdx1 = Idx1 < SrcNumElts ? Idx1 : Idx1 - SrcNumElts;
4913
4914 SDValue Vec0 = SVN->getOperand(VecIdx0);
4915 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
4916 Vec0, DAG.getConstant(EltIdx0, SL, MVT::i32));
4917
4918 SDValue Vec1 = SVN->getOperand(VecIdx1);
4919 SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
4920 Vec1, DAG.getConstant(EltIdx1, SL, MVT::i32));
4921 Pieces.push_back(DAG.getBuildVector(PackVT, SL, { Elt0, Elt1 }));
4922 }
4923 }
4924
4925 return DAG.getNode(ISD::CONCAT_VECTORS, SL, ResultVT, Pieces);
4926}
4927
4928SDValue SITargetLowering::lowerBUILD_VECTOR(SDValue Op,
4929 SelectionDAG &DAG) const {
4930 SDLoc SL(Op);
4931 EVT VT = Op.getValueType();
4932
4933 if (VT == MVT::v4i16 || VT == MVT::v4f16) {
4934 EVT HalfVT = MVT::getVectorVT(VT.getVectorElementType().getSimpleVT(), 2);
4935
4936 // Turn into pair of packed build_vectors.
4937 // TODO: Special case for constants that can be materialized with s_mov_b64.
4938 SDValue Lo = DAG.getBuildVector(HalfVT, SL,
4939 { Op.getOperand(0), Op.getOperand(1) });
4940 SDValue Hi = DAG.getBuildVector(HalfVT, SL,
4941 { Op.getOperand(2), Op.getOperand(3) });
4942
4943 SDValue CastLo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Lo);
4944 SDValue CastHi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Hi);
4945
4946 SDValue Blend = DAG.getBuildVector(MVT::v2i32, SL, { CastLo, CastHi });
4947 return DAG.getNode(ISD::BITCAST, SL, VT, Blend);
4948 }
4949
4950 assert(VT == MVT::v2f16 || VT == MVT::v2i16)((VT == MVT::v2f16 || VT == MVT::v2i16) ? static_cast<void
> (0) : __assert_fail ("VT == MVT::v2f16 || VT == MVT::v2i16"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4950, __PRETTY_FUNCTION__))
;
4951 assert(!Subtarget->hasVOP3PInsts() && "this should be legal")((!Subtarget->hasVOP3PInsts() && "this should be legal"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget->hasVOP3PInsts() && \"this should be legal\""
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 4951, __PRETTY_FUNCTION__))
;
4952
4953 SDValue Lo = Op.getOperand(0);
4954 SDValue Hi = Op.getOperand(1);
4955
4956 // Avoid adding defined bits with the zero_extend.
4957 if (Hi.isUndef()) {
4958 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
4959 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo);
4960 return DAG.getNode(ISD::BITCAST, SL, VT, ExtLo);
4961 }
4962
4963 Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Hi);
4964 Hi = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Hi);
4965
4966 SDValue ShlHi = DAG.getNode(ISD::SHL, SL, MVT::i32, Hi,
4967 DAG.getConstant(16, SL, MVT::i32));
4968 if (Lo.isUndef())
4969 return DAG.getNode(ISD::BITCAST, SL, VT, ShlHi);
4970
4971 Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i16, Lo);
4972 Lo = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Lo);
4973
4974 SDValue Or = DAG.getNode(ISD::OR, SL, MVT::i32, Lo, ShlHi);
4975 return DAG.getNode(ISD::BITCAST, SL, VT, Or);
4976}
4977
4978bool
4979SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4980 // We can fold offsets for anything that doesn't require a GOT relocation.
4981 return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
4982 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS ||
4983 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) &&
4984 !shouldEmitGOTReloc(GA->getGlobal());
4985}
4986
4987static SDValue
4988buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
4989 const SDLoc &DL, unsigned Offset, EVT PtrVT,
4990 unsigned GAFlags = SIInstrInfo::MO_NONE) {
4991 // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
4992 // lowered to the following code sequence:
4993 //
4994 // For constant address space:
4995 // s_getpc_b64 s[0:1]
4996 // s_add_u32 s0, s0, $symbol
4997 // s_addc_u32 s1, s1, 0
4998 //
4999 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5000 // a fixup or relocation is emitted to replace $symbol with a literal
5001 // constant, which is a pc-relative offset from the encoding of the $symbol
5002 // operand to the global variable.
5003 //
5004 // For global address space:
5005 // s_getpc_b64 s[0:1]
5006 // s_add_u32 s0, s0, $symbol@{gotpc}rel32@lo
5007 // s_addc_u32 s1, s1, $symbol@{gotpc}rel32@hi
5008 //
5009 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
5010 // fixups or relocations are emitted to replace $symbol@*@lo and
5011 // $symbol@*@hi with lower 32 bits and higher 32 bits of a literal constant,
5012 // which is a 64-bit pc-relative offset from the encoding of the $symbol
5013 // operand to the global variable.
5014 //
5015 // What we want here is an offset from the value returned by s_getpc
5016 // (which is the address of the s_add_u32 instruction) to the global
5017 // variable, but since the encoding of $symbol starts 4 bytes after the start
5018 // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
5019 // small. This requires us to add 4 to the global variable offset in order to
5020 // compute the correct address.
5021 SDValue PtrLo =
5022 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags);
5023 SDValue PtrHi;
5024 if (GAFlags == SIInstrInfo::MO_NONE) {
5025 PtrHi = DAG.getTargetConstant(0, DL, MVT::i32);
5026 } else {
5027 PtrHi =
5028 DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags + 1);
5029 }
5030 return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, PtrLo, PtrHi);
5031}
5032
5033SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
5034 SDValue Op,
5035 SelectionDAG &DAG) const {
5036 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
5037 const GlobalValue *GV = GSD->getGlobal();
5038 if ((GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
5039 shouldUseLDSConstAddress(GV)) ||
5040 GSD->getAddressSpace() == AMDGPUAS::REGION_ADDRESS ||
5041 GSD->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS)
5042 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
5043
5044 SDLoc DL(GSD);
5045 EVT PtrVT = Op.getValueType();
5046
5047 if (GSD->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
5048 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, GSD->getOffset(),
5049 SIInstrInfo::MO_ABS32_LO);
5050 return DAG.getNode(AMDGPUISD::LDS, DL, MVT::i32, GA);
5051 }
5052
5053 if (shouldEmitFixup(GV))
5054 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
5055 else if (shouldEmitPCReloc(GV))
5056 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
5057 SIInstrInfo::MO_REL32);
5058
5059 SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
5060 SIInstrInfo::MO_GOTPCREL32);
5061
5062 Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
5063 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
5064 const DataLayout &DataLayout = DAG.getDataLayout();
5065 unsigned Align = DataLayout.getABITypeAlignment(PtrTy);
5066 MachinePointerInfo PtrInfo
5067 = MachinePointerInfo::getGOT(DAG.getMachineFunction());
5068
5069 return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Align,
5070 MachineMemOperand::MODereferenceable |
5071 MachineMemOperand::MOInvariant);
5072}
5073
5074SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
5075 const SDLoc &DL, SDValue V) const {
5076 // We can't use S_MOV_B32 directly, because there is no way to specify m0 as
5077 // the destination register.
5078 //
5079 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
5080 // so we will end up with redundant moves to m0.
5081 //
5082 // We use a pseudo to ensure we emit s_mov_b32 with m0 as the direct result.
5083
5084 // A Null SDValue creates a glue result.
5085 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue,
5086 V, Chain);
5087 return SDValue(M0, 0);
5088}
5089
5090SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
5091 SDValue Op,
5092 MVT VT,
5093 unsigned Offset) const {
5094 SDLoc SL(Op);
5095 SDValue Param = lowerKernargMemParameter(DAG, MVT::i32, MVT::i32, SL,
5096 DAG.getEntryNode(), Offset, 4, false);
5097 // The local size values will have the hi 16-bits as zero.
5098 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
5099 DAG.getValueType(VT));
5100}
5101
5102static SDValue emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5103 EVT VT) {
5104 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5105 "non-hsa intrinsic with hsa target",
5106 DL.getDebugLoc());
5107 DAG.getContext()->diagnose(BadIntrin);
5108 return DAG.getUNDEF(VT);
5109}
5110
5111static SDValue emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL,
5112 EVT VT) {
5113 DiagnosticInfoUnsupported BadIntrin(DAG.getMachineFunction().getFunction(),
5114 "intrinsic not supported on subtarget",
5115 DL.getDebugLoc());
5116 DAG.getContext()->diagnose(BadIntrin);
5117 return DAG.getUNDEF(VT);
5118}
5119
5120static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
5121 ArrayRef<SDValue> Elts) {
5122 assert(!Elts.empty())((!Elts.empty()) ? static_cast<void> (0) : __assert_fail
("!Elts.empty()", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5122, __PRETTY_FUNCTION__))
;
5123 MVT Type;
5124 unsigned NumElts;
5125
5126 if (Elts.size() == 1) {
5127 Type = MVT::f32;
5128 NumElts = 1;
5129 } else if (Elts.size() == 2) {
5130 Type = MVT::v2f32;
5131 NumElts = 2;
5132 } else if (Elts.size() == 3) {
5133 Type = MVT::v3f32;
5134 NumElts = 3;
5135 } else if (Elts.size() <= 4) {
5136 Type = MVT::v4f32;
5137 NumElts = 4;
5138 } else if (Elts.size() <= 8) {
5139 Type = MVT::v8f32;
5140 NumElts = 8;
5141 } else {
5142 assert(Elts.size() <= 16)((Elts.size() <= 16) ? static_cast<void> (0) : __assert_fail
("Elts.size() <= 16", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5142, __PRETTY_FUNCTION__))
;
5143 Type = MVT::v16f32;
5144 NumElts = 16;
5145 }
5146
5147 SmallVector<SDValue, 16> VecElts(NumElts);
5148 for (unsigned i = 0; i < Elts.size(); ++i) {
5149 SDValue Elt = Elts[i];
5150 if (Elt.getValueType() != MVT::f32)
5151 Elt = DAG.getBitcast(MVT::f32, Elt);
5152 VecElts[i] = Elt;
5153 }
5154 for (unsigned i = Elts.size(); i < NumElts; ++i)
5155 VecElts[i] = DAG.getUNDEF(MVT::f32);
5156
5157 if (NumElts == 1)
5158 return VecElts[0];
5159 return DAG.getBuildVector(Type, DL, VecElts);
5160}
5161
5162static bool parseCachePolicy(SDValue CachePolicy, SelectionDAG &DAG,
5163 SDValue *GLC, SDValue *SLC, SDValue *DLC) {
5164 auto CachePolicyConst = cast<ConstantSDNode>(CachePolicy.getNode());
5165
5166 uint64_t Value = CachePolicyConst->getZExtValue();
5167 SDLoc DL(CachePolicy);
5168 if (GLC) {
5169 *GLC = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
5170 Value &= ~(uint64_t)0x1;
5171 }
5172 if (SLC) {
5173 *SLC = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
5174 Value &= ~(uint64_t)0x2;
5175 }
5176 if (DLC) {
5177 *DLC = DAG.getTargetConstant((Value & 0x4) ? 1 : 0, DL, MVT::i32);
5178 Value &= ~(uint64_t)0x4;
5179 }
5180
5181 return Value == 0;
5182}
5183
5184static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT,
5185 SDValue Src, int ExtraElts) {
5186 EVT SrcVT = Src.getValueType();
5187
5188 SmallVector<SDValue, 8> Elts;
5189
5190 if (SrcVT.isVector())
5191 DAG.ExtractVectorElements(Src, Elts);
5192 else
5193 Elts.push_back(Src);
5194
5195 SDValue Undef = DAG.getUNDEF(SrcVT.getScalarType());
5196 while (ExtraElts--)
5197 Elts.push_back(Undef);
5198
5199 return DAG.getBuildVector(CastVT, DL, Elts);
5200}
5201
5202// Re-construct the required return value for a image load intrinsic.
5203// This is more complicated due to the optional use TexFailCtrl which means the required
5204// return type is an aggregate
5205static SDValue constructRetValue(SelectionDAG &DAG,
5206 MachineSDNode *Result,
5207 ArrayRef<EVT> ResultTypes,
5208 bool IsTexFail, bool Unpacked, bool IsD16,
5209 int DMaskPop, int NumVDataDwords,
5210 const SDLoc &DL, LLVMContext &Context) {
5211 // Determine the required return type. This is the same regardless of IsTexFail flag
5212 EVT ReqRetVT = ResultTypes[0];
5213 int ReqRetNumElts = ReqRetVT.isVector() ? ReqRetVT.getVectorNumElements() : 1;
5214 int NumDataDwords = (!IsD16 || (IsD16 && Unpacked)) ?
5215 ReqRetNumElts : (ReqRetNumElts + 1) / 2;
5216
5217 int MaskPopDwords = (!IsD16 || (IsD16 && Unpacked)) ?
5218 DMaskPop : (DMaskPop + 1) / 2;
5219
5220 MVT DataDwordVT = NumDataDwords == 1 ?
5221 MVT::i32 : MVT::getVectorVT(MVT::i32, NumDataDwords);
5222
5223 MVT MaskPopVT = MaskPopDwords == 1 ?
5224 MVT::i32 : MVT::getVectorVT(MVT::i32, MaskPopDwords);
5225
5226 SDValue Data(Result, 0);
5227 SDValue TexFail;
5228
5229 if (IsTexFail) {
5230 SDValue ZeroIdx = DAG.getConstant(0, DL, MVT::i32);
5231 if (MaskPopVT.isVector()) {
5232 Data = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MaskPopVT,
5233 SDValue(Result, 0), ZeroIdx);
5234 } else {
5235 Data = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MaskPopVT,
5236 SDValue(Result, 0), ZeroIdx);
5237 }
5238
5239 TexFail = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
5240 SDValue(Result, 0),
5241 DAG.getConstant(MaskPopDwords, DL, MVT::i32));
5242 }
5243
5244 if (DataDwordVT.isVector())
5245 Data = padEltsToUndef(DAG, DL, DataDwordVT, Data,
5246 NumDataDwords - MaskPopDwords);
5247
5248 if (IsD16)
5249 Data = adjustLoadValueTypeImpl(Data, ReqRetVT, DL, DAG, Unpacked);
5250
5251 if (!ReqRetVT.isVector())
5252 Data = DAG.getNode(ISD::TRUNCATE, DL, ReqRetVT.changeTypeToInteger(), Data);
5253
5254 Data = DAG.getNode(ISD::BITCAST, DL, ReqRetVT, Data);
5255
5256 if (TexFail)
5257 return DAG.getMergeValues({Data, TexFail, SDValue(Result, 1)}, DL);
5258
5259 if (Result->getNumValues() == 1)
5260 return Data;
5261
5262 return DAG.getMergeValues({Data, SDValue(Result, 1)}, DL);
5263}
5264
5265static bool parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE,
5266 SDValue *LWE, bool &IsTexFail) {
5267 auto TexFailCtrlConst = cast<ConstantSDNode>(TexFailCtrl.getNode());
5268
5269 uint64_t Value = TexFailCtrlConst->getZExtValue();
5270 if (Value) {
5271 IsTexFail = true;
5272 }
5273
5274 SDLoc DL(TexFailCtrlConst);
5275 *TFE = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
5276 Value &= ~(uint64_t)0x1;
5277 *LWE = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32);
5278 Value &= ~(uint64_t)0x2;
5279
5280 return Value == 0;
5281}
5282
5283SDValue SITargetLowering::lowerImage(SDValue Op,
5284 const AMDGPU::ImageDimIntrinsicInfo *Intr,
5285 SelectionDAG &DAG) const {
5286 SDLoc DL(Op);
5287 MachineFunction &MF = DAG.getMachineFunction();
5288 const GCNSubtarget* ST = &MF.getSubtarget<GCNSubtarget>();
5289 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
5290 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
5291 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfo(Intr->Dim);
5292 const AMDGPU::MIMGLZMappingInfo *LZMappingInfo =
5293 AMDGPU::getMIMGLZMappingInfo(Intr->BaseOpcode);
5294 const AMDGPU::MIMGMIPMappingInfo *MIPMappingInfo =
5295 AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
5296 unsigned IntrOpcode = Intr->BaseOpcode;
5297 bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10;
5298
5299 SmallVector<EVT, 3> ResultTypes(Op->value_begin(), Op->value_end());
5300 SmallVector<EVT, 3> OrigResultTypes(Op->value_begin(), Op->value_end());
5301 bool IsD16 = false;
5302 bool IsA16 = false;
5303 SDValue VData;
5304 int NumVDataDwords;
5305 bool AdjustRetType = false;
5306
5307 unsigned AddrIdx; // Index of first address argument
5308 unsigned DMask;
5309 unsigned DMaskLanes = 0;
5310
5311 if (BaseOpcode->Atomic) {
5312 VData = Op.getOperand(2);
5313
5314 bool Is64Bit = VData.getValueType() == MVT::i64;
5315 if (BaseOpcode->AtomicX2) {
5316 SDValue VData2 = Op.getOperand(3);
5317 VData = DAG.getBuildVector(Is64Bit ? MVT::v2i64 : MVT::v2i32, DL,
5318 {VData, VData2});
5319 if (Is64Bit)
5320 VData = DAG.getBitcast(MVT::v4i32, VData);
5321
5322 ResultTypes[0] = Is64Bit ? MVT::v2i64 : MVT::v2i32;
5323 DMask = Is64Bit ? 0xf : 0x3;
5324 NumVDataDwords = Is64Bit ? 4 : 2;
5325 AddrIdx = 4;
5326 } else {
5327 DMask = Is64Bit ? 0x3 : 0x1;
5328 NumVDataDwords = Is64Bit ? 2 : 1;
5329 AddrIdx = 3;
5330 }
5331 } else {
5332 unsigned DMaskIdx = BaseOpcode->Store ? 3 : isa<MemSDNode>(Op) ? 2 : 1;
5333 auto DMaskConst = cast<ConstantSDNode>(Op.getOperand(DMaskIdx));
5334 DMask = DMaskConst->getZExtValue();
5335 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask);
5336
5337 if (BaseOpcode->Store) {
5338 VData = Op.getOperand(2);
5339
5340 MVT StoreVT = VData.getSimpleValueType();
5341 if (StoreVT.getScalarType() == MVT::f16) {
5342 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
5343 return Op; // D16 is unsupported for this instruction
5344
5345 IsD16 = true;
5346 VData = handleD16VData(VData, DAG);
5347 }
5348
5349 NumVDataDwords = (VData.getValueType().getSizeInBits() + 31) / 32;
5350 } else {
5351 // Work out the num dwords based on the dmask popcount and underlying type
5352 // and whether packing is supported.
5353 MVT LoadVT = ResultTypes[0].getSimpleVT();
5354 if (LoadVT.getScalarType() == MVT::f16) {
5355 if (!Subtarget->hasD16Images() || !BaseOpcode->HasD16)
5356 return Op; // D16 is unsupported for this instruction
5357
5358 IsD16 = true;
5359 }
5360
5361 // Confirm that the return type is large enough for the dmask specified
5362 if ((LoadVT.isVector() && LoadVT.getVectorNumElements() < DMaskLanes) ||
5363 (!LoadVT.isVector() && DMaskLanes > 1))
5364 return Op;
5365
5366 if (IsD16 && !Subtarget->hasUnpackedD16VMem())
5367 NumVDataDwords = (DMaskLanes + 1) / 2;
5368 else
5369 NumVDataDwords = DMaskLanes;
5370
5371 AdjustRetType = true;
5372 }
5373
5374 AddrIdx = DMaskIdx + 1;
5375 }
5376
5377 unsigned NumGradients = BaseOpcode->Gradients ? DimInfo->NumGradients : 0;
5378 unsigned NumCoords = BaseOpcode->Coordinates ? DimInfo->NumCoords : 0;
5379 unsigned NumLCM = BaseOpcode->LodOrClampOrMip ? 1 : 0;
5380 unsigned NumVAddrs = BaseOpcode->NumExtraArgs + NumGradients +
5381 NumCoords + NumLCM;
5382 unsigned NumMIVAddrs = NumVAddrs;
5383
5384 SmallVector<SDValue, 4> VAddrs;
5385
5386 // Optimize _L to _LZ when _L is zero
5387 if (LZMappingInfo) {
5388 if (auto ConstantLod =
5389 dyn_cast<ConstantFPSDNode>(Op.getOperand(AddrIdx+NumVAddrs-1))) {
5390 if (ConstantLod->isZero() || ConstantLod->isNegative()) {
5391 IntrOpcode = LZMappingInfo->LZ; // set new opcode to _lz variant of _l
5392 NumMIVAddrs--; // remove 'lod'
5393 }
5394 }
5395 }
5396
5397 // Optimize _mip away, when 'lod' is zero
5398 if (MIPMappingInfo) {
5399 if (auto ConstantLod =
5400 dyn_cast<ConstantSDNode>(Op.getOperand(AddrIdx+NumVAddrs-1))) {
5401 if (ConstantLod->isNullValue()) {
5402 IntrOpcode = MIPMappingInfo->NONMIP; // set new opcode to variant without _mip
5403 NumMIVAddrs--; // remove 'lod'
5404 }
5405 }
5406 }
5407
5408 // Check for 16 bit addresses and pack if true.
5409 unsigned DimIdx = AddrIdx + BaseOpcode->NumExtraArgs;
5410 MVT VAddrVT = Op.getOperand(DimIdx).getSimpleValueType();
5411 const MVT VAddrScalarVT = VAddrVT.getScalarType();
5412 if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16))) {
5413 // Illegal to use a16 images
5414 if (!ST->hasFeature(AMDGPU::FeatureR128A16) && !ST->hasFeature(AMDGPU::FeatureGFX10A16))
5415 return Op;
5416
5417 IsA16 = true;
5418 const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
5419 for (unsigned i = AddrIdx; i < (AddrIdx + NumMIVAddrs); ++i) {
5420 SDValue AddrLo;
5421 // Push back extra arguments.
5422 if (i < DimIdx) {
5423 AddrLo = Op.getOperand(i);
5424 } else {
5425 // Dz/dh, dz/dv and the last odd coord are packed with undef. Also,
5426 // in 1D, derivatives dx/dh and dx/dv are packed with undef.
5427 if (((i + 1) >= (AddrIdx + NumMIVAddrs)) ||
5428 ((NumGradients / 2) % 2 == 1 &&
5429 (i == DimIdx + (NumGradients / 2) - 1 ||
5430 i == DimIdx + NumGradients - 1))) {
5431 AddrLo = Op.getOperand(i);
5432 if (AddrLo.getValueType() != MVT::i16)
5433 AddrLo = DAG.getBitcast(MVT::i16, Op.getOperand(i));
5434 AddrLo = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, AddrLo);
5435 } else {
5436 AddrLo = DAG.getBuildVector(VectorVT, DL,
5437 {Op.getOperand(i), Op.getOperand(i + 1)});
5438 i++;
5439 }
5440 AddrLo = DAG.getBitcast(MVT::f32, AddrLo);
5441 }
5442 VAddrs.push_back(AddrLo);
5443 }
5444 } else {
5445 for (unsigned i = 0; i < NumMIVAddrs; ++i)
5446 VAddrs.push_back(Op.getOperand(AddrIdx + i));
5447 }
5448
5449 // If the register allocator cannot place the address registers contiguously
5450 // without introducing moves, then using the non-sequential address encoding
5451 // is always preferable, since it saves VALU instructions and is usually a
5452 // wash in terms of code size or even better.
5453 //
5454 // However, we currently have no way of hinting to the register allocator that
5455 // MIMG addresses should be placed contiguously when it is possible to do so,
5456 // so force non-NSA for the common 2-address case as a heuristic.
5457 //
5458 // SIShrinkInstructions will convert NSA encodings to non-NSA after register
5459 // allocation when possible.
5460 bool UseNSA =
5461 ST->hasFeature(AMDGPU::FeatureNSAEncoding) && VAddrs.size() >= 3;
5462 SDValue VAddr;
5463 if (!UseNSA)
5464 VAddr = getBuildDwordsVector(DAG, DL, VAddrs);
5465
5466 SDValue True = DAG.getTargetConstant(1, DL, MVT::i1);
5467 SDValue False = DAG.getTargetConstant(0, DL, MVT::i1);
5468 unsigned CtrlIdx; // Index of texfailctrl argument
5469 SDValue Unorm;
5470 if (!BaseOpcode->Sampler) {
5471 Unorm = True;
5472 CtrlIdx = AddrIdx + NumVAddrs + 1;
5473 } else {
5474 auto UnormConst =
5475 cast<ConstantSDNode>(Op.getOperand(AddrIdx + NumVAddrs + 2));
5476
5477 Unorm = UnormConst->getZExtValue() ? True : False;
5478 CtrlIdx = AddrIdx + NumVAddrs + 3;
5479 }
5480
5481 SDValue TFE;
5482 SDValue LWE;
5483 SDValue TexFail = Op.getOperand(CtrlIdx);
5484 bool IsTexFail = false;
5485 if (!parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail))
5486 return Op;
5487
5488 if (IsTexFail) {
5489 if (!DMaskLanes) {
5490 // Expecting to get an error flag since TFC is on - and dmask is 0
5491 // Force dmask to be at least 1 otherwise the instruction will fail
5492 DMask = 0x1;
5493 DMaskLanes = 1;
5494 NumVDataDwords = 1;
5495 }
5496 NumVDataDwords += 1;
5497 AdjustRetType = true;
5498 }
5499
5500 // Has something earlier tagged that the return type needs adjusting
5501 // This happens if the instruction is a load or has set TexFailCtrl flags
5502 if (AdjustRetType) {
5503 // NumVDataDwords reflects the true number of dwords required in the return type
5504 if (DMaskLanes == 0 && !BaseOpcode->Store) {
5505 // This is a no-op load. This can be eliminated
5506 SDValue Undef = DAG.getUNDEF(Op.getValueType());
5507 if (isa<MemSDNode>(Op))
5508 return DAG.getMergeValues({Undef, Op.getOperand(0)}, DL);
5509 return Undef;
5510 }
5511
5512 EVT NewVT = NumVDataDwords > 1 ?
5513 EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumVDataDwords)
5514 : MVT::i32;
5515
5516 ResultTypes[0] = NewVT;
5517 if (ResultTypes.size() == 3) {
5518 // Original result was aggregate type used for TexFailCtrl results
5519 // The actual instruction returns as a vector type which has now been
5520 // created. Remove the aggregate result.
5521 ResultTypes.erase(&ResultTypes[1]);
5522 }
5523 }
5524
5525 SDValue GLC;
5526 SDValue SLC;
5527 SDValue DLC;
5528 if (BaseOpcode->Atomic) {
5529 GLC = True; // TODO no-return optimization
5530 if (!parseCachePolicy(Op.getOperand(CtrlIdx + 1), DAG, nullptr, &SLC,
5531 IsGFX10 ? &DLC : nullptr))
5532 return Op;
5533 } else {
5534 if (!parseCachePolicy(Op.getOperand(CtrlIdx + 1), DAG, &GLC, &SLC,
5535 IsGFX10 ? &DLC : nullptr))
5536 return Op;
5537 }
5538
5539 SmallVector<SDValue, 26> Ops;
5540 if (BaseOpcode->Store || BaseOpcode->Atomic)
5541 Ops.push_back(VData); // vdata
5542 if (UseNSA) {
5543 for (const SDValue &Addr : VAddrs)
5544 Ops.push_back(Addr);
5545 } else {
5546 Ops.push_back(VAddr);
5547 }
5548 Ops.push_back(Op.getOperand(AddrIdx + NumVAddrs)); // rsrc
5549 if (BaseOpcode->Sampler)
5550 Ops.push_back(Op.getOperand(AddrIdx + NumVAddrs + 1)); // sampler
5551 Ops.push_back(DAG.getTargetConstant(DMask, DL, MVT::i32));
5552 if (IsGFX10)
5553 Ops.push_back(DAG.getTargetConstant(DimInfo->Encoding, DL, MVT::i32));
5554 Ops.push_back(Unorm);
5555 if (IsGFX10)
5556 Ops.push_back(DLC);
5557 Ops.push_back(GLC);
5558 Ops.push_back(SLC);
5559 Ops.push_back(IsA16 && // r128, a16 for gfx9
5560 ST->hasFeature(AMDGPU::FeatureR128A16) ? True : False);
5561 if (IsGFX10)
5562 Ops.push_back(IsA16 ? True : False);
5563 Ops.push_back(TFE);
5564 Ops.push_back(LWE);
5565 if (!IsGFX10)
5566 Ops.push_back(DimInfo->DA ? True : False);
5567 if (BaseOpcode->HasD16)
5568 Ops.push_back(IsD16 ? True : False);
5569 if (isa<MemSDNode>(Op))
5570 Ops.push_back(Op.getOperand(0)); // chain
5571
5572 int NumVAddrDwords =
5573 UseNSA ? VAddrs.size() : VAddr.getValueType().getSizeInBits() / 32;
5574 int Opcode = -1;
5575
5576 if (IsGFX10) {
5577 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode,
5578 UseNSA ? AMDGPU::MIMGEncGfx10NSA
5579 : AMDGPU::MIMGEncGfx10Default,
5580 NumVDataDwords, NumVAddrDwords);
5581 } else {
5582 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5583 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx8,
5584 NumVDataDwords, NumVAddrDwords);
5585 if (Opcode == -1)
5586 Opcode = AMDGPU::getMIMGOpcode(IntrOpcode, AMDGPU::MIMGEncGfx6,
5587 NumVDataDwords, NumVAddrDwords);
5588 }
5589 assert(Opcode != -1)((Opcode != -1) ? static_cast<void> (0) : __assert_fail
("Opcode != -1", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5589, __PRETTY_FUNCTION__))
;
5590
5591 MachineSDNode *NewNode = DAG.getMachineNode(Opcode, DL, ResultTypes, Ops);
5592 if (auto MemOp = dyn_cast<MemSDNode>(Op)) {
5593 MachineMemOperand *MemRef = MemOp->getMemOperand();
5594 DAG.setNodeMemRefs(NewNode, {MemRef});
5595 }
5596
5597 if (BaseOpcode->AtomicX2) {
5598 SmallVector<SDValue, 1> Elt;
5599 DAG.ExtractVectorElements(SDValue(NewNode, 0), Elt, 0, 1);
5600 return DAG.getMergeValues({Elt[0], SDValue(NewNode, 1)}, DL);
5601 } else if (!BaseOpcode->Store) {
5602 return constructRetValue(DAG, NewNode,
5603 OrigResultTypes, IsTexFail,
5604 Subtarget->hasUnpackedD16VMem(), IsD16,
5605 DMaskLanes, NumVDataDwords, DL,
5606 *DAG.getContext());
5607 }
5608
5609 return SDValue(NewNode, 0);
5610}
5611
5612SDValue SITargetLowering::lowerSBuffer(EVT VT, SDLoc DL, SDValue Rsrc,
5613 SDValue Offset, SDValue CachePolicy,
5614 SelectionDAG &DAG) const {
5615 MachineFunction &MF = DAG.getMachineFunction();
5616
5617 const DataLayout &DataLayout = DAG.getDataLayout();
5618 unsigned Align =
5619 DataLayout.getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5620
5621 MachineMemOperand *MMO = MF.getMachineMemOperand(
5622 MachinePointerInfo(),
5623 MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
5624 MachineMemOperand::MOInvariant,
5625 VT.getStoreSize(), Align);
5626
5627 if (!Offset->isDivergent()) {
5628 SDValue Ops[] = {
5629 Rsrc,
5630 Offset, // Offset
5631 CachePolicy
5632 };
5633
5634 // Widen vec3 load to vec4.
5635 if (VT.isVector() && VT.getVectorNumElements() == 3) {
5636 EVT WidenedVT =
5637 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), 4);
5638 auto WidenedOp = DAG.getMemIntrinsicNode(
5639 AMDGPUISD::SBUFFER_LOAD, DL, DAG.getVTList(WidenedVT), Ops, WidenedVT,
5640 MF.getMachineMemOperand(MMO, 0, WidenedVT.getStoreSize()));
5641 auto Subvector = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp,
5642 DAG.getVectorIdxConstant(0, DL));
5643 return Subvector;
5644 }
5645
5646 return DAG.getMemIntrinsicNode(AMDGPUISD::SBUFFER_LOAD, DL,
5647 DAG.getVTList(VT), Ops, VT, MMO);
5648 }
5649
5650 // We have a divergent offset. Emit a MUBUF buffer load instead. We can
5651 // assume that the buffer is unswizzled.
5652 SmallVector<SDValue, 4> Loads;
5653 unsigned NumLoads = 1;
5654 MVT LoadVT = VT.getSimpleVT();
5655 unsigned NumElts = LoadVT.isVector() ? LoadVT.getVectorNumElements() : 1;
5656 assert((LoadVT.getScalarType() == MVT::i32 ||(((LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType
() == MVT::f32)) ? static_cast<void> (0) : __assert_fail
("(LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType() == MVT::f32)"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5657, __PRETTY_FUNCTION__))
5657 LoadVT.getScalarType() == MVT::f32))(((LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType
() == MVT::f32)) ? static_cast<void> (0) : __assert_fail
("(LoadVT.getScalarType() == MVT::i32 || LoadVT.getScalarType() == MVT::f32)"
, "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 5657, __PRETTY_FUNCTION__))
;
5658
5659 if (NumElts == 8 || NumElts == 16) {
5660 NumLoads = NumElts / 4;
5661 LoadVT = MVT::getVectorVT(LoadVT.getScalarType(), 4);
5662 }
5663
5664 SDVTList VTList = DAG.getVTList({LoadVT, MVT::Glue});
5665 SDValue Ops[] = {
5666 DAG.getEntryNode(), // Chain
5667 Rsrc, // rsrc
5668 DAG.getConstant(0, DL, MVT::i32), // vindex
5669 {}, // voffset
5670 {}, // soffset
5671 {}, // offset
5672 CachePolicy, // cachepolicy
5673 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
5674 };
5675
5676 // Use the alignment to ensure that the required offsets will fit into the
5677 // immediate offsets.
5678 setBufferOffsets(Offset, DAG, &Ops[3], NumLoads > 1 ? 16 * NumLoads : 4);
5679
5680 uint64_t InstOffset = cast<ConstantSDNode>(Ops[5])->getZExtValue();
5681 for (unsigned i = 0; i < NumLoads; ++i) {
5682 Ops[5] = DAG.getTargetConstant(InstOffset + 16 * i, DL, MVT::i32);
5683 Loads.push_back(getMemIntrinsicNode(AMDGPUISD::BUFFER_LOAD, DL, VTList, Ops,
5684 LoadVT, MMO, DAG));
5685 }
5686
5687 if (NumElts == 8 || NumElts == 16)
5688 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Loads);
5689
5690 return Loads[0];
5691}
5692
5693SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5694 SelectionDAG &DAG) const {
5695 MachineFunction &MF = DAG.getMachineFunction();
5696 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
5697
5698 EVT VT = Op.getValueType();
5699 SDLoc DL(Op);
5700 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5701
5702 // TODO: Should this propagate fast-math-flags?
5703
5704 switch (IntrinsicID) {
5705 case Intrinsic::amdgcn_implicit_buffer_ptr: {
5706 if (getSubtarget()->isAmdHsaOrMesa(MF.getFunction()))
5707 return emitNonHSAIntrinsicError(DAG, DL, VT);
5708 return getPreloadedValue(DAG, *MFI, VT,
5709 AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR);
5710 }
5711 case Intrinsic::amdgcn_dispatch_ptr:
5712 case Intrinsic::amdgcn_queue_ptr: {
5713 if (!Subtarget->isAmdHsaOrMesa(MF.getFunction())) {
5714 DiagnosticInfoUnsupported BadIntrin(
5715 MF.getFunction(), "unsupported hsa intrinsic without hsa target",
5716 DL.getDebugLoc());
5717 DAG.getContext()->diagnose(BadIntrin);
5718 return DAG.getUNDEF(VT);
5719 }
5720
5721 auto RegID = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ?
5722 AMDGPUFunctionArgInfo::DISPATCH_PTR : AMDGPUFunctionArgInfo::QUEUE_PTR;
5723 return getPreloadedValue(DAG, *MFI, VT, RegID);
5724 }
5725 case Intrinsic::amdgcn_implicitarg_ptr: {
5726 if (MFI->isEntryFunction())
5727 return getImplicitArgPtr(DAG, DL);
5728 return getPreloadedValue(DAG, *MFI, VT,
5729 AMDGPUFunctionArgInfo::IMPLICIT_ARG_PTR);
5730 }
5731 case Intrinsic::amdgcn_kernarg_segment_ptr: {
5732 return getPreloadedValue(DAG, *MFI, VT,
5733 AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
5734 }
5735 case Intrinsic::amdgcn_dispatch_id: {
5736 return getPreloadedValue(DAG, *MFI, VT, AMDGPUFunctionArgInfo::DISPATCH_ID);
5737 }
5738 case Intrinsic::amdgcn_rcp:
5739 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
5740 case Intrinsic::amdgcn_rsq:
5741 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
5742 case Intrinsic::amdgcn_rsq_legacy:
5743 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5744 return emitRemovedIntrinsicError(DAG, DL, VT);
5745
5746 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
5747 case Intrinsic::amdgcn_rcp_legacy:
5748 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5749 return emitRemovedIntrinsicError(DAG, DL, VT);
5750 return DAG.getNode(AMDGPUISD::RCP_LEGACY, DL, VT, Op.getOperand(1));
5751 case Intrinsic::amdgcn_rsq_clamp: {
5752 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
5753 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
5754
5755 Type *Type = VT.getTypeForEVT(*DAG.getContext());
5756 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
5757 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
5758
5759 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
5760 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
5761 DAG.getConstantFP(Max, DL, VT));
5762 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
5763 DAG.getConstantFP(Min, DL, VT));
5764 }
5765 case Intrinsic::r600_read_ngroups_x:
5766 if (Subtarget->isAmdHsaOS())
5767 return emitNonHSAIntrinsicError(DAG, DL, VT);
5768
5769 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5770 SI::KernelInputOffsets::NGROUPS_X, 4, false);
5771 case Intrinsic::r600_read_ngroups_y:
5772 if (Subtarget->isAmdHsaOS())
5773 return emitNonHSAIntrinsicError(DAG, DL, VT);
5774
5775 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5776 SI::KernelInputOffsets::NGROUPS_Y, 4, false);
5777 case Intrinsic::r600_read_ngroups_z:
5778 if (Subtarget->isAmdHsaOS())
5779 return emitNonHSAIntrinsicError(DAG, DL, VT);
5780
5781 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5782 SI::KernelInputOffsets::NGROUPS_Z, 4, false);
5783 case Intrinsic::r600_read_global_size_x:
5784 if (Subtarget->isAmdHsaOS())
5785 return emitNonHSAIntrinsicError(DAG, DL, VT);
5786
5787 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5788 SI::KernelInputOffsets::GLOBAL_SIZE_X, 4, false);
5789 case Intrinsic::r600_read_global_size_y:
5790 if (Subtarget->isAmdHsaOS())
5791 return emitNonHSAIntrinsicError(DAG, DL, VT);
5792
5793 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5794 SI::KernelInputOffsets::GLOBAL_SIZE_Y, 4, false);
5795 case Intrinsic::r600_read_global_size_z:
5796 if (Subtarget->isAmdHsaOS())
5797 return emitNonHSAIntrinsicError(DAG, DL, VT);
5798
5799 return lowerKernargMemParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
5800 SI::KernelInputOffsets::GLOBAL_SIZE_Z, 4, false);
5801 case Intrinsic::r600_read_local_size_x:
5802 if (Subtarget->isAmdHsaOS())
5803 return emitNonHSAIntrinsicError(DAG, DL, VT);
5804
5805 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5806 SI::KernelInputOffsets::LOCAL_SIZE_X);
5807 case Intrinsic::r600_read_local_size_y:
5808 if (Subtarget->isAmdHsaOS())
5809 return emitNonHSAIntrinsicError(DAG, DL, VT);
5810
5811 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5812 SI::KernelInputOffsets::LOCAL_SIZE_Y);
5813 case Intrinsic::r600_read_local_size_z:
5814 if (Subtarget->isAmdHsaOS())
5815 return emitNonHSAIntrinsicError(DAG, DL, VT);
5816
5817 return lowerImplicitZextParam(DAG, Op, MVT::i16,
5818 SI::KernelInputOffsets::LOCAL_SIZE_Z);
5819 case Intrinsic::amdgcn_workgroup_id_x:
5820 return getPreloadedValue(DAG, *MFI, VT,
5821 AMDGPUFunctionArgInfo::WORKGROUP_ID_X);
5822 case Intrinsic::amdgcn_workgroup_id_y:
5823 return getPreloadedValue(DAG, *MFI, VT,
5824 AMDGPUFunctionArgInfo::WORKGROUP_ID_Y);
5825 case Intrinsic::amdgcn_workgroup_id_z:
5826 return getPreloadedValue(DAG, *MFI, VT,
5827 AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
5828 case Intrinsic::amdgcn_workitem_id_x:
5829 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5830 SDLoc(DAG.getEntryNode()),
5831 MFI->getArgInfo().WorkItemIDX);
5832 case Intrinsic::amdgcn_workitem_id_y:
5833 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5834 SDLoc(DAG.getEntryNode()),
5835 MFI->getArgInfo().WorkItemIDY);
5836 case Intrinsic::amdgcn_workitem_id_z:
5837 return loadInputValue(DAG, &AMDGPU::VGPR_32RegClass, MVT::i32,
5838 SDLoc(DAG.getEntryNode()),
5839 MFI->getArgInfo().WorkItemIDZ);
5840 case Intrinsic::amdgcn_wavefrontsize:
5841 return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(),
5842 SDLoc(Op), MVT::i32);
5843 case Intrinsic::amdgcn_s_buffer_load: {
5844 bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10;
5845 SDValue GLC;
5846 SDValue DLC = DAG.getTargetConstant(0, DL, MVT::i1);
5847 if (!parseCachePolicy(Op.getOperand(3), DAG, &GLC, nullptr,
5848 IsGFX10 ? &DLC : nullptr))
5849 return Op;
5850 return lowerSBuffer(VT, DL, Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
5851 DAG);
5852 }
5853 case Intrinsic::amdgcn_fdiv_fast:
5854 return lowerFDIV_FAST(Op, DAG);
5855 case Intrinsic::amdgcn_sin:
5856 return DAG.getNode(AMDGPUISD::SIN_HW, DL, VT, Op.getOperand(1));
5857
5858 case Intrinsic::amdgcn_cos:
5859 return DAG.getNode(AMDGPUISD::COS_HW, DL, VT, Op.getOperand(1));
5860
5861 case Intrinsic::amdgcn_mul_u24:
5862 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT, Op.getOperand(1), Op.getOperand(2));
5863 case Intrinsic::amdgcn_mul_i24:
5864 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT, Op.getOperand(1), Op.getOperand(2));
5865
5866 case Intrinsic::amdgcn_log_clamp: {
5867 if (Subtarget->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS)
5868 return SDValue();
5869
5870 DiagnosticInfoUnsupported BadIntrin(
5871 MF.getFunction(), "intrinsic not supported on subtarget",
5872 DL.getDebugLoc());
5873 DAG.getContext()->diagnose(BadIntrin);
5874 return DAG.getUNDEF(VT);
5875 }
5876 case Intrinsic::amdgcn_ldexp:
5877 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT,
5878 Op.getOperand(1), Op.getOperand(2));
5879
5880 case Intrinsic::amdgcn_fract:
5881 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
5882
5883 case Intrinsic::amdgcn_class:
5884 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
5885 Op.getOperand(1), Op.getOperand(2));
5886 case Intrinsic::amdgcn_div_fmas:
5887 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
5888 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
5889 Op.getOperand(4));
5890
5891 case Intrinsic::amdgcn_div_fixup:
5892 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
5893 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
5894
5895 case Intrinsic::amdgcn_trig_preop:
5896 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
5897 Op.getOperand(1), Op.getOperand(2));
5898 case Intrinsic::amdgcn_div_scale: {
5899 const ConstantSDNode *Param = cast<ConstantSDNode>(Op.getOperand(3));
5900
5901 // Translate to the operands expected by the machine instruction. The
5902 // first parameter must be the same as the first instruction.
5903 SDValue Numerator = Op.getOperand(1);
5904 SDValue Denominator = Op.getOperand(2);
5905
5906 // Note this order is opposite of the machine instruction's operations,
5907 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
5908 // intrinsic has the numerator as the first operand to match a normal
5909 // division operation.
5910
5911 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
5912
5913 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
5914 Denominator, Numerator);
5915 }
5916 case Intrinsic::amdgcn_icmp: {
5917 // There is a Pat that handles this variant, so return it as-is.
5918 if (Op.getOperand(1).getValueType() == MVT::i1 &&
5919 Op.getConstantOperandVal(2) == 0 &&
5920 Op.getConstantOperandVal(3) == ICmpInst::Predicate::ICMP_NE)
5921 return Op;
5922 return lowerICMPIntrinsic(*this, Op.getNode(), DAG);
5923 }
5924 case Intrinsic::amdgcn_fcmp: {
5925 return lowerFCMPIntrinsic(*this, Op.getNode(), DAG);
5926 }
5927 case Intrinsic::amdgcn_fmed3:
5928 return DAG.getNode(AMDGPUISD::FMED3, DL, VT,
5929 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
5930 case Intrinsic::amdgcn_fdot2:
5931 return DAG.getNode(AMDGPUISD::FDOT2, DL, VT,
5932 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
5933 Op.getOperand(4));
5934 case Intrinsic::amdgcn_fmul_legacy:
5935 return DAG.getNode(AMDGPUISD::FMUL_LEGACY, DL, VT,
5936 Op.getOperand(1), Op.getOperand(2));
5937 case Intrinsic::amdgcn_sffbh:
5938 return DAG.getNode(AMDGPUISD::FFBH_I32, DL, VT, Op.getOperand(1));
5939 case Intrinsic::amdgcn_sbfe:
5940 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
5941 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
5942 case Intrinsic::amdgcn_ubfe:
5943 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
5944 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
5945 case Intrinsic::amdgcn_cvt_pkrtz:
5946 case Intrinsic::amdgcn_cvt_pknorm_i16:
5947 case Intrinsic::amdgcn_cvt_pknorm_u16:
5948 case Intrinsic::amdgcn_cvt_pk_i16:
5949 case Intrinsic::amdgcn_cvt_pk_u16: {
5950 // FIXME: Stop adding cast if v2f16/v2i16 are legal.
5951 EVT VT = Op.getValueType();
5952 unsigned Opcode;
5953
5954 if (IntrinsicID == Intrinsic::amdgcn_cvt_pkrtz)
5955 Opcode = AMDGPUISD::CVT_PKRTZ_F16_F32;
5956 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_i16)
5957 Opcode = AMDGPUISD::CVT_PKNORM_I16_F32;
5958 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pknorm_u16)
5959 Opcode = AMDGPUISD::CVT_PKNORM_U16_F32;
5960 else if (IntrinsicID == Intrinsic::amdgcn_cvt_pk_i16)
5961 Opcode = AMDGPUISD::CVT_PK_I16_I32;
5962 else
5963 Opcode = AMDGPUISD::CVT_PK_U16_U32;
5964
5965 if (isTypeLegal(VT))
5966 return DAG.getNode(Opcode, DL, VT, Op.getOperand(1), Op.getOperand(2));
5967
5968 SDValue Node = DAG.getNode(Opcode, DL, MVT::i32,
5969 Op.getOperand(1), Op.getOperand(2));
5970 return DAG.getNode(ISD::BITCAST, DL, VT, Node);
5971 }
5972 case Intrinsic::amdgcn_fmad_ftz:
5973 return DAG.getNode(AMDGPUISD::FMAD_FTZ, DL, VT, Op.getOperand(1),
5974 Op.getOperand(2), Op.getOperand(3));
5975
5976 case Intrinsic::amdgcn_if_break:
5977 return SDValue(DAG.getMachineNode(AMDGPU::SI_IF_BREAK, DL, VT,
5978 Op->getOperand(1), Op->getOperand(2)), 0);
5979
5980 case Intrinsic::amdgcn_groupstaticsize: {
5981 Triple::OSType OS = getTargetMachine().getTargetTriple().getOS();
5982 if (OS == Triple::AMDHSA || OS == Triple::AMDPAL)
5983 return Op;
5984
5985 const Module *M = MF.getFunction().getParent();
5986 const GlobalValue *GV =
5987 M->getNamedValue(Intrinsic::getName(Intrinsic::amdgcn_groupstaticsize));
5988 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0,
5989 SIInstrInfo::MO_ABS32_LO);
5990 return {DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, GA), 0};
5991 }
5992 case Intrinsic::amdgcn_is_shared:
5993 case Intrinsic::amdgcn_is_private: {
5994 SDLoc SL(Op);
5995 unsigned AS = (IntrinsicID == Intrinsic::amdgcn_is_shared) ?
5996 AMDGPUAS::LOCAL_ADDRESS : AMDGPUAS::PRIVATE_ADDRESS;
5997 SDValue Aperture = getSegmentAperture(AS, SL, DAG);
5998 SDValue SrcVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32,
5999 Op.getOperand(1));
6000
6001 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec,
6002 DAG.getConstant(1, SL, MVT::i32));
6003 return DAG.getSetCC(SL, MVT::i1, SrcHi, Aperture, ISD::SETEQ);
6004 }
6005 default:
6006 if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
6007 AMDGPU::getImageDimIntrinsicInfo(IntrinsicID))
6008 return lowerImage(Op, ImageDimIntr, DAG);
6009
6010 return Op;
6011 }
6012}
6013
6014// This function computes an appropriate offset to pass to
6015// MachineMemOperand::setOffset() based on the offset inputs to
6016// an intrinsic. If any of the offsets are non-contstant or
6017// if VIndex is non-zero then this function returns 0. Otherwise,
6018// it returns the sum of VOffset, SOffset, and Offset.
6019static unsigned getBufferOffsetForMMO(SDValue VOffset,
6020 SDValue SOffset,
6021 SDValue Offset,
6022 SDValue VIndex = SDValue()) {
6023
6024 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) ||
6025 !isa<ConstantSDNode>(Offset))
6026 return 0;
6027
6028 if (VIndex) {
6029 if (!isa<ConstantSDNode>(VIndex) || !cast<ConstantSDNode>(VIndex)->isNullValue())
6030 return 0;
6031 }
6032
6033 return cast<ConstantSDNode>(VOffset)->getSExtValue() +
6034 cast<ConstantSDNode>(SOffset)->getSExtValue() +
6035 cast<ConstantSDNode>(Offset)->getSExtValue();
6036}
6037
6038static unsigned getDSShaderTypeValue(const MachineFunction &MF) {
6039 switch (MF.getFunction().getCallingConv()) {
6040 case CallingConv::AMDGPU_PS:
6041 return 1;
6042 case CallingConv::AMDGPU_VS:
6043 return 2;
6044 case CallingConv::AMDGPU_GS:
6045 return 3;
6046 case CallingConv::AMDGPU_HS:
6047 case CallingConv::AMDGPU_LS:
6048 case CallingConv::AMDGPU_ES:
6049 report_fatal_error("ds_ordered_count unsupported for this calling conv");
6050 case CallingConv::AMDGPU_CS:
6051 case CallingConv::AMDGPU_KERNEL:
6052 case CallingConv::C:
6053 case CallingConv::Fast:
6054 default:
6055 // Assume other calling conventions are various compute callable functions
6056 return 0;
6057 }
6058}
6059
6060SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
6061 SelectionDAG &DAG) const {
6062 unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6063 SDLoc DL(Op);
6064
6065 switch (IntrID) {
6066 case Intrinsic::amdgcn_ds_ordered_add:
6067 case Intrinsic::amdgcn_ds_ordered_swap: {
6068 MemSDNode *M = cast<MemSDNode>(Op);
6069 SDValue Chain = M->getOperand(0);
6070 SDValue M0 = M->getOperand(2);
6071 SDValue Value = M->getOperand(3);
6072 unsigned IndexOperand = M->getConstantOperandVal(7);
6073 unsigned WaveRelease = M->getConstantOperandVal(8);
6074 unsigned WaveDone = M->getConstantOperandVal(9);
6075
6076 unsigned OrderedCountIndex = IndexOperand & 0x3f;
6077 IndexOperand &= ~0x3f;
6078 unsigned CountDw = 0;
6079
6080 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10) {
6081 CountDw = (IndexOperand >> 24) & 0xf;
6082 IndexOperand &= ~(0xf << 24);
6083
6084 if (CountDw < 1 || CountDw > 4) {
6085 report_fatal_error(
6086 "ds_ordered_count: dword count must be between 1 and 4");
6087 }
6088 }
6089
6090 if (IndexOperand)
6091 report_fatal_error("ds_ordered_count: bad index operand");
6092
6093 if (WaveDone && !WaveRelease)
6094 report_fatal_error("ds_ordered_count: wave_done requires wave_release");
6095
6096 unsigned Instruction = IntrID == Intrinsic::amdgcn_ds_ordered_add ? 0 : 1;
6097 unsigned ShaderType = getDSShaderTypeValue(DAG.getMachineFunction());
6098 unsigned Offset0 = OrderedCountIndex << 2;
6099 unsigned Offset1 = WaveRelease | (WaveDone << 1) | (ShaderType << 2) |
6100 (Instruction << 4);
6101
6102 if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10)
6103 Offset1 |= (CountDw - 1) << 6;
6104
6105 unsigned Offset = Offset0 | (Offset1 << 8);
6106
6107 SDValue Ops[] = {
6108 Chain,
6109 Value,
6110 DAG.getTargetConstant(Offset, DL, MVT::i16),
6111 copyToM0(DAG, Chain, DL, M0).getValue(1), // Glue
6112 };
6113 return DAG.getMemIntrinsicNode(AMDGPUISD::DS_ORDERED_COUNT, DL,
6114 M->getVTList(), Ops, M->getMemoryVT(),
6115 M->getMemOperand());
6116 }
6117 case Intrinsic::amdgcn_ds_fadd: {
6118 MemSDNode *M = cast<MemSDNode>(Op);
6119 unsigned Opc;
6120 switch (IntrID) {
6121 case Intrinsic::amdgcn_ds_fadd:
6122 Opc = ISD::ATOMIC_LOAD_FADD;
6123 break;
6124 }
6125
6126 return DAG.getAtomic(Opc, SDLoc(Op), M->getMemoryVT(),
6127 M->getOperand(0), M->getOperand(2), M->getOperand(3),
6128 M->getMemOperand());
6129 }
6130 case Intrinsic::amdgcn_atomic_inc:
6131 case Intrinsic::amdgcn_atomic_dec:
6132 case Intrinsic::amdgcn_ds_fmin:
6133 case Intrinsic::amdgcn_ds_fmax: {
6134 MemSDNode *M = cast<MemSDNode>(Op);
6135 unsigned Opc;
6136 switch (IntrID) {
6137 case Intrinsic::amdgcn_atomic_inc:
6138 Opc = AMDGPUISD::ATOMIC_INC;
6139 break;
6140 case Intrinsic::amdgcn_atomic_dec:
6141 Opc = AMDGPUISD::ATOMIC_DEC;
6142 break;
6143 case Intrinsic::amdgcn_ds_fmin:
6144 Opc = AMDGPUISD::ATOMIC_LOAD_FMIN;
6145 break;
6146 case Intrinsic::amdgcn_ds_fmax:
6147 Opc = AMDGPUISD::ATOMIC_LOAD_FMAX;
6148 break;
6149 default:
6150 llvm_unreachable("Unknown intrinsic!")::llvm::llvm_unreachable_internal("Unknown intrinsic!", "/build/llvm-toolchain-snapshot-11~++20200309111110+2c36c23f347/llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
, 6150)
;
6151 }
6152 SDValue Ops[] = {
6153 M->getOperand(0), // Chain
6154 M->getOperand(2), // Ptr
6155 M->getOperand(3) // Value
6156 };
6157
6158 return DAG.getMemIntrinsicNode(Opc, SDLoc(Op), M->getVTList(), Ops,
6159 M->getMemoryVT(), M->getMemOperand());
6160 }
6161 case Intrinsic::amdgcn_buffer_load:
6162 case Intrinsic::amdgcn_buffer_load_format: {
6163 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
6164 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(6))->getZExtValue();
6165 unsigned IdxEn = 1;
6166 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
6167 IdxEn = Idx->getZExtValue() != 0;
6168 SDValue Ops[] = {
6169 Op.getOperand(0), // Chain
6170 Op.getOperand(2), // rsrc
6171 Op.getOperand(3), // vindex
6172 SDValue(), // voffset -- will be set by setBufferOffsets
6173 SDValue(), // soffset -- will be set by setBufferOffsets
6174 SDValue(), // offset -- will be set by setBufferOffsets
6175 DAG.getTargetConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
6176 DAG.getTargetConstant(IdxEn, DL, MVT::i1), // idxen
6177 };
6178
6179 unsigned Offset = setBufferOffsets(Op.getOperand(4), DAG, &Ops[3]);
6180 // We don't know the offset if vindex is non-zero, so clear it.
6181 if (IdxEn)
6182 Offset = 0;
6183
6184 unsigned Opc = (IntrID == Intrinsic::amdgcn_buffer_load) ?
6185 AMDGPUISD::BUFFER_LOAD : AMDGPUISD::BUFFER_LOAD_FORMAT;
6186
6187 EVT VT = Op.getValueType();
6188 EVT IntVT = VT.changeTypeToInteger();
6189 auto *M = cast<MemSDNode>(Op);
6190 M->getMemOperand()->setOffset(Offset);
6191 EVT LoadVT = Op.getValueType();
6192
6193 if (LoadVT.getScalarType() == MVT::f16)
6194 return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16,
6195 M, DAG, Ops);
6196
6197 // Handle BUFFER_LOAD_BYTE/UBYTE/SHORT/USHORT overloaded intrinsics
6198 if (LoadVT.getScalarType() == MVT::i8 ||
6199 LoadVT.getScalarType() == MVT::i16)
6200 return handleByteShortBufferLoads(DAG, LoadVT, DL, Ops, M);
6201
6202 return getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
6203 M->getMemOperand(), DAG);
6204 }
6205 case Intrinsic::amdgcn_raw_buffer_load:
6206 case Intrinsic::amdgcn_raw_buffer_load_format: {
6207 const bool IsFormat = IntrID == Intrinsic::amdgcn_raw_buffer_load_format;
6208
6209 auto Offsets = splitBufferOffsets(Op.getOperand(3), DAG);
6210 SDValue Ops[] = {
6211 Op.getOperand(0), // Chain
6212 Op.getOperand(2), // rsrc
6213 DAG.getConstant(0, DL, MVT::i32), // vindex
6214 Offsets.first, // voffset
6215 Op.getOperand(4), // soffset
6216 Offsets.second, // offset
6217 Op.getOperand(5), // cachepolicy, swizzled buffer
6218 DAG.getTargetConstant(0, DL, MVT::i1), // idxen
6219 };
6220
6221 auto *M = cast<MemSDNode>(Op);
6222 M->getMemOperand()->setOffset(getBufferOffsetForMMO(Ops[3], Ops[4], Ops[5]));
6223 return lowerIntrinsicLoad(M, IsFormat, DAG, Ops);
6224 }
6225 case Intrinsic::amdgcn_struct_buffer_load:
6226 case Intrinsic::amdgcn_struct_buffer_load_format: {
6227 const bool IsFormat = IntrID == Intrinsic::amdgcn_struct_buffer_load_format;
6228
6229 auto Offsets = splitBufferOffsets(Op.getOperand(4), DAG);
6230 SDValue Ops[] = {
6231 Op.getOperand(0), // Chain
6232 Op.getOperand(2), // rsrc
6233 Op.getOperand(3), // vindex
6234 Offsets.first, // voffset
6235 Op.getOperand(5), // soffset
6236 Offsets.second, // offset
6237 Op.getOperand(6), // cachepolicy, swizzled buffer
6238 DAG.getTargetConstant(1, DL, MVT::i1), // idxen
6239 };
6240
6241 auto *M = cast<MemSDNode>(Op);
6242 M->getMemOperand()->setOffset(getBufferOffsetForMMO(Ops[3], Ops[4], Ops[5],
6243 Ops[2]));
6244 return lowerIntrinsicLoad(cast<MemSDNode>(Op), IsFormat, DAG, Ops);
6245 }
6246 case Intrinsic::amdgcn_tbuffer_load: {
6247 MemSDNode *M = cast<MemSDNode>(Op);
6248 EVT LoadVT = Op.getValueType();
6249
6250 unsigned Dfmt = cast<ConstantSDNode>(Op.getOperand(7))->getZExtValue();
6251 unsigned Nfmt = cast<ConstantSDNode>(Op.getOperand(8))->getZExtValue();
6252 unsigned Glc = cast<ConstantSDNode>(Op.getOperand(9))->getZExtValue();
6253 unsigned Slc = cast<ConstantSDNode>(Op.getOperand(10))->getZExtValue();
6254 unsigned IdxEn = 1;
6255 if (auto Idx = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
6256 IdxEn = Idx->getZExtValue() != 0;
6257 SDValue Ops[] = {
6258 Op.getOperand(0), // Chain
6259 Op.getOperand(2), // rsrc
6260 Op.getOperand(3), // vindex
6261 Op.getOperand(4), // voffset
6262 Op.getOperand(5), // soffset
6263 Op.getOperand(6), // offset
6264 DAG.getTargetConstant(Dfmt | (Nfmt << 4), DL, MVT::i32), // format
6265 DAG.getTargetConstant(Glc | (Slc << 1), DL, MVT::i32), // cachepolicy
6266 DAG.getTargetConstant(IdxEn, DL, MVT::i1) // idxen
6267 };
6268
6269 if (LoadVT.getScalarType() == MVT::f16)
6270 return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
6271 M, DAG, Ops);
6272 return getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
6273 Op->getVTList(), Ops, LoadVT, M->getMemOperand(),
6274 DAG);
6275 }
6276 case Intrinsic::amdgcn_raw_tbuffer_load: {
6277 MemSDNode *M = cast<MemSDNode>(Op);
6278 EVT LoadVT = Op.getValueType();
6279 auto Offsets = splitBufferOffsets(Op.getOperand(3), DAG);
6280
6281 SDValue Ops[] = {
6282 Op.getOperand(0), // Chain
6283 Op.getOperand(2), // rsrc
6284 DAG.getCon