Bug Summary

File:llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Warning:line 1614, column 15
Called C++ object pointer is uninitialized

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name SIInstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/include -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/Target/AMDGPU -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-12-11-181444-25759-1 -x c++ /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
<
1//===- SIInstrInfo.cpp - SI Instruction Information ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// SI Implementation of TargetInstrInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SIInstrInfo.h"
15#include "AMDGPU.h"
16#include "AMDGPUSubtarget.h"
17#include "GCNHazardRecognizer.h"
18#include "SIDefines.h"
19#include "SIMachineFunctionInfo.h"
20#include "SIRegisterInfo.h"
21#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22#include "Utils/AMDGPUBaseInfo.h"
23#include "llvm/ADT/APInt.h"
24#include "llvm/ADT/ArrayRef.h"
25#include "llvm/ADT/SmallVector.h"
26#include "llvm/ADT/StringRef.h"
27#include "llvm/ADT/iterator_range.h"
28#include "llvm/Analysis/AliasAnalysis.h"
29#include "llvm/Analysis/MemoryLocation.h"
30#include "llvm/Analysis/ValueTracking.h"
31#include "llvm/CodeGen/MachineBasicBlock.h"
32#include "llvm/CodeGen/MachineDominators.h"
33#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineFunction.h"
35#include "llvm/CodeGen/MachineInstr.h"
36#include "llvm/CodeGen/MachineInstrBuilder.h"
37#include "llvm/CodeGen/MachineInstrBundle.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/MachineOperand.h"
40#include "llvm/CodeGen/MachineRegisterInfo.h"
41#include "llvm/CodeGen/RegisterScavenging.h"
42#include "llvm/CodeGen/ScheduleDAG.h"
43#include "llvm/CodeGen/SelectionDAGNodes.h"
44#include "llvm/CodeGen/TargetOpcodes.h"
45#include "llvm/CodeGen/TargetRegisterInfo.h"
46#include "llvm/IR/DebugLoc.h"
47#include "llvm/IR/DiagnosticInfo.h"
48#include "llvm/IR/Function.h"
49#include "llvm/IR/InlineAsm.h"
50#include "llvm/IR/LLVMContext.h"
51#include "llvm/MC/MCInstrDesc.h"
52#include "llvm/Support/Casting.h"
53#include "llvm/Support/CommandLine.h"
54#include "llvm/Support/Compiler.h"
55#include "llvm/Support/ErrorHandling.h"
56#include "llvm/Support/MachineValueType.h"
57#include "llvm/Support/MathExtras.h"
58#include "llvm/Target/TargetMachine.h"
59#include <cassert>
60#include <cstdint>
61#include <iterator>
62#include <utility>
63
64using namespace llvm;
65
66#define GET_INSTRINFO_CTOR_DTOR
67#include "AMDGPUGenInstrInfo.inc"
68
69namespace llvm {
70namespace AMDGPU {
71#define GET_D16ImageDimIntrinsics_IMPL
72#define GET_ImageDimIntrinsicTable_IMPL
73#define GET_RsrcIntrinsics_IMPL
74#include "AMDGPUGenSearchableTables.inc"
75}
76}
77
78
79// Must be at least 4 to be able to branch over minimum unconditional branch
80// code. This is only for making it possible to write reasonably small tests for
81// long branches.
82static cl::opt<unsigned>
83BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16),
84 cl::desc("Restrict range of branch instructions (DEBUG)"));
85
86SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
87 : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
88 RI(ST), ST(ST) {}
89
90//===----------------------------------------------------------------------===//
91// TargetInstrInfo callbacks
92//===----------------------------------------------------------------------===//
93
94static unsigned getNumOperandsNoGlue(SDNode *Node) {
95 unsigned N = Node->getNumOperands();
96 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
97 --N;
98 return N;
99}
100
101/// Returns true if both nodes have the same value for the given
102/// operand \p Op, or if both nodes do not have this operand.
103static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
104 unsigned Opc0 = N0->getMachineOpcode();
105 unsigned Opc1 = N1->getMachineOpcode();
106
107 int Op0Idx = AMDGPU::getNamedOperandIdx(Opc0, OpName);
108 int Op1Idx = AMDGPU::getNamedOperandIdx(Opc1, OpName);
109
110 if (Op0Idx == -1 && Op1Idx == -1)
111 return true;
112
113
114 if ((Op0Idx == -1 && Op1Idx != -1) ||
115 (Op1Idx == -1 && Op0Idx != -1))
116 return false;
117
118 // getNamedOperandIdx returns the index for the MachineInstr's operands,
119 // which includes the result as the first operand. We are indexing into the
120 // MachineSDNode's operands, so we need to skip the result operand to get
121 // the real index.
122 --Op0Idx;
123 --Op1Idx;
124
125 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx);
126}
127
128bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
129 AliasAnalysis *AA) const {
130 // TODO: The generic check fails for VALU instructions that should be
131 // rematerializable due to implicit reads of exec. We really want all of the
132 // generic logic for this except for this.
133 switch (MI.getOpcode()) {
134 case AMDGPU::V_MOV_B32_e32:
135 case AMDGPU::V_MOV_B32_e64:
136 case AMDGPU::V_MOV_B64_PSEUDO:
137 // No implicit operands.
138 return MI.getNumOperands() == MI.getDesc().getNumOperands();
139 default:
140 return false;
141 }
142}
143
144bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
145 int64_t &Offset0,
146 int64_t &Offset1) const {
147 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode())
148 return false;
149
150 unsigned Opc0 = Load0->getMachineOpcode();
151 unsigned Opc1 = Load1->getMachineOpcode();
152
153 // Make sure both are actually loads.
154 if (!get(Opc0).mayLoad() || !get(Opc1).mayLoad())
155 return false;
156
157 if (isDS(Opc0) && isDS(Opc1)) {
158
159 // FIXME: Handle this case:
160 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1))
161 return false;
162
163 // Check base reg.
164 if (Load0->getOperand(0) != Load1->getOperand(0))
165 return false;
166
167 // Skip read2 / write2 variants for simplicity.
168 // TODO: We should report true if the used offsets are adjacent (excluded
169 // st64 versions).
170 int Offset0Idx = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
171 int Offset1Idx = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
172 if (Offset0Idx == -1 || Offset1Idx == -1)
173 return false;
174
175 // XXX - be careful of datalesss loads
176 // getNamedOperandIdx returns the index for MachineInstrs. Since they
177 // include the output in the operand list, but SDNodes don't, we need to
178 // subtract the index by one.
179 Offset0Idx -= get(Opc0).NumDefs;
180 Offset1Idx -= get(Opc1).NumDefs;
181 Offset0 = cast<ConstantSDNode>(Load0->getOperand(Offset0Idx))->getZExtValue();
182 Offset1 = cast<ConstantSDNode>(Load1->getOperand(Offset1Idx))->getZExtValue();
183 return true;
184 }
185
186 if (isSMRD(Opc0) && isSMRD(Opc1)) {
187 // Skip time and cache invalidation instructions.
188 if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
189 AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
190 return false;
191
192 assert(getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1))((getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1))
? static_cast<void> (0) : __assert_fail ("getNumOperandsNoGlue(Load0) == getNumOperandsNoGlue(Load1)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 192, __PRETTY_FUNCTION__))
;
193
194 // Check base reg.
195 if (Load0->getOperand(0) != Load1->getOperand(0))
196 return false;
197
198 const ConstantSDNode *Load0Offset =
199 dyn_cast<ConstantSDNode>(Load0->getOperand(1));
200 const ConstantSDNode *Load1Offset =
201 dyn_cast<ConstantSDNode>(Load1->getOperand(1));
202
203 if (!Load0Offset || !Load1Offset)
204 return false;
205
206 Offset0 = Load0Offset->getZExtValue();
207 Offset1 = Load1Offset->getZExtValue();
208 return true;
209 }
210
211 // MUBUF and MTBUF can access the same addresses.
212 if ((isMUBUF(Opc0) || isMTBUF(Opc0)) && (isMUBUF(Opc1) || isMTBUF(Opc1))) {
213
214 // MUBUF and MTBUF have vaddr at different indices.
215 if (!nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::soffset) ||
216 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::vaddr) ||
217 !nodesHaveSameOperandValue(Load0, Load1, AMDGPU::OpName::srsrc))
218 return false;
219
220 int OffIdx0 = AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::offset);
221 int OffIdx1 = AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::offset);
222
223 if (OffIdx0 == -1 || OffIdx1 == -1)
224 return false;
225
226 // getNamedOperandIdx returns the index for MachineInstrs. Since they
227 // include the output in the operand list, but SDNodes don't, we need to
228 // subtract the index by one.
229 OffIdx0 -= get(Opc0).NumDefs;
230 OffIdx1 -= get(Opc1).NumDefs;
231
232 SDValue Off0 = Load0->getOperand(OffIdx0);
233 SDValue Off1 = Load1->getOperand(OffIdx1);
234
235 // The offset might be a FrameIndexSDNode.
236 if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
237 return false;
238
239 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
240 Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
241 return true;
242 }
243
244 return false;
245}
246
247static bool isStride64(unsigned Opc) {
248 switch (Opc) {
249 case AMDGPU::DS_READ2ST64_B32:
250 case AMDGPU::DS_READ2ST64_B64:
251 case AMDGPU::DS_WRITE2ST64_B32:
252 case AMDGPU::DS_WRITE2ST64_B64:
253 return true;
254 default:
255 return false;
256 }
257}
258
259bool SIInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt,
260 const MachineOperand *&BaseOp,
261 int64_t &Offset,
262 const TargetRegisterInfo *TRI) const {
263 unsigned Opc = LdSt.getOpcode();
264
265 if (isDS(LdSt)) {
266 const MachineOperand *OffsetImm =
267 getNamedOperand(LdSt, AMDGPU::OpName::offset);
268 if (OffsetImm) {
269 // Normal, single offset LDS instruction.
270 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
271 // TODO: ds_consume/ds_append use M0 for the base address. Is it safe to
272 // report that here?
273 if (!BaseOp)
274 return false;
275
276 Offset = OffsetImm->getImm();
277 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 278, __PRETTY_FUNCTION__))
278 "operands of type register.")((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 278, __PRETTY_FUNCTION__))
;
279 return true;
280 }
281
282 // The 2 offset instructions use offset0 and offset1 instead. We can treat
283 // these as a load with a single offset if the 2 offsets are consecutive. We
284 // will use this for some partially aligned loads.
285 const MachineOperand *Offset0Imm =
286 getNamedOperand(LdSt, AMDGPU::OpName::offset0);
287 const MachineOperand *Offset1Imm =
288 getNamedOperand(LdSt, AMDGPU::OpName::offset1);
289
290 uint8_t Offset0 = Offset0Imm->getImm();
291 uint8_t Offset1 = Offset1Imm->getImm();
292
293 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) {
294 // Each of these offsets is in element sized units, so we need to convert
295 // to bytes of the individual reads.
296
297 unsigned EltSize;
298 if (LdSt.mayLoad())
299 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16;
300 else {
301 assert(LdSt.mayStore())((LdSt.mayStore()) ? static_cast<void> (0) : __assert_fail
("LdSt.mayStore()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 301, __PRETTY_FUNCTION__))
;
302 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
303 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8;
304 }
305
306 if (isStride64(Opc))
307 EltSize *= 64;
308
309 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr);
310 Offset = EltSize * Offset0;
311 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 312, __PRETTY_FUNCTION__))
312 "operands of type register.")((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 312, __PRETTY_FUNCTION__))
;
313 return true;
314 }
315
316 return false;
317 }
318
319 if (isMUBUF(LdSt) || isMTBUF(LdSt)) {
320 const MachineOperand *SOffset = getNamedOperand(LdSt, AMDGPU::OpName::soffset);
321 if (SOffset && SOffset->isReg()) {
322 // We can only handle this if it's a stack access, as any other resource
323 // would require reporting multiple base registers.
324 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
325 if (AddrReg && !AddrReg->isFI())
326 return false;
327
328 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
329 const SIMachineFunctionInfo *MFI
330 = LdSt.getParent()->getParent()->getInfo<SIMachineFunctionInfo>();
331 if (RSrc->getReg() != MFI->getScratchRSrcReg())
332 return false;
333
334 const MachineOperand *OffsetImm =
335 getNamedOperand(LdSt, AMDGPU::OpName::offset);
336 BaseOp = SOffset;
337 Offset = OffsetImm->getImm();
338 return true;
339 }
340
341 const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
342 if (!AddrReg)
343 return false;
344
345 const MachineOperand *OffsetImm =
346 getNamedOperand(LdSt, AMDGPU::OpName::offset);
347 BaseOp = AddrReg;
348 Offset = OffsetImm->getImm();
349
350 if (SOffset) // soffset can be an inline immediate.
351 Offset += SOffset->getImm();
352
353 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 354, __PRETTY_FUNCTION__))
354 "operands of type register.")((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 354, __PRETTY_FUNCTION__))
;
355 return true;
356 }
357
358 if (isSMRD(LdSt)) {
359 const MachineOperand *OffsetImm =
360 getNamedOperand(LdSt, AMDGPU::OpName::offset);
361 if (!OffsetImm)
362 return false;
363
364 const MachineOperand *SBaseReg = getNamedOperand(LdSt, AMDGPU::OpName::sbase);
365 BaseOp = SBaseReg;
366 Offset = OffsetImm->getImm();
367 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 368, __PRETTY_FUNCTION__))
368 "operands of type register.")((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 368, __PRETTY_FUNCTION__))
;
369 return true;
370 }
371
372 if (isFLAT(LdSt)) {
373 const MachineOperand *VAddr = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
374 if (VAddr) {
375 // Can't analyze 2 offsets.
376 if (getNamedOperand(LdSt, AMDGPU::OpName::saddr))
377 return false;
378
379 BaseOp = VAddr;
380 } else {
381 // scratch instructions have either vaddr or saddr.
382 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::saddr);
383 }
384
385 Offset = getNamedOperand(LdSt, AMDGPU::OpName::offset)->getImm();
386 assert(BaseOp->isReg() && "getMemOperandWithOffset only supports base "((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 387, __PRETTY_FUNCTION__))
387 "operands of type register.")((BaseOp->isReg() && "getMemOperandWithOffset only supports base "
"operands of type register.") ? static_cast<void> (0) :
__assert_fail ("BaseOp->isReg() && \"getMemOperandWithOffset only supports base \" \"operands of type register.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 387, __PRETTY_FUNCTION__))
;
388 return true;
389 }
390
391 return false;
392}
393
394static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
395 const MachineOperand &BaseOp1,
396 const MachineInstr &MI2,
397 const MachineOperand &BaseOp2) {
398 // Support only base operands with base registers.
399 // Note: this could be extended to support FI operands.
400 if (!BaseOp1.isReg() || !BaseOp2.isReg())
401 return false;
402
403 if (BaseOp1.isIdenticalTo(BaseOp2))
404 return true;
405
406 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
407 return false;
408
409 auto MO1 = *MI1.memoperands_begin();
410 auto MO2 = *MI2.memoperands_begin();
411 if (MO1->getAddrSpace() != MO2->getAddrSpace())
412 return false;
413
414 auto Base1 = MO1->getValue();
415 auto Base2 = MO2->getValue();
416 if (!Base1 || !Base2)
417 return false;
418 const MachineFunction &MF = *MI1.getParent()->getParent();
419 const DataLayout &DL = MF.getFunction().getParent()->getDataLayout();
420 Base1 = GetUnderlyingObject(Base1, DL);
421 Base2 = GetUnderlyingObject(Base1, DL);
422
423 if (isa<UndefValue>(Base1) || isa<UndefValue>(Base2))
424 return false;
425
426 return Base1 == Base2;
427}
428
429bool SIInstrInfo::shouldClusterMemOps(const MachineOperand &BaseOp1,
430 const MachineOperand &BaseOp2,
431 unsigned NumLoads) const {
432 const MachineInstr &FirstLdSt = *BaseOp1.getParent();
433 const MachineInstr &SecondLdSt = *BaseOp2.getParent();
434
435 if (!memOpsHaveSameBasePtr(FirstLdSt, BaseOp1, SecondLdSt, BaseOp2))
436 return false;
437
438 const MachineOperand *FirstDst = nullptr;
439 const MachineOperand *SecondDst = nullptr;
440
441 if ((isMUBUF(FirstLdSt) && isMUBUF(SecondLdSt)) ||
442 (isMTBUF(FirstLdSt) && isMTBUF(SecondLdSt)) ||
443 (isFLAT(FirstLdSt) && isFLAT(SecondLdSt))) {
444 const unsigned MaxGlobalLoadCluster = 6;
445 if (NumLoads > MaxGlobalLoadCluster)
446 return false;
447
448 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdata);
449 if (!FirstDst)
450 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdst);
451 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdata);
452 if (!SecondDst)
453 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdst);
454 } else if (isSMRD(FirstLdSt) && isSMRD(SecondLdSt)) {
455 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::sdst);
456 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::sdst);
457 } else if (isDS(FirstLdSt) && isDS(SecondLdSt)) {
458 FirstDst = getNamedOperand(FirstLdSt, AMDGPU::OpName::vdst);
459 SecondDst = getNamedOperand(SecondLdSt, AMDGPU::OpName::vdst);
460 }
461
462 if (!FirstDst || !SecondDst)
463 return false;
464
465 // Try to limit clustering based on the total number of bytes loaded
466 // rather than the number of instructions. This is done to help reduce
467 // register pressure. The method used is somewhat inexact, though,
468 // because it assumes that all loads in the cluster will load the
469 // same number of bytes as FirstLdSt.
470
471 // The unit of this value is bytes.
472 // FIXME: This needs finer tuning.
473 unsigned LoadClusterThreshold = 16;
474
475 const MachineRegisterInfo &MRI =
476 FirstLdSt.getParent()->getParent()->getRegInfo();
477
478 const Register Reg = FirstDst->getReg();
479
480 const TargetRegisterClass *DstRC = Register::isVirtualRegister(Reg)
481 ? MRI.getRegClass(Reg)
482 : RI.getPhysRegClass(Reg);
483
484 return (NumLoads * (RI.getRegSizeInBits(*DstRC) / 8)) <= LoadClusterThreshold;
485}
486
487// FIXME: This behaves strangely. If, for example, you have 32 load + stores,
488// the first 16 loads will be interleaved with the stores, and the next 16 will
489// be clustered as expected. It should really split into 2 16 store batches.
490//
491// Loads are clustered until this returns false, rather than trying to schedule
492// groups of stores. This also means we have to deal with saying different
493// address space loads should be clustered, and ones which might cause bank
494// conflicts.
495//
496// This might be deprecated so it might not be worth that much effort to fix.
497bool SIInstrInfo::shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1,
498 int64_t Offset0, int64_t Offset1,
499 unsigned NumLoads) const {
500 assert(Offset1 > Offset0 &&((Offset1 > Offset0 && "Second offset should be larger than first offset!"
) ? static_cast<void> (0) : __assert_fail ("Offset1 > Offset0 && \"Second offset should be larger than first offset!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 501, __PRETTY_FUNCTION__))
501 "Second offset should be larger than first offset!")((Offset1 > Offset0 && "Second offset should be larger than first offset!"
) ? static_cast<void> (0) : __assert_fail ("Offset1 > Offset0 && \"Second offset should be larger than first offset!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 501, __PRETTY_FUNCTION__))
;
502 // If we have less than 16 loads in a row, and the offsets are within 64
503 // bytes, then schedule together.
504
505 // A cacheline is 64 bytes (for global memory).
506 return (NumLoads <= 16 && (Offset1 - Offset0) < 64);
507}
508
509static void reportIllegalCopy(const SIInstrInfo *TII, MachineBasicBlock &MBB,
510 MachineBasicBlock::iterator MI,
511 const DebugLoc &DL, MCRegister DestReg,
512 MCRegister SrcReg, bool KillSrc) {
513 MachineFunction *MF = MBB.getParent();
514 DiagnosticInfoUnsupported IllegalCopy(MF->getFunction(),
515 "illegal SGPR to VGPR copy",
516 DL, DS_Error);
517 LLVMContext &C = MF->getFunction().getContext();
518 C.diagnose(IllegalCopy);
519
520 BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg)
521 .addReg(SrcReg, getKillRegState(KillSrc));
522}
523
524void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
525 MachineBasicBlock::iterator MI,
526 const DebugLoc &DL, MCRegister DestReg,
527 MCRegister SrcReg, bool KillSrc) const {
528 const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg);
529
530 if (RC == &AMDGPU::VGPR_32RegClass) {
531 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||((AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass
.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)
) ? static_cast<void> (0) : __assert_fail ("AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 533, __PRETTY_FUNCTION__))
532 AMDGPU::SReg_32RegClass.contains(SrcReg) ||((AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass
.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)
) ? static_cast<void> (0) : __assert_fail ("AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 533, __PRETTY_FUNCTION__))
533 AMDGPU::AGPR_32RegClass.contains(SrcReg))((AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass
.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)
) ? static_cast<void> (0) : __assert_fail ("AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 533, __PRETTY_FUNCTION__))
;
534 unsigned Opc = AMDGPU::AGPR_32RegClass.contains(SrcReg) ?
535 AMDGPU::V_ACCVGPR_READ_B32 : AMDGPU::V_MOV_B32_e32;
536 BuildMI(MBB, MI, DL, get(Opc), DestReg)
537 .addReg(SrcReg, getKillRegState(KillSrc));
538 return;
539 }
540
541 if (RC == &AMDGPU::SReg_32_XM0RegClass ||
542 RC == &AMDGPU::SReg_32RegClass) {
543 if (SrcReg == AMDGPU::SCC) {
544 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg)
545 .addImm(-1)
546 .addImm(0);
547 return;
548 }
549
550 if (DestReg == AMDGPU::VCC_LO) {
551 if (AMDGPU::SReg_32RegClass.contains(SrcReg)) {
552 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::VCC_LO)
553 .addReg(SrcReg, getKillRegState(KillSrc));
554 } else {
555 // FIXME: Hack until VReg_1 removed.
556 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg))((AMDGPU::VGPR_32RegClass.contains(SrcReg)) ? static_cast<
void> (0) : __assert_fail ("AMDGPU::VGPR_32RegClass.contains(SrcReg)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 556, __PRETTY_FUNCTION__))
;
557 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
558 .addImm(0)
559 .addReg(SrcReg, getKillRegState(KillSrc));
560 }
561
562 return;
563 }
564
565 if (!AMDGPU::SReg_32RegClass.contains(SrcReg)) {
566 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
567 return;
568 }
569
570 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
571 .addReg(SrcReg, getKillRegState(KillSrc));
572 return;
573 }
574
575 if (RC == &AMDGPU::SReg_64RegClass) {
576 if (DestReg == AMDGPU::VCC) {
577 if (AMDGPU::SReg_64RegClass.contains(SrcReg)) {
578 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
579 .addReg(SrcReg, getKillRegState(KillSrc));
580 } else {
581 // FIXME: Hack until VReg_1 removed.
582 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg))((AMDGPU::VGPR_32RegClass.contains(SrcReg)) ? static_cast<
void> (0) : __assert_fail ("AMDGPU::VGPR_32RegClass.contains(SrcReg)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 582, __PRETTY_FUNCTION__))
;
583 BuildMI(MBB, MI, DL, get(AMDGPU::V_CMP_NE_U32_e32))
584 .addImm(0)
585 .addReg(SrcReg, getKillRegState(KillSrc));
586 }
587
588 return;
589 }
590
591 if (!AMDGPU::SReg_64RegClass.contains(SrcReg)) {
592 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
593 return;
594 }
595
596 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
597 .addReg(SrcReg, getKillRegState(KillSrc));
598 return;
599 }
600
601 if (DestReg == AMDGPU::SCC) {
602 assert(AMDGPU::SReg_32RegClass.contains(SrcReg))((AMDGPU::SReg_32RegClass.contains(SrcReg)) ? static_cast<
void> (0) : __assert_fail ("AMDGPU::SReg_32RegClass.contains(SrcReg)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 602, __PRETTY_FUNCTION__))
;
603 BuildMI(MBB, MI, DL, get(AMDGPU::S_CMP_LG_U32))
604 .addReg(SrcReg, getKillRegState(KillSrc))
605 .addImm(0);
606 return;
607 }
608
609 if (RC == &AMDGPU::AGPR_32RegClass) {
610 assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||((AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass
.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)
) ? static_cast<void> (0) : __assert_fail ("AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 612, __PRETTY_FUNCTION__))
611 AMDGPU::SReg_32RegClass.contains(SrcReg) ||((AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass
.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)
) ? static_cast<void> (0) : __assert_fail ("AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 612, __PRETTY_FUNCTION__))
612 AMDGPU::AGPR_32RegClass.contains(SrcReg))((AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass
.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)
) ? static_cast<void> (0) : __assert_fail ("AMDGPU::VGPR_32RegClass.contains(SrcReg) || AMDGPU::SReg_32RegClass.contains(SrcReg) || AMDGPU::AGPR_32RegClass.contains(SrcReg)"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 612, __PRETTY_FUNCTION__))
;
613 if (!AMDGPU::VGPR_32RegClass.contains(SrcReg)) {
614 // First try to find defining accvgpr_write to avoid temporary registers.
615 for (auto Def = MI, E = MBB.begin(); Def != E; ) {
616 --Def;
617 if (!Def->definesRegister(SrcReg, &RI))
618 continue;
619 if (Def->getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32)
620 break;
621
622 MachineOperand &DefOp = Def->getOperand(1);
623 assert(DefOp.isReg() || DefOp.isImm())((DefOp.isReg() || DefOp.isImm()) ? static_cast<void> (
0) : __assert_fail ("DefOp.isReg() || DefOp.isImm()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 623, __PRETTY_FUNCTION__))
;
624
625 if (DefOp.isReg()) {
626 // Check that register source operand if not clobbered before MI.
627 // Immediate operands are always safe to propagate.
628 bool SafeToPropagate = true;
629 for (auto I = Def; I != MI && SafeToPropagate; ++I)
630 if (I->modifiesRegister(DefOp.getReg(), &RI))
631 SafeToPropagate = false;
632
633 if (!SafeToPropagate)
634 break;
635
636 DefOp.setIsKill(false);
637 }
638
639 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
640 .add(DefOp);
641 return;
642 }
643
644 RegScavenger RS;
645 RS.enterBasicBlock(MBB);
646 RS.forward(MI);
647
648 // Ideally we want to have three registers for a long reg_sequence copy
649 // to hide 2 waitstates between v_mov_b32 and accvgpr_write.
650 unsigned MaxVGPRs = RI.getRegPressureLimit(&AMDGPU::VGPR_32RegClass,
651 *MBB.getParent());
652
653 // Registers in the sequence are allocated contiguously so we can just
654 // use register number to pick one of three round-robin temps.
655 unsigned RegNo = DestReg % 3;
656 unsigned Tmp = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
657 if (!Tmp)
658 report_fatal_error("Cannot scavenge VGPR to copy to AGPR");
659 RS.setRegUsed(Tmp);
660 // Only loop through if there are any free registers left, otherwise
661 // scavenger may report a fatal error without emergency spill slot
662 // or spill with the slot.
663 while (RegNo-- && RS.FindUnusedReg(&AMDGPU::VGPR_32RegClass)) {
664 unsigned Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0);
665 if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs)
666 break;
667 Tmp = Tmp2;
668 RS.setRegUsed(Tmp);
669 }
670 copyPhysReg(MBB, MI, DL, Tmp, SrcReg, KillSrc);
671 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
672 .addReg(Tmp, RegState::Kill);
673 return;
674 }
675
676 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
677 .addReg(SrcReg, getKillRegState(KillSrc));
678 return;
679 }
680
681 unsigned EltSize = 4;
682 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
683 if (RI.isSGPRClass(RC)) {
684 // TODO: Copy vec3/vec5 with s_mov_b64s then final s_mov_b32.
685 if (!(RI.getRegSizeInBits(*RC) % 64)) {
686 Opcode = AMDGPU::S_MOV_B64;
687 EltSize = 8;
688 } else {
689 Opcode = AMDGPU::S_MOV_B32;
690 EltSize = 4;
691 }
692
693 if (!RI.isSGPRClass(RI.getPhysRegClass(SrcReg))) {
694 reportIllegalCopy(this, MBB, MI, DL, DestReg, SrcReg, KillSrc);
695 return;
696 }
697 } else if (RI.hasAGPRs(RC)) {
698 Opcode = RI.hasVGPRs(RI.getPhysRegClass(SrcReg)) ?
699 AMDGPU::V_ACCVGPR_WRITE_B32 : AMDGPU::COPY;
700 } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(RI.getPhysRegClass(SrcReg))) {
701 Opcode = AMDGPU::V_ACCVGPR_READ_B32;
702 }
703
704 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize);
705 bool Forward = RI.getHWRegIndex(DestReg) <= RI.getHWRegIndex(SrcReg);
706
707 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
708 unsigned SubIdx;
709 if (Forward)
710 SubIdx = SubIndices[Idx];
711 else
712 SubIdx = SubIndices[SubIndices.size() - Idx - 1];
713
714 if (Opcode == TargetOpcode::COPY) {
715 copyPhysReg(MBB, MI, DL, RI.getSubReg(DestReg, SubIdx),
716 RI.getSubReg(SrcReg, SubIdx), KillSrc);
717 continue;
718 }
719
720 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
721 get(Opcode), RI.getSubReg(DestReg, SubIdx));
722
723 Builder.addReg(RI.getSubReg(SrcReg, SubIdx));
724
725 if (Idx == 0)
726 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
727
728 bool UseKill = KillSrc && Idx == SubIndices.size() - 1;
729 Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
730 }
731}
732
733int SIInstrInfo::commuteOpcode(unsigned Opcode) const {
734 int NewOpc;
735
736 // Try to map original to commuted opcode
737 NewOpc = AMDGPU::getCommuteRev(Opcode);
738 if (NewOpc != -1)
739 // Check if the commuted (REV) opcode exists on the target.
740 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
741
742 // Try to map commuted to original opcode
743 NewOpc = AMDGPU::getCommuteOrig(Opcode);
744 if (NewOpc != -1)
745 // Check if the original (non-REV) opcode exists on the target.
746 return pseudoToMCOpcode(NewOpc) != -1 ? NewOpc : -1;
747
748 return Opcode;
749}
750
751void SIInstrInfo::materializeImmediate(MachineBasicBlock &MBB,
752 MachineBasicBlock::iterator MI,
753 const DebugLoc &DL, unsigned DestReg,
754 int64_t Value) const {
755 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
756 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
757 if (RegClass == &AMDGPU::SReg_32RegClass ||
758 RegClass == &AMDGPU::SGPR_32RegClass ||
759 RegClass == &AMDGPU::SReg_32_XM0RegClass ||
760 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) {
761 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
762 .addImm(Value);
763 return;
764 }
765
766 if (RegClass == &AMDGPU::SReg_64RegClass ||
767 RegClass == &AMDGPU::SGPR_64RegClass ||
768 RegClass == &AMDGPU::SReg_64_XEXECRegClass) {
769 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
770 .addImm(Value);
771 return;
772 }
773
774 if (RegClass == &AMDGPU::VGPR_32RegClass) {
775 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
776 .addImm(Value);
777 return;
778 }
779 if (RegClass == &AMDGPU::VReg_64RegClass) {
780 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
781 .addImm(Value);
782 return;
783 }
784
785 unsigned EltSize = 4;
786 unsigned Opcode = AMDGPU::V_MOV_B32_e32;
787 if (RI.isSGPRClass(RegClass)) {
788 if (RI.getRegSizeInBits(*RegClass) > 32) {
789 Opcode = AMDGPU::S_MOV_B64;
790 EltSize = 8;
791 } else {
792 Opcode = AMDGPU::S_MOV_B32;
793 EltSize = 4;
794 }
795 }
796
797 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize);
798 for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
799 int64_t IdxValue = Idx == 0 ? Value : 0;
800
801 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
802 get(Opcode), RI.getSubReg(DestReg, Idx));
803 Builder.addImm(IdxValue);
804 }
805}
806
807const TargetRegisterClass *
808SIInstrInfo::getPreferredSelectRegClass(unsigned Size) const {
809 return &AMDGPU::VGPR_32RegClass;
810}
811
812void SIInstrInfo::insertVectorSelect(MachineBasicBlock &MBB,
813 MachineBasicBlock::iterator I,
814 const DebugLoc &DL, unsigned DstReg,
815 ArrayRef<MachineOperand> Cond,
816 unsigned TrueReg,
817 unsigned FalseReg) const {
818 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
819 MachineFunction *MF = MBB.getParent();
820 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
821 const TargetRegisterClass *BoolXExecRC =
822 RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
823 assert(MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&((MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
"Not a VGPR32 reg") ? static_cast<void> (0) : __assert_fail
("MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass && \"Not a VGPR32 reg\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 824, __PRETTY_FUNCTION__))
824 "Not a VGPR32 reg")((MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass &&
"Not a VGPR32 reg") ? static_cast<void> (0) : __assert_fail
("MRI.getRegClass(DstReg) == &AMDGPU::VGPR_32RegClass && \"Not a VGPR32 reg\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 824, __PRETTY_FUNCTION__))
;
825
826 if (Cond.size() == 1) {
827 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
828 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
829 .add(Cond[0]);
830 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
831 .addImm(0)
832 .addReg(FalseReg)
833 .addImm(0)
834 .addReg(TrueReg)
835 .addReg(SReg);
836 } else if (Cond.size() == 2) {
837 assert(Cond[0].isImm() && "Cond[0] is not an immediate")((Cond[0].isImm() && "Cond[0] is not an immediate") ?
static_cast<void> (0) : __assert_fail ("Cond[0].isImm() && \"Cond[0] is not an immediate\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 837, __PRETTY_FUNCTION__))
;
838 switch (Cond[0].getImm()) {
839 case SIInstrInfo::SCC_TRUE: {
840 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
841 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
842 : AMDGPU::S_CSELECT_B64), SReg)
843 .addImm(-1)
844 .addImm(0);
845 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
846 .addImm(0)
847 .addReg(FalseReg)
848 .addImm(0)
849 .addReg(TrueReg)
850 .addReg(SReg);
851 break;
852 }
853 case SIInstrInfo::SCC_FALSE: {
854 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
855 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
856 : AMDGPU::S_CSELECT_B64), SReg)
857 .addImm(0)
858 .addImm(-1);
859 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
860 .addImm(0)
861 .addReg(FalseReg)
862 .addImm(0)
863 .addReg(TrueReg)
864 .addReg(SReg);
865 break;
866 }
867 case SIInstrInfo::VCCNZ: {
868 MachineOperand RegOp = Cond[1];
869 RegOp.setImplicit(false);
870 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
871 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
872 .add(RegOp);
873 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
874 .addImm(0)
875 .addReg(FalseReg)
876 .addImm(0)
877 .addReg(TrueReg)
878 .addReg(SReg);
879 break;
880 }
881 case SIInstrInfo::VCCZ: {
882 MachineOperand RegOp = Cond[1];
883 RegOp.setImplicit(false);
884 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
885 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
886 .add(RegOp);
887 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
888 .addImm(0)
889 .addReg(TrueReg)
890 .addImm(0)
891 .addReg(FalseReg)
892 .addReg(SReg);
893 break;
894 }
895 case SIInstrInfo::EXECNZ: {
896 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
897 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC());
898 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
899 : AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
900 .addImm(0);
901 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
902 : AMDGPU::S_CSELECT_B64), SReg)
903 .addImm(-1)
904 .addImm(0);
905 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
906 .addImm(0)
907 .addReg(FalseReg)
908 .addImm(0)
909 .addReg(TrueReg)
910 .addReg(SReg);
911 break;
912 }
913 case SIInstrInfo::EXECZ: {
914 Register SReg = MRI.createVirtualRegister(BoolXExecRC);
915 Register SReg2 = MRI.createVirtualRegister(RI.getBoolRC());
916 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
917 : AMDGPU::S_OR_SAVEEXEC_B64), SReg2)
918 .addImm(0);
919 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
920 : AMDGPU::S_CSELECT_B64), SReg)
921 .addImm(0)
922 .addImm(-1);
923 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
924 .addImm(0)
925 .addReg(FalseReg)
926 .addImm(0)
927 .addReg(TrueReg)
928 .addReg(SReg);
929 llvm_unreachable("Unhandled branch predicate EXECZ")::llvm::llvm_unreachable_internal("Unhandled branch predicate EXECZ"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 929)
;
930 break;
931 }
932 default:
933 llvm_unreachable("invalid branch predicate")::llvm::llvm_unreachable_internal("invalid branch predicate",
"/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 933)
;
934 }
935 } else {
936 llvm_unreachable("Can only handle Cond size 1 or 2")::llvm::llvm_unreachable_internal("Can only handle Cond size 1 or 2"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 936)
;
937 }
938}
939
940unsigned SIInstrInfo::insertEQ(MachineBasicBlock *MBB,
941 MachineBasicBlock::iterator I,
942 const DebugLoc &DL,
943 unsigned SrcReg, int Value) const {
944 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
945 Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
946 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
947 .addImm(Value)
948 .addReg(SrcReg);
949
950 return Reg;
951}
952
953unsigned SIInstrInfo::insertNE(MachineBasicBlock *MBB,
954 MachineBasicBlock::iterator I,
955 const DebugLoc &DL,
956 unsigned SrcReg, int Value) const {
957 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
958 Register Reg = MRI.createVirtualRegister(RI.getBoolRC());
959 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
960 .addImm(Value)
961 .addReg(SrcReg);
962
963 return Reg;
964}
965
966unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
967
968 if (RI.hasAGPRs(DstRC))
969 return AMDGPU::COPY;
970 if (RI.getRegSizeInBits(*DstRC) == 32) {
971 return RI.isSGPRClass(DstRC) ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
972 } else if (RI.getRegSizeInBits(*DstRC) == 64 && RI.isSGPRClass(DstRC)) {
973 return AMDGPU::S_MOV_B64;
974 } else if (RI.getRegSizeInBits(*DstRC) == 64 && !RI.isSGPRClass(DstRC)) {
975 return AMDGPU::V_MOV_B64_PSEUDO;
976 }
977 return AMDGPU::COPY;
978}
979
980static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
981 switch (Size) {
982 case 4:
983 return AMDGPU::SI_SPILL_S32_SAVE;
984 case 8:
985 return AMDGPU::SI_SPILL_S64_SAVE;
986 case 12:
987 return AMDGPU::SI_SPILL_S96_SAVE;
988 case 16:
989 return AMDGPU::SI_SPILL_S128_SAVE;
990 case 20:
991 return AMDGPU::SI_SPILL_S160_SAVE;
992 case 32:
993 return AMDGPU::SI_SPILL_S256_SAVE;
994 case 64:
995 return AMDGPU::SI_SPILL_S512_SAVE;
996 case 128:
997 return AMDGPU::SI_SPILL_S1024_SAVE;
998 default:
999 llvm_unreachable("unknown register size")::llvm::llvm_unreachable_internal("unknown register size", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 999)
;
1000 }
1001}
1002
1003static unsigned getVGPRSpillSaveOpcode(unsigned Size) {
1004 switch (Size) {
1005 case 4:
1006 return AMDGPU::SI_SPILL_V32_SAVE;
1007 case 8:
1008 return AMDGPU::SI_SPILL_V64_SAVE;
1009 case 12:
1010 return AMDGPU::SI_SPILL_V96_SAVE;
1011 case 16:
1012 return AMDGPU::SI_SPILL_V128_SAVE;
1013 case 20:
1014 return AMDGPU::SI_SPILL_V160_SAVE;
1015 case 32:
1016 return AMDGPU::SI_SPILL_V256_SAVE;
1017 case 64:
1018 return AMDGPU::SI_SPILL_V512_SAVE;
1019 case 128:
1020 return AMDGPU::SI_SPILL_V1024_SAVE;
1021 default:
1022 llvm_unreachable("unknown register size")::llvm::llvm_unreachable_internal("unknown register size", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1022)
;
1023 }
1024}
1025
1026static unsigned getAGPRSpillSaveOpcode(unsigned Size) {
1027 switch (Size) {
1028 case 4:
1029 return AMDGPU::SI_SPILL_A32_SAVE;
1030 case 8:
1031 return AMDGPU::SI_SPILL_A64_SAVE;
1032 case 16:
1033 return AMDGPU::SI_SPILL_A128_SAVE;
1034 case 64:
1035 return AMDGPU::SI_SPILL_A512_SAVE;
1036 case 128:
1037 return AMDGPU::SI_SPILL_A1024_SAVE;
1038 default:
1039 llvm_unreachable("unknown register size")::llvm::llvm_unreachable_internal("unknown register size", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1039)
;
1040 }
1041}
1042
1043void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1044 MachineBasicBlock::iterator MI,
1045 unsigned SrcReg, bool isKill,
1046 int FrameIndex,
1047 const TargetRegisterClass *RC,
1048 const TargetRegisterInfo *TRI) const {
1049 MachineFunction *MF = MBB.getParent();
1050 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
1051 MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1052 const DebugLoc &DL = MBB.findDebugLoc(MI);
1053
1054 unsigned Size = FrameInfo.getObjectSize(FrameIndex);
1055 unsigned Align = FrameInfo.getObjectAlignment(FrameIndex);
1056 MachinePointerInfo PtrInfo
1057 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
1058 MachineMemOperand *MMO
1059 = MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
1060 Size, Align);
1061 unsigned SpillSize = TRI->getSpillSize(*RC);
1062
1063 if (RI.isSGPRClass(RC)) {
1064 MFI->setHasSpilledSGPRs();
1065 assert(SrcReg != AMDGPU::M0 && "m0 should not be spilled")((SrcReg != AMDGPU::M0 && "m0 should not be spilled")
? static_cast<void> (0) : __assert_fail ("SrcReg != AMDGPU::M0 && \"m0 should not be spilled\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1065, __PRETTY_FUNCTION__))
;
1066
1067 // We are only allowed to create one new instruction when spilling
1068 // registers, so we need to use pseudo instruction for spilling SGPRs.
1069 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
1070
1071 // The SGPR spill/restore instructions only work on number sgprs, so we need
1072 // to make sure we are using the correct register class.
1073 if (Register::isVirtualRegister(SrcReg) && SpillSize == 4) {
1074 MachineRegisterInfo &MRI = MF->getRegInfo();
1075 MRI.constrainRegClass(SrcReg, &AMDGPU::SReg_32_XM0RegClass);
1076 }
1077
1078 BuildMI(MBB, MI, DL, OpDesc)
1079 .addReg(SrcReg, getKillRegState(isKill)) // data
1080 .addFrameIndex(FrameIndex) // addr
1081 .addMemOperand(MMO)
1082 .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
1083 .addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit);
1084 // Add the scratch resource registers as implicit uses because we may end up
1085 // needing them, and need to ensure that the reserved registers are
1086 // correctly handled.
1087 if (RI.spillSGPRToVGPR())
1088 FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
1089 return;
1090 }
1091
1092 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillSaveOpcode(SpillSize)
1093 : getVGPRSpillSaveOpcode(SpillSize);
1094 MFI->setHasSpilledVGPRs();
1095
1096 auto MIB = BuildMI(MBB, MI, DL, get(Opcode));
1097 if (RI.hasAGPRs(RC)) {
1098 MachineRegisterInfo &MRI = MF->getRegInfo();
1099 Register Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1100 MIB.addReg(Tmp, RegState::Define);
1101 }
1102 MIB.addReg(SrcReg, getKillRegState(isKill)) // data
1103 .addFrameIndex(FrameIndex) // addr
1104 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
1105 .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1106 .addImm(0) // offset
1107 .addMemOperand(MMO);
1108}
1109
1110static unsigned getSGPRSpillRestoreOpcode(unsigned Size) {
1111 switch (Size) {
1112 case 4:
1113 return AMDGPU::SI_SPILL_S32_RESTORE;
1114 case 8:
1115 return AMDGPU::SI_SPILL_S64_RESTORE;
1116 case 12:
1117 return AMDGPU::SI_SPILL_S96_RESTORE;
1118 case 16:
1119 return AMDGPU::SI_SPILL_S128_RESTORE;
1120 case 20:
1121 return AMDGPU::SI_SPILL_S160_RESTORE;
1122 case 32:
1123 return AMDGPU::SI_SPILL_S256_RESTORE;
1124 case 64:
1125 return AMDGPU::SI_SPILL_S512_RESTORE;
1126 case 128:
1127 return AMDGPU::SI_SPILL_S1024_RESTORE;
1128 default:
1129 llvm_unreachable("unknown register size")::llvm::llvm_unreachable_internal("unknown register size", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1129)
;
1130 }
1131}
1132
1133static unsigned getVGPRSpillRestoreOpcode(unsigned Size) {
1134 switch (Size) {
1135 case 4:
1136 return AMDGPU::SI_SPILL_V32_RESTORE;
1137 case 8:
1138 return AMDGPU::SI_SPILL_V64_RESTORE;
1139 case 12:
1140 return AMDGPU::SI_SPILL_V96_RESTORE;
1141 case 16:
1142 return AMDGPU::SI_SPILL_V128_RESTORE;
1143 case 20:
1144 return AMDGPU::SI_SPILL_V160_RESTORE;
1145 case 32:
1146 return AMDGPU::SI_SPILL_V256_RESTORE;
1147 case 64:
1148 return AMDGPU::SI_SPILL_V512_RESTORE;
1149 case 128:
1150 return AMDGPU::SI_SPILL_V1024_RESTORE;
1151 default:
1152 llvm_unreachable("unknown register size")::llvm::llvm_unreachable_internal("unknown register size", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1152)
;
1153 }
1154}
1155
1156static unsigned getAGPRSpillRestoreOpcode(unsigned Size) {
1157 switch (Size) {
1158 case 4:
1159 return AMDGPU::SI_SPILL_A32_RESTORE;
1160 case 8:
1161 return AMDGPU::SI_SPILL_A64_RESTORE;
1162 case 16:
1163 return AMDGPU::SI_SPILL_A128_RESTORE;
1164 case 64:
1165 return AMDGPU::SI_SPILL_A512_RESTORE;
1166 case 128:
1167 return AMDGPU::SI_SPILL_A1024_RESTORE;
1168 default:
1169 llvm_unreachable("unknown register size")::llvm::llvm_unreachable_internal("unknown register size", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1169)
;
1170 }
1171}
1172
1173void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1174 MachineBasicBlock::iterator MI,
1175 unsigned DestReg, int FrameIndex,
1176 const TargetRegisterClass *RC,
1177 const TargetRegisterInfo *TRI) const {
1178 MachineFunction *MF = MBB.getParent();
1179 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
1180 MachineFrameInfo &FrameInfo = MF->getFrameInfo();
1181 const DebugLoc &DL = MBB.findDebugLoc(MI);
1182 unsigned Align = FrameInfo.getObjectAlignment(FrameIndex);
1183 unsigned Size = FrameInfo.getObjectSize(FrameIndex);
1184 unsigned SpillSize = TRI->getSpillSize(*RC);
1185
1186 MachinePointerInfo PtrInfo
1187 = MachinePointerInfo::getFixedStack(*MF, FrameIndex);
1188
1189 MachineMemOperand *MMO = MF->getMachineMemOperand(
1190 PtrInfo, MachineMemOperand::MOLoad, Size, Align);
1191
1192 if (RI.isSGPRClass(RC)) {
1193 MFI->setHasSpilledSGPRs();
1194 assert(DestReg != AMDGPU::M0 && "m0 should not be reloaded into")((DestReg != AMDGPU::M0 && "m0 should not be reloaded into"
) ? static_cast<void> (0) : __assert_fail ("DestReg != AMDGPU::M0 && \"m0 should not be reloaded into\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1194, __PRETTY_FUNCTION__))
;
1195
1196 // FIXME: Maybe this should not include a memoperand because it will be
1197 // lowered to non-memory instructions.
1198 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
1199 if (Register::isVirtualRegister(DestReg) && SpillSize == 4) {
1200 MachineRegisterInfo &MRI = MF->getRegInfo();
1201 MRI.constrainRegClass(DestReg, &AMDGPU::SReg_32_XM0RegClass);
1202 }
1203
1204 if (RI.spillSGPRToVGPR())
1205 FrameInfo.setStackID(FrameIndex, TargetStackID::SGPRSpill);
1206 BuildMI(MBB, MI, DL, OpDesc, DestReg)
1207 .addFrameIndex(FrameIndex) // addr
1208 .addMemOperand(MMO)
1209 .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
1210 .addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit);
1211 return;
1212 }
1213
1214 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize)
1215 : getVGPRSpillRestoreOpcode(SpillSize);
1216 auto MIB = BuildMI(MBB, MI, DL, get(Opcode), DestReg);
1217 if (RI.hasAGPRs(RC)) {
1218 MachineRegisterInfo &MRI = MF->getRegInfo();
1219 Register Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1220 MIB.addReg(Tmp, RegState::Define);
1221 }
1222 MIB.addFrameIndex(FrameIndex) // vaddr
1223 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
1224 .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1225 .addImm(0) // offset
1226 .addMemOperand(MMO);
1227}
1228
1229/// \param @Offset Offset in bytes of the FrameIndex being spilled
1230unsigned SIInstrInfo::calculateLDSSpillAddress(
1231 MachineBasicBlock &MBB, MachineInstr &MI, RegScavenger *RS, unsigned TmpReg,
1232 unsigned FrameOffset, unsigned Size) const {
1233 MachineFunction *MF = MBB.getParent();
1234 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
1235 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
1236 const DebugLoc &DL = MBB.findDebugLoc(MI);
1237 unsigned WorkGroupSize = MFI->getMaxFlatWorkGroupSize();
1238 unsigned WavefrontSize = ST.getWavefrontSize();
1239
1240 unsigned TIDReg = MFI->getTIDReg();
1241 if (!MFI->hasCalculatedTID()) {
1242 MachineBasicBlock &Entry = MBB.getParent()->front();
1243 MachineBasicBlock::iterator Insert = Entry.front();
1244 const DebugLoc &DL = Insert->getDebugLoc();
1245
1246 TIDReg = RI.findUnusedRegister(MF->getRegInfo(), &AMDGPU::VGPR_32RegClass,
1247 *MF);
1248 if (TIDReg == AMDGPU::NoRegister)
1249 return TIDReg;
1250
1251 if (!AMDGPU::isShader(MF->getFunction().getCallingConv()) &&
1252 WorkGroupSize > WavefrontSize) {
1253 Register TIDIGXReg =
1254 MFI->getPreloadedReg(AMDGPUFunctionArgInfo::WORKGROUP_ID_X);
1255 Register TIDIGYReg =
1256 MFI->getPreloadedReg(AMDGPUFunctionArgInfo::WORKGROUP_ID_Y);
1257 Register TIDIGZReg =
1258 MFI->getPreloadedReg(AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
1259 Register InputPtrReg =
1260 MFI->getPreloadedReg(AMDGPUFunctionArgInfo::KERNARG_SEGMENT_PTR);
1261 for (unsigned Reg : {TIDIGXReg, TIDIGYReg, TIDIGZReg}) {
1262 if (!Entry.isLiveIn(Reg))
1263 Entry.addLiveIn(Reg);
1264 }
1265
1266 RS->enterBasicBlock(Entry);
1267 // FIXME: Can we scavenge an SReg_64 and access the subregs?
1268 unsigned STmp0 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
1269 unsigned STmp1 = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
1270 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
1271 .addReg(InputPtrReg)
1272 .addImm(SI::KernelInputOffsets::NGROUPS_Z);
1273 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
1274 .addReg(InputPtrReg)
1275 .addImm(SI::KernelInputOffsets::NGROUPS_Y);
1276
1277 // NGROUPS.X * NGROUPS.Y
1278 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
1279 .addReg(STmp1)
1280 .addReg(STmp0);
1281 // (NGROUPS.X * NGROUPS.Y) * TIDIG.X
1282 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
1283 .addReg(STmp1)
1284 .addReg(TIDIGXReg);
1285 // NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)
1286 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
1287 .addReg(STmp0)
1288 .addReg(TIDIGYReg)
1289 .addReg(TIDReg);
1290 // (NGROUPS.Z * TIDIG.Y + (NGROUPS.X * NGROPUS.Y * TIDIG.X)) + TIDIG.Z
1291 getAddNoCarry(Entry, Insert, DL, TIDReg)
1292 .addReg(TIDReg)
1293 .addReg(TIDIGZReg)
1294 .addImm(0); // clamp bit
1295 } else {
1296 // Get the wave id
1297 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
1298 TIDReg)
1299 .addImm(-1)
1300 .addImm(0);
1301
1302 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
1303 TIDReg)
1304 .addImm(-1)
1305 .addReg(TIDReg);
1306 }
1307
1308 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
1309 TIDReg)
1310 .addImm(2)
1311 .addReg(TIDReg);
1312 MFI->setTIDReg(TIDReg);
1313 }
1314
1315 // Add FrameIndex to LDS offset
1316 unsigned LDSOffset = MFI->getLDSSize() + (FrameOffset * WorkGroupSize);
1317 getAddNoCarry(MBB, MI, DL, TmpReg)
1318 .addImm(LDSOffset)
1319 .addReg(TIDReg)
1320 .addImm(0); // clamp bit
1321
1322 return TmpReg;
1323}
1324
1325void SIInstrInfo::insertWaitStates(MachineBasicBlock &MBB,
1326 MachineBasicBlock::iterator MI,
1327 int Count) const {
1328 DebugLoc DL = MBB.findDebugLoc(MI);
1329 while (Count > 0) {
1330 int Arg;
1331 if (Count >= 8)
1332 Arg = 7;
1333 else
1334 Arg = Count - 1;
1335 Count -= 8;
1336 BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP))
1337 .addImm(Arg);
1338 }
1339}
1340
1341void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,
1342 MachineBasicBlock::iterator MI) const {
1343 insertWaitStates(MBB, MI, 1);
1344}
1345
1346void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const {
1347 auto MF = MBB.getParent();
1348 SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
1349
1350 assert(Info->isEntryFunction())((Info->isEntryFunction()) ? static_cast<void> (0) :
__assert_fail ("Info->isEntryFunction()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1350, __PRETTY_FUNCTION__))
;
1351
1352 if (MBB.succ_empty()) {
1353 bool HasNoTerminator = MBB.getFirstTerminator() == MBB.end();
1354 if (HasNoTerminator) {
1355 if (Info->returnsVoid()) {
1356 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::S_ENDPGM)).addImm(0);
1357 } else {
1358 BuildMI(MBB, MBB.end(), DebugLoc(), get(AMDGPU::SI_RETURN_TO_EPILOG));
1359 }
1360 }
1361 }
1362}
1363
1364unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) {
1365 switch (MI.getOpcode()) {
1366 default: return 1; // FIXME: Do wait states equal cycles?
1367
1368 case AMDGPU::S_NOP:
1369 return MI.getOperand(0).getImm() + 1;
1370 }
1371}
1372
1373bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1374 MachineBasicBlock &MBB = *MI.getParent();
1375 DebugLoc DL = MBB.findDebugLoc(MI);
1376 switch (MI.getOpcode()) {
1
Control jumps to 'case V_SET_INACTIVE_B64:' at line 1464
5
Control jumps to 'case V_SET_INACTIVE_B64:' at line 1464
9
Control jumps to 'case V_SET_INACTIVE_B64:' at line 1464
13
Control jumps to 'case V_MOV_B64_DPP_PSEUDO:' at line 1448
1377 default: return TargetInstrInfo::expandPostRAPseudo(MI);
1378 case AMDGPU::S_MOV_B64_term:
1379 // This is only a terminator to get the correct spill code placement during
1380 // register allocation.
1381 MI.setDesc(get(AMDGPU::S_MOV_B64));
1382 break;
1383
1384 case AMDGPU::S_MOV_B32_term:
1385 // This is only a terminator to get the correct spill code placement during
1386 // register allocation.
1387 MI.setDesc(get(AMDGPU::S_MOV_B32));
1388 break;
1389
1390 case AMDGPU::S_XOR_B64_term:
1391 // This is only a terminator to get the correct spill code placement during
1392 // register allocation.
1393 MI.setDesc(get(AMDGPU::S_XOR_B64));
1394 break;
1395
1396 case AMDGPU::S_XOR_B32_term:
1397 // This is only a terminator to get the correct spill code placement during
1398 // register allocation.
1399 MI.setDesc(get(AMDGPU::S_XOR_B32));
1400 break;
1401
1402 case AMDGPU::S_OR_B32_term:
1403 // This is only a terminator to get the correct spill code placement during
1404 // register allocation.
1405 MI.setDesc(get(AMDGPU::S_OR_B32));
1406 break;
1407
1408 case AMDGPU::S_ANDN2_B64_term:
1409 // This is only a terminator to get the correct spill code placement during
1410 // register allocation.
1411 MI.setDesc(get(AMDGPU::S_ANDN2_B64));
1412 break;
1413
1414 case AMDGPU::S_ANDN2_B32_term:
1415 // This is only a terminator to get the correct spill code placement during
1416 // register allocation.
1417 MI.setDesc(get(AMDGPU::S_ANDN2_B32));
1418 break;
1419
1420 case AMDGPU::V_MOV_B64_PSEUDO: {
1421 Register Dst = MI.getOperand(0).getReg();
1422 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
1423 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
1424
1425 const MachineOperand &SrcOp = MI.getOperand(1);
1426 // FIXME: Will this work for 64-bit floating point immediates?
1427 assert(!SrcOp.isFPImm())((!SrcOp.isFPImm()) ? static_cast<void> (0) : __assert_fail
("!SrcOp.isFPImm()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1427, __PRETTY_FUNCTION__))
;
1428 if (SrcOp.isImm()) {
1429 APInt Imm(64, SrcOp.getImm());
1430 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1431 .addImm(Imm.getLoBits(32).getZExtValue())
1432 .addReg(Dst, RegState::Implicit | RegState::Define);
1433 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1434 .addImm(Imm.getHiBits(32).getZExtValue())
1435 .addReg(Dst, RegState::Implicit | RegState::Define);
1436 } else {
1437 assert(SrcOp.isReg())((SrcOp.isReg()) ? static_cast<void> (0) : __assert_fail
("SrcOp.isReg()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1437, __PRETTY_FUNCTION__))
;
1438 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1439 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
1440 .addReg(Dst, RegState::Implicit | RegState::Define);
1441 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1442 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
1443 .addReg(Dst, RegState::Implicit | RegState::Define);
1444 }
1445 MI.eraseFromParent();
1446 break;
1447 }
1448 case AMDGPU::V_MOV_B64_DPP_PSEUDO: {
1449 expandMovDPP64(MI);
14
Calling 'SIInstrInfo::expandMovDPP64'
1450 break;
1451 }
1452 case AMDGPU::V_SET_INACTIVE_B32: {
1453 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
1454 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
1455 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1456 .addReg(Exec);
1457 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
1458 .add(MI.getOperand(2));
1459 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1460 .addReg(Exec);
1461 MI.eraseFromParent();
1462 break;
1463 }
1464 case AMDGPU::V_SET_INACTIVE_B64: {
1465 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64;
2
'?' condition is false
6
'?' condition is false
10
'?' condition is false
1466 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
3
'?' condition is false
7
'?' condition is false
11
'?' condition is false
1467 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1468 .addReg(Exec);
1469 MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
1470 MI.getOperand(0).getReg())
1471 .add(MI.getOperand(2));
1472 expandPostRAPseudo(*Copy);
4
Calling 'SIInstrInfo::expandPostRAPseudo'
8
Calling 'SIInstrInfo::expandPostRAPseudo'
12
Calling 'SIInstrInfo::expandPostRAPseudo'
1473 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1474 .addReg(Exec);
1475 MI.eraseFromParent();
1476 break;
1477 }
1478 case AMDGPU::V_MOVRELD_B32_V1:
1479 case AMDGPU::V_MOVRELD_B32_V2:
1480 case AMDGPU::V_MOVRELD_B32_V4:
1481 case AMDGPU::V_MOVRELD_B32_V8:
1482 case AMDGPU::V_MOVRELD_B32_V16: {
1483 const MCInstrDesc &MovRelDesc = get(AMDGPU::V_MOVRELD_B32_e32);
1484 Register VecReg = MI.getOperand(0).getReg();
1485 bool IsUndef = MI.getOperand(1).isUndef();
1486 unsigned SubReg = AMDGPU::sub0 + MI.getOperand(3).getImm();
1487 assert(VecReg == MI.getOperand(1).getReg())((VecReg == MI.getOperand(1).getReg()) ? static_cast<void>
(0) : __assert_fail ("VecReg == MI.getOperand(1).getReg()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1487, __PRETTY_FUNCTION__))
;
1488
1489 MachineInstr *MovRel =
1490 BuildMI(MBB, MI, DL, MovRelDesc)
1491 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1492 .add(MI.getOperand(2))
1493 .addReg(VecReg, RegState::ImplicitDefine)
1494 .addReg(VecReg,
1495 RegState::Implicit | (IsUndef ? RegState::Undef : 0));
1496
1497 const int ImpDefIdx =
1498 MovRelDesc.getNumOperands() + MovRelDesc.getNumImplicitUses();
1499 const int ImpUseIdx = ImpDefIdx + 1;
1500 MovRel->tieOperands(ImpDefIdx, ImpUseIdx);
1501
1502 MI.eraseFromParent();
1503 break;
1504 }
1505 case AMDGPU::SI_PC_ADD_REL_OFFSET: {
1506 MachineFunction &MF = *MBB.getParent();
1507 Register Reg = MI.getOperand(0).getReg();
1508 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
1509 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
1510
1511 // Create a bundle so these instructions won't be re-ordered by the
1512 // post-RA scheduler.
1513 MIBundleBuilder Bundler(MBB, MI);
1514 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_GETPC_B64), Reg));
1515
1516 // Add 32-bit offset from this instruction to the start of the
1517 // constant data.
1518 Bundler.append(BuildMI(MF, DL, get(AMDGPU::S_ADD_U32), RegLo)
1519 .addReg(RegLo)
1520 .add(MI.getOperand(1)));
1521
1522 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
1523 .addReg(RegHi);
1524 MIB.add(MI.getOperand(2));
1525
1526 Bundler.append(MIB);
1527 finalizeBundle(MBB, Bundler.begin());
1528
1529 MI.eraseFromParent();
1530 break;
1531 }
1532 case AMDGPU::ENTER_WWM: {
1533 // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
1534 // WWM is entered.
1535 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
1536 : AMDGPU::S_OR_SAVEEXEC_B64));
1537 break;
1538 }
1539 case AMDGPU::EXIT_WWM: {
1540 // This only gets its own opcode so that SIPreAllocateWWMRegs can tell when
1541 // WWM is exited.
1542 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64));
1543 break;
1544 }
1545 case TargetOpcode::BUNDLE: {
1546 if (!MI.mayLoad() || MI.hasUnmodeledSideEffects())
1547 return false;
1548
1549 // If it is a load it must be a memory clause
1550 for (MachineBasicBlock::instr_iterator I = MI.getIterator();
1551 I->isBundledWithSucc(); ++I) {
1552 I->unbundleFromSucc();
1553 for (MachineOperand &MO : I->operands())
1554 if (MO.isReg())
1555 MO.setIsInternalRead(false);
1556 }
1557
1558 MI.eraseFromParent();
1559 break;
1560 }
1561 }
1562 return true;
1563}
1564
1565std::pair<MachineInstr*, MachineInstr*>
1566SIInstrInfo::expandMovDPP64(MachineInstr &MI) const {
1567 assert (MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO)((MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO) ? static_cast
<void> (0) : __assert_fail ("MI.getOpcode() == AMDGPU::V_MOV_B64_DPP_PSEUDO"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1567, __PRETTY_FUNCTION__))
;
15
'?' condition is true
1568
1569 MachineBasicBlock &MBB = *MI.getParent();
1570 DebugLoc DL = MBB.findDebugLoc(MI);
1571 MachineFunction *MF = MBB.getParent();
1572 MachineRegisterInfo &MRI = MF->getRegInfo();
1573 Register Dst = MI.getOperand(0).getReg();
1574 unsigned Part = 0;
1575 MachineInstr *Split[2];
1576
1577
1578 for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) {
16
Assuming '__begin1' is equal to '__end1'
1579 auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
1580 if (Dst.isPhysical()) {
1581 MovDPP.addDef(RI.getSubReg(Dst, Sub));
1582 } else {
1583 assert(MRI.isSSA())((MRI.isSSA()) ? static_cast<void> (0) : __assert_fail (
"MRI.isSSA()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1583, __PRETTY_FUNCTION__))
;
1584 auto Tmp = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1585 MovDPP.addDef(Tmp);
1586 }
1587
1588 for (unsigned I = 1; I <= 2; ++I) { // old and src operands.
1589 const MachineOperand &SrcOp = MI.getOperand(I);
1590 assert(!SrcOp.isFPImm())((!SrcOp.isFPImm()) ? static_cast<void> (0) : __assert_fail
("!SrcOp.isFPImm()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1590, __PRETTY_FUNCTION__))
;
1591 if (SrcOp.isImm()) {
1592 APInt Imm(64, SrcOp.getImm());
1593 Imm.ashrInPlace(Part * 32);
1594 MovDPP.addImm(Imm.getLoBits(32).getZExtValue());
1595 } else {
1596 assert(SrcOp.isReg())((SrcOp.isReg()) ? static_cast<void> (0) : __assert_fail
("SrcOp.isReg()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1596, __PRETTY_FUNCTION__))
;
1597 Register Src = SrcOp.getReg();
1598 if (Src.isPhysical())
1599 MovDPP.addReg(RI.getSubReg(Src, Sub));
1600 else
1601 MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
1602 }
1603 }
1604
1605 for (unsigned I = 3; I < MI.getNumExplicitOperands(); ++I)
1606 MovDPP.addImm(MI.getOperand(I).getImm());
1607
1608 Split[Part] = MovDPP;
1609 ++Part;
1610 }
1611
1612 if (Dst.isVirtual())
17
Assuming the condition is true
18
Taking true branch
1613 BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
1614 .addReg(Split[0]->getOperand(0).getReg())
19
Called C++ object pointer is uninitialized
1615 .addImm(AMDGPU::sub0)
1616 .addReg(Split[1]->getOperand(0).getReg())
1617 .addImm(AMDGPU::sub1);
1618
1619 MI.eraseFromParent();
1620 return std::make_pair(Split[0], Split[1]);
1621}
1622
1623bool SIInstrInfo::swapSourceModifiers(MachineInstr &MI,
1624 MachineOperand &Src0,
1625 unsigned Src0OpName,
1626 MachineOperand &Src1,
1627 unsigned Src1OpName) const {
1628 MachineOperand *Src0Mods = getNamedOperand(MI, Src0OpName);
1629 if (!Src0Mods)
1630 return false;
1631
1632 MachineOperand *Src1Mods = getNamedOperand(MI, Src1OpName);
1633 assert(Src1Mods &&((Src1Mods && "All commutable instructions have both src0 and src1 modifiers"
) ? static_cast<void> (0) : __assert_fail ("Src1Mods && \"All commutable instructions have both src0 and src1 modifiers\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1634, __PRETTY_FUNCTION__))
1634 "All commutable instructions have both src0 and src1 modifiers")((Src1Mods && "All commutable instructions have both src0 and src1 modifiers"
) ? static_cast<void> (0) : __assert_fail ("Src1Mods && \"All commutable instructions have both src0 and src1 modifiers\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1634, __PRETTY_FUNCTION__))
;
1635
1636 int Src0ModsVal = Src0Mods->getImm();
1637 int Src1ModsVal = Src1Mods->getImm();
1638
1639 Src1Mods->setImm(Src0ModsVal);
1640 Src0Mods->setImm(Src1ModsVal);
1641 return true;
1642}
1643
1644static MachineInstr *swapRegAndNonRegOperand(MachineInstr &MI,
1645 MachineOperand &RegOp,
1646 MachineOperand &NonRegOp) {
1647 Register Reg = RegOp.getReg();
1648 unsigned SubReg = RegOp.getSubReg();
1649 bool IsKill = RegOp.isKill();
1650 bool IsDead = RegOp.isDead();
1651 bool IsUndef = RegOp.isUndef();
1652 bool IsDebug = RegOp.isDebug();
1653
1654 if (NonRegOp.isImm())
1655 RegOp.ChangeToImmediate(NonRegOp.getImm());
1656 else if (NonRegOp.isFI())
1657 RegOp.ChangeToFrameIndex(NonRegOp.getIndex());
1658 else
1659 return nullptr;
1660
1661 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug);
1662 NonRegOp.setSubReg(SubReg);
1663
1664 return &MI;
1665}
1666
1667MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
1668 unsigned Src0Idx,
1669 unsigned Src1Idx) const {
1670 assert(!NewMI && "this should never be used")((!NewMI && "this should never be used") ? static_cast
<void> (0) : __assert_fail ("!NewMI && \"this should never be used\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1670, __PRETTY_FUNCTION__))
;
1671
1672 unsigned Opc = MI.getOpcode();
1673 int CommutedOpcode = commuteOpcode(Opc);
1674 if (CommutedOpcode == -1)
1675 return nullptr;
1676
1677 assert(AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) ==((AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) == static_cast
<int>(Src0Idx) && AMDGPU::getNamedOperandIdx(Opc
, AMDGPU::OpName::src1) == static_cast<int>(Src1Idx) &&
"inconsistency with findCommutedOpIndices") ? static_cast<
void> (0) : __assert_fail ("AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) == static_cast<int>(Src0Idx) && AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) == static_cast<int>(Src1Idx) && \"inconsistency with findCommutedOpIndices\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1681, __PRETTY_FUNCTION__))
1678 static_cast<int>(Src0Idx) &&((AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) == static_cast
<int>(Src0Idx) && AMDGPU::getNamedOperandIdx(Opc
, AMDGPU::OpName::src1) == static_cast<int>(Src1Idx) &&
"inconsistency with findCommutedOpIndices") ? static_cast<
void> (0) : __assert_fail ("AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) == static_cast<int>(Src0Idx) && AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) == static_cast<int>(Src1Idx) && \"inconsistency with findCommutedOpIndices\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1681, __PRETTY_FUNCTION__))
1679 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) ==((AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) == static_cast
<int>(Src0Idx) && AMDGPU::getNamedOperandIdx(Opc
, AMDGPU::OpName::src1) == static_cast<int>(Src1Idx) &&
"inconsistency with findCommutedOpIndices") ? static_cast<
void> (0) : __assert_fail ("AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) == static_cast<int>(Src0Idx) && AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) == static_cast<int>(Src1Idx) && \"inconsistency with findCommutedOpIndices\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1681, __PRETTY_FUNCTION__))
1680 static_cast<int>(Src1Idx) &&((AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) == static_cast
<int>(Src0Idx) && AMDGPU::getNamedOperandIdx(Opc
, AMDGPU::OpName::src1) == static_cast<int>(Src1Idx) &&
"inconsistency with findCommutedOpIndices") ? static_cast<
void> (0) : __assert_fail ("AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) == static_cast<int>(Src0Idx) && AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) == static_cast<int>(Src1Idx) && \"inconsistency with findCommutedOpIndices\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1681, __PRETTY_FUNCTION__))
1681 "inconsistency with findCommutedOpIndices")((AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) == static_cast
<int>(Src0Idx) && AMDGPU::getNamedOperandIdx(Opc
, AMDGPU::OpName::src1) == static_cast<int>(Src1Idx) &&
"inconsistency with findCommutedOpIndices") ? static_cast<
void> (0) : __assert_fail ("AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0) == static_cast<int>(Src0Idx) && AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1) == static_cast<int>(Src1Idx) && \"inconsistency with findCommutedOpIndices\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1681, __PRETTY_FUNCTION__))
;
1682
1683 MachineOperand &Src0 = MI.getOperand(Src0Idx);
1684 MachineOperand &Src1 = MI.getOperand(Src1Idx);
1685
1686 MachineInstr *CommutedMI = nullptr;
1687 if (Src0.isReg() && Src1.isReg()) {
1688 if (isOperandLegal(MI, Src1Idx, &Src0)) {
1689 // Be sure to copy the source modifiers to the right place.
1690 CommutedMI
1691 = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, Src0Idx, Src1Idx);
1692 }
1693
1694 } else if (Src0.isReg() && !Src1.isReg()) {
1695 // src0 should always be able to support any operand type, so no need to
1696 // check operand legality.
1697 CommutedMI = swapRegAndNonRegOperand(MI, Src0, Src1);
1698 } else if (!Src0.isReg() && Src1.isReg()) {
1699 if (isOperandLegal(MI, Src1Idx, &Src0))
1700 CommutedMI = swapRegAndNonRegOperand(MI, Src1, Src0);
1701 } else {
1702 // FIXME: Found two non registers to commute. This does happen.
1703 return nullptr;
1704 }
1705
1706 if (CommutedMI) {
1707 swapSourceModifiers(MI, Src0, AMDGPU::OpName::src0_modifiers,
1708 Src1, AMDGPU::OpName::src1_modifiers);
1709
1710 CommutedMI->setDesc(get(CommutedOpcode));
1711 }
1712
1713 return CommutedMI;
1714}
1715
1716// This needs to be implemented because the source modifiers may be inserted
1717// between the true commutable operands, and the base
1718// TargetInstrInfo::commuteInstruction uses it.
1719bool SIInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
1720 unsigned &SrcOpIdx0,
1721 unsigned &SrcOpIdx1) const {
1722 return findCommutedOpIndices(MI.getDesc(), SrcOpIdx0, SrcOpIdx1);
1723}
1724
1725bool SIInstrInfo::findCommutedOpIndices(MCInstrDesc Desc, unsigned &SrcOpIdx0,
1726 unsigned &SrcOpIdx1) const {
1727 if (!Desc.isCommutable())
1728 return false;
1729
1730 unsigned Opc = Desc.getOpcode();
1731 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
1732 if (Src0Idx == -1)
1733 return false;
1734
1735 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1736 if (Src1Idx == -1)
1737 return false;
1738
1739 return fixCommutedOpIndices(SrcOpIdx0, SrcOpIdx1, Src0Idx, Src1Idx);
1740}
1741
1742bool SIInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
1743 int64_t BrOffset) const {
1744 // BranchRelaxation should never have to check s_setpc_b64 because its dest
1745 // block is unanalyzable.
1746 assert(BranchOp != AMDGPU::S_SETPC_B64)((BranchOp != AMDGPU::S_SETPC_B64) ? static_cast<void> (
0) : __assert_fail ("BranchOp != AMDGPU::S_SETPC_B64", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1746, __PRETTY_FUNCTION__))
;
1747
1748 // Convert to dwords.
1749 BrOffset /= 4;
1750
1751 // The branch instructions do PC += signext(SIMM16 * 4) + 4, so the offset is
1752 // from the next instruction.
1753 BrOffset -= 1;
1754
1755 return isIntN(BranchOffsetBits, BrOffset);
1756}
1757
1758MachineBasicBlock *SIInstrInfo::getBranchDestBlock(
1759 const MachineInstr &MI) const {
1760 if (MI.getOpcode() == AMDGPU::S_SETPC_B64) {
1761 // This would be a difficult analysis to perform, but can always be legal so
1762 // there's no need to analyze it.
1763 return nullptr;
1764 }
1765
1766 return MI.getOperand(0).getMBB();
1767}
1768
1769unsigned SIInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
1770 MachineBasicBlock &DestBB,
1771 const DebugLoc &DL,
1772 int64_t BrOffset,
1773 RegScavenger *RS) const {
1774 assert(RS && "RegScavenger required for long branching")((RS && "RegScavenger required for long branching") ?
static_cast<void> (0) : __assert_fail ("RS && \"RegScavenger required for long branching\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1774, __PRETTY_FUNCTION__))
;
1775 assert(MBB.empty() &&((MBB.empty() && "new block should be inserted for expanding unconditional branch"
) ? static_cast<void> (0) : __assert_fail ("MBB.empty() && \"new block should be inserted for expanding unconditional branch\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1776, __PRETTY_FUNCTION__))
1776 "new block should be inserted for expanding unconditional branch")((MBB.empty() && "new block should be inserted for expanding unconditional branch"
) ? static_cast<void> (0) : __assert_fail ("MBB.empty() && \"new block should be inserted for expanding unconditional branch\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1776, __PRETTY_FUNCTION__))
;
1777 assert(MBB.pred_size() == 1)((MBB.pred_size() == 1) ? static_cast<void> (0) : __assert_fail
("MBB.pred_size() == 1", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1777, __PRETTY_FUNCTION__))
;
1778
1779 MachineFunction *MF = MBB.getParent();
1780 MachineRegisterInfo &MRI = MF->getRegInfo();
1781
1782 // FIXME: Virtual register workaround for RegScavenger not working with empty
1783 // blocks.
1784 Register PCReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1785
1786 auto I = MBB.end();
1787
1788 // We need to compute the offset relative to the instruction immediately after
1789 // s_getpc_b64. Insert pc arithmetic code before last terminator.
1790 MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
1791
1792 // TODO: Handle > 32-bit block address.
1793 if (BrOffset >= 0) {
1794 BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
1795 .addReg(PCReg, RegState::Define, AMDGPU::sub0)
1796 .addReg(PCReg, 0, AMDGPU::sub0)
1797 .addMBB(&DestBB, MO_LONG_BRANCH_FORWARD);
1798 BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
1799 .addReg(PCReg, RegState::Define, AMDGPU::sub1)
1800 .addReg(PCReg, 0, AMDGPU::sub1)
1801 .addImm(0);
1802 } else {
1803 // Backwards branch.
1804 BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32))
1805 .addReg(PCReg, RegState::Define, AMDGPU::sub0)
1806 .addReg(PCReg, 0, AMDGPU::sub0)
1807 .addMBB(&DestBB, MO_LONG_BRANCH_BACKWARD);
1808 BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32))
1809 .addReg(PCReg, RegState::Define, AMDGPU::sub1)
1810 .addReg(PCReg, 0, AMDGPU::sub1)
1811 .addImm(0);
1812 }
1813
1814 // Insert the indirect branch after the other terminator.
1815 BuildMI(&MBB, DL, get(AMDGPU::S_SETPC_B64))
1816 .addReg(PCReg);
1817
1818 // FIXME: If spilling is necessary, this will fail because this scavenger has
1819 // no emergency stack slots. It is non-trivial to spill in this situation,
1820 // because the restore code needs to be specially placed after the
1821 // jump. BranchRelaxation then needs to be made aware of the newly inserted
1822 // block.
1823 //
1824 // If a spill is needed for the pc register pair, we need to insert a spill
1825 // restore block right before the destination block, and insert a short branch
1826 // into the old destination block's fallthrough predecessor.
1827 // e.g.:
1828 //
1829 // s_cbranch_scc0 skip_long_branch:
1830 //
1831 // long_branch_bb:
1832 // spill s[8:9]
1833 // s_getpc_b64 s[8:9]
1834 // s_add_u32 s8, s8, restore_bb
1835 // s_addc_u32 s9, s9, 0
1836 // s_setpc_b64 s[8:9]
1837 //
1838 // skip_long_branch:
1839 // foo;
1840 //
1841 // .....
1842 //
1843 // dest_bb_fallthrough_predecessor:
1844 // bar;
1845 // s_branch dest_bb
1846 //
1847 // restore_bb:
1848 // restore s[8:9]
1849 // fallthrough dest_bb
1850 ///
1851 // dest_bb:
1852 // buzz;
1853
1854 RS->enterBasicBlockEnd(MBB);
1855 unsigned Scav = RS->scavengeRegisterBackwards(
1856 AMDGPU::SReg_64RegClass,
1857 MachineBasicBlock::iterator(GetPC), false, 0);
1858 MRI.replaceRegWith(PCReg, Scav);
1859 MRI.clearVirtRegs();
1860 RS->setRegUsed(Scav);
1861
1862 return 4 + 8 + 4 + 4;
1863}
1864
1865unsigned SIInstrInfo::getBranchOpcode(SIInstrInfo::BranchPredicate Cond) {
1866 switch (Cond) {
1867 case SIInstrInfo::SCC_TRUE:
1868 return AMDGPU::S_CBRANCH_SCC1;
1869 case SIInstrInfo::SCC_FALSE:
1870 return AMDGPU::S_CBRANCH_SCC0;
1871 case SIInstrInfo::VCCNZ:
1872 return AMDGPU::S_CBRANCH_VCCNZ;
1873 case SIInstrInfo::VCCZ:
1874 return AMDGPU::S_CBRANCH_VCCZ;
1875 case SIInstrInfo::EXECNZ:
1876 return AMDGPU::S_CBRANCH_EXECNZ;
1877 case SIInstrInfo::EXECZ:
1878 return AMDGPU::S_CBRANCH_EXECZ;
1879 default:
1880 llvm_unreachable("invalid branch predicate")::llvm::llvm_unreachable_internal("invalid branch predicate",
"/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1880)
;
1881 }
1882}
1883
1884SIInstrInfo::BranchPredicate SIInstrInfo::getBranchPredicate(unsigned Opcode) {
1885 switch (Opcode) {
1886 case AMDGPU::S_CBRANCH_SCC0:
1887 return SCC_FALSE;
1888 case AMDGPU::S_CBRANCH_SCC1:
1889 return SCC_TRUE;
1890 case AMDGPU::S_CBRANCH_VCCNZ:
1891 return VCCNZ;
1892 case AMDGPU::S_CBRANCH_VCCZ:
1893 return VCCZ;
1894 case AMDGPU::S_CBRANCH_EXECNZ:
1895 return EXECNZ;
1896 case AMDGPU::S_CBRANCH_EXECZ:
1897 return EXECZ;
1898 default:
1899 return INVALID_BR;
1900 }
1901}
1902
1903bool SIInstrInfo::analyzeBranchImpl(MachineBasicBlock &MBB,
1904 MachineBasicBlock::iterator I,
1905 MachineBasicBlock *&TBB,
1906 MachineBasicBlock *&FBB,
1907 SmallVectorImpl<MachineOperand> &Cond,
1908 bool AllowModify) const {
1909 if (I->getOpcode() == AMDGPU::S_BRANCH) {
1910 // Unconditional Branch
1911 TBB = I->getOperand(0).getMBB();
1912 return false;
1913 }
1914
1915 MachineBasicBlock *CondBB = nullptr;
1916
1917 if (I->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
1918 CondBB = I->getOperand(1).getMBB();
1919 Cond.push_back(I->getOperand(0));
1920 } else {
1921 BranchPredicate Pred = getBranchPredicate(I->getOpcode());
1922 if (Pred == INVALID_BR)
1923 return true;
1924
1925 CondBB = I->getOperand(0).getMBB();
1926 Cond.push_back(MachineOperand::CreateImm(Pred));
1927 Cond.push_back(I->getOperand(1)); // Save the branch register.
1928 }
1929 ++I;
1930
1931 if (I == MBB.end()) {
1932 // Conditional branch followed by fall-through.
1933 TBB = CondBB;
1934 return false;
1935 }
1936
1937 if (I->getOpcode() == AMDGPU::S_BRANCH) {
1938 TBB = CondBB;
1939 FBB = I->getOperand(0).getMBB();
1940 return false;
1941 }
1942
1943 return true;
1944}
1945
1946bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
1947 MachineBasicBlock *&FBB,
1948 SmallVectorImpl<MachineOperand> &Cond,
1949 bool AllowModify) const {
1950 MachineBasicBlock::iterator I = MBB.getFirstTerminator();
1951 auto E = MBB.end();
1952 if (I == E)
1953 return false;
1954
1955 // Skip over the instructions that are artificially terminators for special
1956 // exec management.
1957 while (I != E && !I->isBranch() && !I->isReturn() &&
1958 I->getOpcode() != AMDGPU::SI_MASK_BRANCH) {
1959 switch (I->getOpcode()) {
1960 case AMDGPU::SI_MASK_BRANCH:
1961 case AMDGPU::S_MOV_B64_term:
1962 case AMDGPU::S_XOR_B64_term:
1963 case AMDGPU::S_ANDN2_B64_term:
1964 case AMDGPU::S_MOV_B32_term:
1965 case AMDGPU::S_XOR_B32_term:
1966 case AMDGPU::S_OR_B32_term:
1967 case AMDGPU::S_ANDN2_B32_term:
1968 break;
1969 case AMDGPU::SI_IF:
1970 case AMDGPU::SI_ELSE:
1971 case AMDGPU::SI_KILL_I1_TERMINATOR:
1972 case AMDGPU::SI_KILL_F32_COND_IMM_TERMINATOR:
1973 // FIXME: It's messy that these need to be considered here at all.
1974 return true;
1975 default:
1976 llvm_unreachable("unexpected non-branch terminator inst")::llvm::llvm_unreachable_internal("unexpected non-branch terminator inst"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 1976)
;
1977 }
1978
1979 ++I;
1980 }
1981
1982 if (I == E)
1983 return false;
1984
1985 if (I->getOpcode() != AMDGPU::SI_MASK_BRANCH)
1986 return analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify);
1987
1988 ++I;
1989
1990 // TODO: Should be able to treat as fallthrough?
1991 if (I == MBB.end())
1992 return true;
1993
1994 if (analyzeBranchImpl(MBB, I, TBB, FBB, Cond, AllowModify))
1995 return true;
1996
1997 MachineBasicBlock *MaskBrDest = I->getOperand(0).getMBB();
1998
1999 // Specifically handle the case where the conditional branch is to the same
2000 // destination as the mask branch. e.g.
2001 //
2002 // si_mask_branch BB8
2003 // s_cbranch_execz BB8
2004 // s_cbranch BB9
2005 //
2006 // This is required to understand divergent loops which may need the branches
2007 // to be relaxed.
2008 if (TBB != MaskBrDest || Cond.empty())
2009 return true;
2010
2011 auto Pred = Cond[0].getImm();
2012 return (Pred != EXECZ && Pred != EXECNZ);
2013}
2014
2015unsigned SIInstrInfo::removeBranch(MachineBasicBlock &MBB,
2016 int *BytesRemoved) const {
2017 MachineBasicBlock::iterator I = MBB.getFirstTerminator();
2018
2019 unsigned Count = 0;
2020 unsigned RemovedSize = 0;
2021 while (I != MBB.end()) {
2022 MachineBasicBlock::iterator Next = std::next(I);
2023 if (I->getOpcode() == AMDGPU::SI_MASK_BRANCH) {
2024 I = Next;
2025 continue;
2026 }
2027
2028 RemovedSize += getInstSizeInBytes(*I);
2029 I->eraseFromParent();
2030 ++Count;
2031 I = Next;
2032 }
2033
2034 if (BytesRemoved)
2035 *BytesRemoved = RemovedSize;
2036
2037 return Count;
2038}
2039
2040// Copy the flags onto the implicit condition register operand.
2041static void preserveCondRegFlags(MachineOperand &CondReg,
2042 const MachineOperand &OrigCond) {
2043 CondReg.setIsUndef(OrigCond.isUndef());
2044 CondReg.setIsKill(OrigCond.isKill());
2045}
2046
2047unsigned SIInstrInfo::insertBranch(MachineBasicBlock &MBB,
2048 MachineBasicBlock *TBB,
2049 MachineBasicBlock *FBB,
2050 ArrayRef<MachineOperand> Cond,
2051 const DebugLoc &DL,
2052 int *BytesAdded) const {
2053 if (!FBB && Cond.empty()) {
2054 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2055 .addMBB(TBB);
2056 if (BytesAdded)
2057 *BytesAdded = 4;
2058 return 1;
2059 }
2060
2061 if(Cond.size() == 1 && Cond[0].isReg()) {
2062 BuildMI(&MBB, DL, get(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO))
2063 .add(Cond[0])
2064 .addMBB(TBB);
2065 return 1;
2066 }
2067
2068 assert(TBB && Cond[0].isImm())((TBB && Cond[0].isImm()) ? static_cast<void> (
0) : __assert_fail ("TBB && Cond[0].isImm()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2068, __PRETTY_FUNCTION__))
;
2069
2070 unsigned Opcode
2071 = getBranchOpcode(static_cast<BranchPredicate>(Cond[0].getImm()));
2072
2073 if (!FBB) {
2074 Cond[1].isUndef();
2075 MachineInstr *CondBr =
2076 BuildMI(&MBB, DL, get(Opcode))
2077 .addMBB(TBB);
2078
2079 // Copy the flags onto the implicit condition register operand.
2080 preserveCondRegFlags(CondBr->getOperand(1), Cond[1]);
2081
2082 if (BytesAdded)
2083 *BytesAdded = 4;
2084 return 1;
2085 }
2086
2087 assert(TBB && FBB)((TBB && FBB) ? static_cast<void> (0) : __assert_fail
("TBB && FBB", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2087, __PRETTY_FUNCTION__))
;
2088
2089 MachineInstr *CondBr =
2090 BuildMI(&MBB, DL, get(Opcode))
2091 .addMBB(TBB);
2092 BuildMI(&MBB, DL, get(AMDGPU::S_BRANCH))
2093 .addMBB(FBB);
2094
2095 MachineOperand &CondReg = CondBr->getOperand(1);
2096 CondReg.setIsUndef(Cond[1].isUndef());
2097 CondReg.setIsKill(Cond[1].isKill());
2098
2099 if (BytesAdded)
2100 *BytesAdded = 8;
2101
2102 return 2;
2103}
2104
2105bool SIInstrInfo::reverseBranchCondition(
2106 SmallVectorImpl<MachineOperand> &Cond) const {
2107 if (Cond.size() != 2) {
2108 return true;
2109 }
2110
2111 if (Cond[0].isImm()) {
2112 Cond[0].setImm(-Cond[0].getImm());
2113 return false;
2114 }
2115
2116 return true;
2117}
2118
2119bool SIInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
2120 ArrayRef<MachineOperand> Cond,
2121 unsigned TrueReg, unsigned FalseReg,
2122 int &CondCycles,
2123 int &TrueCycles, int &FalseCycles) const {
2124 switch (Cond[0].getImm()) {
2125 case VCCNZ:
2126 case VCCZ: {
2127 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2128 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2129 assert(MRI.getRegClass(FalseReg) == RC)((MRI.getRegClass(FalseReg) == RC) ? static_cast<void> (
0) : __assert_fail ("MRI.getRegClass(FalseReg) == RC", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2129, __PRETTY_FUNCTION__))
;
2130
2131 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
2132 CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
2133
2134 // Limit to equal cost for branch vs. N v_cndmask_b32s.
2135 return RI.hasVGPRs(RC) && NumInsts <= 6;
2136 }
2137 case SCC_TRUE:
2138 case SCC_FALSE: {
2139 // FIXME: We could insert for VGPRs if we could replace the original compare
2140 // with a vector one.
2141 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2142 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2143 assert(MRI.getRegClass(FalseReg) == RC)((MRI.getRegClass(FalseReg) == RC) ? static_cast<void> (
0) : __assert_fail ("MRI.getRegClass(FalseReg) == RC", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2143, __PRETTY_FUNCTION__))
;
2144
2145 int NumInsts = AMDGPU::getRegBitWidth(RC->getID()) / 32;
2146
2147 // Multiples of 8 can do s_cselect_b64
2148 if (NumInsts % 2 == 0)
2149 NumInsts /= 2;
2150
2151 CondCycles = TrueCycles = FalseCycles = NumInsts; // ???
2152 return RI.isSGPRClass(RC);
2153 }
2154 default:
2155 return false;
2156 }
2157}
2158
2159void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,
2160 MachineBasicBlock::iterator I, const DebugLoc &DL,
2161 unsigned DstReg, ArrayRef<MachineOperand> Cond,
2162 unsigned TrueReg, unsigned FalseReg) const {
2163 BranchPredicate Pred = static_cast<BranchPredicate>(Cond[0].getImm());
2164 if (Pred == VCCZ || Pred == SCC_FALSE) {
2165 Pred = static_cast<BranchPredicate>(-Pred);
2166 std::swap(TrueReg, FalseReg);
2167 }
2168
2169 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2170 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
2171 unsigned DstSize = RI.getRegSizeInBits(*DstRC);
2172
2173 if (DstSize == 32) {
2174 unsigned SelOp = Pred == SCC_TRUE ?
2175 AMDGPU::S_CSELECT_B32 : AMDGPU::V_CNDMASK_B32_e32;
2176
2177 // Instruction's operands are backwards from what is expected.
2178 MachineInstr *Select =
2179 BuildMI(MBB, I, DL, get(SelOp), DstReg)
2180 .addReg(FalseReg)
2181 .addReg(TrueReg);
2182
2183 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2184 return;
2185 }
2186
2187 if (DstSize == 64 && Pred == SCC_TRUE) {
2188 MachineInstr *Select =
2189 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
2190 .addReg(FalseReg)
2191 .addReg(TrueReg);
2192
2193 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2194 return;
2195 }
2196
2197 static const int16_t Sub0_15[] = {
2198 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3,
2199 AMDGPU::sub4, AMDGPU::sub5, AMDGPU::sub6, AMDGPU::sub7,
2200 AMDGPU::sub8, AMDGPU::sub9, AMDGPU::sub10, AMDGPU::sub11,
2201 AMDGPU::sub12, AMDGPU::sub13, AMDGPU::sub14, AMDGPU::sub15,
2202 };
2203
2204 static const int16_t Sub0_15_64[] = {
2205 AMDGPU::sub0_sub1, AMDGPU::sub2_sub3,
2206 AMDGPU::sub4_sub5, AMDGPU::sub6_sub7,
2207 AMDGPU::sub8_sub9, AMDGPU::sub10_sub11,
2208 AMDGPU::sub12_sub13, AMDGPU::sub14_sub15,
2209 };
2210
2211 unsigned SelOp = AMDGPU::V_CNDMASK_B32_e32;
2212 const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass;
2213 const int16_t *SubIndices = Sub0_15;
2214 int NElts = DstSize / 32;
2215
2216 // 64-bit select is only available for SALU.
2217 // TODO: Split 96-bit into 64-bit and 32-bit, not 3x 32-bit.
2218 if (Pred == SCC_TRUE) {
2219 if (NElts % 2) {
2220 SelOp = AMDGPU::S_CSELECT_B32;
2221 EltRC = &AMDGPU::SGPR_32RegClass;
2222 } else {
2223 SelOp = AMDGPU::S_CSELECT_B64;
2224 EltRC = &AMDGPU::SGPR_64RegClass;
2225 SubIndices = Sub0_15_64;
2226 NElts /= 2;
2227 }
2228 }
2229
2230 MachineInstrBuilder MIB = BuildMI(
2231 MBB, I, DL, get(AMDGPU::REG_SEQUENCE), DstReg);
2232
2233 I = MIB->getIterator();
2234
2235 SmallVector<unsigned, 8> Regs;
2236 for (int Idx = 0; Idx != NElts; ++Idx) {
2237 Register DstElt = MRI.createVirtualRegister(EltRC);
2238 Regs.push_back(DstElt);
2239
2240 unsigned SubIdx = SubIndices[Idx];
2241
2242 MachineInstr *Select =
2243 BuildMI(MBB, I, DL, get(SelOp), DstElt)
2244 .addReg(FalseReg, 0, SubIdx)
2245 .addReg(TrueReg, 0, SubIdx);
2246 preserveCondRegFlags(Select->getOperand(3), Cond[1]);
2247 fixImplicitOperands(*Select);
2248
2249 MIB.addReg(DstElt)
2250 .addImm(SubIdx);
2251 }
2252}
2253
2254bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) const {
2255 switch (MI.getOpcode()) {
2256 case AMDGPU::V_MOV_B32_e32:
2257 case AMDGPU::V_MOV_B32_e64:
2258 case AMDGPU::V_MOV_B64_PSEUDO: {
2259 // If there are additional implicit register operands, this may be used for
2260 // register indexing so the source register operand isn't simply copied.
2261 unsigned NumOps = MI.getDesc().getNumOperands() +
2262 MI.getDesc().getNumImplicitUses();
2263
2264 return MI.getNumOperands() == NumOps;
2265 }
2266 case AMDGPU::S_MOV_B32:
2267 case AMDGPU::S_MOV_B64:
2268 case AMDGPU::COPY:
2269 case AMDGPU::V_ACCVGPR_WRITE_B32:
2270 case AMDGPU::V_ACCVGPR_READ_B32:
2271 return true;
2272 default:
2273 return false;
2274 }
2275}
2276
2277unsigned SIInstrInfo::getAddressSpaceForPseudoSourceKind(
2278 unsigned Kind) const {
2279 switch(Kind) {
2280 case PseudoSourceValue::Stack:
2281 case PseudoSourceValue::FixedStack:
2282 return AMDGPUAS::PRIVATE_ADDRESS;
2283 case PseudoSourceValue::ConstantPool:
2284 case PseudoSourceValue::GOT:
2285 case PseudoSourceValue::JumpTable:
2286 case PseudoSourceValue::GlobalValueCallEntry:
2287 case PseudoSourceValue::ExternalSymbolCallEntry:
2288 case PseudoSourceValue::TargetCustom:
2289 return AMDGPUAS::CONSTANT_ADDRESS;
2290 }
2291 return AMDGPUAS::FLAT_ADDRESS;
2292}
2293
2294static void removeModOperands(MachineInstr &MI) {
2295 unsigned Opc = MI.getOpcode();
2296 int Src0ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2297 AMDGPU::OpName::src0_modifiers);
2298 int Src1ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2299 AMDGPU::OpName::src1_modifiers);
2300 int Src2ModIdx = AMDGPU::getNamedOperandIdx(Opc,
2301 AMDGPU::OpName::src2_modifiers);
2302
2303 MI.RemoveOperand(Src2ModIdx);
2304 MI.RemoveOperand(Src1ModIdx);
2305 MI.RemoveOperand(Src0ModIdx);
2306}
2307
2308bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
2309 unsigned Reg, MachineRegisterInfo *MRI) const {
2310 if (!MRI->hasOneNonDBGUse(Reg))
2311 return false;
2312
2313 switch (DefMI.getOpcode()) {
2314 default:
2315 return false;
2316 case AMDGPU::S_MOV_B64:
2317 // TODO: We could fold 64-bit immediates, but this get compilicated
2318 // when there are sub-registers.
2319 return false;
2320
2321 case AMDGPU::V_MOV_B32_e32:
2322 case AMDGPU::S_MOV_B32:
2323 case AMDGPU::V_ACCVGPR_WRITE_B32:
2324 break;
2325 }
2326
2327 const MachineOperand *ImmOp = getNamedOperand(DefMI, AMDGPU::OpName::src0);
2328 assert(ImmOp)((ImmOp) ? static_cast<void> (0) : __assert_fail ("ImmOp"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2328, __PRETTY_FUNCTION__))
;
2329 // FIXME: We could handle FrameIndex values here.
2330 if (!ImmOp->isImm())
2331 return false;
2332
2333 unsigned Opc = UseMI.getOpcode();
2334 if (Opc == AMDGPU::COPY) {
2335 bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg());
2336 unsigned NewOpc = isVGPRCopy ? AMDGPU::V_MOV_B32_e32 : AMDGPU::S_MOV_B32;
2337 if (RI.isAGPR(*MRI, UseMI.getOperand(0).getReg())) {
2338 if (!isInlineConstant(*ImmOp, AMDGPU::OPERAND_REG_INLINE_AC_INT32))
2339 return false;
2340 NewOpc = AMDGPU::V_ACCVGPR_WRITE_B32;
2341 }
2342 UseMI.setDesc(get(NewOpc));
2343 UseMI.getOperand(1).ChangeToImmediate(ImmOp->getImm());
2344 UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
2345 return true;
2346 }
2347
2348 if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64 ||
2349 Opc == AMDGPU::V_MAD_F16 || Opc == AMDGPU::V_MAC_F16_e64 ||
2350 Opc == AMDGPU::V_FMA_F32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
2351 Opc == AMDGPU::V_FMA_F16 || Opc == AMDGPU::V_FMAC_F16_e64) {
2352 // Don't fold if we are using source or output modifiers. The new VOP2
2353 // instructions don't have them.
2354 if (hasAnyModifiersSet(UseMI))
2355 return false;
2356
2357 // If this is a free constant, there's no reason to do this.
2358 // TODO: We could fold this here instead of letting SIFoldOperands do it
2359 // later.
2360 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0);
2361
2362 // Any src operand can be used for the legality check.
2363 if (isInlineConstant(UseMI, *Src0, *ImmOp))
2364 return false;
2365
2366 bool IsF32 = Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64 ||
2367 Opc == AMDGPU::V_FMA_F32 || Opc == AMDGPU::V_FMAC_F32_e64;
2368 bool IsFMA = Opc == AMDGPU::V_FMA_F32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
2369 Opc == AMDGPU::V_FMA_F16 || Opc == AMDGPU::V_FMAC_F16_e64;
2370 MachineOperand *Src1 = getNamedOperand(UseMI, AMDGPU::OpName::src1);
2371 MachineOperand *Src2 = getNamedOperand(UseMI, AMDGPU::OpName::src2);
2372
2373 // Multiplied part is the constant: Use v_madmk_{f16, f32}.
2374 // We should only expect these to be on src0 due to canonicalizations.
2375 if (Src0->isReg() && Src0->getReg() == Reg) {
2376 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2377 return false;
2378
2379 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
2380 return false;
2381
2382 unsigned NewOpc =
2383 IsFMA ? (IsF32 ? AMDGPU::V_FMAMK_F32 : AMDGPU::V_FMAMK_F16)
2384 : (IsF32 ? AMDGPU::V_MADMK_F32 : AMDGPU::V_MADMK_F16);
2385 if (pseudoToMCOpcode(NewOpc) == -1)
2386 return false;
2387
2388 // We need to swap operands 0 and 1 since madmk constant is at operand 1.
2389
2390 const int64_t Imm = ImmOp->getImm();
2391
2392 // FIXME: This would be a lot easier if we could return a new instruction
2393 // instead of having to modify in place.
2394
2395 // Remove these first since they are at the end.
2396 UseMI.RemoveOperand(
2397 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
2398 UseMI.RemoveOperand(
2399 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
2400
2401 Register Src1Reg = Src1->getReg();
2402 unsigned Src1SubReg = Src1->getSubReg();
2403 Src0->setReg(Src1Reg);
2404 Src0->setSubReg(Src1SubReg);
2405 Src0->setIsKill(Src1->isKill());
2406
2407 if (Opc == AMDGPU::V_MAC_F32_e64 ||
2408 Opc == AMDGPU::V_MAC_F16_e64 ||
2409 Opc == AMDGPU::V_FMAC_F32_e64 ||
2410 Opc == AMDGPU::V_FMAC_F16_e64)
2411 UseMI.untieRegOperand(
2412 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
2413
2414 Src1->ChangeToImmediate(Imm);
2415
2416 removeModOperands(UseMI);
2417 UseMI.setDesc(get(NewOpc));
2418
2419 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
2420 if (DeleteDef)
2421 DefMI.eraseFromParent();
2422
2423 return true;
2424 }
2425
2426 // Added part is the constant: Use v_madak_{f16, f32}.
2427 if (Src2->isReg() && Src2->getReg() == Reg) {
2428 // Not allowed to use constant bus for another operand.
2429 // We can however allow an inline immediate as src0.
2430 bool Src0Inlined = false;
2431 if (Src0->isReg()) {
2432 // Try to inline constant if possible.
2433 // If the Def moves immediate and the use is single
2434 // We are saving VGPR here.
2435 MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
2436 if (Def && Def->isMoveImmediate() &&
2437 isInlineConstant(Def->getOperand(1)) &&
2438 MRI->hasOneUse(Src0->getReg())) {
2439 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2440 Src0Inlined = true;
2441 } else if ((Register::isPhysicalRegister(Src0->getReg()) &&
2442 (ST.getConstantBusLimit(Opc) <= 1 &&
2443 RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) ||
2444 (Register::isVirtualRegister(Src0->getReg()) &&
2445 (ST.getConstantBusLimit(Opc) <= 1 &&
2446 RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))
2447 return false;
2448 // VGPR is okay as Src0 - fallthrough
2449 }
2450
2451 if (Src1->isReg() && !Src0Inlined ) {
2452 // We have one slot for inlinable constant so far - try to fill it
2453 MachineInstr *Def = MRI->getUniqueVRegDef(Src1->getReg());
2454 if (Def && Def->isMoveImmediate() &&
2455 isInlineConstant(Def->getOperand(1)) &&
2456 MRI->hasOneUse(Src1->getReg()) &&
2457 commuteInstruction(UseMI)) {
2458 Src0->ChangeToImmediate(Def->getOperand(1).getImm());
2459 } else if ((Register::isPhysicalRegister(Src1->getReg()) &&
2460 RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) ||
2461 (Register::isVirtualRegister(Src1->getReg()) &&
2462 RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
2463 return false;
2464 // VGPR is okay as Src1 - fallthrough
2465 }
2466
2467 unsigned NewOpc =
2468 IsFMA ? (IsF32 ? AMDGPU::V_FMAAK_F32 : AMDGPU::V_FMAAK_F16)
2469 : (IsF32 ? AMDGPU::V_MADAK_F32 : AMDGPU::V_MADAK_F16);
2470 if (pseudoToMCOpcode(NewOpc) == -1)
2471 return false;
2472
2473 const int64_t Imm = ImmOp->getImm();
2474
2475 // FIXME: This would be a lot easier if we could return a new instruction
2476 // instead of having to modify in place.
2477
2478 // Remove these first since they are at the end.
2479 UseMI.RemoveOperand(
2480 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod));
2481 UseMI.RemoveOperand(
2482 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp));
2483
2484 if (Opc == AMDGPU::V_MAC_F32_e64 ||
2485 Opc == AMDGPU::V_MAC_F16_e64 ||
2486 Opc == AMDGPU::V_FMAC_F32_e64 ||
2487 Opc == AMDGPU::V_FMAC_F16_e64)
2488 UseMI.untieRegOperand(
2489 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2));
2490
2491 // ChangingToImmediate adds Src2 back to the instruction.
2492 Src2->ChangeToImmediate(Imm);
2493
2494 // These come before src2.
2495 removeModOperands(UseMI);
2496 UseMI.setDesc(get(NewOpc));
2497 // It might happen that UseMI was commuted
2498 // and we now have SGPR as SRC1. If so 2 inlined
2499 // constant and SGPR are illegal.
2500 legalizeOperands(UseMI);
2501
2502 bool DeleteDef = MRI->hasOneNonDBGUse(Reg);
2503 if (DeleteDef)
2504 DefMI.eraseFromParent();
2505
2506 return true;
2507 }
2508 }
2509
2510 return false;
2511}
2512
2513static bool offsetsDoNotOverlap(int WidthA, int OffsetA,
2514 int WidthB, int OffsetB) {
2515 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2516 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2517 int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2518 return LowOffset + LowWidth <= HighOffset;
2519}
2520
2521bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
2522 const MachineInstr &MIb) const {
2523 const MachineOperand *BaseOp0, *BaseOp1;
2524 int64_t Offset0, Offset1;
2525
2526 if (getMemOperandWithOffset(MIa, BaseOp0, Offset0, &RI) &&
2527 getMemOperandWithOffset(MIb, BaseOp1, Offset1, &RI)) {
2528 if (!BaseOp0->isIdenticalTo(*BaseOp1))
2529 return false;
2530
2531 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) {
2532 // FIXME: Handle ds_read2 / ds_write2.
2533 return false;
2534 }
2535 unsigned Width0 = (*MIa.memoperands_begin())->getSize();
2536 unsigned Width1 = (*MIb.memoperands_begin())->getSize();
2537 if (offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) {
2538 return true;
2539 }
2540 }
2541
2542 return false;
2543}
2544
2545bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
2546 const MachineInstr &MIb) const {
2547 assert((MIa.mayLoad() || MIa.mayStore()) &&(((MIa.mayLoad() || MIa.mayStore()) && "MIa must load from or modify a memory location"
) ? static_cast<void> (0) : __assert_fail ("(MIa.mayLoad() || MIa.mayStore()) && \"MIa must load from or modify a memory location\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2548, __PRETTY_FUNCTION__))
2548 "MIa must load from or modify a memory location")(((MIa.mayLoad() || MIa.mayStore()) && "MIa must load from or modify a memory location"
) ? static_cast<void> (0) : __assert_fail ("(MIa.mayLoad() || MIa.mayStore()) && \"MIa must load from or modify a memory location\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2548, __PRETTY_FUNCTION__))
;
2549 assert((MIb.mayLoad() || MIb.mayStore()) &&(((MIb.mayLoad() || MIb.mayStore()) && "MIb must load from or modify a memory location"
) ? static_cast<void> (0) : __assert_fail ("(MIb.mayLoad() || MIb.mayStore()) && \"MIb must load from or modify a memory location\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2550, __PRETTY_FUNCTION__))
2550 "MIb must load from or modify a memory location")(((MIb.mayLoad() || MIb.mayStore()) && "MIb must load from or modify a memory location"
) ? static_cast<void> (0) : __assert_fail ("(MIb.mayLoad() || MIb.mayStore()) && \"MIb must load from or modify a memory location\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2550, __PRETTY_FUNCTION__))
;
2551
2552 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects())
2553 return false;
2554
2555 // XXX - Can we relax this between address spaces?
2556 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
2557 return false;
2558
2559 // TODO: Should we check the address space from the MachineMemOperand? That
2560 // would allow us to distinguish objects we know don't alias based on the
2561 // underlying address space, even if it was lowered to a different one,
2562 // e.g. private accesses lowered to use MUBUF instructions on a scratch
2563 // buffer.
2564 if (isDS(MIa)) {
2565 if (isDS(MIb))
2566 return checkInstOffsetsDoNotOverlap(MIa, MIb);
2567
2568 return !isFLAT(MIb) || isSegmentSpecificFLAT(MIb);
2569 }
2570
2571 if (isMUBUF(MIa) || isMTBUF(MIa)) {
2572 if (isMUBUF(MIb) || isMTBUF(MIb))
2573 return checkInstOffsetsDoNotOverlap(MIa, MIb);
2574
2575 return !isFLAT(MIb) && !isSMRD(MIb);
2576 }
2577
2578 if (isSMRD(MIa)) {
2579 if (isSMRD(MIb))
2580 return checkInstOffsetsDoNotOverlap(MIa, MIb);
2581
2582 return !isFLAT(MIb) && !isMUBUF(MIa) && !isMTBUF(MIa);
2583 }
2584
2585 if (isFLAT(MIa)) {
2586 if (isFLAT(MIb))
2587 return checkInstOffsetsDoNotOverlap(MIa, MIb);
2588
2589 return false;
2590 }
2591
2592 return false;
2593}
2594
2595static int64_t getFoldableImm(const MachineOperand* MO) {
2596 if (!MO->isReg())
2597 return false;
2598 const MachineFunction *MF = MO->getParent()->getParent()->getParent();
2599 const MachineRegisterInfo &MRI = MF->getRegInfo();
2600 auto Def = MRI.getUniqueVRegDef(MO->getReg());
2601 if (Def && Def->getOpcode() == AMDGPU::V_MOV_B32_e32 &&
2602 Def->getOperand(1).isImm())
2603 return Def->getOperand(1).getImm();
2604 return AMDGPU::NoRegister;
2605}
2606
2607MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
2608 MachineInstr &MI,
2609 LiveVariables *LV) const {
2610 unsigned Opc = MI.getOpcode();
2611 bool IsF16 = false;
2612 bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e32 || Opc == AMDGPU::V_FMAC_F32_e64 ||
2613 Opc == AMDGPU::V_FMAC_F16_e32 || Opc == AMDGPU::V_FMAC_F16_e64;
2614
2615 switch (Opc) {
2616 default:
2617 return nullptr;
2618 case AMDGPU::V_MAC_F16_e64:
2619 case AMDGPU::V_FMAC_F16_e64:
2620 IsF16 = true;
2621 LLVM_FALLTHROUGH[[gnu::fallthrough]];
2622 case AMDGPU::V_MAC_F32_e64:
2623 case AMDGPU::V_FMAC_F32_e64:
2624 break;
2625 case AMDGPU::V_MAC_F16_e32:
2626 case AMDGPU::V_FMAC_F16_e32:
2627 IsF16 = true;
2628 LLVM_FALLTHROUGH[[gnu::fallthrough]];
2629 case AMDGPU::V_MAC_F32_e32:
2630 case AMDGPU::V_FMAC_F32_e32: {
2631 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
2632 AMDGPU::OpName::src0);
2633 const MachineOperand *Src0 = &MI.getOperand(Src0Idx);
2634 if (!Src0->isReg() && !Src0->isImm())
2635 return nullptr;
2636
2637 if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0))
2638 return nullptr;
2639
2640 break;
2641 }
2642 }
2643
2644 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
2645 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0);
2646 const MachineOperand *Src0Mods =
2647 getNamedOperand(MI, AMDGPU::OpName::src0_modifiers);
2648 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
2649 const MachineOperand *Src1Mods =
2650 getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
2651 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
2652 const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
2653 const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
2654
2655 if (!Src0Mods && !Src1Mods && !Clamp && !Omod &&
2656 // If we have an SGPR input, we will violate the constant bus restriction.
2657 (ST.getConstantBusLimit(Opc) > 1 ||
2658 !Src0->isReg() ||
2659 !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
2660 if (auto Imm = getFoldableImm(Src2)) {
2661 unsigned NewOpc =
2662 IsFMA ? (IsF16 ? AMDGPU::V_FMAAK_F16 : AMDGPU::V_FMAAK_F32)
2663 : (IsF16 ? AMDGPU::V_MADAK_F16 : AMDGPU::V_MADAK_F32);
2664 if (pseudoToMCOpcode(NewOpc) != -1)
2665 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2666 .add(*Dst)
2667 .add(*Src0)
2668 .add(*Src1)
2669 .addImm(Imm);
2670 }
2671 unsigned NewOpc =
2672 IsFMA ? (IsF16 ? AMDGPU::V_FMAMK_F16 : AMDGPU::V_FMAMK_F32)
2673 : (IsF16 ? AMDGPU::V_MADMK_F16 : AMDGPU::V_MADMK_F32);
2674 if (auto Imm = getFoldableImm(Src1)) {
2675 if (pseudoToMCOpcode(NewOpc) != -1)
2676 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2677 .add(*Dst)
2678 .add(*Src0)
2679 .addImm(Imm)
2680 .add(*Src2);
2681 }
2682 if (auto Imm = getFoldableImm(Src0)) {
2683 if (pseudoToMCOpcode(NewOpc) != -1 &&
2684 isOperandLegal(MI, AMDGPU::getNamedOperandIdx(NewOpc,
2685 AMDGPU::OpName::src0), Src1))
2686 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2687 .add(*Dst)
2688 .add(*Src1)
2689 .addImm(Imm)
2690 .add(*Src2);
2691 }
2692 }
2693
2694 unsigned NewOpc = IsFMA ? (IsF16 ? AMDGPU::V_FMA_F16 : AMDGPU::V_FMA_F32)
2695 : (IsF16 ? AMDGPU::V_MAD_F16 : AMDGPU::V_MAD_F32);
2696 if (pseudoToMCOpcode(NewOpc) == -1)
2697 return nullptr;
2698
2699 return BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpc))
2700 .add(*Dst)
2701 .addImm(Src0Mods ? Src0Mods->getImm() : 0)
2702 .add(*Src0)
2703 .addImm(Src1Mods ? Src1Mods->getImm() : 0)
2704 .add(*Src1)
2705 .addImm(0) // Src mods
2706 .add(*Src2)
2707 .addImm(Clamp ? Clamp->getImm() : 0)
2708 .addImm(Omod ? Omod->getImm() : 0);
2709}
2710
2711// It's not generally safe to move VALU instructions across these since it will
2712// start using the register as a base index rather than directly.
2713// XXX - Why isn't hasSideEffects sufficient for these?
2714static bool changesVGPRIndexingMode(const MachineInstr &MI) {
2715 switch (MI.getOpcode()) {
2716 case AMDGPU::S_SET_GPR_IDX_ON:
2717 case AMDGPU::S_SET_GPR_IDX_MODE:
2718 case AMDGPU::S_SET_GPR_IDX_OFF:
2719 return true;
2720 default:
2721 return false;
2722 }
2723}
2724
2725bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
2726 const MachineBasicBlock *MBB,
2727 const MachineFunction &MF) const {
2728 // XXX - Do we want the SP check in the base implementation?
2729
2730 // Target-independent instructions do not have an implicit-use of EXEC, even
2731 // when they operate on VGPRs. Treating EXEC modifications as scheduling
2732 // boundaries prevents incorrect movements of such instructions.
2733 return TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF) ||
2734 MI.modifiesRegister(AMDGPU::EXEC, &RI) ||
2735 MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
2736 MI.getOpcode() == AMDGPU::S_SETREG_B32 ||
2737 MI.getOpcode() == AMDGPU::S_DENORM_MODE ||
2738 changesVGPRIndexingMode(MI);
2739}
2740
2741bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
2742 return Opcode == AMDGPU::DS_ORDERED_COUNT ||
2743 Opcode == AMDGPU::DS_GWS_INIT ||
2744 Opcode == AMDGPU::DS_GWS_SEMA_V ||
2745 Opcode == AMDGPU::DS_GWS_SEMA_BR ||
2746 Opcode == AMDGPU::DS_GWS_SEMA_P ||
2747 Opcode == AMDGPU::DS_GWS_SEMA_RELEASE_ALL ||
2748 Opcode == AMDGPU::DS_GWS_BARRIER;
2749}
2750
2751bool SIInstrInfo::hasUnwantedEffectsWhenEXECEmpty(const MachineInstr &MI) const {
2752 unsigned Opcode = MI.getOpcode();
2753
2754 if (MI.mayStore() && isSMRD(MI))
2755 return true; // scalar store or atomic
2756
2757 // This will terminate the function when other lanes may need to continue.
2758 if (MI.isReturn())
2759 return true;
2760
2761 // These instructions cause shader I/O that may cause hardware lockups
2762 // when executed with an empty EXEC mask.
2763 //
2764 // Note: exp with VM = DONE = 0 is automatically skipped by hardware when
2765 // EXEC = 0, but checking for that case here seems not worth it
2766 // given the typical code patterns.
2767 if (Opcode == AMDGPU::S_SENDMSG || Opcode == AMDGPU::S_SENDMSGHALT ||
2768 Opcode == AMDGPU::EXP || Opcode == AMDGPU::EXP_DONE ||
2769 Opcode == AMDGPU::DS_ORDERED_COUNT || Opcode == AMDGPU::S_TRAP ||
2770 Opcode == AMDGPU::DS_GWS_INIT || Opcode == AMDGPU::DS_GWS_BARRIER)
2771 return true;
2772
2773 if (MI.isCall() || MI.isInlineAsm())
2774 return true; // conservative assumption
2775
2776 // These are like SALU instructions in terms of effects, so it's questionable
2777 // whether we should return true for those.
2778 //
2779 // However, executing them with EXEC = 0 causes them to operate on undefined
2780 // data, which we avoid by returning true here.
2781 if (Opcode == AMDGPU::V_READFIRSTLANE_B32 || Opcode == AMDGPU::V_READLANE_B32)
2782 return true;
2783
2784 return false;
2785}
2786
2787bool SIInstrInfo::mayReadEXEC(const MachineRegisterInfo &MRI,
2788 const MachineInstr &MI) const {
2789 if (MI.isMetaInstruction())
2790 return false;
2791
2792 // This won't read exec if this is an SGPR->SGPR copy.
2793 if (MI.isCopyLike()) {
2794 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg()))
2795 return true;
2796
2797 // Make sure this isn't copying exec as a normal operand
2798 return MI.readsRegister(AMDGPU::EXEC, &RI);
2799 }
2800
2801 // Make a conservative assumption about the callee.
2802 if (MI.isCall())
2803 return true;
2804
2805 // Be conservative with any unhandled generic opcodes.
2806 if (!isTargetSpecificOpcode(MI.getOpcode()))
2807 return true;
2808
2809 return !isSALU(MI) || MI.readsRegister(AMDGPU::EXEC, &RI);
2810}
2811
2812bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
2813 switch (Imm.getBitWidth()) {
2814 case 1: // This likely will be a condition code mask.
2815 return true;
2816
2817 case 32:
2818 return AMDGPU::isInlinableLiteral32(Imm.getSExtValue(),
2819 ST.hasInv2PiInlineImm());
2820 case 64:
2821 return AMDGPU::isInlinableLiteral64(Imm.getSExtValue(),
2822 ST.hasInv2PiInlineImm());
2823 case 16:
2824 return ST.has16BitInsts() &&
2825 AMDGPU::isInlinableLiteral16(Imm.getSExtValue(),
2826 ST.hasInv2PiInlineImm());
2827 default:
2828 llvm_unreachable("invalid bitwidth")::llvm::llvm_unreachable_internal("invalid bitwidth", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2828)
;
2829 }
2830}
2831
2832bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
2833 uint8_t OperandType) const {
2834 if (!MO.isImm() ||
2835 OperandType < AMDGPU::OPERAND_SRC_FIRST ||
2836 OperandType > AMDGPU::OPERAND_SRC_LAST)
2837 return false;
2838
2839 // MachineOperand provides no way to tell the true operand size, since it only
2840 // records a 64-bit value. We need to know the size to determine if a 32-bit
2841 // floating point immediate bit pattern is legal for an integer immediate. It
2842 // would be for any 32-bit integer operand, but would not be for a 64-bit one.
2843
2844 int64_t Imm = MO.getImm();
2845 switch (OperandType) {
2846 case AMDGPU::OPERAND_REG_IMM_INT32:
2847 case AMDGPU::OPERAND_REG_IMM_FP32:
2848 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
2849 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
2850 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
2851 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: {
2852 int32_t Trunc = static_cast<int32_t>(Imm);
2853 return AMDGPU::isInlinableLiteral32(Trunc, ST.hasInv2PiInlineImm());
2854 }
2855 case AMDGPU::OPERAND_REG_IMM_INT64:
2856 case AMDGPU::OPERAND_REG_IMM_FP64:
2857 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
2858 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
2859 return AMDGPU::isInlinableLiteral64(MO.getImm(),
2860 ST.hasInv2PiInlineImm());
2861 case AMDGPU::OPERAND_REG_IMM_INT16:
2862 case AMDGPU::OPERAND_REG_IMM_FP16:
2863 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
2864 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
2865 case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
2866 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: {
2867 if (isInt<16>(Imm) || isUInt<16>(Imm)) {
2868 // A few special case instructions have 16-bit operands on subtargets
2869 // where 16-bit instructions are not legal.
2870 // TODO: Do the 32-bit immediates work? We shouldn't really need to handle
2871 // constants in these cases
2872 int16_t Trunc = static_cast<int16_t>(Imm);
2873 return ST.has16BitInsts() &&
2874 AMDGPU::isInlinableLiteral16(Trunc, ST.hasInv2PiInlineImm());
2875 }
2876
2877 return false;
2878 }
2879 case AMDGPU::OPERAND_REG_IMM_V2INT16:
2880 case AMDGPU::OPERAND_REG_IMM_V2FP16:
2881 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
2882 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
2883 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
2884 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {
2885 uint32_t Trunc = static_cast<uint32_t>(Imm);
2886 return AMDGPU::isInlinableLiteralV216(Trunc, ST.hasInv2PiInlineImm());
2887 }
2888 default:
2889 llvm_unreachable("invalid bitwidth")::llvm::llvm_unreachable_internal("invalid bitwidth", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2889)
;
2890 }
2891}
2892
2893bool SIInstrInfo::isLiteralConstantLike(const MachineOperand &MO,
2894 const MCOperandInfo &OpInfo) const {
2895 switch (MO.getType()) {
2896 case MachineOperand::MO_Register:
2897 return false;
2898 case MachineOperand::MO_Immediate:
2899 return !isInlineConstant(MO, OpInfo);
2900 case MachineOperand::MO_FrameIndex:
2901 case MachineOperand::MO_MachineBasicBlock:
2902 case MachineOperand::MO_ExternalSymbol:
2903 case MachineOperand::MO_GlobalAddress:
2904 case MachineOperand::MO_MCSymbol:
2905 return true;
2906 default:
2907 llvm_unreachable("unexpected operand type")::llvm::llvm_unreachable_internal("unexpected operand type", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2907)
;
2908 }
2909}
2910
2911static bool compareMachineOp(const MachineOperand &Op0,
2912 const MachineOperand &Op1) {
2913 if (Op0.getType() != Op1.getType())
2914 return false;
2915
2916 switch (Op0.getType()) {
2917 case MachineOperand::MO_Register:
2918 return Op0.getReg() == Op1.getReg();
2919 case MachineOperand::MO_Immediate:
2920 return Op0.getImm() == Op1.getImm();
2921 default:
2922 llvm_unreachable("Didn't expect to be comparing these operand types")::llvm::llvm_unreachable_internal("Didn't expect to be comparing these operand types"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2922)
;
2923 }
2924}
2925
2926bool SIInstrInfo::isImmOperandLegal(const MachineInstr &MI, unsigned OpNo,
2927 const MachineOperand &MO) const {
2928 const MCInstrDesc &InstDesc = MI.getDesc();
2929 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpNo];
2930
2931 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal())((MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal
()) ? static_cast<void> (0) : __assert_fail ("MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal()"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 2931, __PRETTY_FUNCTION__))
;
2932
2933 if (OpInfo.OperandType == MCOI::OPERAND_IMMEDIATE)
2934 return true;
2935
2936 if (OpInfo.RegClass < 0)
2937 return false;
2938
2939 const MachineFunction *MF = MI.getParent()->getParent();
2940 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
2941
2942 if (MO.isImm() && isInlineConstant(MO, OpInfo)) {
2943 if (isMAI(MI) && ST.hasMFMAInlineLiteralBug() &&
2944 OpNo ==(unsigned)AMDGPU::getNamedOperandIdx(MI.getOpcode(),
2945 AMDGPU::OpName::src2))
2946 return false;
2947 return RI.opCanUseInlineConstant(OpInfo.OperandType);
2948 }
2949
2950 if (!RI.opCanUseLiteralConstant(OpInfo.OperandType))
2951 return false;
2952
2953 if (!isVOP3(MI) || !AMDGPU::isSISrcOperand(InstDesc, OpNo))
2954 return true;
2955
2956 return ST.hasVOP3Literal();
2957}
2958
2959bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
2960 int Op32 = AMDGPU::getVOPe32(Opcode);
2961 if (Op32 == -1)
2962 return false;
2963
2964 return pseudoToMCOpcode(Op32) != -1;
2965}
2966
2967bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
2968 // The src0_modifier operand is present on all instructions
2969 // that have modifiers.
2970
2971 return AMDGPU::getNamedOperandIdx(Opcode,
2972 AMDGPU::OpName::src0_modifiers) != -1;
2973}
2974
2975bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
2976 unsigned OpName) const {
2977 const MachineOperand *Mods = getNamedOperand(MI, OpName);
2978 return Mods && Mods->getImm();
2979}
2980
2981bool SIInstrInfo::hasAnyModifiersSet(const MachineInstr &MI) const {
2982 return hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers) ||
2983 hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers) ||
2984 hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers) ||
2985 hasModifiersSet(MI, AMDGPU::OpName::clamp) ||
2986 hasModifiersSet(MI, AMDGPU::OpName::omod);
2987}
2988
2989bool SIInstrInfo::canShrink(const MachineInstr &MI,
2990 const MachineRegisterInfo &MRI) const {
2991 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
2992 // Can't shrink instruction with three operands.
2993 // FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
2994 // a special case for it. It can only be shrunk if the third operand
2995 // is vcc, and src0_modifiers and src1_modifiers are not set.
2996 // We should handle this the same way we handle vopc, by addding
2997 // a register allocation hint pre-regalloc and then do the shrinking
2998 // post-regalloc.
2999 if (Src2) {
3000 switch (MI.getOpcode()) {
3001 default: return false;
3002
3003 case AMDGPU::V_ADDC_U32_e64:
3004 case AMDGPU::V_SUBB_U32_e64:
3005 case AMDGPU::V_SUBBREV_U32_e64: {
3006 const MachineOperand *Src1
3007 = getNamedOperand(MI, AMDGPU::OpName::src1);
3008 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
3009 return false;
3010 // Additional verification is needed for sdst/src2.
3011 return true;
3012 }
3013 case AMDGPU::V_MAC_F32_e64:
3014 case AMDGPU::V_MAC_F16_e64:
3015 case AMDGPU::V_FMAC_F32_e64:
3016 case AMDGPU::V_FMAC_F16_e64:
3017 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
3018 hasModifiersSet(MI, AMDGPU::OpName::src2_modifiers))
3019 return false;
3020 break;
3021
3022 case AMDGPU::V_CNDMASK_B32_e64:
3023 break;
3024 }
3025 }
3026
3027 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3028 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
3029 hasModifiersSet(MI, AMDGPU::OpName::src1_modifiers)))
3030 return false;
3031
3032 // We don't need to check src0, all input types are legal, so just make sure
3033 // src0 isn't using any modifiers.
3034 if (hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
3035 return false;
3036
3037 // Can it be shrunk to a valid 32 bit opcode?
3038 if (!hasVALU32BitEncoding(MI.getOpcode()))
3039 return false;
3040
3041 // Check output modifiers
3042 return !hasModifiersSet(MI, AMDGPU::OpName::omod) &&
3043 !hasModifiersSet(MI, AMDGPU::OpName::clamp);
3044}
3045
3046// Set VCC operand with all flags from \p Orig, except for setting it as
3047// implicit.
3048static void copyFlagsToImplicitVCC(MachineInstr &MI,
3049 const MachineOperand &Orig) {
3050
3051 for (MachineOperand &Use : MI.implicit_operands()) {
3052 if (Use.isUse() && Use.getReg() == AMDGPU::VCC) {
3053 Use.setIsUndef(Orig.isUndef());
3054 Use.setIsKill(Orig.isKill());
3055 return;
3056 }
3057 }
3058}
3059
3060MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,
3061 unsigned Op32) const {
3062 MachineBasicBlock *MBB = MI.getParent();;
3063 MachineInstrBuilder Inst32 =
3064 BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32));
3065
3066 // Add the dst operand if the 32-bit encoding also has an explicit $vdst.
3067 // For VOPC instructions, this is replaced by an implicit def of vcc.
3068 int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
3069 if (Op32DstIdx != -1) {
3070 // dst
3071 Inst32.add(MI.getOperand(0));
3072 } else {
3073 assert(((MI.getOperand(0).getReg() == AMDGPU::VCC) ||((((MI.getOperand(0).getReg() == AMDGPU::VCC) || (MI.getOperand
(0).getReg() == AMDGPU::VCC_LO)) && "Unexpected case"
) ? static_cast<void> (0) : __assert_fail ("((MI.getOperand(0).getReg() == AMDGPU::VCC) || (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) && \"Unexpected case\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 3075, __PRETTY_FUNCTION__))
3074 (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) &&((((MI.getOperand(0).getReg() == AMDGPU::VCC) || (MI.getOperand
(0).getReg() == AMDGPU::VCC_LO)) && "Unexpected case"
) ? static_cast<void> (0) : __assert_fail ("((MI.getOperand(0).getReg() == AMDGPU::VCC) || (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) && \"Unexpected case\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 3075, __PRETTY_FUNCTION__))
3075 "Unexpected case")((((MI.getOperand(0).getReg() == AMDGPU::VCC) || (MI.getOperand
(0).getReg() == AMDGPU::VCC_LO)) && "Unexpected case"
) ? static_cast<void> (0) : __assert_fail ("((MI.getOperand(0).getReg() == AMDGPU::VCC) || (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) && \"Unexpected case\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 3075, __PRETTY_FUNCTION__))
;
3076 }
3077
3078 Inst32.add(*getNamedOperand(MI, AMDGPU::OpName::src0));
3079
3080 const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
3081 if (Src1)
3082 Inst32.add(*Src1);
3083
3084 const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
3085
3086 if (Src2) {
3087 int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
3088 if (Op32Src2Idx != -1) {
3089 Inst32.add(*Src2);
3090 } else {
3091 // In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
3092 // replaced with an implicit read of vcc. This was already added
3093 // during the initial BuildMI, so find it to preserve the flags.
3094 copyFlagsToImplicitVCC(*Inst32, *Src2);
3095 }
3096 }
3097
3098 return Inst32;
3099}
3100
3101bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
3102 const MachineOperand &MO,
3103 const MCOperandInfo &OpInfo) const {
3104 // Literal constants use the constant bus.
3105 //if (isLiteralConstantLike(MO, OpInfo))
3106 // return true;
3107 if (MO.isImm())
3108 return !isInlineConstant(MO, OpInfo);
3109
3110 if (!MO.isReg())
3111 return true; // Misc other operands like FrameIndex
3112
3113 if (!MO.isUse())
3114 return false;
3115
3116 if (Register::isVirtualRegister(MO.getReg()))
3117 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
3118
3119 // Null is free
3120 if (MO.getReg() == AMDGPU::SGPR_NULL)
3121 return false;
3122
3123 // SGPRs use the constant bus
3124 if (MO.isImplicit()) {
3125 return MO.getReg() == AMDGPU::M0 ||
3126 MO.getReg() == AMDGPU::VCC ||
3127 MO.getReg() == AMDGPU::VCC_LO;
3128 } else {
3129 return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
3130 AMDGPU::SReg_64RegClass.contains(MO.getReg());
3131 }
3132}
3133
3134static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
3135 for (const MachineOperand &MO : MI.implicit_operands()) {
3136 // We only care about reads.
3137 if (MO.isDef())
3138 continue;
3139
3140 switch (MO.getReg()) {
3141 case AMDGPU::VCC:
3142 case AMDGPU::VCC_LO:
3143 case AMDGPU::VCC_HI:
3144 case AMDGPU::M0:
3145 case AMDGPU::FLAT_SCR:
3146 return MO.getReg();
3147
3148 default:
3149 break;
3150 }
3151 }
3152
3153 return AMDGPU::NoRegister;
3154}
3155
3156static bool shouldReadExec(const MachineInstr &MI) {
3157 if (SIInstrInfo::isVALU(MI)) {
3158 switch (MI.getOpcode()) {
3159 case AMDGPU::V_READLANE_B32:
3160 case AMDGPU::V_READLANE_B32_gfx6_gfx7:
3161 case AMDGPU::V_READLANE_B32_gfx10:
3162 case AMDGPU::V_READLANE_B32_vi:
3163 case AMDGPU::V_WRITELANE_B32:
3164 case AMDGPU::V_WRITELANE_B32_gfx6_gfx7:
3165 case AMDGPU::V_WRITELANE_B32_gfx10:
3166 case AMDGPU::V_WRITELANE_B32_vi:
3167 return false;
3168 }
3169
3170 return true;
3171 }
3172
3173 if (MI.isPreISelOpcode() ||
3174 SIInstrInfo::isGenericOpcode(MI.getOpcode()) ||
3175 SIInstrInfo::isSALU(MI) ||
3176 SIInstrInfo::isSMRD(MI))
3177 return false;
3178
3179 return true;
3180}
3181
3182static bool isSubRegOf(const SIRegisterInfo &TRI,
3183 const MachineOperand &SuperVec,
3184 const MachineOperand &SubReg) {
3185 if (Register::isPhysicalRegister(SubReg.getReg()))
3186 return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg());
3187
3188 return SubReg.getSubReg() != AMDGPU::NoSubRegister &&
3189 SubReg.getReg() == SuperVec.getReg();
3190}
3191
3192bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
3193 StringRef &ErrInfo) const {
3194 uint16_t Opcode = MI.getOpcode();
3195 if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
3196 return true;
3197
3198 const MachineFunction *MF = MI.getParent()->getParent();
3199 const MachineRegisterInfo &MRI = MF->getRegInfo();
3200
3201 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
3202 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
3203 int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2);
3204
3205 // Make sure the number of operands is correct.
3206 const MCInstrDesc &Desc = get(Opcode);
3207 if (!Desc.isVariadic() &&
3208 Desc.getNumOperands() != MI.getNumExplicitOperands()) {
3209 ErrInfo = "Instruction has wrong number of operands.";
3210 return false;
3211 }
3212
3213 if (MI.isInlineAsm()) {
3214 // Verify register classes for inlineasm constraints.
3215 for (unsigned I = InlineAsm::MIOp_FirstOperand, E = MI.getNumOperands();
3216 I != E; ++I) {
3217 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI);
3218 if (!RC)
3219 continue;
3220
3221 const MachineOperand &Op = MI.getOperand(I);
3222 if (!Op.isReg())
3223 continue;
3224
3225 Register Reg = Op.getReg();
3226 if (!Register::isVirtualRegister(Reg) && !RC->contains(Reg)) {
3227 ErrInfo = "inlineasm operand has incorrect register class.";
3228 return false;
3229 }
3230 }
3231
3232 return true;
3233 }
3234
3235 // Make sure the register classes are correct.
3236 for (int i = 0, e = Desc.getNumOperands(); i != e; ++i) {
3237 if (MI.getOperand(i).isFPImm()) {
3238 ErrInfo = "FPImm Machine Operands are not supported. ISel should bitcast "
3239 "all fp values to integers.";
3240 return false;
3241 }
3242
3243 int RegClass = Desc.OpInfo[i].RegClass;
3244
3245 switch (Desc.OpInfo[i].OperandType) {
3246 case MCOI::OPERAND_REGISTER:
3247 if (MI.getOperand(i).isImm() || MI.getOperand(i).isGlobal()) {
3248 ErrInfo = "Illegal immediate value for operand.";
3249 return false;
3250 }
3251 break;
3252 case AMDGPU::OPERAND_REG_IMM_INT32:
3253 case AMDGPU::OPERAND_REG_IMM_FP32:
3254 break;
3255 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
3256 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
3257 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
3258 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
3259 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
3260 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
3261 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
3262 case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
3263 case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
3264 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: {
3265 const MachineOperand &MO = MI.getOperand(i);
3266 if (!MO.isReg() && (!MO.isImm() || !isInlineConstant(MI, i))) {
3267 ErrInfo = "Illegal immediate value for operand.";
3268 return false;
3269 }
3270 break;
3271 }
3272 case MCOI::OPERAND_IMMEDIATE:
3273 case AMDGPU::OPERAND_KIMM32:
3274 // Check if this operand is an immediate.
3275 // FrameIndex operands will be replaced by immediates, so they are
3276 // allowed.
3277 if (!MI.getOperand(i).isImm() && !MI.getOperand(i).isFI()) {
3278 ErrInfo = "Expected immediate, but got non-immediate";
3279 return false;
3280 }
3281 LLVM_FALLTHROUGH[[gnu::fallthrough]];
3282 default:
3283 continue;
3284 }
3285
3286 if (!MI.getOperand(i).isReg())
3287 continue;
3288
3289 if (RegClass != -1) {
3290 Register Reg = MI.getOperand(i).getReg();
3291 if (Reg == AMDGPU::NoRegister || Register::isVirtualRegister(Reg))
3292 continue;
3293
3294 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
3295 if (!RC->contains(Reg)) {
3296 ErrInfo = "Operand has incorrect register class.";
3297 return false;
3298 }
3299 }
3300 }
3301
3302 // Verify SDWA
3303 if (isSDWA(MI)) {
3304 if (!ST.hasSDWA()) {
3305 ErrInfo = "SDWA is not supported on this target";
3306 return false;
3307 }
3308
3309 int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst);
3310
3311 const int OpIndicies[] = { DstIdx, Src0Idx, Src1Idx, Src2Idx };
3312
3313 for (int OpIdx: OpIndicies) {
3314 if (OpIdx == -1)
3315 continue;
3316 const MachineOperand &MO = MI.getOperand(OpIdx);
3317
3318 if (!ST.hasSDWAScalar()) {
3319 // Only VGPRS on VI
3320 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) {
3321 ErrInfo = "Only VGPRs allowed as operands in SDWA instructions on VI";
3322 return false;
3323 }
3324 } else {
3325 // No immediates on GFX9
3326 if (!MO.isReg()) {
3327 ErrInfo = "Only reg allowed as operands in SDWA instructions on GFX9";
3328 return false;
3329 }
3330 }
3331 }
3332
3333 if (!ST.hasSDWAOmod()) {
3334 // No omod allowed on VI
3335 const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
3336 if (OMod != nullptr &&
3337 (!OMod->isImm() || OMod->getImm() != 0)) {
3338 ErrInfo = "OMod not allowed in SDWA instructions on VI";
3339 return false;
3340 }
3341 }
3342
3343 uint16_t BasicOpcode = AMDGPU::getBasicFromSDWAOp(Opcode);
3344 if (isVOPC(BasicOpcode)) {
3345 if (!ST.hasSDWASdst() && DstIdx != -1) {
3346 // Only vcc allowed as dst on VI for VOPC
3347 const MachineOperand &Dst = MI.getOperand(DstIdx);
3348 if (!Dst.isReg() || Dst.getReg() != AMDGPU::VCC) {
3349 ErrInfo = "Only VCC allowed as dst in SDWA instructions on VI";
3350 return false;
3351 }
3352 } else if (!ST.hasSDWAOutModsVOPC()) {
3353 // No clamp allowed on GFX9 for VOPC
3354 const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
3355 if (Clamp && (!Clamp->isImm() || Clamp->getImm() != 0)) {
3356 ErrInfo = "Clamp not allowed in VOPC SDWA instructions on VI";
3357 return false;
3358 }
3359
3360 // No omod allowed on GFX9 for VOPC
3361 const MachineOperand *OMod = getNamedOperand(MI, AMDGPU::OpName::omod);
3362 if (OMod && (!OMod->isImm() || OMod->getImm() != 0)) {
3363 ErrInfo = "OMod not allowed in VOPC SDWA instructions on VI";
3364 return false;
3365 }
3366 }
3367 }
3368
3369 const MachineOperand *DstUnused = getNamedOperand(MI, AMDGPU::OpName::dst_unused);
3370 if (DstUnused && DstUnused->isImm() &&
3371 DstUnused->getImm() == AMDGPU::SDWA::UNUSED_PRESERVE) {
3372 const MachineOperand &Dst = MI.getOperand(DstIdx);
3373 if (!Dst.isReg() || !Dst.isTied()) {
3374 ErrInfo = "Dst register should have tied register";
3375 return false;
3376 }
3377
3378 const MachineOperand &TiedMO =
3379 MI.getOperand(MI.findTiedOperandIdx(DstIdx));
3380 if (!TiedMO.isReg() || !TiedMO.isImplicit() || !TiedMO.isUse()) {
3381 ErrInfo =
3382 "Dst register should be tied to implicit use of preserved register";
3383 return false;
3384 } else if (Register::isPhysicalRegister(TiedMO.getReg()) &&
3385 Dst.getReg() != TiedMO.getReg()) {
3386 ErrInfo = "Dst register should use same physical register as preserved";
3387 return false;
3388 }
3389 }
3390 }
3391
3392 // Verify MIMG
3393 if (isMIMG(MI.getOpcode()) && !MI.mayStore()) {
3394 // Ensure that the return type used is large enough for all the options
3395 // being used TFE/LWE require an extra result register.
3396 const MachineOperand *DMask = getNamedOperand(MI, AMDGPU::OpName::dmask);
3397 if (DMask) {
3398 uint64_t DMaskImm = DMask->getImm();
3399 uint32_t RegCount =
3400 isGather4(MI.getOpcode()) ? 4 : countPopulation(DMaskImm);
3401 const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe);
3402 const MachineOperand *LWE = getNamedOperand(MI, AMDGPU::OpName::lwe);
3403 const MachineOperand *D16 = getNamedOperand(MI, AMDGPU::OpName::d16);
3404
3405 // Adjust for packed 16 bit values
3406 if (D16 && D16->getImm() && !ST.hasUnpackedD16VMem())
3407 RegCount >>= 1;
3408
3409 // Adjust if using LWE or TFE
3410 if ((LWE && LWE->getImm()) || (TFE && TFE->getImm()))
3411 RegCount += 1;
3412
3413 const uint32_t DstIdx =
3414 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata);
3415 const MachineOperand &Dst = MI.getOperand(DstIdx);
3416 if (Dst.isReg()) {
3417 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
3418 uint32_t DstSize = RI.getRegSizeInBits(*DstRC) / 32;
3419 if (RegCount > DstSize) {
3420 ErrInfo = "MIMG instruction returns too many registers for dst "
3421 "register class";
3422 return false;
3423 }
3424 }
3425 }
3426 }
3427
3428 // Verify VOP*. Ignore multiple sgpr operands on writelane.
3429 if (Desc.getOpcode() != AMDGPU::V_WRITELANE_B32
3430 && (isVOP1(MI) || isVOP2(MI) || isVOP3(MI) || isVOPC(MI) || isSDWA(MI))) {
3431 // Only look at the true operands. Only a real operand can use the constant
3432 // bus, and we don't want to check pseudo-operands like the source modifier
3433 // flags.
3434 const int OpIndices[] = { Src0Idx, Src1Idx, Src2Idx };
3435
3436 unsigned ConstantBusCount = 0;
3437 unsigned LiteralCount = 0;
3438
3439 if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1)
3440 ++ConstantBusCount;
3441
3442 SmallVector<unsigned, 2> SGPRsUsed;
3443 unsigned SGPRUsed = findImplicitSGPRRead(MI);
3444 if (SGPRUsed != AMDGPU::NoRegister) {
3445 ++ConstantBusCount;
3446 SGPRsUsed.push_back(SGPRUsed);
3447 }
3448
3449 for (int OpIdx : OpIndices) {
3450 if (OpIdx == -1)
3451 break;
3452 const MachineOperand &MO = MI.getOperand(OpIdx);
3453 if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
3454 if (MO.isReg()) {
3455 SGPRUsed = MO.getReg();
3456 if (llvm::all_of(SGPRsUsed, [this, SGPRUsed](unsigned SGPR) {
3457 return !RI.regsOverlap(SGPRUsed, SGPR);
3458 })) {
3459 ++ConstantBusCount;
3460 SGPRsUsed.push_back(SGPRUsed);
3461 }
3462 } else {
3463 ++ConstantBusCount;
3464 ++LiteralCount;
3465 }
3466 }
3467 }
3468 const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
3469 // v_writelane_b32 is an exception from constant bus restriction:
3470 // vsrc0 can be sgpr, const or m0 and lane select sgpr, m0 or inline-const
3471 if (ConstantBusCount > ST.getConstantBusLimit(Opcode) &&
3472 Opcode != AMDGPU::V_WRITELANE_B32) {
3473 ErrInfo = "VOP* instruction violates constant bus restriction";
3474 return false;
3475 }
3476
3477 if (isVOP3(MI) && LiteralCount) {
3478 if (LiteralCount && !ST.hasVOP3Literal()) {
3479 ErrInfo = "VOP3 instruction uses literal";
3480 return false;
3481 }
3482 if (LiteralCount > 1) {
3483 ErrInfo = "VOP3 instruction uses more than one literal";
3484 return false;
3485 }
3486 }
3487 }
3488
3489 // Special case for writelane - this can break the multiple constant bus rule,
3490 // but still can't use more than one SGPR register
3491 if (Desc.getOpcode() == AMDGPU::V_WRITELANE_B32) {
3492 unsigned SGPRCount = 0;
3493 Register SGPRUsed = AMDGPU::NoRegister;
3494
3495 for (int OpIdx : {Src0Idx, Src1Idx, Src2Idx}) {
3496 if (OpIdx == -1)
3497 break;
3498
3499 const MachineOperand &MO = MI.getOperand(OpIdx);
3500
3501 if (usesConstantBus(MRI, MO, MI.getDesc().OpInfo[OpIdx])) {
3502 if (MO.isReg() && MO.getReg() != AMDGPU::M0) {
3503 if (MO.getReg() != SGPRUsed)
3504 ++SGPRCount;
3505 SGPRUsed = MO.getReg();
3506 }
3507 }
3508 if (SGPRCount > ST.getConstantBusLimit(Opcode)) {
3509 ErrInfo = "WRITELANE instruction violates constant bus restriction";
3510 return false;
3511 }
3512 }
3513 }
3514
3515 // Verify misc. restrictions on specific instructions.
3516 if (Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F32 ||
3517 Desc.getOpcode() == AMDGPU::V_DIV_SCALE_F64) {
3518 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3519 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
3520 const MachineOperand &Src2 = MI.getOperand(Src2Idx);
3521 if (Src0.isReg() && Src1.isReg() && Src2.isReg()) {
3522 if (!compareMachineOp(Src0, Src1) &&
3523 !compareMachineOp(Src0, Src2)) {
3524 ErrInfo = "v_div_scale_{f32|f64} require src0 = src1 or src2";
3525 return false;
3526 }
3527 }
3528 }
3529
3530 if (isSOP2(MI) || isSOPC(MI)) {
3531 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3532 const MachineOperand &Src1 = MI.getOperand(Src1Idx);
3533 unsigned Immediates = 0;
3534
3535 if (!Src0.isReg() &&
3536 !isInlineConstant(Src0, Desc.OpInfo[Src0Idx].OperandType))
3537 Immediates++;
3538 if (!Src1.isReg() &&
3539 !isInlineConstant(Src1, Desc.OpInfo[Src1Idx].OperandType))
3540 Immediates++;
3541
3542 if (Immediates > 1) {
3543 ErrInfo = "SOP2/SOPC instruction requires too many immediate constants";
3544 return false;
3545 }
3546 }
3547
3548 if (isSOPK(MI)) {
3549 auto Op = getNamedOperand(MI, AMDGPU::OpName::simm16);
3550 if (Desc.isBranch()) {
3551 if (!Op->isMBB()) {
3552 ErrInfo = "invalid branch target for SOPK instruction";
3553 return false;
3554 }
3555 } else {
3556 uint64_t Imm = Op->getImm();
3557 if (sopkIsZext(MI)) {
3558 if (!isUInt<16>(Imm)) {
3559 ErrInfo = "invalid immediate for SOPK instruction";
3560 return false;
3561 }
3562 } else {
3563 if (!isInt<16>(Imm)) {
3564 ErrInfo = "invalid immediate for SOPK instruction";
3565 return false;
3566 }
3567 }
3568 }
3569 }
3570
3571 if (Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e32 ||
3572 Desc.getOpcode() == AMDGPU::V_MOVRELS_B32_e64 ||
3573 Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
3574 Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64) {
3575 const bool IsDst = Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e32 ||
3576 Desc.getOpcode() == AMDGPU::V_MOVRELD_B32_e64;
3577
3578 const unsigned StaticNumOps = Desc.getNumOperands() +
3579 Desc.getNumImplicitUses();
3580 const unsigned NumImplicitOps = IsDst ? 2 : 1;
3581
3582 // Allow additional implicit operands. This allows a fixup done by the post
3583 // RA scheduler where the main implicit operand is killed and implicit-defs
3584 // are added for sub-registers that remain live after this instruction.
3585 if (MI.getNumOperands() < StaticNumOps + NumImplicitOps) {
3586 ErrInfo = "missing implicit register operands";
3587 return false;
3588 }
3589
3590 const MachineOperand *Dst = getNamedOperand(MI, AMDGPU::OpName::vdst);
3591 if (IsDst) {
3592 if (!Dst->isUse()) {
3593 ErrInfo = "v_movreld_b32 vdst should be a use operand";
3594 return false;
3595 }
3596
3597 unsigned UseOpIdx;
3598 if (!MI.isRegTiedToUseOperand(StaticNumOps, &UseOpIdx) ||
3599 UseOpIdx != StaticNumOps + 1) {
3600 ErrInfo = "movrel implicit operands should be tied";
3601 return false;
3602 }
3603 }
3604
3605 const MachineOperand &Src0 = MI.getOperand(Src0Idx);
3606 const MachineOperand &ImpUse
3607 = MI.getOperand(StaticNumOps + NumImplicitOps - 1);
3608 if (!ImpUse.isReg() || !ImpUse.isUse() ||
3609 !isSubRegOf(RI, ImpUse, IsDst ? *Dst : Src0)) {
3610 ErrInfo = "src0 should be subreg of implicit vector use";
3611 return false;
3612 }
3613 }
3614
3615 // Make sure we aren't losing exec uses in the td files. This mostly requires
3616 // being careful when using let Uses to try to add other use registers.
3617 if (shouldReadExec(MI)) {
3618 if (!MI.hasRegisterImplicitUseOperand(AMDGPU::EXEC)) {
3619 ErrInfo = "VALU instruction does not implicitly read exec mask";
3620 return false;
3621 }
3622 }
3623
3624 if (isSMRD(MI)) {
3625 if (MI.mayStore()) {
3626 // The register offset form of scalar stores may only use m0 as the
3627 // soffset register.
3628 const MachineOperand *Soff = getNamedOperand(MI, AMDGPU::OpName::soff);
3629 if (Soff && Soff->getReg() != AMDGPU::M0) {
3630 ErrInfo = "scalar stores must use m0 as offset register";
3631 return false;
3632 }
3633 }
3634 }
3635
3636 if (isFLAT(MI) && !MF->getSubtarget<GCNSubtarget>().hasFlatInstOffsets()) {
3637 const MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
3638 if (Offset->getImm() != 0) {
3639 ErrInfo = "subtarget does not support offsets in flat instructions";
3640 return false;
3641 }
3642 }
3643
3644 if (isMIMG(MI)) {
3645 const MachineOperand *DimOp = getNamedOperand(MI, AMDGPU::OpName::dim);
3646 if (DimOp) {
3647 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opcode,
3648 AMDGPU::OpName::vaddr0);
3649 int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::srsrc);
3650 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opcode);
3651 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
3652 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
3653 const AMDGPU::MIMGDimInfo *Dim =
3654 AMDGPU::getMIMGDimInfoByEncoding(DimOp->getImm());
3655
3656 if (!Dim) {
3657 ErrInfo = "dim is out of range";
3658 return false;
3659 }
3660
3661 bool IsNSA = SRsrcIdx - VAddr0Idx > 1;
3662 unsigned AddrWords = BaseOpcode->NumExtraArgs +
3663 (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
3664 (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
3665 (BaseOpcode->LodOrClampOrMip ? 1 : 0);
3666
3667 unsigned VAddrWords;
3668 if (IsNSA) {
3669 VAddrWords = SRsrcIdx - VAddr0Idx;
3670 } else {
3671 const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx);
3672 VAddrWords = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 32;
3673 if (AddrWords > 8)
3674 AddrWords = 16;
3675 else if (AddrWords > 4)
3676 AddrWords = 8;
3677 else if (AddrWords == 3 && VAddrWords == 4) {
3678 // CodeGen uses the V4 variant of instructions for three addresses,
3679 // because the selection DAG does not support non-power-of-two types.
3680 AddrWords = 4;
3681 }
3682 }
3683
3684 if (VAddrWords != AddrWords) {
3685 ErrInfo = "bad vaddr size";
3686 return false;
3687 }
3688 }
3689 }
3690
3691 const MachineOperand *DppCt = getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl);
3692 if (DppCt) {
3693 using namespace AMDGPU::DPP;
3694
3695 unsigned DC = DppCt->getImm();
3696 if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 ||
3697 DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST ||
3698 (DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) ||
3699 (DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) ||
3700 (DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) ||
3701 (DC >= DppCtrl::DPP_UNUSED7_FIRST && DC <= DppCtrl::DPP_UNUSED7_LAST) ||
3702 (DC >= DppCtrl::DPP_UNUSED8_FIRST && DC <= DppCtrl::DPP_UNUSED8_LAST)) {
3703 ErrInfo = "Invalid dpp_ctrl value";
3704 return false;
3705 }
3706 if (DC >= DppCtrl::WAVE_SHL1 && DC <= DppCtrl::WAVE_ROR1 &&
3707 ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
3708 ErrInfo = "Invalid dpp_ctrl value: "
3709 "wavefront shifts are not supported on GFX10+";
3710 return false;
3711 }
3712 if (DC >= DppCtrl::BCAST15 && DC <= DppCtrl::BCAST31 &&
3713 ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
3714 ErrInfo = "Invalid dpp_ctrl value: "
3715 "broadcasts are not supported on GFX10+";
3716 return false;
3717 }
3718 if (DC >= DppCtrl::ROW_SHARE_FIRST && DC <= DppCtrl::ROW_XMASK_LAST &&
3719 ST.getGeneration() < AMDGPUSubtarget::GFX10) {
3720 ErrInfo = "Invalid dpp_ctrl value: "
3721 "row_share and row_xmask are not supported before GFX10";
3722 return false;
3723 }
3724 }
3725
3726 return true;
3727}
3728
3729unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) const {
3730 switch (MI.getOpcode()) {
3731 default: return AMDGPU::INSTRUCTION_LIST_END;
3732 case AMDGPU::REG_SEQUENCE: return AMDGPU::REG_SEQUENCE;
3733 case AMDGPU::COPY: return AMDGPU::COPY;
3734 case AMDGPU::PHI: return AMDGPU::PHI;
3735 case AMDGPU::INSERT_SUBREG: return AMDGPU::INSERT_SUBREG;
3736 case AMDGPU::WQM: return AMDGPU::WQM;
3737 case AMDGPU::SOFT_WQM: return AMDGPU::SOFT_WQM;
3738 case AMDGPU::WWM: return AMDGPU::WWM;
3739 case AMDGPU::S_MOV_B32: {
3740 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3741 return MI.getOperand(1).isReg() ||
3742 RI.isAGPR(MRI, MI.getOperand(0).getReg()) ?
3743 AMDGPU::COPY : AMDGPU::V_MOV_B32_e32;
3744 }
3745 case AMDGPU::S_ADD_I32:
3746 return ST.hasAddNoCarry() ? AMDGPU::V_ADD_U32_e64 : AMDGPU::V_ADD_I32_e32;
3747 case AMDGPU::S_ADDC_U32:
3748 return AMDGPU::V_ADDC_U32_e32;
3749 case AMDGPU::S_SUB_I32:
3750 return ST.hasAddNoCarry() ? AMDGPU::V_SUB_U32_e64 : AMDGPU::V_SUB_I32_e32;
3751 // FIXME: These are not consistently handled, and selected when the carry is
3752 // used.
3753 case AMDGPU::S_ADD_U32:
3754 return AMDGPU::V_ADD_I32_e32;
3755 case AMDGPU::S_SUB_U32:
3756 return AMDGPU::V_SUB_I32_e32;
3757 case AMDGPU::S_SUBB_U32: return AMDGPU::V_SUBB_U32_e32;
3758 case AMDGPU::S_MUL_I32: return AMDGPU::V_MUL_LO_U32;
3759 case AMDGPU::S_MUL_HI_U32: return AMDGPU::V_MUL_HI_U32;
3760 case AMDGPU::S_MUL_HI_I32: return AMDGPU::V_MUL_HI_I32;
3761 case AMDGPU::S_AND_B32: return AMDGPU::V_AND_B32_e64;
3762 case AMDGPU::S_OR_B32: return AMDGPU::V_OR_B32_e64;
3763 case AMDGPU::S_XOR_B32: return AMDGPU::V_XOR_B32_e64;
3764 case AMDGPU::S_XNOR_B32:
3765 return ST.hasDLInsts() ? AMDGPU::V_XNOR_B32_e64 : AMDGPU::INSTRUCTION_LIST_END;
3766 case AMDGPU::S_MIN_I32: return AMDGPU::V_MIN_I32_e64;
3767 case AMDGPU::S_MIN_U32: return AMDGPU::V_MIN_U32_e64;
3768 case AMDGPU::S_MAX_I32: return AMDGPU::V_MAX_I32_e64;
3769 case AMDGPU::S_MAX_U32: return AMDGPU::V_MAX_U32_e64;
3770 case AMDGPU::S_ASHR_I32: return AMDGPU::V_ASHR_I32_e32;
3771 case AMDGPU::S_ASHR_I64: return AMDGPU::V_ASHR_I64;
3772 case AMDGPU::S_LSHL_B32: return AMDGPU::V_LSHL_B32_e32;
3773 case AMDGPU::S_LSHL_B64: return AMDGPU::V_LSHL_B64;
3774 case AMDGPU::S_LSHR_B32: return AMDGPU::V_LSHR_B32_e32;
3775 case AMDGPU::S_LSHR_B64: return AMDGPU::V_LSHR_B64;
3776 case AMDGPU::S_SEXT_I32_I8: return AMDGPU::V_BFE_I32;
3777 case AMDGPU::S_SEXT_I32_I16: return AMDGPU::V_BFE_I32;
3778 case AMDGPU::S_BFE_U32: return AMDGPU::V_BFE_U32;
3779 case AMDGPU::S_BFE_I32: return AMDGPU::V_BFE_I32;
3780 case AMDGPU::S_BFM_B32: return AMDGPU::V_BFM_B32_e64;
3781 case AMDGPU::S_BREV_B32: return AMDGPU::V_BFREV_B32_e32;
3782 case AMDGPU::S_NOT_B32: return AMDGPU::V_NOT_B32_e32;
3783 case AMDGPU::S_NOT_B64: return AMDGPU::V_NOT_B32_e32;
3784 case AMDGPU::S_CMP_EQ_I32: return AMDGPU::V_CMP_EQ_I32_e32;
3785 case AMDGPU::S_CMP_LG_I32: return AMDGPU::V_CMP_NE_I32_e32;
3786 case AMDGPU::S_CMP_GT_I32: return AMDGPU::V_CMP_GT_I32_e32;
3787 case AMDGPU::S_CMP_GE_I32: return AMDGPU::V_CMP_GE_I32_e32;
3788 case AMDGPU::S_CMP_LT_I32: return AMDGPU::V_CMP_LT_I32_e32;
3789 case AMDGPU::S_CMP_LE_I32: return AMDGPU::V_CMP_LE_I32_e32;
3790 case AMDGPU::S_CMP_EQ_U32: return AMDGPU::V_CMP_EQ_U32_e32;
3791 case AMDGPU::S_CMP_LG_U32: return AMDGPU::V_CMP_NE_U32_e32;
3792 case AMDGPU::S_CMP_GT_U32: return AMDGPU::V_CMP_GT_U32_e32;
3793 case AMDGPU::S_CMP_GE_U32: return AMDGPU::V_CMP_GE_U32_e32;
3794 case AMDGPU::S_CMP_LT_U32: return AMDGPU::V_CMP_LT_U32_e32;
3795 case AMDGPU::S_CMP_LE_U32: return AMDGPU::V_CMP_LE_U32_e32;
3796 case AMDGPU::S_CMP_EQ_U64: return AMDGPU::V_CMP_EQ_U64_e32;
3797 case AMDGPU::S_CMP_LG_U64: return AMDGPU::V_CMP_NE_U64_e32;
3798 case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
3799 case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
3800 case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
3801 case AMDGPU::S_FLBIT_I32: return AMDGPU::V_FFBH_I32_e64;
3802 case AMDGPU::S_CBRANCH_SCC0: return AMDGPU::S_CBRANCH_VCCZ;
3803 case AMDGPU::S_CBRANCH_SCC1: return AMDGPU::S_CBRANCH_VCCNZ;
3804 }
3805 llvm_unreachable(::llvm::llvm_unreachable_internal("Unexpected scalar opcode without corresponding vector one!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 3806)
3806 "Unexpected scalar opcode without corresponding vector one!")::llvm::llvm_unreachable_internal("Unexpected scalar opcode without corresponding vector one!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 3806)
;
3807}
3808
3809const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
3810 unsigned OpNo) const {
3811 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3812 const MCInstrDesc &Desc = get(MI.getOpcode());
3813 if (MI.isVariadic() || OpNo >= Desc.getNumOperands() ||
3814 Desc.OpInfo[OpNo].RegClass == -1) {
3815 Register Reg = MI.getOperand(OpNo).getReg();
3816
3817 if (Register::isVirtualRegister(Reg))
3818 return MRI.getRegClass(Reg);
3819 return RI.getPhysRegClass(Reg);
3820 }
3821
3822 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
3823 return RI.getRegClass(RCID);
3824}
3825
3826void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
3827 MachineBasicBlock::iterator I = MI;
3828 MachineBasicBlock *MBB = MI.getParent();
3829 MachineOperand &MO = MI.getOperand(OpIdx);
3830 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
3831 const SIRegisterInfo *TRI =
3832 static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
3833 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass;
3834 const TargetRegisterClass *RC = RI.getRegClass(RCID);
3835 unsigned Size = TRI->getRegSizeInBits(*RC);
3836 unsigned Opcode = (Size == 64) ? AMDGPU::V_MOV_B64_PSEUDO : AMDGPU::V_MOV_B32_e32;
3837 if (MO.isReg())
3838 Opcode = AMDGPU::COPY;
3839 else if (RI.isSGPRClass(RC))
3840 Opcode = (Size == 64) ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;
3841
3842 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
3843 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC))
3844 VRC = &AMDGPU::VReg_64RegClass;
3845 else
3846 VRC = &AMDGPU::VGPR_32RegClass;
3847
3848 Register Reg = MRI.createVirtualRegister(VRC);
3849 DebugLoc DL = MBB->findDebugLoc(I);
3850 BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);
3851 MO.ChangeToRegister(Reg, false);
3852}
3853
3854unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
3855 MachineRegisterInfo &MRI,
3856 MachineOperand &SuperReg,
3857 const TargetRegisterClass *SuperRC,
3858 unsigned SubIdx,
3859 const TargetRegisterClass *SubRC)
3860 const {
3861 MachineBasicBlock *MBB = MI->getParent();
3862 DebugLoc DL = MI->getDebugLoc();
3863 Register SubReg = MRI.createVirtualRegister(SubRC);
3864
3865 if (SuperReg.getSubReg() == AMDGPU::NoSubRegister) {
3866 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
3867 .addReg(SuperReg.getReg(), 0, SubIdx);
3868 return SubReg;
3869 }
3870
3871 // Just in case the super register is itself a sub-register, copy it to a new
3872 // value so we don't need to worry about merging its subreg index with the
3873 // SubIdx passed to this function. The register coalescer should be able to
3874 // eliminate this extra copy.
3875 Register NewSuperReg = MRI.createVirtualRegister(SuperRC);
3876
3877 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
3878 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
3879
3880 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
3881 .addReg(NewSuperReg, 0, SubIdx);
3882
3883 return SubReg;
3884}
3885
3886MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
3887 MachineBasicBlock::iterator MII,
3888 MachineRegisterInfo &MRI,
3889 MachineOperand &Op,
3890 const TargetRegisterClass *SuperRC,
3891 unsigned SubIdx,
3892 const TargetRegisterClass *SubRC) const {
3893 if (Op.isImm()) {
3894 if (SubIdx == AMDGPU::sub0)
3895 return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm()));
3896 if (SubIdx == AMDGPU::sub1)
3897 return MachineOperand::CreateImm(static_cast<int32_t>(Op.getImm() >> 32));
3898
3899 llvm_unreachable("Unhandled register index for immediate")::llvm::llvm_unreachable_internal("Unhandled register index for immediate"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 3899)
;
3900 }
3901
3902 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC,
3903 SubIdx, SubRC);
3904 return MachineOperand::CreateReg(SubReg, false);
3905}
3906
3907// Change the order of operands from (0, 1, 2) to (0, 2, 1)
3908void SIInstrInfo::swapOperands(MachineInstr &Inst) const {
3909 assert(Inst.getNumExplicitOperands() == 3)((Inst.getNumExplicitOperands() == 3) ? static_cast<void>
(0) : __assert_fail ("Inst.getNumExplicitOperands() == 3", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 3909, __PRETTY_FUNCTION__))
;
3910 MachineOperand Op1 = Inst.getOperand(1);
3911 Inst.RemoveOperand(1);
3912 Inst.addOperand(Op1);
3913}
3914
3915bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
3916 const MCOperandInfo &OpInfo,
3917 const MachineOperand &MO) const {
3918 if (!MO.isReg())
3919 return false;
3920
3921 Register Reg = MO.getReg();
3922 const TargetRegisterClass *RC = Register::isVirtualRegister(Reg)
3923 ? MRI.getRegClass(Reg)
3924 : RI.getPhysRegClass(Reg);
3925
3926 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
3927 if (MO.getSubReg()) {
3928 const MachineFunction *MF = MO.getParent()->getParent()->getParent();
3929 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF);
3930 if (!SuperRC)
3931 return false;
3932
3933 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg());
3934 if (!DRC)
3935 return false;
3936 }
3937 return RC->hasSuperClassEq(DRC);
3938}
3939
3940bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,
3941 const MCOperandInfo &OpInfo,
3942 const MachineOperand &MO) const {
3943 if (MO.isReg())
3944 return isLegalRegOperand(MRI, OpInfo, MO);
3945
3946 // Handle non-register types that are treated like immediates.
3947 assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal())((MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal
()) ? static_cast<void> (0) : __assert_fail ("MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal()"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 3947, __PRETTY_FUNCTION__))
;
3948 return true;
3949}
3950
3951bool SIInstrInfo::isOperandLegal(const MachineInstr &MI, unsigned OpIdx,
3952 const MachineOperand *MO) const {
3953 const MachineFunction &MF = *MI.getParent()->getParent();
3954 const MachineRegisterInfo &MRI = MF.getRegInfo();
3955 const MCInstrDesc &InstDesc = MI.getDesc();
3956 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx];
3957 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
3958 const TargetRegisterClass *DefinedRC =
3959 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr;
3960 if (!MO)
3961 MO = &MI.getOperand(OpIdx);
3962
3963 int ConstantBusLimit = ST.getConstantBusLimit(MI.getOpcode());
3964 int VOP3LiteralLimit = ST.hasVOP3Literal() ? 1 : 0;
3965 if (isVALU(MI) && usesConstantBus(MRI, *MO, OpInfo)) {
3966 if (isVOP3(MI) && isLiteralConstantLike(*MO, OpInfo) && !VOP3LiteralLimit--)
3967 return false;
3968
3969 SmallDenseSet<RegSubRegPair> SGPRsUsed;
3970 if (MO->isReg())
3971 SGPRsUsed.insert(RegSubRegPair(MO->getReg(), MO->getSubReg()));
3972
3973 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
3974 if (i == OpIdx)
3975 continue;
3976 const MachineOperand &Op = MI.getOperand(i);
3977 if (Op.isReg()) {
3978 RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
3979 if (!SGPRsUsed.count(SGPR) &&
3980 usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) {
3981 if (--ConstantBusLimit <= 0)
3982 return false;
3983 SGPRsUsed.insert(SGPR);
3984 }
3985 } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) {
3986 if (--ConstantBusLimit <= 0)
3987 return false;
3988 } else if (isVOP3(MI) && AMDGPU::isSISrcOperand(InstDesc, i) &&
3989 isLiteralConstantLike(Op, InstDesc.OpInfo[i])) {
3990 if (!VOP3LiteralLimit--)
3991 return false;
3992 if (--ConstantBusLimit <= 0)
3993 return false;
3994 }
3995 }
3996 }
3997
3998 if (MO->isReg()) {
3999 assert(DefinedRC)((DefinedRC) ? static_cast<void> (0) : __assert_fail ("DefinedRC"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 3999, __PRETTY_FUNCTION__))
;
4000 return isLegalRegOperand(MRI, OpInfo, *MO);
4001 }
4002
4003 // Handle non-register types that are treated like immediates.
4004 assert(MO->isImm() || MO->isTargetIndex() || MO->isFI() || MO->isGlobal())((MO->isImm() || MO->isTargetIndex() || MO->isFI() ||
MO->isGlobal()) ? static_cast<void> (0) : __assert_fail
("MO->isImm() || MO->isTargetIndex() || MO->isFI() || MO->isGlobal()"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 4004, __PRETTY_FUNCTION__))
;
4005
4006 if (!DefinedRC) {
4007 // This operand expects an immediate.
4008 return true;
4009 }
4010
4011 return isImmOperandLegal(MI, OpIdx, *MO);
4012}
4013
4014void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
4015 MachineInstr &MI) const {
4016 unsigned Opc = MI.getOpcode();
4017 const MCInstrDesc &InstrDesc = get(Opc);
4018
4019 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
4020 MachineOperand &Src0 = MI.getOperand(Src0Idx);
4021
4022 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
4023 MachineOperand &Src1 = MI.getOperand(Src1Idx);
4024
4025 // If there is an implicit SGPR use such as VCC use for v_addc_u32/v_subb_u32
4026 // we need to only have one constant bus use before GFX10.
4027 bool HasImplicitSGPR = findImplicitSGPRRead(MI) != AMDGPU::NoRegister;
4028 if (HasImplicitSGPR && ST.getConstantBusLimit(Opc) <= 1 &&
4029 Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) ||
4030 isLiteralConstantLike(Src0, InstrDesc.OpInfo[Src0Idx])))
4031 legalizeOpWithMove(MI, Src0Idx);
4032
4033 // Special case: V_WRITELANE_B32 accepts only immediate or SGPR operands for
4034 // both the value to write (src0) and lane select (src1). Fix up non-SGPR
4035 // src0/src1 with V_READFIRSTLANE.
4036 if (Opc == AMDGPU::V_WRITELANE_B32) {
4037 const DebugLoc &DL = MI.getDebugLoc();
4038 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
4039 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4040 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4041 .add(Src0);
4042 Src0.ChangeToRegister(Reg, false);
4043 }
4044 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) {
4045 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4046 const DebugLoc &DL = MI.getDebugLoc();
4047 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4048 .add(Src1);
4049 Src1.ChangeToRegister(Reg, false);
4050 }
4051 return;
4052 }
4053
4054 // No VOP2 instructions support AGPRs.
4055 if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg()))
4056 legalizeOpWithMove(MI, Src0Idx);
4057
4058 if (Src1.isReg() && RI.isAGPR(MRI, Src1.getReg()))
4059 legalizeOpWithMove(MI, Src1Idx);
4060
4061 // VOP2 src0 instructions support all operand types, so we don't need to check
4062 // their legality. If src1 is already legal, we don't need to do anything.
4063 if (isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src1))
4064 return;
4065
4066 // Special case: V_READLANE_B32 accepts only immediate or SGPR operands for
4067 // lane select. Fix up using V_READFIRSTLANE, since we assume that the lane
4068 // select is uniform.
4069 if (Opc == AMDGPU::V_READLANE_B32 && Src1.isReg() &&
4070 RI.isVGPR(MRI, Src1.getReg())) {
4071 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4072 const DebugLoc &DL = MI.getDebugLoc();
4073 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4074 .add(Src1);
4075 Src1.ChangeToRegister(Reg, false);
4076 return;
4077 }
4078
4079 // We do not use commuteInstruction here because it is too aggressive and will
4080 // commute if it is possible. We only want to commute here if it improves
4081 // legality. This can be called a fairly large number of times so don't waste
4082 // compile time pointlessly swapping and checking legality again.
4083 if (HasImplicitSGPR || !MI.isCommutable()) {
4084 legalizeOpWithMove(MI, Src1Idx);
4085 return;
4086 }
4087
4088 // If src0 can be used as src1, commuting will make the operands legal.
4089 // Otherwise we have to give up and insert a move.
4090 //
4091 // TODO: Other immediate-like operand kinds could be commuted if there was a
4092 // MachineOperand::ChangeTo* for them.
4093 if ((!Src1.isImm() && !Src1.isReg()) ||
4094 !isLegalRegOperand(MRI, InstrDesc.OpInfo[Src1Idx], Src0)) {
4095 legalizeOpWithMove(MI, Src1Idx);
4096 return;
4097 }
4098
4099 int CommutedOpc = commuteOpcode(MI);
4100 if (CommutedOpc == -1) {
4101 legalizeOpWithMove(MI, Src1Idx);
4102 return;
4103 }
4104
4105 MI.setDesc(get(CommutedOpc));
4106
4107 Register Src0Reg = Src0.getReg();
4108 unsigned Src0SubReg = Src0.getSubReg();
4109 bool Src0Kill = Src0.isKill();
4110
4111 if (Src1.isImm())
4112 Src0.ChangeToImmediate(Src1.getImm());
4113 else if (Src1.isReg()) {
4114 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
4115 Src0.setSubReg(Src1.getSubReg());
4116 } else
4117 llvm_unreachable("Should only have register or immediate operands")::llvm::llvm_unreachable_internal("Should only have register or immediate operands"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 4117)
;
4118
4119 Src1.ChangeToRegister(Src0Reg, false, false, Src0Kill);
4120 Src1.setSubReg(Src0SubReg);
4121 fixImplicitOperands(MI);
4122}
4123
4124// Legalize VOP3 operands. All operand types are supported for any operand
4125// but only one literal constant and only starting from GFX10.
4126void SIInstrInfo::legalizeOperandsVOP3(MachineRegisterInfo &MRI,
4127 MachineInstr &MI) const {
4128 unsigned Opc = MI.getOpcode();
4129
4130 int VOP3Idx[3] = {
4131 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0),
4132 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1),
4133 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)
4134 };
4135
4136 if (Opc == AMDGPU::V_PERMLANE16_B32 ||
4137 Opc == AMDGPU::V_PERMLANEX16_B32) {
4138 // src1 and src2 must be scalar
4139 MachineOperand &Src1 = MI.getOperand(VOP3Idx[1]);
4140 MachineOperand &Src2 = MI.getOperand(VOP3Idx[2]);
4141 const DebugLoc &DL = MI.getDebugLoc();
4142 if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
4143 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4144 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4145 .add(Src1);
4146 Src1.ChangeToRegister(Reg, false);
4147 }
4148 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {
4149 Register Reg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
4150 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4151 .add(Src2);
4152 Src2.ChangeToRegister(Reg, false);
4153 }
4154 }
4155
4156 // Find the one SGPR operand we are allowed to use.
4157 int ConstantBusLimit = ST.getConstantBusLimit(Opc);
4158 int LiteralLimit = ST.hasVOP3Literal() ? 1 : 0;
4159 SmallDenseSet<unsigned> SGPRsUsed;
4160 unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
4161 if (SGPRReg != AMDGPU::NoRegister) {
4162 SGPRsUsed.insert(SGPRReg);
4163 --ConstantBusLimit;
4164 }
4165
4166 for (unsigned i = 0; i < 3; ++i) {
4167 int Idx = VOP3Idx[i];
4168 if (Idx == -1)
4169 break;
4170 MachineOperand &MO = MI.getOperand(Idx);
4171
4172 if (!MO.isReg()) {
4173 if (!isLiteralConstantLike(MO, get(Opc).OpInfo[Idx]))
4174 continue;
4175
4176 if (LiteralLimit > 0 && ConstantBusLimit > 0) {
4177 --LiteralLimit;
4178 --ConstantBusLimit;
4179 continue;
4180 }
4181
4182 --LiteralLimit;
4183 --ConstantBusLimit;
4184 legalizeOpWithMove(MI, Idx);
4185 continue;
4186 }
4187
4188 if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) &&
4189 !isOperandLegal(MI, Idx, &MO)) {
4190 legalizeOpWithMove(MI, Idx);
4191 continue;
4192 }
4193
4194 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
4195 continue; // VGPRs are legal
4196
4197 // We can use one SGPR in each VOP3 instruction prior to GFX10
4198 // and two starting from GFX10.
4199 if (SGPRsUsed.count(MO.getReg()))
4200 continue;
4201 if (ConstantBusLimit > 0) {
4202 SGPRsUsed.insert(MO.getReg());
4203 --ConstantBusLimit;
4204 continue;
4205 }
4206
4207 // If we make it this far, then the operand is not legal and we must
4208 // legalize it.
4209 legalizeOpWithMove(MI, Idx);
4210 }
4211}
4212
4213unsigned SIInstrInfo::readlaneVGPRToSGPR(unsigned SrcReg, MachineInstr &UseMI,
4214 MachineRegisterInfo &MRI) const {
4215 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
4216 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);
4217 Register DstReg = MRI.createVirtualRegister(SRC);
4218 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32;
4219
4220 if (RI.hasAGPRs(VRC)) {
4221 VRC = RI.getEquivalentVGPRClass(VRC);
4222 Register NewSrcReg = MRI.createVirtualRegister(VRC);
4223 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4224 get(TargetOpcode::COPY), NewSrcReg)
4225 .addReg(SrcReg);
4226 SrcReg = NewSrcReg;
4227 }
4228
4229 if (SubRegs == 1) {
4230 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4231 get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
4232 .addReg(SrcReg);
4233 return DstReg;
4234 }
4235
4236 SmallVector<unsigned, 8> SRegs;
4237 for (unsigned i = 0; i < SubRegs; ++i) {
4238 Register SGPR = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4239 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4240 get(AMDGPU::V_READFIRSTLANE_B32), SGPR)
4241 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
4242 SRegs.push_back(SGPR);
4243 }
4244
4245 MachineInstrBuilder MIB =
4246 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4247 get(AMDGPU::REG_SEQUENCE), DstReg);
4248 for (unsigned i = 0; i < SubRegs; ++i) {
4249 MIB.addReg(SRegs[i]);
4250 MIB.addImm(RI.getSubRegFromChannel(i));
4251 }
4252 return DstReg;
4253}
4254
4255void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,
4256 MachineInstr &MI) const {
4257
4258 // If the pointer is store in VGPRs, then we need to move them to
4259 // SGPRs using v_readfirstlane. This is safe because we only select
4260 // loads with uniform pointers to SMRD instruction so we know the
4261 // pointer value is uniform.
4262 MachineOperand *SBase = getNamedOperand(MI, AMDGPU::OpName::sbase);
4263 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {
4264 unsigned SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI);
4265 SBase->setReg(SGPR);
4266 }
4267 MachineOperand *SOff = getNamedOperand(MI, AMDGPU::OpName::soff);
4268 if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {
4269 unsigned SGPR = readlaneVGPRToSGPR(SOff->getReg(), MI, MRI);
4270 SOff->setReg(SGPR);
4271 }
4272}
4273
4274void SIInstrInfo::legalizeGenericOperand(MachineBasicBlock &InsertMBB,
4275 MachineBasicBlock::iterator I,
4276 const TargetRegisterClass *DstRC,
4277 MachineOperand &Op,
4278 MachineRegisterInfo &MRI,
4279 const DebugLoc &DL) const {
4280 Register OpReg = Op.getReg();
4281 unsigned OpSubReg = Op.getSubReg();
4282
4283 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg(
4284 RI.getRegClassForReg(MRI, OpReg), OpSubReg);
4285
4286 // Check if operand is already the correct register class.
4287 if (DstRC == OpRC)
4288 return;
4289
4290 Register DstReg = MRI.createVirtualRegister(DstRC);
4291 MachineInstr *Copy =
4292 BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).add(Op);
4293
4294 Op.setReg(DstReg);
4295 Op.setSubReg(0);
4296
4297 MachineInstr *Def = MRI.getVRegDef(OpReg);
4298 if (!Def)
4299 return;
4300
4301 // Try to eliminate the copy if it is copying an immediate value.
4302 if (Def->isMoveImmediate() && DstRC != &AMDGPU::VReg_1RegClass)
4303 FoldImmediate(*Copy, *Def, OpReg, &MRI);
4304
4305 bool ImpDef = Def->isImplicitDef();
4306 while (!ImpDef && Def && Def->isCopy()) {
4307 if (Def->getOperand(1).getReg().isPhysical())
4308 break;
4309 Def = MRI.getUniqueVRegDef(Def->getOperand(1).getReg());
4310 ImpDef = Def && Def->isImplicitDef();
4311 }
4312 if (!RI.isSGPRClass(DstRC) && !Copy->readsRegister(AMDGPU::EXEC, &RI) &&
4313 !ImpDef)
4314 Copy->addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
4315}
4316
4317// Emit the actual waterfall loop, executing the wrapped instruction for each
4318// unique value of \p Rsrc across all lanes. In the best case we execute 1
4319// iteration, in the worst case we execute 64 (once per lane).
4320static void
4321emitLoadSRsrcFromVGPRLoop(const SIInstrInfo &TII, MachineRegisterInfo &MRI,
4322 MachineBasicBlock &OrigBB, MachineBasicBlock &LoopBB,
4323 const DebugLoc &DL, MachineOperand &Rsrc) {
4324 MachineFunction &MF = *OrigBB.getParent();
4325 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
4326 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4327 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
4328 unsigned SaveExecOpc =
4329 ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32 : AMDGPU::S_AND_SAVEEXEC_B64;
4330 unsigned XorTermOpc =
4331 ST.isWave32() ? AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term;
4332 unsigned AndOpc =
4333 ST.isWave32() ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
4334 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4335
4336 MachineBasicBlock::iterator I = LoopBB.begin();
4337
4338 Register VRsrc = Rsrc.getReg();
4339 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef());
4340
4341 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
4342 Register CondReg0 = MRI.createVirtualRegister(BoolXExecRC);
4343 Register CondReg1 = MRI.createVirtualRegister(BoolXExecRC);
4344 Register AndCond = MRI.createVirtualRegister(BoolXExecRC);
4345 Register SRsrcSub0 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4346 Register SRsrcSub1 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4347 Register SRsrcSub2 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4348 Register SRsrcSub3 = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4349 Register SRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
4350
4351 // Beginning of the loop, read the next Rsrc variant.
4352 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0)
4353 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub0);
4354 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub1)
4355 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub1);
4356 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub2)
4357 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub2);
4358 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub3)
4359 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub3);
4360
4361 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc)
4362 .addReg(SRsrcSub0)
4363 .addImm(AMDGPU::sub0)
4364 .addReg(SRsrcSub1)
4365 .addImm(AMDGPU::sub1)
4366 .addReg(SRsrcSub2)
4367 .addImm(AMDGPU::sub2)
4368 .addReg(SRsrcSub3)
4369 .addImm(AMDGPU::sub3);
4370
4371 // Update Rsrc operand to use the SGPR Rsrc.
4372 Rsrc.setReg(SRsrc);
4373 Rsrc.setIsKill(true);
4374
4375 // Identify all lanes with identical Rsrc operands in their VGPRs.
4376 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg0)
4377 .addReg(SRsrc, 0, AMDGPU::sub0_sub1)
4378 .addReg(VRsrc, 0, AMDGPU::sub0_sub1);
4379 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg1)
4380 .addReg(SRsrc, 0, AMDGPU::sub2_sub3)
4381 .addReg(VRsrc, 0, AMDGPU::sub2_sub3);
4382 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndCond)
4383 .addReg(CondReg0)
4384 .addReg(CondReg1);
4385
4386 MRI.setSimpleHint(SaveExec, AndCond);
4387
4388 // Update EXEC to matching lanes, saving original to SaveExec.
4389 BuildMI(LoopBB, I, DL, TII.get(SaveExecOpc), SaveExec)
4390 .addReg(AndCond, RegState::Kill);
4391
4392 // The original instruction is here; we insert the terminators after it.
4393 I = LoopBB.end();
4394
4395 // Update EXEC, switch all done bits to 0 and all todo bits to 1.
4396 BuildMI(LoopBB, I, DL, TII.get(XorTermOpc), Exec)
4397 .addReg(Exec)
4398 .addReg(SaveExec);
4399 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(&LoopBB);
4400}
4401
4402// Build a waterfall loop around \p MI, replacing the VGPR \p Rsrc register
4403// with SGPRs by iterating over all unique values across all lanes.
4404static void loadSRsrcFromVGPR(const SIInstrInfo &TII, MachineInstr &MI,
4405 MachineOperand &Rsrc, MachineDominatorTree *MDT) {
4406 MachineBasicBlock &MBB = *MI.getParent();
4407 MachineFunction &MF = *MBB.getParent();
4408 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
4409 const SIRegisterInfo *TRI = ST.getRegisterInfo();
4410 MachineRegisterInfo &MRI = MF.getRegInfo();
4411 MachineBasicBlock::iterator I(&MI);
4412 const DebugLoc &DL = MI.getDebugLoc();
4413 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
4414 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
4415 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4416
4417 Register SaveExec = MRI.createVirtualRegister(BoolXExecRC);
4418
4419 // Save the EXEC mask
4420 BuildMI(MBB, I, DL, TII.get(MovExecOpc), SaveExec).addReg(Exec);
4421
4422 // Killed uses in the instruction we are waterfalling around will be
4423 // incorrect due to the added control-flow.
4424 for (auto &MO : MI.uses()) {
4425 if (MO.isReg() && MO.isUse()) {
4426 MRI.clearKillFlags(MO.getReg());
4427 }
4428 }
4429
4430 // To insert the loop we need to split the block. Move everything after this
4431 // point to a new block, and insert a new empty block between the two.
4432 MachineBasicBlock *LoopBB = MF.CreateMachineBasicBlock();
4433 MachineBasicBlock *RemainderBB = MF.CreateMachineBasicBlock();
4434 MachineFunction::iterator MBBI(MBB);
4435 ++MBBI;
4436
4437 MF.insert(MBBI, LoopBB);
4438 MF.insert(MBBI, RemainderBB);
4439
4440 LoopBB->addSuccessor(LoopBB);
4441 LoopBB->addSuccessor(RemainderBB);
4442
4443 // Move MI to the LoopBB, and the remainder of the block to RemainderBB.
4444 MachineBasicBlock::iterator J = I++;
4445 RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
4446 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
4447 LoopBB->splice(LoopBB->begin(), &MBB, J);
4448
4449 MBB.addSuccessor(LoopBB);
4450
4451 // Update dominators. We know that MBB immediately dominates LoopBB, that
4452 // LoopBB immediately dominates RemainderBB, and that RemainderBB immediately
4453 // dominates all of the successors transferred to it from MBB that MBB used
4454 // to properly dominate.
4455 if (MDT) {
4456 MDT->addNewBlock(LoopBB, &MBB);
4457 MDT->addNewBlock(RemainderBB, LoopBB);
4458 for (auto &Succ : RemainderBB->successors()) {
4459 if (MDT->properlyDominates(&MBB, Succ)) {
4460 MDT->changeImmediateDominator(Succ, RemainderBB);
4461 }
4462 }
4463 }
4464
4465 emitLoadSRsrcFromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, Rsrc);
4466
4467 // Restore the EXEC mask
4468 MachineBasicBlock::iterator First = RemainderBB->begin();
4469 BuildMI(*RemainderBB, First, DL, TII.get(MovExecOpc), Exec).addReg(SaveExec);
4470}
4471
4472// Extract pointer from Rsrc and return a zero-value Rsrc replacement.
4473static std::tuple<unsigned, unsigned>
4474extractRsrcPtr(const SIInstrInfo &TII, MachineInstr &MI, MachineOperand &Rsrc) {
4475 MachineBasicBlock &MBB = *MI.getParent();
4476 MachineFunction &MF = *MBB.getParent();
4477 MachineRegisterInfo &MRI = MF.getRegInfo();
4478
4479 // Extract the ptr from the resource descriptor.
4480 unsigned RsrcPtr =
4481 TII.buildExtractSubReg(MI, MRI, Rsrc, &AMDGPU::VReg_128RegClass,
4482 AMDGPU::sub0_sub1, &AMDGPU::VReg_64RegClass);
4483
4484 // Create an empty resource descriptor
4485 Register Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
4486 Register SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4487 Register SRsrcFormatHi = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
4488 Register NewSRsrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass);
4489 uint64_t RsrcDataFormat = TII.getDefaultRsrcDataFormat();
4490
4491 // Zero64 = 0
4492 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64)
4493 .addImm(0);
4494
4495 // SRsrcFormatLo = RSRC_DATA_FORMAT{31-0}
4496 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatLo)
4497 .addImm(RsrcDataFormat & 0xFFFFFFFF);
4498
4499 // SRsrcFormatHi = RSRC_DATA_FORMAT{63-32}
4500 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatHi)
4501 .addImm(RsrcDataFormat >> 32);
4502
4503 // NewSRsrc = {Zero64, SRsrcFormat}
4504 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::REG_SEQUENCE), NewSRsrc)
4505 .addReg(Zero64)
4506 .addImm(AMDGPU::sub0_sub1)
4507 .addReg(SRsrcFormatLo)
4508 .addImm(AMDGPU::sub2)
4509 .addReg(SRsrcFormatHi)
4510 .addImm(AMDGPU::sub3);
4511
4512 return std::make_tuple(RsrcPtr, NewSRsrc);
4513}
4514
4515void SIInstrInfo::legalizeOperands(MachineInstr &MI,
4516 MachineDominatorTree *MDT) const {
4517 MachineFunction &MF = *MI.getParent()->getParent();
4518 MachineRegisterInfo &MRI = MF.getRegInfo();
4519
4520 // Legalize VOP2
4521 if (isVOP2(MI) || isVOPC(MI)) {
4522 legalizeOperandsVOP2(MRI, MI);
4523 return;
4524 }
4525
4526 // Legalize VOP3
4527 if (isVOP3(MI)) {
4528 legalizeOperandsVOP3(MRI, MI);
4529 return;
4530 }
4531
4532 // Legalize SMRD
4533 if (isSMRD(MI)) {
4534 legalizeOperandsSMRD(MRI, MI);
4535 return;
4536 }
4537
4538 // Legalize REG_SEQUENCE and PHI
4539 // The register class of the operands much be the same type as the register
4540 // class of the output.
4541 if (MI.getOpcode() == AMDGPU::PHI) {
4542 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
4543 for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) {
4544 if (!MI.getOperand(i).isReg() ||
4545 !Register::isVirtualRegister(MI.getOperand(i).getReg()))
4546 continue;
4547 const TargetRegisterClass *OpRC =
4548 MRI.getRegClass(MI.getOperand(i).getReg());
4549 if (RI.hasVectorRegisters(OpRC)) {
4550 VRC = OpRC;
4551 } else {
4552 SRC = OpRC;
4553 }
4554 }
4555
4556 // If any of the operands are VGPR registers, then they all most be
4557 // otherwise we will create illegal VGPR->SGPR copies when legalizing
4558 // them.
4559 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) {
4560 if (!VRC) {
4561 assert(SRC)((SRC) ? static_cast<void> (0) : __assert_fail ("SRC", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 4561, __PRETTY_FUNCTION__))
;
4562 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) {
4563 VRC = &AMDGPU::VReg_1RegClass;
4564 } else
4565 VRC = RI.hasAGPRs(getOpRegClass(MI, 0))
4566 ? RI.getEquivalentAGPRClass(SRC)
4567 : RI.getEquivalentVGPRClass(SRC);
4568 } else {
4569 VRC = RI.hasAGPRs(getOpRegClass(MI, 0))
4570 ? RI.getEquivalentAGPRClass(VRC)
4571 : RI.getEquivalentVGPRClass(VRC);
4572 }
4573 RC = VRC;
4574 } else {
4575 RC = SRC;
4576 }
4577
4578 // Update all the operands so they have the same type.
4579 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
4580 MachineOperand &Op = MI.getOperand(I);
4581 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg()))
4582 continue;
4583
4584 // MI is a PHI instruction.
4585 MachineBasicBlock *InsertBB = MI.getOperand(I + 1).getMBB();
4586 MachineBasicBlock::iterator Insert = InsertBB->getFirstTerminator();
4587
4588 // Avoid creating no-op copies with the same src and dst reg class. These
4589 // confuse some of the machine passes.
4590 legalizeGenericOperand(*InsertBB, Insert, RC, Op, MRI, MI.getDebugLoc());
4591 }
4592 }
4593
4594 // REG_SEQUENCE doesn't really require operand legalization, but if one has a
4595 // VGPR dest type and SGPR sources, insert copies so all operands are
4596 // VGPRs. This seems to help operand folding / the register coalescer.
4597 if (MI.getOpcode() == AMDGPU::REG_SEQUENCE) {
4598 MachineBasicBlock *MBB = MI.getParent();
4599 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0);
4600 if (RI.hasVGPRs(DstRC)) {
4601 // Update all the operands so they are VGPR register classes. These may
4602 // not be the same register class because REG_SEQUENCE supports mixing
4603 // subregister index types e.g. sub0_sub1 + sub2 + sub3
4604 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
4605 MachineOperand &Op = MI.getOperand(I);
4606 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg()))
4607 continue;
4608
4609 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
4610 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
4611 if (VRC == OpRC)
4612 continue;
4613
4614 legalizeGenericOperand(*MBB, MI, VRC, Op, MRI, MI.getDebugLoc());
4615 Op.setIsKill();
4616 }
4617 }
4618
4619 return;
4620 }
4621
4622 // Legalize INSERT_SUBREG
4623 // src0 must have the same register class as dst
4624 if (MI.getOpcode() == AMDGPU::INSERT_SUBREG) {
4625 Register Dst = MI.getOperand(0).getReg();
4626 Register Src0 = MI.getOperand(1).getReg();
4627 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
4628 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
4629 if (DstRC != Src0RC) {
4630 MachineBasicBlock *MBB = MI.getParent();
4631 MachineOperand &Op = MI.getOperand(1);
4632 legalizeGenericOperand(*MBB, MI, DstRC, Op, MRI, MI.getDebugLoc());
4633 }
4634 return;
4635 }
4636
4637 // Legalize SI_INIT_M0
4638 if (MI.getOpcode() == AMDGPU::SI_INIT_M0) {
4639 MachineOperand &Src = MI.getOperand(0);
4640 if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))
4641 Src.setReg(readlaneVGPRToSGPR(Src.getReg(), MI, MRI));
4642 return;
4643 }
4644
4645 // Legalize MIMG and MUBUF/MTBUF for shaders.
4646 //
4647 // Shaders only generate MUBUF/MTBUF instructions via intrinsics or via
4648 // scratch memory access. In both cases, the legalization never involves
4649 // conversion to the addr64 form.
4650 if (isMIMG(MI) ||
4651 (AMDGPU::isShader(MF.getFunction().getCallingConv()) &&
4652 (isMUBUF(MI) || isMTBUF(MI)))) {
4653 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc);
4654 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
4655 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI);
4656 SRsrc->setReg(SGPR);
4657 }
4658
4659 MachineOperand *SSamp = getNamedOperand(MI, AMDGPU::OpName::ssamp);
4660 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) {
4661 unsigned SGPR = readlaneVGPRToSGPR(SSamp->getReg(), MI, MRI);
4662 SSamp->setReg(SGPR);
4663 }
4664 return;
4665 }
4666
4667 // Legalize MUBUF* instructions.
4668 int RsrcIdx =
4669 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
4670 if (RsrcIdx != -1) {
4671 // We have an MUBUF instruction
4672 MachineOperand *Rsrc = &MI.getOperand(RsrcIdx);
4673 unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass;
4674 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),
4675 RI.getRegClass(RsrcRC))) {
4676 // The operands are legal.
4677 // FIXME: We may need to legalize operands besided srsrc.
4678 return;
4679 }
4680
4681 // Legalize a VGPR Rsrc.
4682 //
4683 // If the instruction is _ADDR64, we can avoid a waterfall by extracting
4684 // the base pointer from the VGPR Rsrc, adding it to the VAddr, then using
4685 // a zero-value SRsrc.
4686 //
4687 // If the instruction is _OFFSET (both idxen and offen disabled), and we
4688 // support ADDR64 instructions, we can convert to ADDR64 and do the same as
4689 // above.
4690 //
4691 // Otherwise we are on non-ADDR64 hardware, and/or we have
4692 // idxen/offen/bothen and we fall back to a waterfall loop.
4693
4694 MachineBasicBlock &MBB = *MI.getParent();
4695
4696 MachineOperand *VAddr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
4697 if (VAddr && AMDGPU::getIfAddr64Inst(MI.getOpcode()) != -1) {
4698 // This is already an ADDR64 instruction so we need to add the pointer
4699 // extracted from the resource descriptor to the current value of VAddr.
4700 Register NewVAddrLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4701 Register NewVAddrHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
4702 Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4703
4704 const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4705 Register CondReg0 = MRI.createVirtualRegister(BoolXExecRC);
4706 Register CondReg1 = MRI.createVirtualRegister(BoolXExecRC);
4707
4708 unsigned RsrcPtr, NewSRsrc;
4709 std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc);
4710
4711 // NewVaddrLo = RsrcPtr:sub0 + VAddr:sub0
4712 const DebugLoc &DL = MI.getDebugLoc();
4713 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e64), NewVAddrLo)
4714 .addDef(CondReg0)
4715 .addReg(RsrcPtr, 0, AMDGPU::sub0)
4716 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
4717 .addImm(0);
4718
4719 // NewVaddrHi = RsrcPtr:sub1 + VAddr:sub1
4720 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e64), NewVAddrHi)
4721 .addDef(CondReg1, RegState::Dead)
4722 .addReg(RsrcPtr, 0, AMDGPU::sub1)
4723 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
4724 .addReg(CondReg0, RegState::Kill)
4725 .addImm(0);
4726
4727 // NewVaddr = {NewVaddrHi, NewVaddrLo}
4728 BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
4729 .addReg(NewVAddrLo)
4730 .addImm(AMDGPU::sub0)
4731 .addReg(NewVAddrHi)
4732 .addImm(AMDGPU::sub1);
4733
4734 VAddr->setReg(NewVAddr);
4735 Rsrc->setReg(NewSRsrc);
4736 } else if (!VAddr && ST.hasAddr64()) {
4737 // This instructions is the _OFFSET variant, so we need to convert it to
4738 // ADDR64.
4739 assert(MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration()((MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration
() < AMDGPUSubtarget::VOLCANIC_ISLANDS && "FIXME: Need to emit flat atomics here"
) ? static_cast<void> (0) : __assert_fail ("MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS && \"FIXME: Need to emit flat atomics here\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 4741, __PRETTY_FUNCTION__))
4740 < AMDGPUSubtarget::VOLCANIC_ISLANDS &&((MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration
() < AMDGPUSubtarget::VOLCANIC_ISLANDS && "FIXME: Need to emit flat atomics here"
) ? static_cast<void> (0) : __assert_fail ("MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS && \"FIXME: Need to emit flat atomics here\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 4741, __PRETTY_FUNCTION__))
4741 "FIXME: Need to emit flat atomics here")((MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration
() < AMDGPUSubtarget::VOLCANIC_ISLANDS && "FIXME: Need to emit flat atomics here"
) ? static_cast<void> (0) : __assert_fail ("MBB.getParent()->getSubtarget<GCNSubtarget>().getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS && \"FIXME: Need to emit flat atomics here\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 4741, __PRETTY_FUNCTION__))
;
4742
4743 unsigned RsrcPtr, NewSRsrc;
4744 std::tie(RsrcPtr, NewSRsrc) = extractRsrcPtr(*this, MI, *Rsrc);
4745
4746 Register NewVAddr = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
4747 MachineOperand *VData = getNamedOperand(MI, AMDGPU::OpName::vdata);
4748 MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
4749 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset);
4750 unsigned Addr64Opcode = AMDGPU::getAddr64Inst(MI.getOpcode());
4751
4752 // Atomics rith return have have an additional tied operand and are
4753 // missing some of the special bits.
4754 MachineOperand *VDataIn = getNamedOperand(MI, AMDGPU::OpName::vdata_in);
4755 MachineInstr *Addr64;
4756
4757 if (!VDataIn) {
4758 // Regular buffer load / store.
4759 MachineInstrBuilder MIB =
4760 BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode))
4761 .add(*VData)
4762 .addReg(NewVAddr)
4763 .addReg(NewSRsrc)
4764 .add(*SOffset)
4765 .add(*Offset);
4766
4767 // Atomics do not have this operand.
4768 if (const MachineOperand *GLC =
4769 getNamedOperand(MI, AMDGPU::OpName::glc)) {
4770 MIB.addImm(GLC->getImm());
4771 }
4772 if (const MachineOperand *DLC =
4773 getNamedOperand(MI, AMDGPU::OpName::dlc)) {
4774 MIB.addImm(DLC->getImm());
4775 }
4776
4777 MIB.addImm(getNamedImmOperand(MI, AMDGPU::OpName::slc));
4778
4779 if (const MachineOperand *TFE =
4780 getNamedOperand(MI, AMDGPU::OpName::tfe)) {
4781 MIB.addImm(TFE->getImm());
4782 }
4783
4784 MIB.addImm(getNamedImmOperand(MI, AMDGPU::OpName::swz));
4785
4786 MIB.cloneMemRefs(MI);
4787 Addr64 = MIB;
4788 } else {
4789 // Atomics with return.
4790 Addr64 = BuildMI(MBB, MI, MI.getDebugLoc(), get(Addr64Opcode))
4791 .add(*VData)
4792 .add(*VDataIn)
4793 .addReg(NewVAddr)
4794 .addReg(NewSRsrc)
4795 .add(*SOffset)
4796 .add(*Offset)
4797 .addImm(getNamedImmOperand(MI, AMDGPU::OpName::slc))
4798 .cloneMemRefs(MI);
4799 }
4800
4801 MI.removeFromParent();
4802
4803 // NewVaddr = {NewVaddrHi, NewVaddrLo}
4804 BuildMI(MBB, Addr64, Addr64->getDebugLoc(), get(AMDGPU::REG_SEQUENCE),
4805 NewVAddr)
4806 .addReg(RsrcPtr, 0, AMDGPU::sub0)
4807 .addImm(AMDGPU::sub0)
4808 .addReg(RsrcPtr, 0, AMDGPU::sub1)
4809 .addImm(AMDGPU::sub1);
4810 } else {
4811 // This is another variant; legalize Rsrc with waterfall loop from VGPRs
4812 // to SGPRs.
4813 loadSRsrcFromVGPR(*this, MI, *Rsrc, MDT);
4814 }
4815 }
4816}
4817
4818void SIInstrInfo::moveToVALU(MachineInstr &TopInst,
4819 MachineDominatorTree *MDT) const {
4820 SetVectorType Worklist;
4821 Worklist.insert(&TopInst);
4822
4823 while (!Worklist.empty()) {
4824 MachineInstr &Inst = *Worklist.pop_back_val();
4825 MachineBasicBlock *MBB = Inst.getParent();
4826 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
4827
4828 unsigned Opcode = Inst.getOpcode();
4829 unsigned NewOpcode = getVALUOp(Inst);
4830
4831 // Handle some special cases
4832 switch (Opcode) {
4833 default:
4834 break;
4835 case AMDGPU::S_ADD_U64_PSEUDO:
4836 case AMDGPU::S_SUB_U64_PSEUDO:
4837 splitScalar64BitAddSub(Worklist, Inst, MDT);
4838 Inst.eraseFromParent();
4839 continue;
4840 case AMDGPU::S_ADD_I32:
4841 case AMDGPU::S_SUB_I32:
4842 // FIXME: The u32 versions currently selected use the carry.
4843 if (moveScalarAddSub(Worklist, Inst, MDT))
4844 continue;
4845
4846 // Default handling
4847 break;
4848 case AMDGPU::S_AND_B64:
4849 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_AND_B32, MDT);
4850 Inst.eraseFromParent();
4851 continue;
4852
4853 case AMDGPU::S_OR_B64:
4854 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_OR_B32, MDT);
4855 Inst.eraseFromParent();
4856 continue;
4857
4858 case AMDGPU::S_XOR_B64:
4859 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XOR_B32, MDT);
4860 Inst.eraseFromParent();
4861 continue;
4862
4863 case AMDGPU::S_NAND_B64:
4864 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_NAND_B32, MDT);
4865 Inst.eraseFromParent();
4866 continue;
4867
4868 case AMDGPU::S_NOR_B64:
4869 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_NOR_B32, MDT);
4870 Inst.eraseFromParent();
4871 continue;
4872
4873 case AMDGPU::S_XNOR_B64:
4874 if (ST.hasDLInsts())
4875 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_XNOR_B32, MDT);
4876 else
4877 splitScalar64BitXnor(Worklist, Inst, MDT);
4878 Inst.eraseFromParent();
4879 continue;
4880
4881 case AMDGPU::S_ANDN2_B64:
4882 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ANDN2_B32, MDT);
4883 Inst.eraseFromParent();
4884 continue;
4885
4886 case AMDGPU::S_ORN2_B64:
4887 splitScalar64BitBinaryOp(Worklist, Inst, AMDGPU::S_ORN2_B32, MDT);
4888 Inst.eraseFromParent();
4889 continue;
4890
4891 case AMDGPU::S_NOT_B64:
4892 splitScalar64BitUnaryOp(Worklist, Inst, AMDGPU::S_NOT_B32);
4893 Inst.eraseFromParent();
4894 continue;
4895
4896 case AMDGPU::S_BCNT1_I32_B64:
4897 splitScalar64BitBCNT(Worklist, Inst);
4898 Inst.eraseFromParent();
4899 continue;
4900
4901 case AMDGPU::S_BFE_I64:
4902 splitScalar64BitBFE(Worklist, Inst);
4903 Inst.eraseFromParent();
4904 continue;
4905
4906 case AMDGPU::S_LSHL_B32:
4907 if (ST.hasOnlyRevVALUShifts()) {
4908 NewOpcode = AMDGPU::V_LSHLREV_B32_e64;
4909 swapOperands(Inst);
4910 }
4911 break;
4912 case AMDGPU::S_ASHR_I32:
4913 if (ST.hasOnlyRevVALUShifts()) {
4914 NewOpcode = AMDGPU::V_ASHRREV_I32_e64;
4915 swapOperands(Inst);
4916 }
4917 break;
4918 case AMDGPU::S_LSHR_B32:
4919 if (ST.hasOnlyRevVALUShifts()) {
4920 NewOpcode = AMDGPU::V_LSHRREV_B32_e64;
4921 swapOperands(Inst);
4922 }
4923 break;
4924 case AMDGPU::S_LSHL_B64:
4925 if (ST.hasOnlyRevVALUShifts()) {
4926 NewOpcode = AMDGPU::V_LSHLREV_B64;
4927 swapOperands(Inst);
4928 }
4929 break;
4930 case AMDGPU::S_ASHR_I64:
4931 if (ST.hasOnlyRevVALUShifts()) {
4932 NewOpcode = AMDGPU::V_ASHRREV_I64;
4933 swapOperands(Inst);
4934 }
4935 break;
4936 case AMDGPU::S_LSHR_B64:
4937 if (ST.hasOnlyRevVALUShifts()) {
4938 NewOpcode = AMDGPU::V_LSHRREV_B64;
4939 swapOperands(Inst);
4940 }
4941 break;
4942
4943 case AMDGPU::S_ABS_I32:
4944 lowerScalarAbs(Worklist, Inst);
4945 Inst.eraseFromParent();
4946 continue;
4947
4948 case AMDGPU::S_CBRANCH_SCC0:
4949 case AMDGPU::S_CBRANCH_SCC1:
4950 // Clear unused bits of vcc
4951 if (ST.isWave32())
4952 BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B32),
4953 AMDGPU::VCC_LO)
4954 .addReg(AMDGPU::EXEC_LO)
4955 .addReg(AMDGPU::VCC_LO);
4956 else
4957 BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B64),
4958 AMDGPU::VCC)
4959 .addReg(AMDGPU::EXEC)
4960 .addReg(AMDGPU::VCC);
4961 break;
4962
4963 case AMDGPU::S_BFE_U64:
4964 case AMDGPU::S_BFM_B64:
4965 llvm_unreachable("Moving this op to VALU not implemented")::llvm::llvm_unreachable_internal("Moving this op to VALU not implemented"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 4965)
;
4966
4967 case AMDGPU::S_PACK_LL_B32_B16:
4968 case AMDGPU::S_PACK_LH_B32_B16:
4969 case AMDGPU::S_PACK_HH_B32_B16:
4970 movePackToVALU(Worklist, MRI, Inst);
4971 Inst.eraseFromParent();
4972 continue;
4973
4974 case AMDGPU::S_XNOR_B32:
4975 lowerScalarXnor(Worklist, Inst);
4976 Inst.eraseFromParent();
4977 continue;
4978
4979 case AMDGPU::S_NAND_B32:
4980 splitScalarNotBinop(Worklist, Inst, AMDGPU::S_AND_B32);
4981 Inst.eraseFromParent();
4982 continue;
4983
4984 case AMDGPU::S_NOR_B32:
4985 splitScalarNotBinop(Worklist, Inst, AMDGPU::S_OR_B32);
4986 Inst.eraseFromParent();
4987 continue;
4988
4989 case AMDGPU::S_ANDN2_B32:
4990 splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_AND_B32);
4991 Inst.eraseFromParent();
4992 continue;
4993
4994 case AMDGPU::S_ORN2_B32:
4995 splitScalarBinOpN2(Worklist, Inst, AMDGPU::S_OR_B32);
4996 Inst.eraseFromParent();
4997 continue;
4998 }
4999
5000 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) {
5001 // We cannot move this instruction to the VALU, so we should try to
5002 // legalize its operands instead.
5003 legalizeOperands(Inst, MDT);
5004 continue;
5005 }
5006
5007 // Use the new VALU Opcode.
5008 const MCInstrDesc &NewDesc = get(NewOpcode);
5009 Inst.setDesc(NewDesc);
5010
5011 // Remove any references to SCC. Vector instructions can't read from it, and
5012 // We're just about to add the implicit use / defs of VCC, and we don't want
5013 // both.
5014 for (unsigned i = Inst.getNumOperands() - 1; i > 0; --i) {
5015 MachineOperand &Op = Inst.getOperand(i);
5016 if (Op.isReg() && Op.getReg() == AMDGPU::SCC) {
5017 // Only propagate through live-def of SCC.
5018 if (Op.isDef() && !Op.isDead())
5019 addSCCDefUsersToVALUWorklist(Op, Inst, Worklist);
5020 Inst.RemoveOperand(i);
5021 }
5022 }
5023
5024 if (Opcode == AMDGPU::S_SEXT_I32_I8 || Opcode == AMDGPU::S_SEXT_I32_I16) {
5025 // We are converting these to a BFE, so we need to add the missing
5026 // operands for the size and offset.
5027 unsigned Size = (Opcode == AMDGPU::S_SEXT_I32_I8) ? 8 : 16;
5028 Inst.addOperand(MachineOperand::CreateImm(0));
5029 Inst.addOperand(MachineOperand::CreateImm(Size));
5030
5031 } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) {
5032 // The VALU version adds the second operand to the result, so insert an
5033 // extra 0 operand.
5034 Inst.addOperand(MachineOperand::CreateImm(0));
5035 }
5036
5037 Inst.addImplicitDefUseOperands(*Inst.getParent()->getParent());
5038 fixImplicitOperands(Inst);
5039
5040 if (Opcode == AMDGPU::S_BFE_I32 || Opcode == AMDGPU::S_BFE_U32) {
5041 const MachineOperand &OffsetWidthOp = Inst.getOperand(2);
5042 // If we need to move this to VGPRs, we need to unpack the second operand
5043 // back into the 2 separate ones for bit offset and width.
5044 assert(OffsetWidthOp.isImm() &&((OffsetWidthOp.isImm() && "Scalar BFE is only implemented for constant width and offset"
) ? static_cast<void> (0) : __assert_fail ("OffsetWidthOp.isImm() && \"Scalar BFE is only implemented for constant width and offset\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5045, __PRETTY_FUNCTION__))
5045 "Scalar BFE is only implemented for constant width and offset")((OffsetWidthOp.isImm() && "Scalar BFE is only implemented for constant width and offset"
) ? static_cast<void> (0) : __assert_fail ("OffsetWidthOp.isImm() && \"Scalar BFE is only implemented for constant width and offset\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5045, __PRETTY_FUNCTION__))
;
5046 uint32_t Imm = OffsetWidthOp.getImm();
5047
5048 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
5049 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
5050 Inst.RemoveOperand(2); // Remove old immediate.
5051 Inst.addOperand(MachineOperand::CreateImm(Offset));
5052 Inst.addOperand(MachineOperand::CreateImm(BitWidth));
5053 }
5054
5055 bool HasDst = Inst.getOperand(0).isReg() && Inst.getOperand(0).isDef();
5056 unsigned NewDstReg = AMDGPU::NoRegister;
5057 if (HasDst) {
5058 Register DstReg = Inst.getOperand(0).getReg();
5059 if (Register::isPhysicalRegister(DstReg))
5060 continue;
5061
5062 // Update the destination register class.
5063 const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(Inst);
5064 if (!NewDstRC)
5065 continue;
5066
5067 if (Inst.isCopy() &&
5068 Register::isVirtualRegister(Inst.getOperand(1).getReg()) &&
5069 NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) {
5070 // Instead of creating a copy where src and dst are the same register
5071 // class, we just replace all uses of dst with src. These kinds of
5072 // copies interfere with the heuristics MachineSink uses to decide
5073 // whether or not to split a critical edge. Since the pass assumes
5074 // that copies will end up as machine instructions and not be
5075 // eliminated.
5076 addUsersToMoveToVALUWorklist(DstReg, MRI, Worklist);
5077 MRI.replaceRegWith(DstReg, Inst.getOperand(1).getReg());
5078 MRI.clearKillFlags(Inst.getOperand(1).getReg());
5079 Inst.getOperand(0).setReg(DstReg);
5080
5081 // Make sure we don't leave around a dead VGPR->SGPR copy. Normally
5082 // these are deleted later, but at -O0 it would leave a suspicious
5083 // looking illegal copy of an undef register.
5084 for (unsigned I = Inst.getNumOperands() - 1; I != 0; --I)
5085 Inst.RemoveOperand(I);
5086 Inst.setDesc(get(AMDGPU::IMPLICIT_DEF));
5087 continue;
5088 }
5089
5090 NewDstReg = MRI.createVirtualRegister(NewDstRC);
5091 MRI.replaceRegWith(DstReg, NewDstReg);
5092 }
5093
5094 // Legalize the operands
5095 legalizeOperands(Inst, MDT);
5096
5097 if (HasDst)
5098 addUsersToMoveToVALUWorklist(NewDstReg, MRI, Worklist);
5099 }
5100}
5101
5102// Add/sub require special handling to deal with carry outs.
5103bool SIInstrInfo::moveScalarAddSub(SetVectorType &Worklist, MachineInstr &Inst,
5104 MachineDominatorTree *MDT) const {
5105 if (ST.hasAddNoCarry()) {
5106 // Assume there is no user of scc since we don't select this in that case.
5107 // Since scc isn't used, it doesn't really matter if the i32 or u32 variant
5108 // is used.
5109
5110 MachineBasicBlock &MBB = *Inst.getParent();
5111 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5112
5113 Register OldDstReg = Inst.getOperand(0).getReg();
5114 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5115
5116 unsigned Opc = Inst.getOpcode();
5117 assert(Opc == AMDGPU::S_ADD_I32 || Opc == AMDGPU::S_SUB_I32)((Opc == AMDGPU::S_ADD_I32 || Opc == AMDGPU::S_SUB_I32) ? static_cast
<void> (0) : __assert_fail ("Opc == AMDGPU::S_ADD_I32 || Opc == AMDGPU::S_SUB_I32"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5117, __PRETTY_FUNCTION__))
;
5118
5119 unsigned NewOpc = Opc == AMDGPU::S_ADD_I32 ?
5120 AMDGPU::V_ADD_U32_e64 : AMDGPU::V_SUB_U32_e64;
5121
5122 assert(Inst.getOperand(3).getReg() == AMDGPU::SCC)((Inst.getOperand(3).getReg() == AMDGPU::SCC) ? static_cast<
void> (0) : __assert_fail ("Inst.getOperand(3).getReg() == AMDGPU::SCC"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5122, __PRETTY_FUNCTION__))
;
5123 Inst.RemoveOperand(3);
5124
5125 Inst.setDesc(get(NewOpc));
5126 Inst.addOperand(MachineOperand::CreateImm(0)); // clamp bit
5127 Inst.addImplicitDefUseOperands(*MBB.getParent());
5128 MRI.replaceRegWith(OldDstReg, ResultReg);
5129 legalizeOperands(Inst, MDT);
5130
5131 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5132 return true;
5133 }
5134
5135 return false;
5136}
5137
5138void SIInstrInfo::lowerScalarAbs(SetVectorType &Worklist,
5139 MachineInstr &Inst) const {
5140 MachineBasicBlock &MBB = *Inst.getParent();
5141 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5142 MachineBasicBlock::iterator MII = Inst;
5143 DebugLoc DL = Inst.getDebugLoc();
5144
5145 MachineOperand &Dest = Inst.getOperand(0);
5146 MachineOperand &Src = Inst.getOperand(1);
5147 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5148 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5149
5150 unsigned SubOp = ST.hasAddNoCarry() ?
5151 AMDGPU::V_SUB_U32_e32 : AMDGPU::V_SUB_I32_e32;
5152
5153 BuildMI(MBB, MII, DL, get(SubOp), TmpReg)
5154 .addImm(0)
5155 .addReg(Src.getReg());
5156
5157 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
5158 .addReg(Src.getReg())
5159 .addReg(TmpReg);
5160
5161 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5162 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5163}
5164
5165void SIInstrInfo::lowerScalarXnor(SetVectorType &Worklist,
5166 MachineInstr &Inst) const {
5167 MachineBasicBlock &MBB = *Inst.getParent();
5168 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5169 MachineBasicBlock::iterator MII = Inst;
5170 const DebugLoc &DL = Inst.getDebugLoc();
5171
5172 MachineOperand &Dest = Inst.getOperand(0);
5173 MachineOperand &Src0 = Inst.getOperand(1);
5174 MachineOperand &Src1 = Inst.getOperand(2);
5175
5176 if (ST.hasDLInsts()) {
5177 Register NewDest = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5178 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src0, MRI, DL);
5179 legalizeGenericOperand(MBB, MII, &AMDGPU::VGPR_32RegClass, Src1, MRI, DL);
5180
5181 BuildMI(MBB, MII, DL, get(AMDGPU::V_XNOR_B32_e64), NewDest)
5182 .add(Src0)
5183 .add(Src1);
5184
5185 MRI.replaceRegWith(Dest.getReg(), NewDest);
5186 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
5187 } else {
5188 // Using the identity !(x ^ y) == (!x ^ y) == (x ^ !y), we can
5189 // invert either source and then perform the XOR. If either source is a
5190 // scalar register, then we can leave the inversion on the scalar unit to
5191 // acheive a better distrubution of scalar and vector instructions.
5192 bool Src0IsSGPR = Src0.isReg() &&
5193 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
5194 bool Src1IsSGPR = Src1.isReg() &&
5195 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
5196 MachineInstr *Xor;
5197 Register Temp = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5198 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5199
5200 // Build a pair of scalar instructions and add them to the work list.
5201 // The next iteration over the work list will lower these to the vector
5202 // unit as necessary.
5203 if (Src0IsSGPR) {
5204 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);
5205 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
5206 .addReg(Temp)
5207 .add(Src1);
5208 } else if (Src1IsSGPR) {
5209 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src1);
5210 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
5211 .add(Src0)
5212 .addReg(Temp);
5213 } else {
5214 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), Temp)
5215 .add(Src0)
5216 .add(Src1);
5217 MachineInstr *Not =
5218 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest).addReg(Temp);
5219 Worklist.insert(Not);
5220 }
5221
5222 MRI.replaceRegWith(Dest.getReg(), NewDest);
5223
5224 Worklist.insert(Xor);
5225
5226 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
5227 }
5228}
5229
5230void SIInstrInfo::splitScalarNotBinop(SetVectorType &Worklist,
5231 MachineInstr &Inst,
5232 unsigned Opcode) const {
5233 MachineBasicBlock &MBB = *Inst.getParent();
5234 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5235 MachineBasicBlock::iterator MII = Inst;
5236 const DebugLoc &DL = Inst.getDebugLoc();
5237
5238 MachineOperand &Dest = Inst.getOperand(0);
5239 MachineOperand &Src0 = Inst.getOperand(1);
5240 MachineOperand &Src1 = Inst.getOperand(2);
5241
5242 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5243 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
5244
5245 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), Interm)
5246 .add(Src0)
5247 .add(Src1);
5248
5249 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)
5250 .addReg(Interm);
5251
5252 Worklist.insert(&Op);
5253 Worklist.insert(&Not);
5254
5255 MRI.replaceRegWith(Dest.getReg(), NewDest);
5256 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
5257}
5258
5259void SIInstrInfo::splitScalarBinOpN2(SetVectorType& Worklist,
5260 MachineInstr &Inst,
5261 unsigned Opcode) const {
5262 MachineBasicBlock &MBB = *Inst.getParent();
5263 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5264 MachineBasicBlock::iterator MII = Inst;
5265 const DebugLoc &DL = Inst.getDebugLoc();
5266
5267 MachineOperand &Dest = Inst.getOperand(0);
5268 MachineOperand &Src0 = Inst.getOperand(1);
5269 MachineOperand &Src1 = Inst.getOperand(2);
5270
5271 Register NewDest = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
5272 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
5273
5274 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Interm)
5275 .add(Src1);
5276
5277 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), NewDest)
5278 .add(Src0)
5279 .addReg(Interm);
5280
5281 Worklist.insert(&Not);
5282 Worklist.insert(&Op);
5283
5284 MRI.replaceRegWith(Dest.getReg(), NewDest);
5285 addUsersToMoveToVALUWorklist(NewDest, MRI, Worklist);
5286}
5287
5288void SIInstrInfo::splitScalar64BitUnaryOp(
5289 SetVectorType &Worklist, MachineInstr &Inst,
5290 unsigned Opcode) const {
5291 MachineBasicBlock &MBB = *Inst.getParent();
5292 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5293
5294 MachineOperand &Dest = Inst.getOperand(0);
5295 MachineOperand &Src0 = Inst.getOperand(1);
5296 DebugLoc DL = Inst.getDebugLoc();
5297
5298 MachineBasicBlock::iterator MII = Inst;
5299
5300 const MCInstrDesc &InstDesc = get(Opcode);
5301 const TargetRegisterClass *Src0RC = Src0.isReg() ?
5302 MRI.getRegClass(Src0.getReg()) :
5303 &AMDGPU::SGPR_32RegClass;
5304
5305 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
5306
5307 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5308 AMDGPU::sub0, Src0SubRC);
5309
5310 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5311 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
5312 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
5313
5314 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
5315 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
5316
5317 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5318 AMDGPU::sub1, Src0SubRC);
5319
5320 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
5321 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
5322
5323 Register FullDestReg = MRI.createVirtualRegister(NewDestRC);
5324 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5325 .addReg(DestSub0)
5326 .addImm(AMDGPU::sub0)
5327 .addReg(DestSub1)
5328 .addImm(AMDGPU::sub1);
5329
5330 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
5331
5332 Worklist.insert(&LoHalf);
5333 Worklist.insert(&HiHalf);
5334
5335 // We don't need to legalizeOperands here because for a single operand, src0
5336 // will support any kind of input.
5337
5338 // Move all users of this moved value.
5339 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
5340}
5341
5342void SIInstrInfo::splitScalar64BitAddSub(SetVectorType &Worklist,
5343 MachineInstr &Inst,
5344 MachineDominatorTree *MDT) const {
5345 bool IsAdd = (Inst.getOpcode() == AMDGPU::S_ADD_U64_PSEUDO);
5346
5347 MachineBasicBlock &MBB = *Inst.getParent();
5348 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5349 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5350
5351 Register FullDestReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5352 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5353 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5354
5355 Register CarryReg = MRI.createVirtualRegister(CarryRC);
5356 Register DeadCarryReg = MRI.createVirtualRegister(CarryRC);
5357
5358 MachineOperand &Dest = Inst.getOperand(0);
5359 MachineOperand &Src0 = Inst.getOperand(1);
5360 MachineOperand &Src1 = Inst.getOperand(2);
5361 const DebugLoc &DL = Inst.getDebugLoc();
5362 MachineBasicBlock::iterator MII = Inst;
5363
5364 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
5365 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
5366 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
5367 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
5368
5369 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5370 AMDGPU::sub0, Src0SubRC);
5371 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
5372 AMDGPU::sub0, Src1SubRC);
5373
5374
5375 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5376 AMDGPU::sub1, Src0SubRC);
5377 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
5378 AMDGPU::sub1, Src1SubRC);
5379
5380 unsigned LoOpc = IsAdd ? AMDGPU::V_ADD_I32_e64 : AMDGPU::V_SUB_I32_e64;
5381 MachineInstr *LoHalf =
5382 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0)
5383 .addReg(CarryReg, RegState::Define)
5384 .add(SrcReg0Sub0)
5385 .add(SrcReg1Sub0)
5386 .addImm(0); // clamp bit
5387
5388 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64;
5389 MachineInstr *HiHalf =
5390 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1)
5391 .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
5392 .add(SrcReg0Sub1)
5393 .add(SrcReg1Sub1)
5394 .addReg(CarryReg, RegState::Kill)
5395 .addImm(0); // clamp bit
5396
5397 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5398 .addReg(DestSub0)
5399 .addImm(AMDGPU::sub0)
5400 .addReg(DestSub1)
5401 .addImm(AMDGPU::sub1);
5402
5403 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
5404
5405 // Try to legalize the operands in case we need to swap the order to keep it
5406 // valid.
5407 legalizeOperands(*LoHalf, MDT);
5408 legalizeOperands(*HiHalf, MDT);
5409
5410 // Move all users of this moved vlaue.
5411 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
5412}
5413
5414void SIInstrInfo::splitScalar64BitBinaryOp(SetVectorType &Worklist,
5415 MachineInstr &Inst, unsigned Opcode,
5416 MachineDominatorTree *MDT) const {
5417 MachineBasicBlock &MBB = *Inst.getParent();
5418 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5419
5420 MachineOperand &Dest = Inst.getOperand(0);
5421 MachineOperand &Src0 = Inst.getOperand(1);
5422 MachineOperand &Src1 = Inst.getOperand(2);
5423 DebugLoc DL = Inst.getDebugLoc();
5424
5425 MachineBasicBlock::iterator MII = Inst;
5426
5427 const MCInstrDesc &InstDesc = get(Opcode);
5428 const TargetRegisterClass *Src0RC = Src0.isReg() ?
5429 MRI.getRegClass(Src0.getReg()) :
5430 &AMDGPU::SGPR_32RegClass;
5431
5432 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
5433 const TargetRegisterClass *Src1RC = Src1.isReg() ?
5434 MRI.getRegClass(Src1.getReg()) :
5435 &AMDGPU::SGPR_32RegClass;
5436
5437 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
5438
5439 MachineOperand SrcReg0Sub0 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5440 AMDGPU::sub0, Src0SubRC);
5441 MachineOperand SrcReg1Sub0 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
5442 AMDGPU::sub0, Src1SubRC);
5443 MachineOperand SrcReg0Sub1 = buildExtractSubRegOrImm(MII, MRI, Src0, Src0RC,
5444 AMDGPU::sub1, Src0SubRC);
5445 MachineOperand SrcReg1Sub1 = buildExtractSubRegOrImm(MII, MRI, Src1, Src1RC,
5446 AMDGPU::sub1, Src1SubRC);
5447
5448 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5449 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
5450 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
5451
5452 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC);
5453 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
5454 .add(SrcReg0Sub0)
5455 .add(SrcReg1Sub0);
5456
5457 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC);
5458 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)
5459 .add(SrcReg0Sub1)
5460 .add(SrcReg1Sub1);
5461
5462 Register FullDestReg = MRI.createVirtualRegister(NewDestRC);
5463 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5464 .addReg(DestSub0)
5465 .addImm(AMDGPU::sub0)
5466 .addReg(DestSub1)
5467 .addImm(AMDGPU::sub1);
5468
5469 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
5470
5471 Worklist.insert(&LoHalf);
5472 Worklist.insert(&HiHalf);
5473
5474 // Move all users of this moved vlaue.
5475 addUsersToMoveToVALUWorklist(FullDestReg, MRI, Worklist);
5476}
5477
5478void SIInstrInfo::splitScalar64BitXnor(SetVectorType &Worklist,
5479 MachineInstr &Inst,
5480 MachineDominatorTree *MDT) const {
5481 MachineBasicBlock &MBB = *Inst.getParent();
5482 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5483
5484 MachineOperand &Dest = Inst.getOperand(0);
5485 MachineOperand &Src0 = Inst.getOperand(1);
5486 MachineOperand &Src1 = Inst.getOperand(2);
5487 const DebugLoc &DL = Inst.getDebugLoc();
5488
5489 MachineBasicBlock::iterator MII = Inst;
5490
5491 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5492
5493 Register Interm = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
5494
5495 MachineOperand* Op0;
5496 MachineOperand* Op1;
5497
5498 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) {
5499 Op0 = &Src0;
5500 Op1 = &Src1;
5501 } else {
5502 Op0 = &Src1;
5503 Op1 = &Src0;
5504 }
5505
5506 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B64), Interm)
5507 .add(*Op0);
5508
5509 Register NewDest = MRI.createVirtualRegister(DestRC);
5510
5511 MachineInstr &Xor = *BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B64), NewDest)
5512 .addReg(Interm)
5513 .add(*Op1);
5514
5515 MRI.replaceRegWith(Dest.getReg(), NewDest);
5516
5517 Worklist.insert(&Xor);
5518}
5519
5520void SIInstrInfo::splitScalar64BitBCNT(
5521 SetVectorType &Worklist, MachineInstr &Inst) const {
5522 MachineBasicBlock &MBB = *Inst.getParent();
5523 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5524
5525 MachineBasicBlock::iterator MII = Inst;
5526 const DebugLoc &DL = Inst.getDebugLoc();
5527
5528 MachineOperand &Dest = Inst.getOperand(0);
5529 MachineOperand &Src = Inst.getOperand(1);
5530
5531 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
5532 const TargetRegisterClass *SrcRC = Src.isReg() ?
5533 MRI.getRegClass(Src.getReg()) :
5534 &AMDGPU::SGPR_32RegClass;
5535
5536 Register MidReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5537 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5538
5539 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
5540
5541 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
5542 AMDGPU::sub0, SrcSubRC);
5543 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC,
5544 AMDGPU::sub1, SrcSubRC);
5545
5546 BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);
5547
5548 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
5549
5550 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5551
5552 // We don't need to legalize operands here. src0 for etiher instruction can be
5553 // an SGPR, and the second input is unused or determined here.
5554 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5555}
5556
5557void SIInstrInfo::splitScalar64BitBFE(SetVectorType &Worklist,
5558 MachineInstr &Inst) const {
5559 MachineBasicBlock &MBB = *Inst.getParent();
5560 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
5561 MachineBasicBlock::iterator MII = Inst;
5562 const DebugLoc &DL = Inst.getDebugLoc();
5563
5564 MachineOperand &Dest = Inst.getOperand(0);
5565 uint32_t Imm = Inst.getOperand(2).getImm();
5566 uint32_t Offset = Imm & 0x3f; // Extract bits [5:0].
5567 uint32_t BitWidth = (Imm & 0x7f0000) >> 16; // Extract bits [22:16].
5568
5569 (void) Offset;
5570
5571 // Only sext_inreg cases handled.
5572 assert(Inst.getOpcode() == AMDGPU::S_BFE_I64 && BitWidth <= 32 &&((Inst.getOpcode() == AMDGPU::S_BFE_I64 && BitWidth <=
32 && Offset == 0 && "Not implemented") ? static_cast
<void> (0) : __assert_fail ("Inst.getOpcode() == AMDGPU::S_BFE_I64 && BitWidth <= 32 && Offset == 0 && \"Not implemented\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5573, __PRETTY_FUNCTION__))
5573 Offset == 0 && "Not implemented")((Inst.getOpcode() == AMDGPU::S_BFE_I64 && BitWidth <=
32 && Offset == 0 && "Not implemented") ? static_cast
<void> (0) : __assert_fail ("Inst.getOpcode() == AMDGPU::S_BFE_I64 && BitWidth <= 32 && Offset == 0 && \"Not implemented\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5573, __PRETTY_FUNCTION__))
;
5574
5575 if (BitWidth < 32) {
5576 Register MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5577 Register MidRegHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5578 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5579
5580 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
5581 .addReg(Inst.getOperand(1).getReg(), 0, AMDGPU::sub0)
5582 .addImm(0)
5583 .addImm(BitWidth);
5584
5585 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
5586 .addImm(31)
5587 .addReg(MidRegLo);
5588
5589 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
5590 .addReg(MidRegLo)
5591 .addImm(AMDGPU::sub0)
5592 .addReg(MidRegHi)
5593 .addImm(AMDGPU::sub1);
5594
5595 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5596 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5597 return;
5598 }
5599
5600 MachineOperand &Src = Inst.getOperand(1);
5601 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5602 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass);
5603
5604 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
5605 .addImm(31)
5606 .addReg(Src.getReg(), 0, AMDGPU::sub0);
5607
5608 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
5609 .addReg(Src.getReg(), 0, AMDGPU::sub0)
5610 .addImm(AMDGPU::sub0)
5611 .addReg(TmpReg)
5612 .addImm(AMDGPU::sub1);
5613
5614 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5615 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5616}
5617
5618void SIInstrInfo::addUsersToMoveToVALUWorklist(
5619 unsigned DstReg,
5620 MachineRegisterInfo &MRI,
5621 SetVectorType &Worklist) const {
5622 for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
5623 E = MRI.use_end(); I != E;) {
5624 MachineInstr &UseMI = *I->getParent();
5625
5626 unsigned OpNo = 0;
5627
5628 switch (UseMI.getOpcode()) {
5629 case AMDGPU::COPY:
5630 case AMDGPU::WQM:
5631 case AMDGPU::SOFT_WQM:
5632 case AMDGPU::WWM:
5633 case AMDGPU::REG_SEQUENCE:
5634 case AMDGPU::PHI:
5635 case AMDGPU::INSERT_SUBREG:
5636 break;
5637 default:
5638 OpNo = I.getOperandNo();
5639 break;
5640 }
5641
5642 if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) {
5643 Worklist.insert(&UseMI);
5644
5645 do {
5646 ++I;
5647 } while (I != E && I->getParent() == &UseMI);
5648 } else {
5649 ++I;
5650 }
5651 }
5652}
5653
5654void SIInstrInfo::movePackToVALU(SetVectorType &Worklist,
5655 MachineRegisterInfo &MRI,
5656 MachineInstr &Inst) const {
5657 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5658 MachineBasicBlock *MBB = Inst.getParent();
5659 MachineOperand &Src0 = Inst.getOperand(1);
5660 MachineOperand &Src1 = Inst.getOperand(2);
5661 const DebugLoc &DL = Inst.getDebugLoc();
5662
5663 switch (Inst.getOpcode()) {
5664 case AMDGPU::S_PACK_LL_B32_B16: {
5665 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5666 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5667
5668 // FIXME: Can do a lot better if we know the high bits of src0 or src1 are
5669 // 0.
5670 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5671 .addImm(0xffff);
5672
5673 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_B32_e64), TmpReg)
5674 .addReg(ImmReg, RegState::Kill)
5675 .add(Src0);
5676
5677 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32), ResultReg)
5678 .add(Src1)
5679 .addImm(16)
5680 .addReg(TmpReg, RegState::Kill);
5681 break;
5682 }
5683 case AMDGPU::S_PACK_LH_B32_B16: {
5684 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5685 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5686 .addImm(0xffff);
5687 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_BFI_B32), ResultReg)
5688 .addReg(ImmReg, RegState::Kill)
5689 .add(Src0)
5690 .add(Src1);
5691 break;
5692 }
5693 case AMDGPU::S_PACK_HH_B32_B16: {
5694 Register ImmReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5695 Register TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
5696 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
5697 .addImm(16)
5698 .add(Src0);
5699 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5700 .addImm(0xffff0000);
5701 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32), ResultReg)
5702 .add(Src1)
5703 .addReg(ImmReg, RegState::Kill)
5704 .addReg(TmpReg, RegState::Kill);
5705 break;
5706 }
5707 default:
5708 llvm_unreachable("unhandled s_pack_* instruction")::llvm::llvm_unreachable_internal("unhandled s_pack_* instruction"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5708)
;
5709 }
5710
5711 MachineOperand &Dest = Inst.getOperand(0);
5712 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5713 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist);
5714}
5715
5716void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op,
5717 MachineInstr &SCCDefInst,
5718 SetVectorType &Worklist) const {
5719 // Ensure that def inst defines SCC, which is still live.
5720 assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() &&((Op.isReg() && Op.getReg() == AMDGPU::SCC &&
Op.isDef() && !Op.isDead() && Op.getParent()
== &SCCDefInst) ? static_cast<void> (0) : __assert_fail
("Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() && !Op.isDead() && Op.getParent() == &SCCDefInst"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5721, __PRETTY_FUNCTION__))
5721 !Op.isDead() && Op.getParent() == &SCCDefInst)((Op.isReg() && Op.getReg() == AMDGPU::SCC &&
Op.isDef() && !Op.isDead() && Op.getParent()
== &SCCDefInst) ? static_cast<void> (0) : __assert_fail
("Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() && !Op.isDead() && Op.getParent() == &SCCDefInst"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5721, __PRETTY_FUNCTION__))
;
5722 // This assumes that all the users of SCC are in the same block
5723 // as the SCC def.
5724 for (MachineInstr &MI : // Skip the def inst itself.
5725 make_range(std::next(MachineBasicBlock::iterator(SCCDefInst)),
5726 SCCDefInst.getParent()->end())) {
5727 // Check if SCC is used first.
5728 if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI) != -1)
5729 Worklist.insert(&MI);
5730 // Exit if we find another SCC def.
5731 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1)
5732 return;
5733 }
5734}
5735
5736const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
5737 const MachineInstr &Inst) const {
5738 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
5739
5740 switch (Inst.getOpcode()) {
5741 // For target instructions, getOpRegClass just returns the virtual register
5742 // class associated with the operand, so we need to find an equivalent VGPR
5743 // register class in order to move the instruction to the VALU.
5744 case AMDGPU::COPY:
5745 case AMDGPU::PHI:
5746 case AMDGPU::REG_SEQUENCE:
5747 case AMDGPU::INSERT_SUBREG:
5748 case AMDGPU::WQM:
5749 case AMDGPU::SOFT_WQM:
5750 case AMDGPU::WWM: {
5751 const TargetRegisterClass *SrcRC = getOpRegClass(Inst, 1);
5752 if (RI.hasAGPRs(SrcRC)) {
5753 if (RI.hasAGPRs(NewDstRC))
5754 return nullptr;
5755
5756 switch (Inst.getOpcode()) {
5757 case AMDGPU::PHI:
5758 case AMDGPU::REG_SEQUENCE:
5759 case AMDGPU::INSERT_SUBREG:
5760 NewDstRC = RI.getEquivalentAGPRClass(NewDstRC);
5761 break;
5762 default:
5763 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
5764 }
5765
5766 if (!NewDstRC)
5767 return nullptr;
5768 } else {
5769 if (RI.hasVGPRs(NewDstRC) || NewDstRC == &AMDGPU::VReg_1RegClass)
5770 return nullptr;
5771
5772 NewDstRC = RI.getEquivalentVGPRClass(NewDstRC);
5773 if (!NewDstRC)
5774 return nullptr;
5775 }
5776
5777 return NewDstRC;
5778 }
5779 default:
5780 return NewDstRC;
5781 }
5782}
5783
5784// Find the one SGPR operand we are allowed to use.
5785unsigned SIInstrInfo::findUsedSGPR(const MachineInstr &MI,
5786 int OpIndices[3]) const {
5787 const MCInstrDesc &Desc = MI.getDesc();
5788
5789 // Find the one SGPR operand we are allowed to use.
5790 //
5791 // First we need to consider the instruction's operand requirements before
5792 // legalizing. Some operands are required to be SGPRs, such as implicit uses
5793 // of VCC, but we are still bound by the constant bus requirement to only use
5794 // one.
5795 //
5796 // If the operand's class is an SGPR, we can never move it.
5797
5798 unsigned SGPRReg = findImplicitSGPRRead(MI);
5799 if (SGPRReg != AMDGPU::NoRegister)
5800 return SGPRReg;
5801
5802 unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
5803 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
5804
5805 for (unsigned i = 0; i < 3; ++i) {
5806 int Idx = OpIndices[i];
5807 if (Idx == -1)
5808 break;
5809
5810 const MachineOperand &MO = MI.getOperand(Idx);
5811 if (!MO.isReg())
5812 continue;
5813
5814 // Is this operand statically required to be an SGPR based on the operand
5815 // constraints?
5816 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
5817 bool IsRequiredSGPR = RI.isSGPRClass(OpRC);
5818 if (IsRequiredSGPR)
5819 return MO.getReg();
5820
5821 // If this could be a VGPR or an SGPR, Check the dynamic register class.
5822 Register Reg = MO.getReg();
5823 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
5824 if (RI.isSGPRClass(RegRC))
5825 UsedSGPRs[i] = Reg;
5826 }
5827
5828 // We don't have a required SGPR operand, so we have a bit more freedom in
5829 // selecting operands to move.
5830
5831 // Try to select the most used SGPR. If an SGPR is equal to one of the
5832 // others, we choose that.
5833 //
5834 // e.g.
5835 // V_FMA_F32 v0, s0, s0, s0 -> No moves
5836 // V_FMA_F32 v0, s0, s1, s0 -> Move s1
5837
5838 // TODO: If some of the operands are 64-bit SGPRs and some 32, we should
5839 // prefer those.
5840
5841 if (UsedSGPRs[0] != AMDGPU::NoRegister) {
5842 if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
5843 SGPRReg = UsedSGPRs[0];
5844 }
5845
5846 if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
5847 if (UsedSGPRs[1] == UsedSGPRs[2])
5848 SGPRReg = UsedSGPRs[1];
5849 }
5850
5851 return SGPRReg;
5852}
5853
5854MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
5855 unsigned OperandName) const {
5856 int Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), OperandName);
5857 if (Idx == -1)
5858 return nullptr;
5859
5860 return &MI.getOperand(Idx);
5861}
5862
5863uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
5864 if (ST.getGeneration() >= AMDGPUSubtarget::GFX10) {
5865 return (22ULL << 44) | // IMG_FORMAT_32_FLOAT
5866 (1ULL << 56) | // RESOURCE_LEVEL = 1
5867 (3ULL << 60); // OOB_SELECT = 3
5868 }
5869
5870 uint64_t RsrcDataFormat = AMDGPU::RSRC_DATA_FORMAT;
5871 if (ST.isAmdHsaOS()) {
5872 // Set ATC = 1. GFX9 doesn't have this bit.
5873 if (ST.getGeneration() <= AMDGPUSubtarget::VOLCANIC_ISLANDS)
5874 RsrcDataFormat |= (1ULL << 56);
5875
5876 // Set MTYPE = 2 (MTYPE_UC = uncached). GFX9 doesn't have this.
5877 // BTW, it disables TC L2 and therefore decreases performance.
5878 if (ST.getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS)
5879 RsrcDataFormat |= (2ULL << 59);
5880 }
5881
5882 return RsrcDataFormat;
5883}
5884
5885uint64_t SIInstrInfo::getScratchRsrcWords23() const {
5886 uint64_t Rsrc23 = getDefaultRsrcDataFormat() |
5887 AMDGPU::RSRC_TID_ENABLE |
5888 0xffffffff; // Size;
5889
5890 // GFX9 doesn't have ELEMENT_SIZE.
5891 if (ST.getGeneration() <= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
5892 uint64_t EltSizeValue = Log2_32(ST.getMaxPrivateElementSize()) - 1;
5893 Rsrc23 |= EltSizeValue << AMDGPU::RSRC_ELEMENT_SIZE_SHIFT;
5894 }
5895
5896 // IndexStride = 64 / 32.
5897 uint64_t IndexStride = ST.getWavefrontSize() == 64 ? 3 : 2;
5898 Rsrc23 |= IndexStride << AMDGPU::RSRC_INDEX_STRIDE_SHIFT;
5899
5900 // If TID_ENABLE is set, DATA_FORMAT specifies stride bits [14:17].
5901 // Clear them unless we want a huge stride.
5902 if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
5903 ST.getGeneration() <= AMDGPUSubtarget::GFX9)
5904 Rsrc23 &= ~AMDGPU::RSRC_DATA_FORMAT;
5905
5906 return Rsrc23;
5907}
5908
5909bool SIInstrInfo::isLowLatencyInstruction(const MachineInstr &MI) const {
5910 unsigned Opc = MI.getOpcode();
5911
5912 return isSMRD(Opc);
5913}
5914
5915bool SIInstrInfo::isHighLatencyInstruction(const MachineInstr &MI) const {
5916 unsigned Opc = MI.getOpcode();
5917
5918 return isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc);
5919}
5920
5921unsigned SIInstrInfo::isStackAccess(const MachineInstr &MI,
5922 int &FrameIndex) const {
5923 const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
5924 if (!Addr || !Addr->isFI())
5925 return AMDGPU::NoRegister;
5926
5927 assert(!MI.memoperands_empty() &&((!MI.memoperands_empty() && (*MI.memoperands_begin()
)->getAddrSpace() == AMDGPUAS::PRIVATE_ADDRESS) ? static_cast
<void> (0) : __assert_fail ("!MI.memoperands_empty() && (*MI.memoperands_begin())->getAddrSpace() == AMDGPUAS::PRIVATE_ADDRESS"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5928, __PRETTY_FUNCTION__))
5928 (*MI.memoperands_begin())->getAddrSpace() == AMDGPUAS::PRIVATE_ADDRESS)((!MI.memoperands_empty() && (*MI.memoperands_begin()
)->getAddrSpace() == AMDGPUAS::PRIVATE_ADDRESS) ? static_cast
<void> (0) : __assert_fail ("!MI.memoperands_empty() && (*MI.memoperands_begin())->getAddrSpace() == AMDGPUAS::PRIVATE_ADDRESS"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5928, __PRETTY_FUNCTION__))
;
5929
5930 FrameIndex = Addr->getIndex();
5931 return getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg();
5932}
5933
5934unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
5935 int &FrameIndex) const {
5936 const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::addr);
5937 assert(Addr && Addr->isFI())((Addr && Addr->isFI()) ? static_cast<void> (
0) : __assert_fail ("Addr && Addr->isFI()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5937, __PRETTY_FUNCTION__))
;
5938 FrameIndex = Addr->getIndex();
5939 return getNamedOperand(MI, AMDGPU::OpName::data)->getReg();
5940}
5941
5942unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
5943 int &FrameIndex) const {
5944 if (!MI.mayLoad())
5945 return AMDGPU::NoRegister;
5946
5947 if (isMUBUF(MI) || isVGPRSpill(MI))
5948 return isStackAccess(MI, FrameIndex);
5949
5950 if (isSGPRSpill(MI))
5951 return isSGPRStackAccess(MI, FrameIndex);
5952
5953 return AMDGPU::NoRegister;
5954}
5955
5956unsigned SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
5957 int &FrameIndex) const {
5958 if (!MI.mayStore())
5959 return AMDGPU::NoRegister;
5960
5961 if (isMUBUF(MI) || isVGPRSpill(MI))
5962 return isStackAccess(MI, FrameIndex);
5963
5964 if (isSGPRSpill(MI))
5965 return isSGPRStackAccess(MI, FrameIndex);
5966
5967 return AMDGPU::NoRegister;
5968}
5969
5970unsigned SIInstrInfo::getInstBundleSize(const MachineInstr &MI) const {
5971 unsigned Size = 0;
5972 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
5973 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
5974 while (++I != E && I->isInsideBundle()) {
5975 assert(!I->isBundle() && "No nested bundle!")((!I->isBundle() && "No nested bundle!") ? static_cast
<void> (0) : __assert_fail ("!I->isBundle() && \"No nested bundle!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 5975, __PRETTY_FUNCTION__))
;
5976 Size += getInstSizeInBytes(*I);
5977 }
5978
5979 return Size;
5980}
5981
5982unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
5983 unsigned Opc = MI.getOpcode();
5984 const MCInstrDesc &Desc = getMCOpcodeFromPseudo(Opc);
5985 unsigned DescSize = Desc.getSize();
5986
5987 // If we have a definitive size, we can use it. Otherwise we need to inspect
5988 // the operands to know the size.
5989 if (isFixedSize(MI))
5990 return DescSize;
5991
5992 // 4-byte instructions may have a 32-bit literal encoded after them. Check
5993 // operands that coud ever be literals.
5994 if (isVALU(MI) || isSALU(MI)) {
5995 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
5996 if (Src0Idx == -1)
5997 return DescSize; // No operands.
5998
5999 if (isLiteralConstantLike(MI.getOperand(Src0Idx), Desc.OpInfo[Src0Idx]))
6000 return isVOP3(MI) ? 12 : (DescSize + 4);
6001
6002 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
6003 if (Src1Idx == -1)
6004 return DescSize;
6005
6006 if (isLiteralConstantLike(MI.getOperand(Src1Idx), Desc.OpInfo[Src1Idx]))
6007 return isVOP3(MI) ? 12 : (DescSize + 4);
6008
6009 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
6010 if (Src2Idx == -1)
6011 return DescSize;
6012
6013 if (isLiteralConstantLike(MI.getOperand(Src2Idx), Desc.OpInfo[Src2Idx]))
6014 return isVOP3(MI) ? 12 : (DescSize + 4);
6015
6016 return DescSize;
6017 }
6018
6019 // Check whether we have extra NSA words.
6020 if (isMIMG(MI)) {
6021 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
6022 if (VAddr0Idx < 0)
6023 return 8;
6024
6025 int RSrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);
6026 return 8 + 4 * ((RSrcIdx - VAddr0Idx + 2) / 4);
6027 }
6028
6029 switch (Opc) {
6030 case TargetOpcode::IMPLICIT_DEF:
6031 case TargetOpcode::KILL:
6032 case TargetOpcode::DBG_VALUE:
6033 case TargetOpcode::EH_LABEL:
6034 return 0;
6035 case TargetOpcode::BUNDLE:
6036 return getInstBundleSize(MI);
6037 case TargetOpcode::INLINEASM:
6038 case TargetOpcode::INLINEASM_BR: {
6039 const MachineFunction *MF = MI.getParent()->getParent();
6040 const char *AsmStr = MI.getOperand(0).getSymbolName();
6041 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo(),
6042 &MF->getSubtarget());
6043 }
6044 default:
6045 return DescSize;
6046 }
6047}
6048
6049bool SIInstrInfo::mayAccessFlatAddressSpace(const MachineInstr &MI) const {
6050 if (!isFLAT(MI))
6051 return false;
6052
6053 if (MI.memoperands_empty())
6054 return true;
6055
6056 for (const MachineMemOperand *MMO : MI.memoperands()) {
6057 if (MMO->getAddrSpace() == AMDGPUAS::FLAT_ADDRESS)
6058 return true;
6059 }
6060 return false;
6061}
6062
6063bool SIInstrInfo::isNonUniformBranchInstr(MachineInstr &Branch) const {
6064 return Branch.getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO;
6065}
6066
6067void SIInstrInfo::convertNonUniformIfRegion(MachineBasicBlock *IfEntry,
6068 MachineBasicBlock *IfEnd) const {
6069 MachineBasicBlock::iterator TI = IfEntry->getFirstTerminator();
6070 assert(TI != IfEntry->end())((TI != IfEntry->end()) ? static_cast<void> (0) : __assert_fail
("TI != IfEntry->end()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 6070, __PRETTY_FUNCTION__))
;
6071
6072 MachineInstr *Branch = &(*TI);
6073 MachineFunction *MF = IfEntry->getParent();
6074 MachineRegisterInfo &MRI = IfEntry->getParent()->getRegInfo();
6075
6076 if (Branch->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
6077 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC());
6078 MachineInstr *SIIF =
6079 BuildMI(*MF, Branch->getDebugLoc(), get(AMDGPU::SI_IF), DstReg)
6080 .add(Branch->getOperand(0))
6081 .add(Branch->getOperand(1));
6082 MachineInstr *SIEND =
6083 BuildMI(*MF, Branch->getDebugLoc(), get(AMDGPU::SI_END_CF))
6084 .addReg(DstReg);
6085
6086 IfEntry->erase(TI);
6087 IfEntry->insert(IfEntry->end(), SIIF);
6088 IfEnd->insert(IfEnd->getFirstNonPHI(), SIEND);
6089 }
6090}
6091
6092void SIInstrInfo::convertNonUniformLoopRegion(
6093 MachineBasicBlock *LoopEntry, MachineBasicBlock *LoopEnd) const {
6094 MachineBasicBlock::iterator TI = LoopEnd->getFirstTerminator();
6095 // We expect 2 terminators, one conditional and one unconditional.
6096 assert(TI != LoopEnd->end())((TI != LoopEnd->end()) ? static_cast<void> (0) : __assert_fail
("TI != LoopEnd->end()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
, 6096, __PRETTY_FUNCTION__))
;
6097
6098 MachineInstr *Branch = &(*TI);
6099 MachineFunction *MF = LoopEnd->getParent();
6100 MachineRegisterInfo &MRI = LoopEnd->getParent()->getRegInfo();
6101
6102 if (Branch->getOpcode() == AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO) {
6103
6104 Register DstReg = MRI.createVirtualRegister(RI.getBoolRC());
6105 Register BackEdgeReg = MRI.createVirtualRegister(RI.getBoolRC());
6106 MachineInstrBuilder HeaderPHIBuilder =
6107 BuildMI(*(MF), Branch->getDebugLoc(), get(TargetOpcode::PHI), DstReg);
6108 for (MachineBasicBlock::pred_iterator PI = LoopEntry->pred_begin(),
6109 E = LoopEntry->pred_end();
6110 PI != E; ++PI) {
6111 if (*PI == LoopEnd) {
6112 HeaderPHIBuilder.addReg(BackEdgeReg);
6113 } else {
6114 MachineBasicBlock *PMBB = *PI;
6115 Register ZeroReg = MRI.createVirtualRegister(RI.getBoolRC());
6116 materializeImmediate(*PMBB, PMBB->getFirstTerminator(), DebugLoc(),
6117 ZeroReg, 0);
6118 HeaderPHIBuilder.addReg(ZeroReg);
6119 }
6120 HeaderPHIBuilder.addMBB(*PI);
6121 }